US Pat. No. 10,170,600

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device, comprising the steps of:forming a silicon layer over a substrate;
forming a resin layer over the silicon layer;
forming a transistor over the resin layer;
forming a conductive layer over the silicon layer and the resin layer; and
separating the substrate and the transistor from each other,
wherein the resin layer comprises an opening over the silicon layer,
wherein the conductive layer is in contact with the silicon layer through the opening of the resin layer, and
wherein in the step of separating the substrate and the transistor from each other, silicon contained in the silicon layer and metal contained in the conductive layer react with each other by irradiation of the silicon layer with light to form a metal silicide layer.

US Pat. No. 10,170,599

SEMICONDUCTOR DEVICE INCLUDING INSULATING FILMS WITH DIFFERENT THICKNESSES AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film over a substrate;
forming a first oxide insulating film over and in contact with the oxide semiconductor film, in an apparatus and by chemical vapor deposition in a first atmosphere, and with a first radio-frequency power supplied to an electrode of the apparatus; and
forming a second oxide insulating film over and in contact with the first oxide insulating film, in the apparatus and by chemical vapor deposition in a second atmosphere, and with a second radio-frequency power supplied to the electrode of the apparatus,
wherein the first radio-frequency power is lower than the second radio-frequency power,
wherein the first oxide insulating film is formed thinner than the second oxide insulating film, and a thickness of the first oxide insulating film is less than or equal to 50 nm, and
wherein spin densities of the first oxide insulating film measured by electron spin resonance are less than or equal to a lower limit of detection at a g-factor of 2.001.

US Pat. No. 10,170,598

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming an oxynitride semiconductor layer over an oxide insulating layer formed over an insulating surface;
forming a gate insulating layer over the oxynitride semiconductor layer; and
forming a gate electrode over the gate insulating layer,
wherein the oxynitride semiconductor layer includes a channel region, a source region, and a drain region,
wherein an amount of oxygen released by the oxide insulating layer in thermal desorption spectroscopy is greater than or equal to 1.0×1020 atoms/cm3, and
wherein the oxynitride semiconductor layer is an n-type semiconductor layer.

US Pat. No. 10,170,597

METHOD FOR FORMING FLASH MEMORY UNIT

Integrated Silicon Soluti...

1. A method for forming flash memory units, each of the flash memory units comprising a select gate PMOS transistor and a control gate PMOS transistor, the method comprising the steps of:providing a P-type substrate and forming an N-type well in the P-type substrate, wherein the N-type well comprises a plurality of flash memory unit areas each comprising a select gate PMOS transistor area and a control gate PMOS transistor area;
forming a channel area, a gate oxide layer, an N-type floating gate and an insulating layer sequentially for the select gate PMOS transistor and the control gate PMOS transistor in the flash memory unit area;
etching a part or all of the insulating layer in the select gate PMOS transistor area, and forming a logic gate on the etched insulating layer in the flash memory unit area;
implanting P-type impurities into the logic gate in the flash memory unit area, wherein a doping concentration of the logic gate is larger than a doping concentration of the N-type floating gate;
separating the logic gate in the select gate PMOS transistor area from the logic gate in the control gate PMOS transistor area by etching;
diffusing the P-type impurities in the logic gate in the select gate PMOS transistor area to the N-type floating gate in the select gate PMOS transistor area using a heating process, such that the N-type floating gate in the select gate PMOS transistor area changes to a P-type floating gate; and
forming electrodes for the select gate PMOS transistor and the control gate PMOS transistor.

US Pat. No. 10,170,596

FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH

International Business Ma...

1. An arrangement of active and inactive fins on a substrate, comprising:a substrate;
a pair of vertical fins on the substrate;
an inactive vertical fin on the substrate between the pair of vertical fins, wherein the inactive vertical fin includes a lower portion made of a semiconductor material and an upper portion made of an insulating material;
a protective liner on a lower portion of each of the pair of vertical fins and the lower portion of the inactive vertical fin; and
a filler layer on the protective liner and the substrate, wherein a top surface of the filler layer is above the protective liner and the lower portion of the inactive vertical fin made of the semiconductor material.

US Pat. No. 10,170,594

PUNCH THROUGH STOPPER IN BULK FINFET DEVICE

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device comprising:forming a gate structure on a channel region portion of a fin structure after forming an isolation region;
forming a spacer on the gate structure;
exposing a lower portion of a sidewall of the fin structure;
forming a doped material on the lower portion of the fin structure, wherein said forming the doped material on the exposed lower portion of the sidewall of the fin structure comprises epitaxial deposition of a semiconductor material that is in situ doped with an n-type or p-type dopant; and
diffusing dopant from the doped material to a base portion of the fin structure.

US Pat. No. 10,170,593

THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT

International Business Ma...

1. A method of forming an arrangement of long fin and short fin devices on a substrate, comprising:forming a plurality of long fins on the substrate;
forming a plurality of short fins on the substrate, wherein the short fins are shorter than the long fins;
forming a first active gate across the plurality of long fins;
forming a second active gate across the plurality of short fins, wherein at least one of the plurality of long fins is adjacent to at least one of the plurality of short fins; and
forming at least two dummy gates across the plurality of long fins.

US Pat. No. 10,170,592

INTEGRATED CIRCUIT STRUCTURE WITH SUBSTRATE ISOLATION AND UN-DOPED CHANNEL

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a circuit device, the method comprising:receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition;
patterning the first semiconductor layer, the second semiconductor layer, and the substrate to form a fin structure that includes the first semiconductor layer, the second semiconductor layer, and a patterned portion of the substrate; and
performing a selective oxidization process to the first semiconductor layer, such that a bottom portion of the first semiconductor layer is fully oxidized while a top portion of the first semiconductor layer directly above the oxidized bottom portion and the patterned portion of the substrate directly below the oxidized bottom portion remain un-oxidized.

US Pat. No. 10,170,591

SELF-ALIGNED FINFET FORMATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, the method comprising:forming a first hardmask on a semiconductor substrate;
forming a planarizing layer on the first hardmask;
forming a second hardmask on the planarizing layer;
removing portions of the second hardmask;
forming alternating blocks of a first material and a second material over the second hardmask;
removing the blocks of the second material to expose portions of the planarizing layer;
removing exposed portions of the planarizing layer to expose portions of the first hardmask and removing portions of the first hardmask to expose portions of the semiconductor substrate;
removing exposed portions of the semiconductor substrate to form a first fin and a second fin, wherein the first fin is arranged under a portion of the planarizing layer;
further removing exposed portions of the semiconductor substrate to further increase the height of the first fin and substantially remove the second fin; and
forming a gate stack over a channel region of the first fin;
wherein the planarizing layer includes an organic planarizing material;
wherein the second hardmask includes a first layer arranged on the planarizing layer, a second layer arranged on the first layer, and a third layer arranged on the second layer; and
wherein a layer of the first material is deposited over portions of the first layer of the second hardmask prior to forming the alternating blocks of the first material and the second material.

US Pat. No. 10,170,590

VERTICAL FIELD EFFECT TRANSISTORS WITH UNIFORM THRESHOLD VOLTAGE

INTERNATIONAL BUSINESS MA...

9. A semiconductor structure, comprising:semiconductor fins on a substrate, the semiconductor fins being arranged in a direction;
a spacer layer between the semiconductor fins, the spacer layer being on a surface of the substrate upon which the semiconductor fins are formed;
a high dielectric constant layer, wherein a first portion of the high dielectric constant layer is on sidewalls of the semiconductor fins, and a second portion of the high dielectric constant layer is over the spacer layer;
a work function metal layer on sidewalls of the semiconductor fins and on the high dielectric constant layer, a thickness of the work function metal layer in the direction being uniform; and
a top spacer layer, wherein the top spacer layer is on a portion of the low resistance metal layer, a portion of the work function metal layer, and a portion of the high-dielectric constant layer.

US Pat. No. 10,170,589

VERTICAL POWER MOSFET AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor region;
a gate dielectric over the semiconductor region;
a gate electrode over the gate dielectric;
a drain region and a source region at a top surface of the semiconductor region and adjacent to the gate electrode;
a gate spacer on a sidewall of the gate electrode;
a dielectric layer over the gate electrode and the gate spacer, wherein the dielectric layer comprises a portion, with the portion comprising a first sidewall contacting the gate spacer, and a second sidewall opposite to the first sidewall;
a deep metal via in the semiconductor region, wherein an edge of the deep metal via is aligned to the second sidewall of the portion of the dielectric layer;
a source electrode underlying the semiconductor region, wherein the source electrode is electrically shorted to the source region through the deep metal via; and
a Metal-Oxide-Semiconductor (MOS) device selected from the group consisting essentially of a low-voltage MOSFET and a high-side MOSFET formed at a top surface of the semiconductor region, wherein the MOSFET comprises an additional source region and an additional drain region at the top surface of the semiconductor region, and the source electrode extends directly underlying, and is electrically decoupled from, the additional source region and the additional drain region.

US Pat. No. 10,170,588

METHOD OF FORMING VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTOR WITH HIGH-K DIELECTRIC FEATURE UNIFORMITY

International Business Ma...

1. A method of forming a vertical transport fin field effect transistor, comprising:forming a doped layer on a substrate;
forming a multilayer fin on the doped layer, wherein the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the lower trim layer portion and the upper trim layer portion;
removing a portion of the lower trim layer portion to form a lower trim layer post;
removing a portion of the upper trim layer portion to form an upper trim layer post;
forming an upper recess filler adjacent to the upper trim layer post, and a lower recess filler adjacent to the lower trim layer post; and
removing a portion of the fin channel portion to form a fin channel post between the upper trim layer post and lower trim layer post.

US Pat. No. 10,170,587

HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION

International Business Ma...

1. A semiconductor device fabrication process comprising:forming a sacrificial portion upon a substrate;
forming a sacrificial gate stack upon the sacrificial portion;
forming a sacrificial gate spacer upon the sacrificial portion against the sacrificial gate;
forming a source drain region of a first doped material upon the substrate against the gate spacer;
removing the sacrificial gate stack forming a replacement gate trench;
forming an extension trench between the sacrificial gate spacer and the substrate by removing the sacrificial portion accessible via the replacement gate trench;
forming an extension region of a second doped material that has a higher mobility relative to the first doped material within the extension trench against the sacrificial gate spacer and against the substrate;
removing the sacrificial gate spacer; and
forming a replacement gate spacer upon the extension region.

US Pat. No. 10,170,586

UNIPOLAR SPACER FORMATION FOR FINFETS

International Business Ma...

1. A method for forming a spacer for a semiconductor device, comprising:depositing a dummy spacer layer over surfaces of gate structures and fins, the gate structures being transversely orientated relative to the fins;
planarizing a dielectric fill formed over the gate structures and the fins to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of sidewalls of the gate structures;
forming channels by removing the dummy spacer layer along the sidewalls of the gate structures, the fins being protected by the dielectric fill;
forming a spacer by filling the channels with a spacer material; and
removing the dielectric fill and the dummy spacer layer to expose the tins.

US Pat. No. 10,170,585

SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

International Business Ma...

1. A method of forming equal thickness gate spacers for PFET (p-type field effect transistor) and NFET (n-type field effect transistor) devices, the method comprising:depositing at least a first dielectric layer to pinch-off space between gates;
recessing the first dielectric layer such that a first gate hard mask is exposed;
depositing a first conformal atomic layer deposition (ALD) layer or depositing a first directed self-assembly (DSA) layer adjacent gate masks of the PFET and NFET devices;
masking the NFET device and etching the first dielectric layer in a PFET region using the first ALD layer or the first DSA layer as a mask to form a PFET spacer;
forming PFET epi growth regions;
depositing a first nitride liner and a first inter-level dielectric (ILD) over the PFET and NFET devices;
recessing the ILD and the nitride liner to reveal a second gate hard mask;
depositing a second conformal ALD layer or depositing a second DSA layer adjacent the gate masks of the PFET and NFET devices;
masking the PFET device and etching the first dielectric layer in NFET region using the second ALD layer or the second DSA layer as a mask to form an NFET spacer;
forming NFET epi growth regions;
depositing a second nitride liner and a second inter-level dielectric (ILD) over the PFET and NFET devices; and
removing the gate masks of the PFET and NFET devices to form high-k metal gates (HKMGs) between the PFET and NFET epi growth regions.

US Pat. No. 10,170,584

NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS

International Business Ma...

1. A method of forming a nanosheet device, comprising:forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer;
forming a stack cover layer on at least a portion of the channel stack, wherein the stack cover layer is formed on at least a portion of exposed sides of the at least one nanosheet channel layer and the at least one sacrificial release layer;
forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate;
removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib; and
forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

US Pat. No. 10,170,582

UNIFORM BOTTOM SPACER FOR VERTICAL FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:forming a protective liner above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a nitride-oxide-nitride hardmask positioned on top of the fin, wherein the protective liner comprises a metal oxide material;
removing the protective liner from a top surface of the semiconductor substrate and a top surface of the nitride-oxide-nitride hardmask, wherein the protective liner remains on sidewalls of the fin and the nitride-oxide-nitride hardmask;
forming a first dielectric layer above and in direct contact with the semiconductor substrate, the protective liner and the top surface of the nitride-oxide-nitride hardmask;
simultaneously removing top portions of the first dielectric layer and the nitride-oxide-nitride hardmask, wherein the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate;
removing the protective liner from the semiconductor structure, wherein removing the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin; and
forming a second dielectric layer, the second dielectric layer fills the opening between the first dielectric layer and the bottom portion of the fin.

US Pat. No. 10,170,581

FINFET WITH REDUCED PARASITIC CAPACITANCE

International Business Ma...

1. A method of fabricating a finFET semiconductor device, the method comprising:forming a dummy gate above and perpendicular to semiconductor fins;
forming sidewall spacers on opposite sides of the dummy gate;
covering exposed portions of the semiconductor fins not covered by the dummy gate or the sidewall spacers with a dummy dielectric material;
forming an isolation region adjacent to and in direct contact with the dummy dielectric material, an upper surface of the isolation region is substantially flush with an upper surface of the dummy dielectric material;
replacing the dummy gate with a metal gate electrode covered by a dielectric gate cap;
replacing the dummy dielectric material with a self-aligned silicide contact, the self-aligned silicide contact being adjacent to and in direct contact with the sidewall spacers which separates it from the metal gate electrode, wherein the dummy dielectric material is removed selective to the isolation region, the sidewall spacers, and the dielectric gate cap;
forming a blanket metal layer on top of both the metal gate electrode and the self-aligned silicide contact, the blanket metal layer being in direct contact with the self-aligned silicide contact but physically isolated from the metal gate electrode by the dielectric gate cap;
patterning the blanket metal layer to form a source-drain contact;
removing excess material from the self-aligned silicide contact by recessing all of the self-aligned silicide contact except for a portion directly beneath the source-drain contact, wherein after recessing the self-aligned silicide contact has a stepped profile, the stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being in direct contact with the source-drain contact and above the second upper surface;
depositing an interlevel dielectric layer directly on top of the isolation region, the gate cap, and the second upper surface of the self-aligned silicide contact;
forming an opening in the interlevel dielectric and the gate cap to expose an upper surface of the metal gate electrode; and
forming a gate contact within the opening above and in direct contact with the metal gate electrode.

US Pat. No. 10,170,580

STRUCTURE OF GAN-BASED TRANSISTOR AND METHOD OF FABRICATING THE SAME

INDUSTRIAL TECHNOLOGY RES...

1. A GaN-based transistor device, comprising:a substrate;
a buffer layer, disposed on the substrate;
a channel layer, disposed on the buffer layer;
a barrier layer, disposed on a part of the channel layer;
a passivation layer, disposed on the barrier layer, wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall, and the first side wall and the second side wall are corresponding to each other;
a barrier metal layer, disposed on the passivation layer, wherein the barrier metal layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening to expose a part of the barrier layer;
a gate electrode, disposed on the exposed part of the barrier layer;
a source electrode, disposed on the channel layer, wherein the source electrode covers the first side wall and a part of the barrier metal layer adjacent to the first side wall; and
a drain electrode, disposed on the channel layer, wherein the drain electrode covers the second side wall and another part of the barrier metal layer adjacent to the second side wall;
wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.

US Pat. No. 10,170,579

SURFACE TREATMENT AND PASSIVATION FOR HIGH ELECTRON MOBILITY TRANSISTORS

TAIWAN SEMICONDUCTOR MANU...

1. A High Electron Mobility Transistor (HEMT), comprising:a first III-V compound layer having a first band gap;
a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap;
a first oxide layer over the second III-V compound layer;
a first interfacial layer over the first oxide layer, wherein the first interfacial layer comprises a crystalline semiconductor material; and
a passivation layer over the first interfacial layer.

US Pat. No. 10,170,578

THROUGH-SUBSTRATE VIA POWER GATING AND DELIVERY BIPOLAR TRANSISTOR

International Business Ma...

1. A semiconductor substrate, comprising:a through-substrate via (TSV) comprising:
a sidewall insulator defining an outer boundary of the TSV, and
a bipolar junction transistor disposed within the sidewall insulator, the bipolar junction transistor comprising:
a first semiconductor layer doped with a first-type of dopant, wherein the first semiconductor layer comprises a collector,
a second semiconductor layer doped with a second-type of dopant, wherein the second semiconductor layer comprises a base, and
a third semiconductor layer doped with the first-type of dopant, wherein the third semiconductor layer comprises an emitter, and wherein the first, second, and third semiconductor layers are arranged in the TSV to form one of: a PNP junction and an NPN junction, wherein the base is disposed between the collector and the emitter in the TSV, wherein a material of the collector forms an annular shape, wherein a base contact is disposed in a central opening of the annular shape, wherein the base contact comprises a conductive material that directly contacts the base in the second semiconductor layer.

US Pat. No. 10,170,577

VERTICAL TRANSPORT FETS HAVING A GRADIENT THRESHOLD VOLTAGE

International Business Ma...

1. A semiconductor structure comprising:at least one semiconductor fin present in a device region and extending upwards from a surface of a base semiconductor substrate;
a bottom source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom source/drain structure serves as a drain region;
a gate dielectric layer located above the bottom source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
a gate structure located laterally adjacent a sidewall of the gate dielectric layer, the gate structure comprising a TiN liner having a first threshold voltage and a TiN portion having a second threshold voltage that is greater than the first threshold voltage; and
a top source/drain structure located on an upper portion of the at least one semiconductor fin, wherein the top source/drain structure serves as a source region.

US Pat. No. 10,170,576

STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES

International Business Ma...

1. A method for forming a gate structure for a field effect transistor, comprising:forming a gate dielectric layer over and between a plurality of fins;
depositing a single diffusion prevention layer on the gate dielectric layer over and between the plurality of fins; and
depositing an oxygen affinity layer on the diffusion prevention layer by pinching off portions of the oxygen affinity layer within the diffusion prevention layer to merge the portions without intervening layers between the portions.

US Pat. No. 10,170,575

VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a material stack including a surface semiconductor layer present on a metal semiconductor alloy layer;
a first of a source region or a drain region present in the surface semiconductor layer, the surface semiconductor layer including the first of the source or the drain region having a first portion that extends continuously across an entirety of a width of the semiconductor device, and a second portion that has a pedestal geometry that does not extend the entirety of the width of the semiconductor device;
a vertically orientated channel having a first end contacting and aligned with the second portion of the surface semiconductor layer that has the pedestal geometry;
a gate structure in direct contact with the vertically orientated channel;
a second of the source region or the drain region present at a second end of the vertically oriented channel that is opposite said first end of the vertically orientated channel; and
a via contact in electrical communication with the metal semiconductor alloy layer providing a contact to said first of said source region or said drain region of the semiconductor device, wherein the metal semiconductor alloy layer extends continuously across the entirety of the width of the semiconductor device including being present directly underlying a portion of the surface semiconductor layer that is present directly underlying an entirety of the vertically , orientated channel.

US Pat. No. 10,170,573

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate;
a metal gate on the substrate, wherein the metal gate comprises a tungsten layer protruding from the top surface of the metal gate;
a first inter-layer dielectric (ILD) layer around the metal gate, wherein a top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate, wherein the recessed region is separated by the tungsten layer into a first sub-region and a second sub-region;
a mask layer in the recessed region;
a first void in the mask layer within the first sub-region of the recessed region;
a second void in the mask layer within the second sub-region of the recessed region;
a second inter-layer dielectric (ILD) layer on the mask layer and the first ILD layer;
a contact hole extending into the second ILD layer and the mask layer, wherein the contact hole exposes the top surface of the metal gate and communicates with the first and second voids; and
a conductive layer disposed in the contact hole and the first and second voids.

US Pat. No. 10,170,571

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a composite gate structure formed over a semiconductor substrate, wherein the composite gate structure comprises:
a gate dielectric layer;
a metal layer disposed on the gate dielectric layer; and
a semiconductor layer disposed on the gate dielectric layer, wherein the metal layer and the semiconductor layer are stacked on the gate dielectric layer side by side.

US Pat. No. 10,170,570

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction, and stacked one over the other with an insulating layer disposed between each adjacent electrode;
the plurality of electrodes including a first side, and a second side, each extending in the second direction and spaced from each other in the first direction;
a plurality of protrusion portions extending from the first side of at least two of the electrodes, the protrusion portions spaced from one another in the second direction;
an extraction portion extending from the second side of the electrode on the at least two electrodes having protrusion portions extending from the first side thereof; and
first and second contact plugs extending in a third direction, orthogonal to the first and second directions, one of each contacting the extraction portions connected to one of the two electrodes having protrusion portions extending from the first side thereof,
wherein the extraction portion extending from the uppermost of the two electrodes having protrusion portions extending from the first side thereof is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the two electrodes having protrusion portions extending from the first side thereof.

US Pat. No. 10,170,569

THIN FILM TRANSISTOR FABRICATION UTLIZING AN INTERFACE LAYER ON A METAL ELECTRODE LAYER

APPLIED MATERIALS, INC., ...

1. A thin film transistor structure, comprising:a metal electrode layer disposed on a barrier layer formed above a gate insulating material;
an interface layer disposed on and in direct contact with the metal electrode layer, wherein the interface layer is an oxygen free dielectric material sized to be formed on and to have the same width as the metal electrode layer; and
an inorganic insulating material layer disposed on and in direct contact with the interface layer, wherein the inorganic insulating material layer is an oxygen containing dielectric layer.

US Pat. No. 10,170,568

HIGH VOLTAGE LATERALLY DIFFUSED MOSFET WITH BURIED FIELD SHIELD AND METHOD TO FABRICATE SAME

International Business Ma...

1. A method to fabricate laterally diffused MOSFETs comprising:providing a semiconductor substrate having disposed over a top surface thereof a bottom surface of an n-type layer;
forming a recess in a top surface of the n-type layer;
forming in the recess an electrically conductive field shield member covered completely with a dielectric material;
epitaxially growing in vertical and lateral directions from the top surface of the n-type layer additional n-type semiconductor material so as to completely bury the electrically conductive field shield member and dielectric material, where the n-type layer and the additional n-type semiconductor material are doped for forming an n-type drift region;
forming, in the n-type drift region, a p-type body region overlying the buried electrically conductive field shield member and dielectric material and forming first and second n+ drain regions;
forming, in the p-type body region, first and second n+ source regions and a p+ body contact region overlying the buried electrically conductive field shield member and dielectric material;
depositing first and second gate dielectrics and gate electrodes so as to overly a portion of the p-type body region and the n-type drift region, where a first gate electrode is disposed on the first gate dielectric associated with a first laterally diffused MOSFET and where a second gate electrode is disposed on the second gate dielectric associated with a second laterally diffused MOSFET; and
providing a plurality of additional field shields, where one of the additional field shields is disposed on the first gate dielectric in proximity to the first gate electrode and a first portion of the n-type drift region, and where another one of the additional field shields is disposed on the second gate dielectric in proximity to the second gate electrode and overlying a second portion of the n-type drift region;
where the p+ body contact region is formed by implanting p-type dopant atoms into a region of the n-type drift region where two growth fronts, formed during the step of epitaxially growing in the lateral direction the additional n-type semiconductor material, meet and grow together.

US Pat. No. 10,170,566

SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a semiconductor substrate having a plurality of active regions and a device isolation region for isolating the plurality of active regions from each other;
a buried bit line and a buried gate electrode which are formed in the semiconductor substrate;
a gate trench having a bottom surface, a first side surface and a second side surface opposite to the first side surface, wherein the buried gate electrode is embedded in the gate trench,
wherein the device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a conductive shield pillar,
wherein the conductive shield pillar has a height that overlaps a portion of the buried gate electrode and the buried bit line,
wherein a top surface of the conductive shield pillar being at a higher level than a bottom surface of the buried gate electrode, and
wherein a bottom surface of the conductive shield pillar being at lower level than a bottom surface of the buried bit line.

US Pat. No. 10,170,565

IMAGING DEVICE, METHOD FOR DRIVING IMAGING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An imaging device comprising:a photoelectric conversion element;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a first capacitor,
wherein one terminal of the photoelectric conversion element is directly connected to one of a source electrode and a drain electrode of the first transistor,
wherein the other terminal of the photoelectric conversion element is directly connected to a first power supply line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor,
wherein the other of the source electrode and the drain electrode of the first transistor is directly connected to one terminal of the first capacitor,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the other terminal of the first capacitor,
wherein the one of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is directly connected to one of a source electrode and a drain electrode of the fifth transistor,
wherein the gate electrode of the fourth transistor is directly connected to the other terminal of the first capacitor,
wherein the other of the source electrode and the drain electrode of the fifth transistor is directly connected to a second power supply line, and
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor.

US Pat. No. 10,170,564

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate, the manufacturing method of a semiconductor device comprising:forming an n-type gallium nitride layer on a gallium nitride monocrystalline substrate having a threading dislocation density of less than 1E+7 cm?2; and
forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, the impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein
at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

US Pat. No. 10,170,563

GALLIUM NITRIDE SEMICONDUCTOR DEVICE WITH IMPROVED TERMINATION SCHEME

Alpha and Omega Semicondu...

1. A gallium nitride based semiconductor power device comprising:a top gallium nitride layer comprises a plurality of guard rings disposed in a peripheral area of the top gallium nitride layer wherein the guard rings comprise a plurality of trenches having substantially a same depth opened in an upper portion of the top gallium nitride layer filled with a P-doped gallium-based epitaxial layer therein and wherein the guard rings surrounding a first electrode of the semiconductor power device comprises a metal layer covering over a middle portion of a top surface of the top gallium nitride layer; and
a heavily doped bottom gallium nitride epitaxial layer extending beyond an outer edge of the top gallium nitride layer wherein an extended portion of the bottom gallium nitride epitaxial layer having an exposed top surface not covered by the top gallium nitride layer and wherein a second electrode of the semiconductor power device is disposed directly on the exposed top surface of the extended portion of the bottom gallium nitride layer.

US Pat. No. 10,170,562

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;
an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; and
a cathode electrode formed on the rear surface of the SiC semiconductor layer, wherein
a Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer,
fine recesses are formed only in a SiC semiconductor layer side of a Schottky junction portion between the anode electrode and the front surface of the SiC semiconductor layer,
a part of the anode electrode is embedded in the fine recesses, and
the fine recesses have a depth not greater than 20 nm and are irregularly arranged on the SiC semiconductor layer.

US Pat. No. 10,170,561

DIAMOND SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A diamond semiconductor device comprising:a first diamond semiconductor layer of a first conductivity type having a main surface;
a second diamond semiconductor layer of an i-type or a second conductivity type provided on the main surface of the first diamond semiconductor layer, and having a first side surface with a plane orientation of a {111};
a third diamond semiconductor layer of the first conductivity type provided on the first side surface; and
a fourth diamond semiconductor layer of the second conductivity type provided on the main surface of the first diamond semiconductor layer and on a side surface of the second diamond semiconductor layer, at a side opposite to a side of the third diamond semiconductor layer.

US Pat. No. 10,170,560

SEMICONDUCTOR DEVICES WITH ENHANCED DETERMINISTIC DOPING AND RELATED METHODS

ATOMERA INCORPORATED, Lo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of stacked groups of layers on the semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region, the dopant having a fall-off steeper than 3.3 nm/decade.

US Pat. No. 10,170,558

LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

International Business Ma...

1. A method for doping punch through stoppers (PTSs), comprising:recessing a dielectric layer to form gaps between a top portion of the dielectric layer and a spacer formed on sidewalls of fins to expose the fins in the gaps; and
doping the fins through the gaps to form PTSs in the fins, wherein a doped region extends from a bottom surface of the PTSs into a substrate, wherein each fin is formed of a material compound that is different from the substrate.

US Pat. No. 10,170,557

THYRISTOR WITH IMPROVED PLASMA SPREADING

ABB Schweiz AG, Baden (C...

1. A thyristor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a first electrode layer, which is arranged on the first main side;
a second electrode layer, which is arranged on the first main side and which is electrically separated from the first electrode layer;
a third electrode layer, which is arranged on the second main side;
wherein the semiconductor wafer includes the following layers;
a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer;
a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first, p-n junction;
a second base layer of the first conductivity type, the second base layer and the fist base layer forming a second p-n junction;
a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and
wherein the second emitter layer and the second base layer form a third p-n junction.
wherein the thyristor device comprises a plurality of discrete emitter shorts, each emitter short penetrating through the first emitter layer to electrically connect the first base layer with the first electrode layer,
wherein in an orthogonal projection onto a plane parallel to the first main side, a contact area covered by an electrical contact of the first electrode layer with the first emitter layer and the emitter shorts includes areas in the shape of lanes in which no emitter shorts are arranged,
wherein the width of the lanes is at least two times the average distance between centers of emitter shorts next to each other in the contact area,
the lanes are curved, and in the orthogonal projection onto the plane parallel to the first main side, the lanes extend from an edge of the contact area adjacent to the second electrode layer in a direction away from the second electrode layer.

US Pat. No. 10,170,556

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device manufacturing method, comprising:preparing a semiconductor substrate of a first conductivity type;
forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate;
forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate;
forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction;
covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film;
after the covering the side wall of each of the first ditches, forming gate electrodes inside the first ditches and the second ditches;
forming a first semiconductor region of a second conductivity type different from the first conductivity type over a side wall of each of the first ditches; and
forming a source region of the first conductivity type in an upper surface portion of the semiconductor layer,
wherein, in the first ditches adjacently arranged in the first direction, distances between an upper surface of the grate electrodes and a bottom surface of the second insulating film are different.

US Pat. No. 10,170,555

INTERMETALLIC DOPING FILM WITH DIFFUSION IN SOURCE/DRAIN

Taiwan Semiconductor Manu...

1. A method comprising:etching a substrate to form a first semiconductor strip;
forming a first dummy gate structure over a first channel region of the first semiconductor strip, the first dummy gate structure being perpendicular to the first semiconductor strip;
etching a first recess in the first semiconductor strip on a first side of the first dummy gate structure;
etching a second recess in the first semiconductor strip on a second side of the first dummy gate structure;
forming a first intermetallic doping film in the first recess and the second recess;
diffusing a first dopant of the first intermetallic doping film into the first semiconductor strip proximate the first recess and into the first semiconductor strip proximate the second recess;
epitaxially growing a source/drain region in the first recess; and
epitaxially growing a source/drain region in the second recess.

US Pat. No. 10,170,554

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate structure on a substrate, the gate structure comprising:
a gate dielectric layer, disposed on the substrate;
a raised source/drain region adjacent to the gate structure, the raised source/drain region comprising a tip region under the gate structure;
a channel region under gate dielectric layer of the gate structure; and
a protection layer, wherein:
the protection layer is interposed between the substrate and the raised source/drain region, and
an atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region, and the atom stacking arrangement of the protection layer is an amorphous state having a higher degree of lattice disorder than that of the substrate and the raised source/drain region, and the protection layer has a first end portion with the amorphous state formed between the tip region under the gate structure and the channel region under the gate dielectric layer.

US Pat. No. 10,170,552

CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming nanosheet semiconductor devices, comprising:forming a first stack in a first device region comprising layers of a first channel material and layers of a sacrificial material;
forming a second stack in a second device region comprising layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material; and
etching away the sacrificial material using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner, wherein the liner protects the second channel material from the wet etch.

US Pat. No. 10,170,551

SIDEWALL IMAGE TRANSFER NANOSHEET

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a nanosheet stack on a substrate, the nanosheet stack comprising:
a sacrificial nanosheet layer on the substrate; and
a nanosheet layer on the sacrificial nanosheet layer;
an etch stop layer on the nanosheet stack;
a mandrel on the etch stop layer;
sidewalls adjacent to sidewalls of the mandrel; and
a fill layer on exposed portions of the etch stop layer.

US Pat. No. 10,170,550

STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming an alternating stack of disposable material portions and semiconductor material portions on a substrate;
forming a disposable gate structure straddling, and contacting sidewalls of, said alternating stack;
removing said disposable material portions selective to said semiconductor material portions and said disposable gate structure;
forming a first gate structure between each vertically neighboring pair among said semiconductor material portions, said first gate structure including a first gate dielectric and a first gate electrode;
forming a planarization dielectric layer around said disposable gate structure;
forming a gate cavity by removing said disposable gate structure selective to said planarization dielectric layer; and
forming a second gate structure within said gate cavity, said second gate structure including a second gate dielectric and a second gate electrode, wherein said forming the first gate structure comprises forming, after removing said disposable material portions, a first gate dielectric layer on surfaces of said semiconductor material portions, forming a first gate conductor layer on said first gate dielectric layer, anisotropically etching said first gate conductor layer and said first gate dielectric layer employing a combination of said disposable gate structure and said semiconductor material portions as an etch mask, and isotropically etching remaining portions of said first gate conductor layer and said first gate dielectric layer between said vertically neighboring pair among said semiconductor material portions.

US Pat. No. 10,170,549

STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET

Samsung Electronics Co., ...

1. A method for fabricating a nanosheet stack structure having one or more sub-stacks, the method comprising:growing an epitaxial crystalline initial stack of the one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are each kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing such that the non-sacrificial layers B and C remain metastable and without relaxation during processing, and wherein the sacrificial layer A is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A;
proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that hold the nanosheets in place after selective etch of the sacrificial layers; and
selectively removing sacrificial layers A from all non-sacrificial layers B and C, while the remaining layers B and C in the stack are held in place by the pillar structures, so that after removal of the sacrificial layers A, each of the sub-stacks contains the non-sacrificial layers B and C, the sacrificial layer A differing from the non-sacrificial layers B and C such that removal of the sacrificial layer A leaves the non-sacrificial layer B and the non-sacrificial layer C in all of the plurality of sub-stacks and such that no sub-stack includes the non-sacrificial layer B in the absence of the non-sacrificial layer C and no sub-stack includes the non-sacrificial layer C in the absence of the non-sacrificial layer B, the sacrificial layer A being at least three times as thick as the non-sacrificial layer B and as the non-sacrificial layer C.

US Pat. No. 10,170,548

INTEGRATED CAPACITORS WITH NANOSHEET TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:depositing alternating nanosheet layers and sacrificial layers onto a substrate;
simultaneously forming fins in a capacitor region and fins in a device region, wherein the fins in the capacitor region have a greater width than the fins in the device region;
selectively etching the sacrificial layers to form an undercut in the capacitor region and complete removal in the device region;
doping the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region;
depositing a high k dielectric layer onto the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region, and on the nanosheet layers in the device region; and
forming top and bottom electrodes in the capacitor region.

US Pat. No. 10,170,547

NANODEVICE

JAPAN SCIENCE AND TECHNOL...

1. A nanodevice comprising:nanogap electrodes comprising a first electrode and a second electrode so as to have a nanosized gap in between;
a nanoparticle disposed between the nanogap electrodes;
one or more gate electrodes, each of the one or more gate electrodes connected to a wire so as to apply an input voltage;
a floating gate electrode;
a control gate electrode to control a state of electric charge of the floating gate electrode;
a first insulating layer on which the nanogap electrodes and the floating gate electrode are disposed; and
a second insulating layer disposed on the first insulating layer, the nanogap electrodes, the floating gate electrode, and the nanoparticle,
wherein the control gate electrode is disposed on the first insulating layer, and
the control gate electrode is disposed on an opposite side to the nanoparticle with the floating gate electrode interposed therebetween, or
wherein the control gate electrode is disposed on the second insulating layer and above the floating gate electrode, and
wherein the one or more gate electrodes do not include the floating gate electrode and the control gate electrode.

US Pat. No. 10,170,545

MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a semiconductor substrate;
a trench extending into the substrate and proximate a transistor, the trench comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a transition configuration between the lower and upper portions of the trench, the transition configuration comprising a curved configuration and the liner comprising the only transition configuration for the lower and upper portions of the trench; and
an electrically insulative material in the lower and upper portions of the trench.

US Pat. No. 10,170,543

VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AIR GAP SPACERS

International Business Ma...

1. A method of forming a fin field effect transistor device with air gaps, comprising:forming a vertical fin on a substrate;
forming an inner protective cap on the vertical fin;
forming an outer protective cap on the inner protective cap;
forming a source/drain layer in contact with the vertical fin;
forming a sacrificial bottom spacer on each side of the vertical fin, and on the source/drain layer; and
forming a spacer cap layer on the sacrificial bottom spacer.

US Pat. No. 10,170,542

SEMICONDUCTOR DEVICE

Nuvoton Technology Corpor...

1. A semiconductor device, comprising:a substrate of a first conductivity type;
a metal-oxide-semiconductor-field-effect transistor (MOSFET), located on the substrate, wherein the MOSFET comprises:
a first epitaxial layer of a second conductivity type;
at least two body regions of the first conductivity type, respectively located in the first epitaxial layer;
at least two first doped regions of the second conductivity type, respectively located in the body regions; and
a gate structure, located on the first epitaxial layer between the first doped regions;
a first junction gate field-effect transistor (JFET), located on the substrate, the first JFET having a second epitaxial layer of the second conductivity type;
an isolation structure, located between the MOSFET and the first JFET to separate the first epitaxial layer from the second epitaxial layer; and
a buried layer of the second conductivity type, located between the MOSFET and the substrate, wherein the buried layer extends from below the MOSFET to below the isolation structure and below the first JFET, so as to electrically connect the MOSFET to the first JFET.

US Pat. No. 10,170,541

SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF ELECTRODES AND SUPPORTERS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a plurality of electrode structures on a substrate, the plurality of electrode structures having side surfaces; and
an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures, respectively, the upper supporter group including a plurality of upper supporters, at least some of the plurality of upper supporters each having an upper surface and a lower surface, the at least some of the plurality of upper supporters having a thickness between the upper surface and the lower surface, respectively,
wherein a first one of the upper surface and the lower surface has a curved profile, and a second one of the upper surface and lower surface has a flat profile, and
at least some of the plurality of upper supporters have the thickness that decreases towards the plurality of electrode structures.

US Pat. No. 10,170,540

CAPACITORS

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming separate wiring lines on a substrate, with spacing between adjacent separate wiring lines;
forming air gaps within the spacing by depositing capping material on the separate wiring lines and the spacing between the adjacent separate wiring lines;
forming a dielectric material over the capping material;
forming a trench in the dielectric material and over plural ones of the adjacent separate wiring lines, wherein the forming the trench opens the air gaps by removing a surface of the capping material; and
depositing conductive material within the opened air gaps through the trench.

US Pat. No. 10,170,539

STACKED CAPACITOR WITH ENHANCED CAPACITANCE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first conductive layer over the semiconductor substrate;
a second conductive layer over the first conductive layer;
a dielectric layer between the first conductive layer and the second conductive layer;
a cap layer over the second conductive layer;
a first contact via through the cap layer, the second conductive layer and the dielectric layer, and electrically connected to the first conductive layer, wherein a bottom of the first contact via stops at an upper surface of the first conductive layer; and
a second contact via through the cap layer, and electrically connected to the second conductive layer, wherein a bottom of the second contact via stops at an upper surface of the second conductive layer.

US Pat. No. 10,170,537

CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS

International Business Ma...

1. A method of forming an electrical device comprising:forming a stacked structure of at least a first semiconductor material layer and a second semiconductor material layer, wherein a material of the first and second semiconductor material layers have different oxidation rates;
oxidizing a sidewall of the stacked structure to form an oxide layer, wherein a first thickness of a first portion of the oxide layer that is present on the first semiconductor material layer is different from a second thickness of a second portion of the oxide layer that is present on the second semiconductor material layer;
removing the first or second portion of the oxide layer having a lesser thickness to provide an exposed surface of the stacked structure;
forming a replacement structure on a first portion of the stacked structure;
forming an epitaxial semiconductor material on the exposed surface of the stacked structure, wherein portions of the stacked structure having the epitaxial semiconductor material has a greater width than portions of the stacked structure not including the epitaxial semiconductor material;
forming an epitaxial crystalline semiconductor material on end portions of the stacked structure on opposing sides of the replacement structure;
forming a dielectric layer on exposed portions of the stacked structure having the epitaxial semiconductor material; and
forming a conductive material on the dielectric layer.

US Pat. No. 10,170,536

MAGNETIC MEMORY WITH METAL OXIDE ETCH STOP LAYER AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a first passivation layer over the substrate;
a second passivation layer over the first passivation layer;
a magnetic layer in the second passivation layer; and
an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer is in contact with the magnetic layer, and the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide.

US Pat. No. 10,170,535

ACTIVE-MATRIX TOUCHSCREEN

X-Celeprint Limited, Cor...

1. An active-matrix touchscreen having a touch area in which the active-matrix touchscreen is responsive to touches, the touchscreen comprising:a substrate;
a system controller;
a plurality of spatially separated independent touch elements disposed in a two-dimensional array within the touch area on and in contact with the substrate, each touch element comprising:
a mutual-capacitive touch sensor comprising at least two electrical conductors in a common layer on and in contact with the substrate, the two electrical conductors forming a capacitor; and
a touch controller circuit on and in contact with the substrate for providing one or more sensor-control signals to the touch sensor and for receiving a sense signal responsive to the one or more sensor-control signals from the touch sensor, wherein each touch sensor operates independently of any other touch sensor of the plurality of touch elements, wherein the two electrical conductors of each touch element are electrically separate from the two electrical conductors of any other touch element,
wherein the touch controller circuit of one or more of the plurality of spatially separated independent touch elements is disposed between the respective touch sensors of two or more of the plurality of spatially separated independent touch elements over the substrate.

US Pat. No. 10,170,534

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a plurality of display elements in a display area of the substrate, wherein each of the plurality of display elements includes a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode;
a drive circuit on an outer side of the display area and including a thin film transistor;
a first insulating layer on the drive circuit;
a first power supply line layer on the first insulating layer and overlapping the drive circuit;
a second insulating layer on the first power supply line layer; and
a connection electrode layer on the second insulating layer, wherein the connection electrode layer electrically connects the first power supply line layer to the opposite electrode.

US Pat. No. 10,170,533

DISPLAY DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. A display device comprising:a pixel array unit having pixels arranged in a matrix, at least one of the pixels having an electro-optical element, a first capacitor, a second capacitor, a first transistor configured to supply a data signal from a data line to the first capacitor, and a second transistor configured to flow a drive current to the electro-optical element;
a data signal line extending in a first direction; and
a scan line extending in a second direction perpendicular to the first direction,
wherein,
the first capacitor has a first electrode and a second electrode overlapped with the first electrode partly,
the second capacitor has a third electrode and a fourth electrode overlapped with the third electrode partly,
the first electrode is disposed in a first layer,
the fourth electrode is disposed in a second layer which is different from the first layer, and the second layer is disposed over the first layer,
the first electrode is electrically connected to a control terminal of the second transistor,
the second electrode is electrically connected to a first current terminal of the second transistor,
the third electrode is electrically connected to an anode electrode of the electro-optical element, and
the second electrode and the third electrode are electrically connected.

US Pat. No. 10,170,532

EL DISPLAY PANEL, POWER SUPPLY LINE DRIVE APPARATUS, AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An electroluminescence display device comprising:a plurality of pixel circuits arranged in a matrix form having a column and a row; and
a peripheral circuit configured to drive the pixel circuits,
wherein the pixel circuits includes:
a first pixel circuit configured to drive a first electroluminescence element, and
a second pixel circuit adjacent to the first pixel circuit along a column direction and configured to drive a second electroluminescence element,
wherein the peripheral circuits includes:
a first buffer circuit including a first transistor and a second transistor serially connected between a first node and a second node, and configured to alternatively output a high potential and a low potential, to the first pixel circuit via a first extraction wire,
a second buffer circuit including a third transistor and a fourth transistor serially connected between a third node and a fourth node, and configured to alternatively output a high potential and a low potential, to the second pixel circuit via a second extraction wire,
a first line connected to the first node of the first buffer circuit and the third node the second buffer circuit, and
a second line connected to the second node of the first buffer circuit and the fourth node the second buffer circuit,
wherein the first line and the second line is disposed on an input side of first buffer circuit.

US Pat. No. 10,170,531

ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING REACTION BLOCKING MEMBER ON COMMON VOLTAGE LINE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display comprising:a substrate divided into a pixel area, and a peripheral area enclosing the pixel area;
an organic light emitting diode which is in the pixel area, and comprises a first electrode, an organic emission layer and a second electrode;
a switching element which is in the pixel area, and controls the organic light emitting diode;
a protective layer covering the switching element;
a pixel defining layer which defines the pixel area in which the organic light emitting diode is disposed;
a common voltage line which is in the peripheral area, and transmits a common voltage to the second electrode; and
a reaction blocking part which is in the peripheral area and overlaps the common voltage line, the reaction blocking part comprising a same material as the first electrode,
wherein in the peripheral area:
a side surface of the common voltage line which is furthest from the pixel area is exposed by each of the protective layer and the pixel defining layer, and
the reaction blocking part which comprises the same material as the first electrode overlaps an entirety of the exposed side surface of the common voltage line which is furthest from the pixel area.

US Pat. No. 10,170,530

DISPLAY DEVICE INCLUDING FIRST AND SECOND SUBSTRATES, ONE INCLUDING A PAD ELECTRODE

Japan Display Inc., Mina...

1. A display device comprising:a first substrate including an insulating substrate with a first through hole, a pad electrode positioned above the insulating substrate, and a signal line electrically connected to the pad electrode;
a second substrate opposed to the first substrate;
a sealant which adheres the first substrate and the second substrate;
a line substrate including a connection line and disposed below the insulating substrate; and
a conductive material which electrically connects the pad electrode and the connection line, wherein
the pad electrode and the first through hole overlap the sealant,
a first part of the first through hole does not overlap the pad electrode and overlaps the sealant, and a second part of the first through hole overlaps both of the pad electrode and the sealant, and
the sealant is less absorptive than is the insulating substrate as to a wavelength less than 350 nm.

US Pat. No. 10,170,529

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:preparing a processed member, the processed member comprising:
an organic resin layer over a substrate; and
an element layer comprising a transistor over the organic resin layer;
irradiating the organic resin layer with a linear beam through the substrate by using a first apparatus, the first apparatus comprising:
a laser oscillator configured to emit a laser light;
an optical device configured to extend the laser light; and
a lens configured to condense the laser light into the linear beam; and
separating the organic resin layer from the substrate by using a separation apparatus after irradiating the organic resin layer with the linear beam,
wherein the separation apparatus comprises a roller, and
wherein the organic resin layer and the element layer are rolled up by the roller at the step of separating the organic resin layer from the substrate.

US Pat. No. 10,170,528

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display panel comprising:a driver circuit;
a signal line electrically connected to the driver circuit; and
a pixel electrically connected to the signal line, the pixel comprising:
a first display element comprising a first conductive film;
a second conductive film comprising a region overlapping with the first conductive film;
an insulating film comprising a region between the first conductive film and the second conductive film;
a pixel circuit electrically connected to the second conductive film and the signal line, the pixel circuit comprising a first transistor comprising silicon in a channel formation region; and
a second display element electrically connected to the pixel circuit,
wherein the insulating film comprises a first opening,
wherein the first conductive film comprises a second opening,
wherein the second opening overlaps the second display element, and
wherein the second conductive film is electrically connected to the first conductive film in the first opening.

US Pat. No. 10,170,527

ORGANIC LIGHT EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display, comprising:a substrate including a pixel region and a peripheral region enclosing the pixel region;
a scan line on the substrate and transferring a scan signal;
a data line crossing the scan line and transferring a data voltage;
a switching transistor disposed in the pixel region and electrically connected to the scan line and the data line;
a driving transistor disposed in the pixel region and electrically connected to the switching transistor;
a pixel-area passivation layer disposed on the switching transistor and the driving transistor;
a pixel electrode disposed on the pixel-area passivation layer;
a pixel partition wall layer disposed on the pixel-area passivation layer and having a pixel opening overlapping the pixel electrode;
an organic light emission layer disposed in the pixel opening and disposed on the pixel electrode;
a common electrode disposed on the organic light emission layer and the pixel partition wall layer;
a common voltage line disposed in the peripheral region and electrically connected to the common electrode;
a peripheral passivation layer disposed in the peripheral region and contacting a side wall of the common voltage line;
a peripheral driving voltage line disposed in the peripheral region and which transfers a driving voltage ELVDD;
a driving voltage pad to which the driving voltage ELVDD is applied from the outside;
a driving voltage connecting part connecting the driving voltage pad and the peripheral driving voltage line,
wherein the driving voltage pad is disposed at the same layer as the common voltage line.

US Pat. No. 10,170,524

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an input/output device comprising a display portion and a touch sensor, the input/output device having a first region, a second region adjacent to the first region, and a third region adjacent to the second region;
a member over the input/output device, the member having a first part and a second part;
a first fixing portion configured to fix an end of the first region of the input/output device and an end of the first part of the member;
a second fixing portion configured to fix an end of the third region of the input/output device; and
a roll-up portion connected to an end of the second part of the member and the second fixing portion,
wherein the second part of the member is located over the second region and the third region of the input/output device in an unfolded state,
wherein the roll-up portion is configured to roll up the second part of the member in a folded state, and
wherein the input/output device reversibly exists in the folded state and the unfolded state.

US Pat. No. 10,170,520

NEGATIVE-CAPACITANCE STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a negative capacitance steep-switch transistor comprising:receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, a shallow trench isolation (STI) layer disposed upon the substrate, and an inter-layer dielectric disposed on the trench contact and the cap;
forming a source/drain recess in the inter-layer dielectric extending to the trench contact;
forming a gate recess in the inter-layer dielectric extending to the gate;
depositing a ferroelectric material within the gate recess;
forming a source/drain contact within the source/drain recess in contact with the trench contact;
forming a gate contact within the gate recess in contact with the ferroelectric material;
forming a contact recess in a portion of the source/drain contact;
depositing a bi-stable resistive system (BRS) material in the contact recess in contact with the portion of the source/drain contact; and
forming a metallization layer contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

US Pat. No. 10,170,519

MAGNETORESISTIVE ELEMENT AND MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive element comprising:a first metal layer having a body-centered cubic structure;
a second metal layer having a hexagonal close-packed structure on the first metal layer;
a metal nitride layer on the second metal layer;
a first magnetic layer on the metal nitride layer;
an insulating layer on the first magnetic layer; and
a second magnetic layer on the insulating layer.

US Pat. No. 10,170,518

SELF-ASSEMBLED PATTERN PROCESS FOR FABRICATING MAGNETIC JUNCTIONS USABLE IN SPIN TRANSFER TORQUE APPLICATIONS

Samsung Electronics Co., ...

1. A method for providing a plurality of magnetic junctions on a substrate and usable in a magnetic device, the method comprising:providing a patterned seed layer, the patterned seed layer including a plurality of magnetic seed islands interspersed with an insulating matrix;
providing at least a portion of a magnetoresistive stack after the step of providing the patterned seed layer, the magnetoresistive stack including at least one magnetic segregating layer, the at least one magnetic segregating layer including at least one magnetic material and at least one insulator;
annealing the at least the portion of the magnetoresistive stack such that the at least one magnetic segregating layer segregates such that a plurality of portions of at least one magnetic material align with the plurality of magnetic seed islands and such that a plurality of portions of the at least one insulator align with the insulating matrix.

US Pat. No. 10,170,517

METHOD FOR FORMING IMAGE SENSOR DEVICE

Taiwan Semiconductor Manu...

1. A method for forming an image sensor device on a substrate, comprising:(a) recessing a portion of the substrate thereby forming a first shallow trench;
(b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench;
(c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as an intact mask thereby shrinking a width of the first deep trench;
(d) removing the spacer layer;
(e) forming a second oxide layer over the sidewall of the first shallow trench;
(f) forming a second liner layer in the substrate surrounding the first shallow trench; and
(g) filling the first shallow trench with a first isolation material thereby forming a first shallow trench isolation (STI) feature in the substrate.

US Pat. No. 10,170,515

IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;
performing a first implantation process on the substrate from the first surface to form a first shallow implantation region in the substrate adjacent to the first surface;
forming a device on the first surface adjacent to the first shallow implantation region;
performing a thinning process on the second surface of the substrate; and
performing a second implantation process on the substrate from the second surface to form a first deep implantation region and a second deep implantation region in the substrate adjacent to the second surface, wherein the first deep implantation region is formed to adjoin the first shallow implantation region, the second implantation process is performed such that at least a portion of the second deep implantation region is separated from the first deep implantation region, and the second deep implantation region is formed to peripherally surround the first deep implantation region.

US Pat. No. 10,170,514

IMAGE SENSOR

CMOSIS BVBA, Antwerp (BE...

1. An image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixels, each of the pixels comprising:a pinned photodiode;
a first sense node;
a second sense node;
a transfer gate connected between the pinned photodiode and the first sense node;
a first reset transistor connected between a voltage reference line and the second sense node;
a second reset transistor connected between the first sense node and the second sense node; and
a buffer amplifier having an input connected to the first sense node;the image sensor further comprising:a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array;
a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array;
wherein the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in each of the conversion gain modes the control logic is arranged to operate one of the first reset control line and the second reset control line to continuously switch on one of the first reset transistor and the second reset transistor during a readout period of an operational cycle of the pixels and;wherein, in each of the conversion gain modes the control logic is arranged to operate the first reset control line and the second reset control line such that the first reset transistor and the second reset transistor are switched on during a non-readout period of the operational cycle of the pixels;wherein for the low conversion gain mode;
the second reset transistor is switched on during a readout period, and the first reset control line is operated to switch on the first reset transistor to reset the first sense node and
for the high conversion pain mode;
the first reset transistor is switched on during a readout period, and the second reset control line is operated to switch on the second reset transistor to reset the first sense node.

US Pat. No. 10,170,512

UNIFORM-SIZE BONDING PATTERNS

Taiwan Semiconductor Manu...

15. A method comprising:forming an image sensor comprising:
depositing a first passivation layer over a first substrate, the first substrate having a plurality of photosensitive elements therein;
forming a first plurality of bonding pads in the first passivation layer, the first plurality of bonding pads having a first width and a first pitch; and
forming a second plurality of bonding pads in the first passivation layer, the second plurality of bonding pads having the first width, the second plurality of bonding pads being grouped into clusters, the second plurality of bonding pads having a second pitch between neighboring clusters and the first pitch between adjacent bonding pads in a first cluster, the first pitch being smaller than the second pitch;
forming a second substrate comprising:
forming a second passivation layer over a second substrate; and
forming a third plurality of hybrid bonding pads in the second passivation layer; and
bonding the second substrate is to the image sensor such that the first plurality of bonding pads and the second plurality of bonding pads are coupled with respective ones of the third plurality of bonding pads.

US Pat. No. 10,170,510

COLOR SEPARATION ELEMENT ARRAY, IMAGE SENSOR INCLUDING THE SAME, AND ELECTRONIC DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A color separation element array comprising:a transparent layer; and
a plurality of color separation elements provided in the transparent layer and configured to separate an incident light into a color light according to wavelength bands,
wherein the plurality of color separation elements comprise a first element having a first refractive index and a second element arranged in one side of the first element in a horizontal direction and having a second refractive index.

US Pat. No. 10,170,506

LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME

Shenzhen China Star Optoe...

1. A method for producing a low temperature poly-silicon (LTPS) array substrate, comprising:forming a gate of a thin-film transistor (TFT) on a substrate;
forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one in which an upper surface of the insulating layer is a plane;
exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer;
forming a source and a drain of the TFT on the polycrystalline silicon layer;
forming a pixel electrode on the insulating layer and a part of the drain;
forming a plain passivation layer on a source-drain electrode layer, which is fabricated from the source and the drain, and forming contact vias in the plain passivation layer for exposing surfaces of the gate and the drain, and the contact vias being disposed outside the polycrystalline silicon layer; and
forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is electrically connected to the gate via the contact via;
wherein before the insulating layer is formed on the substrate, a pre-operation is carried out to form a buffer layer on a portion of the substrate that is not covered by the gate such that an upper surface of the buffer layer and an upper surface of the gate collectively form a plane, and the pre-operation comprises the following steps:
forming the buffer layer and a negative photoresist layer on the substrate in sequence;
exposing one side of the substrate on the opposite side of the gate for removing a portion of the negative photoresist layer disposed right above the gate; and
removing the buffer layer disposed right above the gate such that a portion of the buffer layer is preserved on the portion of the substrate that is not covered by the gate; and
wherein the step of “exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer” comprises the following sub-steps:
exposing one side of the substrate on the opposite side of the gate for only preserving the first positive photoresist layer disposed on a first section disposed right above the gate;
injecting P-type impurity ions into the semiconductor layer outside the first section;
exposing one side of the substrate on the opposite side of the gate for forming the first positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; and
removing the first positive photoresist layer disposed on the second section.

US Pat. No. 10,170,505

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate comprising a display area and a peripheral area outside the display area;
a display unit over an upper surface of the substrate to correspond to the display area; and
a protective film comprising a protective film base and an adhesive layer, the protective film being attached to a lower surface of the substrate by the adhesive layer,
wherein the protective film base comprises a first protective film base corresponding at least to the display area, and a second protective film base having a physical property that is different from a physical property of the first protective film base and corresponding to at least a part of the peripheral area, and
wherein the second protective film base has a light transmittance that is greater than a light transmittance of the first protective film base.

US Pat. No. 10,170,504

MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate, comprising a thin film transistor and a pixel electrode formed on a base substrate, the pixel electrode being electrically connected with a drain electrode of the thin film transistor,wherein
the array substrate further comprises a light-shielding pattern provided above the thin film transistor;
the array substrate further comprises: a passivation layer provided between the thin film transistor and the pixel electrode, and a passivation layer via hole penetrating the passivation layer;
the array substrate further comprises a light-shielding conductive metal layer formed of a same material as the light-shielding pattern, and an entirety of the light-shielding conductive metal layer is provided in the passivation layer via hole; and
the pixel electrode is electrically connected with the drain electrode of the thin film transistor through the light-shielding conductive metal layer.

US Pat. No. 10,170,503

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL PANEL

Wuhan China Star Optoelec...

1. A thin film transistor array substrate, comprising: a substrate, a silicon thin film transistor formed on the substrate, an oxide semiconductor transistor, and a capacitor; the silicon thin film transistor and the oxide semiconductor transistor having a top gate structure; the capacitor and the silicon thin film transistor or the capacitor and the oxide semiconductor transistor being overlapping arrangement;wherein, the thin film transistor array substrate comprises:
a polysilicon layer and a semiconductor oxide layer provided and spaced on the substrate;
a gate insulating layer covering the polysilicon layer and the semiconductor oxide layer;
a first gate, a first metal layer, and a second gate provided and spaced on the gate insulating layer, the first gate being provided on the polysilicon layer, the second gate being provided on the semiconductor oxide layer;
an etch stop layer covering the first gate, the first metal layer, and the second gate, the etch stop layer comprising a first insulating layer and a second insulating layer provided by stacking;
a source-drain metal layer provided on the etch stop layer, the source-drain metal layer comprising a first source, a first drain, a second source, and a second drain, the first source and the first drain being respectively contacted with the polysilicon layer, the second source and the second drain being respectively contacted with the semiconductor oxide layer;
wherein, the polysilicon layer, the gate insulating layer, the first gate, the etch stop layer, the first source, and the first drain form the silicon thin film transistor; the semiconductor oxide layer, the gate insulating layer, the second gate, the etch stop layer, the second source, and the second drain form the oxide semiconductor transistor;
wherein, the silicon thin film transistor further comprises a floating gate;
wherein, the floating gate is provided between the first insulating layer and the second insulating layer, the floating gate is located on the first gate;
wherein, the first gate and the second gate are formed using the same mask process.

US Pat. No. 10,170,502

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel comprising:a substrate;
a buffer layer positioned on the substrate;
a semiconductor layer positioned on the buffer layer;
an intermediate insulating layer positioned on the semiconductor layer;
an upper conductive layer positioned on the intermediate insulating layer;
a lower conductive layer positioned between the substrate and the buffer layer,
wherein the semiconductor layer includes a first contact hole,
wherein the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole,
wherein the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole,
wherein the buffer layer comprises a third contact hole positioned over and exposing the lower conductive layer,
wherein the intermediate insulating layer comprises a fourth contact hole positioned in an overlapping relationship with the third contact hole,
wherein the lower conductive layer comprises a different material from a material of the semiconductor layer, and
wherein the upper conductive layer is in contact with an upper surface of the buffer layer in the fourth contact hole, and is in contact with an upper surface of the lower conductive layer in the third contact hole.

US Pat. No. 10,170,501

DISPLAY PANEL

INNOLUX CORPORATION, Mia...

1. A display panel, comprising:a substrate comprising a display region and a non-display region adjacent to the display region; and
a thin film transistor disposed on the non-display region of the substrate, wherein the thin film transistor comprises:
a semiconductor layer disposed over the substrate;
a first insulating layer disposed over the semiconductor layer;
a first metal layer disposed over the first insulating layer, and the first metal layer comprises a first branch portion and a second branch portion, wherein the first branch portion and the second branch portion are electrically connected to each other;
a second insulating layer disposed over the first insulating layer;
a plurality of first via holes and a plurality of second via holes penetrating through the first insulating layer and the second insulating layer, wherein the first branch portion and the second branch portion are disposed between the plurality of first via holes and the second via holes; and
a second metal layer disposed over the second insulating layer, wherein the second metal layer comprises a first portion electrically connected to the semiconductor layer through the plurality of first via holes and a second portion electrically connected to the semiconductor layer through the plurality of second via holes,
wherein a minimum distance between one of the first via holes and the first branch portion is a first distance, and a minimum distance between one of the second via holes and the second branch portion is a second distance, and the second distance is different from the first distance,
wherein the first metal layer serves as a gate electrode of the thin film transistor and the second metal layer serves as a source/drain electrode of the thin film transistor.

US Pat. No. 10,170,500

TRANSISTOR, LIQUID CRYSTAL DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:a transistor comprising a gate electrode, a source electrode, a drain electrode, and a semiconductor layer;
a first wiring electrically connected to the gate electrode, the first wiring extending in a first direction;
a second wiring electrically connected to the source electrode, the second wiring extending in a second direction and intersecting the first wiring;
a pixel electrode electrically connected to the drain electrode; and
a capacitor wiring having a first part extending in parallel with the first direction, and second and third parts each extending in parallel with the second direction,
wherein the pixel electrode has a first edge portion overlapping with the first part of the capacitor wiring, a second edge portion overlapping with the second part of the capacitor wiring, and a third edge portion overlapping with the third part of the capacitor wiring,
wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and
wherein the semiconductor layer overlaps with an entirety of the pixel electrode.

US Pat. No. 10,170,499

FINFET DEVICE WITH ABRUPT JUNCTIONS

International Business Ma...

1. A method of forming a FinFET device comprising:providing a plurality of semiconductor fins on a surface of an insulator layer;
forming a plurality of gate structures orientated perpendicular to and straddling each semiconductor fin of said plurality of semiconductor fins;
providing a dielectric spacer on vertical sidewalls of each gate structure;
removing, entirely by an anisotropic etch, an entirety of each semiconductor fin and a portion of said insulator layer, not protected by said gate structures and said dielectric spacers, wherein said removing provides semiconductor fin portions located on pedestal insulator portions of said insulator layer;
forming a source-side doped semiconductor material portion on one exposed vertical sidewall of each semiconductor fin portion and a drain-side doped semiconductor portion on another exposed vertical sidewall of each semiconductor fin portion; and
diffusing, by annealing, a dopant from said source-side doped semiconductor material portion into each semiconductor fin portion to form a source region along an entirety of said one exposed vertical sidewall of each semiconductor fin portion, and a dopant from said drain-side doped semiconductor material portion into each semiconductor fin portion to form a drain region along an entirety of said another exposed vertical sidewall of each semiconductor fin portion, said source region and said drain region are laterally separated from each other by a channel region of said semiconductor fin portion, and wherein a first junction between the source region and the channel region has a first dopant concentration gradient of less than 6 nm per decade, and a second junction between the drain region and the channel region has a second dopant concentration gradient of less than 6 nm per decade.

US Pat. No. 10,170,498

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

International Business Ma...

1. A method for fabricating a FinFET device comprising:providing a first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices on a strain relaxation buffer (SRB) substrate;
cutting the first long silicon fin forming a first and a second cut silicon fin, each of the first and second cut silicon fins having a vertical face at a fin end of the respective cut silicon fin, wherein the vertical faces of the first and second cut silicon fins are oriented facing each other;
cutting the first long silicon germanium fin forming a first and a second cut silicon germanium fins, each of the first and the second cut silicon germanium cut fin having a vertical face at a fin end of the respective cut silicon germanium fin, wherein the vertical faces of the first and second cut silicon germanium fins are oriented facing each other;
forming a tensile dielectric structure which bridges the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins; and
forming a compressive dielectric structure which bridges the vertical faces of the first and second cut silicon germanium fins to maintain compressive strain in the first and second cut silicon germanium fins.

US Pat. No. 10,170,497

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND METHOD FOR OPERATING AN ELECTRONIC DEVICE

1. A method for manufacturing an electronic device, the method comprising:providing a carrier comprising a hollow chamber structure within the carrier;
forming a first trench structure extending from a surface of the carrier to the hollow chamber structure such that an electrically isolated region is formed over the hollow chamber structure; and
forming at least one second trench structure extending from the surface of the carrier into a second region of the carrier, the second region of the carrier being laterally adjacent to the electrically isolated region, the second trench structure being at least a part of an electronic component provided in the second region of the carrier.

US Pat. No. 10,170,495

STACKED MEMORY DEVICE, OPTICAL PROXIMITY CORRECTION (OPC) VERIFYING METHOD, METHOD OF DESIGNING LAYOUT OF STACKED MEMORY DEVICE, AND METHOD OF MANUFACTURING STACKED MEMORY DEVICE

Samsung Electronics Co., ...

1. A method of manufacturing a stacked memory device, the method comprising:designing a layout of the stacked memory device, the layout including a first pattern;
calculating value of shift of the first pattern according to a first location of the first pattern in the layout;
obtaining a difference value between the first location of the first pattern and a second location of a second pattern formed through a first optical proximity correction (OPC) with respect to the first pattern;
determining, by a processor that executes software instructions, whether a second OPC is to be performed, based on the value of shift and the difference value;
when the processor determines that the second OPC is to be performed, forming a third pattern through the second OPC;
forming a mask, based on the second pattern or third pattern formed through the second OPC; and
forming the stacked memory device through a lithographic process using the mask.

US Pat. No. 10,170,494

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A stacked semiconductor memory device comprising:a stacked body comprising:
a plurality of underlying metal films comprising:
a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %,
a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or
a tungsten film;
a plurality of metal films provided on the underlying metal films and in contact with the underlying metal films, the metal films containing at least one of tungsten and molybdenum, and having a main orientation of (100) or (111); and
a plurality of insulator films,
wherein
the underlying metal films are provided between a lower surface of the metal films and the insulator films, and the underlying metal films are not provided on an upper surface of the metal-films, and
at least one of the plurality of insulator films contacts at least one of the plurality of underlying metal films and at least one the plurality of metal films.

US Pat. No. 10,170,493

ASSEMBLIES HAVING VERTICALLY-STACKED CONDUCTIVE STRUCTURES

Micron Technology, Inc., ...

1. An assembly, comprising:a stack of alternating first and second levels; the first levels comprising insulative material, and the second levels comprising conductive material; the assembly including channel material structures extending through the stack, and including insulative panel structures extending through the stack; the conductive material within the second levels having outer edges; the outer edges having proximal regions near the insulative panel structures and distal regions spaced from the insulative panel structures by the proximal regions; and
interface material along the outer edges of the conductive material, the interface material having a first composition along the proximal regions of the outer edges, and having a second composition along the distal regions of the outer edges; the first composition being different than the second composition.

US Pat. No. 10,170,492

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A memory device, comprising:a semiconductor substrate;
a first conductive layer, disposed on the semiconductor substrate;
a plurality insulating layers, disposed on the first conductive layer;
a plurality of second conductive layers, alternatively stacked with the insulating layers and insulated from the first conductive layer;
at least one contact plug comprising a first conductive material, passing through the insulating layers and the second conductive layers, insulated from the second conductive layers and electrically contacting to the first conductive layer; and
at least one dummy plug, formed in an opening passing through a bottommost layer of the insulating layers and the second conductive layers, corresponding to the at least one contact plug, wherein the at least one dummy plug comprises a dielectric isolation layer formed on a sidewall and a bottom of the opening and a second conductive material fully filling the opening and insulated from the second conductive layers and the first conductive layer.

US Pat. No. 10,170,491

MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER

Micron Technology, Inc., ...

1. A memory comprising:a vertical pillar coupled to a source; and
a dielectric etch stop tier over the source, the dielectric etch stop tier comprising a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the dielectric etch stop tier and separating the dielectric etch stop tier into multiple dielectric tiers.

US Pat. No. 10,170,490

MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS

Micron Technology, Inc., ...

1. An apparatus comprising:a piece of semiconductor material formed over a substrate;
a pillar extending through the piece of semiconductor material;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar; and
transistors coupled to the select gate through a portion of the piece of semiconductor material, the transistors including sources and drains, the transistors including gates electrically uncoupled to each other, and at least a portion of the piece of semiconductor material forms the sources and drains of the transistors, and a portion of the select gate.

US Pat. No. 10,170,489

HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:first, second, third, and fourth high-voltage transistors arranged on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent each other in a gate-width direction, the third and fourth high-voltage transistors being adjacent each other in the gate-width direction, the first and third high-voltage transistors being adjacent each other in a gate-length direction, the second and fourth high-voltage transistors being adjacent each other in the gate-length direction, and each of the transistors having a gate electrode, and a gate electrode contact formed on the gate electrode; and
a conductive line provided on a portion of an element isolation region, the conductive line positioned between the first and third transistors and between the second and fourth transistors,
wherein the gate electrode contact is formed on a fringe portion formed by extending an end portion of the gate electrode onto the element isolation region in the gate-width direction.

US Pat. No. 10,170,488

NON-VOLATILE MEMORY OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANF...

1. A semiconductor device, comprising:a substrate having a surface;
a plurality of isolation structures disposed in the substrate to at least define a first region, a second region, and a third region on the substrate;
a floating gate memory cell disposed in the first region, wherein the floating gate memory cell comprises:
an erase gate structure disposed on the surface of the substrate;
a first floating gate structure and a second floating gate structure recessed in the substrate and located at two opposite sides of the erase gate structure;
a first word line disposed on the surface of the substrate, wherein the first word line is adjacent to the first floating gate structure opposite to the erase gate structure;
a common source disposed in the substrate between the first floating gate structure and the second floating gate structure;
a second word line disposed on the surface of the substrate, wherein the second word line is adjacent to the second floating gate structure opposite to the erase gate structure;
a first spacer disposed between the first floating gate structure and the first word line; and
a second spacer disposed between the second floating gate structure and the second word line;
a first device disposed in the second region; and
a second device disposed in the third region.

US Pat. No. 10,170,487

DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A three-dimensional integrated circuit comprising:a first transistor on a first level;
a word line coupled to the first transistor;
a first via coupled to the first transistor;
a second transistor on a second level different from the first level;
another word line coupled to the second transistor; and
a second via coupled between the first transistor and the second transistor.

US Pat. No. 10,170,486

SEMICONDUCTOR STORAGE DEVICE COMPRISING PERIPHERAL CIRCUIT, SHIELDING LAYER, AND MEMORY CELL ARRAY

Semiconductor Energy Labo...

1. A semiconductor storage device comprising:a first transistor;
a conductive film over the first transistor; and
a plurality of second transistors each comprising a channel region,
wherein a channel region of the first transistor comprises silicon,
wherein each of the plurality of channel regions of second transistors comprises an oxide semiconductor, and
wherein entirety of the plurality of second transistors overlaps with the conductive film.

US Pat. No. 10,170,485

THREE-DIMENSIONAL STACKED JUNCTIONLESS CHANNELS FOR DENSE SRAM

International Business Ma...

1. A method, comprising:forming a heteroepitaxial stack of layers of a p-doped material, an n-doped material, and a sacrificial material;
patterning the heteroepitaxial stack;
forming a dummy gate on the patterned heteroepitaxial stack;
forming sidewall spacers on the dummy gate;
removing the sacrificial material from between the layers of p-doped material and n-doped material;
depositing a dielectric isolation material adjacent the sidewall spacers and between the layers of p-doped material and n-doped material;
removing the dummy gate to form a gate opening;
removing the dielectric isolation material from between the layers of p-doped material and n-doped material;
depositing a gate dielectric on surfaces in the gate opening and on the layers of p-doped material and n-doped material under the gate opening;
depositing a workfunction metal on the gate dielectric;
filling the gate opening with a fill metal; and
forming contacts to the layers of p-doped material and n-doped material;
wherein the deposited gate dielectric on the layers of p-doped material and n-doped material and the deposited workfunction metal define junctionless field effect transistor devices.

US Pat. No. 10,170,483

SEMICONDUCTOR DEVICE, STATIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) cell comprising:two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors, wherein the PU transistors and the PD transistors are configured to form two cross-coupled inverters, the PG transistors are electrically connected to the cross-coupled inverters, and at least one of the PU transistors, the PG transistors, and the PD transistors comprises:
a semiconductor fin comprising at least one channel portion;
an epitaxy structure over the semiconductor fin;
at least one isolation structure adjacent to the semiconductor fin; and
a plurality of dielectric fin sidewall structures on opposite sides of the epitaxy structure and over the isolation structure.

US Pat. No. 10,170,481

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor memory device comprising:a substrate, wherein the substrate comprises a memory cell region and a periphery region;
a plurality of bit lines, disposed on the substrate, within the memory cell region;
a gate, disposed on the substrate, within the periphery region;
a spacer layer covering the bit lines and a sidewall of the gate; and
a first spacer disposed on the sidewall and an opposite sidewall of the gate and covering the spacer layer.

US Pat. No. 10,170,480

METHODS FOR MANUFACTURING A FIN-BASED SEMICONDUCTOR DEVICE INCLUDING A METAL GATE DIFFUSION BREAK STRUCTURE WITH A CONFORMAL DIELECTRIC LAYER

TAIWAN SEMICONDUCTOR MANU...

16. A method of forming a fin-like field-effect transistor (FinFET) device, the method comprising:forming a first active region and a second active region on a substrate, such that the first active region and the second active region are spaced apart from each other in a first direction;
forming a first group of fins in the first active region and a second group of fins in the second active region, such that each fin of the first and second groups of fins extends along a second direction substantially perpendicular to the first direction;
forming one or more gates over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and a functional gate;
forming a first sidewall spacer along the first isolation gate; and
forming a source/drain feature on a side of the first sidewall spacer and extending into the substrate to a first depth,
wherein the first isolation gate includes a dielectric layer and a metal gate layer, the first isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, the source/drain feature, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a second depth that is greater than the first depth.

US Pat. No. 10,170,479

FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

International Business Ma...

1. A complementary metal oxide semiconductor (CMOS) device with punch-through stops/wells, comprising:one or more vertical fin(s) on a substrate in a first region and one or more vertical fin(s) on the substrate in a second region, wherein the first region is adjacent to the second region;
a first dopant source on the one or more vertical fin(s) in the first region, wherein the first dopant source extends along a portion of the length of each of the one or more vertical fins in the first region;
a second dopant source on the one or more vertical fin(s) in the second region, wherein the second dopant source extends along a portion of the length of each of the one or more vertical fins in the second region;
a first doped region in the substrate forming a first punch-through stop/well below the first dopant source, wherein the first punch-through stop/well includes a first dopant at a concentration in the range of about 1×1017/cm3 to about 1×1019/cm3;
a second doped region in the substrate forming a second punch-through stop/well below the second dopant source, wherein the second punch-through stop/well includes a second dopant at a concentration in the range of about 1×1017/cm3 to about 1×1019/cm3;
an isolation spacer on the first dopant source and the second dopant source, wherein the thickness of the first dopant source and second dopant source are in the range of about 50 nm to about 150 nm; and
a gate dielectric layer on at least a portion of the isolation spacer, at least a portion of the one or more vertical fins) in the first region, and at least a portion of the one or more vertical fin(s) in the second region.

US Pat. No. 10,170,478

SPACER FOR DUAL EPI CMOS DEVICES

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor comprising:forming a first semiconductor device comprising two or more first gate stacks formed on a first substrate, and forming a second semiconductor device comprising two or more second gate stacks formed on the first substrate, the first semiconductor device including a first fin region having first source-drain areas and the second semiconductor device including a second fin region having second source-drain areas, the first source-drain area and the second source drain area each comprising a horizontal surface on an upper surface of the respective source-drain area:
depositing a wet-etch resistant spacer material on the first and second semiconductor devices;
removing a portion of the wet-etch resistant spacer material from the first fin region and the second fin region with anisotropic spacer reactive ion etch such that remaining portions of the wet-etch resistant spacer material form first wet-etch resistant spacers having a first thickness on the first semiconductor device and second wet-etch resistant spacers having a second thickness equal to the first thickness on the second semiconductor device;
depositing a first nitride liner on the first and second semiconductor devices;
depositing a dielectric layer on the first nitride liner;
planarizing the dielectric layer;
selectively removing the dielectric layer from between the first wet-etch resistant spacer material in the first fin region and the second wet-etch resistant spacer in the second fin region;
depositing a second nitride liner on the first and second semiconductor devices and selectively removing the second nitride liner from the first semiconductor device;
growing a first epitaxial layer on the first source-drain area by an epitaxial growth process such that the first epitaxial layer extends the length of the first source-drain area and covers the horizontal surface of the first source-drain area except areas covered by the first gate stack and the first wet-etch resistant spacer material;
depositing a third nitride liner on the first and second semiconductor devices and selectively removing the third nitride liner from the second semiconductor device; and
growing a second epitaxial layer on the second source-drain area by a second epitaxial growth process.

US Pat. No. 10,170,477

FORMING MOSFET STRUCTURES WITH WORK FUNCTION MODIFICATION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first transistor of a first type comprising a first channel region material and a first gate electrode, the first gate electrode comprising gate materials including a work function material and a work function modifying material; and a second transistor of a second type comprising a second channel region material and a second gate electrode, the second gate electrode comprising gate materials including the work function material; wherein the work function modifying material is lanthanum oxide; the work function modifying material is applied to a dielectric layer; the work function material for the first and second gate electrodes are identical; and the work function modifying material is configured to change the threshold voltage of the first transistor; and an insulator layer between the first transistor and the second transistor, wherein a first portion of the insulator layer includes the work function material and a second portion of the insulator layer includes the work function material and the work function modifying material, wherein the first channel region and the second channel region extends through a horizontal insulator layer.

US Pat. No. 10,170,476

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY

INTERNATIONAL BUSINESS MA...

1. A method of manufacturing a semiconductor structure, comprising:forming an N-well in a p-type substrate;
forming a P-well in the substrate;
forming a PFET device on the N-well at a front side of the substrate;
forming an NFET device on the P-well at the front side of the substrate;
forming an isolation region at the front side of the substrate and contacting both the N-well and the P-well; and
forming a through wafer via (TWV) extending from a back side of the substrate to a bottom surface of the isolation region,
wherein the P-well is devoid of a substrate contact at the front side of the substrate; and
the N-well comprises an N-well contact at the front side of the substrate.

US Pat. No. 10,170,474

TWO DIMENSION MATERIAL FIN SIDEWALL

International Business Ma...

1. A semiconductor structure fabrication method comprising:forming neighboring fins associated with a semiconductor substrate, the neighboring fins separated by a fin well;
forming a fin cap upon each neighboring fin;
forming a well-plug within a bottom portion of the fin well such that sidewall portions of the neighboring fins are exposed to an upper portion of the fin well; and
forming a 2D material upon the sidewall portions of the neighboring fins.

US Pat. No. 10,170,472

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

16. An integrated circuit device, comprising:a substrate comprising adjacent first and second substrate regions;
active fins protruding from the substrate in the first and second substrate regions and extending parallel to one another in a first direction;
first and second gate electrodes extending co-linearly in a second direction that intersects the first direction, wherein the first and second gate electrodes are electrically isolated and extend on first and second active fins of the active fins in the first substrate region to define first and second transistors, respectively;
first and second wordlines extending in parallel on the first and second substrate regions; and
first and second wordline contacts connecting the first and second gate electrodes to the first and second wordlines, respectively,
wherein the first and second transistors in the first substrate region are between the first and second wordline contacts.

US Pat. No. 10,170,471

BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

International Business Ma...

1. A semiconductor device, comprising:a base layer; and
a plurality of fins atop the base layer, wherein:
each fin comprises:
an undoped silicon oxide fin layer atop the base layer;
a doped silicon oxide fin layer atop the undoped silicon oxide fin layer;
a silicon fin layer atop the doped silicon oxide fin layer; and
a hard mask cap atop the silicon fin layer;
each fin has a uniform width along a height of the respective fin along a first direction;
the height spans from an upper surface of the base layer to an upper surface of the hard mask cap; and
the first direction is a direction that intersects a first fin and a second fin of the plurality of fins.

US Pat. No. 10,170,470

SWITCHING DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A switching device, comprising:a semiconductor substrate;
a plurality of gate trenches provided in an upper surface of the semiconductor substrate;
bottom insulating layers covering bottom surfaces of the gate trenches;
gate insulating layers covering side surfaces of the gate trenches; and
gate electrodes arranged in the gate trenches and insulated from the semiconductor substrate by the bottom insulating layers and the gate insulating layers,
wherein
a device region is a region in the upper surface in which the plurality of gate trenches is provided,
the device region includes a peripheral portion provided at a periphery of the device region and a center portion surrounded by the peripheral portion, the gate insulating layers being located in the peripheral portion and the center portion,
the gate insulating layers in the center portion have a first thickness and a first dielectric constant,
one or more of the gate insulating layers in the peripheral portion has, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant, and
the semiconductor substrate comprises:
a first region being of a first conductivity type and in contact with the gate insulating layers in the center portion and the peripheral portion;
a body region being of a second conductivity type and in contact with the gate insulating layers under the first region in the center portion and the peripheral portion; and
a second region being of the first conductivity type and in contact with the gate insulating layers under the body region in the center portion and the peripheral portion.

US Pat. No. 10,170,469

VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

International Business Ma...

1. A semiconductor structure comprising:a first vertical field-effect transistor comprising a first threshold voltage; and
at least a second vertical field-effect transistor comprising a second threshold voltage that is different from the first threshold voltage,
wherein each of the first vertical field-effect transistor and the second vertical field-effect transistor comprises
a source layer and a drain layer, wherein each drain layer is formed in a region of the first vertical field-effect transistor and second vertical field-effect transistor, respectively, above the source layer,
substrate in contact with the source layer,
a first spacer layer on the source layer,
a second spacer layer, where a portion of the drain layer extends over the second spacer, and
metal gate in contact with sidewalls of the epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer.

US Pat. No. 10,170,467

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three dimensional (3D) semiconductor memory device, comprising:a semiconductor substrate, having a first protruding portion;
a first transistor formed in the semiconductor substrate, comprising:
a first source line, disposed in the semiconductor substrate and partially extending below the first protruding portion;
a first gate line configured to surround and cover the first protruding portion and electrically separated from the first source line and the first protruding portion; and
a first drain electrode formed on and connecting to the first protruding portion;
a plurality of conductive planes stacked on the semiconductor substrate and electrically separated from each other;
a first conductive pillar passing through the conductive planes and connecting to the first drain electrode;
a first memory layer disposed between the conductive planes and the first conductive pillar; and
a plurality of memory cells formed at a plurality points of intersection correspondingly formed between the conductive planes, the first conductive pillar and the memory layer; and connected in series by the first conductive pillar.

US Pat. No. 10,170,466

DEVICE HAVING AN ACTIVE CHANNEL REGION

HEWLETT-PACKARD DEVELOPME...

1. A transistor comprising:a substrate;
a drain in the substrate;
a source in the substrate;
a channel between the drain and the source, the channel surrounding the drain and having a channel length to width ratio; and
a gate over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

US Pat. No. 10,170,465

CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

International Business Ma...

9. A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:forming a bottom spacer layer on a substrate;
forming a dummy gate layer on the bottom spacer layer;
forming a top spacer layer on the dummy gate layer;
forming one or more fin trenches, where at least one of the one or more fin trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a vertical fin in at least one of the one or more fin trenches;
forming one or more diode trenches, where at least one of the one or more diode trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches; and
forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, wherein the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

US Pat. No. 10,170,464

COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

International Business Ma...

1. A semiconductor device, comprising:a semiconductor substrate;
a buffer layer disposed on the semiconductor substrate, wherein the buffer layer comprises a first buffer layer and a second buffer layer, wherein the first buffer layer comprises a first layer of epitaxial compound semiconductor material that is epitaxially grown on the semiconductor substrate, wherein the second buffer layer comprises a second layer of epitaxial compound semiconductor material that is epitaxially grown on the first buffer layer, wherein the first and second layers of epitaxial compound semiconductor material are formed of different compositions of compound semiconductor material;
an active device layer disposed on the buffer layer, wherein the active device layer comprises a layer of epitaxial semiconductor material that is epitaxially grown on the buffer layer;
a contact plug disposed within a contact opening formed in the second buffer layer; and
a buried resistor disposed within a cavity formed within the first buffer layer below the second buffer layer and the active device layer, wherein a portion of the cavity within the first buffer layer comprises an undercut region which undercuts a portion of the second buffer layer surrounding the contact plug within the contact opening formed in the second buffer layer such that a portion of the buried resistor within the undercut region of the cavity is disposed underneath a bottom surface of the second buffer layer;
wherein the contact plug is connected to the buried resistor;
wherein the buffer layer serves to match a lattice constant of the semiconductor substrate to a lattice constant of the layer of epitaxial semiconductor material of the active device layer.

US Pat. No. 10,170,463

BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating two transistors, comprising:forming a first semiconductor fin and a second semiconductor fin, where each of the first and second semiconductor fins comprises a doped lower portion;
forming lower spacers around the first and second semiconductor fins, the lower spacer around the first semiconductor fin having a height lower than a height of the lower spacer around the second semiconductor fin;
forming a gate stack around the first semiconductor fin and the second semiconductor fin;
wherein the height of the lower spacer around the first semiconductor fin rises below a level of the doped lower portion of the first semiconductor fin and wherein the height of the lower spacer around the second semiconductor fin rises above a level of the doped lower portion of the second semiconductor fin;
forming an upper spacer around the first and second semiconductor fin and over the gate stacks;
etching away the gate stack around the second semiconductor fin; and
forming an extrinsic base around the second semiconductor fin and under the upper spacer in a region exposed by etching away the gate stack.

US Pat. No. 10,170,462

DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising a display panel including an active area where an image is displayed and a pad area corresponding to a non-display area, the display device comprising:a first substrate and a second substrate, which face each other;
an organic light emitting diode arranged on the first substrate in the active area;
a signal pad arranged on the first substrate in the pad area;
a connection electrode connected with one side of the signal pad; and
a flexible circuit film connected with the connection electrode,
wherein the signal pad includes a plurality of lines arranged by interposing an insulating film therebetween, and the plurality of lines are electrically connected with each other, and
wherein the signal pad includes at least two lines of a first line arranged on the same layer as a gate line arranged in the active area, a second line arranged on the same layer as a data line arranged in the active area, and a third line arranged on the same layer as a pixel electrode arranged in the active area.

US Pat. No. 10,170,461

ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

Taiwan Semiconductor Manu...

1. A method of testing a semiconductor device, the semiconductor device comprising:a semiconductor substrate;
a interconnect structure disposed over the semiconductor substrate;
a first conductive pad disposed over the interconnect structure;
a second conductive pad disposed over the interconnect structure and spaced apart from the first conductive pad;
a third conductive pad disposed over the interconnect structure and spaced apart from the first and second conductive pads;
a fourth conductive pad disposed over the interconnect structure and spaced apart from the first, second, and third conductive pads;
a first ESD protection element, including a first fuse, electrically coupled between the first and second conductive pads;
a second ESD protection element, including a second fuse, electrically coupled between the third and fourth conductive pads;
a first device under test (DUT) electrically coupled between the first and third conductive pads; and
a second DUT electrically coupled between the second and fourth conductive pads;
the method comprising:
subjecting the semiconductor device to an electrostatic discharge (ESD) prone environment during manufacturing or testing of the semiconductor device;
after subjecting the semiconductor device to the ESD prone environment, blowing away the first fuse and blowing away the second fuse; and
after blowing away the first and second fuses, conducting an electro-migration test by applying electrical stress to the first DUT or to the second DUT.

US Pat. No. 10,170,460

VOLTAGE BALANCED STACKED CLAMP

International Business Ma...

1. An apparatus for balancing voltages, comprising:a voltage supply pin operatively connected to a voltage divider, wherein the voltage supply pin supplies a total voltage to the voltage divider;
a stacked circuit operatively connected to the voltage divider, wherein the stacked circuit comprises a first layer and a second layer, wherein the first layer is not coupled to the second layer, and the voltage divider distributes the total voltage as to the stacked circuit;
a voltage grounder operatively connected to the voltage divider and wherein the first layer and the second layer comprise:
a group of inverters within the first layer operatively connected to a first n-type channel field effect transistor (NFET), wherein the group of inverters within the first layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the first n-type channel field effect transistor (NFET); and
a group of inverters within the second layer operatively connected to a second n-type channel field effect transistor (NFET), wherein the group of inverters within the second layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the second n-type channel field effect transistor (NFET); and
a third node, wherein the third node is point (principal nodes or junctions) coupled to a first p-type field effect transistor (PFET) at a gate terminal of the first PFET, the second inverter, and the third inverter of the first layer.

US Pat. No. 10,170,457

COWOS STRUCTURES AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:attaching a first die and a second die to an interposer;
attaching a first substrate to a first surface of the first die and a first surface of the second die, the first substrate comprising silicon, the first surface of the first die being opposite to a second surface of the first die that is attached to the interposer, and the first surface of the second die being opposite to a second surface of the second die that is attached to the interposer;
forming a plurality of electrical connectors over the interposer, each electrical connector of the plurality of electrical connectors being electrically connected to a respective through via of a plurality of through vias comprised in the interposer, wherein the first substrate physically supports the interposer during the forming of the plurality of electrical connectors;
bonding the interposer to a second substrate using the plurality of electrical connectors; and
attaching a heat dissipation lid to the second substrate, the interposer being disposed in an inner cavity of the heat dissipation lid.

US Pat. No. 10,170,456

SEMICONDUCTOR PACKAGES INCLUDING HEAT TRANSFERRING BLOCKS AND METHODS OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semiconductor chips,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via is electrically isolated from the interconnection layer and the first and second semiconductor chips.

US Pat. No. 10,170,454

METHOD AND APPARATUS FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICE DIE FROM A MAPPED WAFER

1. A system for performing a direct transfer of a plurality of semiconductor die from a first substrate to a second substrate, the system comprising:a first conveyance mechanism to convey the first substrate;
a second conveyance mechanism to convey the second substrate;
a transfer mechanism disposed adjacent to the first conveyance mechanism to effectuate the direct transfer;
a controller including one or more processors communicatively coupled with the first conveyance mechanism, the second conveyance mechanism, and the transfer mechanism, the controller having executable instructions, which when executed, cause the one or more processors to perform operations including:
determining positions of the plurality of semiconductor die based at least in part on map data, the map data describing the positions of the plurality of semiconductor die of a semiconductor wafer,
conveying at least one of the first substrate or the second substrate such that the first substrate, the second substrate, and the transfer mechanism are in a direct transfer position, and
activating the transfer mechanism to perform the direct transfer of the plurality of semiconductor die.

US Pat. No. 10,170,451

SEMICONDUCTOR DEVICE METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;
exposing the first set of through vias and the reference via with a planarization process on a first side of the semiconductor die;
connecting the first set of through vias on a second side of the semiconductor die opposite the first side to a second semiconductor die; and
after the connecting the first set of through vias, exposing a first surface of the reference via with a singulation process.

US Pat. No. 10,170,450

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

IMEC vzw, Leuven (BE)

1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate, wherein each IC device comprises a dielectric bonding layer at its outer surface, and wherein each IC device further comprises one or more metal contact structures, the method comprising:producing at least one cavity in the outer surface of the first IC device, the cavity traversing at least the dielectric bonding layer of the first IC device;
aligning the first substrate with respect to the second substrate, and forming a substrate assembly by direct bonding between the dielectric bonding layers, so that in the substrate assembly the cavity formed in the first IC device overlaps a metal contact structure of the second IC device;
after bonding, optionally thinning the first substrate;
producing a Through Substrate Via (TSV) opening in the first substrate, the TSV opening overlapping the cavity;
forming an aggregate opening comprising the TSV opening and the cavity, thereby exposing at least part of the metal contact structure of the second IC device;
after the formation of an isolation liner on at least part of the sidewalls of the aggregate opening, producing a metal interconnection plug in the aggregate opening, that contacts the metal contact structure of the second IC device, and forms at least part of an interconnection path between the metal contact structure of the second IC device and a metal contact structure of the first IC device, wherein the first IC device comprises a stack of dielectric layers with the dielectric bonding layer being present on top of the stack of dielectric layers, wherein the cavity further traverses one or more of the stack of dielectric layers, wherein the first IC device comprises a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, and wherein the stack of dielectric layers comprises a stack of intermetal dielectric layers in the BEOL portion, or in the BEOL portion as well as in the FEOL portion of the first IC device.

US Pat. No. 10,170,449

DEFORMABLE CLOSED-LOOP MULTI-LAYERED MICROELECTRONIC DEVICE

International Business Ma...

1. A deformable closed-loop multi-layered microelectronic device comprising:a top layer comprising at least a first section and a second section, wherein the first section and the second section of the top layer are pivotable with respect to each other to deform the top layer;
a bottom layer comprising at least a first section and a second section, wherein the first section of the bottom layer is vertically aligned with the first section of the top layer and the second section of the bottom layer is vertically aligned with the second section of the top layer, wherein the first section and the second section of the bottom layer are pivotable with respect to each other to deform the bottom layer; and
a middle layer disposed between the top layer and the bottom layer, the middle layer comprising at least a first section and a second section, wherein the first section and the second section of the middle layer are pivotable with respect to each other to deform the middle layer,
wherein the middle layer comprises a first pivot provided to a first terminal end of the first section of the middle layer for allowing the first section to rotate about the first pivot, wherein the first terminal end of the first section of the middle layer is vertically sandwiched between a first terminal end of the first section of the top layer and a first terminal end of the first section of the bottom layer; and
wherein the first pivot is connected to the first terminal end of the first section of the bottom layer through a first adhesive and connected to the first terminal end of the first section of the top layer through a second adhesive, such that the first section of the bottom layer and the first section of the top layer are pivotable in a substantially synchronized manner to deform the bottom layer and the top layer in a substantially synchronized manner.

US Pat. No. 10,170,448

APPARATUS AND METHOD OF POWER TRANSMISSION SENSING FOR STACKED DEVICES

Micron Technology, Inc., ...

1. An apparatus comprising:a substrate;
a plurality of dies, each die of the plurality of dies comprising:
a circuit;
a first conductive via through each die, configured to provide a power supply voltage;
an on-die bus coupled to the first conductive via and configured to provide the power supply voltage from the first conductive via to the circuit;
a second conductive via through each die; and
a switch disposed between the on-die bus and the second conductive via, configured to selectively couple the on-die bus to the second conductive via,
a first conductive path across the substrate and the plurality of dies, configured to provide the power supply voltage to the first conductive via, the first conductive path comprising:
a first bump between the substrate and the plurality of dies, coupled to a corresponding first conductive via of a die of the plurality of dies adjacent to the substrate and the first bump configured to provide the power supply voltage to the corresponding first conductive via;
a plurality of the first pillars configured to couple the first conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of first conductive vias; and
a second conductive path across the substrate and the plurality of dies, the second conductive path comprising:
a second bump between the substrate and the plurality of dies, coupled to a corresponding second conductive via of the die of the plurality of dies adjacent to the substrate;
a plurality of second pillars configured to couple the second conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of the second conductive vias.

US Pat. No. 10,170,447

ADVANCED CHIP TO WAFER STACKING

International Business Ma...

1. A method of forming a 3D chip stack comprising:forming a first bonding layer on a top surface of a first wafer, the first wafer comprising first chips having an upper surface coplanar with the top surface of the first wafer;
forming a second bonding layer on a top surface of a second wafer, the second wafer comprising second chips having an upper surface coplanar with the top surface of the second wafer;
separating the second chips from the second wafer;
placing the separated second chips in loading bays of a vacuum chuck, wherein a location of each of the loading bays is in a corresponding position to each of the first chips on the first wafer, the separated second chips are held in the loading bays using vacuum suction to a surface of the separated second chips opposite the second bonding layer, and each loading bay of the vacuum chuck comprises a plurality of moveable columns together providing a curved contact surface to hold the separated second chips;
bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process creating a third bonding layer, wherein the third bonding layer includes the first bonding layer and the second bonding layer; and
depositing a dielectric over the bonded first chips and second chips.

US Pat. No. 10,170,446

STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT

INTERNATIONAL BUSINESS MA...

1. A method forming an interconnect structure, the method comprising:depositing a first solder bump on a chip;
depositing a second solder bump on a laminate, the second solder bump comprising a nickel copper colloid;
joining the chip to the laminate;
depositing an underfill material around the first solder bump and the second solder bump; and
performing a reflow process at a temperature that is lower than a temperature used to join the chip to the laminate to convert the first solder bump and the second solder bump to an all intermetallic interconnect.

US Pat. No. 10,170,444

PACKAGES FOR SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A package for a semiconductor device, comprising:an integrated circuit die mounting region;
a molding material disposed around the integrated circuit die mounting region;
an interconnect structure disposed over the molding material and the integrated circuit die mounting region, the interconnect structure comprising a plurality of contact pads;
a connector coupled to each of the plurality of contact pads, wherein two or more connectors each comprises a first portion having a ball shape including a rounded top and sides and a second portion having a raised edge vertically further from a respective contact pad than the first portion, the second portion having vertical sidewalls and a planar top surface protruding from the rounded top of the first portion, wherein a material composition of the second portion has a same material composition as the first portion, wherein the first portion is in contact with a respective contact pad of the plurality of contact pads, wherein the second portion comprises an alignment feature, and wherein the first portion and second portion comprises a eutectic material; and
a raised insulating material layer disposed over at least one of the connectors having an alignment feature, the raised insulating material layer having a same shape as the alignment feature, the raised insulating material layer comprising an oxide of the material composition of the second portion.

US Pat. No. 10,170,443

DEBONDING CHIPS FROM WAFER

International Business Ma...

1. A debonding device comprising:a first member provided with a recess for receiving a carrier body, the carrier body including a first plate, a second plate, and a plurality of semiconductor chips, the semiconductor chips being sandwiched between the first plate and the second plate, the first plate being opposed to a bottom of the recess; and
a second member having a location figured to change with respect to the first member, wherein
the second member holds the second plate using a vacuum suction in a position; and
the first member is provided with an inlet to introduce gas into a gap between the first plate and the second plate.

US Pat. No. 10,170,441

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
an alignment mark adjacent to a surface of the substrate;
a plurality of pillars protruding from the substrate; and
a seal wall protruding from the surface of the substrate and surrounding the alignment mark, wherein the seal wall is between the plurality of pillars and the alignment mark, and the plurality of pillars are configured into at least two different groups wherein a group has an average height different from an average height of an another group.

US Pat. No. 10,170,440

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THEREOF

EPISTAR CORPORATION, Hsi...

1. A semiconductor device, comprising,a semiconductor die comprising a stacking structure, a first bonding pad with a flat top side in a cross-sectional view, positioned away from the stacking structure, and a second bonding pad, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 microns;
a carrier comprising a connecting surface;
a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and
a conductive connecting layer comprising
a first conductive part formed between the first bonding pad and the third bonding pad, and comprising a first conductive material having a first shape with a width;
a second conductive part formed between the second bonding pad and the fourth bonding pad, and comprising the first conductive material; and
a blocking part covering the first conductive part and comprising a second conductive material having a second shape with a diameter less than the width in the cross-sectional view,
wherein the first shape has a height greater than the diameter, and
wherein the first conductive part fully covers the top flat side in the cross-sectional view.

US Pat. No. 10,170,435

GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME

MEDIATEK SINGAPORE PTE. L...

1. A method for forming a seal ring structure, comprising:providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type;
forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions and extending along a second direction perpendicular to the first direction;
performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of bridge portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction;
removing the patterned photoresist layers;
forming an isolation region between and adjacent to the patterned first doping regions; and
forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder.

US Pat. No. 10,170,434

WARPAGE CONTROL IN PACKAGE-ON-PACKAGE STRUCTURES

Taiwan Semiconductor Manu...

1. A package comprising:a bottom package comprising:
a package component; and
a device die over and bonded to the package component;
an adhesive layer over a top surface of the device die, wherein the adhesive layer comprises a slanted sidewall, a planar top surface, and a curved corner joining the slanted sidewall to the planar top surface;
a rigid plate over and contacting the planar top surface of the adhesive layer;
a molding compound, wherein at least a lower portion of the device die is in the molding compound; and
a top package bonded to the bottom package through solder regions penetrating through the molding compound.

US Pat. No. 10,170,433

INSULATED CIRCUIT BOARD, POWER MODULE AND POWER UNIT

Mitsubishi Electric Corpo...

1. An insulated circuit board comprising:an insulated substrate;
a first electrode formed on one main surface of the insulated substrate and having a polygonal shape in plan view; and
a second electrode formed on the other main surface opposite to the one main surface of the insulated substrate and having a polygonal shape in plan view,
a thin portion being formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, so that the thin portion occupies only a portion of an entire length of the outer edges, the thin portion having a thickness smaller than a thickness of a region of the at least one of the first and second electrodes other than the thin portion,
the thin portion in the at least one of the first and second electrodes having a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.

US Pat. No. 10,170,431

ELECTRONIC CIRCUIT PACKAGE

TDK CORPORATION, Tokyo (...

1. An electronic circuit package comprising:a substrate having a main surface, the main surface having a first region and a second region located on a same plane as the first region;
a first electronic component mounted on the first region;
a second electronic component mounted on the second region;
a mold resin that covers the main surface of the substrate so as to embed the first and second electronic components therein;
a magnetic film formed on the mold resin; and
a metal film formed on the mold resin, wherein the metal film covers the first electronic component with an intervention of the magnetic film while the metal film covers the second electronic component without an intervention of the magnetic film.

US Pat. No. 10,170,430

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method of fabricating an integrated fan-out package, the method comprising:attaching an integrated circuit component onto a carrier through a die attach film,
forming an insulating encapsulation on the carrier to laterally encapsulate the integrated circuit component and the die attach film, wherein an uplifted segment of the die attach film is lifted during forming the insulating encapsulation, and the uplifted segment raises toward sidewalls of the integrated circuit component; and
forming a redistribution circuit structure on the integrated circuit component and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit component.

US Pat. No. 10,170,429

METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a package structure, comprising:forming a first bump over a substrate;
placing an integrated circuit die comprising a second bump over the substrate, wherein the second bump is placed on the first bump;
reflowing the first bump and the second bump to form a solder joint and bond the integrated circuit die and the substrate together through the solder joint, wherein a first intermetallic compound is formed between the solder joint and the first bump, and a second intermetallic compound is formed between the solder joint and the second bump;
annealing the solder joint, the first bump and the second bump to react the solder joint with the first bump and the second bump until the first intermetallic compound and the second intermetallic compound become connected to each other; and
migrating a remaining portion of the solder joint to the first bump or the second bump during a high-temperature storage test or a temperature cycling test.

US Pat. No. 10,170,428

CAVITY GENERATION FOR EMBEDDED INTERCONNECT BRIDGES UTILIZING TEMPORARY STRUCTURES

Intel Corporation, Santa...

1. A method comprising:fabricating a package substrate;
placing at least one temporary structure in a first location on the package substrate;
subsequent to placing the at least one temporary structure in the first location on the package substrate, applying a first dielectric material to the package substrate, to surround at least a portion of the at least one temporary structure;
subsequent to applying the first dielectric material to the package substrate, removing the at least one temporary structure from the package substrate to generate a cavity in the package substrate, wherein a portion of the first dielectric material remains over the cavity subsequent to removing the temporary structure;
removing the portion of the first dielectric material from over the cavity;
subsequent to removing the portion of the first dielectric material from over the cavity, bonding an interconnect bridge in the cavity, the interconnect bridge including a plurality of interconnections;
applying a second dielectric material to the package substrate; and
installing a plurality of contacts to a surface of the package substrate, the plurality of contacts being coupled with the interconnect bridge.

US Pat. No. 10,170,427

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

7. A semiconductor device comprising:a gate stack over a semiconductor fin;
a source/drain region adjacent to the gate stack; and
a first contact to the source/drain region, wherein the first contact has a curved surface, the curved surface extending above a top surface of the gate stack.

US Pat. No. 10,170,426

MANUFACTURING METHOD OF WIRING STRUCTURE AND WIRING STRUCTURE

FUJITSU LIMITED, Kawasak...

1. A wiring structure, comprising:a first insulating film including a connection hole;
a second insulating film which is on the first insulating film and includes a wiring trench;
a first conductive material which fills an inside of the connection hole; and
a second conductive material which fills an inside of the wiring trench, wherein
the first conductive material is made of a first graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the connection hole,
the second conductive material is made of a second graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the wiring trench, and
the first graphene layer and the second graphene layer are directly connected to each other.

US Pat. No. 10,170,425

MICROSTRUCTURE OF METAL INTERCONNECT LAYER

INTERNATIONAL BUSINESS MA...

1. A method of forming a metal interconnect layer, the method comprising:forming an opening in a dielectric layer;
forming an embedded metal layer fully filled in the opening, wherein the embedded metal layer is in direct contact with a bottom surface of the dielectric layer;
forming an overburden layer over a top surface of the embedded metal layer and the dielectric layer;
disposing a metal passivation layer in direct contact with a surface of the overburden layer, the metal passivation layer comprising a metal selected only from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy including only Co, Ru, Ti, or W thereof, nitrides of only Co, Ru, Ti, Ni, or W, and any combination thereof;
performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade; and
performing a chemical-mechanical planarization (CMP) to remove the metal passivation layer and the overburden layer.

US Pat. No. 10,170,424

COBALT FIRST LAYER ADVANCED METALLIZATION FOR INTERCONNECTS

International Business Ma...

1. A method for fabricating an advanced metal conductor structure comprising:providing a pattern in a dielectric layer, wherein the pattern includes a set of features in the dielectric for a set of metal conductor structures and an adhesion promoting layer in the set of features;
depositing a ruthenium metal layer disposed on the adhesion promoting layer;
using a physical vapor deposition process to deposit a cobalt layer disposed on the ruthenium layer;
performing a thermal anneal which reflows the cobalt layer to fill a first portion of the set of features leaving a second, remaining portion of the set of features unfilled; and
depositing a second metal layer to fill the second, remaining portion of the set of features, wherein the second metal is a metal other than cobalt, wherein a thickness of the reflowed cobalt layer from the ruthenium layer to a bottom of the second metal layer and a thickness of the second metal layer after planarization are substantially equal.

US Pat. No. 10,170,423

METAL CAP INTEGRATION BY LOCAL ALLOYING

International Business Ma...

1. An interconnect structure, comprising:a dielectric layer having a top surface;
a plurality of open-ended trenches extending within the dielectric layer;
interconnects comprising copper within the open-ended trenches, a plurality of interconnects of the interconnect structure having top surfaces that are substantially coplanar with the top surface of the dielectric layer;
a plurality of metal alloy caps for preventing electromigration, each of the metal alloy caps being integral with one of the interconnects and comprising an alloy of copper and at least one of titanium, ruthenium and cobalt, wherein the metal alloy caps exhibit a stoichiometry of at least one part titanium, ruthenium or cobalt per one part of copper.

US Pat. No. 10,170,422

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Taiwan Semiconductor Manu...

18. A method of forming an integrated chip, comprising:forming a plurality of gate structures extending in a second direction over an active area within a substrate;
forming a first middle-end-of-the-line (MEOL) structure and a second MEOL structure extending in the second direction over the active area and interleaved between the plurality of gate structures along a first direction perpendicular to the second direction, wherein the second MEOL structure extends a non-zero distance past the first MEOL structure along the second direction;
forming a first power rail extending in the first direction, wherein the first power rail is coupled to the second MEOL structure by a first conductive path comprising a conductive contact directly below the first power rail;
forming a first metal wire extending in the first direction over the first MEOL structure;
forming a metal strap coupled to the first metal wire; and
forming a second power rail extending in the first direction over the first power rail, wherein the second power rail is coupled to the first MEOL structure along a second conductive path comprising the first metal wire and the metal strap.

US Pat. No. 10,170,421

LOGIC SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A logic semiconductor device, comprising:a plurality of active patterns extending in a first direction and being spaced apart from each other in a second direction, the first and second directions being perpendicular to each other;
an isolation layer defining the active patterns;
a plurality of gate patterns extending in the second direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the first direction and at least one of the gate patterns being on the plurality of active patterns;
active contacts connected to upper portions of the active patterns adjacent to the gate patterns;
a plurality of sub-wirings integrally connected to the active contacts, the sub-wirings extending in the first direction; and
wirings extending in the second direction over the sub-wirings.

US Pat. No. 10,170,420

PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a semiconductor substrate;
a first interconnect layer over the semiconductor substrate, the first interconnect layer comprising: a first dielectric material having a conductive body embedded therein, the conductive body comprising a first sidewall, a second sidewall, and a bottom surface, and a spacer element having a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body; and
a second interconnect layer overlying the first interconnect layer comprising a second dielectric material having at least one via therein, the at least one via filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer;
wherein a height of the spacer element is greater than a height of the conductive body.

US Pat. No. 10,170,419

BICONVEX LOW RESISTANCE METAL WIRE

International Business Ma...

1. A semiconductor structure comprising:a dielectric material layer having at least one opening located in said dielectric material layer, said at least one opening physically exposing a pair of curved sidewalls of said dielectric material layer and having a biconvex shape comprising a lower portion having a first width, a middle portion having a second width, and an upper portion having a third width, wherein the second width is greater than the first and third widths;
a diffusion barrier liner located in said at least one opening and contacting at least said pair of curved sidewalls of said dielectric material layer;
a reflow enhancement liner located on said diffusion barrier liner; and
a metallic region located on said reflow enhancement liner, said metallic region having a pair of curved outermost sidewalls, said biconvex shape and comprising a lower metallic region portion having a first metallic region width, a middle metallic region portion having a second metallic region width, and an upper metallic region portion having a third metallic region width, wherein the second metallic region width is greater than the first and third metallic region widths.

US Pat. No. 10,170,418

BACKSIDE DEVICE CONTACT

International Business Ma...

1. A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the method comprising:forming a trench in the device layer;
forming a sacrificial plug in the trench;
removing the handle wafer to reveal the buried insulator layer;
partially removing the buried insulator layer to expose the sacrificial plug at a bottom of the trench;
removing the sacrificial plug;
performing backside processing of the buried insulator layer;
filling the trench with a conductor to form a contact plug;
coupling a final substrate to the buried insulator layer such that the contact plug contacts metallization of the final substrate.

US Pat. No. 10,170,417

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a dielectric layer on the substrate and comprising a recess feature therein;
a metal layer in the recess feature, wherein the metal layer has an oxygen content less than about 0.1 atomic percent; and
a tungsten layer in the recess feature and in contact with the metal layer.

US Pat. No. 10,170,416

SELECTIVE BLOCKING BOUNDARY PLACEMENT FOR CIRCUIT LOCATIONS REQUIRING ELECTROMIGRATION SHORT-LENGTH

International Business Ma...

1. A semiconductor structure comprising:a first insulating layer deposited over a semiconductor substrate;
trenches formed by etching the first insulating layer, the trenches configured to receive copper (Cu) wiring, wherein the Cu wiring is selectively recessed in one or more of the trenches resulting in recessed Cu wiring regions and non-recessed Cu wiring regions, the recessed Cu wiring regions corresponding to circuit locations calling for electromigration (EM) short-length;
self-aligned conducting caps formed over the one or more trenches where the Cu wiring has been selectively recessed; and
a first via directly contacting a top surface of the Cu wiring in the non-recessed Cu wiring regions.

US Pat. No. 10,170,414

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

10. A semiconductor device, comprising:a first group of dummy gate structures disposed over a substrate;
a first interlayer dielectric layer in which the first group of dummy gate structures are embedded;
a second interlayer dielectric layer disposed over the first interlayer dielectric layer;
a third interlayer dielectric layer disposed over the second interlayer dielectric layer; and
a resistor wire formed by a conductive material and embedded in the third interlayer dielectric layer, wherein:
the resistor wire is separated from the first group of dummy gate structures by the second and third interlayer dielectric layers,
the first group of dummy gate structure includes two or more first dummy gate structures and
at least one first dummy gate structure of the first group of dummy gate structures fully overlaps the resistor wire.

US Pat. No. 10,170,413

SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a semiconductor substrate;
a fin field effect transistor (FinFet) comprising:
a fin over the semiconductor substrate;
a gate structure over the fin; and
a source/drain structure adjoining the fin and adjacent to the gate structure;
a shallow trench isolation structure surrounding the fin;
a buried metal line under a top surface of the shallow trench isolation structure; and
a metal segment over the source/drain structure, wherein a portion of the metal segment extends into the shallow trench isolation structure to be electrically coupled to the buried metal line.

US Pat. No. 10,170,412

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. An apparatus, comprising:conductive elements of a conductive layer on a bottom side of a package;
wire bond wires coupled to and extending from first upper surface portions of the conductive elements;
a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;
a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; and
a dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.

US Pat. No. 10,170,411

AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT

International Business Ma...

1. A method for via alignment, comprising:depositing a pinch off layer to close off openings to first airgaps between interconnect structures;
forming a protection layer in divots formed in the pinch off layer; and
etching the pinch off layer using the protection layer as an etch stop to form and align a via and expose the interconnect structures through the via.

US Pat. No. 10,170,410

SEMICONDUCTOR PACKAGE WITH CORE SUBSTRATE HAVING A THROUGH HOLE

Samsung Electro-Mechanics...

1. A semiconductor package, comprising:a frame comprising a through hole;
an electronic component disposed in the through hole;
a metal layer disposed on either one or both of an inner surface of the through hole and an upper surface of the electronic component;
a redistribution portion disposed below the frame and the electronic component; and
a conductive layer electrically connected to the metal layer,
wherein the redistribution portion comprises an insulating layer formed of an insulating material, and a wiring layer provided in the insulating layer, and
wherein the insulating layer extends to a space formed by a portion of the metal layer formed on an inner surface of the frame and an outer surface of the electronic component.

US Pat. No. 10,170,409

PACKAGE ON PACKAGE ARCHITECTURE AND METHOD FOR MAKING

INTEL CORPORATION, Santa...

1. A method of fabricating a package assembly, the method comprising:forming a package-on-package (POP) land by partially embedding a prefabricated via bar in a region on a first side of a mold compound and extended to a location between the first side of the mold compound and a second side of the mold compound disposed opposite to the first side, wherein the prefabricated via bar extends across a plurality of package assemblies including a first package assembly and a second package assembly separated from the first package assembly, and wherein a die is at least partially embedded in the mold compound and has an active side proximal to the first side of the mold compound;
removing material of the mold compound to expose a portion of the POP land in a region on the second side of the mold compound after the forming of the POP land; and
depositing at least one of a conductive material, a passivation layer, or a noble metal on the exposed portion of the POP land.

US Pat. No. 10,170,408

MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

Taiwan Semiconductor Manu...

1. A memory circuit, comprising:at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first conductive layer arranged at a first level, the first conductive layer comprising a first landing pad and a second landing pad, the first landing pad forming a landing site formed in the first conductive layer and on which a via lands, the via connecting the first conductive layer to a second conductive layer;
the second conductive layer coupled to the first conductive layer and arranged at a second level different from and over the first level, the second conductive layer being routed to define the first voltage line and the second voltage line, the first voltage line and the second voltage line extending in a first direction, wherein the first voltage line and the second voltage line are located within the second conductive layer; and
a third conductive layer coupled to the second conductive layer and arranged at a third level different from the first level and the second level, the third level over the second level, the third conductive layer being routed to define the word line, the word line extending in a second direction perpendicular to the first direction, wherein the bit line is located within the first conductive layer adjacent to the first landing pad, wherein the bit line in the first conductive layer extends past a periphery of the at least one memory cell in the first direction, wherein the bit line bar is located within the first conductive layer adjacent to the second landing pad, and wherein the bit line bar in the first conductive layer extends past the periphery of the at least one memory cell in the first direction.

US Pat. No. 10,170,406

TRACE/VIA HYBRID STRUCTURE AND METHOD OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method of forming an interconnect comprising:providing a sacrificial trace structure using an additive forming method;
forming a seed metal layer on the sacrificial trace structure;
removing the sacrificial trace structure, wherein the seed metal layer remains;
forming an interconnect metal layer on the continuous seed layer;
forming a dielectric material on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of said interconnect metal layer are exposed to provide said interconnect extending through said dielectric material;
forming a solder bump on said ends of the interconnect metal layer; and
bonding said solder bump to a substrate including at least one microprocessor.

US Pat. No. 10,170,405

WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:an insulating layer; and
a wiring layer buried in the insulating layer at a first surface of the insulating layer,
the wiring layer including a first portion and a second portion, the first portion being narrower and thinner than the second portion, the first portion including a first surface exposed at the first surface of the insulating layer, the second portion including a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer, the opening being open at a second surface of the insulating layer opposite to the first surface thereof,
wherein the wiring layer includes a first surface exposed at the first surface of the insulating layer, a second surface opposite to the first surface of the wiring layer, and a side surface, and
wherein a surface roughness of the second surface of the wiring layer and the side surface of the wiring layer is greater than a surface roughness of the first surface of the wiring layer.

US Pat. No. 10,170,404

MONOLITHIC 3D INTEGRATION INTER-TIER VIAS INSERTION SCHEME AND ASSOCIATED LAYOUT STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure; and
forming a dummy gate over the second substrate, wherein the dummy gate is formed to be electrically coupled to the via.

US Pat. No. 10,170,402

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface;
a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate; and
a plurality of wires electrically connected with the plurality of terminals, respectively,
wherein, in plan view, the first semiconductor chip is mounted over the upper surface of the wiring substrate such that the plurality of terminals of the wiring substrate is exposed from the first semiconductor chip,
wherein, in plan view, the plurality of terminals is arranged along a first side of the first main surface of the first semiconductor chip,
wherein the plurality of terminals has a plurality of first terminals, and a second terminal,
wherein, in plan view, the second terminal has a first part located on a virtual line comprised of an arrangement of the plurality of first terminals, and a second part not located on the virtual line,
wherein each of the plurality of wires has a ball part, and a stitch part,
wherein, in plan view, a width of the ball part is larger than a width of the stitch part,
wherein the plurality of wires has a plurality of first wires, and a second wire,
wherein, the plurality of first wires are connected to the plurality of first terminals, respectively, via the stitch part,
wherein the second wire is connected to the second part of the second terminal via the ball part, and
wherein a distance from the first side of the first main surface of the first semiconductor chip to the second part of the second terminal is greater than a distance from the first side of the first main surface of the first semiconductor chip to each of the first terminals in a direction perpendicular to the first side of the first main surface of the first semiconductor chip.

US Pat. No. 10,170,400

MULTI-FINGER TRANSISTOR AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A multi-finger transistor comprising:a plurality of gate fingers arranged in an active region on a semiconductor substrate;
a plurality of source fingers and a plurality of drain fingers which are alternately arranged in said active region in such a way as to sandwich said gate fingers therebetween, respectively;
a gate pad disposed outside said active region, said gate fingers being connected to said gate pad via a gate bus;
a source pad disposed in a region which is located outside said active region and on a side where said gate pad is disposed with respect to said active region, said source fingers being connected to said source pad;
a drain pad disposed in a region which is located outside said active region and which is located at an opposite side of said gate pad across said active region, said drain fingers being connected to said drain pad;
and a source via grounding said source pad, wherein
said multi-finger transistor further comprises a circuit suppressing a variation in voltage current distribution, said circuit connecting said gate fingers to each other, or connecting said source fingers to each other with a resistive member having a resistance higher than said source fingers, in a region which is located outside said active region and on a side where said drain pad is disposed, and
said multi-finger transistor is configured so as to be linearly symmetric with respect to a direction of propagation of a signal from said gate pad at a position of said gate pad.

US Pat. No. 10,170,399

CAPPED THROUGH-SILICON-VIAS FOR 3D INTEGRATED CIRCUITS

Board of Regents, The Uni...

1. A three dimensional (3D) integrated circuit comprising a plurality of electrically connected chips, at least one chip comprisinga wafer;
a back-end-of-line (BEOL) layer deposited on the wafer;
a chip through-silicon-via (TSV) in the wafer, the chip TSV containing a conductive material;
a chip cap layer disposed over the chip TSV and between the chip TSV and the BEOL layer, wherein the chip cap layer is configured to reduce via extrusion of conductive material located in the chip TSV during operation of the chip; and
an interposer on which the plurality of electrically connected chips are located, wherein the interposer comprises a plurality of interposer TSVs and a interposer cap layer configured to reduce via extrusion of conductive material located in the interposer TSV during fabrication or operation of the circuit, or both.

US Pat. No. 10,170,398

THREE-DIMENSIONAL INTEGRATED CIRCUIT

INDUSTRY-ACADEMIC COOPERA...

1. A three-dimensional integrated circuit divided into a plurality of groups, the three-dimensional integrated circuit comprising:a plurality of through-silicon vias (TSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups; and
two or more redundant through-silicon vias (RTSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups,
wherein an RTSV of two or more RTSVs in one group of the plurality of groups is configured to receive a signal of a first failed TSV of a plurality of TSVs in the one group and process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group when a number of failed TSVs among the plurality of TSVs in the one group does not exceed a repairable number, and wherein each of the failed TSVs does not normally perform a function as an electrode, and the repairable number is a number of RTSVs capable of replacing functions of the failed TSVs in the one group, and
wherein the RTSV of the two or more RTSVs in the one group is configured to receive the signal of the first failed TSV of the plurality of TSVs in the one group, process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group, receive a signal of a second failed TSV of the plurality of TSVs in the one group and output the signal of the second failed TSV to an RTSV of two or more RTSVs in another group of the plurality of groups such that a function of the second failed TSV is performed by the RTSV in the another group when the number of failed TSVs among the plurality of TSVs in the one group exceeds the repairable number, the another group being adjacent to the one group.

US Pat. No. 10,170,396

THROUGH VIA STRUCTURE EXTENDING TO METALLIZATION LAYER

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming an intermetal dielectric layer over a substrate;
forming a metal via and a metal line in the intermetal dielectric layer using a dual-damascene process, the metal line formed in a metal one layer (M1);
after forming the intermetal dielectric layer, removing portions of the intermetal dielectric layer to form an opening through the intermetal dielectric layer;
after removing portions of the intermetal dielectric layer, filling the opening with a conductive material to form a through via (TV), the through via extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the metal line; and
after forming the through via, forming one or more dielectric layers over the through via.

US Pat. No. 10,170,395

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor module housing a first semiconductor element and a third semiconductor element;
a second semiconductor module housing a second semiconductor element and a fourth semiconductor element, the second semiconductor element having a switching voltage threshold that is lower than a switching voltage threshold of the first semiconductor element of the first semiconductor module, and the fourth semiconductor element having a switching voltage threshold that is higher than a switching voltage threshold of the third semiconductor element of the first semiconductor module; and
a first busbar that connects an external terminal of the first semiconductor element of the first semiconductor module to an external terminal of the second semiconductor element of the second semiconductor module in parallel to a first common terminal; and
a second busbar that connects an external terminal of the third semiconductor element of the first semiconductor module to an external terminal of the fourth semiconductor element of the second semiconductor module in parallel to a second common terminal, wherein
an inductance of a current path from the first common terminal to the first semiconductor element in the first semiconductor module is lower than an inductance of a current path from the first common terminal to the second semiconductor element in the second semiconductor module, and
an inductance of a current path from the second common terminal to the third semiconductor element of the first semiconductor module is higher than an inductance of a current path from the second common terminal to the fourth semiconductor element of the second semiconductor module.

US Pat. No. 10,170,394

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

10. A semiconductor device comprising:a laminated substrate having a circuit board;
a semiconductor chip having electrodes on a front surface, and a rear surface fixed to the circuit board;
a terminal having a wiring portion with a plate shape, and a leading end portion with a hollow shape extending from the wiring portion, the wiring portion and the leading end portion being integrally formed of one conductive member, the leading end portion having a front open end forming an end of the terminal and a rear open end where a part of the leading end portion continues to the wiring portion; and
a joining material which electrically and mechanically connects the electrode and the front open end of the leading end portion,
wherein the front open end of the leading end portion is located to face the electrode, and is closed by the joining material entered into the front open end, and
a space is arranged between the front open end of the terminal and the electrode so that the joining material enters the front open end of the leading end portion and the space to connect the leading end portion to the electrode.

US Pat. No. 10,170,392

WAFER LEVEL INTEGRATION FOR EMBEDDED COOLING

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a silicon wafer, comprising:
channel structures formed on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas; and
integrated circuits formed on a second surface of the silicon first wafer that opposes the first surface; and
a manifold wafer bonded to the first surface of the silicon wafer, wherein portions of the manifold wafer enclose the radial channels and wherein inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas.

US Pat. No. 10,170,389

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method of forming a semiconductor die assembly, the method comprising:electrically coupling a plurality of first semiconductor dies together in a single stack;
electrically coupling the single stack of first semiconductor dies to a second semiconductor die such that the stack of first semiconductor dies is centered with respect to the second semiconductor die along at least one axis, the second semiconductor die having a peripheral portion that extends laterally outward beyond at least one side of the stack of first semiconductor dies, and wherein the stack of first semiconductor dies forms a first thermal path that transfers heat away from the second semiconductor die;
depositing an underfill material between the first semiconductor dies, wherein the underfill material extends from between the first semiconductor dies onto the peripheral portion of the second semiconductor die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the second semiconductor die adjacent to at most a first side and a second side of the single stack of first semiconductor dies and spaced laterally apart from the at most first and second sides of the single stack of first semiconductor dies, wherein the thermal transfer feature is a blank silicon member, and wherein the thermal transfer feature forms a second thermal path away from the second semiconductor die that is separate from the first thermal path; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation generally corresponding to that of a topmost one of the first semiconductor dies in the stack of first semiconductor dies, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation generally corresponding to that of the topmost one of the first semiconductor dies.

US Pat. No. 10,170,388

SURFACE PASSIVATION HAVING REDUCED INTERFACE DEFECT DENSITY

INTERNATIONAL BUSINESS MA...

1. A method of passivating a surface of a semiconductor, the method comprising:forming a semiconductor layer on a substrate;
contacting a surface of the semiconductor layer with a sulfur source comprising thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer;
forming a dielectric layer on the sulfur passivation layer; and
annealing the dielectric layer at a temperature of about 390 degrees Celsius for about 30 minutes;
wherein a minimum interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.

US Pat. No. 10,170,387

TEMPORARY BONDING SCHEME

Taiwan Semiconductor Manu...

15. A structure comprising:an integrated circuit device;
a molding compound encapsulating the integrated circuit device, the molding compound having a major surface; and
a thermoplastic material within the molding compound having a concentration of from 1 ppm to 100 ppm at the major surface.

US Pat. No. 10,170,386

ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component package comprising:a frame having a cavity;
an electronic component disposed in the cavity of the frame;
a first metal layer disposed on an inner wall of the cavity of the frame;
a second metal layer disposed on a lower surface of the frame;
a third metal layer disposed on an upper surface of the frame;
an encapsulant encapsulating at least a portion of the electronic component; and
a redistribution layer disposed below the frame and the electronic component,
wherein a lower surface of the encapsulant is substantially coplanar with lower surfaces of the electronic component, the first metal layer and second metal layer.

US Pat. No. 10,170,385

SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED VIAS WITHIN INTERCONNECT STRUCTURE FOR FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor die;
an encapsulant deposited over and around the semiconductor die;
a first insulating layer formed over the semiconductor die and encapsulant including a first opening formed through the first insulating layer;
a first conductive layer formed over a top surface of the first insulating layer and extending through the first opening to the encapsulant;
a second insulating layer formed over the semiconductor die and encapsulant including a second opening formed through the second insulating layer, wherein a size of the second opening at the first conductive layer is approximately equal to a size of the first opening, and the second opening is aligned with the first opening;
a second conductive layer formed over a top surface of the second insulating layer and extending through the second opening to the first conductive layer;
a third opening formed through the encapsulant, first conductive layer, and second conductive layer, wherein a size of the third opening at the first conductive layer is smaller than the size of the first opening and the size of the second opening; and
a solder material deposited in the third opening to form a conductive via, wherein the solder material in the third opening is exposed from a top surface of the encapsulant opposite the first conductive layer.

US Pat. No. 10,170,384

METHODS AND APPARATUS PROVIDING A GRADED PACKAGE FOR A SEMICONDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A method comprising:generating a graded package for encapsulating a die by spatially varying package material of the graded package based on a package grading design, wherein the generating of the graded package includes:
moving a printhead to a first location of the graded package;
printing at least one of a first material or a first combination of materials at the first location;
moving the printhead to a second location of the graded package; and
printing at least one of a second material or a second combination of materials at the second location, the second material being different from the first material and the second combination being different than the first combination.

US Pat. No. 10,170,383

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an insulating board;
a circuit pattern disposed on the insulating board;
a semiconductor chip connected to the circuit pattern;
a case disposed on and entirely to one side of the insulating board to surround the circuit pattern and the semiconductor chip; and
a cured resin disposed in the case to seal the circuit pattern and the semiconductor chip, wherein
the case includes a surface portion directly opposing and adjacent to a surface portion of the insulating board, and
no bonding material other than the resin is disposed between the opposing and adjacent surface portions.

US Pat. No. 10,170,382

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and
a resin layer disposed between the encapsulant and the second interconnection member and contacting at least portions of side surfaces of the protrusion bump,
wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad,
the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer and contacting the second interconnection member, and
the resin layer contacts at least portions of side surfaces of the third redistribution layer.

US Pat. No. 10,170,381

SEMICONDUCTOR WAFER AND METHOD OF BACKSIDE PROBE TESTING THROUGH OPENING IN FILM FRAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer including a non-active surface;
forming a conductive layer over the non-active surface;
providing a wafer holder;
forming a first opening through the wafer holder;
mounting the semiconductor wafer to the wafer holder with the conductive layer on the non-active surface oriented toward the wafer holder; and
probe testing the semiconductor wafer by contacting the conductive layer through the first opening in the wafer holder.

US Pat. No. 10,170,380

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display region and a peripheral circuit region located outside the display region,
wherein a first gate line, a first data line and a pixel region adjacent to the first gate line and the first data line are arranged in the display region; the pixel region includes a first pixel electrode and a first thin film transistor, and the first thin film transistor includes a first gate electrode connected to the first gate line, a first source electrode connected to the first data line and a first drain electrode connected to the first pixel electrode;
wherein the array substrate further comprises a test unit arranged in the peripheral circuit region, the test unit comprising:
a second gate line and a second data line intersecting with each other, wherein when the array substrate is in a working state, a first signal inputted to the second gate line is identical with a second signal inputted to the first gate line, and a third signal inputted to the second data line is identical with a fourth signal inputted to the first data line;
a second testing pixel electrode arranged close to the intersection of the second gate line and the second data line;
a second testing thin film transistor arranged at the intersection of the second gate line and the second data line, wherein the second testing thin film transistor includes a second gate electrode connected to the second gate line, a second source electrode connected to the second data line and a second drain electrode connected to the second testing pixel electrode, wherein a first test port exposed outside of the display region is provided for the second gate electrode, a second test port exposed outside of the display region is provided for the second source electrode, and a third test port exposed outside of the display region is provided for the second drain electrode,
wherein, the display region is further provided with a first common electrode line and a first common electrode connected to the first common electrode line;
the test unit further includes: a second common electrode line and a second testing common electrode connected to the second common electrode line, wherein the second testing common electrode and the first common electrode are arranged on a same layer and are identical in material and shape; and the second testing common electrode is connected to a third test lead through a first transparent conductive connecting line which is located on the same layer with the second testing common electrode, wherein one end of the first transparent conductive connecting line is connected to the second testing common electrode and the other end of the first transparent conductive connecting line is connected to the third test lead, and the first transparent conductive connecting line and the second testing common electrode are identical in material,
wherein, the first transparent conductive connecting line is intersected with the second common electrode line in a plan view of the array substrate.

US Pat. No. 10,170,379

WAFER PROCESSING SYSTEM

DISCO CORPORATION, Tokyo...

1. A wafer processing system for processing wafers one at a time, the wafer processing system comprising:a plurality of trays each configured to accommodate a wafer;
a conveyor configured to transfer the wafers accommodated in the trays;
first and second tray holding apparatuses arranged to be spaced from each other along the conveyor, the first and second tray holding apparatuses unloading the trays from the conveyor and loading the unloaded trays onto the conveyor;
first and second apparatuses provided for the first and second tray holding apparatuses, respectively, the first and second apparatuses including processing means configured to process the wafers transferred by the conveyor, and loading/unloading means configured to unload a wafer from or load a wafer onto one of the trays that is held by the first or second tray holding apparatus; and
a pair of rail members, with one of said rail members formed on each side of the conveyor, wherein each of said rail members includes first and second accommodation grooves therein, and further wherein said pair of first accommodation grooves are configured and arranged to accommodate downward movement of said first tray holding apparatus and said pair of second accommodation grooves are configured and arranged to accommodate downward movement of said second tray holding apparatus.