US Pat. No. 10,142,087

TRANSMISSION/RECEPTION MODULE

MURATA MANUFACTURING CO.,...

1. A transmission/reception module comprising:a power amplifier that outputs a first transmission signal and a second transmission signal to an input/output terminal;
a low-noise amplifier that amplifies a first reception signal and a second reception signal input from the input/output terminal;
a first duplexer that has a first common node, a first transmission node, and a first reception node, the first transmission signal being provided from the first transmission node to the input/output terminal and the first reception signal being provided from the input/output terminal to the first reception node, wherein the duplexer is configured to isolate the first transmission signal and the first reception signal from each other;
a second duplexer that has a second common node, a second transmission node, and a second reception node, the second transmission signal being provided from the second transmission node to the input/output terminal and the second reception signal being provided from the input/output terminal to the second reception node, wherein the duplexer is configured to isolate the second transmission signal and the second reception signal from each other;
a first phase-shift circuit that has a first input node connected to the first reception node of the first duplexer and a first output node connected to an input node of the low-noise amplifier, wherein the first phase-shift circuit is configured to adjust an impedance at the first output node with respect to the first transmission signal, the first reception signal, and the second transmission signal such that gains of the first transmission signal and the second transmission signal are smaller than a gain of the first reception signal; and
a second phase-shift circuit that has a second input node connected to the second reception node of the second duplexer and a second output node connected to the input node of the low-noise amplifier, wherein the second phase-shift circuit is configured to adjust an impedance at the second output node with respect to the first transmission signal, the second transmission signal, and the second reception signal such that gains of the first transmission signal and the second transmission signal are smaller than a gain of the second reception signal.

US Pat. No. 10,142,085

ASSIGNING AN ACCESS POINT BASED UPON A POWER STATE OF A MOBILE DEVICE

10. A method comprising:detecting, by a processor deployed in a wireless network, power states of a plurality of mobile endpoint devices that are in communication with a first access point of the wireless network, the power states including a first power state of a first mobile endpoint device of the plurality of mobile endpoint devices, wherein the first power state is one of: a battery operated state or an alternating current powered state;
determining, by the processor, a loading condition of a region of the wireless network that includes the first access point; and
assigning, by the processor, the first mobile endpoint device to a second access point that is outside of the region in response to the detecting the first mobile endpoint device is in the first power state and the determining of the loading condition of the region of the wireless network.

US Pat. No. 10,142,084

FULL-DUPLEX SELF-INTERFERENCE CANCELLATION

Intel Corporation, Santa...

1. A device comprising:at least one memory storing computer-executable instructions; and
at least one processor configured to access the at least one memory, wherein the at least one processor is configured to execute the computer-executable instructions to:
cause to send at least one first symbol sequence at least twice on a first transmit chain and at least one second symbol sequence twice on a second transmit chain;
determine at least one third symbol sequence at least twice on a first receive chain and at least one fourth symbol sequence at least twice on a second receive chain;
determine a first impulse response of a first power amplifier on the first transmit chain and a second impulse response of a second power amplifier on the second transmit chain;
cause a first circulator to detect at least one first signal corresponding to the at least one third symbol sequence, and a first amplified signal from the first power amplifier;
cause a second circulator to detect at least one second signal corresponding to the at least one fourth symbol sequence, and a second amplified signal from the second power amplifier;
determine a first aggregate impulse response associated with one or more first devices on the first transmit chain and the first receive chain;
determine a second aggregate impulse response associated with one or more second devices on the second transmit chain and the second receive chain;
determine a third impulse response based at least in part on the first and second impulse response, and the first and second aggregate impulse response; and
determine an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.

US Pat. No. 10,142,083

METHOD AND APPARATUS FOR TRANSMITTING CONTROL CHANNEL DEPENDING ON UE CAPABILITY IN INTRA-CELL CARRIER AGGREGATION SYSTEM

Samsung Electronics Co., ...

1. A method of transmitting and/or receiving a control channel by a base station in a wireless communication system supporting a carrier aggregation (CA), the method comprising:receiving, from a terminal, capability information of the terminal, the capability information comprising first information on whether a transmission of a physical uplink control channel (PUCCH) on at least one secondary cell (SCell) in addition to a primary cell (PCell) is supported by the terminal;
transmitting, to the terminal, configuration information associated with the PUCCH based on the capability information, the configuration information indicating whether an SCell is configured to carry PUCCH or not;
transmitting, to the terminal, scheduling information and downlink data corresponding to the scheduling information; and
receiving, from the terminal, the PUCCH for the downlink data on the PCell or on the PCell and the SCell, based on the configuration information,
wherein, if the configuration information indicates that the SCell is configured to carry the PUCCH, the PUCCH for the downlink data is received on the PCell and the SCell using HARQ timing for the PCell and the SCell, and
wherein, if the configuration information indicates that the SCell is not configured to carry the PUCCH, the PUCCH for the downlink data is received on the PCell using HARQ timing for the PCell.

US Pat. No. 10,142,081

FILTER-BASED GUARDBAND DETERMINATION AND SUBCARRIER SELECTION

T-Mobile USA, Inc., Bell...

9. One or more non-transitory computer-readable media having stored thereon a plurality of computer-executable instructions which, when executed by a base station of a telecommunication network, cause the base station to perform operations comprising:receiving, from a mobile device, an indication of a roll-off of a filter of the mobile device or a type of the filter;
determining a guardband for a frequency channel based at least in part on the roll-off or the type of the filter, the determined guardband being specific to the mobile device;
selecting a subcarrier for transmissions from the mobile device to the base station based at least in part on the determined guardband; and
instructing the mobile device to utilize the selected subcarrier.

US Pat. No. 10,142,080

UPLINK CONTROL INFORMATION TRANSMITTING/RECEIVING METHOD AND DEVICE IN A WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting an Acknowledgement/Negative Acknowledgement (ACK/NACK) information at a User Equipment (UE) configured to use Physical Uplink Control Channel (PUCCH) format 3 in a wireless communication system, the method comprising:determining that transmission of a scheduling request is configured in one uplink subframe in which a transmission of ACK/NACK information for downlink transmission in a downlink subframe set including one or more downlink subframes is to be transmitted; and
transmitting the ACK/NACK information and the scheduling request using PUCCH format 1b in the one uplink subframe, when transmission of the ACK/NACK information coincides with the one uplink subframe for the transmission of the scheduling request and at least one of specific conditions is met,
wherein the specific conditions comprise:
a first condition that the ACK/NACK information corresponds to one Semi-Persistent Scheduling (SPS) release Physical Downlink Control Channel (PDCCH) having a Downlink Assignment Index (DAT) value of 1 in the downlink subframe set, and
a second condition that the ACK/NACK information corresponds to one Physical Downlink Shared Channel (PDSCH) indicated by detection of a corresponding PDCCH having a DAI value of 1 that is received only on a Primary Cell (PCell) in the downlink subframe set.

US Pat. No. 10,142,077

TERMINAL APPARATUS AND COMMUNICATION METHOD

Sun Patent Trust, New Yo...

1. A terminal apparatus comprising:a receiver, which, in operation, receives a first downlink control channel signal in an enhanced Physical Downlink Control Channel (ePDCCH) and receives a second downlink control channel signal in a Physical Downlink Control Channel (PDCCH), wherein the first downlink control channel signal indicates a first downlink data transmission on a secondary cell (SCell) and the second downlink control channel signal indicates a second downlink data transmission on another SCell;
a controller, which is coupled to the receiver and which, in operation, determines a physical uplink control channel (PUCCH) resource value using at least one of a first indicator value received in the ePDCCH and a second indicator value received in the PDCCH, wherein the first indicator value and the second indicator value are identical and denote a common PUCCH resource; and
a transmitter, which is coupled to the controller and which, in operation, transmits a response signal using the common PUCCH resource indicated by the determined PUCCH resource value.

US Pat. No. 10,142,076

METHOD AND APPARATUS FOR SENDING AND RECEIVING CONTROL CHANNEL IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for transmitting downlink control information (DCI) by a base station in a communication system, the method comprising:generating subframe information associated with a control channel;
transmitting, to a terminal, the subframe information using a higher layer signaling;
generating the downlink control information including information on at least one resource block to be used for data transmission or data reception of the terminal; and
transmitting, to the terminal, the downlink control information on the control channel based on the subframe information,
wherein the subframe information is used to indicate, to the terminal, information regarding the control channel being located in a physical downlink shared channel (PDSCH) region.

US Pat. No. 10,142,074

TECHNIQUES AND APPARATUSES FOR COMMON UPLINK BURST

QUALCOMM Incorporated, S...

1. A method of wireless communication, comprising:configuring, by a wireless communication device, a wireless communication structure to include at least a data portion and a common uplink portion, wherein the common uplink portion includes a first symbol and a second symbol, and wherein the first symbol precedes the second symbol;
mapping, by the wireless communication device, at least a portion of one or more reference signals or an uplink payload to at least one of the first symbol or the second symbol, wherein a first portion of the one or more reference signals and a first portion of the uplink payload are mapped to the first symbol, and wherein a second portion of the one or more reference signals and a second portion of the uplink payload are mapped to the second symbol; and
transmitting the one or more reference signals and the uplink payload in the common uplink portion of the wireless communication structure, the transmitting including using cyclic prefix orthogonal frequency-division multiplexing (CP-OFDM) or discrete Fourier transform spread orthogonal frequency-division multiplexing (DFT-s-OFDM), and wherein the first symbol and the second symbol are transmitted using different frequency bands.

US Pat. No. 10,142,073

TERMINAL APPARATUS, RADIO COMMUNICATION SYSTEM AND COMMUNICATION METHOD

PANASONIC CORPORATION, O...

1. A terminal apparatus comprising a computer that executes a program stored in a memory, the computer configured to:detect a presence or absence of an error in a downlink signal transmitted from a base station apparatus;
configure a different preamble depending on whether or not the downlink signal includes an error; and
transmit an uplink signal including the configured preamble,
wherein:
the computer transmits an uplink signal that has been subjected to OFDM (Orthogonal Frequency Division Multiplexing) modulation, using a first subcarrier group having predetermined subcarrier spacing,
the computer maps a preamble to a second subcarrier group composed of some subcarriers of the first subcarrier group, when there is no error in the downlink signal,
the computer maps a preamble to a third subcarrier group composed of some subcarriers of the first subcarrier group and including at least one subcarrier not included in the second subcarrier group, when there is an error in the downlink signal,
the second subcarrier group comprises subcarriers having subcarrier spacing which is N times (N is an integer equal to or greater than 4) the predetermined subcarrier spacing,
the third subcarrier group comprises the second subcarrier group and the at least one subcarrier, and
the third subcarrier group has subcarrier spacing which is M times (M is an integer equal to or greater than 2 but less than N) the predetermined subcarrier spacing.

US Pat. No. 10,142,070

CELL-SPECIFIC REFERENCE SIGNALS

Sprint Spectrum L.P., Ov...

1. A method for transmitting downlink reference signals, the method comprising:transmitting a first plurality of subframes comprising a first reference signal associated with a first antenna port, the first reference signal having a first format within the first plurality of subframes;
transmitting a second plurality of subframes comprising a second reference signal associated with a second antenna port, the second reference signal having a second format within the second plurality of subframes;
detecting that a coherence time of the second antenna port is lower than a coherence time of the first antenna port; and
in response to the detecting, switching a format of each of the first and second reference signals, such that a third plurality of subframes is transmitted with the first reference signal in the second format, and a fourth plurality of subframes is transmitted with the second reference signal in the first format.

US Pat. No. 10,142,069

NETWORK NODE AND A METHOD THEREIN; A POSITIONING NODE AND A METHOD THEREIN; A USER EQUIPMENT AND A METHOD THEREIN, FOR HANDLING TRANSMISSION OF A REFERENCE SIGNAL

Telefonaktiebolaget LM Er...

1. A method performed by a network node of handling transmission of a positioning reference signal (PRS) in a network comprising a user equipment and a positioning node, the method comprising:determining a PRS configuration for use in a cell served by the network node;
when at least one subframe containing said PRS is also configured as a flexible subframe;
wherein the flexible subframe refers to a subframe whose direction can dynamically change between uplink and downlink over time,
comparing at least one parameter related to the PRS configuration with a threshold, wherein said at least one parameter comprises a PRS periodicity, a number of PRS subframes, a number of PRS occasions, a PRS bandwidth, a transmit power of a PRS and a PRS muting configuration;
wherein said threshold for each said at least one parameter is pre-defined or configured by another network node based on the at least one parameter related to the PRS configuration; and
deciding based on said comparison whether to operate the at least one subframe as a flexible subframe or only as a downlink subframe containing PRS transmission;
wherein while deciding, if a PRS muting is applied in that one or more PRS occasions are muted over a certain time period, then operating the at least one subframe as a PRS subframe if a number of PRS muting occasions is above said threshold, and otherwise operating the at least one subframe as a flexible subframe.

US Pat. No. 10,142,068

METHODS AND DEVICE FOR COMMUNICATIONS OF OFDM SIGNALS OVER WIDEBAND CARRIER

Futurewei Technologies, I...

17. A method for wireless communications, comprising:receiving, by a device, an orthogonal frequency division multiplexing (OFDM) signal transmitted over a single carrier within a transmission time interval, the OFDM signal comprising a first data stream and a second data stream;
obtaining, from the OFDM signal, a first baseband signal carried over a first sub-group of contiguous subcarriers in a group of contiguous subcarriers of the single carrier and a second baseband signal carried over a second sub-group of contiguous subcarriers in the group of contiguous subcarriers of the single carrier, the first baseband signal corresponding to the first data stream, and the second baseband signal corresponding to the second data stream;
performing first baseband processing on the first baseband signal to obtain the first data stream; and
performing second baseband processing on the second baseband signal to obtain the second data stream, the first baseband processing being performed on the first baseband signal independently and separately from the second baseband processing on the second baseband signal.

US Pat. No. 10,142,065

ENHANCED UE PERFORMANCE IN HETNET POOR COVERAGE SCENARIOS

Apple Inc., Cupertino, C...

1. A user equipment (UE), comprising:an antenna;
a radio coupled to the antenna; and
a processing element coupled to the radio;
wherein the UE is configured to:
receive at least one mobility offset from a first base station in a cellular network, wherein the UE is camped on a first cell, wherein the at least one received mobility offset specifies an adjustment for use by the UE in adjusting a measurement report submitted by the UE to the base station;
measure a quality of a downlink channel between the UE and the first base station;
compare the measured quality of the downlink channel to a threshold; and
in response to the measurement of the downlink channel being less than or equal to the threshold:
begin cell reselection, wherein to perform the cell reselection the UE is configured to submit the measurement report to the base station, wherein the measurement report does not include the adjustment specified by the at least one received mobility offset, wherein the submission of the measurement report without the adjustment specified by the at least one received mobility offset influences cell reselection; and
change from being camped on the first cell to camping on a second cell in response to the cell reselection.

US Pat. No. 10,142,064

TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH MACHINE TYPE COMMUNICATION IN ENHANCED COVERAGE MODE

Intel IP Corporation, Sa...

1. A user equipment (UE) comprising:transceiver circuitry to:
transmit, to an evolved node B (eNB), data in a first bundle of repeated Physical Uplink Shared Channel (PUSCH) transmissions; and
receive, from the eNB, a Hybrid Automatic Repeat reQuest (HARQ) negative-acknowledgement (NACK) in a Physical Downlink Control Channel (PDCCH) transmission, wherein the HARQ NACK from the eNB to the UE in response to the data in the first bundle of repeated PUSCH transmissions is received multiple times at a predefined or configured level of repetition across a plurality of subframes of the PDCCH transmission; and
logic circuitry coupled with the transceiver circuitry, the logic circuitry to determine an uplink starting subframe, based on the predefined or configured level of repetition, at which to begin retransmission of the data in a second PUSCH transmission in response to the HARQ NACK, and further to determine a downlink starting subframe at which to begin receipt of the PDCCH transmission of HARQ NACK for multiple times, based on a last subframe of the first bundle of repeated PUSCH transmissions.

US Pat. No. 10,142,061

METHOD AND APPARATUS FOR TRANSMITTING SIGNAL USING SPACE TIME BLOCK CODE OR SPACE FREQUENCY BLOCK CODE IN MULTI-CARRIER SYSTEM

Samsung Electronics Co., ...

1. A method for a transmitter to transmit a signal to a receiver in a diversity transmission mode, the method comprising:transmitting, to the receiver, a filter index indicating a filter allocated to the receiver; and
transmitting, to the receiver, space time block code (STBC) symbols at symbol positions selected based on the filter index.

US Pat. No. 10,142,060

COMMUNICATION SYSTEM AND METHOD HAVING POLAR CODING WITH TWO CONCATENATED CYCLIC REDUNDANCY CHECK CODES

QUALCOMM Incorporated, S...

10. A method for communication, comprising:receiving input data over a channel, the input data representing a polar-encoded combination of source data, second cyclic redundancy check (CRC) data, and first CRC data, the second CRC data encoding a combination of the source data and concatenated first CRC data, the first CRC data encoding the source data, wherein in the polar-encoded combination of source data, second cyclic redundancy check (CRC) data, and first CRC data at least one cluster of non-frozen bit positions includes information bit positions and CRC bit positions, and the non-frozen bit positions of the cluster separated from each other by a minimal number of frozen bit positions; and
decoding the input data using a plurality of successive decoding stages by, at each stage:
generating exactly two duplicate decoding paths for each of L paths to provide a set of 2L candidate paths, the two duplicate decoding paths representing respective decisions of 0 and 1, where L is an integer greater than 1;
evaluating, based on the source data, the set of 2L candidate paths to determine a set of L most reliable paths out of the set of 2L candidate paths;
removing from further evaluation all but the set of L most reliable paths, and preserving the set of L most reliable paths for a next decoding stage;
evaluating, based on the second CRC data, the set of L most reliable paths to determine a subset of paths passing a parity check;
terminating decoding if the subset of paths passing a parity check is empty; and
continuing decoding with the next decoding stage if the subset of paths passing the parity check is not empty.

US Pat. No. 10,142,059

METHOD FOR VERIFYING THE INTEGRITY OF DATA TRANSMISSION BETWEEN A MAIN UPSTREAM UNIT AND A MAIN DOWNSTREAM UNIT

1. Method for verifying the integrity of data transmission between a main upstream unit and a main downstream unit, the method being characterized in that it comprises implementing the steps of:(a) Generation, by a data processing module of the main upstream unit, of a first frame comprising a data packet to be transmitted and a cyclic redundancy code of said packet, and transmission to an interface module of the main upstream unit;
(b) Encapsulation, by said interface module of the main upstream unit, of the first frame in a second frame also including a cyclic redundancy code of the first frame;
(c) Transmission of the second frame to interface modules of the main downstream unit and of at least one auxiliary upstream unit;
(d) Extraction of the first frame from the second frame by the interface modules of the main downstream unit and of the at least one auxiliary upstream unit; and transmission to data processing modules of the main downstream unit and of the at least one auxiliary upstream unit;
(e) Extraction of the packet from the first frame by the data processing module of the main downstream unit; and extraction of the cyclic redundancy code of packet by the data processing module of the at least one auxiliary upstream unit;
(f) Encapsulation, by said interface module of the main upstream unit, of the cyclic redundancy code of packet in a third frame;
(g) Transmission of the third frame to the interface module of the at least one auxiliary upstream unit;
(h) Extraction of the cyclic redundancy code of packet from the third frame by the interface module of the at least one auxiliary upstream unit; and transmission to the data processing module of the at least one auxiliary upstream unit;
(i) Comparison by the data processing module of the at least one auxiliary upstream unit of each of the cyclic redundancy codes extracted from the first frame and from the third frame; and confirmation of the integrity of data transmission to the main downstream unit only if comparison is positive.

US Pat. No. 10,142,058

COMMUNICATION DEVICE AND COMMUNICATION METHOD

LSIS CO., LTD., Anyang-s...

1. A communication method for a first communication device transmitting data to a second communication device, the communication method comprising:generating, by a safety unique identifier generation unit of the first communication device, a safety unique identifier (ID) for confirming validity of connection between the first communication device and the second communication device using a unique ID of the first communication device and a unique ID of the second communication device;
calculating by an error detection code calculation unit of the first communication device, a header error detection code for detecting an error of header data using the generated safety unique ID, a sequence number and the header data;
calculating by the error detection code calculation unit of the first communication device, a data error detection code for detecting an error of safety data using the generated safety unique ID, the sequence number and the safety data;
generating by a PDU generation unit of the first communication device, a packet comprising the safety data, the calculated data error detection code, and the calculated header error detection code; and
transmitting by a data transmission unit of the first communication device, the generated packet to the second communication device,
wherein the safety unique identifier is generated by using a source Media Address Control (MAC) address of the first communication device, a source device ID of the first communication device, a destination MAC address of the second communication device and a destination device ID of the second communication device,
wherein the safety data is related to a command field, and
wherein if a value of the command field is a first value, the safety data represents a reset command,
if the value of the command field is a second value, the safety data represents a connection command,
if the value of the command field is a third value, the safety data represents a parameter transmission command, and
if the value of the command field is a fourth value, the safety data represents a data transmission command.

US Pat. No. 10,142,054

TRANSMISSION APPARATUS, CONTROL METHOD, AND PROGRAM

NEC Corporation, Tokyo (...

1. A transmission apparatus transmitting collection information to a collection apparatus through multiple portable terminals, comprising:a communication unit performing directly wireless communication with a portable terminal;
a collection information acquisition unit acquiring the collection information;
a division transmission unit generating multiple pieces of partial collection information by dividing the collection information, and transmitting pieces of partial collection information being different from each other to the multiple portable terminals using the communication unit;
a redundancy transmission unit transmitting same collection information to the multiple portable terminals using the communication unit;
an index value acquisition unit acquiring any one or two of a reliability index value and a capacity index value for the portable terminal, the reliability index value indicating reliability of communication being performed between the portable terminal and the transmission apparatus, the capacity index value indicating capacity of the portable terminal; and
a transmission control unit selecting either of the division transmission unit or the redundancy transmission unit, based on any one or two of the reliability index value and the capacity index value of the portable terminal, and causing the selected unit to perform the transmission of the collection information.

US Pat. No. 10,142,053

METHOD AND APPARATUS FOR TRANSMITTING CONTROL INFORMATION TO REMOVE AND SUPPRESS INTERFERENCE IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A communication method of a user terminal, the method comprising:receiving, from a serving base station, at least one first interference parameters associated with a neighbor base station;
receiving, from the serving base station, information on a candidate group of available values for at least one second interference parameters associated with the neighbor base station;
performing blind detection of the at least one second interference parameters based on the information on the candidate group;
receiving, from the serving base station, downlink data; and
decoding the downlink data based on the at least one first interference parameters and the at least one second interference parameters.

US Pat. No. 10,142,051

TRANSMISSION DEVICE AND RECEPTION DEVICE

KYOCERA Corporation, Kyo...

1. A transmission device configured to transmit transmission information to a reception device via a communication channel, comprising:a grouping unit configured to divide the transmission information into a plurality of information groups;
an error detection code adding unit configured to add an error detection code to the plurality of information groups; and
a transmission processing unit configured to perform a process of transmitting the plurality of information groups to the reception device, wherein
the transmission processing unit performs, for each information group included in the plurality of information groups, a transmission process by using methods having different error tolerance on the communication channel.

US Pat. No. 10,142,050

ENCODING MODULATION METHOD AND TRANSMITTER

1. An encoding modulation method, comprising:performing a process of oversampling and noise-shaping for received multi-bit data to obtain N-bit data;
looking up a table to obtain a pulse modulation signal of a Pulse Width Modulator, PWM, according to the N-bit data used as an address of the lookup table;
multiplexing In-phase Quadrature, IQ, complex data of the pulse modulation signal of the PWM to be a stream of real number signal data to realize up-conversion transformation with a quarter of a sampling rate;
converting the multiplexed real number signal data to an analog signal and performing power amplification on the analog signal to output, and
wherein, N is an integer of which a number of bits is smaller than that of the received multi-bit data.

US Pat. No. 10,142,047

OPTICAL TRANSMISSION APPARATUS AND OPTICAL TRANSMISSION METHOD

FUJITSU LIMITED, Kawasak...

1. An optical transmission apparatus, comprising:a receiver configured to receive a wavelength division multiplexing optical signal including a first optical signal modulated based on a first modulation system and a second optical signal modulated based on a second modulation system with a higher multi-level degree than the first modulation system;
a wavelength selective switch configured to attenuate power of the first optical signal to a first level and attenuate power of the second optical signal to a second level lower than the first level;
an optical amplifier configured to amplify the wavelength division multiplexing optical signal including the first optical signal and the second optical signal output from the wavelength selective switch; and
a transmitter configured to transmit the wavelength division multiplexing optical signal amplified by the optical amplifier.

US Pat. No. 10,142,043

TIME DIFFERENTIAL DIGITAL CIRCUIT

VIAVI SOLUTIONS INC., Mi...

1. A time differential digital circuit comprising:a synchronization pattern generator to generate synchronization bit pattern;
a first input to receive the synchronization bit pattern or a first change in the synchronization bit pattern;
a second input to receive the synchronization bit pattern or a second change in the synchronization bit pattern;
a bit pattern detector to:
detect the first change in feedback of the synchronization bit pattern at the first input caused by a first event signal, and generate a first timestamp of the detected first change at the first input; and
detect the second change in the feedback of the synchronization bit pattern at the second input caused by a second event signal, and generate a second timestamp of the detected second change at the second input; and
a differential time detector to determine, based on the first and second timestamps and delays associated with delay paths for the first and second inputs, a time difference between receiving the first and second event signals.

US Pat. No. 10,142,042

METHOD AND SYSTEM FOR A DISTRIBUTED RECEIVER

Radioxio, LLC, Saint Pau...

1. A first semiconductor die comprising:an interface receiver circuit operable to:
receive an externally-generated signal that carries decision outputs of a symbol de-mapper that is external to the first semiconductor die, the externally-generated signal comprising a plurality of time stamps, each one of the plurality of time stamps corresponding to one of the decision outputs of the symbol de-mapper, and
process the externally-generated signal to recover the decision outputs of the symbol de-mapper carried in the externally-generated signal; and
a demodulation circuit operable to recover one datastreams based on the decision outputs of the symbol de-mapper.

US Pat. No. 10,142,041

HOMODYNE RECEIVER CALIBRATION

Telefonaktiebolaget LM Er...

1. A method for calibrating a homodyne receiver in a signal distribution network for time division duplex, the method being performed by a baseband calibration module, the method comprising:acquiring a transmission signal being input to a homodyne transmitter of the signal distribution network;
acquiring, from a heterodyne transmitter observation receiver of the signal distribution network, a first received version of said transmission signal;
acquiring, from a homodyne receiver of the signal distribution network, a second received version of said transmission signal; and,
calibrating the homodyne receiver using a comparison of said first received version of said transmission signal and said second received version of said transmission signal, using said first received version of said transmission signal as a reference signal, and using said transmission signal as a calibration signal.

US Pat. No. 10,142,040

APPARATUS FOR REDUCING AN AMPLITUDE IMBALANCE AND A PHASE IMBALANCE BETWEEN AN IN-PHASE SIGNAL AND A QUADRATURE SIGNAL

Intel IP Corporation, Sa...

1. An apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal, the in-phase signal and the quadrature signal being based on a radio frequency receive signal, comprising:an imbalance estimation circuit configured to generate a first correction signal related to a first phase shift, and to generate a second correction signal related to a second phase shift, wherein the first and second correction signals are generated based on the in-phase signal and the quadrature signal;
a first digital-to-time converter configured to receive the first correction signal and a local oscillator signal, and to supply a first replica of the local oscillator signal for a first mixer generating the in-phase signal, the first replica of the local oscillator signal having the first phase shift with respect to the local oscillator signal; and
a second digital-to-time converter configured to receive the second correction signal and the local oscillator signal, and to supply a second replica of the local oscillator signal for a second mixer generating the quadrature signal, the second replica of the local oscillator signal having the second phase shift with respect to the local oscillator signal,
wherein the imbalance estimation circuit is configured to calculate the first phase shift based on at least one of information related to the amplitude imbalance and information related to the phase imbalance, and
wherein the imbalance estimation circuit is configured to calculate the first phase shift according to an operation which is mathematically correspondent to

 with ?1 denoting the first phase shift, and k denoting an estimation of the amplitude imbalance, or
wherein the imbalance estimation circuit is configured to calculate the first phase shift according to an operation which is mathematically correspondent to

 with ?1 denoting the first phase shift, and k denoting an estimation of the amplitude imbalance.

US Pat. No. 10,142,038

MIMO SIGNAL GENERATOR WITH FREQUENCY MULTIPLEXING

1. A MIMO signal generator, adapted to generate a MIMO signal, comprising:a signal generator, a signal divider, and a frequency shifter,
wherein the signal generator is adapted to generate a plurality of frequency shifted partial MIMO signals within a first signal generator output signal, the plurality of frequency shifted partial MIMO signals being arranged on a frequency axis in a non-overlapping manner,
wherein the signal divider is adapted to divide the first signal generator output signal onto a plurality of signal paths,
wherein the frequency shifter is adapted to shift frequencies of the plurality of frequency shifted partial MIMO signals to a joint carrier frequency, resulting in a plurality of partial MIMO signals, forming the MIMO signal, and
wherein the signal generator is adapted arrange the plurality of frequency shifted partial MIMO signals on the frequency axis in the non-overlapping manner, by placing a carrier frequency of all but one of the plurality of frequency shifted partial MIMO signals to different frequencies.

US Pat. No. 10,142,037

MEASUREMENT DEVICE AND MEASUREMENT METHOD

ANRITSU CORPORATION, Kan...

3. A measurement device, comprising:a plurality of measurement means that are respectively connected to a plurality of devices to be measured capable of using a plurality of communication frequency bands, and perform measurements of at least one of transmission characteristics and reception characteristics of the plurality of devices to be measured in parallel using different communication frequency bands,
wherein the communication frequency bands correspond to different channels and/or different communication protocols,
wherein each of the plurality of measurement means comprises:
signal input means for receiving a signal for measuring the transmission characteristics with a frequency in a communication frequency band from each of the plurality of measurement devices, respectively; and
signal output means for outputting a signal for measuring the reception characteristics with a frequency in a communication frequency band to each of the plurality of devices to be measured, respectively,
wherein the measurement device further comprises:
band information storage means for storing information on the communication frequency bands handled by the plurality of signal input means and the plurality of signal output means;
band setting means for setting a communication frequency band handled by the plurality of signal input means and the plurality of signal output means; and
band management means for executing a process of storing information on a communication frequency band handled by the plurality of signal input means and the plurality of signal output means in the band information storage means, and clearing the information on the used communication frequency band from the band information storage means when the plurality of signal input means and the plurality of signal output means end measurement,
wherein the band setting means outputs a use request for use of the signal input means or the signal output means, and a communication frequency band desired to be used, to the band management means,
wherein the band management means determines permission or refusal in response to the use request on the basis of the information on the communication frequency band stored in the band information storage means with respect to the band setting means, and
wherein in the plurality of measurement means:
the band information storage means is included in the plurality of measurement means, and includes a plurality of used band information storage means for storing information on a communication frequency band handled by the signal input means and the signal output means of the own measurement means; and
the band setting means is included in the plurality of measurement means, and includes used band setting means for setting the communication frequency band handled by the signal input means and the signal output means of the own measurement means on the basis of information on the communication frequency band stored in the used band information storage means of another measurement means.

US Pat. No. 10,142,035

INFORMATION TRANSMISSION METHOD, APPARATUS AND SYSTEM

Tencent Technology (Shenz...

1. An information transfer method, applied to a first terminal having one or more processors and a memory for storing program instructions that are executed by the one or more processors, the method comprising:acquiring to-be-transmitted information;
encoding the to-be-transmitted information at least once by using a preset encoding mode, to obtain vibration code information; and
determining, according to a preset rule, a vibration rhythm corresponding to the vibration code information, and causing the first terminal to vibrate according to the determined vibration rhythm, so as to transfer the to-be-transmitted information to a second terminal.

US Pat. No. 10,142,032

TEMPERATURE INSENSITIVE DELAY LINE INTERFEROMETER

INPHI CORPORATION, Santa...

1. A photonics optical system comprising:a photonics device with temperature insensitive characteristics comprising:
a first waveguide comprising a first length of a first material characterized by a first group index corresponding to a first phase delay for transferring a first light wave with a first peak frequency at an ambient temperature;
a second waveguide comprising a second length of a second material characterized by a second group index corresponding to a second phase delay for transferring a second light wave with a second peak frequency with a time-delay difference relative to the first light wave at the same ambient temperature;
wherein the first phase delay and the second phase delay are configured to change by a same amount upon any change of the ambient temperature, and the time-delay difference of the first light wave and the second light wave is equal to an inversed value of a free spectral range (FSR) configured to align the first peak frequency and the second peak frequency to two channels in a designated frequency grid; and
a network.

US Pat. No. 10,142,029

DEVICE FOR MODULATING THE INTENSITY OF AN OPTICAL SIGNAL ON FOUR DIFFERENT LEVELS

1. Device for modulating the intensity of an optical signal on four different levels, wherein the device comprises:a power divider comprising an input to receive an initial optical signal to be modulated and first and second outputs which each deliver, respectively, first and second optical signals to be modulated, the intensity of each of these first and second optical signals to be modulated being equal to a non-zero fraction of the intensity of the initial optical signal received on the input of the power divider,
a first resonant ring modulator comprising:
an input port optically coupled to the first output of the power divider to receive the first optical signal to be modulated,
a first output port configured to deliver a first intensity-modulated optical signal, constructed by modulating the intensity of the optical signal received on the input port between only a high level and a low level,
a control port configured to receive a first binary control signal in response to which the first resonant ring modulator varies the intensity of the first optical signal to be modulated between the high and low levels to obtain the first modulated optical signal,
a second output configured to deliver an optical signal complementary to the first modulated optical signal, the intensity of the complementary optical signal being at the low level when the intensity of the first modulated optical signal is at the high level and vice versa,
second resonant ring modulator comprising:
an input port optically coupled to the second output of the power divider to receive the second optical signal to be modulated,
an output port configured to deliver a second modulated optical signal constructed by modulating the intensity of the optical signal received on its input port between only a high level and a low level,
a control port configured to receive a second binary control signal in response to which the second resonant ring modulator varies the intensity of the optical signal received on its input port between the high and low levels to obtain the second modulated optical signal,
a first optical assembler comprising:
a first input optically coupled to one of the first and second output ports of the first resonant ring modulator to receive the first modulated optical signal,
a second input optically coupled to the output port of the second resonant ring resonator modulator to receive the second modulated optical signal, and
an output configured to generate a first combined optical signal constructed by combining optical signals received on the first and second inputs of the first optical assembler,
a second optical assembler comprising:
a first input optically coupled to the output port of the first optical assembler
a second input optically coupled to the other of the first and second output ports of the first resonant ring modulator, and
an output configured to deliver the optical signal of which the intensity is modulated on at most four different levels constructed by combining optical signals received on its first and second inputs.

US Pat. No. 10,142,028

SIGNALING METHOD FOR LEVERAGING POWER ATTENUATION IN A MANDREL-WRAPPED OPTICAL FIBER

Dell Products L.P., Roun...

11. A non-transitory computer readable medium comprising processor executable program instructions that, when executed by the processor, cause operations including:monitoring a parameter of an optical signal transmitted between two endpoints via an optical fiber;
modifying a diameter of a mandrel around which a portion of the optical fiber is wrapped to modulate the parameter wherein the mandrel comprises a high order mode filter (HOMF); and
identifying data in accordance with the modulation of the monitored parameter;
wherein the optical signal is transmitted from a first endpoint to a second endpoint and wherein the monitored parameter comprises a received power parameter indicative of an average power of the optical signal as received at the second endpoint.

US Pat. No. 10,142,025

HIGH-DIRECTIVITY DIRECTIONAL COUPLER, AND RELATED METHODS AND SYSTEMS

Corning Optical Communica...

1. A high-directivity directional coupler, comprising:a substrate;
a ground plane disposed underneath the substrate;
an input port configured to receive an input signal;
an output port configured to output the received input signal as an output signal;
a coupled port configured to output a coupled signal proportional to the input signal;
an isolated port configured to provide isolation to the input signal and the coupled signal;
a first microstrip disposed above the substrate, the first microstrip configured to convey the input signal from the input port to the output port; and
a second microstrip disposed above the substrate parallel to the first microstrip, the second microstrip configured to:
provide a linear forward path for conveying an even mode current from the coupled port to the ground plane; and
provide a non-linear return path longer than the linear forward path for conveying an odd mode current in an opposite direction from the even mode current.

US Pat. No. 10,142,024

HIGHER-LEVEL CLOCK AND DATA RECOVERY (CDR) IN PASSIVE OPTICAL NETWORKS (PONS)

Futurewei Technologies, I...

1. An apparatus comprising:an optical-to-electrical (OE) component configured to convert an optical signal with a first modulation format to an analog electrical signal;
an analog-to-digital converter (ADC) coupled to the OE component and configured to convert the analog electrical signal to a first digital signal; and
a clock and data recovery (CDR) sub-system coupled to the ADC and configured to:
equalize the first digital signal into a second digital signal with a second modulation format, the second modulation format having more levels than the first modulation format; and
perform CDR on the second digital signal.

US Pat. No. 10,142,023

ANTENNA SYSTEM AND METHODS FOR WIRELESS OPTICAL NETWORK TERMINATION

CenturyLink Intellectual ...

1. An optical network termination system comprising:an optical fiber in communication with an external telecommunications information network;
a processor in communication with the optical fiber and providing for the processing of telecommunications information conveyed over the optical fiber to or from the external telecommunications information network said processor being housed outside of a premises;
an electrically conductive internal transport medium in communication with the processor, wherein the electrically conductive internal transport medium provides for the bidirectional conveyance of a first subset of the telecommunications information from the processor into the premises;
a wireless internal transport medium comprising a wireless access point in communication with the processor and housed with the processor outside of the premises:
a distributed antenna in communication with the wireless access point, the distributed antenna comprising a feed line attached to one or more walls of the customer premises and one or more radiating elements extending from the feed line, wherein the wireless internal transport medium provides for the bidirectional wireless conveyance of a second subset of the telecommunication information from the one or more radiating elements into the premises;
a signal detection circuit in communication with the distributed antenna providing for the detection of a signal received by the one or more radiating elements and further providing for the disabling or enabling of selected radiating elements based upon detected signal strength;
a port terminating the electrically conductive internal transport medium within the premises;
a power supply configured to be connected to an AC outlet within the premises; and
a back-power cable providing for the transmission of power from the power supply to the wireless access point over the electrically conductive internal transport medium upon connection of the back-power cable to the port, wherein the power is provided, over the electrically conductive internal transport medium, to the selected radiating elements.

US Pat. No. 10,142,022

ADJUSTMENT OF CONTROL PARAMETERS OF SECTION OF OPTICAL FIBER NETWORK

Ciena Corporation, Hanov...

1. A method for adjustment of one or more control parameters of a section of an optical fiber network, the method comprising:taking measurements of optical signals in the section;
deriving estimated data from the measurements and from knowledge of the section, where the estimated data is a function of optical nonlinearity and of amplified spontaneous emission;
evaluating gradients of an objective function using the measurements and the estimated data; and
applying one or more control algorithms using at least the gradients to adjust the one or more control parameters.

US Pat. No. 10,142,021

SATELLITE SYSTEM USING OPTICAL GATEWAYS AND GROUND BASED BEAMFORMING

1. A ground based subsystem for use in transmitting an optical feeder uplink beam to a satellite that includes a multiple element antenna feed array and that is configured to receive the optical feeder uplink beam and in dependence thereon use the multiple element antenna feed array to produce and transmit a plurality of RF service downlink beams to service terminals, the ground based subsystem comprising:a ground based beamformer (GBBF) configured to accept a plurality of spot beam signals, produce or otherwise obtain phase and amplitude beamforming coefficients, and output a plurality of feed element signals in dependence on the plurality of spot beam signals and the phase and amplitude beamforming coefficients;
a plurality of lasers, each of the lasers operable to emit an optical signal having a different peak wavelength within a specified optical wavelength range;
a plurality of electro-optical modulators (EOMs), each EOM of the plurality of EOMs configured to accept an optical carrier signal from a respective one of the plurality of lasers, accept a different one of the plurality of feed element signals from the GBBF, and output a respective optical feed element signal in dependence on the optical carrier signal and the feed element signal accepted by the EOM;
a wavelength-division multiplexing (WDM) multiplexer configured to accept the optical feed element signals output by the plurality of EOMs, and combine the plurality of optical feed element signals into a wavelength division multiplexed optical signal;
an optical amplifier configured to amplify the wavelength division multiplexed optical signal to thereby produce an optically amplified wavelength division multiplexed optical signal; and
transmitter optics configured to accept the optically amplified wavelength division multiplexed optical signal and transmit an optical feeder uplink beam to the satellite in dependence thereon.

US Pat. No. 10,142,020

REPRODUCTION METHOD FOR REPRODUCING CONTENTS

PANASONIC INTELLECTUAL PR...

1. A reproduction method comprising:receiving a visible light signal from a sensor of a terminal device from a transmitter which transmits the visible light signal by a light source changing in luminance;
transmitting a request signal for requesting a content associated with the visible light signal from the terminal device to a server;
receiving from the server, with the terminal device, the content including time points and pieces of data, each of which corresponds to one of the time points, to be reproduced; and
reproducing one of the pieces of data among the pieces of data of the content with the terminal device,
wherein the terminal device synchronizes one of the time points, corresponding to the one of the pieces of reproduced data, with a terminal device time point indicated by a clock included in the terminal device.

US Pat. No. 10,142,019

END USER DEVICE AND ASSOCIATED METHOD FOR SELECTING VISIBLE LIGHT COMMUNICATION PERSONAL AREA NETWORK COORDINATOR

WIPRO LIMITED, Bangalore...

10. An End User Device (EUD) in a Light Fidelity (Li-Fi) network, the EUD comprising:a network interface communicatively coupled to a current Visible light communication Personal Area Network Coordinator (VPANC);
a processor; and
a memory communicatively coupled to the processor, wherein the memory stores processor instructions, which, on execution, causes the processor to:
receive a set of customized channel scan parameters and a VPANC selection policy from the current VPANC the EUD is associated with, wherein the set of customized channel scan parameters and the VPANC selection policy are created by the current VPANC,
wherein the set of customized channel scan parameters and the VPANC selection policy are created by the current VPANC based on one or more channel scan parameters and VPANC controlling parameters associated with neighboring VPANCs of the current VPANC and EUD information received from a plurality of EUDs associated with the current VPANC, and
wherein the one or more channel scan parameters comprises a range of frequencies, a channel scan duration, and a time interval between channel scans, and wherein the VPANC control parameters comprises number of the neighboring VPANCs of the current VPANC, list of the neighboring VPANCs, geo-location of dead zones near the current VPANC, and VPANC measurement reports associated with each neighboring VPANC;
assess quality of an active channel currently used by the EUD, wherein the active channel is associated with the current VPANC; and
switch to a new VPANC from a plurality of VPANCs based on the set of customized channel scan parameters and the VPANC selection policy in response to the assessing, wherein the plurality of VPANCs comprise the current VPANC.

US Pat. No. 10,142,017

BEACON DEMODULATION WITH BACKGROUND SUBTRACTION

X Development LLC, Mount...

1. A method comprising:collecting, at a receiver of a first communication device, a plurality of frames, each frame being an image of a location and having a resolution including a plurality of pixels, each pixel having a pixel value corresponding to a color;
determining, by one or more processors of the first communication device, a static background of the location by averaging the pixel values of the plurality of frames collected at the receiver;
determining, by the one or more processors, pixel difference values for each frame by subtracting the determined static background from the pixel values of each frame;
identifying, by the one or more processors, a first subset of frames and a second subset of frames using the pixel difference values for each frame in the plurality of frames;
determining, by the one or more processors, an average pixel difference by averaging the pixel difference values of the first subset of frames and an inverse of the pixel difference values of the second subset of frames; and
determining, by the one or more processors, a position of a beacon of a second communication device at the location using the average pixel difference in order to align the first communication device and the second communication device for a communication link.

US Pat. No. 10,142,014

MULTI-FUNCTION DEVICE AND TERMINAL DEVICE

Brother Kogyo Kabushiki K...

1. A multi-function device configured to perform at least one of a printing function and scanning function, the multi-function device comprising:a short-range wireless interface configured to perform wireless communication with a terminal device using a short-range wireless communication protocol, the short-range wireless interface operable in a peer-to-peer mode and another mode which is one of a reader/writer mode and a card emulation mode;
a Wi-Fi interface configured to perform wireless communication with the terminal device using a Wi-Fi-compliant communication protocol;
a processor; and
a memory storing computer-readable instructions therein, the computer-readable instruction, when executed by the processor, causing the multi-function device to perform:
receiving, over a short-range wireless connection via the short-range wireless interface in the peer-to-peer mode, request information from the terminal device for causing the multi-function device to perform the at least one of the printing function and the scanning function;
in a case where a first determination process for causing only a permitted user to perform the at least one of the print function and the scanning function is to be executed,
transmitting, via the short-range wireless interface in the peer-to-peer mode, first response information to the terminal device in response to the receiving of the request information, wherein the first response information causes the terminal device to transmit authentication information for performing the at least one of the printing function and the scanning function via the short-range wireless interface in the another mode;
terminating the short-range wireless connection to the terminal device in the peer-to-peer mode after transmitting the first response information to the terminal device;
reactivating the short-range wireless connection to the terminal device in the another mode after terminating the short-range wireless connection to the terminal device;
receiving from the terminal device, via the short-range wireless interface in the another mode, the authentication information for performing the at least one of the printing function and the scanning function;
executing the first determination process in which the multi-function device determines whether performing the at least one of the printing function and the scanning function is permitted or not by determining whether the authentication information is correct in response to the receiving the authentication information;
when determined, in the first determination process, that performing the at least one of the printing function and the scanning function is permitted by determining that the authentication information is correct, performing, via the short-range wireless interface in the another mode, communication of network information to be used to connect with the Wi-Fi interface, otherwise, when determined, in the first determination process, that performing the at least one of the printing function and the scanning function is not permitted by determining that the authentication information is incorrect, not performing the communication of the network information; and
when the network information has been communicated, performing wireless communication with the terminal device using the Wi-Fi interface and performing the at least one of the printing function and the scanning function; and
in a case where the first determination process for causing only a permitted user to perform the at least one of the print function and the scanning function is not to be executed,
terminating the short-range wireless connection to the terminal device in the peer-to-peer mode without transmitting the first response information to the terminal device;
performing via the short-range wireless interface, communication of network information to be used to connect with the Wi-Fi interface;
performing wireless communication with the terminal device using the Wi-Fi interface; and
performing the at least one of the print function and the scanning function.

US Pat. No. 10,142,013

METHOD OF OPTIMIZING AN INTERPLANETARY COMMUNICATIONS NETWORK

The Boeing Company, Chic...

1. A method of optimizing a communications network, said method comprising:providing an initial network configuration for an interplanetary communications network, said interplanetary communications network having a plurality (k) of nodes;
providing forecasts of traffic demand in said interplanetary communications network;
determining objective functions by a computer responsive to said demands and characterizing communications over links between said nodes in said network;
determining by said computer at least one limit for each said objective function;
adjusting said initial network configuration, and thereby producing an adjusted network configuration, responsive to said at least one limit for each said objective function; and
deploying said interplanetary communications network with said adjusted network configuration.

US Pat. No. 10,142,009

INTERFACE MODULE FOR A UNIT OF AN ANTENNA DISTRIBUTION SYSTEM, AND ANTENNA DISTRIBUTION SYSTEM

Andrew Wireless Systems G...

1. A distributed antenna system comprising:at least one master unit communicatively coupled to at least one base station; and
a plurality of remote units located remotely from the at least one master unit, wherein each of the plurality of remote units is communicatively coupled to the master unit over at least one transport communication link;
the system configured to distribute a first signal, received from the at least one base station, from the master unit to at least one remote unit in analog form, wherein the at least one remote unit radiates a second signal derived from the first signal from at least one antenna associated with the at least one remote unit;
a digital circuit configured to generate digital samples by digitally sampling the first signal;
a network interface for communicating with an external central control computer configured for central control of the distributed antenna system, wherein the external central control computer is distinct from the at least one base station;
the digital circuit configured to process the digital samples and communicate information about parameters of the first signal to the external central control computer via the network interface.

US Pat. No. 10,142,008

DATA COMPRESSION FOR WIRELESS RELAYS IN A DATA COMMUNICATION NETWORK

Sprint Communications Com...

1. A method of operating a wireless relay to serve User Equipment (UE) over a Radio Area Network (RAN) and a Wide Area Network (WAN), the method comprising:an evolved Node B (eNodeB) performing Tunneling Compression Multiplexing (TCM) on S1-MME signaling data and X2 signaling data and exchanging the compressed S1-MME signaling data and the compressed X2 signaling data with a data switch;
the eNodeB wirelessly exchanging user data with the UE and exchanging the user data with a Local Gateway (L-GW);
the L-GW separating the user data into RAN user data and WAN user data, performing TCM on the RAN user data, the WAN user data, and S11 signaling data, and exchanging the compressed RAN user data, the compressed WAN user data, and the compressed S11 signaling data with the data switch;
the data switch exchanging the compressed RAN user data, the S1-MME signaling data, the compressed X2 signaling data, and the compressed S11 signaling data with a Relay Equipment (RE) and exchanging the compressed WAN user data with an Internet Protocol Security (IPSec) agent;
the RE performing Robust Header Compression over Long Term Evolution (ROHCoLTE) for a RAN data tunnel and wirelessly exchanging the compressed RAN user data, the compressed S1-MME signaling data, the compressed X2 signaling data, and the compressed S11 signaling data over the compressed RAN data tunnel; and
the IPSec agent performing Robust Header Compression over IPSec (ROHCoIPSec) for a compressed WAN data tunnel and exchanging the compressed WAN user data over the compressed WAN data tunnel.

US Pat. No. 10,142,007

RADIO COMMUNICATION DEVICES AND METHODS FOR CONTROLLING A RADIO COMMUNICATION DEVICE

Intel Deutschland GmbH, ...

25. A radio communication device comprising:an antenna configured to operate in an operation mode of a plurality of operation modes that are respective radiation patterns;
a transmitter configured to transmit data using the antenna;
an evaluation circuit configured to evaluate a plurality of operation modes of the antenna in a plurality of cells;
a mode switching circuit configured to switch the operation mode of the antenna at least if the transmitter fulfils a predetermined transmitter criterion,
wherein the predetermined transmitter criterion is an indication of non-urgent uplink data;
a selection circuit configured to select the operation mode of the antenna based on a further predetermined criterion, wherein the further predetermined criterion is a highest acknowledgement rate of the plurality of operation modes evaluated by the evaluation circuit;
a memory configured to temporarily store the non-urgent uplink data until the selection circuit selects the operation mode of the antenna.

US Pat. No. 10,142,003

PRECODING INFORMATION OBTAINING APPARATUS, METHOD, AND SYSTEM

Huawei Technologies Co., ...

1. A precoding information obtaining method, comprising:determining a transformation matrix according to a steering vector of an antenna form and a departure-angle range;
sending information about the transformation matrix to a terminal for determining a precoding matrix indicator (PMI) according to the information about the transformation matrix, a codebook for obtaining channel information, and a pilot measurement result, wherein sending the information about the transformation matrix comprises:
sending a system information block to the terminal, wherein the system information block comprises the information about the transformation matrix, wherein the system information block comprises:
a horizontal transformation matrix indicator for indicating whether the transformation matrix is in a horizontal direction,
a horizontal transformation matrix dimension for indicating a dimension of the transformation matrix in the horizontal direction,
a horizontal transformation matrix nonzero quantity for indicating a quantity of nonzero elements of the transformation matrix in the horizontal direction, and
a horizontal transformation matrix element for indicating a value of the nonzero element of the transformation matrix in the horizontal direction; and
receiving the PMI reported by the terminal.

US Pat. No. 10,142,002

METHOD OF HANDLING MULTIUSER CQI FOR MU-MIMO AND RELATED COMMUNICATION DEVICE

Industrial Technology Res...

1. A method of handling at least one multiuser channel quality indicator (MU-CQI) set for a communication device, the method being utilized in a communication device and comprising:being indicated at least one companion precoding matrix index (PMI) set by a network via receiving information of the at least one companion PMI set from the network, wherein the at least one companion PMI set is determined by the network rather than the communication device, and the information of the at least one companion PMI set is transmitted by the network;
determining at least one MU-CQI set according to the at least one companion PMI set, respectively, wherein each MU-CQI of each MU-CQI set of the at least one MU-CQI set corresponds to each companion PMI of each companion PMI set of the at least one companion PMI set;
receiving a plurality of PMI sets via a higher layer signaling transmitted by the network:
selecting the at least one companion PMI set from the plurality of PMI sets according to the information: and
transmitting the at least one MU-CQI set to the network aperiodically.

US Pat. No. 10,142,000

ANTENNA APPARATUS

Mitsubishi Electric Corpo...

1. An antenna apparatus comprising:a plurality of sub-arrays (2-n: n=1, . . . , N) each of which is constituted by a plurality of element antennas (3-k: k=1, . . . , K);
a terminal position detector (32) to detect positions of a plurality of user terminals being communication objects;
a sub-array number determinator (41) to determine a number of sub-arrays to be allocated to each of the plurality of user terminals detected by the terminal position detector (32) on a basis of relation between the positions of the plurality of user terminals and a position of the antenna apparatus; and
an antenna selector (50) to select sub-arrays for the number determined by the sub-array number determinator (41) from among the plurality of sub-arrays (2-n) and allocate the selected sub-arrays for the determined number to each of the plurality of user terminals.

US Pat. No. 10,141,998

UTILIZATION OF ANTENNA BEAM INFORMATION

TELEFONAKTIEBOLAGET LM ER...

1. A method for utilizing antenna beam information, the method comprising a network node:acquiring antenna beam information indicative of a direction of a wireless device (WD) specific beam of the network node;
classifying the acquired antenna beam information into a cell-specific beam category based on an angular difference between the direction of the WD-specific beam and a direction of main lobe of a cell-specific beam of the network node; and
performing at least one of a load balancing action of the WD and a radiation beam pattern change related to the cell-specific beam category.

US Pat. No. 10,141,994

TECHNIQUE FOR REDUCING RESPONDING SECTOR SWEEP TIME FOR MILLIMETER-WAVE DEVICES

QUALCOMM Incorporated, S...

1. An apparatus for wireless communications, comprising:a first interface for obtaining first frames from a wireless node during a sector sweep procedure;
a processing system configured to generate feedback regarding a transmit beamforming sector associated with one of the first frames, based on received signal qualities of the first frames as observed at the apparatus, and to generate second frames including the feedback, wherein the first frames have a first frame format and the second frames have a second frame format that is different from the first frame format; and
a second interface configured to output the second frames for transmission to the wireless node, wherein the second frame format has a frame control field having fewer bits than a frame control field of the first frame format.

US Pat. No. 10,141,993

MODULAR ANTENNA ARRAY BEAM FORMING

Intel Corporation, Santa...

1. A radio communication device comprising:a plurality of antenna arrays each configured to generate a steerable antenna beam according to a respective beamforming codeword, wherein each of the plurality of antenna arrays is configured to obtain the respective beamforming codeword from a single-antenna-array steering codebook that is common to each of the plurality of antenna arrays; and
a beamforming circuit configured to weight signals for the plurality of antenna arrays to coordinate the steerable antenna beams from a subset of the plurality of antenna arrays independently of the respective beamforming codewords assigned to the plurality of antenna arrays to form a combined antenna beam in a first steering direction.

US Pat. No. 10,141,992

CODEBOOK DESIGN AND STRUCTURE FOR ADVANCED WIRELESS COMMUNICATION SYSTEMS

Samsung Electronics Co., ...

1. A user equipment (UE) capable of communicating with a base station (BS), the UE comprising:a transceiver configured to:
receive, from the BS, downlink signals including precoding matrix indicator (PMI) codebook parameters comprising:
first and second quantities of antenna ports, N1 and N2, indicating respective quantities of antenna ports in first and second dimensions of a dual-polarized antenna array at the BS,
first and second oversampling factors, O1 and O2, indicating respective oversampling factors for Discrete Fourier Transform (DFT) beams in the first and second dimensions, and
a beam group configuration among a plurality of beam group configurations; and
a controller configured to:
determine a plurality of PMIs using a PMI codebook corresponding to the received PMI codebook parameters, wherein the plurality of PMIs comprises a first PMI (i1) indicating a plurality of DFT beams in a beam group, and a second PMI (i2) indicating one beam selection out of the plurality DFT beams and a co-phase value selection for the two polarizations of the antenna array the BS, and
cause the transceiver to transmit uplink signals containing the plurality of PMIs to the BS.

US Pat. No. 10,141,991

ADAPTIVE CODEWORD AND CODEBLOCK SELECTION IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:identifying, for a carrier supporting a plurality of service types, resources for a first multiple-input multiple-output (MIMO) transmission;
identifying a first service type associated with the first MIMO transmission;
determining a first number of codewords to be received in the first MIMO transmission based at least in part on the first service type;
receiving the first MIMO transmission; and
decoding one or more codewords received in the first MIMO transmission, the one or more codewords corresponding to the first number of codewords.

US Pat. No. 10,141,989

SYSTEM AND METHOD FOR QUANTIZATION OF ANGLES FOR BEAMFORMING FEEDBACK

Huawei Technologies Co., ...

1. A method for beamforming feedback comprising:receiving a sounding packet for a beamforming transmission;
performing planar rotation in accordance with the sounding packet to generate phi and psi angle values;
quantizing the phi and psi angle values such that a quantized resolution of the phi angle value is different from a quantized resolution of the psi angle value; and
feeding back the quantized phi and psi angle values.

US Pat. No. 10,141,988

METHOD AND FIRST RADIO NODE FOR COMMUNICATING DATA USING PRECODERS

Telefonaktiebolaget LM Er...

1. A method performed by a first radio node for communicating data with a second radio node in a wireless network, the method comprising:communicating, with the second radio node, a first data transmission using a first set of precoders;
communicating, with the second radio node, a precoder indicator that is based on quality of the communicated first data transmission;
identifying a second set of precoders within the first set, based on the communicated precoder indicator; and
communicating, with the second radio node, a second data transmission using the second set of precoders.

US Pat. No. 10,141,987

METHOD FOR FEEDING BACK REFERENCE SIGNAL INFORMATION IN MULTI-ANTENNA WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for feeding back reference signal information by a user equipment (UE) in wireless communication using a two-dimensional active antenna system (2D-AAS) including multiple antennas, the method comprising:receiving, from a base station (BS), a reference signal configuration including identifiers (IDs) of a plurality of reference signals included in a first reference signal set and a second reference signal set;
receiving, from the BS, the plurality of reference signals, where a plurality of precoding is applied respectively;
determining a reference signal that is not successfully received based on the reference signal configuration;
measuring reference signal received power (RSRP) for each of the plurality of reference signals; and
transmitting, to the BS, information on at least part of the first reference signal set and information on at least part of the second reference signal set based on the measured RSRP, and an ID of the determined reference signal, which is not successfully received,
wherein precoding for the UE is determined based on the information on the at least part of the first reference signal set, and
wherein interference information on the UE is determined based on the information on the at least part of the second reference signal set.

US Pat. No. 10,141,986

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING SIGNAL THROUGH BEAMFORMING IN COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A signal transmission and reception method of a terminal of a mobile communication system, the method comprising:receiving, from a base station, first information including a request associated with a beam of the terminal;
transmitting, to the base station, second information associated with the beam in response to the first information;
identifying at least one of a transmitting (Tx) beam or a receiving (Rx) beam of the terminal associated with the base station based on the first information and the second information; and
applying the identified at least one of the Tx beam or the Rx beam in response to the receiving of the first information or in response to the transmitting of the second information.

US Pat. No. 10,141,985

DETERMINING ACTUAL LOOP GAIN IN A DISTRIBUTED ANTENNA SYSTEM (DAS)

Corning Optical Communica...

1. A method for measuring actual loop gain in a wireless distribution system, comprising:disconnecting a downlink path into a first contact point and a second contact point;
providing at least one test signal having a first power level from the first contact point to at least one remote antenna unit (RAU) on the downlink path;
receiving at least one loopback test signal having a second power level from the second contact point;
determining a difference between the first power level of the at least one test signal at the first contact point and the second power level of the at least one loopback test signal at the second contact point;
determining an actual loop gain of the wireless distribution system based on the determined difference between the first power level and the second power level; and
recording the actual loop gain of the wireless distribution system in at least one storage medium.

US Pat. No. 10,141,982

RFID PROTOCOLS WITH NON-INTERACTING VARIANTS

RUIZHANG TECHNOLOGY LIMIT...

1. A method for operating an RFID reader, the method comprising:transmitting to a tag, a query command from a reader that is configured to store a first pair of keys including a first key and a second key, wherein the tag is configured to store a second pair of keys including a third key and a fourth key, and wherein the first pair of keys and the second pair of keys are used to create a sub-selection of a population of readers and tags;
transmitting to the tag, the first key from the reader;
receiving a first value from the tag if the first key from the reader matches the third key stored in the tag;
encrypting the first value using the second key stored in the reader to obtain a second value;
transmitting the second value to the tag that is configured to decrypt the second value using the fourth key to derive a challenge value;
receiving an identifier from the tag if a comparison of the first value to the challenge value indicates that the first value matches the challenge value.

US Pat. No. 10,141,981

METHODS AND APPARATUS FOR DETERMINING NEARFIELD LOCALIZATION USING PHASE AND RSSI DELIVERY

Texas Instruments Incorpo...

1. A receiver comprising:a receiver antenna to:
receive an electromagnetic signal; and
break the electromagnetic signal into an electric field signal and a magnetic field signal;
at least one processor coupled to the receiver antenna; and
a non-transitory computer readable storage medium storing a program for execution by the at least one processor, the program including instructions to:
determine an electric RSSI value of the electric field signal;
determine a magnetic RSSI value of the magnetic field signal;
determine an RSSI difference between the electric RSSI value and the magnetic RSSI value; and
determine a transmitter distance based on the RSSI difference.

US Pat. No. 10,141,979

APPARATUS AND METHOD FOR USING NEAR FIELD COMMUNICATION AND WIRELESS POWER TRANSMISSION

Samsung Electronics Co., ...

1. A power receiving apparatus comprising:a resonator configured to receive a power and to output the power;
a near field communication (NFC) transceiver configured to perform wireless communication using the power output by the resonator;
a wireless power transmission (WPT) receiver configured to supply a voltage using the power output by the resonator;
a connecting unit configured to selectively connect the resonator to either the NFC transceiver or the WPT receiver;
a mode selector configured to control the connecting unit to selectively connect the resonator to either the NFC transceiver or the WPT receiver based on the power output by the resonator; and
an antenna/matching circuit configured to be connected to the NFC transceiver,
wherein the NFC transceiver transmits transmission (TX) data to the antenna/matching circuit and receives reception (RX) data from the antenna/matching circuit.

US Pat. No. 10,141,978

DATA ENCODER FOR POWER LINE COMMUNICATIONS

TEXAS INSTRUMENTS INCORPO...

1. A power line communication (PLC) transmitter comprising:a forward error correction (FEC) encoder to receive a physical layer (PHY) frame containing payload data and to create an encoded output of FEC code words;
a fragmenter to receive an FEC code word block that includes two or more of the FEC code words and to partition the FEC code word block into fragments;
a fragment repetition encoder to receive the fragments and to copy each of the fragments a selected number of times; and
an interleaver to receive the copies of fragments and to interleave the copies of the plurality of fragments for transmission on a power line.

US Pat. No. 10,141,977

SPECIAL OPERATIONS CHANNEL IN VECTORED SYSTEMS

Lantiq Deutschland GmbH, ...

1. A method, comprising:assigning an identification to each line associated with a provider equipment; and
transmitting a special operation channel (SOC) signal over at least one of the lines, wherein SOC symbols of the SOC signal transmitted over each of the at least one of the lines are modified by the identification of that line.

US Pat. No. 10,141,976

CROSSTALK MITIGATION

1. A method, comprising:estimating crosstalk from at least one first communication line not operating according to a vector standard to at least one second communication line operating according to a vector standard;
wherein estimating crosstalk comprises transmitting a probe signal from a central office device on the at least one first communication line, wherein communication via the at least one first communication line is a multitone communication; wherein transmitting the probe signal comprises transmitting a predetermined data sequence modulated on a predefined set of tones of a multitone modulation;
adapting a vectoring based on the estimated crosstalk; and
in order to prevent data communication on the predefined set of tones, at least one of: adding artificial noise to the tones of the predefined set of tones, excluding the predefined set of tones from a supported set of tones, excluding the tones of the predefined set of tones by a mask parameter, and excluding the predefined set of tones from communication by modifying a communication device coupled to the at least one first communication line.

US Pat. No. 10,141,975

METHOD AND APPARATUS FOR COMMUNICATING NETWORK MANAGEMENT TRAFFIC OVER A NETWORK

1. A first waveguide system comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, the operations comprising:
receiving network management data associated with a communication device; and
transmitting, to a second waveguide system, first electromagnetic waves to a physical interface of a transmission medium that propagate along an outer surface of the transmission medium without requiring an electrical return path, wherein the first electromagnetic waves are guided by the transmission medium, wherein the first electromagnetic waves convey the network management data without conveying data traffic associated with the communication device, and wherein the transmitting the first electromagnetic waves is over a virtual private network connection associated with the communication device and is responsive to a request from a management server for an out of band link with the communication device.

US Pat. No. 10,141,973

ENDPOINT PROXIMITY PAIRING USING ACOUSTIC SPREAD SPECTRUM TOKEN EXCHANGE AND RANGING INFORMATION

Cisco Technology, Inc., ...

16. A method comprising:at a first endpoint device: generating an acoustic spread spectrum signal including a pilot sequence and a spread data sequence synchronized with the pilot sequence, wherein the spread data sequence encodes a token and a future transmit time at which the acoustic spread spectrum signal will be transmitted; and transmitting the acoustic spread spectrum signal at the future transmit time;
at a second endpoint device: receiving the acoustic spread spectrum signal; determining from the received acoustic spread spectrum signal a receive time, a second token corresponding to the token, and the future transmit time; computing a separation distance between the first endpoint device and the second endpoint device based on a difference between the receive time and the future transmit time; and sending to the network the second token and the computed separation distance;
receiving from the second endpoint device over the network the second token and the computed separation distance; and
pairing the first endpoint device with the second endpoint device when the second token matches the token and the computed separation distance is less than a threshold distance.

US Pat. No. 10,141,971

TRANSCEIVER CIRCUIT HAVING A SINGLE IMPEDANCE MATCHING NETWORK

Silicon Laboratories Inc....

1. A transceiver circuit, comprising:a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit;
a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, wherein the first and second amplifiers are directly connected to a shared node;
a single impedance matching network coupled to the antenna, directly connected to the shared node, and configured to transform an impedance of the antenna into a resistance at the shared node, wherein the single impedance matching network comprises a multiple stage inductor-capacitor (LC) network including at least a first stage and a second stage cascaded with the first stage, wherein the first stage and the second stage each comprise at least one variable capacitor having a capacitance that is reconfigurable; and
a control circuit coupled to the single impedance matching network, and configured to control the capacitance of the variable capacitors included within the first and second stages to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode:
wherein the first resistance is a resistance at an input of the first amplifier that achieves a maximum voltage gain at the input of the first amplifier;
wherein the second resistance is a resistance at an output of the second amplifier that achieves a maximum output power at the output of the second amplifier; and
wherein the second resistance is different from the first resistance.

US Pat. No. 10,141,970

TRANSCEIVER CIRCUIT AND METHODS FOR TUNING A COMMUNICATION SYSTEM AND FOR COMMUNICATION BETWEEN TRANSCEIVERS

ams AG, Unterpremstaette...

1. A transceiver circuit with a front-end and a back-end, the front-end comprising:a first terminal and a second terminal for coupling to a first capacitor and to a second capacitor, respectively;
a tunable first resistor coupled between the first terminal and a reference terminal; and
a tunable second resistor coupled between the second terminal and the reference terminal,
wherein the front-end is configured to, during a tuning mode of operation,
receive receiver signals at the first and the second terminal utilizing a first setting for the first and the second resistor, and
generate a receiver data packet based on the receiver signals, wherein the back-end is configured to, during the tuning mode,
check the receiver data packet for errors with respect to a defined tuning data packet,
if an error is found with the checking, set the first and the second resistor to a default setting, and
if no error is found with the checking, set the first and the second resistor to a second setting,
wherein the tuning mode of operation is separate from a normal mode of operation for the transceiver circuit, and
wherein, during the tuning mode of operation, the first resistor and the second resistor are set to the default setting or to the second setting for operating the transceiver circuit in the normal mode of operation.

US Pat. No. 10,141,969

MOBILE ELECTRONIC DEVICE PROTECTION CASE

1. A mobile electronic device protection case comprising:a plurality of corner protectors;
each of the plurality of corner protectors comprising a first clip support, a second clip support, a lateral support, and a protective coating;
the first clip support and the second clip support each comprise a first securing arm, a second securing arm and a clip base;
the first securing arm being adjacently connected to the clip base;
the second securing arm being adjacently connected to the clip base;
the first securing arm being oppositely positioned to the second securing arm along the clip base;
the clip base of the first clip support being adjacently connected to the lateral support;
the clip base of the second clip support being adjacently connected to the lateral support;
the clip base of the first clip support being oppositely positioned to the clip base of the second clip support about the lateral support;
the protective coating being superimposed on the first clip support, the second clip support, and the lateral support;
a plurality of supporting struts;
each of the plurality of corner protectors being connected to another corner protector of the plurality of corner protectors through a supporting strut of the plurality of supporting struts;
a plurality of elastic strut ties;
each supporting strut of the plurality of supporting struts comprising a first strut portion and a second strut portion; and
the first strut portion being connected to the second strut portion through an elastic strut tie of the plurality of elastic strut ties.

US Pat. No. 10,141,968

DEVICE FOR REFLECTING, DEFLECTING, AND/OR ABSORBING ELECTROMAGENTIC RADIATION EMITTED FROM AN ELECTRONIC DEVICE AND METHOD THEREFOR

ROWTAN TECHNOLOGIES, LLC,...

1. A device for deflecting radio frequency (RF) radiation away from a user of a mobile phone comprising:a metallic plate configured to be positioned between the mobile phone and at least one of a decorative or protective cover, the metallic plate positioned over a rear surface of the mobile phone, wherein the metallic plate is removable and non-permanently attached to the mobile phone and the at least one of a decorative or protective cover and wherein the metallic plate includes:
a copper plate; and
a powder coating formed over the copper plate.

US Pat. No. 10,141,966

UPDATE OF A TRUSTED NAME LIST

Apple Inc., Cupertino, C...

1. A method comprising:by a first electronic subscriber identity module (eSIM) server:
receiving, from a carrier server, a first request for an eSIM of a first type;
when the first eSIM server hosts eSIMs of the first type,
initiating an eSIM installation process with a device; and
when the first eSIM server does not host eSIMs of the first type:
sending, to a second eSIM server, a second request to reserve the eSIM on behalf of the device,
receiving, from the second eSIM server, a first identifier of the eSIM, and
sending, to the carrier server, the first identifier.

US Pat. No. 10,141,965

METHOD AND EQUIPMENT FOR CONFIGURING RADIO COMMUNICATIONS

Alcatel Lucent, Boulogne...

1. A method for configuring a radio communication channel between a first device and a second device wherein said first and second devices each include a physical data port and a radio communicator, said method comprising:providing a direct physical contact between the physical data ports of said first and second devices in order to establish communication between the physical data ports of said first and second devices;
exchanging configuration data through the direct physical contact; and
configuring a radio communication channel between the radio communicators of the first and second devices in accordance with the exchanged configuration data.

US Pat. No. 10,141,964

LOW-POWER CHANNEL SELECT FILTER USING TRANSRESISTANCE AMPLIFIER FOR DVB-H RECEIVERS

King Fahd University of P...

1. A channel select filter comprising:a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal;
two first resistors, each having one end connected to a respective differential input terminal of the FDTRA and having another end connected to a node;
two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node;
two first capacitors, each connected between ground and the node; and
two second capacitors, each connected between ground and a respective differential impedance terminal.

US Pat. No. 10,141,963

OPERATING METHOD OF RECEIVER, SOURCE DRIVER AND DISPLAY DRIVING CIRCUIT INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of operating a receiver, the method comprising:determining, by a controller of the receiver, whether a full initialization or a partial initialization of the receiver is needed;
adjusting, by the controller, alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode when the controller determines the full initialization is needed; and
adjusting, by the controller, the AC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed,
wherein the adjusting of the AC characteristics comprises adjusting an equalization coefficient of an equalizer that is located in the receiver or causing a clock data recovery circuit of the receiver to enter a lock state.

US Pat. No. 10,141,962

DEMODULATOR

Asahi Kasei Microdevices ...

1. A demodulator comprising:a filter configured to reduce a high frequency component of a downconverted signal downconverted from a modulated signal;
a demodulation section configured to output a demodulated signal demodulated from the downconverted signal, in which the high frequency component is reduced; and
a noise remover configured to reduce a noise in the demodulated signal demodulated from the downconverted signal by using:
an integration section configured to integrate the demodulated signal;
a zone detection section configured to detect a replacement target zone in the demodulated signal based on an integrated signal output by the integration section; and
a replacement section configured to replace a signal of the replacement target zone in the demodulated signal with a replacement target signal.

US Pat. No. 10,141,959

RADIO-FREQUENCY INTEGRATED CIRCUIT (RFIC) CHIP(S) FOR PROVIDING DISTRIBUTED ANTENNA SYSTEM FUNCTIONALITIES, AND RELATED COMPONENTS, SYSTEMS, AND METHODS

Corning Optical Communica...

1. A central unit for providing communications signals in a wireless communications system, comprising:a radio-frequency (RF) communications interface configured to:
receive downlink RF communication signals at a RF communications frequency for a RF communications service; and
provide uplink RF communication signals at the RF communications frequency for the RF communications service;
at least one RF integrated circuit (IC) (RFIC) chip comprising at least one of:
a first frequency conversion circuitry configured to shift a frequency of the downlink RF communication signals to an intermediate frequency (IF) having a different frequency than the RF communications frequency, to provide downlink IF communications signals; and
a second frequency conversion circuitry configured to shift the frequency of uplink IF communication signals to the RF communications frequency to provide the uplink RF communications signals, wherein
the downlink RF communication signals are comprised of MIMO downlink RF communication signals,
the uplink RF communications signals are comprised of MIMO uplink RF communication signals,
the downlink IF communications signals are comprised of MIMO downlink IF communication signals,
the uplink IF communication signals are comprised of MIMO uplink IF communications signals; and
the RF communications interface is further configured to:
receive second MIMO downlink RF communication signals at the RF communications frequency for the RF communications service; and
receive second MIMO uplink RF communication signals at the RF communications frequency for the RF communications service, the central unit further comprising
at least one second RFIC chip comprising at least one of:
a third frequency conversion circuitry configured to shift the frequency of the second MIMO downlink RF communication signals to a second IF having a different frequency than the RF communications frequency, to provide second MIMO downlink IF communications signals; and
a fourth frequency conversion circuitry configured to shift the frequency of second MIMO uplink IF communication signals to the RF communications frequency to provide the second MIMO uplink RF communications signals.

US Pat. No. 10,141,956

DEVICE FOR BI-DIRECTIONAL AND MULTI-BAND RF COMMUNICATION OVER SINGLE RESONANT TRANSMISSION LINE AND METHOD OF ITS REALIZATION

14. A duplexing system comprising:a duplexer;
an antenna configured to transmit and receive electromagnetic signals;
a transmitter configured to couple electromagnetic signals to said antenna for transmission;
a receiver configured to receive electromagnetic signals;
wherein the duplexer comprises a first transmission line and a second transmission line, wherein a portion of said first transmission line is placed in a first proximity to a portion of said second transmission line, the first proximity causing electromagnetic coupling between said first transmission line and said second transmission line;
wherein a first end of said first transmission line is connected to a first duplexer port coupled to said antenna and a second end of said first transmission line is connected to a second duplexer port coupled to said transmitter; and
wherein both ends of said second transmission line are connected to loads;
wherein said second transmission line comprises a high directivity coupler comprising an interior transmission line connected at a first end to a third duplexer port coupled to the receiver and at a second end to ground;
wherein a portion of said interior transmission line is in a second proximity to a portion of said second transmission line, the second proximity causing electromagnetic coupling between said second transmission line and said interior transmission line.

US Pat. No. 10,141,953

LOW-DENSITY PARITY-CHECK APPARATUS AND MATRIX TRAPPING SET BREAKING METHOD

VIA Technologies, Inc., ...

1. A low-density parity-check (LDPC) apparatus, configured to perform an iteration operation to decode an original codeword, comprising:a log likelihood ratio (LLR) mapping circuit, configured to convert the original codeword into a LLR vector according to a mapping relationship;
a variable node (VN) calculation circuit, coupled to the LLR mapping circuit for receiving the LLR vector, and configured to calculate at least one original variable-node to check-node (V2C) information from at least one VN to at least one check node (CN) by using the LLR vector and at least one check-node to variable-node (C2V) information;
an adjustment circuit, coupled to the VN calculation circuit to receive the original V2C information, and configured to adjust the original V2C information to obtain at least one adjusted V2C information according to at least one factor, wherein the factor is multiplied to the original V2C information;
a check node calculation circuit, coupled to the adjustment circuit to receive the adjusted V2C information, and configured to calculate the at least one C2V information from the CN to the VN by using the adjusted V2C information, and providing the at least one C2V information to the VN calculation circuit; and
a controller, coupled to the adjustment circuit, and configured to determine whether to adjust the factor, wherein when the iteration operation falls into a matrix trapping set, the controller decides to adjust the factor to break the iteration operation away from the matrix trapping set.

US Pat. No. 10,141,952

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A memory system comprising:a memory device; and
a controller including an ECC circuit and coupled with the memory device, wherein the controller is configured to
receive a message in response to a request from a host,
generate a message matrix by the ECC circuit into at least one buffer of the ECC circuit, including predetermined row codes and predetermined column codes symmetrical to the predetermined row codes in accordance with the received message, wherein the message matrix includes a first triangular matrix and a second triangular matrix symmetrical to the first triangular matrix,
encode the message matrix by the ECC circuit using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BCH) code with a symmetrical structure, and
store the encoded message by the ECC circuit into the memory device, and decode the encoded message by the ECC circuit using a block-wise concatenated BCH code with a symmetrical structure.

US Pat. No. 10,141,951

TRANSMITTER AND SHORTENING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


where ?s(j) represents an index of a bit group area padded in the j-th order among the plurality of bit group areas, and Ninfo group represents a number of the plurality of bit group areas.

US Pat. No. 10,141,949

MODULAR SERIALIZER AND DESERIALIZER

Cavium, LLC, Santa Clara...

1. A deserializer circuit, comprising:an input buffer configured to receive a serial data signal; and
an array of cells, each cell comprising an input flip-flop and an output flip-flop, the array of cells including:
a bottom row of cells configured to receive a plurality of partial words in parallel from the input buffer to the input flip-flops of the bottom row of cells, the plurality of partial words corresponding to the serial data signal;
at least one intermediary row of cells configured to 1) receive the plurality of partial words from a preceding row of cells, and 2) transfer a subset of the plurality of partial words to a successive row of cells of the array of cells; and
a top row of cells configured to receive one of the plurality of partial words from a preceding row of cells of the array of cells;
the array of cells outputting a word in parallel via the output flip-flops, the word corresponding to the plurality of partial words.

US Pat. No. 10,141,947

SIGNAL GENERATING DEVICE

NIPPON TELEGRAPH AND TELE...

1. A signal generating device comprising:a digital signal processing unit;
two digital-to-analog converters (DACs); and
an analog multiplexer that alternatingly switches analog signals outputted from the two DACs with a frequency fc for outputting as analog signals, wherein
the digital signal processing unit includes:
when a signal, among desired output signals having an upper limit frequency of less than fc, made of a component having an absolute value of a frequency being substantially fc/2 or less is assumed as a low-frequency signal, and
when, for a positive frequency component and a negative frequency component which are made of a component having an absolute value of a frequency being substantially fc/2 or more among the desired output signals, a signal in which the positive frequency component is shifted by ?fc on a frequency axis and a signal in which the negative frequency component is shifted by +fc on the frequency axis are assumed as a folded signal,
means for generating a first signal that is equal to a signal obtained by multiplying the folded signal by a constant and adding a resultant to the low-frequency signal; and
means for generating a second signal that is equal to a signal obtained by multiplying the folded signal by the constant and subtracting a resultant from the low-frequency signal, and wherein:
a digital signal corresponding to the first signal generated in the digital signal processing unit is inputted into one of the two DACs; and
a digital signal corresponding to the second signal generated in the digital signal processing unit is inputted into the other one of the two DACs.

US Pat. No. 10,141,946

MULTI-PATH ANALOG SYSTEM WITH MULTI-MODE HIGH-PASS FILTER

Cirrus Logic, Inc., Aust...

1. A system comprising:an input for receiving an input signal;
an output for generating an output signal;
a capacitor coupled between the input and the output;
a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance; and
control circuitry configured to:
determine a difference between the input signal and the output signal; and
switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

US Pat. No. 10,141,941

DIFFERENTIAL PLL WITH CHARGE PUMP CHOPPING

HUAWEI TECHNOLOGIES CO., ...

1. A charge pump circuit comprising:an intake chopper circuit configured to switch input signals received at the first and second inputs of the intake chopper circuit between first and second outputs of the intake chopper circuit at a chopping frequency, wherein successive input signals at the first input are provided alternatively at the first and second outputs in successive cycles of the chopping frequency and successive input signals at the second input are provided alternatively at the second and first outputs in successive cycles of the chopping frequency;
a differential charge pump configured to receive the signals from the first and second outputs of the intake chopper circuit and produce corresponding first and second charge pumped signals; and
an output chopper circuit configured to receive the first and second charge pumped signals at respective first and second inputs, provide the first charge pumped signals alternatively at first and second outputs in successive cycles of the chopping frequency, and provide the second charge pumped signals alternatively at the second and first outputs in successive cycles of the chopping frequency.

US Pat. No. 10,141,938

STACKED COLUMNAR INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A semiconductor device, comprising:a first integrated circuit (IC) die including a first column of cascade-coupled resource blocks;
a second IC die including a second column of cascade-coupled resource blocks, where an active side of the second IC die is mounted to an active side of the first IC die; and
a plurality of electrical connections between the active side of the first IC and the active side of the second IC, the plurality of electrical connections including at least one electrical connection between the first column of cascade-coupled resource blocks and the second column of cascade-coupled resource blocks.

US Pat. No. 10,141,936

PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECTIONS

Altera Corporation, San ...

1. An integrated circuit, comprising:a selection circuit configured to receive first and second signals;
control circuitry coupled to the selection circuit and configured to receive a clock signal and to control the selection circuit to generate a double data rate signal based on the clock signal by serializing the first and second signals, wherein the selection circuit is configured to generate the double data rate signal in a first mode of operation and to generate a single data rate signal in a second mode of operation; and
a storage element coupled to the selection circuit and configured to store the double data rate signal.

US Pat. No. 10,141,935

PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM

Intel Corporation, Santa...

1. A memory device with on-die termination (ODT) comprising:a hardware interface to couple to a memory bus shared by multiple memory devices;
an ODT circuit to selectively apply ODT to the hardware interface for a memory access operation in accordance with an ODT latency setting in response to receipt of a memory access command;
a first addressable register to store a dynamically programmable first ODT latency setting to control ODT turn on timing or turn off timing for a Read operation; and
a second addressable register separate from the first addressable register to store a dynamically programmable second ODT latency setting to control ODT turn on or turn off timing or turn off timing for a Write operation.

US Pat. No. 10,141,933

SELF-REPAIRING DIGITAL DEVICE WITH REAL-TIME CIRCUIT SWITCHING INSPIRED BY ATTRACTOR-CONVERSION CHARACTERISTICS OF A CANCER CELL

KOREA ADVANCED INSTITUTE ...

1. An electric device, comprising:a first switch-unit providing a first internal circuit signal;
a first delay circuit unit outputting a second internal circuit signal which is generated by delaying the first internal circuit signal;
a first AND logic outputting a first repair-signal generated by a logical AND operation between the first internal circuit signal and the second internal circuit signal;
a first OR logic outputting a second repair-signal generated by a logical OR operation between the first internal circuit signal and the second internal circuit signal; and
a second switch-unit selecting one of the first repair-signal and the second repair-signal according to a third internal circuit signal generated by an operation including a logical AND operation between the first repair-signal and the second repair-signal and providing the selected one as an output signal through an output terminal;
wherein, the first switch-unit chooses one of the first repair-signal and the second repair-signal according to the output signal and provides the chosen one as first internal circuit signal.

US Pat. No. 10,141,932

WIRING WITH EXTERNAL TERMINAL

Micron Technology, Inc., ...

1. An apparatus comprising a semiconductor die, wherein the semiconductor die comprises:an area including a first side and a second side opposite to the first side;
a first via disposed on the first side of the area;
a second via disposed on the second side of the area;
a first pad disposed in a pad formation area and configured to receive a first voltage;
a first distribution conductor extending from the first pad to the first and second vias and configured to couple the first pad to the first and second vias;
a first conductive line coupled to the first via;
a second conductive line coupled to the second via;
a third conductive line configured to be coupled to the first conductive line;
a fourth conductive line configured to be coupled to the second conductive line;
a first switch disposed between the first and third conductive lines and configured to couple the first conductive line to the third conductive line; and
a second switch disposed between the second and fourth conductive lines and configured to couple the second conductive line to the fourth conductive line.

US Pat. No. 10,141,931

MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND SLEW RATE CALIBRATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a main driver configured to provide an output signal to a host based on a driving signal; and
a pre-driver configured to provide the main driver with the driving signal in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host.

US Pat. No. 10,141,930

THREE STATE LATCH

Nvidia Corporation, Sant...

1. An electronic circuit comprising a single latch having three stable states, said latch comprising three inputs and three outputs for indicating said three stable states, and wherein said latch is configured wherein all said three outputs reflect a change at any one of said inputs in not more than two gate delays.

US Pat. No. 10,141,926

ULTRA-LOW POWER CROSS-POINT ELECTRONIC SWITCH APPARATUS AND METHOD

Ciena Corporation, Hanov...

1. An electrical switch circuit adapted to switch digital, high-speed signals with low power, the electrical switch circuit comprising:a plurality of input buffers comprising a first set of digital inverters and each is coupled to an associated input transmission line of a plurality of input transmission lines;
a plurality of output buffers comprising a second set of digital inverters and each is coupled to an associated output transmission line of a plurality of output transmission lines; and
a plurality of switches each coupled to an associated input transmission line and an associated output transmission line and between the first set of digital inverters and the second set of digital inverters, wherein each of the input transmission line, the output transmission line, and the plurality of switches are in a single line configuration, wherein the plurality of input buffers, the plurality of output buffers, and the plurality of switches are arranged in a tile and comprise an N×N cross-point switch, wherein an M×M cross point switch, M>N, is formed by a plurality of tiles, and wherein each tile is sized smaller than a bit period length of the digital, high-speed signals.

US Pat. No. 10,141,923

SYSTEM AND METHOD FOR ELIMINATING GATE VOLTAGE OSCILLATION IN PARALLELED POWER SEMICONDUCTOR SWITCHES

1. A damping circuit for a semiconductor device, comprising:a switch having an input terminal and an output terminal for driving voltage;
a plurality of resistors connected to the output terminal of the switch including a first resistor and a second resistor;
a plurality of inductors that include a first inductor and a second inductor, an input of the first inductor connected to the first resistor and an input of the second inductor connected to the second resistor;
a plurality of capacitors that include a first capacitor and a second capacitor and configured to provide a capacitance for electrical storage, an input of the first capacitor connected to an output of the first inductor at a first gate terminal and an input of the second capacitor connected to an output of the second inductor at a second gate terminal;
a plurality of power semiconductor switches including a first power semiconductor switch and a second power semiconductor switch, the first power semiconductor switch being connected to the output of the first inductor at the first gate terminal and the second semiconductor switch being connected to the output of the second inductor at the second gate terminal;
a plurality of gate terminal switches including a first gate terminal switch and a second gate terminal switch; and
a plurality of gate terminal resistors including a first gate terminal resistor connected in series with the first gate terminal switch and a second gate terminal resistor connected in series with the second gate terminal switch, the first gate teiininal resistor and the first gate terminal switch being connected in between the first power semiconductor switch at the first gate terminal and a ground, the second gate terminal resistor and the second gate terminal switch being connected in between the second power semiconductor switch at the second gate terminal and the ground.

US Pat. No. 10,141,921

SIGNAL GENERATOR USING MULTI-SAMPLING AND EDGE COMBINING AND ASSOCIATED SIGNAL GENERATING METHOD

MEDIATEK INC., Hsin-Chu ...

1. A signal generator for generating an output signal having a waveform with transition edges according to an oscillating signal having a waveform, the signal generator comprising:a plurality of edge sampling circuits, each configured to receive the oscillating signal and a bias voltage, sample the waveform of the oscillating signal using the bias voltage to generate at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and output a sampled signal using the at least one of the rising edge and the falling edge; and
an edge combining circuit, configured to combine a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal;
wherein the edge sampling circuits comprise at least a first edge sampling circuit and a second edge sampling circuit, and the signal generator further comprises:
a voltage generator, configured to generate a first bias voltage to the first edge sampling circuit and generate a second bias voltage to the second edge sampling circuit;
wherein the first bias voltage is different from the second bias voltage, the first edge sampling circuit obtains a first set of a rising edge and a falling edge in a cycle of the oscillating signal according to the first bias voltage, the second edge sampling circuit obtains a second set of a rising edge and a falling edge in the cycle of the oscillating signal according to the second bias voltage, and the first set of the rising edge and the falling edge is different from the second set of the rising edge and the falling edge.

US Pat. No. 10,141,920

CLOCK SIGNAL CONTROLLER

INTERNATIONAL BUSINESS MA...

1. A clock signal controller, comprising:a first transistor being connected to a working level and a first connecting point, and a gate of the first transistor being connected to a first clock signal input end;
a second transistor being connected to a first connecting point and to a reference level, and a gate of the second transistor being connected to the first clock signal input end;
a third transistor being connected to the working level and to a second connecting point, and a gate of the third transistor being connected to a second clock signal input end; and
a fourth transistor being connected to the working level and the second connecting point, and a gate of the fourth transistor being connected to the second clock signal input end;
wherein the first connecting point and the second connecting point are connected to a first clock signal output end.

US Pat. No. 10,141,918

APPARATUS AND METHOD FOR SIGNAL PROCESSING BY CONVERTING AMPLIFIED DIFFERENCE SIGNAL

Samsung Electronics Co., ...

1. A signal processing apparatus, comprising:a difference signal acquirer configured to obtain a difference signal reflecting changes in an input signal at preset time intervals based on a reference signal;
a signal amplifier configured to amplify the difference signal; and
a signal restorer configured to generate an output signal reflecting the input signal by converting the amplified difference signal to a digital signal and incrementally summing the digital signal over the time intervals, wherein, for the incrementally summing over the time intervals, the signal restorer is configured to sum a digital signal of a current time to a summed digital signal of a previous time.

US Pat. No. 10,141,917

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

Lattice Semiconductor Cor...

1. A programmable logic device (PLD), comprising:a plurality of programmable logic blocks (PLBs); and
at least first and second logic cells within at least one of the plurality of PLBs, each logic cell comprising a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT, wherein:
the associated mode logic is configured to use a single physical output port to provide a logic cell output signal from its respective logic cell corresponding to an operational mode selected from a logic function operational mode, a ripple arithmetic operational mode, and an extended logic function operational mode;
when the selected operational mode for the first logic cell comprises the logic function operational mode, the associated mode logic for the first logic cell is configured to provide the LUT output signal of the first logic cell as the logic cell output signal on the single physical output port; and
when the selected operational mode for the first logic cell comprises the extended logic function operational mode, the associated mode logic for the first logic cell is configured to:
multiplex the LUT output signal of the first logic cell and the LUT output signal of the second logic cell, and
provide the multiplexed signal as a first logic cell output signal on the single physical output port of the first logic cell and to an input of the second logic cell.

US Pat. No. 10,141,916

HIGH-SPEED FLIP-FLOP SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor circuit comprising:a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;
a second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal; and
a third logic gate that receives inputs of a second input signal and a scan-enable signal and performs a third logical operation on the second input signal and the scan-enable signal to generate the first input signal.

US Pat. No. 10,141,915

SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT

INTERNATIONAL BUSINESS MA...

1. A method of operating an integrated circuit having a resonant clock distribution network, the method comprising:generating a distributed clock signal within the resonant clock distribution network by driving the resonant clock distribution network with a plurality of clock driver circuits that receive a clock input from a global clock signal and have outputs connected to corresponding locations within sectors of the resonant clock distribution network;
controlling pulse widths of individual ones of the plurality of clock drivers according to a plurality of control signals provided to corresponding ones of the plurality of clock driver circuits, wherein the pulse widths of the individual clock drivers differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network
from a first control logic, selecting an operating mode or frequency of the resonant clock distribution network; and
from a second control logic, generating the plurality of control signals such that, responsive to the selecting having selected a new operating mode or a new frequency, the pulse widths of the individual clock driver circuits are set to new pulse width values, wherein the individual clock driver circuits are operated at the new pulse width values, and wherein the new pulse width values differ for at least some of the sectors.

US Pat. No. 10,141,913

MULTIPLEXER, TRANSMISSION APPARATUS, AND RECEPTION APPARATUS

Murata Manufacturing Co.,...

1. A multiplexer that transmits and receives a plurality of high-frequency signals via an antenna element, the multiplexer comprising:a plurality of elastic wave filters that have pass bands different from one another; and
a common terminal that is connected to the antenna element by a connection path, a first inductance element being connected between the connection path and a reference terminal; wherein
each of the plurality of elastic wave filters includes at least one of a series resonator connected between an input terminal and an output terminal of each of the plurality of elastic wave filters, and a parallel resonator connected between the reference terminal and a connection path connecting the input terminal and the output terminal to each other;
a terminal closer to the antenna element among the input terminal and the output terminal of one elastic wave filter among the plurality of elastic wave filters is connected to the parallel resonator and is connected to the common terminal with a second inductance element interposed therebetween; and
a terminal closer to the antenna element among the input terminal and the output terminal of each of other elastic wave filters other than the one elastic wave filter among the plurality of elastic wave filters is connected to the common terminal and the series resonator.

US Pat. No. 10,141,912

RF RESONATORS AND FILTERS

ZHUHAI CRYSTAL RESONANCE ...

1. A filter package comprising an array of piezoelectric films sandwiched between an array of upper electrodes and lower electrodes:the individual piezoelectric films and the upper electrodes being separated by a passivation material; the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the filter package further comprising a silicon wafer of known thickness attached over the upper electrodes with an array of upper cavities between the silicon wafer and a silicon cover; each upper cavity aligned with a piezoelectric film in the array of piezoelectric films, the upper cavities having side walls comprising the passivation material.

US Pat. No. 10,141,911

HIGH-FREQUENCY MODULE AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...

1. A high-frequency module comprising:a plurality of filters including first and second filters and including respective pass bands which are different from one another;
a connection circuit that commonly connects a plurality of paths in which the plurality of filters are respectively provided; and
a low noise amplifier that is connected to the connection circuit; wherein
the connection circuit is connected between the plurality of filters and the low noise amplifier;
in paths in which the first and second filters are respectively provided among the plurality of paths, the respective filters and the connection circuit are connected without connecting impedance elements;
each of the first and second filters has a respective output impedance located in a matching region between a noise figure matching impedance at which a noise figure of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in the respective pass band of each of the first and second filters on a Smith chart.

US Pat. No. 10,141,906

HIGH Q QUARTZ-BASED MEMS RESONATORS AND METHOD OF FABRICATING SAME

HRL Laboratories, LLC, M...

16. A method of fabricating a resonator, comprising:providing a quartz application-specific integrated circuit (ASIC) wafer comprising a first bond pad and a second bond pad;
providing a quartz resonator comprising a first side, a second side opposite said first side, a via, a first electrode, a second electrode and a third electrode, wherein said first electrode is on said first side and overlaps said via, wherein said second electrode is on said second side, extends into said via and is in electrical contact with said first electrode, wherein said second electrode is in electrical contact with said first bond pad, and wherein said third electrode is on said second side and is in electrical contact with said second bond pad, wherein said via is formed by a dry etching process; and
providing a first mesa located on said first side, said first mesa being defined by forming a first groove into said first side so that said first mesa is at least partially surrounded by material having the same thickness relative to said first groove as said first mesa but positioned laterally of said first mesa and separated therefrom by said first groove;
providing a second mesa located on said second side, said second mesa being defined by forming a second groove into said second side so that said second mesa is at least partially surrounded by material having the same thickness relative to said second groove as said second mesa but positioned laterally of said second mesa and separated therefrom by said first groove, the first and second groves increasing the quality factor (Q) of the resonator being fabricated; and
providing a first electrode on said first mesa and providing a second electrode on said second mesa, the first electrode filling a portion of said first groove.

US Pat. No. 10,141,901

FLIP-CHIP AMPLIFIER WITH TERMINATION CIRCUIT

Skyworks Solutions, Inc.,...

1. A power amplifier module comprising:a flip-chip power amplifier die including a power amplifier configured to amplify a radio frequency signal;
a first circuit element included in a matching network that is configured to provide impedance matching at a fundamental frequency of the radio frequency signal; and
a second circuit element included in a harmonic termination circuit, the second circuit element and the first circuit element being electrically connected to an output of the power amplifier by way of different bumps.

US Pat. No. 10,141,899

BROADBAND RADIO FREQUENCY POWER AMPLIFIERS, AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A packaged amplifier device having a bandwidth defined by a range of frequencies between a low cutoff frequency and an upper cutoff frequency, the amplifier device comprising:an input lead configured to receive an input radio frequency (RF) signal;
an output lead configured to produce an amplified RF signal;
a reference node;
a transistor die that includes
a first node,
a second node,
a transistor having a gate, a first current conducting terminal coupled to the output lead, and a second current conducting terminal coupled to the reference node,
a first integrated capacitance having a first terminal coupled to the first node, and a second terminal coupled to the reference node,
a first inductance having a first terminal coupled to the first node, and a second terminal coupled to the second node, and
a second integrated capacitance having a first terminal coupled to the second node, and a second terminal coupled to the reference node; and
a second inductance having a first terminal coupled to the input lead and a second terminal coupled to the first node of the transistor die,
wherein the first inductance, the first integrated capacitance, the second inductance, and the second integrated capacitance form a multiple pole filter of an input impedance matching circuit that is configured to filter the input RF signal to produce a filtered RF signal at the gate of the transistor, and wherein a first pole of the multiple pole filter is positioned at a first frequency within the bandwidth, and a second pole of the multiple pole filter is positioned at a second frequency outside the bandwidth.

US Pat. No. 10,141,898

HIGH CURRENT LOW-COST DC COUPLED DAC FOLLOWER LOW PASS FILTER HEADPHONE AMPLIFIER

TYMPHANY HK LIMITED, Hon...

1. A digital-to-analog converter (DAC) circuit comprising:a pair of output stages, each output stage comprising:
a DAC configured to convert a digital audio signal into an analog audio signal;
an low-pass filter circuit including an operational amplifier in signal communication with the DAC, the operation amplifier configured to generate a filtered analog signal based on the analog audio signal; and
an amplifier network in signal communication with the operational amplifier to generate an amplified audio signal based on the filtered analog signal,
wherein the operational amplifier includes a feedback circuit path including a first node connected to the output of the amplifier network and a second node connected to the input of the operational amplifier,
wherein the amplifier network is electrically nested in the feedback circuit path, and
wherein each output stage includes a DC servo circuit configured to equalize an impedance of the operational amplifier.

US Pat. No. 10,141,897

SOURCE FOLLOWER

SILICON INTERGRATED SYSTE...

1. A source follower, comprising:a first transistor having a first terminal, a second terminal and a control terminal, with the first terminal of the first transistor configured to receive a first base voltage, the second terminal of the first transistor electrically connected to a first output terminal, the control terminal of the first transistor configured to receive a first control voltage, and the first transistor configured to generate a first current according to the first control voltage;
a first output module electrically connected to the first output terminal and providing an output voltage to the first output terminal according to an input voltage signal and the first current;
a second transistor having a first terminal, a second terminal and a control terminal, with the first terminal of the second transistor configured to receive the first base voltage, the second terminal of the second transistor electrically connected to a second output terminal, the control terminal of the second transistor configured to receive the first control voltage and the second transistor configured to generate a second current according to the first control voltage;
a second output module electrically connected to the second output terminal and providing a common-mode voltage to the second output terminal according to a second base voltage and the second current; and
a feedback module electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node in the second output module, the feedback module configured to regulate a voltage level of the reference node and a voltage level of the first control voltage according to a reference voltage, wherein the feedback module comprising:
an amplifier, with a first input terminal of the amplifier configured to receive the reference voltage, a second input terminal of the amplifier electrically connected to the reference node, an output terminal of the amplifier electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, and the amplifier providing the first control voltage through the output terminal.

US Pat. No. 10,141,896

CURVE FITTING CIRCUIT, ANALOG PREDISTORTER, AND RADIO FREQUENCY SIGNAL TRANSMITTER

Huawei Technologies Co., ...

1. A curve fitting circuit, comprising:n segmentation processing circuits, wherein n is greater than or equal to 2; and
q first adder circuits, wherein q is a natural number;
wherein each segmentation processing circuit of the n segmentation processing circuits is configured to:
receive an input signal;
intercept a part of the input signal according to a preset rule;
generate a to-be-processed signal according to the intercepted part; and
generate q output signals according to the to-be-processed signal using a polynomial fitting method, wherein parts of the input signal intercepted by different segmentation processing circuits are not exactly the same; and
wherein each first adder circuit is configured to:
receive one signal in the q output signals of each segmentation processing circuit; and
obtain one output signal of the curve fitting circuit according to a sum of received n signals, wherein different first adder circuits receive different output signals in q output signals of a same segmentation processing circuit.

US Pat. No. 10,141,894

RADIO FREQUENCY (RF) AMPLIFIER

QUALCOMM Incorporated, S...

1. A circuit, comprising:a first amplifier path comprising a first amplifier, MA;
a second amplifier path comprising a cascode device and a second amplifier, MB;
a node defined by a source of the cascode device and a drain of the second amplifier, MB;
a capacitance coupled between the node and a source of the second amplifier, MB; and
an input configured to receive a radio frequency signal, the input being coupled to a gate of the first amplifier, MA, and to a gate of the second amplifier, MB.

US Pat. No. 10,141,889

SEMICONDUCTOR INTEGRATED CIRCUIT, SENSOR READER, AND SENSOR READOUT METHOD

Mitsubishi Electric Corpo...

1. A semiconductor integrated circuit comprising:a plurality of first amplifiers, each first amplifier of the plurality of first amplifiers amplifying a sensor signal input from a corresponding sensor element of a plurality of sensor elements;
a plurality of first switches, each first switch of the plurality of first switches connecting to an output of a first amplifier to perform switching between conducting and blocking of the output;
a second switch to perform switching of a sensor amplification signal output via a first switch from the first amplifier, the switching of the second switch being between closing to conduct to, and opening to block, an external output terminal; and
a control circuit to cause:
when the second switch is closed, operating of the first switches so that sensor amplification signals output from the plurality of first amplifiers are output sequentially one at a time; and
when the second switch is open, setting a bias current and a gain of at least one first amplifier of the plurality of first amplifiers to second setting values that are lower than first setting values, the first setting values being the bias current and the gain when the second switch is closed.

US Pat. No. 10,141,887

OSCILLATOR FOR DETECTING TEMPERATURE OF ATMOSPHERE

NIHON DEMPA KOGYO CO., LT...

1. An oscillator that detects a temperature of an atmosphere where a crystal resonator providing an oscillation output is placed using a temperature detector to stabilize the temperature by controlling a temperature of a heater based on a temperature detection value, the oscillator comprising:a buffer amplifier interposed in a signal path of a control signal generated based on the temperature detection value;
a heater constituted of a transistor having a collector and an emitter positioned between a power source unit and a ground, and a base connected to an output port of the buffer amplifier; and
a first differential amplifier disposed to adjust a gain of the buffer amplifier so as to cancel a voltage fluctuation of the power source unit, the first differential amplifier amplifying a difference between a voltage corresponding to a voltage of the power source unit and a preliminarily set voltage to input to a gain adjustment port of the buffer amplifier.

US Pat. No. 10,141,886

METHOD AND APPARATUS FOR EXTRACTING ELECTRICAL ENERGY FROM PHOTOVOLTAIC MODULE

Techinvest-Eco, Limited L...

1. An apparatus for electrical energy take-off from a photovoltaic module (PVM), the apparatus comprising:one of
a DC/AC inverter having a maximum power not less than a nominal power of the PVM, and configured to connect an output of the DC/AC inverter to a local AC electrical power distribution system, or
a DC/DC converter having a maximum power not less than the nominal power of the PVM, and configured to connect to an input of an energy storage system;
a capacitor connected in parallel between the PVM and one of an input of the DC/AC inverter or an input of the DC/DC converter;
a means for voltage measurement on the capacitor; and
a control module connected to one of the DC/AC inverter or the DC/DC converter and further connected to the means for voltage measurement on the capacitor,
wherein the DC/AC inverter and the DC/DC converter are configured to switch between at least three power levels,
wherein the means for voltage measurement is configured to supply data to the control module regarding at least three predetermined fixed values of the capacitor voltage, the control module is configured to switch the at least three power levels of one of the DC/AC inverter or the DC/DC converter depending on the capacitor voltage,
wherein an internal resistance of the capacitor is at least half of an internal resistance of the PVM at a maximum power point (MPP) of the PVM, and
wherein capacity of the capacitor is defined as follows:
C?(k*PB)/(UB2?U12),
where
C is capacitance of the capacitor in Farads (F);
PB is maximal power of PVM under its maximal insolation in Watts (W);
UB is voltage of PVM at the maximum power point under maximal insolation in Volts (V);
U1 is an intermediate fixed voltage at the maximum power point under insolation that is less than maximal insolation closest to the UB in Volts (V); and
k is a factor with an absolute value of 0.3-0.5 seconds (sec).

US Pat. No. 10,141,885

FLOATING SOLAR PANEL SYSTEMS

1. A floating solar system, comprising:a border pontoon adapted to float on water defining a closed peripheral shape surrounding an interior space;
an array of interconnected photovoltaic panels distributed within the peripheral shape and structurally supported by support cables extending across between sides of the pontoon so as to span the interior space, each photovoltaic panel having a flotation device secured thereto so that the array is at least partially buoyant, the photovoltaic panels being electrically connected; and
a stabilizing skirt downwardly-depending from the border pontoon to surround a column of water underneath the array of photovoltaic panels, the skirt being weighted to remain substantially vertical in the water and forming a barrier around the column of water so as to create a more stable volume of water within the peripheral shape than outside of the border pontoon, wherein the skirt has a depth that is between about 10-40% of the width of the closed peripheral shape.

US Pat. No. 10,141,884

COOLING FAN FILTERING

Dell Products L.P., Roun...

5. An apparatus for cooling a system component of an information handling system, the apparatus comprising:at least one cooling fan configured to cool the system component; and
a controller coupled to the at least one cooling fan to apply a filtered first PWM control signal to the at least one cooling fan,
wherein the controller is configured to perform steps for controlling the at least one cooling fan comprising:
generating a first pulse width modulation (PWM) control signal for controlling the at least one cooling fan; and
filtering the first PWM control signal to generate the filtered first PWM control signal, the filtering comprising dampening the first PWM control signal such that a rate of change of the filtered first PWM control signal is decreased as a target process value is approached,
wherein the step of dampening the first PWM control signal comprises generating a new PWM control signal by adding the filtered first PWM control signal to a product of a gain parameter multiplied by a second parameter proportional to a difference between the first PWM control signal and the filtered first PWM control signal, and wherein the controller is further configured to apply the new PWM control signal to the at least one cooling fan.

US Pat. No. 10,141,881

APPARATUS FOR CONTROLLING INVERTER

LSIS CO., LTD., Anyang-s...

1. An apparatus for controlling an inverter contained in an inverter system configured to drive a motor, comprising:a slip frequency decision unit configured to determine a first slip frequency to be used for compensation of a frequency of a first reference voltage, not only using a first reference voltage (including an amplitude and frequency) of the first reference voltage applied to the inverter, but also using an output current of the motor or a rotor speed of the motor; and
a reference voltage generation unit configured to determine not only a frequency of a second reference voltage achieved by compensation of the first slip frequency, but also an amplitude of the second reference voltage corresponding to the frequency of the second reference voltage, and apply the second reference voltage to the inverter,
wherein the slip frequency decision unit includes:
a closed-loop controller configured to determine a second slip frequency using the rotor speed of the motor; and
an open-loop controller configured to determine a third slip frequency, using an output current of the motor, the amplitude and frequency of the first reference voltage, and a nominal value of the motor.

US Pat. No. 10,141,880

DRIVING CIRCUIT FOR VOICE COIL MOTOR HAVING A FIRST DRIVER COUPLED TO A FIRST END OF A COIL AND A SECOND DRIVER COUPLED TO A SECOND END OF THE COIL

ROHM CO., LTD., Kyoto (J...

1. A driving circuit that supplies a bi-directional driving current to a voice coil motor, the driving circuit comprising:a current detection circuit structured to generate a detection voltage VS represented by VS=VREF+k×IDRV, with the driving current as IDRV, with a reference voltage as VREF, and with a gain as k;
an error amplifier structured to amplify a difference between the detection voltage VS and a control voltage that indicates a position of the voice coil motor so as to generate an error voltage;
a first driver having its output to be coupled to a first end of a coil of the voice coil motor, and structured to switch the driving current between a state in which the driving current flows as a source current and a state in which the driving current flows as a sink current according to the error voltage; and
a second driver having its output to be coupled to a second end of the coil of the voice coil motor, and structured to switch the driving current between a state in which the driving current flows as a sink current and a state in which the driving current flows as a source current according to the error voltage,
wherein a level of the reference voltage VREF is settable externally.

US Pat. No. 10,141,878

CONTROLLER FOR PERMANENT MAGNET SYNCHRONOUS MOTOR, AND CONTROL METHOD FOR ESTIMATING INITIAL POSITION OF ROTOR

KONICA MINOLTA, INC., To...

1. A controller for a sensorless permanent magnet synchronous motor having a rotor using a permanent magnet, the rotor rotating by a rotating magnetic field caused by a current flowing through an armature, the controller comprising:a drive portion configured to apply a voltage to the armature to drive the rotor;
an initial position estimating portion configured to estimate an initial position which is a position of magnetic poles of the rotor which is in a stop state; and
a control unit configured to control the drive portion; wherein
the initial position estimating portion gives instructions to the control unit to apply a pulse voltage for generating a magnetic field vector for searching for the initial position to each of search sections obtained by dividing a target range narrows down a target range in such a manner that a search section in which a largest amount of current flows through the armature by application of the pulse voltage is selected as a subsequent target range, and estimates the initial position.

US Pat. No. 10,141,877

CONTROLLER FOR PERMANENT MAGNET SYNCHRONOUS MOTOR, CONTROL METHOD, AND IMAGE FORMING APPARATUS

Konica Minolta, Inc., Ch...

1. A controller for a permanent magnet synchronous motor having a rotor using a permanent magnet, the rotor rotating by a rotating magnetic field caused by a current flowing through an armature, the controller comprising:a drive portion configured to feed a current to the armature to drive the rotor;
a speed estimating portion configured to estimate a rotational speed of the rotor based on the current flowing through the armature;
a magnetic pole position estimating portion configured to estimate a position of magnetic poles of the rotor based on an estimated speed that is the rotational speed estimated;
a control unit configured to control, based on an estimated angle that is an estimated value of the position of magnetic poles outputted by the magnetic pole position estimating portion, the drive portion to cause the rotating magnetic field rotating at a target speed indicated in an inputted speed command;
a step-out presuming portion configured to presume, based on the target speed and the estimated speed, whether or not a step-out occurs; and
a correction portion configured to correct the estimated angle when the step-out presuming portion presumes that a step-out occurs; wherein
when the correction portion corrects the estimated angle, the control unit controls, based on a post-correction estimated angle that is the estimated angle corrected by the correction portion, the drive portion to cause the rotating magnetic field depending on the target speed.

US Pat. No. 10,141,876

POWER GENERATOR SYSTEM, POWER GENERATOR CONTROL DEVICE, AND POWER-GENERATION BALANCE CONTROL METHOD FOR POWER GENERATOR SYSTEM

Mitsubishi Electric Corpo...

1. A generator system, comprising:a first generator control device comprising a first PWM signal generation part configured to generate a first PWM signal, the first generator control device being configured to control, based on the first PWM signal, a first field current to be supplied to a field coil of a first generator; and
a second generator control device comprising a second PWM signal generation part configured to generate a second PWM signal, the second generator control device being configured to control, based on the second PWM signal, a second field current to be supplied to a field coil of a second generator, wherein:
the first generator control device further comprises a duty restriction part configured to use a duty lower limit value that is more than 0% and a duty upper limit value that is less than 100% to perform, every X cycles, duty restriction processing on the first PWM signal generated by the first PWM signal generation part in continuous Y cycles out of the X cycles, and to transmit the first PWM signal after the restriction processing to the second generator control device;
the second generator control device further comprises a signal output control part configured to:
receive the first PWM signal after the restriction processing transmitted from the duty restriction part as a received PWM signal;
determine that a reception abnormality exists when the received PWM signal is received continuously in (X?Y+1) cycles as a signal representing a duty less than the duty lower limit value or a duty more than the duty upper limit value;
control the second field current based on the second PWM signal generated by the second PWM signal generation part in a cycle in which the reception abnormality is determined to exist; and
control the second field current based on the received PWM signal in a cycle in which the reception abnormality is not determined to exist; and
X and Y are integers satisfying X>Y>0.

US Pat. No. 10,141,861

POWER CONVERSION UNIT, POWER CONVERTER AND METHOD OF MANUFACTURING POWER CONVERTER

Hitachi, Ltd., Tokyo (JP...

1. A power conversion unit comprising:a circuit connection part including a plurality of conductors having different potentials, that is, at least a positive electrode conductor having an external positive terminal, at least a negative electrode conductor having an external negative terminal, and at least an AC conductor having an external AC terminal, wherein the circuit connection part has an approximately flat plate-like structure with a front side and a rear side;
a power semiconductor module connected to some of the plurality of conductors at the rear side of the circuit connection part; and
at least a capacitor connected to some of the plurality of conductors at the rear side of the circuit connection part,
wherein the positive electrode conductor is connectable to a different positive electrode conductor of a different power conversion unit through a unit connection part that is connected to the positive electrode conductor at the front side of the circuit connection part, and
wherein the negative electrode conductor is connectable to a different negative electrode conductor of the different power conversion unit through the unit connection part that is connected to the negative electrode conductor at the front side of the circuit connection part.

US Pat. No. 10,141,837

DEVICE AND METHOD FOR ENERGY HARVESTING USING A SELF-OSCILLATING POWER-ON-RESET START-UP CIRCUIT WITH AUTO-DISABLING FUNCTION

Agency for Science, Techn...

1. A device for energy harvesting, comprising:a start-up circuit including a power-on reset circuit for generating a sequence of pulses to control self-oscillation of the start-up circuit, an auxiliary voltage boost circuit coupled to the power-on reset circuit and an input of the start-up circuit for boosting an input voltage of the start-up circuit, and a feedback loop including an energy source, the auxiliary voltage boost circuit and the power-on reset circuit such that the start-up circuit generates the sequence of pulses for self-oscillation through the feedback loop for initial boosting of the input voltage from the energy source;
a main boost circuit for boosting the input voltage during a steady state phase;
a clock generator circuit for generating clock signals which control voltage boosting of the main boost circuit during the steady state phase; and
a switching circuit coupled to the start-up circuit, the main boost circuit and the clock generator circuit for switching powering of the clock generator circuit between the start-up circuit and the main boost circuit such that the clock generator circuit is powered by only one of the start-up circuit and the main boost circuit at any point in time.

US Pat. No. 10,141,814

LIQUID CRYOGEN VAPORIZER METHOD AND SYSTEM

Airgas USA, LLC, Radnor,...

1. A method for vaporizing liquid cryogen to supply a flow of gaseous cryogen, said method comprising the steps of:feeding a liquid cryogen from a storage tank to at least one pressure building vaporizer located at an installation, the storage tank having a headspace pressure P1;
exchanging heat between the fed liquid cryogen and a relatively warmer fluid across said at least one vaporizer to produce pressurized gaseous cryogen at pressure P2 exceeding P1;
feeding the pressurized gaseous cryogen from said at least one vaporizer to an expander located at the installation to expand the gaseous cryogen to a pressure P3;
feeding the expanded gaseous cryogen into a supply conduit;
feeding the expanded gaseous cryogen from the supply conduit to a point of use located at the installation, wherein P2?2×P3,
further comprising n pressure building vaporizers operated in an alternating sequence where n is an integer greater than 1; wherein as the liquid cryogen is being fed to a first vaporizer of the n vaporizers, no liquid cryogen is being fed to a second vaporizer of the n vaporizers
simultaneous with feeding the liquid cryogen to the first vaporizer, gaseous cryogen is fed from another of the n vaporizer to the turbine and expanded with said turbine; and
simultaneous with feeding the liquid cryogen to the second vaporizer, gaseous cryogen is fed from another of the n vaporizers to the turbine and expanded across the turbine and converting the turbine power to electricity using an alternator.

US Pat. No. 10,141,785

WIRELESS POWER TRANSMISSION APPARATUS AND WIRELESS POWER TRANSMISSION METHOD

Wilus Institute Of Standa...

1. A wireless power transmitting method of a wireless power transmitting apparatus,wherein a standby state of determining whether at least one wireless power receiving apparatus is positioned within a wireless charge range of the wireless power transmitting apparatus and a power transfer state of transmitting power to the corresponding wireless power receiving apparatus when at least one wireless power receiving apparatus is detected in the standby state are provided, and
the standby state includes a first standby state of periodically transmitting a weak detector signal and a strong detector signal and a second standby state in which at least one of a transmission period of the weak detector signal and a transmission period of the strong detector signal is different from that of the first standby state, the method comprising:
determining any one state of the first standby state and the second standby state of the wireless power transmitting apparatus; and
transmitting the weak detector signal and the strong detector signal based on the determined standby state,
wherein the transmission period of the weak detector signal in the second standby state is longer than the transmission period of the weak detector signal in the first standby state.

US Pat. No. 10,141,772

COMMUNICATION DEVICE

PANASONIC INTELLECTUAL PR...

1. A communication device comprising:a substrate having an upper surface, a lower surface, and a first edge surface connecting to the upper surface and the lower surface;
a magnetic sheet disposed above the upper surface of the substrate;
a first coil disposed above an upper surface of the magnetic sheet;
a second coil having a portion facing the first edge surface of the substrate in a direction parallel with the upper surface of the substrate; and
an electronic component disposed on the upper surface of the substrate, the electronic component configured to generate noise,
wherein the magnetic sheet has a portion overlapping the second coil in a thickness direction of the magnetic sheet, and
wherein the electronic component does not overlap the magnetic sheet in the thickness direction of the magnetic sheet such that the electronic component is exposed from the magnetic sheet when viewed in plan.

US Pat. No. 10,141,753

STORAGE BATTERY SYSTEM

TOSHIBA MITSUBISHI-ELECTR...

1. A storage battery system for which N (N?2) power conditioning systems are connected to a power system and a storage battery module group formed by connecting one or more storage battery modules in parallel is connected to each of the N power conditioning systems, and which is operated on a basis of a charge/discharge request from an energy management system that manages electric power supply/demand of the power system, the storage battery system comprising:battery management units that monitor a state of the storage battery module group; and
a controller that receives the charge/discharge request and storage battery information supplied from the battery management units, and controls the N power conditioning systems on the basis of the charge/discharge request and the storage battery information, wherein the power conditioning system has a function of converting AC power of the power system to DC power and charging the DC power to the storage battery module group, and a function of converting the DC power of the storage battery module group to the AC power and discharging the AC power to the power system,
wherein a maximum power storage capacity of the storage battery modules configuring at least one storage battery module group is different from a maximum power storage capacity of the storage battery modules configuring the other storage battery module groups, and
wherein the controller includes a charge/discharge command unit that determines a charge/discharge amount of each of the N power conditioning systems so as to satisfy a relational expression (1) below:

 where,
Pi is the charge/discharge amount of an i-th power conditioning system (1?i?N),
Preq is the charge/discharge request,
Bnumi is the number of the storage battery modules connected to the i-th power conditioning system, and
Cratioi is a capacity ratio of the maximum power storage capacity of the storage battery modules connected to the i-th power conditioning system to a reference power storage capacity.

US Pat. No. 10,141,751

CONTROL SYSTEM FOR ELECTRIC STORAGE SYSTEM

Hitachi, Ltd., Tokyo (JP...

1. A control system to control an electric storage system in which a plurality of pairs of storage batteries and converters are connected in parallel to a power system, comprising:a controller configured to control a charge total power received by the plurality of pairs of storage batteries and converters,
wherein a total number of the plurality of pairs of storage batteries and converters is N, and N is ?2,
wherein the controller is configured to:
compare the charge total power (P) to be received by the plurality of pairs of storage batteries and converters with a limit output (p0) corresponding to a predetermined conversion efficiency of a first pair of the storage batteries and converters
when p0?P?N×p0, determine an operation number (n) of the pairs of storage batteries and converters which are to operate to receive the P in parallel, where n is equal to an integer quotient of P/p0, and
wherein the controller is further configured to:
determine respective charge powers (Pi) of each of the n pairs of storage batteries and converters for a charge operation based on respective states of charge (SOCi) of each of the n pairs of storage batteries and converters and a predetermined upper limit charge amount (SOCmax).

US Pat. No. 10,141,743

BIPOLAR VSC-HVDC AND UPFC HYBRID TOPOLOGY AND AN OPERATION METHOD THEREOF

State Grid Jiangsu Electr...

1. A bipolar VSC-HVDC and UPFC hybrid topology, comprisinga first control circuit, a second control circuit, a DC transmission line and a third control circuit, wherein,
the first control circuit is a double circuit lines structure used as a circuit at series side of UPFC, and comprises a series side positive circuit and a series side negative circuit, both of which include a series VSC converter and a series transformer,
the first control circuit further comprises a thyristor bypass switch, a mechanical bypass switch and a resistor connected between the VSC converter and the series transformer, the VSC converters in the series side positive circuit and the series side negative circuit operate in bipolar mode, and positive and negative electrodes of the first control circuit is connected to a DC bus via a DC breaker;
the second control circuit comprises a positive circuit and a negative circuit, both of which include a shunt transformer and a VSC converter,
the VSC converters in the positive and negative circuit operate in bipolar mode and are configured with an earth electrode, and positive and negative electrodes of the second control circuit are connected to the DC bus via a DC breaker;
the third control circuit is the same as the second control circuit in terms of structures;
one end of the DC transmission line is connected to the DC bus via a DC breaker and the other end of the DC transmission line is connected to positive and negative electrodes of the third control circuit via a DC breaker respectively.

US Pat. No. 10,141,742

SYSTEM AND METHOD FOR PROVIDING A BALANCING POWER FOR AN ELECTRICAL POWER GRID

CATERVA GMBH, Pullach Im...

1. A regulating system adapted to provide in the event of a deviation from a nominal grid frequency a balancing power for an electrical power grid that is operated at the nominal grid frequency,wherein the regulating system comprises:
multiple energy storage system, ESS, units that are connected in each case by means of an inverter to the electrical power grid and comprise in each case at least one energy storage device; and
a control centre adapted to divide into sub-frequency intervals a frequency deviation interval that lies between a minimum grid frequency and a maximum grid frequency around the nominal grid frequency and adapted, in dependence upon the states of charge of the energy storage devices that are included in the energy storage system, ESS, units, to allocate different energy storage system, ESS, units to each sub-frequency interval so as to form an ESS cluster for the respective sub-frequency interval, wherein said ESS-cluster delivers a portion of the balancing power that is to be provided by the regulating system in the respective sub-frequency interval.

US Pat. No. 10,141,733

VARIABLE FREQUENCY DRIVE OVERVOLTAGE PROTECTION

Trane International Inc.,...

1. A method comprising:operating a variable frequency motor drive including an AC/DC converter electrically coupled with an AC power source, a DC link electrically coupled with the AC/DC converter, and a DC/AC converter electrically coupled with the DC link;
receiving information indicative of a voltage of the DC link at a microprocessor-based controller;
processing the received information to model a condition of at least one power electronics component of the variable frequency motor drive; and
disconnecting the AC/DC converter from the AC power source if the modeled condition meets a protection criterion;
wherein the disconnecting comprises performing a shunt trip operation performed in response to an evaluation of a DC bus voltage relative to a threshold, the shunt trip operation occurring without occurrence of an overcurrent condition.

US Pat. No. 10,141,721

LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF

SONY CORPORATION, Tokyo ...

1. A method of manufacturing a light-emitting element, the method comprising:forming a selective growth mask layer on a GaN substrate, wherein the selective growth mask layer comprises a first light reflecting layer;
selectively growing a first compound semiconductor layer from a surface of the GaN substrate not covered with the selective growth mask layer, and covering the GaN substrate and the selective growth mask layer with the first compound semiconductor layer;
forming an active layer on the first compound semiconductor layer;
forming a second compound semiconductor layer on the active layer;
forming an electrode on the second compound semiconductor layer; and
forming a second light reflecting layer on the electrode, wherein
an off angle of plane orientation of the surface of the GaN substrate is 0.4 degrees or less,
an area of the selective growth mask layer is 0.8S0 or less, where S0 represents an area of the GaN substrate, and
a thermal expansion relaxation film is on the GaN substrate as a bottom layer of the selective growth mask layer.

US Pat. No. 10,141,714

METHOD FOR MANUFACTURING GALLIUM AND NITROGEN BEARING LASER DEVICES WITH IMPROVED USAGE OF SUBSTRATE MATERIAL

Soraa Laser Diode, Inc., ...

1. A plurality of dies, comprising:a gallium and nitrogen containing substrate having a surface region;
an epitaxial material formed overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active region, wherein the epitaxial material is patterned to form the plurality of dies on the surface region, the dies corresponding to a laser device, wherein each of the plurality of dies comprises:
a release region composed of a material with a smaller bandgap than an adjacent epitaxial material, wherein a lateral width of the release region is narrower than a lateral width of immediately adjacent layers above and below the release region to form undercut regions bounding each side of the release region; and
a passivation region extending along sidewalls of the active region.

US Pat. No. 10,141,655

SWITCH ASSEMBLY WITH INTEGRATED TUNING CAPABILITY

Ethertronics, Inc., San ...

1. A radio frequency integrated circuit (RFIC) containing a switch assembly with integrated tuning capability, the RFIC comprising:a plurality of multi-port switches, including:
a first multi-port switch configured to couple with a first antenna adapted for communication at low-frequency bands between 698 MHz and 960 MHz,
a second multi-port switch configured to couple with a second antenna adapted for communication at mid-frequency bands between 850 MHz and 900 MHz, and
a third multi-port switch configured to couple with a third antenna adapted for communication at high-frequency bands between 1710 MHz and 2700 MHz,
each of the first through third multi-port switches further configured to couple with a plurality of RF paths of an RF front end within a communication system;
a first tunable component coupled to the first multi-port switch, wherein the first tunable component is configured to vary an impedance associated with the first multi-port switch;
a second tunable component coupled to the second multi-port switch, wherein the second tunable component is configured to vary an impedance associated with the second multi-port switch;
a memory cell configured for storing information; and
a look-up table resident in said memory cell and containing said information, wherein the information includes: switch state data for configuring a state of each of the first through third multi-port switches, and tuning state data for configuring a state of each of the first and second tunable components;
wherein each of the first through third multi-port switches and the first and second tunable components are adapted to couple with a processor for receiving control signals for configuring a switch state or tuning state, respectively; and
wherein the third multi-port switch is not connected to a tunable component.

US Pat. No. 10,141,637

PATTERN ANTENNA

MegaChips Corporation, O...

1. A pattern antenna comprising:a substrate;
a first ground formed on a first surface of the substrate;
an antenna including a first conductor in which a plurality of bents are formed, the first conductor being formed on the first surface of the substrate and being electrically connected to the first ground;
a circuit including a second conductor formed in a second surface, which is a different surface from the first surface, the second conductor being formed so as to at least partially overlap with the first conductor of the antenna as viewed in planar view, the circuit including:
a first taper with a tapered shape, a feed point being disposed at a tip of the first taper or in proximity of the tip of the first taper; and
an extension extended toward a side opposite to the feed point as viewed in planar view, the extension being electrically connected to the first taper;
a connector configured to electrically connect the first conductor with the second conductor; and
a second ground, with no contact with the first taper, with such a shape that sandwiches at least a part of the first taper as viewed in planar view, wherein
the second ground includes a second taper, and
the second taper is tapered such that the second ground does not contact with the first taper.

US Pat. No. 10,141,548

BATTERY PACKAGING MATERIAL, BATTERY, AND METHOD FOR PRODUCING SAME

DAI NIPPON PRINTING CO., ...

1. A battery packaging material comprising a laminate in which at least a base material layer, a metal layer, an adhesive layer, and a sealant layer containing a polyolefin resin are laminated in this order, whereinthe sealant layer contains an amide-based lubricant,
an amount of the amide-based lubricant in the adhesive layer is 100 ppm or less,
the value Y calculated from the following formula (1) is in the range of 250 to 750:
Y=(A×C+B×D)/(C+D)  (1)
where:
A represents an amount of the amide-based lubricant in the sealant layer,
B represents an amount of the amide-based lubricant in the adhesive layer,
C represents a thickness of the sealant layer, and
D represents a thickness of the adhesive layer, and
the intensity ratio X=P/Q is in a range of from 0.05 to 0.80, where P is a peak intensity P at 1650 cm?1 originating from C?O stretching vibration of the amide group of an amide-based lubricant, and Q is a peak intensity Q at 1460 cm?1 originating from bending vibration of the group —CH2— of the polyolefin resin, each of which is measured from an absorption spectrum obtained by splitting reflected light in irradiation of the surface of the sealant layer with an infrared ray, and P/Q is a ratio of the peak intensity P to the peak intensity Q.

US Pat. No. 10,141,543

METHOD FOR MANUFACTURING ELECTRONIC DEVICE

LG Chem, Ltd., Seoul (KR...

1. A method of manufacturing an organic electronic device, comprising:laminating an encapsulating film onto a surface of the organic electronic device, wherein the encapsulating film is formed by a first layer comprising a first adhesive component and a second layer comprising a second adhesive component, wherein the first and second adhesive components are different, and the laminating comprising placing the encapsulating film onto the organic electronic device such that the second layer is in contact with the organic electronic device, and the first layer is not in contact with the organic electronic device,
wherein the first adhesive component of the first layer comprises polyisobutene resin, the first layer further comprising a tackifier, and wherein the first layer comprises 5 to 250 parts by weight of a moisture scavenger relative to 100 parts by weight of the first adhesive component; and
wherein the second layer comprises less than 5 parts by weight of the moisture scavenger relative to 100 parts by weight of a solid content of the second layer.

US Pat. No. 10,141,535

OPTOELECTRONIC COMPONENT AND A METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT

OSRAM OLED GMBH, Regensb...

1. An optoelectronic component, comprising:a first electrode comprising at least one outer electrode segment which is formed at a lateral edge of the first electrode, and at least one inner electrode segment which is formed in a manner spaced apart from the lateral edge of the first electrode,
an electrically conductive current distribution structure formed above the first electrode and comprising at least one outer substructure which extends at least over the outer electrode segment, and at least one inner substructure which extends at least over the inner electrode segment and which is electrically insulated from the outer substructure,
at least one current lead which extends from the lateral edge of the first electrode toward the inner substructure, which is electrically coupled to the inner substructure, which is electrically insulated from the outer substructure and which structure corresponds to the current distribution structure,
an insulation structure, which covers the current distribution structure and the current lead,
an organic functional layer structure above the first electrode, the current distribution structure, the current lead and the insulation structure, and a second electrode above the organic functional layer structure.

US Pat. No. 10,141,520

COATING LIQUID FOR FORMING LIGHT EMITTING LAYER, ORGANIC ELECTROLUMINESCENT ELEMENT, METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENT ELEMENT, AND LIGHTING/DISPLAY DEVICE

Konica Minolta, Inc., To...

1. A coating solution for forming a luminous layer included in one or more organic layers disposed between an anode and a cathode, the coating solution comprising:a thermally-activated delayed fluorescent, compound, and
a heavy atom compound having an external heavy-atom effect to promote intersystem crossing of the thermally-activated delayed fluorescent compound from a triplet excited state to a singlet excited state to increase a fluorescent intensity,
wherein the heavy atom compound is a phosphorescent metal complex,
a lowest excited triplet energy level (T1(TADF)) of the thermally-activated delayed fluorescent compound and a lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex are within ranges allowing transfer of energy electrons therebetween,
a difference in energy between a lowest excited singlet energy level (S1(TADF)) of the thermally-activated delayed fluorescent compound and the lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex is within a range represented by Expression (1):
?0.2 eV?[S1(TADF)-T1(P)]?1.0 eV  (1), and
a difference in energy between the lowest excited triplet energy level (T1(TADF)) of the thermally-activated delayed fluorescent compound and the lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex is within a range represented by Expression (3):
?0.2 eV?[T1(TADF)?T1(P)]?0.5 eV  (3)

US Pat. No. 10,141,516

COMPOUND FOR ORGANIC ELECTRIC ELEMENT, ORGANIC ELECTRIC ELEMENT COMPRISING THE SAME AND ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound represented by Formula 1 below:
wherein,
m is an integer from 1 to 4,
n is an integer from 1 to 3,
R1 is selected from the group consisting of hydrogen, deuterium, tritium, a C6-C60 aryl group, and a fluorenyl group, and R2 is selected from the group consisting of hydrogen, deuterium, tritium, a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the aryl group, heterocyclic group, and fluorenyl group may be substituted by one or more substituents selected from the group consisting of halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group,
Ar1 is selected from the group consisting of a fluorenyl group, a C6-C60 aryl group, a C2-C20 alkenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, and a C1-C50 alkyl group, wherein the aryl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group; and the heterocyclic group, fluorenyl group, alkyl group, and alkenyl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group,
L1 is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, and a C2-C60 bivalent heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the arylene group, fluorenylene group, and heterocyclic group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group, and
Ar2 and Ar3 are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the aryl group, heterocyclic group, and fluorenyl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, -L?-N(R?)(R?), a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group, wherein L? is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; and R? and R? are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P.

US Pat. No. 10,141,505

BROMINE CONTAINING SILICON PRECURSORS FOR ENCAPSULATION LAYERS

Lam Research Corporation,...

16. An apparatus comprisingat least one process chamber comprising a pedestal for holding a substrate;
at least one outlet for coupling to a vacuum;
one or more process gas inlets coupled to process gas sources; and
a controller for controlling operations, comprising machine-readable instructions for:
causing introduction of diiodosilane or hexaiodosilane to the at least one process chamber; and
causing introduction of a second reactant to the at least one process chamber.

US Pat. No. 10,141,501

MAGNETORESISTIVE ELEMENT

TDK CORPORATION, Tokyo (...

1. A magnetoresistive element comprising:a channel layer;
a first ferromagnetic layer;
a second ferromagnetic layer; and
a reference electrode, wherein:
the first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode are apart from each other and are electrically connected to each other through the channel layer;
the first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode do not overlap each other and are apart from each other when viewed in a thickness direction of the channel layer;
the channel layer includes a first region that overlaps the first ferromagnetic layer when viewed in the thickness direction, a second region that overlaps the second ferromagnetic layer when viewed in the thickness direction, a third region that overlaps the reference electrode when viewed in the thickness direction, a fourth region located between the first region and the second region, and a fifth region located between the second region and the third region;
the second region is located between the first region and the third region in the channel layer;
the first region, the second region, and the fourth region form a sixth region;
the second region, the third region, and the fifth region form a seventh region; and
an average cross-sectional area of the sixth region according to a first plane which perpendicularly intersects a shortest path in the channel layer between an end surface of the first region that is opposite to a surface of the first region that is in contact with the fourth region and an end surface of the second region that is opposite to a surface of the second region that is in contact with the fourth region is smaller than an average cross-sectional area of the seventh region according to a second plane which perpendicularly intersects a shortest path in the channel layer between an end surface of the second region that is opposite to a surface of the second region that is in contact with the fifth region and an end surface of the third region that is opposite to a surface of the third region that is in contact with the fifth region.

US Pat. No. 10,141,498

MAGNETORESISTIVE STACK, SEED REGION THEREOF AND METHOD OF MANUFACTURING SAME

Everspin Technologies, In...

1. A method of manufacturing a magnetoresistive stack comprising:depositing a seed region on an electrically conductive material, wherein depositing the seed region includes:
depositing an alloy including nickel and chromium having a thickness greater than or equal to 40 Angstroms and a material composition of chromium in the range of 25-60% by atomic percent;
depositing a fixed magnetic region on and in direct contact with the seed region, wherein depositing the fixed magnetic region includes:
depositing a multilayer unpinned, fixed synthetic antiferromagnetic structure including (i) depositing a first ferromagnetic structure on and in direct contact with the seed region, (ii) depositing a coupling material on and in direct contact with the first ferromagnetic structure, and (iii) depositing a second ferromagnetic structure on and in direct contact with the coupling material,
depositing a transition layer on and in direct contact with the second ferromagnetic structure, wherein the transition layer includes a non-ferromagnetic transition metal, and
forming a high-iron alloy interface region over the transition layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition;
depositing one or more dielectric layers wherein, after annealing, the one or more dielectric layers are on and in direct contact with the high-iron alloy interface region of the fixed magnetic region; and
depositing a free magnetic region over the one or more dielectric layers.

US Pat. No. 10,141,490

COMPOSITE BASE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, comprising:providing a light emitting device set that includes
a lead frame including a plurality of pairs of supporting leads each of which pairs consists of a first supporting lead and a second supporting lead,
a plurality of packages respectively supported by the plurality of pairs of supporting leads, and
a plurality of light emitting elements respectively mounted on the plurality of packages; and
removing the plurality of packages from the lead frame,
wherein the packages each include a resin molded body,
the resin molded body includes
a first outer surface supported by the first supporting lead,
a second outer surface positioned opposite to the first outer surface and supported by the second supporting lead,
a third outer surface positioned between the first outer surface and the second outer surface,
a fourth outer surface positioned opposite to the third outer surface,
a first recess that is open at the first outer surface and the third outer surface, and
a second recess that is open at the second outer surface and the third outer surface,
wherein the first supporting lead fits into the first recess, and the second supporting lead fits into the second recess, and
wherein the packages are each removed from the lead frame by the third outer surface being pushed.

US Pat. No. 10,141,483

SEMICONDUCTOR ILLUMINATING DEVICE

OSRAM Opto Semiconductors...

1. A semiconductor illuminating device for emitting illumination light comprising:an LED configured for emitting blue primary radiation; and
an LED phosphor arranged and configured such that it emits secondary light that forms at least one component of the illumination light,
wherein the LED phosphor comprises a red phosphor for emitting red light as a component of the secondary light and a green phosphor for emitting green light as a component of the secondary light, wherein the green light has a color point located above a first straight line having a slope m1 and a y-intercept n1 in a CIE standard chromaticity diagram, with the slope m1=1.189 and the y-intercept n1=0.226, and
wherein the components of the illumination light are at such a ratio to one another that the illumination light has a color temperature of at most 5500 K.

US Pat. No. 10,141,482

SEMICONDUCTOR LIGHT EMITTING DEVICE

ALPAD CORPORATION, Tokyo...

1. A semiconductor light emitting device, comprising:a light emitting chip having a semiconductor layer at a first surface of the light emitting chip;
a transparent film on the first surface and forming an interface with the semiconductor layer;
a phosphor resin layer including a resin and a phosphor, on the transparent film;
a first electrode having an upper surface on which the light emitting chip is disposed;
a second electrode having an upper surface and being spaced from the first electrode in a direction parallel to the upper surface of the first electrode; and
a reflection layer provided on the upper surfaces of the first and second electrodes, wherein
a refractive index of the transparent film is greater than a refractive index of the semiconductor layer.

US Pat. No. 10,141,480

LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME

Seoul Viosys Co., Ltd., ...

1. A method of fabricating a light emitting diode chip, the method comprising:forming a light emitting structure on a first surface of a substrate, the light emitting structure comprising:
a first conductive-type semiconductor layer;
a second conductive-type semiconductor layer; and
an active layer disposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer;
removing a portion of the substrate by grinding a second surface of the substrate;
after the grinding, reducing the surface roughness of the second surface of the substrate by lapping the substrate; and
forming a distributed Bragg reflector on the second surface of the substrate,
wherein the distributed Bragg reflector comprises a first material layer comprising TiO2, a second material layer comprising SiO2, a third material layer comprising TiO2, and a fourth material layer comprising SiO2, and
wherein the first material layer has an optical thickness that is different from an optical thickness of the third material layer.

US Pat. No. 10,141,468

METHOD AND APPARATUS FOR A THERMOPHOTOVOLTAIC CELL

Atrius Energy, Inc., Hun...

1. A thermophotovoltaic cell, comprising:a PN junction comprising a p-type semiconductor layer, wherein said p-type semiconductor layer further comprises chromium oxide;
a passivation layer; and
a pair of opposing conductive current collectors;
wherein said PN junction and said passivation layer are positioned between said pair of opposing conductive current collectors.

US Pat. No. 10,141,434

COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Huawei Technologies Co., ...

1. A complementary tunneling field effect transistor, comprising:a first drain region and a first source region disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant;
a first channel disposed on the first drain region and a second channel disposed on the first source region;
a second source region disposed on the first channel and a second drain region disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant;
a first epitaxial layer disposed on the first drain region and the second source region, and a second epitaxial layer disposed on the second drain region and the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region;
a first gate stack layer disposed on the first epitaxial layer, and a second gate stack layer disposed on the second epitaxial layer;
a first isolator disposed on the second source region and the first drain region, and a second isolator disposed on the first source region and the second drain region, wherein the first isolator is in contact with the first epitaxial layer and the first gate stack layer, and the second isolator is in contact with the second epitaxial layer and the second gate stack layer; and
wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.

US Pat. No. 10,141,431

EPITAXY SOURCE/DRAIN REGIONS OF FINFETS AND METHOD FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming isolation regions extending into a semiconductor substrate, wherein the forming the isolation regions comprises:
in a common etching process, etching the semiconductor substrate to form two first trenches and a second trench between the two first trenches;
forming a hard mask layer comprising first bottom portions extending to bottoms of the two first trenches, and a second bottom portion extending to a bottom of the second trench;
performing an etching step, wherein both the two first bottom portions and the second bottom portion are exposed to an etchant used in the etching step, and the first bottom portions and portions of the semiconductor substrate directly underlying the first bottom portions are etched to extend the two first trenches down, and the second bottom portion protects a portion of the semiconductor substrate directly underlying the second bottom portion; and
filling the two first trenches and the second trench with a dielectric material to form isolation regions;
recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins;
recessing the semiconductor fins to form recesses;
epitaxially growing a first semiconductor material from the recesses;
etching the first semiconductor material; and
epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

US Pat. No. 10,141,404

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGION

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
a first cell and a second cell, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
a second mesa included in the second cell, the second mesa including a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in the direction, wherein the insulation structure houses:
a control electrode structure for controlling the load current within the first mesa and the second mesa, the control electrode structure being electrically insulated from the first load terminal structure; and
a guidance electrode electrically insulated from the control electrode structure and arranged in between the first mesa and the second mesa,
wherein the control electrode structure is configured to induce an inversion channel within the first channel region and an accumulation channel within the second channel region.

US Pat. No. 10,141,398

HIGH VOLTAGE MOS STRUCTURE AND ITS MANUFACTURING METHOD

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a high-voltage (HV) NMOS structure, comprising:
a source region and a drain region separated from each other;
a channel region disposed between the source region and the drain region, the channel region having a channel direction from the source region toward the drain region;
a gate dielectric disposed on the channel region and on portions of the source region and the drain region; and
a gate electrode disposed on the gate dielectric, the gate electrode comprising:
a first portion of n-type doping; and
two second portions of p-type doping disposed at two sides of the first portion, the two second portions having an extending direction perpendicular to the channel direction;
wherein the HV NMOS structure further comprises:
a substrate;
a first n-type doped region and a second n-type doped region disposed in the substrate and separated from each other;
an isolation structure disposed in the substrate, the isolation structure having a first through opening and a second through opening in the first n-type doped region and the second n-type doped region, respectively;
a first n-type heavily doped region and a second n-type heavily doped region disposed in the first through opening and the second through opening, respectively;
wherein the first n-type doped region and the first n-type heavily doped region are disposed in the source region, and the second n-type doped region and the second n-type heavily doped region are disposed in the drain region.

US Pat. No. 10,141,391

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR CONTAINING AN EMBEDDED RESISTOR STRUCTURE

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic pad structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic pad structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a metal resistor structure on a recessed surface of the first metallic pad structure or the second metallic pad structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the metal resistor structure and the first metallic pad structure or the second metallic pad structure.

US Pat. No. 10,141,388

DISPLAY DEVICE WITH TRANSISTOR SAMPLING FOR IMPROVED PERFORMANCE

SONY CORPORATION, Tokyo ...

1. An apparatus comprising:a plurality of pixels arranged in a matrix form, each of the pixels including a capacitor, a first transistor, a second transistor, and a light emitting element;
a plurality of first lines that extend along a first direction and connected to the pixels;
a plurality of second line that extend along a second direction and connected to the pixels, the second direction being perpendicular to the first direction;
wherein,
(a) each of the first lines includes a first lower wiring portion, a second lower wiring portion, and an upper wiring portion, and
(b) in each of the first lines:
(i) the upper wiring portion is connected to the first lower wiring portion via a first plurality of contact holes formed in an insulating film, and connected to the second lower wiring portion via a second plurality of contact holes formed in the insulating film,
(ii) the upper wiring portion is on the insulating film,
(iii) the insulating film is on the lower wiring portion,
(iv) the power supply line crosses the first lower wiring portion, and
(v) the second lower wiring portion crosses a corresponding one of the second lines.

US Pat. No. 10,141,384

ORGANIC ELECTROLUMINESCENT PANEL AND LUMINESCENT UNIT

Joled Inc., Tokyo (JP)

1. An organic electroluminescent panel comprising:a plurality of pixels each including a plurality of subpixels, the subpixels each including an organic electroluminescent element, the organic electroluminescent element including a first electrode, a second electrode, and an organic material layer that is provided between the first electrode and the second electrode; and
a plurality of banks that define each of the subpixels in each of the pixels,
the organic electroluminescent element in each of the subpixels being provided in a gap between adjacent two of the plurality of banks, and
the following relational expression being satisfied:
y?0.0001714x2+0.0151429x+0.2914286
where y denotes a height, from a bottom surface of the gap, of a pinning position at which a surface of the organic material layer and one of the banks are in contact with each other, and x denotes a width of the bottom surface of the gap.

US Pat. No. 10,141,375

DISPLAY DEVICE HAVING A SOLAR CELL LAYER

LG Display Co., Ltd., Se...

1. A display device comprising:a first light-emitting area provided on a lower substrate;
a second light-emitting area provided on the lower substrate;
a third light-emitting area provided on the lower substrate;
a solar cell layer provided on an upper substrate facing the lower substrate, the solar cell layer producing power by absorbing light, the solar cell layer including first, second and third organic solar cell layers which are disposed in areas corresponding to the respective first, second and third light-emitting areas,
wherein the solar cell layer includes:
a first electrode provided on the upper substrate;
a hole transporting layer provided between the first electrode and each of the first, second and third organic solar cell lavers,
an electron transporting layer provided the first, second and third organic solar cell layers, and
a second electrode provided on the electron transporting layer and disposed in areas corresponding to the respective first, second and third organic solar cell layers.

US Pat. No. 10,141,371

WIDE BAND GAP DEVICE INTEGRATED CIRCUIT DEVICE

Qromis, Inc., Santa Clar...

1. A device comprising:a plurality of groups of gallium nitride (GaN) epitaxial layers, a combined thickness of the plurality of groups of GaN epitaxial layers greater than ten microns;
mesas etched within at least some groups of the plurality of groups of GaN epitaxial layers;
internal interconnects formed within the mesas;
electrodes formed on at least one of the internal interconnects or the GaN epitaxial layers, the electrodes configuring each group of GaN epitaxial layers of the plurality of groups of GaN epitaxial layers into a GaN device of a plurality of GaN devices; and
external interconnects formed over at least some of the electrodes for connecting the plurality of GaN devices into an integrated circuit.

US Pat. No. 10,141,359

IMAGE SENSOR

HIMAX TECHNOLOGIES LIMITE...

1. An image sensor, comprising:an infrared receiving portion configured to receive infrared, and
a visible light receiving portion configured to receive a visible light, wherein the visible light receiving portion comprises an infrared cutoff filter grid and a color filter;
wherein the infrared cutoff filter grid has a grid structure;
wherein the infrared cutoff filter grid is configured to block the transmission of the infrared laterally passing the color filter;
wherein when viewed in cross section, the infrared cutoff filter grid comprises a base portion having an upper surface, and a plurality of pillar portions extending upwardly from the upper surface of the base portion, each adjacent pair of the pillar portions forming a space therebetween to thereby form a plurality of spaces;
wherein the color filter comprises a red color filter unit, a blue color filter unit, and a green color filter unit, and each of the red color filter unit, the blue color filter unit, and the green color filter unit is filled in one of the spaces;
wherein the visible light receiving portion further comprises a visible light photodiode and an infrared cutoff filter disposed on the visible light photodiode;
wherein the infrared cutoff filter and infrared cutoff filter grid are formed in one-piece.

US Pat. No. 10,141,356

IMAGE SENSOR PIXELS HAVING DUAL GATE CHARGE TRANSFERRING TRANSISTORS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor pixel, comprising:a photodiode that generates charge in response to image light;
a floating diffusion node; and
a charge transferring transistor having a first gate and a second gate, wherein the first gate and the second gate are controlled by respective first and second control lines, wherein the charge transferring transistor is configured to transfer the generated charge from the photodiode to the floating diffusion node, wherein the second control line is configured to modulate a bias applied to the second gate between at least three different voltages, wherein the at least three different voltages include a reset voltage, a transfer voltage, and an intermediate voltage, and wherein the intermediate voltage is dynamically adjusted while the generated charge is transferred from the photodiode to the floating diffusion node to change a conversion gain of the image sensor pixel.

US Pat. No. 10,141,353

PASSIVE COMPONENTS IMPLEMENTED ON A PLURALITY OF STACKED INSULATORS

QUALCOMM Incorporated, S...

1. An integrated circuit apparatus, comprising:a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface;
a first conductor disposed on the first insulator;
a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface;
a second conductor disposed on the second insulator; and
a dielectric layer disposed between the first conductor of the first insulator and the second conductor of the second insulator;
wherein:
a capacitor is formed by the first conductor disposed on the first insulator, the dielectric layer, and the second conductor disposed on the second insulator; and
an inductor is formed on the first insulator and the second insulator.

US Pat. No. 10,141,349

THIN-FILM TRANSISTOR ARRAY, FABRICATION METHOD THEREFOR, IMAGE DISPLAY DEVICE AND DISPLAY METHOD

TOPPAN PRINTING CO., LTD....

1. A thin-film transistor array, comprising:a plurality of thin-film transistors each having a configuration in which a gate electrode, a gate wiring connected to the gate electrode, capacitor electrode, and a capacitor wiring connected to the capacitor electrode are provided on an insulating substrate, with a source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern being formed, in a region overlapping with the gate electrode via a gate insulator film, the semiconductor pattern being covered with a protective layer, two thin-film transistors of the plurality of thin-film transistors being independently formed for each pixel, two source electrodes in each pixel being separately connected to two respective source wirings, two drain electrodes each being directly connected to an electrode of the pixel via respective drain-connecting electrodes,
wherein the thin-film transistor array includes source-connecting electrodes each connecting between the source electrodes of the two thin-film transistors formed for each pixel,
wherein the protective layer is in a stripe pattern and formed along the gate wirings such that the protective layer covers the semiconductor patterns and the source wirings,
wherein the protective layer does not cover a portion of the source-connecting electrodes, and
wherein the thin-film transistor array includes an insulating film that covers the source wirings and the portion of the source-connecting electrodes not covered by the protective layer.

US Pat. No. 10,141,343

OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive layer;
a second conductive layer;
a first insulating layer over the first conductive layer and the second conductive layer;
an oxide semiconductor layer over the first insulating layer;
a third conductive layer electrically connected to the oxide semiconductor layer;
a fourth conductive layer electrically connected to the oxide semiconductor layer; and
a fifth conductive layer over the first insulating layer,
wherein the first conductive layer includes a region functioning as a gate electrode of a transistor,
wherein the second conductive layer includes a region functioning as a first electrode of a capacitor,
wherein the oxide semiconductor layer includes a region functioning as a channel formation region of the transistor,
wherein the third conductive layer includes a region functioning as one of a source electrode and a drain electrode of the transistor,
wherein the fourth conductive layer includes a region functioning as the other one of the source electrode and the drain electrode of the transistor,
wherein the fourth conductive layer is electrically connected to the second conductive layer,
wherein the fifth conductive layer includes a region functioning as a second electrode of the capacitor,
wherein the oxide semiconductor layer includes In, Ga, and Zn, and
wherein a concentration of Zn is lower than a concentration of In or a concentration of Ga.

US Pat. No. 10,141,341

THIN-FILM-TRANSISTOR (TFT) ARRAY PANEL WITH STRESS ELIMINATION LAYER AND METHOD OF MANUFACTURING THE SAME

Shenzhen China Star Optoe...

1. A method for manufacturing a TFT array panel, the TFT array panel comprising:a flexible baseplate;
a buffer layer, disposed on the flexible baseplate, on which a stress-elimination portion for eliminating a stress of the flexible baseplate is disposed;
a display-element layer, disposed on the buffer layer;
wherein the method comprises steps:
A. disposing the buffer layer on the flexible baseplate;
B. disposing the stress-elimination portion on the buffer layer, wherein the stress-elimination portion is used to eliminate a stress of the flexible baseplate;
C. disposing the display-element layer on the buffer layer;
wherein the step B comprises:
b1. Performing a photo-mask process and/or an etching process on the buffer layer, to form the stress-elimination portion;
the stress-elimination portion is disposed on a plane of the buffer layer, and the plane is positioned closer to the display-element layer than a position of one other plane of the buffer layer;
wherein the stress-elimination portion comprises at least one recess and at least one protrusion portion, wherein the at least one recess and the at least one protrusion portion are lined up as a one dimensional array or a two dimensional array.

US Pat. No. 10,141,339

EMBEDDED SECURITY CIRCUIT FORMED BY DIRECTED SELF-ASSEMBLY

International Business Ma...

1. A method, comprising:defining at least two regions of a circuit structure on a substrate, wherein the at least two regions comprise a security region and a non-security region;
forming a guiding pattern on the substrate, wherein the guiding pattern comprises a plurality of raised features formed within the security and non-security regions, wherein the raised features of the guiding pattern formed within the non-security region are separated by a first distinct width, and wherein the raised features of the guiding pattern formed within the security region are separated by a second distinct width;
depositing a self-assembling material comprising at least one of a block copolymer and a block copolymer/homopolymer combination, within spaces between the raised features of the guiding pattern, wherein the self-assembling material comprises block materials that are configured to assemble into a block pattern with a natural pitch;
annealing the self-assembling material to initiate a self-assembly process directed by the plurality of raised features of the guiding pattern, and form block patterns of the block materials within the spaces between the raised features of the guiding pattern; and
selectively removing one of the block materials of the assembled block patterns to define a pattern of fin structures by the remaining block material in the spaces between the raised features of the guiding pattern;
wherein the pattern of fin structures comprises a pattern of unbroken fin structures within the non-security region, and a pattern of broken fin structures within the security region;
wherein the broken fin structures comprise discontinuous regions that are formed due to a dissimilarity between the second distinct width and the natural pitch of the block materials of the self-assembling material.

US Pat. No. 10,141,338

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

International Business Ma...

1. A FinFET device comprising:a strain relaxation buffer (SRB) substrate;
a set of cut silicon fins on the SRB substrate, each fin in the set of cut silicon fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;
a set of cut silicon germanium fins on the SRB substrate, each fin in the set of silicon germanium fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;
a set of tensile dielectric structures, wherein respective ones of the tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins; and
a set of compressive dielectric structures, wherein respective ones of the compressive dielectric structure bridge between the short vertical faces of respective pairs of the cut silicon germanium fins to maintain compressive strain at the fin ends of the pair of cut silicon germanium fins.

US Pat. No. 10,141,337

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising a silicon semiconductor layer including a first channel formation region;
an insulating layer comprising a first nitride insulating layer and a second nitride insulating layer over the first transistor;
a second transistor comprising an oxide semiconductor layer including a second channel formation region over the insulating layer; and
a third nitride insulating layer over the second transistor,
wherein the second nitride insulating layer is between the first nitride insulating layer and the oxide semiconductor layer,
wherein a density of the second nitride insulating layer is higher than or equal to 2.75 g/cm3, and
wherein a density of the third nitride insulating layer is higher than or equal to 2.75 g/cm3.

US Pat. No. 10,141,336

POWER GATE SWITCHING SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. A power gate switching system, comprising:a first row including a first virtual power line, a first power gate cell and a second power gate cell, wherein the first power gate cell includes a first gate electrode disposed between first and second diffusion regions, and at least one tab, wherein the second power gate cell includes a second gate electrode disposed between third and fourth diffusion regions and does not include a tab; and
a second row including a second virtual power line, a third power gate cell and a fourth power gate cell, wherein the third power gate cell includes a third gate electrode disposed between fifth and sixth diffusion regions, and at least one tab, and the fourth power gate cell includes a fourth gate electrode disposed between seventh and eighth diffusion regions and does not include a tab, and
wherein the fourth power gate cell is connected to the second power gate cell.

US Pat. No. 10,141,335

SEMICONDUCTOR CIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in and end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each of the first-metal structures having at least one adjacent first-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers;
at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit.

US Pat. No. 10,141,334

SEMICONDUCTOR CHIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST-METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each gate structure in the region having a substantially rectangular shape with a width of less than or equal to about 45 nanometers and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate structure positioned thereon, wherein each pair of gate structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers, wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure in the region having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each first-metal structure in the region having at least one adjacent first-metal structure positioned next to each of its sides in accordance with a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers; and
at least six contact structures formed within the region of the semiconductor chip, wherein at least six gate structures within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six contact structures, each of the at least six contact structures having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structures positioned and sized to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein the logic circuit includes electrical connections that collectively include first-metal structures positioned on at least five of the at least eight first-metal gridlines.

US Pat. No. 10,141,331

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SUPPORT PILLARS UNDERNEATH A RETRO-STEPPED DIELECTRIC MATERIAL AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a memory array region and a terrace region;
memory stack structures extending through the memory array region of the alternating stack, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel contacting an inner sidewall of the respective memory film; and
support pillar structures extending through the terrace region of the alternating stack,
wherein the support pillar structures have different heights from each other;
wherein each of the support pillar structures has a respective topmost surface that is coplanar with a top surface of a respective one of the insulating layers in the alternating stack; and
wherein each of the support pillar structures comprises a dummy vertical semiconductor channel that is identical to the vertical semiconductor channels in material composition.

US Pat. No. 10,141,330

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES, SEMICONDUCTOR DEVICES, AND ELECTRONIC SYSTEMS

Micron Technology, Inc., ...

1. A method of forming a semiconductor device structure, comprising:forming a stack structure comprising stacked tiers, each of the stacked tiers comprising a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure;
forming a patterned hard mask structure over the stack structure;
forming dielectric structures within openings in the patterned hard mask structure;
forming a photoresist structure over the dielectric structures and the patterned hard mask structure;
subjecting the photoresist structure, the dielectric structures, and the stack structure to a series of material removal processes to selectively remove portions of the photoresist structure, portions of the dielectric structures not covered by remaining portions of the photoresist structure, and portions of the stack structure not covered by one or more of the patterned hard mask structure and the remaining portions of the photoresist structure to form apertures extending to different depths within the stack structure;
forming dielectric structures over side surfaces of the stack structure within the apertures, upper surfaces of the dielectric structures substantially coplanar with an upper surface of the patterned hard mask structure; and
forming conductive contact structures longitudinally extending to bottoms of the apertures.

US Pat. No. 10,141,329

METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A method for manufacturing a semiconductor memory device, comprising:forming, in a stacked body including a plurality of first layers and a plurality of second layers each of which is provided between the first layers, a plurality of first holes and a plurality of second holes in which a channel film is to be formed inside the first holes, the first holes and the second holes extending through the stacked body in a stacking direction of the stacked body and being arrayed in a first direction intersecting the stacking direction and in a direction oblique to the first direction;
etching a portion between the second holes next to each other in the stacked body to connect the second holes next to each other in the first direction and the second holes next to each other in the direction oblique to the first direction via the etched portion and form a trench in the stacked body.

US Pat. No. 10,141,328

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) memory device, comprising:a substrate;
a ridge-shaped stack, including a plurality of conductive strips stacked on the substrate along a first direction;
a memory layer, stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight angle with the first direction, and having a first narrow sidewall with a first long side extending along the first direction and a first narrow side extending along the second direction;
a channel layer, stacked on the memory layer along the second direction, the channel layer having a portion recessed in a third direction by an etch back process to form a second narrow sidewall having a second long side extending along the first direction and a second narrow side extending along the second direction, wherein the first narrow sidewall is separated from the second narrow sidewall along the third direction, and the third direction forms a non-straight angle with both the first direction and the second direction; and
a capping layer stacked on the second narrow sidewall along the third direction.

US Pat. No. 10,141,327

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a first insulating layer disposed on a semiconductor substrate;
a first semiconductor layer disposed on the semiconductor substrate;
a plurality of memory cells arranged three-dimensionally above the first insulating layer and disposed above the first semiconductor layer;
a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate;
a second insulating layer covering a side surface of a lowermost layer of the plurality of conductive layers;
an oxide layer disposed on a side surface of the first semiconductor layer and contacting the second insulating layer; and
a high permittivity layer provided between the first insulating layer and the second insulating layer, a permittivity of the high permittivity layer being higher than that of the first insulating layer and the high permittivity layer directly contacting the side surface of the first semiconductor layer.

US Pat. No. 10,141,326

SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a peripheral circuit element provided over a lower substrate;
an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element;
a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and
a plurality of transistors electrically coupling the gate lines to the peripheral circuit element,
the transistors comprising:
a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction;
a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and
gate dielectric layers disposed between the vertical channels and the gate electrode.