US Pat. No. 10,115,743

ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor comprising an oxide semiconductor layer including a channel region;
a third transistor;
an insulating layer including an opening over the first transistor, the second transistor, and the third transistor;
a color filter over the insulating layer;
a light-emitting element including a first electrode over the color filter; and
a capacitor;
a signal line; and
a power supply line;
wherein one of a source and a drain of the first transistor is directly connected to the signal line,
wherein the other one of the source and the drain of the first transistor is directly connected to a gate of the second transistor and one terminal of the capacitor,
wherein the other one terminal of the capacitor is directly connected to one of the source and the drain of the second transistor, one of a source and a drain of the third transistor, and the light-emitting element,
wherein the other one of the source and the drain of the second transistor is directly connected to the power supply line,
wherein the opening does not overlap with the color filter and an edge portion of the opening does not align with an edge portion of the color filter,
wherein the oxide semiconductor layer comprises In, Ga, and Zn, and
wherein the first electrode is directly connected to the one of the source and the drain of the second transistor through the opening.

US Pat. No. 10,115,742

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A transistor comprising:a first gate electrode;
an oxide semiconductor film, the oxide semiconductor film including a drain region;
a second gate electrode;
an insulating film over the oxide semiconductor film, the insulating film including an opening; and
a drain electrode over the insulating film, the drain electrode being in contact with the drain region in the opening,
wherein the first gate electrode and the second gate electrode are electrically connected to each other,
wherein, under a first condition, a difference between a minimum value and a maximum value of field-effect mobility of the transistor is less than or equal to 15 cm2/Vs, and
wherein the first condition is that voltages applied to the first gate electrode and the second gate electrode are in a range from 3 V to 10 V and a voltage applied to the drain region of the oxide semiconductor film is 20 V.

US Pat. No. 10,115,741

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first circuit comprising a first transistor and a capacitor electrically connected to a drain of the first transistor; and
a second circuit comprising a second transistor and a node electrically connected to a gate of the second transistor,
wherein:
the first transistor comprises a first semiconductor layer and a first back gate,
the second transistor comprises a second semiconductor layer,
the first circuit is configured to write data by turning on the first transistor, and to retain the data in the capacitor by turning off the first transistor,
the second circuit is configured to supply a potential at which the first transistor is turned off to the first back gate by turning on the second transistor, and to retain the potential in the node by turning off the second transistor, and
a threshold voltage of the second transistor is higher than a threshold voltage of the first transistor when a potential of the first back gate is set to the same as a potential of a source or a gate of the first transistor.

US Pat. No. 10,115,739

DISPLAY UNIT AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A display unit, comprising:a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor,
wherein one channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.

US Pat. No. 10,115,738

SELF-ALIGNED BACK-PLANE AND WELL CONTACTS FOR FULLY DEPLETED SILICON ON INSULATOR DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a back-plane, a p-well and an n-well formed within a bulk substrate;
a contact extending from each of the back-plane, the p-well and the n-well;
a gate structure formed above the back-plane, the p-well and the n-well;
at least one deep trench isolation (DTI) structure extending through the back-plane and the p-well and into the n-well; and
an insulating spacer isolating the contact of the back-plane from the gate structure and the at least one DTI structure.

US Pat. No. 10,115,737

CHARGE STORAGE REGION IN NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. A memory cell, comprising:a semiconductor channel;
a tunnel dielectric;
a charge storage region comprising: a first p-type silicon region adjacent the tunnel dielectric, a second p-type silicon region, an n-type silicon region between the first and second p-type silicon regions, a first dielectric region between the first p-type silicon region and the n-type silicon region, a second dielectric region between the n-type silicon region and the second p-type silicon region;
a conductive control gate; and
a control gate dielectric between the control gate and the charge storage region, the charge storage region being between the tunnel dielectric and the control gate dielectric, the second p-type silicon region being adjacent to the control gate dielectric.

US Pat. No. 10,115,736

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY DEVICES WITH SIDE SOURCE LINE AND MECHANICAL SUPPORT

SanDisk Technologies LLC,...

1. A method of fabricating a monolithic three dimensional memory structure, the method comprising:forming a stack of alternating word line and dielectric layers above a substrate;
forming a source line above the substrate;
forming a memory hole extending through the alternating word line and dielectric layers and the source line; and
forming a mechanical support element on the substrate adjacent to the memory hole, the mechanical support element extending through the source line.

US Pat. No. 10,115,735

SEMICONDUCTOR DEVICE CONTAINING MULTILAYER TITANIUM NITRIDE DIFFUSION BARRIER AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor device, comprising:a silicon surface;
a titanium silicide layer contacting the silicon surface;
a first titanium nitride layer located over the titanium silicide layer;
a titanium oxynitride layer contacting the first titanium nitride layer;
a second titanium nitride layer contacting the titanium oxynitride layer; and
a metallic fill material portion located over the second titanium nitride layer.

US Pat. No. 10,115,734

SEMICONDUCTOR DEVICE INCLUDING INTERLAYER SUPPORT PATTERNS ON A SUBSTRATE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a stack of interlayer support patterns on a substrate;
a stack of horizontal conductive patterns on the substrate and disposed laterally of the stack of interlayer support patterns;
an interlayer insulating layer interposed between vertically adjacent ones of the interlayer support patterns in the stack of interlayer support patterns, extending between vertically adjacent ones of the horizontal conductive patterns in the stack of horizontal conductive patterns, and disposed parallel to a surface of the substrate, the interlayer insulating layer being in contact with the vertically adjacent ones of the interlayer support patterns;
a conductive structure extending in a direction perpendicular to said surface of the substrate;
first vertical structures each extending vertically through the vertically adjacent ones of the horizontal conductive patterns and the interlayer insulating layer extending between the vertically adjacent ones of the horizontal conductive patterns; and
second vertical structures each extending vertically through the vertically adjacent ones of the interlayer support patterns and the interlayer insulating layer extending between the vertically adjacent ones of the interlayer support patterns,
wherein each of the first vertical structures and each of the second vertical structures includes a channel semiconductor layer extending in a direction perpendicular to the substrate.

US Pat. No. 10,115,733

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a connecting member having a through hole;
a first insulating film provided on the connecting member;
a stacked body provided on the first insulating film, the stacked body including electrode films and second insulating films, each of the electrode films and each of the second insulating films being alternately stacked;
a semiconductor pillar extending in a stacking direction of the electrode films and the second insulating films, piercing through the stacked body and the first insulating film, the semiconductor pillar being electrically connected to the connecting member;
a third insulating film provided between the semiconductor pillar and the stacked body; and
a support portion disposed in the through-hole of the connecting member.

US Pat. No. 10,115,732

THREE DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE SILICON NITRIDE CHARGE STORAGE REGIONS

SANDISK TECHNOLOGIES LLC,...

1. A structure comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
a memory stack structure extending through a memory opening in the alternating stack and comprising memory elements laterally surrounding a vertical semiconductor channel, wherein:
each of the memory elements comprise, from outside to inside, a blocking dielectric portion that is a region of a continuous blocking dielectric layer, a charge trapping material portion having a vertical sidewall portion and comprising silicon nitride, and a tunneling dielectric portion that is a region of a continuous tunneling dielectric layer directly contacting the continuous blocking dielectric layer, wherein a continuous interface between the continuous blocking dielectric layer and the alternating stack vertically extends through multiple electrically conductive layers of the alternating stack, and a continuous interface between the continuous tunneling dielectric layer and the vertical semiconductor channel vertically extends through the multiple electrically conductive layers of the alternating stack;
each of the insulating layers includes an upper recessed annular rim, a lower recessed annular rim, and an annular center portion located between the upper and lower recessed annular rims, wherein the annular center portion protrudes inward toward a vertical axis of the memory opening relative to the upper and lower recessed rims; and
each of the charge trapping material portions is vertically spaced from one another, and does not contact any other of the charge trapping material portions.

US Pat. No. 10,115,731

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer;
a stacked body including a plurality of electrode layers stacked on the interconnect layer,
a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and
an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body,
the semiconductor layer including a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region being in contact with the conductive layer.

US Pat. No. 10,115,730

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING STRUCTURALLY REINFORCED PEDESTAL CHANNEL PORTIONS AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface;
a memory opening extending through the alternating stack;
a pedestal channel portion located at a bottom portion of the memory opening, comprising a semiconductor material, and contacting a top surface of the semiconductor surface; and
a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film,
wherein:
a maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure, the entire interface includes all surfaces at which the pedestal channel portion directly contacts the memory stack structure; and
the maximum lateral extent of the pedestal channel portion is provided above a horizontal plane including a top surface of the bottommost electrically conductive layer among the electrically conductive layers or below a horizontal plane including a bottom surface of a bottommost electrically conductive layer.

US Pat. No. 10,115,729

ANTI-FUSE NONVOLATILE MEMORY DEVICES EMPLOYING LATERAL BIPOLAR JUNCTION TRANSISTORS AS SELECTION TRANSISTORS

SK Hynix Inc., Gyeonggi-...

1. An anti-fuse nonvolatile memory device comprising:an anti-fuse memory cell; and
a select transistor having a structure of bipolar junction transistor,
wherein the structure of bipolar junction transistor comprises;
a well region of a first conductivity type acting as a base region, the well region having first, second and third upper portions, the third upper portion of the well region being spaced apart from the second upper portion of the well region;
a first collector region of a second conductivity type disposed in the second upper portion of the well region, wherein an end of the second upper portion of the well region overlaps with an end of the first upper portion of the well region in a first direction;
an emitter region of the second conductivity type disposed in the third upper portion of the well region; and
a contact region of the first conductivity type disposed in the well region,
wherein the anti-fuse memory cell includes an anti-fuse insulation layer on a first upper portion of the well region and a gate stacked on the anti-fuse insulation layer; and
wherein the gate is coupled to a word line, the contact region is coupled to a well bias line, the emitter region is coupled to a bit line, and the first collector region is electrically floated.

US Pat. No. 10,115,728

LASER SPIKE ANNEALING FOR SOLID PHASE EPITAXY AND LOW CONTACT RESISTANCE IN AN SRAM WITH A SHARED PFET AND NFET TRENCH

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, the method comprising:forming a first semiconductor fin opposite a surface of a substrate;
forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin;
prior to forming a replacement metal gate (RMG), forming a first doped region over portions of the first semiconductor fin and a second doped region over portions of the second semiconductor fin;
forming a dielectric layer over the first and second doped regions;
after forming the RMG, forming a shared trench in the dielectric layer exposing portions of the first and second doped regions;
concurrently amorphizing the exposed first and second doped regions; and
concurrently recrystallizing the amorphized first and second doped regions.

US Pat. No. 10,115,727

METHOD FOR MANUFACTURING A MICROELECTRONIC CIRCUIT AND CORRESPONDING MICROELECTRONIC CIRCUIT

Fraunhofer-Gesellschaft z...

1. A method for manufacturing a microelectronic circuit, comprising:providing a substrate,
producing a source contact, a bulk contact and a drain contact each for a transistor and for a memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing the metal layer and the insulating layer of the memory transistor as parts of a MOS capacitor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing a gate contact connected to a metal layer of the capacitor of the memory transistor.

US Pat. No. 10,115,726

METHOD AND SYSTEM FOR FORMING MEMORY FIN PATTERNS

Tokyo Electron Limited, ...

1. A method for patterning a substrate, the method comprising:forming a multi-line layer above a memorization layer on a substrate, the multi-line layer including a region having a pattern of alternating lines of three materials that differ chemically from each other by having different etch resistivities relative to each other, the three materials include material A, material B, and material C, the pattern of alternating lines of three materials includes a repeating sequence of A-B-C-B-A-B-C-B in that materials alternate in a direction parallel to a working surface of the substrate, each line of material extending from a top surface of the multi-line layer to a bottom surface of the multi-line layer;
forming a first etch mask above the multi-line layer, the first etch mask defining first trenches that uncover a first portion of the multi-line layer such that defined first trenches elevationally intersect multiple lines from the pattern of alternating lines;
etching through uncovered portions of material A and portions of the memorization layer directly underneath the uncovered portions of material A using the first etch mask;
forming a second etch mask above the multi-line layer, the second etch mask defining second trenches that uncover a second portion of the multi-line layer such that defined second trenches elevationally intersect multiple lines from the pattern of alternating lines;
etching through uncovered portions of material C and portions of the memorization layer directly underneath the uncovered portions of material C using the second etch mask; and
etching through material B and portions of the memorization layer directly underneath material B while the multi-line layer is uncovered.

US Pat. No. 10,115,725

STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS

International Business Ma...

1. A device, comprising:a semiconductor-on-insulator (SOI) substrate having an SOI layer, a BOX layer and a substrate layer;
a pad nitride layer deposited on a top surface of the SOI layer;
a trench formed in the SOI substrate, wherein the trench extends into the substrate layer;
a node dielectric layer deposited on a bottom and sidewalls of the first trench;
a liner layer deposited on the node dielectric layer;
a first conductive material deposited in the trench, wherein a top surface of the first conductive material is below a bottom surface of the SOI layer and above a top surface of the substrate layer, wherein a top surface of the node dielectric layer and a top surface of the liner layer are coplanar with the top surface of the first conductive material; and
a second conductive material deposited on the top surface of the first conductive material, wherein a top surface of the second conductive material is below the top surface of the SOI layer and below a bottom surface of the pad nitride layer.

US Pat. No. 10,115,724

DOUBLE DIFFUSION BREAK GATE STRUCTURE WITHOUT VESTIGIAL ANTENNA CAPACITANCE

International Business Ma...

1. A semiconductor structure comprising:a double diffusion break region located between a first device region and a second device region, wherein the double diffusion break region includes a sacrificial gate material and wherein an interlevel dielectric material is present adjacent to each side of the sacrificial gate material and beneath at least a portion of the sacrificial gate material.

US Pat. No. 10,115,723

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES EMPLOYING PLASMA-DOPED SOURCE/DRAIN STRUCTURES AND RELATED METHODS

QUALCOMM Incorporated, S...

1. A complementary metal oxide semiconductor (CMOS) device, comprising:a substrate;
a semiconductor material structure disposed above the substrate, the semiconductor material structure comprising one or more channel structures, each channel structure comprising:
a semiconductor material having a first end portion and a second end portion;
a source in the first end portion, the source comprising a first plasma-doped portion comprising a dopant above a solid state solubility of the semiconductor material structure of the semiconductor material at the first end portion;
a drain in the second end portion of the semiconductor material, the drain comprising a second plasma-doped portion comprising a dopant above the solid state solubility of the semiconductor material structure of the semiconductor material at the second end portion; and
a channel disposed between the source and the drain; and
a gate material disposed adjacent to the channel.

US Pat. No. 10,115,722

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a plurality of logic cells disposed along a first direction;
active patterns protruding from the substrate; and
a device isolation layer on the substrate, the device isolation layer including a first double diffusion break region that has a first width, as measured along the first direction, and is disposed between a pair of adjacent logic cells and a second double diffusion break region that has a second width, as measured along the first direction, greater than the first width and is disposed between another pair of adjacent logic cells,
wherein the active patterns comprise:
a plurality of pairs of first active patterns spaced apart from each other along the first direction with the first double diffusion break region interposed therebetween; and
a plurality of pairs of second active patterns spaced apart from each other along the first direction with the second double diffusion break region interposed therebetween,
wherein the first active patterns comprise first end portions that are adjacent to a side of the first double diffusion break region and are aligned along a second direction crossing the first direction, and
wherein the second active patterns comprise second end portions that are adjacent to a side of the second double diffusion break region, and wherein one of the second end portions is offset from another of the second end portions along the first direction.

US Pat. No. 10,115,720

INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

10. A manufacturing method for a semiconductor device, the method comprising:providing a substrate comprising a first region and a second region;
forming a thick gate insulating layer on the first region;
forming a gate electrode on the thick gate insulating layer;
performing a wet etching process on the thick gate insulating layer disposed outside the gate electrode such that a thin buffer insulating layer is formed adjacent to the thick gate insulating layer, located outside of the gate electrode;
performing a sidewall oxidation of the gate electrode:
forming an LDD region in the substrate; and
forming a first spacer on the thin buffer insulating layer.

US Pat. No. 10,115,719

INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME

GLOBALFOUNDRIES, Inc., G...

1. A method for fabricating an integrated circuit, the method comprising:providing a semiconductor substrate with a resistor area and a capacitor area;
depositing a conductive capacitor material over the resistor area and the capacitor area of the semiconductor substrate;
forming a resistor structure from the conductive capacitor material in the resistor area;
forming electrical connections to the resistor structure in the resistor area; and
forming a resistor shield around the resistor structure in the resistor area, wherein the resistor shield includes a first shield portion and a second shield portion, and wherein the resistor structure is located directly between the first shield portion and the second shield portion.

US Pat. No. 10,115,718

METHOD, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor device, comprising:a semiconductor substrate;
a field-effect transistor (FET) comprising a gate disposed on the semiconductor substrate, a source disposed on or in the semiconductor substrate, and a drain disposed on or in the semiconductor substrate, wherein the gate, the source, and the drain extend parallel to each other in a first horizontal direction;
at least one source electrostatic discharge (ESD) protection circuit comprising a source contact disposed on the source at a first location, and a first source ballasting resistor, wherein said source ballasting resistor comprises a first source conductive element disposed on the source contact and extending in a second horizontal direction perpendicular to the first horizontal direction between a position above the first location and a position above a second location, wherein the second location is on the drain;
a source terminal disposed above and in electrical contact with the first source ballasting resistor, wherein the source terminal extends in the first direction;
at least one drain ESD protection circuit comprising a first drain ballasting resistor; and
a drain terminal disposed above and in electrical contact with the first drain ballasting resistor, wherein the drain terminal extends in the first horizontal direction.

US Pat. No. 10,115,716

DIE BONDING TO A BOARD

SEMICONDUCTOR COMPONENTS ...

1. A method of bonding a plurality of die having a plurality of metal layers on a die surface to a board or metal lead frame, comprising:placing a first die onto a solderable surface of the board or the metal lead frame, the first die comprising at least three metal layers, the board comprising one of a ceramic board or substrate board, or a metal lead frame wherein a top metal die layer is disposed against the solderable surface of the first die;
first reflowing at least one of first and second metal die layers of the first die at a first reflow temperature in a range of 220 degrees C. to 260 degrees C. for a first period to form a first alloy to create a bond between the first die and the board or metal lead frame; and
maintaining heat at the first reflow temperature for a second period to reflow the board or metal lead frame and the first and second metal die layers to form a second alloy
placing a second die onto the solderable surface of the board or the metal lead frame, the second die comprising at least three metal layers, wherein a top metal die layer is disposed against the solderable surface of the second die;
second reflowing at least one of first and second metal die layers of the second die at the first reflow temperature in the range of 220 degrees C. to 260 degrees C. for the first period to form the first alloy to create a bond between the second die and the board or metal lead frame; and
maintaining heat at the first reflow temperature for the second period to reflow the board or metal lead frame and the first and second metal die layers of the second die to form the second alloy,
wherein the first and second alloys have melting temperature temperatures that are higher than 260 degrees C.

US Pat. No. 10,115,715

METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES

Micron Technology, Inc., ...

1. A method of fabricating a semiconductor device package, comprising:providing a fan out wafer comprising semiconductor-device-package locations at a base level, each semiconductor-device-package location comprising:
at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the at least two mutually spaced semiconductor dice and extending between adjacent semiconductor-device-package locations; and
electrically conductive traces extending over active surfaces of the at least two semiconductor dice and laterally beyond peripheries of the at least two semiconductor dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric material;
stacking laterally offset semiconductor dice on at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice;
electrically connecting the laterally offset semiconductor dice to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations by forming wire bonds extending from a respective bond pad of an overlying semiconductor die of the laterally offset semiconductor dice to an adjacent bond pad of an underlying semiconductor die of the laterally offset semiconductor dice and by forming a wire bond extending from a respective bond pad of a lowest semiconductor die of the laterally offset semiconductor dice to an adjacent via of the electrically conductive vias or to an adjacent trace of the electrically conductive traces; and
singulating the semiconductor-device-package locations having stacks of semiconductor dice thereon from the fan out wafer.

US Pat. No. 10,115,714

SEMICONDUCTOR DEVICE AND OPTICAL COUPLING DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a substrate having a first surface side and a second surface side opposite the first surface side, the first surface side including a first surface region at a first end of the substrate in a first direction and a second surface region on a second end of the substrate in the first direction opposite the first end;
a wiring pattern on the second surface side of the substrate;
a first terminal and a second terminal on the substrate in the first surface region;
a third terminal and a fourth terminal on the substrate in the second surface region;
a first semiconductor element having a first surface, the first semiconductor element being bonded to the substrate on the first surface side between the first and second surface regions;
a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element;
a first bonding wire connecting the first terminal and anode terminal of the second semiconductor element;
a second bonding wire connecting the second terminal and a cathode terminal of the second semiconductor element;
a third semiconductor element bonded to the substrate on the first surface side between the first semiconductor element and the second surface region;
a third bonding wire connecting the first semiconductor element and the third semiconductor element, the third bonding wire being connected to a pad on the first surface of the first semiconductor element;
a silicone gel covering an upper surface of the second semiconductor element and contacting a portion of the first surface of the first semiconductor device; and
a resin portion covering the silicone gel, the first semiconductor element, the third semiconductor element, the first bonding wire, the second bonding wire, the third bonding wire, the first surface region, and the second surface region, wherein
the resin portion has a durometer-measured hardness greater than a durometer-measured hardness of the silicone gel,
the first semiconductor element includes a light receiving element facing the first surface of the first semiconductor element,
the second semiconductor element includes a light emitting element that emits light at the lower surface of the second semiconductor element, and
the silicone gel is opaque at a wavelength of light emitted by the light emitting element.

US Pat. No. 10,115,711

VERTICAL LIGHT EMITTING DIODE WITH MAGNETIC BACK CONTACT

International Business Ma...

1. A structure comprising:an opening located in a display substrate;
a first contact structure lining at least one sidewall of the opening and a bottom wall of the opening and present on a topmost surface of the display substrate;
a first magnetic material located on a portion of the first contact structure that is located on the bottom wall of the opening;
a second magnetic material located on a surface of the first magnetic material;
a vertical light emitting diode located on a surface of the second magnetic material and having a topmost surface that is located entirely below a topmost surface of the first contact structure that is located on the topmost surface of the display substrate; and
a pair of second contact structures, wherein one of the pair of second contact structures is in direct contact with a topmost surface of the vertical light emitting diode, and another of the pair of second contact structures is in direct contact with a surface of the first contact structure.

US Pat. No. 10,115,710

PACKAGE INCLUDING A PLURALITY OF STACKED SEMICONDUCTOR DEVICES, AN INTERPOSER AND INTERFACE CONNECTIONS

1. A package, comprising:a first dynamic random access memory (DRAM) semiconductor device, a second DRAM semiconductor device, and a third DRAM semiconductor device stacked in a first direction above a first surface of an interposer;
a first wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and a second surface, opposite the first surface, of the interposer;
a first external connection formed on the second surface of the interposer, the first wiring electrically connected at a central portion of the first external connection, the first external connection configured to receive a first power supply potential;
the first DRAM semiconductor device includes a first through via, the first through via providing an electrical connection between a first surface and a second surface of the first DRAM semiconductor device;
the second DRAM semiconductor device includes a second through via, the second through via providing an electrical connection between a first surface and a second surface of the second DRAM semiconductor device;
the third DRAM semiconductor device includes a third through via, the third through via providing an electrical connection between a first surface and a second surface of the third DRAM semiconductor device;
a first interface connection formed between the first DRAM semiconductor device and the second DRAM semiconductor device providing an electrical connection between the first and second through vias;
a second interface connection formed between the second DRAM semiconductor device and the third DRAM semiconductor device providing an electrical connection between the second and third through vias;
a third interface connection formed between the interposer and the first DRAM semiconductor device providing an electrical connection between the first wiring and the first through via, the first wiring providing an electrical connection between the third interface connection and the first external connection;
a second wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and the second surface, opposite the first surface, of the interposer; and
a second external connection formed on the second surface of the interposer, the second wiring electrically connected at a central portion of the second external connection, the second external connection configured to receive a first data signal.

US Pat. No. 10,115,709

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first chip and a second chip; each of the first and second chips comprising:
a multilevel wiring structure including a first level wiring layer, a second level wiring layer and an insulating film between the first level wiring layer and the second level wiring layer; and
a redistribution wiring layer over the multilevel wiring structure, the redistribution wiring layer including a redistribution wiring and a pad electrically coupled to the redistribution wiring;
wherein the first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip, and the pad of the first chip faces the pad of the second chip; the pad of the first chip being vertically spaced from the pad of the second chip by an intervening insulative region; the redistribution wiring of the second chip being electrically coupled to the redistribution wiring of the first chip through a bonding region; the pad of the first chip being electrically coupled to the pad of the second chip through the redistribution wiring of the first chip and the redistribution wiring of the second chip; and
wherein:
the first redistribution wiring includes first bonding pads;
the second redistribution wiring includes second bonding pads;
the first bonding pads are not overlapped by the second chip;
the second bonding pads are not overlapped by the first chip; and
the first chip is shifted relative to the second chip by a distance “a”, wherein the bonding region includes a first coupling region from the first chip and second coupling region from the second chip; and wherein the first coupling region is offset from the pad of the first chip by a distance of a/2, and the second coupling region is offset from the pad of the second chip by the distance of a/2.

US Pat. No. 10,115,708

SEMICONDUCTOR PACKAGE HAVING A REDISTRIBUTION LINE STRUCTURE

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip having first bonding pads which are arranged in two rows on a middle portion of a first active surface;
a second semiconductor chip having substantially the same size as the first semiconductor chip, and having second bonding pads which are arranged in two rows on a middle portion of a second active surface;
redistribution lines formed on the first active surface, and corresponding to the first bonding pads, respectively, the redistribution lines each having a redistribution line pad, a wire bonding pad, and coupling lines electrically coupling the redistribution line pad, the wire bonding pad and the corresponding first bonding pad; and
bumps formed on the second bonding pads of the second semiconductor chip, respectively,
wherein the location of the second bonding pads in relation to the second semiconductor chip is the same as the location of the corresponding first bonding pads in relation to the first semiconductor chip,
wherein the first semiconductor chip and the second semiconductor chip are stacked such that the first active surface and the second active surface face each other, and are disposed to be offset from each other, and
wherein the bumps are bonded to the redistribution line pads of the redistribution lines, respectively.

US Pat. No. 10,115,707

ADHESIVE FILM AND SEMICONDUCTOR PACKAGE USING ADHESIVE FILM

FURUKAWA ELECTRIC CO., LT...

1. An adhesive film, which comprises: (A) a bismaleimide resin; (B) a radical initiator; and (C) a coupling agent that contains a (meth)acrylic group, wherein at least one of the following applies:(1) radical initiator (B) has a one-hour half-life temperature of 140° C. or higher, or
(2) a filler (D) is present, having a content of 75 percent or higher by mass based on 100 percent by mass in the adhesive film.

US Pat. No. 10,115,706

SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor chip comprising a plurality of input/output units, the semiconductor chip comprising:a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads comprise at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and
a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads comprise at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further comprise a third pad through which a signal is input and/or output,
wherein the at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units, and
wherein, when the plurality of additional pads comprise the first additional pad and the plurality of pads comprise the first pad, the first additional pad is electrically connected to the first pad through an internal interconnection underneath the surface.

US Pat. No. 10,115,705

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor package comprising:a first semiconductor device electrically connected to a second semiconductor device, wherein:
the first semiconductor device comprises a first surface, and the first surface comprises at least a first portion and a second portion that does not overlap with the first portion, wherein the first portion is a portion of the first surface that is not under the second semiconductor device; a first encapsulant material surrounding side edges of the first semiconductor device; a first dielectric layer above the first encapsulant material and the first portion; at least one redistribution layer (RDL) above the first dielectric layer; a second dielectric layer above the at least one RDL and the second portion, wherein:
a maximum thickness of the second dielectric layer above the second portion and adjacent to the second semiconductor device is less than a sum of the thicknesses of the first dielectric layer above the first portion, the at least one RDL, and the second dielectric layer above the at least one RDL; and
a passivation layer directly above the first surface, wherein:
the passivation layer directly contacts both the first dielectric layer and the first surface, and
the passivation layer directly contacts both the second dielectric layer and the first surface.

US Pat. No. 10,115,704

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode;
a second semiconductor chip having a third surface that faces the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface, and a third electrode on the fourth surface;
a metal wire that electrically connects the third electrode to the first electrode;
a first insulating layer that is on the second surface of the first semiconductor chip and includes a first opening;
a first conductive layer that is in the first opening and on a part of the first insulating layer and is electrically connected to the second electrode;
a second conductive layer that is directly in contact with the first conductive layer;
a second insulating layer that is on the first insulating layer and the second conductive layer and includes a second opening;
a third conductive layer that is in the second opening and is electrically connected to the second conductive layer; and
a first external terminal in direct contact with the third conductive layer, wherein
no wiring substrate is present between the first semiconductor chip and the first external terminal.

US Pat. No. 10,115,703

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first semiconductor substrate;
a second semiconductor substrate facing the first semiconductor substrate;
a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;
a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;
a first insulating layer disposed on an edge portion of the first semiconductor substrate and the first pad electrode;
a second insulating layer disposed on an edge portion the second semiconductor substrate and the second pad electrode;
a base metal layer disposed on the second insulating layer and a center portion of the second pad electrode, the base metal layer having a stepped first surface and a planar second surface opposite the stepped first surface;
a first metal layer disposed over the first semiconductor substrate and facing the second semiconductor substrate;
a second metal layer disposed on the base metal layer and facing the first metal layer, the second metal layer having a planar first surface in contact with the base metal layer, and a planar second surface opposite the planar first surface;
a third metal layer disposed between the first metal layer and the second metal layer;
a first alloy layer disposed between the first metal layer and the third metal layer comprising a component of the first metal layer and a component of the third metal layer; and
a second alloy layer disposed between the second metal layer and the third metal layer, comprising a component of the second metal layer and a component of the third metal layer,
wherein the first metal layer includes a stepped surface adjacent to and in contact with the first alloy layer, the stepped surface of the first metal layer including edge portions that extend beyond a central portion thereof.

US Pat. No. 10,115,702

SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor system comprising:a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor; and
a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information, the second temperature sensor configured to generate a control signal based on the first temperature information and temperature measured by the second temperature sensor, the control signal adjusting an operation performed on the second chip, wherein
the second chip is a dynamic random access memory (DRAM) chip, and
the control signal is configured to determine a self-refresh interval of the DRAM chip.

US Pat. No. 10,115,699

METHOD FOR MANUFACTURING WIRE BONDING STRUCTURE, WIRE BONDING STRUCTURE, AND ELECTRONIC DEVICE

ROHM CO., LTD., Kyoto (J...

12. A wire bonding structure comprising:a first joining target having a first surface;
a second joining target; and
a wire joined to both the first joining target and the second joining target,
wherein the wire is made of Cu and has a circular cross-sectional shape with a diameter of 150 to 1000 ?m, the circular cross-sectional shape having a curvature depending on the diameter,
the wire includes a bonding part joined to the first joining target,
the bonding part has an outer circumferential surface and a joining surface joined to the first joining target,
the joining surface is withdrawn toward a central axis of the wire from the outer circumferential surface and elongated along the central axis,
in a cross-section perpendicular to the central axis of the wire, the bonding part comprises first, second and third arcs spaced apart from each other about the central axis,
the first arc is disposed opposite to the joining surface with respect to the central axis, and the second arc and the third arc are spaced apart from each other via the joining surface, and
each of the first, the second and the third arcs has a curvature that is equal to the curvature of the circular cross-sectional shape of the wire.

US Pat. No. 10,115,692

METHOD OF FORMING SOLDER BUMPS

International Business Ma...

1. A method of forming solder bumps, the method includes:preparing a substrate having a surface on which a plurality of electrode pads are formed;
forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads;
forming a conductive pillar in each of the openings of the resist layer;
forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer;
filling molten solder in each of the openings in which the conductive layers has been formed, wherein the conductive layers include metals having a same composition ratio as a composition ratio of metals of the molten solder; and
removing the resist layer.

US Pat. No. 10,115,686

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor structure, comprising:forming a conductive layer on a first insulating layer;
etching a portion of the conductive layer to expose a portion of the first insulating layer;
deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and
removing a residue of the conductive layer from the rough surface of the first insulating layer.

US Pat. No. 10,115,685

METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:providing a transceiver;
forming a molding to surround the transceiver;
forming a plurality of recesses extending through the molding;
disposing a conductive material into the plurality of recesses to form a plurality of vias;
disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver; and
forming a redistribution layer (RDL) over the insulating layer;wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.

US Pat. No. 10,115,684

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a first semiconductor chip comprising:
a first plurality of wiring layers;
a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and
a first resin film formed over the uppermost layer of the first plurality of the wiring layers, a thickness of the first resin film being uniform between the first coil and the first dummy wires, and over top surfaces of the first coil and the first dummy wires; and
a second semiconductor chip comprising:
a second plurality of wiring layers;
a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers; and
a second resin film formed over the uppermost layer of the second plurality of the wiring layers, a thickness of the second resin film being uniform between the second coil and the second dummy wires, and over top surfaces of the second coil and the second dummy wires,
wherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet,
wherein the first dummy wires are isolated from each other,
wherein the second dummy wires are isolated from each other, and
wherein the first coil and the second coil are magnetically coupled with each other.

US Pat. No. 10,115,683

ELECTROSTATIC DISCHARGE PROTECTION FOR ANTENNA USING VIAS

NXP USA, Inc., Austin, T...

1. An antenna comprising:a metal patch comprising a metal region on one side of a first centerline of the metal patch;
a ground plane; and
a plurality of vias, each of the plurality of vias connected to the ground plane and wherein the plurality of vias is disposed only in the metal region and symmetrically about a second centerline of the metal patch.

US Pat. No. 10,115,682

ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY

EMEMORY TECHNOLOGY INC., ...

1. An erasable programmable non-volatile memory, comprising:a first transistor comprising a select gate, a first doped region and a second doped region, wherein the select gate is connected with a word line, and the first doped region is connected with a source line;
a second transistor comprising the second doped region, a third doped region and a floating gate, wherein the third doped region is connected with a bit line, the first transistor and the second transistor are n-type transistors, and the first doped region, the second doped region and the third doped region are n-type doped regions;
an erase gate region connected with an erase line, wherein the floating gate is extended over and located near the erase gate region; and
a metal layer disposed over the floating gate and connected with the bit line;
wherein the first transistor and the second transistor are constructed in a p-well region, and the erasable programmable non-volatile memory further comprises a deep n-well region between the p-well region and a p-type substrate.

US Pat. No. 10,115,681

COMPACT THREE-DIMENSIONAL MEMORY DEVICE HAVING A SEAL RING AND METHODS OF MANUFACTURING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor die, comprising:a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate;
groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film;
a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, wherein each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers; and
at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.

US Pat. No. 10,115,680

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a substrate;
a first stacked body provided in a first region on the substrate, and including a first insulating film and an electrode film stacked alternately on one another;
a columnar part provided in the first stacked body, extending in a stacking direction of the first stacked body, and including a connection part widened in width in a first direction along an upper surface of the substrate;
a second insulating film provided in a second region on the substrate, and having a first thickness in the stacking direction; and
a second stacked body provided on the second insulating film, and including a first film and a third insulating film stacked alternately on one another,
an uppermost first film in the second stacked body being located at a first distance in the stacking direction from the upper surface of the substrate, and
the first thickness is not less than 30 percent of the first distance.

US Pat. No. 10,115,679

TRENCH STRUCTURE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A trench structure comprising:a top metal layer;
a silicon carbide (SiC) layer on the top metal layer;
a first passivation layer overlying the SiC layer; and
a second passivation layer overlying the first passivation layer,
wherein
a first sidewall of the trench structure, a second sidewall of the trench structure, and the top metal layer form a trench, and
at least one of the first sidewall or the second sidewall comprises:
a sidewall of the SiC layer; and
a sidewall of the second passivation layer,
wherein a portion of the second passivation layer is between the first passivation layer and the at least one of the first sidewall or the second sidewall.

US Pat. No. 10,115,678

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Invensas Corporation, Sa...

1. An apparatus, comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;
a first and a second microelectronic device coupled to the upper surface of the substrate;
an EMI shield covering the first microelectronic device, the EMI shield comprising at least one side portion and a top portion, the at least one side portion including wire bond wires having first ends bonded to the bond pads, the wire bond wires arranged in a preselected manner for one or more frequencies associated with an interference, the wire bond wires positioned on at least one side of the first microelectronic device to shield the interference relative to the first microelectronic device; and
the second microelectronic device located in a region not covered by the EMI shield.

US Pat. No. 10,115,677

VERTICAL INTERCONNECTS FOR SELF SHIELDED SYSTEM IN PACKAGE (SIP) MODULES

Apple Inc., Cupertino, C...

9. A semiconductor device package, comprising:a substrate;
one or more terminals coupled to a lower surface of the substrate;
a first device coupled to an upper surface of the substrate;
a second device coupled to the upper surface of the substrate;
a ground ring coupled to the lower surface of the substrate, the ground ring being electrically coupled to at least one of the terminals coupled to the lower surface of the substrate;
a plurality of conductive structures individually attached to the upper surface of the substrate, wherein at least one of the conductive structures is electrically coupled to the ground ring, wherein the plurality of conductive structures at least partially surround the first device on the upper surface of the substrate, and wherein at least one conductive structure is located between the first device and the second device on the upper surface of the substrate; and
a shield positioned above the first device, the second device, and the conductive structures, the shield being electrically coupled to at least one of the conductive structures electrically coupled to the ground ring.

US Pat. No. 10,115,676

INTEGRATED CIRCUIT AND METHOD OF MAKING AN INTEGRATED CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An integrated circuit comprising:a semiconductor substrate; and
a metallization stack located on a major surface of the semiconductor substrate, the metallization stack comprising a plurality of metal layers including patterned metal features, wherein each metal layer of the metallization stack is separated by an intervening dielectric layer,
wherein the metallization stack forms a first grid including patterned metal features for supplying power and providing signal connections to components of the integrated circuit located in the semiconductor substrate, and
wherein the metallization stack also forms a second grid for securing the integrated circuit against electromagnetic attacks, wherein the second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack, and wherein the patterned metal features of the second grid are electrically connected to the first grid.

US Pat. No. 10,115,675

PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A PACKAGED SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A packaged semiconductor device, comprising:a first package structure having a first cut edge, wherein the first package structure comprises a die, a molding compound and at least one outer via, the die and the outer via are encapsulated by the molding compound, and the outer via penetrates the molding compound;
at least one outer conductive bump disposed on the first package structure and having a second cut edge;
a second package structure jointed onto the first package structure;
a sealing material disposed on the first package structure, surrounding the second package structure, and covering the outer conductive bump, wherein the sealing material has a third cut edge and the sealing material is in physical contact with the outer conductive bump; and
an electromagnetic interference (EMI) shielding layer disposed over the first cut edge, the second cut edge, and the third cut edge, and being in electrical contact with the outer conductive bump, wherein the EMI shielding layer is electrically connected with the outer via through the outer conductive bump.

US Pat. No. 10,115,674

SEMICONDUCTOR DEVICE INCLUDING ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING LAYER AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor device, comprising:providing a substrate having a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface;
providing a semiconductor chip on the first surface;
forming a resin portion that seals the semiconductor chip;
forming a conductive film on an upper surface of the resin portion and a side surface of the resin portion, the conductive film being electrically connectable to a ground potential source; and
forming a film stack including a first film that is a metal oxide film formed by depositing metal in an oxygen containing environment or a metal nitride film formed by depositing metal in a nitrogen containing environment, wherein
a lightness value of the film stack is less than a lightness value of the resin portion.

US Pat. No. 10,115,673

EMBEDDED SUBSTRATE PACKAGE STRUCTURE

1. An embedded substrate package structure, comprising: a first substrate being disposed with a plurality of first through holes, and having an upper surface and a lower surface disposed respectively with a first upper wire layer and a first lower wire layer, the first upper wire layer and the first lower wire layer being electrically connected by the plurality of first through holes;a first dielectric layer covering the first lower wire layer on the lower surface of the first substrate, and having a plurality of openings located at a position of the first lower wire layer to expose a portion of a surface of the first lower wire layer, and the exposed surface being disposed with a conductive bump;
a second dielectric layer covering the first upper wire layer on the upper surface of the first substrate, and having a plurality of openings located at a position of the first upper wire layer to expose a portion of a surface of the first upper wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy;
a second substrate being disposed with at least a cavity and a plurality of second through holes, the at least a cavity being for accommodating a chip, and the second substrate having an upper surface and a lower surface disposed respectively with a second upper wire layer and a second lower wire layer;
a third dielectric layer covering the second lower wire layer on the lower surface of the second substrate, and having a plurality of openings located at a position of the second lower wire layer to expose a portion of a surface of the second lower wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy;
a fourth dielectric layer covering the second upper wire layer and the chip, serving as a protective layer of the back of the chip, and having a plurality of openings located at a position of the second upper wire layer to expose a portion of a surface of the second upper wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy; and
a fifth dielectric layer covering surroundings of the chip to fill gaps between the chip and the cavity and fixing the chip to inside of the cavity, wherein the second dielectric layer and the third dielectric layer respectively have a plurality of openings at positions of the cavity, inside of the plurality of openings being disposed with an under bump metallurgy or a solder bump, and a conductive bump or a solder bump is formed on a pad of the chip, the chip being disposed in the cavity and electrically connected to the first upper wire layer of the first substrate through the conductive bump or the solder bump.

US Pat. No. 10,115,671

INCORPORATION OF PASSIVES AND FINE PITCH THROUGH VIA FOR PACKAGE ON PACKAGE

SnapTrack, Inc., San Die...

1. A package-on-package comprising:a bottom package vertically integrated with a second package, wherein
the bottom package includes a first die, a glass via bar, and a package substrate, wherein the first die and the glass via bar are attached to the same side of the package substrate, wherein the first die is oriented laterally to the glass via bar on the package substrate, and wherein the first die and the glass via bar are each electrically coupled to the package substrate by distinct electrical connections;
the second package includes a second die; and
the first die is configured to be in electrical communication with the second die through the glass via bar, wherein the glass via bar includes an amorphous silicate glass sidewall surface that extends through a thickness of the glass via bar and wherein the glass via bar includes an integrated passive component, wherein the integrated passive component is disposed on one or more surfaces of the glass via bar or is embedded within the glass via bar.

US Pat. No. 10,115,670

FORMATION OF ADVANCED INTERCONNECTS INCLUDING SET OF METAL CONDUCTOR STRUCTURES IN PATTERNED DIELECTRIC LAYER

International Business Ma...

1. A method for fabricating an advanced metal conductor structure comprising:providing a pattern in a dielectric layer, wherein the pattern includes a set of features in the dielectric layer for a set of metal conductor structures, the set of features having a first dimension;
creating an adhesion promoting layer disposed over the patterned dielectric layer;
depositing a ruthenium layer disposed on the adhesion promoting layer;
depositing a cobalt layer over the ruthenium layer;
performing a high temperature thermal anneal which creates a ruthenium cobalt alloy layer to cover surfaces of the set of features; wherein a portion of the cobalt layer is unreacted with the ruthenium layer after the high temperature thermal anneal producing unreacted cobalt;
etching the unreacted cobalt from the ruthenium cobalt alloy layer; and
depositing a metal layer disposed on the ruthenium cobalt alloy layer to form the set of metal conductor structures.

US Pat. No. 10,115,669

HIGH DENSITY NONVOLATILE MEMORY CELL UNIT ARRAY

Sony Semiconductor Soluti...

1. A memory cell unit array, comprisingmemory cell units arranged in a two-dimensional matrix form in a first direction and a second direction, the memory cell units being each constituted of
a plurality of first wires extending in the first direction,
a plurality of second wires that are disposed separately from the first wires in upper and lower directions and extend in the second direction unlike the first wires, and
a nonvolatile memory cell that is disposed in a region in which the first wires and the second wires overlap one another and connected to the first wires and the second wires, wherein
each of the memory cell units includes, below the memory cell unit, a control circuit that controls an operation of the memory cell unit,
the control circuit is constituted of
a first control circuit that controls an operation of the nonvolatile memory cell that constitutes the memory cell unit via the first wires, and
a second control circuit that controls an operation of the nonvolatile memory cell that constitutes the memory cell unit via the second wires,
the second wires that constitute the memory cell unit are connected to the second control circuit that constitutes the memory cell unit,
some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes the memory cell unit, and
others of the first wires that constitute the memory cell unit are connected to a first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.

US Pat. No. 10,115,668

SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS

Intel IP Corporation, Sa...

1. A semiconductor package, comprising:an integrated circuit die encapsulated in a mold compound, the integrated circuit die having an exposed surface co-planar with a surface of the mold compound;
a dielectric layer having a front surface and a back surface opposite from the front surface, wherein one or more openings extend from the front surface to the back surface, wherein the front surface of the dielectric layer is on the co-planar exposed surface of the integrated circuit die and on the surface of the mold compound; and
a redistribution layer on the back surface, wherein the redistribution layer includes a plurality of first conductive traces, the plurality of first conductive traces immediately adjacent to each other and having a first thickness and a first pitch, and wherein the redistribution layer includes a plurality of second conductive traces, the plurality of second conductive traces immediately adjacent to each other and having a second thickness and a second pitch, and wherein the first thickness is different than the second thickness and both thicknesses are measured in a same direction normal to the exposed surface of the integrated circuit die, and wherein the first pitch is different than the second pitch.

US Pat. No. 10,115,667

SEMICONDUCTOR DEVICE WITH AN INTERCONNECTION STRUCTURE HAVING INTERCONNECTIONS WITH AN INTERCONNECTION DENSITY THAT DECREASES MOVING AWAY FROM A CELL SEMICONDUCTOR PATTERN

AMSUNG ELECTRONICS CO., L...

1. A semiconductor device, comprising:a cell semiconductor pattern disposed on a semiconductor substrate;
a first circuit disposed between the semiconductor substrate and the cell semiconductor pattern;
a cell array region disposed on the cell semiconductor pattern, the cell semiconductor pattern extending beyond the cell array region;
a first interconnection structure disposed between the semiconductor substrate and the cell semiconductor pattern and electrically connected to the first circuit, wherein the first interconnection structure includes a plurality of first interconnections, and the first interconnections have an interconnection density that decreases moving away from the cell semiconductor pattern;
a first dummy structure disposed between the semiconductor substrate and the cell semiconductor pattern, wherein the first dummy structure includes first dummy patterns co-planar with the first interconnections; and
second dummy patterns disposed on the semiconductor substrate, wherein the second dummy patterns are co-planar with the first interconnections,
wherein the second dummy patterns have a lower pattern density at an area closer to the cell semiconductor pattern than at an area farther away from the cell semiconductor pattern.

US Pat. No. 10,115,666

METHOD FOR MAKING A PHOTOLITHOGRAPHY MASK INTENDED FOR THE FORMATION OF CONTACTS, MASK AND INTEGRATED CIRCUIT CORRESPONDING THERETO

STMICROELECTRONICS (ROUSS...

1. A method for making a photolithography mask used for formation of electrically conducting contact pads between metallic tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer, the semiconductor wafer including the electrically active zones and dummy zones that are separated from the electrically active zones by isolation regions, the method comprising:forming a first photolithography mask region corresponding to the electrically active zones, the first photolithography mask region including first openings for the formation of the contact pads, the first openings having a first degree of opening defined by a first ratio between a surface area of the first openings and a useful total surface area of the photolithography mask, the first degree of opening being less than 3.5%; and
increasing an overall degree of opening of the photolithography mask to reduce defects in the formation of the contact pads in the electrically active zones by forming a second photolithography mask region corresponding to the dummy zones, the second photolithography mask region including additional openings for the formation of dummy contact pads, the first openings and the additional openings together having the overall degree of opening of the photolithography mask defined by a second ratio between a surface area of all of the first and additional openings and the useful total surface area of the photolithography mask, the overall degree of opening being equal to or greater than 3.5%, wherein each of the additional openings has a surface area that is greater than a surface area of each of the first openings.

US Pat. No. 10,115,665

SEMICONDUCTOR RESISTOR STRUCTURES EMBEDDED IN A MIDDLE-OF-THE-LINE (MOL) DIELECTRIC

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing a substrate having a first doped semiconductor material structure present in a first device region, and a second doped semiconductor material structure present in a second device region, wherein a middle-of-the-line (MOL) dielectric material is located on the substrate and surrounds the first and second doped semiconductor material structures, and wherein the MOL dielectric material contains a lower contact structure containing a metal liner and a contact metal present in both the first and second device regions;
forming a hard mask in the first device region and atop the MOL dielectric material and the lower contact structure, while leaving the second device region physically exposed;
removing at least a portion of the contact metal of the lower contact structure present in the second device region to physically expose at least a portion of the metal liner; and
forming a next level dielectric material located above the lower contact structure present in the first device region and between and above the metal liner present in the second device region, wherein the next level dielectric material contains an upper contact structure in both of the first and second device regions.

US Pat. No. 10,115,664

DISPLAY PANEL AND DISPLAY DEVICE

XIAMEN TIANMA MICRO-ELECT...

1. A display panel, comprising:a first substrate having a step area;
a second substrate disposed opposite to the first substrate, wherein the second substrate has a first surface facing the first substrate and an opposite second surface;
a Chip On Flex (COF) disposed on the step area of the first substrate and comprising at least one ground pad, wherein the COF has a first surface facing the first substrate and an opposite second surface, and the at least one ground pad is disposed on the second surface of the COF;
a conductive layer disposed on the second surface of the second substrate; and
a conductive adhesive electrically connected to the conductive layer and the at least one ground pad.

US Pat. No. 10,115,663

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Monolithic 3D Inc., San ...

1. A 3D semiconductor device, the device comprising:a first single crystal layer comprising a plurality of first transistors and a first metal layer,
wherein said first metal layer comprises interconnecting said first transistors forming a plurality of logic gates;
a plurality of second transistors overlaying said first single crystal layer;
a plurality of third transistors overlaying said second transistors;
a second metal layer overlaying said third transistors;
Input/Output pads to provide connection to external devices;
a global power grid to distribute power to said device, said global power grid overlaying said first metal layer; and
a local power grid to distribute power to said plurality of logic gates,
wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,
wherein said first single crystal layer comprises an Electrostatic Discharge (“ESD”) structure connected to at least one of said Input/Output pads,
wherein said global power grid is connected to said local power grid by a plurality of vias,
wherein at least one of said plurality of vias has a radius of less than 200 nm,
wherein at least one of said third transistors is a junction-less transistor, and
wherein a memory cell comprises at least one of said third transistors.

US Pat. No. 10,115,662

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CURVED IMAGE SENSOR

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor die including a base semiconductor material comprising a first surface and a second surface opposite the first surface, wherein the second surface includes an image sensor area;
removing a portion of the first surface of the base semiconductor material to form a first curved surface;
disposing the semiconductor die on a substrate with the first curved surface oriented toward the substrate; and
asserting movement of the base semiconductor material by external force to change orientation of the second surface with the image sensor area into a second curved surface.

US Pat. No. 10,115,661

SUBSTRATE-LESS DISCRETE COUPLED INDUCTOR STRUCTURE

QUALCOMM Incorporated, S...

1. An inductor structure, comprising:a first inductor winding that includes an electrically conductive material;
a second inductor winding that includes an electrically conductive material; and
an epoxy filler laterally located between the first inductor winding and the second inductor winding, the epoxy filler configured to provide structural coupling of the first and second inductor windings, wherein the first inductor winding, the second inductor winding and the epoxy filler are substrate-less, and not in direct contact with any substrate base portion,
wherein the inductor structure comprises a thickness of 200 microns or less.

US Pat. No. 10,115,660

LEADFRAME STRIP WITH VERTICALLY OFFSET DIE ATTACH PADS BETWEEN ADJACENT VERTICAL LEADFRAME COLUMNS

TEXAS INSTRUMENTS INCORPO...

1. A leadframe strip comprising:a first leadframe column and a second leadframe column, each of the first leadframe column and the second leadframe column including a plurality of leadframes, each of the plurality of leadframes including a die attach pad of a plurality of die attach pads, the plurality of die attach pads including a first die attach pad of the first leadframe column and a second die attach pad of the second leadframe column; and
a plurality of leads associated with each of the plurality of die attach pads, the plurality of leads associated with the first die attach pad and the second die attach pad connected to a first dam bar associated with the first die attach pad and a second dam bar associated with the second die attach pad, the first and second dam bars connected together using a portion of the leadframe strip, the portion aligned in a first direction;
wherein the first die attach pad and the second die attach pad are offset from each other in a second direction, the second direction being at an angle with respect to the first direction.

US Pat. No. 10,115,659

MULTI-TERMINAL DEVICE PACKAGING USING METAL SHEET

Sensor Electronics Techno...

1. A device package array comprising:a wafer including a plurality of devices;
a first metal sheet located adjacent to the wafer, wherein the first metal sheet is patterned to include a plurality of openings extending through the first metal sheet; and
a second metal sheet located adjacent to the first metal sheet, wherein the second metal sheet is patterned to include a plurality of openings extending through the second metal sheet, wherein the first metal sheet and the second metal sheet are positioned such that the plurality of openings in the first metal sheet alternate with the plurality of openings in the second metal sheet, such that a first electrode in each device of the plurality of devices is bonded to the first metal sheet and a second electrode in each device of the plurality of devices is bonded to the second metal sheet.

US Pat. No. 10,115,658

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor chip having a first upper surface on which a plurality of electrodes are formed and a first back surface opposite the first upper surface;
a tab having a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along a first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the semiconductor chip has a second side along which the plurality of electrodes are arranged and extended in a first direction,
wherein, in the plan view, the first side of the tab is extended along the second side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the second side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab formed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has a first portion extended in the first direction, and a second portion extended from the first portion toward the first side of the tab and also extended in a second direction crossing the first direction,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab, is located between the slit and the first side of the tab,
wherein, in the plan view, each of the plurality of second wires intersects with the slit, and
wherein a length of the first portion of the slit in the first direction is longer than a length of the second portion of the slit in the second direction.

US Pat. No. 10,115,656

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a substrate;
a semiconductor chip coupled onto the substrate via a bump electrode; and
an underfill material disposed between the substrate and the semiconductor chip,
wherein the underfill material contains a resin, potassium ions, and graphene particles.

US Pat. No. 10,115,655

HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING HEAT DISSIPATION SUBSTRATE

SUPERUFO291 TEC, Kyoto (...

12. A heat dissipation substrate, comprising:an alloy composite body mainly composed of a principal metal, an additional metal which is different from the principal metal and is at least one substance selected from a group consisting of Ti, Cr, Co, Mn, Ni, Fe, B, Y, Mg and Zn, and diamond, the diamond being provided as a powder of diamond; and
a metallic layer composed of Cu, the metallic layer being formed on a surface of the alloy composite body,
wherein a coefficient of linear expansion of the heat dissipation substrate is in a range of 6.5 ppm/K or higher and 15 ppm/K or lower,
a degree of thermal conductivity of the heat dissipation substrate is 420 W/m·K or higher,
a percentage of defects on the surface of the metallic layer is 5% or lower, and
a carbide of the additional metal is formed on a surface of the powder of diamond.

US Pat. No. 10,115,654

BURIED THERMALLY CONDUCTIVE LAYERS FOR HEAT EXTRACTION AND SHIELDING

PALO ALTO RESEARCH CENTER...

1. A device comprising:a plurality of blocks grown sequentially on each other, the plurality of the blocks being interconnected by vertical vias filled with thermally conducting material, wherein each of the blocks comprises:
an insulating layer,
a semiconductor layer being deposited on the insulating layer below,
a thermally insulating layer being deposited on the semiconductor layer below, and
a buried thermally conductive layer being deposited on the thermally insulating layer below; and
a thermally conductive layer bonded to bottom or top of the plurality of blocks as a ground plane or a heat extraction layer, the thermally conductive layer having a high thermal conductivity,
wherein
the vertical vias contact the thermally conductive layer and pass through the insulating layer, the thermally insulating layer, and the buried thermally conductive layer in the plurality of blocks,
the vertical vias do not contact the semiconductor layers of the plurality of blocks, and
inter-plane vias connect the semiconductor layers of the plurality of blocks.

US Pat. No. 10,115,653

THERMAL DISSIPATION THROUGH SEAL RINGS IN 3DIC STRUCTURE

Taiwan Semiconductor Manu...

1. A package comprising:a first die comprising a first seal ring comprising a plurality of sides adjacent to edges of the first die;
a heat spreader encircling the first die;
a thermal conductive path connecting the heat spreader to the first seal ring, wherein an entirety of the thermal conductive path is formed of metal-containing features; and
an interposer underlying and bonded to the first die through a first solder region, wherein the interposer comprises:
a substrate;
a metal line over the substrate, wherein the metal line forms a portion of the thermal conductive path, and the metal line is in contact with the first solder region;
a plurality of through-vias penetrating through the substrate of the interposer; and
a second seal ring over the substrate of the interposer, wherein the second seal ring is electrically coupled to the heat spreader.

US Pat. No. 10,115,652

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS

Renesas Electronics Corpo...

1. A semiconductor device comprising:a power device; and
a temperature detection diode,
wherein the semiconductor device has a device structure configured to insulate between a power line of the power device and the temperature detection diode, and
wherein the device structure comprises a resistor between a first conductive type electrode included in the power line of the power device and a cathode electrode of the temperature detection diode.

US Pat. No. 10,115,651

ELECTRONIC COMPONENT HAVING A CHIP MOUNTED ON A SUBSTRATE WITH A SEALING RESIN AND MANUFACTURING METHOD THEREOF

ROHM CO., LTD., Kyoto (J...

1. An electronic component, comprising:a substrate that has a first principal surface and a second principal surface;
a chip that includes a mounting surface on which a plurality of terminal electrodes are formed, and a non-mounting surface opposite to the mounting surface, the mounting surface facing the first principal surface of the substrate; and
a sealing resin that is disposed on the first principal surface of the substrate, and seals the chip so as to expose the non-mounting surface of the chip, the sealing resin having an outer surface that is flush with the non-mounting surface of the chip.

US Pat. No. 10,115,650

DIE-ON-INTERPOSER ASSEMBLY WITH DAM STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:bonding a die to a chip area on a frontside of a wafer to form a die-on-wafer assembly, the wafer having the frontside and a backside, the chip area being surrounded by scribe line regions, the chip area comprising four corner areas;
forming a dam structure in each of the four corner areas on the backside of the wafer; and
performing a dicing process on the scribe line regions, wherein after performing the dicing process, each of the four corner areas of the chip area includes at least a portion of one of the dam structures, each of the remaining portions of the dam structures being at least a part of a circle in a plane parallel to the backside of the wafer.

US Pat. No. 10,115,649

EXTERNAL CONNECTION MECHANISM, SEMICONDUCTOR DEVICE, AND STACKED PACKAGE

TOHOKU-MICROTEC CO., LTD....

1. A semiconductor device comprising:a connecting base including:
a semiconductor substrate,
a surface insulating-film having a flat upper face and provided on the semiconductor substrate,
an interconnection buried in the surface insulating-film, and
a surface electrode arranged on the upper face of the surface insulating-film and connected to the interconnection;
a passivation film covering the upper face of the surface insulating-film and the surface electrode, establishing a groove that exposes a central part of the surface electrode at a bottom;
a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film so as to cover an area corresponding to the surface electrode in a plane pattern; and
a plurality of micro-bumps arranged on the barrier-metal film located on the passivation film.

US Pat. No. 10,115,648

FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A semiconductor package comprising:a semiconductor chip;
a first interconnection member stacking on the semiconductor chip, electrically connected to the semiconductor chip, and having a connection terminal pad; and
a passivation layer disposed at one side of the first interconnection member and having an opening part opening a portion of the connection terminal pad,
wherein distances from a center of the connection terminal pad to at least two points of an edge thereof are different from each other, and
the center of the connection terminal pad and the at least two points of the edge are positioned in a plane vertical to a stacking direction of the first interconnection member and the semiconductor chip.

US Pat. No. 10,115,647

NON-VERTICAL THROUGH-VIA IN PACKAGE

1. A package comprising:a device die;
a through-via, wherein the through-via has a sand timer profile, wherein a longitudinal cross-section profile of the through-via is curved continuously;
a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die;
a first dielectric layer overlapping the molding material and the device die;
a second dielectric layer overlapped by the molding material and the device die;
a via in the second dielectric layer, wherein the via and the through-via in combination comprise:
a metal seed layer comprising a first metal, wherein the metal seed layer comprises a first portion as a bottom portion of the via, a second portion as a bottom portion of the through-via, and a third portion lining a sidewall of the via; and
a metallic material comprising a second metal different from the first metal; and
a plurality of redistribution lines (RDLs) extending into the first dielectric layer to electrically couple to the device die and the through-via.

US Pat. No. 10,115,646

SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR SYSTEM AND METHOD OF FORMING A SEMICONDUCTOR ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A semiconductor arrangement, comprising:an electrically conductive plate having a top surface;
a plurality of power semiconductor devices arranged on the top surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices is electrically coupled to the electrically conductive plate;
a plurality of electrically conductive blocks, each electrically conductive block being electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and
encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the top surface of the electrically conductive plate is free from the encapsulation material.

US Pat. No. 10,115,645

REPACKAGED RECONDITIONED DIE METHOD AND ASSEMBLY

Global Circuit Innovation...

1. A method comprising:removing one or more existing ball bonds from an extracted die, the extracted die comprising a fully functional semiconductor die removed from a previous package;
reconditioning die pads of the extracted die to create a reconditioned die, reconditioning comprising applying a plurality of metallic layers to the die pads;
securing the reconditioned die within a cavity of a new package base;
providing a plurality of bond connections interconnecting the reconditioned die pads and package leads or downbonds of the new package base;
applying an encapsulating compound over the reconditioned die and the plurality of bond connections to create an assembled package base, the encapsulating compound configured to exhibit low thermal expansion; and
securing a lid to the new package base.

US Pat. No. 10,115,644

INTERPOSER MANUFACTURING METHOD

Disco Corporation, Tokyo...

1. An interposer manufacturing method for manufacturing a plurality of interposers from a material substrate including a glass substrate having a first surface and a second surface opposite to said first surface and a multilayer member provided on said first surface or said second surface of said glass substrate, said glass substrate being partitioned by a plurality of crossing division lines to define a plurality of separate regions, said multilayer member including an insulating layer and a wiring layer, said interposer manufacturing method comprising:a cut groove forming step of cutting an exposed surface of said multilayer member along each division line by using a first cutting blade to thereby form a cut groove on said exposed surface of said multilayer member, said cut groove having a depth not reaching said glass substrate; and
a dividing step of cutting said glass substrate along each cut groove by using a second cutting blade having a thickness smaller than the width of each cut groove to thereby divide said glass substrate and manufacture said plurality of interposers.

US Pat. No. 10,115,643

CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:receiving an integrated circuit (IC) having a first layer, wherein the first layer has a first surface and a second surface;
attaching probe pads to the first surface;
applying a first fault testing to the IC through the probe pads, wherein the first fault testing is designed to detect faults in at least the first layer, wherein the first fault testing includes supplying first test patterns to the IC, receiving first outputs from the IC, and determining whether the first outputs are acceptable;
after determining that the first outputs are acceptable, forming a second layer of the IC over the second surface and connected to the first layer; and
after the forming of the second layer, applying a second fault testing to the IC through the probe pads that are attached to the first surface, the IC having the first and second layers, wherein the second fault testing is designed to detect faults in at least the second layer, wherein the second fault testing includes supplying second test patterns to the IC, receiving second outputs from the IC, and determining whether the second outputs are acceptable.

US Pat. No. 10,115,642

SEMICONDUCTOR DEVICES COMPRISING NITROGEN-DOPED GATE DIELECTRIC, AND METHODS OF FORMING SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

1. A method of forming a semiconductor device comprising:forming a gate dielectric layer extending across a location of a channel region of a PMOS transistor and across a location of a channel region of an NMOS transistor;
doping a first region of the gate dielectric layer with nitrogen to a first concentration;
after doping the first region of the gate dielectric layer with the nitrogen to the first concentration, doping a second region of the gate dielectric layer with nitrogen to a second concentration different from the first concentration; one of the nitrogen-doped first and second regions of the gate dielectric layer including a nitrogen-doped NMOS gate dielectric material over and in direct physical contact with the channel region location of the NMOS transistor, and the other of the nitrogen-doped first and second regions of the gate dielectric layer including a nitrogen-doped PMOS gate dielectric material over and in direct physical contact with the channel region location of the PMOS transistor; and
the nitrogen-doped NMOS gate dielectric material being doped to a higher concentration of nitrogen than the nitrogen-doped PMOS gate dielectric material.

US Pat. No. 10,115,641

SEMICONDUCTOR ARRANGEMENT, METHOD OF MANUFACTURING THE SAME ELECTRONIC DEVICE INCLUDING THE SAME

Institute of Microelectro...

1. A semiconductor arrangement, comprising a first semiconductor device and a second semiconductor device stacked in sequence on a substrate, wherein each of the first semiconductor device and the second semiconductor device comprises:a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence, wherein the channel layer comprises a semiconductor material different from that of the first source/drain layer and from that of the second source/drain layer; and
a gate stack surrounding a periphery of the channel layer.

US Pat. No. 10,115,640

METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing an integrated circuit device, the method comprising:providing a substrate with a pattern structure, the pattern structure comprising a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween;
forming at least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction;
forming, while the at least one support structure contacts the upper surface of the pattern structure, a buried layer that fills the spaces between the plurality of first patterns; and
removing the at least one support structure from the pattern structure,
wherein in the forming of the at least one support structure, a lower surface of the at least one support structure that faces the substrate includes a first local surface and a second local surface without a step difference between the first local surface and the second local surface, the first local surface facing the upper surface of the pattern structure, the second local surface facing the space, the lower surface having a planar shape that extends in the second direction.

US Pat. No. 10,115,639

FINFET DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:depositing an amorphous material in an opening disposed between a first semiconductor structure and a second semiconductor structure, the amorphous material comprising at least one first void;
recrystallizing the amorphous material to form a first conductive material comprising the at least one void;
removing a portion of the first conductive material to form a trench, the trench exposing the at least one first void and being defined by a remaining portion of the first conductive material; and
depositing a second conductive material in the trench, the second conductive material and the remaining portion of the first conductive material forming a dummy gate layer, wherein depositing the second conductive material in the trench is sufficient to cause the dummy gate layer to be free from voids.

US Pat. No. 10,115,638

PARTIALLY RECESSED CHANNEL CORE TRANSISTORS IN REPLACEMENT GATE FLOW

TEXAS INSTRUMENTS INCORPO...

1. A method of forming an integrated circuit, comprising the steps of:providing a substrate comprising semiconductor material;
concurrently removing a first sacrificial gate in a first MOS transistor and removing a second sacrificial gate in a second MOS transistor;
concurrently removing a first sacrificial gate dielectric layer in said first MOS transistor and removing a second sacrificial gate dielectric layer in said second MOS transistor;
forming an etch mask over said substrate in said second MOS transistor so as to expose said substrate in said first MOS transistor;
concurrently removing semiconductor material from said substrate in an area for a recessed replacement gate in said first MOS transistor and from a field oxide adjacent to the area to form a recess, such that an etched surface of said substrate is substantially coplanar with an etched surface of field oxide adjacent to said etched surface of said substrate at a bottom of said recess, and such that semiconductor material is not removed from said substrate in said second MOS transistor;
concurrently forming a first replacement gate dielectric layer in said first MOS transistor and forming a second replacement gate dielectric layer in said second MOS transistor; and
concurrently forming a recessed first replacement gate on said first replacement gate dielectric layer and forming a second replacement gate on said second replacement gate dielectric layer;
so that said recessed first replacement gate is recessed below a top surface of said substrate and said first MOS transistor and said second MOS transistor have a same polarity.

US Pat. No. 10,115,636

PROCESSING METHOD FOR WORKPIECE

Disco Corporation, Tokyo...

1. A method of processing a workpiece in which a plurality of low-dielectric-constant insulation films and a metallic pattern are stacked on a surface of a semiconductor substrate and in which devices are formed in a plurality of regions formed in a grid pattern, the method comprising:a masking step of covering surfaces of the devices formed on the workpiece with a surface protective member, leaving spaces between adjacent regions exposed;
a wet blasting step of dispersing abrasive grains in an etching liquid capable of dissolving the metallic pattern, and blasting the dispersion against the workpiece together with compressed gas so as to remove the low-dielectric-constant insulation films and the metallic pattern in the regions, thereby exposing the semiconductor substrate to form streets in the regions; and
a dividing step of subjecting the workpiece with the semiconductor substrate exposed by the wet blasting step to dry etching so as to divide the workpiece along the streets,
wherein dissolving of the metallic pattern on the streets and removal of the low dielectric constant insulation films are simultaneous in the wet blasting step.

US Pat. No. 10,115,635

METHOD FOR FILLING A WAFER VIA WITH SOLDER

KOREA INSTITUTE OF INDUST...

1. A wafer via solder filling method using a wafer via solder filling device comprising a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air outlet for exhausting air from the accommodation space; a fixing unit for fixing the wafer having a via formed in one surface in the accommodation space to seal the accommodation space airtight; and a pressing unit for pressing a bottom of the molten solder arranged in the solder bath and moving the molten solder upward, to fill the molten solder in the via, the wafer via solder filling method comprising:a fixing step of fixing the wafer in the accommodation space, using the fixing unit, and sealing the accommodation space airtight;
an exhausting step of exhausting air inside the sealed accommodation space through the air outlet; and
a filling step of filling the molten solder in the via as pressing the bottom of the molten solder and moving the molten solder upward, using the pressing unit.

US Pat. No. 10,115,634

SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor component comprising:a semiconductor substrate having an opening;
a first dielectric liner having a first stress over an interior surface of the opening;
a second dielectric liner having a second stress over the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress; and
a conductive material over the second dielectric liner.

US Pat. No. 10,115,633

METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:trench lines formed in a dielectric layer;
each trench line including a pair of self aligned line end vias; and
a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias,
wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

US Pat. No. 10,115,632

THREE-DIMENSIONAL MEMORY DEVICE HAVING CONDUCTIVE SUPPORT STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect-level metal interconnect structures;
a horizontal layer overlying the lower-interconnect-level dielectric material layer;
an alternating stack of insulating layers and electrically conductive layers located over the horizontal layer;
an array of memory stack structures extending through the alternating stack;
laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer, wherein each of the laterally-insulated conductive via structures comprises a respective first conductive core that is electrically shorted to a respective one of the lower-interconnect-level metal interconnect structures, and a respective first cylindrical dielectric spacer that laterally surrounds the respective first conductive core;
laterally-insulated support structures that vertically extend through a subset of layers in the alternating stack, wherein each of the laterally-insulated support structures comprises a respective second conductive core having a same composition as the first conductive core, and a respective second cylindrical dielectric spacer that laterally surrounds the respective second conductive core, and wherein an entirety of a top planar surface of each second conductive core contacts a respective bottom surface of an overlying upper-interconnect-level dielectric material layer;
wherein:
the alternating stack includes a staircase region in which each electrically conductive layer except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack;
a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and
the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion.

US Pat. No. 10,115,631

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a circuit comprising a first transistor;
a first pixel and a second pixel; and
a first wire, a second wire, and a third wire, wherein the first wire, the second wire and the third wire are electrically connected to the circuit,
wherein the second wire is electrically connected to the first pixel,
wherein the third wire is electrically connected to the second pixel,
wherein the circuit is configured to distribute a signal from the first wire to the second wire and the third wire,
wherein the first transistor comprises a first oxide semiconductor film and a second oxide semiconductor film on the first oxide semiconductor film, and
wherein an atomic ratio of indium in the first oxide semiconductor film is different from an atomic ratio of indium in the second oxide semiconductor film.

US Pat. No. 10,115,630

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming an interconnect structure, comprising:forming a lower etch stop layer (ESL);
forming a middle low-k (LK) dielectric layer over the lower ESL;
forming a supporting layer over the middle LK dielectric layer;
forming an upper LK dielectric layer over the supporting layer;
forming an upper conductive feature in the upper LK dielectric layer through the supporting layer;
forming a gap along an interface of the upper conductive feature and the upper LK dielectric layer and along an interface of the upper conductive feature and the middle LK dielectric layer, wherein the step of forming the gap along the interface of the upper conductive feature and the upper LK dielectric layer is performed by removing a portion of the upper LK dielectric layer along the interface by a wet etching process; and
forming an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

US Pat. No. 10,115,629

AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

International Business Ma...

1. A semiconductor device, comprising:a first metallic structure and a second metallic structure disposed adjacent to each other on a substrate with a space disposed between the first and second metallic structures, wherein the first metallic structure comprises a gate structure of a transistor and wherein the second metallic structure comprises a source/drain contact; and
a dielectric capping layer formed over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;
wherein an upper portion of the air gap is disposed above an upper surface the first metallic structure and below an upper surface of the second metallic structure; and
wherein a bottom portion of the air gap is disposed below a bottom surface of the second metallic structure.

US Pat. No. 10,115,627

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a base;
a memory cell region on the base comprising a first plurality of conductive layers including first and second portions, and a first plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers;
a first stacked body on the base comprising a second plurality of insulating layers and a second plurality of conductive layers fewer than the number of the first plurality of conductive layers, each of the conductive layers of the second plurality being connected to one of the conductive layers of the first portion of the first plurality, wherein an insulating layer of the second plurality of insulating layers extends between, and separates, each two adjacent conductive layers of the second plurality of conductive layers, an end portion of the first stacked body having a first stair portion having a first stair-like shape wherein a surface of each of the second plurality of conductive layers is exposed; and
a second stacked body on the base comprising a third plurality of insulating layers and a third plurality of conductive layers fewer in number than the first plurality of conductive layers, each of the conductive layers of the third plurality being connected to one of the conductive layers of the second portion of the first plurality, wherein an insulating layer of the third plurality of insulating layers extends between, and separates, each two adjacent conductive layers of the third plurality of conductive layers, an end portion of the second stacked body having a second stair portion having a second stair-like shape wherein a surface of each of the third plurality of conductive layers is exposed, the second stair portion spaced from the first stair portion by a first distance, wherein
the lowermost layer of the first stacked body is in contact with the base and the lowermost layer of the second stacked body is in contact with the base.

US Pat. No. 10,115,624

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION

Taiwan Semiconductor Manu...

1. A method comprising:forming a plurality of fin elements extending from a substrate using a hardmask layer;
forming isolation features disposed between adjacent fin elements;
irradiating the isolation features using a first pulsed laser beam having a first pulse duration,
wherein prior to the irradiating the isolation features, the isolation features have a first etch rate in a first solution, and
wherein after the irradiating the isolation features, a top portion of the isolation features has a second etch rate less than the first etch rate in the first solution, and a bottom portion of the isolation features has the first etch rate;
after the irradiating the isolation features, removing the hardmask layer over the substrate by an etching process using the first solution;
forming a gate structure over the plurality of fin elements;
depositing an inter-level dielectric (ILD) layer over the gate structure; and
irradiating the ILD layer using a second pulsed laser beam having a second pulse duration different from the first pulse duration.

US Pat. No. 10,115,623

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus for processing a substrate, comprising:a substrate holding part for holding a substrate;
a substrate rotation mechanism for rotating said substrate holding part about a central axis perpendicular to said substrate; and
a magnetic-material movement mechanism for moving a first chucking magnetic material into close proximity to said substrate holding part and moving said first chucking magnetic material away from said substrate holding part,
wherein said substrate holding part includes:
a chuck support part; and
at least three chuck members supported on said chuck support part,
said at least three chuck members includes at least one movable chuck member whose position can be changed between a chuck position and an unchuck position,
each movable chuck member included in said at least one movable chuck member includes a second chucking magnetic material that applies a force that holds an outer edge portion of said substrate on said each movable chuck member by magnetic action between said first chucking magnetic material and said second chucking magnetic material when said first chucking magnetic material is moved into close proximity to said substrate holding part, and
said substrate rotation mechanism includes:
a rotor that has an annular shape centered about said central axis and includes a permanent magnet; and
a stator that has an annular shape centered about said central axis and rotates said rotor that is in a floating state.

US Pat. No. 10,115,622

WAFER PROCESSING LAMINATE AND METHOD FOR PROCESSING WAFER

SHIN-ETSU CHEMICAL CO., L...

1. A wafer processing laminate comprising a support, a temporary adhesive material layer laminated on the support, and a wafer stacked on the temporary adhesive material layer, the wafer having a front surface on which a circuit is formed and a back surface to be processed, the temporary adhesive material layer comprising a first temporary adhesive layer composed of a thermoplastic resin layer (A) laminated on the front surface of the wafer, a second temporary adhesive layer composed of a thermosetting resin layer (B) laminated on the first temporary adhesive layer, and a third temporary adhesive layer composed of a separation layer (C) laminated between the support and the thermosetting resin layer (B), the thermoplastic resin layer (A) being soluble in a cleaning liquid (D) after processing the wafer, the thermosetting resin layer (B) being insoluble in the cleaning liquid (D) after heat curing and capable of absorbing the cleaning liquid (D) such that the cleaning liquid (D) permeates into the layer (B), the layer (C) having a peeling force of 0.5 gf or more and 50 gf or less which is required for peeling the thermosetting resin layer (B) along an interface between the thermosetting polymer layer (B) and the separation layer (C), or which is required for peeling the thermosetting polymer layer (B) with cohesion failure of the separation layer (C), when the polymer layer (B) laminated on the separation layer (C) on the support is thermally cured, as measured by 180° peeling using a test piece having a width of 25 mm.

US Pat. No. 10,115,621

METHOD FOR IN-DIE OVERLAY CONTROL USING FEOL DUMMY FILL LAYER

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:providing parallel structures in a first layer on a substrate;
determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements;
forming overlay trenches with a first reticle, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures;
determining a trench center-of-gravity of an overlay trench by measuring a first distance from a first edge of the overlay trench to the structure with a critical dimension scanning electron microscope (CDSEM); and measuring a second distance from a second edge, opposing the first edge, of the overlay trench to the structure with the CDSEM;
determining a structure center-of-gravity of a structure exposed in the overlay trench;
determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity; and
upgrading the first reticle with a second reticle.

US Pat. No. 10,115,619

COUPLING TRANSFER SYSTEM

NATIONAL INSTITUTE OF ADV...

1. A transfer box having a sealing structure hermetically sealable by means of tight coupling of a transfer box body and a transfer box door, said transfer box structured in such a way that magnets of the transfer box body face magnetic bodies of the transfer box door when the transfer box door is closed on the transfer box body, wherein these magnets and the magnetic bodies which are connected together form a loop constituting a first magnetic closed circuit in which magnetism is transmitted through the magnets and the magnetic bodies, said magnetic bodies of the transfer box door being configured to form a loop constituting a second magnetic closed circuit with magnetized electromagnets connected together with the magnetic bodies when the electromagnets face the magnetic bodies on a side opposite to the transfer box body side in which magnetism is transmitted through the magnetic bodies and the magnetized electromagnets.

US Pat. No. 10,115,618

RETICLE TRANSFER SYSTEM AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:moving reticles in a local fabrication system, the local fabrication system comprising:
a plurality of lithography apparatuses;
a first service area configured to serve a first group of lithography apparatuses;
a second service area configured to serve a second group of lithography apparatuses; and
an internal buffer located at a boundary between the first service area and the second service area, wherein the internal buffer is a movable buffer;
transporting a first reticle from the first service area to a lithography apparatus in the second service area;
transporting a second reticle from the second service area to the lithography apparatus in the second service area; and
loading the first reticle into the internal buffer when the second reticle is processed in the lithography apparatus.

US Pat. No. 10,115,617

SYSTEM ARCHITECTURE FOR VACUUM PROCESSING

INTEVAC, INC., Santa Cla...

1. A system for processing wafers in a vacuum processing chamber, comprising:a plurality of carriers, each carrier comprising a frame having a plurality of openings, each opening configured to accommodate a single wafer;
a transport mechanism configured to transport the plurality of carriers through a loading station, to the vacuum processing chamber, and to an unloading station;
a return mechanism configured to return empty carriers from the unloading station to the loading station in an atmospheric environment, the return mechanism comprising a first carrier elevator positioned in the unloading station, a second carrier elevator positioned in the loading station, and a conveyor between the first and second carrier elevators;
a plurality of susceptors, each susceptor configured for supporting a single wafer;
an attachment mechanism for attaching a plurality of susceptors to each of the carriers, wherein each of the susceptors is attached to a corresponding position at an underside of a corresponding carrier, such that a wafer positioned on one of the susceptors is situated within one of the plurality of opening in the carrier;
a plurality of masks, each mask attached over front side of one of the plurality of opening in the carrier;
an alignment mechanism, configured to align the wafers to the masks;
a lifter configured for separating the susceptors from the carrier and masks;wherein said plurality of masks comprise:a plurality of inner masks, each configured for placing on top of one of the plurality of opening in the carrier, the inner mask having an opening-pattern to mask parts of the wafer and expose remaining parts of the wafer; and,
a plurality of outer masks, each configured for placing on top of a corresponding inner mask, the outer mask having an opening configured to partially cover the inner mask.

US Pat. No. 10,115,616

CARRIER ADAPTER INSERT APPARATUS AND CARRIER ADAPTER INSERT DETECTION METHODS

Applied Materials, Inc., ...

5. An adapter insert, comprising:an adapter frame configured to be received within a substrate carrier, wherein the substrate carrier is adapted to hold 450 mm substrates;
a plurality of support rails coupled to the adapter frame and adapted to support a plurality of 300 mm substrates;
a frame extension adapted to be coupled to the adapter frame; and
a mapping feature located on the frame extension and configured to be detected by a sensor affixed to an end effector of a robot external to the substrate carrier when the adapter insert is received within the substrate carrier, the mapping feature for determining whether the adapter insert is present or absent in a the substrate carrier.

US Pat. No. 10,115,615

SUBSTRATE PROCESSING APPARATUS AND CONTROL METHOD OF SUBSTRATE PROCESSING APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A substrate processing apparatus comprising:a processing unit to process a substrate; and
a manipulator for maintenance, the manipulator being placed near the processing unit,
wherein the manipulator includes:
a first arm; and
a second arm combined with the first arm,
the manipulator causes the first arm and the second arm to move independently of each other according to control of a controller;
the substrate processing apparatus further comprises a load lock chamber for maintenance that can accommodate the first arm and the second arm;
wherein the manipulator, according to control of the controller, causes at least a tip portion of the second arm to move into the processing unit for the tip portion to suck a part in the processing unit and causes the first arm and the second arm to hand the part from the second arm onto the first arm and to transfer the part with the first arm into the load lock chamber.

US Pat. No. 10,115,614

TRANSFER CHAMBER AND METHOD FOR PREVENTING ADHESION OF PARTICLE

TOKYO ELECTRON LIMITED, ...

1. A method for preventing particle adhesion to a target substrate in a chamber, the chamber comprising a chamber main body which is switchable between a depressurized environment and an atmospheric pressure environment, an ionization unit configured to generate an ionized gas to be supplied into the chamber main body, and a gas exhaust unit configured to exhaust the chamber main body, the method comprising:accommodating the target substrate into the chamber main body in the atmospheric pressure environment while supplying the ionized gas into the chamber main body;
performing a first step in which an inner pressure of the chamber main body is decreased to a first pressure by exhausting the chamber main body;
performing a second step in which the inner pressure is increased to a second pressure by supplying the ionized gas into the chamber main body without exhausting the chamber main body; and
performing a third step in which the inner pressure is decreased to a third pressure by exhausting the chamber main body,
wherein the second and third steps are both sequentially repeated a plurality of times until an environment of the chamber main body reaches a predetermined pressure which is lower than the pressure of the atmospheric pressure environment,
wherein the third pressure is lower than the first and the second pressures and the second pressure is higher than the first pressure and lower than the pressure of the atmospheric pressure environment, andwherein, for each sequential repetition of the second and third steps, the second and the third pressures of a subsequent repetition are lower than the second and third pressures, respectively, of a prior repetition of the second and third steps.

US Pat. No. 10,115,613

METHOD OF FABRICATING A FAN-OUT PANEL LEVEL PACKAGE AND A CARRIER TAPE FILM THEREFOR

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor package, comprising:forming a cavity in a package substrate;
providing the package substrate and a die on a carrier tape film, the carrier tape film including a tape substrate, an adhesive layer on the tape substrate, and an insulating layer on the adhesive layer, and the die being provided in the cavity of the package substrate, wherein the adhesive layer and the insulating layer have a first light initiator and a second light initiator respectively, and wherein the package substrate includes substrate pads on a top and bottom surface of the package substrate;
forming an encapsulation layer to cover the insulating layer and the die in the cavity and cover the package substrate on the insulating layer;
irradiating a first light that selectively reacts with the first light initiator onto the adhesive layer to reduce an adhesive strength of the adhesive layer;
removing the tape substrate from the insulating layer; and
irradiating a second light that reacts with the second light initiator onto a portion of the insulating layer to form first contact holes on a portion of the package substrate and on a portion of the die.

US Pat. No. 10,115,612

MANUFACTURING METHOD FOR VERTICAL CAVITY SURFACE EMITTING LASER

Murata Manufacturing Co.,...

1. A manufacturing method for a vertical cavity surface emitting laser, the method comprising steps of:forming, on a substrate, a multilayer body including first and second Distributed Bragg Reflector layers, an active layer, and a to-be-oxidized layer becoming a current constriction structure;
processing the multilayer body such that a lateral surface of at least the to-be-oxidized layer is exposed; and
forming the current constriction structure by oxidizing the to-be-oxidized layer from the lateral surface thereof after the multilayer body has been processed,
wherein the step of forming the current constriction structure includes steps of:
placing a uniformly-heated plate on a heat conduction member, the uniformly-heated plate having a planar upper surface;
positioning the substrate along the uniformly-heated plate so that the entire substrate is spaced from the planar upper surface of the uniformly-heated plate thereby forming a gap between the planar upper surface of the uniformly-heated plate and the substrate; and
heating the substrate by radiant heat from the uniformly-heated plate by heating the heat conduction member,
wherein the uniformly-heated plate is made of an anisotropic material having a larger thermal conductivity in a planar direction than in a vertical direction, and
wherein the step of positioning the substrate includes a step of supporting a peripheral edge portion of the substrate by a spacer that is attached to the heat conduction member, and a thermal conductivity of the spacer is smaller than the thermal conductivity of the uniformly-heated plate in the vertical direction.

US Pat. No. 10,115,611

SUBSTRATE COOLING METHOD, SUBSTRATE TRANSFER METHOD, AND LOAD-LOCK MECHANISM

TOKYO ELECTRON LIMITED, ...

1. A substrate cooling method for, by using a load-lock mechanism for controlling a pressure therein between a first pressure and a second pressure in the case of transferring the substrate between a first module maintained at a first pressure close to an atmospheric pressure and a second module maintained at a second pressure in a vacuum state, cooling a high-temperature substrate transferred from the second module to the first module, the load-lock mechanism including a chamber accommodating a substrate, a cooling member disposed in the chamber and configured to cool the substrate disposed proximate to the cooling member, a gas exhaust unit configured to exhaust the chamber, and a purge gas inlet unit configured to introduce a purge gas into the chamber, the method comprising:maintaining a pressure in the chamber to the second pressure, allowing the chamber to communicate with the second module, and loading the high-temperature substrate into the chamber;
placing the substrate to a cooling position close to the cooling member;
exhausting the chamber to a third pressure at which a region between a surface of the cooling member and a backside of the substrate satisfies a molecular flow condition to obtain uniform temperature distribution of the substrate; and
after maintaining the third pressure in the chamber at the third pressure for a first duration, introducing a purge gas into the chamber to increase the pressure in the chamber to the first pressure, and cooling the substrate by using the cooling member.

US Pat. No. 10,115,610

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus comprising:a spin chuck including a disk-shaped spin base including a circular upper surface disposed under a substrate and an outer peripheral surface whose outer diameter is greater than that of the substrate, a plurality of chuck pins that hold a substrate horizontally such that a lower surface of the substrate and the upper surface of the spin base are opposed in an up-down direction across an interval, and a spin motor that rotates the spin base and the plurality of chuck pins about a vertical rotation axis passing through a central portion of the substrate held by the plurality of chuck pins;
a shielding member including a disk portion, which includes an opposed surface disposed over the substrate held by the spin chuck, and a cylinder portion, which includes an inner peripheral surface surrounding the substrate held by the spin chuck about the rotation axis and an outer peripheral surface provided with an annular outer vertical portion extending vertically, wherein a lowest end of the inner peripheral surface is disposed around the spin base, and a distance in a radial direction from the lowest end of the inner peripheral surface to the outer peripheral surface of the spin base is not less than a distance in a vertical direction from the upper surface of the substrate held by the spin chuck to the opposed surface;
an upper inert gas supply unit that causes a downward discharge port provided at the opposed surface of the shielding member to discharge downward an inert gas;
a cup that is open upward and includes a cup tubular portion that surrounds the spin base about the rotation axis, an annular cup upper end portion that is disposed at a more inward position than the cup tubular portion and an annular cup inclined portion that extends obliquely upward from the cup tubular portion to the cup upper end portion; and
an exhaust unit that discharges a gas in the cup to outside of the cup; wherein
the cup upper end portion includes an annular cup inner peripheral end, which defines a circular opening having a diameter greater than the outer diameter of the outer peripheral surface of the spin base, and a cup lower end extending downward from an inner end of the cup inclined portion,
the cup inner peripheral end is a portion that is positioned most inward in the cup upper end portion,
the cylinder portion of the shielding member is disposed between the cup upper end portion and the spin base,
the lowest end of the inner peripheral surface of the shielding member and the outer peripheral surface of the spin base define an annular discharge port which discharges an atmosphere between the substrate and the shielding member, and
the outer vertical portion of the cylinder portion of the shielding member and the cup lower end define an annular clearance between the outer vertical portion and the cup lower end.

US Pat. No. 10,115,609

SEPARATION AND REGENERATION APPARATUS AND SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A separation and regeneration apparatus comprising:a controller including a processor coupled with a memory;
a mixed gas generating unit configured to receive a wafer covered with a first fluorine-containing organic solvent having a first boiling point;
a supercritical fluid supply line connecting to the mixed gas generating unit, the supercritical fluid supply line being provided with a first valve;
a discharge line connected to the mixed gas generating unit and including a second valve; and
a distillation tank configured to store hot water, the distillation tank including:
a water supply line that allows for periodic supply of water into the distillation tank,
a water level gauge configured to measure a level of the hot water within the distillation tank,
a distillation tank heater, and
an introduction line connected to the discharge line and running between the mixed gas generating unit and the distillation tank, the introduction line terminating in the distillation tank,
wherein the controller is programmed to:
control a mixed gas generating unit heater that heats the mixed gas generating unit to a predetermined temperature;
control the distillation tank heater to maintain the water within the distillation tank at a temperature between the first boiling point and the second boiling point,
open the first valve of the supercritical fluid supply line so as to introduce a second fluorine-containing organic solvent having a second boiling point lower than the first boiling point from the supercritical fluid supply line into the mixed gas generating unit, such that a mixed gas is generated from the first fluorine-containing organic solvent covering the wafer and the second fluorine-containing organic solvent introduced from the supercritical fluid supply line; and
close the first valve of the supercritical fluid supply line and open the second valve of the discharge line so as to discharge the mixed gas from the mixed gas generating unit to the distillation tank through the discharge line such that the mixed gas is conveyed into the hot water within the distillation tank through the introduction line to be separated into a liquid state of the first fluorine-containing organic solvent, a gaseous state of the second fluorine-containing organic solvent, and F ions that will be incorporated into the hot water.

US Pat. No. 10,115,608

METHOD AND APPARATUS FOR RAPID PUMP-DOWN OF A HIGH-VACUUM LOADLOCK

Novellus Systems, Inc., ...

1. An apparatus configured to be installed as part of a semiconductor processing tool, the semiconductor processing tool selected from the group consisting of: a semiconductor processing tool having one or more process chambers and a loadlock with a loadlock volume, and a semiconductor processing tool having one or more process chambers, a loadlock with a loadlock volume, and one or more transfer chambers, the apparatus comprising:a housing having internal surfaces defining a gas expansion volume, wherein the gas expansion volume is at least one and a half times larger than the loadlock volume;
a gas expansion volume valve, wherein:
the housing is configured to connect with the loadlock such that the gas expansion volume valve is interposed between the loadlock volume and the gas expansion volume when so connected,
the gas expansion volume is configured to be separate from the one or more process chambers and separate from any transfer chamber of the semiconductor processing tool,
the gas expansion volume valve is configured to be movable between an open state and a closed state,
the gas expansion volume valve permits fluidic communication between the loadlock volume and the gas expansion volume when in the open state and when the apparatus is connected with the loadlock, and
the gas expansion volume valve prevents fluidic communication between the loadlock volume and the gas expansion volume when in the closed state and when the apparatus is connected with the loadlock;
a first mechanism that comprises a high-vacuum pump configured to evacuate gas from the housing regardless of whether the gas expansion volume valve is in the open state or the closed state; and
a controller with at least one processor and a memory, the memory storing computer-executable instructions for controlling the at least one processor to:
a) control the gas expansion volume valve to enter the closed state;
b) cause the loadlock to be fluidically isolated from the one or more process chambers;
c) control a roughing pump to, after (a) and (b), evacuate gas from within the loadlock volume to reach a first lower-than-atmospheric pressure when the gas expansion volume valve is in the closed state;
d) control, after (a), the high-vacuum pump to evacuate gas from within the housing to reach a second lower-than-atmospheric pressure, wherein the second lower-than-atmospheric pressure is lower than the first lower-than-atmospheric pressure; and
e) control, after (c) and (d), the gas expansion valve to enter the open state thereby allowing gas in the gas expansion volume to mix with gas from the loadlock volume and reach equilibrium, wherein:
the first mechanism is fluidically connected with the gas expansion volume,
the first mechanism is configured to control gas pressure within the housing and to cause the pressure in the housing to be reducible to lower than 10E-3 Torr, and
the first mechanism is fluidically isolated from the loadlock volume when the gas expansion volume valve is in the closed state and when the apparatus is connected with the loadlock.

US Pat. No. 10,115,607

METHOD AND APPARATUS FOR WAFER OUTGASSING CONTROL

APPLIED MATERIALS, INC., ...

1. A semiconductor processing system, comprising:a purge station, comprising:
an enclosure;
a gas supply coupled to the enclosure;
an exhaust pump coupled to the enclosure;
a first purge gas port formed in the enclosure;
a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, wherein the first channel comprises:
a particle filter;
a heater; and
a flow controller;
a second purge gas port formed in the enclosure; and
a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end, wherein the second channel comprises a dry scrubber.

US Pat. No. 10,115,606

METHODS OF PROMOTING ADHESION BETWEEN UNDERFILL AND CONDUCTIVE BUMPS AND STRUCTURES FORMED THEREBY

Intel Corporation, Santa...

1. A method of forming a package structure comprising:modifying a filler to have a surface comprising a thiol based adhesion promoter; and
subsequent to modifying the filler, adding the modified filler to an underfill material; and
forming the underfill material having the modified filler on conductive bumps of the package structure, wherein the thiol based adhesion promoter comprises a molecular weight above about 150 g/mol.

US Pat. No. 10,115,605

VACUUM ASSISTED SEALING PROCESSES AND SYSTEMS FOR INCREASING AIR CAVITY PACKAGE MANUFACTURING RATES

RJR Technologies, Inc., ...

1. A sealing process for air cavity electronic packages comprising the steps of:providing a base and a lid, at least one of the base and the lid having a mating surface coated with an adhesive;
maintaining an air gap between the base and the lid;
generating a vacuum around the base, the lid, and the adhesive;
mating the base and the lid together after the vacuum has been generated to create a mated package assembly with a vacuum therein; and
heating the mated package assembly to a curing temperature to cure the adhesive.

US Pat. No. 10,115,604

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE

MediaTek Inc., Hsin-Chu ...

1. A method for fabricating a base for a semiconductor package, comprising:providing a carrier with conductive seed layers on the top surface and the bottom surface of the carrier;
forming radio-frequency (RF) devices respectively on the conductive seed layers;
laminating a first base material layer and a second base material layer respectively on the conductive seed layers, covering the RF devices; and
separating the first base material layer the second base material layer, which contain the RF devices thereon, from the carrier to form a first base and a second base.

US Pat. No. 10,115,602

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device, comprising:alternately stacking mold insulating layers and sacrificial layers on a substrate;
forming a plurality of channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing a plurality of recessed regions to be formed in the substrate;
cleaning a surface of the plurality of recessed regions, wherein processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the plurality of recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ;
forming epitaxial layers on the plurality of recessed regions of the substrate using the substrate in the plurality of recessed regions as seed;
forming a gate dielectric layer and a first semiconductor layer, covering a side wall of each of the channel holes and a top surface of the epitaxial layers;
forming a spacer on the gate dielectric layer, wherein processes of forming a second protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the first semiconductor layer are alternately repeated one or more times, in-situ;
removing a portion of the gate dielectric layer on the top surface of the epitaxial layers, wherein processes of forming a third protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the gate dielectric layer using the spacer as an etching mask are alternately repeated one or more times, in-situ; and
forming second semiconductor layers connected to the epitaxial layer in the channel holes.

US Pat. No. 10,115,601

SELECTIVE FILM FORMATION FOR RAISED AND RECESSED FEATURES USING DEPOSITION AND ETCHING PROCESSES

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:providing a substrate having a recessed feature with a sidewall and a bottom portion;
depositing a film in the recessed feature and on a field area around the opening of the recessed feature, wherein the film is non-conformally deposited with a greater film thickness on the bottom portion than on the sidewall and the field area;
etching the film in an atomic layer etching (ALE) process in the absence of a plasma, wherein the etching thins the film on the bottom portion and removes the film from the sidewall and the field area; and
repeating the depositing and the etching at least once to increase the film thickness on the bottom portion.

US Pat. No. 10,115,600

METHOD OF ETCHING SEMICONDUCTOR STRUCTURES WITH ETCH GAS

American Air Liquide, Inc...

1. A method of depositing an etch-resistant polymer layer on a substrate, the method comprising:introducing a vapor of a compound into a reaction chamber containing the substrate, the compound having a formula selected from the group consisting of: C2F4S2 (CAS 1717-50-6), F3CSH (CAS 1493-15-8), F3C—CF2—SH (CAS 1540-78-9), F3C—CH2—SH (CAS 1544-53-2), CHF2—CF2—SH (812-10-2), CF3—CF2—CH2—SH (CAS 677-57-6), F3C—CH(SH)—CF3 (CAS 1540-06-3), F3C—S—CF3 (CAS 371-78-8), F3C—S—CHF2 (CAS 371-72-2), F3C—CF2—S—CF2—CF3 (CAS 155953-22-3), F3C—CF2—CF2—S—CF2—CF2—CF3 (CAS 356-63-8), c(—S—CF2—CF2—CHF—CF2—) (CAS 1035804-79-5), c(—S—CF2—CHF—CHF—CF2—) (CAS 30835-84-8), c(—S—CF2—CF2—CF2—CF2—CF2—) (CAS 24345-52-6), c(—S—CFH—CF2—CF2—CFH—)(2 R, 5 R) (CAS 1507363-75-8), c(—S—CFH—CF2—CF2—CFH—)(2 R, 5 S) (CAS 1507363-76-9), and c(—S—CFH—CF2—CF2—CH2—) (CAS 1507363-77-0); and
plasma activating the compound to form the etch-resistant polymer layer on the substrate.

US Pat. No. 10,115,599

SPECTRALLY AND TEMPORALLY ENGINEERED PROCESSING USING PHOTOELECTROCHEMISTRY

The Board of Trustees of ...

1. A method for fabricating a photodetector integral with a parabolic reflector, the method comprising:a. photoelectroplating a top-contact metal-semiconductor-metal photodetector on a semiconductor wafer; and
b. defining a parabolic surface on the semiconductor wafer by
i. applying an etch solution to the surface of the semiconductor wafer;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor wafer; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination.

US Pat. No. 10,115,598

SUBSTRATE HOLDER, A METHOD FOR HOLDING A SUBSTRATE WITH A SUBSTRATE HOLDER, AND A PLATING APPARATUS

EBARA CORPORATION, Tokyo...

1. An apparatus for plating a substrate, comprising:a plating bath configured to house the substrate and an anode; and
an intermediate mask arranged between the substrate and the anode, wherein
the intermediate mask has a plate-shaped member having an opening through which an electric field from the anode to the substrate is made to pass and a plurality of edge parts that form the opening, and wherein
the apparatus further includes a drive mechanism configured to move each of the edge parts in a direction toward the substrate in a state where the plate-shaped member is fixed to the plating bath.

US Pat. No. 10,115,597

SELF-ALIGNED DUAL-METAL SILICIDE AND GERMANIDE FORMATION

Taiwan Semiconductor Manu...

1. A method comprising:growing a first epitaxy semiconductor region on a wafer, wherein the first epitaxy semiconductor region comprises an upward facing facet facing upwardly and a downward facing facet facing downwardly;
forming a second epitaxy semiconductor region on the upward facing facet and the downward facing facet;
forming a first metal layer over the second epitaxy semiconductor region on the upward facing facet; and
performing a first anneal, wherein the first metal layer reacts with the second epitaxy semiconductor region to form a first metal silicide/germanide layer, the downward facing facet being free of the first metal silicide/germanide layer.

US Pat. No. 10,115,596

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A T-SHAPE IN THE METAL GATE LINE-END

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a metal gate structure in a semiconductor device, the method comprising:removing a dummy poly gate;
removing interlayer (IL) oxide and shallow trench isolation (STI) using a dry etch process and a wet lateral etch process to form a reversed T-shape void in the semiconductor device; and
depositing metal gate material in the reversed T-shape void to form a reversed T-shape structure in a metal gate line-end.

US Pat. No. 10,115,593

CHEMICAL MODIFICATION OF HARDMASK FILMS FOR ENHANCED ETCHING AND SELECTIVE REMOVAL

Applied Materials, Inc., ...

1. A carbon-based hardmask layer, comprising:a substrate; and
an amorphous carbon layer above the substrate, the amorphous carbon layer comprising carbon and hydrogen, and the amorphous carbon layer comprising a metallic filler bonded to the carbon, wherein a total atomic percentage of the hydrogen in the amorphous carbon layer is between 5% and 50%, and the total atomic percentage of the metallic filler in the amorphous carbon layer is between 5% and 90%.

US Pat. No. 10,115,592

PATTERNING PROCESS WITH SILICON MASK LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A lithography method, comprising:forming an under layer on a substrate;
forming a silicon-containing middle layer on the under layer, wherein the silicon-containing layer includes a type of monomers that each has four cross-linkable sides, and wherein the silicon-containing middle layer has a thermal base generator (TBG) composite that is capable of releasing a base;
forming a photosensitive layer on the silicon-containing middle layer;
performing an exposing process to the photosensitive layer; and
developing the photosensitive layer, thereby forming a patterned photosensitive layer.

US Pat. No. 10,115,591

SELECTIVE SIARC REMOVAL

Tokyo Electron Limited, ...

1. A method for an integration process of selectively removing a silicon-containing antireflective coating (SiARC) in a substrate, the method comprising:providing a substrate in a process chamber, the substrate comprising:
a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer;
performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer;
performing a nitridation modification process on the SiARC layer of the structure, the nitridation modification process using a plasma of nitrogen ions and bombarding the SiARC layer to implant the nitrogen ions therein to an implantation depth, converting the SiARC layer into a nitrided SiARC layer having an increased nitrogen content; and
performing a removal process of the nitrided SiARC layer of the structure, wherein the increased nitrogen content increases percent removal of the SiARC layer and increases etch selectivity of the SiARC layer relative to the pattern transfer layer and/or the underlying layer.

US Pat. No. 10,115,590

MANUFACTURING OF SILICON STRAINED IN TENSION ON INSULATOR BY AMORPHISATION THEN RECRYSTALLISATION

1. A method for making a structure comprising a strained silicon layer, the method comprising:providing a substrate that has at least one region coated with a stack comprising a silicon semiconducting layer, the silicon semiconducting layer itself being coated with a second semiconducting area comprising silicon germanium, the second semiconducting area itself being coated with a third semiconducting area comprising an interface delimitation layer that is in contact with the second semiconducting area, the interface delimitation layer being made of silicon or silicon germanium with a germanium concentration lower than a germanium concentration of the second semiconducting area;
making at least one ion implantation such that the silicon semiconducting layer and the second semiconducting area are selectively amorphised, while keeping a continuous crystalline portion in the third semiconducting area; and then
recrystallising the second semiconducting area and the silicon semiconducting layer using the continuous crystalline portion of the third semiconducting area as a starting area for a recrystallisation front, the second semiconducting area imposing its parameter on the silicon semiconducting layer so as to strain the silicon semiconducting layer.

US Pat. No. 10,115,588

SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate treating apparatus, comprising:a mount unit on which a carrier for accommodating a plurality of substrates is placed;
a substrate level detecting mechanism that detects presence/absence of a substrate and a level of the substrate;
a substrate condition acquiring unit that acquires an inclination of the substrate in a forward/backward direction relative to a horizontal direction in accordance with the detected presence/absence of the substrate and the detected level of the substrate;
a poor inclination determining unit that determines whether or not the inclination of the substrate is larger than a pre-set threshold; and
an unloading order changing unit that reverses an order, in regard to unloading of the plurality of substrates in the carrier from the top, between the poor inclined substrate and a substrate at least immediately above the poor inclined substrate when the poor inclination determining unit determines presence of the poor inclined substrate.

US Pat. No. 10,115,587

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device comprising:providing a silicon wafer manufactured by a floating method from a polycrystalline silicon ingot, the silicon wafer having a first main surface and a second main surface that are opposite to each other;
forming an oxide layer on the first main surface of the silicon wafer, the oxide layer having an opening through which the silicon wafer is exposed and in which a diffusion source is filled; and
performing heat treatment to the silicon wafer with the oxide layer formed thereon, to thereby diffuse impurity from the diffusion source at the first main surface to the second main surface of the silicon wafer, so as to create a diffusion layer that forms a pn junction with the silicon wafer, wherein
the heat treatment is performed for a time that is at least as long as a time for forming the diffusion layer with a predetermined diffusion depth of 100 ?m, and
the entire heat treatment has a single heat treatment step that is performed in a diffusion furnace, in a nitrogen-free inert gas atmosphere and at a temperature that is more than 1300° C. and no more than 1350° C.

US Pat. No. 10,115,586

METHOD FOR DEPOSITING A PLANARIZATION LAYER USING POLYMERIZATION CHEMICAL VAPOR DEPOSITION

Tokyo Electron Limited, ...

1. A method for processing a substrate, the method comprising:providing a substrate containing a plurality of features with gaps between the plurality of features;
delivering precursor molecules by gas phase exposure to the substrate;
adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules; and
reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.

US Pat. No. 10,115,583

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

HITACHI KOKUSAI ELECTRIC ...

1. A method of manufacturing a semiconductor device, comprising:supplying a process gas to a process chamber in a state in which a substrate with an insulating film formed thereon is mounted on a substrate support part inside the process chamber;
forming a first silicon nitride layer on the insulating film by supplying a first electric power from a plasma generation part to the process chamber and generating plasma of the process gas; and
forming a second silicon nitride layer, whose stress is lower than a stress of the first silicon nitride layer, on the first silicon nitride layer by supplying a second electric power from an ion control part to the process chamber in addition to supplying the first electric power and generating the plasma of the process gas.

US Pat. No. 10,115,582

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate comprising a MEMS region and a connection region thereon;
a dielectric layer disposed on said substrate in said connection region;
a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer;
a connection pad disposed on said poly-silicon layer;
a passivation layer covering said dielectric layer and directly contacting with said poly-silicon layer, wherein said passivation layer comprises an opening that exposes entire said connection pad and a transition region between said connection pad and said passivation layer; and
a conductive layer conformally covering said connection pad and said poly-silicon layer in said opening of said passivation layer.

US Pat. No. 10,115,581

REMOVAL OF PARTICLES ON BACK SIDE OF WAFER

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:loading a semiconductor wafer into a wafer handling system, the semiconductor wafer having a front side and a back side and having an outer rim, an inner region, and an outer region, wherein one or more alignment marks are positioned in an outer region of the wafer's front side, wherein the outer region is shaped an as annular ring having a predetermined width, wherein an outer boundary of the annular ring is spaced apart from the outer rim of the wafer by a distance in a range of about 2 mm to about 3 mm;
removing, with a brush, contaminant particles in the outer region of the wafer's back side without brushing the outer rim and without brushing the inner region, such that the brush is passed over the outer region on the back side of the wafer;
holding the brush against the back side of the wafer with tension provided by a spring; and
collecting the removed contaminant particles and discarding the collected contaminant particles out of the wafer handling system.

US Pat. No. 10,115,580

METHOD FOR MANUFACTURING AN SOI WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for manufacturing an SOI wafer having an SOI layer including a thinning step to adjust an SOI film thickness of the SOI wafer, comprising the steps of:(A1) measuring the S01 film thickness of the SOI wafer having the SOT layer before the thinning step;
(A2) determining a rotational position of the SOI wafer by rotating the SOI wafer before the thinning step on the basis of a radial SOI film thickness distribution obtained in the measuring of the film thickness of the step (A1) and a previously determined radial stock removal distribution in the thinning step, and rotating the SOI wafer around the central axis thereof so as to bring the SOI wafer to the determined rotational position; and
(A3) thinning the SOI layer of the SOI wafer after being rotated in the step (A2), wherein the wafer is not rotated during the thinning step.

US Pat. No. 10,115,578

WAFER AND METHOD OF PROCESSING WAFER

Disco Corporation, Tokyo...

1. A method of processing a wafer having on a face side thereof a device area with a plurality of devices formed therein and an outer circumferential excess area surrounding the device area, comprising:a grinding step for grinding a reverse side of the wafer corresponding to the device area with a grinding wheel that is smaller in diameter than the wafer, thereby forming a first portion corresponding to the device area and an annular second portion surrounding said first portion, said annular second portion being thicker and more protrusive toward a reverse side thereof than said first portion,
wherein in the grinding step, said grinding wheel and said wafer are moved relatively to each other so that an angle formed between the reverse side of said first portion and an inner side surface of said annular second portion is larger than 45° and smaller than 75°.

US Pat. No. 10,115,577

ISOTOPE RATIO MASS SPECTROMETRY

California Institute of T...

1. A method of isotope ratio mass spectrometry, comprising:injecting a sample for analysis into a gas chromatography column;
directing an effluent from the gas chromatography column to a switching arrangement; and
selecting a configuration of the switching arrangement, such that: in a first mode, the effluent from the gas chromatography column is provided as an input to a peak broadener; and in a second mode, an effluent from the peak broadener is provided to a mass spectrometer for isotope ratio mass spectrometry without the effluent from the gas chromatography column being provided as an input to the peak broadener.

US Pat. No. 10,115,576

METHOD AND AN APPARATUS FOR ANALYZING A COMPLEX SAMPLE

WATERS TECHNOLOGIES CORPO...

1. A computer-implemented method of analyzing a complex sample, comprising:generating, via a sequential chromatographic-IMS-MS apparatus, a separated sample by separating the complex sample based on a chromatographic retention time via a chromatography module and an ion-mobility drift time via an ion-mobility spectrometry (IMS) module;
performing, via a mass spectrometry (MS) module of the sequential chromatographic-IMS-MS apparatus, mass analysis of the separated sample to generate a plurality of experimental mass spectra having isotopic clusters, wherein each spectrum of the plurality of spectra is associated with the chromatographic retention time and the ion-mobility drift time; and
resolving, via a data processing unit operably coupled to the sequential chromatographic-IMS-MS apparatus, one or more saturated or interfered peaks of the experimental isotopic cluster by:
calculating a model isotopic cluster of a precursor or product ion associated with a candidate compound in the sample, in correspondence to the natural isotopic-abundance ratios of elements composing the compound; and
comparing peaks of the model isotopic cluster to corresponding peaks of an isotopic cluster of one of the experimental mass spectra to extract one or more saturated or interfered peaks of the experimental isotopic cluster, wherein the peaks of the experimental isotopic cluster comprise at least one un-saturated and un-interfered peak.

US Pat. No. 10,115,575

PROBABILITY-BASED LIBRARY SEARCH ALGORITHM (PROLS)

DH Technologies Developme...

1. A system for determining corresponding mass peaks in experimental and library product ion spectra using a mass-to-charge ratio (m/z) tolerance probability function with values between 1 and 0, comprising:an ion source that ionizes one or more known compounds of a sample, producing an ion beam of precursor ions;
a tandem mass spectrometer that receives the ion beam from the ion source and that selects at least one precursor ion from the ion beam corresponding to at least one compound of the one or more known compounds and fragments the at least one precursor ion, producing a product ion mass spectrum for the at least one precursor ion; and
a processor in communication with the tandem mass spectrometer that
receives the product ion mass spectrum from the tandem mass spectrometer,
receives an m/z tolerance probability function that varies from 1 to 0 with increasing values of an m/z difference between two mass peaks and that includes one or more values between 1 and 0,
retrieves from a memory a library product ion mass spectrum for the at least one compound,
calculates an m/z difference between at least one experimental product ion mass peak in the product ion mass spectrum and at least one library product ion mass peak in the library product ion mass spectrum,
calculates an m/z tolerance probability, (pm/z)1, from the m/z difference using the m/z tolerance probability function, and
determines if the at least one experimental product ion mass peak and the at least one library product ion mass peak are corresponding peaks based on the m/z tolerance probability, (pm/z)1.

US Pat. No. 10,115,574

HERMETICALLY SEALED MAGNETIC KEEPER CATHODE

Kurt J. Lesker Company, ...

1. A sputtering cathode comprising:a magnet array including an outer, ring magnet surrounding an inner, disk magnet;
a sputtering target on one side of the magnet array covering a side of the ring magnet and a side of the disk magnet;
a magnetic keeper disk between the sputtering target and the disk magnet, the magnetic keeper disk in contact with the sputtering target and spaced from the disk magnet by a gap;
a cooling well between the ring magnet and the disk magnet, wherein the cooling well is in direct contact with the sputtering target;
one or more cooling tubes coupled to the cooling well;
an outer body flange surrounding the one or more cooling tubes and contacting a side of the ring magnet opposite the sputtering target;
an inner body flange contacting a side of the disk magnet opposite the sputtering target; and
one or more insulators positioned between the ring magnet and the disk magnet, the one or more insulators coupling the inner body flange, the outer body flange, and the one or more cooling tubes together in an operative relation, and electrically isolating the inner body flange, the outer body flange, and the one or more cooling tubes from each other without the use of one or more elastomer seals.

US Pat. No. 10,115,573

APPARATUS FOR HIGH COMPRESSIVE STRESS FILM DEPOSITION TO IMPROVE KIT LIFE

APPLIED MATERIALS, INC., ...

1. A process kit, comprising:a first ring having an inner wall defining an inner diameter, an outer wall defining an outer diameter, an upper surface disposed between the inner wall and the outer wall, and an opposing lower surface disposed between the inner wall and the outer wall, wherein a first portion of the upper surface proximate the inner wall is concave, and wherein a second portion of the upper surface has a length that extends horizontally away from the first portion and terminates at the outer wall; and
a second ring having an upper surface and an opposing lower surface, wherein a first portion of the lower surface of the second ring is configured to rest upon the length of the upper surface of the second portion of the first ring, wherein a second portion of the lower surface of the second ring is convex and extends into but does not touch the concave first portion of the upper surface of the first ring.

US Pat. No. 10,115,572

METHODS FOR IN-SITU CHAMBER CLEAN IN PLASMA ETCHING PROCESSING CHAMBER

Applied Materials, Inc., ...

1. A method for in-situ chamber cleaning after an etching process, comprising:supplying a cleaning gas mixture including at least an oxygen containing gas and a hydrogen containing gas into a processing chamber in which the etching process was performed on a substrate comprising Cr containing material;
controlling a processing pressure at less than 2 millitorr;
applying a RF source power to the processing chamber to form a plasma from the cleaning gas mixture; and
cleaning the processing chamber in the presence of the plasma.

US Pat. No. 10,115,571

REAGENT DELIVERY SYSTEM FREEZE PREVENTION HEAT EXCHANGER

APPLIED MATERIALS, INC., ...

1. A reagent delivery system, comprising:a water tank having an inner volume that holds a reagent liquid when disposed therein; and
a heat exchanger having a central opening disposed in the inner volume and configured to keep a top surface of the reagent liquid from freezing when reagent liquid is disposed within the water tank,
wherein the heat exchanger is formed from a plurality of concentric cylinders that permits a flow of a reagent liquid between the concentric cylinders, and wherein each of the plurality of concentric cylinders is perforated to allow the reagent liquid to flow through the concentric cylinders.

US Pat. No. 10,115,570

PLASMA SOURCE AND METHODS FOR DEPOSITING THIN FILM COATINGS USING PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION

AGC FLAT GLASS NORTH AMER...

1. A method of forming a coating using plasma enhanced chemical vapor deposition (PECVD), comprising:a) providing a plasma source comprising a first hollow cathode and a second hollow cathode disposed adjacently and separated by a space;
b) producing, with the plasma source, a plasma that is linear and that is made substantially uniform over its length in the substantial absence of Hall current;
c) providing a substrate with at least one surface to be coated proximate to the plasma;
d) flowing a precursor gas through the space;
e) energizing, partially decomposing, or fully decomposing the precursor gas by contacting the plasma with the precursor gas; and
f) depositing the coating on the at least one surface of the substrate using PECVD;
wherein the depositing includes one of bonding and condensing a chemical fragment of the precursor gas containing a desired chemical element for coating on the at least one surface of the substrate.

US Pat. No. 10,115,569

PLASMA GENERATOR

JEHARA CORPORATION, Gyeo...

1. A plasma generator which includes a source electrode unit and a bias electrode unit disposed to face each other in a vacuum chamber and an RF power unit and a bias RF power unit supplying RF power to the source electrode unit and the bias electrode unit, respectively, the plasma generator comprising:a common contact point which is connected with a plurality of contact points disposed along the edge of the source electrode unit; and
an impedance controller which is connected with the common contact point to control the impedance.

US Pat. No. 10,115,567

PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus of generating plasma by high frequency discharge of a processing gas within a decompression processing vessel that accommodates therein a processing target object, which is loaded into and unloaded from the processing vessel, and performing a process on the processing target object within the processing vessel with the plasma, the plasma processing apparatus comprising:a first high frequency power supply configured to output a first high frequency power;
a first high frequency power modulation unit configured to pulse-modulate an output of the first high frequency power supply with a modulation pulse having a regular frequency such that the first high frequency power has a high level during a first period and has a low level lower than the high level during a second period, the first period and the second period being repeated alternately with a preset duty ratio;
a first high frequency transmission line configured to transmit the first high frequency power outputted from the first high frequency power supply to a first electrode provided within or in the vicinity of the processing vessel; and
a first matching device configured to measure a load impedance on the first high frequency transmission line with respect to the first high frequency power supply, and configured to match a weighted average measurement value, which is obtained by weighted-averaging a load impedance measurement value during the first period and a load impedance measurement value during the second period with a preset weighted value, with an output impedance of the first high frequency power supply.

US Pat. No. 10,115,566

METHOD AND APPARATUS FOR CONTROLLING A MAGNETIC FIELD IN A PLASMA CHAMBER

APPLIED MATERIALS, INC., ...

1. An electromagnetic cosine-theta (cos ?) coil ring assembly for use in a process, comprising:a cylindrical body;
an inner electromagnetic cosine-theta (cos ?) coil ring including a first plurality of inner coils disposed about an inner surface of the cylindrical body and configured to generate a magnetic field in a first direction; and
an outer electromagnetic cosine-theta (cos ?) coil ring including a second plurality of outer coils disposed about an outer surface of the cylindrical body and configured to generate a magnetic field in a second direction different from the first direction, wherein the outer electromagnetic cos ? coil ring is disposed concentrically about the inner electromagnetic cos ? coil ring.

US Pat. No. 10,115,563

ELECTRON-BEAM LITHOGRAPHY METHOD AND SYSTEM

NATIONAL TAIWAN UNIVERSIT...

1. An electron-beam lithography method, comprising:performing a low-temperature treatment to chill a developer solution;
utilizing an electron-beam to irradiate an exposure region of a positive-tone electron-sensitive layer; and
utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer, wherein the development region is present within the exposure region, and an area of the development region is smaller than an area of the exposure region;
inputting a size value of a predetermined pattern to be formed in the positive-tone electron-sensitive layer into a pattern dimension simulation system; and
computing and outputting a parameter recipe of the electron-beam used to irradiate the positive-tone electron-sensitive layer by the pattern dimension simulation system, wherein the parameter recipe of the electron-beam includes a high current parameter, and the high current parameter is substantially in a range between 30 pA to 300 pA, such that the pattern dimension simulation system is based on a model of two dimensional Gaussian function.

US Pat. No. 10,115,562

SYSTEMS INCLUDING A BEAM PROJECTION DEVICE PROVIDING VARIABLE EXPOSURE DURATION RESOLUTION

Samsung Electronics Co., ...

1. A beam projection device, comprising: a charged particle beam source configured to radiate a first beam; an aperture plate having a first array of apertures therein, respective ones of the apertures configured to generate respective second beams from the first beam; a blanking aperture plate having an array of blanking apertures therein corresponding to respective apertures of the first array of apertures and configured to selectively deflect second beams passing therethrough responsive to voltages applied to respective potential electrodes of the blanking apertures; a limiting aperture plate comprising a limiting aperture configured to pass ones of the second beams not deflected by the blanking apertures; and a plurality of electrode control circuits, respective ones of which are configured to apply voltages to respective ones of the potential electrodes, wherein, during a first time interval, the plurality of electrode control circuits applies voltages to the potential electrodes for durations based on clock signal with a first frequency, wherein, during a second time interval, the plurality of electrode control circuits applies voltages to the potential electrodes for durations based on a clock signal with a second frequency different from the first frequency, and wherein, during the first time interval and second time interval, beams passing through the limiting aperture are projected on the same target object to provide overlapping exposures of the target object.

US Pat. No. 10,115,560

APPARATUS FOR MODIFYING SURFACES OF TITANIUM IMPLANTS MADE OF TITANIUM ALLOY

Sodick Co., Ltd., Kanaga...

1. A metal surface modification apparatus for modifying surfaces of titanium implants made of a titanium alloy, the metal surface modification apparatus comprising:a vacuum chamber configured to accommodate the implants in a vacuum environment;
a transfer unit disposed within the vacuum chamber, and configured to move the implants at least in a first horizontal uniaxial direction and in a second horizontal uniaxial direction perpendicular to the first horizontal uniaxial direction;
a table disposed on the transfer unit, and configured such that the implants are placed thereon;
an electron gun including a cathode electrode, an annular anode electrode configured to generate plasma, and a solenoid configured to generate a magnetic field; and
a tilting unit configured to tilt the implants to a predetermined angle as the transfer unit moves the implants;
wherein the tilting unit further comprises:
a plurality of holding jigs configured to have a plurality of respective lower parts having curved surfaces, respectively, and to hold the implants, respectively;
a movable holding base fastened onto the table, and configured to have a plurality of receiving depressions formed through an upper surface thereof to have curved surfaces corresponding to the curved surfaces of the lower parts of the holding jigs; and
a stationary pushing plate disposed on the movable holding base to cover the movable holding base, and configured to be moved relative to the movable holding base and to have a plurality of through holes positioned to face the receiving depressions.

US Pat. No. 10,115,559

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

HERMES MICROVISION, INC.,...

1. A method for converting a single charged particle source into a plurality of virtual sub-sources, comprising steps of:deflecting, by a plurality of micro-deflectors of a micro-deflector array, a charged-particle beam of the single charged-particle source into a plurality of parallel beamlets forming a plurality of virtual images respectively, wherein each of the plurality of virtual images is one of the plurality of sub-sources;
adding, by a plurality of micro-compensators of a micro-compensator array, aberrations to each of the plurality of virtual images, wherein each micro-compensator of the plurality of micro-compensators is aligned with a corresponding one of the micro-deflectors; and
cutting a current of each of the plurality of beamlets.

US Pat. No. 10,115,557

X-RAY GENERATION DEVICE HAVING MULTIPLE METAL TARGET MEMBERS

HAMAMATSU PHOTONICS K.K.,...

1. An X-ray generation device comprising:an electron gun for emitting an electron beam;
a target unit having a target buried in a substrate having principal faces opposed to each other;
a housing at one end side of which the target unit is arranged and at the other end side opposed to the one end side of which the electron gun is arranged, the housing having an electron passage for the electron beam to pass;
a deflector for deflecting the electron beam passing in the electron passage to enable scanning on the target unit;
a signal acquisition unit for acquiring an incident signal generated from scanning the target unit with the electron beam; and
a control unit for controlling the deflector, based on the incident signal acquired by the signal acquisition unit,
wherein the target unit comprises:
the substrate comprising an electrical insulating material having X-ray permeability
a plurality of first metal members buried in the substrate and serving as the target; and
one or more second metal members, the one or more second metal members being surrounded by the plurality of first metal members or surrounding at least one of the plurality of first metal members, and the one or more second metal members generating location information by serving as a reference when identifying a location of the at least one of the plurality of first metal members based on the incident signal generated from the scanning with the electron beam,
wherein the one or more second metal members, when viewed from a normal direction to the principal faces, have a surface area larger than the a surface area of the plurality of first metal members, and have a length in the normal direction shorter than a length of the target, and
the control unit controls the deflector to scan the electron beam over the target, detects the plurality of first metal members based on the location information of the one or more second metal members acquired from the incident signal, and controls the deflector to irradiate the first metal member with the electron beam and generate X-rays.

US Pat. No. 10,115,556

TRIODE HOLLOW CATHODE ELECTRON GUN FOR LINEAR PARTICLE ACCELERATORS

Altair Technologies, Inc....

1. A triode hollow-cathode electron gun configured to provide electrons and substantially mitigates the impact of back-streaming electrons, the triode hollow-cathode electron gun comprising;a hollow cathode with a concave surface configured to emit a beam of electrons, wherein the cathode is impregnated with Barium to enhances emission of the beam of electrons by lowering work function of the cathode, and wherein the hollow cathode includes an axially-oriented cylindrical channel configured to accommodate back streaming of the beam of electrons;
a heating filament configured to provide heat to the hollow cathode enabling a thermionic emission process;
an anode configured to attract and focus the beam of electrons emitted from the hollow cathode by maintaining a positive voltage potential relative to the cathode;
a control grid configured to control or modulate and focus the beam of electrons emitted from the hollow cathode, wherein the control grid has a concave profile; and
a protruding sleeve that is substantially centered on the axis of the triode hollow-cathode electron gun and configured to maintain a convergent shape and a trajectory of the emitted beam of electron, wherein the protruding sleeve increasing the laminarity of the beam of electrons by reducing undesirable transverse momentum of the beam of electrons, and wherein the sleeve is further configured to inhibit release of Barium from the cathode thereby increasing cathode life.

US Pat. No. 10,115,555

ELECTRICAL SWITCH FOR A LOAD IN A VEHICLE

Amazon Technologies, Inc....

1. An unmanned aerial vehicle (UAV), comprising:a frame;
a power load;
a power source; and
an electrical switch comprising a moving member and a plurality of electrically conductive members, the plurality of electrically conductive members configured to move between mechanical positions in a predefined order to electrically couple the power load and the power source, wherein:
a first electrically conductive member is configured to move to a first mechanical position and form a first electrically conductive path between the power load and the power source based at least in part on the first mechanical position, the first electrically conductive path having first electrical resistivity;
a second electrically conductive member is configured to move to a second mechanical position and form a second electrically conductive path between the power load and the power source based at least in part on the second mechanical position, the second electrically conductive path having second electrical resistivity different from the first electrical resistivity; and
the moving member is configured to move the second electrically conductive member based at least in part on movement of the first electrically conductive member to the first mechanical position such that movement of the second electrically conductive member to the second mechanical position occurs based at least in part on the movement of the first electrically conductive member according to the predefined order.

US Pat. No. 10,115,554

FUSE CASE AND CASE COVER OF VACUUM CONTACTOR

LSIS CO., LTD., Anyang-S...

1. A fuse case and a case cover, which are detachable and applied to a vacuum contactor including a truck, a main circuit unit, and a front cover covering a front side of the main circuit unit, the fuse case and the case cover comprising:a fuse connected to an upper terminal of the main circuit unit and blowing, when a fault current is generated in a circuit, to break the circuit;
the fuse case opened in an upper side, accommodating the fuse, and having an insertion coupling part formed on a side surface thereof; and
the case cover coupled to the upper side of the fuse case, coupled to the insertion coupling part in an insertion-coupling manner, and covering a rear end portion of the fuse,
wherein the case cover includes an upper surface portion and side surface portions, and the side surface portions include a first side surface portion formed on a front side and a second side surface portion formed on a rear side,
wherein the first and second side surface portions are formed as dual walls and have a first rail recess and a second rail recess, respectively, and
wherein the side surface of the fuse case is inserted into the first rail recess and the second rail recess.

US Pat. No. 10,115,553

GROUND FAULT CIRCUIT INTERRUPTER AND RESET MECHANISM THEREOF

ZHANGJIAGANG CITY BAREP E...

1. A reset mechanism of a ground fault circuit interrupter (GFCI), comprising: a reset button and a reset lever disposed at a bottom of the reset button, wherein the reset mechanism further comprises: an electromagnet, a slide rocker, a rotary lifting block, and a reset mounting bracket, wherein rotating shafts are separately disposed at two sides of the rotary lifting block; the rotary lifting block is disposed on the reset mounting bracket in a movable manner by using the pair of rotating shafts; lifting parts protruding outwards are separately disposed at two sides of one end of the rotary lifting block; a clamping hook facing inwards is disposed on a bottom surface of another end of the rotary lifting block; a lifting block spring used for resetting the rotary lifting block is disposed on one side of the lifting part of the rotary lifting block; a bottom of the lifting block spring abuts against the rotary lifting block; a position-limiting block matched with one side of the lifting part of the rotary lifting block is disposed on the reset mounting bracket; the reset mounting bracket is provided with a rocker insertion hole matched with the slide rocker below the rotary lifting block; the slide rocker penetrates the rocker insertion hole in a movable manner; the slide rocker is provided with a rocker bending part on an end part of one side of the lifting part of the rotary lifting block; an end part of the rocker bending part is provided with a rocker bayonet; the electromagnet is disposed at one side of the rocker bending part of the slide rocker; an iron core of the electromagnet is provided with an iron core card slot matched with the rocker bayonet; the rocker bayonet is clamped to the iron core card slot of the iron core; the reset lever is disposed above one side of the clamping hook of the rotary lifting block in a movable manner; and a reset lever spring used for resetting the reset button is sleeved on the reset lever.

US Pat. No. 10,115,552

RETROFIT CAFI/GFI REMOTE CONTROL MODULE

Schneider Electric USA, I...

1. A retrofit remote control module providing a simple thermal-magnetic circuit breaker with arc fault or ground fault, or both, sensing and interruption capabilities for a branch circuit, comprising:a case housing a current path with neutral and line conductors,
line sensors for sensing current flow within the current path,
electronics connected to the line sensors to determine anomalies in the sensed current flow, and
a bistable relay in the current path between the simple thermal-magnetic circuit breaker and the load, the relay being operated by said electronics to open the branch circuit; and
connectors for attaching the neutral and line conductors to a branch circuit on a downstream side of the module, and attaching the neutral and line conductors to the load side of the simple thermal-magnetic circuit breaker on an upstream side of the module.

US Pat. No. 10,115,551

PROTECTIVE CIRCUIT BREAKER

SIEMENS AKTIENGESELLSCHAF...

1. A protective circuit breaker comprising:a switch housing;
a first and a second connection piece, each of the first and a second connection pieces extending on a rear side through and outside the switch housing and each of the first and a second connection pieces being connectable to a busbar;
a switching contact, arranged in the switch housing, including two contact elements configured to rest against one another when the switching contact is closed and configured to separate from one another when the switching contact is open, wherein at least one of the two contact elements is designed to be movable, and wherein the two contact elements are each respectively electrically connected to a respective one of the first and a second connection pieces;
a converter housing, including a first passage opening, inserted into a recess in the switch housing, wherein the second connection piece runs through the first passage opening;
a converter coil, arranged in the converter housing around the passage opening and around the second connection piece, connectable to a first electronics system to trigger opening of the switching contact;
a plate-like converter cover, covering the converter housing to the outside and including a second passage opening through which the second connection piece extends and runs to the outside, a side of the plate-like converter cover, facing the protective circuit breaker, including arranged on thereon
a first contact bearing against the second connection piece at the plate-like converter cover in a region of the passage opening,
a second contact, electrically connectable to the first connection piece, and
a third contact, connectable to the first or a second electronics system; and
an electrical connection, via which the third contact is selectively connectable to the first or second contact.

US Pat. No. 10,115,550

ELECTRICAL SWITCHING DEVICE WITH A LOW SWITCHING NOISE

TE Connectivity Germany G...

1. An arrangement for an electrical switching device, comprising:a contact spring; and
a component attached to the contact spring at a fastening location and having an edge extending in an inclined manner with respect to a longitudinal direction of the contact spring, the component having at least two switching state positions and a transition phase between the switching state positions, the component movable with respect to the contact spring between the two switching state positions and abutting the contact spring along the edge in the transition phase, the edge abutting the contact spring at an abutting location positioned at an intersection of the edge with a line extending through the fastening location orthogonal to the longitudinal direction.

US Pat. No. 10,115,549

ELECTRICAL STORAGE SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. An electrical storage system comprising:an electrical storage device;
a load;
a positive electrode line that connects the electrical storage device to the load;
a negative electrode line that connects the electrical storage device to the load;
a first relay provided in the positive electrode line;
a second relay provided in the negative electrode line;
a third relay connected in series with a first resistive element, the third relay and the first resistive element being connected in parallel with the first relay, the first resistive element being provided in the positive electrode line;
a drive circuit including a coil, a first power line, a second power line, and a sensor,
the coil being configured to generate electromagnetic force for switching the second relay and the third relay from a non-energized state to an energized state by energization at a first current value, the coil being configured to generate electromagnetic force for switching the first relay, the second relay and the third relay from a non-energized state to an energized state by energization at a second current value larger than the first current value, the energized state being on state, the non-energized state being off state,
the first power line including a first switch element and a second switch element connected in series with each other, the first power line being configured to supply current having the second current value from a power supply to the coil,
the second power line including a second resistive element and a third switch element connected in series with each other, the second power line being configured to supply current having the first current value from the power supply to the coil, and
the sensor being configured to change an output signal on the basis of whether each switch element is in the energized state or the non-energized state,
the drive circuit being configured to cause both the second and third relays and the first relay to operate at different timings; and
a controller configured to:
(a) control operation of the drive circuit,
(b) output a control signal for setting each switch element to the non-energized state, and
(c) determine whether any one of the switch elements has a failure in the energized state on the basis of the output signal of the sensor.

US Pat. No. 10,115,548

GAS CIRCUIT BREAKER

MITSUBISHI ELECTRIC CORPO...

1. A gas circuit breaker comprising:a rod-shaped fixed arc contact;
a cylindrical movable arc contact to contact or be separated from the fixed arc contact, the movable arc contact having a plurality of contact pieces on a side of the fixed arc contact, the contact pieces being separated from one another by a plurality of slits arranged in a circumferential direction of the movable arc contact and extending in an axial direction of the movable arc contact, each of the contact pieces having a proximal part and a distal end part larger in thickness than the proximal part, the distal end part of each contact piece including a bend having opposed walls extending in the axial direction of the movable arc contact, the distal end parts of the plurality of contact pieces having receiving holes, each of the receiving holes being defined between the opposed walls of a corresponding one of the distal end parts;
a puffer chamber storing an arc-extinguishing gas to be blown to an arc generated between the fixed arc contact and the movable arc contact; and
an insulator received within the receiving holes, the receiving holes being open to an opposite side to a side of the fixed arc contact, a portion of an end surface of the insulator on the side of the fixed arc contact facing the side of the fixed arc contact via opening ends of the slits on the side of the fixed arc contact, the end surface on the side of the fixed arc contact being disposed on the opposite side to the side of the fixed arc contact and farther from the side of the fixed arc contact than the opening ends are, the insulator being made of an ablation material to be vaporized by heat of the arc.

US Pat. No. 10,115,546

ELECTRICAL TRIPOUT DEVICE INTEGRATING A CIRCUIT BREAKER AND AN ISOLATOR

GENERAL ELECTRIC TECHNOLO...

1. A current-interrupter device (1) comprising a circuit breaker (2) including a first stationary conductive support (4) carrying both a stationary arcing contact (14) and a movable arcing contact (16) that is movable between a closed position and an open position, and also carrying a movable permanent contact (17) that is movable between a closed position and an open position, the movable arcing contact (16) and the movable permanent contact (17) being dynamically linked together by forming a single movable unit and being electrically connected to the first stationary conductive support (4), and a disconnector (3) including a second stationary conductive support (6) carrying a disconnector contact (18) that is movable between a closed position and an open position, and wherein:the movable disconnector contact (18) is electrically connected with the stationary arcing contact (14) when the movable disconnector contact (18) is in its closed position;
the movable disconnector contact (18) is spaced apart from the stationary arcing contact (14) when the movable disconnector contact (18) is in its open position;
the movable disconnector contact (18) and the movable permanent contact (17) are electrically connected to each other when they are both in their respective closed positions;
the movable disconnector contact (18) and the movable permanent contact (17) are spaced apart from one another when the movable disconnector contact (18) is in its open position; and
the movable disconnector contact (18) and the movable permanent contact (17) are spaced apart from one another when the movable permanent contact (17) is in its open position.

US Pat. No. 10,115,545

ACTUATING METHOD AND DEVICE FOR A HELICOIDAL SWITCH

GORLAN TEAM, S.L.U., (ES...

1. An actuating device for mechanically converting rotational movement into helicoidal movement, the actuating device comprising:a fixed body having a through cavity extending along an axis, said fixed body being provided with two guiding surfaces parallel to one another and arranged in an inclined manner,
a moving rod housed such that it has the capacity for movement in said through cavity, the moving rod being provided with a lug emerging radially with respect to an axial axis of the rod,
wherein said lug is arranged tightly between said guiding surfaces, such that it can slide over them, making contact with both surfaces; and
wherein the guiding surfaces comprise an annular shape arranged around the through cavity, and where the guiding surfaces are accessible from outside the fixed body.

US Pat. No. 10,115,544

SINGULATED KEYBOARD ASSEMBLIES AND METHODS FOR ASSEMBLING A KEYBOARD

APPLE INC., Cupertino, C...

1. A row of interconnected key assemblies comprising:an array of key assemblies, each key assembly comprising:
a chassis having a first retaining feature and a second retaining feature;
a switch housing formed on the chassis;
a key mechanism surrounding the switch housing and engaged with the first retaining feature; and
a buckling dome positioned within an opening defined through the switch housing and engaged with the second retaining feature.

US Pat. No. 10,115,543

KEYBOARD COVER AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A keyboard cover, comprising:a first sheet material having a surface including a plurality of key tops configured of roughened convex surfaces and a base configured of a smooth surface connecting a plurality of the key tops, a plurality of the key tops being projected from the base viewed from the surface; and
a second sheet of porous material covering a rear surface of the first sheet material and having concave parts corresponding to a plurality of the key tops viewed from the rear surface;
wherein the first sheet material includes:
a surface layer composed of a synthetic resin material forming the surface, and
an intermediate layer disposed between the surface layer and the second sheet material and composed of a thermoplastic resin material;
wherein a plurality of the key tops in the first sheet material includes at least one groove disposed along a diagonal line in a plane of the key tops.

US Pat. No. 10,115,539

LUMINATED KEY STRUCTURE AND ELECTRONIC DEVICE WITH THE SAME

Chiun Mai Communication S...

1. A key structure comprising:a substrate having at least one light emitting element disposed on a substrate surface thereof;
a light guiding element being made of optical transmission material and disposed opposite to the substrate; wherein the light guiding element comprises a main body and a light guiding portion, and the main body comprises a first surface and a second surface opposite to the first surface, wherein the light guiding portion projects from the first surface, and the light guiding portion and the first surface cooperatively form a receiving space;
a key body being mad of opaque material and received in the receiving space;
a first reflective film being disposed on the second surface;
a second reflective film being disposed on the substrate surface of the substrate;
wherein when light is emitted from the at least one light emitting element, the light is reflected between the first reflective film and the second reflective film, transmitted to the light guiding portion, and transmitted out of the key structure through the light guiding portion.

US Pat. No. 10,115,538

LIGHT-PERVIOUS BICOLOR KEY CAP

TAIWAN TAI-HAO ENTERPRISE...

1. A light-pervious bicolor key cap, including:a key frame, having a first color and formed with a plurality of thin ribs, wherein front ends of said plural thin ribs are formed with at least one letter or one punctuation, and said letter or said punctuation is formed in a continuous status without any notch; and
a cap cover, having a second color, wherein said letter or said punctuation is formed on a surface of said cap cover so as to form a bicolor key cap, an outer side of said cap cover is formed with a material filling protrusion allowing a plastic having said second color to be filled in, and an inner surface of said cap cover is formed with at least one convex piece located below said letter or said punctuation, and said plastic having said second color is allowed to pass two sides defined at a bottom end of said convex piece for enabling said convex piece having said second color to be formed, and said convex piece is not fixedly combined with said key frame; so that through removing said convex piece, said letter or said punctuation of said cap cover is prevented from being formed with any notch and capable of allowing light to fully permeate.

US Pat. No. 10,115,537

APPARATUS FOR DETECTING A SWITCH POSITION

Robert Bosch GmbH, Stutt...

1. An apparatus for detecting a configuration of a switch comprising:a first circuit node and a second circuit node configured to connect the apparatus to an AC electric voltage;
a switch connected between the first circuit node and a third circuit node;
a resistor connected between the first circuit node and the third circuit node in parallel with the switch;
a calculation device connected between the second circuit node and a microcomputer device, the calculation device further comprising at least one transistor or filter stage configured to generate digitized values of the AC electric voltage for detection by the microcomputer device; and
the microcomputer device operatively connected to the calculation device and configured to identify the configuration of the switch, the microcomputer device being operatively configured to:
measure a first amplitude of a positive half-cycle of the AC electric voltage during at least one full cycle of the AC electric voltage based on the digitized values generated by the calculation device;
measure a second amplitude of a negative half-cycle of the AC electric voltage during the at least one full cycle of the AC electric voltage based on the digitized values generated by the calculation device;
detect that the switch is open in response to an asymmetry between the first amplitude and the second amplitude of the AC electric voltage; and
detect that the switch is closed in response to a symmetry between the first amplitude and the second amplitude of the AC electric voltage.

US Pat. No. 10,115,536

ELECTROMAGNETIC ACTUATOR AND ELECTRICAL CONTACTOR COMPRISING SUCH AN ACTUATOR

SCHNEIDER ELECTRIC INDUST...

1. An electromagnetic actuator for operation of an electrical contactor, the actuator comprising:a fixed part including:
at least one coil that generates a magnetic field and that is centered on a longitudinal axis,
at least one core that concentrates the magnetic flux, the core being installed within the coil, and including a spreading plate for the magnetic field which defines an active surface which is perpendicular to the longitudinal axis and at least one magnetic flux return element;
an armature that is moveable in translation along the longitudinal axis with respect to the fixed part, between a first position which is remote from the active surface and a second position which is closer to the surface, in response to a load induced by the magnetic field;
at least one elastic return member that restores the armature to a predetermined position, from among the first position and the second position;
wherein the spreading plate includes at least one rib closing magnetic field lines between the spreading plate and the armature, the rib protrudes with respect to the active surface on the armature side, the rib is arranged at a level of one edge of the spreading plate, and the rib includes braces extending in a direction perpendicular to a longest dimension of the rib.

US Pat. No. 10,115,535

ELECTRIC STORAGE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electric storage device comprising:an electric storage element having a positive electrode and a negative electrode;
a non-aqueous electrolytic solution that contains a non-aqueous solvent primarily constituted by a non-carbonate cyclic ester and a cyclic carbonate ester, an electrolyte containing lithium salt, and a sulfonate ester derivative whose reduction potential is higher than that of the non-carbonate cyclic ester and that of the cyclic carbonate ester; and
an outer container that stores the electric storage element and non-aqueous electrolytic solution,
wherein a volume ratio of the non-carbonate cyclic ester to the cyclic carbonate ester in the non-aqueous solvent is 1/9 or more but 7/3 or less.

US Pat. No. 10,115,533

RECHARGEABLE POWER SOURCE COMPRISING FLEXIBLE SUPERCAPACITOR

UNIVERSITI PUTRA MALAYSIA...

1. A rechargeable power source for an electronic device, characterized in that, the rechargeable power source comprising:a flexible supercapacitor comprising an electrolyte sandwiched between nickel foams electrodeposited with a nanocomposite, wherein the said nanocomposite comprises a conducting polymer, graphene oxide and a metal oxide; and
a charge connection unit comprising a microcontroller having an electrical connection line connecting an energy collecting unit with the flexible supercapacitor.

US Pat. No. 10,115,531

ENERGY STORAGE DEVICE HAVING IMPROVED HEAT-DISSIPATION CHARACTERISTIC

LS MITRON LTD., Anyang-s...

1. An energy storage device, comprising:a cell assembly formed by connecting at least two cylindrical energy storage cells in series;
a case having an accommodation portion shaped corresponding to an outer surface of the energy storage cells to accommodate the cell assembly; and
a heat-dissipating pad installed between the outer surface of the energy storage cells of the cell assembly and an inner surface of the accommodation portion,
wherein the case includes at least two case blocks,
wherein the accommodation portion is formed by coupling the case blocks,
wherein the heat-dissipating pad has elasticity, and
wherein an interval between the accommodation portion and the energy storage cells is smaller than a thickness of the heat-dissipating pad before being compressed and greater than a diameter tolerance of the energy storage cells.

US Pat. No. 10,115,530

SOLAR CELL AND METHODS OF FABRICATION AND USE THEREOF

SEQUENCE DESIGN LTD., No...

1. A dye-sensitized solar cell comprising:a) a first electrically conductive layer;
b) a mesoporous oxide layer contiguous with the first electrically conductive layer and comprised of volcanic ash particles and photoactive dye molecules adsorbed on the ash particles;
c) an electrolyte layer contiguous with the mesoporous oxide layer and comprised of a redox mediator;
d) a catalyst layer comprised of an electrically conductive catalyst material; and
e) a second electrically conductive layer contiguous with the catalyst layer.

US Pat. No. 10,115,529

ELECTROLYTIC CAPACITOR HAVING A SOLID ELECTROLYTE LAYER AND MANUFACTURING METHOD THEREOF

NIPPON CHEMI-CON CORPORAT...

1. A solid electrolytic capacitor, comprising:a capacitor element with an anode electrode foil and a cathode electrode foil wound with an interposed separator,
a solid electrolyte layer formed in the capacitor element by using a conductive polymer dispersion in which particles of a conductive polymer are dispersed in a solvent; and
voids inside the capacitor element in which the solid electrolyte layer has been formed filled with an electrolytic solution containing less than 9 wt % of an ammonium salt of a composite compound of inorganic acid and organic acid as a solute and containing 20 wt % or more ethylene glycol with respect to a solvent in the electrolytic solution.

US Pat. No. 10,115,527

THIN FILM DIELECTRIC STACK

BlackBerry Limited, Wate...

1. A method for fabricating a thin film capacitor, the method comprising:determining a first temperature according to a material of a first electrode layer and according to a determination of a hillock temperature above which hillocks form on the material, wherein the first temperature is below the hillock temperature;
determining a second temperature according to the material of the first electrode layer and according to the determination of the hillock temperature, wherein the second temperature is below the hillock temperature;
depositing a first dielectric layer on the first electrode layer utilizing a first process that is performed at the first temperature;
depositing a second dielectric layer on the first dielectric layer utilizing a second process that is performed at the second temperature and that forms a randomly-oriented grain structure for the second dielectric layer;
depositing a third dielectric layer on the second dielectric layer utilizing a third process that is performed at a third temperature and that forms a columnar-oriented grain structure for the third dielectric layer, wherein the third temperature is higher than the first temperature; and
depositing a second electrode layer on the third dielectric layer to form the thin film capacitor, wherein the first and third processes result in an average grain size of the first dielectric layer being smaller than an average grain size of the third dielectric layer.

US Pat. No. 10,115,526

CAPACITOR, CAPACITOR MOUNTING STRUCTURE, AND TAPED ELECTRONIC COMPONENT SERIES

Murata Manufacturing Co.,...

1. A capacitor comprising:a capacitor main body including a first main surface and a second main surface which extend along a longitudinal direction and a width direction, a first side surface and a second side surface which extend along the longitudinal direction and a thickness direction, and a first end surface and a second end surface which extend along the width direction and the thickness direction; and
a first inner electrode and a second inner electrode provided in the capacitor main body and opposing each other via a ceramic section; wherein
in the capacitor main body, a dimension along the thickness direction of a first region where the first and second inner electrodes are provided is t1;
in the capacitor main body, a dimension along the thickness direction of a second region that is positioned on a side of the first main surface relative to the first region is t2;
in the capacitor main body, a dimension along the thickness direction of a third region that is positioned on a side of the second main surface relative to the first region is t3;
a condition of t3/t1>about 0.07 is satisfied;
the ceramic section includes BaTiO3 and Mn;
a content of Mn in the ceramic section is less than about 0.2 mol part with respect to BaTiO3 of 100 mol part;
a distance along the width direction from a portion where both of the first and second inner electrodes are provided to the first side surface is w2 and a distance along the width direction from a portion where both of the first and second inner electrodes are provided to the second side surface is w3;
at least one of w2 and w3 is no more than about 70 ?m; and
at least one of w2 and w3 is no less than about 55 ?m.

US Pat. No. 10,115,525

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a body including a capacitance portion having dielectric layers formed of a dielectric material;
internal electrodes and a cover portion covering at least one surface of the capacitance portion, the cover portion including cover layers formed of a dielectric material, the cover portion including a plurality of first and second cover layers that are stacked alternately; and
an external electrode disposed on the body, the external electrode connected to the internal electrodes,
wherein average diameters of dielectric grains included in the first and second cover layers are different from each other.