US Pat. No. 10,770,373

RADIATOR FOR LIQUID COOLING TYPE COOLING DEVICE AND METHOD OF PRODUCING THE SAME

SHOWA DENKO K.K., Tokyo ...

1. A radiator for a liquid cooling type cooling device, wherein the radiator is arranged in a coolant passage formed in a casing of the liquid cooling type cooling device to radiate heat emitted from a heating element to a coolant, and wherein the liquid cooling type device is provided with the casing having a top wall, a bottom wall, and a peripheral wall and the coolant passage through which the coolant flowed into the casing flows and is configured to cool the heating element mounted on at least either one of an outer surface of the top wall and an outer surface of the bottom wall of the casing by the coolant flowing through the coolant passage,the radiator comprising:
a plurality of vertically elongated rectangular shaped fin plates arranged in parallel at intervals; and
a connecting member integrally connecting all the fin plates,
wherein the fin plate includes:
a plate body in which a longitudinal direction is oriented in a flow direction of the coolant and a width direction is oriented in a vertical direction, the plate body being provided with flat plate-shaped portions at certain length portions close to both ends of the longitudinal direction; and
a narrow portion integrally provided at each of both longitudinal end portions of the plate body so as to protrude outward from the longitudinal end portions in the longitudinal direction of the plate body and having both upper and lower ends positioned inner than both upper and lower side edges of the plate body in the width direction of the plate body,
wherein all the fin plates are arranged at intervals in a thickness direction of the fin plate in a state in which the longitudinal direction of the plate body is oriented in the flow direction of the coolant and the width direction of the plate body is oriented in the vertical direction,
wherein the connecting member is formed into a corrugated shape and composed of flat plate portions each integrated with the narrow portion of the plate body of the fin plate and arcuate portions each alternately connecting adjacent flat plate portions at upper and lower ends of the adjacent flat plate portions,
wherein the flat plate portions of the connecting member are arranged so that a longitudinal direction of the flat plate portion is oriented in the vertical direction and a thickness direction of the flat plate portion is oriented in the thickness direction of the plate body of the fin plate,
wherein both the upper and lower ends of the connecting member are positioned inner than both the upper and lower ends of the plate body in the width direction of the plate body,
wherein an intermediate portion of an upper arcuate portion of the connecting member protrudes upward and an intermediate portion of a lower arcuate portion of the connecting member protrudes downward,
wherein the plate body and the narrow portion of the fin plate, and the flat plate portion of the connecting member are equal in thickness, and
wherein both side surfaces of the flat plate-shaped portion of the plate body in the thickness direction, both side surfaces of the narrow portion in the thickness direction, and both side surfaces of the flat plate portion of the connecting member in the thickness direction are positioned on a same plane.

US Pat. No. 10,770,372

FLUID ROUTING DEVICES AND METHODS FOR COOLING INTEGRATED CIRCUIT PACKAGES

Altera Corporation, San ...

1. A fluid routing device comprising:a fluid inlet;
first vertical channels that are open to the fluid inlet;
a horizontal channel that is open to each of the first vertical channels, wherein the first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel, and wherein the horizontal channel is open on one side of the fluid routing device such that an apparatus attached to a bottom of the fluid routing device forms a sidewall of the horizontal channel;
second vertical channels that are open to the horizontal channel, wherein the second vertical channels are oriented to provide fluid coolant vertically up away from the horizontal channel, wherein the first vertical channels are interleaved between the second vertical channels, and wherein each of the first vertical channels and each of the second vertical channels is directly connected at one end to the horizontal channel; and
a fluid outlet that is open to the second vertical channels such that fluid coolant from the second vertical channels exits the fluid routing device through the fluid outlet,
wherein each of the first vertical channels has a constricted opening to the horizontal channel directly above the horizontal channel, wherein a width of the constricted opening of each of the first vertical channels is narrower than a width of the first vertical channel above the constricted opening, and wherein an opening of each of the second vertical channels to the horizontal channel directly above the horizontal channel is wider than the constricted opening to the horizontal channel of each of the first vertical channels.

US Pat. No. 10,770,371

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a base plate made of a metal and having a through-hole;
an insulating substrate on the base plate;
a semiconductor chip on the insulating substrate;
a case having a screw-hole formed only partially through the case, communicating with the through-hole, covering the insulating substrate and the semiconductor chip, and disposed on the base plate;
a screw made of a metal and inserted into the through-hole and the screw-hole to fix the case to the base plate; and
a flexible material having flexibility, compressed and filled in a cavity between a bottom surface of the screw-hole in the case and a distal end of the screw, wherein
volume of the flexible material when it is uncompressed is larger than that of the cavity,
an electrically conductive coat is applied to a side surface and the bottom surface of the screw-hole in the case, and
the entire flexible material is composed of only a silicone rubber sponge or a fluorocarbon rubber sponge.

US Pat. No. 10,770,370

ELECTRONIC DEVICE AND HEAT DISSIPATING SHEET

FUJITSU LIMITED, Kawasak...

1. An electronic device comprising:a component;
a resin film formed to the component; and
a plurality of carbon nanotubes whose end portions pass through the resin film and are in contact with the component,
wherein
a first portion of each of the carbon nanotubes is covered with the resin film,
the first portion has a first length which is greater than a thickness of the resin film, and
an intermediate portion of each of the carbon nanotubes other than the first portion is uncovered with and exposed from the resin film.

US Pat. No. 10,770,369

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a substrate having a surface;
a first electronic component and a second electronic component disposed over the surface of the substrate and arranged along a direction substantially parallel to the surface, wherein the first electronic component and the second electronic component are separated by a space therebetween;
a heat dissipation lid disposed over the first electronic component and the second electronic component, wherein the heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component; and
a thermal isolation disposed in the one or more apertures of the heat dissipation lid,
wherein the one or more apertures includes a first aperture over the space between the first electronic component and the second electronic component, and one or more second apertures over at least one of the first electronic component or the second electronic component, and the first aperture is distinct from the one or more second apertures, wherein the first aperture partially overlaps an edge of the first electronic component and an edge of the second electronic component.

US Pat. No. 10,770,368

CHIP ON FILM PACKAGE AND HEAT-DISSIPATION STRUCTURE FOR A CHIP PACKAGE

Novatek Microelectronics ...

1. A chip on film package, comprising:a base film comprising a first surface and a second surface opposite to the first surface;
a chip disposed on the first surface, having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface and being perpendicular to the top surface and the bottom surface, and having a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis, wherein the first axis and the second axis define a plane parallel to the top surface and the bottom surface; and
a first heat-dissipation structure comprising a covering portion, the covering portion at least partially covering the chip, exposing the side surface of the chip, and having a first length along the first axis and a second length along the second axis being longer than the chip width of the chip.

US Pat. No. 10,770,367

SEMICONDUCTOR APPARATUS, METHOD FOR MANUFACTURING THE SAME AND ELECTRIC POWER CONVERSION DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor apparatus comprising:a substrate including an insulator disposed between a circuit pattern on an upper surface side and a metal plate on a lower surface side;
a semiconductor device joined to the circuit pattern via a conductive component;
a case located to surround the substrate, a gap being between the case and a lateral side face of the substrate;
a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and
a bonding agent bonding the case and the metal plate on the lateral side face of the substrate, the bonding agent extending along a bottom surface of the case and filling the gap between the case and the lateral side face of the substrate.

US Pat. No. 10,770,366

INTEGRATED CIRCUIT PACKAGES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a solder region on a wafer, wherein the wafer comprises a plurality of chips, with the solder region being in a first chip of the plurality of chips;
forming a dielectric layer to embed a portion of the solder region in the dielectric layer, wherein the dielectric layer comprises a first portion and a second portion;
thinning the first portion of the dielectric layer without thinning the second portion of the dielectric layer; and
sawing the wafer to separate the plurality of chips from each other, wherein the sawing comprises using a feature underlying the thinned first portion of the dielectric layer for alignment.

US Pat. No. 10,770,365

PACKAGE STRUCTURES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A structure comprising:a first side of an interposer bonded to a package substrate;
active sides of a first die and a second die bonded to a second side of the interposer, the second side being opposite the first side;
a dummy die attached to the second side of the interposer, the dummy die being adjacent to at least one of first die or the second die; and
a cover structure attached to backside of the second die, the second die comprising one or more memory dies, the cover structure being thicker than each of the one or more memory dies.

US Pat. No. 10,770,364

CHIP SCALE PACKAGE (CSP) INCLUDING SHIM DIE

XILINX, INC., San Jose, ...

1. A structure comprising:a first integrated circuit die;
a shim die being a dummy die having no active or passive circuitry thereon;
an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die;
a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant, wherein the redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die,
conductive bumps attached to the redistribution structure, the conductive bumps including a plurality of input/output (IO) bumps aligned in a direction and contained within a dimension, the dimension being a sum of:
(i) a dimension of the first integrated circuit die along the direction,
(ii) a dimension of the shim die along the direction,
(iii) a dimension of the encapsulant disposed along the direction and between a side opposite from the first integrated circuit die and another side opposite from the shim die.

US Pat. No. 10,770,363

POWER SWITCHING SYSTEM FOR ESC WITH ARRAY OF THERMAL CONTROL ELEMENTS

Lam Research Corporation,...

1. A substrate support for supporting a substrate in a plasma processing chamber, comprising:a heater array comprising thermal control elements to control a temperature of the substrate, the thermal control elements configured to receive power via two or more power supply lines and two or more power return lines, wherein each power supply line is connected to at least two of the thermal control elements and each power return line is connected to at least two of the thermal control elements;
a power distribution circuit mated to a baseplate of the substrate support, the power distribution circuit connected to each power supply line and power return line of the heater array, wherein the power distribution circuit is formed on a first circuit board having a conductive common plane that is attached to the baseplate and that is at an electrical potential of the baseplate;
a power switching device connected to the power distribution circuit to independently supply power to each one of the thermal control elements via one of the power supply lines and one of the power return lines; and
a capacitor connected between each power supply line and the baseplate and between each power return line and the baseplate to shunt RF between the baseplate and the heater array so that the baseplate and the heater array are at a same RF potential,
wherein one end of each capacitor is connected to a power supply line or a power return line and another end of each capacitor is connected to the conductive common plane that is attached to the baseplate.

US Pat. No. 10,770,362

DISPERSION MODEL FOR BAND GAP TRACKING

KLA Corporation, Milpita...

1. A method comprising:illuminating a multi-layer structure disposed over a substrate with an amount of illumination light;
detecting an amount of collected light from the multi-layer structure in response to the amount of illumination light;
generating a spectral measurement of the multi-layer structure across a spectral range based at least in part on the amount of collected light;
determining a plurality of parameter values of an optical dispersion model of one or more layers of the multi-layer structure based at least in part on the spectral measurement, wherein the optical dispersion model includes a constrained Cody-Lorentz model having a rate of attenuation of an Urbach function defined such that a first derivative of a dielectric function with respect to energy is continuous at an Urbach transition energy of the constrained Cody-Lorentz model; and
storing the plurality of parameter values of the optical dispersion model in a memory.

US Pat. No. 10,770,361

CONTROLLING ACTIVE FIN HEIGHT OF FINFET DEVICE USING ETCH PROTECTION LAYER TO PREVENT RECESS OF ISOLATION LAYER DURING GATE OXIDE REMOVAL

International Business Ma...

1. A method for fabricating a semiconductor device, comprising:forming a vertical semiconductor fin on a semiconductor substrate;
forming an isolation layer on the semiconductor substrate, wherein the isolation layer covers a bottom portion of the vertical semiconductor fin, and wherein an active portion of the vertical semiconductor fin extends above a surface of the isolation layer;
forming a gate structure over a portion of the active portion of the vertical semiconductor fin, wherein the gate structure comprises a sacrificial gate oxide layer and a sacrificial gate electrode layer formed over the sacrificial gate oxide layer;
opening the gate structure to form a gate opening which exposes the sacrificial gate oxide layer;
forming a first etch protection layer on a portion of the isolation layer exposed within the gate opening; and
etching the exposed portion of the sacrificial gate oxide layer to remove the sacrificial gate oxide layer within the gate opening, wherein the first etch protection layer protects the exposed portion of the isolation layer from being etched during the etching of the sacrificial gate oxide layer.

US Pat. No. 10,770,360

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor structure, comprising:providing a base structure having a first transistor region and a second transistor region, wherein the base structure includes a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in the first transistor region, and a plurality of second openings formed in the dielectric layer in the second transistor region;
forming a first work function layer on the dielectric layer and covering bottom and sidewall surfaces of each of the plurality of the first opening and of each of the plurality of the second opening;
forming a first sacrificial layer in each first opening and each second opening, wherein a top surface of the first sacrificial layer is lower than a top surface of the dielectric layer;
removing a portion of the first work function layer exposed by the first sacrificial layer in each first opening and each second opening using the first sacrificial layer as a first etch mask;
forming a second sacrificial layer in the second transistor region;
removing the first sacrificial layer from each first opening after removing the portion of the first work function layer formed in each first opening and a remaining portion of the first work function layer formed in each first opening by etching using the second sacrificial layer as a second etch mask;
removing the second sacrificial layer in the second transistor region;
removing the first sacrificial layer from each second opening after removing the remaining portion of the first work function layer formed in each first opening, wherein the second sacrificial layer and the first sacrificial layer are removed by a same etching process after removing the portion of the first work function layer formed in the first transistor region; and
forming a second work function layer and then a gate electrode in each first opening and each second opening.

US Pat. No. 10,770,359

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A device comprising:a first fin extending from a substrate;
a first gate stack over and along sidewalls of the first fin;
a first gate spacer disposed along a sidewall of the first gate stack; and
a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region comprising:
a first epitaxial layer on the first fin, the first epitaxial layer comprising silicon and carbon;
a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin; and
a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer and the second epitaxial layer.

US Pat. No. 10,770,358

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor wire structure horizontally extending over a substrate and having a channel region, and a source region and a drain region disposed at ends of the channel region in a horizontal direction, wherein:
a source contact layer is formed over the source region,
the source contact layer is embedded in an dielectric layer,
an isolation insulating layer is disposed between the dielectric layer and the substrate,
a bottom of the source region is separated from the substrate by an insulating layer made of a different material than the isolation insulating layer and the dielectric layer, and a bottom of the drain region is separated from the substrate by the insulating layer,
the substrate includes a protrusion below the source region, and
the insulating layer is disposed between the bottom of the source region and the protrusion.

US Pat. No. 10,770,357

INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION

STMicroelectronics (Croll...

1. An integrated circuit, comprising:a semiconductor substrate doped with a first conductivity type;
a semiconductor well doped with the first conductivity type, wherein a bottom of the semiconductor well is isolated from the semiconductor substrate by a buried semiconductor region doped with a second conductivity type;
an upper trench isolation extending from a front surface of the semiconductor well to a depth located a distance from the bottom of the semiconductor well;
at least two additional isolating zones that are electrically insulated from the semiconductor well and which extend inside the semiconductor well in a first direction and extend vertically from the front surface to the bottom of the semiconductor well;
at least one hemmed resistive region bounded by said at least two additional isolating zones, the upper trench isolation and the buried semiconductor region; and
at least two contact zones located level with the front surface of the semiconductor well and being electrically coupled to said at least one hemmed resistive region;
wherein said buried semiconductor region is configured to be biased to change a resistance of the at least one hemmed resistive region extending between the at least two contact zones.

US Pat. No. 10,770,356

CONTACT STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. An apparatus comprising:a first source and a common drain in a substrate and on opposite sides of a first gate, the first gate being surrounded by a first gate spacer;
a second source and the common drain in the substrate and on opposite sides of a second gate, the second gate being surrounded by a second gate spacer;
a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope;
a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope;
a lower drain contact between the first gate and the second gate, the lower drain contact has an inverted-trapezoidal shape; and
an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

US Pat. No. 10,770,355

SEMICONDUCTOR DEVICES WITH VARIOUS LINE WIDTHS AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a plurality of dummy gate structures on a substrate, the substrate including a first region and a second region, the plurality of dummy gate structures extending in a first direction and arranged in the first region and the second region, the plurality of dummy gate structures in the first region and the second region having uniform pitches in a second direction, the second direction being different from the first direction, the plurality of dummy gate structures in the first region and the second region having uniform widths in the second direction;
forming a first cover layer conformally covering, in the first region, the substrate and the plurality of dummy gate structures;
forming a second cover layer conformally covering the first cover layer in the first region and conformally covering, in the second region, the substrate and the plurality of dummy gate structures;
forming a spacer layer covering a) the second cover layer that covers opposite side walls of the plurality of dummy gate structures in the first region and b) the first cover layer that covers opposite side walls of the plurality of dummy gate structures in the second region;
forming a plurality of first gate spaces in the first region and a plurality of second gate spaces in the second region by removing together, from the first region and the second region, the plurality of dummy gate structures, a portion of the first cover layer, and a portion of the second cover layer; and
forming a) a plurality of first gate lines filling the plurality of first gate spaces and b) a plurality of second gate lines filling the plurality of second gate spaces.

US Pat. No. 10,770,354

METHOD OF FORMING INTEGRATED CIRCUIT WITH LOW-K SIDEWALL SPACERS FOR GATE STACKS

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate;
forming a spacer on a side surface of the gate stack;
curing the spacer to form a cured spacer having a plurality of voids from the curing, wherein the cured spacer includes a spacer layer with a low-k dielectric material, the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9, wherein the low-k dielectric material includes a dielectric material and a dopant selected from the group consisting of an n-type dopant and a p-type dopant;
forming a source/drain region in the substrate; and
forming a source/drain contact coupled to the source/drain region, wherein the spacer layer of the cured spacer is disposed between the source/drain contact and the gate stack.

US Pat. No. 10,770,353

METHOD OF FORMING MULTI-THRESHOLD VOLTAGE DEVICES USING DIPOLE-HIGH DIELECTRIC CONSTANT COMBINATIONS AND DEVICES SO FORMED

Samsung Electronics Co., ...

1. A method for providing a gate structure for a plurality of components of a semiconductor device, the method comprising:providing a first dipole combination on a first portion of the plurality of components, the first dipole combination including a first dipole layer and a first high dielectric constant layer on the first dipole layer, the providing the first dipole combination further including
providing a masking layer on the second portion of the plurality of components;
depositing a first layer on at least the first portion and the second portion of the plurality of components, a first portion of the first layer on the first portion of the plurality of components forming the first dipole layer;
depositing an additional layer on the at least the first portion and the second portion of the plurality of components, a first portion of the additional layer on the first portion of the plurality of components forming the first high dielectric constant layer;
removing a second portion of the first layer and a second portion of the additional layer from the second portion of the plurality of components;
providing a second dipole combination on a second portion of the plurality of components, the second dipole combination including a second dipole layer and a second high dielectric constant layer on the second dipole layer, the first dipole combination being different from the second dipole combination;
providing at least one work function metal layer on the first dipole combination and the second dipole combination;
performing a low temperature anneal after the providing the at least one work function metal layer; and
providing a contact metal layer on the work function metal layer.

US Pat. No. 10,770,352

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

3. The method of forming a semiconductor device according to claim 1, wherein forming the second gate electrode comprises:forming a photoresist layer on the first gate electrode and on the gate electrode layer in the second region; and
etching the gate electrode layer using the photoresist layer as an etching mask to form the second gate electrode.

US Pat. No. 10,770,351

SEMICONDUCTOR SUBSTRATE PRODUCTION SYSTEMS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method of separating a wafer from a boule comprising a semiconductor material, the method comprising:creating a damage layer in a boule comprising semiconductor material, wherein the boule has a first end and a second end; and
cooling the first end of the boule;
wherein a thermal gradient between the first end and the second end assists a silicon carbide wafer to separate from the boule at the damage layer.

US Pat. No. 10,770,350

METHOD OF SEPARATING A BACK LAYER ON A SINGULATED SEMICONDUCTOR WAFER ATTACHED TO CARRIER SUBSTRATE

SEMICONDUCTOR COMPONENTS ...

1. A method of forming an electronic device comprising:providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has a first major surface and a second major surface opposite to the first major surface, and wherein a layer of material is disposed atop the second major surface, and wherein the layer of material is placed onto a first carrier substrate comprising a first adhesive layer;
singulating the wafer through the spaces to form singulation lines without singulating through the layer of material so that portions of the layer of material overlap the singulation lines;
placing a second carrier substrate comprising a second adhesive layer onto the singulated wafer such that the second adhesive layer faces the first carrier substrate and the singulated wafer is interposed between the first carrier substrate and the second carrier substrate; and
moving a roller structure adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the portions of layer of material that overlap singulation lines.

US Pat. No. 10,770,349

CRITICAL DIMENSION CONTROL FOR SELF-ALIGNED CONTACT PATTERNING

Applied Materials, Inc., ...

1. A method of forming a contact pattern, the method comprising:providing a substrate having a substrate surface with a feature, the feature having sidewalls and a bottom;
forming a conformal liner in the feature, leaving a gap between the conformal liner on the sidewalls of the feature;
filling the gap between the sidewalls of the conformal liner with tungsten; and
volumetrically expanding the tungsten by nitridation to grow a pillar of tungsten nitride extending above the substrate surface.

US Pat. No. 10,770,348

LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE

INTERNATIONAL BUSINESS MA...

1. A system for completing of annealing metal interconnect overburden layers on semiconductor devices being fabricated on a chip on a semiconductor wafer, comprising:a scanning electron microscope (SEM) equipped with an electron backscatter diffraction (EBSD) capability;
a laser;
a processor; and
a memory, the memory storing instructions to cause the processor to perform:
detecting an orientation of early recrystallizing grains at specific locations on a top surface of the semiconductor wafer, as implemented and controlled by the processor, using data from the SEM equipped with the EBSD capability;
selectively performing a laser anneal of the metal interconnect overburden layer, as implemented and controlled by the processor, using the laser, based on a result of the determining.

US Pat. No. 10,770,347

INTERCONNECT STRUCTURE

Tessera, Inc., San Jose,...

1. A method of making an interconnect structure comprising:forming a copper interconnect structure in a dielectric material;
forming a capping layer in contact with a top surface of the copper interconnect structure, wherein an interface of a bottom surface of the capping layer and the top surface of the copper interconnect structure is co-planar with a top surface of the dielectric material; and
forming a barrier layer outdiffused from a top surface and side surfaces of the capping layer,
wherein the copper interconnect structure comprises:
a layer of Tantalum Nitride (TaN);
a layer of CuMn directly on the TaN layer; and
an electroplated copper layer on the CuMn layer.

US Pat. No. 10,770,346

SELECTIVE COBALT REMOVAL FOR BOTTOM UP GAPFILL

Applied Materials, Inc., ...

1. An etching method comprising:flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber;
forming a plasma of the chlorine-containing precursor to produce plasma effluents;
contacting an exposed region of cobalt with the plasma effluents, wherein the plasma effluents produce cobalt chloride at the exposed region of cobalt to a modification depth of at least about 5 ?;
flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber;
contacting the cobalt chloride with the nitrogen-containing precursor;
recessing the exposed region of cobalt to at least the modification depth, and
removing residue from exposed cobalt surfaces.

US Pat. No. 10,770,345

INTEGRATED CIRCUIT AND FABRICATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating an integrated circuit, comprising:depositing a first inter-layer dielectric layer over a memory device, wherein the first inter-layer dielectric layer has a first portion over the memory device and a second portion adjacent the first portion of the first inter-layer dielectric layer;
depositing a first polish stop layer over the first inter-layer dielectric layer, wherein the first polish stop layer has a first portion over the memory device and a second portion over the second portion of the first inter-layer dielectric layer;
removing the second portion of the first polish stop layer and the second portion of the first inter-layer dielectric layer, wherein the first portion of the first polish stop layer is at least partially directly above the first portion of the first inter-layer dielectric layer and a top electrode of the memory device after removing the second portion of the first polish stop layer;
depositing a second inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer and the second portion of the first inter-layer dielectric layer; and
polishing the second inter-layer dielectric layer until reaching the first portion of the first polish stop layer.

US Pat. No. 10,770,344

CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method of fabricating interconnects in a semiconductor device comprising:forming an interconnect layer comprising a conductive line;
depositing a first aluminum-containing layer over the interconnect layer;
depositing a dielectric layer over the first aluminum-containing layer;
depositing a second aluminum-containing layer over the dielectric layer; and
forming a via opening in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

US Pat. No. 10,770,343

METHODS OF FORMING MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a memory array, comprising:forming an assembly which comprises capacitors extending within a matrix; the capacitors having first electrodes, second electrodes, and insulative capacitor material between the first and second electrodes; the capacitors being arranged in array, the array comprising edges and the capacitors along the edges being edge capacitors; the capacitors that are not along the edges being internal capacitors of the array; the edge capacitors having inner edges facing toward the internal capacitors, and having outer edges in opposing relation to the inner edges; the matrix including an insulative beam over a sacrificial material; the insulative beam extending laterally between the capacitors and being along the upper regions of the capacitors; the insulative beam having peripheral extensions that extend laterally beyond the edge capacitors;
removing the sacrificial material to form first void regions under the insulative beam, along the lower regions of the internal capacitors, and along the inner edges of the edge capacitors, and to form second void regions along the outer edges of the edge capacitors;
forming at least one conductive plate over the insulative beam and electrically coupled with the second electrodes; and
forming an insulative structure over the at least one conductive plate; the insulative structure including vertical regions along the outer edges of the edge capacitors and spaced from the outer edges of the edge capacitors by the second void regions.

US Pat. No. 10,770,342

DEVICES AND METHODS FOR RADIATION HARDENING INTEGRATED CIRCUITS USING SHALLOW TRENCH ISOLATION

TallannQuest LLC, Plano,...

1. A radiation-hardened NMOS transistor fabricated using a shallow trench isolation process, comprising:a silicon substrate having a top surface that is lightly doped p-type;
a trench insulator formed in selected areas on the top surface of said substrate;
at least one active region, defined by an area on the top surface in which said trench insulator is not present, the trench insulator having an edge along a boundary of the active region;
a gate overlying a portion of the at least one active region, and crossing the active region along a width direction from a first boundary of the active region to a second boundary of the active region opposite said first boundary, the gate having a length dimension L along said first and second boundaries, said length dimension of the gate defining a length direction and further defining at least one channel under the gate having two ends, said channel having a length L along said length direction;
at least one n-type region formed within the active region, said n-type region formed by an N+ doping and comprising at least one of a source region and a drain region, a width of the n-type region adjacent said gate defining, in said width direction, a width W of the channel, wherein at least one segment of a border of the n-type region along the first and second boundaries is pulled back in said width direction a nonzero pullback distance g from the edge of said trench insulator into the active region, said at least one pulled-back segment defining at least one gap region within the active region, each said gap region comprising an area of the active region outside the n-type region that is contiguous with both the pulled-back segment of the border of the n-type region and the edge of the trench insulator; and
a conductive metal silicide layer disposed on top of, and in electrical contact with, the n-type region, said metal silicide layer excluded from the gap region, thereby preventing the metal silicide layer from establishing a conductive connection from the n-type region to the top surface of the substrate in the gap region;
whereby a radiation-induced leakage current is reduced by increasing a threshold voltage of a parasitic field transistor formed along the edge of the trench insulator and running along the length of the channel.

US Pat. No. 10,770,341

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A method for manufacturing a semiconductor device, comprising:forming a first insulating film on a semiconductor substrate, the first insulating film being patterned;
forming a trench in the semiconductor substrate using the first insulating film as a mask;
depositing a second insulating film in the trench and on the first insulating film;
depositing a third insulating film on the second insulating film;
removing the second insulating film and the third insulating film on the first insulating film using a CMP method;
removing a portion of the second insulating film and a portion of the third insulating film using isotropic etching; and
removing the first insulating film, wherein an etching rate of the third insulating film during the isotropic etching is lower than an etching rate of the second insulating film.

US Pat. No. 10,770,340

ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF FOR HIGH-VOLTAGE DEVICE IN A HIGH-VOLTAGE BCD PROCESS

HANGZHOU SILAN INTEGRATED...

1. A method for manufacturing an isolation structure for a high-voltage device in a high-voltage BCD process, comprising:providing a semiconductor substrate having a first type of doping;
forming an epitaxial layer having a second type of doping on the semiconductor substrate;
forming an isolation region having the first type of doping in the epitaxial layer to isolate an epitaxial island on the semiconductor substrate, wherein the high-voltage device is located in the epitaxial island, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, wherein the isolation region has a doping concentration on the same order of magnitude as a doping concentration of the epitaxial layer, and the first type of doping is opposite to the second type of doping and wherein the isolation region increases the breakdown voltage of the high-voltage device in the BCD process; and
forming a field oxide layer over the isolation region.

US Pat. No. 10,770,339

AUTOMATED REPLACEMENT OF CONSUMABLE PARTS USING INTERFACING CHAMBERS

Lam Research Corporation,...

1. A system used for processing a substrate, comprising:an atmospheric transfer module (ATM) housing a first robot;
a replacement station configured to be coupled to a first side of the ATM, the replacement station including a part buffer with a plurality of compartments for storing consumable parts, the plurality of compartments aligned in a horizontally stacked orientation within the replacement station, the replacement station is accessed using a carrier plate that is used for transporting a consumable part to and from a compartment of the replacement station, wherein the carrier plate supports the consumable part at three points that contact outer edges of the consumable part,
wherein the carrier plate is configured for moving the consumable part to a loadlock chamber for use in a process module.

US Pat. No. 10,770,338

SYSTEM COMPRISING A SINGLE WAFER, REDUCED VOLUME PROCESS CHAMBER

GLOBALFOUNDRIES Inc., Gr...

1. A system, comprising:a processing tool;
a process chamber within said processing tool;
a wafer chuck, said wafer chuck adapted to be positioned at a wafer processing position located within said process chamber and at a chuck wafer transfer position located outside of said process chamber; and
at least one lift pin opening in said wafer chuck.

US Pat. No. 10,770,337

LIFT PIN ASSEMBLY, SUBSTRATE SUPPORT APPARATUS AND SUBSTRATE PROCESSING APPARATUS HAVING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A lift pin assembly, comprising:a lift pin having a first longitudinal axis substantially parallel with a first direction;
a pin connection block combined with a lower end portion of the lift pin, the pin connection block comprising a first guide recess formed in a side surface of the pin connection block in a lower end portion of the pin connection block, the first guide recess extending in a second direction substantially perpendicular to the first direction, and the side surface of the pin connection block extending in the first direction; and
a lift pin holder having a second longitudinal axis substantially parallel with the first direction, the lift pin holder comprising a first sliding portion to be received movably in the second direction within the first guide recess by an eccentricity distance of the second longitudinal axis from the first longitudinal axis when the lift pin holder is connected to the lower end portion of the pin connection block.

US Pat. No. 10,770,336

SUBSTRATE LIFT MECHANISM AND REACTOR INCLUDING SAME

ASM IP Holding B.V., Alm...

1. A reactor comprising a common substrate processing and transfer region, the reactor comprising:a reaction chamber comprising a reaction region; a susceptor having a susceptor top surface within the reaction region;
a substrate lift mechanism comprising:
at least one lift pin;
a lift pin support member that removably engages to the at least one pin;
and a movable shaft coupled to the lift pin support member, a rotatable shaft; and
a susceptor support comprising one or more susceptor support arms and one or more susceptor support structures, the susceptor support coupled to the rotatable shaft,
wherein the substrate lift mechanism causes the at least one lift pin to extend through a width of the susceptor and above the susceptor top surface,
wherein the one or more susceptor support arms comprise an aperture to receive the at least one lift pin at a location radially exterior to a susceptor support structure of the one or more susceptor support structures,
wherein the one or more susceptor support structures engage with the susceptor, and
wherein the susceptor retains the at least one lift pin when the at least one lift pin is not engaged by the lift pin support member.

US Pat. No. 10,770,335

SUBSTRATE SUPPORTING APPARATUS

ACM Research (Shanghai) I...

1. A substrate supporting apparatus, comprising:a rotatable chuck for supporting a substrate, defining a plurality of first injecting ports and a plurality of second injecting ports, the first injecting ports connecting to a gas pipe for supplying gas to the substrate and sucking the substrate by Bernoulli effect, the second injecting ports connecting to another gas pipe for supplying gas to the substrate and lifting the substrate;
a plurality of locating pins disposed at the top surface of the rotatable chuck, the plurality of locating pins being divided into a first group of locating pins and a second group of locating pins, every locating pin being driven by an independent cylinder, the cylinders which drive the first group of locating pins connecting to a gas pipe, the cylinders which drive the second group of locating pins connecting to another gas pipe;
a hollow shaft, an inner wall of the hollow shaft defining four gas grooves, each gas groove configured to supply gas to a corresponding one of the gas pipes for supplying gas to the substrate and sucking the substrate by Bernoulli effect, the another gas pipe for supplying gas to the substrate and lifting the substrate, the gas pipe connecting to the cylinders which drive the first group of locating pins, or the another gas pipe connecting to the cylinders which drive the second group of locating pins;
a rotary spindle, being set in the hollow shaft and a spacing formed between an outer wall of the rotary spindle and the inner wall of the hollow shaft;
two pairs of seal rings, wherein one pair of seal rings is disposed at opposite sides of one gas groove which supplies gas to the cylinders for driving the first group of locating pins, one pair of seal rings is disposed at opposite sides of one gas groove which supplies gas to the cylinders for driving the second group of locating pins;
wherein the hollow shaft defines an exhaust port between two adjacent gas grooves, wherein one gas groove supplies gas to the cylinders for driving the first group of locating pins or the second group of locating pins, one gas groove supplies gas to the first injecting ports or the second injecting ports, wherein the outer wall of the rotary spindle defines a blocking wall corresponding to the exhaust port of the hollow shaft and a recess matching the gas groove which supplies gas to the first injecting ports or the second injecting ports.

US Pat. No. 10,770,334

SUBSTRATE HOLDING DEVICE

NGK SPARK PLUG CO., LTD.,...

1. A substrate holding device comprising:a base body having a flat plate-like shape and including:
an upper surface;
a lower surface; and
a plurality of upper protrusions protruding upward from the upper surface;
the base body defining:
an elongated groove that opens on the lower surface with a bottom surface of the groove positioned a depth away from the lower surface of the base body; and
at least one gas hole extending from the upper surface to the bottom surface of the elongated groove;
the base body further including a plurality of first lower protrusions protruding downward from the bottom surface of the elongated groove.

US Pat. No. 10,770,331

SEMICONDUCTOR WAFER DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:providing a carrier;
defining a plurality of die regions over the carrier along a first direction and a second direction to arrange the plurality of die regions in a plurality of rows and a plurality of columns, wherein each of the die regions has a first side parallel to the first direction and a second side parallel to the second direction;
identifying a row when a shortest distance between an edge of the carrier and the second side of a die region disposed at an end of the row is larger than a half of a length of the first side;
shifting the row along the first direction in a predetermined distance;
disposing an additional die region at an end of the shifted row; and
forming a die in each of the plurality of die regions and the additional die region.

US Pat. No. 10,770,329

GAS FLOW FOR CONDENSATION REDUCTION WITH A SUBSTRATE PROCESSING CHUCK

Applied Materials, Inc., ...

1. An apparatus comprising:a puck to carry a workpiece for fabrication processes;
a top plate thermally coupled to the puck;
a cooling plate fastened to and thermally coupled to the top plate;
a base plate fastened to the cooling plate opposite the puck;
and a dry gas outlet of the base plate to supply a dry gas under pressure to a space between the base plate and the cooling plate, the dry gas outlet positioned between a central shaft and a periphery of the base plate,
wherein the base plate has a groove configured to allow the dry gas to flow in and out of the groove to the space between the base plate and the cooling plate, the groove having a path from the dry gas outlet to the central shaft, wherein a portion of the path is from the periphery of the base plate to the central shaft; and
a cylindrical bore through the cooling plate to allow the dry gas to flow between the base plate and the cooling plate to between the cooling plate and the top plate, the cylindrical bore being positioned so that the groove leads the dry gas to flow to the cylindrical bore.

US Pat. No. 10,770,328

SUBSTRATE SUPPORT WITH SYMMETRICAL FEED STRUCTURE

APPLIED MATERIALS, INC., ...

1. A substrate support for a plasma processing apparatus, comprising:a substrate support having a support surface for supporting a substrate the substrate support having a central axis;
a first electrode disposed within the substrate support to provide RF power to a substrate when disposed on the support surface;
an inner conductor coupled to the first electrode about a center of a surface of the first electrode opposing the support surface, wherein the inner conductor is tubular and extends from the first electrode parallel to and about the central axis in a direction away from the support surface of the substrate support;
an inner dielectric layer disposed within and throughout an axial opening of the inner conductor;
an outer conductor disposed about the inner conductor; and
an outer dielectric layer disposed continuously and throughout between the inner and outer conductors.

US Pat. No. 10,770,327

SYSTEM AND METHOD FOR CORRECTING NON-IDEAL WAFER TOPOGRAPHY

Taiwan Semiconductor Manu...

1. A scanner comprising:a light source configured to apply a light to a backside of a wafer at a first adjustable incident angle with respect to a first horizontal axis;
a first mirror positioned to receive light reflected from a backside of a wafer when the light source is applied to the backside of the wafer and reflect the light, wherein a change in the first adjustable incident angle of ?? corresponds to a horizontal movement of the first mirror ?x on a second horizontal axis parallel to the first horizontal axis; and
a sensor positioned to receive light reflected from the first mirror when the light source is applied to the backside of the wafer, wherein the sensor is configured to generate an output signal indicative of a backside topography of the wafer.

US Pat. No. 10,770,326

POSITIONING DEVICE, LOADING AND/OR UNLOADING SYSTEM AND METHOD FOR OPERATING A POSITIONING DEVICE

VAT Holding AG, Haag (CH...

1. A loading and/or unloading system for loading and/or unloading wafers from a wafer transportation container with a positioning device for positioning the wafer transportation container in a loading and/or unloading position of a loading and/or unloading station by contactlessly controlling an at least two-dimensional movement of the wafer transportation container in such a manner that the wafer transportation container assumes a spatial alignment in a plane which lies at least substantially perpendicular to a main direction of movement, along which the wafer transportation container moves during a coupling process, when approaching the loading and/or unloading position, in which the wafer transportation container is connectable to the loading and/or unloading station in a vacuum-tight manner,the positioning device comprising:
the loading and/or unloading station, configured at least for loading and/or unloading wafers from the wafer transportation container,
the wafer transportation container,
a final positioning mechanism, which is realized in a contacting manner comprising a guide rail of a guide unit with at least one guide projection slidably engageable in the guide rail,
a clean room-suitable pre-positioning mechanism which is configured for a contactless pre-positioning of the wafer transportation container in a coupling process of the wafer transportation container and the loading and/or unloading station, with the clean room-suitable contactless pre-positioning mechanism being independent of any wafer transportation container transport which is configured for logistics of wafer transportation containers, and
a controller, including a processor and a storage with a control and/or regulation program stored therein which is executed by the processor, wherein said controller is configured to control and/or regulate the pre-positioning mechanism to contactlessly pre-position the wafer transportation container in the coupling process of the wafer transportation container and the loading and/or unloading station,
the clean room-suitable contactless pre-positioning mechanism being realized separately from the final positioning mechanism,
the clean room-suitable pre-positioning mechanism comprising:
at least one positioning element, which is realized as a permanent magnet, which is arranged on the wafer transportation container and which is configured for the purpose of generating at least one positioning force field, and
at least one further positioning element, which includes at least one magnetic coil, which is configured for the purpose of generating at least one contactlessly transmissible positioning force field and which, for a purpose of interacting with a static magnetic field of the at least one positioning element, is configured for a generating of a controllable and/or regulatable magnetic field by means of the magnetic coil,
wherein the clean room-suitable contactless pre-positioning mechanism is arranged in a proximity to the loading and/or unloading station and is configured for a proximity positioning of the wafer transportation container in the loading and/or unloading position, and
wherein the clean room-suitable contactless pre-positioning mechanism is configured for the purpose of generating a force which acts in proximity to the loading and/or unloading station and which develops its greatest effect in a proximity to the loading and/or unloading station.

US Pat. No. 10,770,325

TOOL AUTO-TEACH METHOD AND APPARATUS

Brooks Automation, Inc, ...

1. A process tool comprising:a frame;
a substrate transport connected to the frame and having an end effector configured to support a substrate; and
a substrate transport apparatus auto-teach system for auto-teaching a substrate station location, the substrate transport apparatus auto-teach system including a controller configured to
move the substrate transport so as to contact a substrate station feature with the substrate on the end effector to confirm an eccentricity of the substrate, relative to a coordinate system of the substrate transport, so that a change in eccentricity resolves to a common eccentricity determinative of the substrate station location.

US Pat. No. 10,770,324

SUBSTRATE HOLDING DEVICE, SUBSTRATE TRANSPORT DEVICE, PROCESSING ARRANGEMENT AND METHOD FOR PROCESSING A SUBSTRATE

1. A substrate transportation system comprising a substrate holding device and a transportation device for transporting the substrate holding device, wherein the substrate holding device comprises:a carrier plate comprising a cavity, wherein the cavity extends from an upper side of the carrier plate through the carrier plate to a lower side of the carrier plate;
a holding frame, which has a frame opening and a supporting surface for holding a substrate in the cavity, wherein the substrate is directly supported on the supporting surface, said supporting surface at least partially surrounding the frame opening, wherein the cavity is substantially cuboid shaped and has four corner regions, and wherein the holding frame rests on the carrier plate only in the corner regions of the cavity;
wherein the holding frame, when inserted into the cavity, partially rests on the carrier plate; and
two holding regions at which the carrier plate can be supported for transporting the carrier plate, wherein the cavity is disposed between the two holding regions;wherein the transportation device has two holding elements in such a manner that the carrier plate of the substrate holding device is held only in the two holding regions.

US Pat. No. 10,770,323

STACKABLE SUBSTRATE CARRIERS

Brooks Automation GmbH, ...

1. A side-by-side stackable carrier for a plurality of substrates, wherein the side-by-side stackable carrier is configured for use in a semiconductor fabrication facility, the side-by-side stackable carrier comprising:two side structures comprising slot marks for holding substrates;
two end structures securing to the side structures, at least one of the end structures comprising a bidirectional attaching mechanism including mating features configured to mate with an end structure of another side-by-side stackable carrier such that the bidirectional attaching mechanism engages sequentially in a first direction and in a subsequent second direction arranged at an angle relative to the first direction, wherein the sequential engagement in the second direction subsequent to the engagement in the first direction locks engagement between the mating features,
wherein the bidirectional attaching mechanisms of two mated end structures are configured to be mated by themselves without an additional component.

US Pat. No. 10,770,322

METHOD AND APPARATUS FOR USE IN WAFER PROCESSING

Infineon Technologies AG,...

1. A method comprising:providing a wafer on a receptacle, wherein the receptacle comprises a plate and a light port, wherein the light port includes a source of light, wherein providing the wafer comprises positioning the wafer on the plate extending above a peripheral recess configured to receive the source of light, and wherein positioning the wafer on the plate is performed such that an edge of the wafer extends beyond the plate;
shining light from the source of light at an edge of the wafer thereby passing light by the edge of the wafer; and
processing the wafer on the receptacle based on the light passing by the edge of the wafer and received by a light sensitive element.

US Pat. No. 10,770,321

PROCESS KIT EROSION AND SERVICE LIFE PREDICTION

Applied Materials, Inc., ...

1. A method of monitoring a service life of a chamber component, comprising:receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber, each sensor monitoring a respective power measurement, wherein receiving one or more power measurements comprises:
receiving a first power measurement directed to a current of DC bias power from a first sensor;
receiving a second power measurement directed to a voltage of DC bias power from a second sensor; and
receiving a third power measurement directed to a DC bias match position from a third sensor;
comparing the one or more power measurements to one or more threshold values corresponding to the service life of the chamber component, wherein each power measurements has a respective threshold value;
determining whether the one or more power measurements exceed the one or more threshold values; and
responsive to determining that the one or more power measurements exceed the threshold values, issuing a notice of a state of the chamber component.

US Pat. No. 10,770,320

UNIVERSAL CHIP BATCH-BONDING APPARATUS AND METHOD

Shanghai Micro Electronic...

1. A universal chip batch-bonding apparatus, comprising a material pick-and-place area and a transfer work area, whereinthe material pick-and-place area comprises a blue tape pick-and-place section for providing chips and a substrate pick-and-place section for storing a substrate, the blue tape pick-and-place section and the substrate pick-and-place section being disposed at opposing ends of the transfer work area, respectively;
the transfer work area sequentially comprises a chip pickup and separation section, a chip alignment and fine-tuning section, and a chip batch-bonding section along a direction from the blue tape pick-and-place section to the substrate pick-and-place section; and
a chip carrying board conveyor is disposed in the transfer work area and arranged across the transfer work area, the chip carrying board conveyor moving between the chip pickup and separation section, the chip alignment and fine-tuning section, and the chip batch-bonding section to deliver materials,
wherein the chip carrying board conveyor comprises a first moving platform, a pressurizing apparatus mounted on the first moving platform, and a carrying board mounted on the pressurizing apparatus.

US Pat. No. 10,770,319

EPI THICKNESS TUNING BY PULSE OR PROFILE SPOT HEATING

APPLIED MATERIALS, INC., ...

1. A processing chamber, comprising:an enclosure for a processing volume;
a rotatable support within the enclosure, the rotatable support having a shaft that extends outside the enclosure;
one or more signal features disposed on the shaft outside the enclosure;
an energy module within the enclosure, wherein the shaft extends through the energy module;
one or more directed energy sources coupled to the enclosure; and
one or more signalers positioned proximate to the signal feature, the one or more signalers corresponding to at least one of the directed energy sources.

US Pat. No. 10,770,316

SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD AND RECORDING MEDIUM

TOKYO ELECTRON LIMITED, ...

1. A substrate liquid processing method, comprising:discharging a processing liquid toward a surface of a substrate from an outer nozzle provided at a position at an outside of an outer edge of the substrate; and
adjusting a height position or a discharge angle of the outer nozzle by using an actuator such that the processing liquid discharged from the outer nozzle arrives at a target arrival position on the substrate,
wherein, after a central portion of the surface of the substrate is covered with the processing liquid discharged from the outer nozzle, a discharge flow rate of the processing liquid is reduced and the height position of the outer nozzle is raised, and
wherein the substrate liquid processing method is performed while rotating the substrate,
when the processing liquid is being discharged from the outer nozzle to arrive at a center of the substrate, the processing liquid is discharged downwards from a movable nozzle provided at a nozzle arm such that the processing liquid arrives at a preset position, and
the preset position is near the center of the substrate, and is located, when viewed from directly above the substrate being rotated, within a fourth quadrant of an XY orthogonal coordinate system in which a straight line including a flight trajectory of the processing liquid is defined as an Y-axis, a flight direction of the processing liquid is defined as a positive Y-axis direction, a straight line including a second vector obtained by rotating a first vector, which is started from a rotation center of the substrate and faces toward the positive Y-axis direction, by 90 degrees in a rotational direction of the substrate with respect to the rotation center of the substrate is defined as an X-axis, and a direction of the second vector is defined as a positive X-axis direction.

US Pat. No. 10,770,315

FALL-PROOF APPARATUS FOR CLEANING SEMICONDUCTOR DEVICES AND A CHAMBER WITH THE APPARATUS

ACM Research (Shanghai) I...

1. A fall-proof apparatus for cleaning semiconductor devices, comprising:a nozzle connecting with a carrier;
a megasonic/ultrasonic wave generator that is fan-shaped, is fixed to the carrier, and generates megasonic/ultrasonic waves to clean the semiconductor devices;
a sensor that detects the distance between the megasonic/ultrasonic wave generator and the carrier and determines, based on the distance, whether the megasonic/ultrasonic wave generator is loose and going to fall,
wherein, during a cleaning process, the megasonic/ultrasonic wave generator is immerged into chemical liquids sprayed by the nozzle and generates megasonic/ultrasonic waves to clean the semiconductor devices.

US Pat. No. 10,770,314

SEMICONDUCTOR DEVICE, TOOL, AND METHOD OF MANUFACTURING

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming an opening through a dielectric layer to expose a conductive element of a semiconductor wafer, the opening exposing first sidewalls of the dielectric layer;
placing the semiconductor wafer into a first processing tool;
wet cleaning the opening within the first processing tool using a first etchant comprising an oxidizer and a solvent, the oxidizer comprising hydrogen peroxide, ozone water, or phosphate salt, wherein the first sidewalls of the dielectric layer are exposed by the opening during the wet cleaning;
plasma cleaning the opening within the first processing tool after the wet cleaning, wherein the first sidewalls of the dielectric layer are exposed by the opening during the plasma cleaning; and
forming a barrier layer along the first sidewalls of the dielectric layer and along an upper surface of the conductive element after the wet cleaning and the plasma cleaning, the barrier layer contacting the upper surface of the conductive element.

US Pat. No. 10,770,313

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

8. An integrated fan-out package, comprising:a first redistribution structure, comprising:
a first dielectric layer;
a ground plane disposed on the first dielectric layer;
a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer covers the ground plane, and the second dielectric layer has a plurality of trenches; and
a first feed line disposed on the first dielectric layer and located in the plurality of trenches;
a die, disposed on the first redistribution structure;
an insulation encapsulation encapsulating the die, wherein the insulation encapsulation fills into the plurality of trenches to cover the first feed line and sidewalls of the plurality of trenches, and the insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the first dielectric layer; and
a second redistribution structure disposed on the die and the insulation encapsulation.

US Pat. No. 10,770,312

UNDER-FILL DEFLASH FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE

SKYWORKS SOLUTIONS, INC.,...

1. A method of fabricating a packaged radio-frequency device, the method comprising:mounting components to a first side of a packaging substrate;
mounting a lower component to a second side of the packaging substrate, the second side of the packaging substrate including a plurality of contact pads for mounting solder balls;
under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent, the under-filling agent coating a portion of at least one of the plurality of contact pads;
deflashing a portion of the under-filling agent; and
mounting the solder balls on the contact pads of the second side of the packaging substrate after the portion of the under-filling agent has been deflashed.

US Pat. No. 10,770,311

STACK PACKAGE AND METHODS OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a stack package, the method comprising:attaching a first semiconductor device onto a first surface of a first package substrate;
attaching a molding resin material layer onto a first surface of a second package substrate;
arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other so that the molding resin material layer contacts an upper surface of the first semiconductor device;
compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and
hardening the reflowed molding resin material layer,
wherein the compressing of the first package substrate and the second package substrate comprises:
reflowing the molding resin material layer so that the molding resin material layer contacts side surfaces of the first semiconductor device; and
electrically connecting the first package substrate and the second package substrate.

US Pat. No. 10,770,310

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor layer and a first electrode overlapping with each other;
an insulating layer between the first electrode and the oxide semiconductor layer, the insulating layer being in contact with the oxide semiconductor layer; and
a pair of second electrodes in electrical contact with the oxide semiconductor layer,
wherein the insulating layer includes silicon, oxygen, and nitrogen oxide,
wherein the insulating layer includes a portion whose spin density measured by electron spin resonance spectroscopy is greater than or equal to 1×1017 spins/cm3 and less than 1×1018 spins/cm3,
wherein an electron spin resonance spectrum of the portion has a first signal that appears at a g-factor in a range greater than or equal to 2.037 and less than or equal to 2.039, a second signal that appears at a g-factor in a range greater than or equal to 2.001 and less than or equal to 2.003, and a third signal that appears at a g-factor in a range greater than or equal to 1.964 and less than or equal to 1.966, and
wherein the first signal, the second signal, and the third signal are attributed to the nitrogen oxide.

US Pat. No. 10,770,308

ETCHING METHOD

TOKYO ELECTRON LIMITED, ...

1. A method for etching a ruthenium film, comprising:a first step of etching the ruthenium film by plasma processing using oxygen-containing gas;
a second step of etching the ruthenium film by plasma processing using chlorine-containing gas; and
acquiring in-plane distribution data of a thickness of the ruthenium film,
wherein the first step and the second step are alternately performed, and
in the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step, and
in the first step and the second step, in-plane temperature distribution of the ruthenium film is controlled based on the in-plane distribution data of the thickness.

US Pat. No. 10,770,306

METHOD OF ETCHING A CAVITY IN A STACK OF LAYERS

STMicroelectronics (Croll...

1. A method, comprising:depositing a first layer made of a first material;
depositing a second layer made of a second material on top of an upper surface of the first layer;
depositing a third layer made of the first material on top of an upper surface of the second layer;
depositing a fourth layer made of the second material on top of an upper surface of the third layer;
wherein the third layer includes a first opening and wherein material of the fourth layer is located within the first opening;
forming a first etch mask over the fourth layer, the first etch mask having a second opening aligned with the first opening;
etching the fourth layer through the first opening to form a first cavity having a depth which does not reach the second layer;
forming a second etch mask over the fourth layer and within the first cavity, the second etch mask having a third opening which is aligned with the first cavity, wherein dimensions of the third opening are, in top view, smaller than dimensions of the first opening and second opening; and
etching a remaining portion of the fourth layer and the second layer through the third opening to form a second cavity having a depth which reaches the upper surface of the first layer.

US Pat. No. 10,770,305

METHOD OF ATOMIC LAYER ETCHING OF OXIDE

Tokyo Electron Limited, ...

1. A method for etching a substrate, comprising:providing a first layer comprising silicon oxide, the first layer to be etched selective to a second layer;
exposing the first layer to a first plasma comprising carbon tetrafluoride (CF4) to modify at least a surface of the first layer to form a modified surface layer, the modified surface layer being silicon rich compared to a remainder of the first layer; and
exposing the modified surface layer to a second plasma comprising hydrogen (H2), the plasma comprising H2 removing at least a portion of the modified surface layer,
wherein a combination of use of the first plasma and the second plasma reduces at least a portion of a thickness of the first layer.

US Pat. No. 10,770,304

HYBRID DOUBLE PATTERNING METHOD FOR SEMICONDUCTOR MANUFACTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating an integrated circuit (IC), comprising:converting an IC layout having a set of patterns into a graph, wherein the graph includes vertices and edges that connect some of the vertices, wherein the vertices correspond to the patterns of the IC layout, and wherein the edges correspond to spacings between the patterns;
dividing the edges into a first group and a second group, the first group including edges corresponding to spacings that are less than a first distance, the second group including edges corresponding to spaces that are at least the same as the first distance but less than a second distance;
assigning a first color to some of the vertices in the graph; and
assigning a second color different from the first color to some of the vertices connected to vertices of the first color, wherein vertices of the first color are patternable by a first lithography technique having a resolution of the first distance, and wherein vertices of the second color are patternable by a second lithography technique having a resolution of the second distance.

US Pat. No. 10,770,302

SEMICONDUCTOR FINFET DEVICE AND METHOD

Taiwan Semiconductor Manu...

16. A method of forming a semiconductor device, the method comprising:depositing a mask layer over a substrate;
patterning the mask layer to form a plurality of mask regions, wherein each mask region has convex sidewalls;
etching the substrate using the plurality of mask regions as an etching mask to form a plurality of fins, wherein after etching the substrate, the convex sidewalls of the mask regions extend laterally beyond upper sidewalls of the fins;
forming an isolation region surrounding the fins;
forming a gate structure over top surfaces of the fins and on the upper sidewalls of the fins; and
forming source and drain regions in the fin adjacent the gate structure.

US Pat. No. 10,770,300

REMOTE HYDROGEN PLASMA TITANIUM DEPOSITION TO ENHANCE SELECTIVITY AND FILM UNIFORMITY

Applied Materials, Inc., ...

1. A processing method comprising:flowing a first precursor into a volume in a processing chamber, the volume bounded by a chamber top and a gas distribution assembly;
energizing the first precursor in the volume to form H+ and H* species and allowing the first precursor to flow through first fluid channels formed in the gas distribution assembly into a processing region in the processing chamber; and
flowing a second precursor comprising a metal halide through the gas distribution assembly through second fluid channels into the processing region to react the first precursor in the processing region, wherein the metal halide and the H+ and H* species react to deposit a metal film on a first surface and a second surface of a substrate and unreacted metal halide species etch the metal film formed on the second surface to selectively deposit the metal film on the first surface with a selectivity greater than or equal to about 10:1.

US Pat. No. 10,770,299

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor fin extending along a first direction above a substrate; and
a gate structure extending across the semiconductor fin along a second direction substantially perpendicular to the first direction, the gate structure comprising a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.

US Pat. No. 10,770,298

AUTOMATIC INSPECTION DEVICE AND METHOD OF LASER PROCESSING EQUIPMENT

EO TECHNICS CO., LTD., G...

1. An automatic inspection method for inspecting processing quality of laser processing equipment that forms a modified area by irradiating a laser beam into an object to be processed, the automatic inspection method comprising:preparing the object to be processed on which an image film is coated;
performing a processing operation by irradiating the laser beam into the object to be processed by using the laser processing equipment;
detecting a damage image of the object to be processed formed on the image film through irradiation of the laser beam; and
processing the damage image of the object to be processed.

US Pat. No. 10,770,297

METHOD TO FORM ULTRASHALLOW JUNCTIONS USING ATOMIC LAYER DEPOSITION AND ANNEALING

Lam Research Corporation,...

1. A method comprising:depositing a first layer on a layer of a substrate using atomic layer deposition (ALD), the layer including a material selected from a group consisting of silicon (Si), germanium (Ge) and silicon germanium (Si1-xGex);
depositing a second layer on the first layer using ALD,
wherein depositing one of the first layer and the second layer includes depositing phosphorus oxide and depositing the other one of the first layer and the second layer includes depositing antimony oxide;
wherein depositing the one of the first layer and the second layer includes performing a plurality of ALD supercycles; and
wherein each of the plurality of ALD supercycles includes depositing N phosphorus oxide layers and M silicon oxide layers, where M and N are integers greater than zero; and
annealing the substrate to drive antimony and phosphorus from the first ayer and the second layer into the layer of the substrate to create a junction.

US Pat. No. 10,770,296

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A method of manufacturing a semiconductor device, the method comprising:forming a gate oxide film on an upper surface of a semiconductor layer;
forming a gate conductive film to come in contact with the gate oxide film in a unit cell portion;
forming a gate wire to come in contact with the gate oxide film in a termination region provided to surround the unit cell portion in plan view;
forming a first insulation film on an upper surface of the gate wire in the termination region;
subjecting an upper surface of the gate conductive film in the unit cell portion to thermal oxidation with use of the first insulation film as a mask to form a thermal oxide film on the upper surface of the gate conductive film; and
forming a second insulation film covering the first insulation film and the thermal oxide film.

US Pat. No. 10,770,295

PATTERNING METHOD

IMEC VZW, Leuven (BE)

1. A patterning method comprising:forming a layer stack comprising in a bottom-up direction a target layer, a lower memorization layer and an upper memorization layer,
forming above the upper memorization layer a first mask layer, wherein a set of trenches are formed in the first mask layer using lithography and etching,
patterning a set of upper trenches in the upper memorization layer, the patterning comprising using the first mask layer as an etch mask,
forming a spacer layer on sidewalls of the set of upper trenches,
forming a first block pattern, the first block pattern comprising a set of first blocks, each first block extending across an upper trench in the upper memorization layer,
patterning a first set of lower trenches in the lower memorization layer, the patterning comprising using the patterned upper memorization layer, the spacer layer and the first block pattern as an etch mask, wherein at least a subset of the first set of lower trenches are interrupted by a trench interruption, each trench interruption being formed by a portion of the lower memorization layer preserved under a respective one of the first blocks,
patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, each second block being formed of a respective remaining portion of the upper memorization layer,
forming above the patterned lower memorization layer and the second block pattern a second mask layer, wherein a set of trenches are formed in the second mask layer using lithography and etching, wherein each trench of the set of trenches is formed over a respective remaining portion of the patterned lower memorization layer,
patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask, wherein at least a subset of the second set of lower trenches are interrupted by a trench interruption, each trench interruption being formed by a portion of the lower memorization layer preserved under a respective one of the second blocks, and
wherein the method further comprises patterning in the target layer a first set of target trenches under the first set of lower trenches and a second set of target trenches under the second set of lower trenches.

US Pat. No. 10,770,294

SELECTIVE ATOMIC LAYER DEPOSITION (ALD) OF PROTECTIVE CAPS TO ENHANCE EXTREME ULTRA-VIOLET (EUV) ETCH RESISTANCE

TOKYO ELECTRON LIMITED, ...

1. A method of processing microelectronic workpieces, comprising:providing a patterned extreme ultraviolet (EUV) photoresist layer above an underlying layer, the patterned EUV photoresist layer including openings having sidewalls, with the openings forming a pattern for the EUV photoresist layer;
depositing a protective material on the patterned EUV photoresist layer using selective atomic layer deposition (ALD) to form protective caps on top regions for the patterned EUV photoresist layer, the protective material comprising aluminum oxide, silicon oxide or titanium oxide; and
transferring the pattern for the patterned EUV photoresist layer to the underlying layer using one or more etch processes.

US Pat. No. 10,770,293

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, the method comprising:forming a photo resist layer over a substrate with underlying structures;
exposing the photo resist layer to exposure radiation;
developing the exposed photo resist layer with a developing solution; and
forming a planarization layer over the developed photo resist layer, wherein:
the underlying structures include concave portions, and
one of the concave portions is filled by the developed photo resist layer and one of the concave portions does not include the developed photo resist layer.

US Pat. No. 10,770,292

WAFER TREATMENT FOR ACHIEVING DEFECT-FREE SELF-ASSEMBLED MONOLAYERS

Applied Materials, Inc., ...

1. A processing method comprising:providing a substrate with an exposed first material and an exposed second material;
exposing the substrate to a pre-clean process in a pre-clean chamber, the pre-clean process comprising heating the substrate to a first temperature, cleaning the substrate of contaminants and activating a surface of the first material to promote formation of a self-assembled monolayer (SAM) on the exposed first material;
forming a SAM on the exposed first material at a second temperature by exposing the substrate to a plurality of cycles of a SAM formation process followed by a final exposure to a SAM molecule, each cycle of the SAM formation process comprising exposing the substrate to the SAM molecule followed by heating the substrate and reactivation of the surface of the first material; and
selectively depositing a film on the exposed second material,
wherein activating the surface of the first material comprises exposing the substrate to an activating agent comprising water vapor provided by a remote plasma source that generates hydroxyl terminations on the surface.

US Pat. No. 10,770,291

METHODS AND MASKS FOR LINE END FORMATION FOR BACK END OF LINE (BEOL) INTERCONNECTS AND STRUCTURES RESULTING THEREFROM

Intel Corporation, Santa...

1. A method of fabricating an interconnect structure for a semiconductor die, the method comprising:forming a hardmask layer above an interlayer dielectric (ILD) material layer;
forming a first patterned hardmask layer above the hardmask layer, the first patterned hardmask layer having a grating pattern with a first direction;
forming a second patterned hardmask layer above the first patterned hardmask layer, the second patterned hardmask layer having a grating pattern with a second direction orthogonal to the first direction;
forming a lithographic patterning mask above the second patterned hardmask layer, the lithographic patterning mask having regions protecting selected line end locations for the ILD material layer;
removing portions of the second patterned hardmask layer not protected by the regions of the lithographic patterning mask to form a third patterned hardmask layer and then removing the lithographic patterning mask; and
transferring a combined pattern of the third patterned hardmask layer and the first patterned hardmask layer to the hardmask layer and to the ILD material layer.

US Pat. No. 10,770,290

METHOD FOR FORMING STACKED NANOWIRE TRANSISTORS

TAIWAN SEMICONDUCTOR MANU...

11. A semiconductor device, comprising:a substrate;
a first nanowire stack including a first plurality of nanowires; and
a second nanowire stack including a second plurality of nanowires, wherein a nanowire of the first plurality of nanowires has a different thickness than a nanowire of the second plurality of nanowires, and wherein a top surface of a top-most nanowire of the first plurality of nanowires is coplanar with a top surface of a top-most nanowire of the second plurality of nanowires, wherein a bottommost nanowire from the first nanowire stack is closer to the substrate than a bottommost nanowire from the second nanowire stack without either bottommost nanowires from the first or second nanowire stacks directly contacting the substrate, wherein the bottommost nanowire from the second nanowire stack is thicker than the bottommost nanowire from the first nanowire stack, wherein the top-most nanowire of the first plurality of nanowires is formed of a different material than the top-most nanowire of the second plurality of nanowires.

US Pat. No. 10,770,289

SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER

Massachusetts Institute o...

19. A method, comprising:forming a single-crystalline film on a graphene layer that is on a substrate having a potential field, wherein the potential field of the substrate reaches beyond the graphene layer to seed the growth of the single-crystalline film; and
separating the single-crystalline film and the substrate.

US Pat. No. 10,770,288

SELECTIVE CAPPING PROCESSES AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A structure comprising:a first dielectric layer over a substrate, the first dielectric layer having a dielectric surface terminated with a species comprising a hydrophobic functional group, wherein the hydrophobic functional group is in a monolayer of hydrophobic functional groups along a top surface of the first dielectric layer;
a conductive feature in the first dielectric layer;
a metal cap on the conductive feature, wherein the metal cap comprises a fluorine free tungsten; and
a second dielectric layer on the dielectric surface and the metal cap.

US Pat. No. 10,770,287

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:(a) forming NH termination on a surface of a substrate by supplying a first reactant containing N and H to the substrate;
(b) forming a first SiN layer having SiCl termination formed on its surface by supplying SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4;
(c) forming a second SiN layer having NH termination formed on its surface by supplying a second reactant containing N and H to the substrate to react the SiCl termination formed on the surface of the first SiN layer with the second reactant; and
(d) forming a SiN film on the substrate by performing a cycle a predetermined number of times under a condition where the SiCl4 is not gas-phase decomposed after performing (a), the cycle including non-simultaneously performing (b) and (c).

US Pat. No. 10,770,286

METHODS FOR SELECTIVELY FORMING A SILICON NITRIDE FILM ON A SUBSTRATE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

ASM IP Holdings B.V., Al...

1. A method for selectively forming a silicon nitride film on a substrate comprising a first metallic surface and a second dielectric surface by a cyclical deposition process, the method comprising:determining a first incubation period for forming the silicon nitride film on the first metallic surface;
determining a second incubation period for forming the silicon nitride film on the second dielectric surface;
determining a process condition, in response to determining the first incubation period and determining the second incubation period, wherein the first incubation period is less than the second incubation period such that a deposition selectivity favors deposition of the silicon nitride film on the first metallic surface relative to the second dielectric surface; and
performing the cyclical deposition process, at the process condition, comprising:
contacting the substrate with a first reactant comprising a silicon halide source, and
contacting the substrate with a second reactant comprising a nitrogen source,
wherein the second reactant reacts with first reactant molecules to form the silicon nitride film, and
wherein the process condition comprises heating the substrate to a temperature of between approximately 200° C. and approximately 350° C. during the cyclical deposition process;
wherein the first metallic surface comprises at least one of clustered titanium nitride,tantalum silicon nitride (TaSiN), and molybdenum (Mo).

US Pat. No. 10,770,285

SILICON MEMBER AND METHOD OF PRODUCING THE SAME

MITSUBISHI MATERIALS CORP...

2. A method of producing a holding plate comprising steps of:excising a large-sized plate material made of a poly-crystalline silicon or a pseudosingle-crystalline silicon from a unidirectionally solidified columnar crystal ingot;
forming a coating layer composed of a product of silicon formed by reaction of the silicon on a surface of the large-sized plate material which has micro-cracks on the surface before forming the coating layer, wherein
the large-sized plate material has the dimension: width W being 500 mm to 1500 mm; length L being 500 mm to 1500 mm; and thickness H being 5 mm to 50 mm,
the step of forming the coating layer comprises the steps of:
forming a silicon oxide film on the surface of the large-sized plate material in a furnace by pyrogenic oxidation;
removing the silicon oxide film from the large-sized plate material using a buffered hydrofluoric acid solution; and
forming a silicon nitride film on the surface of the large-sized plate material as the coating layer while flowing ammonia into the furnace.

US Pat. No. 10,770,284

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing method comprising:(a) supplying an etchant onto a first surface of a substrate to etch a circuit pattern convexly formed on the first surface;
(b) setting, in parallel with the step (a), a first temperature in a lower portion of the circuit pattern in the etchant lower than a second temperature in an upper portion of the circuit pattern in the etchant based on a reactivity of the etchant at the first temperature and the second temperature; and
(c) supplying rinse liquid onto the etched first surface after the step (a) to replace the etchant remaining on the circuit pattern with the rinse liquid so that an amount of etching of the lower portion of the circuit pattern equals an amount of etching of the upper portion of the circuit pattern.

US Pat. No. 10,770,283

SUBSTRATE ALIGNING METHOD, SUBSTRATE RECEIVING METHOD, SUBSTRATE LIQUID PROCESSING METHOD, SUBSTRATE ALIGNING APPARATUS, SUBSTRATE RECEIVING APPARATUS, SUBSTRATE LIQUID PROCESSING APPARATUS, AND SUBSTRATE PROCESSING SYSTEM

TOKYO ELECTRON LIMITED, ...

1. A substrate aligning apparatus comprising:a substrate support configured to carry a plurality of substrates, the substrate support including a plurality of pairs of arms, each pair of arms being configured to carry one of the plurality of substrates;
a substrate aligner configured to rotate the plurality of substrates; and
a controller including a non-transitory computer readable storage medium having stored therein a program that when executed performs an overall control of the substrate aligning apparatus, wherein the controller is configured to:
receive deformation information of each of the plurality of substrates recorded in advance identifying positions of warped portions along an outer periphery edge of each of the plurality of substrates,
rotate the plurality of substrates relative to the substrate support according to the received deformation information such that the warped portions of each of the plurality of substrates identified by the received deformation information are aligned to be offset relative to a front of the plurality of pairs of arms of the substrate support, and
move each of the pairs of arms of the substrate support along each of the plurality of substrates from an outside of the outer periphery edge of each of the plurality of substrates toward a central portion thereof without being impeded by the warped portions of each of the plurality of substrates after the plurality of substrates are aligned.

US Pat. No. 10,770,282

LASER-PUMPED PLASMA LIGHT SOURCE AND PLASMA IGNITION METHOD

RnD-ISAN, Ltd, Troitsk, ...

1. A laser-pumped plasma light source, comprising: a gas filled chamber, at least a part of which is optically transparent; a region of radiating plasma sustained in the chamber by a focused beam of a continuous wave (CW) laser; at least one output beam of plasma radiation exiting the chamber, a means for plasma ignition characterized in thatthe means for plasma ignition is a pulsed laser system generating a first and a second laser beams focused in the chamber, whereas
said first laser beam is arranged for a gas optical breakdown, and
said second laser beam is arranged for plasma ignition after the optical breakdown.

US Pat. No. 10,770,281

ION TRAP DEVICE

Shimadzu Corporation, Ky...

1. An ion trap device, comprising:a) an ion trap including a plurality of electrodes;
b) a rectangular voltage generator including a voltage source for generating a direct voltage and a switching section, the rectangular voltage generator configured to operate the switching section to generate a rectangular voltage by switching the direct voltage generated by the voltage source, and to apply the rectangular voltage to at least one of the plurality of electrodes; and
c) a switching section temperature controller configured to control a temperature of the switching section so as to maintain the temperature of the switching section at a target temperature which is higher than a highest reaching temperature of the switching section during an operation of the ion trap and lower than a highest permissible temperature for an operation of the switching section.

US Pat. No. 10,770,280

RIGHT ANGLE TIME-OF-FLIGHT DETECTOR WITH AN EXTENDED LIFE TIME

LECO Corporation, St. Jo...

1. A time-of-flight detector, comprising:a conductive converter exposed parallel to a time-front of detected ion packets and generating secondary electrons;
at least one electrode with a side window, wherein the converter is negatively floated relative to the electrode by a voltage difference between 100V and 1000V;
at least one magnet with magnetic field strength between 10 Gauss and 1000 Gauss for bending electron trajectories towards said side window;
a scintillator floated positively relative to a surface of said converter by 1 kV to 20 kV and located past said side window at 45 degrees to 180 degrees relative to said converter; and
a sealed photo-multiplier past said scintillator.

US Pat. No. 10,770,279

ION TRANSFER APPARATUS

SHIMADZU CORPORATION, Ky...

1. An ion transfer apparatus for transferring ions from an ion source at an ion source pressure, which ion source pressure is atmospheric pressure, along a path towards a mass analyser at a mass analyser pressure that is lower than the ion source pressure, the apparatus including:five or more pressure controlled chambers, wherein each pressure controlled chamber in the ion transfer apparatus includes an ion inlet opening for receiving ions from the ion source on the path and an ion outlet opening for outputting the ions on the path;
wherein the pressure controlled chambers are arranged in succession along the path from an initial pressure controlled chamber of the pressure controlled chambers to a final pressure controlled chamber of the pressure controlled chambers, wherein the ion outlet opening of each pressure controlled chamber other than the final pressure controlled chamber is in flow communication with the ion inlet opening of a successive adjacent pressure controlled chamber, of the pressure controlled chambers;
wherein the ion transfer apparatus is configured to have, in use, a plurality of pairs of adjacent pressure controlled chambers of the pressure controlled chambers for which a ratio of pressure in an upstream pressure controlled chamber to pressure in a downstream pressure controlled chamber in each pair is set to be greater than 1 and less than 1.8 such that there is substantially subsonic gas flow in the downstream pressure controlled chamber in each pair;
wherein the ion transfer apparatus is configured to have, in use, a ratio of the ion source pressure to pressure in the initial pressure controlled chamber of 1.8 or less such that there is substantially subsonic gas flow in the initial pressure controlled chamber.

US Pat. No. 10,770,278

EXTRACTION SYSTEM FOR CHARGED SECONDARY PARTICLES FOR USE IN A MASS SPECTROMETER OR OTHER CHARGED PARTICLE DEVICE

Luxembourg Institute of S...

1. A charged particle beam deflecting system, the charged particle beam deflecting system comprising:an inner spherical sector;
an outer spherical sector;
an entry for the charged particle beam;
an exit passageway with an exit axis through which a deflected charged particle beam leaves the system;
a deflecting gap which is formed between the spherical sectors and which communicates with the entry and with the exit passageway;
an exit wall electrode with an exit opening facing the deflecting gap, the exit wall electrode comprising an exit wall potential;
the spherical sectors being biased at deflecting potentials in order to deflect the charged particle beam entering the deflecting gap by a given angle;
wherein the system further comprises:
an intermediate electrode with a plate shape and with an exit through hole, the intermediate electrode being arranged between the deflecting gap and the exit wall electrode; and
two side plates both facing the spherical sectors, the side plates being biased in order to create an electrostatic field perpendicular to the exit axis.

US Pat. No. 10,770,277

SYSTEM AND METHOD FOR THE ACOUSTIC LOADING OF AN ANALYTICAL INSTRUMENT USING A CONTINUOUS FLOW SAMPLING PROBE

LABCYTE, INC., San Jose,...

1. An acoustic loading system for transporting an analyte in a fluid sample to an analytical instrument, comprising:(a) a reservoir housing a fluid sample containing an analyte, the fluid sample having a fluid surface;
(b) an acoustic droplet ejector for generating acoustic radiation in a manner effective to eject a droplet of the fluid sample from the fluid surface; and
(c) a continuous flow sampling probe spaced apart from the fluid surface, comprising (i) a sampling tip for receiving the ejected droplet of the fluid sample, (ii) a solvent inlet for receiving a solvent from a solvent source, (iii) a solvent transport capillary for transporting the solvent from the solvent inlet to the sampling tip, where the ejected droplet combines with the solvent to form an analyte-solvent dilution, (iv) a sample outlet through which the analyte-solvent dilution is directed away from the sampling probe to an analytical instrument, and (v) a sample transport capillary for transporting the analyte-solvent dilution from the sampling tip to the sample outlet, wherein the sample transport capillary and the solvent transport capillary are in fluid communication at the sampling tip.

US Pat. No. 10,770,276

TECHNIQUES OF MASS SPECTROMETRY FOR ISOTOPOMER ANALYSIS AND RELATED SYSTEMS AND METHODS

Yale University, New Hav...

1. A spectrometer, configured to:receive molecules of a plurality of metabolites including one or more molecules of a first metabolite;
filter the received molecules to retain molecules of the first metabolite including a plurality of different mass isotopomers of the first metabolite;
fragment molecules of a first mass isotopomer of the retained molecules to produce a first plurality of daughter ions;
measure abundances of the first plurality of daughter ions as a function of daughter ion mass;
fragment molecules of a second mass isotopomer, different from the first mass isotopomer, of the retained molecules to produce a second plurality of daughter ions; and
measure abundances of the second plurality of daughter ions as a function of daughter ion mass.

US Pat. No. 10,770,275

FILM FORMING UNIT FOR SPUTTERING APPARATUS

ULVAC, INC., Kanagawa (J...

1. A film forming unit for a sputtering apparatus comprising:a supporting plate detachably disposed on an opening in a vacuum chamber, provided that one-side surface of the supporting plate is defined as an upper side, the supporting plate having on the upper side thereof;
at least one target, each target having a backing plate bonded to a lower surface of the target;
a magnet unit fixedly disposed between the backing plate and the supporting plate so as to cause leakage magnetic field to function on the target; and
driving means for reciprocating the target relative to the magnet unit along the supporting plate while electric power is applied from a sputtering power source to the target, thereby sputtering the target,
wherein:
each backing plate has a supply pipe and a discharge pipe for coolant,
the supply pipe and discharge pipe protrude into the backing plate for communication with coolant passages formed inside the backing plate;
the supporting plate has a slit hole which is elongated in the direction of reciprocating movement of the target and through which the supply pipe and the discharge pipe, both for coolant, are respectively inserted;
the supporting plate has on its lower surface a cap body which hermetically encloses, inclusive of the slit hole, those portions of the supply pipe and the discharge pipe which are protruded downward from the slit hole;
bellows pipes are respectively inserted onto an outside of those portions of the supply pipe and discharge pipe which are protruded in the reciprocating direction out of the cap body; and
a drive part of the driving means is coupled to at least one of the supply pipe and the discharge pipe.

US Pat. No. 10,770,273

OES DEVICE, PLASMA PROCESSING APPARATUS INCLUDING THE SAME AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A plasma processing apparatus comprising:a chamber configured to perform a plasma process on a wafer;
a viewport configured to transmit plasma light generated in the chamber;
a rotation module coupled to the viewport to be rotatable around a rotation axis; and
an OES (Optical Emission Spectroscopy) device which is coupled to the rotation module and configured to receive the plasma light,
wherein the rotation module includes a first surface facing the viewport and a second surface facing the OES device,
wherein the first surface is configured to block a part of the plasma light, and includes a first opening through which an inside of the rotation module is configured to be exposed to a part of the plasma light, and
wherein the second surface includes a second opening configured to be in optical communication with the first opening.

US Pat. No. 10,770,272

PLASMA-ENHANCED ANNEAL CHAMBER FOR WAFER OUTGASSING

Applied Materials, Inc., ...

1. A substrate processing apparatus, comprising:a first thermal process chamber defining a first process volume;
a second thermal process chamber defining a second process volume;
a first remote plasma source coupled to the first thermal process chamber by a first plasma conduit configured to deliver a plasma from the first remote plasma source to a first showerhead disposed in the first process volume;
a second plasma conduit coupled between the first remote plasma source and the second process chamber, the second plasma conduit configured to deliver the plasma for the first remote plasma source to a second showerhead disposed in the second process volume;
a plasma flow controller disposed in the second plasma conduit;
a second remote plasma source coupled to the second process chamber by a third plasma conduit;
an exhaust coupled to the first thermal process chamber by a first exhaust conduit and to the second thermal process chamber by a second exhaust conduit;
a common exhaust conduit coupling the first exhaust conduit and the second exhaust conduit to the exhaust;
a total exhaust flow controller disposed in the common exhaust conduit; and
a chamber exhaust flow controller disposed in the first exhaust conduit.

US Pat. No. 10,770,271

PLASMA-ACTIVATED SALINE SOLUTIONS AND METHOD OF MAKING PLASMA ACTIVATED SALINE SOLUTIONS

U.S. Patent Innovations L...

1. A method for manufacturing plasma-activated saline for treatment of cancer cells comprising:immersing a cathode in saline solution in a container;
positioning an anode at a fixed distance from a surface of said saline solution in said container; and
applying electrical energy to said anode for a fixed period of time;
wherein said fixed distance and said fixed period of time are selected to cause a plasma self-organized pattern at a surface of said saline solution with an atmospheric discharge between said anode and said cathode and
where in said plasma self-organized pattern comprises a double ring structure.

US Pat. No. 10,770,270

HIGH POWER ELECTROSTATIC CHUCK WITH APERTURE-REDUCING PLUG IN A GAS HOLE

Applied Materials, Inc., ...

1. An electrostatic chuck to carry a workpiece for processing, the electrostatic chuck comprising:a top plate to carry the workpiece, the top plate having an electrode to grip the workpiece;
a cooling plate under the top plate to cool the top plate;
a gas hole through the cooling plate and the top plate to feed a gas to the workpiece through the top plate, wherein the cooling plate feeds the gas into a plug in the top plate, the plug having a top surface and a tapered shape, the top surface facing away from the cooling plate, and the tapered shape inwardly tapering in a direction from the cooling plate to the top plate, wherein a portion of the gas hole extends from the top surface of the plug through the top plate; and
an aperture-reducing plug in the cooling plate gas hole to conduct gas flow through the hole.

US Pat. No. 10,770,269

APPARATUS AND METHODS FOR REDUCING PARTICLES IN SEMICONDUCTOR PROCESS CHAMBERS

Applied Materials, Inc., ...

1. A processing apparatus, comprising:a chamber body and a chamber lid enclosing a processing region;
a substrate support assembly;
a substrate support liner surrounding the substrate support assembly;
a plasma screen disposed below the processing region and above the substrate support liner; and
a chamber liner disposed inside the chamber body, the chamber liner comprising:
a bottom; and
a sidewall extending from a periphery of the bottom, wherein the sidewall forms a closed loop surrounding the substrate support assembly, the sidewall having a first plurality of through holes grouped together and formed through a portion of the sidewall, and a remaining portion of the sidewall free from additional through holes.

US Pat. No. 10,770,268

PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method comprising:a first film forming step of forming a carbon-containing film on surfaces of components in a chamber by using a plasma of a carbon-containing gas;
a second film forming step of forming a silicon-containing film whose film thickness is determined based on a film thickness of the carbon-containing film on a surface of the carbon-containing film by a silicon-containing gas;
a plasma processing step of processing a target object loaded into the chamber by using a plasma of a processing gas after the formation of the silicon-containing film;
a first removal step of removing the silicon-containing film from the surface of the carbon-containing film by using a plasma of a fluorine-containing gas after the target object processed by the plasma is unloaded from the chamber; and
a second removal step of removing the carbon-containing film from the surfaces of the components by using a plasma of an oxygen-containing gas,
wherein the film thickness of the silicon-containing film determined in the second film forming step is greater than or equal to a predetermined fraction of the film thickness of the carbon-containing film to maintain a balance between a film stress of the silicon-containing film and a film stress of the carbon-containing film.

US Pat. No. 10,770,267

METHODS AND APPARATUS FOR SUPPLYING RF POWER TO PLASMA CHAMBERS

APPLIED MATERIALS, INC., ...

1. A method for matching an impedance of a process chamber, comprising:dynamically matching a load impedance of the process chamber with an impedance matching circuit coupled between a radio frequency (RF) power source and the process chamber, the impedance matching circuit configured to compensate for changes in the load impedance to match an impedance of the RF power source over a wide range of load impedances;
filtering power feeding back from the process chamber with a first filter positioned between the impedance matching circuit and the process chamber, the first filter configured as a wide bandpass filter; and
filtering residual signals with a second filter positioned between the impedance matching circuit and the RF power source, the second filter configured as a low pass filter.

US Pat. No. 10,770,266

CHARGED PARTICLE BEAM DEVICE AND CAPTURING CONDITION ADJUSTING METHOD IN CHARGED PARTICLE BEAM DEVICE

Hitachi High-Tech Corpora...

1. A charged particle beam device, comprising:an electron source which generates an electron beam;
an objective lens which is applied with a coil current to converge the electron beam on a sample;
a control unit which controls the coil current to be applied to the objective lens;
a hysteresis characteristic storage unit which stores hysteresis characteristic information of the objective lens;
a history information storage unit which stores history information related to the coil current; and
an estimation unit which estimates a magnetic field generated by the objective lens on the basis of the coil current, the history information, and the hysteresis characteristic information.

US Pat. No. 10,770,265

SYSTEM AND METHOD FOR PREPARING CRYO-EM GRIDS

Neptune Fluid Flow System...

1. An electron microscopy (EM) sample preparation apparatus comprising:a cryogenically-cooled stage; and
a sample dispenser that is movable and rotatable with respect to the stage and that is configured to deposit, at a selected rate of deposition, a liquid sample onto the stage,
wherein the liquid sample deposited onto the stage by the sample dispenser is vitrified automatically and immediately in place with a user-defined vitreous ice thickness.

US Pat. No. 10,770,264

INTERFERENCE OPTICAL SYSTEM UNIT, CHARGED PARTICLE BEAM INTERFERENCE APPARATUS, AND METHOD FOR OBSERVING CHARGED PARTICLE BEAM INTERFERENCE IMAGE

RIKEN, Saitama (JP)

1. An interference optical system unit comprising:at least one electromagnetic lens that forms an image of a charged particle beam; and
at least one charged particle beam biprism;
wherein the electromagnetic lens, the charged particle beam biprism, and a space to an image plane of the electromagnetic lens are integrally configured as one unit,
the interference optical system unit is disposed to have an optical axis coaxialized with an optical axis of an imaging optical system of an upstream stage, the imaging optical system being disposed on an upstream side of the unit in a flow direction of the charged particle beam, and
a focal length of the electromagnetic lens and a deflection angle of the charged particle beam given by the charged particle beam biprism are controlled to generate an interference fringe of the charged particle beam on the image plane of the electromagnetic lens.

US Pat. No. 10,770,263

METHODS AND SYSTEMS FOR DETERMINING A FAULT IN A GAS HEATER CHANNEL

Lam Research Corporation,...

1. A controller comprising:a processor configured to:
receive an amount of current flowing via a plurality of heater elements coupled in series and an amount of voltage across each of the plurality of heater elements coupled in series;
calculate a measured parallel resistance from the amount of current and the amount of voltage;
compare the measured parallel resistance with an ideal parallel resistance for the plurality of heater elements; and
determine, based on the comparison between the measured parallel resistance and the ideal parallel resistance, that at least one of the plurality of heater elements is faulty; and
a memory device coupled to the processor.

US Pat. No. 10,770,262

APPARATUS, METHOD AND SYSTEM FOR IMAGING AND UTILIZATION OF SEM CHARGED PARTICLES

1. A scanning electron microscope (SEM) system, comprising:an electron source that emits a beam of primary electrons toward a sample such that the primary electrons being incident on the sample causes emission of charged particles from the sample;
an electron focusing element that is configured to accelerate the charged particles away from the sample;
a detector positioned such that the electron focusing element accelerates the charged particles toward a surface of the detector such that the charged particles are projected onto the surface of the detector according to a distribution of the charged particles about the beam of primary electrons, wherein responsive to a charged particle in the charged particles being incident on the surface of the detector, the detector emits light indicative of a location at which the charged particle struck the surface of the detector, the location being indicative of at least one of an energy or an angle of emission of the charged particle;
an imaging system that outputs an image of the detector; and
a computing system that receives the image of the detector from the imaging system and computes an Abel transform based upon the image, wherein the Abel transform is indicative of the distribution of the charged particles about the beam of primary electrons, and wherein the computing system outputs data indicative of the energy and the angle of emission of the charged particle based upon the Abel transform.

US Pat. No. 10,770,261

SYSTEM AND METHOD TO MONITOR GLITCH ENERGY

Varian Semiconductor Equi...

1. An apparatus for processing a workpiece, comprising:an ion source;
an electrically biased component, wherein the component is used to attract, accelerate, decelerate or focus ions along a path of an ion beam;
a controller; and
a glitch capture module, wherein the glitch capture module is in communication with the electrically biased component and the controller, and wherein the glitch capture module monitors a voltage present on the electrically biased component, captures and holds a lowest voltage detected on the electrically biased component, and transmits the lowest voltage to the controller, wherein the lowest voltage is captured and held for a predetermined period of time so as to be longer in duration than a sampling period of the controller.

US Pat. No. 10,770,260

DEFECT OBSERVATION DEVICE

HITACHI HIGH-TECHNOLOGIES...

1. A defect observation device comprising:a first imaging unit that captures a plurality of defects detected by an external inspection device;
a control unit that corrects positional information on the defects by using an image captured by the first imaging unit; and
a scanning electron microscope configured with a second imaging function and comprising a second imaging unit that captures the defects based on the corrected position information,
wherein the first imaging unit includes a plurality of imaging portions,
the control unit selects one of the first imaging unit and the second imaging unit as a next imaging unit for each of the defects based on the information obtained by imaging the defect by the first imaging unit,
the control unit sets a next imaging portion of the first imaging unit from the plurality of imaging portions in the first imaging unit or an imaging condition of the second imaging unit,
the control unit sets an accumulation frame number, an acceleration voltage, a probe current, an imaging magnification or an imaging field of view as the imaging condition of the second aging unit, and
the control unit calculates a coordinate correction formula based on the positional information of the defect detected by the first imaging unit and the information obtained by an image acquired by the first imaging unit, and images the defect by using the second imaging unit based on the corrected positional information.

US Pat. No. 10,770,259

STAGE DEVICE AND CHARGED PARTICLE BEAM DEVICE

HITACHI HIGH-TECH CORPORA...

1. A sample stage to support a sample, the sample stage comprising:a table;
a guide rail that extends in a moving direction;
a carriage configured to move along the guide rail in the moving direction together with the table by rotation of a rolling element included inside the carriage; and
an adapter connecting the table and the carriage,
wherein the adapter has a first protruding portion protruding toward the carriage and connected the carriage, and the first protruding portion has a length in the moving direction which is longer than a length thereof in a direction orthogonal to the moving direction, and
wherein the adapter has a second protruding portion protruding toward the table and connected to the table, and the second protruding portion has a length in the direction orthogonal to the moving direction which is longer than a length thereof in the moving direction.

US Pat. No. 10,770,258

METHOD AND SYSTEM FOR EDGE-OF-WAFER INSPECTION AND REVIEW

KLA-Tencor Corporation, ...

1. A system comprising:an electron beam source configured to generate one or more electron beams;
a sample stage configured to secure a sample;
an electron-optical column including a set of electron-optical elements configured to direct at least a portion of the one or more electron beams onto an edge portion of the sample, the set of electron-optical elements including at least one of one or more electron-optical lenses or one or more scanning elements;
a detector assembly configured to detect electrons emanating from the sample; and
a controller, wherein the controller is communicatively coupled to one or more portions of at least one of the electron beam source, the set of electron-optical elements of the electron-optical column or the sample stage, wherein the controller includes one or more processors configured for executing program instructions stored in memory, wherein the program instructions are configured to cause the one or more processors to:
receive one or more parameters representative of one or more characteristics of the one or more electron beams at the edge portion of the sample;
generate a look-up table for compensating for one or more fringe fields within the system via a simulation, wherein the generated look-up table includes a set of coefficients and corresponding fringe-field offsets, wherein the set of coefficients are a function of use conditions of electron beam energy, electron beam landing energy, and extracting field of the sample; and
adjust one or more characteristics of the system based on the generated look-up table.

US Pat. No. 10,770,257

SUBSTRATE PROCESSING METHOD

ASM IP Holding B.V., Alm...

1. A substrate processing method comprising:plasma processing a substrate placed on a susceptor;
applying power to an RF electrode facing the susceptor for only a first predetermined static electricity removal time to generate a plasma after the plasma processing, thereby reducing an amount of charge of the substrate;
measuring a self-bias voltage of the RF electrode after generation of the plasma while susceptor pins are made to protrude from a top surface of the susceptor and lift up the substrate; and
by a controller that is configured to shorten static electricity removal time based entirely on the self-bias voltage and to lengthen static electricity removal time based entirely on the self-bias voltage, shortening a subsequent static electricity removal time when the self-bias voltage has a positive value, and lengthening the subsequent static electricity removal time when the self-bias voltage has a negative value, and after the subsequent static electricity removal time has been lengthened or shortened, plasma processing a subsequent substrate placed on the susceptor followed by applying the power to the RF electrode facing the susceptor for the subsequent static electricity removal time.

US Pat. No. 10,770,255

SELF-RESETTING CURRENT LIMITER

EATON INTELLIGENT POWER L...

1. A self-resetting current limiter, comprising:a first connecting contact configured to bring the current limiter into contact with a first electrical conductor;
a second connecting contact configured to bring the current limiter into contact with a second electrical conductor;
a first movable contact member;
a second movable contact member; and
a first compression spring and a second compression spring,
wherein the first and the second movable contact members are electrically interconnected in a first position of the first and the second movable contact member, such that a current path between the first and the second connecting contact is closed, and
wherein the first and the second movable contact members are separated from one another in a second position of the first and the second movable contact member, such that the current path between the first and the second connecting contact is interrupted,
wherein, when a short-circuit current occurs between the first and the second connecting contacts, a force caused by the short-circuit current acts on the first movable contact member and a force caused by the short-circuit current acts on the second movable contact member, by which forces the first and the second movable contact members are spun into the second position,
wherein the first compression spring is configured to exert, on the first movable contact member, a counter force with respect to the force caused by the short-circuit current when the first movable contact member is spun,
wherein the second compression spring is configured to exert, on the second movable contact member, a counter force with respect to the force caused by the short-circuit current when the second movable contact member is spun,
wherein the first movable contact member has a first arm comprising a support element configured to support the first compression spring on the first arm of the first movable contact member,
wherein the first arm of the first movable contact member extends from the support element of the first arm of the first movable contact member to a rotary shaft of the first movable contact member,
wherein the second movable contact member has a first arm comprising a support element configured to support the second compression spring on the first arm of the second movable contact member,
wherein the first arm of the second movable contact member extends from the support element of the second movable contact member to a rotary shaft of the second movable contact member,
wherein the first movable contact member has a second arm, which extends from the rotary shaft of the first movable contact member,
wherein the second arm of the first movable contact member is not arranged in an extension of a direction of the first arm of the first movable contact member,
wherein the second movable contact member has a second arm, which extends from the rotary shaft of the second movable contact member, and
wherein the second arm of the second movable contact member is not arranged in an extension of a direction of the first arm of the second movable contact member.

US Pat. No. 10,770,254

PLUG-ON NEUTRAL CONNECTOR FOR USE WITH A FAULT CIRCUIT INTERRUPT CIRCUIT BREAKER

ABB Schweiz AG, Baden (C...

1. A plug-on neutral connector comprising:a neutral terminal plug arranged to be inserted into a neutral terminal of a circuit breaker;
a conductive fastener electrically coupled to said neutral terminal plug and arranged to be fastened on a neutral bus bar of a load center, said conductive fastener comprising a first pass-through; and
a housing disposed over at least a portion of said conductive fastener, said housing comprising a second pass-through disposed in alignment with said first pass-through.

US Pat. No. 10,770,253

SWITCH ARRANGEMENTS FOR MICROELECTROMECHANICAL SYSTEMS

Qorvo US, Inc., Greensbo...

1. A microelectromechanical system (MEMS) switch device comprising:a first MEMS switch configured to receive a first MEMS switch control signal;
a plurality of second MEMs switches configured to receive a second MEMS switch control signal that is different than the first MEMS switch control signal, wherein the first MEMS switch and the plurality of second MEMS switches are arranged in parallel with each other; and
control circuitry configured to provide the first MEMS switch control signal and the second MEMS switch control signal.

US Pat. No. 10,770,251

ALTERNATING CURRENT CONTACTOR

ZHEJIANG CHINT ELECTRICS ...

1. An alternating current contactor, comprising a base and a magnetic yoke, wherein the magnetic yoke is mounted on a bottom plate of the base, and a magnetic yoke support for supporting and buffering the magnetic yoke is respectively provided at two sides of the magnetic yoke, wherein the sidewalls at two sides of each magnetic yoke support, which are connected with the magnetic yoke are different in thickness.

US Pat. No. 10,770,250

FLOAT ASSEMBLY

1. A float operated electric switch actuating mechanism comprising;an electric switch;
a float;
a frame limiting the displacement of a rod to a vertical dimension, wherein said float slides along the length of said rod in response to the fluid level, said rod having a cross beam mechanically connected to said electric switch so that said cross beam movement activates/deactivates said switch as said rod moves;
wherein said cross beam's pivot point is mechanically linked to said frame at a near end, said cross beam makes contact with said switch at a point between said near end and said mechanical connection to said rod and said cross beam further extends to form said beam's distal end;
an adjustable upper limit nut located along the upper portion of said rod; and
an adjustable lower limit nut located along the lower portion of said rod.

US Pat. No. 10,770,249

POLE PART FOR A LOW-, MEDIUM OR HIGH VOLTAGE CIRCUIT BREAKER, AND METHOD FOR MANUFACTURING THE SAME

ABB SCHWEIZ AG, Baden (C...

1. A pole part for a medium or high voltage circuit breaker, comprising:an insulating housing;
a vacuum interrupter; and
a compensation layer,
wherein the vacuum interrupter is in the insulating housing,
wherein the compensation layer is in contact with a surface of the vacuum interrupter,
wherein the compensation layer is between the vacuum interrupter and the insulating housing, and
wherein the compensation layer comprises an epoxy based potting material with a shore hardness of 12 to 90 shore A.

US Pat. No. 10,770,248

MOLDED CASE CIRCUIT BREAKER

LSIS CO., LTD., Anyang-S...

1. A molded case circuit breaker, comprising:a fixed contact;
a movable contact configured to be brought into contact with or separated from the fixed contact;
an insulating barrier configured to enter between the fixed contact and the movable contact during interruption, wherein the insulating barrier comprises a free end portion and is formed of a flexible material, and
a guide portion protruded on part of a base mold and configured to guide the free end portion of the insulating barrier,
wherein the insulating barrier is coupled to the movable contact to rotate along a circumferential surface of a shaft body,
wherein the guide portion comprises a pair of protrusion portions spaced apart from each other,
wherein when an external force does not act on the insulating barrier, the insulating barrier is configured to maintain a shape of surrounding the circumferential surface of the shaft body, and be bent by being brought into contact with the guide portion, and
wherein when the movable contact is connected to the fixed contact, the free end portion of the insulating barrier is configured to be lifted up from the shaft body by the guide portion.

US Pat. No. 10,770,247

VARISTOR TYPE MULTI-DIRECTIONAL INPUT DEVICE

Dongguan City Kaihua Elec...

1. A varistor type multi-directional input device, comprising a base,an upper cover, wherein an opening is provided on an upper surface of the upper cover, and the upper cover is disposed on the base to form a central cavity;
a rocker assembly, wherein the rocker assembly is mounted in the central cavity, comprising a rocking bar, an upper rocker arm, and a lower rocker arm; the upper rocker arm and the lower rocker arm are arranged in an upper and lower cross; the upper rocker arm is in a shape of an arch, the upper rocker arm comprises a first convex portion formed by a central upward convex, a first shaft end and a second shaft end disposed at two sides of the first convex portion, and a first through hole at a center of the first convex portion; the lower rocker arm comprises a second convex portion formed by a central upward convex, a third shaft end and a fourth shaft end disposed at two sides of the second convex portion, and a second through hole at a center of the second convex portion; the upper rocker arm and the lower rocker arm are respectively provided with an eccentric wheel; the rocking bar comprises an upper end, and a lower end, the lower end is riveted with the lower rocker arm, protrudes from the second through hole of the lower rocker arm and passes through the first through hole of the upper rocker arm, extends to pass through the opening of the upper cover, and the eccentric wheels of the upper rocker arm and the lower rocker arm are driven by the rocking bar to swing;
a reset assembly, wherein the reset assembly is mounted under the rocker assembly for resetting the rocker assembly after the rocker assembly is pressed;
an electrical component, wherein the electrical component controls a change in resistance, and is configured for converting a motion signal of the rocker assembly into an electrical signal; the electrical component comprises a varistor, an on-off switch; the on-off switch comprises a switch guide core and a conductive elastic piece; and
a terminal assembly configured to output the electrical signal, comprising a varistor terminal and a switch terminal, wherein the varistor terminal is mounted on an outside of the varistor, and the switch terminal is mounted on an outside of the switch guide core; the switch guide core is pressed by the eccentric wheels of the upper rocker arm or the lower rocker arm when the rocking bar is pressed, to connect and disconnect the conductive elastic piece and the switch terminal.

US Pat. No. 10,770,246

KEYBOARD COVERING FILM, WATERPROOF KEYBOARD, METHOD FOR FABRICATING KEYBOARD COVERING FILM, WATERPROOF KEYCAP ASSEMBLY, AND ILLUMINATING KEYBOARD

DARFON ELECTRONICS CORP.,...

1. A keyboard covering film, comprising:a transparent layer;
a fabric layer disposed on a lower surface of the transparent layer; and
a mask layer disposed on a lower surface of the fabric layer;
wherein the transparent layer and the fabric layer are treated by a hot pressing process to form a plurality of hollow keycap receiving sections;
wherein within each of the keycap receiving sections, portion of the fabric layer and the mask layer are removed to form a hollow pattern, so that a light can penetrate each hollow keycap receiving section by passing through the hollow pattern and the transparent layer, wherein the transparent layer has a plurality of press portions, an upper surface of each of the press portions is flat, and each press portion is disposed above a corresponding one of the keycaps and covers a corresponding one of the hollow patterns.

US Pat. No. 10,770,245

CONTACT STRUCTURE FOR SWITCH, TRIGGER SWITCH AND ELECTRIC POWER TOOL

Omron Corporation, Kyoto...

1. A switch contact structure comprising:an operation section;
a first movable contact member, the first movable contact member including an elastic member; and
a first counter contact member configured to face the first movable contact member,
wherein the operation section is configured such that:
in a case where an amount of movement of the operation section reaches a first movement amount, the first movable contact member coming into contact with the first counter contact member due to a spring force applied to the first movable contact member, and
in a case where the amount of movement of the operation section reaches a second movement amount which is larger than the first movement amount, the operation section comes into contact with the elastic member, the operation section pressing the first movable contact member so as to cause the elastic member to elastically deform, and the operation section pressing the first movable contact member against the first counter contact member.

US Pat. No. 10,770,244

CONTROL MODULAR ASSEMBLY AND SWITCH INCLUDING THE SAME

Schneider Electric (Austr...

1. A control modular assembly for a switch, wherein the control modular assembly comprises:a driving mechanism comprising an output shaft;
a control unit coupled to the driving mechanism and configured to receive and process a signal for controlling the switch so as to control a movement of the output shaft of the driving mechanism; and
an operating member coupled to the output shaft;
wherein the control modular assembly is detachably coupled to an internal functional assembly of the switch, so that the operating member can be driven by the output shaft to move within a given movement range in response to the signal for controlling the switch, such that the operating state of the switch is controlled by controlling the internal functional assembly;
wherein the control modular assembly further comprises a transmission mechanism, the transmission mechanism comprises a driving element and a driven element engaged with each other, and wherein the driving element is coupled to and driven by the output shaft, the driven element is coupled to the operating member to drive the operating member to move within a given movement range;
wherein the driving element and the driven element are gears, and wherein the driven element is integrated with the operating member, and wherein a rotation axis of the driven element coincides with a rotation axis of the operating member; and
wherein the operating member comprises two contact arms, the two contact arms are provided with at least one protrusion on opposite inner surfaces.

US Pat. No. 10,770,243

PUSH-BUTTON SWITCH WITH GOOD BALANCE

DONGGUAN CITY KAIHUA ELEC...

1. A push-button switch with good balance, comprising: a base and a cover covering the base; wherein the cover is provided with an orifice; the push-button switch further comprises a press core, a torsion spring, a conductive assembly and a press core slider, which are respectively arranged on the base; a guide pillar is protruded upwardly from a center of an upper end of the base; a guide hole is formed in a center of the guide pillar; one end of the base is provided with a conductive assembly slot configured to accommodate the conductive assembly, an other end of the base is provided with a torsion spring slot configured to accommodate the torsion spring; two baffles are arranged on the upper end of the base and at each of opposite sides of the guide pillar, a gap is provided between the two baffles, such that an annular receiving slot is formed around the two baffles and the guide pillar; the press core slider is arranged at a side of the press core; an annular slot is formed at a lower end of the press core; a cylinder is protruded downward from a center position of the annular slot; the cylinder is inserted into the guide hole of the base, and the guide pillar of the base is inserted into the annular slot; the guide pillar and an outer side of the cylinder are sleeved with a spring; a balance rod assembly is arranged in the annular receiving slot; the balance rod assembly is split-type and formed by a first balance rod and a second balance rod cross-connected with each other; the first balance rod and the second balance rod are both clamped at the lower end of the press core; two crossing junctions of the first balance rod and the second balance rod are limited by a positioning slider arranged in the annular receiving slot and in the gap between the two baffles at a same side; a side edge of the positioning slider is provided with a limiting slot for clamping the first balance rod and the second balance rod; during a movement of the press core up and down, the first balance rod and the second balance rod swing up and down under a limit of the positioning slider, thereby keeping a press balance.

US Pat. No. 10,770,242

BUTTON ASSEMBLY FOR A PORTABLE COMMUNICATION DEVICE

MOTOROLA SOLUTIONS, INC.,...

1. A push-to-talk assembly for a portable communication device, the push-to-talk assembly comprising:a metal ring defining an interior aperture and including at least one exterior protrusion configured to couple the metal ring to a surface of the portable communication device;
a button coupled to the metal ring and including a flexible polymer material disposed within the interior aperture and co-molded to the metal ring, the button including a first side configured to be contacted and pressed, and a second, opposite side configured to face an interior of the portable communication device;
a metal backing plate coupled to the second side of the button, and
a reinforcement metal plate configured to be coupled to a printed circuit board within the portable communication device.

US Pat. No. 10,770,241

HIGH SPEED ARC SUPPRESSOR

Arc Suppression Technolog...

1. A high speed arc suppressor configured to suppress arcing across a power contactor coupled to an alternating current (AC) power source, the high speed arc suppressor comprising:a first phase-specific arc suppressor configured to suppress arcing across contacts of the power contactor in a positive domain, comprising:
a first high speed switch configured to enable or disable operation of the first phase-specific arc suppressor; and
a first driver, coupled to the first high speed switch, configured to cause the first high speed switch to enable operation of the first phase-specific arc suppressor when an input signal from the contacts is in the positive domain and disable operation of the first phase-specific are suppressor when the input signal from the contacts is in a negative domain; and
a second phase-specific arc suppressor configured to suppress arcing across the contacts in a negative domain, comprising:
a second high speed switch configured to enable or disable operation of the second phase-specific arc suppressor; and
a second driver, coupled to the second high speed switch, configured to cause the second high speed switch to enable operation of the first phase-specific arc suppressor when an input signal from the contacts is in the negative domain and disable operation of the first phase-specific arc suppressor when the input signal from the contacts is in the positive domain;
wherein the first and second high speed switches are configured to switch the first and second phase-specific arc suppressors between the enable operation and the disable operation in not more than ten (10) microseconds;
wherein the first and second high speed switches are insulated gate bipolar transistors (IGBT); and
wherein each of the first and second phase-specific arc suppressors further comprises:
an arc ignition detector circuit;
a trigger lock circuit; and
an arc burn memory.

US Pat. No. 10,770,239

HIGH-EFFICIENCY AND DURABLE OPTOELECTRONIC DEVICES USING LAYERED 2D PEROVSKITES

TRIAD NATIONAL SECURITY, ...

1. A thin film for an optoelectronic device, the thin film comprising a layered 2D perovskite material comprising two or more inorganic perovskite layers, the thin film comprising the layered 2D perovskite material comprising a substantially single-crystalline uniform thin film,the layered 2D perovskite material being represented by (BA)2(MA)n?1PbnI3n+1, wherein BA is an n-butyl ammonium cation and MA is a methyl ammonium cation.

US Pat. No. 10,770,238

SOLID ELECTROLYTIC CAPACITOR ASSEMBLY WITH HYDROPHOBIC COATINGS

AVX Corporation, Fountai...

1. A capacitor assembly comprising:a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric that overlies the anode body, and a solid electrolyte that overlies the dielectric;
a casing material that encapsulates the capacitor element, wherein the casing material has an outer surface that forms an outermost surface of the capacitor element;
an anode termination that is in electrical connection with the anode body and contains a portion that is positioned external to the casing material, wherein a first hydrophobic coating is disposed in contact with the outer surface of the casing material and the external portion of the anode termination; and
a cathode termination that is in electrical connection with the solid electrolyte and contains a portion that is positioned external to the casing material, wherein a second hydrophobic coating is disposed in contact with the outer surface of the casing material and the external portion of the cathode termination,
wherein the first hydrophobic coating is separate from the second hydrophobic coating.

US Pat. No. 10,770,236

MULTILAYER CERAMIC ELECTRONIC COMPONENT ARRAY

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component array comprising:a plurality of multilayer ceramic electronic components each including a ceramic body including a dielectric layer and first and second internal electrodes stacked with the dielectric layer interposed therebetween, the first and second internal electrodes being alternately exposed to first and second outer surfaces, respectively, and first and second external electrodes disposed on the first and second outer surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively;
a first terminal structure electrically connected to first external electrodes of the plurality of multilayer ceramic electronic components;
a second terminal structure electrically connected to second external electrodes of the plurality of multilayer ceramic electronic components;
a first conductive bonding member bonding the first external electrodes of the plurality of multilayer ceramic electronic components and the first terminal structure;
a second conductive bonding member bonding the second external electrodes of the plurality of multilayer ceramic electronic components and the second terminal structure; and
a first ceramic bonding member contacting first surfaces of ceramic bodies of the plurality of multilayer ceramic electronic components and extending onto second surfaces of the ceramic bodies.

US Pat. No. 10,770,235

MULTILAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body including an active region including a plurality of dielectric layers and a plurality of internal electrodes stacked with each of the dielectric layers interposed therebetween, having first and second surfaces opposing each other, and having third and fourth surfaces connected to the first and second surfaces and opposing each other, wherein one end of each internal electrode of the plurality of stacked internal electrodes is exposed through an alternating one of the third and fourth surfaces; and
first and second external electrodes disposed, respectively, on the third and fourth surfaces of the capacitor body, and connected, respectively, to the internal electrodes exposed through the third and fourth surfaces of the capacitor body,
wherein the active region includes a first active region adjacent to the second surface of the capacitor body and a second active region adjacent to the first surface of the capacitor body, the first surface of the capacitor body being a mounting surface of the capacitor body,
an area of overlap between adjacent internal electrodes in the second active region is smaller than an area of overlap between adjacent internal electrodes in the first active region,
a deviation between areas of overlap between the adjacent internal electrodes in the first active region is 5% or less, and a deviation between areas of overlap between the adjacent internal electrodes in the second active region is 5% or less, and
the multilayer capacitor further includes a plurality of dummy electrodes each co-planar with a corresponding one of the internal electrodes in the second active region and spaced apart from the corresponding one of the internal electrodes and from the third and fourth surfaces, and both the dummy electrodes and the internal electrodes in the second active region overlap each of the internal electrodes in the first active region in a thickness direction.

US Pat. No. 10,770,233

MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor comprising:a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked in a thickness direction and a margin portion disposed on outer surfaces of the active portion; and
external electrodes disposed on outer surfaces of the ceramic body,
wherein the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to an edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half, and the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less,
in margin portions disposed on upper and lower surfaces of the active portion in the thickness direction, average sizes of dielectric grains of the inner half and the outer half are different from each other, and
the inner half of the margin portion covering upper, lower and side surfaces of the active portion is made of a same composition.

US Pat. No. 10,770,232

MULTILAYER ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a capacitor body including first and second surfaces facing each other, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and facing each other, and including a plurality of dielectric layers, and first and second internal electrodes, alternately disposed across the dielectric layers to expose one end of the first and second internal electrodes through the third and fourth surfaces;
a first conductive layer and a second conductive layer disposed on the third and fourth surfaces of the capacitor body and connected to the first and second internal electrodes, respectively;
a first plating layer and a second plating layer covering surfaces of the first and second conductive layers; and
a plurality of coating layers configured in a multilayer structure on a surface of the capacitor body to expose the first and second plating layers and having an entire thickness of 10 nm to 200 nm,
wherein the plurality of coating layers is arranged and configured such that at least a portion of the surface of the capacitor body is exposed to an outside of the capacitor body through at least one gap between adjacent portions of the plurality of coating layers.

US Pat. No. 10,770,231

MULTILAYER CERAMIC ELECTRONIC COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic electronic component comprising:a component body of roughly rectangular solid shape having a dielectric body in which internal conductor layers are embedded, and a pair of external electrodes provided on the component body and also connected to the internal conductor layers, wherein:
when, of the six faces of the component body, a direction in which a first pair of faces are opposing each other is given as a first direction, a direction in which a second pair of faces are opposing each other is given as a second direction, and a direction in which a third pair of faces are opposing each other is given as a third direction,
each of the external electrodes is constituted by a base part present on one first-direction face of the component body, and a first part, continuously from the base part, present at least on one third-direction face, among the one third-direction face, the other third-direction face, one second-direction face, and the other second-direction face, of the component body; and
a group of metal protrusions is provided along the first direction of the component body only over the one third-direction face and/or the other third-direction face, both of which are dielectric, of the component body, in a manner separating the respective metal protrusions from each other on a dielectric surface of the other third-direction face so that no electrical current flows through the group of metal protrusions, whereby dispersing heat through the protrusions.

US Pat. No. 10,770,230

MULTILAYER CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor comprising: a body including a dielectric layer and first and second internal electrodes; and external electrodes disposed on at least one surface of the body, wherein the external electrodes each include: an electrode layer in contact with the first or second internal electrode; an intermediate layer disposed on the electrode layer and including a first intermetallic compound; and a conductive resin layer disposed on the intermediate layer and contacting only the intermediate layer, from among the electrode and intermediate layers, and including a plurality of metal particles, a second intermetallic compound fully enclosing at least one metal particle of the plurality of metal particles, and a base resin.

US Pat. No. 10,770,229

DIELECTRIC COMPOSITION AND ELECTRONIC COMPONENT CONTAINING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A dielectric composition comprising:a base material powder containing BamTiO3 (0.995?m?1.010);
a first accessory ingredient containing at least one element corresponding to a transition metal in Group 5 of the periodic table in a total content of 0.3 to 1.2 moles, based on 100 moles of the base material powder;
a second accessory ingredient containing at least one of ions, oxides, carbides, and hydrates of Si in a total content of 0.6 to 4.5 moles, based on 100 moles of the base material powder;
a third accessory ingredient, distinct from the second accessory ingredient, containing at least one element in Period 4 or higher; and
a fourth accessory ingredient containing at least one element in Period 3,
wherein 0.70×B?C+D?1.50×B and 0.20?D/(C+D)?0.80, in which B is a total content of the second accessory ingredient, C is a total content of the third accessory ingredient, and D is a total content of the fourth accessory ingredient.

US Pat. No. 10,770,228

CAPACITOR INCLUDING ELECTRODES HAVING COMPLEMENTARY PATTERN FORMED IN HORIZONTAL DIRECTION

LG Chem, Ltd., Seoul (KR...

1. A capacitor comprising:an electrode assembly comprising at least one positive electrode, at least one negative electrode, and at least one dielectric interposed between the positive electrode and the negative electrode; and
a case for receiving the electrode assembly,
wherein each positive electrode and each negative electrode has an L-shape with one straight portion in a horizontal direction and another straight portion in a width direction perpendicular to the horizontal direction, the horizontal and the width directions being perpendicular to a thickness direction of the electrode assembly,
wherein one positive electrode and one negative electrode constitute a basic unit, and
wherein the positive electrode and the negative electrode of each basic unit are arranged to have a complementary pattern such that each basic unit has a rectangular shape in a plan view with respect to the thickness direction.

US Pat. No. 10,770,227

CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor, comprising:a body including dielectric layers and internal electrodes; and
external electrodes disposed on the body,
wherein the capacitor includes Sn, the Sn having an alpha particle emission rate equal to or less than 0.02 cph/cm2.

US Pat. No. 10,770,226

COMPOSITE ELECTRONIC COMPONENT, METHOD OF MANUFACTURING THE SAME, BOARD FOR MOUNTING THEREOF, AND PACKAGING UNIT THEREOF

SAMSUNG ELECTRO-MECHANICS...

1. A composite electronic component comprising:a composite body including a capacitor and an electrostatic discharge (ESD) protection device coupled to each other, the capacitor including a ceramic body in which a plurality of dielectric layers and internal electrodes are stacked in a thickness direction on with a respective dielectric layer interposed between the internal electrodes, and the ESD protection device including first and second electrodes disposed on the ceramic body, a discharging part disposed between the first and second electrodes, and a protective layer disposed on the first and second electrodes and the discharging part to substantially cover the entirety of upper surfaces of the first and second electrodes and the discharging part;
an input terminal disposed on a first end surface of the composite body, partially disposed on a surface of the protective layer in the thickness direction, and connected to internal electrodes of the capacitor and the first electrode; and
a ground terminal disposed on a second end surface of the composite body, partially disposed on a surface of the protective layer in the thickness direction, and connected to internal electrodes of the capacitor and the second electrode, the second end surface opposing the first end surface in a length direction of the ceramic body,
wherein the protective layer extends from at least one of the first end surface or the second end surface of the ceramic body, and
wherein a dimension of the ceramic body in the length direction is longer than a dimension of the ceramic body in a width direction.

US Pat. No. 10,770,225

MULTILAYERED COILS

Hamilton Sundstrand Corpo...

1. An electrical coil comprising:a stack of coil layers, wherein at least two of the coil layers each include:
a layer substrate with an electrically conductive coil pattern thereon, wherein each coil pattern includes an inner end at a first via through the substrate at a point inside the coil pattern, and an outer end at a second via through the substrate at a point outside the coil pattern;
wherein each of the coil layers is joined to the stack with successive coil patterns connected to one another through the vias to form a conductive coil extending through the stack,
wherein each successive pair of inner vias are joined to one another at a respective inner via location that is varied from pair to pair in the stack of coil layers so no two pairs of coil layers are short circuited to one another through the vias.

US Pat. No. 10,770,224

METHOD FOR FORMING ELECTROLYTIC COPPER PLATING FILM ON SURFACE OF RARE EARTH METAL-BASED PERMANENT MAGNET

HITACHI METALS, LTD., To...

1. A method for forming an electrolytic copper plating film on the surface of a rare earth metal-based permanent magnet, comprising the steps of:immersing the rare earth metal-based permanent magnet in a plating solution containing Cu2+ ions,
applying an increasing cathode current density in a range of 0.05 A/dm2 to 4.0 A/dm2 to the rare earth metal-based permanent magnet over 10 seconds to 180 seconds, wherein a cathode current density increase rate for applying the increasing cathode current density is 0.002 A/(dm2×sec) to 0.4 A/(dm2×sec), until a predetermined value of current density is reached, and then
performing an electrolytic copper plating treatment at the predetermined value of current density.

US Pat. No. 10,770,223

HIGH FREQUENCY COMPONENT

MURATA MANUFACTURING CO.,...

1. A high frequency component comprising:a ceramic substrate;
a ground electrode disposed inside the ceramic substrate;
a shield film covering at least a lateral surface among surfaces of the ceramic substrate; and
a connecting portion connecting the ground electrode and the shield film to each other,
wherein a weight ratio of a metal ingredient in the connecting portion is higher than a weight ratio of a metal ingredient in the ground electrode,
the connecting portion is disposed inside of the shield film.

US Pat. No. 10,770,222

MULTILAYER ELECTRONIC COMPONENT

TDK CORPORATION, Tokyo (...

1. A multilayer electronic component comprising:a multilayer stack including a plurality of dielectric layers and a plurality of conductor layers stacked together;
a plurality of terminals integrated with the multilayer stack; and
a shield formed of a conductor and integrated with the multilayer stack, wherein
the multilayer stack has a top surface and a bottom surface located at opposite ends in a first direction, and four side surfaces connecting the top surface and the bottom surface,
the plurality of terminals are provided on the bottom surface of the multilayer stack,
the shield entirely covers the top surface and the four side surfaces of the multilayer stack, and
the shield includes a portion thicker than the other portions of the shield.

US Pat. No. 10,770,221

COIL COMPONENT HAVING TERMINAL ELECTRODES WITH HIGH MOUNTING STRENGTH, AND ELECTRONIC DEVICE INCLUDING THE COIL COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising an air-core coil embedded in a magnetic body constituted by resin and metal magnetic grains, and having terminal electrodes electrically connected to both ends of the coil, wherein:both ends of the coil are exposed on a surface of the magnetic body;
the terminal electrodes are formed across the surface of the magnetic body and ends of the coil, and constituted by an underlying layer formed with metal material and a cover layer placed on an outer side of the underlying layer; and
the underlying layer is in contact with the resin and metal parts of the metal magnetic grains along an interface between the underlying layer and the magnetic body,
wherein the interface has resin-contacting areas where the underlying layer is in contact with the resin, and metal-contacting areas where the underlying layer is in contact with the metal parts of the metal magnetic gains, wherein the resin-contacting areas are concave toward the magnetic body with respect to the metal-contacting areas.

US Pat. No. 10,770,220

PLANAR TRANSFORMER LAYER, ASSEMBLY OF LAYERS FOR PLANAR TRANSFORMER, AND PLANAR TRANSFORMER

THALES, Courbevoie (FR)

1. An assembly of layers comprising a plurality of primary planar transformer layer turns of windings, each of the primary planar transformer layer turns of windings comprising distinct electrical connections and thermal connections having a hole in primary layers, the hole with an extension towards an interior of the layer based on a top view to locally maximize the heat flux towards a heat sink, wherein the extension is narrower than the hole.

US Pat. No. 10,770,219

COIL COMPONENT

TDK CORPORATION, Tokyo (...

1. A coil component comprising:a drum core having a winding core part and first and second flange parts provided on both sides of the winding core part;
a wire wound around the winding core part;
a plurality of terminal electrodes connected with end portions of the wire, each of the terminal electrodes being provided on an associated one of the first and second flange parts; and
a top plate fixed to the first and second flange parts,
wherein the top plate includes:
a magnetic layer comprising magnetic powder and binder resin; and
a resin layer having a smaller content of the magnetic powder than that of the magnetic layer, and
wherein the resin layer is positioned between the first and second flange parts and the magnetic layer,
wherein the magnetic layer of the top plate has a lower surface facing the resin layer and an upper surface positioned on an opposite side to the lower surface, and
wherein a density of the binder resin is higher at a surface layer part on the upper surface side than at a surface layer part on the lower surface side.

US Pat. No. 10,770,218

REACTOR, MOTOR DRIVER, POWER CONDITIONER AND MACHINE

Fanuc Corporation, Yaman...

1. A reactor comprising:an outer peripheral iron core;
at least three iron-core coils contacting or connected to an inner surface of the outer peripheral iron core,
wherein each of the iron-core coils includes iron cores and coils wound onto the iron cores, wherein a radial inner end portion of each of the iron cores converges towards a center of the outer peripheral iron core;
gaps that can magnetically connect one iron-core coil of the at least three iron-core coils and an iron-core coil adjacent to the one iron-core coil to each other are formed between the one iron-core coil of the at least three iron-core coils and the iron-core coil adjacent to the one iron-core coil, wherein the radial inner end portion of the iron core of the one iron-core coil is separated from the radial inner end portions of each adjacent iron core by the gaps;
wherein each of the iron cores extends only in a radial direction of the outer peripheral iron core; and
an external cooling unit is disposed circumferentially outside the outer peripheral iron core, for cooling the outer peripheral iron core.

US Pat. No. 10,770,217

MOUNTING KIT FOR A THROTTLE, AND THROTTLE

1. Mounting kit for a throttle with a toroidal core, wherein an insulating element passes through an opening in the toroidal core, comprising:a first half shell and a second half shell for accommodating the toroidal core;
a baseplate; and
a latching means and guide means, extending from the baseplate into the opening in the toroidal core, that connects and relatively aligns the first half shell, the second half shell, the insulating element and the baseplate to one another from within an inner radius of the toroidal core,
wherein the second latching means and/or guide means have at least three projections which emerge from the baseplate and at the free ends of which latching lugs are arranged.

US Pat. No. 10,770,216

REACTOR

Fanuc Corporation, Yaman...

1. A reactor comprising:an outer peripheral iron core;
at least three core coils contacting or connected to an inner surface of the outer peripheral iron core;
each of the core coils including a core and a coil wound onto the core; and
an attachment unit disposed on one end surface of the outer peripheral iron core, for attaching the outer peripheral iron core in a predetermined position, the attachment unit including an end plate and a plurality of extension portions cantilevered to the end plate, each of the plurality of extension portions having a respective base abutting the end plate, the plurality of extension portions each extending in a perpendicular direction from the base to a respective distal end, each respective distal end of the plurality of extension portions abutting the end surface of the outer peripheral iron core at separate respective locations, the plurality of extension portions spaced apart from each other on the end plate to form ventilation ports between the end surface of the outer peripheral iron core and the end plate,
wherein the outer peripheral iron core has a plurality of holes extending in an axial direction, and each of the plurality of extension portions has a respective hole extending in the axial direction from each respective distal end of the plurality of extension portions, and
wherein the holes of the outer peripheral iron core and the holes of the extension portions are aligned, such that the attachment unit and the outer peripheral iron core are connected with screws extending through the holes of the outer peripheral iron core and the holes of the extension portions.

US Pat. No. 10,770,215

ELECTRONIC COMPONENT, DIAPHRAGM, ELECTRONIC DEVICE, AND ELECTRONIC COMPONENT MANUFACTURING METHOD

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:an insulating base material substrate including a first main surface defining a mounting surface, the insulating base material substrate including a plurality of insulating base material layers that are laminated in a lamination direction;
a coil including a coil conductor provided on at least one of the plurality of insulating base material layers and including a winding axis extending in the lamination direction; and
a mounting electrode that is provided on the first main surface and connected to the coil; wherein
an area of the first main surface is smaller than an area of a section, which is different in area from the first main surface and is closest to the first main surface, among sections parallel or substantially parallel to the first main surface; and
an entirety or substantially an entirety of the first main surface is disposed inside a section having the largest area among the sections parallel or substantially parallel to the first main surface when viewed from the lamination direction.

US Pat. No. 10,770,213

MAGNETORESISTIVE DEVICE COMPRISING CHROMIUM

IMEC vzw, Leuven (BE)

1. A magnetoresistive device, comprising:a magnetic tunnel junction (MTJ) structure formed over a substrate, the MTJ structure comprising, in a bottom-up direction away from the substrate, a free layer, a tunnel barrier layer and a reference layer;
a pinning layer formed of a material comprising chromium (Cr) and formed above the reference layer, wherein the pinning layer pins a magnetization direction of the reference layer; and
a capping layer comprising Cr formed above the pinning layer, wherein a concentration profile of Cr in the pinning layer is a diffusion profile resulting from diffusion of Cr from the capping layer as a source of Cr into the pinning layer, wherein the diffusion profile extends from the capping layer.

US Pat. No. 10,770,212

DETERMINING ARMATURE STROKE BY MEASURING MAGNETIC HYSTERESIS CURVES

Robert Bosch GmbH, Stutt...

1. A method for ascertaining a hysteresis curve of an electromagnetically actuatable valve (1) made of an electromagnet (2, 2a, 2b), an armature (3) that is movable by way of the electromagnet (2, 2a, 2b), and a valve body (5) with means (4, 4a, 4b, 4c) for converting a movement of the armature (3) into opening or closing of the valve (1), wherein the electromagnet (2, 2a, 2b) and the armature (3) are inserted into the valve body (5), the method comprising recording a magnetic hysteresis curve (10) of a combination (6) of the electromagnet (2, 2a, 2b) with a test armature (3a) contacting said electromagnet (2, 2a, 2b) prior to inserting the electromagnet (2, 2a, 2b) into the valve body (5), ascertaining the slope m1 of a first, substantially linear curve portion (11) of the hysteresis curve (10) in an unsaturated state, and ascertaining, from the slope m1, the slope m1* of a curve portion (31), corresponding to the first curve portion (11), of a hysteresis curve (30) of the fully assembled valve (1) with an armature (3) permanently in contact with the electromagnet (2, 2a, 2b).

US Pat. No. 10,770,209

SOFT MAGNETIC POWDER, MAGNETIC CORE, METHOD FOR MANUFACTURING SOFT MAGNETIC POWDER, AND METHOD FOR MANUFACTURING MAGNETIC CORE

AutoNetworks Technologies...

1. A magnetic core constituted by a composite material containing soft magnetic powder and resin,wherein the soft magnetic powder is constituted by an Fe alloy containing Si, wherein soft magnetic particles of the soft magnetic powder include a SiO2 layer formed on a surface of the particles, and a surface layer formed directly on the SiO2 layer, the surface layer includes a first material that constitutes a matrix and a second material that is dispersed in the matrix, and the first material is silicone or phosphate, and the second material is silicone or phosphate and is different from the first material;
wherein a volume percentage of the soft magnetic powder in the composite material is 50% or more and 85% or less, and
Bs/?m is 0.056 or more, where Bs is a saturation flux density of the composite material and ?m is a maximum magnetic permeability.

US Pat. No. 10,770,207

RARE-EARTH PERMANENT MAGNET AND METHOD FOR MANUFACTURING RARE-EARTH PERMANENT MAGNET

NITTO DENKO CORPORATION, ...

1. A manufacturing method of a rare-earth permanent magnet comprising, in order, steps of:milling magnet material into magnet powder;
mixing the magnet powder with a binder to obtain a mixture;
forming the mixture into a formed body;
calcining the formed body in a non-oxidizing atmosphere, wherein the calcining comprises a calcination process during which the formed body is held at a temperature in a range of 200 degrees Celsius to 900 degrees Celsius and the on-oxidizing atmosphere is pressurized at 0.5 MPa or higher so that a residual oxygen content contained in the formed body after sintering is 5000 ppm or less; and
holding the calcined formed body at a sintering temperature so as to sinter the calcined formed body,
wherein the binder consists of a resin that is made of a polymer or a copolymer consisting essentially of one or more kinds of monomers expressed with a general formula (1):

wherein R1 and R2 represent a hydrogen atom, a lower alkyl group, a phenyl group or a vinyl group, and
wherein the calcination process has a duration of several hours.

US Pat. No. 10,770,206

SYSTEM AND METHOD FOR FABRICATING A STRAIN SENSING DEVICE DIRECTLY ON A STRUCTURE

1. A method for fabricating a strain sensing device directly on a structure, the method comprising:printing a material on the structure, the material exhibiting a piezo-resistive effect;
sintering a strain sensing pattern from the material such that the strain sensing pattern becomes electrically conductive; and
attaching a pin connector to the electrically conductive strain sensing pattern.

US Pat. No. 10,770,205

METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. A method for manufacturing an electronic component comprising the steps of:preparing an element assembly in which inner electrodes are embedded and including a pair of main surfaces, a pair of side surfaces respectively connecting the main surfaces, and a pair of end surfaces respectively perpendicular or substantially perpendicular to the pair of main surfaces and the pair of side surfaces; and
providing an outer electrode on the element assembly so that the outer electrode is electrically connected with the inner electrodes; wherein
the step of providing the outer electrode includes a step of providing a sintered layer including a sintered metal, a step of providing an insulation layer including an electric insulation material, and a step of providing a Sn-containing layer including Sn;
in the step of providing the sintered layer, the sintered layer extends from each of the pair of end surfaces onto at least one of the pair of main surfaces so as to cover each of the pair of end surfaces;
in the step of providing the insulation layer, the insulation layer is directly provided on the sintered layer at each of the pair of end surfaces to extend in a direction perpendicular or substantially perpendicular to the pair of side surfaces so as to constitute a portion of a surface of the outer electrode; and
in the step of providing the Sn-containing layer, the Sn-containing layer is provided to cover the sintered layer except for a portion of the sintered layer that is covered by the insulation layer so as to constitute another portion of the surface of the outer electrode, and the Sn-containing layer covers a portion of the sintered layer on at least a portion of one of the pair of main surfaces and a portion of one of the pair of side surfaces of the element assembly.

US Pat. No. 10,770,203

PLUG-IN POWER AND DATA CONNECTIVITY MICRO GRIDS FOR INFORMATION AND COMMUNICATION TECHNOLOGY INFRASTRUCTURE AND RELATED METHODS OF DEPLOYING SUCH MICRO GRIDS

CommScope Technologies LL...

1. A power and data connectivity micro grid, comprising:a local power supply;
a first power sourcing equipment device having a first power port, a second power port, a first data port and a second data port, the first power sourcing equipment device coupled to the local power supply and configured to deliver respective direct current (“DC”) power signals to the first power port and the second power port;
a first remote distribution node;
a second remote distribution node;
a first splice enclosure having a power input port, a data input port, a power tap port, a data tap port, a power output port and a data output port;
a second splice enclosure having a power input port, a data input port, a power tap port, a data tap port, a power output port and a data output port;
a first composite power-data cable coupled between the first power port and the first data port of the first power sourcing equipment device and the power input port and the data input port of the first splice enclosure; and
a second composite power-data cable coupled between the second power port and the second data port of the first power sourcing equipment device and the power input port and the data input port of the second splice enclosure;
wherein the power tap port and the data tap port of the first splice enclosure are coupled to a power input port and a data input port of the first remote distribution node, respectively.

US Pat. No. 10,770,201

METHOD OF MANUFACTURING POWER CABLES AND RELATED POWER CABLE

PRYSMIAN S.p.A., Milan (...

1. A method for manufacturing a power cable comprising:providing at least one core comprising an electrical conductor;
arranging at least one copper sheath around the at least one core, said arranging the copper sheath comprising:
providing at least one copper foil having two opposite first edges;
bending the copper foil around the core until the first edges of the copper foil are contacted to each other;
welding the first edges of the copper foil to each other to form a corresponding welded joint; and
deposing a copper coating on the copper foil and the welded joint, wherein said deposing the copper coating is carried out by a thermal spray process.

US Pat. No. 10,770,200

SHIELDED CONDUCTIVE PATH

Sumitomo Wiring Systems, ...

1. A shielded conductive path in which a plurality of conductive members each including a conductor, an insulating portion and a shield disposed from a central part toward an outer peripheral side are arranged in parallel in a width direction, wherein:at least one of the conductor, the insulating portion and the shield is formed by a shape retaining member capable of retaining each conductive member in a set shape,
the conductor is formed by a pipe made of conductive metal and comprises the shape retaining member, and
a plurality of the conductor constituting the plurality of conductive members arranged in parallel in the width direction are squeezed in a height direction into a flat shape extending in the width direction.

US Pat. No. 10,770,198

METHOD AND FACILITY FOR FILLING A GAS-INSULATED ELECTRICAL APPARATUS COMPRISING A MIXTURE OF (CF3)2CFCN AND CO2

General Electric Technolo...

1. A method of filling a closed casing containing at least one electrical component of equipment for a high-or medium-voltage electricity transmission line with a gas mixture comprising heptafluoroisobutyronitrile and carbon dioxide in predefined proportions, said method comprising:a) preparing, in a container, a pressurized liquid mixture comprising heptafluoroisobutyronitrile and carbon dioxide in predefined proportions;
b) heating, in the container, the pressurized liquid mixture prepared in a) until it reaches a temperature that is higher than or equal to the critical temperature of the mixture whereby a gas mixture comprising heptafluoroisobutyronitrile and carbon dioxide in predefined proportions is obtained; and
c) transferring said gas mixture obtained in b) from the container to the casing via a transfer circuit in which the gas mixture is decompressed and maintained at a temperature that is higher than the liquefaction temperature of heptafluoroisobutyronitrile at its partial pressure in the transfer circuit before it enters the casing to be filled.

US Pat. No. 10,770,197

POLYMER-SILICA HYBRID PDOTS AND METHODS OF USE THEREOF

University of Washington,...

1. An organic-inorganic hybrid polymer dot comprising:a semiconducting chromophoric polymer; and
an inorganic network,
wherein the semiconducting chromophoric polymer and the inorganic network form an organic-inorganic interpenetrated network through physical association of the semiconducting chromophoric polymer and the inorganic network, and
wherein the physical association of the semiconducting chromophoric polymer and the inorganic network does not include covalent bonding between the semiconducting chromophoric polymer and the inorganic network.

US Pat. No. 10,770,196

BINARY MULTILEAF COLLIMATOR DELIVERY WITH PER-LEAF FIELD WIDTH

ACCURAY INCORPORATED, Su...

1. A method of controlling a two-bank multileaf collimator (MLC) of a radiation treatment delivery system, comprising:determining a plurality of radiation beam delivery positional sections to contain MLC leaf control instructions while a radiation beam is active, wherein each of the plurality of radiation beam delivery positional sections corresponds to a range of radiation beam positions over a discrete time interval, wherein the discrete time interval is based on an average open-time and a modulation factor;
generating a plurality of openings for each of the plurality of radiation beam delivery positional sections, each of the plurality of openings corresponding to one of a plurality of leaf pairs of the MLC, wherein two or more of the plurality of openings correspond to different widths;
generating a plurality of leaf open-time fractions for each of the plurality of radiation beam delivery positional sections, each of the plurality of leaf open-time fractions corresponding to one of the plurality of leaf pairs of the MLC; and
controlling, by a processing device, the plurality of leaf pairs of the MLC such that each leaf pair of the plurality of leaf pairs is opened to a corresponding opening of the plurality of openings for a corresponding leaf open-time fraction of the plurality of leaf open-time fractions during the discrete time interval corresponding to the range of radiation beam positions, while the radiation beam of the radiation treatment system is active.

US Pat. No. 10,770,195

X-RAY CHOPPER WHEEL ASSEMBLY

VIKEN DETECTION CORPORATI...

1. An x-ray chopper wheel assembly comprising:a disk chopper wheel configured to rotate about a rotation axis thereof, the rotation axis perpendicular to a rotation plane of the disk chopper wheel, the disk chopper wheel having a solid cross-sectional area in the rotation plane, the disk chopper wheel configured to absorb x-ray radiation received from an x-ray source at a source side of the disk chopper wheel, the disk chopper wheel defining one or more radial slit openings configured to pass x-ray radiation from the source side of the disk chopper wheel to an output side of the disk chopper wheel;
a source-side scatter plate having a solid cross-sectional area in a plane substantially parallel to the rotation plane of the disk chopper wheel, the source-side scatter plate configured to absorb x-ray radiation and defining an open slot therein configured to pass x-ray radiation, wherein the solid cross-sectional area of the source-side scatter plate is substantially smaller than the solid cross-sectional area of the disk chopper wheel; and
a support structure configured to secure the source-side scatter plate in the plane substantially parallel to the rotation plane of the disk chopper wheel with a source-side gap between the source-side scatter plate and the source side of the disk chopper wheel wherein the disk chopper wheel and source-side scatter plate are arranged relative to each other to cause a substantial confinement of x-rays that are scattered from the disk chopper wheel.

US Pat. No. 10,770,194

NUCLEAR FUEL STORAGE CASK

1. A nuclear fuel storage cask comprising:an outer shell having a length extending from a first end to a second end of the outer shell positioned opposite the first end, the outer shell defining:
an inner cavity circumscribed by the outer shell;
an outer perimeter extending around the outer shell;
an inner perimeter positioned inward from the outer perimeter and positioned between the outer perimeter and the inner cavity; and
a cooling circuit extending along the length of the outer shell, the cooling circuit comprising an inner passage, and an outer passage positioned outward of and in fluid communication with the inner passage;
a coolant positioned within the cooling circuit, wherein the coolant is configured to move through the inner passage, absorbing heat from the inner cavity of the outer shell, and the coolant is configured to move through the outer passage, dissipating heat through the outer perimeter of the outer shell; and
a lid coupled to the outer shell, wherein the lid covers the inner cavity of the outer shell and the lid comprises a lid cooling circuit, the lid cooling circuit comprising a vapor passage and a lid outer passage distinct from one another, the lid outer passage positioned outward of the vapor passage, and a lid coolant positioned within the lid cooling circuit, wherein the lid coolant remains in the lid cooling circuit and circulates between the vapor passage and the lid outer passage.

US Pat. No. 10,770,193

SYSTEM FOR STORAGE CONTAINER WITH REMOVABLE SHIELD PANELS

Veolia Nuclear Solutions,...

1. A storage container system, the system comprising:a plurality of storage containers each including a plurality of side walls, each of the side walls having a shield mounting point, wherein the plurality of storage containers are arrangeable in a plurality of storage configurations, each storage configuration including a plurality of exposed side walls along an outermost portion of the storage configuration, the exposed side walls each formed by a side wall of storage container that is not mated with a side wall of an adjacent storage container;
a plurality of shield panels each having a shield mounting point, each of the plurality of shield panels having a different shielding material property from the plurality of storage containers and configured to be removably coupled to one of the plurality of exposed side walls; and
a plurality of shield mounts configured to removably couple the plurality of shield panels to the plurality of exposed side walls, wherein each of the plurality of shield mounts includes a first slot and a second slot, the first slot configured to engage with the mounting point on one of the plurality of storage containers, the second slot engaging the mounting point on one of the plurality of shield panels.

US Pat. No. 10,770,192

CASK HANDLING SYSTEM AND METHOD

MHE Technologies, Inc., ...

1. A system for removing spent nuclear fuel from a fuel pool having a penetration comprising:a handling mechanism located at a fixed position below the penetration of the fuel pool;
a transporter configured to move a cask below the handling mechanism;
wherein the handling mechanism is configured to raise the cask from the transporter to the penetration and to support the cask as the cask is secured to the penetration; and
wherein the transporter and the handling mechanism is configured to move the transporter away from the handling mechanism after the cask is raised off of the transporter by the handling mechanism.

US Pat. No. 10,770,191

SYSTEMS AND METHODS FOR REDUCING SURFACE DEPOSITION AND CONTAMINATION

GE-Hitachi Nuclear Energy...

1. A system for reducing contaminant deposition on a surface immersed in a fluid, the system comprising:a fluid source including a pump configured to draw the fluid from a cavity in which the apparatus is immersed; and
an apparatus configured to discharge a fluid from the fluid source against a surface while immersed in the fluid, wherein the apparatus includes the pump such that the pump is immersed in the fluid.

US Pat. No. 10,770,190

CATALYTIC RECOMBINER AND FILTER APPARATUS

Framatome GmbH, Erlangen...

1. A catalytic recombiner and filter apparatus, comprising:a duct;
a number of catalytic elements disposed in said duct for recombining hydrogen and oxygen, or carbon monoxide and oxygen, contained in a gas flow through said duct;
a number of adsorber elements arranged inside said duct, said adsorber elements having iodine adsorbing surfaces and macroscopic flow channels formed in between said iodine adsorbing surfaces, wherein said iodine adsorbing surfaces are flown over by the gas flow;
said adsorber elements being arranged downstream of the catalytic elements in a direction of the gas flow;
a housing enclosing said duct, said housing having a section between said adsorber elements and said catalytic elements with a number of ventilation slots for facilitating an influx of ambient air into said duct; and
a movable cover element disposed for covering a respective said ventilation slot and coupled to a temperature-dependent passive actuator, configured for opening said ventilation slot above a pre-defined critical temperature prevailing in said duct.

US Pat. No. 10,770,189

MAGNETICALLY-ACTUATED ISOLATED ROD COUPLINGS FOR USE IN A NUCLEAR REACTOR CONTROL ROD DRIVE

GE-HITACHI NUCLEAR ENERGY...

1. A control rod drive for positioning a control element in a nuclear reactor, the drive comprising:a control element;
a linear drive;
a releasable latch between the control element and linear drive, wherein the releasable latch secures the control element with the linear drive when subject to a magnetic field and releases the control element from the linear drive when not subject to the magnetic field; and
an induction coil or magnetic material selectively generating the magnetic field, wherein the induction coil or magnetic material is configured to move in unison with the releasable latch across a stroke distance of the control element.

US Pat. No. 10,770,187

NUCLEAR FUEL PEBBLE AND METHOD OF MANUFACTURING THE SAME

X-ENERGY, LLC, Greenbelt...

1. A nuclear fuel element comprising:a fuel zone comprising:
fuel particles disposed in parallel layers and in a predetermined pattern, the fuel particles comprising fissile particles, burnable poison particles, breeder particles, or a combination thereof; and
a matrix configured to separate the fuel particles, the matrix comprising graphite powder, graphite spheres, or a combination thereof; and
a fuel particle-free shell comprising graphite powder and surrounding the fuel zone, wherein:
the fuel zone comprises a central region and a peripheral region surrounding the central region;
a fuel particle density of the peripheral region is greater than a fuel particle density of the central region; and
the matrix comprises layers of graphite powder configured to separate adjacent layers of fuel particles.

US Pat. No. 10,770,185

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

Sony Corporation, Tokyo ...

1. An information processing system comprising:a processor including a processing device and a memory storing instructions that, when executed by the processing device, cause the processor to:
obtain blood-sugar level information and electronic payments information of a patient, the blood-sugar level information being obtained from a blood-sugar level meter and the electronic payments information including information regarding goods purchased by the patient;
save the blood-sugar level information and the electronic payments information to a storage device;
calculate a calorie value based on the information regarding goods purchased;
calculate a future estimated blood-sugar level based on the blood-sugar level information and the calculated calorie value using a predetermined metabolism model; and
output the future estimated blood-sugar level as an image or a sound signal for action by the patient, including outputting a warning when the future estimated blood-sugar level does not fall within a suitable range.

US Pat. No. 10,770,184

DETERMINING PATIENT CONDITION FROM UNSTRUCTURED TEXT DATA

CERNER INNOVATION, INC., ...

1. Non-transitory computer-readable media having computer-executable instructions embodied thereon that when executed, facilitate a method for generating a structured topic model (STM) for use to determine one or more patient conditions from unstructured text data, the method comprising:acquiring a set of historical text documents related to care of human patients, each document having metadata labels ascribing one or more conditions of a patient associated with the document, the one or more conditions identified at the time the document was created;
calculating a structured topic modeling (STM) model associating terms from the set of historical text documents with the metadata labels;
using the STM model, performing Expectation Maximization iterations to determine optimal associations of the terms with the metadata labels thereby forming a set of clusters, each cluster comprising an association of one or more terms and one or more metadata labels;
determining a set of candidate conditions associated with each cluster based on the association of one or more terms and one or more metadata labels;
storing an electric record of the set of clusters in a data store;
receiving unstructured clinical narratives associated with a particular patient;
determining, using the STM model and the received unstructured clinical narratives, a likely cluster membership of the particular patient into one or more of the clusters, wherein the likely cluster membership is determined by calculating a quantitative lexical distance between the unstructured clinical narratives associated with the particular patient and the set of candidate conditions; and
storing the likely cluster membership of the particular patient in the data store.

US Pat. No. 10,770,182

SYSTEMS AND METHODS FOR ASSESSING THE HEALTH STATUS OF A PATIENT

Boston Scientific Scimed,...

1. A method of assessing the health status of a patient comprising:evaluating the presence of volatile organic compounds in a breath or gas sample of the patient with a plurality of graphene sensors to generate volatile organic compound data, wherein the plurality of graphene sensors include sensors that are specific for different volatile organic compounds;
collecting data regarding the patient's sympathetic nervous activity, the data comprising at least one of heart rate variability (HRV), electrodermal activity (EDA), respiratory sinus arrhythmia (RSA), and baroreceptor sensitivity (BRS);
combining the volatile organic compound data with the collected data regarding the patient's sympathetic nervous activity to form a combined data set; and
matching the combined data set against one or more previously determined data patterns using a pattern matching algorithm to determine the data pattern that is the best match, wherein the specific previously determined data pattern that is the best match indicates the health status of the patient.

US Pat. No. 10,770,181

SYSTEMS AND METHODS FOR REDUCING RESOURCE CONSUMPTION VIA INFORMATION TECHNOLOGY INFRASTRUCTURE

Alegeus Technologies, LLC...

1. A system to reduce resource consumption via information technology infrastructure, comprising:a communications interface executed by a server and configured to receive one or more data packets including data indicating a healthcare transaction event corresponding to a participant of a plurality of participants of a healthcare management platform, wherein the healthcare transaction event includes a denial;
a forecast engine executed by the server and configured to:
identify a machine learning engine configured to train healthcare trend models that predict resource allocations to reduce resource consumption using at least one of decision tree learning, a predictive model, association rule learning, support vector machines, clustering, or reinforcement learning;
train, using the machine learning engine, the healthcare trend model to include a baseline threshold for one or more features using previously received data packets including data indicating healthcare transaction events corresponding to the plurality of participants of the healthcare management platform;
select the healthcare trend model to provide healthcare related recommendations to the plurality of participants of the healthcare management platform maintained by the server;
initiate, based on a comparison between the healthcare transaction event and the baseline threshold of the selected healthcare trend model, a notification engine to cause the notification engine to reduce resource consumption of information technology infrastructure;
the notification engine executed by the server and configured to:
perform, responsive to initiation by the forecast engine, a lookup in a recommendation data structure using an identifier of the selected healthcare trend model to identify a plurality of healthcare related recommendations linked with the selected healthcare trend model;
determine a correlation coefficient between each of the plurality of healthcare related recommendations and the selected healthcare trend model, wherein the correlation coefficient indicates a likelihood that the plurality of healthcare related recommendations reduces resource consumption of information technology infrastructure by reducing an occurrence of denied transactions;
select, based on a rank of each correlation coefficient, a highest ranking healthcare related recommendation of the plurality of healthcare related recommendations configured to reduce resource consumption of information technology infrastructure by reducing the occurrence of denied transactions;
retrieve, responsive to the selection of the highest ranking healthcare related recommendation, a notification template from a notification template data structure that maps to the highest ranking healthcare related recommendation;
generate, using the notification template, a notification corresponding to the highest ranking healthcare related recommendation configured to reduce a likelihood of future occurrences of the healthcare transaction event;
generate a request to deliver the notification corresponding to the highest ranking healthcare related recommendation at a destination address of a computing device of the participant; and
transmit, to the computing device via a communication channel established between the server and the computing device, responsive to the request, the notification to the computing device of the participant to reduce a likelihood of future occurrences of the healthcare transaction event.

US Pat. No. 10,770,179

DETERMINING EFFICIENT EXPERIMENTAL DESIGN AND AUTOMATED OPTIMAL EXPERIMENTAL TREATMENT DELIVERY

JUNTOS, INC., San Carlos...

1. A computer implemented method for determining an optimal sample size for experiments targeting units having specific static criteria, the method comprising:maintaining access, by a computer, to a plurality of units of a production set, wherein the units comprise mobile computing devices that are associated with empirically measurable activity, such that the empirically measurable activity can be influenced by using specific treatments mapped to a specific goal, wherein the production set comprises a plurality of units that are being exposed to a plurality of treatments over time and corresponding empirical results are being measured and tracked, wherein the treatments comprise electronic messages automatically transmitted by a sample size and treatment optimization system to the mobile computing devices;
selecting, by the computer, at a specific point in time, a subset of units of the production set meeting specific static criteria, the selected subset comprising a given number of units, the given number having been determined for creating a treatment group and a control group;
creating, by the computer, a treatment group of units from the subset meeting the specific static criteria and a control group of units from the subset meeting the specific static criteria;
performing, by the computer, a paired comparison test on the treatment group and the control group, wherein the paired comparison test compares empirical results for the units of the treatment group to empirical results for the units of the control group, the empirical results for the units of the treatment group and for the units of control group being against the specific goal over time, measured at the specific point in time at which the units were selected from the production set;
accepting, by the computer, the treatment group and the control group only in response to a mean percentage difference between the treatment group and the control group being less than a specific threshold value;
calculating, by the computer, expected signal-to-noise ratio of the units of the treatment group and the units of control group according to a specific signal-to-noise ratio calculation rule set, taking into account empirical results for the units of the treatment group and for the units of control group against the specific goal over time, measured at the specific point in time at which the units were selected from the production set;
performing, by the computer, a test of the calculated expected signal-to-noise ratio of the units of the treatment group and the units of control group;
accepting, by the computer, the treatment group and the control group only in response to the calculated expected signal-to-noise ratio exceeding a specific threshold value;
recording, by the computer, mean of the control group, mean of the treatment group, pairwise standard deviation of the treatment and control groups, and pairwise mean of the treatment and control groups, calculated based on measured empirical results for the units of the treatment group and for the units of the control group against the specific goal over time, measured at the specific point in time at which the units were selected from the production set;
performing, by the computer, an experiment comprising exposing the units of the treatment group to a specific treatment and not exposing the units of the control group to the specific treatment;
calculating, by the computer, an effect of the performed experiment as mean difference in measured activity between the units of the treatment group and the units of the control group after having performed the experiment;
recording, by the computer, the calculated effect of the performed experiment; and
calculating, by the computer, an optimal sample size to use for subsequent experiments targeting units having the specific static criteria, according to a specific sample size calculation rule set taking into account target effect of the performed experiment and an updated expected signal-to-noise ratio, wherein the updated expected signal-to-noise ratio is calculated based on measured empirical results for the units of the treatment group and for the units of the control group against the specific goal over time, measured at a second specific point in time occurring after the performing of the experiment.

US Pat. No. 10,770,178

METHOD AND APPARATUS TO ACCOUNT FOR TRANSPONDER TAGGED OBJECTS USED DURING CLINICAL PROCEDURES EMPLOYING A SHIELDED RECEPTACLE WITH ANTENNA

Covidien LP, Mansfield, ...

1. An apparatus for use in clinical environments, the apparatus comprising:at least one shielded receptacle, the at least one shielded receptacle having an interior, a port that provides access to the interior from an exterior of the shielded receptacle, and at least one shield that shields the interior of the at least one shielded receptacle and any wireless communications transponders in the interior of the at least one shielded receptacle from at least one of radio or microwave frequency energy emitted externally from the at least one shielded receptacle at least when the port is in a closed configuration;
a cover operatively associated with the at least one shielded receptacle, wherein the cover is:
positionable on the port to place the at least one shielded receptacle in the closed configuration; and
removable from the port to place the at least one shielded receptacle in an open configuration; and
at least one receptacle radio frequency identification (RFID) interrogator, the at least one RFID interrogator communicatively coupled to:
a first set of antennas supported on an inner surface of the cover, the first set of antennas positioned and oriented to provide coverage for at least a portion of the interior of the at least one shielded receptacle,
wherein the first set of antennas is configured to emit at least one of radio or microwave frequency energy interrogation signals; and
a second set of antennas supported on the exterior of the shielded receptacle, the second set of antennas positioned and oriented to detect response signals originating from any wireless communications transponders contained within the interior of the shielded receptacle,
wherein the at least one RFID interrogator, via the second set of antennas, is configured to generate an alert indicating that transponders contained within the interior of the shielded receptacle are not completely shielded.

US Pat. No. 10,770,177

DISPATCH MANAGEMENT PLATFORM FOR NURSE CALL SYSTEM

1. A dispatch management system for workflow optimization of the patient-nurse call process, said dispatch management system being integrated with an existing healthcare provider client-server network including a computer network in communication with a medical records database and a nurse call system, the dispatch management system comprising:a plurality of RTLS tracking tags each identified by a unique identification code, each assigned to a nurse, and each periodically transmitting a message at least including said unique identification code and location information;
an RTLS location server in communication with said healthcare provider client-server network, said RTLS location server comprising a computer having non-transitory computer memory connected to said healthcare provider client-server network, said RTLS location server running application software comprising computer instructions stored on said non-transitory computer memory for tracking a real time position of each of said RTLS tracking tags;
a nurse call server in communication with said healthcare provider client-server network, said nurse call server comprising a computer having non-transitory computer memory connected to said healthcare provider client-server network, said nurse call server running application software comprising computer instructions stored on said non-transitory computer memory for maintaining a database of nurses, and for querying said RTLS location server to determine a position of said nurses within a facility;
a portable quarterback (QB) computer in communication with said nurse call server, said portable QB computer connected to said healthcare provider client-server network, said portable QB computer running a QB computer application for displaying a QB Call Browser comprising a plurality of screens inclusive of an overview screen presenting a nurse call cancellation button, a task selection screen comprising a listing of task types selectable for assignment, a listing of nurse calls including task type, patient room, name, and reason for call, and a listing of nurses qualified to perform the task type of each nurse call in said listing, said QB Application further comprising a timer for tracking time to completion of each nurse call;
a plurality of mobile devices each assigned to a nurse, each mobile device being connected to said nurse call server, and each mobile device comprising a computer running application software comprising a Nurse Browser for remotely displaying a subset of information displayed on said QB Call Browser; and
a plurality of room door tablet computers each mounted outside the patient room and each in communication with said nurse call server, said portable QB computer, and said healthcare provider client-server network for determining and displaying room status and an occupant of said patient room.

US Pat. No. 10,770,176

SYSTEM AND METHOD FOR IDENTIFYING RELATIONSHIPS IN COMMUNITY HEALTHCARE MEASURES

Optum, Inc., Minnetonka,...

1. A method implemented on a data processing system identifying related factors affecting geographic community health care attributes, the method comprising:receiving, by the data processing system, health care information from a plurality of health care claims;
receiving, by the data processing system, community information associated with the health care information from the plurality of health care claims, the community information identifying one or more communities associated with corresponding claims in the plurality of health care claims;
storing, by the data processing system, the health care information for each of the health care claims in association with the community identifying information for each of the health care claims;
identifying, by the data processing system, a set of community health care measures including measures of the stored health care information;
receiving, by the data processing system, values of one or more of the community health care measures from the health care information;
storing, by the data processing system, the values and/or statistics of the values for each of the communities in association with the corresponding community identifying information;
receiving, by a computer implemented application of a community measures tool having a graphical user interface, a first user interface (UI) input that selects one of the community health care measures as a first measure;
receiving, by the computer implemented application of the community measures tool, a second UI input that selects another one of the community health care measures as a second measure;
automatically computing, by the computer implemented application of the community measures tool, correlated data between the first measure and the second measure for the each of the communities in response to receiving the first UI input and the second UI input;
processing, by the computer implemented application of the community measures tool, the correlated data, the processing of correlated data comprising:
generating, by the computer implemented application of the community measures tool, a community score for the plurality of communities;
displaying, by the graphical user interface of the computer implemented application of the community measures tool, a visual representation of the selected communities, population attributes, and health care outcomes, the visual representation comprising a first correlation graph of data points, wherein each of the data points corresponds to a community and wherein a graph location of each of the data points is defined by a value of the first measure on a horizontal axis and a value of the second measure on a vertical axis for the corresponding community;
receiving, by the graphical user interface of the computer implemented application of the community measures tool, selection of user-defined weights for one or more of the communities, population attributes, and/or one or more of the health care outcomes to customize the visual representation and community score to the user;
automatically updating, by the graphical user interface of the computer implemented application of the community measures tool, the visual representation of the correlated data in response to changes to the user-defined weights input to the graphical user interface of the computer implemented application;
receiving, by the graphical user interface of the computer implemented application of the community measures tool, a user input that selects one or more of the plurality of communities from the visual representation of the selected communities, population attributes, and health care outcomes; and
identifying, by the computer implemented application of the community measures tool, other geographic communities that are similar or dissimilar to the selected communities from the visual representation of the selected communities, population attributes, and health care outcomes on the graphical user interface based on the selected user-defined weights for one or more of the communities, population attributes, and/or one or more of the health care outcomes.

US Pat. No. 10,770,175

SYSTEM AND METHOD FOR SEGMENTATION AND VISUALIZATION OF MEDICAL IMAGE DATA

MULTUS MEDICAL LLC, Temp...

1. A computing device comprising:a processor;
a display coupled to the processor;
a user interface coupled to the processor for entering data into the computing device; and
a memory coupled to the processor, the memory storing program instructions that when executed by the processor, causes the processor to:
load medical image data, wherein the medical image date is a plurality of two-dimensional images;
match the medical image data to an anatomical model stored in a database having a data set closest to the medical image data;
adjust at least one property on the anatomical model to form a modified three-dimensional anatomical model to match the medical data image; and
detect if areas on the modified three-dimensional anatomical model exceeds predefined ranges indicating potential injured areas.

US Pat. No. 10,770,174

MONITORING SYSTEM FOR A DIALYSIS MACHINE

Fresenius Medical Care De...

1. A monitoring system, wherein the monitoring system comprises a processor and a non-transitory computer-readable medium having processor-executable instructions stored thereon, wherein the processor-executable instructions, when executed by the processor, facilitate:receiving, by the monitoring system, data from a dialysis machine via a first data communication network, wherein the data includes machine data, error codes, operational data, environmental data, consumables data, network data, and/or treatment data;
storing, by the monitoring system, the received data corresponding to the dialysis machine;
analyzing, by the monitoring system, the stored data corresponding to the dialysis machine to determine a fault with respect to a first component of the dialysis machine;
assigning, by the monitoring system, an error code to the determined fault;
determining, by the monitoring system, a user or user group to which information relating to the fault to is to be sent based on the assigned error code; and
sending, by the monitoring system, to the determined user or user group, the information relating to the fault via a second data communication network.

US Pat. No. 10,770,173

EFFECTING PAYMENTS USING OPTICAL COUPLING

APPLE INC., Cupertino, C...

1. A computer-implemented method comprising:receiving, at a server of a prescription clearinghouse system, a first data file corresponding to a prescription, wherein the first data file includes a patient identifier associated with the prescription;
generating, via the server, a database entry in a database of the prescription clearinghouse system associating a unique claim number with the first data file and a prescription fulfillment status indicating non-fulfillment;
transmitting, by the server to a mobile client device associated with the patient identifier, a second data file including an optical code encoding the unique claim number;
receiving, from a pharmacy system registered with the server, a request for access to the prescription associated with the optical code captured by the pharmacy system, the request including the unique claim number;
transmitting, by the server to the pharmacy system in response to the request, the prescription associated with the unique claim number, the prescription having the patient identity and the doctor identity anonymized;
reconciling payment for the prescription and sending confirmation of payment to the pharmacy system;
receiving, at the server from the pharmacy system, a confirmation message indicating that the prescription was processed by the pharmacy system; and
updating, via the server, the prescription fulfillment status in the database for the unique claim number based on the confirmation message.