US Pat. No. 10,431,501

SEMICONDUCTOR DEVICE WITH HIGH-K GATE DIELECTRIC LAYER AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:forming an interlayer dielectric layer on a base substrate;
forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to one second opening, the one first opening being between the one second opening and the base substrate to expose the base substrate;
forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings;
forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer;
forming an amorphous silicon layer on the cap layer and at least on the bottom surfaces of the first openings, wherein forming the amorphous silicon layer comprises:
forming an amorphous silicon film on the cap layer on the side and bottom surfaces of the first openings and the side surfaces of the second openings;
forming a filling layer to fill the first openings;
etching portions of the amorphous silicon film on the side surfaces of the second openings using the filling layer as an etching mask; and
removing the filling layer;
after forming the amorphous silicon layer, performing a thermal annealing process on the cap layer and the high-K gate dielectric layer through the amorphous silicon layer to cause the oxygen ions to diffuse into the high-K gate dielectric layer and the amorphous silicon layer to absorb the oxygen ions;
removing the amorphous silicon layer; and
forming a metal layer to fill the first openings and the second openings.

US Pat. No. 10,431,500

MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a trench in a material;
forming a conductor in a lower portion of the trench;
performing a first atomic layer deposition (ALD) of a first liner material to line a middle portion and an upper portion of the trench, the middle portion is between the lower portion and the upper portion;
flowing a fill material comprising an insulator to fill the middle portion and the upper portion of the trench;
removing the fill material from the upper portion of the trench to leave the fill material in the middle portion of the trench; and
performing a second ALD of a second material to fill the upper portion of the trench with the second material.

US Pat. No. 10,431,499

INSULATING GATE SEPARATION STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit product, comprising:a first final gate structure for a first transistor device;
a second final gate structure for a second transistor device, said first and second transistors having a gate width direction and a gate length direction that is substantially normal to said gate width direction; and
an insulating gate separation structure positioned between said first and second final gate structures, said insulating gate separation structure comprising an upper portion and a lower portion, said lower portion having a first lateral width in said gate width direction that is substantially uniform throughout a vertical height of said lower portion, said upper portion having a substantially uniform second lateral width in said gate width direction that is substantially uniform throughout a vertical height of said upper portion, wherein said second lateral width is less than said first lateral width and wherein said insulating gate separation structure has a substantially uniform third lateral width in said gate length direction throughout an overall vertical height of said gate separation structure, wherein there is a stepped transition between said upper portion and said lower portion of said gate separation structure.

US Pat. No. 10,431,498

SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF

Semiconductor Manufacturi...

15. A semiconductor structure, comprising:a base substrate;
a plurality of gate structures formed on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode;
a sacrificial layer formed on the sidewall spacers on each side surface of the gate electrode; and
source/drain doped regions formed in the base substrate on opposite sides of each gate structure, wherein
each of the source/drain doped regions includes an amorphous layer exposed by the sacrificial layer from an ion implantation using the sacrificial layer as a mask and a remaining portion of each of the source/drain doped regions directly covered by the sacrificial layer, and
the amorphous layer and the remaining portion of each of the source/drain doped regions are divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures.

US Pat. No. 10,431,497

MANUFACTURING METHOD OF EPITAXIAL FIN-SHAPED STRUCTURE

UNITED MICROELECTRONICS C...

1. A manufacturing method of an epitaxial fin-shaped structure, comprising:providing a substrate;
forming a recess in the substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer is partly formed in the recess and partly formed outside the recess, and the epitaxial layer comprises a dent formed on the top surface of the epitaxial layer and formed corresponding to the recess in a thickness direction of the substrate;
forming a nitride layer conformally on the epitaxial layer;
forming an oxide layer on the nitride layer;
performing a first planarization process to remove a part of the oxide layer, wherein the first planarization process is stopped on the nitride layer; and
patterning the epitaxial layer in the recess for forming at least one epitaxial fin-shaped structure.

US Pat. No. 10,431,496

DEVICE CHIP PACKAGE MANUFACTURING METHOD

DISCO CORPORATION, Tokyo...

1. A device chip package manufacturing method comprising:a cutting step of forming cut grooves having a depth reaching a finished thickness of device chips by cutting a device wafer from a top surface of the device wafer along a plurality of intersecting streets formed on the top surface by a cutting blade, the device wafer having devices formed in respective regions demarcated by the streets;
a cut groove inclination state detecting step of detecting an inclination state of the cut grooves that is performed after the cutting step is performed;
a sealing resin layer forming step of forming a sealing resin layer coating the top surface and the cut grooves of the device wafer by supplying a sealing resin to the top surface of the device wafer after the cutting step and the cut groove inclination state detecting step are performed;
a grinding step of thinning the device wafer to the finished thickness of the device chips by grinding an undersurface of the device wafer after the sealing resin layer forming step is performed; and
a laser processing step of dividing the device wafer into individual chips and forming device chip packages by holding the device wafer by a holding surface of a chuck table and applying a laser beam having a wavelength absorbable by the sealing resin layer along the cut grooves of the device wafer held by the chuck table after the grinding step is performed;
the laser processing step applying the laser beam in parallel with the cut grooves while the holding surface of the chuck table and the laser beam are inclined relative to each other on the basis of the inclination state of the cut grooves, the inclination state being detected in the cut groove inclination state detecting step.

US Pat. No. 10,431,495

SEMICONDUCTOR DEVICE WITH LOCAL CONNECTION

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a first trench silicide (TS) coupled to a first source or drain (S/D), a second TS coupled to a second S/D, and a gate metal separated from the first and second TS;
forming a trench above and on sides of the gate metal;
forming a local connection metal in the trench such that the gate metal is coupled to the first TS and the second TS; and
forming a local connection cap on top of the local connection metal.

US Pat. No. 10,431,494

BEOL SELF-ALIGNED INTERCONNECT STRUCTURE

International Business Ma...

1. An interconnect structure comprising:a lower interconnect level comprising a first interconnect dielectric material layer having a first electrically conductive line feature embedded therein;
an upper interconnect level located above the lower interconnect level and comprising a second interconnect dielectric material layer having a first electrically conductive via feature, a second electrically conductive line feature, and a second electrically conductive via feature stacked one atop the other, and embedded in the second interconnect dielectric material layer, wherein the first and second electrically conductive via features are self-aligned perpendicularly to, and along the direction of, the second electrically conductive line feature;
a third interconnect dielectric material layer having a lower portion embedded in the second interconnect dielectric material layer and laterally adjacent the second electrically conductive via feature, and an upper portion that is located above the second interconnect dielectric material layer and the second electrically conductive via feature; and
a first metal liner located on an entirety of a topmost surface of the second electrically conductive line feature and entirely separating the second electrically conductive line feature from the second electrically conductive via feature and from the third interconnect dielectric material layer.

US Pat. No. 10,431,493

DOPING CONTROL OF METAL NITRIDE FILMS

APPLIED MATERIALS, INC., ...

1. A method for controlling doping of a tantalum nitride film, the method comprising:controlling a temperature during deposition of a tantalum nitride film to control a density of the deposited tantalum nitride film, the density of the tantalum nitride film less than or equal to about 9.5 g/cm3; and
exposing the tantalum nitride film to a dopant metal precursor to form a doped tantalum nitride film,
wherein there is no plasma treatment during deposition of the tantalum nitride film or between deposition of the tantalum nitride film and doping of the tantalum nitride film.

US Pat. No. 10,431,491

SEMICONDUCTOR DEVICE HAVING A TRIPLE INSULATING FILM SURROUNDED VOID

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first semiconductor region extending in a first direction and having a first conductivity type;
a second semiconductor region extending in the first direction, disposed with the first semiconductor region in a second direction crossing the first direction, surrounding a void, and having a second conductivity type;
an insulating section provided between the void and the second semiconductor region, and including a first insulating film including silicon oxide, a second insulating film including silicon nitride, and a third insulating film including silicon oxide;
a third semiconductor region provided on the first semiconductor region and the second semiconductor region, and having the second conductivity type; and
a cover film provided on the void, the insulating section being located between the third semiconductor region and the cover film.

US Pat. No. 10,431,490

WAFER SCALE PACKAGING

Akoustis, Inc., Huntersv...

1. A method for packaging a resonator device, the method using a wafer scale packaging process, the method comprising:providing a single crystal acoustic resonator device formed on a silicon substrate having a first thickness, the single crystal acoustic resonator device comprising a resonator structure and a contact structure;
forming a patterned solder structure configured overlying the single crystal acoustic resonator device and the surface region to form a first air gap region provided from the patterned solder structure and configured between the resonator structure and a first portion of a mounting substrate member, wherein the first air gap region having a height of 10 um to 50 um, the patterned solder structure having a patterned upper surface region;
forming a thickness of an epoxy material overlying the patterned upper surface region, while maintaining the resonator structure free from any of the epoxy material;
positioning the mounting substrate member to the epoxy material;
curing the epoxy material to mate the single crystal acoustic resonator device to the mounting substrate member, the mounting substrate member being optically transparent, the mounting substrate member comprising a surface region; and
processing the silicon substrate to remove a portion of the silicon substrate to form a resulting silicon substrate of a second thickness, the second thickness being less than the first thickness, the resulting silicon substrate having a silicon backside region.

US Pat. No. 10,431,488

LIFT PIN AND METHOD FOR MANUFACTURING SAME

KOMICO CO., LTD., Anseon...

1. A lift pin passing through a hole of a susceptor on which a wafer is placed inside a process chamber in which an epitaxial process for the wafer is performed, to support the wafer, and having a surface formed of a glassy carbon material, the lift pin comprising:a pin head formed at an upper part of the lift pin, the upper part contacting the wafer;
a shaft passing through the hole of the susceptor; and
a pin neck comprising, between the pin head and the shaft, an outer circumferential surface inclinedly formed to be gradually narrower from the pin head to the shaft, wherein the lift pin includes a base member formed of ceramic material, and the glassy carbon material coated on the base member,
wherein a mirror surface treatment is performed on the glassy carbon material of the lift pin to reduce a friction among the lift pin, the wafer, and the susceptor to stably prevent a generation of particles caused by the friction,
wherein a heat conductivity of the glassy carbon is relatively lower than a heat conductivity of the base member made of the ceramic material in order to prevent the portion of the wafer contacting the lift pin from deteriorating.

US Pat. No. 10,431,487

MICRO-TRANSFER-PRINTABLE FLIP-CHIP STRUCTURES AND METHODS

X-Celeprint Limited, Cor...

1. A semiconductor structure suitable for transfer printing, comprising:a handle substrate;
a cured bonding layer disposed in contact with the handle substrate;
a capping layer disposed in contact with the bonding layer;
a patterned release layer disposed in contact with the capping layer; and
a completed semiconductor device disposed on or over the patterned release layer and attached to an anchor disposed on the handle substrate with at least one tether,
wherein the at least one tether is in a common plane with an exposed entry path to the patterned release layer.

US Pat. No. 10,431,486

WAFER ALIGNING DEVICE AND METHOD FOR ALIGNING A WAFER INTO A SPECIFIED ROTATIONAL ANGULAR POSITION

1. A wafer aligning device for placing a wafer in a predetermined rotational angular position (?S), the wafer aligning device comprising:a wafer table having a table receiving area configured to receive the wafer at the predetermined rotational angular position (?S); and
an aligning mechanism having an aligning receiving area configured to align the wafer into the predetermined rotational angular position (?S),
wherein the aligning receiving area is configured in an aligning position (PA) when receiving the wafer such that the aligning receiving area is positioned above the wafer table,
wherein the aligning mechanism is configured to place the wafer received in the aligning receiving area on the table receiving area of the wafer table by traversing toward the table receiving area via a vertical downward movement, and
wherein the aligning mechanism is configured to simultaneously align the wafer to the predetermined rotational angular position while traversing toward the table receiving area via the vertical downward movement.

US Pat. No. 10,431,485

ARTICLE TRANSPORT FACILITY

Daifuku Co., Ltd., Osaka...

1. An article transport facility comprising:a fixed support portion that is provided in a fixed state and supports an article;
a moving member that moves along a moving path that extends via a stop position that is set for the fixed support portion;
a transfer apparatus that is provided with a moving support portion configured to move integrally with the moving member along a widthwise direction that is orthogonal to a lengthwise direction of the moving path within a horizontal plane, and receives and supplies an article from and to the fixed support portion while the moving support portion moves to protrude and retract between a retracted position at which the moving support portion is housed within the moving path in terms of the widthwise direction and a protruding position at which the moving support portion protrudes outward from the moving path in the widthwise direction; and
a control unit that controls movement of the moving member and a transfer operation that is performed by the transfer apparatus, the control unit configured to execute a stopping control to stop the moving member at the stop position, and a protrusion control to move the moving support portion of the transfer apparatus from the retracted position to the protruding position,
wherein the article transport facility further comprises:
a detection target member that is provided at a position corresponding to the stop position, and has a length that is equal to a length of an acceptable stop range that is an acceptable range of the stop position, in the lengthwise direction; and
a detection unit that is provided on the moving member, at a fixed position relative to the retracted position, and detects the detection target member with the moving member being located within the acceptable stop range, and
the control unit is configured to start execution of the protrusion control upon the moving member reaching a protrusion start position as a result of the stopping control, the protrusion start position being set upstream of the stop position in a direction in which the moving member moves, and after the moving member has reached a protrusion monitoring start position that is set downstream of the protrusion start position in the direction in which the moving member moves toward the stop position, the control unit is configured to continue execution of the protrusion control as long as the detection unit is detecting the detection target member.

US Pat. No. 10,431,484

METHOD AND STATION FOR MEASURING THE CONTAMINATION OF A TRANSPORT BOX FOR THE ATMOSPHERIC CONVEYANCE AND STORAGE OF SUBSTRATES

PFEIFFER VACUUM, Annecy ...

1. A method for measuring contamination of a transport box for atmospheric conveyance and storage of substrates, the method comprising:measuring a concentration of at least one gaseous species inside the transport box by a measurement device comprising at least one gas analyzer and a measurement line connecting the at least one gas analyzer to an interface, the interface placing the measurement line in communication with an internal atmosphere of the transport box; and
supplying a gas flow containing water vapor to the measurement device.

US Pat. No. 10,431,483

TRANSFER SUPPORT AND TRANSFER MODULE

Industrial Technology Res...

1. A transfer support, adapted to contact a plurality of elements, the transfer support comprises a first surface, a second surface opposite to the first surface, a recess located on the second surface, a plurality of platforms protruded from the first surface, a plurality of supporting pillars distributed in the recess and a plurality of through holes, wherein the platforms comprise carry surfaces adapted to contact the elements, the through holes extend from the carry surfaces of the platforms to the recess, and two of the adjacent supporting pillars are spaced apart from each other so as to form an airway passage.

US Pat. No. 10,431,482

SUBSTRATE CONVEYANCE ROBOT AND SUBSTRATE DETECTION METHOD

KAWASAKI JUKOGYO KABUSHIK...

5. A substrate detection method for detecting a substrate held by a substrate conveyance robot, comprising:a preparation step of driving a robot arm of the substrate conveyance robot so as to bring a substrate holding device mounted to the robot arm close to a position where the substrate is arranged; and
a detection step of detecting the substrate by elevating a substrate sensor provided to the substrate holding device without elevating the robot arm so as to scan a region including a position where the substrate is arranged.

US Pat. No. 10,431,480

EXTERNAL SUBSTRATE ROTATION IN A SEMICONDUCTOR PROCESSING SYSTEM

APPLIED MATERIALS, INC., ...

1. A processing system for semiconductor processing, the processing system comprising:two transfer chambers;
a processing chamber coupled to one of the two transfer chambers; and
a rotation module positioned between the transfer chambers, the rotation module comprising:
a plurality of sidewalls;
a ceiling, wherein an interior volume is bounded by the plurality of sidewalls and the ceiling; and
a substrate support comprising a single substrate platform;
wherein a first portion of the single substrate platform is disposed within the interior volume of the rotation module and a second portion of the single substrate platform extends into an interior volume of a first transfer chamber and a second transfer chamber of the two transfer chambers, the rotation module configured to rotate a substrate while the second portion is extended into the first and second transfer chambers.

US Pat. No. 10,431,478

TIME-VARYING FREQUENCY POWERED HEAT SOURCE

1. An apparatus comprising:an article of manufacture, comprising an active heat source including:
a predefined substrate; and
two or more electrodes, formed at manufacture to be located directly or indirectly on the substrate, the electrodes configured to receive a non-zero frequency time-varying electrical energy that is coupled by the one or more electrodes to the substrate to generate a frequency-controlled heat source in the substrate, the heat source location selected along a length of the two or more electrodes by adjusting the frequency of the time-varying electrical energy; and
wherein the two or more electrodes include first and second electrodes separated from each other by different minimum spacing at different locations on at least one of the first and second electrodes so that adjusting the frequency of the time-varying electrical energy is capable of selectably adjusting at least one corresponding frequency-dependent current path between the first and second electrodes to provide the frequency-controlled heat at at least one desired location in the substrate.

US Pat. No. 10,431,477

METHOD OF PACKAGING CHIP AND CHIP PACKAGE STRUCTURE

Pep Innovation PTE Ltd., ...

1. A method of packaging a chip, comprising:mounting at least one chip to be packaged and at least one electrically conductive module on a carrier, wherein the at least one chip to be packaged has a back surface facing upwards and an active surface facing towards the carrier, and the at least one electrically conductive module is in the vicinity of the at least one chip to be packaged;
forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the at least one electrically conductive module, wherein the first encapsulation layer is disposed with at least one concave first cavity and at least one concave second cavity, wherein the at least one chip is located in the at least one first cavity, the back surface of the at least one chip facing towards the first encapsulation layer, and the at least one electrically conductive module is located in the at least one second cavity, wherein the first encapsulation layer encapsulates the at least one electrically conductive module and wherein the at least one electrically conductive module comprises an electrically conductive array formed by a plurality of electrically conductive studs, the electrically conductive array being integrally packaged by an insulating material;
detaching the carrier to expose the active surface of the at least one chip to be packaged and a first surface of the at least one electrically conductive module; and
completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged and the first surface of the at least one electrically conductive module, wherein a rewiring structure is formed on the active surface of the at least one chip and the first surface of the at least one electrically conductive module for leading out pads on the active surface of the at least one chip and the first surface of the at least one electrically conductive module.

US Pat. No. 10,431,476

METHOD OF MAKING A PLURALITY OF PACKAGED SEMICONDUCTOR DEVICES

NXP B.V., Eindhoven (NL)...

1. A method of making a plurality of packaged semiconductor devices, the method comprising:providing a carrier blank having a die receiving surface and an underside;
mounting a plurality of semiconductor dies on the die receiving surface of the carrier blank,
wherein the dies extend to a first height above the die receiving surface;
depositing an encapsulant on the die receiving surface,
wherein an upper surface of the encapsulant is located above said first height,
whereby the encapsulant covers the plurality of semiconductor dies; and
singulating the carrier blank and encapsulant to form the plurality of packaged semiconductor devices by:
sawing into the underside of the carrier to saw through the carrier blank and
saw partially through the encapsulant to a saw depth intermediate the first height and the upper surface of the encapsulant,
wherein said sawing separates the carrier blank into a plurality of carriers,
each carrier having
an underside corresponding to the underside of the carrier blank and
a die receiving surface corresponding to the die receiving surface of the carrier blank,
wherein the die receiving surface of each carrier has at least one of said semiconductor dies mounted thereon; and
removing encapsulant from upper surface of the encapsulant at least until said saw depth is reached;
further comprising contacting an electrical probe to the underside of at least some of the carriers to test the packaged semiconductor devices; and
performing solder reflow;
wherein said solder reflow is performed after said testing the packaged semiconductor devices;
further comprising contacting an electrical probe to the underside of at least some of the carriers to re-test the packaged semiconductor devices after said solder reflow is performed.

US Pat. No. 10,431,475

COLD PLATE WITH DAM ISOLATION

Intel Corporation, Santa...

1. A cold plate, comprising: a base; and a lid affixed to the base via a braze joint, wherein the braze joint extends around a perimeter of the lid, and wherein one of the lid or the base includes: a dam having a perimeter located inside of the perimeter of the lid, wherein the dam is compressed against another of the lid or the base and is liquid-tight to the other of the lid or the base, wherein the dam is unitary with the lid or the base, and wherein a cavity is located between the base and the lid within the perimeter of the dam to provide a circulation passage for a liquid coolant; wherein the base includes a first side and a second side opposite to the first side, wherein the lid is affixed to the first side of the base, wherein the first side of the base includes a first surface and a second surface, wherein the second surface is further from the second side than the first surface is from the second side, and wherein the braze joint affixes the lid to the first surface and the dam is compressed against the second surface.

US Pat. No. 10,431,473

FINFET WITH SOURCE/DRAIN STRUCTURE AND METHOD OF FABRICATION THEREOF

Taiwan Semiconductor Manu...

1. A method of semiconductor device fabrication, comprising:providing a plurality of adjacent first fins extending from a substrate, wherein the plurality of adjacent first fins include at least two inner first-fin sidewalls facing each other and two outer first-fin sidewalls facing away from the plurality of adjacent first fins;
depositing a first spacer layer over the plurality of adjacent first fins, wherein the first spacer layer includes a first region disposed along the at least two inner first-fin sidewalls and a second region disposed over the top of the plurality of adjacent first fins and along the two outer first-fin sidewalls;
performing a tilted implantation process to the first spacer layer so that the second region and a top portion of the first region of the first spacer layer have a first dopant concentration corresponding to a first etch rate and a bottom portion of the first region has a second dopant concentration corresponding to a second etch rate greater than the first etch rate;
performing an etching process to remove a top portion of the second region to form two outer first-fin spacers along the two outer first-fin sidewalls, remove a top portion of the plurality of adjacent first fins, and remove at least partially the first region; and
forming a first epitaxial layer over a remaining portion of the plurality of adjacent first fins, wherein the forming of at least a portion of the first epitaxial layer is laterally constrained by the two outer first-fin spacers.

US Pat. No. 10,431,472

GAS COMPOSITION FOR DRY ETCHING AND DRY ETCHING METHOD

KANTO DENKA KOGYO CO., LT...

1. A dry etching method comprising a selective etching step wherein a multilayer structure including(a1) a carbon-containing silicon-based film, (a2) a crystalline silicon film, (a3) an amorphous silicon film, (a4) a polycrystalline silicon film (polysilicon film), (a5) a silicon oxynitride film, or (a6) an amorphous carbon film, and
(b1) a silicon oxide film or (b2) a silicon nitride filmis subjected to plasma etching by using a gas composition for dry etching comprising a hydrofluorocarbon gas that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z?2x and y?z are satisfied, and thus selectively etching the silicon oxide film (b1) or the silicon nitride film (b2).

US Pat. No. 10,431,471

METHOD OF PLANARIZING A SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER

Infineon Technologies AG,...

1. A method of planarizing a semiconductor wafer, wherein the method comprises:providing a semiconductor wafer comprising a surface;
forming a mask layer directly on the surface of the semiconductor wafer, wherein a thickness of the mask layer is smaller in thinning areas, which are to be thinned for planarizing, than in areas which are not to be thinned for planarizing,
wherein the forming of the mask layer comprises forming a raw mask layer and subsequently removing portions of the raw mask layer in the thinning areas by polishing, wherein a greater amount of material of the raw mask layer is removed in the thinning areas than in other areas; and
removing material of the semiconductor wafer in the thinning areas by a polishing process and an etching process, wherein the material of the semiconductor wafer is removed faster than the material of the mask layer.

US Pat. No. 10,431,470

METHOD OF QUASI-ATOMIC LAYER ETCHING OF SILICON NITRIDE

TOKYO ELECTRON LIMITED, ...

1. A method of etching, comprising:providing a substrate having a first material containing silicon nitride and a second material that is different from the first material with the second material provided along first and second side walls of the first material such that the first material is between the second material on the first and second side walls and the first material fills a region between the second material on the first and second side walls;
forming a first chemical mixture by plasma-excitation of a first process gas containing H and optionally a noble gas;
exposing the first material on the substrate to the first chemical mixture to hydrogenate a surface and subsurface regions of the first material, the subsurface regions including a first portion and a second portion below the first portion, and after the exposing first material to the first chemical mixture the first portion has a hydrogen concentration greater than that at the surface and the second portion has a hydrogen concentration lower than that at the surface;
thereafter, forming a second chemical mixture by plasma-excitation of a second process gas containing S and F, and optionally a noble element;
exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material; and
repeating the exposing the first material to the first chemical mixture and the exposing the first material to the second plasma-excited process gas to remove the first material between the second material until a layer positioned under the first material is exposed, and after the layer positioned under the first material is exposed, the second material remains on the substrate.

US Pat. No. 10,431,469

METHOD FOR HIGH ASPECT RATIO PHOTORESIST REMOVAL IN PURE REDUCING PLASMA

Mattson Technology, Inc.,...

1. A method for removing photoresist and an-oxidation layer-from a semiconductor substrate, comprising:placing a substrate in a processing chamber, the processing chamber located downstream from a plasma chamber for generating a non-oxidizing plasma to be used in treating the substrate, the processing chamber separated from the plasma chamber by a separation grid, the separation grid configured to be transparent to neutral particles and not transparent to plasma;
generating a first non-oxidizing plasma from a first reactant gas and a first carrier gas in the plasma chamber, wherein the first non-oxidizing plasma comprises from about 10% to about 40% of the first reactant gas, wherein the first reactant gas has a flow rate of from about 0.05 standard cubic centimeters per minute per square centimeter of the substrate to about 12.5 standard cubic centimeters per minute per square centimeter of the substrate, and wherein the first carrier gas has a flow rate of from about 0.25 standard cubic centimeters per minute per square centimeter of the substrate to about 15 standard cubic centimeters per minute per square centimeter of the substrate, wherein the first reactant gas comprises ammonia, and the first carrier gas comprises nitrogen;
channeling neutral particles of the first non-oxidizing plasma through the separation grid to the surface of the substrate;
treating the substrate by exposing the substrate to the neutral particles of the first non-oxidizing plasma in the processing chamber to at least partially remove the photoresist layer from the substrate;
wherein the substrate contains high aspect ratio channels having an aspect ratio of greater than about 50;
subsequent to removing the photoresist from the substrate, generating a second non-oxidizing plasma from a second reactant gas and a second carrier gas in the plasma chamber, wherein the second non-oxidizing plasma comprises from about 10% to about 40% of the second reactant gas, wherein the second reactant gas has a flow rate of from about 100 standard cubic centimeters per minute to about 15,000 standard cubic centimeters per minute, and wherein the second carrier gas has a flow rate of from about 500 standard cubic centimeters to about 20,000 standard cubic centimeters per minute, wherein the second reactant gas comprises hydrogen, and the second carrier gas comprises argon;
channeling neutral particles of the second non-oxidizing plasma through the separation grid to the surface of the substrate; and
treating the substrate by exposing the substrate to the neutral particles of the second non-oxidizing plasma in the processing chamber to at least partially remove the oxidation layer from the substrate.

US Pat. No. 10,431,468

LOCATION-SPECIFIC TUNING OF STRESS TO CONTROL BOW TO CONTROL OVERLAY IN SEMICONDUCTOR PROCESSING

Tokyo Electron Limited, ...

1. A method for correcting wafer overlay, the method comprising:receiving a substrate having a working surface and having a backside surface opposite to the working surface, the substrate having an initial overlay error resulting from one or more micro fabrication processing steps that have been executed to create at least part of a semiconductor device on the working surface of the substrate;
receiving an initial bow measurement of the substrate that maps z-height deviations on the substrate relative to one or more reference z-height values;
generating an overlay correction pattern that defines adjustments to internal stresses at specific locations on the substrate based on the initial bow measurement of the substrate, wherein a first given location on the substrate has a different internal stress adjustment defined as compared to a second given location on the substrate in the overlay correction pattern; and
physically modifying internal stresses on the substrate at specific locations on the substrate according to the overlay correction pattern resulting in a modified bow of the substrate, the substrate with the modified bow having a second overlay error, the second overlay error having reduced overlay error as compared to the initial overlay error.

US Pat. No. 10,431,467

MODULE INCLUDING METALLIZED CERAMIC TUBES FOR RF AND GAS DELIVERY

Lam Research Corporation,...

1. A module useful for processing semiconductor substrates in a vacuum chamber including a processing zone in which a semiconductor substrate may be processed, the module comprising:a ceramic body;
a stem made of ceramic material having a flange bonded to the ceramic body; and
at least one metallized ceramic tube configured to supply gas to the ceramic body and supply power to an electrode embedded in the ceramic body.

US Pat. No. 10,431,466

HYDROGENATION AND NITRIDIZATION PROCESSES FOR MODIFYING EFFECTIVE OXIDE THICKNESS OF A FILM

APPLIED MATERIALS, INC., ...

1. A method of forming a structure in a semiconductor device, the method comprising:depositing a metal nitride layer on a high-k dielectric layer formed on a semiconductor substrate to form a portion of the structure, wherein the semiconductor substrate is disposed over a substrate supporting surface of a pedestal disposed in a first processing chamber in a cluster tool;
sequentially exposing an exposed surface of the deposited metal nitride layer formed on the semiconductor substrate to a non-oxidizing plasma-excited hydrogen species followed by a plasma-excited nitrogen species while a bias is applied to the semiconductor substrate, which is disposed over a substrate supporting surface of a pedestal disposed in a second processing chamber in the cluster tool;
depositing a silicon-containing layer on the exposed surface;
performing a thermal anneal process on the silicon-containing layer; and
removing the silicon-containing layer.

US Pat. No. 10,431,465

SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor structure, comprising:a semiconductor substrate;
a trench disposed in the semiconductor substrate; and
a doped semiconductor material filled in the trench, wherein a top surface of the doped semiconductor material is planar with a top surface of the semiconductor substrate, and a dopant in the doped semiconductor material has a decreasing concentration gradient in a depth direction of the trench,
wherein the dopant in a top portion of the doped semiconductor material has a concentration between 15 wt % and 40 wt % and the dopant in a bottom portion of the doped semiconductor material is between 0 wt % and 35 wt %.

US Pat. No. 10,431,464

LINER PLANARIZATION-FREE PROCESS FLOW FOR FABRICATING METALLIC INTERCONNECT STRUCTURES

International Business Ma...

1. A method for fabricating a device, comprising:forming a dielectric layer on a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
depositing a first layer of metallic material over the dielectric layer to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening;
depositing a second layer of metallic material to fill the opening with metallic material;
removing an overburden portion of the second layer of metallic material by planarizing the second layer of metallic material down to an overburden portion of the liner layer on the upper surface of the dielectric layer;
applying a surface treatment to the overburden portion of the liner layer on the upper surface of the dielectric layer to convert the overburden portion of the liner layer into a layer of metal nitride material, wherein the portion of the liner layer deposited on exposed surfaces within the opening is not converted into the layer of metal nitride material; and
wherein applying a surface treatment comprises performing a plasma nitridation surface treatment to infuse nitrogen atoms into the overburden portion of the liner layer; and selectively etching away the layer of metal nitride material.

US Pat. No. 10,431,463

SUBSTRATE HOLDING DEVICE, LITHOGRAPHY APPARATUS, AND ARTICLE PRODUCTION METHOD

Canon Kabushiki Kaisha, ...

1. A substrate holding device configured to hold a substrate, the substrate holding device comprising:a holding member including a center part having a hole through which gas is exhausted from a space between the substrate and the holding member and an outer peripheral part surrounding the center part;
a moving unit configured to relatively move the substrate and the holding member in a direction perpendicular to a substrate holding surface of the center part; and
a seal member provided on the outer peripheral part, configured to seal the space and configured to be deformed in response to a distance between the substrate and the holding member relatively moved by the moving unit,
wherein at least one of the outer peripheral part and the seal member has a through hole, and
wherein a first end of the through hole faces the space and a second end of the through hole faces an atmosphere.

US Pat. No. 10,431,462

PLASMA ASSISTED DOPING ON GERMANIUM

Lam Research Corporation,...

1. A method for forming a junction in a germanium (Ge) layer of a substrate, comprising:arranging the substrate in a processing chamber;
forming the junction in the germanium (Ge) layer by plasma doping including:
one or more plasma treatments using a first plasma gas mixture including a phosphorus (P) gas species during a predetermined P doping period; and
one or more plasma treatments using a second plasma gas mixture including an antimony (Sb) gas species during a predetermined Sb doping period; and
annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.

US Pat. No. 10,431,460

METHOD FOR PRODUCING SIC COMPOSITE SUBSTRATE

SHIN-ETSU CHEMICAL CO., L...

1. A method for producing a SiC composite substrate comprising a monocrystalline SiC layer on a polycrystalline SiC substrate, the method comprising the steps of in order: providing a monocrystalline SiC layer on the front side of a support substrate that is made of silicon and has a silicon oxide film on front and back sides thereof so as to produce a monocrystalline SiC layer carrier; removing some or all of the thickness of the silicon oxide film over some region or all of the back side of the support substrate in the monocrystalline SiC layer carrier so as to impart warpage to the monocrystalline SiC layer carrier; depositing polycrystalline SiC onto the monocrystalline SiC layer by chemical vapor deposition so as to form a polycrystalline Sic substrate; and physically and/or chemically removing the support substrate.

US Pat. No. 10,431,459

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device, the method comprising:forming an etching target layer on a substrate;
forming an upper mask layer on the etching target layer;
forming a plurality of preliminary mask patterns on the upper mask layer, two neighboring preliminary mask patterns of the plurality of preliminary mask patterns defining a preliminary opening; and
performing an ion beam etching process on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns,
wherein the first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

US Pat. No. 10,431,458

MASK SHRINK LAYER FOR HIGH ASPECT RATIO DIELECTRIC ETCH

LAM RESEARCH CORPORATION,...

1. A method of forming an etched feature in a dielectric-containing stack on a semiconductor substrate, the method comprising:(a) receiving a substrate comprising the dielectric-containing stack and a mask layer positioned over the dielectric-containing stack, the mask layer including a pattern comprising openings in the mask layer;
(b) depositing a mask shrink layer on the mask layer, wherein the mask shrink layer is formed through a vapor deposition process and comprises tungsten, and wherein the mask shrink layer lines the openings in the mask layer;
(c) generating an etching plasma comprising an etching reactant, exposing the substrate to the etching plasma, and etching the feature in the dielectric-containing stack, wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,431,457

METHOD FOR FORMING PATTERNED STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for forming a patterned structure, comprising:providing a layout pattern, wherein the layout pattern comprises:
a plurality of first lines, wherein each of the first lines is elongated in a first direction; and
a plurality of second lines, wherein each of the second lines is elongate in a second direction, wherein the first direction is orthogonal to the second direction;
decomposing the layout pattern for forming:
a first mask comprising:
a plurality of first line patterns corresponding to the first lines; and
a first block pattern corresponding to the second lines; and
a second mask comprising:
a plurality of second line patterns corresponding to the second lines; and
a second block pattern corresponding to the first lines; and
performing a first photolithography process with the first mask and a second photolithography process with the second mask for forming a patterned structure comprising:
a plurality of first line structures, wherein each of the first line structures is elongated in the first direction, and the first line structures are defined by and structurally confined to a region where the first line patterns and the second block pattern overlap with one another; and
a plurality of second line structures, wherein each of the second line structures is elongated in the second direction, and the second line structures are defined by and structurally confined to a region where the second line patterns and the first block pattern overlap with one another.

US Pat. No. 10,431,456

IMPRINT APPARATUS AND METHOD

SAMSUNG DISPLAY CO., LTD....

1. An imprint method comprising:applying a material layer for forming a patterned layer having a pattern, to a substrate;
feeding a stamp film including a stamp pattern corresponding to the pattern of the patterned layer, along a pressure roller and an idle roller, to dispose the stamp pattern of the stamp film facing the material layer on the substrate;
forming the patterned layer having the pattern, comprising:
the pressure roller pressing the stamp film including the stamp pattern toward the material layer on the substrate to contact the stamp pattern of the stamp film with the material layer and form the pattern in the material layer,
curing the material layer in contact with the stamp pattern of the stamp film, and
moving the pressure roller and the idle roller to peel the stamp film including the stamp pattern off the material layer which is cured, by a peeling force, to form the patterned layer having the pattern from the material layer which is cured; and
detecting a defect in the pattern of the formed patterned layer, during the peeling of the stamp film off the material layer which is cured, by sensing the peeling force in real time by a pressure sensor connected to the pressure roller.

US Pat. No. 10,431,455

FEMTOSECOND LASER-INDUCED FORMATION OF SINGLE CRYSTAL PATTERNED SEMICONDUCTOR SURFACE

THE REGENTS OF THE UNIVER...

1. A method of manufacturing a surface corrugation in a material using light energy, said method comprising:applying a plurality of laser energy pulses focused at a surface of the material, each of said plurality of laser energy pulses being about 150 femtoseconds in duration, said plurality of laser energy inducing point defect accumulation and diffusion in the material resulting in epitaxial surface corrugation, the epitaxial surface corrugation having a period less than 0.3 times a wavelength of the laser.

US Pat. No. 10,431,454

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

Nuvoton Technology Corpor...

1. A semiconductor substrate, comprising:a base;
a buffer layer, disposed on the base, wherein doped regions are disposed in a portion of a surface of the buffer layer and the doped regions are separated from each other;
a mask layer, disposed on the buffer layer and located on the doped regions; and
a first GaN layer, disposed on the buffer layer and covering the mask layer.

US Pat. No. 10,431,453

ELECTRIC FIELD ASSISTED PLACEMENT OF NANOMATERIALS THROUGH DIELECTRIC ENGINEERING

INTERNATIONAL BUSINESS MA...

1. A method of positioning nanomaterials comprising:patterning guiding dielectric structures from a single material layer on a substrate including electrodes, wherein an exposed portion of the substrate between the guiding dielectric structures provides a deposition surface;
producing an electric field by the electrodes that is attenuated through the guiding dielectric structures to create an attractive dielectrophoretic force that guides at least one nanostructure to be positioned directly on the deposition surface of the substrate, the at least one nanostructure abutting the guiding dielectric structures, but is not positioned directly atop the guiding dielectric structures; and
removing the guiding dielectric surfaces.

US Pat. No. 10,431,452

PROTECTIVE FILM FORMING METHOD

Tokyo Electron Limited, ...

1. A protective film forming method, comprising steps of:causing an entire surface of a silicon-containing underfilm to be terminated with fluorine by supplying an activated fluorine-containing gas to the silicon-containing underfilm formed on a substrate having a surface including a plurality of recesses and a flat surface provided between the adjacent recesses, the substrate being provided in a process chamber;
nitriding a surface of the silicon-containing underfilm formed on the flat surface of the substrate by supplying a nitriding gas converted to plasma to the silicon-containing underfilm terminated with fluorine such that a silicon adsorption site is formed on the surface of the silicon-containing underfilm formed on the flat surface of the substrate;
adsorbing a silicon-containing gas on the silicon adsorption site by supplying the silicon-containing gas to the silicon-containing underfilm;
changing a rotational speed of the turntable between the steps of causing the entire surface of the silicon-containing underfilm to be terminated with fluorine and nitriding the surface of the silicon-containing underfilm,
wherein the substrate is arranged on a turntable along a circumferential direction thereof,
wherein a fluorine-containing gas supply region configured to supply the activated fluorine-containing gas to the substrate, a silicon-containing gas supply region configured to supply the silicon-containing gas to the substrate, and a nitriding gas supply region configured to supply the nitriding gas to the substrate are arranged above the turntable, along the circumferential direction, and apart from each other,
wherein the step of causing the entire surface of the silicon-containing underfilm to be terminated with fluorine is performed by stopping the supply of the silicon-containing gas in the silicon-containing gas supply region and the supply of the nitriding gas in the nitriding gas supply region and supplying the activated fluorine-containing gas to the substrate in the fluorine-containing gas supply region while rotating the turntable at least one time,
wherein the step of nitriding the surface of the silicon-containing underfilm is performed by stopping the supply of the activated fluorine-containing gas in the fluorine-containing gas supply region and supplying the nitriding gas converted to the plasma in the nitriding gas supply region while rotating the turntable a plurality of times, and
wherein the step of adsorbing the silicon-containing gas on the silicon adsorption site is performed by stopping the supply of the activated fluorine-containing gas in the fluorine-containing gas supply region and supplying the silicon-containing gas to the substrate in the silicon-containing gas supply region while rotating the turntable a plurality of times.

US Pat. No. 10,431,450

FILM FORMING METHOD

TOKYO ELECTRON LIMITED, ...

1. A film forming method for a target object including a main surface and grooves formed in the main surface, the method comprising:accommodating the target object in a processing chamber of a plasma processing apparatus;
after the accommodating, supplying a first gas into the processing chamber; and
after the supplying the first gas, supplying a second gas and a high frequency power for plasma generation in the processing chamber by using a gas that includes the second gas in the processing chamber,
wherein:
the first gas comprises an oxidizing agent that does not include a hydrogen atom;
the second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom;
a film containing silicon and oxygen is selectively formed on the main surface of the target object except the grooves; and
a temperature of the target object during the supplying the second gas is lower than 450° C.

US Pat. No. 10,431,449

MICROELECTRONIC SYSTEMS CONTAINING EMBEDDED HEAT DISSIPATION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, Inc., Austin, T...

1. A microelectronic system, comprising:a substrate having a tunnel therein;
a microelectronic component attached to the substrate at a location enclosing an end of the tunnel;
a solder material attaching the microelectronic component to the substrate, the solder material having a first thermal conductivity; and
an embedded heat dissipation structure at least partially contained within the tunnel, the embedded heat dissipation structure comprising:
a thermally-conductive component bond layer in contact with the microelectronic component and having a second thermal conductivity substantially equivalent to or exceeding the first thermal conductivity;
a thermal conduit member at least partially contained within the tunnel and bonded to the microelectronic component through the thermally-conductive component bond layer; and
a conduit bond layer extending around a periphery of the thermal conduit member and bonding the thermal conduit member to inner sidewalls of the substrate defining the tunnel.

US Pat. No. 10,431,448

WET ETCHING METHOD, SUBSTRATE LIQUID PROCESSING APPARATUS, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A wet etching method for wet-etching a substrate including a first surface and a second surface opposite to the first surface and formed with a first layer as a lower layer and a second layer as an upper layer that are laminated on at least a peripheral edge portion of the first surface of the substrate, the method comprising:a process of rotating the substrate;
a process of supplying a chemical liquid capable of etching both the first layer and the second layer, to the first surface of the rotating substrate; and
a first process of supplying an etching inhibiting liquid to the second surface of the substrate while supplying the chemical liquid to the substrate;
wherein in the first process, the etching inhibiting liquid is supplied while rotating the substrate such that the etching inhibiting liquid wraps around the first surface through an edge of the substrate and reaches a first region extending from the edge of the substrate on the peripheral edge portion of the first surface to a first radial position located radially inward from the edge on the first surface.

US Pat. No. 10,431,447

POLYSILICON CHIP RECLAMATION ASSEMBLY AND METHOD OF RECLAIMING POLYSILICON CHIPS FROM A POLYSILICON CLEANING APPARATUS

HEMLOCK SEMICONDUCTOR COR...

1. A polysilicon chip reclamation assembly comprising:a polysilicon cleaning apparatus configured to clean a plurality of bodies of polysilicon;
a plurality of polysilicon chips generated from the bodies of polysilicon during cleaning thereof, wherein each of the plurality of polysilicon chips has a longest dimensional length ranging from 0.1 mm to 25.0 mm;
a polysilicon apparatus drain line configured to route the plurality of polysilicon chips from the polysilicon cleaning apparatus to a main chip drain line, wherein the main chip drain line is oriented at a downward slope away from the polysilicon apparatus drain line;
a fluid source fluidly coupled to the main chip drain line and configured to inject a fluid into the main chip drain line to drive the plurality of polysilicon chips through the main chip drain line;
a chip collection tank, wherein the main chip drain line comprises an outlet proximate the chip collection tank, the outlet configured to direct the plurality of polysilicon chips into the chip collection tank; and
a chip routing line extending between an outlet of the chip collection tank and a conveyor.

US Pat. No. 10,431,446

WET PROCESSING APPARATUS

NATIONAL INSTITUTE OF ADV...

1. A heating wet processing method, comprising:a placing step of placing a plate-shaped object to be processed on a stage by mounting the object on engaging pins separated from one another at predetermined intervals in a circumferential direction around a condensing plate, the object being mounted on the engaging pins in a state when a surface of the object is oriented upward, and;
a supplying step of supplying a processing liquid from above the stage to the surface of the object placed on the stage; and
a processing step of heating at least an interface between the object and the processing liquid by emitting light:
to the condensing plate to irradiate the object with the light condensed by the condensing plate from a position facing the object engaged by the engaging pins in a state, and
from a position blocked with respect to the stage with a blocking member and irradiate the light to the condensing plate, when the supplying step is supplying the processing liquid, wherein the condensing plate is mounted on the blocking member.

US Pat. No. 10,431,444

SYSTEMS AND METHODS FOR AUTOMATED ANALYSIS OF OUTPUT IN SINGLE PARTICLE INDUCTIVELY COUPLED PLASMA MASS SPECTROMETRY AND SIMILAR DATA SETS

PerkinElmer Health Scienc...

1. A method for automated analysis of spectrometry data the method comprising:(a) accessing, by a processor of a computing device, a sequence of pulse count values acquired by a spectrometer to produce, for each of at least one given peak corresponding to particles comprising an analyte and being present in a sample, pulse count values being greater than a threshold background intensity value;
(b) determining, by the processor, from a first array of the pulse count values, a threshold for identifying pulse count values as corresponding to a peak signal, and adjusting the threshold based on remaining pulse count values following each of a series of iterations, with a given subsequent iteration including pulse count values not identified as corresponding to a peak in a preceding iteration, wherein a final background threshold is determined upon convergence of the threshold within acceptable tolerance;
(c) building, by the processor, from the first array of the pulse count values, a smoothed data array comprising smoothed values and identifying, as identified peaks, a subset of the smoothed values that are larger than both subsequent and preceding smoothed values of the smoothed data array and also larger than the final background threshold; and
(d) automatically determining, by the processor, based on the identified peaks, at least one of:
(A) a particle mass distribution and/or particle size distribution for the particles in the sample; and
(B) statistical data for the particles in the sample.

US Pat. No. 10,431,443

DEVICE FOR MANIPULATING CHARGED PARTICLES

Shimadzu Research Laborat...

1. A device for manipulating charged particles, the device comprising:a series of electrodes arranged so as to form a channel for transportation of the charged particles;
a power supply unit adapted to provide supply voltages to said electrodes so as to create a non-uniform high-frequency electric field within said channel, the pseudopotential of said field having two or more local maxima along the length of said channel for transportation of charged particles, at least within a certain interval of time, wherein transportation of the charged particles along the length of the channel is provided by transposition of the at least two of said maxima of the pseudopotential such that the at least two of said maxima are caused to travel with time along the channel, at least within a certain interval of time and at least within a part of the length of the channel, wherein the supply voltages are high-frequency voltages;
wherein the device is configured to transport ions/charged particles through a viscous gas region, wherein the gas pressure within said viscous gas region meets the condition ?/L<0.01, where L is a width of the transport channel (m) and ? is the mean free path of molecules of said viscous gas (m).

US Pat. No. 10,431,442

ELECTROSTATIC TRAP MASS SPECTROMETER WITH IMPROVED ION INJECTION

LECO Corporation, St. Jo...

1. A method of mass spectral analysis comprising:injecting a continuous ion beam into a multiplexed analytical electrostatic trap (i) including a pair of concentric, cylindrical trap electrodes having static and non-ramped potentials, the pair of cylindrical trap electrodes including a set of aligned slits, and (ii) defining a cylindrical electrostatic field volume, the cylindrical electrostatic field volume including multiple volumes of an electrostatic trapping field, wherein the continuous ion beam is injected through the aligned slits of the pair of cylindrical trap electrodes.

US Pat. No. 10,431,441

REDUCING CALIBRATION OF COMPONENTS IN AN IMAGING PLATE SCANNER

PALODEX GROUP OY, Tuusul...

1. A photomultiplier tube for use in an imaging plate scanner, the photomultiplier tube comprising:a housing having a window;
a focusing electrode located in the housing;
an electron multiplier dynode located in the housing;
an anode;
a cathode and
a memory storing parameters.

US Pat. No. 10,431,440

METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE

APPLIED MATERIALS, INC., ...

1. A process chamber, comprising:a chamber body defining an interior volume;
a substrate support to support a substrate within the interior volume;
a plurality of cathodes coupled to the chamber body and having a corresponding plurality of targets to be sputtered onto the substrate;
a shield rotatably coupled to an upper portion of the chamber body and having at least one hole to expose at least one of the plurality of targets to be sputtered and at least one pocket disposed in a backside of the shield to accommodate and cover at least another one of the plurality of targets not to be sputtered,
wherein a sputtering surface of at least one of the plurality of targets extends beyond the lowermost surface of the shield when the shield is in a retracted position,
wherein the shield is configured to rotate about and linearly move along a central axis of the process chamber, and
wherein the at least another one of the plurality of targets extends at least partially into the at least one pocket when the shield is in a retracted position;
a chamber body adapter coupled to an upper portion of the chamber body, wherein the chamber body adapter is grounded; and
a plurality of grounding rings disposed between the shield and the chamber body adapter to directly ground the shield to the chamber body adapter when the shield is in a retracted position.

US Pat. No. 10,431,436

METHOD AND SYSTEM OF MONITORING AND CONTROLLING DEFORMATION OF A WAFER SUBSTRATE

SPTS TECHNOLOGIES LIMITED...

1. A method of monitoring and controlling deformation of an electrically insulating wafer substrate during plasma etching of the wafer substrate, the method comprising:disposing an electrically insulating wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the electrically insulating wafer substrate is exposed;
passing a process gas into the process chamber;
applying a radio frequency bias voltage to the platen assembly;
etching the exposed entire upper surface of the electrically insulating wafer substrate by generating a plasma within the process chamber;
determining, during said etching, a warping of the electrically insulating wafer substrate relative to the platen assembly by monitoring a voltage difference between the platen assembly and the process chamber;
attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.

US Pat. No. 10,431,435

WAFER CARRIER WITH INDEPENDENT ISOLATED HEATER ZONES

Applied Materials, Inc., ...

1. An apparatus comprising:a puck to carry a workpiece for fabrication processes;
a heater plate having a plurality of thermally isolated blocks each thermally coupled to the puck, and each having a heater to heat a respective block of the heater plate; and
a cooling plate fastened to and thermally coupled to the heater plate, the cooling plate having a cooling channel to carry a heat transfer fluid to transfer heat from the cooling plate,
wherein each heater extends into a corresponding bore of the cooling plate,
wherein the cooling channel is on each of two opposite sides of each thermally isolated block and thermally coupled to each thermally isolated block to remove heat from the two sides of each thermally isolated block through a heat transfer surface, wherein the heat transfer surface is adjacent to and surrounds the heater of the respective block, and wherein the cooling plate is laterally adjacent to a portion of each of the plurality of thermally isolated blocks.

US Pat. No. 10,431,433

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a chamber main body defining a chamber;
a stage, provided in the chamber, including a lower electrode and an electrostatic chuck provided on the lower electrode, on which a focus ring is arranged to surround a substrate mounted on the electrostatic chuck;
a first high frequency power supply configured to supply a first high frequency power for generating plasma of a gas in the chamber;
a second high frequency power supply configured to supply a second high frequency power for ion attraction to the lower electrode;
a DC power supply configured to generate a negative DC voltage to be applied to the focus ring in order to correct inclination of an incident direction of ions to an edge region of the substrate mounted on the electrostatic chuck with respect to a vertical direction;
a switching unit configured to stop the application of the DC voltage to the focus ring; and
a controller configured to control one or both of the high frequency power supply and the second high frequency power supply and control the switching unit,
wherein the controller controls one or both of the first high frequency power supply and the second high frequency power supply to periodically stop the supply of one or both of the first high frequency power and the second high frequency power, and
the controller also controls the switching unit to apply the DC voltage to the focus ring from a first time after a predetermined period of time in which a self-bias voltage of the lower electrode is decreased from a start point of each period in which one or both of the first high frequency power and the second high frequency power are supplied and to stop the application of the DC voltage to the focus ring during each period in which the supply of one or both of the first high frequency power and the second high frequency power is stopped.

US Pat. No. 10,431,432

PLASMA TREATMENT SYSTEM INCLUDING COVER PLATE TO INSULATE WINDOW

SAMSUNG ELECTRONICS CO., ...

1. A plasma treatment system, comprising:a window;
an antenna electrode disposed on the window; and
a cover plate disposed between the antenna electrode and the window, the cover plate extending to a side surface of the window to cover a top surface and at least a portion of the side surface of the window,
wherein the cover plate comprises:
a disk portion disposed on the window to have an opening partially exposing the window;
an upper edge end portion connected to an edge of a top surface of the disk portion to enclose the antenna electrode; and
upper blocks upwardly protruding from the disk portion, the upper blocks disposed between the opening and the antenna electrode and the upper blocks being spaced apart from each other in a substantially equal interval.

US Pat. No. 10,431,431

GAS SUPPLY DELIVERY ARRANGEMENT INCLUDING A GAS SPLITTER FOR TUNABLE GAS FLOW CONTROL

LAM RESEARCH CORPORATION,...

1. A gas supply delivery arrangement for supplying process gas to a chamber of a plasma processing system wherein a semiconductor substrate is processed with gases introduced through at least first, second, and third gas injection zones, comprising:a plurality of process gas supply inlets and a plurality of tuning gas inlets; a mixing manifold comprising a plurality of gas supply sticks each of which is adapted to provide fluid communication with a respective process gas supply;
a plurality of tuning gas sticks each of which is adapted to provide fluid communication with a respective tuning gas supply;
a first gas outlet adapted to deliver gas to the first gas injection zone, a second gas outlet adapted to deliver gas to the second gas injection zone, and a third gas outlet adapted to deliver gas to the third gas injection zone;
a gas splitter in fluid communication with the mixing manifold, the gas splitter including a first valve arrangement which splits mixed gas exiting the mixing manifold into:
a first mixed gas which can be supplied to the first gas outlet; and
a second mixed gas which can at different times be supplied to:
only the second gas outlet;
only the third gas outlet; and
the second and third gas outlets; and
a second valve arrangement which, at different times, selectively delivers tuning gas from the tuning gas sticks to:
only the first gas outlet;
only the second gas outlet;
only the third gas outlet;
only the first and second gas outlets;
only the first and third gas outlets;
only the second and third gas outlets; and
the first, second, and third gas outlets.

US Pat. No. 10,431,430

PLASMA TREATMENT OF AN ELASTOMERIC MATERIAL FOR ADHESION

NIKE, Inc., Beaverton, O...

1. A plasma treatment system, the plasma treatment system comprising:a first plasma torch;
a first multi-axis conveyance mechanism coupled with the first plasma torch, the first multi-axis conveyance mechanism able to position the first plasma torch within a 20-40 millimeter offset height range from a surface of an elastomeric component;
a component identification mechanism; and
computer readable media having instructions embodied thereon that when executed by a processor:
generate a tool path for the first multi-axis conveyance mechanism based on an input from the component identification mechanism; and
control the first plasma torch and the first multi-axis conveyance mechanism to apply plasma to the surface while maintaining the 20-40 millimeter offset height range to form an altered region extending from the surface into the elastomeric component.

US Pat. No. 10,431,429

SYSTEMS AND METHODS FOR RADIAL AND AZIMUTHAL CONTROL OF PLASMA UNIFORMITY

Applied Materials, Inc., ...

1. A system that generates a plasma for processing a workpiece, comprising:a process chamber that is operable to be evacuated;
a housing that defines a waveguide cavity;
a first conductive plate disposed within the housing, wherein the first conductive plate faces the process chamber and is disposed on a distal side of the waveguide cavity from the process chamber;
one or more adjustment devices that couple with the first conductive plate and the housing, wherein the one or more adjustment devices are operable to adjust at least a position of the first conductive plate within a range of positions;
a second conductive plate, coupled with the housing and interposed between the waveguide cavity and the process chamber, the second conductive plate forming a plurality of apertures therein for allowing electromagnetic radiation within the waveguide cavity to propagate, through the apertures, into the process chamber;
a dielectric plate that seals off the process chamber from the waveguide cavity such that the waveguide cavity is not evacuated when the process chamber is evacuated; and
one or more electronics sets that transmit the electromagnetic radiation into the waveguide cavity, such that the plasma forms when at least one process gas is within the process chamber, and the electromagnetic radiation propagates into the process chamber from the waveguide cavity.

US Pat. No. 10,431,428

SYSTEM FOR PROVIDING VARIABLE CAPACITANCE

RENO TECHNOLOGIES, INC.

21. A semiconductor processing tool comprising:a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising:
an RF input configured to be operably coupled to an RF source;
an RF output operably coupled to the plasma chamber, the plasma chamber having a variable impedance;
electronically variable capacitors (EVCs) each comprising discrete capacitors operably coupled in parallel, the discrete capacitors comprising:
fine capacitors each having a capacitance value substantially similar to a fine capacitance value; and
coarse capacitors each having a capacitance value substantially similar to a coarse capacitance value, the coarse capacitance value being greater than the fine capacitance value;
wherein each EVC has a variable total capacitance that is increased when the discrete capacitors are switched in and decreased when the discrete capacitors are switched out; and
a control circuit operably coupled to the EVCs, the control circuit configured to determine the variable impedance of the plasma chamber;
the control circuit further configured to:
determine, based on the determined variable impedance, a total number of coarse capacitors of the coarse capacitors to have switched in;
determine, based on the determined variable impedance, a total number of fine capacitors of the fine capacitors to have switched in; and
cause an impedance match by causing the total number of coarse capacitors and the total number of fine capacitors to be switched in;
wherein the increase of the variable total capacitance of each EVC is achieved by switching in more of the coarse capacitors or more of the fine capacitors than are already switched in without switching out a coarse capacitor that is already switched in.

US Pat. No. 10,431,427

MONOPOLE ANTENNA ARRAY SOURCE WITH PHASE SHIFTED ZONES FOR SEMICONDUCTOR PROCESS EQUIPMENT

Applied Materials, Inc., ...

1. A plasma reactor comprising:a chamber body having an interior space that provides a plasma chamber;
a gas distribution port to deliver a processing gas to the plasma chamber;
a workpiece support to hold a workpiece;
an antenna array comprising a plurality of monopole antennas extending partially into the plasma chamber, wherein the plurality of monopole antennas are divided into a plurality of groups of monopole antennas; and
an AC power source to supply a first AC power to the plurality of monopole antennas, wherein the AC power source is configured to generate AC power on a plurality of power supply lines at a plurality of different phases, and different groups of monopole antennas are coupled to different power supply lines.

US Pat. No. 10,431,426

GAS PLENUM ARRANGEMENT FOR IMPROVING ETCH NON-UNIFORMITY IN TRANSFORMER-COUPLED PLASMA SYSTEMS

LAM RESEARCH CORPORATION,...

1. A gas plenum arrangement for a substrate processing system, the gas plenum arrangement comprising:a gas plenum body having an inner opening and an outer edge, wherein
the gas plenum body is arranged to define a gas plenum between a coil and a processing chamber, and
the coil is arranged around and outside of the outer edge of the gas plenum body; and
a plurality of discrete flux attenuating portions, wherein
the plurality of discrete flux attenuating portions is arranged outside of the outer edge of the gas plenum body and extends radially outward from the outer edge of the gas plenum body, and
the plurality of discrete flux attenuating portions (i) overlaps, in a vertical direction, some angular portions of the coil outside of the outer edge of the gas plenum body and (ii) does not overlap, in the vertical direction, other angular portions of the coil outside of the outer edge of the gas plenum body.

US Pat. No. 10,431,425

POLY-PHASED INDUCTIVELY COUPLED PLASMA SOURCE

Tokyo Electron Limited, ...

1. A system for plasma processing comprising:a metal source configured to supply a metal for ionized physical vapor deposition on a substrate in a process chamber;
a high-density plasma source configured to generate a dense plasma, the high-density plasma source comprising a plurality of individual inductively coupled antennas arranged in a pattern around an axis in the process chamber;
a substrate bias source configured to provide a potential necessary to thermalize and further ionize the plasma;
the high density plasma source including a control system and matching network coupled with the plurality of antennas and configured to deliver power to each individual antenna at an individual phase orientation determined according to a phase arrangement;
the high density plasma source further configured, according to the phase arrangement, for dynamically varying the delivery of power and phase orientation over time to each individual antenna in the process chamber according to a phase pattern to dynamically vary the radiation pattern delivered to the plasma, and for delivering power, in the phase pattern, to a first group of antennas at a synchronized phase at a first time period, and then for sequentially delivering power to other different groups of the antennas at a synchronized phase progressively in the process chamber at further sequential time periods following the first time period for consistent plasma processing.

US Pat. No. 10,431,424

PARASITIC CAPACITANCE COMPENSATION CIRCUIT

RENO TECHNOLOGIES INC.

7. A semiconductor processing tool comprising:a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising:
an RF input configured to be operably coupled to an RF source;
an RF output operably coupled to the plasma chamber; and
an electronically variable capacitor (EVC), the EVC comprising discrete capacitors, each discrete capacitor having a corresponding switch for switching in and out the discrete capacitor, each corresponding switch comprising a parasitic capacitance compensation circuit comprising:
a first inductor operably coupled between a first terminal and a second terminal of the corresponding switch, the first inductor causing a first inductance between the first and second terminals, the first and second terminals configured to be operably coupled, respectively, to first and second terminals of the switch; and
a second inductor operably coupled between the first and second terminals and parallel to the first inductor, the second inductor causing a second inductance between the first and second terminals of the switch when the second inductor is switched in, the second inductor being switched in when a peak voltage on the first and second terminals falls below a first voltage;
wherein the first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage; and
wherein the first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

US Pat. No. 10,431,423

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

Taiwan Semiconductor Manu...

1. A method of semiconductor device fabrication, comprising:identifying a first template having a first layout pattern with a first pattern density (PD) and a second template having a second layout pattern with a second PD less than the first PD;
splitting the first template into a plurality of subset templates, wherein a first subset template has a first subset PD that is outside of a PD target, and wherein the second PD is outside of the PD target;
performing a PD uniformity (PDU) optimization to both the first subset template and the second template to make the first subset PD and the second PD satisfy the PD target; and
performing multiple individual electron beam (e-beam) lithography exposure processes with an e-beam lithography tool to a semiconductor substrate, using respective ones of the subset templates.

US Pat. No. 10,431,422

METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY

D2S, Inc., San Jose, CA ...

1. A system for fracturing or mask data preparation, the system comprising:a device configured to determine pattern exposure information that forms a reticle pattern on a resist-coated reticle with a charged particle beam writer;
wherein the reticle is to be used to form a wafer pattern on a substrate using optical lithography; and
wherein the device configured to determine calculates a sensitivity of the wafer pattern to changes in dimension of the reticle pattern.

US Pat. No. 10,431,421

APPARATUS AND TECHNIQUES FOR BEAM MAPPING IN ION BEAM SYSTEM

VARIAN SEMICONDUCTOR EQUI...

1. An apparatus for monitoring of an ion beam, comprising:a processor; and
a memory unit coupled to the processor, including a display routine, the display routine operative on the processor to manage monitoring of the ion beam, the display routine comprising:
a measurement processor to:
receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan, the fast scan comprising a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction;
receive position information from the detector, the position information comprising a plurality of detector locations, collected at a plurality of instances, wherein the plurality of spot beam profiles correspond to the plurality of detector locations;
determine a spot beam center position at the plurality of detector locations;
determine a difference between the spot beam center position and an ideal center position at a plurality of detector locations; and
send a signal to display the difference as a function of detector location.

US Pat. No. 10,431,420

POST COLUMN FILTER WITH ENHANCED ENERGY RANGE

FEI Company, Hillsboro, ...

1. A method of operating a Post Column Filter (PCF) in a Scanning/Transmission Electron Microscope, the method comprising:receiving, at an entrance plane, an incoming beam of electrons;
dispersing, by an electrostatic energy dispersive device, magnetic energy dispersive device, or combination of electrostatic and magnetic energy dispersive device, the incoming beam of electrons into an energy dispersed beam of electrons;
disposing a first plurality of quadrupoles between the entrance plane and a slit plane;
based on the Post Column Filter operating in an electron energy loss spectroscopy (EELS) mode:
exciting one or more quadrupoles of the first plurality of quadrupoles at a first excitation level, wherein the first excitation level does not enlarge the energy dispersion of the energy dispersed beam of electrons; and
forming an image of the energy dispersed beam of electrons on an image plane, the image being an EELS spectrum; and
based on the Post Column Filter operating in an energy filtering transmission electron microscope (EFTEM) mode:
including a slit at the slit plane in an optical path;
exciting one or more quadrupoles of the first plurality of quadrupoles at a second excitation level, the second excitation level different from the first excitation level;
forming an energy dispersed focus of the energy dispersed beam of electrons on the slit at the slit plane; and
enlarging the energy dispersion of the energy dispersed beam of electrons caused by the electrostatic energy dispersive device, magnetic energy dispersive device, or combination of electrostatic and magnetic energy dispersive device based on the one or more first plurality quadrupoles excited at the second excitation level.

US Pat. No. 10,431,419

SPARSE SAMPLING METHODS AND PROBE SYSTEMS FOR ANALYTICAL INSTRUMENTS

Battelle Memorial Institu...

1. A method for sparse sampling with an analytical probe, the method comprising:a) acquiring in a serial mode a plurality of contiguous measured values lying at positions along a scan path extending in a line toward a first direction and having random perturbations in a second direction, wherein the random perturbations are limited within a predetermined distance from the line; and
b) inpainting among the measured values and reconstructing a representation of actual information.

US Pat. No. 10,431,417

CHARGED PARTICLE BEAM DEVICE AND SAMPLE HOLDER

Hitachi High-Technologies...

1. A charged particle beam device comprising a charged particle source, a sample holder placed with a sample thereon, a charged particle beam optical system in which the sample is irradiated with a charged particle emitted from the charged particle source as a charged particle beam, a detector detecting a signal emitted from the sample, and a controller controlling each constituent element, whereinthe sample holder includes
a sample placement portion including a first top surface on which a counterbore part is formed and a rotational axis for rotating the first top surface horizontally, the counterbore part being aligned by being mounted with a sample supporting member having a pattern for alignment including a central marker and a pattern and an address marker for analyzing magnification and a rotation angle,
a sample base portion including an opening through which the sample placement portion is capable of moving vertically and a second top surface around the opening, and
a sample cover portion which has conductivity, includes a window through which the pattern for alignment of the sample supporting member is exposed, and is pressed down toward a direction of the second top surface of the sample base portion, so that a top surface of the sample supporting member placed on the sample placement portion and the second top surface are flush with each other.

US Pat. No. 10,431,416

OBSERVATION SUPPORT UNIT FOR CHARGED PARTICLE MICROSCOPE AND SAMPLE OBSERVATION METHOD USING SAME

HITACHI HIGH-TECHNOLOGIES...

1. An observation support device for observation by irradiating a sample disposed in a non-vacuum space separated by a diaphragm from an inner space of a charged particle optical lens barrel that generates a charged particle beam, with the charged particle beam, comprising:a cover comprising a main body portion which defines a hole portion that forms an observation region where the sample is observed,
wherein the observation support device is disposed directly between the sample and the diaphragm and is mounted on the sample.

US Pat. No. 10,431,414

COMPOSITE TARGET AND X-RAY TUBE WITH THE COMPOSITE TARGET

NanoRay Biotech Co., Ltd....

1. A composite target, being interacted with an electron to generate an X-ray, and an energy of the electron is capable of being changed by controlling a tube voltage at least, and the composite target comprising:a target body;
an interposing layer, connected with the target body; and
a protective layer, disposed at an upstream side of the composite target, and the protective layer facing the electron, a critical energy of electron sputtering of the protective layer is more than a critical energy of electron sputtering of the target body,
wherein the interposing layer moves a highest peak of an energy spectrum of the X-ray toward a high energy direction,
a low energy photon of the X-ray is filtered by the interposing layer, and the low energy photon of the X-ray is capable of being increased by increasing a thickness of the interposing layer,
as the tube voltage is enhanced, an amount of a high energy photon of the X-ray generated is increased.

US Pat. No. 10,431,413

X-RAY SOURCE AND SYSTEM COMPRISING AN X-RAY SOURCE

LIGHTLAB SWEDEN AB, Upps...

1. An x-ray source configured to provide an omnidirectional transmission of x-ray radiation, the x-ray source comprising:an anode;
a field emission cathode;
an evacuated chamber transparent to x-ray radiation, the anode and the field emission cathode being arranged inside of the evacuated envelope,
wherein the evacuated envelope is an extended tube shaped evacuated chamber having an essentially circular symmetry, the field emission cathode is arranged adjacently to an inside surface of the extended tube shaped evacuated chamber, and the anode is centrally arranged inside of the extended tube shaped evacuated chamber,
the field emission cathode surrounds the anode,
the field emission cathode comprises a plurality of ZnO nanostructures selected to be at least 1 micrometer,
the field emission cathode is substantially transparent to X-ray radiation and formed as a transmission cathode, and
the x-ray source is connected to a controllable high voltage source, electrons during operation of the x-ray source are accelerated from the field emission cathode in a direction towards the anode, and x-ray radiation is omnidirectionally irradiated from the anode towards and through the field emission cathode and out from the x-ray source.

US Pat. No. 10,431,412

COMPACT ION BEAM SOURCES FORMED AS MODULAR IONIZER

Massachusetts Institute o...

1. A compact ion beam source comprising:an electron beam unit, comprising:
a modular housing unit that is selectively impermeable to gasses including oxidizing gaseous molecules, the modular housing unit comprising:
a base portion; and
a membrane window made of a single monolayer two-dimensional material and selectively transmissive to electrons;
an electron beam source disposed in the modular housing unit, the electron beam source comprising:
at least one field emitter element disposed over the base portion, comprising:
a first end that is proximate to the base portion; and
a field emitter tip disposed proximate to a second end that is opposite to the first end; and
at least one gate electrode disposed proximate to the second end of the at least one field emitter element, to apply a potential difference proximate to the field emitter tip of the at least one field emitter elements, thereby extracting electrons from the at least one field emitter tip to form an electron beam; and
at least one anode component disposed in the modular housing unit and configured to accelerate the electron beam in a path directed at the membrane window of the modular housing unit.

US Pat. No. 10,431,411

FUSE WITH A THERMOMECHANICAL COMPENSATION ELEMENT

PACIFIC ENGINEERING CORPO...

1. A melting fuse, especially for a motor vehicle that has a high-voltage circuit, said fuse comprising:an electrically insulating housing;
a fusible conductor inside the housing;
two contacts connected with each other by the fusible conductor,
wherein, between two longitudinal areas that are adjacent to each other, the fusible conductor has a rotation point around which the longitudinal areas are rotatable during thermo-mechanical expansion,
wherein the fusible conductor is bent uniformly and free of kinks so as to allow expansions of the fusible conductor caused by thermo-mechanical stresses to be converted into rotational movement,
wherein the fusible conductor is surrounded in the insulating housing by an arc suppressing means, and
wherein the fusible conductor is movable inside the arc suppressing means that surrounds it.

US Pat. No. 10,431,409

ELECTRICAL SWITCHING APPARATUS AND ACCESSORY WIRE RETENTION ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. An accessory wire retention assembly for an electrical switching apparatus, said electrical switching apparatus comprising a housing, separable contacts and an accessory enclosed by the housing, an operating mechanism for opening and closing said separable contacts, and a number of wires adapted to be electrically connected to said accessory, the housing including an interior, an exterior, and an aperture, said wires extending from the interior through said aperture to the exterior, said accessory wire retention assembly comprising:an insert structured to cooperate with the housing and to establish a predetermined position of said wires with respect to said accessory and said aperture; and
a fastening mechanism structured to fasten said wires to said insert to maintain said wires in said predetermined position,
wherein said insert is an elongated molded member comprising a number of molded features structured to cooperate with the housing, said wires, and said fastening mechanism, and
wherein said housing further includes a base and a cover coupled to said base; wherein said aperture extends through said base; and wherein said number of molded features includes a guide portion structured to cooperate with said base to accurately position said insert and said wires proximate said accessary and said aperture.

US Pat. No. 10,431,408

TEMPERATURE SENSITIVE SYSTEM

Tsinghua University, Bei...

5. A temperature sensitive system comprising: a power supply, a detector, a first electrode, a second electrode and an actuator; the power supply, the detector, the first electrode, the second electrode and the actuator are connected to form a loop circuit; wherein the loop circuit is in an on state or an off state, the state of the loop circuit is switched by a deformation of the actuator in response to a temperature change of the actuator; the detector is connected to the actuator in parallel or in series and shows a current change of the loop circuit; wherein the actuator is a free-standing composite structure comprising vanadium dioxide and a plurality of carbon nanotubes.

US Pat. No. 10,431,406

PYROTECHNIC CIRCUIT BREAKER

AUTOLIV DEVELOPMENT AB, ...

1. A pyrotechnic circuit breaker comprising:a housing including a first housing part, a second housing part and at least one cutting chamber;
at least one electrical conductor to be sectioned traversing at least a part of the housing at a level of the at least one cutting chamber, the at least one electrical conductor including a molded-on insert moulded thereon;
at least one punch arranged in the housing facing the at least one cutting chamber and moveable between a first position and a second position, the at least one punch designed to section the at least one electrical conductor during movement of the at least one punch from the first to the second position; and
at least one pyrotechnical actuator for making the at least one punch pass from the first position to the second position when activated;
a seal for sealing the at least one cutting chamber, the seal disposed between the molded-on insert and one of the first housing part and the second housing part,
wherein the seal is compressed directly between the molded-on insert and the one of the first and second housing parts to confine gases in the at least one cutting chamber;
wherein the at least one electrical conductor is elongated in a direction of elongation and wherein the molded on insert surrounds the at least one electrical conductor at a first distinct zone and a second distinct zone, the first and second distinct zones spaced from one another in the direction of elongation.

US Pat. No. 10,431,405

SWITCHING DEVICE COMPRISING A VACUUM TUBE

SIEMENS AKTIENGESELLSCHAF...

1. A switching device comprising:a vacuum tube;
an adjustable drive configured to open and close contacts of the switching device; and
a sensor configured to detect a position of the switching device relative to a mounting location at which the switching device is mounted wherein the detected position is used to adjust the adjustable drive, to at least one of open and close the contacts, wherein the sensor for measuring the position of the switching device is configured to detect a change in an angular position of the switching device.

US Pat. No. 10,431,404

LINKAGE ASSEMBLY AND KEY SWITCH DEVICE HAVING THE SAME

SUNREX TECHNOLOGY CORP., ...

1. A linkage assembly for guiding movement of a key cap in an upright direction relative to a support board between a normal position, where the keycap is distal from the support board, and a pressed position, where the key cap is proximate to the support board, said linkage assembly comprising:a left modular linking member including
a pair of left arms which are spaced apart from each other in a front-to-rear direction, each of said left arms extending in a left-to-right direction and including
a left power segment configured for pivotally coupling with the key cap so as to move therewith in said upright direction,
a left weight segment disposed rightwardly of said left power segment, and having a first left sub-segment, and a second left sub-segment opposite to said first left sub-segment in said front-to-rear direction, and
a left fulcrum area which is disposed between said left weight segment and said left power segment, and which is configured for pivotally coupling to the support board about a first moving axis in said front-to-rear direction, such that in response to downward movement of the key cap from the normal position to the pressed position, said left weight segment is moved angularly and upwardly about the first moving axis, and such that in response to upward movement of the key cap from the pressed position to the normal position, said left weight segment is moved angularly and downwardly about the first moving axis, and
a left crosspiece extending in said front-to-rear direction to interconnect said left power segments of said left arms; and
a right modular linking member including
a pair of right arms which are spaced apart from each other in said front-to-rear direction, each of said right arms extending in said left-to-right direction and including
a right power segment configured for pivotally coupling to the key cap so as to move therewith in said upright direction,
a right weight segment disposed leftwardly of said right power segment, and having a first right sub-segment, and a second right sub-segment opposite to said first right sub-segment in said front-to-rear direction, and
a right fulcrum area which is disposed between said right weight segment and said right power segment, and which is configured for pivotally coupling to the support board about a second moving axis parallel to the first moving axis, such that in response to the downward movement of the key cap, said right weight segment is moved angularly and upwardly about the second moving axis, and such that in response to the upward movement of the key cap, said right weight segment is moved angularly and downwardly about the second moving axis, and
a right crosspiece extending in said front-to-rear direction to interconnect said right power segments of said right arms; and
a pair of synchronizing units which are configured to couple said left weight segments of said left arms respectively to said right weight segments of said right arms so as to synchronize movement of each of said left arms and a corresponding one of said right arms, each of said synchronizing units including
a left upper cavity which is formed in and extends from an upper surface of said first left sub-segment to terminate at a left upward abutment region,
a left lower cavity which is formed in and extends from a lower surface of said second left sub-segment to terminate at a left downward abutment region,
a right upper cavity which is formed in and extends from an upper surface of said first right sub-segment to terminate at a right upward abutment region confronting said left downward abutment region,
a right lower cavity which is formed in and extends from a lower surface of said second right sub-segment to terminate at a right downward abutment region confronting said left upward abutment region such that in response to the downward movement of the key cap, said left upward abutment region is brought into frictional engagement with said right downward abutment region to thereby retain the key cap in the pressed position, and such that in response to the upward movement of the key cap, said left downward abutment region is brought into frictional engagement with said right upward abutment region to thereby retain the key cap in the normal position.

US Pat. No. 10,431,403

REACTIVE FORCE GENERATION DEVICE

YAMAHA CORPORATION, Hama...

1. A reactive force generation device comprising:a to-be-depressed member including a base section, and a dome section formed of an elastic material and protruding from the base section, a sectional shape of the dome section orthogonal to an axis line of the dome section being substantially line-symmetric about a symmetry axis, the dome section having a three-dimensional shape that is substantially symmetric with respect to a virtual plane containing the symmetry axis and the axis line; and
an opposed member having an opposed surface opposed to a distal end of the dome section, the opposed member in a non-operated state being located remote from the to-be-depressed member,
at least one of the opposed member and the to-be-depressed member being constructed to make a swinging movement in response to a depressing operation applied thereto, wherein the opposed member relatively approaches the base section in response to the depressing operation, the dome section deforms by contact between the opposed surface and the distal end during the relative approaching, and the relative approaching is stopped in a depression-completed state corresponding to a maximum movable range of the opposed member relative to the base section,
the virtual plane being defined so as not to vary throughout an entire depression stroke from an initial state, where no depressing operation is applied yet, to the depression-completed state,
the to-be-depressed member and the opposed member being constructed in such a manner that, as for a variation amount of an angle of the axis line relative to a normal line of the opposed surface during the depression stroke, an acute-side angle defined between the axis line and the normal line of the opposed surface in the initial state falls in an angle range from a first variation amount of the angle of the axis line relative to the normal line during a transition from the initial state to a state where the distal end of the dome section starts contacting the opposed surface to a second variation amount of the angle of the axis line relative to the normal line during a transition from the initial state to the depression-completed state,
the first variation amount of the angle of the axis line relative to the normal line being greater than zero degree.

US Pat. No. 10,431,402

BUTTON SWITCH WITH ADJUSTABLE TACTILE FEEDBACK

DARFON ELECTRONICS CORP.,...

1. A button switch connected to a cap, the button switch comprising:a base having a pillar extending along a Z-axis, the Z-axis, an X-axis and a Y-axis being perpendicular to each other;
a cover disposed on the base;
a flexible acoustic member having a fixing rod and a flexible rod, the fixing rod being fixed to the base;
a sleeve rotatably jacketing the pillar to be movable upward and downward between a high position and a low position along the Z-axis, an upper end of the sleeve passing through the cover to be connected to the cap, the sleeve having an outer annular surface, the outer annular surface having a first convex portion, a first concave portion, a second convex portion, a second concave portion, and a protruding edge located between the second convex portion and the second concave portion;
an upward-force-applying member abutting against the sleeve and the base respectively for driving the sleeve to move away from the base; and
a resilient arm adjacent to the pillar, the resilient arm selectively abutting against the first convex portion at a first position or a second position with rotation of the sleeve on the pillar around the Z-axis when the sleeve is located at the high position, the resilient arm moving to a position corresponding to the first concave portion when the sleeve is located at the low position;
wherein when the sleeve rotates to make the resilient arm abut against the first convex portion at the first position, the protruding edge is misaligned with the flexible rod, and the sleeve receives an external force to move downward along the Z-axis, the flexible rod does not need to cross the protruding edge and the resilient arm moves from the first position to the position corresponding to the first concave portion with downward movement of the sleeve;
when the sleeve rotates to make the resilient arm abut against the first convex portion at the second position, the protruding edge is located above the flexible rod, and the sleeve receives the external force to move downward along the Z-axis, the flexible rod needs to cross the protruding edge and the resilient arm moves from the second position to a position corresponding to the second concave portion with downward movement of the sleeve;
when the sleeve moves downward along the Z-axis and deformation of the flexible rod caused by pressing of the protruding edge is not enough to make the flexible rod cross the protruding edge, the flexible rod deforms downward with the protruding edge;
when deformation of the flexible rod is enough to make the flexible rod cross the protruding edge, the flexible rod is released and then moves upward to collide with the cover for making a sound;
when the external force is released, the upward-force-applying member drives the sleeve to move upward relative to the pillar along the Z-axis for making the resilient arm abut against the first convex portion at the first position or the second position.

US Pat. No. 10,431,401

LOCK OUT/TAG OUT DEVICE HAVING A TIE-RECEIVING PASSAGEWAY

Brady Worldwide, Inc., M...

1. A device for temporarily restricting use of a control via at least one of lock out and tag out, the device comprising:a first portion having a passageway extending therethrough along a distance of passageway extension, the passageway being adapted for reception of a tie;
a second portion having a tang comprising an arm extending to a distal end having a projection, the arm being elastically flexible relative to a remainder of the second portion to accommodate a temporary deflection of the projection of the tang, the second portion being movable relative to the first portion to move the tang transversely across the passageway relative to the direction of passageway extension thereby toggling the device between an opened position in which the projection of the tang is on one side of the passageway and a closed position in which the projection of the tang is on the other side of the passageway; and
wherein a tie is receivable in the passageway and a reception of the tie in the passageway prevents the device from being moved from the closed position back into the opened position due to inability of the tang of the second portion to be moved past the tie in the passageway of the first portion.

US Pat. No. 10,431,400

PROGRAM SWITCH AND MODULAR PROGRAM SWITCH ARRANGEMENT FOR MOUNTING ON A PRINTED CIRCUIT BOARD AND METHOD FOR PRODUCING SUCH A PROGRAM SWITCH ARRANGEMENT

1. A program switch for forming a modular program switch arrangement and for mounting on a printed circuit board, the program switch comprising:a housing;
an insulator component with contact elements arranged thereon; and
a switching element movable between an on switching position and an off switching position and the switching element contacting the contact elements in the on switching position, wherein the housing has a first side wall and a second side wall and at least two connection elements are arranged on each side of the first side wall and the second side wall and spaced apart from each other for connection to adjacent program switches, wherein the at least two connection elements on each side wall are identical, wherein an inner side of the housing is embodied such that the insulator component is positioned in a defined manner in the housing such that the switching element is assigned unambiguously to the on switching position and the off switching position.

US Pat. No. 10,431,398

SWIVEL CATCH APPARATUS, ENCLOSED SWITCH ASSEMBLIES, AND OPERATIONAL METHODS THEREOF

SIEMENS INDUSTRY, INC., ...

1. A switch box mechanism, comprising:a swivel catch having an elongated body, a pivot configured to allow the swivel catch to rotate, and a catch end, the catch end including a catch configured to engage with a lid, and a slide feature formed in the elongated body;
a rod including a first end configured to couple to a switch engagement member that is configured to engage with a rotor of a line base assembly, and a slide portion of the rod slidably engaged with the slide feature; and
a spring configured to bias the swivel catch,
wherein the catch end of the elongated body of the swivel catch including a lock-out hole therethrough and a second lock-out hole formed through an operating handle such that the swivel catch is mounted in such a way that the lock-out hole aligns with the second lock-out hole in an off position which allows a lock to be placed through the swivel catch and the operating handle while a gap between the swivel catch and the operating handle allows the lock to pass only through the swivel catch and not the operating handle thus providing a cover lock-out function in that an enclosure is locked with the lock without locking the operating handle.

US Pat. No. 10,431,396

CHARGING RAM ASSEMBLY, AND PIN ASSEMBLY AND SECURING METHOD THEREFOR

EATON INTELLIGENT POWER L...

1. A pin assembly for a charging ram assembly of an electrical switching apparatus, said charging ram assembly comprising a biasing element, a ram member structured to bias said biasing element, and a plate member, said pin assembly comprising:a pin member structured to extend through said biasing element and said plate member, said pin member having a first end portion and a second end portion disposed opposite and distal from said first end portion;
a plurality of collar members comprising a first collar member and a second collar member each being coupled to said first end portion, each of said first collar member and said second collar member comprising a first disc-shaped portion, a second disc-shaped portion disposed opposite the first portion, and a third disc-shaped portion extending between the first portion and the second portion; and
a securing apparatus comprising a retaining member coupled to said first collar member and said second collar member in order to prevent said pin member from moving with respect to said first collar member and said second collar member,
wherein the first portion, the second portion, and the third portion each have a width; and
wherein the width of the third portion is less than the width of the first portion and the width of the second portion.

US Pat. No. 10,431,395

MULTI-FUNCTION CONTROLLER AND MOBILE DEVICE HAVING SAME

HON HAI PRECISION INDUSTR...

1. A multi-function controller comprising:a mounting member having a receiving hole defined therein;
a control member partially received in the receiving hole of the mounting member, and being capable of being pressed and rotated with respect to the mounting member;
a first switch located at an end of the mounting member;
a second switch disposed at a peripheral wall of the mounting member,
a third switch located spaced from the second switch and at the peripheral wall of the mounting member; and
a processing unit, the processing unit being electrically connected to the first switch, the second switch, and the third switch;
wherein the processing unit is configured for selectively receiving a first control signal from the first switch when the control member is pressed, receiving a second control signal from the second switch when the control member is rotated clockwise, or receiving a third control signal from the third switch when the control member is rotated counterclockwise, wherein the control member comprises a control tube received in the receiving hole of the mounting member and a control ring, the control tube comprises a conventional audio jack, an open end and a closed end, the control ring extends from the open end of the control tube.

US Pat. No. 10,431,394

CAPACITOR

Panasonic Intellectual Pr...

1. A capacitor comprising a capacitor element including a positive electrode and a negative electrode, whereinat least one of the positive electrode and the negative electrode contains activated carbon,
a sum of volumes per unit weight of pores having a pore diameter of from 30 ? to 100 ? inclusive among pores of the activated carbon is 0.2 cm3/g or more,
in a volume distribution of the pores of the activated carbon, a top of a maximum peak in the volume distribution is situated at a position corresponding to a pore diameter of more than 1 ? and less than 20 ?, and
an absolute value of an average slope of the volume distribution of the pores of the activated carbon versus the logarithmic pore diameter at pore diameters ranging from 40 ? to 100 ? is less than an absolute value of an average slope of the volume distribution of the pores of the activated carbon versus the pore diameter at pore diameters ranging from 100 ? to 300 ?.

US Pat. No. 10,431,392

ELECTRICAL STORAGE DEVICE, MANUFACTURING METHOD OF THE SAME, AND SEPARATOR

PANASONIC INTELLECTUAL PR...

1. An electrical storage device comprising:an electrical storage element including:
an anode body;
a cathode body facing the anode body; and
a separator including a separator substrate and a conductive polymer adhering to the separator substrate, and interposed between the anode body and the cathode body; and
an electrolytic solution with which the electrical storage element is impregnated, wherein:
the separator includes a first surface layer having a first surface facing the anode body, and a second surface layer having a second surface facing the cathode body,
the first surface layer includes a first region that is not provided with the conductive polymer,
the second surface layer includes a second region provided with the conductive polymer,
the first surface layer includes a third region provided with the conductive polymer, and
an area, of the third region in the first surface layer, facing the anode body is smaller than an area, of the second region in the second surface layer, facing the cathode body.

US Pat. No. 10,431,391

CAPACITOR PACKAGE STRUCTURE AND ANTI-OXIDATION ELECTRODE FOIL THEREOF

APAQ TECHNOLOGY CO., LTD....

1. An anti-oxidation electrode foil, comprising:a base material structure having a top surface and a bottom surface;
a first conductive material structure disposed on the top surface of the base material structure; and
a first carbonaceous material structure disposed on the first conductive material structure;
wherein one portion of the first conductive material structure is a first outermost layer for contacting the first carbonaceous material structure, the first outermost layer of the first conductive material structure is a first oxygen-containing metal compound layer formed by an oxidation process, and the first oxygen-containing metal compound layer is disposed between the other portion of the first conductive material structure and the first carbonaceous material structure so as to prevent oxygen from contacting the other portion of the first conductive material structure;
wherein, the first conductive material structure composed of a Ti layer, a TiNx layer formed on the Ti layer, and a TiNxCy layer (0?x?1) formed on the TiNx layer; the first conductive material structure is heated so as to transform the TiNxCy layer into a TiNxCyOz layer.

US Pat. No. 10,431,390

ELECTROLYTIC CAPACITOR AND METHOD FOR MANUFACTURING SAME

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising:an anode body having a dielectric layer on a surface of the anode body;
a cathode body; and
an electrolytic solution interposed between the anode body and the cathode body,
wherein:
the electrolytic solution contains a first ester compound and a second ester compound, the first ester compound being a condensate of boric acid and a sugar alcohol, and
the second ester compound contains at least one condensate selected from the group consisting of a condensate of boric acid and a monool compound and a condensate of boric acid and a polyol compound excluding a sugar alcohol.

US Pat. No. 10,431,389

SOLID ELECTROLYTIC CAPACITOR FOR HIGH VOLTAGE ENVIRONMENTS

AVX Corporation, Fountai...

1. A method of forming a high voltage solid electrolytic capacitor element, the method comprising:subjecting a sintered anode pellet to a formation profile to form an anode, wherein the formation profile includes subjecting the pellet to an increasing current so that a target forming voltage is achieved in about 30 minutes or less; and
applying a solid electrolyte to the anode.

US Pat. No. 10,431,388

VOLTAGE TUNABLE MULTILAYER CAPACITOR

AVX Corporation, Fountai...

1. A tunable multilayer capacitor comprising:first active electrodes that are in electrical contact with a first active termination and alternating second active electrodes that are in electrical contact with a second active termination;
first DC bias electrodes that are in electrical contact with a first DC bias termination and alternating second DC bias electrodes that are in electrical contact with a second DC bias termination; and
a plurality of dielectric layers disposed between the alternating first and second active electrodes and between the alternating first and second bias electrodes, wherein at least a portion of the dielectric layers contain a tunable dielectric material that exhibits a variable dielectric constant upon the application of an applied voltage;
wherein the dielectric material has a voltage tunability coefficient of from about 10% to about 90%, wherein the voltage tunability coefficient is determined according to the following general equation:
T=100×(?0??V)/?0
wherein,
T is the voltage tunability coefficient;
?0 is the static dielectric constant of the material without an applied voltage;
and
?V is the variable dielectric constant of the material after application of an applied voltage (DC).

US Pat. No. 10,431,385

MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a pair of external electrodes;
a first internal electrode that contains a base metal and is coupled to one of the pair of external electrodes;
a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and the base metal, wherein a main component of the dielectric layer is the ceramic material; and
a second internal electrode that is stacked on the dielectric layer, contains the base metal, and is coupled to another one of the pair of external electrodes, wherein
a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, each of the five regions including the base metal, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, wherein abundance of Ba and Ti in each of the five regions is more than 90% as measured by measuring abundance of Ba atoms and Ti atoms by a transmission electron microscope,
an average grain size in the dielectric layer is 200 nm or less, and
the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain.

US Pat. No. 10,431,383

MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a pair of external electrodes;
a first internal electrode that contains a base metal and is coupled to one of the pair of external electrodes;
a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and the base metal, wherein a main component of the dielectric layer is the ceramic material; and
a second internal electrode that is stacked on the dielectric layer, contains the base metal, and is coupled to another one of the pair of external electrodes, wherein
a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, each of the five regions including the base material, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, wherein abundance of Ba and Ti in each of the five regions is more than 90% as measured by measuring abundance of Ba atoms and Ti atoms by a transmission electron microscope,
a thickness of the first internal electrode and a thickness of the second internal electrode are 0.2 ?m or greater, and
the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain.

US Pat. No. 10,431,382

PRINTED CIRCUIT BOARD ASSEMBLY HAVING A DAMPING LAYER

Apple Inc., Cupertino, C...

1. A printed circuit board assembly, comprising:a printed circuit board (PCB) having a first flexural modulus and a top surface;
a plurality of electronic components mounted on the top surface of the PCB;
a damping layer mounted on the top surface of the PCB, wherein the damping layer includes a continuous layer of viscoelastic material covering the plurality of electronic components, wherein the damping layer is attached to the top surface of the PCB at a plurality of locations around the plurality of electronic components, and wherein the damping layer includes a second flexural modulus lower than the first flexural modulus; and
an overmold layer mounted on the top surface of the PCB, wherein the overmold layer is a continuous layer of waterproof material covering the plurality of electronic components and the continuous layer of viscoelastic material, and wherein the overmold layer is in direct contact with the damping layer and is attached to the top surface of the PCB at a plurality of locations around the damping layer.

US Pat. No. 10,431,381

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body having a length and a width substantially equal to each other, and including dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces and the third and fourth surfaces and opposing each other;
a first external electrode disposed on the third surface of the capacitor body, a portion of the first external electrode extending to cover a portion of the fifth surface of the capacitor body; and
a second external electrode disposed on the fourth surface of the capacitor body, a portion of the second external electrode extending to cover a portion of the sixth surface of the capacitor body,
wherein each of the plurality of first internal electrodes has a first lead portion exposed to a first corner of the capacitor body in which the third and fifth surfaces of the capacitor body meet each other and covered with the first external electrode, such that adjacent edges of each of the plurality of first internal electrodes are spaced apart from the third and fifth surfaces of the capacitor body, respectively, by a substantially same distance, and
each of the plurality of second internal electrodes has a second lead portion exposed to a second corner of the capacitor body at which the fourth and sixth surfaces of the capacitor body meet each other and covered with the second external electrode, such that adjacent edges of each of the plurality of second internal electrodes are spaced apart from the fourth and sixth surfaces of the capacitor body, respectively, by a substantially same distance.

US Pat. No. 10,431,379

METHOD OF MANUFACTURING A MULTILAYER CERAMIC CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A method of manufacturing a multilayer ceramic capacitor, comprising:preparing a first ceramic green sheet on which a plurality of stripe-type first inner electrode patterns are formed to be spaced apart from one another by a predetermined distance and a second ceramic green sheet on which a plurality of stripe-type second inner electrode patterns are formed to be spaced apart from one another by a predetermined distance;
forming a ceramic green sheet laminate by alternately stacking the first ceramic green sheet and the second ceramic green sheet in such a manner that a central portion of each of the stripe-type first inner electrode patterns and a predetermined distance between the stripe-type second inner electrode patterns overlap with each other;
forming first and second groove portions on at least one of a top surface and a bottom surface of the ceramic green sheet laminate, wherein the first groove portions are formed at locations aligned, in a stacking direction of the ceramic green sheet laminate, with the predetermined distance formed between the stripe-type first inner electrode patterns formed on the first ceramic green sheet, and the second groove portions are formed at locations aligned, in the stacking direction of the ceramic green sheet laminate, with the predetermined distance formed between the stripe-type second inner electrode patterns formed on the second ceramic green sheet; and
cutting the ceramic green sheet laminate.

US Pat. No. 10,431,378

METHOD FOR MANUFACTURING ELECTRONIC COMPONENT WITH COIL

SUMIDA CORPORATION, (JP)...

1. A method for manufacturing an electronic component comprising:placing a T-shaped core and an air-core coil in a mold;
placing a mixture of a metal magnetic material and a thermosetting resin into the mold so as to embed the T-shaped core and the air-core coil in the mixture;
after placing the mixture, applying pressure in a range of 0.1 to 20.0 kg/cm2 to the placed mixture so that a shape of the placed mixture conforms to the T-shaped core, the air-core coil, and the mold; and
after applying the pressure, heating the mixture at a predetermined temperature for a predetermined time so that the placed mixture is hardened.

US Pat. No. 10,431,377

HIGH EFFICIENCY MAGNETIC COMPONENT

1. A magnetic air core apparatus, comprising:a first toroid formed of a plate like structure continuously wrapped in a helical shape having a substantially circular cross-section, and including an air core, the plate like structure having an outer peripheral surface and an inner peripheral surface, a width of each turn of the plate-like structure varies in width, and a gap between successive turns is straight, has a constant width, and is angled in a radial direction of the first toroid;
a second toroid substantially enveloping the first toroid in a concentric manner, the first and second toroids having a first air gap provided therebetween;
a start terminal connected to the first toroid; and
a return terminal connected to the second toroid, the start and return terminals enabling connection to other electrical devices,
wherein the second toroid includes at least one poloidal slot to enable access to the first toroid, and
the poloidal slot has a notch adjacent thereto to allow access to the start and return terminals.

US Pat. No. 10,431,375

HARDENED INDUCTIVE DEVICE AND SYSTEMS AND METHODS FOR PROTECTING THE INDUCTIVE DEVICE FROM CATASTROPHIC EVENTS

ABB Schweiz AG, Baden (C...

1. An inductive device comprising: a tank with top, bottom and side walls, and wherein each said side wall has an outer substrate surface; a core having at least one core limb extending between a pair of yokes, at least one coil assembly mounted to the at least one core limb, and an insulating medium disposed in an internal volume of said tank; and a coating layer bonded to said tank side wall outer substrate surfaces, and wherein said coating is a polyurea coating upon reaction, said polyurea coating formed of first and second components prior to reaction, comprising: a first component comprising a member selected from the group consisting of an aromatic diisocyanate and an aliphatic diisocyanate; and a second component comprising a polyamine.

US Pat. No. 10,431,374

MANUFACTURING METHOD OF A FILTER STRUCTURE

Guangdong MISUN Technolog...

1. A manufacturing method of a filter structure, the filter structure comprising:a box, having a cavity;
a plurality of coil components, installed in the cavity; and
a plurality of wiring components, each having a positive wiring pin and a negative wiring pin fixed to the box;
conductive wires coupled to both ends of each coil component being welded and fixed to the positive wiring pin and the negative wiring pin respectively, wherein the manufacturing method comprises the steps of:
(A) embedding a plurality of wiring components into both sides of the box respectively;
(B) installing a coil component into a chamber of a welding fixture, and latching the conductive wires at both ends of the coil component into a latch slot of the welding fixture tightly;
(C) installing a welding fixture to a top of the box, pressing the conductive wire by a protruding portion, so that the conductive wire is contacted with the positive wiring pin or the negative wiring pin;
(D) using a spot welding machine to sequentially weld the conductive wire and the positive wiring pin or the negative wiring pin; and
(E) packaging the filter structure.

US Pat. No. 10,431,373

COUPLED INDUCTOR

1. Coupled inductor havinga core and two windings,
wherein a first winding has a first and second terminal end and wherein a second winding had a third and fourth terminal end,
wherein the first to fourth terminal ends are arranged on a lower side of the core,
wherein each winding has an intermediate section extending through a through hole in the core,
wherein the two windings are designed at least in the intermediate section as flat stripes each having first and second side faces with a large width and third and fourth side faces having a small width compared to the width of the first and second side faces,
wherein the first side laces of both windings are arranged in the intermediate section perpendicular to the lower side of the core and wherein the two first side faces of the windings in the intermediate section face each other and/or abut each other in the intermediate section,
wherein the core has a front side surface and a backside surface, wherein the intermediate sections of the windings continuously extends from the front side surface to the back side surface of the core, and wherein the windings have sections arranged parallel to the front side surface and the back side surface of the core,
wherein the terminal ends are connected to the sections of the windings.

US Pat. No. 10,431,372

HIGH CURRENT, LOW EQUIVALENT SERIES RESISTANCE PRINTED CIRCUIT BOARD COIL FOR POWER TRANSFER APPLICATION

Futurewei Technologies, I...

1. A device, comprising:a housing; and
a wireless charging coil, the coil including a layered structure of electric conductors on a printed circuit board (PCB), wherein the layered structure comprises:
a first layer including a first electrically conductive trace comprising a first turn and a second turn adjacent to the first turn;
a second layer including a second electrically conductive trace comprising a third turn and a fourth turn adjacent to the third turn; and
a plurality of vias coupling the first layer and the second layer, wherein the plurality of the vias include a first via, a second via and a third via distributed separately along a length of the first turn, each of the first via, the second via and the third via electrically connecting the first turn and the third turn, wherein the plurality of the vias further include a fourth via, a fifth via and sixth via distributed separately along a length of the second turn, each of the fourth via, fifth via and sixth via connecting the second turn and the fourth turn, wherein thickness of the device is less than 1 centimeter.

US Pat. No. 10,431,371

MANUFACTURING METHODS FOR MAGNETIC CORE INDUCTORS WITH BIASED PERMEABILITY

Ferric Inc., New York, N...

1. A method of forming an inductor assembly, comprising:depositing a magnetic core on a planar substrate, the magnetic core lying in a core plane;
forming an inductor coil that winds around the magnetic core, the inductor coil configured to generate an inductor magnetic field that passes through the magnetic core in a closed loop parallel to the core plane; and
annealing the magnetic core while applying an external magnetic field that passes through the magnetic core in a radial direction to permanently fix an easy axis of magnetization of the magnetic core parallel to the radial direction, the radial direction orthogonal to the closed loop,
wherein permanently fixing the easy axis of magnetization parallel to the radial direction causes a hard axis of magnetization of the magnetic core to be permanently oriented in a generally circular closed path parallel to the closed loop.

US Pat. No. 10,431,370

ELECTRONICS SYSTEM AND METHOD OF FORMING SAME

SCHNEIDER ELECTRIC SOLAR ...

1. A heat-generating electrical component and base assembly configured to be secured to a component wall, the assembly comprising:a base including an upper portion having a recess and a lower portion having a floating electrical connector including a threaded element disposed within a retaining body including one or more flattened inner walls which prevent rotation of the threaded element within the retaining body and a ring lug that retains the threaded element within an internal volume of the retaining body;
a heat-generating electrical component secured in the recess of the base and including an electrical lead in electrical communication with the floating electrical connector; and
a gasket circumscribing a perimeter of the lower portion.

US Pat. No. 10,431,369

REACTOR

TAMURA CORPORATION, Toky...

1. A reactor comprising:a reactor body having a core; and
a case that is substantially rectangular and houses the reactor body; wherein
the reactor body has:
a resin member that covers a circumference of the core; and
no more and no less than three fixing portions for fixing the reactor body to the case, the three fixing portions being a first fixing portion, a second fixing portion and a third fixing portion,
the case has:
sidewalls that are flexible; and
mount portions that are provided on the sidewalls and are for mounting the fixing portions, and
the core is an annular core including:
two or more leg portions; and
a pair of yoke portions arranged at both end portions of the leg portions, each yoke portion having a bent portion,
the resin member includes a first joint portion that covers one of the pair of yoke portions,
the third fixing portion is provided at a central part of the first joint portion,
the reactor body is fixed to the case by the fixing portions being mounted on the mount portions, and
a clearance is formed between corners of the case and a portion of the first joint portion covering the bent portion of the one of the pair of yoke portions.

US Pat. No. 10,431,367

METHOD FOR GAPPING AN EMBEDDED MAGNETIC DEVICE

Radial Electronics, Inc.,...

1. A method comprising:forming a feature on a substrate, the feature being a depression defining an inside surface;
disposing a first conductive pattern on the substrate and the inside surface of the feature;
disposing a permeability material on the inside surface of the feature and the first conductive pattern, the permeability material being a separate solid object placed within the feature;
disposing a substrate material on the substrate and the feature;
disposing a second conductive pattern on the substrate material, the second conductive pattern substantially matching the first conductive pattern to wrap the permeability material between the first conductive pattern and the second conductive pattern producing a winding type structure electrically coupling the first conductive pattern and the second conductive pattern in electrical connection to define at least one electrical circuit to facilitate a magnetic field in the permeability material; and
gapping the permeability material, after the permeability material has been disposed on the inside surface of the feature on the substrate, to remove at least a portion of the permeability material to produce a gap in the at least a portion of the permeability material.

US Pat. No. 10,431,366

NOISE FILTER

YAZAKI CORPORATION, Mina...

1. A noise filter used for a plurality of conducting members, the noise filter comprising,a ring-shaped core made from a magnetic material, the ring-shaped core being attached to the plurality of conducting members to reduce noise of currents flowing through each of the plurality of the conducting members,
the ring-shaped core including:
a base core having a plurality of support pillar portions extending outward in radial directions; and
a plurality of divisional cores each being placed between two of the plurality of the support pillar portions adjacent to each other in the circumferential direction, and each having two end surfaces connected to end portions of the two of the plurality of the support pillar portions,
the plurality of the divisional cores being configured to allow the plurality of the conducting members to be wound on the plurality of the divisional cores,
a magnetic path being formed between the end surface of each of the plurality of the divisional cores and the end portion of each of the plurality of the support pillar portions contacting the end surface,
the ring-shaped core being configured to form a common-mode magnetic path passing through all of the plurality of the divisional cores and all of the end portions of the plurality of the support pillar portions and normal-mode magnetic paths each passing through one of the plurality of the divisional cores and the two of the plurality of the support pillar portions connected to the one of the plurality of the divisional cores, the normal-mode magnetic paths being the same in number as the conducting members.

US Pat. No. 10,431,365

ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a main body made from a metal magnetic powder and an insulating resin;
a coating film covering the surface of the main body;
a conductor disposed inside the main body;
inorganic particles adhering to the surface of the coating film, the inorganic particles having an average particle diameter of 1 nm or more and 200 nm or less; and
outer electrodes which are electrically connected to the conductor and which cover portions of the surface of the coating film while inorganic particles adhere to the portions,
wherein the coating film contains a resin and metal cations.

US Pat. No. 10,431,364

ELECTRO-MECHANICAL DEVICE AND MANUFACTURING METHODS FOR VARIOUS APPLICATIONS

1. A single monolithic electromechanical device wherein;each single component of the device's electrical structure is staked alternately with magnetic material core segments and,
the entire device is also completely encapsulated by this magnetic material core material on the device's entire surface,
this encapsulation is done in a manner to totally suppress induced currents produced by the proximity effect.

US Pat. No. 10,431,363

PLUNGER FOR MAGNETIC LATCHING SOLENOID ACTUATOR

JOHNSON ELECTRIC INTERNAT...

1. A plunger for a magnetic latching solenoid actuator, the plunger comprising:an elongate plunger body; and
a plunger head at one end of the plunger body;
a first portion of the plunger body;
a second portion of the plunger body having a same transverse cross-section as a transverse cross-section of the first portion;
a magnet-interface body portion of the body portion between the first portion of the plunger body and the second portion of the plunger body which defines first and second planar surfaces on opposite lateral sides of the plunger body with a different transverse cross-section than the transverse cross-sections of the first and second portions of the plunger body.

US Pat. No. 10,431,360

BALANCED MAGNETIC ARRAY

Apple Inc., Cupertino, C...

1. A consumer electronic device, comprising:a housing that carries a first array of magnetic elements that include a pinning magnet and first magnetic attachment elements, each of the first magnetic attachment elements is limited to forming a magnetic circuit with a corresponding second magnetic attachment element carried by an accessory device, and
wherein the pinning magnet has a length that alters a magnetic property of the magnetic circuits such that the magnetic circuits taken together have a net zero torque or a near net zero torque value, and a net non-zero attraction force.

US Pat. No. 10,431,359

METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET

JFE Steel Corporation, T...

1. A method for producing a grain-oriented electrical steel sheet comprising a series of steps of:heating a steel slab having a chemical composition comprising C: 0.04-0.12 mass %, Si: 1.5-5.0 mass %, Mn: 0.01-1.0 mass %, sol. Al: 0.010-0.040 mass %, N: 0.004-0.02 mass %, one or two of S and Se: 0.005-0.05 mass % in total and the remainder being Fe and inevitable impurities to not lower than 1250° C.,
hot rolling to obtain a hot rolled sheet having a thickness of not less than 1.8 mm,
subjecting the hot rolled sheet to a single cold rolling or two or more cold rollings including an intermediate annealing therebetween to obtain a cold rolled sheet having a final thickness of 0.15-0.20 mm, and
subjecting the cold rolled sheet to primary recrystallization annealing and further to final annealing,
wherein a content ratio of sol. Al to N in the steel slab (sol. Al/N) and a final thickness d (mm) satisfy the following formulas (1) and (2):
4d+1.52?sol. Al/N?4d+2.32  (1)
sol. Al/N?2.84  (2)
and the steel sheet in the heating process of the final annealing is held at a temperature of 775-875° C. for 40-200 hours and then heated in a temperature region of 875-1050° C. at a heating rate of 20-60° C./hr, and
wherein a region of 200-700° C. in the heating process of the primary recrystallization annealing is heated at a heating rate of not less than 50° C./s, while any temperature between 250-600° C. is held for 1-5 seconds.

US Pat. No. 10,431,358

RESISTOR PRODUCTION METHOD, RESISTOR, AND ELECTRONIC DEVICE

STANLEY ELECTRIC CO., LTD...

1. A method of manufacturing a resistor including (i) a substrate, and (ii) a resistive film provided on the substrate, wherein one portion or a whole of the resistive film is configured of a layer of sintered conductive nanosized particles with a particle diameter of less than 1 ?m, the method comprising:a first step of applying a solution wherein at least the conductive nanosized particles with a particle diameter of less than 1 ?m and an insulating material are dispersed, or a solution wherein at least the conductive nanosized particles covered with an insulating material layer are dispersed, in a desired form on a surface of the substrate, thereby forming a film;
a second step of irradiating one portion of the film with light in a predetermined pattern, and sintering the conductive nanosized particles with the light, thereby forming the resistive film, which is a conductive particle layer of the predetermined pattern;
a third step of measuring a resistance value of the resistive film; and
a fourth step of sintering the conductive nanosized particles by irradiating the film with light, thereby forming an additional resistive film, when the measured resistance value is greater than a range of a desired resistance value, and irradiating the resistive film with light, thereby trimming the resistive film, when the measured resistance value is smaller than the range of the desired resistance value.

US Pat. No. 10,431,357

VERTICALLY-CONSTRUCTED, TEMPERATURE-SENSING RESISTORS AND METHODS OF MAKING THE SAME

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material;
a first contact coupled to the first doped region;
a second contact opposite the first contact coupled to the second doped region; and
an isolation trench to circumscribe the third doped region.

US Pat. No. 10,431,356

MOLDED PART-EQUIPPED ELECTRICAL CABLE AND MOLDED PART-EQUIPPED ELECTRICAL CABLE MANUFACTURING METHOD

AutoNetworks Technologies...

1. A molded part-equipped electrical cable, comprising:a terminal-equipped electrical cable including an insulated electrical cable having a core and an insulation coating covering the periphery of the core and a terminal connected to an end part of the insulated electrical cable;
an adhesive provided on a surface of the insulation coating of the terminal-equipped electrical cable; and
a molded member covering from a part provided with the adhesive on the insulation coating of the terminal-equipped electrical cable to a connected part of the insulated electrical cable and the terminal,
wherein:
the molded member includes a first molded part and a second molded part separately molded;
the first molded part includes a part entirely covering the adhesive while being in contact with the adhesive;
the second molded part is present on the terminal side of the first molded part covering the adhesive in a longitudinal direction of the terminal-equipped electrical cable; and
the first molded part includes no part covering the terminal and the second molded part includes no part covering the insulation coating.

US Pat. No. 10,431,355

FEED-THROUGH ASSEMBLY FOR CONVEYANCE OF A FEED ELEMENT

United States of America ...

1. A feed-through assembly comprising,a) a lower compression member including an axially extending aperture extending between an inner, lower compression member surface and an outer, lower compression member surface;
b) an upper compression member including an axially extending aperture extending between an inner, upper compression member surface and an outer, upper compression member surface;
c) a packing stack including a plurality of packing buttons each including axially extending apertures, said packing stack has a lower packing button adjacent to said inner, lower compression member surface and an upper packing button adjacent to said inner, upper compression member surface, and wherein each of said packing buttons is made from expanded polytetrafluoroethylene (ePTFE) foam material; and
d) at least one feed element including a distal end and a proximal end, said at least one feed element extends through said apertures of each of said lower compression member, said packing stack including a plurality of packing buttons, and said upper compression member surface, said distal end of said at least one feed element is exposed to a first boundary environment and said proximal end is exposed to a second boundary environment.

US Pat. No. 10,431,354

METHODS FOR DIRECT PRODUCTION OF GRAPHENE ON DIELECTRIC SUBSTRATES, AND ASSOCIATED ARTICLES/DEVICES

Guardian Glass, LLC, Aub...

1. A method of making a coated article comprising a graphene-inclusive film on a substrate, the method comprising:disposing a metal-inclusive catalyst layer on the substrate;
exposing the substrate with the metal-inclusive catalyst layer thereon to a precursor gas and a strain-inducing gas at a temperature of no more than 900 degrees C., the strain-inducing gas inducing strain in the metal-inclusive catalyst layer; and
forming and/or allowing formation of graphene, from the precursor gas, both over and contacting the metal-inclusive catalyst layer, and between the substrate and the catalyst metal-inclusive catalyst layer, as facilitated by the strain induced in the metal-inclusive catalyst layer, in making the coated article.

US Pat. No. 10,431,352

CABLE AND METHOD FOR PRODUCING A CABLE

1. A cable comprising: at least one litz wire having twisted litz wire strands for conducting electrical current and an insulation sheath surrounding the at least one litz wire for electrical insulation of the at least one litz wire, where the cable has an interruption segment without insulation sheath disposed between two cable segments with insulation sheath, characterized in that the at least one litz wire is birdcaged in the interruption segment in order to interrupt the transport of moisture through the cable, in particular through the at least one litz wire due to capillary pressure and/or temperature-related pressure differences along the cable, and the interruption segment is not sealed so that a pressure equalization to the external environment takes place.

US Pat. No. 10,431,351

FLAT CABLE AND PRODUCTION METHOD THEREFOR

AUTONETWORKS TECHNOLOGIES...

1. A flat cable, comprising:a plurality of conductors respectively extending in an axial direction; and
an insulating sheath configured to, in a state where the conductors are lined up in a width direction orthogonal to the axial direction of the conductors, restrict the conductors from outside and collectively cover the conductors,
wherein the insulating sheath has an expander enabling bending in the width direction by permitting relative displacement between the conductors, and the expander, by expanding so as to partially separate from the conductors in at least a thickness direction orthogonal to both the width direction and the axial direction, forms an internal space permitting relative displacement such that adjacent conductors overlap in the thickness direction.

US Pat. No. 10,431,350

NON-CIRCULAR ELECTRICAL CABLE HAVING A REDUCED PULLING FORCE

Southwire Company, LLC, ...

1. A process for producing non-circular electrical cable, wherein the non-circular electrical cable comprises one or more conductors arranged in a non-circular arrangement and an exterior sheath comprising a first sheath layer and a second sheath layer, said process comprising steps for:advancing the one or more conductors through an extruder head;
extruding a first sheath layer comprising a plastic material around the one or more conductors, wherein the first sheath layer is initially extruded in a substantially circular shape having an inner surface and an exterior surface and at least a portion of the inner surface thereof is spaced from the one or more conductors;
extruding a second sheath layer comprising a nylon material around an exterior surface of the first sheath layer, wherein the second sheath layer has a different polymer composition than the first sheath layer;
applying a negative pressure to the interior surface of the first sheath layer, thereby pulling the first sheath layer and second sheath layer onto the one or more conductors and into a non-circular shape having a cross section substantially similar to the combined cross section of the one or more conductors; and
cooling the first and second sheath layers.

US Pat. No. 10,431,348

PRESSURE SENSOR INCLUDING ELECTRICAL CONDUCTORS COMPRISING ELECTROCONDUCTIVE RESIN COMPOSITION THAT DOES NOT NEED CROSS-LINKING

HITACHI METALS, LTD., To...

1. A pressure sensor, comprising:an insulator having a hollow portion; and
a plurality of electrical conductors that have been disposed apart from each other along the inner surface facing the hollow portion of the insulator,
wherein the insulator comprises an insulating resin composition made of a material which does not need cross-linking,
wherein the plurality of electrical conductors comprise an electroconductive resin composition made of a material which does not need cross-linking,
wherein the insulating resin composition and the electroconductive resin composition comprise a process oil, and a mass percentage concentration of the process oil in the electroconductive resin composition is higher than a mass percentage concentration of the process oil in the insulating resin composition.

US Pat. No. 10,431,345

SMALL FORM FACTOR BETAVOLTAIC BATTERY FOR USE IN APPLICATIONS REQUIRING A VOLUMETRICALLY-SMALL POWER SOURCE

CITY LABS, INC., Homeste...

1. A betavoltaic power source comprising:a source of beta particles;
a plurality of regions each for collecting the beta particles and for generating electron hole pairs responsive thereto, a first set of the plurality of regions disposed proximate a first surface of the source and a second set of the plurality of regions disposed proximate a second surface, the first and second surface in opposing relation; and
a secondary power source charged by a current developed by the electron hole pairs.

US Pat. No. 10,431,344

ASSEMBLY WITH A TUBE LOCKING DEVICE, AND ASSOCIATED MAINTENANCE METHOD

AREVA NP, Courbevoie (FR...

1. An assembly comprising:a plurality of tubes having respective segments parallel to one another;
a locking device for locking the tubes in position relative to one another, the device including:
at least one first arm;
a locking axle having a plurality of bearing surfaces; and
a link connecting the locking axle to the first arm, the locking axle being movable relative to the first arm between a locking position, in which the segments of the tubes are each pinched between one of said bearing surfaces and the first arm, and a released position, in which the segments of the tubes are free relative to the first arm,
the bearing surfaces being depressions hollowed along the locking axle.

US Pat. No. 10,431,342

TRACKING THE PROBABILITY FOR IMMINENT HYPOGLYCEMIA IN DIABETES FROM SELF-MONITORING BLOOD GLUCOSE (SMBG) DATA

University of Virginia Pa...

1. A method for maintaining the health of a diabetic patient by preventing the occurrence of a hypoglycemic event in said patient, comprising:obtaining self monitoring blood glucose (SMBG) readings from the patient;
measuring glycemic variability of said patient and low blood glucose (BG) of said patient based on said obtained SMBG readings;
creating in a processor a bivariate distribution that maps probability for an upcoming hypoglycemic event in said patient jointly to values of said measured glycemic variability and said measured low blood glucose (BG);
optimizing in said processor the bivariate distribution to achieve prediction of a predetermined percentage of hypoglycemic events below a predetermined BG value occurring in said patient within a predetermined future time period;
tracking in said processor the optimized distribution over time using routine SMBG readings from the patient;
outputting via said processor a message to said patient when said optimized distribution indicates a certain probability for the occurrence of a hypoglycemic event in said patient within said predetermined future time period, based on SMBG data obtained from said patient; and
causing said patient to take a physical action in response to receiving said message to prevent a hypoglycemic event from occurring in said patient.

US Pat. No. 10,431,341

DETECTION DEVICE, METHOD, AND PROGRAM FOR ASSISTING NETWORK ENTROPY-BASED DETECTION OF PRECURSOR TO STATE TRANSITION OF BIOLOGICAL OBJECT

Japan Science and Technol...

1. A detection device for detecting a pre-disease state comprising detecting a biomarker candidate that serves as an early-warning signal indicating the pre-disease state by detecting an index of a symptom of a biological object to be measured, based on measured data of a plurality of factors obtained by measurement on the biological object, said device comprising:selection means for selecting the factors based on time-dependent changes of measurement data of each of the factors;
microscopic calculation means for calculating microscopic entropy as understood in statistical mechanics between the factors selected by the selection means and neighboring factors thereof;
index detection means for detecting the index based on the microscopic entropy calculated by the microscopic calculation means;
precursor detection means for detecting a precursor to a state transition based on the index detected by the index detection means,
wherein the selection means selects the factors of which the measured data shows the time-dependent changes beyond a predetermined criterion,
wherein the microscopic calculation means calculates the microscopic entropy as understood in statistical mechanics between each of the factors selected by the selection means and every neighboring factor thereof,
wherein the precursor detection means detects the precursor to the state transition when the microscopic entropy calculated by the microscopic calculation means shows a decrease beyond a predetermined detection criterion,
choosing means for choosing, as a candidate for a biomarker, a factor for which the microscopic entropy calculated by the microscopic calculation means shows a decrease beyond a predetermined choosing criterion, the biomarker being the index of the symptom of the biological object,
wherein the precursor detection means detects the precursor to the state transition when the microscopic entropy for the factor chosen by the choosing means shows the decrease beyond the predetermined detection criterion; and
an acquisition unit configured to acquire the measurement data on the plurality of factors of the biological object to be measured.

US Pat. No. 10,431,340

SYSTEMS FOR PREDICTING HYPOGLYCEMIA AND METHODS OF USE THEREOF

Eco-Fusion, Ramat Gan (I...

1. A system, comprising:at least one user-wearable device, wherein the at least one user-wearable device is in contact with a skin of a user when the user wears the at least one user-wearable device, and wherein the at least one user-wearable device comprises at least one sensor configured to acquire physiological measurements for at least one hypoglycemia-related physiological characteristic of the user that is correlated with at least one of a blood insulin excess or a hypoglycemic blood glucose level;
wherein the at least one hypoglycemia-related physiological characteristic is chosen from beat-to-beat heart rate, heart rate variability, oxygen saturation, galvanic skin response, and any combination thereof;
a non-transient computer readable medium having hypoglycemia-predictive software;
at least one processor configured to execute the hypoglycemia-predictive software;
wherein, upon execution of the hypoglycemia-predictive software, the at least one processor is at least configured to:
receive, in real-time, user-specific data from a user, wherein the user-specific data comprises: food intake of the user, glucose readings of the user, medication intake by the user, user behavior data and at least one insulin dose taken by the user;
receive, in real-time, from the at least one user-wearable device, user-specific hypoglycemia-related physiological data, comprising at least one particular physiological measurement of the at least one hypoglycemia-related physiological characteristic of the user;
determine, in real-time, a hypoglycemic event of the user, based on the at least one particular physiological measurement of the at least one hypoglycemia-related physiological characteristic of the user and at least one chosen from:
1) a predicted user-specific value of the at least one hypoglycemia-related physiological characteristic, determined based on the user-specific data, and
2) an expected population-based value of the at least one hypoglycemia-related physiological characteristic, determined based on a population of individuals identified based on the user-specific data;
generate, in real-time, in response to the determination of the hypoglycemic event of the user, at least one alert, instructing the user to consume glucose-rich intake; and
output, in real-time, the at least one alert to at least one of: the user, at least one family member, at least one medical practitioner, or any combination thereof.

US Pat. No. 10,431,339

METHOD AND SYSTEM FOR DETERMINING RELEVANT PATIENT INFORMATION

EPIC Systems Corporation,...

1. A non-transitory computer-readable medium having stored thereon instructions executable by a processing system to cause the processing system to perform functions comprising:receiving data indicative of a patient identity of a patient and a current condition;
in response to receiving the data indicative of the patient identity and the current condition, transmitting a request for historical patient information, and wherein the historical patient information is received in response to the transmitted request;
dividing the historical patient information into a plurality of classifications, wherein at least one of the plurality of classifications is representative of a past diagnosis of the patient;
using a weighted graph unique to the patient to determine a weight between the past diagnosis and the current condition;
using the weight and an input value to determine a relevance score of the past diagnosis to the current condition;
determining a level of prominence with which to display the historical information based on the relevance score, wherein determining the level of prominence comprises comparing the relevance score to a plurality of thresholds, and wherein each threshold of the plurality of thresholds defines a different level of prominence for displaying the historical patient information; and
displaying the historical patient information on a graphical user interface in accordance with the determined level of prominence such that historical patient information satisfying a first threshold of the plurality of thresholds is displayed in a first manner and historical patient information satisfying a second threshold of the plurality of thresholds is displayed in a second manner.

US Pat. No. 10,431,338

SYSTEM AND METHOD FOR WEIGHTING MANAGEABLE PATIENT ATTRIBUTES DURING CRITERIA EVALUATIONS FOR TREATMENT

International Business Ma...

1. A computer-implemented method for evaluating attribute values to determine eligibility for a first treatment, the computer-implemented method comprising:responsive to receiving input regarding a first patient, determining a topic based on parsing the received input using natural language processing, the topic comprising a request to identify treatment protocols for which the first patient can be eligible, wherein the topic is determined by a question classifier component of an application and stored in a feature store;
determining, based on a corpus and by a pipeline execution component of the application, a set of required attributes associated with a treatment protocol associated with the first treatment, wherein the pipeline execution component reduces processing of sources in the corpus that do not pertain to the stored topic;
responsive to receiving a case, wherein the case includes a patient history containing patient attribute values for the first patient, identifying, by an attribute verification component of the application, a first patient attribute value that does not satisfy a first attribute specified by the treatment protocol as a required attribute;
determining that the first patient is not currently eligible to receive the first treatment, based on determining that the first patient attribute value does not satisfy the first attribute specified by the treatment protocol;
upon determining that the first patient is not currently eligible to receive the first treatment, determining, by operation of one or more computer processors and based on evaluating the patient history using one or more machine learning models, a likelihood that the patient will meet the first attribute in the future due to a change in the first patient attribute value, thereby determining potential eligibility of the first patient for the treatment protocol with a greater measure of accuracy than absent determining the likelihood, wherein the likelihood is determined based on an upward or downward trend of the first patient attribute value and based further on an extent by which the first patient attribute value differs from the required attribute; and
causing approval, based on the determined likelihood, of the first patient for receiving the treatment protocol, whereafter the treatment protocol is applied to the first patient, wherein absent determining the likelihood, the first patient would have been denied from receiving the treatment protocol.

US Pat. No. 10,431,337

SYSTEM AND METHOD FOR WEIGHTING MANAGEABLE PATIENT ATTRIBUTES DURING CRITERIA EVALUATIONS FOR TREATMENT

International Business Ma...

1. A system for evaluating attribute values to determine eligibility for a first treatment, the system comprising:one or more computer processors; and
a memory containing a program which, when executed by the one or more computer processors performs an operation comprising:
responsive to receiving input regarding a first patient, determining a topic based on parsing the received input using natural language processing, the topic comprising a request to identify treatment protocols for which the first patient can be eligible, wherein the topic is determined by a question classifier component of an application and stored in a feature store;
determining, based on a corpus and by a pipeline execution component of the application, a set of required attributes associated with a treatment protocol associated with the first treatment, wherein the pipeline execution component reduces processing of sources in the corpus that do not pertain to the stored topic;
responsive to receiving a case, wherein the case includes a patient history containing patient attribute values for the first patient, identifying, by an attribute verification component of the application, a first patient attribute value that does not satisfy a first attribute specified by the treatment protocol as a required attribute;
determining that the first patient is not currently eligible to receive the first treatment, based on determining that the first patient attribute value does not satisfy the first attribute specified by the treatment protocol;
upon determining that the first patient is not currently eligible to receive the first treatment, determining, based on evaluating the patient history using one or more machine learning models, a likelihood that the patient will meet the first attribute in the future due to a change in the first patient attribute value, thereby determining potential eligibility of the first patient for the treatment protocol with a greater measure of accuracy than absent determining the likelihood, wherein the likelihood is determined based on an upward or downward trend of the first patient attribute value and based further on an extent by which the first patient attribute value differs from the required attribute; and
causing approval, based on the determined likelihood, of the first patient for receiving the treatment protocol, whereafter the treatment protocol is applied to the first patient, wherein absent determining the likelihood, the first patient would have been denied from receiving the treatment protocol.

US Pat. No. 10,431,335

MOBILE APPLICATIONS FOR MEDICAL DEVICES

Fenwal, Inc., Lake Zuric...

16. A computer-implemented method for medical device management using a handheld mobile device, said method comprising:providing, via a handheld mobile device graphical user interface, a representation of one or more medical devices, the medical devices comprising at least one of a blood processing device, an infusion pump, and a drug delivery device, with a visual indication of a status for each medical device, the representation visually conveying information regarding each of the one or more medical devices and selectable by a user to provide additional information regarding each of the one or more medical devices;
updating the status for each medical device via wireless communication with the handheld mobile device;
receiving an indication of an alarm code at the handheld mobile device, the alarm code representing an alarm or error condition of one or more of the medical devices;
providing information at the handheld mobile device to assist a user in handling the alarm or error condition of the one or more of medical devices; and
displaying an inventory of available products for the one or more medical devices at a healthcare facility and facilitating inventory control via the mobile device.

US Pat. No. 10,431,334

PERFORMING AN APHERESIS PROCEDURE ON A HUMAN SUBJECT WITH IDENTITY CONFIRMATION

Fenwal, Inc., Lake Zuric...

1. A system for performing an apheresis procedure on a human subject, comprising:an apheresis treatment device configured to draw blood from a human subject, separate the blood by blood component, and return at least one of the components to the human subject; and
a remote data storage device located remotely from the apheresis treatment device and configured to communicate with the apheresis treatment device over a network, the remote data storage device programmed with a plurality of subject data entries, each subject data entry associated with a human subject, each subject data entry comprising subject-specific information, the remote data storage device configured to download subject-specific information comprising a name and a birth date from the subject data entry and further configured to program the apheresis treatment device with a plurality of parameters for the apheresis medical procedure;
the apheresis treatment device comprising:
a wireless circuit configured to communicate with the remote data storage device;
a touch screen configured to receive an input; and
a controller configured to confirm an identity of the human subject based on the input and, based at least in part on the result of the confirmation, provide access to an apheresis procedure operated according to the programmed parameters on the apheresis treatment device.

US Pat. No. 10,431,333

SYSTEMS AND METHOD FOR DEVELOPING RADIATION DOSAGE CONTROL PLANS USING A PARETOFRONT (PARETO SURFACE)

Fraunhofer Gesellschaft z...

1. A system for selecting a desired portion of a subject to receive a radiation dose the system comprising: a radiation apparatus, a computer, the computer comprising multiple cores and wherein a Pareto Surface is developed for intensity modulated radiation therapy (IMRT) or volumetric arc therapy (VMAT) planning and controlling delivery of radiation to the desired portion of the subject by adjusting, based on an IMRT or VMAT treatment plan including the developed Pareto Surface, positions of movable elements of the radiation apparatus;the system further comprising a non-transitory computer readable medium having computer readable program code thereon, the computer readable program code comprising a series of computer readable program steps to develop the Pareto Surface for said intensity modulated radiation therapy (IMRT) or volumetric arc therapy (VMAT);
and comprising
a) Covering the yet un-determined Pareto surface by a set of m-dimensional boxes, the Pareto surface having a plurality of points wherein at least three points from the plurality of points are selected and by solving a Pascoletti-Serafini problem along a diagonal of a corresponding box;
b) Applying a measure to find the largest available box;
c) Comparing the measure to a threshold value and update the set of boxes;
d) Repeating steps b) and c) along a first direction (q1) until the measure of the corresponding box is below the threshold value and using a first core of the computer, comprising said multiple cores for repeating the steps;
e) Selecting the second point on the Pareto surface and repeating steps corresponding to steps b) and c) along a second direction (q2) using the second core of the computer comprising the multiple cores;
f) Selecting the third point on the Pareto surface and repeating steps corresponding to steps b) to d) along a third direction (q3) using the third core of the computer comprising the multiple cores until the measure of the corresponding box is below the threshold value.

US Pat. No. 10,431,332

MEDICAL ASSISTANCE DEVICE, OPERATION METHOD AND OPERATION PROGRAM FOR MEDICAL ASSISTANCE DEVICE, AND MEDICAL ASSISTANCE SYSTEM

FUJIFILM Corporation, To...

1. A medical assistance device, comprising:a storage device, configured to store historical medical data of a patient, a plurality of diagnostic assistance programs, and recommended data ranges preset for each of the diagnostic assistance programs;
a processor, configured to:
control a diagnostic assistance program, selected from among the plurality of diagnostic assistance programs, that is executed to perform calculation using medical data of the patient as input data and output a result of the calculation as diagnostic assistance information for assisting diagnosis of the patient, wherein the medical data of the patient is extracted from the historical medical data of the patient;
receive an input of a designated data range, which is designated as a range to be used for the input data, of the medical data, wherein the input of the designated data range is input by a medical staff other than the patient;
acquire a recommended data range, from the stored recommended data ranges, that is preset for the selected diagnostic assistance program and is recommended as a range to be used for the input data, of the medical data of the patient; and
in response to determining a difference between the designated data range and the recommended data range display difference information indicating the difference on a graphical user interface configured to display the diagnostic assistance information.

US Pat. No. 10,431,331

COMPUTER-EXECUTABLE APPLICATION THAT IS CONFIGURED TO PROCESS CROSS-CLINICAL GENOMICS DATA

ALLSCRIPTS SOFTWARE, LLC,...

1. A computing system comprising:at least one processor; and
memory that has an application loaded therein, wherein the application, when executed by the at least one processor, is configured to perform acts comprising:
responsive to receipt of an identifier of a patient:
retrieving clinical data about the patient based upon the identifier of the patient, the clinical data being accessible by the application and identifies health problem of the patient;
applying a rule for a genetic disorder to the health problem identified in the clinical data;
determining using the rule that the patient is a candidate for genetic testing for the genetic disorder;
causing graphical data to be presented on a display of a computing device, the graphical data indicating to a clinician that the patient is a candidate for genetic testing for the genetic disorder;
based upon determining that the patient is a candidate for genetic testing for the genetic disorder, transmitting an order for a genetic test for the genetic disorder to a genetics lab computing device that is in network communication with the computing system;
receiving results for the genetic test from the genetics lab computing device; and
causing a visualization based upon the results to be presented on the display of the computing device, wherein the visualization is based on a relationship between:
a body system affected by the genetic disorder;
the genetic disorder; and
a genetic mutation associated with the genetic disorder, and further wherein the visualization comprises:
a first group of icons assigned to body systems of the patient, the body system that is affected by the genetic disorder is included in the body systems;
a second group of icons assigned to genetic disorders of the body systems, the genetic disorder is included in the genetic disorders; and
a third group of icons assigned to genetic mutations that cause the genetic disorders, the genetic mutation that is associated with the genetic disorder that is tested for in the genetic test is included in the genetic mutations,wherein the relationship is indicated in the visualization by a visually perceptible connection between a first icon corresponding to the body system from the first group, a second icon corresponding to the genetic disorder from the second group, and a third icon corresponding to the genetic mutation from the third group, the relationship being between the body system, the genetic disorder, and the genetic mutation.

US Pat. No. 10,431,330

METHOD AND SYSTEM TO PROVIDE PATIENT INFORMATION AND FACILITATE CARE OF A PATIENT

1. A method comprising:retrieving, by a server computer system, patient medical records pertaining to a patient;
processing, by the server computer system, the patient medical records to extract patient medical data pertaining to the patient, wherein said processing includes, by the server computer system,
accessing medical record datasets of a plurality of different types, associated with the patient,
identifying one or more first data fields in the medical record datasets as being relevant to a particular medical condition of the patient,
identifying one or more second data fields in the medical record datasets as having been classified as being classified as sensitive or protected information,
flagging the identified first data fields and the identified second data fields for subsequent processing, and
merging at least portions of the medical record datasets of the plurality of different types, including the flagged first data fields and second data fields, into a single database record for the patient;
creating, by the server computer system, a patient webpage specific to the patient from the single database record for the patient, the patient webpage including the patient medical data, wherein said creating the patient webpage includes creating the patient webpage to include the one or more first data fields in the patient webpage and to omit the one or more second data fields from the patient webpage, based on said flagging;
providing a wallet-size patient identification card associated with a patient, the patient identification card including a processor, an embedded fingerprint scanner, a memory to store a fingerprint of the patient, and a display device, the patient identification card further having an indicator disposed thereon, the indicator being a network resource locator corresponding to the patient webpage or a machine-readable code representing the network resource locator corresponding to the patient webpage;
receiving, by the server computer system, from a second computer, a request corresponding to the network resource locator, the request having been sent by the second computer in response to the second computer having received as input the network resource locator or an image of a machine readable code corresponding to the network resource locator, the request having been sent by the second computer in connection with the patient being treated by or seeking treatment or advice from a first health care provider other than a primary care physician of the patient;
the processor of the patient identification card being configured to cause the embedded fingerprint scanner of the wallet-size patient identification card to acquire a fingerprint of a person and to compare the acquired fingerprint to a stored fingerprint of the patient stored in the memory and, when the acquired fingerprint matches the stored fingerprint, to cause a personal identifier to be displayed on the display device of the patient identification card;
receiving the personal identifier at the server computer system from the second computer system, after the personal identifier is provided as input to the second computer by a user in response to display of the personal identifier by the display device of the patient identification card;
determining, by the server computer system, whether the personal identifier is correct;
in response to determining that the personal identifier is correct, transmitting, by the server computer system, the patient webpage to the second computer; and
in response to the network resource locator being accessed in connection with the patient being treated by or seeking treatment or advice from the first health care provider other than the primary care physician of the patient, automatically generating a notification message to the primary care physician of the patient, indicative that the patient webpage has been accessed, wherein the patient webpage is not owned or controlled by the first health care provider or the primary care physician of the patient.

US Pat. No. 10,431,329

REAL-TIME SYMPTOM ANALYSIS SYSTEM AND METHOD

1. A method of presenting real-time health information, the method comprising steps of:(a) administering by a user interface associated with a mobile device, a virtual questionnaire to obtain information regarding the user's symptoms,
(b) determining the location of the user using a location determination circuit associated with the mobile device;
(c) obtaining environmental data from an internet-accessible database corresponding with the user's local environmental conditions at the time the questionnaire is administered;
(d) automatically by a processor associated with the mobile device determining the health status of the user based on the user's response to the virtual questionnaire;
(e) storing the health status of the user and corresponding environmental data in a data store associated with the mobile device;
(f) developing a data structure from which the health status of the user is correlated with the user's local environmental conditions to identify causes of symptoms for the user;
(g) repeating steps (a) through (e) a plurality of different times, and recorrelating health status with the user's local environmental conditions to refine and enhance the data structure;
(h) determining at predetermined times the location of the user using the location determination circuit of the mobile device;
(i) obtaining current or predicted environmental data from the internet-accessible database at the location determined in step (h) contemporaneously with step (h);
(j) predicting future symptoms based upon the data structure and current or predicted local environmental conditions determined in step (i);
(k) determining whether to deliver a warning of environmental risks that are predicted to induce symptoms in the user; and
(l) presenting by a display associated with the mobile device a visualization indicative of the future symptoms if it is determined that a warning is to be delivered wherein presenting the visualization includes:
generating a map image;
overlaying a plurality of animated particles over the map image; and
displaying the map image and the plurality of animated particles on the display.

US Pat. No. 10,431,328

METHOD AND SYSTEM FOR ANATOMICAL TREE STRUCTURE ANALYSIS

BEIJING CURACLOUD TECHNOL...

1. A computer-implemented method for an anatomical tree structure analysis, comprising the following steps:receiving a task of the anatomical tree structure analysis;
setting, by a processor, a set of positions in an anatomical tree structure, wherein the anatomical tree structure represents a vessel or an airway;
determining, by the processor, a model input at each position among the set of positions on the basis of the task;
selecting, by the processor, an encoder for each position on the basis of the task, wherein the encoder is configured to receive the model input at each position and extract features for the corresponding position;
constructing, by the processor, a tree structured recurrent neural network (RNN) with nodes corresponding to the set of positions, by selecting an RNN unit for each node on the basis of the task and setting an information propagation among the nodes on the basis of spatial constraints of the set of positions in the anatomical tree structure, wherein each encoder is connected with the corresponding node of the tree structured RNN; and
providing the tree structured RNN for performing the task of the anatomical tree structure analysis.

US Pat. No. 10,431,327

COMPUTER GRAPHICAL USER INTERFACE WITH GENOMIC WORKFLOW

Palantir Technologies Inc...

1. A method comprising:presenting, in a graphical user interface, graphical components representing a source from which one or more nucleic acid sequences are to be obtained and one or more sets of instructions for processing data, including at least one set of instructions for processing the one or more nucleic acid sequences, wherein the source and the one or more sets of instructions are represented as nodes within a workspace;
wherein the source and the one or more sets of instructions are arranged as a workflow comprising a series of nodes, the series of nodes indicating, for each particular set of instructions of the one or more sets of instructions, that output from one of the source or another particular set of instructions is to be input into the particular set of instructions;
generating an output for the workflow, wherein the output comprises a set of one or more items of genomic data that are based upon the one or more nucleic acid sequences that are processed by each set of instructions of the one or more sets of instructions in an order indicated by the series of nodes;
generating a first data node from the output, the first data node comprising the set of one or more items of genomic data, the first data node linked to a last set of instructions in the series;
receiving, via the graphical user interface, a first input that selects a subset of one or more items of genomic data from the set of one or more items of genomic data in the first data node;
receiving, via the graphical user interface, a second input that moves the subset of one or more items of genomic data to a location on the graphical user interface not associated with the first data node;
generating a second data node comprising the subset of one or more items of genomic data, wherein the output for the workflow is reconfigured to generate multiple data nodes; and
wherein the method is performed by one or more computing devices.

US Pat. No. 10,431,324

DATA STORAGE DEVICE FOR PERFORMING DECODING OPERATION AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A data storage device comprising:a nonvolatile memory device configured to store a codeword; and
a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword,
wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.

US Pat. No. 10,431,322

MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system, comprising:a memory device including;
a bit line;
a word line;
a first string coupled to the bit line via a first transistor and including a first cell transistor; and
a second string coupled to the bit line via a second transistor and including a second cell transistor, the second cell transistor and the first cell transistor being coupled to the word line; and
a controller configured to:
instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor; and
instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.

US Pat. No. 10,431,321

EMBEDDED TRANSCONDUCTANCE TEST CIRCUIT AND METHOD FOR FLASH MEMORY CELLS

Integrated Silicon Soluti...

1. A transconductance test method implemented in a flash memory device, the flash memory device comprising a two-dimensional array of memory cells, the method comprising:after an erase operation applied to one or more memory cells of the flash memory device, selecting a first test step as a present test step;
applying a first bias level of the present test step to a control terminal of a selected memory cell;
measuring a cell current of the selected memory cell in response to the first bias level of the present test step being applied to the control terminal;
determining if the cell current is greater than a first reference level;
in response to the cell current being greater than the first reference level, setting an indicator for the selected memory cell;
applying a second bias level of the present test step to the control terminal of the selected memory cell, the second bias level being the first bias level plus a predetermined margin;
measuring the cell current of the selected memory cell in response to the second bias level of the present test step being applied to the control terminal;
determining if the cell current is greater than a second reference level, the second reference level being greater than the first reference level; and
in response to the indicator for the selected memory cell being set and in response to the cell current being less than the second reference level, storing a memory cell address associated with the selected memory cell in a memory, the stored memory cell address indicating the selected memory cell has been detected to have a low transconductance value.

US Pat. No. 10,431,320

SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of testing a semiconductor memory device comprising a memory cell block including a plurality of memory cells, a first group of word lines coupled to first memory cells among the plurality, and a second group of word lines coupled to second memory cells among the plurality that alternate with the first group, the method comprising:writing data to the first and second memory cells during a first period;
applying a first boosted voltage to the second group of word lines and a second boosted voltage to the first group of word lines during a second period after the first period, wherein the first boosted voltage has a voltage level different from that of the second boosted voltage; and
reading the data from the first memory cells coupled to the first group of the word lines during a third period after the second period to determine whether each of the first memory cells is defective.

US Pat. No. 10,431,319

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells; and
a controller, wherein the controller is coupled to the array of memory cells and includes control circuitry configured to:
store a number of sets of trim settings; and
select a particular set of trims settings of the number of sets of trim settings including particular trim setting parameters based on desired operational characteristics for the array of memory cells, wherein the particular trim setting parameters include programming signal magnitude, sensing signal magnitude, erase signal magnitude, programming signal length, erase signal length, and sensing signal length.

US Pat. No. 10,431,318

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a ninth transistor,
wherein:
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have a same conductivity type;
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to the second wiring;
the other of the source and the drain of the second transistor is electrically connected to a third wiring;
one of a source and a drain of the third transistor is electrically connected to a fourth wiring;
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;
one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor;
the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring;
a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;
the first conductive layer is configured to be the gate of the first transistor;
the third conductive layer is configured to be a gate of the third transistor, and
the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor.

US Pat. No. 10,431,317

MEMORY SYSTEM

NXP B.V., Eindhoven (NL)...

1. A memory system comprising:a memory cell comprising:
a poly-fuse-resistor,
a bipolar junction transistor having a collector-emitter channel and a base-terminal, wherein the collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal; and the base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor, and
a NOR logic gate having p-channel transistors configured to provide the transistor-control-signal.

US Pat. No. 10,431,315

OPERATION METHOD OF A NONVOLATILE MEMORY DEVICE FOR CONTROLLING A RESUME OPERATION

SAMSUNG ELECTRONICS CO., ...

1. An operation method of a nonvolatile memory device for erasing a selected memory block from among a plurality of memory blocks, the method comprising:performing an erase operation;
suspending the erase operation after performing a first portion of the erase operation;
resuming the erase operation to perform a second portion of the erase operation, wherein the erase operation is resumed when a resume time, which is a time elapsed since the erase operation was suspended, is less than a reference time, wherein the reference time is a length of time for securing reliability of the erase operation with respect to a threshold voltage distribution of the suspended erase operation; and
erasing a memory block different than the selected memory block when the resume time is equal to or greater than the reference time.

US Pat. No. 10,431,314

NON-VOLATILE MEMORY DEVICE FOR IMPROVING DATA RELIABILITY AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A non-volatile memory device, comprising:a memory cell array comprising a plurality of memory cells connected to a plurality of word lines, some of the plurality of word lines corresponding to a deterioration area; and
a voltage generator configured to generate a program voltage provided to the plurality of memory cells through the plurality of word lines,
wherein control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the plurality of word lines,
wherein the deterioration area comprises word lines of a first group, where data of at least one first bit is written in each of the plurality of memory cells, and word lines of a second group where data of at least two second bits is written in each of the plurality of memory cells, wherein the at least two second bits are more than the at least one first bits, and
wherein the control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.

US Pat. No. 10,431,313

GROUPING MEMORY CELLS INTO SUB-BLOCKS FOR PROGRAM SPEED UNIFORMITY

SanDisk Technologies LLC,...

1. A memory device, comprising:a set of NAND strings which extends through a plurality of word line layers, wherein the plurality of word line layers are vertically spaced apart from one another by dielectric layers in a stack, the set of NAND strings comprises one row of NAND strings at one distance from a first edge of the plurality of word line layers and another row of NAND strings at another distance from the first edge of the plurality of word line layers, greater than the one distance; and
a control circuit configured to program the one row of NAND strings and to separately program the another row of NAND strings, wherein the control circuit is configured to program the one row of NAND strings using incremental step pulse programming with one initial program voltage and to program the another row of NAND strings using incremental step pulse programming with another initial program voltage which is higher than the one initial program voltage.

US Pat. No. 10,431,312

NONVOLATILE MEMORY APPARATUS AND REFRESH METHOD THEREOF

Winbond Electronics Corp....

1. A non-volatile memory apparatus, comprising:a non-volatile memory; and
a control circuit, coupled to the non-volatile memory and refreshing a non-selected block when an erasing operation is performed, wherein the non-selected block comprises a plurality of memory sectors, each of the memory sectors comprises a plurality of memory cells, and the control circuit determines whether threshold voltages of the memory cells in the memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, wherein the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage,
wherein the control circuit further determines whether a first memory sector to which a current address corresponds comprises the memory cell having the threshold voltage larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage, and if the first memory sector to which the current address corresponds does not comprise the memory cell having the threshold voltage larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage, a refresh operation of the remaining memory sectors in the non-selected block is skipped to complete the refresh operation of the non-selected block.

US Pat. No. 10,431,311

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a plurality of conductors being stacked with insulators being interposed therebetween;
a pillar through the plurality of conductors, the pillar including a first pillar portion, a second pillar portion above the first pillar portion, and a joint portion between the first pillar portion and the second pillar portion, the pillar functioning as a transistor in parts where the pillar crosses the respective conductors; and
a controller configured to perform a write operation, wherein
among the plurality of conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line,
among the plurality of conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line,
the controller
performs a program loop which includes a program operation in the write operation, the program operation including a pre-charge operation,
applies a first voltage higher than a ground voltage to the first word line, the first dummy word line, the second dummy word line, and the second word line, in the pre-charge operation in the write operation for which the first word line is selected,
applies a second voltage lower than the first voltage to the first word line, and applies the first voltage to the second dummy word line and the second word line, in the pre-charge operation in the write operation for which the second word line is selected.

US Pat. No. 10,431,310

BOOSTED CHANNEL PROGRAMMING OF MEMORY

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:boosting a channel voltage of a first memory cell selected for programming to a first voltage level for a particular programming pulse, and boosting a channel voltage of a second memory cell selected for programming to a second voltage level for the particular programming pulse;
boosting the channel voltage of the first memory cell selected for programming to a third voltage level, greater than the first voltage level, for a subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a fourth voltage level, greater than the second voltage level, for the subsequent programming pulse; and
boosting the channel voltage of the first memory cell selected for programming to a fifth voltage level, greater than the third voltage level, for a next subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a sixth voltage level, greater than the fourth voltage level, for the next subsequent programming pulse;
wherein the sixth voltage level is greater than the fifth voltage level;
wherein a difference between the third voltage level and the first voltage level is the same as a difference between the fifth voltage level and the third voltage level;
wherein a difference between the fourth voltage level and the second voltage level is the same as a difference between the sixth voltage level and the fourth voltage level;
wherein the second memory cell is selected for programming to a data state corresponding to a range of threshold voltages less than a range of threshold voltages corresponding to a data state to which the first memory cell is selected for programming; and
wherein the difference between the third voltage level and the first voltage level is different than the difference between the fourth voltage level and the second voltage level.

US Pat. No. 10,431,309

SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a bit line;
a source line;
a memory cell unit including
a first selection transistor connected to the bit line,
a second selection transistor connected to the source line, and
a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including
a first memory cell,
a second memory cell located closer to the first selection transistor than the first memory cell,
a third memory cell located closer to the first selection transistor than the second memory cell, and
a fourth memory cell located closer to the first selection transistor than the third memory cell;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a third word line connected to the third memory cell;
a fourth word line connected to the fourth memory cell;
a driver circuit configured to apply a voltage to
the first word line,
the second word line,
the third word line, and
the fourth word line;
a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the driver circuit;
a second transistor connected between the second word line and the driver circuit;
a third transistor connected between the third word line and the driver circuit; and
a fourth transistor connected between the fourth word line and the driver circuit,
wherein when data is written into the first memory cell,
a first voltage is applied to
the first word line,
a second voltage is applied to
the second word line,
a third voltage is applied to
the third word line, and
a fourth voltage is applied to
the fourth word line,
wherein the first voltage is larger than the second voltage, the third voltage and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage,
wherein the second word line, the third word line, and the fourth word line are not located above the first diffused layer and the second diffused layer, and
wherein each of the first word line, the second word line, the third word line, and the fourth word line is arranged in a first direction,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor has a gate length in a second direction perpendicular to the first direction,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in the first direction, and
wherein a distance between the first transistor and the memory cell unit is smaller than a distance between the second transistor and the memory cell unit.

US Pat. No. 10,431,308

MEMORY CELL SIZE REDUCTION FOR SCALABLE LOGIC GATE NON-VOLATILE MEMORY ARRAYS

Flashsilicon Incorporatio...

1. An array of nonvolatile memory (NVM) cells comprising:a plurality of source lines and bit lines; and
a plurality of NVM cells organized in rows and columns on a substrate, each NVM cell having a source region, a drain region, a floating gate, a control gate region and a channel region, the NVM cells in a row being arranged in cell pairs, such that each cell pair comprises a sharing source region connected to a common source line and two drain regions connected to two different bit lines, wherein two drain regions of any two column-adjacent NVM cells in each row are connected to two different bit lines;
wherein the floating gate is disposed over and insulated from both the channel region and the control gate region and the floating gate extends in a column direction from the channel region to the control gate region, and wherein a gate width of the floating gate are aligned with the boundaries of the channel region and the control gate region without protruding from the channel region and the control gate region;
means for processing the array with CMOS logic technologies;
wherein the means for processing the array with CMOS logic technologies limits a gate length of the floating gate to a minimal feature size of a process technology node; and
wherein the control gate region, the source region and the drain region have the same conductivity type; and
wherein a control gate length of the array is perpendicular to the bit lines.

US Pat. No. 10,431,307

ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIONS WITH CONTENT ADDRESSABLE MEMORY (CAM) CIRCUITS

INTERNATIONAL BUSINESS MA...

1. A circuit comprising:a first portion of a content addressable memory (CAM) configured to perform a first inequality operation implemented between 1 to n CAM entries, wherein the 1 to n CAM entries of the first portion are read from left to right to perform the first inequality operation;
a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries, wherein the 1 to n CAM entries of the second portion are read from right to left to perform the second inequality operation;
a first matchline configured to indicate a match or mismatch for each of the 1 to n CAM entries implemented in the first portion; and
a second matchline configured to indicate a match or mismatch for each of the 1 to n CAM entries implemented in the second portion,
wherein the first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines,
wherein two valid bits are provided for each of the 1 to n CAM entries as extra bits, in addition to data bits defining each of the 1 to n CAM entries, to indicate that the data bits defining each of the 1 to n CAM entries comprise a valid pattern,
wherein the first and second portions of the CAM are each comprised of binary CAM (BCAM) cells,
wherein, for each 1 to n CAM entry, the valid bit is latched in a latch circuit, wherein the latch circuit is coupled to a precharge driver for the first and second matchlines such that the first and second matchlines will only be precharged when the valid bit for a corresponding one of the 1 to n CAM entries is latched in the latch circuit, and
wherein, for each 1 to n CAM entry, one valid bit is provided for the first matchline and another valid bit is provided for the second matchline.

US Pat. No. 10,431,306

RECONFIGURABLE SEMICONDUCTOR INTEGRATED CIRCUIT

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor integrated circuit comprising:first wiring lines;
at least two second wiring lines intersecting with the first wiring lines;
third wiring lines intersecting with the first wiring lines;
first memory elements disposed in a cross region between the first wiring lines and the second wiring lines, at least one of the first memory elements including a first terminal connected to corresponding one of the first wiring lines and a second terminal connected to corresponding one of the second wiring lines;
second memory elements disposed in a cross region between the first wiring lines and the third wiring lines, at least one of the second memory elements including a third terminal connected to corresponding one of the first wiring lines and a fourth terminal connected to corresponding one of the third wiring lines;
a first write control circuit connected to the first wiring lines;
a first circuit connected to one of the second wiring lines, the first circuit supplying a first potential;
a second circuit connected to the other one of the second wiring lines, the second circuit supplying a second potential lower than the first potential;
SRAM cells disposed to correspond to the third wiring lines, and at least one of the SRAM cells being connected to corresponding one of the third wiring lines; and
a selection circuit including input terminals corresponding to the first wiring lines and an output terminal, each of the input terminals being electrically connected to corresponding one of the first wiring lines, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

US Pat. No. 10,431,305

HIGH-PERFORMANCE ON-MODULE CACHING ARCHITECTURES FOR NON-VOLATILE DUAL IN-LINE MEMORY MODULE (NVDIMM)

Advanced Micro Devices, I...

1. A hybrid memory module, comprising:a first non-volatile memory;
a first integrated control buffer coupled directly to the first non-volatile memory, wherein the first integrated control buffer operates as both a data buffer and a multiplexer; and
a first volatile memory and a first volatile memory tag unit coupled directly to the first integrated control buffer, wherein the first integrated control buffer is integrated with first cache integration logic to perform cache operations and the first integrated control buffer performs data multiplexing between at least two of the first non-volatile memory, the first volatile memory, and the first volatile memory tag unit, wherein the cache operations include at least one of instructing the first non-volatile memory and the first volatile memory to load a cache line when a miss operation occurs, write back to the cache line when an eviction occurs, or read the cache line when a hit operation occurs.

US Pat. No. 10,431,304

METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

ARM Ltd., Cambridge (GB)...

1. A method comprising:applying a first programing signal across first and second terminals of a correlated electron switch (CES) element to place the CES element in a conductive or low impedance state;
applying a second programming signal across the first and second terminals to place the CES element in an insulative or high impedance state, the second programming signal comprising a second voltage across the first and second terminals; and
applying a third voltage across the first and second terminals as a supply voltage during a read operation, and wherein a magnitude of the third voltage is equal or greater to a magnitude of the second voltage.

US Pat. No. 10,431,303

RESISTANCE CHANGE TYPE MEMORY INCLUDING WRITE CONTROL CIRCUIT TO CONTROL WRITE TO VARIABLE RESISTANCE ELEMENT

NATIONAL INSTITUTE OF ADV...

1. A resistance change type memory comprising:a variable resistance element connected between a first bit line and a second bit line;
a write control circuit including
a first transistor including a first terminal connected to the first bit line;
a second transistor including a second terminal connected to the first bit line;
a first element including a first output terminal outputting a first signal which controls ON and OFF of the first transistor;
a first interconnect connected to the first output terminal; and
a second element including a first input terminal connected to the first interconnect, and a second output terminal outputting a second signal which controls ON and OFF of the second transistor, the second signal being based on the first signal from the first interconnect,
the write control circuit controlling write to the variable resistance element;
a second interconnect supplied with a first voltage and connected to the first bit line via the first transistor; and
a third interconnect supplied with a second voltage which is higher than the first voltage, and connected to the first bit line via the second transistor,
wherein the write control circuit:
supplies the first voltage to the first bit line via the first transistor which is in an ON state;
sets the second transistor in an ON state after supplying the first voltage; and
supplies the second voltage to the first bit line with a first pulse width via the second transistor which is in the ON state.

US Pat. No. 10,431,302

METHODS, ARTICLES, AND DEVICES FOR PULSE ADJUSTMENT TO PROGRAM A MEMORY CELL

Micron Technology, Inc., ...

1. A method, comprising:determining that a resistance value for a memory cell is lower than a previous resistance value for the memory cell;
adjusting a parameter of an electrical pulse based at least in part on determining that the resistance value is lower than the previous resistance value; and
applying the electrical pulse to the memory cell based at least in part on the adjusted parameter.

US Pat. No. 10,431,301

AUTO-REFERENCED MEMORY CELL READ TECHNIQUES

Micron Technology, Inc., ...

1. A method, comprising:initializing a counter in a controller coupled with a memory array;
activating at least a portion of a first group of memory cells of the memory array by applying a read voltage to the memory array;
determining that a set of memory cells has been activated based at least in part on applying the read voltage;
updating the counter to a first value based at least in part on determining that the set of memory cells has been activated;
comparing the first value of the updated counter to a threshold stored at the controller; and
reading one or more memory cells of the memory array based at least in part on the comparison.

US Pat. No. 10,431,300

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A nonvolatile memory device comprising:a memory cell array including a plurality of memory cells and dummy cells formed on a body;
a row decoder connected to the memory cells through word lines;
a dummy bit line bias circuit connected to the dummy cells through a dummy bit line;
a dummy word line bias circuit connected to the dummy cells through a plurality of dummy word lines;
a write driver and sense amplifier connected to the memory cells through bit lines;
a source line driver connected to the memory cells through a plurality of source lines; and
a leakage detector connected to the dummy cells through a dummy source line.

US Pat. No. 10,431,299

SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A semiconductor storage device comprising:a plurality of memory cells, each of the plurality of memory cells being capable of storing data of n bits (n is an integer equal to or larger than 3);
a word line which is connected to the plurality of memory cells; and
a control circuitry including a first latch circuitry, a second latch circuitry, a third latch circuitry, and a fourth latch circuitry, wherein the control circuitry is configured to;
in response to a first read request, perform a first read operation of reading first data out of the plurality of memory cells with a first voltage applied to the word line, and storing the first data in the second latch circuitry, and
in response to a second read request,
perform a second read operation of reading second data out of the plurality of memory cells with a second voltage within first voltage range and a third voltage within a second voltage range applied the word line, and storing the second data in the third latch circuitry, the first voltage range smaller than the first voltage, the second voltage range larger than the first voltage,
perform first logical operation of logically processing the first data stored in the second latch circuitry and the second data stored in the third latch circuitry,
store third data generated by the first logical operation in the first latch circuitry, and
output the third data stored in the first latch circuitry.

US Pat. No. 10,431,298

NONVOLATILE MEMORY AND WRITING METHOD

Toshiba Memory Corporatio...

1. A method for controlling a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store data by correlating three bits with eight threshold regions, the eight threshold regions corresponding to first to eighth threshold regions defined in ascending order of threshold voltage, each of the plurality of memory cells connected to a word line, the three bits respectively corresponding to first to third pages, a threshold voltage of an unwritten state of the memory cells being set at the first threshold region, the method comprising:when writing a first value to the first page of an unwritten memory cell, performing programming such that the threshold voltage of the unwritten memory cell is within the fifth threshold region;
when performing writing of the second page of the memory cell after the writing of the first page of the memory cell,
if a value corresponding to the first page of the memory cell is a second value and a value to be written to the second page is the first value, performing programming such that the threshold voltage of the memory cell is within the second threshold region, and
if a value corresponding to the first page of the memory cell is the first value and a value to be written to the second page is the first value, performing programming such that the threshold voltage of the memory cell is within the seventh threshold region;
when performing writing of the third page of the memory cell after the writing of the second page of the memory cell,
if a value corresponding to the first page of the memory cell is the second value, a value corresponding to the second page of the memory cell is the second value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the fourth threshold region,
if a value corresponding to the first page of the memory cell is the second value, a value corresponding to the second page of the memory cell is the first value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the third threshold region;
if a value corresponding to the first page of the memory cell is the first value, a value corresponding to the second page of the memory cell is the second value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the sixth threshold region,
if a value corresponding to the first page of the memory cell is the first value, a value corresponding to the second page of the memory cell is the first value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the eighth threshold region, and
when reading out data from the first page, reading out the data using a fourth read voltage, the fourth read voltage being a boundary voltage between the fourth threshold region and the fifth threshold region, and determining data of the first page on a basis of the read out data;
when reading out data from the second page, reading out the data using a first, a third and a sixth read voltage, the first read voltage being a boundary voltage between the first threshold region and the second threshold region, the third read voltage being a boundary voltage between the third threshold region and the fourth threshold region, the sixth read voltage being a boundary voltage between the sixth threshold region and the seventh threshold region, and determining data of the second page on a basis of the read our data; and
when reading out data from the third page, reading out the data using a second, a fifth and a seventh read voltage, the second read voltage being a boundary voltage between the second threshold region and the third threshold region, the fifth read voltage being a boundary voltage between the fifth threshold region and the sixth threshold region, the seventh read voltage being a boundary voltage between the seventh threshold region and the eighth threshold region, and determining data of the third page on a basis of the read out data.

US Pat. No. 10,431,297

SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in a matrix, each of the memory cells being capable of storing data of three bits including a first bit, a second bit, and a third bit; and
a control circuit which is configured to controls the memory cell array,
wherein the control circuit writes two-bit data of the first bit and the second bit to a first memory cell,
the control circuit subsequently writes two-bit data of the first bit and the second bit to a second memory cell adjacent to the first memory cell, and
the control circuit subsequently writes, to the first memory cell, three-bit data formed of the third bit and the two-bit data of the first bit and the second bit stored in the first memory cell.

US Pat. No. 10,431,296

SERIALIZED SRAM ACCESS TO REDUCE CONGESTION

Taiwan Semiconductor Manu...

1. A system, comprising:a plurality of memory arrays each comprising a plurality of columns having a plurality of bit-cells therein, wherein each of the plurality of memory arrays is configured to receive a serialized input signal and generate a serialized output signal;
a plurality of clock generators, wherein each of the plurality of clock generators is configured to generate an array-specific clock signal for a respective one of the plurality of memory arrays, and wherein the respective one of the plurality of memory arrays is configured to sequentially latch a respective bit of the serialized input signal or sequentially output a respective bit of the serialized output signal when the array-specific clock signal is active.

US Pat. No. 10,431,295

STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) comprising:a memory cell, wherein the memory cell comprises at least two p-type pass gates;
a bit line connected to the memory cell;
a bit line bar connected to the memory cell;
a word line connected to the memory cell;
an n-type transistor connected between a ground voltage and a first node;
a first inverter having an input terminal configured to receive a data signal and an output terminal connected to the word line, the first inverter being connected between a supply voltage and the first node; and
a voltage control unit configured to control the N-type transistor and to control the memory cell by providing an operating voltage on the first node which affects operation of the first inverter and thereby causes a voltage on the word line to undergo at least a double transition including a first transition to the ground voltage and then a second transition to an intermediate voltage which is greater than the ground voltage but substantially lower than the supply voltage; and
wherein:
the voltage control unit includes a p-type capacitor-connected transistor connected to the first node and thereby to the word line; and
the voltage control unit is further configured to selectively adjust voltages correspondingly of the bit line and the bit line bar.

US Pat. No. 10,431,294

WRITE LEVEL ARBITER CIRCUITRY

Micron Technology, Inc., ...

1. A semiconductor device comprising:memory comprising a group of storage elements;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory;
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory; and
arbiter circuitry configured to detect which phase of the plurality of phases captures a write start signal for the write command, wherein the arbiter circuitry comprises a latch that is configured to:
receive a first indication of a pulse in a first phase of the plurality of phases; and
receive a second indication of a pulse in a second phase of the plurality of phases.

US Pat. No. 10,431,293

SYSTEMS AND METHODS FOR CONTROLLING DATA STROBE SIGNALS DURING READ OPERATIONS

Micron Technology, Inc., ...

1. An apparatus comprising:a first data strobe (DQS) output buffer (OB) and a second DQS OB each coupled to a DQS terminal, the first DQS OB and the second DQS OB configured to provide a DQS signal to the DQS terminal responsive to a read clock signal; and
control logic configured to receive the read clock signal to control the first DQS OB and the second DQS OB,
wherein the apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

US Pat. No. 10,431,292

METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A COMMON BUS BY MULTIPLE COMPONENTS

Micron Technology, Inc., ...

1. An apparatus comprising:a first memory die;
a first bus;
a common bus; and
an interface control logic stacked with the first memory die and coupled to the first memory die through the first bus and the common bus, the interface control logic including:
a plurality of delay circuits configured to output a plurality of strobe signals having different amounts of delay from one another; and
a multiplexer configured to select a first one of the plurality of strobe signals, responsive to a first command, based on a type of the first command and a first latency of the first memory die, transferred through the common bus and output the first one of the plurality of strobe signals to the first bus;
wherein the first memory die is configured to capture the first command responsive to the first one of the plurality of strobe signals.

US Pat. No. 10,431,291

SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL VOLTAGE BOOSTING

Micron Technology, Inc., ...

1. A memory device, comprising:a memory array having at least one memory cell;
a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof;
a first bus configured to provide a first electric power to the sense amplifier circuit; and
a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell, wherein the first bus is electrically coupled to a first power supply, wherein the second bus is electrically coupled to a second power supply, and wherein the second power supply is configured to deliver a voltage higher than the first power supply.

US Pat. No. 10,431,290

PROTOCOL FOR MEMORY POWER-MODE CONTROL

Rambus Inc., Sunnyvale, ...

1. A dynamic random access memory (DRAM) device comprising:a memory core having a plurality of memory cells;
a command/address (CA) interface to receive command and address information;
a data interface to output data in response to a command received via the CA interface;
an interface to receive a power mode signal; and
a plurality of mode registers to store parameter values including a first parameter value that sets a power down mode for the CA interface and the data interface, such that a combination of the first parameter value and a level of the power mode signal determine which of the data interface and the CA interface are powered down in response to a transition in the level of the power mode signal, the parameter values further associated with a plurality of operating clock frequencies of a clock signal.