US Pat. No. 10,367,576

SYSTEM AND METHOD FOR DEMONSTRATION AND EVALUATION OF A NANOSATELLITE COMMUNICATION CONSTELLATION

The United States of Amer...

1. A system comprising:a computing device configured to implement a central user ground module that enables a user to emulate a plurality of central user ground nodes having fixed locations and that transmit and receive messages from at least one nanosatellite (nanosat);
a second computing device configured to implement a remote user ground module that enables a user to emulate a plurality of remote user ground nodes that do not have fixed locations and that transmit and receive messages from at least one nanosat, wherein each of the central user ground module and the remote user ground module include an orbit simulator configured to provide scenario data for a specified nanosat constellation, wherein the scenario data includes contact time windows; and
at least one additional computing device configured to implement a nanosat space module that emulates a nanosat, wherein the nanosat transmits and receives messages to and from the ground nodes.

US Pat. No. 10,367,575

HIGH POINTING ACCURACY SPACECRAFT

13. A method comprising:receiving, with a tracking receiver of a spacecraft payload subsystem, by way of an input multiplexer, multiplexed signals from a plurality of pseudo-monopulse (PSM) couplers, each PSM coupler being disposed proximate to a respective tracking feed element; and
adjusting the pointing of a plurality of antenna reflectors, responsive to the received multiplexed signals; wherein:
the spacecraft payload subsystem includes
the tracking receiver
an input multiplexer;
an antenna pointing mechanism (APM) controller; and
the plurality of antenna reflectors, each antenna reflector mechanically coupled with a respective APM, and illuminated by a respective tracking feed element, each respective tracking feed element being configured to receive a respective uplink beacon signal from the ground by way of one of the antenna reflectors and being coupled by way of a respective one of the plurality of PSM couplers and the input multiplexer to the tracking receiver;
the tracking receiver is configured to receive the multiplexed signals from the PSM couplers by way of the input multiplexer and output corresponding pointing error information to the APM controller;
the APM controller is configured to send commands to one or more of the APMs; and
each APM is configured to point a respective antenna reflector in response to the commands,
wherein each PSM coupler is disposed proximate to a respective tracking feed element, wherein each PSM coupler is communicatively coupled with a respective tracking feed element by a waveguide having a run length less than ten feet.

US Pat. No. 10,367,572

REPEATER SYSTEM AND METHOD

Andrew Wireless Systems G...

1. A repeater system, comprising:a host unit configured to:
receive a plurality of downlink signals from multiple communication sources located outside of a coverage area and combine the plurality of downlink signals into a combined downlink signal for transmission to one or more remote units, and
receive a combined uplink signal from the one or more remote units and produce a plurality of uplink signals from the combined uplink signal for transmission to the multiple communication sources; and
the one or more remote units communicatively coupled to the host unit, the one or more remote units configured to:
receive the combined downlink signal from the host unit and modulate the combined downlink signal according to at least one modulation scheme to produce a downlink RF communication signal for transmission into a coverage area to a plurality of user terminals located within the coverage area, and
receive uplink RF communication signals, from the plurality of user terminals located within the coverage area, and demodulate the received uplink RF communication signals to produce the combined uplink signal from the uplink RF communication signal for transmission to the host unit; and
multiplex modulated signals produced from the combined downlink signal to form the downlink RF communication signal for transmission into the coverage area;
wherein a first of the plurality of user terminals communicates with a different one of the multiple communication sources than a second of the plurality of user terminals.

US Pat. No. 10,367,570

ELECTRONIC DEVICES HAVING PRINTED CIRCUITS FOR ANTENNAS

Apple Inc., Cupertino, C...

1. An electronic device comprising:a substrate;
a radio-frequency transceiver;
control circuitry configured to generate control signals;
an antenna that includes an antenna resonating element arm, an antenna ground, and an antenna feed coupled between the antenna resonating element arm and the antenna ground;
a tunable component coupled to the antenna and configured to tune a frequency response of the antenna;
a flexible printed circuit; and
a connector that mechanically secures the flexible printed circuit to the substrate and that is electrically coupled to the radio-frequency transceiver and the control circuitry, wherein the flexible printed circuit comprises a radio-frequency transmission line coupled between the antenna feed and the connector and a control signal path coupled between the tunable component and the connector, the connector is configured to convey the radio-frequency signals between the radio-frequency transceiver and the radio-frequency transmission line on the flexible printed circuit, and the connector is configured to convey the control signals from the control circuitry to the control signal path on the flexible printed circuit.

US Pat. No. 10,367,569

PHASE ARRAY RECEIVER

ELECTRONICS AND TELECOMMU...

1. A phase array receiver comprising:a plurality of antennas configured to receive RF signals;
a plurality of low-noise amplifiers configured to receive the RF signals from the plurality of antennas and amplify the RF signals to generate a plurality of RF amplification signals;
a plurality of phase shifters configured to adjust a gain and a phase of the plurality of RF amplification signals to generate a plurality of RF phase adjustment signals;
a plurality of transconductors configured to convert the plurality of RF phase adjustment signals into a plurality of RF current signals based on a gain control signal;
a passive frequency mixer configured to receive a sum of the plurality of RF current signals and convert a frequency of the plurality of RF current signals to generate a mixed current signal; and
a transimpedance amplifier configured to convert the mixed current signal into a mixed voltage signal.

US Pat. No. 10,367,568

DETERMINING PRECODING COEFFICIENTS FOR FRONTHAUL LINKS IN A CLOUD RADIO ACCESS NETWORK

1. A baseband unit device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
determining a group of beamforming coefficients for a stream of data, wherein the group of beamforming coefficients comprises respective subgroups of beamforming coefficients that correspond to respective basis vectors;
determining spectral efficiencies associated with portions of the respective subgroups of beamforming coefficients;
selecting a portion of the respective subgroups of beamforming coefficients with a threshold spectral efficiency of the portions of the respective subgroups of the beamforming coefficients to add to a reduced size group of beamforming coefficients; and
transmitting the reduced size group of beamforming coefficients to a remote radio unit device to facilitate digital beamforming of a transmission to occur at the remote radio unit device.

US Pat. No. 10,367,566

TECHNIQUES FOR NON-COHERENT JOINT TRANSMISSIONS IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:receiving a communication configuration for reception of a first portion of a non-coherent joint transmission (NCJT) from a first transmission point (TP) and a second portion of the NCJT from the first TP or a second TP, wherein the communication configuration is received in a single downlink control information (DCI) transmission; and
receiving, based at least in part on the communication configuration, the first portion as a first codeword of a single-user multiple-input multiple-output (SU-MIMO) transmission and the second portion as a second codeword of the SU-MIMO transmission,
wherein the DCI transmission comprises a field to indicate antenna ports, a scrambling ID, and a number of layers for each of the first codeword and the second codeword that:
provides a same structure as a legacy SU-MIMO DCI transmission when only the first TP or the second TP is a serving cell; and
provides support for any available number of spatial layers for the first codeword and the second codeword when both the first TP and the second TP are serving cells.

US Pat. No. 10,367,564

CHANNEL STATE INFORMATION FEEDBACK METHOD AND RELATED DEVICE FOR FD MIMO SYSTEM

China Academy of Telecomm...

1. A method for feeding back channel state information in a Full-Dimension, FD, Multiple input Multiple Output, MIMO, system, the method comprising:receiving, by a terminal, a set of Channel State Information, CSI, feedback configurations, and configuration information for feeding back CSI based upon the set of CSI feedback configurations, indicated by a base station; and
measuring and feeding back, by the terminal, CSI according to the set of CSI feedback configurations, and the configuration information;
wherein the set of CSI feedback configurations comprises at least one CSI feedback configuration, and the CSI feedback configuration is a downlink signal configuration for measuring and feeding back downlink CSI;
wherein the configuration information comprises indication information of a downlink channel information item to be fed back over a Physical Uplink Control Channel, PUCCH;
wherein the indication information of a downlink channel information item to be fed back over a PUCCH is:
first indication information to be fed back over a PUCCH, which comprises positional information and CSI corresponding to the optimum CSI feedback configuration in the set of CSI feedback configurations; or
second indication information to be fed back over a PUCCH, which comprises positional information and CSI corresponding to a CSI feedback configuration, specified by the base station, in the set of CSI feedback configurations; or
third indication information to be fed back over a PUCCH, which comprises positional information and CSI corresponding to each CSI feedback configuration in the set of CSI feedback configurations.

US Pat. No. 10,367,563

BASE STATION DEVICE, WIRELESS TERMINAL DEVICE, AND WIRELESS COMMUNICATION METHOD

Panasonic Intellectual Pr...

1. A base station device comprising:frame generation circuitry that generates a first training frame used for receive beam training among frames used for beamforming training and generates at least one trailer as a second training frame, the receive beam training being beam refinement protocol (BRP);
beam controlling circuitry that sets a beam used to transmit the first training frame to an omnidirectional beam;
transmission circuitry that transmits the first training frame at the lowest Modulation and Coding Scheme (MCS) rate defined in IEEE 802.11 and omnidirectionally transmits the second training frame after omnidirectionally transmitting the first training frame;
reception circuitry that receives a first response frame and a second response frame from a wireless terminal device that has received the first training frame after a determined period since transmission of the first training frame; and
frame determination circuitry that determines whether the received first response frame is a response to the receive beam training,
wherein in a case where the received first response frame is a response to the receive beam training, the beam controlling circuitry sets a beam received by the receiver to a directional beam, and the reception circuitry receives the second response frame by using the directional beam.

US Pat. No. 10,367,557

ARTIFICIALLY MUTUAL-COUPLED ANTENNA ARRAYS

Nokia Solutions and Netwo...

1. An apparatus comprising at least one processor and at least one memory storing computer instructions, wherein the at least one processor is configured with the memory and the stored computer instructions to cause the apparatus to:create for a received or transmitted radio signal a precoding matrix WMC that includes artificial mutual antenna coupling coefficients; and
process the received or transmitted radio signal using the created precoding matrix WMC,
wherein the artificial mutual antenna coupling coefficients are selected so as to increase accuracy or coherence interval of a time-domain estimate of a channel over which the radio signal propagates, and
wherein the time-domain estimate of the channel is obtained via a linear prediction on taps of a virtually beamformed and artificially mutually coupled channel impulse response, said linear prediction per tap minimizing the normalized mean square error for the predicted channel state impulse response.

US Pat. No. 10,367,555

PRECODING METHOD, PRECODING DEVICE

Sun Patent Trust, New Yo...

1. A transmission apparatus comprising:encoding circuitry, which in operation, encodes a transmission data sequence to two encoded data sequences that are to be decoded by a reception apparatus;
modulation circuitry, which in operation, modulates the two encoded data sequences to two modulated symbol sequences;
precoding circuitry, which in operation, precodes the two modulated symbol sequences by using a precoding matrix expressed by Math. 1 to generate two precoded symbol sequences;

Orthogonal Frequency Division Multiplexing (OFDM) signal generation circuitry, which in operation, inverse fourier transforms the two precoded symbol sequences to two OFDM signals; and
transmission circuitry, which in operation, transmits the two OFDM signals from different antennas, wherein
in Math. 1, i is an integer that is zero or greater and varies for each modulated symbol, and ?21 satisfies Math. 2,

US Pat. No. 10,367,553

TRANSMISSION SCHEME FOR WIRELESS COMMUNICATION SYSTEMS

MEDIATEK INC., HsinChu (...

1. A method comprising:transmitting scheduling information from a serving base station to a user equipment (UE) for downlink transmission in a wireless communication network;
transmitting a UE-specific reference signal applied with a first precoding matrix, wherein the UE-specific resource signal is a demodulation reference signal (DMRS) configured for the UE and transmitted over predefined DMRS resource elements (REs); and
transmitting a data signal over data REs applied with a second precoding matrix, wherein the second precoding matrix can be represented by the first precoding matrix multiplied by a co-phasing cycling matrix, and wherein a ratio of an energy per resource element (EPRE) of data REs to an EPRE of the DMRS REs is 0 dB.

US Pat. No. 10,367,552

SIGNAL GENERATION METHOD AND SIGNAL GENERATION DEVICE

SUN PATENT TRUST, New Yo...

1. A broadcast signal generation method by a broadcast apparatus, comprising:applying a coding to a set of data bits to generate a first coded signal and a second coded signal;
applying a precoding to the first coded signal and the second coded signal according to a determined matrix F to generate a first precoded signal and a second precoded signal; and
applying a phase change to the second precoded signal to generate a second phase-changed signal, the phase change not being applied to the first precoded signal,,
wherein
the first precoded signal and the second phase-changed signal are outputted to a plurality of transmission antennas to be transmitted on a same frequency band and at a same time as broadcast signals,
the phase change uses a phase change value sequentially selected from among N phase change values, N being an integer greater than two and greater than the number of coded signals, and each of the N phase change values being selected at least once within a determined period, and
a difference between two adjacent phase change values of the N phase change values is 2?/N, the two adjacent phase change values being adjacent to one another in an arrangement order of data included in the second precoded signal.

US Pat. No. 10,367,548

ELECTRONIC DEVICE AND OPERATION METHOD THEREFOR

Samsung Electronics Co., ...

1. An electronic device comprising:a first antenna;
a second antenna;
a third antenna extended from the second antenna;
a first magnetic field module coupled to the first antenna and configured to perform first short range communication through the first antenna; and
a second magnetic field module coupled to the first antenna, the second antenna, and the third antenna, and configured to receive power wirelessly through the first antenna, by using a first charging scheme, to receive power through the second antenna by using a second charging scheme, and to perform second short range communication through the second antenna and the third antenna.

US Pat. No. 10,367,545

ADAPTIVE FILTER WITH MANAGEABLE RESOURCE SHARING

NXP B.V., Eindhoven (NL)...

1. An adaptive filter using resource sharing, said adaptive filter comprising:a tapped-delay-line providing L tapped delay signals, wherein L is a filter order of the adaptive filter, wherein L is a number;
a number of computational blocks each configured for adjusting one filter coefficient, in one cycle of an iterative procedure according to an adaptive convergence algorithm, wherein the number of computational blocks is less than the filter order L;
a cluster controller configured for allocating each of the computational blocks to one of a number of w clusters, wherein w is a positive integer; and
a symbol routing logic arranged for routing a set of tapped delay signals, to each cluster,
wherein the computational blocks of each cluster are provided for adjusting the filter coefficients, associated with the set of tapped delay signals, routed to the respective one of the clusters,
wherein the computational blocks of each cluster are timely shared among the filter coefficients, of one set of tapped delay signals;
and
a routing controller provided for configuring the routing of the tapped delay signals to the respective cluster in accordance with the allocation thereof.

US Pat. No. 10,367,544

APPARATUS AND METHOD FOR SEARCHING FOR CELL IN WIRELESS TERMINAL

Samsung Electronics Co., ...

1. A wireless terminal in a weak electric-field environment comprising:a plurality of antennas comprising a primary antenna and at least one secondary antenna; and
a communication processor (CP) configured to
select one of the plurality of antennas to measure a quality of signal with respect to at least one cell around the wireless terminal in a weak electric-field environment, based on whether at least one from among the at least one secondary antenna is in a driving state and whether a finger of a rake receiver has been allocated, and
perform a cell search through the selected one of the plurality of antennas,
wherein the driving state is a state in which a signal received through the at least one from among the at least one secondary antenna is delivered to the rake receiver.

US Pat. No. 10,367,533

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,532

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,531

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,529

LIST DECODE CIRCUITS

Hewlett Packard Enterpris...

1. A device, comprising:a first polynomial evaluation circuit to evaluate a first polynomial output from a Berlekamp-Massey algorithm for a plurality of values in a finite field in parallel, each of the plurality of values in the finite field corresponding to a possible error location in an error correction codeword;
a second polynomial evaluation circuit to evaluate a second polynomial output from the Berlekamp-Massey algorithm for the plurality of values in the finite field in parallel, the second polynomial evaluation circuit to evaluate the second polynomial output and the first polynomial evaluation circuit to evaluate the first polynomial output in parallel;
a field division circuit to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm by dividing outputs from the evaluation of the first polynomial output by outputs from the evaluation of the second polynomial output for each value in the finite field in parallel;
a discrepancy filter circuit to identify, as potentially valid discrepancy values, speculative discrepancy values that occur in the generated plurality of speculative discrepancy values a quantity of times equal to a quantity of correctable errors in the error correction codeword; and
an error locator polynomial (ELP) circuit to generate an ELP using the potentially valid discrepancy values and the first and second polynomial outputs.

US Pat. No. 10,367,525

INCREMENTAL LOOP MODIFICATION FOR LDPC ENCODING

National Instruments Corp...

6. A method, comprising:receiving first encoding data that corresponds to an encoding matrix;
separately performing, for different rows in the encoding matrix:
generating a set of operations for entries in the row, wherein the set of operations
includes respective operations to be performed on the entries for multiplication of the matrix by a vector;
propagating values of entries in the encoding matrix into the set of operations; and
simplifying ones of the set of operations based on the propagated values to generate an output set of operations; and
configuring circuitry to perform the output sets of operations to encode input data for wireless communication over a medium.

US Pat. No. 10,367,522

HIGH EFFICIENCY POWER AMPLIFIER ARCHITECTURES FOR RF APPLICATIONS

MY Tech, LLC, Irvine, CA...

1. A parallel delta sigma modulator comprising:a signal demultiplexer configured to receive an input signal and to demultiplex the input signal into a plurality of streams of symbols at symbol boundaries;
a plurality of delta sigma modulators, where each delta sigma modulator is configured to receive a stream of symbols from the plurality of streams of symbols and to generate a delta sigma modulated output; and
a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train; and
a frequency up-converter configured to receive the pulse train.

US Pat. No. 10,367,516

JITTER REDUCTION TECHNIQUES WHEN USING DIGITAL PLLS WITH ADCS AND DACS

Analog Devices Global, H...

1. A digital phase lock loop (DPLL) error correction circuit, the DPLL error correction circuit comprising:a primary analog-to-digital converter (ADC) circuit configured to sample an input signal and produce a digital output signal representative of the input signal;
a digital phase lock loop (DPLL) circuit configured to provide a sampling clock signal to the primary ADC circuit;
a timing error calculation circuit operatively coupled to the DPLL circuit and configured to determine a timing error representative of error in the sampling clock signal, wherein the timing error calculation circuit includes:
a slope calculation circuit configured to generate a digital slope signal representative of slope of the input signal; and
a sampling error circuit configured to determine a sampling error representative of sampling error by the primary ADC circuit using the digital slop signal and the sampling clock signal; and
an output circuit operatively coupled to the primary ADC circuit and the timing error calculation circuit and configured to adjust the digital output signal using the determined timing error.

US Pat. No. 10,367,515

DIGITAL-TO-ANALOG CONVERTER (DAC) WITH PARTIAL CONSTANT SWITCHING

Maxlinear, Inc., Carlsba...

1. A digital-to-analog converter (DAC) circuit, comprising:a first DAC element configured to receive a first data stream and generate a first DAC output, wherein the first data stream comprises one or more most significant bits (MSBs) from a digital input;
a second DAC element configured to receive a second data stream and generate a second DAC output, wherein the second data stream comprises one or more least significant bits (LSBs) from the digital input; and
a controller circuit operable to select either the first DAC element or the second DAC element to perform a digital to analog conversion, wherein the selection is based on a first clock and on a function of the digital input.

US Pat. No. 10,367,513

SUPPRESSION OF NOISE UP-CONVERSION MECHANISMS IN LC OSCILLATORS

International Business Ma...

1. A phase-locked loop (PLL) circuit comprising:an oscillator;
a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator; and
a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator,
wherein the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and wherein the bias voltage from the bias optimizer is set to the local minimum.

US Pat. No. 10,367,512

PRE-DELAY ON-DIE TERMINATION SHIFTING

Micron Technology, Inc., ...

1. An apparatus, comprising:a signal shift circuit configured to receive a clock signal in a first domain and an information signal in the first domain and provide a shifted information signal that is shifted a specified amount;
a delay locked loop (DLL) circuit configured to receive the clock signal in the first domain and provide a delayed clock signal in a DLL domain different from the first domain;
a cloned DLL circuit configured to receive the shifted information signal from the signal shift circuit and produce a shifted and delayed information signal in the DLL domain; and
a clock gate configured to receive the clock signal in the first domain and a control signal and, in response to one or more specified control signals, allowing the clock signal to pass to the DLL circuit,
wherein the one or more specified control signals that cause the clock gate to pass the clock signal to the DLL circuit consist of control signals that indicate a read or a write command.

US Pat. No. 10,367,511

COUNTER-BASED SYSREF IMPLEMENTATION

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:an input flip-flop including a clock input terminal and a data input terminal configured to be coupled to a first reference signal, wherein the input flip-flop is configured to use first clock to latch the reference signal to produce a latched reference signal;
a counter coupled to the input flip-flop and configured to count pulses of the first clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the first clock; and
a clock tree configured to divide down the first clock to generate a first output clock;
wherein the clock tree is configured to be synchronized to a pulse of the second reference signal;
wherein the clock tree includes:
a first level clock divider coupled to the first clock and configured to divide down the first clock to generate the first output clock;
a second level clock divider coupled to the first level clock divider and configured to divide down the first output clock to generate a second output clock;
wherein each of the first and second level clock dividers includes a reference signal input configured to receive the second reference signal pulses from the counter, wherein the second reference signal pulses synchronize the first and second level clock dividers.

US Pat. No. 10,367,507

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

INTERNATIONAL BUSINESS MA...

1. A plurality of dynamic decode circuits, each dynamic decode circuit connected between a first power source and a second power source, the each dynamic decode circuit comprising a respective decoder, a respective first node, a respective second node and a respective third node,wherein each decoder is configured to decode a respective plurality of input signals, wherein the each decoder is conductively connected to the respective first node and to the respective third node,
wherein the each dynamic decode circuit further comprises a respective evaluate clock circuit, wherein each evaluate clock circuit is conductively connected between the first power source and the respective second node, wherein the each evaluate clock circuit consists of a first transistor and a second transistor, wherein the first transistor is serially connected by a first interconnecting node to the second transistor, the first transistor comprising a first gate configured to receive an evaluation clock signal, the second transistor comprising a second gate conductively connected to the first node, the first transistor configured to conduct based on the evaluation clock signal being active and the first transistor configured to not conduct based on the evaluation clock signal being inactive,
wherein the each dynamic decode circuit further comprises one or more respective evaluate transistors, wherein the one or more evaluate transistors are connected to the first power source, wherein the one or more evaluate transistors are configured to evaluate a respective dynamic logic during an evaluate phase of the dynamic logic, wherein each of the one or more evaluate transistors are configured to conduct at the same time based on the same evaluation clock signal,
wherein the each dynamic decode circuit further comprises one or more respective precharge circuits, each precharge circuit connected to the second power source, the each precharge circuit configured to precharge a respective node in a precharge phase of the dynamic logic,
wherein each first node is connected to a respective precharge circuit,
wherein each the third node is connected to a respective evaluate transistor,
wherein the each dynamic decode circuit further comprises a respective conditioning circuit configured to condition a shared node of the dynamic decode circuit, the shared node shared by the each dynamic decode circuit of the plurality of dynamic decode circuits,
wherein each respective conditioning circuit of the plurality of dynamic decode circuits is connected in parallel between the shared node and a common power source, wherein the each respective conditioning circuit comprises a first conditioning transistor having a first conditioning gate configured to receive the evaluation clock signal and wherein the each conditioning circuit consists of any one of a precharge circuit and an evaluate transistor.

US Pat. No. 10,367,500

SWITCHING VOLTAGE REGULATOR WITH VARIABLE MINIMUM OFF-TIME

Allegro MicroSystems, LLC...

1. A voltage regulator comprising:a switch having a control terminal;
a bootstrap capacitor coupled to the switch;
a control circuit coupled to a control terminal of the switch and configured to open the switch to allow the bootstrap capacitor to charge and close the switch to allow the bootstrap capacitor to stop charging;
an oscillator circuit that produces a minimum off-time signal that defines a minimum time for the switch to be open and for the bootstrap capacitor to charge;
an under-voltage detection circuit that monitors a voltage across the bootstrap capacitor and, if the voltage across the bootstrap capacitor is less than a predetermined threshold, generates a signal that causes the switch to remain open; and
a minimum off-time circuit that adjusts the minimum off-time signal based on a reference voltage and the voltage across the bootstrap capacitor;
wherein:
the minimum off-time circuit comprises a ramp generator circuit that produces a ramp signal; and
the minimum off-time circuit combines the voltage across the bootstrap capacitor and the ramp signal to produce a modulated signal by summing the voltage across the bootstrap capacitor and the ramp signal.

US Pat. No. 10,367,499

POWER SUPPLY READY INDICATOR CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A power supply ready indicator circuit comprising:a first power-supply-ready-input coupled to a first power supply rail;
a second power-supply-ready-input coupled to a second power supply rail;
a power ready indicator output;
wherein the power supply ready indicator circuit is configured to:
divide a voltage on the first power supply rail,
compare the divided voltage with the second power supply rail voltage, and
generate a power ready signal on the power ready indicator output in response to the divided voltage being greater than the second power supply rail voltage,
wherein a final value of the first power supply rail voltage is greater than a final value of the second power supply rail voltage;
an integrated circuit including the power supply ready indicator circuit;
wherein the integrated circuit includes a voltage regulator having an input coupled to the first power supply rail and an output coupled to the second power supply rail; and
wherein the voltage regulator is configured to generate the second power supply rail voltage.

US Pat. No. 10,367,497

SYSTEM COMPRISING MULTI-DIE POWER AND METHOD FOR CONTROLLING OPERATION OF MULTI-DIE POWER MODULE

MITSUBISHI ELECTRIC CORPO...

1. A system comprising a multi-die power module composed of dies and a controller receiving plural consecutive input patterns for activating the dies of the multi-die power module, the input patterns being composed of rising edges and falling edges, characterized in that the dies are grouped into first, second and third groups of at least one die and in that the controller comprises:means for advancing the falling edge time of a gate signal for the first group of at least one die by a predetermined value,
means for delaying the rising edge time of a gate signal for the second group of at least one die by the predetermined value,
means for delaying the rising edge time of a gate signal for the third group of at least one die by the predetermined value and for advancing the falling edge time of the gate signal for the third group of at least one die by the predetermined value.

US Pat. No. 10,367,494

FAST-RESPONSE REFERENCES-LESS FREQUENCY DETECTOR

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to generate a waveform in response to (a) a frequency of an input clock signal and (b) a threshold frequency; and
a second circuit configured to generate a control signal in response to a type of said waveform, wherein (i) said type of said waveform comprises at least one of (a) pulses and (b) a steady state, (ii) said control signal has (a) a first state when said type of said waveform is said pulses and (b) a second state when said type of said waveform is said steady state and (iii) a width of said pulses is based on said threshold frequency.

US Pat. No. 10,367,493

DUTY CYCLE AND SKEW CORRECTION FOR OUTPUT SIGNALS GENERATED IN SOURCE SYNCHRONOUS SYSTEMS

SanDisk Technologies LLC,...

1. A circuit comprising:a delay circuit configured to output a delayed clock signal to a clock input of an output clock path circuit;
an input buffer configured to generate a buffered clock signal in response to receipt of an output clock signal from the output clock path circuit; and
a duty cycle correction controller configured to:
identify a duty cycle level of the buffered clock signal; and
adjust a delay amount of the delay circuit in response to the identified duty cycle level of the buffered clock signal.

US Pat. No. 10,367,490

ELECTRONIC CIRCUITS FOR OUTPUTTING POST EMPHASIS SIGNALS

Samsung Electronics Co., ...

1. An electronic device comprising:a driver configured to generate a second signal based on a first signal;
a delay circuit configured to delay the first signal by a reference time, to generate a third signal;
a strength control circuit configured to adjust an amplitude of the third signal to generate a fourth signal; and
an adder circuit configured to add the second signal and the fourth signal to generate a fifth signal,
wherein, in a first time interval determined based on the reference time, an amplitude of the fifth signal is greater than an amplitude of the second signal,
wherein, in a second time interval not overlapping with the first time interval, the amplitude of the fifth signal is smaller than the amplitude of the second signal, and
wherein, in the second time interval, the amplitude of the fifth signal is smaller than an amplitude of the first signal.

US Pat. No. 10,367,484

RAMP BASED CLOCK SYNCHRONIZATION FOR STACKABLE CIRCUITS

Texas Instruments Incorpo...

1. A phase generation circuit, comprising:a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal;
a phase selection circuit arranged to generate a reference signal in response to a phase selection signal separated from a peak voltage signal;
a comparator having a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal, the comparator producing a phase clock signal at an output terminal;
a phase error correction circuit arranged to produce an error signal to correct an error in time between the synchronization clock signal and the phase clock signal;
a sample and hold circuit arranged to sample the ramp signal; and
a buffer circuit coupled to receive the sampled ramp signal and the error signal, the buffer circuit having an output terminal coupled to the phase error correction circuit.

US Pat. No. 10,367,481

DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TEST CONTROL BOUNDARY USING AN INVERTED ARRAY CLOCK SIGNAL FEATURE

International Business Ma...

1. A digital logic circuit which is configured to deter a race violation at an array test control boundary, comprising:a clock generation circuitry, wherein the clock generation circuitry includes:
a first local clock buffer to generate:
a primary scan clock signal feature,
a secondary scan clock signal feature, and
a pulsed clock signal feature; and
a second local clock buffer to generate an array clock signal feature, the clock generation circuitry having both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting the array clock signal feature, and wherein the clock generation circuitry is configured to output an output clock signal feature when indicated by a first enable input, and
wherein the output clock signal feature is based on a scan enable input and wherein the output clock signal feature includes:
the primary scan clock signal feature,
the secondary scan clock signal feature, and
the pulsed clock signal feature;
a scannable storage element having both a scannable storage element output and a set of flip-flops, the set of flip-flops including:
a first primary flip-flop which corresponds to a functional data path of the digital logic circuit, wherein the first primary flip-flop connects with the derivative clock signal feature,
a second primary flip-flop which corresponds to a scan data path of the digital logic circuit, wherein the second primary flip-flop connects with the secondary scan clock signal feature and wherein the second primary flip-flop and a secondary flip-flop are part of the scan data path, and
the secondary flip-flop connected to both the pulsed clock signal feature and the scan clock signal feature, wherein the secondary flip-flop is configured to input an output of:
the first primary flip-flop when indicated by the pulsed clock signal feature, and
the second primary flip-flop when indicated by the secondary scan clock signal feature, and wherein the second primary flip-flop is used in a nonperformance critical scan operation; and
a memory array connected with:
the scannable storage element output, and
the array clock signal feature, wherein the memory array includes an array of static random-access memory (SRAM) cells, and wherein the digital logic circuit is configured to avoid the race violation between a set of output data of the first primary flip-flop and the pulsed clock signal feature at the secondary flip-flop independent of the what the derivative clock signal feature indicates, wherein all clock signal features are derived from a common global clock signal.

US Pat. No. 10,367,479

METHOD AND APPARATUS TO REDUCE NOISE IN CT DATA ACQUISITION SYSTEMS

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:an integrator configured to generate an integrated signal in response to a current signal;
a comparator coupled to the integrator and configured to receive the integrated signal and a primary reference voltage signal, the comparator configured to generate a feedback signal; and
a switched capacitor network coupled across the integrator, wherein the feedback signal is configured to activate the switched capacitor network;
a feedback capacitor coupled across the integrator;
an analog-to-digital converter (ADC) coupled across the feedback capacitor; and
a first transconductor configured to receive a secondary reference voltage signal, and an output terminal of the first transconductor coupled to a first output terminal of the integrator.

US Pat. No. 10,367,477

SPARSE CASCADED-INTEGRATOR-COMB FILTERS

Analog Devices, Inc., No...

1. An efficient low-power cascaded-integrator-comb (CIC) filter comprising:a series of integrating stages comprising a last integrating stage in the series of integrating stages operating on signal values from previous integrating stages, wherein the last integrating stage comprises:
an integrator having an adder and a delay unit whose output is fed back to the adder; and
a multiplier, upstream of the adder, to implement time-varying input gain, sequentially receive time-varying coefficients, and multiply each of the time-varying coefficients with corresponding one of the signal values received from previous integrating stages, wherein the time-varying coefficients includes at least one zero;
a decimation stage to decimate an output of the integrator; and
a differentiator downstream from the decimation stage.

US Pat. No. 10,367,475

ACOUSTIC WAVE FILTER INCLUDING SURFACE ACOUSTIC WAVE RESONATORS AND BULK ACOUSTIC WAVE RESONATOR

Skyworks Solutions, Inc.,...

1. A multiplexer comprising four acoustic wave filters coupled to a common node, the four acoustic wave filters including a first acoustic wave filter that includes surface acoustic wave resonators and a series bulk acoustic wave resonator coupled between the surface acoustic wave resonators and the common node, and the four acoustic wave filters including a second acoustic wave filter that includes second surface acoustic wave resonators and a second series bulk acoustic wave resonator coupled between the second surface acoustic wave resonators and the common node.

US Pat. No. 10,367,469

CORNER COUPLING RESONATOR ARRAY

MURATA MANUFACTURING CO.,...

1. A microelectromechanical system (“MEMS”) resonator array comprising:at least a pair of first piezoelectric resonators opposed to each other with a space defined therebetween; and
at least a pair of second piezoelectric resonators that are opposed to each other and that are each coupled to respective corners of each of the first piezoelectric resonators, such that each of the second piezoelectric resonators is partially disposed in the space defined between the pair of first piezoelectric resonators,
wherein each piezoelectric resonator of the respective pairs of first and second piezoelectric resonators comprise a pair of anchoring points on respective opposing sides of each piezoelectric resonator, such that each piezoelectric resonator is configured to vibrate in-plane in a width expansion mode.

US Pat. No. 10,367,465

OPTIMIZED VOLUME ADJUSTMENT

Apple Inc., Cupertino, C...

1. A method of providing audio volume adjustment in a media-editing application, the method comprising:displaying an audio clip;
determining intrinsic segment volume levels individually for segments of the audio clip;
displaying a volume adjuster graph having different volume adjuster segments within the volume adjuster graph at same levels as the determined intrinsic segment volume levels for the segments of the audio clip, the volume adjuster graph being for adjusting volume levels of the segments of the audio clip;
receiving an adjusted level for at least one of the volume adjuster segments of the volume adjuster graph; and
setting a volume level of at least one of the segments of the audio clip by setting the intrinsic segment volume level to the received adjusted level for the at least one of the volume adjuster segments of the volume adjuster graph.

US Pat. No. 10,367,461

COMBINED OUTPUT MATCHING NETWORK AND FILTER FOR POWER AMPLIFIER WITH CONCURRENT FUNCTIONALITY

Skyworks Solutions, Inc.,...

1. A radio frequency power amplifier module for use in a multi-band wireless mobile device comprising:a first semiconductor die including an amplifier circuit configured to amplify a radio frequency input signal received on an input terminal of the power amplifier module for transmission by a first antenna associated with a first transmit path of the mobile device;
an input tuning circuit including at least a first capacitor in communication with the first semiconductor die;
an output tuning circuit including at least a first inductor in communication with an output terminal of the power amplifier module; and
a first circuit connected in series between the input tuning circuit and the output tuning circuit and including at least a second inductor and a second capacitor connected in parallel and configured to transform an output impedance of the amplifier circuit to an input impedance of the first antenna and further configured to block signals radiating from a second antenna associated with a second transmit path of the mobile device and received at the output terminal from traveling backwards along the first transmit path to the amplifier circuit.

US Pat. No. 10,367,460

AMPLIFIER CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An amplifier circuit comprising:a delta-PWM-modulator configured to:
receive a digital-input-signal;
process the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal, wherein the delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulationof the digital-input-signal;
a three-level-DAC configured to receive the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provide a three-level-analogue-signal;
a loop-integrator comprising:
a virtual-ground-node-terminal configured to receive: (i) the three-level-analogue-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop;
an integrator-output-terminal configured to provide a loop-integrator-output-signal, which is proportional to an integral of the signals received at the virtual-ground-node-terminal; and
a comparator comprising:
a comparator-input-terminal configured to receive the loop-integrator-output-signal;
a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and
a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

US Pat. No. 10,367,459

CLASS-D AMPLIFIER CIRCUIT

ROHM CO., LTD., Kyoto (J...

1. A Class-D amplifier circuit comprising:a bridge output stage coupled to an electroacoustic conversion element via an inductor;
a driving circuit structured to drive the output stage according to a pulse signal that corresponds to an audio signal; and
an overcurrent detection circuit structured to assert an overcurrent detection signal (i) when a current that flows through a transistor to be monitored that forms the output stage exceeds a first threshold value for a predetermined first period of time, or (ii) when a current that flows through the transistor to be monitored exceeds a second threshold value that is higher than the first threshold value after a predetermined second period of time elapses after the transistor to be monitored turns on, wherein the overcurrent detection circuit comprises:
a first comparator structured to compare a current detection signal that corresponds to a current that flows through the transistor to be monitored with a first threshold voltage that corresponds to the first threshold value, and to generate a first comparison signal indicating a comparison result;
a second comparator structured to compare the current detection signal with a second threshold voltage that corresponds to the second threshold value, and to generate a second comparison signal indicating a comparison result; and
a judgment circuit structured to generate the overcurrent detection signal based on the first comparison signal and the second comparison signal.

US Pat. No. 10,367,456

AMPLIFIER ASSEMBLY AND SPATIAL POWER COMBINING DEVICE

Qorvo US, Inc., Greensbo...

1. An amplifier assembly for a spatial power combining device that comprises a plurality of amplifier assemblies, the amplifier assembly comprising:a body that forms a first antenna, wherein the first antenna is a first Vivaldi antenna comprising a first circular backstub and a first tapered slot portion;
a second antenna; and
a printed circuit board (PCB) assembly fixed to the body, comprising:
a PCB;
an amplifier mounted on the PCB;
a first transmission line coupled to the first antenna and to the amplifier; and
a second transmission line coupled to the second antenna and to the amplifier.

US Pat. No. 10,367,455

HIGH-FREQUENCY FRONT END CIRCUIT

MURATA MANUFACTURING CO.,...

1. A high-frequency front end circuit comprising:an antenna terminal;
a reception circuit that is connected to the antenna terminal; and
a transmission circuit that is connected to the antenna terminal and that comprises a first amplification circuit, wherein the first amplification circuit comprises:
an input terminal and an output terminal;
an amplification element connected in a signal path between the input terminal and the output terminal; and
a bias circuit having an LC resonance circuit, a first end of the bias circuit being connected to the signal path,
wherein a frequency pass band of the transmission circuit is lower than a frequency pass band of the reception circuit, and
wherein a resonant frequency of the bias circuit is less than a frequency pass band width of the transmission circuit.

US Pat. No. 10,367,450

OSCILLATOR SCHEME CAPABLE OF REDUCING FAR-OUT PHASE NOISE AND CLOSED-IN PHASE NOISE

MediaTek Inc., Hsin-Chu ...

1. An oscillator apparatus, comprising:an oscillator core circuit, comprising:
an inverting transconductance amplifier;
at least one first capacitor, connected between an input of the inverting transconductance amplifier and a ground level;
at least one second capacitor, connected between an output of the inverting transconductance amplifier and the ground level; and
a resonator, having a first port connected to the input of the inverting transconductance amplifier and a second port connected to the output of the inverting transconductance amplifier, the first port of the resonator being decoupled from the second port of the resonator;
a DC coupling circuit, having one end connected to the input of the inverting transconductance amplifier and the first port and having another end connected to a driver; and
the driver, having an input DC coupled to the first port via the DC coupling circuit.

US Pat. No. 10,367,449

MICRO-CONCENTRATOR MODULE AND DEPLOYMENT METHOD

The Boeing Company, Chic...

1. A micro-concentrator module, that comprises:a cover glass;
a printed wiring board that comprises:
on a side, which faces the cover glass, of the printed wiring board, an array of micro-electromechanical systems (MEMS) based reflectors;
on a side, which faces away from the cover glass, of the printed wiring board, an electrical power trace that powers the printed wiring board;
a panel that comprises, on a side, which faces the printed wiring board, first welds that connect the panel to the printed wiring board and support a space between the printed wiring board and the panel;
an application specific integrated circuit configured to control the micro-concentrator module and mounted, within the space, to the side, which faces away from the cover glass, of the printed wiring board;
a plurality of solar cells located on one side of the cover glass and configured to stow adjacent to and deploy to hover at a distance over the array of MEMS based reflectors; and
an electrical connection coupled to:
via second welds, the side, which faces the cover glass, of the printed wiring board;
via third welds, to a bus bar connected to an electrical circuit trace connected to a sub-array of the plurality of solar cells, such that the bus bar forms a continuous trace along a width and a length of a perimeter of the cover glass, the electrical connection configured:
to compress;
comprising a bias to expand until restrained by a tether connected to the printed wiring board and to the cover glass; and
support a separation between the cover glass and the printed wiring board that sustains the distance between the plurality of solar cells and the array of MEMS based reflectors; and
a damping pad mounted as a discontinuous strip aligned along a perimeter of the side, which faces the cover glass, of the printed wiring board, such that with the electrical connection fully compressed the cover glass contacts the damping pad and maintains the cover glass in a spaced relationship above the array of MEMS based reflectors.

US Pat. No. 10,367,448

SOLAR PANEL AWNING AND RELATED SYSTEMS AND METHODS

1. A solar panel awning device comprising:a solar panel having first and second opposing ends, first and second opposing sides extending between said first and second opposing ends, and first and second opposing major surfaces, said first major opposing surface defining a photovoltaic surface;
first and second arms respectively coupled to said first and second opposing ends of said solar panel;
at least one actuator coupled to one of said first and second arms and configured to switch the solar panel between an extended position and a retracted position; and
first and second pivot arms respectively coupled to said first and second opposing ends of said solar panel adjacent the first opposing side of said solar panel, the first and second pivot arms being separate from and spaced apart from said first and second arms;
said first and second arms, and said first and second pivot arms configured to, in the retracted position, fold said solar panel flat against a side of a building;
said first and second arms, and said first and second pivot arms configured to, in the extended position, extend both the first opposing side and the second opposing side of said solar panel so that
said first opposing side is proximal to the side of the building and spaced apart from the side of the building,
said second opposing side is distal to the side of the building, and
said first opposing side extends laterally past an eave of the building;
wherein said first and second arms and said first and second pivot arms each have a first end and an opposing second end, the first end of each of said first and second arms and said first and second pivot arms being attached to the side of the building;
wherein each of said first and second arms is configured to rotate at the first end and the second end to switch from the retracted position to the extended position; and
wherein each of said first and second pivot arms is configured to rotate at the first end to switch from the retracted position to the extended position.

US Pat. No. 10,367,446

MOUNT FOR SOLAR PANEL

FUJI SEIKO CO., LTD., Ha...

1. A mount for a solar panel comprising:a tilted support frame having a pair of horizontal members extending along a horizontal direction in parallel to each other with different heights and a pair of tilted members arranged between the horizontal members and extending in parallel to each other so as to be-tilted in one side;
a fixed support member fixing and supporting the tilted support frame on an installation surface;
a square-shaped panel support member provided above the tilted support frame, on which a solar panel is arranged and fixed;
a support shaft provided so as to extend along a direction parallel to the horizontal members between the tilted support frame and the panel support member and supporting the panel support member so as to rotate at a central portion portions of two facing sides of the panel support member; and
a pair of stopper members respectively provided on each rotating end side of the panel support member so that one end portion of each of the pair of stopper members rotates freely and wherein the pair of stopper members include engaging concave portions having open lower sides engaging with half circumferences of outer peripheries of the horizontal members from above in a rotating direction so as to be removed at positions corresponding to a predetermined tilt angle position of the panel support member.

US Pat. No. 10,367,445

CARRIER STRUCTURE FOR SOLAR PANELS AND METHOD OF PRODUCING SUCH A CARRIER STRUCTURE

Esdec B.V., Deventer (NL...

14. A carrier structure for solar panels, comprising:at least one carrying frame configured to carry at least a part of at least one solar panel, and
at least one accessory which is coupleable to the carrying frame,
wherein at least one of the at least one carrying frame and the at least one accessory comprises at least one coupling pin configured to be at least partly received in a complementary receiving space provided in at least one of the at least one accessory or the at least one carrying frame, wherein the coupling pin and/or the receiving space is provided with at least one locking element for locking the accessory and the carrying frame to each other when the coupling pin is being fitted in the receiving space, and wherein the receiving space is provided with at least one locking element being configured to cut into an outer periphery of the coupling pin, and
wherein the accessory is provided with several receiving spaces, wherein each receiving space is provided with at least one locking element, and wherein the carrying frame comprises several coupling pins configured to be at least partly received in the respective receiving spaces for mutually locking the accessory with respect to the carrying frame.

US Pat. No. 10,367,437

SYSTEMS, METHODS AND DEVICES FOR APPROXIMATE DYNAMIC PROGRAMMING VECTOR CONTROLLERS FOR OPERATION OF IPM MOTORS IN LINEAR AND OVER MODULATION REGIONS

The Board of Trustees of ...

1. A method for controlling an interior-mounted permanent magnet (IPM) alternating-current (AC) electrical machine by:providing a pulse-width modulated (PWM) converter operably connected between an electrical power source and the IPM AC electrical machine;
providing a neural network vector control system operably connected to the PWM converter, the neural network vector control system comprising a current-loop neural network configured to implement an approximate dynamic programming (ADP) algorithm, wherein the current-loop neural network is trained to minimize a cost function of the ADP algorithm using a forward accumulation through time (“FATT”) algorithm;
receiving a plurality of inputs at the current-loop neural network;
outputting a first compensating dq-control voltage from the current-loop neural network, wherein the current-loop neural network is configured to optimize the first compensating dq-control voltage based on the plurality of inputs;
providing a feedforward controller operably connected to the PWM converter;
receiving reference current inputs at the feedforward controller, wherein the inputs at the feedforward controller comprise a reference d-axis current, isd*, and a reference q-axis current, isq*;
outputting a second compensating dq-control voltage from the feedforward controller, wherein the feedforward controller is configured to regulate the second compensating dq-control voltage based on the reference current inputs; and
controlling the PWM converter using the first compensating dq-control voltage and the second compensating dq-control voltage,
wherein the feedforward controller is designed based on default parameters of the IPM AC electrical machine.

US Pat. No. 10,367,435

DUAL-VOLTAGE BRUSHLESS MOTOR

TECHTRONIC INDUSTRIES COM...

1. A dual-voltage brushless motor, comprising:a) a casing;
b) a motor shaft rotatably coupled to said casing;
c) a rotor fixedly connected to said motor shaft; said rotor comprising a plurality of permanent magnets; and
d) a stator configured to face said rotor; wherein said stator comprising a first set of windings and a second set of windings;
wherein the first set of windings is in electrical communication with an AC power supply, wherein the second set of windings is in electrical communication with a DC power supply, wherein said first set of windings is electrically isolated from said second set of windings; and
wherein said dual-voltage brushless motor is driven when said first set of windings receives a first control signal or when said second set of windings receives a second control signal.

US Pat. No. 10,367,429

ACTUATOR ELEMENT USING CARBON ELECTRODE

NATIONAL INSTITUTE OF ADV...

1. A conductive thin film comprising a homogeneous mixture comprising 5-90% by weight of a nano-carbon material, 5-80% by weight of an ionic liquid, 4-70% by weight of a polymer, and an organic molecule component,wherein the homogeneous mixture forms a gel,
wherein the organic molecule component comprises at least one electron-withdrawing organic molecule that is tetracyanoquinodimethane (TCNQ), and
wherein the organic molecule component is present in an amount of 3 to 80 parts by weight per 100 parts by weight of a total amount of the nano-carbon material, the ionic liquid, and the polymer.

US Pat. No. 10,367,427

RESONANT INVERTER DEVICE

DENSO CORPORATION, Kariy...

1. A resonant inverter device comprising:a main circuit configured to convert input power supplied from a direct-current (DC) power source into alternating-current (AC) power and supply the AC power to a resonance load as output power;
an input power measurer configured to measure the input power;
a controller configured to control operations of the main circuit, the controller comprising:
an input to which a target output value that is a target value of the output power is externally input;
a deriver configured to derive a power loss or circuit efficiency of the main circuit as a conversion loss parameter of the main circuit;
an input power calculator configured to calculate an increased target output value by increasing the target output value using the conversion loss parameter, as a target value of the input power; and
an operation controller configured to control operations of the main circuit such that the calculated target value of the input power is input to the main circuit.

US Pat. No. 10,367,419

POWER CONVERSION DEVICE WITH INTEGRATED DISCRETE INDUCTOR

Kinetic Technologies, Sa...

1. A switching regulator, comprising:an inductor housed in an inductor housing;
a first wire electrically coupled to the inductor and housed in the inductor housing;
a first electrical component including a first terminal; and
a board including a first board trace, the first board trace electrically coupling the first terminal with the first wire;
wherein:
the first electrical component and the inductor housing are attached to the board;
the attachment of the inductor housing to the board creates a space between the inductor housing and the board; and
the first electrical component is disposed within the space.

US Pat. No. 10,367,413

RESONANT SYSTEM CONTROLLER AND CYCLE-BY-CYCLE PREDICTIVE SOFT SWITCHING

Pre-Switch, Inc., Raleig...

1. A method of reducing switching losses during successive switch-mode power supply (SMPS) cycles of an SMPS comprising first and second electrically coupled switches that change switching states in response to, respectively, first and second signals, the successive SMPS cycles including first and second SMPS cycles in which the second SMPS cycle follows the first SMPS cycle, the method comprising:generating during the first SMPS cycle the first signal at a first time to change a first switching state of the first switch;
generating during the first SMPS cycle the second signal at a second time to change a second switching state of the second switch, the second time temporally displaced from the first time based on a timing parameter, the timing parameter being adjustable to coordinate the second switch changing its switching state when a soft-switching condition exists, the soft-switching condition characterized by a condition at which minimum hard-switching and diode conduction losses would result from the second switch changing its switching state;
detecting a failure to adequately soft switch the second switch during the first SMPS cycle and whether the failure is attributable to a first or second timing error between when the second switch changes its switching state and when the soft-switching condition actually occurs for the first SMPS cycle, the first and second timing errors occurring when the second switch changes its switching state, respectively, before and after when the soft-switching condition actually occurs for the first SMPS cycle;
in response to detecting the first timing error, adjusting, for the second SMPS cycle, the timing parameter to reduce hard-switching loss by causing the second time at which the second signal is generated to be delayed during the second SMPS cycle; and
in response to detecting the second timing error, adjusting, for the second SMPS cycle, the timing parameter to reduce diode conduction loss by causing the second time at which the second signal is generated to be advanced during the second SMPS cycle.

US Pat. No. 10,367,402

VIBRATION MOTOR

NIDEC SEIMITSU CORPORATIO...

1. A vibration motor comprising:a cover;
a board including an electrical circuit;
a stationary portion including a casing and a coil;
a vibrator including a magnet, and supported to vibrate in one direction with respect to the stationary portion; and
at least one elastic member between the stationary portion and the vibrator; wherein
the magnet is above an upper side of the coil in a vertical direction perpendicular to the one direction;
the stationary portion includes at least one projecting portion that projects in the vertical direction;
a portion of the at least one projecting portion is opposite to a portion of the vibrator in the one direction;
a portion of the board is directly adjacent to and partially surrounds a portion of the at least one projecting portion;
the at least one elastic member includes a plate spring portion that supports at least one of both ends of the vibrator with respect to the one direction; and
the plate spring portion includes a decreased width portion and an increased width portion having a vertical width greater than a vertical width of the decreased width portion, the decreased width portion being above or below a corresponding one of the at least one projecting portion when viewed from one side in the one direction.

US Pat. No. 10,367,401

ELECTRIC MOTOR WITH COMMUTATOR SEGMENTS, ANODE AND CATHODE BRUSHES AND COILS HAVING VARYING NUMBER OF TURNS BASED ON ANODE BRUSH POSITION ANGLE

Mitsuba Corporation, Gun...

1. An electric motor comprising:a motor magnet in which a plurality of magnetic poles are arranged in a circumferential direction;
a rotating shaft that is rotatably provided inside the motor magnet;
an armature core that is mounted on the rotating shaft and includes a plurality of teeth radially extending outward in a radial direction and a plurality of slots formed between the teeth;
coils that are wound on each of the teeth in a concentrated winding manner;
a commutator which is provided so as to rotate integrally with the rotating shaft and on which a plurality of segments are disposed in the circumferential direction; and
an anode brush and a cathode brush that supply power to the coils through the segments,
wherein three coils are wound on each of the teeth,
a number of turns of one coil among the three coils is set to be smaller than a number of turns of each of the other two coils,
the three coils are an advance-angle coil of which a magnetomotive force vector is directed to an advance-angle side, a delay-angle coil of which a magnetomotive force vector is directed to a delay-angle side, and a normal coil of which a magnetomotive force vector is not directed to either the advance-angle side or the delay-angle side, and
when the number of turns of the advance-angle coil is denoted by T1, the number of turns of the normal coil is denoted by T2, and the number of turns of the delay-angle coil is denoted by T3,
in a case in which,
an advance angle ?1 of the magnetomotive force vector of the advance-angle coil satisfies 0° a delay angle ?2 of the magnetomotive force vector of the delay-angle coil satisfies 0° an advance angle ?3 of a position of the anode brush satisfies 0°??3?3°,
T1, T2, and T3 are set so as to satisfy T2>T1>T3.

US Pat. No. 10,367,400

LINE START PERMANENT MAGNET MOTOR USING A HYBRID ROTOR

Coreteq Systems Ltd., Su...

1. A rotor system for a downhole motor comprising:a set of permanent magnets;
a set of conductors comprising discrete conductive bars; and
a pair of end conductor rings connecting the set of conductors;
the set of permanent magnets and the set of conductors being substantially coaxial and having the substantially the same linear extent;
the set of permanent magnets and the set of conductors both being set in a rotor body, the rotor body having an outermost outer surface, the outermost outer surface featuring notches in which the conductors are set; and
a conductive material substantially formed around a cylinder, the thickness of the conductive material varying around the radius of the cylinder in an alternating manner, so as to provide relatively thick portions that are generally axially aligned.

US Pat. No. 10,367,384

TORQUE-OPTIMIZED ROTOR AND SMALL ELECTRIC MOTOR WITH A ROTOR OF THIS TYPE

LAKEVIEW INNOVATION LTD.,...

1. Rotor for an electric motor, comprising:a rotor axis, multiple permanent magnets that are arranged in a spoke-shaped way, and as well as multiple inference cores,
wherein each permanent magnet has two axial ends, two longitudinal sides, one radial outer side and a radial inner side,
wherein respectively one interstitial inference core formed as a wedge is disposed between two adjacent permanent magnets, wherein the wedge has a radially extending plane of symmetry, two flanks, two axial ends and a radial outer side, wherein the two flanks confine a wedge angle A towards one another,
wherein the inference cores protrude radially over the permanent magnets in relation to the rotor axis,
wherein the rotor is enclosed at least partially by a casting mold, wherein the casting mold has multiple struts that extend in an axial direction and that overlap radially with the permanent magnets,
wherein a form closure that acts in a radial direction exists between the struts and the inference cores,
and wherein the inference cores are individual inference cores that are not connected,
wherein the inference cores do not overlap with the permanent magnets on their radial outer sides, and wherein both the permanent magnets as well as the inference cores are held together primarily directly by the casting mold in a radial direction.

US Pat. No. 10,367,383

STRUCTURE FOR FIXING PERMANENT MAGNET AND MOTOR AND METHOD OF FIXING PERMANENT MAGNET

MABUCHI MOTOR CO., LTD., ...

1. A fixing structure for a permanent magnet, comprising:a cylindrical housing;
a permanent magnet housed inside the housing; and
an adhesive layer formed in a gap between the housing and the permanent magnet and having an adhesive for fixing the permanent magnet to the housing, wherein
the adhesive layer is formed such that a filling rate of the adhesive is higher in the gap at another axial end of the permanent magnet than at one axial end of the permanent magnet, and
the permanent magnet is configured such that a density at said other axial end of the permanent magnet is higher than the density at said one axial end of the permanent magnet.

US Pat. No. 10,367,368

WIRELESS POWER TRANSFER METHOD AND WIRELESS POWER TRANSMITTER

LG ELECTRONIC INC., Seou...

1. A wireless power transmitter for performing communication with a wireless power receiver, the wireless power transmitter comprising:a power conversion unit configured to transmit a wireless power signal transferred in a form of an energy field; and
a power transmission control unit configured to transfer power to the wireless power receiver using the wireless power signal,
wherein the power transmission control unit is configured to control the power conversion unit to transmit a near-field communication (NFC) detection signal, other than the wireless power signal, when a preset condition is satisfied,
wherein the power transmission control unit controls the power conversion unit in a different manner according to whether or not a response signal to the NFC detection signal is detected,
wherein the wireless power transmitter further comprises a frequency divider configured to generate the wireless power signal using the NFC detection signal based on the control of the power transmission control unit,
wherein the power conversion unit comprises a coil, and
wherein one of the wireless power signal and the NFC detection signal is selectively transmitted through the coil.

US Pat. No. 10,367,347

ARC FAULT CIRCUIT INTERRUPTER

Leviton Manufacturing Com...

1. A circuit interrupter, comprising:a first conductive path and a second conductive path;
a first arc fault detection circuit including a low frequency sensor, wherein the first conductive path passes through the low frequency sensor, the low frequency sensor including a first coil;
a second arc fault detection circuit including a high frequency sensor wherein the first and second conductive paths pass through the high frequency sensor and the high frequency sensor is configured to sense a difference in magnitude of currents respectively flowing in the first and second conductive paths, the high frequency sensor including a second coil and a third coil; and
a test block configured to perform a test of the high frequency sensor, the test block including:
a current supply configured to provide flow of a test current through the third coil;
a measuring circuit configured to measure a current flowing through the second coil;
logic configured to determine, based on the current flowing through the second coil, that the test current was detected by the second coil; and
an indicator configured to indicate a result of the test.

US Pat. No. 10,367,345

TEMPERATURE DETECTION DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A temperature detection device comprising:a first temperature sensor that is disposed adjacent to a first member in a DC circuit;
a second temperature sensor that is disposed adjacent to a second member in the DC circuit, the second member having a higher potential than the first member;
a sensor input circuit that connects a first terminal of the first temperature sensor and a second terminal of the second temperature sensor to a power supply voltage line and that connects a third terminal of the first temperature sensor and a fourth terminal of the second temperature sensor to a reference voltage line; and
a protection circuit that is provided between the first and second temperature sensors and the sensor input circuit, the protection circuit including:
a first sensor connecting path having a first overcurrent protection element and connecting the first terminal to the power supply voltage line;
a second sensor connecting path having a second overcurrent protection element and connecting the second terminal to the power supply voltage line;
a third sensor connecting path having a third overcurrent protection element and connecting the third terminal to the reference voltage line of;
a fourth sensor connecting path having a fourth overcurrent protection element and connecting the fourth terminal to the reference voltage line;
a rectifying element connecting the first sensor connecting path to the reference voltage line in a section between the first overcurrent protection element and the sensor input circuit, the first sensor connecting path having a normal voltage higher than the reference voltage line, the rectifying element inhibiting flow of current from the first sensor connecting path to the reference voltage line and allowing flow of current from the reference voltage line to the first sensor connecting path; and
an overvoltage protection element connecting the second sensor connecting path to the reference voltage line in a section between the second overcurrent protection element and the sensor input circuit, the second sensor connecting path having a normal voltage higher than the reference voltage line, the overvoltage protection element electrically connecting the second sensor connecting path to the reference voltage line when a voltage of the second sensor connecting path relative to the reference voltage line exceeds a predetermined voltage value, the predetermined voltage value being higher than a maximum value of the normal voltage of the second sensor connecting path and lower than a potential difference between the first member and the second member,
wherein the first overcurrent protection element, the second overcurrent protection element, the third overcurrent protection element, and the fourth overcurrent protection element each lose conductivity when a current exceeding a predetermined current value flows therethrough.

US Pat. No. 10,367,331

POINTING DEVICES, APPARATUS, SYSTEMS AND METHODS FOR HIGH SHOCK ENVIRONMENTS

1. A pointing support device for high shock environments, comprising:a housing having a base, a front stationary wall and a rear stationary wall, the front stationary wall with an opening;
a one piece shaped beam consisting of a cylindrical shaped first end rigidly mounted and fixed directly to the rear stationary wall, and a cylindrical shaped second end aligned with and adjacent to the opening in the front stationary wall, and a section intermediate the first end and the second end that has an elliptical shaped profile;
a pointing payload rigidly and fixed attached to the second end of the one piece shaped beam, wherein the one piece shaped beam provides accurate linear and angular positioning of the payload and maintains initial precise pointing of the payload relative to the surface the pointing device is attached to during and after exposure of the housing to shock and vibration; and
an externally accessible vertical and lateral adjustment mechanism consisting of only one single vertical adjustment component and only one single lateral adjustment component, the adjustment mechanism directly coupled to the pointing payload for adjusting vertical and lateral position of the payload be deflecting the one piece shaped beam along vertical and lateral orientations.

US Pat. No. 10,367,318

MODULAR FIXTURE FOR SUPPLYING POWER, CONTROL SIGNALS, AND/OR DATA COMMUNICATION TO VARIOUS DEVICES

1. A modular fixture, comprising:a housing;
a plurality of fixture connectors coupled to the housing;
a plurality of conductors coupled to each of the plurality of fixture connectors;
a first device including a first device connector operative to mate with each of the plurality of fixture connectors for coupling of the plurality of conductors to the first device; and
a second device including a second device connector operative to mate with each of the plurality of fixture connectors for coupling of the plurality of conductors to the second device;
wherein the first device and the second device are each of a device type selected from the group consisting of: a lighting device, a camera, a wireless communication device, a speaker device, a microphone device, a combination speaker-microphone device, a solar energy device, a wind energy device, a motion sensor, a speed monitoring device, and an unmanned aerial vehicle charging device; and
wherein the first device type is different than the second device type.

US Pat. No. 10,367,317

PORTABLE ELECTRIC POWER HUB WITH AC POWER RECEPTACLES AND USB CHARGING PORTS

Premier Manufacturing Gro...

1. A portable electric power hub for placement on a work surface, comprising:a housing including:
a base section having a perimeter that is defined by a plurality of straight edges joined by a first plurality of rounded corners,
an intermediate section including a plurality of vertically oriented sides that are joined together by a second plurality of rounded corners, wherein each side of the intermediate section is adjacent to and aligned with a corresponding one of the plurality of straight edges of the base section and wherein each of the second plurality of rounded corners is adjacent to and aligned with a corresponding one of the first plurality of rounded corners, wherein the vertically oriented sides are perpendicular to a work surface when the portable electric power hub is placed on such work surface and wherein each vertically oriented side has a surface area that is sufficiently sized for attaching thereto an electric power receptacle;
an upper section including a plurality of angulated sides joined by a third plurality of rounded corners, wherein each angulated side is adjacent to and angulated inward with respect to a corresponding one of the plurality of sides of the intermediate section and wherein each of the third plurality of rounded corners is adjacent and aligned with a corresponding one of the second plurality of rounded corners;
a plurality of AC electric power receptacles, wherein one AC electric power receptacle is positioned on every other angulated side of the upper section;
a plurality of USB female sockets, wherein one USB female socket is positioned on every other vertically oriented side;
a plurality of electrical circuits, wherein each circuit is electrically connected to a corresponding USB female socket and configured to convert AC electric power to DC electric power and provide the DC electric power to the USB female socket;
an electrical power cable for providing electrical power to the AC electric power receptacles and electrical circuits and being adapted to be connected to a source of electrical power; and
means for removably attaching the portable electrical power hub to the work surface.

US Pat. No. 10,367,315

CHAIR MOLDING WITH INTEGRATED ELECTRICAL OUTLETS

1. A power distribution structure comprising:a molding, a plurality of electrical ports, and a national electric grid cable (hereinafter NEG cable);
wherein the molding is configured to attach to a vertical surface;
wherein the molding contains the plurality of electrical ports;
wherein the power distribution structure is configured for use with the vertical surface;
wherein the power distribution structure mounts on the vertical surface;
wherein the power distribution structure is configured for use with an external power structure;
wherein the NEG cable attaches the plurality of electrical ports to the external power structure;
wherein the molding is a sacrificial structure;
wherein the molding is a hollow structure;
wherein the molding comprises a shell and a faceplate;
wherein the faceplate attaches to the shell;
wherein the shell is further defined with an exterior surface, an inferior surface, an interior surface, and a superior surface;
wherein the interior surface is opposite the exterior surface;
wherein the interior surface is adjacent the inferior surface;
wherein the exterior surface is adjacent the superior surface;
wherein the interior surface is configured to attach to the vertical surface;
wherein the shell is a semi-rigid structure;
wherein the inferior surface of the shell is an open surface;
wherein the faceplate is a protective structure;
wherein the faceplate installs in the inferior surface of the shell.

US Pat. No. 10,367,294

ELECTRICAL DEVICE HAVING A GROUND TERMINATION COMPONENT WITH STRAIN RELIEF

TE CONNECTIVITY CORPORATI...

1. An electrical device, comprising:a substrate having a plurality of signal contacts and a ground contact along a surface of the substrate;
a communication cable including a differential pair of signal conductors, a grounding element that surrounds the signal conductors, and a cable jacket surrounding the signal conductors and the grounding element; wherein each of the signal conductors has a wire-terminating end that is terminated to a corresponding signal contact of the substrate, the wire-terminating end projecting beyond a jacket edge of the cable jacket; and
a ground termination component having a main panel electrically coupled with the ground contact, and a strain relief element engaged with at least a portion of the communication cable; wherein the strain relief element includes a connective terminal electrically coupled to the grounding element.

US Pat. No. 10,367,291

MAGNETIC CONNECTOR ARRANGED IN A BENDABLE HOUSING IN AN ELECTRICALLY CONDUCTIVE CONNECTOR ASSEMBLY

SMK Corporation, Tokyo (...

1. A connector configured to be mated with a mating connector, the connector comprising:a plate-shaped housing;
an electrically conductive contact arranged on the housing; and
a plurality of retainer members which are formed from a magnetic substance or magnet and arranged in the housing, and when the connector is mated with the mating connector, attracted to a magnet the mating connector has so as to hold a mating state, wherein
the housing is formed from a bendable insulator,
the plurality of retainer members are spaced apart from each other in a predetermined direction parallel to one plate surface of the housing, and
the electrically conductive contact is formed from an electrically conductive rubber that penetrates through the housing.

US Pat. No. 10,367,290

CONNECTOR DEVICE AND MALE CONNECTOR

AutoNetworks Technologies...

1. A connector device, comprising:a male connector;
at least one male terminal fitting being part of the male connector, the male terminal fitting having a tab substantially projecting forward from a terminal body portion and having a leading end;
a terminal holding portion being part of the male connector, the terminal holding portion being capable of holding the terminal body portion;
a cover to be mounted on the terminal holding portion, a frame that is formed as a front part of the cover and surrounding the tab, the cover being displaceable between a protection position for where the frame at least partly coverings the tab and a retracted position displaced from the protection position to at least partly expose the leading end of the tab, at least one lock projecting in on the frame;
a female connector connectable to the male connector;
at least one female terminal fitting forming part of the female connector, the female terminal fitting being connectable to the tab by connecting the male connector and the female connector;
at least one pushing portion forming part of the female connector, the pushing portion being configured to be inserted into the frame and to displace the cover from the protection position toward or to the retracted position in the process of connecting the female connector to the male connector; and
at least one locking recess formed in an outer surface of the pushing portion and being configured to engage the locks projecting in on the frame and being configured to displace the cover from the retracted position toward or to the protection position by being locked to each other while separating the female connector from the male connector.

US Pat. No. 10,367,289

TERMINAL CONNECTING STRUCTURE AND CONNECTOR DEVICE

AutoNetworks technologies...

1. A connector device, comprising:a male terminal including a male connecting portion;
a female terminal formed from a conductive material and including a female connecting portion with opposite front and rear ends and opposite bottom and top plates extending rearward from the front end of the female connecting portion, the male connecting portion being insertable into and retractable from the front end of the female connecting portion, the inserted male connecting portion being placed on the bottom plate of the female connecting portion;
a movable portion supported in an electrically connected state to the female connecting portion by a support provided on the top plate at the front end of the female connecting portion, the movable portion being displaceable between the top and bottom plates with the support as a supporting portion;
a female contact provided on the movable portion, the female contact being displaceable between a non-pressing state where the female contact does not press the male connecting portion being inserted into the front end of the female connecting portion and a pressing state where the female contact presses the male connecting portion placed on the bottom plate of the female connecting portion in a direction intersecting an inserting/retracting direction of the male connecting portion and toward the bottom plate of the female connecting portion;
a pressed portion pressably provided at a position of the movable portion where a distance from the support to the pressed portion is longer than a distance between the support and the female contact, the pressed portion displacing the female contact from the non-pressing state to the pressing state with the support as a supporting portion by being pressed; and
a pressing portion displaceable toward the front end of the female connecting portion from an initial position where the pressing portion does not press the pressed portion to an end position where the pressing portion presses the pressed portion and causes the female contact to displace toward the bottom plate of the female connecting portion relative to the support provided on the top plate at the front end of the female connecting portion.

US Pat. No. 10,367,277

MULTI-EARTH TERMINAL ASSEMBLY

HYUNDIA MOTOR COMPANY, S...

1. A multi-earth terminal assembly comprising:two or more multi-earth terminals, wherein each of the two or more multi-earth terminals comprising:
a body having a hook piece and a hook rib on an outer edge of the body;
a barrel coupled with a wire;
a connector interconnecting the body with the barrel;
an engagement hole open toward an outer edge of the connector at one side of the connector; and
a hook boss protruding from a surface of the connector,
wherein two or more bodies are stacked vertically and coupled to each other, and
wherein when the two or more bodies are stacked vertically and coupled to each other, each of the two or more bodies includes the hook rib and the hook piece so that the hook rib of a first body that is located at an upper side of the vertically stacked bodies is inserted into and engaged with the hook piece of a second body that is located at a lower side of the vertically stacked bodies,
wherein, when the vertically stacked bodies rotate relative to each other, the hook boss of the second body is inserted into and engaged with the engagement hole of the first body,
wherein the engagement hole has an engagement step along an edge of the engagement hole and having a thickness which is relatively smaller than the connector,
wherein the hook boss has an engagement jaw at an upper end of the hook boss, the engagement jaw having a diameter larger than a diameter of the hook boss, and
wherein, when the hook boss is inserted into the engagement hole, the engagement jaw on the hook boss located at the lower side is seated on and engaged with the engagement step in the engagement hole.

US Pat. No. 10,367,276

CONDUCTIVE COMPONENT STRUCTURE OF WIRE CONNECTION TERMINAL

Switchlab Inc., New Taip...

1. A conductive component structure of wire connection terminal, comprising:a main body made of an electro-conductive material in the form of a plate body; and
a restriction body integrally formed on the main body or assembled/disposed on the main body, the restriction body defining a mouth section and having an oblique wall connected with the mouth section, the oblique wall extending from the mouth section to form a securing section in combination with the main body, the securing section narrowing both horizontally and vertically from the mouth section to thereby guide and secure a conductive wire plugged into the wire connection terminal.

US Pat. No. 10,367,273

SYSTEM AND METHOD FOR SEALING ELECTRICAL TERMINALS

TE CONNECTIVITY CORPORATI...

1. A system for sealing an electrical terminal, comprising:(a) a device for sealing a plurality of electrical wires to a wire attachment portion of an electrical terminal, wherein the device further includes:
(i) a shrinkable tubing having a predetermined length, wherein the shrinkable tubing has been placed over the plurality of electrical wires such that one end thereof extends over the wire attachment portion of the electrical terminal;
(ii) a sealant/adhesive, placed within the shrinkable tubing, the sealant/adhesive having a first portion proximate to an edge of the shrinkable tubing;
(iii) the sealant/adhesive having a strip of high viscosity sealant/adhesive proximate a strip of low viscosity sealant/adhesive;
(b) wherein upon an application of heat to the device after installation of the device over the electrical terminal, the shrinkable tubing starts to recover, the first portion of the sealant/adhesive flows and seals free ends of the plurality of electrical wires to seal the free ends of the electrical wires.

US Pat. No. 10,367,252

BROADBAND ANTENNA

Apple Inc., Cupertino, C...

1. An electronic device having opposing front and rear faces, comprising:a housing having a metal housing wall that forms an antenna ground for an antenna and having a window at the rear face;
a light-based component aligned with the window;
a coil that surrounds the light-based component;
wireless power receiver circuitry that uses the coil to receive wireless power signals through the rear face; and
radio-frequency transceiver circuitry configured to transmit and receive signals through the rear face using an antenna resonating element for the antenna.

US Pat. No. 10,367,243

MINIATURE LTCC COUPLED STRIPLINE RESONATOR FILTERS FOR DIGITAL RECEIVERS

BAE Systems Information a...

1. A low temperature co-fired ceramic stripline resonator filter comprising:a first layer configured as a ground layer comprising a metal;
a second layer comprising a dielectric material;
a third layer configured as a conductor layer comprising the metal and the dielectric material, the metal comprising a plurality of resonators comprising a first half of a stripline resonator pair arranged with an interdigital topology;
a fourth layer comprising the dielectric material;
a fifth layer configured as a conductor layer comprising the metal and the dielectric material, the metal comprising a plurality of resonators comprising a second half of the stripline resonator pair arranged with an interdigital topology;
a sixth layer comprising the dielectric material;
a seventh layer configured as a ground layer comprising the metal;
wherein the first, second, third, fourth, fifth, sixth and seventh layers are assembled to form the stripline filter having a width, a length, a thickness, a first end and a second end, and a first side and a second side;
a narrowband filter transformer loading structure launches an input and an output to a first and a second resonator of the stripline resonator pair, respectively;
a plurality of perimeter through plated vias being spaced apart along the length of the first side and along the length of the second side of the stripline filter and extending through the stripline filter from the first layer to the seventh layer creating a series of electric walls to contain electromagnetic fields inside the stripline filter; and
a plurality of through plated vias located between adjacent resonators of the stripline resonator pair and extending through the stripline filter from the first layer to the seventh layer to create a series of further electric walls thereby reducing the coupling between the adjacent resonators thereby forming a narrowband filter with a bandwidth of about 0.3 GHz to less than 1 GHz.

US Pat. No. 10,367,238

SPACE EFFICIENT BATTERY PACK DESIGNS

FORD GLOBAL TECHNOLOGIES,...

1. A battery pack, comprising:a first side oriented battery assembly;
a second side oriented battery assembly;
a vent chamber arranged between said first side oriented battery assembly and said second side oriented battery assembly; and
a heat exchanger device positioned axially between one of said first side oriented battery assembly and said second side oriented battery assembly and a third side oriented battery assembly,
wherein said heat exchanger device extends along a first longitudinal axis that is parallel to a second longitudinal axis of said vent chamber,
wherein said vent chamber is an enclosed space established by a top plate, a bottom plate, and two end plates,
wherein said top plate and said bottom plate rest against ledge strips that are attached to said first side oriented battery assembly or said second side oriented battery assembly,
wherein said top plate is contiguous with an enclosure lid and said bottom plate is contiguous with an enclosure base.

US Pat. No. 10,367,232

LOCALIZED SUPERCONCENTRATED ELECTROLYTES FOR STABLE CYCLING OF ELECTROCHEMICAL DEVICES

Battelle Memorial Institu...

1. An electrolyte, comprising:an active salt comprising lithium bis(fluorosulfonyl)imide (LiFSI), lithium bis(trifluoromethylsulfonyl)imide (LiTFSI), sodium bis(fluorosulfonyl)imide (NaFSI), sodium bis(trifluoromethylsulfonyl)imide (NaTFSI), lithium bis(oxalato)borate (LiBOB), sodium bis(oxalato)borate (NaBOB), LiPF6, LiAsF6, LiN(SO2CF3)2, LiN(SO2F)2, LiCF3SO3, LiClO4, lithium difluoro oxalato borate anion (LiDFOB), LiI, LiBr, LiCl, LiOH, LiNO3, LiSO4, or any combination thereof;
a solvent comprising dimethoxyethane (DME), dimethyl carbonate (DMC), 1,3-dioxolane (DOL), ethyl methyl carbonate (EMC), diethyl carbonate (DEC), dimethyl sulfoxide (DMSO), ethyl vinyl sulfone (EVS), tetramethylene sulfone (TMS), ethyl methyl sulfone (EMS), ethylene carbonate (EC), vinylene carbonate (VC), fluoroethylene carbonate (FEC), 4-vinyl-1,3-dioxolan-2-one, dimethyl sulfone, methyl butyrate, ethyl propionate, trimethyl phosphate, triethyl phosphate, gamma-butyrolactone, 4-methylene-1,3-dioxolan-2-one, methylene ethylene carbonate (MEC), 4,5-dimethylene-1,3-dioxolan-2-one, allyl ether, triallyl amine, triallyl cyanurate, triallyl isocyanurate, water, or any combination thereof, wherein the active salt is soluble in the solvent and a molar ratio of the active salt to the solvent is within a range of from 0.7 to 1.5; and
a diluent comprising 1,1,2,2-tetrafluoroethyl-2,2,2,3-tetrafluoropropyl ether (TTE), bis(2,2,2-trifluoroethyl) ether (BTFE), 1,1,2,2,-tetrafluoroethyl-2,2,2-trifluoroethyl ether (TFTFE), methoxynonafluorobutane (MOFB), ethoxynonafluorobutane (EOFB), or any combination thereof, wherein the active salt has a solubility in the diluent at least 10 times less than a solubility of the active salt in the solvent.

US Pat. No. 10,367,227

ELECTROLYTE COMPOSITION AND METAL-ION BATTERY EMPLOYING THE SAME

INDUSTRIAL TECHNOLOGY RES...

1. An electrolyte composition, comprising:a metal chloride;
a chlorine-containing ionic liquid; and
an additive, wherein the additive has a structure represented by Formula (I)
[M]i[(A(SO2CxF2x+1)y)b?]j  Formula (I),
wherein M is ammonium cation, azaannulenium cation, azathiazolium cation, benzimidazolium cation, benzofuranium cation, benzotriazolium cation, borolium cation, cholinium cation, cinnolinium cation, diazabicyclodecenium cation, diazabicyclononenium cation, diazabicyclo-undecenium cation, dithiazolium cation, furanium cation, guanidinium cation, imidazolium cation, indazolium cation, indolinium cation, indolium cation, morpholinium cation, oxaborolium cation, oxaphospholium cation, oxazinium cation, oxazolium cation, iso-oxazolium cation, oxathiazolium cation, pentazolium cation, phospholium cation, phosphonium cation, phthalazinium cation, piperazinium cation, piperidinium cation, pyranium cation, pyrazinium cation, pyrazolium cation, pyridazinium cation, pyridinium cation, pyrimidinium cation, pyrrolidinium cation, pyrrolium cation, quinazolinium cation, quinolinium cation, iso-quinolinium cation, quinoxalinium cation, selenozolium cation, sulfonium cation, tetrazolium cation, iso-thiadiazolium cation, thiazinium cation, thiazolium cation, thiophenium cation, thiuronium cation, triazadecenium cation, triazinium cation, triazolium cation, iso-triazolium cation, or uronium cation, wherein M has a valence of a; a is 1, 2, or 3; A is N, O, Si, or C; x is 1, 2, 3, 4, 5, or 6; y is 1, 2, or 3; b is 1, 2, or 3; i is 1, 2, or 3; j is 1, 2, or 3; a/b=j/i; and when y is 2 or 3, the (SO2CxF2x+1) moieties are the same or different.

US Pat. No. 10,367,226

NA BASED SECONDARY BATTERY

SK INNOVATION CO., LTD., ...

1. A Na based secondary battery comprising:an anode containing sodium or a sodium alloy;
a cathode containing metal halide, wherein the metal halide comprises sodium metal halide and a halide of at least one metal selected from a group consisting of transition metals, and Groups 12 to 14 metals, a solvent dissolving the metal halide, anda sodium ion conductive solid electrolyte separating the cathode and the anode from each other,wherein the secondary battery is charged by a charge reaction according to the following Reaction Formula 1 and discharged by a discharge reaction according the following Reaction Formula 2
mNaX+M?mNa+MXm  (Reaction Formula 1)
mNaX+M?mNa+MXm  (Reaction Formula 2)
wherein M is at least one metal selected from a group consisting of a group consisting of the transition metals and Groups 12 to 14 metals, X is a halogen atom, and m is a natural number of 1 to 4,
in which sodium halide (NaX) and metal halide (MXm) of Reaction Formula 1 and 2 are dissolved by the solvent at the time of charging and discharging; andthe cathode further comprises excess NaX (naq)(con) wherein the halide ion X is the same or different from the halide ion of Reaction Formula 1 or 2, andwherein (naq) means the NaX is dissolved in the solvent, and (con) means the NaX does not participate in the charge and discharge reaction of Formulas 1 and 2.

US Pat. No. 10,367,223

FUEL CELL STACK

HONDA MOTOR CO., LTD., T...

1. A fuel cell stack comprising:a stack of power generation cells that are stacked, each of the power generation cells including
a membrane electrode assembly in which electrodes are disposed on both sides of an electrolyte membrane, and
a separator stacked on the membrane electrode assembly;
end plates disposed at both ends of the stack of the power generation cells in a stacking direction; and
a resin fluid manifold member that is disposed on one of the end plates and through which a fluid flows, the fluid being a coolant, a fuel gas, or an oxidant gas,
wherein a plurality of recessed portions are formed, with ribs therebetween, in a contact surface of the resin fluid manifold member, the contact surface being in contact with the one of the end plates,
wherein the ribs have a height that does not extend to a height of the contact surface such that the ribs are spaced apart from the one of the end plates when the resin fluid manifold member is disposed on the one of the end plates.

US Pat. No. 10,367,209

RECYCLING SYSTEM OF ANODE OFF GAS IN FUEL CELL

Hyundai Motor Company, S...

1. A recycling system in which anode off gas of a fuel cell is recycled to a stack, comprising:a purge flow path purging the anode off gas passing through the stack; and
an ejector spraying pure gas supplied from a fuel tank to the stack,
wherein the ejector comprises a nozzle formed at an end of the ejector in a direction which extends toward the stack, and
wherein the nozzle is disposed on a path where the anode off gas is discharged from the stack to the purge flow path, the purge flow path is spaced a certain distance from the ejector, and the anode off gas passing through the stack is mixed with the pure gas by suction force of the ejector to be introduced to the stack, thereby being recycled.

US Pat. No. 10,367,206

METHOD FOR PREPARING METAL CATALYST SUPPORTED IN POROUS CARBON SUPPORT USING PLANT

Korea Institute of Scienc...

1. A method for preparing a metal catalyst supported on a porous carbon support using a plant, comprising:(a) providing a plant having roots and stems;
(b) preparing a metal precursor-absorbed plant by soaking the plant in a solution comprising a metal precursor;
(c) preparing a catalyst precursor by drying the metal precursor-absorbed plant;
(d) preparing a char by charring the catalyst precursor, wherein the preparing the char step comprises:
(d-1) preparing a primary char by charring the catalyst precursor under an air condition;
(d-2) preparing a secondary char by charring the primary char under an inert gas condition; and
(d-3) preparing a tertiary char by charring the secondary char under an ammonia gas condition; and
(e) preparing a metal catalyst supported on a porous carbon support by treating the char with an acid.

US Pat. No. 10,367,191

TIN SILICON ANODE ACTIVE MATERIAL

StoreDot Ltd., Herzeliya...

1. An anode, comprising anode active material particles which comprise 5-80% tin, wherein the anode active material particles further comprise nanoparticles attached thereto, wherein the nanoparticles are at least one order of magnitude smaller than the anode active material particles.

US Pat. No. 10,367,186

SECONDARY BATTERY INCLUDING AN INSULATING MEMBER

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:an electrode assembly comprising a first electrode and a second electrode;
a case containing the electrode assembly;
a cap plate sealing an opening of the case;
a collector terminal electrically connected to the first electrode of the electrode assembly and protruding through the cap plate to an outside of the case;
a coupling plate on the cap plate;
an insulating member on at least one area of the coupling plate; and
a terminal plate on the coupling plate and coupled to the collector terminal at the outside of the case, the insulating member being between the terminal plate and an outer surface of the cap plate,
wherein, in a normal operating state in which the first electrode and the second electrode are not short circuited, the terminal plate is electrically connected to the first electrode of the electrode assembly through the collector terminal and is electrically connected to the cap plate through at least a portion of the coupling plate that is in contact with the cap plate, and the second electrode of the electrode assembly is electrically insulated from the cap plate.

US Pat. No. 10,367,180

BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A battery pack, comprising:a battery holder comprising a cell holder accommodating a plurality of battery cells and a flange formed on a lateral side of the cell holder, wherein at least one coupling hole is formed in the flange;
a lead terminal comprising a lead plate and a lead tab, wherein the lead plate covers electrodes of the battery cells, wherein the lead tab extends from the lead plate toward the flange, wherein the lead tab includes a first portion downwardly extending from an end of the lead plate and a second portion outwardly extending from the first portion, wherein the first and second portions are formed on different planes, wherein at least one coupling hole is formed in the second portion of the lead tab, and wherein the second portion of the lead tab does not vertically overlap the lead plate;
a bus bar configured to form an electrical path between the lead tab and an external terminal, wherein at least one coupling hole is formed in the bus bar; and
a pack case comprising a coupler, wherein the external terminal is formed on the pack case, wherein a fastener is inserted into the at least one coupling hole of the bus bar, the at least one coupling hole of the second portion of the lead tab, and the at least one coupling hole of the flange, and wherein the fastener is engaged with the coupler.

US Pat. No. 10,367,164

FOLDABLE DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A foldable display apparatus that is adjustable between a folded configuration and an unfolded configuration, the foldable display apparatus comprising:a flexible display panel that is foldable;
a case comprising:
a first case that supports a first side of the flexible display panel; and
a second case that supports a second side of the flexible display panel;
an elastic piece connecting the first case to the second case, the elastic piece being substantially flat in the unfolded configuration;
a link member connecting the first case to the second case and comprising a concave-convex type single body metal sheet; and
a locking unit configured to prevent rotation of the first case and the second case in a folding direction when the foldable display apparatus is in the unfolded configuration.

US Pat. No. 10,367,156

ORGANIC METAL COMPLEX, AND ORGANIC LIGHT EMITTING DEVICE AND DISPLAY APPARATUS USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a device, the method comprising:preparing a substrate provided with one of an anode or a cathode;
forming an organic compound layer;
forming the other of the anode or the cathode;
wherein the organic compound layer comprises a metal complex having a structure represented by the following general formula (1):
MLmL?n  (1)
wherein L and L?, which are different from each other, each represent a bidentate ligand;
wherein m represents an integer of 1 to 3 and n represents an integer of 0 to 2, provided that m+n is 3;
wherein M represents Ir;
wherein the partial structure MLm has a structure represented by the following general formula (8):

wherein the benzene ring with R41-R44 attached thereto in the formula (8) is further represented by any one of the following formulae:

wherein *1 shows the connection to the Ir;
wherein *2 shows the connection to the benzo[f]isoquinoline ring represented in the formula (8);
wherein R88 to R102, which may be identical to or different from each other, each represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryloxy group, a substituted or unsubstituted aralkyl group, an amino group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group;
wherein the partial structure ML?n has a structure represented by any one of the following general formulae (10) to (12):

wherein R45 to R52, which may be identical to or different from each other, each represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryloxy group, a substituted or unsubstituted aralkyl group, an amino group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group, and R47 and R48 may be bonded to form a benzene ring that is fused with the benzo[f]isoquinoline ring represented in the formula (8); and
wherein R65 to R79, which may be identical to or different from each other, each represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, an alkoxy group, an aralkyl group, a substituted amino group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group, and adjacent substituents among R65 to R68 may be bonded to form a ring that is fused with the benzene ring represented in the formula (10), and adjacent substituents among R77 to R79 may be bonded to form a ring that is fused with the backbone represented in the formula (12).

US Pat. No. 10,367,138

MAGNETIC TUNNEL JUNCTION DEVICE

JAPAN SCIENCE AND TECHNOL...

1. A magnetic tunnel junction (MTJ) device, comprising:a first electrode comprising a first ferromagnetic material layer that includes Co, Fe, and B;
a barrier layer disposed over the first electrode, the barrier layer comprising a magnesium oxide (MgO) layer that is formed of a poly-crystalline MgO in which a (001) crystal plane is preferentially oriented; and
a second electrode disposed over the barrier layer and comprising a second ferromagnetic material layer that includes Co, Fe, and B, and
wherein each of the first and second ferromagnetic material layers is entirely crystallized,. and
wherein a value of x in MgOx for the MgO layer is greater than 0 and less than 1.

US Pat. No. 10,367,137

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY HAVING A VARIABLE RESISTANCE ELEMENT INCLUDING TWO FREE LAYERS

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory comprising a variable resistance element exhibiting different resistance states for storing data, the variable resistance element comprising:a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein the free layer includes:
a first free layer adjacent to the tunnel barrier layer and including CoFeB alloy; and
a second free layer spaced apart from the tunnel barrier layer by the first free layer and including at least one of CoFeBCd alloy or CoFeBSb alloy;
the variable resistance element further comprises: a seed layer under the free layer; and a capping layer on the pinned layer, wherein the first free layer is closer to the capping layer than the second free layer, and the second free layer is closer to the seed layer than the first free layer.

US Pat. No. 10,367,134

SHADOW MASK SIDEWALL TUNNEL JUNCTION FOR QUANTUM COMPUTING

INTERNATIONAL BUSINESS MA...

1. A tunnel junction device comprising:a first conducting layer having a height dimension greater than a width dimension, wherein a bottom of the first conducting layer is nearest to a substrate and a top of the first conducting layer is farthest from the substrate, wherein the height dimension extends vertically from the bottom to the top;
an oxide layer formed on the first conducting layer; and
a second conducting layer on the oxide layer covering a side portion of the first conducting layer, such that the oxide layer forms a sidewall tunnel junction between the second conducting layer and the side portion of the first conducting layer, wherein an angled portion of the second conducting layer is formed on a top of the first conducting layer such that an angled tunnel junction is formed, wherein the angled portion having a triangular shaped surface positioned to the angled tunnel junction.

US Pat. No. 10,367,133

EPITAXIAL SUPERCONDUCTING DEVICES AND METHOD OF FORMING SAME

The United States of Amer...

1. A method forming a superconducting region comprising the steps of:a. providing monolayers of a crystal;
b. cleaning the surface of said crystal;
c. introducing a plurality of molecules containing acceptor atoms to an uppermost monolayer of the crystal, thereby allowing said acceptor atoms to bind with said crystal;
d. allowing said acceptor atoms to incorporate into said crystal to provide a doped region of said crystal;
e. growing at least one monolayer of crystal over said doped region to form a new uppermost layer;
f. repeating steps c-e until a density of said acceptor atoms in said doped region is sufficient to allow the doped region to function as a superconductor at a desired critical temperature; and
g. encapsulating said superconducting region by growing a monolayer of crystal over said superconducting region.

US Pat. No. 10,367,132

NANOSCALE DEVICE COMPRISING AN ELONGATED CRYSTALLINE NANOSTRUCTURE

University of Copenhagen,...

1. A nanoscale device comprisingan elongated crystalline semiconductor nanostructure having a plurality of substantially plane side facets, and
a crystalline structured first facet layer of a superconductor material covering at least a part of at least one of said side facets,wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

US Pat. No. 10,367,131

EXTENDED AREA OF SPUTTER DEPOSITED N-TYPE AND P-TYPE THERMOELECTRIC LEGS IN A FLEXIBLE THIN-FILM BASED THERMOELECTRIC DEVICE

1. A method of a thin-film based thermoelectric module, comprising:forming the thin-film based thermoelectric module by sputter depositing pairs of N-type thermoelectric legs and P-type thermoelectric legs electrically in contact with one another on corresponding electrically conductive pads on a flexible substrate such that an area of each sputter deposited N-type thermoelectric leg and another area of each sputter deposited P-type thermoelectric leg is more than an area of the corresponding electrically conductive pad to allow for extension thereof outside the corresponding electrically conductive pad, the flexible substrate being one of: aluminum (Al) foil, a sheet of paper, teflon, plastic, a single-sided copper (Cu) clad laminate sheet, and a double-sided Cu clad laminate sheet, and the flexible substrate having a dimensional thickness less than or equal to 25 ?m;
rendering the formed thin-film based thermoelectric module flexible and less than or equal to 100 ?m in dimensional thickness based on choices of fabrication processes with respect to layers of the formed thin-film based thermoelectric module including the sputter deposited N-type thermoelectric legs and the P-type thermoelectric legs; and
encapsulating the formed thin-film based thermoelectric module with an elastomer to render the flexibility thereto, the elastomer encapsulation having a dimensional thickness less than or equal to 15 ?m, the flexibility enabling an array of thin-film based thermoelectric modules, each of which is equivalent to the thin-film based thermoelectric module formed on the flexible substrate with the elastomer encapsulation, to be completely wrappable and bendable around a system element from which the array of the thin-film based thermoelectric modules is configured to derive thermoelectric power, and a layer of the formed thin-film based thermoelectric module including the sputter deposited N-type thermoelectric legs and the P-type thermoelectric legs having a dimensional thickness less than or equal to 25 ?m.

US Pat. No. 10,367,129

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a mounting board comprising:
a base part, and
one or more wiring structures, each of which includes:
one or more first wiring layers located on an upper surface of the base part, and
one or more second wiring layers located on an upper surface of the one or more first wiring layers,
wherein a lower surface of the one or more second wiring layers contacts an upper surface of the one or more first wiring layers,
wherein, in a plan view, an area of each of the one or more second wiring layers is smaller than an area of each of the one or more first wiring layers;
one or more light emitting elements bonded to the second wiring layers via bonding members; and
a reflective member covering at least a portion of the bonding members and at least a portion of the one or more wiring structures,
wherein a reflectance of the one or more first wiring layers is higher than a reflectance of the bonding members,
wherein the one or more second wiring layers and the bonding members comprise the same material at their outermost surfaces,
wherein one or more outermost surfaces of the one or more first wiring layers comprise a metal selected from the group consisting of Al, Ag, Rh, Pt, Pd, and Ru, and an alloy containing at least one of these metals.

US Pat. No. 10,367,128

PIXEL STRUCTURE AND METHOD FOR THE FABRICATION THEREOF

Shenzhen China Star Optoe...

1. A method for fabricating a pixel structure for improving the utilization ratio of micro light emitting diodes, comprising:providing a substrate;
forming a black photoresist layer having a receiving cavity and an isolation region on the substrate;
coating a polyelectrolyte solution on the surface of the black photoresist layer except the isolation region, and air-drying the polyelectrolyte solution to form a polyelectrolyte layer;
coating a metal nanoparticle solution on the surface of the polyelectrolyte layer, and air-drying the metal nanoparticle solution to form a metal nanoparticle layer; and
aligning and transferring a micro light emitting diodes to the isolation region of the black photoresist layer.

US Pat. No. 10,367,127

LEAD FRAME INCLUDING HANGER LEAD, PACKAGE, AND LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A lead frame adapted to be incorporated in a package as being integrally formed with a supporting member, the package having a depression which is open on an upper side and in which a light-emitting element is to be mounted, side walls of the depression being mainly constituted of the supporting member, the lead frame comprising:at least one electrode arranged in a supporting member forming region to be supported by the supporting member and to define at least a part of a bottom surface of the depression, the supporting member forming region having an approximately rectangular shape in plan view, with the at least one electrode overlapping a first side of the approximately rectangular shape of the supporting member forming region in the plan view;
an outer frame connected to the at least one electrode and arranged outside of the supporting member forming region; and
at least one hanger lead extending from the outer frame so as to reach a second side of the approximately rectangular shape of the supporting member forming region with the second side being adjacent to the first side, the at least one hanger lead being arranged outside of the supporting member forming region, the at least one hanger lead being separated from the at least one electrode, the at least one hanger lead including at least one chamfered surface arranged on at least a part of an upper side corner of an end of the at least one hanger lead facing the supporting member forming region.

US Pat. No. 10,367,124

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A light emitting device comprising:a first film;
a first insulating layer over the first film;
a semiconductor layer over the first insulating layer;
a second insulating layer over the first insulating layer;
a gate electrode;
an interlayer insulating layer over the gate electrode and the second insulating layer;
an organic film over the interlayer insulating layer;
a light emitting element over the interlayer insulating layer, the light emitting element being electrically connected to the semiconductor layer; and
a sealant over the organic film,
wherein the gate electrode and the semiconductor layer overlap with each other with the second insulating layer provided therebetween,
wherein the sealant is in direct contact with a top surface of the organic film and an outermost side surface of the organic film, and
wherein the sealant is in direct contact with an upper surface of the first insulating layer in a region between an edge of the first film and the outermost side surface of the organic film.

US Pat. No. 10,367,123

LIGHT EMITTING DEVICE HAVING A DAM SURROUNDING EACH LIGHT EMITTING REGION AND A BARRIER SURROUNDING THE DAM AND FABRICATING METHOD THEREOF

Samsung Display co., Ltd....

1. A light emitting device comprising:a base substrate; and
a plurality of pixel regions on the base substrate, each of the pixel regions comprising:
a light emitting region, the light emitting region comprising a plurality of LEDs;
a barrier on the base substrate and defining the each of the pixel regions;
a dam on the base substrate to be spaced apart from the barrier, the dam being disposed in the each of the pixel regions to surround the light emitting region;
a plurality of first electrode lines disposed in the light emitting region; and
a plurality of second electrode lines disposed in the light emitting region, each of the second electrode lines spaced apart from each of the first electrode lines,
wherein at least one of the LEDs is electrically connected to one of the first electrode lines and one of the second electrode lines.

US Pat. No. 10,367,121

PACKAGE AND LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A package having a recess comprising:a pair of leads forming a surface of a bottom portion on the recess;
a first resin body forming a lateral wall on the recess;
a second resin body arranged between the pair of leads; and
a reflective film covering an inner surface of the lateral wall on the recess and an upper surface and a lower surface of the second resin body.

US Pat. No. 10,367,120

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A light-emitting diode, comprising:a light-emitting epitaxial laminated layer including:
a first semiconductor layer;
an active layer; and
a second semiconductor layer;
an ohmic contact layer over an upper surface of the light-emitting epitaxial laminated layer;
an expanding electrode over the ohmic contact layer;
a transparent insulating layer that covers the expanding electrode and an exposed ohmic contact layer and having a hole through the transparent insulating layer in a position corresponding to the expanding electrode; and
a welding wire electrode over the transparent insulating layer and coupled to the expanding electrode via the hole.

US Pat. No. 10,367,119

METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light-emitting device, the method comprising:providing a light-emitting element including a first region in a plan view thereof and a second region other than the first region, the second region not having an active layer disposed in the plan view of the light-emitting element, the light-emitting element including a layered semiconductor comprising the active layer located on the first region but not on the second region in the plan view of the light-emitting element, wherein the active layer is not visible from outside in a top view;
mounting the light-emitting element on a supporting member;
forming a phosphor layer so as to cover the light-emitting element;
determining a surplus portion of the phosphor layer; and
removing the phosphor layer at least partially from the second region in the light-emitting element.

US Pat. No. 10,367,117

APPARATUS AND METHOD FOR TRANSFERRING MICRO LIGHT-EMITTING DIODES

SHENZHEN CHINA STAR OPTOE...

1. An apparatus for transferring micro light-emitting diodes, which comprises: a main body, and a spraying module, a cooling module and a heating module disposed on said main body;said spraying module applied for spraying metallic adhesive liquid onto the micro light-emitting diodes that wait to transfer;
said cooling module applied for cooling the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes, thereby curing the metallic adhesive liquid to adhesively bond the main body with the wait-to-transfer micro light-emitting diodes together; and
said heating module applied for heating the cured metallic adhesive liquid, thereby melting the metallic adhesive liquid to separate the main body from the wait-to-transfer micro light-emitting diodes;
wherein said main body comprises a number of sequentially arranged transfer heads each disposed with a spraying nozzle on a bottom portion thereof, said spraying module sprays the metallic adhesive liquid onto the wait-to-transfer micro light-emitting diodes by the spraying nozzle;
wherein each neighboring pair of the transfer heads are disposed with a gas-blowing hole on therebetween, said cooling module blows gas outwardly via the gas-blowing hole, for cooling the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes.

US Pat. No. 10,367,116

METHOD OF REDUCING SODIUM CONCENTRATION IN A TRANSPARENT CONDUCTIVE OXIDE LAYER OF A SEMICONDUCTOR DEVICE

BEIJING APOLLO DING RONG ...

1. A semiconductor device manufacturing apparatus, comprising:at least one semiconductor deposition module configured to form a semiconductor material stack including a p-n junction on a substrate;
a conductive oxide deposition module configured to deposit a transparent conductive oxide layer over the semiconductor material stack; and
a fluid treatment module configured to contact a physically exposed surface of the transparent conductive oxide layer with a fluid to remove sodium from the transparent conductive oxide layer.

US Pat. No. 10,367,113

PHOTOELECTRIC CONVERSION DEVICE, IMAGING ELEMENT, AND IMAGING DEVICE

CANON KABUSHIKI KAISHA, ...

1. A device comprising a plurality of photoelectric conversion elements containing a light-emitting material disposed at light incident side of the photoelectric conversion element, the plurality of photoelectric conversion elements, which convert light having color different from each other, comprises:an upper and a lower electrode;
at least one first photoelectric conversion portion between the upper electrode and the lower electrode, the first photoelectric conversion portion including a photoelectric conversion layer;
at least one second photoelectric conversion portion;
a first readout circuit connected to the first photoelectric conversion portion;
a second readout circuit connected to the second photoelectric conversion portion;
an incoming light-blocking member between the first photoelectric conversion portion and the second photoelectric conversion portion; and
a wavelength limiter disposed closer than the first photoelectric conversion portion to the light-incident side, the wavelength limiter limiting the wavelength of light in a range from a minimum wavelength ?L1 to a maximum wavelength ?L2,
wherein the incoming light-blocking member blocks light in a wavelength region from a minimum wavelength ?S1 to a maximum wavelength ?S2, and the incoming light-blocking member and the wavelength limiter satisfy the following relationship (A):
?S1??L1??L2??S2  (A), and
wherein the second photoelectric conversion portion converts light emitted from the light-emitting material into electrical charges.

US Pat. No. 10,367,112

DEVICE FOR DIRECT X-RAY DETECTION

Nokia Technologies Oy, E...

1. An apparatus comprising:a plurality of substantially parallel conductive channels separated from one another by a quantum dot material comprising a plurality of quantum dots separated from one another by ligands having a chain length which is sufficiently short to facilitate transfer of an electron or a hole between neighboring quantum dots,
source and drain electrodes configured to enable a flow of electrical current through the conductive channels, and
a substrate configured to support the conductive channels, quantum dot material and source and drain electrodes, the conductive channels extending substantially perpendicular to the surface of the substrate,
wherein the quantum dot material is configured to generate an electron-hole pair on exposure to incident electromagnetic radiation, and
wherein the conductive channels and quantum dot material are configured such that another one of the electron or the hole of the electron-hole pair is transferred to one of the conductive channels leaving the remaining charge carrier in the quantum dot material, a diffusion length of the remaining charge carrier is limited by a dimension of the conductive channels rather than a thickness of the quantum dot material, the remaining charge carrier exhibiting an electric field which causes a change in electrical current passing through at least one of the conductive channels, the change in electrical current indicative of one or more of the presence and magnitude of the incident electromagnetic radiation.

US Pat. No. 10,367,110

PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING

First Solar, Inc., Tempe...

1. A process for manufacturing a photovoltaic device having a front contact layer stack and a semiconductorer stack, the process comprising:plasma cleaning an exposed surface of the semiconductor stack by exposing it to a plasma of ionized gases, wherein the plasma cleaning step removes from about 5 to about 500 angstroms at the surface of the exposed surface;
exposing the exposed surface of the semiconductor stack to an atmosphere that contains from about 1% to about 60% oxygen in an otherwise inert atmosphere to form an oxide layer on the exposed surface; and
forming a back contact layer stack on the oxide layer.

US Pat. No. 10,367,109

BACK SHEET OF SOLAR CELL MODULE, AND SOLAR CELL MODULE

DAIKIN INDUSTRIES, LTD., ...

1. A back sheet for a solar cell module, comprising:a water-impermeable sheet; and
a film,
the film being disposed on at least one side of the water-impermeable sheet and being formed from a coating containing a fluorine-containing copolymer,
the fluorine-containing copolymer containing:
(a) a C2-C3 perhaloolefin structural unit;
(b) a vinyl acetate structural unit;
(c) a hydroxy-containing vinyl monomer structural unit represented by the formula (1):
CH2?CH—(CH2)l—O—(CH2)m—OH,wherein 1 is 0 or 1, and m is an integer of 2 or greater; and(d) a carboxy-containing monomer structural unit represented by the formula (2):
R1R2C?CR3—(CH2)n—COOHwherein R1, R2, and R3 are the same as or different from each other, and are each a hydrogen atom or a C1-C10 linear or branched alkyl group, and n is 0 or 1.

US Pat. No. 10,367,108

PHOTODETECTION DEVICE AND IMAGING DEVICE

PANASONIC INTELLECTUAL PR...

1. A photodetection device, comprising:a photoelectric converter that generates charge;
a first charge transfer channel that has a first end and a second end, the first end being connected to the photoelectric converter, charge from the photoelectric converter being transferred in the first charge transfer channel in a first direction from the first end toward the second end;
a second charge transfer channel that diverges from the first charge transfer channel at a first position of the first charge transfer channel;
a third charge transfer channel that diverges from the first charge transfer channel at a second position of the first charge transfer channel, the second position being further than the first position from the first end in the first direction;
a first charge accumulator that accumulates charge transferred from the first charge transfer channel through the second charge transfer channel;
a second charge accumulator that accumulates charge transferred from the first charge transfer channel through the third charge transfer channel;
a first gate electrode that switches between transfer and cutoff of charge in the first charge transfer channel; and
at least one second gate electrode that switches between transfer and cutoff of charge in the second charge transfer channel, and that switches between transfer and cutoff of charge in the third charge transfer channel, wherein
a width of the third charge transfer channel is greater than a width of the second charge transfer channel in a plan view.

US Pat. No. 10,367,106

INTEGRATED PHOTODETECTOR WAVEGUIDE STRUCTURE WITH ALIGNMENT TOLERANCE

INTERNATIONAL BUSINESS MA...

1. A sensor structure, comprising:a photodetector with a window exposing a portion of a waveguide structure; and
an encapsulating material of a single material fully encapsulating and surrounding the photodetector, wherein the encapsulating material extends across and directly contacts an uppermost surface of the photodetector, and the encapsulating material is within divots or recesses in shallow trench isolation (STI) structures.

US Pat. No. 10,367,105

SOLAR CELL, SOLAR CELL MODULE, AND MANUFACTURING METHOD FOR SOLAR CELL

Panasonic Intellectual Pr...

1. A solar cell comprising:a photoelectric converter that includes a light receiving surface and a back surface opposed to the light receiving surface and includes n-type regions and p-type regions which are alternately arranged in a first direction on the back surface; and
an electrode layer that is provided only on the back surface, wherein
the photoelectric converter includes a plurality of sub-cells arranged in a second direction intersecting with the first direction and an isolation region provided between adjacent sub-cells,
the electrode layer includes an n-side electrode which is provided on the n-type regions in a first sub-cell at an end of the plurality of sub-cells and disposed within the first sub-cell, a p-side electrode which is provided on the p-type regions in a second sub-cell at the other end of the plurality of sub-cells and disposed within the second sub-cell, and a plurality of sub-electrodes which are provided over two adjacent sub-cells,
each sub-electrode of the plurality of sub-electrodes comprises:
a plurality of n-side parts which are provided on the n-type regions in one sub-cell of the two adjacent sub-cells;
a plurality of p-side parts which are provided on the p-type regions in the other sub-cell of the two adjacent sub-cells; and
a plurality of connection parts, each connecting one of the plurality of n-side parts and one of the plurality of p-type parts, and
in plan view, the plurality of connection parts are arranged along the first direction and spaced apart from each other over the isolation region, wherein
the photoelectric converter further includes:
a first conductivity type layer on the back surface, which forms the n-type regions;
a second conductivity type layer on the back surface, which forms the p-type regions; and
a third conductivity type layer on the light receiving surface, the third conductivity type layer having a first surface facing the light receiving surface of the substrate, and a second surface opposite to the first surface, and
the isolation region extends from the second surface of the third conductivity type layer to the back surface of the substrate through the third conductivity type layer and the substrate.

US Pat. No. 10,367,104

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell, comprising:a semiconductor substrate;
a conductive region on or at the semiconductor substrate;
an electrode electrically connected to the conductive region; and
a passivation layer on a light incident surface of the semiconductor substrate,
wherein the passivation layer comprises a first layer in contact with the light incident surface of the semiconductor substrate and formed of silicon oxynitride for ultraviolet stability,
wherein the first layer comprises a plurality of phases of the silicon oxynitride,
wherein the plurality of phases are formed of the same material of the silicon oxynitride having different compositions,
wherein the plurality of phases comprises a plurality of first phases and a plurality of second phases,
wherein the plurality of first phases have a higher oxygen content and a lower nitrogen content than that of the plurality of the second phases, and
wherein the plurality of first phases and the plurality of second phases are alternatively positioned in a thickness direction of the first layer,
wherein the plurality of first phases are in contact with the semiconductor substrate, and
wherein the plurality of first phases have different oxygen and nitrogen content from each other, or the plurality of second phases have different oxygen and nitrogen content from each other.

US Pat. No. 10,367,103

PHOTOELECTRIC CONVERSION ELEMENT

Ricoh Company, Ltd., Tok...

1. A photoelectric conversion element comprising:a first electrode having opaqueness to light and formed of a metal;
a hole blocking layer provided on the first electrode;
an electron transport layer provided on the hole blocking layer;
a hole transport layer provided on the electron transport layer; and
a second electrode provided on the hole transport layer and having transmissivity to light,
wherein
the hole blocking layer comprises an oxide of the metal in the first electrode, and the hole transport layer comprises a basic compound of formula (1):

wherein R1 and R2 represent a substituted or unsubstituted alkyl group or aromatic hydrocarbon group and may be identical or different, and R1 and R2 may bind with each other to form a substituted or unsubstituted heterocyclic group comprising a nitrogen atom.

US Pat. No. 10,367,102

ELECTRONIC COMPONENT AND EQUIPMENT

CANON KABUSHIKI KAISHA, ...

1. An electronic component comprising:a support member in which a recess part having a bottom face and a side face is provided; and
a device unit that includes a substrate and fixed to the support member so that a primary face of the substrate faces the recess part,
wherein an opening width of the recess part is, on a side of a bottom of the recess part with respect to the primary face, narrower than a width of the device unit and, on an opposite side of the bottom of the recess part with respect to the primary face, wider than the width of the device unit,
wherein an end face of the substrate overlaps with the side face of the recess part in a direction perpendicular to the primary face of the substrate, and
wherein a photoelectric conversion element is arranged on the primary face of the substrate.

US Pat. No. 10,367,101

SCHOTTKY DIODE AND METHOD OF MANUFACTURING THE SAME

GPOWER SEMICONDUCTOR, INC...

1. A Schottky diode, comprising:a substrate;
a first semiconductor layer located on the substrate;
a second semiconductor layer located on the first semiconductor layer, two-dimensional electron gas being formed at an interface between the first semiconductor layer and the second semiconductor layer;
a cathode located on the second semiconductor layer and forming an ohmic contact with the second semiconductor layer;
a first passivation dielectric layer located on the second semiconductor layer;
a field plate groove formed in the first passivation dielectric layer; and
an anode covering the field plate groove and a portion of the first passivation dielectric layer,
wherein a distance between a bottom surface of the field plate groove and the two-dimensional electron gas in a height direction is greater than 5 nm.

US Pat. No. 10,367,099

TRENCH VERTICAL JFET WITH LADDER TERMINATION

United Silicon Carbide, I...

1. A vertical JFET, comprising:a) a substrate, the substrate having a top and a bottom vertically, the substrate having a perimeter horizontally;
b) an active cell region, the active cell region being on the top of the substrate and comprising source regions, gate regions, active region trenches, and active region mesas;
c) a backside drain connection, the backside drain connection being on the bottom of the substrate;
d) a termination region, the termination region being on the top of the substrate and comprising termination region trenches and termination region mesas;
e) in each mesa of the termination region, a region with source doping, the region with source doping being at the top of the mesa and having an N doping type and a doping concentration that is the same as the doping concentration of the source regions, wherein the regions with source doping are ohmically isolated from each other and from the source regions; and
f) in each termination region mesa, a region with gate doping, the region with gate doping being on each wall of the mesa and having a P doping type and a doping concentration that is the same as the doping concentration of the gate regions, wherein the regions with gate doping are ohmically isolated from each other and from the gate regions,
g) such that in each mesa of the termination region, the regions with gate doping on each wall of the mesa abut and form a PNP structure with the region with source doping.

US Pat. No. 10,367,098

VERTICAL JFET MADE USING A REDUCED MASKED SET

United Silicon Carbide, I...

1. A vertical JFET, comprising:a) a substrate, the substrate having a top and a bottom vertically, the substrate having a perimeter horizontally;
b) a backside drain connection, the backside drain connection being on the bottom of the substrate; and
c) on the top of the substrate, an active cell region and a termination region, the active cell region and the termination region each comprising a plurality of mesas and a plurality of trenches;
d) wherein each mesa comprises gate-doped regions on the sides of the mesa, a source-doped region at the top of the mesa, and, between the gate-doped regions and below the source-doped region, a channel region;
e) wherein each mesa further comprises, atop the source-doped region, a source contact silicide region; and
f) wherein each trench comprises, at the bottom of the trench, a gate-doped region connecting to the gate-doped regions of the mesa, and atop the gate-doped region of the trench, a gate contact silicide region;
g) the vertical JFET further comprising a gate buss connecting the gate contact silicide regions of the active cell region, and a source buss connecting the source contact silicide regions of the active cell region;
h) wherein the gate contact silicide regions and the source contact silicide regions of the termination region are individually ohmically isolated from each other, from the gate buss, and from the source buss; and
i) wherein the doping levels of the gate-doped regions, the source-doped regions, and the channel regions, and the width of the mesas in the termination region, are selected such that a punch through voltage of the mesas of the termination region is less than a breakdown voltage of a P-N junction between the gate-doped region and the source-doped region of each mesa of the termination region, such that an off-state blocking voltage of the vertical JFET is the sum of the punch-through voltages of the P-N junctions of the gate-doped regions and the source-doped regions of the termination region.

US Pat. No. 10,367,097

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A liquid crystal display device, comprising:a first substrate and a second substrate spaced apart from each other;
a liquid crystal layer between the first substrate and the second substrate;
a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate;
a first switching element connected to the gate line, the data line, and the first sub-pixel electrode; and
a second switching element connected to the gate line, the first sub-pixel electrode, and the second sub-pixel electrode,
wherein the first switching element has a threshold voltage that is lower than a threshold voltage of the second switching element, and
wherein the first switching element includes a semiconductor layer having a thickness that is 1/y times a thickness of a semiconductor layer of the second switching element, y being a rational number greater than or equal to 3.

US Pat. No. 10,367,096

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, MODULE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductor;
a second conductor;
a third conductor;
a fourth conductor;
a fifth conductor;
a first insulator;
a second insulator;
a third insulator;
a fourth insulator;
a fifth insulator;
a semiconductor; and
an opening,
wherein the second insulator is over the first insulator,
wherein the semiconductor is over the second insulator,
wherein the first conductor and the second conductor are over the semiconductor,
wherein the third conductor is over the first conductor,
wherein the fourth conductor is over the second conductor,
wherein the third insulator is over the first insulator, the semiconductor, the first conductor, the second conductor, the third conductor, and the fourth conductor,
wherein the opening exposes part of the first insulator, part of the semiconductor, part of the first conductor, part of the second conductor, part of the third conductor, and part of the fourth conductor,
wherein the fourth insulator is along a side surface and a bottom surface of the opening,
wherein the fifth insulator is over the fourth insulator,
wherein the fifth conductor comprises a region overlapping with the semiconductor with the fourth insulator and the fifth insulator therebetween, the region being included in the opening,
wherein the first conductor has a shape such that an end portion of the first conductor inwardly extends beyond an end portion of the second third conductor in the opening, and
wherein the second conductor has a shape such that an end portion of the second conductor inwardly extends beyond an end portion of the fourth conductor in the opening.

US Pat. No. 10,367,094

SOURCE/DRAIN STRUCTURE HAVING MULTI-FACET SURFACES

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a semiconductor substrate having a source/drain region and a gate region;
a fin structure disposed over the semiconductor substrate, the fin structure including a first portion having a first height in the source/drain region and a second portion having a second height in the gate region, the second height being different than the first height;
a gate structure disposed over the first portion of the fin structure, the gate structure including a gate dielectric physically contacting the first portion of the fin structure;
a plurality of isolation regions over the semiconductor substrate; and
a source/drain feature disposed over the second portion of the fin structure in the source/drain region, the source/drain feature including:
multiple lower portions that are isolated from each other by a lateral separation; and
a single upper portion over the isolation regions, wherein the single upper portion is merged from the multiple lower portions, wherein the single upper portion has a top surface facing away from a top surface of the isolation regions, wherein the top surface of the single upper portion includes a first flat surface connected to a first multi-facet surface and a second flat surface connected to the first multi-facet surface.

US Pat. No. 10,367,093

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

1. An apparatus comprising:a substrate comprising Si;
a fin comprising Si on the substrate;
a gate electrode having a work function metal comprising: W, Ta, Ti, and N;
a first spacer;
a second spacer, wherein the first and second spacers comprise N;
a gate dielectric between: the gate electrode and the fin, the gate electrode and the first spacer, and the gate electrode and the second spacer, wherein the gate dielectric comprises Hf and O,
a source; and
a drain;
wherein:
a portion of the fin under the gate electrode has a first width,
a portion of the fin outside the gate electrode and closer to the drain or source regions has a second width, and
the second width is greater than the first width.

US Pat. No. 10,367,090

SILICON CARBIDE SEMICONDUCTOR DEVICE, POWER MODULE, AND POWER CONVERSION DEVICE

Hitachi, Ltd., Tokyo (JP...

1. A silicon carbide semiconductor device comprising:a semiconductor substrate which includes an n-type substrate containing silicon carbide and an n-type semiconductor layer containing silicon carbide formed over the n-type substrate, the semiconductor substrate having an element region and a first region surrounding the element region in plan view;
a p-type first semiconductor region formed on an upper surface of the semiconductor substrate within the element region;
an n-type source region formed on an upper surface of the first semiconductor region;
a p-type first contact region formed on the upper surface of the first semiconductor region;
a p-type second semiconductor region formed on the upper surface of the semiconductor substrate within the first region and surrounding the element region in plan view;
a p-type second contact region formed on an upper surface of the second semiconductor region and surrounding the element region in plan view;
an n-type drain region formed on a lower surface of the semiconductor substrate;
a gate electrode formed on the upper surface of the first semiconductor region adjacent to the source region via an insulating film;
a first electrode formed on the second contact region; and
a conductive connecting portion formed on the second contact region and electrically connecting the first electrode and the second contact region to each other,
wherein the gate electrode, the source region and the drain region configure a field effect transistor, and
the second semiconductor region and the semiconductor substrate configure a diode.

US Pat. No. 10,367,089

SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY

GENERAL ELECTRIC COMPANY,...

1. A semiconductor device, comprising:a semiconductor substrate comprising silicon carbide, said substrate having a first surface and a second surface;
a contact layer disposed on the first surface of the substrate covering a portion of a source contact region;
a gate electrode disposed on a portion of the first surface of the substrate;
a drain electrode disposed on the second surface of the substrate;
a dielectric layer disposed on the gate electrode and extending in a direction normal to the first surface;
a remedial layer disposed on the dielectric layer, wherein said remedial layer is configured to mitigate negative bias temperature instability such that a change in threshold voltage is in a range of between 100 millivolts to 1 volt, wherein said change in threshold voltage occurs under a gate to source voltage bias and when a drain current is about 10 microamps with a VDS=0.1 V, wherein said remedial layer has a thickness of less than about 300 nm; and
a source electrode disposed on said remedial layer, wherein said source electrode is electrically coupled to the source contact region of the semiconductor substrate,
wherein said remedial layer comprises titanium and is configured to provide a continuous conformal coverage of the dielectric layer including in the direction normal to the first surface.

US Pat. No. 10,367,087

TRANSISTOR STRUCTURE INCLUDING A SCANDIUM GALLIUM NITRIDE BACK-BARRIER LAYER

1. A transistor comprising:a substrate;
a buffer layer disposed on the substrate;
a back-barrier layer on the buffer layer, the back-barrier layer including scandium gallium nitride;
a channel layer disposed on the back-barrier layer; and
a barrier layer disposed on the channel layer.

US Pat. No. 10,367,084

CASCODE HETEROJUNCTION BIPOLAR TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A structure formed using a device layer of a silicon-on-insulator substrate, the structure comprising:a first heterojunction bipolar transistor including a first emitter in the device layer, a first base layer with an intrinsic base portion on the first emitter, and a first collector on the intrinsic base portion of the first base layer, the intrinsic base portion of the first base layer arranged in a vertical direction between the first emitter and the first collector; and
a second heterojunction bipolar transistor including a second collector in the device layer, a second base layer with an intrinsic base portion on the second collector, and a second emitter on the intrinsic base portion of the second base layer, the intrinsic base portion of the second base layer arranged in the vertical direction between the second emitter and the second collector,
wherein the first emitter is coupled with the second collector, and the first emitter and the second collector each extend vertically in the device layer to a buried oxide layer of the silicon-on-insulator substrate.

US Pat. No. 10,367,080

METHOD OF FORMING A GERMANIUM OXYNITRIDE FILM

ASM IP Holding B.V., Alm...

1. A method of forming a germanium oxynitride film comprising:providing a substrate for processing in a reaction chamber;
using a germanium precursor and an oxygen precursor, performing an atomic layer deposition cycle of an oxide comprising germanium onto the substrate; and
before or after performing the atomic layer deposition cycle of the oxide, using a germanium precursor and a nitrogen precursor, performing an atomic layer deposition cycle of a nitride comprising germanium onto the substrate;
wherein the atomic layer deposition cycle of the oxide and the atomic layer deposition cycle of the nitride are repeated as desired in order to form the germanium oxynitride film of a desired thickness and stoichiometry, and
wherein the oxygen precursor and the nitrogen precursor are different.

US Pat. No. 10,367,079

METHOD AND STRUCTURE FOR FINFET COMPRISING PATTERNED OXIDE AND DIELECTRIC LAYER UNDER SPACER FEATURES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate having a fin projecting upwardly through an isolation structure over the substrate;
a gate stack over the isolation structure and engaging the fin;
a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack;
a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity; and
a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials, wherein the second dielectric layer is in physical contact with the gate spacer.

US Pat. No. 10,367,078

SEMICONDUCTOR DEVICES AND FINFET DEVICES HAVING SHIELDING LAYERS

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate; and
a gate structure over the substrate and comprising:
a high-k layer over the substrate;
a shielding layer over the high-k layer; and
an N-type work function metal layer over the shielding layer,
wherein a dielectric constant of the shielding layer is less than a dielectric constant of the high-k layer.

US Pat. No. 10,367,077

WRAP AROUND CONTACT USING SACRIFICIAL MANDREL

International Business Ma...

15. A semiconductor structure comprising at least:a plurality of unmerged fin structures;
a separate source/drain in contact with each unmerged fin structure of the plurality of unmerged fin structures, wherein the source/drain comprises a rectangular shape; and
a contact layer formed on sidewalls and a top surface of each source/drain.

US Pat. No. 10,367,076

AIR GAP SPACER WITH CONTROLLED AIR GAP HEIGHT

INTERNATIONAL BUSINESS MA...

1. A method for fabricating an air gap spacer in a FinFET, the method comprising:depositing a sacrificial gate structure in a gate region, the sacrificial gate structure having an upper sacrificial layer, a lower sacrificial layer, and an etch stop layer between the upper sacrificial layer and the lower sacrificial layer;
removing the upper sacrificial layer selective to the etch stop layer to expose a sidewall spacer region; and
depositing an airgap spacer material in the exposed sidewall spacer region to form an upper portion of a sidewall spacer, the upper portion having the air gap.

US Pat. No. 10,367,075

APPROACH TO PREVENTING ATOMIC DIFFUSION AND PRESERVING ELECTRICAL CONDUCTION USING TWO DIMENSIONAL CRYSTALS AND SELECTIVE ATOMIC LAYER DEPOSITION

INTERNATIONAL BUSINESS MA...

1. A method of restricting diffusion of miscible materials across a barrier, comprising:forming a plug selectively on each portion of a substrate surface exposed through one or more defects in a 2-dimensional material on the substrate surface; and
forming a solid cover layer on the plug and 2-dimensional material, wherein at least a component of the solid cover layer material is miscible in the substrate material.

US Pat. No. 10,367,074

METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS

Cree, Inc., Durham, NC (...

1. A semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface opposing the first main surface;
an active epitaxial device layer on the first main surface of the silicon carbide substrate;
a via extending from the second main surface into the silicon carbide substrate toward the first main surface;
a first electrical contact over the active epitaxial device layer; and
a second electrical contact overlying the second main surface and within the via, wherein the first electrical contact is separated from the second electrical contact at the active epitaxial device layer.

US Pat. No. 10,367,073

THIN FILM TRANSISTOR (TFT) WITH STRUCTURED GATE INSULATOR

BOE TECHNOLOGY GROUP CO.,...

1. A thin-film transistor (TFT), comprising:a base substrate;
a gate electrode and a gate insulating layer, disposed on the base substrate; and
an active layer, wherein the gate insulating layer is disposed between the active layer and the gate electrode;
the active layer includes a channel region and a doped region disposed on at least one side of the channel region; and
the gate insulating layer is provided with a protrusion which is disposed between the doped region and the gate electrode,
wherein, the protrusion includes a first protrusion and a second protrusion which are spaced from each other, the doped region includes a first doped region and a second doped region which are respectively disposed on both sides of the channel region,
the first doped region comprises a first lightly doped region and a first heavily doped region, the second doped region comprises a second lightly doped region and a second heavily doped region, and a carrier concentration of the first lightly doped region and the second lightly doped region is smaller than a carrier concentration of the first heavily doped region and the second heavily doped region,
the first protrusion further includes a first exposing portion, an orthographic projection of the first exposing portion on the base substrate exceeds an orthographic projection of the gate electrode on the base substrate;
the second protrusion further includes a second exposing portion, an orthographic projection of the second exposing portion on the base substrate exceeds the orthographic projection of the gate electrode on the base substrate, and the first exposing portion at least partially overlaps with the first lightly doped region, the second exposing portion at least partially overlaps with the second lightly doped region,
the gate insulating layer further includes a spacing region disposed between the first protrusion and the second protrusion, and the spacing region is disposed between the gate electrode and the channel region, the spacing region completely overlaps with the channel region, and
the gate insulating layer includes a planarization portion disposed outside the first protrusion and the second protrusion and overlapped with the first heavily doped region and the second heavily doped region,
a thickness of the protrusion is larger than a thickness of the spacing region and a thickness of the planarization portion.

US Pat. No. 10,367,072

ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE

INTERNATIONAL BUSINESS MA...

1. A gate structure comprising a gate material on an asymmetrically thick gate dielectric comprising an oxide wherein the asymmetrically thick gate dielectric is thicker on a drain side of the gate structure than a source side of the gate structure, wherein the asymmetrically thick gate dielectric includes a high-k material and an interfacial dielectric layer of fin material under the high-k material, and a damaged spacer material is on the drain side along a sidewall of the gate structure and a non-damaged spacer material is on the source side of the device along another sidewall of the gate structure.

US Pat. No. 10,367,071

METHOD AND STRUCTURE FOR A LARGE-GRAIN HIGH-K DIELECTRIC

NXP USA, INC., Austin, T...

1. A semiconductor device comprising:a metal oxide comprising a first metal, oxygen, and a catalyst, wherein the first metal has a first concentration, the catalyst has a second concentration, and first concentration is at least ten thousand times greater than the second concentration; and
a conductive layer over the metal oxide.

US Pat. No. 10,367,070

METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED THEREBY

Intel Corporation, Santa...

1. A microelectronic structure comprising:a substrate;
a device layer on the substrate;
at least one device within the device layer, wherein the at least one device comprises a gate electrode between a source region and a/drain region;
a first source contact coupled to a first side of the source region;
a first drain contact coupled to a first side of the drain region;
a second source contact coupled to a second side of the source region; and
a second drain contact coupled to a second side of the drain region, wherein the source region and the drain region comprise an epitaxial material, wherein the epitaxial material comprises silicon and germanium.

US Pat. No. 10,367,067

SEMICONDUCTOR DEVICE HAVING AN OXYGEN DIFFUSION BARRIER

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor body comprising opposite first and second surfaces;
a drift or base zone in the semiconductor body;
an oxygen diffusion barrier comprising SiGe and formed in the semiconductor body, wherein the drift or base zone is located between the first surface and the oxygen diffusion barrier and directly adjoins the oxygen diffusion barrier; and
first and second load terminal contacts, wherein at least one of the first and the second load terminal contacts is electrically connected to the semiconductor body through the first surface.

US Pat. No. 10,367,066

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a thin film transistor, wherein the thin film transistor is provided with a gate layer, a gate insulation layer, an IGZO (indium gallium zinc oxide) layer, a source, and a drain in sequence from inside to outside, and each of the source and the drain is provided with a first metal layer, a second metal layer, and a third metal layer in sequence from inside to outside, the first metal layer being in contact with the IGZO layer, andwherein the method comprises the following steps:
Step I. sequentially preparing the gate layer, the gate insulation layer, and the IGZO layer on a substrate;
Step II. preparing the source and the drain, and sequentially preparing the first metal layer, the second metal layer, and the third metal layer on each of the gate insulation layer and the IGZO layer;
Step III. preparing passivation layers; and
Step IV. performing high temperature annealing treatment on the passivation layers, indium within the first metal layer diffusing into the IGZO layer to form metal diffusion layers, thereby forming Ohmic contact at interfaces both between the IGZO layer and the source and between the IGZO layer and the drain.

US Pat. No. 10,367,065

DEVICE ISOLATION FOR III-V SUBSTRATES

International Business Ma...

1. A method of fabricating a III-V semiconductor device, the method comprising the steps of:providing a substrate having an indium phosphide-ready layer;
forming an iron-doped indium phosphide layer on the indium phosphide-ready layer;
forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer; and
patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more fins which comprise the one or more active areas of the device.

US Pat. No. 10,367,063

SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET INTERCONNECTING A SOURCE REGION AND A DRAIN REGION

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, the method comprising:forming a first semiconductor layer over a substrate;
forming a second semiconductor layer over the first semiconductor layer;
forming a third semiconductor layer over the second semiconductor layer;
forming a recess that extends through the second and third semiconductor layers and into the first semiconductor layer; and
forming a silicide that contacts and surrounds the third semiconductor layer following the formation of the recess.

US Pat. No. 10,367,062

CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming nanosheet semiconductor devices, comprising:forming a first stack comprising layers of a first material and layers of a second material; forming a second stack comprising layers of a third material, layers of the second material, and a liner formed around the layers of the third material;
forming a dummy gate stack over channel regions of each of the first and second stacks;
depositing a passivating insulator layer around the dummy gate stacks; etching away the dummy gate stacks;
etching away the second material after etching away the dummy gate stacks; and
forming gate stacks over and around the layers of first and second channel material to form respective first and second semiconductor devices.

US Pat. No. 10,367,061

REPLACEMENT METAL GATE AND INNER SPACER FORMATION IN THREE DIMENSIONAL STRUCTURES USING SACRIFICIAL SILICON GERMANIUM

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming stacks each of which including two or more nanosheets separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanosheets in the stacks, wherein a lower spacer material is on a periphery of the two or more nanosheets, wherein the lower spacer material is on a top surface of an upper most nanosheet of the two or more nanosheets, wherein an upper spacer material is directly on the lower spacer material such that the upper spacer material is above a top one of the two or more nanosheets; and
forming source and drain regions on sides of the stacks.

US Pat. No. 10,367,060

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

International Business Ma...

1. A method for fabricating a semiconductor device with selective oxidation, the method comprising:depositing a stack of two crystalline semiconductor layers over a base layer, wherein the base layer comprises a semiconductor substrate and a first insulator layer, and wherein the semiconductor substrate is 100 nanometers to 1 micrometer in thickness;
performing shallow trench isolation within the base layer to form a plurality of trenches that expose a set of sides of the two crystalline semiconductor layers;
depositing a second insulator layer into the plurality of trenches of the base layer;
selectively oxidizing a first of the two crystalline semiconductor layers to yield a selectively oxidized layer that serves as an insulator for a second of the two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers maintain a layered configuration after oxidation of the first of the two crystalline semiconductor layers;
forming a dummy gate structure, wherein a set of spacers are along sides of the dummy gate structure;
forming source and drain regions in contact with each exposed side of the set of sides of the oxidized first semiconductor layer and the second semiconductor layer of the two crystalline semiconductor layers;
depositing an insulating material;
planarizing the deposited insulator material until the dummy gate structure is exposed;
removing the dummy gate structure;
etching the selectively oxidized crystalline semiconductor layer;
forming a replacement gate layer between a plurality of walls within the set of spacers;
depositing a high-K insulator around the replacement gate layer; and
rendering a second of the two crystalline semiconductor layers as a channel region.

US Pat. No. 10,367,059

METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING A BURIED RAISED PORTION

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first trench and a second trench in a semiconductor substrate to define a raised portion between the first trench and the second trench;
reducing a height of the raised portion;
filling the first trench and the second trench with a flowable dielectric;
curing the flowable dielectric; and
removing the flowable dielectric after the curing such that the raised portion is buried under the flowable dielectric after the removing.

US Pat. No. 10,367,058

CHANNEL STOP IMP FOR THE FINFET DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate structure including a substrate, at least one semiconductor fin on the substrate entirely formed with a same material as the substrate, and an isolation region on opposite sides of the at least one semiconductor fin;
implanting ions into the substrate structure to form a doped region in the at least one semiconductor fin and in the isolation region;
etching back the isolation region to expose a portion of the at least one semiconductor fin; and
after the isolation region has been etched back, performing an annealing process to activate the implanted ions in the doped region,
wherein providing the substrate structure comprises:
providing an initial substrate;
forming a patterned hardmask on the initial substrate;
etching the initial substrate using the patterned hardmask as a mask to form the substrate, the at least one semiconductor fin, and a recess on the opposite sides of the at least one semiconductor fin;
depositing an isolation material filing the recess and covering the hardmask;
planarizing the isolation material in the recess so that the upper surface of isolation material is substantially flush with the upper surface of the hardmask;
etching back the planarized isolation material to expose a side surface of the hardmask; and
removing the hardmask to form the substrate structure.

US Pat. No. 10,367,057

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGIONS

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
a first cell and a second cell, each being electrically connected to the first load terminal structure on the one side and electrically connected to a drift region of the semiconductor body on the other side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; the first cell being configured to induce a load current path in the first channel region in a conducting state;
a second mesa included in the second cell, the second mesa including: a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by a first insulation structure and exhibiting a total extension of less than 100 nm in said direction;
a further port region comprising an emitter of the second conductivity type being electrically connected to the second load terminal structure,
wherein the power semiconductor device further comprises a third cell being electrically connected to the second load terminal structure on the one side and electrically connected to the drift region on the other side; wherein the third cell includes a third mesa comprising: a third port region having the first conductivity type and being electrically connected to the second load terminal structure; a third channel region being coupled to the drift region; and a third control electrode being insulated from the third mesa by a second insulation structure.

US Pat. No. 10,367,056

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a first semiconductor region of a second conductivity type selectively provided on a semiconductor substrate of a first conductivity-type;
a second semiconductor region of the second conductivity type surrounding a periphery of the first semiconductor region;
a third semiconductor region of the first conductivity type provided outside of the second semiconductor region;
a fourth semiconductor region of the second conductivity type selectively provided in the third semiconductor region;
a fifth semiconductor region of the second conductivity type selectively provided in one of the first semiconductor region and the second semiconductor region, an impurity concentration of the fifth semiconductor region being higher than that of the second semiconductor region;
a first gate electrode provided on a surface of a portion of the third semiconductor region between the fourth semiconductor region and the second semiconductor region, the first gate electrode provided via a first gate insulating film;
a first electrode contacting the third semiconductor region and the fourth semiconductor region;
a second electrode contacting the fifth semiconductor region;
a sixth semiconductor region of the second conductivity type selectively provided in one of the first semiconductor region and the second semiconductor region, separate from the fifth semiconductor region, an impurity concentration of the sixth semiconductor region being higher than that of the second semiconductor region;
a seventh semiconductor region of the first conductivity type selectively provided in the third semiconductor region, an impurity concentration of the seventh semiconductor region being higher than that of the third semiconductor region, wherein the first electrode is in contact with the seventh semiconductor region; and
a third electrode contacting the sixth semiconductor region, wherein
a first distance between the fourth semiconductor region and the fifth semiconductor region is a drift length of a first element,
a second distance between the seventh semiconductor region and the sixth semiconductor region is a drift length of a second element different from the first element, and
the first distance is longer than the second distance.

US Pat. No. 10,367,055

EPITAXIAL STRUCTURE HAVING NANOTUBE FILM FREE OF CARBON NANOTUBES

Tsinghua University, Bei...

1. An epitaxial structure comprising:a substrate having an epitaxial growth surface;
an epitaxial layer located on the epitaxial growth surface of the substrate; and
a nanotube film located between the substrate and the epitaxial layer, wherein the nanotube film comprises a plurality of nanotubes combined with each other by ionic bonds, the nanotube film is free of carbon nanotubes, and the nanotube film is a free-standing structure; a part of the plurality of nanotubes extends from a first side of the nanotube film to a second side opposite to the first side, and a first length of the part of the plurality of nanotubes is the same as a second length or a width of the nanotube film; and adjacent two of the plurality of nanotubes are internal communicated at contacting surface, and the plurality of nanotubes extends along a direction parallel to the epitaxial growth surface; wherein a majority of the plurality of nanotubes are orderly arranged to substantially extend along the same direction, and a minority of the plurality of nanotubes are dispersed on, randomly arranged, and in direct contact with the majority of the plurality of nanotubes.

US Pat. No. 10,367,054

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a plurality of control gate electrodes arranged in a first direction, the first direction intersecting a surface of a substrate;
a first semiconductor layer extending in the first direction and facing side surfaces of the plurality of the control gate electrodes in a second direction, the second direction intersecting the first direction; and
a gate insulating layer provided between the control gate electrode and the first semiconductor layer,
the first semiconductor layer including:
a first portion extending from an end section on a substrate side of the first semiconductor layer to a central region in the first direction of the first semiconductor layer; and
a second portion positioned further from the substrate than the first portion of the first semiconductor layer, and
the first portion having a first crystal plane orientation; and
the second portion having a second crystal plane orientation which is different from the first crystal plane orientation.

US Pat. No. 10,367,053

APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT

Micron Technology, Inc., ...

1. An apparatus comprising:a transistor area comprising at least one n-channel transistor and at least one p-channel transistor, the at least one n-channel transistor and the at least one p-channel transistor being disposed relative to each other in a first direction;
a resistor area comprising at least one resistor, the resistor area being disposed relative to the transistor area in a second direction, the second direction crossing the first direction; and
a delay circuit comprising a logic circuit and the at least one resistor coupled to the logic circuit, wherein the at least one resistor is disposed relative to the logic circuit in the second direction crossing the first direction;
wherein the logic circuit is between the at least one n-channel transistor and the at least one p-channel transistor in the first direction, and wherein the at least one resistor extending in the first direction greater than a size of the logic circuit.

US Pat. No. 10,367,052

DISPLAY PANEL AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A display panel, comprising:a substrate;
a display region, and a non-display region surrounding the display region, wherein the display region is divided into a first display region and at least one second display region smaller than the first display region;
a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer which are sequentially arranged in a direction away from the substrate;
a plurality of gate lines extending in a first direction and arranged in a second direction, a plurality of data lines arranged in the first direction and extending in the second direction, and a plurality of power supply lines arranged in the first direction and extending in the second direction, which are arranged above the substrate, wherein the first direction intersects the second direction, the plurality of gate lines is located on the first metal layer, the plurality of data lines and the plurality of power supply lines are located on the second metal layer, the plurality of gate lines comprises first gate lines and second gate lines shorter than the first gate lines, the plurality of data lines comprises first data lines and second data lines shorter than the first data lines, the first gate lines are located in the first display region, the second gate lines are located in the second display region; and
a plurality of compensation lines and to-be-compensated lines located in the display region, wherein each of the to-be-compensated lines is one of the second gate lines or one of the second data lines, and the plurality of compensation lines is located on the third metal layer, wherein
each of the plurality of compensation lines is electronically connected with one of the to-be-compensated lines, an orthographic projection of the compensation line on the substrate is overlapped with an orthographic projection of one of the plurality of power supply lines on the substrate, and a capacitance is formed between the compensation line and the power supply line; or
each of the plurality of compensation lines is electronically connected with one of the plurality of power supply lines, an orthographic projection of the compensation line on the substrate is overlapped with an orthographic projection of one of the to-be-compensated lines on the substrate, and a capacitance is formed between the compensation line and the to-be-compensated line.

US Pat. No. 10,367,051

ACTIVE-MATRIX DISPLAY DEVICE

JOLED INC., Tokyo (JP)

1. An active-matrix display device, comprising:a pixel matrix that includes a plurality of pixel cells arranged in rows and columns;
a first global power supply wire that is disposed for each of the columns in the pixel matrix and is connected to each of the plurality of pixel cells in the column; and
a second global power supply wire that is disposed for each of the columns in the pixel matrix and is connected to each of the plurality of pixel cells in the column,
wherein each of the plurality of pixel cells includes a first local power supply wire that is directly connected to the first global power supply wire,
each of the plurality of pixel cells includes a second local power supply wire that is directly connected to the second global power supply wire,
all of the plurality of pixel cells in each column are connected to both the first global power supply wire and the second global power supply wire, and
the first local power supply wire does not overlap the second global power supply wire in a plan view of the pixel matrix.

US Pat. No. 10,367,050

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel including a display area in which an image is displayed and a first non-display area in which a pad portion is located,
wherein the display panel includes:
a main area that is substantially flat, the main area including a front surface and a rear surface;
a first bending portion in the display area, the first bending portion being bent at a first curvature radius; and
a second bending portion in the first non-display area between the first bending portion and the pad portion, the second bending portion being bent at a second curvature radius that is smaller than the first curvature radius;
a first area between the first bending portion and the second bending portion; and
a second area outside the second bending portion in the first non-display area, the second area extending from the second bending portion in an extending direction that points toward the rear surface of the main area.

US Pat. No. 10,367,048

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Japan Display Inc., Mina...

1. A display device comprising:a first insulating substrate including a display area and a drive area;
an emitting layer in the display area;
a protective film covering the emitting layer;
a resin base at a position upper than the protective film;
a first adhesive layer under the resin base, in the display area and the drive area;
a second adhesive layer on the resin base; and
a polarizer provided at a position upper than the resin base,
the second adhesive layer covering the drive area and an end portion of the resin base,
the resin base being located between the first adhesive layer and the second adhesive layer in the drive area,
wherein
the resin base is a light transmitting film,
a third adhesive layer is located between the polarizer and the light transmitting film,
the drive area includes a first side connected to the emitting layer and a second side connected to a drive component driving the emitting layer, and
an end portion of the light transmitting film is located more closely to the second side than an end portion of the polarizer.

US Pat. No. 10,367,046

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. An organic light-emitting display device comprising:a thin-film transistor and a metal line disposed on a substrate;
a planarization layer having a pixel contact hole configured to expose the thin-film transistor;
an organic light-emitting element disposed on the planarization layer, the organic light-emitting element including an anode electrode, a cathode electrode and a first organic light-emitting layer;
a first protrusion spaced apart from the anode electrode of the organic light-emitting element and configured to protrude from the planarization layer toward the cathode electrode of the organic light-emitting element, the first protrusion has a side surface angle different in size from a side surface angle of a side surface of the planarization layer that is exposed through the pixel contact hole; and
an auxiliary connection electrode disposed on the first protrusion and connected to the cathode electrode and connected to the metal line through an auxiliary contact hole within the planarization layer,
wherein the first protrusion is disposed on the metal line.

US Pat. No. 10,367,042

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a plurality of organic emitting elements;
an element substrate which has a first surface including a display region on which the plurality of organic elements are arranged, the first surface including a peripheral region surrounding the display region;
an IC chip;
a thermal dispersion film on a second surface of the element substrate, the second surface being opposite to the first surface; and
a metal film on the second surface, wherein
in plan view, the element substrate has a first side, a second side, a third side facing the first side, and a fourth side facing the second side, a first length of each of the first and third sides is longer than a second length of each of the second and fourth sides,
the thermal dispersion film overlaps the IC chip in plan view,
the metal film overlaps the display region, and
a first plane area of the thermal dispersion film is smaller than a second plane area of the metal film.

US Pat. No. 10,367,040

DISPLAY PANEL HAVING FORCE SENSING FUNCTION

HON HAI PRECISION INDUSTR...

1. A display panel comprising:a substrate;
at least one thin film transistor (TFT) on the substrate; and
a force sensor configured to detect touch force on the display panel;
wherein the force sensor comprises a first conductive layer on the substrate and a second conductive layer; wherein the first conductive layer is located between the at least one TFT and the substrate; the second conductive layer is located at a side of the substrate away from the at least one TFT.

US Pat. No. 10,367,038

ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT-EMITTING DIODE DISPLAY

Shenzhen China Star Optoe...

1. A manufacturing method of organic light-emitting diode display device, wherein comprises:arranging a color conversion layer on the substrate by wet film formation; arranging a thin film transistor array, an anode, a hole injection layer and a hole transport layer, a blue light emitting layer, an electron transport layer, an electron injection layer, and a cathode, sequentially;
wherein the color conversion layer comprises red light conversion units, green light conversion units, and opening units which are arranged separately; the red light conversion unit and the green light conversion unit are both film layers made of an organometallic halide perovskite material; the red light conversion unit and the green light conversion unit absorb respectively blue light emitted from the blue light emitting layer and convert the blue light into red light and green light, and the opening unit transmits the blue light to achieve color display;
wherein the organometallic halide perovskite material is a single material containing an organometallic halide perovskite material or a mixed material containing a plurality of organometallic halide perovskite materials; and
wherein the organometallic halide perovskite material has the structural formula CH3NH3PbA3, wherein A is at least one element of chlorine, bromine, and iodine.

US Pat. No. 10,367,035

ELECTROOPTICAL DEVICE, ELECTRONIC APPARATUS, AND HEAD MOUNT DISPLAY

SEIKO EPSON CORPORATION, ...

1. An electrooptical device comprising:a first pixel including a first sub-pixel, a first region, a second sub-pixel and a second region, which are arranged in a first direction in an order of the first sub-pixel, the first region, the second sub-pixel and the second region; and
a second pixel, different from the first pixel, including a third sub-pixel, a third region, a fourth sub-pixel and a fourth region, which are arranged in the first direction in an order of the third sub-pixel, the third region, the fourth sub-pixel and the fourth region, wherein:
the first sub-pixel and the second sub-pixel have different colors from each other;
the third sub-pixel and the fourth sub-pixel have different colors from each other;
the first region is a pixel contact region of the first sub-pixel;
the second region is a pixel contact region of the second sub-pixel;
the third region is a pixel contact region of the third sub-pixel;
the fourth region is a pixel contact region of the fourth sub-pixel;
the first region, the second region, the third region, and the fourth region have a same length in the first direction; and
the first pixel includes a fifth sub-pixel having a length different from lengths of the first and second sub-pixels in the first direction.

US Pat. No. 10,367,034

LUMINAIRE UTILIZING A TRANSPARENT ORGANIC LIGHT EMITTING DEVICE DISPLAY

ABL IP HOLDING LLC, Cony...

1. A transparent display panel, comprising:(a) an array of display pixels configured on a same substrate, wherein the array has horizontal and vertical dimensions on the substrate and each respective display pixel of the array comprises:
a plurality of separately controllable organic light emitting diodes (OLEDs), each of the OLEDs configured one upon another to form an OLED stack on the substrate, wherein each separately controllable OLED is constructed to emit visible light of a different respective one of three colors,
a first of the plurality of OLEDs being stacked on a light emitting surface of a second of the plurality of OLEDs and the second of plurality of OLEDs being stacked on a light emitting surface of a third of the plurality of OLEDs so that: light from a light emitting surface of the third OLED passes through the second and first OLEDs, light from a light emitting surface of the second OLED passes through the first OLED, and light emerging from a light emitting surface of the first OLED includes light emitted by the first OLED as well as light emitted by the second and third OLEDs; and
(b) a transparent region on the substrate adjacent to the OLED stack of the respective display pixel, wherein the transparent region is configured horizontally and vertically on the substrate in-between the OLED stack of the respective display pixel and the OLED stack of at least another adjacent display pixel in the array, and is formed from a transparent material.

US Pat. No. 10,367,033

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Micron Technology, Inc., ...

1. A method, comprising:forming a first conductive line and a second conductive line extending in a first direction, the first conductive line and the second conductive line separated by a space;
covering, with a liner material, sidewalls of the first conductive line and the second conductive line and a surface extending between the sidewalls;
depositing a dielectric material over the liner material, wherein a first sidewall and a second sidewall of the dielectric material are in contact with the liner material; and
forming a pillar of a memory cell stack on the first conductive line or the second conductive line after depositing the dielectric material.

US Pat. No. 10,367,030

PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE

CANON KABUSHIKI KAISHA, ...

1. A device comprising:a substrate which is provided with a photoreceiving portion and a transistor including a gate electrode;
a wiring which is arranged above the substrate;
an insulation film which is arranged between the wiring and the substrate, the insulation film having an opening above the photoreceiving portion, the insulation film containing Si and O;
a region which is arranged in the opening, wherein a material of the region is in contact with the insulating film;
a first portion which is arranged between the region and the photoreceiving portion, the first portion containing Si and N; and
a second portion which is arranged between the insulation film and the substrate, the second portion containing Si and N,
wherein a first distance between the region and the substrate through the first portion is smaller than a second distance between the insulation film and the substrate through the second portion, and a difference between the first distance and the second distance is smaller than a thickness of the gate electrode.

US Pat. No. 10,367,029

IMAGE SENSORS HAVING A SEPARATION IMPURITY LAYER

Samsung Electronics Co., ...

1. An image sensor, comprising:a semiconductor layer of a first conductivity;
a separation impurity layer of the first conductivity, the separation impurity layer in the semiconductor layer and defining a photoelectric conversion region and a readout circuit region;
at least one photoelectric conversion layer of a second conductivity, the at least one photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer;
a floating diffusion region of the second conductivity, the floating diffusion region spaced apart from the at least one photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region;
a transfer gate electrode between the at least one photoelectric conversion layer and the floating diffusion region; and
impurity regions of the second conductivity, the impurity regions in the semiconductor layer of the readout circuit region,
wherein in response to the at least one photoelectric conversion layer being integrated with photo charges, the separation impurity layer has a first potential level around the at least one photoelectric conversion layer and a second potential level on a portion between the at least one photoelectric conversion layer and the impurity regions of the readout circuit region, the second potential level being greater than the first potential level.

US Pat. No. 10,367,027

SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A camera module, comprising:a plurality of lenses;
an imaging device, including:
green pixels including a first green pixel and a second green pixel disposed diagonally in a single line,
wherein the first green pixel is disposed between a first red pixel and a second red pixel in a horizontal direction,
wherein the second green pixel is disposed between a first blue pixel and a second blue pixel in the horizontal direction,
wherein a size of the first blue pixel is smaller than a size of the first green pixel,
wherein a size of the second blue pixel is smaller than the size of the first green pixel, andwherein the plurality of lenses focus an incident light on the camera module.

US Pat. No. 10,367,025

SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE DEVICE

Panasonic Intellectual Pr...

1. A solid-state imaging device comprising:a semiconductor region of a first conductivity type; and
unit pixels, each unit pixel including
a photoelectric converter configured to generate charge;
an impurity region of a second conductivity type forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating the charge from the photoelectric converter;
an amplifier transistor including
a gate electrode electrically connected to the impurity region, and
a source region or a drain region of the second conductivity type in the semiconductor region, and
a channel region in the semiconductor region under the gate electrode, and
a width of the channel region being wider than a width of the source region or a width of the drain region in a width direction of the gate electrode; and
a first isolation region, in the semiconductor region, consisting of an impurity doped region of the first conductivity type and surrounding the amplifier transistor, wherein
entirety of the channel region is the second conductivity type, and
the first conductivity type is different from the second conductivity type.

US Pat. No. 10,367,024

SEMICONDUCTOR IMAGE SENSORS HAVING CHANNEL STOP REGIONS AND METHODS OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a light-receiving element which outputs electric charges in response to incident light; and
a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current that is proportional to the incident light, wherein the drive transistor comprises:
a first gate electrode;
a first channel region under the first gate electrode;
first and second source-drain regions which are disposed at respective ends of the first channel region, the first and second source-drain regions having a first conductivity type;
a first channel step region on a first side of the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type; and
a second channel stop region is on a second side of the first channel region that is opposite the first side of the first channel region,
wherein the first channel region includes a first segment under the first gate electrode that extends in a first direction and a second segment under the first gate electrode that extends in a second direction that intersects the first direction, and
wherein a first end of the first segment directly connects to the first source-drain region, a second end of the first segment directly connects to a first end of the second segment and a second end of the second segment directly connects to the second source-drain region.

US Pat. No. 10,367,023

SEMICONDUCTOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor integrated chip, comprising:an image sensing element arranged within a pixel region of a substrate;
a first dielectric disposed in trenches within a first side of the substrate, wherein the trenches are defined by first sidewalls disposed on opposing sides of the pixel region; and
an internal reflection structure arranged along the first side of the substrate and configured to reflect radiation exiting from the substrate back into the substrate, wherein the substrate includes a recessed portion arranged along the first side of the substrate and defined by second sidewalls of the substrate directly over the image sensing element, the second sidewalls of the substrate are angled to intersect at a point disposed along a horizontal plane that intersects the first sidewalls.

US Pat. No. 10,367,022

SOLID-STATE IMAGING DEVICE, MEMBERS FOR THE SAME, AND IMAGING SYSTEM

CANON KABUSHIKI KAISHA, ...

1. A device comprising:a first semiconductor substrate which is provided with a first transistor and a photoelectric conversion element, the first semiconductor substrate having a first face where the first transistor is provided and having a second face on the opposite side of the first face of the first semiconductor substrate;
a first wiring layer which includes a first wiring being connected to the first transistor, the first wiring being made mainly of copper;
a second semiconductor substrate which is provided with a second transistor, the second semiconductor substrate having a first face where the second transistor is provided and having a second face on the opposite side of the first face of the second semiconductor substrate;
a second wiring layer which includes a second wiring being connected to the second transistor, the second wiring being made mainly of copper;
a first layer which includes a pad being in contact with an external terminal, the pad being made mainly of aluminum; and
a second layer which includes a first portion arranged between the pad and the second semiconductor substrate,
wherein the first wiring layer is arranged between the first semiconductor substrate and the second wiring layer,
wherein the first semiconductor substrate has an opening, the second wiring layer includes a second portion arranged between the opening and the second semiconductor substrate, and the pad is electrically connected to the second portion via the first portion, and
wherein a distance between the first layer and the first face of the second semiconductor substrate is smaller than a distance between the second face of the first semiconductor substrate and the first face of the second semiconductor substrate, and is larger than a distance between the first wiring layer and the first face of the second semiconductor substrate.

US Pat. No. 10,367,021

IMAGE SENSOR DEVICE AND FABRICATING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A backside illuminated (BSI) image sensor device, comprising:a substrate having a first side and a second side opposite to the first side;
a photo sensitive element on the first side of the substrate to receive incident light transmitted through the substrate;
a pixel circuit on the first side of the substrate for electrical interconnecting with the photo sensitive element;
a first dielectric layer disposed on the second side of the substrate;
a second dielectric layer directly on the first dielectric layer, wherein a refractive index of the first dielectric layer is greater than a refractive index of the second dielectric layer;
a grid on the second dielectric layer, wherein a sidewall of the grid is coplanar with a sidewall of the second dielectric layer; and
a convex dielectric lens on the first dielectric layer and provided within the second dielectric layer, the convex dielectric lens having a convex side oriented toward the incident light and a planar side oriented toward the photo sensitive element, wherein a bottom of the convex side of the convex dielectric lens is level with a bottom surface of the second dielectric layer and a refractive index of the convex dielectric lens is smaller than the refractive index of the second dielectric layer.

US Pat. No. 10,367,020

POLARIZERS FOR IMAGE SENSOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor image sensor device, comprising:a semiconductor layer comprising one or more sensing regions configured to sense radiation;
a grid structure, over the semiconductor layer, that comprises one or more cells respectively aligned to the one or more sensing regions; and
a polarizing grating structure in the one or more cells of the grid structure, wherein the polarizing grating structure is configured to polarize light incoming to the semiconductor image sensor device and comprises grating elements with an anti-reflective layer disposed on a metal layer.

US Pat. No. 10,367,019

CMOS IMAGE SENSOR STRUCTURE WITH CROSSTALK IMPROVEMENT

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:forming a silicon device layer on a semiconductor substrate, wherein the silicon device layer is configured to generate photoelectrons therein, the silicon device layer has a first surface and a second surface opposite to the first surface, and the first surface is adjacent to the semiconductor substrate;
forming a grid structure in the silicon device layer, wherein the grid structure is formed to comprise a plurality of cavities in the silicon device layer;
forming a plurality of color filters in the cavities such that the plurality of color filters include:
a first color filter that is adjacent an edge of the semiconductor device; and
a second color filter that has substantially the same thickness and the same color as the first color filter; and
forming a passivation layer on the second surface of the silicon device layer and covering the grid structure and the color filters.

US Pat. No. 10,367,018

IMAGE SENSOR AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. An image sensor, comprising:a photosensitive device;
a storage device adjacent to the photosensitive device, comprising:
a storage node;
a gate dielectric layer over the storage node;
a storage gate electrode over the gate dielectric layer;
an etch stop layer covering the gate dielectric layer and the storage gate electrode;
a shielding layer over the storage gate electrode; and
a protection layer sandwiched between the etch stop layer and the shielding layer; and
a driving circuit adjacent to the storage device.

US Pat. No. 10,367,017

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A method of manufacturing an array substrate, comprising the following steps:Step S1: providing a substrate, sequentially forming a light-shielding layer, a buffer layer, an active layer, a source, a drain, a gate insulating layer, and a gate on the substrate, wherein an indium gallium zinc oxide layer and a second metal layer are continuously deposited on the buffer layer using a halftone mask, and, using the halftone mask, the indium gallium zinc oxide layer is formed into the active layer and the second metal layer is formed simultaneously into the source and the drain;
Step S2: performing a first conductorization process on a corresponding region of the active layer opposite to the source and the drain; and
Step S3: performing a second conductorization process on another corresponding region of the active layer between the source and the gate and between the drain and the gate;
wherein locations of projections of the source, the drain, and the active layer on the substrate within a projection of the light-shielding layer on the substrate cause self-aligning of the active layer; and
wherein use of the halftone mask causes the active layer, the source, and the drain to be simultaneously formed.