US Pat. No. 10,770,545

QUANTUM DOT DEVICES

Intel Corporation, Santa...

1. A device, comprising:a quantum well stack of a quantum dot device;
an insulating material above the quantum well stack, wherein the insulating material includes a first trench and a second trench;
a first gate metal on the insulating material and extending into the first trench; and
a second gate metal on the insulating material and extending into the second trench.

US Pat. No. 10,770,544

SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate including a recess, the substrate defining the recess to include a first region, a second region and a third region having different widths;
a stack structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate;
a common source pattern passing through the stack structure to contact the substrate at the first region of the recess; and
an insulating spacer between the stack structure and the common source pattern, the insulating spacer including silicon nitride.

US Pat. No. 10,770,543

SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES

ALPHA AND OMEGA SEMICONDU...

1. A semiconductor chip comprising a high voltage device and a low voltage device disposed thereon, said semiconductor chip further comprising:a substrate layer of a first conductivity type;
a first epitaxial layer of the first conductivity type on a top surface of the substrate layer;
a second epitaxial layer of a second conductivity opposite to the first conductivity type on a top surface of the first epitaxial layer;
a deep buried implant region of the second conductivity type in an area for the high voltage device;
a buried implant region of the second conductivity type in an area for the low voltage device; and
a first doped well of the first conductivity type extending from a top surface of the second epitaxial layer above the deep buried implant region; and a second doped well of the first conductivity type from a top surface of the second epitaxial layer above the buried implant region, wherein the second doped well of the first conductivity type has a greater doping concentration than the first epitaxial layer and substrate.

US Pat. No. 10,770,542

ISOLATION STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE ISOLATION STRUCTURE

MagnaChip Semiconductor, ...

1. A semiconductor device, comprising:a substrate having a top surface;
an isolation structure comprising:
a trench formed in the substrate;
an oxide layer formed on a sidewall of the trench;
a filler formed on the oxide layer to fill a part of inside of the trench; and
an additional oxide layer filling an upper portion of the trench,
a buried layer formed to abut the trench and having a depth shallower than a depth of the trench;
a first well region and a second well region formed on the buried layer, the first well region abutting against the second well region and the first well region having a depth equal to a depth of the second well region;
a third well region formed in the first well region and having a same conductivity type as the first well region;
a drain region formed in the second well region;
a source region formed in the third well region;
a gate insulating layer formed on the first well region and the second well region; and
a gate electrode formed on the gate insulating layer.

US Pat. No. 10,770,541

SEMICONDUCTOR DEVICE INCLUDING SUPER JUNCTION STRUCTURE

Infineon Technologies Aus...

1. A semiconductor device, comprising:transistor cells in a transistor cell area of a semiconductor body;
a super junction structure in the semiconductor body, the super junction structure comprising a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction, wherein each of the drift sub-regions include first dopants of the first conductivity type partially compensated by second dopants of the second conductivity type; and
a termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area,
the termination area comprising first and third termination sub-regions of the first conductivity type, respectively, and a second termination sub-region of the second conductivity type sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body,
wherein the first and the third termination sub-regions merge and fully surround the second termination sub-region.

US Pat. No. 10,770,540

SMALL-GAP COPLANAR TUNABLE CAPACITORS AND METHODS FOR MANUFACTURING THEREOF

NXP USA, Inc., Austin, T...

1. A method for fabricating a coplanar capacitor, the method comprising:depositing a voltage-tunable dielectric layer on a substrate;
depositing a metal layer on the voltage-tunable dielectric layer;
depositing an inter-level dielectric layer on the metal layer;
etching first material from the inter-level dielectric layer and second material from the metal layer to form a plurality of bias lines covered at least partially by respective portions of the inter-level dielectric layer;
depositing an oxide layer on exposed surface portions of the inter-level dielectric layer and on exposed surface portions of the voltage-tunable dielectric layer, wherein the oxide layer that is deposited includes upright portions between the inter-level dielectric layer and the voltage-tunable dielectric layer;
etching third material from the oxide layer to expose portions of the inter-level dielectric layer, to expose portions of the voltage-tunable dielectric layer and to form, from the upright portions, a plurality of sidewall spacers, wherein each of the plurality of sidewall spacers is located adjacent one of the plurality of bias lines, and wherein the etching of the third material from the oxide layer results in exposed portions of the inter-level dielectric layer and exposed portions of the voltage-tunable dielectric layer;
depositing a metallization layer on the exposed portions of the inter-level dielectric layer and on the exposed portions of the voltage-tunable dielectric layer; and
etching fourth material from the metallization layer to form a plurality of RF electrodes.

US Pat. No. 10,770,539

FINGERED CAPACITOR WITH LOW-K AND ULTRA-LOW-K DIELECTRIC LAYERS

NXP B.V., Eindhoven (NL)...

1. An integrated circuit comprising a plurality of fingers forming a fingered capacitor, the fingered capacitor comprising:a first dielectric cap layer;
a first dielectric layer formed over the dielectric cap layer and having a first K value;
a second dielectric layer formed over the first dielectric layer and having a second K value lower than the first K value, wherein the fingers are formed in the first and second dielectric layers;
a second dielectric cap layer formed over the fingers and the second dielectric layer; and
a third dielectric layer formed over the second dielectric layer and the fingers, wherein the second dielectric cap layer is formed over the third dielectric layer.

US Pat. No. 10,770,538

METHOD AND STRUCTURE FOR DUAL SHEET RESISTANCE TRIMMABLE THIN FILM RESISTORS

TEXAS INSTRUMENTS INCORPO...

1. A method of forming an electronic device, comprising:forming an opening through a dielectric layer located over a first resistive layer with a first sheet resistance;
depositing a second resistive layer over said dielectric layer and into said opening, said second resistive layer having a lower second sheet resistance; and
removing a portion of said second resistive layer, thereby forming a first portion of said second resistive layer over said dielectric layer, and a noncontiguous second portion of said second resistive layer in contact with said first resistive layer.

US Pat. No. 10,770,537

METAL RESISTOR STRUCTURES WITH NITROGEN CONTENT

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure, comprising:a first resistor element and at least one additional resistor element disposed on a dielectric layer formed of a first dielectric material including regions of at least one additional dielectric material within the dielectric layer, wherein the first resistor element is on the first dielectric material and the at least one additional resistor element is on the regions of the at least one additional dielectric material, wherein the first dielectric material is different from the at least one additional dielectric material, wherein the first dielectric material has a percentage of nitrogen ions at a penetration depth between 2 percent and 10 percent and the at least one additional dielectric material has a percentage of nitrogen ions at the penetration depth between 0.5 percent and 1.5 percent, wherein the penetration depth is less than about 10 Angstroms, and wherein the first resistor element has a different resistivity than the at least one additional resistor element.

US Pat. No. 10,770,536

FLEXIBLE DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A flexible display apparatus comprising:a flexible substrate comprising a bending area and a non-bending area, the bending area being configured to bend along a bending axis; and
a wiring line extending across the bending area, a portion of the wiring line at the bending area comprising a plurality of first recessed portions and a plurality of second recessed portions, the first and second recessed portions being recessed in a width direction of the wiring line,
wherein the wiring line has a central axis that extends in a second direction, and the plurality of recessed portions are on both sides of the wiring line about the central axis,
wherein the plurality of recessed portions comprise a plurality of first recessed portions that are on one side of the wiring line about the central axis and a plurality of second recessed portions that are on another side of the wiring line about the central axis,
wherein the first recessed portions and the second recessed portions are alternately arranged along the second direction,
wherein the wiring line has a first width, the first width being a greatest width of the wiring line, and a recessed depth of each of the plurality of recessed portions is less than half the first width, and
wherein the recessed portions do not cross the central axis of the wiring line.

US Pat. No. 10,770,535

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a substrate including a display area and a non-display area;
a plurality of pixels in the display area of the substrate;
data lines for supplying a data signal to the pixels and extending in a first direction; and
a first dummy part in the non-display area and adjacent to an outermost pixel located at an outermost side of the display area from among the plurality of pixels,
wherein the first dummy part comprises a first dummy data line and a dummy power pattern extending in parallel to the data lines.

US Pat. No. 10,770,534

ACTIVE MATRIX ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL

Wuhan China Star Optoelec...

1. An active matrix organic light-emitting diode display panel, comprising:a first metal layer and an interlayer dielectric layer sequentially disposed on a substrate; wherein a first via hole is defined in the interlayer dielectric layer, and the first metal layer is connected to a portion of a second metal layer through the first via hole;
the second metal layer covering the first via hole;
a planarization layer located on the second metal layer, and a second via hole defined the planarization layer; and
a transparent conductive layer covering the second via hole and located on a portion of the planarization layer, the transparent conductive layer connected to the second metal layer through the second via hole; wherein a contact surface of the second metal layer and the transparent conductive layer is a waved surface.

US Pat. No. 10,770,533

ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL HAVING PADS DISPOSED AT DIFFERENT DISTANCES FROM AN EDGE AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME

LG Display Co., Ltd., Se...

1. An organic light emitting diode display panel, comprising:a plurality of data lines arranged in a first direction;
a plurality of gate lines arranged in a second direction to cross the data lines, a plurality of pixel areas being defined by the crossed data lines and gate lines;
at least one driving voltage line arranged in the first direction;
at least one reference voltage line arranged in the first direction;
a plurality of data pads respectively disposed at ends of corresponding ones of the data lines;
a driving voltage pad disposed at an end of the driving voltage line; and
a reference voltage pad disposed at an end of the reference voltage line,
wherein each of the data pads, the driving voltage pad, and the reference voltage pad are disposed in a non-active area of the display panel adjacent to an edge of the display panel and outside of the pixel areas,
wherein a first distance from the edge of the display panel to the data pads is different than a second distance from the edge of the display panel to the driving voltage pad, and
wherein the first distance from the edge of the display panel to the data pads is different than a third distance from the edge of the display panel to the reference voltage pad.

US Pat. No. 10,770,532

DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising a substrate and a plurality of pixel units on the substrate, at least one of the plurality of pixel units comprising a light-emitting unit, a photosensitive unit for detecting light emitted by the light-emitting unit, and an interlayer insulating layer between the photosensitive unit and the light-emitting unit,wherein the interlayer insulating layer comprises a groove, an orthogonal projection of the groove on the substrate does not coincide with an orthogonal projection of the photosensitive unit on the substrate, and the light-emitting unit covers the groove;
wherein the photosensitive unit comprises a photodiode;
wherein the photodiode comprises an N-type doped semiconductor layer and a P-type doped semiconductor layer sequentially arranged on the substrate; wherein
the P-type doped semiconductor layer is electrically connected to a reverse bias voltage signal line;
a side of the photodiode proximate to the reverse bias voltage signal line connected to the P-type doped semiconductor layer is a connection side; and a contour of the orthogonal projection of the groove on the substrate is adjacent to a contour of an orthogonal projection of a portion of the photodiode other than the connection side on the substrate, and
a plurality of scanning lines, a plurality of reverse bias voltage signal lines and a plurality of signal reading lines, the plurality of scanning lines and the plurality of reverse bias voltage signal lines crossing to define the plurality of pixel units, and each of the plurality of pixel units further comprising a switching transistor; wherein
control electrodes of the switching transistors located in a same row are connected to a same scanning line; first electrodes of the switching transistors located in a same column are connected to a same signal reading line; second electrodes of the switching transistor in each of the pixel units are connected to the N-type doped semiconductor layer of the photodiode; and
the P-type doped semiconductor layer of the photodiode located in a same column are connected to a same reverse bias voltage signal line.

US Pat. No. 10,770,530

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:a reflective electrode in a pixel region on a substrate, and including a concave portion defining a concave furrow;
a first filling pattern filling the concave furrow;
a first electrode on the first filling pattern and on a portion of the reflective electrode around the first filling pattern;
an organic light emitting layer on the first electrode;
a second electrode on the organic light emitting layer;
a bank disposed on a boundary of the pixel region;
a passivation layer provided below the reflective electrode, the passivation layer including a concave surface on which the concave portion of the reflective electrode is formed; and
a second filling pattern filling a drain contact hole of the passivation layer,
wherein the bank overlaps with an edge portion of the concave furrow of the reflective electrode,
wherein a drain electrode of a thin film transistor in the pixel region and the reflective electrode are electrically connected with each other through the drain contact hole, and
wherein the second filling pattern is surrounded by the drain electrode, a portion of the reflective electrode and a portion of the first electrode which contacts the portion of the reflective electrode.

US Pat. No. 10,770,529

LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND CELLULAR PHONE

Semiconductor Energy Labo...

1. A display device comprising:a first insulating film;
a transistor formed over a first side of the first insulating film;
a second insulating film over the transistor;
an electrode over the second insulating film and electrically connected to the transistor through a first opening of the second insulating film, wherein a portion of the electrode is formed in a second opening of the second insulating film and an opening of the first insulating film; and
a display element located at a second side of the first insulating film opposite to the first side, wherein an electrode of the display element is electrically connected to the transistor through the electrode.

US Pat. No. 10,770,528

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light emitting display device comprising:a substrate on which a plurality of sub-pixels are arranged in a column direction and a row direction;
a plurality of first electrodes respectively allocated to the plurality of sub-pixels;
a first bank disposed between the plurality of first electrodes neighboring in the column direction and having a plurality of first openings that exposes the plurality of first electrodes arranged in the row direction;
a second bank disposed between the plurality of first electrodes neighboring in the row direction and having a plurality of second openings that exposes the plurality of first electrodes arranged in the column direction,
wherein each of the plurality of first electrodes includes a head portion having a first width in the row direction and a neck portion having a second width less than the first width and extending from one side of the head portion in the column direction,
wherein the head portion of the first electrodes arranged in an odd column neighbors the neck portion of the first electrodes arranged in an even column along the row direction, and
wherein the neck portion of the first electrodes arranged in an odd column neighbors the head portion of the first electrodes arranged in an even column along the row direction.

US Pat. No. 10,770,527

DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display CO., Ltd....

1. A display panel, comprising:a substrate including a circuit layer;
an insulation layer on the substrate, the insulation layer defining a hole;
a first electrode on the insulation layer, the first electrode being electrically connected to the circuit layer in the hole;
a light absorbing layer on the first electrode and overlapping the hole;
a pixel defining layer on the insulation layer and defining an opening through which a top surface of the first electrode is exposed;
at least one organic layer including a light emitting layer in the opening; and
a second electrode on the at least one organic layer.

US Pat. No. 10,770,526

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a circuit layer;
a first electrode on the substrate;
a first pixel defining layer on the substrate and having an opening exposing an upper surface of the first electrode;
a second pixel defining layer on the first pixel defining layer and comprising an amphipathic material;
an organic layer on the first electrode, an upper surface of the organic layer being below a bottom surface of the second pixel defining layer with respect to the substrate; and
a second electrode on the organic layer.

US Pat. No. 10,770,525

ORGANIC LIGHT-EMITTING DISPLAY PANEL, DISPLAY DEVICE, AND FABRICATION METHOD THEREOF

SHANGHAI TIANMA MICRO-ELE...

1. An organic light-emitting display panel, divided into a display region and a non-display region surrounding the display region, and comprising:a substrate;
an array layer formed over the substrate;
a pixel defining layer formed on a surface of the array layer away from the substrate;
a plurality of organic light-emitting devices formed in a plurality of openings of the pixel defining layer, wherein the plurality of organic light-emitting devices are disposed in the display region, and each organic light-emitting device includes an anode, an organic light-emitting layer, and a cathode sequentially formed on the substrate in a direction away from the substrate;
a plurality of support units disposed in the non-display region, wherein at least one support unit of the plurality of support units is disposed on a surface of the pixel defining layer away from the substrate,
wherein:
in the non-display region, the pixel defining layer includes a plurality of island structures isolated from each other, and at least one support unit of the support units is disposed on the plurality of island structures.

US Pat. No. 10,770,524

ORGANIC LIGHT-EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light-emitting display device comprising:pixels:
a bank that defines the pixels and has at least one hollow portion formed between the pixels which neighbor each other;
a light stopper that blocks or absorbs light incident on the light stopper, at least part of which is inserted into the at least one hollow portion; and
a barrier surrounding the light stopper,
wherein the barrier is divided into a first portion and a second portion, and
wherein the first portion and the second portion are made of different materials.

US Pat. No. 10,770,523

DISPLAY DEVICE INCLUDING A LAYER WITH FINE HOLES AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device, comprising:a base;
a bank on the base and including an opening exposing a surface of the base; and
an organic film pattern in the opening on the base, wherein the bank includes side surfaces adjacent to an upper surface, the side surfaces sloping downward from the upper surface toward the opening, and wherein the bank includes a plurality of fine holes on the upper surface and the side surfaces and a plurality of inner holes in the bank,
wherein the plurality of fine holes are spaced from each other, and
wherein at least some of the fine holes from among the plurality of fine holes have a smaller diameter at an entrance thereof than a maximum diameter thereof, and at least some others of the fine holes from among the plurality of fine holes have a diameter at the entrance thereof that is equal to the maximum diameter thereof.

US Pat. No. 10,770,522

EL DEVICE, MANUFACTURING METHOD FOR EL DEVICE, AND MANUFACTURING APPARATUS FOR EL DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An EL device comprising:a display panel configured to display an image on a display area in a display surface; and
an imaging element arranged on a side of a surface opposite to the display surface, the imaging element being configured to image a subject on a side of the display surface,
wherein the display panel includes
a panel substrate in which a plurality of scanning signal lines and a plurality of data signal lines intersecting with the plurality of scanning signal lines are formed, and
an EL layer formed on the panel substrate, the EL layer being configured to display the image based on scanning signals from the plurality of scanning signal lines and data signals from the plurality of data signal lines, and
an imaging hole formed in the display area straddles the plurality of scanning signal lines and the plurality of data signal lines in a case of being viewed from a direction perpendicular to the display surface, the imaging hole being configured to guide light from the subject to the imaging element.

US Pat. No. 10,770,521

DISPLAY PANEL, DISPLAY AND DISPLAYING METHOD

BOE TECHMOLOGY GROUP CO.,...

1. A display panel comprising:a first base substrate and a second base substrate arranged to be opposite to each other;
a liquid crystal layer configured between the first base substrate and the second base substrate; and
a light emitting device layer at a side of the first base substrate facing towards the second base substrate; and
a grating layer between the light emitting device layer and the liquid crystal layer;
wherein the grating layer comprises a plurality of light blocking portions and a plurality of light transmitting portions alternatingly arranged therein, the light blocking portions being reflective;
wherein the display panel further comprises a light converting layer provided on each of the light blocking portions, wherein the light emitting device layer, the grating layer and the light converting layer are arranged in order in a direction from the first base substrate to the second base substrate; and
wherein a second insulating layer and a second electrode layer are provided between the grating layer and the light converting layer, wherein the second electrode layer comprises a plurality of second sub electrodes, the light converting layer comprises a plurality of light converting units, an orthographic projection of each of the light converting units onto the first base substrate being of superposition with an orthographic projection of a corresponding one of the second sub electrodes onto the first base substrate, and the orthographic projection of each of the light converting units onto the first base substrate is within an orthographic projection of a corresponding one of the light blocking portions on the first base substrate.

US Pat. No. 10,770,520

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. Display device comprising:a light emitting device in an active region of a substrate;
an encapsulation layer on the light emitting device;
a touch sensor on the encapsulation;
a touch pad connected to the touch sensor in a pad part of the substrate;
a routing structure connected to the touch sensor; and
at least one seal material between the active region and the pad part,
wherein the touch sensor includes a plurality of a first and a second touch electrodes which cross each other in the active region, at least one bridge pattern electrically connected to the first touch electrodes,
wherein at least one the first and second touch electrodes includes metal mesh patterns, and
wherein the touch pad is in contact with at least one insulating layer on the substrate, in a peripheral region at an outside region of the active region.

US Pat. No. 10,770,519

ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND ORGANIC LIGHT-EMITTING DIODE DISPLAY APPARATUS

Wuhan China Star Optoelec...

1. An organic light-emitting diode display panel, comprising:a base substrate;
an array structure layer;
an organic light-emitting layer;
a thin film packaging layer, wherein the array structure layer, the organic light-emitting layer, and the thin film packaging layer are sequentially arranged on the base substrate;
a touch screen layer and a polarizer layer, wherein at least one of the touch screen layer and the polarizer layer is located in the thin film packaging layer;
wherein the touch screen layer and the polarizer layer are formed of an inorganic material;
wherein the thin film packaging layer further comprises:
a plurality of inorganic material layers,
a plurality of organic material layers,
an inorganic layer made of an inorganic material, and
an organic layer made of an organic material;
wherein
the inorganic layer and the organic layer are alternately arranged;
the inorganic layer comprises at least one of the touch screen layer and the polarizer layer, and comprises the plurality of inorganic material layers;
the organic layer comprises the plurality of organic material layers.

US Pat. No. 10,770,518

OLED-INTEGRATED TOUCH SENSOR AND OLED DISPLAY DEVICE INCLUDING THE SAME

DONGWOO FINE-CHEM CO., LT...

1. An organic light emitting diode (OLED)-integrated touch sensor, comprising:an organic light emitting diode (OLED) device; and
a touch electrode on a surface of the OLED device, the touch electrode including a driving electrode formed on one surface of a base layer and a receiving electrode formed on an opposing surface of the base layer relative to the one surface,
wherein the touch electrode is combined with the OLED device such that the driving electrode faces the surface of the OLED device;
the OLED device includes a display region and a non-display region, and the touch electrode is formed on at least one of the display region and the non-display region; and
the OLED device includes an anode, an organic layer including an organic emitting layer, a cathode, an encapsulation layer and a planarization layer which are sequentially formed, and the planarization layer includes a refractive index matching layer.

US Pat. No. 10,770,517

FOLDABLE DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a flexible display module configured to display an image on a display surface, the flexible display module comprising:
a display panel comprising a light-emitting device; and
a sensor unit disposed on the display panel,
wherein the sensor unit comprises a plurality of sensors, each of the plurality of sensors comprising a first sensor and a second sensor,
wherein, in a folded-in mode in which the flexible display module is folded along a bending axis, a portion of the display surface faces another portion of the display surface,
wherein, in the folded-in mode, the first and second sensors overlap with each other and are capacitively coupled to each other,
wherein the display device is configured to sense a first pressure applied to the flexible display module in the folded-in mode based on a first capacitance between the first and second sensors facing each other,
wherein the first and second sensors are configured to sense a touch of a user in a normal mode, and
wherein the display device is configured to determine a magnitude of the first pressure applied to the flexible display module in the folded-in mode based on the first capacitance.

US Pat. No. 10,770,516

SELF-LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A self-light emitting display device, comprising:at least one pixel, each pixel including first, second and third regions adjacent to one another;
blue walls spaced apart from each other, dividing the first, second and third regions and configured to reflect and scatter blue light;
a blue light-emitting layer configured to output the blue light and including a first blue light-emitting unit disposed between the blue walls in the first region, a second blue light-emitting unit disposed between the blue walls in the second region and a third blue light-emitting unit disposed between the blue wall in the third region;
a color conversion layer disposed over the blue light-emitting layer and including a green conversion unit disposed between the blue walls in the first region and configured to convert the blue light into green light, and a red conversion unit disposed between the blue walls in the second region and configured to convert the blue light into red light; and
a white resin layer disposed between the blue walls in the third region and configured to transmit the blue light.

US Pat. No. 10,770,515

DISPLAY DEVICE INCLUDING COLOR FILTERS

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a plurality of pixels including a first pixel, a second pixel and a third pixel, wherein each of the first to third pixels includes:
a thin film transistor layer disposed on a first substrate,
a first electrode connected to the thin film transistor layer,
an organic light emitting layer disposed on the first electrode, and
a second electrode disposed on the organic light emitting layer;
an encapsulation film disposed on the second electrode and covering the second electrode;
a color filter layer disposed on the encapsulation film, wherein the color filter layer includes:
a first color filter overlapping the first and second pixels,
a second color filter overlapping the first and third pixels,
a third color filter overlapping the second and third pixels, and
an overcoat layer disposed on the first, second and third color filters;
a second substrate disposed on the overcoat layer;
a bank disposed between two adjacent pixels among the first, second and third pixels; and
a protrusion including overlapping portions of the first, second and third color filters, the protrusion extending away from the encapsulation film in a direction toward the overcoat layer,
wherein the encapsulation film contacts at least two of the first, second and third color filters,
wherein a center of the protrusion overlaps with the bank and the thin film transistor,
wherein the bank is disposed between the protrusion and the thin film transistor, and
wherein a gate electrode of the thin film transistor overlaps with both of the bank and the protrusion.

US Pat. No. 10,770,514

DISPLAY PANEL, DISPLAY METHOD AND DISPLAY DEVICE

Shanghai Tianma Micro-Ele...

1. A display panel, comprising:a substrate;
a display function layer disposed on one side of the substrate, and wherein the display function layer comprises a plurality of sub-pixels; and
at least two image motion units, disposed on a light-emitting side of the display panel and sequentially arranged in a direction perpendicular to a plane where the substrate is located;
wherein a frame unit is used for the display panel to display a display picture, and the frame unit comprises at least three subframes: wherein when the display picture of the display panel is switched from a current subframe to a next subframe, the at least two image motion units are configured to move an outgoing position of an outgoing light of at least one of the plurality of sub-pixels to an outgoing position of another sub-pixel emitting a different color of light at the current subframe.

US Pat. No. 10,770,513

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first transistor;
a first electrode, which is electrically connected to the first transistor;
a second electrode, which overlaps the first electrode;
a first intermediate layer, which is positioned between the first electrode and the second electrode, wherein a first electric field generated by the first electrode with the second electrode causes the first intermediate layer to emit first light;
a first changeable layer, which overlaps the first electrode, wherein the first electric field generated by the first electrode with the second electrode causes the first changeable layer to change from having a second transmittance value to having a first transmittance value, wherein the second transmittance value is unequal to the first transmittance value;
a second transistor, wherein no intervening transistor is positioned between the first transistor and the second transistor;
a third electrode, which is electrically connected to the second transistor;
a second intermediate layer, which is positioned between the third electrode and the second electrode and is configured to emit second light when the third electrode and the second electrode generate a second electric field; and
a second changeable layer, which overlaps the third electrode, is configured to have the first transmittance value when the third electrode and the second electrode generate the second electric field, and is configured to have the second transmittance value when the third electrode and the second electrode do not generate the second electric field.

US Pat. No. 10,770,512

STACKED RESISTIVE RANDOM ACCESS MEMORY WITH INTEGRATED ACCESS TRANSISTOR AND HIGH DENSITY LAYOUT

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a stacked resistive random access memory (ReRAM) structure, the method comprising:forming a channel;
layering a ReRAM cell sub-structure comprising ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel; and
building a contact via sub-structure comprising first, second, third and fourth contact vias, which are separate from one another, the first contact via being disposed in exclusive operative contact with the ReRAM cell layer, the second contact via being disposed in exclusive operative contact with the drain layer, the third contact via being disposed in exclusive operative contact with the gate layer, and the fourth contact via being disposed in exclusive operative contact with the source layer.

US Pat. No. 10,770,511

STRUCTURES AND METHODS FOR EMBEDDED MAGNETIC RANDOM ACCESS MEMORY (MRAM) FABRICATION

International Business Ma...

1. A magnetic random access memory (MRAM) device, comprising:at least one conductor disposed in an insulating material of a lower wiring layer;
a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer; and
a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the at least one conductor to a height above the intermediary wiring layer and traversing multiple wiring layers in addition to the intermediary wiring layer, wherein the landing pad directly contacts the MTJ and connects the MTJ structure to the at least one conductor.

US Pat. No. 10,770,510

DUAL THRESHOLD VOLTAGE DEVICES HAVING A FIRST TRANSISTOR AND A SECOND TRANSISTOR

SPIN MEMORY, INC., Fremo...

1. A device comprising:a core;
a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer, wherein:
the core, the first layer, and the second layer correspond to a first transistor;
the second layer, the third layer, and the fourth layer correspond to a second transistor; and
the second layer is a common channel;
a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage;
a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage;
a common source terminal coupled to the core and the fourth layer; and
a cylindrical source contact coupled to the common source terminal.

US Pat. No. 10,770,509

MAGNETIC STORAGE DEVICE RADIATING HEAT FROM SELECTOR

TOSHIBA MEMORY CORPORATIO...

1. A magnetic storage device comprising:a first memory cell including a magnetoresistive effect element, a selector, and a first barrier material disposed between the selector and the magnetoresistive effect element,
wherein the first barrier material has a thermal conductivity between 1 W/mK and 5 W/mK, inclusive,
wherein the first memory cell further includes a second barrier material disposed so that the selector is placed between the first barrier material and the second barrier material, and
wherein the second barrier material has a thermal conductivity higher than the thermal conductivity of the first barrier material.

US Pat. No. 10,770,508

ACTUATOR DEVICE

Pi Ceramic GmbH, Lederho...

1. An actuator device, comprising:a main body with a base body and buildup body which extends from the base body in a thickness direction,
a plurality of actuators forming the buildup body, wherein each of the actuators extends in a depth direction and is formed of an actuator body which is made of a piezoelectric or electrostrictive material and comprises actuation electrodes which are disposed at or in the actuator and which are distanced from each other, wherein the actuators are arranged behind each other in the longitudinal direction of the actuator device, wherein an actuation area segment of a recess is formed between each of two neighboring actuators,
wherein the actuators comprise electroconductive actuator connection coatings which are electrically connected to the actuation electrodes of the actuators, wherein the actuator connection coatings, at least in sections, are disposed:
(i) either on a surface of the base body which is oriented in the thickness direction,
(ii) or on an actuator step section of the actuators, wherein the actuator step section joins, in a depth direction, a respective actuator body of the actuators,
wherein between actuator connection coatings of respective two neighboring actuators a respective connection area segment of a respective recess is disposed,
a printed circuit board which extends in the longitudinal direction of the actuator device over at least sections of the actuator connection coatings, wherein the conductive paths of the printed circuit board are in electrical contact with the actuator connection coatings,
wherein in the connection area segment of the respective recess, at least in sections, a connection layer is disposed which is made of a resin reinforcement material, wherein the connection layer, at least in sections, contacts side surfaces which delimit the respective connection area segment and which are opposed to each other, the surface section of the base body, which is oriented in the thickness direction, and the area of the printed circuit board which faces the surface section of the base body, in order to support the printed circuit board in the area of the respective connection area segments of the respective recess and to fix the printed circuit board to the actuator connection coatings.

US Pat. No. 10,770,507

DEVICES AND SYSTEMS INCORPORATING ENERGY HARVESTING COMPONENTS/DEVICES AS AUTONOMOUS ENERGY SOURCES AND AS ENERGY SUPPLEMENTATION, AND METHODS FOR PRODUCING DEVICES AND SYSTEMS INCORPORATING ENERGY HARVESTING COMPONENTS/DEVICES

face international corpor...

1. A method for forming an electrically-powered device structure, comprising:providing at least one electrically-energized device component on a surface of a structure;
providing an energy harvesting component on the surface of the structure by
forming a first conductor layer of a first conductive material on a mounting surface;
surface conditioning a facing surface of the first conductor layer opposite the mounting surface to have a comparatively low work function value; and
arranging a second conductor layer formed of a second conductive material to have a facing surface of the second conductor layer facing the facing surface of the first conductor layer with a gap formed between respective facing surfaces of the first conductor layer and the second conductor layer, the gap being in a range of 100 angstroms or less in thickness in a direction orthogonal to the respective facing surfaces, the facing surface of the second conductor having a work function value at least 1.0 eV higher than the comparatively low work function value of the facing surface of the first conductor layer,
the energy harvesting component having a stacked configuration on the mounting surface totaling less than 100 ?m thick on the mounting surface; and
electrically connecting an energy harvesting component to the at least one electrically-energized device component,
the energy harvesting being configured to generate an electric potential at any temperature above absolute zero for powering the at least one electrically-energized device component.

US Pat. No. 10,770,506

METHOD FOR PRODUCING A LIGHT-EMITTING DIODE DISPLAY AND LIGHT-EMITTING DIODE DISPLAY

OSRAM OLED GMBH, Regensb...

1. A light-emitting diode display having:a carrier having a plurality of transistors, and
a plurality of individual, radiation-active islands,
wherein
each of the islands comprises an inorganic semiconductor layer sequence having at least one active zone,
a mean diameter of the islands, seen in a top view of the carrier, is between 50 nm and 20 ?m inclusive,
a mean height of the inorganic semiconductor layer sequence of the islands is at least 1.5 ?m,
the islands are electrically interconnected with the transistors, wherein each individual island is electrically conductively connected to precisely one transistor, the islands are electrically controllable individually via the transistors, and the individual islands form micro-pixels of the light-emitting display,
regions between neighboring islands are filled with a filling compound,
the filling compound is divided into a plurality of island-like sections, and
regions between neighboring island-like sections of the filling compound are provided with a reflective filling, which is a metallic filling so that the neighboring island-like sections are optically isolated from one another via the reflective filling.

US Pat. No. 10,770,505

PER-PIXEL PERFORMANCE IMPROVEMENT FOR COMBINED VISIBLE AND ULTRAVIOLET IMAGE SENSOR ARRAYS

Intel Corporation, Santa...

1. An image sensor comprising:a silicon substrate;
a first set of photodetectors on the silicon substrate that have a thin layer that is conductive and is disposed over an active area and that generates a static electrical charge over an n-well of the first set of photodetectors to detect ultra-violet light;
a second set of photodetectors on the silicon substrate that do not have the thin layer to detect light that is other than ultra-violet light; and
an optical system to direct visible and infrared light to the first and the second sets of photodetectors.

US Pat. No. 10,770,504

WIDE SPECTRUM OPTICAL SENSOR

Artilux, Inc., Menlo Par...

1. An optical sensor comprising:a semiconductor substrate;
a first gate formed on the semiconductor substrate;
a die supported by the semiconductor substrate;
a first light absorption region formed in the die, wherein the first light absorption region is configured to:
absorb first photons at a first wavelength range; and
generate first photo-carriers from the absorbed first photons;
a bonding layer between the semiconductor substrate and the die, wherein a part of the bonding layer is between the first gate and the die;
a second light absorption region formed in the semiconductor substrate, wherein the second light absorption region is configured to:
absorb second photons at a second wavelength range; and
generate second photo-carriers from the absorbed second photons; and
a first carrier-collection region formed in the semiconductor substrate, wherein the first carrier-collection region is configured to collect a portion of the first photo-carriers and has a polarity; and
a second carrier-collection region formed in the semiconductor substrate, wherein the second carrier-collection region is configured to collect a portion of the second photo-carriers and has a polarity opposite to the polarity of the first carrier-collection region.

US Pat. No. 10,770,503

SOLID-STATE IMAGING ELEMENT AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An imaging device, comprising:a substrate;
a first pixel, including:
a first region of a first photoelectric conversion element, wherein the first photoelectric conversion element is formed in the substrate;
a first region of a second photoelectric conversion element, wherein the second photoelectric conversion element is formed in the substrate; and
a first vertical transistor connected to the first region of the first photoelectric conversion element;
a second pixel including:
a second region of the first photoelectric conversion element;
a second region of the second photoelectric conversion element;
and a second vertical transistor connected to the second region of the first photoelectric conversion element;
a first floating diffusion, wherein the first floating diffusion stores charges from the first and second regions of the first photoelectric conversion element in the first and second pixels;
a photoelectric conversion film disposed below the substrate; and
a first through electrode, wherein the first through electrode extends from a first side of the substrate to a second side of the substrate.

US Pat. No. 10,770,501

BACK SIDE ILLUMINATED IMAGE SENSOR WITH DEEP TRENCH ISOLATION STRUCTURES AND SELF-ALIGNED COLOR FILTERS

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor image sensor device, comprising:forming a plurality of layers over a substrate that includes a plurality of radiation-sensing elements;
etching a plurality of trenches that vertically extend through the plurality of layers and at least partially into the substrate, wherein the trenches interleave horizontally with the radiation-sensing elements;
forming an isolation structure in each of the trenches, wherein the isolation structure includes a light-reflective material;
partially etching a topmost layer of the plurality of layers between the isolation structures to expose segments of the isolation structures, wherein the exposed segments of the isolation structures and a remaining portion of the plurality of layers define a plurality of recesses; and
forming color filters in the recesses.

US Pat. No. 10,770,500

SOLID STATE IMAGING DEVICE FOR REDUCING DARK CURRENT

Sony Corporation, Tokyo ...

1. A light sensing device, comprising:a substrate including a semiconductor layer, the semiconductor layer comprising a light sensing section, a first surface, and a second surface opposite to the first surface, wherein the first surface is at a light incident side of the semiconductor layer;
a wiring layer on the second surface;
a first electrode extending from the first surface of the semiconductor layer through the second surface of the semiconductor layer and a surface of the wiring layer to a wiring line disposed in the wiring layer; and
at least three layers over the first surface, the at least three layers comprising a first layer, a second layer, and a third layer,
wherein the first layer and the third layer are insulating layers, and the second layer comprises a material selected from the group including hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, hafnium nitride, aluminum nitride, hafnium oxide nitride, and aluminum oxide nitride,
wherein the second layer is disposed between the first layer and third layer,
wherein the semiconductor layer includes at least a first photoelectric conversion region, a second photoelectric conversion region, and a pixel separating region extending from the first surface to the second surface,
wherein the pixel separating region is disposed between the first photoelectric conversion region and the second photoelectric conversion region, and
wherein at least one of the first layer, the second layer, and the third layer is disposed over the first photoelectric conversion region and the second photoelectric conversion region.

US Pat. No. 10,770,499

IMAGE SENSOR

Samsung Electronics Co., ...

1. An image sensor, comprising:a substrate having a first surface;
a first device isolation region in the substrate and adjacent to the first surface of the substrate, the first device isolation region defining a unit pixel;
a transfer gate on the first surface of the substrate at an edge of the unit pixel;
a photoelectric conversion part in the substrate and adjacent to a first side surface of the transfer gate;
a floating diffusion region in the substrate and adjacent to a second side surface of the transfer gate, the second side surface opposing the first side surface; and
a first impurity doped region in the substrate and overlapping the transfer gate,
wherein the first device isolation region is spaced apart from the second side surface of the transfer gate,
wherein the substrate and the first device isolation region are doped with impurities having a first conductivity,
wherein a first impurity concentration of the first device isolation region is greater than a second impurity concentration of the substrate,
wherein the first impurity doped region is doped with impurities having the first conductivity, and
wherein a third impurity concentration of the first impurity doped region is greater than the second impurity concentration of the substrate and less than the first impurity concentration of the first device isolation region.

US Pat. No. 10,770,498

IMAGE SENSOR WITH METAL GRIDS AND MANUFACTURING METHOD THEREOF

Semiconductor Manufacturi...

1. A method for manufacturing an image sensor, comprising:providing a substrate structure, comprising:
a substrate having a first surface, wherein the substrate has a second surface facing the first surface and a third surface connecting the first surface and the second surface, an insulating layer is on the third surface, and the substrate structure further includes an interconnect structure under the second surface of the substrate and a bonding pad on the interconnection structure and separated from the third surface;
a plurality of pixels in the substrate;
isolation structures around each of the plurality of pixels; and
an anti-reflective coating on the first surface of the substrate;
forming a mask layer on the substrate structure, the mask layer having openings, wherein
a lateral size of an upper half of the openings is smaller than a lateral size of a lower half of the openings, and
the openings include first openings exposing a portion of the first surface of the substrate structure above the isolation structures;
depositing a metal grid material covering a surface of the mask layer and a bottom of the openings; and
stripping the mask layer for removing a portion of the metal grid material on the top surface of the mask layer, wherein a remaining portion of the metal grid material at the bottom of the openings forms metal grids, wherein:
the openings further include a second opening exposing a portion of the bonding pad and the insulating layer, and
a portion of the metal grid material on the bottom of the second opening is connected with the bonding pad.

US Pat. No. 10,770,497

COLOR FILTER ARRAY, IMAGERS AND SYSTEMS HAVING SAME, AND METHODS OF FABRICATION AND USE THEREOF

Micron Technology, Inc., ...

1. An imager comprising:a pixel cell array formed in a substrate, the pixel cell array having an array of at least first, second and third photosensors; and
a color filter array corresponding to the array of photosensors, and comprising respective shaped layers formed over first, second and third base materials,
wherein at least one of the shaped layers has a top portion with a shape that is different than a further shape of a top portion of another of the shaped layers, wherein the difference in the shape and the further shape is defined at least in part by a different base material and one or more spacing objects formed between adjacent ones of the first, second and third base materials.

US Pat. No. 10,770,496

OPTICAL SENSORS AND METHODS FOR FORMING THE SAME

VISERA TECHNOLOGIES COMPA...

1. An optical sensor, comprising:an optical layer disposed on a substrate;
a light shielding layer disposed on the optical layer, wherein the light shielding layer comprises first openings that partially expose the optical layer;
a polymer material layer fills the first opening, wherein a top surface of the polymer material layer is higher than a top surface of the light shielding layer, wherein the polymer material layer includes a plurality of protruding portions that respectively fill each of the first openings in the light shielding layer, and the plurality of protruding portions of the polymer material layer are disconnected to each other;
an adhesive layer disposed on the light shielding layer and the polymer material layer; and
a surface component disposed on the adhesive layer.

US Pat. No. 10,770,495

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND CAMERA WITH ALTERNATIVELY ARRANGED PIXEL COMBINATIONS

Sony Semiconductor Soluti...

1. An imaging device, comprising:a pixel array including a plurality of sub-arrays, each of the plurality of sub-arrays including four pixels arranged in 2×2 matrix, each of the four pixels including a photodiode and a transfer transistor; and
a plurality of on-chip lenses, wherein
each pixel of a first sub-array of the plurality of sub-arrays and a second sub-array of the plurality of sub-arrays includes a first color filter,
each pixel of a third sub-array of the plurality of sub-arrays includes a second color filter,
each pixel of a fourth sub-array of the plurality of sub-arrays includes a third color filter,
the first sub-array is disposed diagonally to the second sub-array,
the third sub-array is disposed diagonally to the fourth sub-array, and
a first on-chip lens of the plurality of on-chip lenses is arranged at a light-incident side of at least a first pixel of the first sub-array, a second on-chip lens of the plurality of on-chip lenses is arranged at a light-incident side of at least a second pixel of the second sub-array, a third on-chip lens of the plurality of on-chip lenses is arranged at a light-incident side of at least a third pixel of the third sub-array and a fourth on-chip lens of the plurality of on-chip lenses is arranged at a light-incident side of at least a fourth pixel of the fourth sub-array.

US Pat. No. 10,770,494

IMAGING ASSEMBLY, METHOD AND MOLDING MOLD FOR FABRICATING SAME, CAMERA MODULE, AND SMART TERMINAL

Ningbo Sunny Opotech Co.,...

1. An imaging assembly, comprising:a photosensitive element, having a photosensitive area; and
a molded encapsulation portion, formed around the photosensitive area, directly contacting the photosensitive element and completely enclosing the photosensitive element, wherein the molded encapsulation portion has an inclined inner side surface and a top surface higher than the photosensitive area,
wherein a height difference between the top surface of the molded encapsulation portion and the photosensitive area of the photosensitive element is less than or equal to 0.7 mm, and the inclined inner side surface and the top surface have different surface roughnesses.

US Pat. No. 10,770,493

SOLID-STATE IMAGING APPARATUS WITH HIGH HANDLING RELIABILITY AND METHOD FOR MANUFACTURING SOLID-STATE IMAGING APPARATUS

SONY CORPORATION, Tokyo ...

1. A solid-state imaging apparatus, comprising:a substrate having a recess on a surface thereof;
an imaging chip disposed and fixed on an inner bottom surface of the recess; and
a filler filled and solidified in whole of a gap between a side surface of the imaging chip and an inner surface of the recess, wherein
a groove having a substantially constant width is between the side surface of the imaging chip and the inner surface of the recess, and
an expansion portion is in a part of the groove, and
a width of the expansion portion is equal to or larger than the substantially constant width of the groove.

US Pat. No. 10,770,492

CHIP SCALE PACKAGE AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method for forming a semiconductor package, the method comprising:providing a transparent lid;
patterning a first material on the transparent lid;
patterning a second material on the transparent lid; and
coupling a wafer to the transparent lid at the first material and at the second material;
wherein a modulus of the first material is lower than a modulus of the second material.

US Pat. No. 10,770,491

IMAGING DEVICE INCLUDING PHOTOELECTRIC CONVERTER AND CAPACITOR WITH A CAPACITOR AND A SWITCHING ELEMENT CONNECTED IN SERIES BETWEEN A FIRST ELECTRODE OF A PHOTOELECTRIC CONVERTER AND A VOLTAGE SOURCE OR A GROUND

PANASONIC INTELLECTUAL PR...

1. An imaging device comprising:a photoelectric converter that includes a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode;
a first transistor that has a gate connected to the first electrode; and
a first capacitor and a switching element that are connected, in series, between the first electrode and either a voltage source or a ground.

US Pat. No. 10,770,490

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a first substrate; and
a second substrate bonded to the first substrate, wherein the first substrate includes:
a first floating metal formed at a bonding surface between the first substrate and the second substrate;
a first pad formed at the bonding surface and spaced apart from the first floating metal by part of the first substrate; and
a first wiring connected to the first pad,
wherein the second substrate includes:
a second floating metal formed at the bonding surface;
a second pad formed at the bonding surface and spaced apart from the second floating metal by part of the second substrate; and
a second wiring connected to the second pad,
wherein the first pad is bonded to the second floating metal, the first floating metal is bonded to the second floating metal, and the second pad is bonded to the first floating metal,
wherein, in a plan view, the first floating metal overlaps the second floating metal,
wherein, in the plan view, the first pad overlaps the second floating metal, and
wherein, in the plan view, the second pad overlaps the first floating metal.

US Pat. No. 10,770,489

OPTOELECTRONIC DEVICE ARRANGED AS A MULTI-SPECTRAL LIGHT SENSOR HAVING A PHOTODIODE ARRAY WITH ALIGNED LIGHT BLOCKING LAYERS AND N-WELL REGIONS

VISHAY INTERTECHNOLOGY, I...

1. An optoelectronic device, comprising:a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region, each n-well region having an upper surface;
a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the plurality of guide members being disposed over the n+ regions of the plurality of first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being disposed over and substantially covering an entirety of the upper surfaces of the n-well regions of the plurality of first photodiodes; and
a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

US Pat. No. 10,770,488

ACTIVE SWITCH ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

HKC Corporation Limited, ...

1. A method for manufacturing an active switch array substrate, comprising the following steps:providing a substrate;
coating a first metal layer on the substrate;
forming a gate electrode by treating the first metal layer through a first photolithography process;
depositing an amorphous silicon layer on the substrate and the gate electrode;
coating a second metal layer on the amorphous silicon layer;
forming a patterned second metal layer by treating the second metal layer through a second photolithography process;
coating a passivation layer on the patterned second metal layer;
forming a through hole in the passivation layer by treating the passivation layer through a third photolithography process;
coating a light permeability conductive layer on the passivation layer, the light permeability conductive layer passing through the through hole to contact with the patterned second metal layer; and
carrying out a fourth photolithography process to the light permeability conductive layer, the passivation layer, and the patterned second metal layer, to form a channel, a source electrode, and a drain electrode on the light permeability conductive layer, the passivation layer, and the patterned second metal layer, the source electrode and the drain electrode being located at two sides of the channel respectively, wherein the channel is separated from the through hole.

US Pat. No. 10,770,487

METHOD FOR MANUFACTURING LTPS TYPE TFT

Wuhan China Star Optoelec...

1. A method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT), comprising steps of:providing a substrate, and forming a silicon channel layer on the substrate;
forming a first insulating layer on the silicon channel layer;
forming a first gate electrode of the TFT on the first insulating layer;
performing an ion implantation on a portion of the silicon channel layer to form a doped area, wherein the doped area includes a lightly doped area and a heavily doped area, and the heavily doped area includes a first heavily doped area and a second heavily doped area;
forming a second insulating layer, a source/drain electrode, and a third insulating layer on the first gate electrode in sequence;
forming a first contact hole on the LTPS type TFT, wherein the first contact hole exposes a portion of the source/drain electrode and a portion of the first heavily doped area; and
forming a first transparent electrode on the third insulating layer, wherein the first transparent electrode is electrically connected to the portion of the source/drain electrode and the portion of the first heavily doped area via the first contact hole.

US Pat. No. 10,770,486

METHOD OF PRODUCING LIQUID CRYSTAL CELL, AND LIQUID CRYSTAL CELL

SHARP KABUSHIKI KAISHA, ...

1. A method of producing a liquid crystal cell, the method comprising:a thin-film forming step of forming, on a surface of at least one electrode-attached substrate of a pair of electrode-attached substrates including a TFT substrate and a slot substrate, the TFT substrate including a first dielectric substrate, a plurality of TFTs supported on the first dielectric substrate, and a plurality of patch electrodes electrically connected to the TFTs, the slot substrate including a second dielectric substrate and a slot electrode supported on the second dielectric substrate and having a plurality of slots, a thin film so as to cover the patch electrodes and/or the slot electrode; and
a light irradiating step of irradiating the thin film with light including p-polarized light to provide the thin film with alignment-regulating capability of aligning liquid crystal molecules to thereby obtain an alignment film,
wherein the thin film includes a polymer including a photoreactive functional group and exhibiting the alignment-regulating capability of the thin film in a direction orthogonal to a polarization axis of the p-polarized light.

US Pat. No. 10,770,485

ARRAY SUBSTRATE, DISPLAY PANELS AND DISPLAY DEVICES

Shanghai Tianma Micro-Ele...

1. An array substrate, comprising:a base substrate, which comprises a display area and a non-display area surrounding the display area;
an insulating layer located on a side of the base substrate, wherein the insulating layer comprises at least one plateau-shaped protrusion, wherein the plateau-shaped protrusion includes a first surface and a second surface, wherein the first surface and the second surface are arranged opposite to each other along a direction perpendicular to the base substrate, the first surface is located at a side of the second surface opposite to the base substrate, and an area of the first surface is less than an area of the second surface in a direction perpendicular to the base substrate; and
an electrostatic conductive layer located on a side of the insulating layer away from the base substrate, wherein the electrostatic conductive layer comprises a first wire and at least one first discharge tip, the first wire is electrically connected to the first discharge tip, the first discharge tip is located on a side slope of the plateau-shaped protrusion and is located in the non-display area;
wherein the electrostatic conductive layer further comprises an auxiliary discharge structure, the auxiliary discharge structure and the first discharge tip are disposed opposite to each other.

US Pat. No. 10,770,484

THIN FILM TRANSISTOR, A METHOD OF MANUFACTURING THE SAME, AND A DISPLAY APPARATUS INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A method of manufacturing a thin film transistor, the method comprising:forming a semiconductor layer over a substrate;
sequentially forming a gate insulating material layer and a gate electrode material layer on the substrate to cover the semiconductor layer;
forming a first photoresist pattern on the gate electrode material layer;
forming a gate electrode by etching the gate electrode material layer using the first photoresist pattern as a mask;
forming a second photoresist pattern covering both sidewalls and an upper surface of the gate electrode; and
forming a gate insulating film by etching the gate insulating material layer using the second photoresist pattern as a mask, the gate insulating film including a first region and a second region having portions disposed at opposite sides of the first region, and a thickness of the first region is different than a thickness of the portions of the second region,
wherein a portion of the first region and the portions of the second region do not overlap the gate electrode in a thickness direction of the substrate.

US Pat. No. 10,770,483

THIN FILM TRANSISTOR, DISPLAY DEVICE AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR

SAKAI DISPLAY PRODUCTS CO...

14. A method for manufacturing a thin film transistor comprising:a step (A) of providing a substrate including a gate electrode, and a gate insulating layer that covers the gate electrode, wherein the gate electrode and the gate insulating layer are formed an a surface of the substrate;
a step (B) of forming a semiconductor film made of an amorphous oxide semiconductor on the gate insulating layer;
a step (C) of forming an insulating film on the semiconductor film and patterning the insulating film, thereby forming a protection insulating layer that covers a portion of the semiconductor film that is to be a channel region;
a step (D) of irradiating the semiconductor film with laser light from above the protection insulating layer to crystallize a portion of the semiconductor film that is covered by the protection insulating layer and a portion thereof that is not covered by the protection insulating layer so that a crystallinity of the portion of the semiconductor film that is covered by the protection insulating layer is lower than the portion thereof is not covered by the protection insulating layer, in a region that overlaps with the gate electrode as seen from a direction normal to the substrate; and
a step (E) of forming a source electrode electrically connected to a part of the portion of the semiconductor film that is not covered by the protection insulating layer, and a drain electrode electrically connected to another part of the portion of the semiconductor film that is not covered by the protection insulating layer.

US Pat. No. 10,770,482

DISPLAY DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

13. A display device comprising a pixel, the pixel comprising:a first transistor, a second transistor, a third transistor, a first capacitor, a light-emitting element, a fourth transistor, a second capacitor, and a fifth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the first capacitor,
wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are electrically connected to a first wiring,
wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a second wiring,
wherein a gate of the fourth transistor and one electrode of the second capacitor are electrically connected to the other electrode of the first capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and the other electrode of the second capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the light-emitting element, and
wherein the light-emitting element has a tandem structure where two or more light-emitting layers are connected in series.

US Pat. No. 10,770,481

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

NuFlare Technology, Inc.,...

1. A semiconductor device comprising:a silicon substrate having a first plane with a first plane orientation;
a silicon oxide layer provided on a first region of the silicon substrate;
a first silicon layer provided on the silicon oxide layer, the first silicon layer having a second plane with a second plane orientation different from the first plane orientation;
a wide-bandgap compound semiconductor layer having a hexagonal crystal structure; and
a second silicon layer provided on a second region of the silicon substrate, the second region being different from the first region,
wherein the wide-bandgap compound semiconductor layer is provided on the first silicon layer,
the first plane orientation is {100},
the second plane orientation is {111} and,
the first silicon layer is undoped.

US Pat. No. 10,770,480

SYSTEMS, METHODS, AND APPARATUS FOR ENABLING HIGH VOLTAGE CIRCUITS

pSemi Corporation, San D...

1. A silicon on insulator structure comprising:a high resistivity silicon substrate configured to be coupled to a reference potential;
a buried oxide layer overlying the high resistivity silicon substrate;
a thin silicon layer overlying the buried oxide layer;
a first circuit formed in a first silicon region of the thin silicon layer, the first circuit configured to be coupled to a first potential;
a second circuit formed in a second silicon region of the thin silicon layer, the second circuit configured to be coupled to a second potential different from the first potential, and
at least one through buried oxide contact resistively coupling a local silicon region of one of the first silicon region and the second silicon region to the high resistivity silicon substrate by way of a non-ohmic contact between the through buried oxide contact and the high resistivity silicon substrate,
wherein:
a potential difference between the first potential and the reference potential is equal to or larger than 10 V, and a potential difference between the second potential and the reference potential is equal to or smaller than 5V,
the local silicon region comprises one or more transistors sensitive to a back gate effect, and
the through buried oxide contact is configured to bias a surface potential at a region of the high resistivity silicon substrate proximate the local silicon region to a level substantially equal to one of the first potential and the second potential.

US Pat. No. 10,770,479

THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME

TOKYO ELECTRON LIMITED, ...

1. A semiconductor device, comprising:a plurality of first source/drain (S/D) contacts and a plurality of first sources/drains, each of the plurality of first S/D contacts being formed over a respective first source/drain, and having a bar shape with a top portion, a bottom portion and side portions so that the bottom portion covers the respective first source/drain;
a plurality of first dielectric caps formed over the plurality of first S/D contacts, each of the plurality of first dielectric caps being positioned over a respective first S/D contact to cover the top portion and at least a part of the side portions of the respective first S/D contact;
a plurality of second S/D contacts and a plurality of second sources/drains that are positioned over the plurality of first S/D contacts, each of the plurality of second S/D contacts being formed over a respective second S/D, and having a bar shape with a top portion, a bottom portion and side portions so that the bottom portion covers the respective second source/drain, the plurality of second S/D contacts being staggered over the plurality of first S/D contacts to form a stair-case configuration; and
a plurality of second dielectric caps formed over the plurality of second S/D contacts, each of the plurality of second dielectric caps being positioned over a respective second S/D contact to cover the top portion and at least a part of the side portions of the respective second S/D contact.

US Pat. No. 10,770,478

METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICE HAVING BENT BACKSIDE WORD LINES

YANGTZE MEMORY TECHNOLOGI...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming a notch on at least one edge of a substrate;
forming a semiconductor layer above the substrate and extending laterally beyond the at least one edge of the substrate to cover the notch;
forming a plurality of interleaved conductive layers and dielectric layers along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch; and
removing a portion of the substrate to expose the interleaved conductive layers and dielectric layers below the semiconductor layer.

US Pat. No. 10,770,477

VERTICAL SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A vertical semiconductor device, comprising:a plurality of channel connection patterns contacting an upper surface of a substrate;
a lower insulation layer formed on the channel connection patterns and in a space between the channel connection patterns;
a supporting layer formed on the lower insulation layer to be spaced apart from the channel connection patterns, the supporting layer comprising polysilicon doped with impurities;
a stacked structure formed on the supporting layer, the stacked structure in which insulation layers and gate electrodes are stacked; and
a channel structure passing through the stacked structure, the supporting layer and the lower insulation layer, and extending to an upper portion of the substrate, the channel structure comprising a charge storage structure and a channel,
wherein the channel contacts the channel connection pattern, and
wherein the charge storage structure and the channel are disposed to face the gate electrodes and the supporting layer, and the supporting layer is configured to function a gate of a gate induced drain leakage (GIDL) transistor.

US Pat. No. 10,770,476

SEMICONDUCTOR STRUCTURE FOR THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

MACRONIX INTERNATIONAL CO...

1. A semiconductor structure for a three-dimensional memory device, comprising:a stacked structure disposed on a substrate, wherein the stacked structure comprises a plurality of insulation layers and a plurality of control gate layers which are alternatively stacked, and the stacked structure has a plurality of channel openings vertically penetrating the stacked structure, and a plurality of slits between the adjacent two rows of the channel openings and vertically extending through the stacked structure;
a plurality of channel pillars respectively located in the plurality of the channel openings and contacting the substrate, wherein the plurality of channel pillars each sequentially comprises a blocking insulation layer, a charge trapping layer, a tunneling insulation layer, a channel layer, and a core layer, from outside to inside;
a plurality of isolating insulation layers respectively disposed on the inner walls of the plurality of the slits; and
a plurality of conductive plugs respectively located between the plurality of isolating insulation layers, wherein a bottom part of each of the conductive plugs has a reduced neck structure and an enlarged bottom structure that extends into the substrate.

US Pat. No. 10,770,475

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Sk hynix Inc., Incheon-s...

1. A semiconductor device comprising:a well structure including a well dopant;
a gate stack structure comprising a first stack structure, a second stack structure, and a third stack structure, which are continuously stacked in a first direction over the well structure, the gate stack structure comprising a groove formed in a sidewall of the gate stack structure, wherein the groove is defined between the first stack structure and the third stack structure, and wherein the first stack structure and the third stack structure protrude farther than the second stack structure in a second direction perpendicular to the first direction;
a channel pattern penetrating the gate stack structure, the channel pattern extending along a surface of a horizontal space between the well structure and the gate stack structure;
a memory pattern extending along an outer wall of the channel pattern;
a spacer insulating pattern formed on the sidewall of the gate stack structure; and
a doped semiconductor pattern formed on the spacer insulating pattern, the doped semiconductor pattern extending toward the horizontal space to contact the channel pattern, the doped semiconductor pattern comprising a source dopant.

US Pat. No. 10,770,474

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

SK hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor device, the method comprising:forming a stack structure including a first region and a second region by alternately stacking interlayer insulating layers and sacrificial insulating layers on a lower structure;
forming pillars penetrating the first region of the stack structure;
forming a slit penetrating the second region of the stack structure;
forming first openings between the interlayer insulating layers by removing only a portion of each of the sacrificial insulating layers remaining between a slit-side pillar adjacent to the slit among the pillars and the slit, wherein the forming of the first openings is performed through dry etching using a first etching material introduced through the slit; and
forming second openings between the interlayer insulating layers by removing remaining portions of the sacrificial insulating layers which were not removed while forming the first openings between the interlayer insulating layers, wherein the forming of the second openings is performed through wet etching using a second etching material introduced through the first openings.

US Pat. No. 10,770,473

VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A vertical type semiconductor device, comprising:insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
a channel structure on the substrate and penetrating through the insulation patterns;
a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending towards the channel structure and parallel with the top surface of the substrate; and
a second conductive pattern on the first conductive pattern in the gap and filling the slit,
wherein a width at an entrance of the slit in the first direction is less than a width of an inner space of the slit in the first direction.

US Pat. No. 10,770,472

MEMORY ARRAYS, AND METHODS OF FORMING MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a vertical stack of alternating insulative levels and wordline levels;
channel material extending vertically along the stack;
conductive segments along the wordline levels; individual of the conductive segments having, along a cross-section, first and second ends in opposing relation to one another; the conductive segments comprising gates and wordlines adjacent the gates; the wordlines encompassing the second ends; the gates having substantially parabolic noses encompassing the first ends, the substantially parabolic noses extending outwardly toward the channel material; and
memory cell structures along the wordline levels and located between the channel material and the parabolic noses of the gates; the memory cell structures including charge-storage regions and charge-blocking regions; the charge-blocking regions being between the charge-storage regions and the gates.

US Pat. No. 10,770,471

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a substrate;
a first conductive layer formed in a plate shape, provided above the substrate and extending in parallel with a surface of the substrate so as to spread over first and second regions;
a second conductive layer formed in a plate shape, arranged to be separated at a distance above the first conductive layer so as to have a staircase shape with an end portion of the first conductive layer protruding, the second conductive layer extending in parallel with the first conductive layer so as to spread over the first and second regions;
a first support pillar connected to a lower surface or a side surface of the first conductive layer and extending toward the substrate at a position in the first region and not overlapping with the second conductive layer;
a second support pillar connected to a lower surface or a side surface of the second conductive layer and extending toward the substrate so as to penetrate through the first conductive layer in the first region;
a first contact electrically connected to the first conductive layer with a diameter size smaller than a diameter size of the first support pillar at a region position on an inner side in a radial direction of the first support pillar in the first region and extending to the opposite side of the substrate with respect to the first conductive layer;
a second contact electrically connected to the second conductive layer with a diameter size smaller than a diameter size of the second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer;
a channel body using a semiconductor material and penetrating through the first and second conductive layers in the second region; and
a memory film including a charge accumulation film and provided between each of the first and second conductive layers and the channel body in the second region.

US Pat. No. 10,770,470

MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES

Micron Technology, Inc., ...

1. An apparatus comprising:a substrate;
a memory cell string including a body;
a first control gate located in a first level of the apparatus and along a first portion of the body;
a second control gate located in a second level of the apparatus and along a second portion of the body; and
a connection coupled to the second control gate and to a transistor, the transistor having at least a portion formed in the substrate, the connection including a first portion going through a first portion of the first control gate, and a second portion going through a second portion of the first control gate.

US Pat. No. 10,770,469

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area, the method comprising:forming a protrusion of a substrate in the ring structure area, the protrusion protruding from an isolation insulating layer;
forming a high-k dielectric film, thereby covering the protrusion and the isolation insulating layer;
forming a poly silicon film over the high-k dielectric film;
after the poly silicon film is formed, patterning the poly silicon film and the high-k dielectric film, wherein a part of the isolation insulating layer is exposed by the pattering; and
forming insulating layers over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

US Pat. No. 10,770,468

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) memory structure, the method comprising:forming a dielectric layer;
forming a first plurality of openings in the dielectric layer at a staircase region of the 3D memory structure;
forming a second plurality of openings in the dielectric layer at a peripheral device region of the 3D memory structure;
etching the dielectric layer to form first and second pluralities of via extension regions in top portions of the respective first and second pluralities of openings;
disposing a first conductive material in the first and second pluralities of openings to form respective first and second pluralities of contact wires;
disposing a second conductive material in the first and second pluralities of via extension regions to form first and second pluralities of contact pads; and
forming first and second pluralities of lead wires on the first and second pluralities of contact pads, respectively.

US Pat. No. 10,770,467

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Samsung Electronics Co., ...

1. A method for fabricating a semiconductor device, the method comprising:forming a fin type active pattern defined by a field insulation layer, extending in a first direction, including first to third parts sequentially arranged in the first direction and upwardly protruding from a top surface of the field insulation layer;
forming a dummy gate electrode extending in a second direction different from the first direction and crossing the fin type active pattern on the first part;
trimming the second and third parts upwardly protruding from the top surface of the field insulation layer using the dummy gate electrode as a mask;
forming a gate spacer formed on the second part and sidewalls of the dummy gate electrode after the trimming the second and third parts;
forming a recess in the third part using the dummy gate electrode as a mask; and
forming a source/drain filling the recess on the third part,
wherein the second and third parts upwardly protrude from the top surface of the field insulation layer between the forming the gate spacer and after the trimming the second and third parts.

US Pat. No. 10,770,466

SEMICONDUCTOR DEVICES COMPRISING DIGIT LINE CONTACTS AND RELATED SYSTEMS

Micron Technology, Inc., ...

1. A semiconductor device comprising:laterally-neighboring word lines having respective word line caps thereon;
an active region between the laterally-neighboring word lines and word line caps;
a stack material adjacent the word line caps; and
a digit line contact between opposing substantially vertical surfaces of the stack material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps,
wherein a transition surface between and connecting the substantially horizontal surfaces and the substantially vertical surfaces of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact.

US Pat. No. 10,770,465

METHOD USED IN FORMING INTEGRATED CIRCUITRY

Micron Technology, Inc., ...

1. A method used in forming integrated circuitry, comprising:forming a substrate comprising a conductive line structure comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material, the sacrificial material comprising metal oxide;
removing at least some of the sacrificial material to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of the conductive line structure; and
covering the void space with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the conductive line structure.

US Pat. No. 10,770,464

SEMICONDUCTOR DEVICE INCLUDING BIT LINE STRUCTURE OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a bit line structure on a substrate;
a first spacer around the bit line structure, wherein a bottom surface of the first spacer is even with a bottom surface of the bit line structure;
a second spacer on a sidewall of the first spacer, wherein the second spacer comprises a bottom portion and a top portion, the bottom portion and the top portion comprise different dielectric materials, the bottom portion comprises silicon oxide and the top portion comprises silicon nitride, sidewalls of the bottom portion are vertically aligned with sidewalls of the top portion, and the bottom surface of the first spacer is lower than a bottom surface of the second spacer; and
a third spacer on a sidewall of the second spacer, wherein the third spacer is asymmetrical shaped on two sides, with one side being L-shaped, while another side being I-shaped, and the first spacer extends downwardly into and contacting a shallow trench isolation disposed under the third spacer.

US Pat. No. 10,770,463

SEMICONDUCTOR DEVICES INCLUDING STRUCTURES FOR REDUCED LEAKAGE CURRENT AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device, the method comprising:providing a substrate comprising a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer;
forming a source/drain region in a part of the upper semiconductor layer;
forming a first trench in the upper semiconductor layer, on one side of the source/drain region;
forming a first conductive pattern filling a part of the first trench;
forming a second trench in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer, on the other side of the source/drain region;
forming a second conductive pattern filling at least a part of the second trench; and
forming a unit active region and an element isolation region defining the unit active region, in the substrate,
wherein the first trench is formed in the unit active region of the substrate, and
wherein the second trench is formed in the element isolation region in the substrate.

US Pat. No. 10,770,462

CIRCUIT AND LAYOUT FOR SINGLE GATE TYPE PRECHARGE CIRCUIT FOR DATA LINES IN MEMORY DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a first gate including first, second and third portions, the first, second and third portions located over first, second and third channel regions, respectively;
second and third gates disposed such that the first gate is arranged between the second and third gates, the second and third gates located over fourth and fifth channel regions, respectively;
first and second diffusion regions formed to define the fourth channel region; and
third and fourth diffusion regions formed to define the fifth channel region, wherein each of the first, second, third and fourth diffusion regions includes a respective elongated portion to define the first channel region between the elongated portion of the first diffusion region and the elongated portion of the third diffusion region, the second channel region between the elongated portion of the second diffusion region and the elongated portion of the third diffusion region, and the third channel region between the elongated portion of the second diffusion region and the elongated portion of the fourth diffusion region.

US Pat. No. 10,770,461

ENHANCED FIELD RESISTIVE RAM INTEGRATED WITH NANOSHEET TECHNOLOGY

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing a fin structure comprising a vertical stack of alternating layers of a sacrificial semiconductor material layer and a semiconductor channel material layer located on a surface of a semiconductor substrate, and a first sacrificial gate structure and a second sacrificial gate structure located on different portions of the fin structure.
forming a first mask partially covering the second sacrificial gate structure;
etching physically exposed portions of the fin structure to provide a nanosheet stack comprised of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet beneath the first sacrificial gate structure, and a material stack of alternating layers of a sacrificial semiconductor material layer portion and a semiconductor channel material layer portion beneath the second sacrificial gate structure and the first mask;
recessing each sacrificial semiconductor material nanosheet of the nanosheet stack and each sacrificial semiconductor material layer portion of the material stack;
forming an inner spacer within a gap formed by the recessing;
forming a second mask protecting the first sacrificial gate structure, the nanosheet stack, the inner spacers formed within the gap formed by recessing the sacrificial semiconductor material nanosheets of the nanosheet stack;
recessing the semiconductor channel material layer portions of the material stack;
removing the second mask;
forming a source/drain (S/D) region on physically exposed sidewalls of each semiconductor channel material nanosheet of the nanosheet stack and a S/D region on a physically exposed sidewall of each recessed semiconductor channel material layer portion of the material stack;
removing the first mask;
removing the first and second sacrificial gate structures, each recessed sacrificial semiconductor material nanosheet and a portion of each recessed sacrificial semiconductor material layer portion; and
forming a first functional gate structure wrapping around each suspended semiconductor channel material nanosheet, and a second functional gate structure on exposed surfaces of each recessed semiconductor channel material layer portion of the material stack.

US Pat. No. 10,770,460

VERTICAL FIELD-EFFECT TRANSISTORS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES

International Business Ma...

1. A method, comprising:forming a vertical fin structure on a first substrate, wherein the vertical fin structure comprises a first vertical semiconductor fin, a fin insulating spacer disposed on the first vertical semiconductor fin, and a second vertical semiconductor fin disposed on the fin insulating spacer;
forming a sacrificial layer of insulating material on the first substrate, wherein the sacrificial layer of insulating material encapsulates the first vertical semiconductor fin of the vertical fin structure; and
forming a first device layer on the sacrificial layer of insulating material, wherein the first device layer comprises a first vertical field-effect transistor device which comprises the second vertical semiconductor fin of the vertical fin structure.

US Pat. No. 10,770,459

CMOS DEVICES CONTAINING ASYMMETRIC CONTACT VIA STRUCTURES

SANDISK TECHNOLOGIES LLC,...

1. A CMOS device, comprising:a p-type field effect transistor containing p-doped active regions and located on a semiconductor substrate;
an n-type field effect transistor containing n-doped active regions and located on the semiconductor substrate;
boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions;
first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures;
second active region contact via structures contacting a top surface of a respective one of the n-doped active regions; and
a silicon oxide material portion laterally surrounding one of the second active region contact via structures and not overlying the p-type field effect transistor.

US Pat. No. 10,770,458

NANOWIRE TRANSISTOR DEVICE ARCHITECTURES

Intel Corporation, Santa...

1. An integrated circuit comprising:first and second nanowires comprising semiconductor material;
a gate only partially surrounding each of the first and second nanowires;
a first dielectric structure between the gate and the first nanowire, the first dielectric structure including one or more layers, each of the one or more layers of the first dielectric structure completely surrounding the first nanowire; and
a second dielectric structure between the gate and the second nanowire, the second dielectric structure including one or more layers, each of the one or more layers of the second dielectric structure completely surrounding the second nanowire;
wherein the first and second dielectric structures are in contact with one another, wherein the first and second dielectric structures collectively at a point of contact have an average thickness that is within 70% of twice an average thickness of either the first or second dielectric structure alone at a point without such contact, and wherein an outermost layer of the first dielectric structure is in contact with an outermost layer of the second dielectric structure.

US Pat. No. 10,770,457

COMPENSATED ALTERNATING POLARITY CAPACITIVE STRUCTURES

NXP USA, Inc., Austin, T...

1. An integrated circuit comprising:a capacitive array comprising:
a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein
each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction,
the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and
the first and second fingers are interdigitated in the first direction;
a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row,
a second row of alternating first and second fingers formed in a second conductive layer that is vertically adjacent to the first conductive layer, wherein
each first finger in the second row is vertically aligned with a second finger in the first row, and
each second finger in the second row is vertically aligned with a first finger in the first row, and
a second compensation finger formed in the second conductive layer at an end of the second row nearest a second outer boundary of the capacitive array opposite the first outer boundary, the second compensation finger configured to have an opposite polarity as a second neighboring finger on the end of the second row, wherein each of the first and second compensation fingers is not vertically aligned with and does not vertically overlap the first and second fingers.

US Pat. No. 10,770,456

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device including a semiconductor substrate,the semiconductor substrate having a transistor region,
the transistor region comprising:
a first-conductivity-type drift region;
a plurality of trench portions extending from a front surface of the semiconductor substrate in a depth direction to reach the drift region and extending in a first direction on the front surface;
a plurality of first-conductivity-type emitter regions and a plurality of second-conductivity-type contact regions provided above the drift region and each having an upper surface exposed on the front surface, the plurality of emitter regions and the plurality of contact regions being alternately arranged next to each other in the first direction between two adjacent trench portions of the plurality of trench portions; and
an accumulation region provided between the drift region and the plurality of emitter regions in the depth direction, and having a higher first-conductivity-type doping concentration than the drift region,
wherein a first outermost contact region is an outermost one of the plurality of contact regions in a direction parallel to the first direction, and is longer in the first direction than one contact region of the plurality of contact regions other than the first outermost contact region, and
the accumulation region terminates at a position below the first outermost contact region.

US Pat. No. 10,770,455

ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A VARIABLE CAPACITOR

SEMICONDUCTOR COMPONENTS ...

1. A circuit comprising:a first high electron mobility transistor;
a second high electron mobility transistor, wherein a drain of the first high electron mobility transistor is coupled to a source of the second high electron mobility transistor; and
a first variable capacitor, wherein a first electrode of the first variable capacitor is coupled to a source of the first high electron mobility transistor, and a second electrode of the first variable capacitor is coupled to a gate of the second high electron mobility transistor;
a first diode including a first electrode and a second electrode: and
a second diode including a first electrode and a second electrode, wherein:
the first electrode of the first diode is coupled to the second electrode of the first variable capacitor,
the second electrode of the first diode is electrically connected to the second electrode of the second diode,
the first electrode of the second diode is coupled to the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor,
the first electrodes of the first diode and the second diode are both cathodes, and
the second electrodes of the first diode and the second diode are both anodes.

US Pat. No. 10,770,454

ON-CHIP METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHODS AND SYSTEMS FOR FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a fin in an active region on the semiconductor substrate;
forming an isolation feature on a semiconductor substrate;
forming a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and touching at least one side of the gate electrode, wherein at least one gate of the plurality of gates is on the fin and comprises a gate electrode, and a high-k dielectric layer disposed between the gate electrode and the fin and disposed on and in contact with at least one side of the gate electrode,
forming a spacer touching the high-k dielectric layer on at least one side of the gate electrode of the at least one gate on the fin and touching the high-k dielectric layer on at least one side of each gate electrode of the plurality of gates on the isolation feature; and
depositing a fill metal between the plurality of gates on the isolation feature, wherein the fill metal after deposition touches the high-k dielectric layer on at least one side of and below a top of the gate electrode of at least one of the plurality of gates.

US Pat. No. 10,770,453

SEMICONDUCTOR DEVICE HAVING AN EMITTER REGION AND A CONTACT REGION INSIDE A MESA PORTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
a drift layer of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed in the semiconductor substrate and above the drift layer; and
an accumulation region of the first conductivity type provided between the drift layer and the base region and having an impurity concentration higher than an impurity concentration in the drift layer, wherein
the accumulation region has:
a plurality of first accumulation regions; and
a second accumulation region,
wherein the second accumulation region is in direct contact with at least one of the first accumulation regions on a side of the at least one first accumulation region such that the plurality of first accumulation regions are only on one side of the second accumulation region in a planar view,
the semiconductor device further comprising a transistor portion formed in the semiconductor substrate,
wherein the transistor portion has:
a plurality of trench portions that are formed in a front surface of the semiconductor substrate and are arrayed in a predetermined direction; and
in the front surface of the semiconductor substrate, an emitter region of the first conductivity type having an impurity concentration higher than the impurity concentration in the drift layer formed between the plurality of trench portions,
wherein each of the plurality of first accumulation regions and the second accumulation region are formed between the plurality of trench portions,
wherein, at one end of an array direction in the transistor portion, the transistor portion has a boundary region in which the emitter region is not formed between the plurality of trench portions, and
wherein the boundary region is formed in the transistor portion on a side of a boundary with a diode portion formed in the semiconductor substrate.

US Pat. No. 10,770,452

APPARATUS AND METHODS FOR ELECTRICAL OVERSTRESS PROTECTION

Skyworks Solutions, Inc.,...

1. An integrated circuit with electrical overstress protection, the integrated circuit comprising:a pad;
an internal circuit electrically connected to a signal node; and
an overstress protection circuit including an impedance element having a first end electrically connected to the pad and a second end electrically connected to the signal node, an overstress sensing circuit electrically connected between the first end of the impedance element and a first supply node, a controllable clamp electrically connected between the second end of the impedance element and the first supply node, a first reverse protection circuit electrically connected between the first end of the impedance element and the first supply node, a second reverse protection circuit electrically connected between the second end of the impedance element and the first supply node, and an overshoot limiting circuit electrically connected between the signal node and a second supply node, the overstress sensing circuit configured to activate the controllable clamp to conduct a current from the second end of the impedance element to the first supply node in response to detecting an electrical overstress event at the first end of the impedance element.

US Pat. No. 10,770,451

THIN-FILM ESD PROTECTION DEVICE

MURATA MANUFACTURING CO, ...

1. A thin-film ESD protection device comprising:a semiconductor substrate having first and second principal surfaces that oppose each other;
a first insulating layer disposed on the first principal surface;
a first input/output electrode, a second input/output electrode, and a ground electrode each disposed on a surface of the first insulating layer;
a diode element disposed adjacent to the first principal surface of the semiconductor substrate and electrically connected between the first input/output electrode and the ground electrode;
a capacitor element disposed adjacent to the first principal surface of the semiconductor substrate and electrically connected between the second input/output electrode and the ground electrode; and
an inductor element disposed adjacent to the second principal surface of the semiconductor substrate and electrically connected to the first input/output electrode by a first via conductor passing through the semiconductor substrate between the first and second principal surfaces and to the second input/output electrode by a second via conductor passing through the semiconductor substrate between the first and second principal surfaces.

US Pat. No. 10,770,450

SEMICONDUCTOR INTEGRATED CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit, comprising:a semiconductor substrate having a first conductivity type;
a first well region having a second conductivity type, which is provided in an upper part of the semiconductor substrate in a high-potential side circuit area defined in the semiconductor substrate;
a second well region having the first conductivity type, which is provided in an upper part of the first well region and has an impurity concentration higher than an impurity concentration of the semiconductor substrate; and
a first semiconductor region having the second conductivity type, which is provided in a low-potential side circuit area, the low-potential side circuit area being separated from the high-potential side circuit area to be defined in the semiconductor substrate and being operated with potential as a reference, which is lower than reference potential of the high-potential side circuit area,
wherein a whole semiconductor region having the second conductivity type, which includes the first semiconductor region, has an impurity concentration higher than an impurity concentration of the first well region.

US Pat. No. 10,770,449

INTEGRATED STANDARD CELL STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit, comprising:a first standard cell having a first p-type field-effect transistor (pFET) and a first n-type field-effect transistor (nFET) integrated, and having a first dielectric gate on a first standard cell boundary;
a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary; and
a first filler cell configured between the first and second standard cells, and spanning between the first dielectric gate and the second dielectric gate, wherein
the first pFET and the second pFET are formed on a first continuous active region, and
the first nFET and the second nFET are formed on a second continuous active region.

US Pat. No. 10,770,448

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first masking layer over a substrate, the first masking layer comprising an opening over an active area and a spacer in the substrate;
forming a second masking layer over the substrate, the second masking layer having a block blocking a portion of the opening in the first masking layer;
performing an etching process, using the first masking layer and the second masking layer as an etching mask, to form a contact opening which exposes a portion of the active area and a portion of the spacer, wherein the contact opening has a first edge and a second edge located at opposite sides of the contact opening, and wherein the first edge is defined by an edge of the opening in the first masking layer and the second edge is defined by an edge of the block in the second masking layer; and
forming a contact plug in the contact opening and over the exposed portion of the active area and the exposed portion of the spacer.

US Pat. No. 10,770,447

METHOD FOR FABRICATING SUBSTRATE STRUCTURE AND SUBSTRATE STRUCTURE FABRICATED BY USING THE METHOD

Samsung Electronics Co., ...

1. A substrate structure comprising:a first substrate including first and second surfaces opposite each other, and a first device region at the first surface; and
a second substrate including third and fourth surfaces opposite each other, and a second device region formed at the third surface, a size of the second substrate being less than a size of the first substrate, the third surface of the second substrate being directly bonded to the first surface of the first substrate,
wherein the first device region and the second device region are electrically connected to each other,
the first device region and the second device region each include a device pattern,
a sidewall of the second substrate includes an inclined surface that is acute with respect to the first surface of the first substrate, and
the sidewall of the second substrate includes a continuous profile with a sidewall of the first device region.

US Pat. No. 10,770,446

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a redistribution substrate;
a semiconductor chip on the redistribution substrate;
a conductive member spaced apart from the semiconductor chip on the redistribution substrate;
a solder ball on the conductive member and electrically connected to the conductive member;
a polymer layer between the semiconductor chip and the conductive member on the redistribution substrate, the polymer layer having an opening through which the solder ball is exposed, and a residue on the solder ball and including the same material as the polymer layer, wherein a bottom surface of the solder ball is disposed at a higher level than a bottom surface of the semiconductor chip.

US Pat. No. 10,770,445

METHODS OF FABRICATING SEMICONDUCTOR PACKAGES INCLUDING REINFORCEMENT TOP DIE

SK hynix Inc., Icheon-si...

1. A method of fabricating semiconductor packages, the method comprising:forming stack structures on a base die wafer;
disposing a top die wafer on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the stack structures are comprised of core dies,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions; and
wherein the stack structures overlap with the base die regions, respectively, in a plan view,
further comprising removing the peripheral region of the base die wafer, a portion of the molding layer overlapping with the peripheral region, and a portion of the top die wafer overlapping with the peripheral region.

US Pat. No. 10,770,444

ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF

General Electric Company,...

1. An electronics package comprising:a multi-thickness conductor comprising a first portion and a second portion thicker than the first portion;
an insulating substrate positioned between the first and second portions of the multi-thickness conductor;
a first electrical component coupled to a first surface of the insulating substrate and electrically connected to the first portion of the multi-thickness conductor through at least one via in the insulating substrate; and
a second electrical component coupled to the second portion of the multi-thickness conductor;
wherein the first portion of the multi-thickness conductor is electrically coupled to the second portion of the multi-thickness conductor through at least another via in the insulating substrate.

US Pat. No. 10,770,443

CLOCK ARCHITECTURE IN HETEROGENEOUS SYSTEM-IN-PACKAGE

Intel Corporation, Santa...

1. An electronic device, comprising:a logic die, comprising a plurality of logic elements; and
a base die directly coupled to the logic die via an interface, wherein the base die comprises:
a phase-locked loop configured to generate a first clock signal;
phase detection and calibration circuitry coupled to the phase-locked loop, wherein the phase detection and calibration circuitry is configured to:
receive the first clock signal from the phase-locked loop;
generate a second clock signal and a third clock signal based on the first clock signal;
reduce skew between the second clock signal and the third clock signal in the base die;
provide the second clock signal to a first clock tree; and
provide the third clock signal to a second clock tree;
the first clock tree configured to transmit the second clock signal to a first logic element of the plurality of logic elements via a first connection of the interface; and
the second clock tree configured to transmit the third clock signal to a second logic element of the plurality of logic elements via a second connection of the interface.

US Pat. No. 10,770,442

DISPLAY DEVICE

OSRAM OLED GMBH, Regensb...

17. A display device comprising:a carrier comprising a plurality of switches;
a semiconductor layer sequence arranged on the carrier, the semiconductor layer sequence comprising an active region configured to generate radiation and forming a plurality of pixels, wherein each switch configured to control at least one pixel; and
an optical element arranged on each pixel on a radiation exit surface of the semiconductor layer sequence facing away from the carrier,
wherein each pixel on a side facing the carrier has a connection area in which the pixel is electrically contacted, and
wherein, in plan view of the display device, a surface area of the connection area is at most 10% of a surface area of the corresponding optical element.

US Pat. No. 10,770,441

DISPLAY DEVICE HAVING A PLURALITY OF BANK STRUCTURES

Innolux Corporation, Mia...

1. A display device, comprising:an array substrate;
an opposite substrate disposed opposite to the array substrate;
a plurality of micro light-emitting diodes arranged in an array on the array substrate;
a wavelength converting enhancement layer located between the plurality of micro light-emitting diodes and the opposite substrate;
a color filter layer disposed on the opposite substrate and having a plurality of color filter patterns; and
a plurality of bank structures located between the array substrate and the opposite substrate, wherein the plurality of micro light-emitting diodes are electrically connected to the array substrate, the plurality of bank structures form a plurality of accommodating regions, one of the plurality of micro light-emitting diodes is located in one of the plurality of accommodating regions, and a height of one of the plurality of bank structures is more than or equal to a height of the one of the plurality of micro light-emitting diodes.

US Pat. No. 10,770,440

MICRO-LED DISPLAY ASSEMBLY

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:an interposer;
a plurality of light emitting diode (LED) arrays each of which comprise a plurality of pixels composed of multiple sub-pixels;
a plurality of through-vias composed of an insulator liner, diffusion barrier metal and electroplated metallization feature, each through via of the plurality of through-vias being directly below and connecting to each pixel of the plurality of pixels of each of the plurality of LED arrays by a metal pad that is in physical contact and directly below the each pixel, wherein each through via of the plurality of through vias is further connected to the interposer and a single through via is used per pixel; and
a horizontal plate composed of GaN, wherein the plurality of pixels share the horizontal plate composed of GaN from above the plurality of pixels.

US Pat. No. 10,770,439

ELECTRONIC MODULE

SHINDENGEN ELECTRIC MANUF...

1. An electronic module comprising:a first electronic unit which has a first insulating substrate and a first electronic element provided on the first insulating substrate via a first conductor layer;
a second electronic unit which has a second insulating substrate and a second electronic element provided on the second insulating substrate via a second conductor layer;
a connecting body provided between the first electronic unit and the second electronic unit; and
a coil wound around the connecting body,
wherein the connecting body having the coil wound therearound is provided between the first insulating substrate and the second insulating substrate, and
wherein the first electronic element and the coil are electrically connected through pseudocapacitors in the first insulating substrate, and the second electronic element and the coil are electrically connected through pseudocapacitors in the second insulating substrate.

US Pat. No. 10,770,438

BONDED TWO-DIE DEVICE INCLUDING AN INTEGRATED CIRCUIT (IC) DIE AND A PHASE-CHANGE MATERIAL (PCM) SWITCH DIE

Newport Fab, LLC, Newpor...

15. A bonded two-die device comprising:an integrated circuit (IC) die including at least one active device, said IC die having an IC substrate side and a metallization side;
a phase-change material (PCM) switch die, said PCM switch die having a heat spreading side and a radio frequency (RF) terminal side;
said heat spreading side of said PCM switch die being bonded to said metallization side of said IC die.

US Pat. No. 10,770,437

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor package, comprising:forming a bottom redistribution layer (RDL) over a glass substrate;
forming a through insulator via (TIV) over the bottom RDL;
flip-chip bonding a first die over the bottom RDL;
molding the first die and the TIV;
forming an upper RDL over the first die;
flip-chip bonding a second die over the upper RDL;
forming a solder on the upper RDL and laterally surrounds the second die;
stacking a third packaged die over the second die and electrically connecting the third packaged die to the first die through soldering; and
forming an underfill surrounding the second die and the solder;
wherein the third packaged die having a carrier and a molding on the carrier, the carrier comprising a carrier surface and the molding comprising a molding surface, and the solder is in contact with the carrier surface of the third packaged die.

US Pat. No. 10,770,436

LIGHT-EMITTING DIODE (LED) DEVICE

Samsung Electronics Co., ...

1. A light-emitting diode (LED) device comprising:a plurality of light-emitting structures spaced apart from each other, each light-emitting structure including a first surface and a second surface;
a plurality of electrode layers on first surfaces of separate, respective light-emitting structures of the plurality of light-emitting structures;
a separation layer configured to isolate the plurality of light-emitting structures from each other;
a plurality of wavelength transformers on second surfaces of separate, respective light-emitting structures of the plurality of light-emitting structures; and
a partition layer between the wavelength transformers, such that the partition layer separates the wavelength transformers from each other.

US Pat. No. 10,770,435

APPARATUSES AND METHODS FOR SEMICONDUCTOR DIE HEAT DISSIPATION

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
a thermal interface layer disposed on a surface of the substrate; and
a heat spreader with a plurality of substrate-facing protrusions in proximity to the thermal interface layer, wherein the heat spreader covers an entire surface of a top die of a stack of semiconductor die, and wherein the thermal interface layer includes a plurality of upward-facing protrusions disposed between the plurality of substrate-facing protrusions, the upward-facing protrusions extending into a body of the heat spreader.

US Pat. No. 10,770,433

HIGH BANDWIDTH DIE TO DIE INTERCONNECT WITH PACKAGE AREA REDUCTION

APPLE INC., Cupertino, C...

1. A package structure comprising:a first wiring layer including a first side and a second side opposite the first side;
a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;
a second die face down on and electrically connected with the second side of the vertical interposer; and
a local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer;
wherein the second die occupies a larger area than both the vertical interposer and the local interposer.

US Pat. No. 10,770,432

ASICS FACE TO FACE SELF ASSEMBLY

STMICROELECTRONICS S.r.l....

1. A die structure, comprising:a first die including a first surface and a second surface opposite the first surface, the first die including sidewalls extending between the first and second surfaces;
conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first die, a second group of the conductive ink printed traces on the second surface of the first die, and a third group of the conductive ink printed traces on the sidewalls of the first die, wherein the first group of the conductive ink printed traces on the first surface of the first die includes a plurality of conductive ink printed traces coupled to some of a plurality of conductive ink printed contacts;
a second die having a first surface and a second surface, the first surface of the second die facing the first surface of the first die and including a plurality of traces on the first surface of the second die, each of the plurality of conductive ink printed traces having a first thickness extending towards the first surface of the second die in a direction orthogonal to the first surface of the first die, and each of the plurality of conductive ink printed contacts having a second thickness extending towards the first surface of the second die in the direction orthogonal to the first surface of the first die, the second thickness being greater than the first thickness; and
an anisotropic conductive paste positioned between the first surfaces of the first and second dies, the anisotropic conductive paste including an encapsulant and a plurality of magnetic beads coupled between the plurality of conductive ink printed contacts on the first surface of the first die and the plurality of traces on the first surface of the second die, the encapsulant of the anisotropic conductive paste covering the third group of the conductive ink printed traces on the sidewalls of the first die except for a first portion of the third group of the conductive ink printed traces exposed from the encapsulant as a sidewall contact, the sidewall contact being more adjacent to the second surface of the first die than to the first surface of the first die.

US Pat. No. 10,770,431

MEMORY DIE LAYOUTS FOR FAILURE PROTECTION IN SSDS

WESTERN DIGITAL TECHNOLOG...

1. A storage device, comprising:a controller;
a first memory device coupled to the controller, the first memory device comprising non-volatile memory; and
a second memory device coupled to the controller, the second memory device comprising:
a first package coupled to a first channel and to a second channel parallel to the first channel, the first package comprising an even number of memory dies each having a first storage capacity; and
a second package coupled to the first channel and the second channel, the second package comprising two memory dies each having a second storage capacity less than the first storage capacity,
wherein an equal number of memory dies from the first package having the first storage capacity and an equal number of memory dies from the second package having the second storage capacity are disposed on both the first channel and the second channel.

US Pat. No. 10,770,430

PACKAGE INTEGRATION FOR MEMORY DEVICES

XILINX, INC., San Jose, ...

1. An electronic memory device comprising:a substrate;
a first die stack mounted to the substrate, the first die stack comprising a first dummy die stacked on a first functional die; and
a second die stack disposed adjacent to the first die stack, the second die stack comprising a plurality of serially stacked second functional dies, the first dummy die having a top surface that is substantially coplanar with a top surface of the second die stack, wherein a height of one of the plurality of serially stacked second functional dies is less than a height of the first functional die.

US Pat. No. 10,770,429

MICROELECTRONIC DEVICE STACKS HAVING INTERIOR WINDOW WIREBONDING

Intel Corporation, Santa...

1. A microelectronic package, comprising:a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and
at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening;
wherein the at least one bond pad in or on the second microelectronic device first surface comprises a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.

US Pat. No. 10,770,428

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A device comprising:a first device comprising:
an integrated circuit device comprising a first connector;
a first polymer adhesive layer on the integrated circuit device; and
a first conductive layer on the first connector, the first polymer adhesive layer surrounding the first conductive layer;
a second device comprising:
an interposer comprising a second connector;
a second polymer adhesive layer on the interposer, the second polymer adhesive layer physically connected to the first polymer adhesive layer; and
a second conductive layer on the second connector, the second polymer adhesive layer surrounding the second conductive layer; and
a conductive connector bonding the first conductive layer to the second conductive layer, the conductive connector surrounded by an air gap.

US Pat. No. 10,770,427

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a chip package structure, comprising:forming a conductive via structure in a first substrate;
bonding a chip to a first surface of the first substrate;
forming a barrier layer over a second surface of the first substrate, wherein the barrier layer is in direct contact with the first substrate, and the barrier layer has a first opening exposing the conductive via structure;
forming a first insulating layer over the barrier layer, wherein the first insulating layer has a second opening and a third opening, the second opening is over the first opening and exposes the conductive via structure, the third opening partially exposes the barrier layer, and the barrier layer is thinner than the first insulating layer;
forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening, wherein the conductive pad continuously extends from the conductive via structure into the third opening; and
forming a conductive bump over the conductive pad in the third opening.

US Pat. No. 10,770,426

MICRO DEVICE TRANSFERRING METHOD, AND MICRO DEVICE SUBSTRATE MANUFACTURED BY MICRO DEVICE TRANSFERRING METHOD

CENTER FOR ADVANCED META-...

1. A micro-device transfer method comprising:a compression step in which a carrier film having a micro-device attached to an adhesive layer thereof is brought into contact with a substrate comprising a solder deposited on metal electrodes formed on the substrate and is compressed on the substrate;
a first adhesive strength generation step in which the solder disposed between the micro-device and the metal electrodes is compressed in the compression step to generate first adhesive strength between the micro-device and the solder;
a second adhesive generation step in which the micro-device is bonded to the adhesive layer through press-fitting in the compression step to generate second adhesive strength between the micro-device and the adhesive layer; and
a release step in which the carrier film is separated from the substrate, with the micro-device adhered to the solder,
wherein the second adhesive strength is proportional to a press-fitting depth of the micro-device press-fitted into the adhesive layer and the press-fitting depth of the micro-device in the adhesive layer is determined within a range allowing the second adhesive strength to be less than the first adhesive strength.

US Pat. No. 10,770,425

FLIP-CHIP METHOD

TONGFU MICROELECTRONCS CO...

1. A flip-chip method, comprising:providing a semiconductor chip and conductive connection pillars, wherein each of the conductive connection pillars has a first surface and a second surface opposite to the first surface;
fixing the conductive connection pillars on a surface of the semiconductor chip, wherein the first surfaces of the conductive connection pillars face the semiconductor chip and are in direct contact with the surface of the semiconductor chip;
providing a carrier plate;
forming solder pillars directly on a surface of the carrier plate;
forming a barrier layer directly on the surface of the carrier plate around the solder pillars;
bringing the solder pillars into contact with the second surfaces of the conductive connection pillars, wherein the conductive connection pillars are located above the solder pillars; and
performing a reflow-soldering process on the solder pillars, thereby forming solder layers from the solder pillars.

US Pat. No. 10,770,424

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a first component comprising:
a first dielectric layer;
a first conductive structure in the first dielectric layer, wherein the first conductive structure comprises a first conductive line and a first conductive pad on the first conductive line; and
a first filling material layer on the first conductive line and surrounding the first conductive pad; and
a second component bonded to the first component, comprising:
a second dielectric layer directly in contact with the first dielectric layer;
a second conductive structure in the second dielectric layer, wherein the second conductive structure comprises a second conductive pad and a second conductive line, the second conductive pad is directly in contact with the first conductive pad, and the second conductive line is on the second conductive pad; and
a second filling material layer surrounding the second conductive pad and in contact with the second conductive line.

US Pat. No. 10,770,423

CLAMPING SYSTEM, WIRE BONDING MACHINE, AND METHOD FOR BONDING WIRES

Semiconductor Manufacturi...

1. A clamping system in a wire bonding machine, comprising:a clamping device including:
at least one linear guide rail;
a first clamping rod arranged perpendicular to the linear guide rail;
a second clamping rod arranged perpendicular to the linear guide rail and parallel to the first clamping rod; and
a plurality of card slots spaced apart from one another along a rail guiding direction on the linear guide rail, the plurality of card slots being capable of mounting one or more of the first clamping rod and the second clamping rod.

US Pat. No. 10,770,422

BOND CHUCKS HAVING INDIVIDUALLY-CONTROLLABLE REGIONS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

13. A method for forming a semiconductor device, comprising:providing a chuck having multiple regions including a center region and an outermost region at least partially surrounding the center region;
positioning the chuck over a semiconductor device, the semiconductor device including a first substrate, a second substrate, and an adhesive between the first substrate and the second substrate;
moving at least one of the center region or the outermost region, relative to the other, in a longitudinal direction, thereby affecting a shape of the first substrate to cause the adhesive to flow in a predetermined lateral direction, wherein the outermost region is closer to the semiconductor device than the center region after the movement.

US Pat. No. 10,770,421

BOND CHUCKS HAVING INDIVIDUALLY-CONTROLLABLE REGIONS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A system for manufacturing semiconductor devices, comprising:a chuck having a plurality of regions including a first region, and a second region peripheral to the first region; and
a controller having instructions that, when executed, cause (a) the first region to be heated to a first temperature, and (b) the second region to be heated to a second temperature different than the first temperature.

US Pat. No. 10,770,420

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a lower electrode;
an upper electrode provided above the lower electrode in a first direction;
a semiconductor chip provided between the lower electrode and the upper electrode;
a pressure pad provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip; and
a spiral conductor provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip and the pressure pad, wherein
the spiral conductor has an upper spiral conductor, and a lower spiral conductor which is in contact with a lower end of the upper spiral conductor and faces the upper spiral conductor,
by forming grooves in the upper spiral conductor and the lower spiral conductor, a direction of a current flowing through the upper spiral conductor coincides with a direction of a current flowing through the lower spiral conductor in plan view, and
in a view in a second direction substantially perpendicular to the first direction:
one of the upper spiral conductor and the lower spiral conductor bends convex in the first direction, and
the other of the upper spiral conductor and the lower spiral conductor bends convex in a third direction opposite to the first direction.

US Pat. No. 10,770,419

APPARATUS AND METHOD FOR REDUCING VOLUME OF RESOURCE ALLOCATION INFORMATION MESSAGE IN A BROADBAND WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method performed by a base station in a wireless communication system, the method comprising:broadcasting, to a plurality of mobile stations (MSs), a first message including first information indicating a first periodicity and a first offset of an uplink control channel for a first initial network entry;
receiving, from one MS of the plurality of MSs, and uplink signal for the first initial network entry through the uplink control channel that is identified based on the first periodicity and the first offset;
transmitting, to the one MS, a second message including second information indicating a second periodicity and a second offset of the uplink control channel for a second initial network entry, the second periodicity being different form the first periodicity, and the second offset being different from the first offset; and
receiving, form the one MS, an uplink signal for the second initial network entry through the uplink control channel that is identified based on either the first periodicity and the first offset or the second periodicity and the second offset,
wherein a periodicity is a frame interval between two frames including the uplink control channel,
wherein an offset is a start point of the periodicity, and
wherein the periodicity and the offset are defined by number of frames.

US Pat. No. 10,770,418

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip;
a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;
a rear redistribution layer including a conductor layer embedded in the encapsulant and a seed layer disposed on the conductor layer and being thinner than the conductor layer, a portion of the encapsulant disposed between the rear redistribution layer and the second connection member;
a resin layer disposed on the encapsulant and being in contact with the seed layer of the rear redistribution layer and the encapsulant; and
a conductive connection member penetrating through the resin layer, the rear redistribution layer, and the encapsulant, the conductive connection member contacting exposed side surfaces of the resin layer.

US Pat. No. 10,770,417

CHIP PACKAGES AND METHODS FOR FORMING THE SAME

SHUNSIN TECHNOLOGY (ZHONG...

1. A chip package comprising:a substrate;
a semiconductor element on the substrate, and coupled to the substrate through a first conductive element;
a first colloid body on the substrate and covering the semiconductor element;
an optical element in direct physical contact with the first colloid body and coupled to the substrate through a second conductive element; and
a second colloid body on the first colloid body and covering the optical element, wherein a light transmittance of the second colloid body exceeds a light transmittance of the first colloid body, and the second colloid body is in direct physical contact with both the first colloid body and the optical element.

US Pat. No. 10,770,416

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a connection member having a first surface and a second surface opposing each other, the connection member including at least one insulating layer formed of a photoimageable dielectric material and at least one redistribution layer, a first surface of the at least one insulating layer corresponding to the first surface of the connection member, the at least one redistribution layer including a via penetrating through the at least one insulating layer and a RDL pattern connected to the via while being disposed on a second surface of the at least one insulating layer opposing the first surface of the at least one insulating layer;
a semiconductor chip disposed on the first surface of the connection member, and including a connection pad connected to the at least one redistribution layer; and
an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip,
wherein the at least one redistribution layer includes a seed layer disposed on the second surface of the at least one insulating layer, and a plating layer disposed on the seed layer, and the via has a shape in which a width adjacent to the second surface of the connection member is greater than a width adjacent to the first surface of the connection member, and
wherein an interface between the at least one insulating layer and the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more, and the first uneven surface extends to the entire second surface of the at least one insulating layer.

US Pat. No. 10,770,415

PACKAGED TRANSISTOR DEVICES WITH INPUT-OUTPUT ISOLATION AND METHODS OF FORMING PACKAGED TRANSISTOR DEVICES WITH INPUT-OUTPUT ISOLATION

Cree, Inc., Durham, NC (...

1. A packaged transistor device, comprising:an input lead;
an output lead;
a transistor comprising a control terminal and an output terminal;
a first bond wire electrically coupled between the input lead and the control terminal of the transistor;
a second bond wire electrically coupled between the output lead and the output terminal of the transistor; and
an isolation material that is physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.

US Pat. No. 10,770,414

SEMICONDUCTOR STRUCTURE HAVING MULTIPLE DIELECTRIC WAVEGUIDE CHANNELS AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a base layer;
a first dielectric waveguide disposed over the base layer;
a second dielectric waveguide disposed over the first dielectric waveguide, one of the first dielectric waveguide and the second dielectric waveguide being disposed over a top of the other of the first dielectric waveguide and the second dielectric waveguide, the first dielectric waveguide configured to guide a first electromagnetic signal from a first transmission end portion to a first receiver end portion of the first dielectric waveguide, the second dielectric waveguide configured to guide a second electromagnetic signal from a second transmission end portion to a second receiver end portion of the second dielectric waveguide, the second electromagnetic signal being different in frequency from the first electromagnetic signal;
a first inter-level dielectric (ILD) material disposed between the base layer and the first dielectric waveguide and between the first dielectric waveguide and the second dielectric waveguide;
a first transmitter coupling structure configured to couple a first driver signal generated by a transmitter circuit to the first transmission end portion and accordingly produce the first electromagnetic signal; and
a second transmitter coupling structure configured to couple a second driver signal generated by the transmitter circuit to the second transmission end portion and accordingly produce the second electromagnetic signal,
wherein the first dielectric waveguide has a first thickness, measured in a direction perpendicular to an upper surface of the base layer, associated with the first electromagnetic signal, wherein the second dielectric waveguide has a second thickness, measured in the direction, associated with the second electromagnetic signal, and wherein the first thickness is different from the second thickness.

US Pat. No. 10,770,413

CHIP PACKAGING STRUCTURE AND METHOD, AND ELECTRONIC DEVICE

SHENZHEN GOODIX TECHNOLOG...

1. A chip packaging structure, comprising:a support;
a chip;
at least one conductor; and
a package for plastic packaging the support, the chip, and the conductor;
the chip being disposed on an upper surface of the support, a chip pad being formed on an upper surface of the chip, and the chip pad being connected to an external pad of the support by a bonding wire;
the conductor being connected to a ground pad of the chip pad, and a shortest distance from the conductor to an upper surface of the package being less than a shortest distance from the bonding wire to the upper surface of the package; and
the conductor comprising a first end and a second end which are two free ends located oppositely in a length of the conductor, the first end being connected to the ground pad of the chip pad, the second end extending towards the upper surface of the package, and an end surface of the second end being covered with the package.

US Pat. No. 10,770,412

GUARD RING FOR PHOTONIC INTEGRATED CIRCUIT DIE

GLOBALFOUNDRIES INC., Gr...

1. A photonic integrated circuit (PIC) die, comprising:a semiconductor substrate;
active circuitry on the semiconductor substrate;
an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry;
a photonic element extending from the active circuitry on the semiconductor substrate;
a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including:
a conductive body, and
a conductive bridge element extending over the photonic element, wherein the conductive bridge element includes a first via coupled to a first terminal segment of the conductive body, a second via coupled to a second terminal segment of the conductive body, and a bridge wire coupling the first and second vias, the bridge wire extending over the photonic element;
a grounding via within the ILD coupled to the conductive body; and
a solder bump on the grounding via, wherein the grounding via electrically couples the guard ring to the solder bump, and wherein the first or second terminal segment of the conductive body is coupled to the grounding via through the bridge wire.

US Pat. No. 10,770,411

DEVICE COMPRISING A STACK OF ELECTRONIC CHIPS

STMICROELECTRONICS (ROUSS...

1. A method of protecting a first chip in a multi-chip stack, the method comprising:having the multi-chip stack comprising the first chip stacked on a second chip, the first chip comprising a first semiconductor substrate comprising first active devices at a first major surface and an opposite second major surface, the second chip comprising a second semiconductor substrate comprising second active devices at a first major surface and an opposite second major surface, the second major surface of the first semiconductor substrate facing the second semiconductor substrate;
having a detection circuit disposed in the first chip;
determining, at the detection circuit, an electrical characteristic of a conductive loop that extends over a top portion of the first chip, through the first chip and within a top portion of a second chip that is adjacent a bottom portion of the first chip, wherein the conductive loop comprises
a first through via extending completely through the first semiconductor substrate and having a first end at the first major surface of the first semiconductor substrate and a second end at the second major surface of the first semiconductor substrate,
a second through via extending completely through the first semiconductor substrate and having a first end at the first major surface of the first semiconductor substrate and a second end at the second major surface of the first semiconductor substrate,
a first track disposed in the first chip, the first track connecting the first end of the first through via to the first end of the second through via, and
a second track disposed in the second chip, the second track connecting the second end of the first through via to the second end of the second through via; and
determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.

US Pat. No. 10,770,410

CIRCUIT ALTERATION DETECTION IN INTEGRATED CIRCUITS

ARM LIMITED, Cambridge (...

1. A system, comprising:a shield in at least one metal layer over an integrated circuit and comprising a plurality of shield lines;
a detector coupled to the shield to detect a change in impedance characteristics of one or more of the plurality of shield lines of the shield due to physical alteration of the shield, wherein the detector comprises a comparator, wherein the comparator comprises a first input node selectively coupled to the shield and a second input node coupled to receive a reference voltage; and
three switches for each shield line, including a first switch that selectively couples one end of a shield line to a voltage supply line; a second switch that selectively couples the one end of the shield line to a first voltage line; and a third switch that selectively couples another end of the shield line to the first input node of the comparator;
wherein the comparator reads a middle voltage VMID at the first input node when one of the plurality of shield lines is coupled to the voltage supply line and the first input node and another of the plurality of shield lines is coupled to the first voltage line and the first input node; and outputs an error signal when a voltage difference between VMID and the reference voltage is greater than a tolerance value.

US Pat. No. 10,770,409

METHOD FOR DETECTING THINNING OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK SIDE, AND ASSOCIATED INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A method for detecting back side thinning of a semiconductor substrate of an integrated circuit, wherein the semiconductor substrate includes a semiconductor well isolated by a buried semiconductor layer located under the semiconductor well, the method comprising:producing, in the semiconductor well, a vertical MOS transistor including a first semiconductor electrode region located on a front side of the semiconductor substrate, and an insulated vertical gate region extending between the first semiconductor electrode region and the buried semiconductor layer which includes a second semiconductor electrode region of the vertical MOS transistor;
biasing the vertical MOS transistor to a transistor on state;
comparing a current delivered by one of the first and second semiconductor electrode regions of the vertical MOS transistor in an on state with a threshold value; and
generating a control signal having a first value corresponding to detection of non-thinning of the semiconductor substrate if the value of said current is higher than the threshold value, and having a second value corresponding to detection of thinning of the semiconductor substrate if the value of the current is lower than the threshold value.

US Pat. No. 10,770,408

WIRING BOARD AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring board comprising:an insulating layer;
a plurality of pads formed on a surface of the insulating layer; and
a chip mounting region defined on a surface of the wiring board formed with the plurality of pads,
wherein the plurality of pads are arranged in the chip mounting region,
wherein a cavity is formed in a surface of at least some of the plurality of pads,
wherein the cavity caves in, from the surface of the at least some of the plurality of pads, toward the insulating layer, and
wherein the chip mounting region is segmented into a plurality of segmented regions, and a depth of the cavity is different for each of the plurality of segmented regions.

US Pat. No. 10,770,407

IC STRUCTURE WITH INTERDIGITATED CONDUCTIVE ELEMENTS BETWEEN METAL GUARD STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit (IC) structure, comprising:a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein, wherein the plurality of metal layers includes a lowermost metal layer and an uppermost metal layer;
active circuitry coupled to at least one of the plurality of metal layers of the BEOL stack;
a pair of metal guard structures positioned between the active circuitry and an outer perimeter of the BEOL stack, the pair of metal guard structures concentrically surrounding the active circuitry, wherein each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers, one of the pair of metal guard structures includes a first metal crack stop, and the other of the pair of metal guard structures includes a second metal crack stop, a moisture oxidation barrier (MOB), or a guard ring; and
a set of interdigitating conductive elements within one of the plurality of metal layers, the set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

US Pat. No. 10,770,406

METHODS AND APPARATUS FOR SCRIBE STREET PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor wafer, comprising:a plurality of scribe streets arranged in rows and columns and having saw kerf lanes defined in a central portion and running parallel with the scribe streets;
a plurality of probe pads each formed centered in the scribe streets and intersected by the saw kerf lanes, each probe pad further including:
a lower level conductor layer having an outside border portion coextensive with the outside edge of the probe pad and an opening in a center portion; and
an upper level conductor layer forming two portions of upper level conductor layer material on only two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane.

US Pat. No. 10,770,405

THERMAL INTERFACE MATERIAL HAVING DIFFERENT THICKNESSES IN PACKAGES

Taiwan Semiconductor Manu...

1. A package comprising:a first package component;
a device die over and bonded to the first package component;
a metal cap comprising a top portion over the device die;
a thermal interface material between and contacting the device die and the metal cap, wherein the thermal interface material comprises:
a first portion directly over an inner portion of the device die, wherein the first portion has a first thickness; and
a second portion, wherein an entirety of the second portion is directly over, and overlaps, an outer portion of the device die, wherein the second portion has a second thickness greater than the first thickness, and the first thickness and the second thickness are measured in a direction orthogonal to a major top surface of the device die; and
an encapsulating material encircling the device die, wherein the second portion of the thermal interface material having the second thickness further extends directly over an additional portion of the encapsulating material.

US Pat. No. 10,770,404

SHIELDING FOR THROUGH-SILICON-VIA NOISE COUPLING

Taiwan Semiconductor Manu...

1. A method of shielding to prevent signals carried by a through substrate via from causing noise in an active area of an integrated circuit, comprising:forming a first guard ring around a first area comprising the through substrate via, wherein the first guard ring has a first conductivity type; and
forming a second guard ring around a second area comprising the active area, wherein the second guard ring has the first conductivity type;
wherein the through substrate via is outside of the second area fully surrounded by the second guard ring,
wherein the active area is outside of the first area fully surrounded by the first guard ring, and
wherein the active area is directly between a first portion of the second guard ring and a second portion of the second guard ring, wherein the first portion of the second guard ring is directly between the active area and the through substrate via, and wherein the first portion of the second guard ring has a first thickness greater than a second thickness of the second portion of the second guard ring.

US Pat. No. 10,770,403

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a connection member including an insulating layer and a redistribution layer;
a semiconductor chip disposed on the connection member;
an encapsulant encapsulating the semiconductor chip; and
an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes.

US Pat. No. 10,770,402

INTEGRATED FAN-OUT PACKAGE

Taiwan Semiconductor Manu...

1. A package, comprising:an integrated circuit comprising an antenna region;
an insulating encapsulation encapsulating the integrated circuit; and
a redistribution circuit structure disposed on the integrated circuit and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit, and the redistribution circuit structure comprising a redistribution region and a dummy region comprising a plurality of dummy patterns embedded therein, wherein the antenna region comprises an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

US Pat. No. 10,770,401

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE LINE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a first mask layer over a dielectric layer, wherein the first mask layer has a first trench, and the first trench has an inner wall and a bottom surface;
forming a second mask layer over a first top surface of the first mask layer, the inner wall, and the bottom surface;
removing the second mask layer covering the bottom surface to form a second trench in the second mask layer, wherein the second trench exposes the bottom surface and is over a first portion of the dielectric layer;
forming an anti-bombardment layer over a second top surface of the second mask layer, wherein the second mask layer and the anti-bombardment layer are made of different materials;
removing the first portion, the first mask layer, the second mask layer, and the anti-bombardment layer to form a third trench in the dielectric layer; and
forming a conductive structure in the third trench.

US Pat. No. 10,770,400

SEMICONDUCTOR MODULE

KABUSHIKI KAISHA TOYOTA J...

1. A semiconductor module comprising:a substrate;
a bare chip including a plurality of electrodes disposed on an upper surface thereof and an electrode disposed on a lower surface thereof, the electrode on the lower surface being mounted on the substrate; and
a conductor including a first joining portion that is joined to a control signal electrode of the electrodes disposed on the upper surface of the bare chip, a second joining portion that is joined to a control signal pattern on the substrate, and a connecting portion that electrically connects the first joining portion and the second joining portion, wherein the conductor is a metal plate having a first end portion, a second end portion, and a central portion between the first end portion and the second end portion, the metal plate forming the first joining portion with the first end portion, forming the second joining portion with the second end portion, and forming the connecting portion with the central portion, wherein the first joining portion, the connecting portion and the second joining portion of the metal plate form a U-shape, wherein
the connecting portion is provided with an insulating member,
a plurality of signal electrodes that includes the control signal electrode is provided for the one bare chip,
the conductor is a plurality of conductors that are disposed respectively on the plurality of the signal electrodes,
the connecting portions of the plurality of conductors are fixed by the single insulating member, and
the insulating member and the substrate are in surface contact with each other.

US Pat. No. 10,770,399

SEMICONDUCTOR PACKAGE HAVING A FILLED CONDUCTIVE CAVITY

Infineon Technologies AG,...

1. A semiconductor package, comprising:a frame comprising an insulative body having a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body;
a thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces, the thermally and/or electrically conductive material providing a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body; and
a semiconductor die attached to the frame at the first main surface of the insulative body and electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body,
wherein the semiconductor die is a power semiconductor die,
wherein a high-power terminal of the power semiconductor die facing the first main surface of the insulative body is electrically connected to the thermally and/or electrically conductive material filling the first cavity in the insulative body.

US Pat. No. 10,770,398

GRAPHICS PROCESSING UNIT AND HIGH BANDWIDTH MEMORY INTEGRATION USING INTEGRATED INTERFACE AND SILICON INTERPOSER

MICRON TECHNOLOGY, INC., ...

1. A semiconductor device assembly comprising:a substrate having a first side and a second side;
an interposer having a first side and a second side, the second side of the interposer connected to the first side of the substrate, wherein the interposer comprises complementary metal-oxide-semiconductor circuits;
a plurality of electrical interconnects connected to the second side of the substrate;
a first semiconductor device connected directly to the first side of the interposer;
a second semiconductor device connected directly to the first side of the interposer, wherein the interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer;
wherein the first semiconductor device is a processing unit;
wherein the second semiconductor device is a memory device; and
wherein the plurality of complementary metal-oxide-semiconductor circuits provide a buffer for data transfer between the first semiconductor device and the second semiconductor device.

US Pat. No. 10,770,397

SEMICONDUCTOR MODULE

Taiyo Yuden Co., Ltd., T...

1. A semiconductor module, comprising:a base substrate that includes a first dielectric film and an electrode layer, the first dielectric film having a mounting surface, the mounting surface including a first mounting area and a second mounting area;
a first semiconductor part mounted on the first mounting area; and
a second semiconductor part mounted on the second mounting area, the second semiconductor part including a vertical power semiconductor device, a conductive block to be connected to the electrode layer, and a wiring substrate, the vertical power semiconductor device having a first surface and a second surface, the first surface including a first terminal to be connected to the electrode layer, the second surface including a second terminal, and the wiring substrate electrically connecting the conductive block and the second terminal,
wherein the wiring substrate includes a second dielectric film and a wiring layer provided on the second dielectric film, the second dielectric film supporting the vertical power semiconductor device and the conductive block, and the wiring layer connecting the conductive block and the second terminal, and
wherein the wiring layer includes a plurality of vias connected to the vertical power semiconductor device and the conductive block, and a metal layer provided on the second dielectric film, the plurality of vias penetrating the second dielectric film, and the metal layer connecting the plurality of vias to each other.

US Pat. No. 10,770,396

SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor structure, comprising:a substrate;
an epitaxial layer disposed on the substrate;
a conductive feature disposed in the epitaxial layer and having a protruding portion that is higher than the epitaxial layer;
a diffusion barrier layer disposed on sidewalls of the conductive feature, wherein the diffusion barrier layer comprises a barrier oxide layer, wherein a bottom surface of the conductive feature is in direct contact with the epitaxial layer; and
a source region disposed in the epitaxial layer, wherein the diffusion barrier layer contacts the source region and separates the source region from the conductive feature.

US Pat. No. 10,770,395

SILICON CARBIDE AND SILICON NITRIDE INTERCONNECTS

International Business Ma...

1. A method for fabricating an interconnect structure for integrated circuit comprising:providing a recess in a first dielectric layer comprising a first dielectric and a second dielectric layer comprised of a second dielectric, the first and second dielectric layers disposed over a substrate, the second dielectric layer disposed over the first dielectric layer;
filling the recess with a metal conductor;
performing a chemical mechanical polishing process to remove the metal conductor from field areas on the second dielectric layer; and
after the chemical mechanical polishing process, removing the second dielectric layer, creating an interconnect element having a top face which protrudes higher than a top face of the first dielectric layer, the metal conductor of the interconnect element having direct contact with a surface of the first dielectric layer forming the recess.

US Pat. No. 10,770,394

FAN-OUT SEMICONDUCTOR PACKAGING STRUCTURE WITH ANTENNA MODULE AND METHOD MAKING THE SAME

SJ SEMICONDUCTOR (JIANGYI...

1. A fan-out semiconductor packaging structure with an antenna module, comprising:a semiconductor chip;
a plastic packaging material layer comprising a first surface and a second surface opposite to the first surface, wherein the plastic packaging material layer is patterned to enclose a periphery of the semiconductor chip and exposes a front surface of the semiconductor chip;
a filling structure patterned inside the plastic packaging material layer, wherein the filling structure is made of a material matching an antenna signal better than a material of the plastic packaging layer, such that a loss caused by the filling structure to the antenna signal is smaller than a loss caused by the plastic packaging material layer to the antenna signal;
wherein a top surface of the filling structure, the first surface of the plastic packaging material layer, and the front surface of the semiconductor chip are arranged in a same plane;
an antenna module disposed directly on the top surface of the filling structure;
a redistribution layer disposed on the second surface of the plastic packaging material layer, and electrically connecting with the semiconductor chip; and
a solder bump disposed on a surface of the redistribution layer, and electrically connecting with the redistribution layer.

US Pat. No. 10,770,393

BEOL THIN FILM RESISTOR

INTERNATIONAL BUSINESS MA...

1. An integrated circuit comprising:a dielectric layer including one or more metal interconnects:
one or more heat sinks in the dielectric layer and underlying one or more of the metal interconnects;
a resistor formed in a recess of the dielectric layer of a material having a resistivity greater than doped polysilicon;
wherein the resistor has sidewalls, wherein the resistor sidewalls are electrically coupled to sidewalls of adjacent metal interconnects;
wherein the resistor in the recess of the dielectric layer, the dielectric layer outside of the recess, and the one or more metal interconnects have coplanar upper surfaces; and
a cap layer on the coplanar surfaces of the resistor, the adjacent metal interconnects electrically coupled to the sidewalls of the resistor, and the dielectric layer such that the resistor is embedded under the cap layer within the recess of the dielectric layer.

US Pat. No. 10,770,392

LINE END STRUCTURES FOR SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES INC., Gr...

1. A method of fabricating a semiconductor device structure comprising:depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask;
depositing a metal layer covering the hard mask to form a metal hard mask;
forming vias in the dielectric stack using the metal hard mask;
removing the metal hard mask; and
forming trenches in the dielectric stack using the hard mask, wherein the metal hard mask and the hard mask are used to define a line end structure separating the trenches.

US Pat. No. 10,770,391

TRANSISTOR WITH GATE EXTENSION TO LIMIT SECOND GATE EFFECT

QUALCOMM Incorporated, S...

1. A transistor, comprising:a semiconductor layer comprising a source region, a drain region, and a channel region between the source region and the drain region, the channel region having a source interface, a drain interface, and bounded by edges of the channel region extending from the source interface to the drain interface, wherein the edges of the channel region are on two boundaries between a field-sensitive semiconductor material and an isolation material;
an insulator layer on the channel region;
a gate on the insulator layer, the gate disposed over the channel region and extending entirely between the source region and the drain region, the gate having extensions beyond the edges of the channel region, the extensions configured to protect the edges of the channel region from electrical fields generated from a handle wafer; and
a conductive shield over the gate extended beyond the edges of the channel region.

US Pat. No. 10,770,390

ENERGY STORING INTERPOSER DEVICE AND MANUFACTURING METHOD

SMOLTEK AB, Gothenburg (...

1. An interposer device for electrically and mechanically interconnecting a first electrical circuit element and a second electrical circuit element, said interposer device having a first side to be electrically and mechanically connected to said first electrical circuit element, and a second side, opposite the first side, to be electrically and mechanically connected to said second electrical circuit element, wherein said interposer device comprises:a first conductor pattern on the first side of said interposer device, said first conductor pattern defining a portion of said interposer device to be covered by said first electrical circuit element when said first electrical circuit element is electrically and mechanically connected to said first conductor pattern;
a second conductor pattern on the second side of said interposer device to be electrically and mechanically connected to said second electrical circuit element, said second conductor pattern being electrically coupled to said first conductor pattern; and
a plurality of nanostructure energy storage devices arranged within the portion of said interposer device to be covered by said first electrical circuit element, each of said nanostructure energy storage devices comprising:
at least a first plurality of conductive nanostructures;
a conduction controlling material embedding each conductive nanostructure in said first plurality of conductive nanostructures;
a first electrode connected to each conductive nanostructure in said first plurality of conductive nanostructures; and
a second electrode separated from each conductive nanostructure in said first plurality of conductive nanostructures by said conduction controlling material,
wherein at least one of said first electrode and said second electrode is connected to said first conductor pattern to allow electrical connection of said nanostructure energy storage device to said first electrical circuit element.

US Pat. No. 10,770,389

PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHES WITH CAPACITIVELY COUPLED RF TERMINALS

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) switch comprising:a phase-change material (PCM) and a heating element approximately underlying an active segment of said PCM and extending outward and transverse to said PCM;
RF terminals comprising lower metal portions and upper metal portions;
at least one of said lower metal portions of said RF terminals being ohmically separated from and capacitively coupled to passive segments of said PCM;
said upper metal portions of said RF terminals being ohmically connected to said lower metal portions of said RF terminals.

US Pat. No. 10,770,388

TRANSISTOR WITH RECESSED CROSS COUPLE FOR GATE CONTACT OVER ACTIVE REGION INTEGRATION

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:a semiconductor structure including a substrate having a first region and a second region;
a first source/drain disposed on the substrate in the first region;
an interlevel dielectric (ILD) disposed on the source/drain;
a first gate disposed on the substrate;
a first spacer disposed between the first source/drain and the first gate;
a first contact trench within the ILD extending to the first source/drain;
a first trench contact within the first contact trench;
a first source/drain contact trench extending to the first trench contact;
a cross couple contact trench within the ILD; and
a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact, the cross couple contact coupling the first source/drain and the first gate such that the cross couple contact is substantially connected to a singular surface of the first source/drain.

US Pat. No. 10,770,387

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

INTEL CORPORATION, Santa...

1. A method for providing a package substrate, comprising:providing one or more lands on a first side of the package substrate, the package substrate including a second side opposite the first side;
disposing one or more die bond pads on the second side, including providing the one or more die bond pads in a die interconnect region of the package substrate, wherein the die interconnect region comprises a silicon bridge;
depositing a first surface finish on at least one of the one or more lands; and
depositing a second surface finish on at least one of the die bond pads;
wherein the second surface finish has a different chemical composition than the first surface finish.

US Pat. No. 10,770,386

WIRING BOARD, ELECTRONIC DEVICE, AND WIRING BOARD MANUFACTURING METHOD

FUJITSU INTERCONNECT TECH...

1. A wiring board comprising:a first insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface;
a conductive layer that is disposed on the second surface;
a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer;
an electrode that is disposed on the first surface and connected to the via; and
a glass plate that is not in contact with the conductive layer or the electrode and is disposed on the first surface and includes a second through-hole through which the electrode is disposed.

US Pat. No. 10,770,385

CONNECTED PLANE STIFFENER WITHIN INTEGRATED CIRCUIT CHIP CARRIER

International Business Ma...

1. A method of fabricating an integrated circuit (IC) chip carrier comprising a lower surface, an upper surface, and a center, the method comprising:forming a first plane fabrication layer upon a lower periphery layer, the lower periphery layer comprising the lower surface of the IC chip carrier;
forming one or more first planes within the first plane fabrication layer;
forming a plane separation layer upon the one or more first planes and upon the first plane fabrication layer;
forming a plurality of channel vias within the plane separation layer and upon the one or more first planes, each channel via comprising a width, a length greater than the width, and a width bisector that is coincident with the center of the IC chip carrier;
forming a second plane fabrication layer upon the plurality of channel vias and upon the plane separation layer;
forming one or more second planes within the second plane fabrication layer and upon the plurality of channel vias; and
forming an upper periphery layer upon the one or more second planes and upon the plane fabrication layer, the upper periphery layer comprising the upper surface of the IC chip carrier.

US Pat. No. 10,770,384

PRINTED CIRCUIT BOARD HAVING INSULATING METAL OXIDE LAYER COVERING CONNECTION PAD

SAMSUNG ELECTRONICS CO., ...

1. A printed circuit board (PCB) comprising:a base substrate layer;
a first connection pad and a second connection pad disposed on a first surface and a second surface of the base substrate layer, respectively,
wherein the first connection pad includes a top surface and a plurality of side surfaces extending from the top surface to the first surface of the base substrate layer,
and wherein the first connection pad and the second connection pad each comprises a first metal;
a first pad cover layer covering the top surface of the first connection pad and comprising an insulating metal oxide having a second metal different from the first metal;
a first wire disposed on the first surface of the base substrate layer and located at a same level as the first connection pad with respect to the second surface of the base substrate layer, wherein the first wire comprises a same material as the first connection pad;
a first wire cover layer covering a top surface of the first wire and comprising a same material as the first pad cover layer; and
a first solder resist layer disposed on the first surface of the base substrate layer to cover entirely a top surface of the first wire cover layer without covering a portion of the first pad cover layer,
wherein the first pad cover layer is absent from the plurality of side surfaces of the first connection pad.

US Pat. No. 10,770,383

SEMICONDUCTOR DEVICE HAVING FLEXIBLE INTERCONNECTION AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a first semiconductor chip having a circuit layer; and
a redistribution layer disposed on the circuit layer of the first semiconductor chip,
wherein the redistribution layer comprises:
a redistribution line electrically connected to the circuit layer; and
an insulating layer surrounding the redistribution line,
wherein a portion of the insulating layer covers a sidewall of the first semiconductor chip,
wherein a portion of the redistribution line is disposed on the portion of the insulating layer,
wherein the insulating layer is more flexible than the first semiconductor chip, and
wherein the redistribution layer extends sideward from the first semiconductor chip to a second semiconductor chip such that a distance between the first and second semiconductor chips changes when the redistribution layer is bent.

US Pat. No. 10,770,382

LOW INDUCTANCE STACKABLE SOLID-STATE SWITCHING MODULE AND METHOD OF MANUFACTURING THEREOF

General Electric Company,...

1. A modular electronics package comprising:a pair of electronics packages comprising a first electronics package and a second electronics package, each of the first and second electronics packages comprising:
a metallized insulating substrate comprising an insulating layer and a first conductor layer positioned on the insulating layer; and
a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate; and
a conductive joining material positioned between the first electronics package and the second electronics package to electrically connect the first electronics package to the second electronics package;
wherein the first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.

US Pat. No. 10,770,381

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor component, comprising:a support having a surface and a cathode lead that is integral with and extends from the support;
an anode lead adjacent to and electrically isolated from the support;
a substrate having a first portion and a second portion, the substrate bonded to the support;
a first semiconductor chip having a first surface and a second surface, wherein a source bond pad extends from a first portion of the first surface, a drain bond pad extends from a second portion of the first surface, and a gate bond pad extends from a third portion of the first surface, the second surface bonded to the first portion of the substrate, the drain bond pad coupled to the surface of the support, wherein the first semiconductor chip is configured from a III-N semiconductor material;
a first electrical interconnect having a first end and a second end, the first end of the first electrical interconnect coupled to the source bond pad of the first semiconductor chip and the second end of the first electrical interconnect coupled to the second portion of the substrate;
a second semiconductor chip electrically coupled to the second end of the first electrical interconnect, the second semiconductor chip electrically isolated from the cathode lead of the support by the substrate, wherein the second semiconductor chip comprises a diode having a first surface and a second surface, and wherein an anode is formed from the first surface and a cathode is formed from the second surface; and
a second electrical interconnect having a first end and a second end, the first end of the second electrical interconnect coupled to the anode lead and the second end of the second electrical interconnect coupled to the second semiconductor chip.

US Pat. No. 10,770,380

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A power module, comprising:a first semiconductor chip mounted on a first island part;
a second semiconductor chip mounted on a second island part;
a third semiconductor chip mounted on a third island part;
a fourth semiconductor chip mounted on a forth island part;
a fifth semiconductor chip mounted on the forth island part;
a sixth semiconductor chip mounted on the forth island part;
a first driving semiconductor chip mounted on a fifth island part and connected to each of the first to third semiconductor chips;
a second driving semiconductor chip mounted on a sixth island part and connected to each of the fourth to sixth semiconductor chips;
a first plurality of wires connecting the first driving semiconductor chip to the first, second and third semiconductor chips;
a second plurality of wires connecting the second driving semiconductor chip to the fourth, fifth and sixth semiconductor chips;
a first lead terminal connected to the first semiconductor chip by a first wire;
a second lead terminal connected to the second semiconductor chip by a second wire;
a third lead terminal connected to the third semiconductor chip by a third wire;
a fourth lead terminal connected to the fourth semiconductor chip by a fourth wire and extending from the first island part;
a fifth lead terminal connected to the fifth semiconductor chip by a fifth wire and extending from the second island part;
a sixth lead terminal connected to the sixth semiconductor chip by a sixth wire and extending from the third island part; and
a seventh lead terminal extending from the forth island part,
wherein the first to sixth semiconductor chips are arranged in a first direction, the first driving semiconductor chip and the second driving semiconductor chip are arranged in the first direction, and the second driving semiconductor chip and the seventh lead terminal are arranged opposite to each other in a second direction across the fourth to sixth semiconductor chips, the second direction being perpendicular to the first direction,
wherein the first to sixth wires are directly connected to the first to sixth lead terminals, respectively,
the first to sixth wires are electrically connected only between the first to sixth lead terminals and the first to sixth semiconductor chips, respectively.

US Pat. No. 10,770,379

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device in which a semiconductor chip is sealed with a sealing resin, comprising:a first corner portion,
a second corner portion adjacent to the first corner portion,
a third corner portion facing the first corner portion diagonally,
a fourth corner portion opposed to the second corner portion diagonally,
a first terminal disposed in the vicinity of the first corner portion for electrically connecting to the outside,
a second terminal disposed in the vicinity of the second corner portion for electrically connecting to the outside,
a third terminal disposed in the vicinity of the fourth corner portion for electrically connecting to the outside, and
a fourth terminal disposed in the vicinity of the third corner portion for electrically connecting to the outside,
wherein an area as seen in plan view of the first terminal and an area as seen in plan view of the second terminal are the same size,
an area as seen in plan view of the third terminal and an area as seen in plan view of the fourth terminal are the same size,
the area as seen in plan view of the third terminal is larger than the area as seen in plan view of the first terminal,
no terminal exists between the first terminal and the third terminal in plan view, and
no terminal exists between the second terminal and the fourth terminal in plan view.

US Pat. No. 10,770,378

ISOLATED COMPONENT DESIGN

TEXAS INSTRUMENTS INCORPO...

1. A microelectronic device, comprising:a first conductor;
a second conductor separated from the first conductor by a first lateral separation, the first lateral separation extending from a first straight tangent line that is tangent to the first conductor, to a second straight tangent line that is tangent to the second conductor, wherein:
the first conductor has a first low field contour along a side facing the second conductor;
the first straight tangent line is tangent to the first conductor on the first low field contour;
the first low field contour has a first offset from the first straight tangent line, the first offset being located at a first lateral distance of 25 percent of the first lateral separation from a first end of the first conductor, the first offset being 19 percent to 28 percent of the first lateral separation;
the first low field contour has a second offset from the first straight tangent line, the second offset being located at a second lateral distance of 50 percent of the first lateral separation from the first end of the first conductor, the second offset being 9 percent to 14 percent of the first lateral separation; and
the first low field contour has a third offset from the first straight tangent line, the third offset being located at a third lateral distance of 75 percent of the first lateral separation from the first end of the first conductor, the third offset being 4 percent to 6 percent of the first lateral separation.

US Pat. No. 10,770,377

LEADFRAME DIE PAD WITH PARTIALLY-ETCHED GROOVE BETWEEN THROUGH-HOLE SLOTS

TEXAS INSTRUMENTS INCORPO...

8. An integrated circuit (IC) package, comprising:a semiconductor die having a top side with active circuitry and bond pads;
a leadframe including a die pad having a die attach resin material including a resin mounting the semiconductor die top side up, the leadframe having leads or leads terminals beyond the die pad, the die pad comprising:
slots including at least a first slot and a second slot on at least a first side of the die pad that penetrate a full thickness of the die pad;
at least one non-penetrating groove in the die pad providing a fluid connection between the first and second slots for providing a flow channel for guiding the resin when received after bleeding out from under the semiconductor die to flow to at least one of the first and second slots;
bond wires between some of the bond pads of the semiconductor die and the leads and lead terminals, and
a mold compound covering the semiconductor die the bond wires and at least a portion of the leadframe.

US Pat. No. 10,770,376

SEMICONDUCTOR DEVICE, INVERTER UNIT AND AUTOMOBILE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a conductive substrate;
at least one semiconductor chip bonded to an upper surface of the conductive substrate;
a control terminal disposed outside the semiconductor chip and connected to a control electrode of the semiconductor chip via a lead;
a case surrounding the semiconductor chip;
at least one lead frame; and
a sealing material sealing the semiconductor chip,
wherein the lead frame includes
a bonded part joined to the semiconductor chip, and
an upright part embedded in the case, extending from the bonded part to an outer side of the control terminal, and standing upright vertically relative to an upper surface of the semiconductor chip, and
at least part of the upright part is formed inside of the control terminal.

US Pat. No. 10,770,375

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a die pad including a first main surface and a second main surface opposite to the first main surface;
a semiconductor chip mounted on the first main surface of the die pad, the semiconductor chip including a first front surface, a first rear surface opposite to the first front surface, and a plurality of electrodes arranged on the first front surface;
a plurality of leads including a first lead facing the die pad in plan view, the plurality of leads being arranged at positions so as to be spaced apart from the die pad, the plurality of leads being electrically connected with the semiconductor chip;
a plurality of wires including a first wire and a second wire; and
an encapsulation body encapsulating the semiconductor chip, the plurality of wires, and the die pad,
wherein the plurality of electrodes of the semiconductor chip includes 1) a first electrode electrically connected with the first lead via the first wire, and 2) a second electrode electrically connected with the die pad via the second wire,
wherein the die pad includes 1) a wire-bonding region that is A) not overlapping with the semiconductor chip in plan view and B) covered by a first metal film partially covering the first main surface of the die pad, and 2) a first through hole that penetrates through the die pad from the first main surface to the second main surface,
wherein the second wire is bonded to the first metal film in the wire-bonding region,
wherein the first through hole is formed at a position overlapping with the first metal film or around the first metal film, and
wherein an opening area of the first through hole is smaller than an area of the first metal film in plan view.

US Pat. No. 10,770,374

THROUGH-SILICON VIAS FOR HETEROGENEOUS INTEGRATION OF SEMICONDUCTOR DEVICE STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a plurality of enclosed cavity structures provided in a single substrate;
at least one optical device provided on two sides of the single substrate and between the plurality of enclosed cavity structures; and
a through wafer optical via extending through the substrate, between the plurality of enclosed cavity structures and which exposes a backside to the at least one optical device,
wherein the plurality of enclosed cavity structures have walls formed from semiconductor material of the single substrate and sealed with a reflowed epitaxial material at an upper portion.

US Pat. No. 10,770,373

RADIATOR FOR LIQUID COOLING TYPE COOLING DEVICE AND METHOD OF PRODUCING THE SAME

SHOWA DENKO K.K., Tokyo ...

1. A radiator for a liquid cooling type cooling device, wherein the radiator is arranged in a coolant passage formed in a casing of the liquid cooling type cooling device to radiate heat emitted from a heating element to a coolant, and wherein the liquid cooling type device is provided with the casing having a top wall, a bottom wall, and a peripheral wall and the coolant passage through which the coolant flowed into the casing flows and is configured to cool the heating element mounted on at least either one of an outer surface of the top wall and an outer surface of the bottom wall of the casing by the coolant flowing through the coolant passage,the radiator comprising:
a plurality of vertically elongated rectangular shaped fin plates arranged in parallel at intervals; and
a connecting member integrally connecting all the fin plates,
wherein the fin plate includes:
a plate body in which a longitudinal direction is oriented in a flow direction of the coolant and a width direction is oriented in a vertical direction, the plate body being provided with flat plate-shaped portions at certain length portions close to both ends of the longitudinal direction; and
a narrow portion integrally provided at each of both longitudinal end portions of the plate body so as to protrude outward from the longitudinal end portions in the longitudinal direction of the plate body and having both upper and lower ends positioned inner than both upper and lower side edges of the plate body in the width direction of the plate body,
wherein all the fin plates are arranged at intervals in a thickness direction of the fin plate in a state in which the longitudinal direction of the plate body is oriented in the flow direction of the coolant and the width direction of the plate body is oriented in the vertical direction,
wherein the connecting member is formed into a corrugated shape and composed of flat plate portions each integrated with the narrow portion of the plate body of the fin plate and arcuate portions each alternately connecting adjacent flat plate portions at upper and lower ends of the adjacent flat plate portions,
wherein the flat plate portions of the connecting member are arranged so that a longitudinal direction of the flat plate portion is oriented in the vertical direction and a thickness direction of the flat plate portion is oriented in the thickness direction of the plate body of the fin plate,
wherein both the upper and lower ends of the connecting member are positioned inner than both the upper and lower ends of the plate body in the width direction of the plate body,
wherein an intermediate portion of an upper arcuate portion of the connecting member protrudes upward and an intermediate portion of a lower arcuate portion of the connecting member protrudes downward,
wherein the plate body and the narrow portion of the fin plate, and the flat plate portion of the connecting member are equal in thickness, and
wherein both side surfaces of the flat plate-shaped portion of the plate body in the thickness direction, both side surfaces of the narrow portion in the thickness direction, and both side surfaces of the flat plate portion of the connecting member in the thickness direction are positioned on a same plane.

US Pat. No. 10,770,372

FLUID ROUTING DEVICES AND METHODS FOR COOLING INTEGRATED CIRCUIT PACKAGES

Altera Corporation, San ...

1. A fluid routing device comprising:a fluid inlet;
first vertical channels that are open to the fluid inlet;
a horizontal channel that is open to each of the first vertical channels, wherein the first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel, and wherein the horizontal channel is open on one side of the fluid routing device such that an apparatus attached to a bottom of the fluid routing device forms a sidewall of the horizontal channel;
second vertical channels that are open to the horizontal channel, wherein the second vertical channels are oriented to provide fluid coolant vertically up away from the horizontal channel, wherein the first vertical channels are interleaved between the second vertical channels, and wherein each of the first vertical channels and each of the second vertical channels is directly connected at one end to the horizontal channel; and
a fluid outlet that is open to the second vertical channels such that fluid coolant from the second vertical channels exits the fluid routing device through the fluid outlet,
wherein each of the first vertical channels has a constricted opening to the horizontal channel directly above the horizontal channel, wherein a width of the constricted opening of each of the first vertical channels is narrower than a width of the first vertical channel above the constricted opening, and wherein an opening of each of the second vertical channels to the horizontal channel directly above the horizontal channel is wider than the constricted opening to the horizontal channel of each of the first vertical channels.

US Pat. No. 10,770,371

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a base plate made of a metal and having a through-hole;
an insulating substrate on the base plate;
a semiconductor chip on the insulating substrate;
a case having a screw-hole formed only partially through the case, communicating with the through-hole, covering the insulating substrate and the semiconductor chip, and disposed on the base plate;
a screw made of a metal and inserted into the through-hole and the screw-hole to fix the case to the base plate; and
a flexible material having flexibility, compressed and filled in a cavity between a bottom surface of the screw-hole in the case and a distal end of the screw, wherein
volume of the flexible material when it is uncompressed is larger than that of the cavity,
an electrically conductive coat is applied to a side surface and the bottom surface of the screw-hole in the case, and
the entire flexible material is composed of only a silicone rubber sponge or a fluorocarbon rubber sponge.

US Pat. No. 10,770,370

ELECTRONIC DEVICE AND HEAT DISSIPATING SHEET

FUJITSU LIMITED, Kawasak...

1. An electronic device comprising:a component;
a resin film formed to the component; and
a plurality of carbon nanotubes whose end portions pass through the resin film and are in contact with the component,
wherein
a first portion of each of the carbon nanotubes is covered with the resin film,
the first portion has a first length which is greater than a thickness of the resin film, and
an intermediate portion of each of the carbon nanotubes other than the first portion is uncovered with and exposed from the resin film.

US Pat. No. 10,770,369

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a substrate having a surface;
a first electronic component and a second electronic component disposed over the surface of the substrate and arranged along a direction substantially parallel to the surface, wherein the first electronic component and the second electronic component are separated by a space therebetween;
a heat dissipation lid disposed over the first electronic component and the second electronic component, wherein the heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component; and
a thermal isolation disposed in the one or more apertures of the heat dissipation lid,
wherein the one or more apertures includes a first aperture over the space between the first electronic component and the second electronic component, and one or more second apertures over at least one of the first electronic component or the second electronic component, and the first aperture is distinct from the one or more second apertures, wherein the first aperture partially overlaps an edge of the first electronic component and an edge of the second electronic component.

US Pat. No. 10,770,368

CHIP ON FILM PACKAGE AND HEAT-DISSIPATION STRUCTURE FOR A CHIP PACKAGE

Novatek Microelectronics ...

1. A chip on film package, comprising:a base film comprising a first surface and a second surface opposite to the first surface;
a chip disposed on the first surface, having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface and being perpendicular to the top surface and the bottom surface, and having a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis, wherein the first axis and the second axis define a plane parallel to the top surface and the bottom surface; and
a first heat-dissipation structure comprising a covering portion, the covering portion at least partially covering the chip, exposing the side surface of the chip, and having a first length along the first axis and a second length along the second axis being longer than the chip width of the chip.