US Pat. No. 10,367,655

NETWORK SYSTEM AND METHOD FOR CONNECTING A PRIVATE NETWORK WITH A VIRTUAL PRIVATE NETWORK

Alibaba Group Holding Lim...

1. A networking method, comprising steps of:receiving, at an edge router of a cloud data center, a virtual private cloud (“VPC”) network communication from a private network via a dedicated physical connection line to the edge router;
forwarding the VPC network communication from the edge router to a gateway hardware group connected to the edge router via a first connection using Virtual Extensible Local Area Network (“VXLAN”) technology; and
forwarding the VPC network communication from the gateway hardware group to a virtual machine (“VM”) in a VPC of a user of the private network connected to the gateway hardware group via a second connection using VXLAN technology to access the VM,
wherein the gateway hardware group is partitioned into regional gateway hardware subgroups based on a geographic location of the regional gateway hardware subgroups, respectively, and
wherein the regional gateway hardware subgroups are linked via a logical connection via which a network traffic load is balanced among multiple regional gateway hardware subgroups.

US Pat. No. 10,367,654

NETWORK DESIGN METHOD FOR ETHERNET RING PROTECTION SWITCHING

FUJITSU LIMITED, Kawasak...

1. A method for configuring networks, the method comprising:based on topology information representing a network, the topology information comprising nodes and links between the nodes, identifying at least two core nodes and a major ring including the core nodes;
adding a virtual node V and virtual links to the topology information, the virtual node V connecting to the core nodes with the virtual links;
for each non-core node in the topology information, identifying two diverse paths from the non-core node to the virtual node V;
populating a node set Snc with at least some of the non-core nodes;
sorting the node set Snc according to a decreasing number hops of diverse paths to the virtual node V;
repeating until the node set Snc is an empty set:
selecting a first non-core node K in the node set Snc with the greatest number of hops of diverse paths to the virtual node V;
identifying a next sub-ring having two diverse paths from the first non-core node K to the virtual node V;
initializing a node set Pnc with the non-core nodes shared by the node set Snc and the next sub-ring;
adding the first non-core node K to the next sub-ring;
removing the first non-core node K from the node set Snc and the node set Pnc; and
adding additional non-core nodes from the node set Pnc to the next sub-ring until a termination condition for the next sub-ring is satisfied; and
causing the network to be configured with the major ring and the sub-rings.

US Pat. No. 10,367,651

SYSTEM, METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR CONFIGURING A NETWORK CONNECTED APPLIANCE TO USE ONLINE SERVICES

ELECTROLUX HOME PRODUCTS,...

1. A method for configuring an appliance to use a home automation system, the method comprising a computer system:causing a plurality of home automation systems to be presented as selectable options via an interface accessed over a network via a user device associated with a user, the plurality of home automation systems being distinct and available for use with a network connected appliance;
receiving an indication of a selected home automation system for the network connected appliance, the indication being received from the user device, and the selected home automation system being user-selected from the plurality of home automation systems presented as selectable options via the interface;
registering the network connected appliance to the selected home automation system; and
enabling communication between the network connected appliance and the selected home automation system, enabling communication between the network connected appliance and the selected home automation system comprising remotely configuring the network connected appliance via a network to communicate with the selected home automation system.

US Pat. No. 10,367,649

SMART SCHEDULING AND REPORTING FOR TEAMS

SALESFORCE.COM, INC., Sa...

1. An apparatus, comprising:a processor; and
a memory device coupled to the processor, the memory device having instructions stored thereon for operating a calendar application, the instructions, in response to execution by the processor, performing operations comprising:
defining a collaboration group within the calendar application, the collaboration group including a plurality of users engaged on a same project;
identifying information based on interactions by the users with the calendaring application about the project, wherein the information includes metadata about the events and additional data, the metadata including quantity of events, types of events, users involved in events, positions of users involved in events, companies of users involved in events, or locations of events, the additional data including content of messages communicated regarding the events, documents associated with the events, or notes associated with the events;
determining a context based on the collected information and using a plural-ML-model (machine learning) based system;
deriving, based on the context, a visualization to inform one or more of the users on a performance of the collaboration group with respect to the project;
comparing the performance of the collaboration group with respect to the project to a performance of a different collaboration group having a different plurality of users, wherein deriving, based on the context, a visualization to inform one or more of the users on a performance of the collaboration group with respect to the project further comprises deriving the visualization based on the comparing; and
presenting the visualization to at least one user of the plurality of users.

US Pat. No. 10,367,648

MULTICAST FORWARDING TABLE ENTRY IN AN OVERLAY NETWORK

Hewlett Packard Enterpris...

1. A method of establishing multicast forwarding table entries in an overlay network, comprising:receiving, by an edge device (ED), a query packet for a multicast group;
recording, by the ED, a port that received the query packet into at least one list in a multicast forwarding table entry corresponding to the multicast group;
if the port that received the query packet is an overlay tunnel port and the query packet includes a forwarding flag, removing, by the ED, the forwarding flag in the query packet to create a modified query packet, and sending the modified query packet to all of overlay tunnel ports in a virtual local area network (VLAN) to which the query packet belongs except the overlay tunnel port that received the query packet, and
wherein the recording, by the ED, the port that received the query packet comprises:
if the port that received the query packet is an overlay tunnel port and the query packet includes a forwarding flag, adding the overlay tunnel port into a list of router ports corresponding to the multicast group; and
if the port that received the query packet is an overlay tunnel port and the query packet does not include a forwarding flag, adding the overlay tunnel port into a list of virtual router ports corresponding to the multicast group.

US Pat. No. 10,367,646

CRYPTOGRAPHIC MATERIAL DISTRIBUTION AND MANAGEMENT

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:receiving, by a cryptographic material management service of a computing resource service provider, a request to make cryptographic material available for use by one or more virtual computing resources of a customer of the computing resource service provider;
obtaining, by the cryptographic material management service, cryptographic material that includes a private key associated with a digital certificate; and
distributing, to a control domain, the cryptographic material for use by the one or more virtual computing resources, wherein the control domain:
launches, for each virtual computing resource of the one or more virtual computing resources, a secure module usable to store the cryptographic material or comprising a cryptoprocessor for performing cryptographic operations using the cryptographic material, the secure module being detectable by the virtual computing resource; and
sends the cryptographic material for storage by the secure module, the cryptographic material being non-exportable to the virtual computing resource and use of the cryptographic material for performing one or more cryptographic operations being programmatically available to the virtual computing resource via an interface.

US Pat. No. 10,367,645

PROOF-OF-WORK FOR SMART CONTRACTS ON A BLOCKCHAIN

International Business Ma...

1. A method, comprising:retrieving, via a device, a predefined set of nonce values that are derived based on predefined data to nonce transformations, obtained over a predefined period of time, on predefined data fields of eligible measurement blocks (EMBs) that are subset of measurement blocks associated with the device on a blockchain;
calculating, via the device, a proof-of-work using the predefined set of nonce values;
storing, via the device, the proof-of-work on the blockchain; and
broadcasting, via the device, and to the blockchain, the proof-of-work as a broadcast message.

US Pat. No. 10,367,644

METHODS FOR MANAGING CONTENT, COMPUTER PROGRAM PRODUCTS AND SECURE ELEMENT

NXP B.V., Eindhoven (NL)...

1. A method for managing content, comprising:generating, by a service provider, an authenticable management script configured to manage content comprised in a secure element;
adding, by the service provider, a management certificate provided by a certificate authority to the authenticable management script, wherein the management certificate comprises a definition of rights of specific management operations permitted to be performed by the service provider using an authenticated management script on content of the secure element; and
providing, by said service provider, the authenticable management script to the secure element, wherein the authenticable management script is authenticated by the secure element, the authenticated management script is verified to have a right to execute specific management operations by the definition of rights on the content of the secure element, and the specific management operations are executed with the authenticated management script by the secure element.

US Pat. No. 10,367,643

SYSTEMS AND METHODS FOR MANAGING ENCRYPTION KEYS FOR SINGLE-SIGN-ON APPLICATIONS

Symantec Corporation, Mo...

1. A computer-implemented method for managing encryption keys for single-sign-on applications, at least a portion of the method being performed by a client computing device comprising at least one processor, the method comprising:receiving, by the client computing device, from an identity service, a notification of a request to access encrypted data on a cloud service, the notification including a session key for encrypting and decrypting a master key for decrypting cloud service keys;
deriving, by the client computing device, based on at least one authentication element received from a user, the master key, wherein the at least one authentication element comprises an authentication factor and wherein deriving the master key comprises:
converting the authentication factor to a cryptographic key utilizing a hash-based key derivation function;
authenticating the user based on the authentication element;
in response to authenticating the user, retrieving a private key for encrypting and decrypting the master key; and
using the private key to decrypt the master key;
decrypting, by the client computing device, using the master key, a cloud service key for decrypting data on the cloud service;
storing, by the client computing device, the master key, encrypted using the session key, in a client key store;
receiving, by the client computing device, from the identity service, an additional notification of an additional request to access encrypted data on an additional cloud service, the notification including the session key;
without again obtaining the authentication element from the user, decrypting, by the client computing device, the master key by using the session key;
decrypting, by the client computing device, using the master key, an additional cloud service key for decrypting data on the additional cloud service; and
performing, by the client computing device, a security action, wherein the security action allows access to the single-sign-on applications and protects the encrypted data from being accessed by the cloud services by storing the encrypted data on the cloud service without the session key.

US Pat. No. 10,367,642

CRYPTOGRAPHIC DEVICE CONFIGURED TO TRANSMIT MESSAGES OVER AN AUXILIARY CHANNEL EMBEDDED IN PASSCODES

EMC IP Holding Company LL...

1. A method comprising:determining multiple sets of passcodes in a first cryptographic device, the multiple sets comprising respective different valid passcodes for possible release in association with a given one of a plurality of epochs;
determining a message to communicate from the first cryptographic device to a second cryptographic device in conjunction with the given epoch;
selecting a particular one of the multiple sets of passcodes based on content of said message;
releasing a passcode associated with the given epoch from the selected set; and
communicating said message over an auxiliary channel embedded in the released passcode, wherein communicating said message comprises transmitting the released passcode from the first cryptographic device to the second cryptographic device.

US Pat. No. 10,367,641

CHAIN OF TRUST IDENTIFICATION SYSTEM AND METHOD

Intel Corporation, Santa...

16. A method to create a chain of trust, the method comprising:using a processor coupled to memory to perform operations comprising:
sending, from a first device in a trusted environment with a second device and a third device, a public test value, determined using a private secret value, directly to the second device;
directly receiving, at the first device outside the trusted environment, a challenge from the third device, the third device in communication with the second device, the third device having received a test value from the second device, and the challenge generated in response to receiving the test value, the test value generated by the second device by modifying the public test value sent to the second device from the first device;
determining a verification to the challenge using the private secret value;
sending directly, from the first device outside the trusted environment, the verification to the second device;
directly receiving, at the first device outside the trusted environment, a confirmation from the third device that the verification was successfully verified by the second device and the third device; and
sending a secure communication to the third device via the second device after receiving the confirmation.

US Pat. No. 10,367,639

GRAPHICS PROCESSOR WITH ENCRYPTED KERNELS

Intel Corporation, Santa...

1. An electronic processing system, comprising:an application processor;
a graphics processor communicatively coupled to the application processor, the graphics processor including a kernel executor, wherein in a specified mode, the kernel executor is to force decryption of any executable kernel loaded on the kernel executor in accordance with a kernel security key;
a display engine communicatively coupled to the graphics processor; and
a security engine communicatively coupled to the graphics processor and the display engine, wherein the security engine is to:
decrypt protected content in accordance with a content title key,
create a display security key,
share the display security key with the graphics processor and the display engine,
create the kernel security key,
retrieve a signed and encrypted kernel that is encrypted according to a first security key, wherein the first security key is different from the kernel security key,
decrypt and verify the signed and encrypted kernel according to the first security key,
encrypt the decrypted and verified kernel in accordance with the kernel security key to generate a newly encrypted kernel that is to be loaded onto the kernel executor, and
share the kernel security key with the graphics processor.

US Pat. No. 10,367,637

MODULAR EXPONENTIATION WITH TRANSPARENT SIDE CHANNEL ATTACK COUNTERMEASURES

QUALCOMM Incorporated, S...

1. A method of implementing security in a modular exponentiation function for cryptographic operations, comprising:obtaining a key as a parameter when the modular exponentiation function is invoked;
ascertaining, within the modular exponentiation function, whether the key is greater than L bits long, where L is a positive integer;
implementing a countermeasure against an attack if the key is greater than L bits long; and
performing one or more exponentiation operations using the key.

US Pat. No. 10,367,636

PHASE CALIBRATION OF CLOCK SIGNALS

Rambus Inc., Sunnyvale, ...

1. A receiver with clock phase calibration, the receiver comprising:a first sampler configured to sample an input signal according to a first sampling phase that is based on a first clock signal and generate first digital data based on the input signal sampled according to the first sampling phase;
a first deserializer configured to deserialize the first digital data generated by the first sampler;
a second sampler configured to sample the input signal according to a second sampling phase that is based on a second clock signal and generate second digital data based on the input signal sampled according to the second sampling phase;
a second deserializer configured to deserialize the second digital data generated by the second sampler;
a multiplexor configured to receive the deserialized first digital data generated by the first sampler and the deserialized second digital data generated by the second sampler and select either the deserialized first digital data or the deserialized second digital data as output data by the receiver based on an output selection signal; and
a phase calibration circuit to generate the output selection signal.

US Pat. No. 10,367,635

SIGNAL TRANSMISSION APPARATUS, CARRIER PHASE RECOVERY APPARATUS AND METHOD

FUJITSU LIMITED, Kawasak...

1. A signal transmission apparatus, comprising:a memory that stores a plurality of instructions;
a processor that couples to the memory and causes the signal transmission apparatus to:
insert at least one phase modulation signal with at least one variable amplitude into data modulation signals, to perform carrier phase recovery at a receiving end, and
transmit transmission signals formed after the at least one phase modulation signal is inserted into the data modulation signals,
wherein the at least one phase modulation signal is among at least two of phase modulation signals inserted into the data modulation signal,
wherein the at least two phase modulation signals have at least one of multiple amplitudes or a single amplitude, and
wherein a phase difference between any two phase modulation signals in the at least phase modulation signals is
where, m and n are non-zero integers.

US Pat. No. 10,367,633

WIRELESS COMMUNICATION

Nokia Technologies Oy, E...

1. An apparatus comprising:at least one processing core configured to:
determine that the apparatus has uplink information to transmit;
cause a transmitter to transmit a beacon in response to the determination that the apparatus has the uplink information to transmit;
make at least one determination concerning a response to the beacon;
transmit information or a request about whether to use a half duplex resource or a full duplex resource based at least in part on the at least one determination concerning the response to the beacon, and
transmit the uplink information using either a full duplex resource or a half duplex resource, wherein the apparatus uses the full duplex resource to transmit the uplink information in response to a determination that no response to the beacon is received; and
a receiver configured to listen for the response to the beacon.

US Pat. No. 10,367,632

CONTROL SIGNALING FOR FLEXIBLE DUPLEX IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for providing flexible duplexing in wireless communications, comprising:communicating with a cell using frequency division duplexing (FDD) to separate an uplink frequency band and a downlink frequency band with the cell;
receiving an indicator from the cell to implement time division duplexing (TDD) on the uplink frequency band; and
communicating with the cell using TDD to separate the uplink frequency band into a plurality of downlink subframes for receiving downlink communications from the cell and a plurality of uplink subframes for transmitting uplink communications to the cell based at least in part on receiving the indicator.

US Pat. No. 10,367,631

FRONT END FOR FULL DUPLEX CABLE MODEM

Cisco Technology, Inc., ...

1. A full-duplex cable modem (CM), comprising:an upstream (US) signal path receiving a digital US input signal and transmitting an analog-converted US signal in a US frequency range to a cable modem termination system (CMTS), wherein the US signal path comprises a first DAC, a first amplifier, and a first low-pass filter;
a downstream (DS) signal path receiving an analog DS signal in a DS frequency range and converting the analog DS signal into a digital DS signal, wherein the DS signal path comprises an analog EC circuit receiving the analog DS signal, a second amplifier, a first ADC, and a digital EC circuit wherein,
the analog EC circuit is configured to subtract from the analog DS signal an analog correction signal derived from the digital US input signal after passing the digital US input signal through a DSP, a second DAC, a second amplifier and a low-pass filter, wherein the analog EC limits ACI, and
the digital EC circuit configured to subtract from the digital DS signal a first digital echo correction signal generated from the analog-converted US signal which is filtered by a first notch filter to eliminate spurious signals in the US frequency range, and subtracting from the digital DS signal a second digital echo correction signal generated from the analog correction signal which is filtered by a second notch filter to eliminate spurious signals in the US frequency range, wherein the digital EC limits ALI, with the digital EC circuit outputting an echo-cancelled digital DS signal; and
an echo cancellation (EC) circuit configured to subtract, from at least one of the analog DS signal and the digital DS signal, a correction signal generated from the digital US input signal or from the analog-converted US signal to generate an echo-cancelled digital DS input signal.

US Pat. No. 10,367,630

METHOD AND DEVICE FOR PERFORMING COMMUNICATION USING PLURALITY OF SUBFRAMES IN TDD-BASED WIRELESS COMMUNICATION SYSTEM

LG Electronics Inc., Seo...

1. A method for performing communication using a plurality of subframes in a time division duplex (TDD)-based wireless communication system, the method comprising:setting, by a first base station (BS), a group by grouping a first configuration, in which at least one downlink symbol and at least one uplink symbol are arranged in each subframe, and a second configuration, in which at least one downlink symbol and at least one uplink symbol are arranged in each subframe, the first configuration and the second configuration being grouped such that a downlink symbol does not overlap with an uplink symbol in a particular symbol period;
transmitting, by the first BS, information indicating the group used for at least one subframe among the plurality of subframes to a terminal; and
transmitting, by the first BS, information indicating a configuration for the at least one subframe to be used for the terminal among the first configuration and the second configuration in the group to the terminal.

US Pat. No. 10,367,629

METHOD FOR ESTIMATING, BY DEVICE USING FDR SCHEME, NON-LINEAR SELF-INTERFERENCE SIGNAL CHANNEL

LG ELECTRONICS INC., Seo...

1. A method of estimating a non-linear self-interference signal channel by an apparatus using a full-duplex radio (FDR) scheme, the method comprising:measuring an intensity of a residual self-interference signal after antenna self-interference cancellation and analog self-interference cancellation;
determining whether a self-interference signal component in a radio frequency (RF) reception (Rx) chain of the apparatus is non-linear;
estimating the non-linear self-interference signal channel using a first sequence set included in a predefined first sequence group if the self-interference signal component in the RF Rx chain of the apparatus is non-linear;
estimating the non-linear self-interference signal channel using a second sequence set included in a predefined second sequence group if the self-interference signal component in the RF Rx chain is not non-linear,
wherein the predefined first sequence group is defined in consideration of a non-linear self-interference signal component in an RF transmission (Tx) chain and an RF Rx chain, and
wherein the predefined second sequence group is defined in consideration of only a non-linear self-interference signal component of the RF Tx chain among non-linear self-interference signal components in the RF Tx chain and the RF Rx chain.

US Pat. No. 10,367,628

METHOD, BASE STATION AND USER EQUIPMENT FOR RADIO COMMUNICATION IN RADIO COMMUNICATION SYSTEM

SONY CORPORATION, Tokyo ...

1. An electronic device, which communicates directly with a base station, comprising:circuitry, configured to:
communicate directly with the base station on a primary component carrier and at least one secondary component carrier in carrier aggregation,
configure a PUCCH on a secondary component carrier in the at least one secondary component carrier in addition to the primary component carrier based on configuration information from the base station,
conduct HARQ feedback on the PUCCH of the secondary component carrier in response to downlink transmissions, and
acquire the configuration information in a Radio Resource Control signaling from the base station.

US Pat. No. 10,367,626

CHANNEL QUALITY INDICATORS

Samsung Electronics Co., ...

1. A method by a base station in a wireless communication system, the method comprising:receiving at least one of first channel quality indicator (CQI) values from a plurality of devices;
determining at least one of second CQI values corresponding to the at least one of first CQI values for the plurality of devices by subtracting a value from each of the at least one of first CQI values, the value being proportional to an elapsed time that is measured between the reception of each of the at least one of first CQI values and the determination of each of the at least one of second CQI values;
selecting at least one of data transmission parameters based on the at least one of second CQI values for each of the plurality of devices;
identifying a first device having a lowest second CQI value among the plurality of devices;
transmitting a first message for requesting an updated first CQI value to the first device; and
receiving the updated first CQI value from the first device.

US Pat. No. 10,367,625

HYBRID BEAMFORMING METHOD AND APPARATUS FOR MULTI-RANK SUPPORT IN WIRELESS ACCESS SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for a first transmitting node to transmit a radio signal to three receiving nodes respectively served by the first transmitting node, a second transmitting node and a third transmitting node in coordination with the second and third transmitting nodes using two radio resource units in a wireless communication system, the method performed by the first transmitting node, the method comprising:configuring a channel state information-reference signal (CSI-RS) resource and a CSI-interference measurement (CSI-IM) resource for a first receiving node of the three receiving nodes;
receiving a recommended precoding matrix index (PMI) for the first transmitting node including a first recommended PMI and a second recommended PMI,
wherein the first recommended PMI is received from the first receiving node and is determined based on information measured on the CSI-RS resource and the CSI-IM resource and the second recommended PMI is received from at least one of the second transmitting node or the third transmitting node after having been respectively reported by second and third receiving nodes of the three receiving nodes;
transmitting a first signal in a first radio resource unit of the two radio resource units based either on the first recommended PMI or on the second recommended PMI; and
muting the first signal in a second radio resource unit of the two radio resource units,
wherein the second transmitting node transmits a second signal to the three receiving nodes in both of the two radio resource units,
wherein the third transmitting node mutes a third signal in the first radio resource unit and transmits the third signal in the second radio resource unit, and
wherein the first recommended PMI indicates a precoding matrix that does not cause an interference to at least one of the second receiving node or the third receiving node.

US Pat. No. 10,367,624

UPLINK MULTI-BITS ACKNOWLEDGEMENT FOR SELF CONTAINED TRANSMISSIONS

QUALCOMM Incorporated, S...

1. A method for communicating feedback in wireless communications, comprising:receiving, at a user equipment (UE) and in a downlink portion of a slot, data communications from a base station, wherein the data communications comprise multiple code blocks received in one or more downlink symbols;
generating, by the UE, one or more feedback bits to provide feedback for the multiple code blocks; and
transmitting, from the UE to the base station and in an uplink portion of the slot, an indication of the one or more feedback bits, wherein transmitting the indication of the one or more feedback bits further comprises:
transmitting, in an uplink symbol of the uplink portion of the slot, at least a portion of the one or more feedback bits; and
transmitting, in a last uplink symbol of the uplink portion of the slot, a single feedback bit to represent at least a remaining portion of the one or more feedback bits.

US Pat. No. 10,367,623

DATA TRAFFIC MANAGEMENT IN VIRTUAL ACCESS POINT (VAP) ENABLED NETWORKS

Cisco Technology, Inc., ...

1. A method comprising:forming, by a supervisory device in a network, a virtual access point (VAP) for a node in the network, wherein a plurality of access points (APs) in the network are mapped to the VAP as part of a VAP mapping, and wherein the node treats the APs in the VAP mapping as a single AP for purposes of communicating with the network;
determining, by the supervisory device, a data traffic management strategy for the node based on traffic associated with the node, wherein the data traffic management strategy is determined by a machine learning model that optimizes one or more objective functions associated with a traffic type of the traffic; and
instructing, by the supervisory device, the APs in the VAP mapping to implement the data traffic management strategy for the node, wherein the data traffic management strategy adjusts the plurality of APs in the VAP mapping and a data rate used by the APs, based on the optimization of the one or more objective functions associated with the traffic type.

US Pat. No. 10,367,621

FOUNTAIN HARQ FOR RELIABLE LOW LATENCY COMMUNICATION

QUALCOMM Incorporated, S...

1. A method of wireless communication comprising:transmitting a data block using a first set of resources based at least in part on a low latency operational mode;
transmitting a redundancy version of the data block using a second set of resources based at least in part on the low latency operational mode, the redundancy version of the data block being transmitted prior to determining whether a feedback message is received for the data block;
receiving an augmented feedback message that comprises feedback information and a transmission scheme adjustment request, based at least in part on a number of the redundancy versions received prior to successful decoding of the data block; and
adjusting a transmission scheme based at least in part on the feedback information and the transmission scheme adjustment request.

US Pat. No. 10,367,618

TECHNIQUES FOR TRANSMITTING POSITIONING REFERENCE SIGNALS IN AN UNLICENSED RADIO FREQUENCY SPECTRUM BAND

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:generating a positioning reference signal (PRS);
configuring the PRS in at least one downlink subframe of a clear channel assessment (CCA) frame of an unlicensed radio frequency spectrum band;
performing a CCA procedure for the CCA frame of the unlicensed radio frequency spectrum band;
determining that the CCA procedure was successful; and
transmitting the PRS in the at least one downlink subframe across a plurality of frequencies of the unlicensed radio frequency spectrum band based at least in part on the determination that the CCA procedure was successful, wherein the transmitting occupies at least a threshold percentage of a bandwidth of the unlicensed radio frequency spectrum band associated with occupancy of the unlicensed radio frequency spectrum band.

US Pat. No. 10,367,617

METHOD, BASE STATION AND USER EQUIPMENT FOR TRANSMISSION

Telefonaktiebolaget LM Er...

1. A method for transmission in a User Equipment, comprising:detecting a discovery reference signal based on a first window comprising two or more channels, at least one of the two or more channels having a first priority level, the discovery reference signal detected based on the first priority level; and
determining a second window based at least partly on a resource block for reception of the discovery reference signal.

US Pat. No. 10,367,616

DYNAMIC SOUNDING REFERENCE SIGNAL SCHEDULING

QUALCOMM Incorporated, S...

1. A method of wireless communication comprising:receiving signaling aperiodically, at a user equipment (UE) via a control channel, the signaling comprising a sounding reference signal (SRS) grant message from a base station, the SRS grant message comprising an indication of SRS parameters that include a timing component, wherein the timing component is associated with a physical uplink transmission, and wherein the SRS parameters comprise a repetition parameter associated with the one or more SRS transmissions;
determining, from the received SRS grant message, one or more symbol locations for making one or more SRS transmissions; and
transmitting, to the base station on the one or more symbol locations, one or more SRS transmissions.

US Pat. No. 10,367,614

METHOD AND APPARATUS FOR MU RESOURCE REQUEST

Marvell World Trade Ltd.,...

1. An apparatus for wireless communication, comprising:a transceiver configured to transmit and receive wireless signals; and
a processing circuit configured to:
configure a field within a data unit for buffer information report;
determine a first scale factor for scaling a first value indicative of buffered traffic of a first category, and a second scale factor for scaling a second value indicative of buffered traffic of a category;
configure the field to include the first scale factor with the first value and the second scale factor with the second value; and
provide the data unit to the transceiver for transmitting to another apparatus that allocates resources for transmission between the two apparatuses.

US Pat. No. 10,367,612

PROCESS VARIABLE TRANSMITTER WITH SELF-LEARNING LOOP DIAGNOSTICS

ROSEMOUNT INC., Shakopee...

1. A two-wire process variable transmitter for use in an industrial process, comprising:a process variable sensor configured to sense a process variable of a process fluid of the industrial process;
output circuitry configured to provide an output on a two-wire process control loop which is related to the sensed process variable;
terminal voltage measurement circuitry configured to measure a terminal voltage of the process variable transmitter, the terminal voltage comprising a voltage measured across an electrical connection of the two-wire process variable transmitter to the two-wire process control loop;
a microprocessor configured to:
use loop current values for loop currents set in response to the sensed process variable and measured terminal voltages to set coefficients of a polynomial equation which relates loop current and terminal voltage;
perform loop diagnostics on the two-wire process control loop based upon a determined loop current, a further measured terminal voltage and upon the coefficients of the polynomial.

US Pat. No. 10,367,609

ERROR CORRECTION FOR DATA PACKETS TRANSMITTED USING AN ASYNCHRONOUS CONNECTION-LESS COMMUNICATION LINK

QUALCOMM Incorporated, S...

1. A method of wireless communication for a first device configured for wireless communications over a short-range wireless area network with a second device configured for wireless communications, comprising:receiving, by the first device over the short-range wireless area network, a retransmission of a data packet from the second device when a previous transmission of the data packet is unacknowledged by the first device, the data packet including at least a packet header and a payload;
maintaining, by the first device, each transmission of the data packet up to a threshold number of the maintained data packets when the data packet is unacknowledged by the first device;
applying, by the first device, a packet header mask to the packet header in each of the maintained data packets when the threshold number of maintained data packets is reached;
determining, by the first device, if the packet header in each of the maintained data packets is the same after the packet header mask is applied;
determining, by the first device, if a number of differences between payloads in each paired combination of the maintained data packets meets a threshold criteria when it is determined that the packet header in each of the maintained data packets is the same after the packet header mask is applied; and
performing, by the first device, a bit-wise majority vote on the payload on corresponding payload bits of the maintained data packets to determine an error-corrected data packet when it is determined that the number of differences between the payloads for each paired combination of the maintained data packets does not meet the threshold criteria, the error-corrected data packet including a majority-voted payload.

US Pat. No. 10,367,608

WIRELESS COMMUNICATION CHANNEL SCAN

Hewlett Packard Enterpris...

9. A method comprising:receiving, by an access point (AP), an instruction to scan a wireless communication channel, wherein the wireless communication channel is different than the operating channel of the AP;
in response to the reception of the instruction to scan, transmitting, by the AP, a Clear To Send (CTS)-to-self frame on the operating channel of the AP, wherein the CTS-to-self frame includes a basic service set (BSS) color associated with the AP and a network allocation vector (NAV) set to a scan time;
subsequent to the transmission of the CTS-to-self frame, scanning, by the AP, on the wireless communication channel for other APs and client devices operating on the wireless communication channel; and
deferring, by the AP, data transmissions received from client devices, in response to the data transmission including the BSS color associated with the AP, during the scanning of the wireless communication channel.

US Pat. No. 10,367,607

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

LG ELECTRONICS INC., Seo...

1. An apparatus for receiving broadcast signals, the apparatus comprising:a tuner to receive the broadcast signals carrying at least one signal frame;
a demodulator to demodulate the broadcast signals by an Orthogonal Frequency Division Multiplex (OFDM) scheme;
a time deinterleaver to de-interleave data in the at least one signal frame based on a convolutional de-interleaver and a block de-interleaver,
the convolutional de-interleaver to de-interleave the data in the at least one signal frame,
the block de-interleaver to write the convolutional de-interleaved data to a memory based on a Time Interleaving (TI) block including a number of actual Forward Error Correction (FEC) blocks having the convolutional de-interleaved data, and to read the TI block from the memory based on addresses for the memory and position information for one or more virtual FEC blocks,
wherein a number of virtual FEC blocks is equal to a difference between the number of actual FEC blocks of the TI block and a maximum number of FEC blocks which is obtained based on signaling data in the at least one signal frame; and
a decoder to decode the time-de-interleaved data.

US Pat. No. 10,367,606

TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,605

HIGH SPEED INTERCONNECT SYMBOL STREAM FORWARD ERROR-CORRECTION

INTEL CORPORATION, Santa...

1. An apparatus, comprising:a processor circuit; and
a forward-error correction (FEC) component executable by the processor circuit, the FEC component to:
receive a high-speed interconnect symbol stream having a plurality of symbols;
determine FEC parity bits based in part on the plurality of symbols of the symbol stream;
generate a FEC correctable symbol stream based on the plurality of symbols and the FEC parity bits.

US Pat. No. 10,367,604

ENCODING VARIABLE LENGTH SYMBOLS TO ENABLE PARALLEL DECODING

International Business Ma...

1. A method implemented by an information handling system, the method comprising:separating a symbol stream into a plurality of symbol sub-streams, wherein each of the plurality of symbol sub-streams comprise a plurality of symbols having one or more different symbol lengths;
partitioning, on each of the plurality of symbol sub-streams, each of a plurality of symbol sets into a plurality of fixed width data chunks, wherein a fixed width size of each of the plurality of fixed width data chunks is based on a longest one of the plurality of different symbol lengths, and wherein the partitioning generates one or more boundaries between each of the plurality of fixed width data chunks;
identifying one or more locations of one or more of the plurality of symbols having the or more different symbol lengths relative to at least one of the one or more boundaries;
creating symbol boundary information corresponding to the identified one or more locations;
combining the plurality of fixed width data chunks into a multiplexed bit stream based on the symbol boundary information; and
providing the multiplexed bit stream to a destination system.

US Pat. No. 10,367,603

METHOD AND APPARATUS FOR ADJUSTING A MODE OF COMMUNICATION IN A COMMUNICATION NETWORK

1. A method, comprising:detecting, by a first waveguide system comprising a processor, an impairment, wherein the impairment is a physical discontinuity present on a surface of a first transmission medium that adversely affects a propagation of electromagnetic waves along the first transmission medium;
adjusting, by the first waveguide system, a mode of communication for transmitting or receiving the electromagnetic waves guided by the first transmission medium to mitigate an adverse effect of the impairment; and
notifying, by the first waveguide system, a second waveguide system of the adjusting of the mode of communication for transmitting or receiving the electromagnetic waves.

US Pat. No. 10,367,602

DATA MODULATION METHOD FOR IEEE 802.11 DEVICES TO GENERATE LOW FREQUENCY SIGNALS

1. A method of transmitting information, the method comprising:receiving, by a transceiver with a transmitter and a receiver, binary data to be transmitted to one or more receivers and one or more identifiers of the one or more receivers, said transmitter being a high-rate transmitter compliant with the IEEE 802.11 communication standard and said one or more receivers capable of detecting said binary data generated from IEEE 802.11 frames;
encapsulating, by the transmitter, the one or more identifiers of the one or more receivers in a first field of a low rate (LR) frame and binary data, to be transmitted to one or more receivers, in a second field of the LR frame, wherein the LR frame is used to encapsulate said binary data and said identifiers at a rate slower than the data rate of the IEEE 802.11 frame transmission, and the LR frame is composed of sequential transmission of high rate IEEE 802.11 frames;
encoding, by the transmitter, the LR frame based on a line encoding method to generate a waveform that includes a pattern alternating between a first value (ON) and a second value (OFF); and
transmitting, by the transmitter, a signal corresponding to an On-Off Keying (OOK)-modulated signal,
wherein the first value (ON) of the transmitted signal includes two frequency components, having a first frequency component lower than a second frequency component, and the second value (OFF) of the transmitted signal contains no transmissions;
wherein the second frequency component is used to generate the first value (ON) of the transmitted signal with the transmission of a certain number of successive null data packets (NDP), control, data or management frames defined in the IEEE 802.11 standard, that are all of a same type, have a certain duration, and are separated by regular time intervals; and
wherein said certain number, type, duration and time separation of the successive NDP, control, data or management frames defined in the IEEE 802.11 standard are chosen to determine the first frequency component.

US Pat. No. 10,367,601

METHOD AND DEVICE FOR PROVIDING PIPELINE REORDERING OF ENCODER PARAMETER CONTROLLERS FOR AN ENCODER

Google LLC, Mountain Vie...

1. A method of operating an encoder in a communication device comprising:determining, by control logic, when a network condition has changed by evaluating network condition data;
based on a detected network condition change, reordering an encoder parameter controller execution sequence for a plurality of encoder parameter controllers in the communication device from a prior order;
generating encoder control parameters from the reordered plurality of encoder parameter controllers wherein an encoder parameter determination from a prior encoder parameter controller is used as a decision input for a subsequent encoder parameter controller; and
encoding data, by the encoder, using the generated encoder control parameters from the reordered plurality of encoder parameter controllers.

US Pat. No. 10,367,600

FORWARD ERROR CORRECTION WITH CONTRAST CODING

CIENA CORPORATION, Hanov...

1. A method for transmission of information bits over a communications channel between a transmitter device and a receiver device, the method comprising:at the transmitter device
applying forward error correction (FEC) encoding to a set of information bits to generate first bits consisting of N classes of bits, wherein N?2, and wherein each class is associated with a distinct information rate;
applying contrast encoding to the first bits to generate second bits, the second bits comprising at least one group consisting of second bits that are dependent on the first bits of at least two of the N classes;
mapping the second bits to symbols; and
transmitting a signal representative of the symbols over the communications channel;
at the receiver device
detecting received symbols from a signal received over the communications channel;
decoding estimates of the second bits from the received symbols;
applying contrast decoding to the estimates of the second bits to generate estimates of a first class of the first bits, wherein the contrast decoding is the inverse of the contrast encoding applied at the transmitter device;
applying a first FEC decoding operation to the estimates of the first class to generate first error-free bits; and
using the contrast decoding and the first error-free bits to generate estimates of a second class of the first bits.

US Pat. No. 10,367,591

OPTICAL DRIVER WITH ASYMMETRIC PRE-EMPHASIS

XILINX, INC., San Jose, ...

1. An optical driver circuit, comprising:an input terminal to receive an input signal;
an output terminal to generate a level-shifted output signal;
a pull-up circuit including an input node responsive to the input signal, further including an output node inductively coupled to the output terminal, and configured to adjust rising edge transitions in the level-shifted output signal based on a first control signal;
a pull-down circuit including an input node responsive to the input signal, including an output node inductively coupled to the output terminal, and configured to adjust falling edge transitions in the level-shifted signal based on a second control signal; and
an inductive circuit comprising:
a first inductor coupled between the output node of the pull-up circuit and the output terminal of the optical driver circuit; and
a second inductor coupled between the output node of the pull-down circuit and the output terminal of the optical driver circuit.

US Pat. No. 10,367,590

CONCURRENTLY PERFORMING ATTRIBUTE-DEPENDENT OPERATIONS ON OPTICAL SIGNALS

Hewlett Packard Enterpris...

1. A method comprising:providing, to a passive linear optical circuit, a first plurality of signals having a first optical property and encoding a first vector;
providing, to the passive linear optical circuit, a second plurality of signals having a second optical property and encoding a second vector, wherein the first optical property is different from the second optical property;
performing, via the passive linear optical circuit, a first attribute-dependent operation on the first plurality of signals to perform a first matrix multiplication operation on the first vector; and
concurrent with the first attribute-dependent operation, performing, via the passive linear optical circuit, a second attribute-dependent operation on the second plurality of signals to perform a second matrix multiplication operation on the second vector, wherein the first matrix multiplication operation and the second matrix multiplication operation are different based on the first optical property being different from the second optical property.

US Pat. No. 10,367,586

METHODS AND APPARATUS FOR LOW-LOSS RECONFIGURABLE OPTICAL QUADRATURE AMPLITUDE MODULATION (QAM) SIGNAL GENERATION

Juniper Networks, Inc., ...

1. An apparatus, comprising:a quadrature amplitude modulation (QAM) optical modulator including a first phase modulator, a second phase modulator, a tunable optical coupler, and an optical combiner, each of the first phase modulator and the second phase modulator operatively coupled to the tunable optical coupler and the optical combiner,
the tunable optical coupler configured to split a light wave at an adjustable power splitting ratio to produce a first split light wave and a second split light wave,
the first phase modulator configured to modulate the first split light wave in response to a first multi-level electrical signal to produce a first modulated light wave such that the first modulated light wave when represented in a constellation diagram includes a first plurality of constellation points on a first circle,
the second phase modulator configured to modulate the second split light wave in response to a second multi-level electrical signal to produce a second modulated light wave such that the second modulated light wave when represented in the constellation diagram includes a second plurality of constellation points on a second circle, a set of modulation instructions of the second phase modulator being determined based on at least one cross point of the first circle and the second circle when represented in the constellation diagram,
the optical combiner configured to combine the first modulated light wave and the second modulated light wave to generate a QAM optical signal.

US Pat. No. 10,367,583

DRIVER CIRCUIT, OPTICAL TRANSMISSION MODULE AND OPTICAL TRANSMISSION DEVICE

FUJITSU LIMITED, Kawasak...

1. A driver circuit having a differential input and a single-ended output, the driver circuit comprising:a variable current source configured to include:
a first current source coupled to a first input node to which a first signal is input from an external,
a second current source coupled to a second input node to which a second signal as an inversion of the first signal is input from the external,
a first bypass circuit coupled between the first current source and the first input node, the first bypass circuit being switched according to the second signal, and
a second bypass circuit coupled between the second current source and the second input node, the second bypass circuit being switched according to the first signal; and
a terminal circuit configured to be terminated for an optical device driven by a drive signal according to the first signal, the drive signal being output from an output node coupled between the terminal circuit and the variable current source.

US Pat. No. 10,367,581

NOTIFICATION DEVICE, NOTIFICATION METHOD, AND NON-TRANSITORY RECORDING MEDIUM

CASIO COMPUTER CO., LTD.,...

14. A notification method, comprising:an acquisition step of successively acquiring images;
a search step of acquiring a predetermined image region corresponding to a detection target from the successively acquired images;
a notification step of providing a notice, when the predetermined image region is acquired in the search step, as to whether the predetermined image region is a region of a light signal emitted by a transmission device based on comparing optical change in brightness and/or hue in the predetermined image region with search rules defining signal formats of the light signal, the signal formats having predetermined time periods, each of the signal formats including a light-non-emission period and light-emission periods in every predetermined time period;
wherein in the notification step, a determination result in the determination step is notified,
wherein in the notification step, the controller displays the notice in a display, and
wherein in the notification step, the display provides the notice as to whether the predetermined image region is a region of information transmitted by the transmission device of the visible light communication system by means of light emission in a superimposed manner of displaying texts on the acquired images.

US Pat. No. 10,367,580

REVERSE-DIRECTION TAP (RDT), REMOTE DIAGNOSTIC MANAGEMENT TOOL (RDMT), AND ANALYSES USING THE RDT AND THE RDMT

Futurewei Technologies, I...

1. A hybrid fiber-coaxial (HFC) network comprising:a headend;
a first amplifier coupled to the headend;
a second amplifier; and
a tap coupled to the first amplifier and the second amplifier so that the first amplifier is positioned between the headend and the tap and the tap is positioned between the first amplifier and the second amplifier, the tap is configured to couple to a plurality of cable modems (CMs), and the tap comprises:
a diagnostic forward (DF) port configured to:
receive a downstream signal from the first amplifier, and
inject an upstream test signal in an upstream direction for analysis at the headend of a first fault occurring upstream from the tap; and
a diagnostic reverse (DR) port configured to:
receive an upstream signal from the second amplifier, and
inject a downstream test signal in a downstream direction for analysis at one of the CMs of a second fault occurring downstream from the tap.

US Pat. No. 10,367,579

DEVICE AND METHOD OF HANDLING COMMUNICATION OPERATION

HTC Corporation, Taoyuan...

1. A base station (BS) of a network of handling a communication operation, comprising:a storage device; and
a processing circuit, coupled to the storage device, wherein the storage device stores, and the processing circuit is configured to execute instructions of:
transmitting a first duration of a first type subframe to a communication device;
transmitting a multiplexing scheme for the first type subframe and a second type subframe to the communication device, wherein the first duration of the first type subframe is shorter than a second duration of the second type subframe, and the second type subframe is a normal subframe defined in the 3rd Generation Partnership Project (3GPP);
determining a third duration of a third type subframe, when the second duration of the second type subframe is not an integral multiple of the first duration of the first type subframe, wherein the third duration of the third type subframe is different from the first duration of the first type subframe and is different from the second duration of the second type subframe;
transmitting the third duration of the third type subframe to the communication device; and
performing the communication operation with the communication device in a plurality of first type subframes in at least one third type subframe according to the multiplexing scheme via a physical channel.

US Pat. No. 10,367,577

SYSTEMS AND METHODS FOR BEACON DETECTION INFRASTRUCTURES

Cable Television Laborato...

1. A communication system, comprising:an earth station configured to receive a downlink transmission from a satellite and transmit an uplink transmission to the satellite;
a server in operable communication with the earth station;
a beacon detector in operable communication with the server;
an access point configured to operate within a proximity of the earth station; and
a beacon transmitter disposed within close proximity to the access point, the beacon transmitter configured to transmit a beacon signal to one or more of the server and the beacon detector, wherein the beacon signal uniquely identifies the access point,
wherein the server is configured to implement a measurement-based protection scheme with respect to at least one of the downlink transmission and the uplink transmission.

US Pat. No. 10,367,576

SYSTEM AND METHOD FOR DEMONSTRATION AND EVALUATION OF A NANOSATELLITE COMMUNICATION CONSTELLATION

The United States of Amer...

1. A system comprising:a computing device configured to implement a central user ground module that enables a user to emulate a plurality of central user ground nodes having fixed locations and that transmit and receive messages from at least one nanosatellite (nanosat);
a second computing device configured to implement a remote user ground module that enables a user to emulate a plurality of remote user ground nodes that do not have fixed locations and that transmit and receive messages from at least one nanosat, wherein each of the central user ground module and the remote user ground module include an orbit simulator configured to provide scenario data for a specified nanosat constellation, wherein the scenario data includes contact time windows; and
at least one additional computing device configured to implement a nanosat space module that emulates a nanosat, wherein the nanosat transmits and receives messages to and from the ground nodes.

US Pat. No. 10,367,575

HIGH POINTING ACCURACY SPACECRAFT

13. A method comprising:receiving, with a tracking receiver of a spacecraft payload subsystem, by way of an input multiplexer, multiplexed signals from a plurality of pseudo-monopulse (PSM) couplers, each PSM coupler being disposed proximate to a respective tracking feed element; and
adjusting the pointing of a plurality of antenna reflectors, responsive to the received multiplexed signals; wherein:
the spacecraft payload subsystem includes
the tracking receiver
an input multiplexer;
an antenna pointing mechanism (APM) controller; and
the plurality of antenna reflectors, each antenna reflector mechanically coupled with a respective APM, and illuminated by a respective tracking feed element, each respective tracking feed element being configured to receive a respective uplink beacon signal from the ground by way of one of the antenna reflectors and being coupled by way of a respective one of the plurality of PSM couplers and the input multiplexer to the tracking receiver;
the tracking receiver is configured to receive the multiplexed signals from the PSM couplers by way of the input multiplexer and output corresponding pointing error information to the APM controller;
the APM controller is configured to send commands to one or more of the APMs; and
each APM is configured to point a respective antenna reflector in response to the commands,
wherein each PSM coupler is disposed proximate to a respective tracking feed element, wherein each PSM coupler is communicatively coupled with a respective tracking feed element by a waveguide having a run length less than ten feet.

US Pat. No. 10,367,572

REPEATER SYSTEM AND METHOD

Andrew Wireless Systems G...

1. A repeater system, comprising:a host unit configured to:
receive a plurality of downlink signals from multiple communication sources located outside of a coverage area and combine the plurality of downlink signals into a combined downlink signal for transmission to one or more remote units, and
receive a combined uplink signal from the one or more remote units and produce a plurality of uplink signals from the combined uplink signal for transmission to the multiple communication sources; and
the one or more remote units communicatively coupled to the host unit, the one or more remote units configured to:
receive the combined downlink signal from the host unit and modulate the combined downlink signal according to at least one modulation scheme to produce a downlink RF communication signal for transmission into a coverage area to a plurality of user terminals located within the coverage area, and
receive uplink RF communication signals, from the plurality of user terminals located within the coverage area, and demodulate the received uplink RF communication signals to produce the combined uplink signal from the uplink RF communication signal for transmission to the host unit; and
multiplex modulated signals produced from the combined downlink signal to form the downlink RF communication signal for transmission into the coverage area;
wherein a first of the plurality of user terminals communicates with a different one of the multiple communication sources than a second of the plurality of user terminals.

US Pat. No. 10,367,570

ELECTRONIC DEVICES HAVING PRINTED CIRCUITS FOR ANTENNAS

Apple Inc., Cupertino, C...

1. An electronic device comprising:a substrate;
a radio-frequency transceiver;
control circuitry configured to generate control signals;
an antenna that includes an antenna resonating element arm, an antenna ground, and an antenna feed coupled between the antenna resonating element arm and the antenna ground;
a tunable component coupled to the antenna and configured to tune a frequency response of the antenna;
a flexible printed circuit; and
a connector that mechanically secures the flexible printed circuit to the substrate and that is electrically coupled to the radio-frequency transceiver and the control circuitry, wherein the flexible printed circuit comprises a radio-frequency transmission line coupled between the antenna feed and the connector and a control signal path coupled between the tunable component and the connector, the connector is configured to convey the radio-frequency signals between the radio-frequency transceiver and the radio-frequency transmission line on the flexible printed circuit, and the connector is configured to convey the control signals from the control circuitry to the control signal path on the flexible printed circuit.

US Pat. No. 10,367,569

PHASE ARRAY RECEIVER

ELECTRONICS AND TELECOMMU...

1. A phase array receiver comprising:a plurality of antennas configured to receive RF signals;
a plurality of low-noise amplifiers configured to receive the RF signals from the plurality of antennas and amplify the RF signals to generate a plurality of RF amplification signals;
a plurality of phase shifters configured to adjust a gain and a phase of the plurality of RF amplification signals to generate a plurality of RF phase adjustment signals;
a plurality of transconductors configured to convert the plurality of RF phase adjustment signals into a plurality of RF current signals based on a gain control signal;
a passive frequency mixer configured to receive a sum of the plurality of RF current signals and convert a frequency of the plurality of RF current signals to generate a mixed current signal; and
a transimpedance amplifier configured to convert the mixed current signal into a mixed voltage signal.

US Pat. No. 10,367,568

DETERMINING PRECODING COEFFICIENTS FOR FRONTHAUL LINKS IN A CLOUD RADIO ACCESS NETWORK

1. A baseband unit device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
determining a group of beamforming coefficients for a stream of data, wherein the group of beamforming coefficients comprises respective subgroups of beamforming coefficients that correspond to respective basis vectors;
determining spectral efficiencies associated with portions of the respective subgroups of beamforming coefficients;
selecting a portion of the respective subgroups of beamforming coefficients with a threshold spectral efficiency of the portions of the respective subgroups of the beamforming coefficients to add to a reduced size group of beamforming coefficients; and
transmitting the reduced size group of beamforming coefficients to a remote radio unit device to facilitate digital beamforming of a transmission to occur at the remote radio unit device.

US Pat. No. 10,367,566

TECHNIQUES FOR NON-COHERENT JOINT TRANSMISSIONS IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for wireless communication, comprising:receiving a communication configuration for reception of a first portion of a non-coherent joint transmission (NCJT) from a first transmission point (TP) and a second portion of the NCJT from the first TP or a second TP, wherein the communication configuration is received in a single downlink control information (DCI) transmission; and
receiving, based at least in part on the communication configuration, the first portion as a first codeword of a single-user multiple-input multiple-output (SU-MIMO) transmission and the second portion as a second codeword of the SU-MIMO transmission,
wherein the DCI transmission comprises a field to indicate antenna ports, a scrambling ID, and a number of layers for each of the first codeword and the second codeword that:
provides a same structure as a legacy SU-MIMO DCI transmission when only the first TP or the second TP is a serving cell; and
provides support for any available number of spatial layers for the first codeword and the second codeword when both the first TP and the second TP are serving cells.

US Pat. No. 10,367,564

CHANNEL STATE INFORMATION FEEDBACK METHOD AND RELATED DEVICE FOR FD MIMO SYSTEM

China Academy of Telecomm...

1. A method for feeding back channel state information in a Full-Dimension, FD, Multiple input Multiple Output, MIMO, system, the method comprising:receiving, by a terminal, a set of Channel State Information, CSI, feedback configurations, and configuration information for feeding back CSI based upon the set of CSI feedback configurations, indicated by a base station; and
measuring and feeding back, by the terminal, CSI according to the set of CSI feedback configurations, and the configuration information;
wherein the set of CSI feedback configurations comprises at least one CSI feedback configuration, and the CSI feedback configuration is a downlink signal configuration for measuring and feeding back downlink CSI;
wherein the configuration information comprises indication information of a downlink channel information item to be fed back over a Physical Uplink Control Channel, PUCCH;
wherein the indication information of a downlink channel information item to be fed back over a PUCCH is:
first indication information to be fed back over a PUCCH, which comprises positional information and CSI corresponding to the optimum CSI feedback configuration in the set of CSI feedback configurations; or
second indication information to be fed back over a PUCCH, which comprises positional information and CSI corresponding to a CSI feedback configuration, specified by the base station, in the set of CSI feedback configurations; or
third indication information to be fed back over a PUCCH, which comprises positional information and CSI corresponding to each CSI feedback configuration in the set of CSI feedback configurations.

US Pat. No. 10,367,555

PRECODING METHOD, PRECODING DEVICE

Sun Patent Trust, New Yo...

1. A transmission apparatus comprising:encoding circuitry, which in operation, encodes a transmission data sequence to two encoded data sequences that are to be decoded by a reception apparatus;
modulation circuitry, which in operation, modulates the two encoded data sequences to two modulated symbol sequences;
precoding circuitry, which in operation, precodes the two modulated symbol sequences by using a precoding matrix expressed by Math. 1 to generate two precoded symbol sequences;

Orthogonal Frequency Division Multiplexing (OFDM) signal generation circuitry, which in operation, inverse fourier transforms the two precoded symbol sequences to two OFDM signals; and
transmission circuitry, which in operation, transmits the two OFDM signals from different antennas, wherein
in Math. 1, i is an integer that is zero or greater and varies for each modulated symbol, and ?21 satisfies Math. 2,

US Pat. No. 10,367,553

TRANSMISSION SCHEME FOR WIRELESS COMMUNICATION SYSTEMS

MEDIATEK INC., HsinChu (...

1. A method comprising:transmitting scheduling information from a serving base station to a user equipment (UE) for downlink transmission in a wireless communication network;
transmitting a UE-specific reference signal applied with a first precoding matrix, wherein the UE-specific resource signal is a demodulation reference signal (DMRS) configured for the UE and transmitted over predefined DMRS resource elements (REs); and
transmitting a data signal over data REs applied with a second precoding matrix, wherein the second precoding matrix can be represented by the first precoding matrix multiplied by a co-phasing cycling matrix, and wherein a ratio of an energy per resource element (EPRE) of data REs to an EPRE of the DMRS REs is 0 dB.

US Pat. No. 10,367,552

SIGNAL GENERATION METHOD AND SIGNAL GENERATION DEVICE

SUN PATENT TRUST, New Yo...

1. A broadcast signal generation method by a broadcast apparatus, comprising:applying a coding to a set of data bits to generate a first coded signal and a second coded signal;
applying a precoding to the first coded signal and the second coded signal according to a determined matrix F to generate a first precoded signal and a second precoded signal; and
applying a phase change to the second precoded signal to generate a second phase-changed signal, the phase change not being applied to the first precoded signal,,
wherein
the first precoded signal and the second phase-changed signal are outputted to a plurality of transmission antennas to be transmitted on a same frequency band and at a same time as broadcast signals,
the phase change uses a phase change value sequentially selected from among N phase change values, N being an integer greater than two and greater than the number of coded signals, and each of the N phase change values being selected at least once within a determined period, and
a difference between two adjacent phase change values of the N phase change values is 2?/N, the two adjacent phase change values being adjacent to one another in an arrangement order of data included in the second precoded signal.

US Pat. No. 10,367,544

APPARATUS AND METHOD FOR SEARCHING FOR CELL IN WIRELESS TERMINAL

Samsung Electronics Co., ...

1. A wireless terminal in a weak electric-field environment comprising:a plurality of antennas comprising a primary antenna and at least one secondary antenna; and
a communication processor (CP) configured to
select one of the plurality of antennas to measure a quality of signal with respect to at least one cell around the wireless terminal in a weak electric-field environment, based on whether at least one from among the at least one secondary antenna is in a driving state and whether a finger of a rake receiver has been allocated, and
perform a cell search through the selected one of the plurality of antennas,
wherein the driving state is a state in which a signal received through the at least one from among the at least one secondary antenna is delivered to the rake receiver.

US Pat. No. 10,367,533

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,532

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,531

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,367,529

LIST DECODE CIRCUITS

Hewlett Packard Enterpris...

1. A device, comprising:a first polynomial evaluation circuit to evaluate a first polynomial output from a Berlekamp-Massey algorithm for a plurality of values in a finite field in parallel, each of the plurality of values in the finite field corresponding to a possible error location in an error correction codeword;
a second polynomial evaluation circuit to evaluate a second polynomial output from the Berlekamp-Massey algorithm for the plurality of values in the finite field in parallel, the second polynomial evaluation circuit to evaluate the second polynomial output and the first polynomial evaluation circuit to evaluate the first polynomial output in parallel;
a field division circuit to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm by dividing outputs from the evaluation of the first polynomial output by outputs from the evaluation of the second polynomial output for each value in the finite field in parallel;
a discrepancy filter circuit to identify, as potentially valid discrepancy values, speculative discrepancy values that occur in the generated plurality of speculative discrepancy values a quantity of times equal to a quantity of correctable errors in the error correction codeword; and
an error locator polynomial (ELP) circuit to generate an ELP using the potentially valid discrepancy values and the first and second polynomial outputs.

US Pat. No. 10,367,517

ANALOG TO DIGITAL CONVERSION APPARATUS AND ANALOG TO DIGITAL CONVERTER CALIBRATION METHOD OF THE SAME

REALTEK SEMICONDUCTOR COR...

1. An analog to digital conversion apparatus, comprising:an analog to digital converter (ADC) comprising;
a capacitor array configured to receive an input signal to perform a capacitor-switching to generate a capacitor array output signal;
a comparator configured to compare the capacitor array output signal and a comparing signal to generate a digital code output result; and
a control circuit configured to control the capacitor-switching according to the digital code output result;
a linearity calculating module configured to generate a linearity related parameter according to the digital code output result; and
a calibration module configured to generate a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

US Pat. No. 10,367,516

JITTER REDUCTION TECHNIQUES WHEN USING DIGITAL PLLS WITH ADCS AND DACS

Analog Devices Global, H...

1. A digital phase lock loop (DPLL) error correction circuit, the DPLL error correction circuit comprising:a primary analog-to-digital converter (ADC) circuit configured to sample an input signal and produce a digital output signal representative of the input signal;
a digital phase lock loop (DPLL) circuit configured to provide a sampling clock signal to the primary ADC circuit;
a timing error calculation circuit operatively coupled to the DPLL circuit and configured to determine a timing error representative of error in the sampling clock signal, wherein the timing error calculation circuit includes:
a slope calculation circuit configured to generate a digital slope signal representative of slope of the input signal; and
a sampling error circuit configured to determine a sampling error representative of sampling error by the primary ADC circuit using the digital slop signal and the sampling clock signal; and
an output circuit operatively coupled to the primary ADC circuit and the timing error calculation circuit and configured to adjust the digital output signal using the determined timing error.

US Pat. No. 10,367,515

DIGITAL-TO-ANALOG CONVERTER (DAC) WITH PARTIAL CONSTANT SWITCHING

Maxlinear, Inc., Carlsba...

1. A digital-to-analog converter (DAC) circuit, comprising:a first DAC element configured to receive a first data stream and generate a first DAC output, wherein the first data stream comprises one or more most significant bits (MSBs) from a digital input;
a second DAC element configured to receive a second data stream and generate a second DAC output, wherein the second data stream comprises one or more least significant bits (LSBs) from the digital input; and
a controller circuit operable to select either the first DAC element or the second DAC element to perform a digital to analog conversion, wherein the selection is based on a first clock and on a function of the digital input.

US Pat. No. 10,367,513

SUPPRESSION OF NOISE UP-CONVERSION MECHANISMS IN LC OSCILLATORS

International Business Ma...

1. A phase-locked loop (PLL) circuit comprising:an oscillator;
a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator; and
a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator,
wherein the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and wherein the bias voltage from the bias optimizer is set to the local minimum.

US Pat. No. 10,367,512

PRE-DELAY ON-DIE TERMINATION SHIFTING

Micron Technology, Inc., ...

1. An apparatus, comprising:a signal shift circuit configured to receive a clock signal in a first domain and an information signal in the first domain and provide a shifted information signal that is shifted a specified amount;
a delay locked loop (DLL) circuit configured to receive the clock signal in the first domain and provide a delayed clock signal in a DLL domain different from the first domain;
a cloned DLL circuit configured to receive the shifted information signal from the signal shift circuit and produce a shifted and delayed information signal in the DLL domain; and
a clock gate configured to receive the clock signal in the first domain and a control signal and, in response to one or more specified control signals, allowing the clock signal to pass to the DLL circuit,
wherein the one or more specified control signals that cause the clock gate to pass the clock signal to the DLL circuit consist of control signals that indicate a read or a write command.

US Pat. No. 10,367,511

COUNTER-BASED SYSREF IMPLEMENTATION

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:an input flip-flop including a clock input terminal and a data input terminal configured to be coupled to a first reference signal, wherein the input flip-flop is configured to use first clock to latch the reference signal to produce a latched reference signal;
a counter coupled to the input flip-flop and configured to count pulses of the first clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the first clock; and
a clock tree configured to divide down the first clock to generate a first output clock;
wherein the clock tree is configured to be synchronized to a pulse of the second reference signal;
wherein the clock tree includes:
a first level clock divider coupled to the first clock and configured to divide down the first clock to generate the first output clock;
a second level clock divider coupled to the first level clock divider and configured to divide down the first output clock to generate a second output clock;
wherein each of the first and second level clock dividers includes a reference signal input configured to receive the second reference signal pulses from the counter, wherein the second reference signal pulses synchronize the first and second level clock dividers.

US Pat. No. 10,367,507

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

INTERNATIONAL BUSINESS MA...

1. A plurality of dynamic decode circuits, each dynamic decode circuit connected between a first power source and a second power source, the each dynamic decode circuit comprising a respective decoder, a respective first node, a respective second node and a respective third node,wherein each decoder is configured to decode a respective plurality of input signals, wherein the each decoder is conductively connected to the respective first node and to the respective third node,
wherein the each dynamic decode circuit further comprises a respective evaluate clock circuit, wherein each evaluate clock circuit is conductively connected between the first power source and the respective second node, wherein the each evaluate clock circuit consists of a first transistor and a second transistor, wherein the first transistor is serially connected by a first interconnecting node to the second transistor, the first transistor comprising a first gate configured to receive an evaluation clock signal, the second transistor comprising a second gate conductively connected to the first node, the first transistor configured to conduct based on the evaluation clock signal being active and the first transistor configured to not conduct based on the evaluation clock signal being inactive,
wherein the each dynamic decode circuit further comprises one or more respective evaluate transistors, wherein the one or more evaluate transistors are connected to the first power source, wherein the one or more evaluate transistors are configured to evaluate a respective dynamic logic during an evaluate phase of the dynamic logic, wherein each of the one or more evaluate transistors are configured to conduct at the same time based on the same evaluation clock signal,
wherein the each dynamic decode circuit further comprises one or more respective precharge circuits, each precharge circuit connected to the second power source, the each precharge circuit configured to precharge a respective node in a precharge phase of the dynamic logic,
wherein each first node is connected to a respective precharge circuit,
wherein each the third node is connected to a respective evaluate transistor,
wherein the each dynamic decode circuit further comprises a respective conditioning circuit configured to condition a shared node of the dynamic decode circuit, the shared node shared by the each dynamic decode circuit of the plurality of dynamic decode circuits,
wherein each respective conditioning circuit of the plurality of dynamic decode circuits is connected in parallel between the shared node and a common power source, wherein the each respective conditioning circuit comprises a first conditioning transistor having a first conditioning gate configured to receive the evaluation clock signal and wherein the each conditioning circuit consists of any one of a precharge circuit and an evaluate transistor.

US Pat. No. 10,367,500

SWITCHING VOLTAGE REGULATOR WITH VARIABLE MINIMUM OFF-TIME

Allegro MicroSystems, LLC...

1. A voltage regulator comprising:a switch having a control terminal;
a bootstrap capacitor coupled to the switch;
a control circuit coupled to a control terminal of the switch and configured to open the switch to allow the bootstrap capacitor to charge and close the switch to allow the bootstrap capacitor to stop charging;
an oscillator circuit that produces a minimum off-time signal that defines a minimum time for the switch to be open and for the bootstrap capacitor to charge;
an under-voltage detection circuit that monitors a voltage across the bootstrap capacitor and, if the voltage across the bootstrap capacitor is less than a predetermined threshold, generates a signal that causes the switch to remain open; and
a minimum off-time circuit that adjusts the minimum off-time signal based on a reference voltage and the voltage across the bootstrap capacitor;
wherein:
the minimum off-time circuit comprises a ramp generator circuit that produces a ramp signal; and
the minimum off-time circuit combines the voltage across the bootstrap capacitor and the ramp signal to produce a modulated signal by summing the voltage across the bootstrap capacitor and the ramp signal.

US Pat. No. 10,367,499

POWER SUPPLY READY INDICATOR CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A power supply ready indicator circuit comprising:a first power-supply-ready-input coupled to a first power supply rail;
a second power-supply-ready-input coupled to a second power supply rail;
a power ready indicator output;
wherein the power supply ready indicator circuit is configured to:
divide a voltage on the first power supply rail,
compare the divided voltage with the second power supply rail voltage, and
generate a power ready signal on the power ready indicator output in response to the divided voltage being greater than the second power supply rail voltage,
wherein a final value of the first power supply rail voltage is greater than a final value of the second power supply rail voltage;
an integrated circuit including the power supply ready indicator circuit;
wherein the integrated circuit includes a voltage regulator having an input coupled to the first power supply rail and an output coupled to the second power supply rail; and
wherein the voltage regulator is configured to generate the second power supply rail voltage.

US Pat. No. 10,367,497

SYSTEM COMPRISING MULTI-DIE POWER AND METHOD FOR CONTROLLING OPERATION OF MULTI-DIE POWER MODULE

MITSUBISHI ELECTRIC CORPO...

1. A system comprising a multi-die power module composed of dies and a controller receiving plural consecutive input patterns for activating the dies of the multi-die power module, the input patterns being composed of rising edges and falling edges, characterized in that the dies are grouped into first, second and third groups of at least one die and in that the controller comprises:means for advancing the falling edge time of a gate signal for the first group of at least one die by a predetermined value,
means for delaying the rising edge time of a gate signal for the second group of at least one die by the predetermined value,
means for delaying the rising edge time of a gate signal for the third group of at least one die by the predetermined value and for advancing the falling edge time of the gate signal for the third group of at least one die by the predetermined value.

US Pat. No. 10,367,494

FAST-RESPONSE REFERENCES-LESS FREQUENCY DETECTOR

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to generate a waveform in response to (a) a frequency of an input clock signal and (b) a threshold frequency; and
a second circuit configured to generate a control signal in response to a type of said waveform, wherein (i) said type of said waveform comprises at least one of (a) pulses and (b) a steady state, (ii) said control signal has (a) a first state when said type of said waveform is said pulses and (b) a second state when said type of said waveform is said steady state and (iii) a width of said pulses is based on said threshold frequency.

US Pat. No. 10,367,493

DUTY CYCLE AND SKEW CORRECTION FOR OUTPUT SIGNALS GENERATED IN SOURCE SYNCHRONOUS SYSTEMS

SanDisk Technologies LLC,...

1. A circuit comprising:a delay circuit configured to output a delayed clock signal to a clock input of an output clock path circuit;
an input buffer configured to generate a buffered clock signal in response to receipt of an output clock signal from the output clock path circuit; and
a duty cycle correction controller configured to:
identify a duty cycle level of the buffered clock signal; and
adjust a delay amount of the delay circuit in response to the identified duty cycle level of the buffered clock signal.

US Pat. No. 10,367,490

ELECTRONIC CIRCUITS FOR OUTPUTTING POST EMPHASIS SIGNALS

Samsung Electronics Co., ...

1. An electronic device comprising:a driver configured to generate a second signal based on a first signal;
a delay circuit configured to delay the first signal by a reference time, to generate a third signal;
a strength control circuit configured to adjust an amplitude of the third signal to generate a fourth signal; and
an adder circuit configured to add the second signal and the fourth signal to generate a fifth signal,
wherein, in a first time interval determined based on the reference time, an amplitude of the fifth signal is greater than an amplitude of the second signal,
wherein, in a second time interval not overlapping with the first time interval, the amplitude of the fifth signal is smaller than the amplitude of the second signal, and
wherein, in the second time interval, the amplitude of the fifth signal is smaller than an amplitude of the first signal.

US Pat. No. 10,367,488

DEVICE AND METHOD FOR ELIMINATING ELECTROMAGNETIC INTERFERENCE

HKC CORPORATION LIMITED, ...

1. A device for eliminating electromagnetic interference (EMI), comprising:a timing control chip; and
a phase-locked loop module, electrically connected to the timing control chip and comprising:
a phase detection unit, configured to detect a frequency generated by a clock cycle to generate a frequency difference;
a charge pump unit, configured to generate a regulation voltage;
a voltage-controlled oscillator unit, configured to control an oscillation frequency when the regulation voltage is input;
a plurality of frequency divider units, configured to generate a new output clock frequency by using an input clock frequency; and
a selector unit, configured to electrically connect to the plurality of frequency divider units,
wherein the timing control chip receives one piece of display data by using a front-end system,
wherein after processing the display data, the timing control chip outputs a data signal and a clock cycle signal,
wherein the frequency divider units have at least one frequency dividing multiple, and
wherein the selector unit is electrically connected to at least four different power circuits.

US Pat. No. 10,367,484

RAMP BASED CLOCK SYNCHRONIZATION FOR STACKABLE CIRCUITS

Texas Instruments Incorpo...

1. A phase generation circuit, comprising:a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal;
a phase selection circuit arranged to generate a reference signal in response to a phase selection signal separated from a peak voltage signal;
a comparator having a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal, the comparator producing a phase clock signal at an output terminal;
a phase error correction circuit arranged to produce an error signal to correct an error in time between the synchronization clock signal and the phase clock signal;
a sample and hold circuit arranged to sample the ramp signal; and
a buffer circuit coupled to receive the sampled ramp signal and the error signal, the buffer circuit having an output terminal coupled to the phase error correction circuit.

US Pat. No. 10,367,481

DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TEST CONTROL BOUNDARY USING AN INVERTED ARRAY CLOCK SIGNAL FEATURE

International Business Ma...

1. A digital logic circuit which is configured to deter a race violation at an array test control boundary, comprising:a clock generation circuitry, wherein the clock generation circuitry includes:
a first local clock buffer to generate:
a primary scan clock signal feature,
a secondary scan clock signal feature, and
a pulsed clock signal feature; and
a second local clock buffer to generate an array clock signal feature, the clock generation circuitry having both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting the array clock signal feature, and wherein the clock generation circuitry is configured to output an output clock signal feature when indicated by a first enable input, and
wherein the output clock signal feature is based on a scan enable input and wherein the output clock signal feature includes:
the primary scan clock signal feature,
the secondary scan clock signal feature, and
the pulsed clock signal feature;
a scannable storage element having both a scannable storage element output and a set of flip-flops, the set of flip-flops including:
a first primary flip-flop which corresponds to a functional data path of the digital logic circuit, wherein the first primary flip-flop connects with the derivative clock signal feature,
a second primary flip-flop which corresponds to a scan data path of the digital logic circuit, wherein the second primary flip-flop connects with the secondary scan clock signal feature and wherein the second primary flip-flop and a secondary flip-flop are part of the scan data path, and
the secondary flip-flop connected to both the pulsed clock signal feature and the scan clock signal feature, wherein the secondary flip-flop is configured to input an output of:
the first primary flip-flop when indicated by the pulsed clock signal feature, and
the second primary flip-flop when indicated by the secondary scan clock signal feature, and wherein the second primary flip-flop is used in a nonperformance critical scan operation; and
a memory array connected with:
the scannable storage element output, and
the array clock signal feature, wherein the memory array includes an array of static random-access memory (SRAM) cells, and wherein the digital logic circuit is configured to avoid the race violation between a set of output data of the first primary flip-flop and the pulsed clock signal feature at the secondary flip-flop independent of the what the derivative clock signal feature indicates, wherein all clock signal features are derived from a common global clock signal.

US Pat. No. 10,367,479

METHOD AND APPARATUS TO REDUCE NOISE IN CT DATA ACQUISITION SYSTEMS

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:an integrator configured to generate an integrated signal in response to a current signal;
a comparator coupled to the integrator and configured to receive the integrated signal and a primary reference voltage signal, the comparator configured to generate a feedback signal; and
a switched capacitor network coupled across the integrator, wherein the feedback signal is configured to activate the switched capacitor network;
a feedback capacitor coupled across the integrator;
an analog-to-digital converter (ADC) coupled across the feedback capacitor; and
a first transconductor configured to receive a secondary reference voltage signal, and an output terminal of the first transconductor coupled to a first output terminal of the integrator.

US Pat. No. 10,367,477

SPARSE CASCADED-INTEGRATOR-COMB FILTERS

Analog Devices, Inc., No...

1. An efficient low-power cascaded-integrator-comb (CIC) filter comprising:a series of integrating stages comprising a last integrating stage in the series of integrating stages operating on signal values from previous integrating stages, wherein the last integrating stage comprises:
an integrator having an adder and a delay unit whose output is fed back to the adder; and
a multiplier, upstream of the adder, to implement time-varying input gain, sequentially receive time-varying coefficients, and multiply each of the time-varying coefficients with corresponding one of the signal values received from previous integrating stages, wherein the time-varying coefficients includes at least one zero;
a decimation stage to decimate an output of the integrator; and
a differentiator downstream from the decimation stage.

US Pat. No. 10,367,475

ACOUSTIC WAVE FILTER INCLUDING SURFACE ACOUSTIC WAVE RESONATORS AND BULK ACOUSTIC WAVE RESONATOR

Skyworks Solutions, Inc.,...

1. A multiplexer comprising four acoustic wave filters coupled to a common node, the four acoustic wave filters including a first acoustic wave filter that includes surface acoustic wave resonators and a series bulk acoustic wave resonator coupled between the surface acoustic wave resonators and the common node, and the four acoustic wave filters including a second acoustic wave filter that includes second surface acoustic wave resonators and a second series bulk acoustic wave resonator coupled between the second surface acoustic wave resonators and the common node.

US Pat. No. 10,367,469

CORNER COUPLING RESONATOR ARRAY

MURATA MANUFACTURING CO.,...

1. A microelectromechanical system (“MEMS”) resonator array comprising:at least a pair of first piezoelectric resonators opposed to each other with a space defined therebetween; and
at least a pair of second piezoelectric resonators that are opposed to each other and that are each coupled to respective corners of each of the first piezoelectric resonators, such that each of the second piezoelectric resonators is partially disposed in the space defined between the pair of first piezoelectric resonators,
wherein each piezoelectric resonator of the respective pairs of first and second piezoelectric resonators comprise a pair of anchoring points on respective opposing sides of each piezoelectric resonator, such that each piezoelectric resonator is configured to vibrate in-plane in a width expansion mode.

US Pat. No. 10,367,465

OPTIMIZED VOLUME ADJUSTMENT

Apple Inc., Cupertino, C...

1. A method of providing audio volume adjustment in a media-editing application, the method comprising:displaying an audio clip;
determining intrinsic segment volume levels individually for segments of the audio clip;
displaying a volume adjuster graph having different volume adjuster segments within the volume adjuster graph at same levels as the determined intrinsic segment volume levels for the segments of the audio clip, the volume adjuster graph being for adjusting volume levels of the segments of the audio clip;
receiving an adjusted level for at least one of the volume adjuster segments of the volume adjuster graph; and
setting a volume level of at least one of the segments of the audio clip by setting the intrinsic segment volume level to the received adjusted level for the at least one of the volume adjuster segments of the volume adjuster graph.

US Pat. No. 10,367,462

CRYSTAL AMPLIFIER WITH ADDITIONAL HIGH GAIN AMPLIFIER CORE TO OPTIMIZE STARTUP OPERATION

Silicon Laboratories Inc....

1. A crystal amplifier for driving a crystal to oscillate at a resonant frequency, comprising:a controlled current source having a control input, wherein said current source provides a core bias current to a source node;
an amplifier input node and an amplifier output node for coupling across the crystal;
a primary amplifier core coupled between said source node and a reference node, having an input coupled to said amplifier input node having an output coupled to said amplifier output node;
a high gain amplifier core coupled between said source node and said reference node, having an input coupled to said amplifier input node, having an output coupled to said amplifier output node, and having an enable input;
a level detector having at least one input coupled to at least one of said amplifier input node and said amplifier output node and having an output providing a level indication when a level threshold is achieved, and wherein said level detector initially selects a first threshold value at said startup time; and
a controller coupled to said current source and to said high gain amplifier core and having an input receiving said level value, wherein said controller sets said current source to a predetermined high current level and enables said high gain amplifier core to achieve a high negative resistance at a startup time, and wherein said controller determines that said oscillation is achieved when said level indication is provided and sets said current source to a lower steady state current level and disables said high gain amplifier core after oscillation is achieved;
wherein in response to said level indication indicating said first threshold value, said controller sets said current source to an intermediate current level that is less than said high current level and greater than said steady state current level, wherein after said level indication is first provided after said startup time, said level detector selects a second threshold value, and wherein in response to said level indication indicating said second threshold value, said controller sets said current source to said steady state current level.

US Pat. No. 10,367,461

COMBINED OUTPUT MATCHING NETWORK AND FILTER FOR POWER AMPLIFIER WITH CONCURRENT FUNCTIONALITY

Skyworks Solutions, Inc.,...

1. A radio frequency power amplifier module for use in a multi-band wireless mobile device comprising:a first semiconductor die including an amplifier circuit configured to amplify a radio frequency input signal received on an input terminal of the power amplifier module for transmission by a first antenna associated with a first transmit path of the mobile device;
an input tuning circuit including at least a first capacitor in communication with the first semiconductor die;
an output tuning circuit including at least a first inductor in communication with an output terminal of the power amplifier module; and
a first circuit connected in series between the input tuning circuit and the output tuning circuit and including at least a second inductor and a second capacitor connected in parallel and configured to transform an output impedance of the amplifier circuit to an input impedance of the first antenna and further configured to block signals radiating from a second antenna associated with a second transmit path of the mobile device and received at the output terminal from traveling backwards along the first transmit path to the amplifier circuit.

US Pat. No. 10,367,460

AMPLIFIER CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An amplifier circuit comprising:a delta-PWM-modulator configured to:
receive a digital-input-signal;
process the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal, wherein the delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulationof the digital-input-signal;
a three-level-DAC configured to receive the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provide a three-level-analogue-signal;
a loop-integrator comprising:
a virtual-ground-node-terminal configured to receive: (i) the three-level-analogue-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop;
an integrator-output-terminal configured to provide a loop-integrator-output-signal, which is proportional to an integral of the signals received at the virtual-ground-node-terminal; and
a comparator comprising:
a comparator-input-terminal configured to receive the loop-integrator-output-signal;
a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and
a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

US Pat. No. 10,367,459

CLASS-D AMPLIFIER CIRCUIT

ROHM CO., LTD., Kyoto (J...

1. A Class-D amplifier circuit comprising:a bridge output stage coupled to an electroacoustic conversion element via an inductor;
a driving circuit structured to drive the output stage according to a pulse signal that corresponds to an audio signal; and
an overcurrent detection circuit structured to assert an overcurrent detection signal (i) when a current that flows through a transistor to be monitored that forms the output stage exceeds a first threshold value for a predetermined first period of time, or (ii) when a current that flows through the transistor to be monitored exceeds a second threshold value that is higher than the first threshold value after a predetermined second period of time elapses after the transistor to be monitored turns on, wherein the overcurrent detection circuit comprises:
a first comparator structured to compare a current detection signal that corresponds to a current that flows through the transistor to be monitored with a first threshold voltage that corresponds to the first threshold value, and to generate a first comparison signal indicating a comparison result;
a second comparator structured to compare the current detection signal with a second threshold voltage that corresponds to the second threshold value, and to generate a second comparison signal indicating a comparison result; and
a judgment circuit structured to generate the overcurrent detection signal based on the first comparison signal and the second comparison signal.

US Pat. No. 10,367,456

AMPLIFIER ASSEMBLY AND SPATIAL POWER COMBINING DEVICE

Qorvo US, Inc., Greensbo...

1. An amplifier assembly for a spatial power combining device that comprises a plurality of amplifier assemblies, the amplifier assembly comprising:a body that forms a first antenna, wherein the first antenna is a first Vivaldi antenna comprising a first circular backstub and a first tapered slot portion;
a second antenna; and
a printed circuit board (PCB) assembly fixed to the body, comprising:
a PCB;
an amplifier mounted on the PCB;
a first transmission line coupled to the first antenna and to the amplifier; and
a second transmission line coupled to the second antenna and to the amplifier.

US Pat. No. 10,367,455

HIGH-FREQUENCY FRONT END CIRCUIT

MURATA MANUFACTURING CO.,...

1. A high-frequency front end circuit comprising:an antenna terminal;
a reception circuit that is connected to the antenna terminal; and
a transmission circuit that is connected to the antenna terminal and that comprises a first amplification circuit, wherein the first amplification circuit comprises:
an input terminal and an output terminal;
an amplification element connected in a signal path between the input terminal and the output terminal; and
a bias circuit having an LC resonance circuit, a first end of the bias circuit being connected to the signal path,
wherein a frequency pass band of the transmission circuit is lower than a frequency pass band of the reception circuit, and
wherein a resonant frequency of the bias circuit is less than a frequency pass band width of the transmission circuit.

US Pat. No. 10,367,449

MICRO-CONCENTRATOR MODULE AND DEPLOYMENT METHOD

The Boeing Company, Chic...

1. A micro-concentrator module, that comprises:a cover glass;
a printed wiring board that comprises:
on a side, which faces the cover glass, of the printed wiring board, an array of micro-electromechanical systems (MEMS) based reflectors;
on a side, which faces away from the cover glass, of the printed wiring board, an electrical power trace that powers the printed wiring board;
a panel that comprises, on a side, which faces the printed wiring board, first welds that connect the panel to the printed wiring board and support a space between the printed wiring board and the panel;
an application specific integrated circuit configured to control the micro-concentrator module and mounted, within the space, to the side, which faces away from the cover glass, of the printed wiring board;
a plurality of solar cells located on one side of the cover glass and configured to stow adjacent to and deploy to hover at a distance over the array of MEMS based reflectors; and
an electrical connection coupled to:
via second welds, the side, which faces the cover glass, of the printed wiring board;
via third welds, to a bus bar connected to an electrical circuit trace connected to a sub-array of the plurality of solar cells, such that the bus bar forms a continuous trace along a width and a length of a perimeter of the cover glass, the electrical connection configured:
to compress;
comprising a bias to expand until restrained by a tether connected to the printed wiring board and to the cover glass; and
support a separation between the cover glass and the printed wiring board that sustains the distance between the plurality of solar cells and the array of MEMS based reflectors; and
a damping pad mounted as a discontinuous strip aligned along a perimeter of the side, which faces the cover glass, of the printed wiring board, such that with the electrical connection fully compressed the cover glass contacts the damping pad and maintains the cover glass in a spaced relationship above the array of MEMS based reflectors.

US Pat. No. 10,367,448

SOLAR PANEL AWNING AND RELATED SYSTEMS AND METHODS

1. A solar panel awning device comprising:a solar panel having first and second opposing ends, first and second opposing sides extending between said first and second opposing ends, and first and second opposing major surfaces, said first major opposing surface defining a photovoltaic surface;
first and second arms respectively coupled to said first and second opposing ends of said solar panel;
at least one actuator coupled to one of said first and second arms and configured to switch the solar panel between an extended position and a retracted position; and
first and second pivot arms respectively coupled to said first and second opposing ends of said solar panel adjacent the first opposing side of said solar panel, the first and second pivot arms being separate from and spaced apart from said first and second arms;
said first and second arms, and said first and second pivot arms configured to, in the retracted position, fold said solar panel flat against a side of a building;
said first and second arms, and said first and second pivot arms configured to, in the extended position, extend both the first opposing side and the second opposing side of said solar panel so that
said first opposing side is proximal to the side of the building and spaced apart from the side of the building,
said second opposing side is distal to the side of the building, and
said first opposing side extends laterally past an eave of the building;
wherein said first and second arms and said first and second pivot arms each have a first end and an opposing second end, the first end of each of said first and second arms and said first and second pivot arms being attached to the side of the building;
wherein each of said first and second arms is configured to rotate at the first end and the second end to switch from the retracted position to the extended position; and
wherein each of said first and second pivot arms is configured to rotate at the first end to switch from the retracted position to the extended position.

US Pat. No. 10,367,446

MOUNT FOR SOLAR PANEL

FUJI SEIKO CO., LTD., Ha...

1. A mount for a solar panel comprising:a tilted support frame having a pair of horizontal members extending along a horizontal direction in parallel to each other with different heights and a pair of tilted members arranged between the horizontal members and extending in parallel to each other so as to be-tilted in one side;
a fixed support member fixing and supporting the tilted support frame on an installation surface;
a square-shaped panel support member provided above the tilted support frame, on which a solar panel is arranged and fixed;
a support shaft provided so as to extend along a direction parallel to the horizontal members between the tilted support frame and the panel support member and supporting the panel support member so as to rotate at a central portion portions of two facing sides of the panel support member; and
a pair of stopper members respectively provided on each rotating end side of the panel support member so that one end portion of each of the pair of stopper members rotates freely and wherein the pair of stopper members include engaging concave portions having open lower sides engaging with half circumferences of outer peripheries of the horizontal members from above in a rotating direction so as to be removed at positions corresponding to a predetermined tilt angle position of the panel support member.

US Pat. No. 10,367,445

CARRIER STRUCTURE FOR SOLAR PANELS AND METHOD OF PRODUCING SUCH A CARRIER STRUCTURE

Esdec B.V., Deventer (NL...

14. A carrier structure for solar panels, comprising:at least one carrying frame configured to carry at least a part of at least one solar panel, and
at least one accessory which is coupleable to the carrying frame,
wherein at least one of the at least one carrying frame and the at least one accessory comprises at least one coupling pin configured to be at least partly received in a complementary receiving space provided in at least one of the at least one accessory or the at least one carrying frame, wherein the coupling pin and/or the receiving space is provided with at least one locking element for locking the accessory and the carrying frame to each other when the coupling pin is being fitted in the receiving space, and wherein the receiving space is provided with at least one locking element being configured to cut into an outer periphery of the coupling pin, and
wherein the accessory is provided with several receiving spaces, wherein each receiving space is provided with at least one locking element, and wherein the carrying frame comprises several coupling pins configured to be at least partly received in the respective receiving spaces for mutually locking the accessory with respect to the carrying frame.

US Pat. No. 10,367,437

SYSTEMS, METHODS AND DEVICES FOR APPROXIMATE DYNAMIC PROGRAMMING VECTOR CONTROLLERS FOR OPERATION OF IPM MOTORS IN LINEAR AND OVER MODULATION REGIONS

The Board of Trustees of ...

1. A method for controlling an interior-mounted permanent magnet (IPM) alternating-current (AC) electrical machine by:providing a pulse-width modulated (PWM) converter operably connected between an electrical power source and the IPM AC electrical machine;
providing a neural network vector control system operably connected to the PWM converter, the neural network vector control system comprising a current-loop neural network configured to implement an approximate dynamic programming (ADP) algorithm, wherein the current-loop neural network is trained to minimize a cost function of the ADP algorithm using a forward accumulation through time (“FATT”) algorithm;
receiving a plurality of inputs at the current-loop neural network;
outputting a first compensating dq-control voltage from the current-loop neural network, wherein the current-loop neural network is configured to optimize the first compensating dq-control voltage based on the plurality of inputs;
providing a feedforward controller operably connected to the PWM converter;
receiving reference current inputs at the feedforward controller, wherein the inputs at the feedforward controller comprise a reference d-axis current, isd*, and a reference q-axis current, isq*;
outputting a second compensating dq-control voltage from the feedforward controller, wherein the feedforward controller is configured to regulate the second compensating dq-control voltage based on the reference current inputs; and
controlling the PWM converter using the first compensating dq-control voltage and the second compensating dq-control voltage,
wherein the feedforward controller is designed based on default parameters of the IPM AC electrical machine.

US Pat. No. 10,367,436

SINGLE-AXIS LINEAR MOTION SYSTEM

Invetech, Inc., San Dieg...

1. A linear motion system comprising:a base;
a moving carriage configured to move back and forth along a single linear direction relative to the base;
at least one motor coil;
at least one motor magnet;
at least one printed circuit board mounted on the base;
an electronic motion controller configured to provide motion commands to an electronic drive; and
the electronic drive configured to translate commands from the electronic motion controller into currents supplied to the at least one motor coil;
wherein the electronic motion controller and electronic drive are mounted on the at least one printed circuit board.

US Pat. No. 10,367,435

DUAL-VOLTAGE BRUSHLESS MOTOR

TECHTRONIC INDUSTRIES COM...

1. A dual-voltage brushless motor, comprising:a) a casing;
b) a motor shaft rotatably coupled to said casing;
c) a rotor fixedly connected to said motor shaft; said rotor comprising a plurality of permanent magnets; and
d) a stator configured to face said rotor; wherein said stator comprising a first set of windings and a second set of windings;
wherein the first set of windings is in electrical communication with an AC power supply, wherein the second set of windings is in electrical communication with a DC power supply, wherein said first set of windings is electrically isolated from said second set of windings; and
wherein said dual-voltage brushless motor is driven when said first set of windings receives a first control signal or when said second set of windings receives a second control signal.

US Pat. No. 10,367,429

ACTUATOR ELEMENT USING CARBON ELECTRODE

NATIONAL INSTITUTE OF ADV...

1. A conductive thin film comprising a homogeneous mixture comprising 5-90% by weight of a nano-carbon material, 5-80% by weight of an ionic liquid, 4-70% by weight of a polymer, and an organic molecule component,wherein the homogeneous mixture forms a gel,
wherein the organic molecule component comprises at least one electron-withdrawing organic molecule that is tetracyanoquinodimethane (TCNQ), and
wherein the organic molecule component is present in an amount of 3 to 80 parts by weight per 100 parts by weight of a total amount of the nano-carbon material, the ionic liquid, and the polymer.

US Pat. No. 10,367,427

RESONANT INVERTER DEVICE

DENSO CORPORATION, Kariy...

1. A resonant inverter device comprising:a main circuit configured to convert input power supplied from a direct-current (DC) power source into alternating-current (AC) power and supply the AC power to a resonance load as output power;
an input power measurer configured to measure the input power;
a controller configured to control operations of the main circuit, the controller comprising:
an input to which a target output value that is a target value of the output power is externally input;
a deriver configured to derive a power loss or circuit efficiency of the main circuit as a conversion loss parameter of the main circuit;
an input power calculator configured to calculate an increased target output value by increasing the target output value using the conversion loss parameter, as a target value of the input power; and
an operation controller configured to control operations of the main circuit such that the calculated target value of the input power is input to the main circuit.

US Pat. No. 10,367,413

RESONANT SYSTEM CONTROLLER AND CYCLE-BY-CYCLE PREDICTIVE SOFT SWITCHING

Pre-Switch, Inc., Raleig...

1. A method of reducing switching losses during successive switch-mode power supply (SMPS) cycles of an SMPS comprising first and second electrically coupled switches that change switching states in response to, respectively, first and second signals, the successive SMPS cycles including first and second SMPS cycles in which the second SMPS cycle follows the first SMPS cycle, the method comprising:generating during the first SMPS cycle the first signal at a first time to change a first switching state of the first switch;
generating during the first SMPS cycle the second signal at a second time to change a second switching state of the second switch, the second time temporally displaced from the first time based on a timing parameter, the timing parameter being adjustable to coordinate the second switch changing its switching state when a soft-switching condition exists, the soft-switching condition characterized by a condition at which minimum hard-switching and diode conduction losses would result from the second switch changing its switching state;
detecting a failure to adequately soft switch the second switch during the first SMPS cycle and whether the failure is attributable to a first or second timing error between when the second switch changes its switching state and when the soft-switching condition actually occurs for the first SMPS cycle, the first and second timing errors occurring when the second switch changes its switching state, respectively, before and after when the soft-switching condition actually occurs for the first SMPS cycle;
in response to detecting the first timing error, adjusting, for the second SMPS cycle, the timing parameter to reduce hard-switching loss by causing the second time at which the second signal is generated to be delayed during the second SMPS cycle; and
in response to detecting the second timing error, adjusting, for the second SMPS cycle, the timing parameter to reduce diode conduction loss by causing the second time at which the second signal is generated to be advanced during the second SMPS cycle.

US Pat. No. 10,367,402

VIBRATION MOTOR

NIDEC SEIMITSU CORPORATIO...

1. A vibration motor comprising:a cover;
a board including an electrical circuit;
a stationary portion including a casing and a coil;
a vibrator including a magnet, and supported to vibrate in one direction with respect to the stationary portion; and
at least one elastic member between the stationary portion and the vibrator; wherein
the magnet is above an upper side of the coil in a vertical direction perpendicular to the one direction;
the stationary portion includes at least one projecting portion that projects in the vertical direction;
a portion of the at least one projecting portion is opposite to a portion of the vibrator in the one direction;
a portion of the board is directly adjacent to and partially surrounds a portion of the at least one projecting portion;
the at least one elastic member includes a plate spring portion that supports at least one of both ends of the vibrator with respect to the one direction; and
the plate spring portion includes a decreased width portion and an increased width portion having a vertical width greater than a vertical width of the decreased width portion, the decreased width portion being above or below a corresponding one of the at least one projecting portion when viewed from one side in the one direction.

US Pat. No. 10,367,401

ELECTRIC MOTOR WITH COMMUTATOR SEGMENTS, ANODE AND CATHODE BRUSHES AND COILS HAVING VARYING NUMBER OF TURNS BASED ON ANODE BRUSH POSITION ANGLE

Mitsuba Corporation, Gun...

1. An electric motor comprising:a motor magnet in which a plurality of magnetic poles are arranged in a circumferential direction;
a rotating shaft that is rotatably provided inside the motor magnet;
an armature core that is mounted on the rotating shaft and includes a plurality of teeth radially extending outward in a radial direction and a plurality of slots formed between the teeth;
coils that are wound on each of the teeth in a concentrated winding manner;
a commutator which is provided so as to rotate integrally with the rotating shaft and on which a plurality of segments are disposed in the circumferential direction; and
an anode brush and a cathode brush that supply power to the coils through the segments,
wherein three coils are wound on each of the teeth,
a number of turns of one coil among the three coils is set to be smaller than a number of turns of each of the other two coils,
the three coils are an advance-angle coil of which a magnetomotive force vector is directed to an advance-angle side, a delay-angle coil of which a magnetomotive force vector is directed to a delay-angle side, and a normal coil of which a magnetomotive force vector is not directed to either the advance-angle side or the delay-angle side, and
when the number of turns of the advance-angle coil is denoted by T1, the number of turns of the normal coil is denoted by T2, and the number of turns of the delay-angle coil is denoted by T3,
in a case in which,
an advance angle ?1 of the magnetomotive force vector of the advance-angle coil satisfies 0° a delay angle ?2 of the magnetomotive force vector of the delay-angle coil satisfies 0° an advance angle ?3 of a position of the anode brush satisfies 0°??3?3°,
T1, T2, and T3 are set so as to satisfy T2>T1>T3.

US Pat. No. 10,367,400

LINE START PERMANENT MAGNET MOTOR USING A HYBRID ROTOR

Coreteq Systems Ltd., Su...

1. A rotor system for a downhole motor comprising:a set of permanent magnets;
a set of conductors comprising discrete conductive bars; and
a pair of end conductor rings connecting the set of conductors;
the set of permanent magnets and the set of conductors being substantially coaxial and having the substantially the same linear extent;
the set of permanent magnets and the set of conductors both being set in a rotor body, the rotor body having an outermost outer surface, the outermost outer surface featuring notches in which the conductors are set; and
a conductive material substantially formed around a cylinder, the thickness of the conductive material varying around the radius of the cylinder in an alternating manner, so as to provide relatively thick portions that are generally axially aligned.

US Pat. No. 10,367,393

MOTOR ROTATOR, MOTOR DEVICE, AND METHOD FOR MANUFACTURING THE MOTOR ROTATOR

SANYO DENKI CO., LTD., T...

1. A motor rotator comprising:a rotor shaft configured to be journaled to a pair of bearing members of a motor device; and
a rotor stack that includes a plurality of lamination plates and a plurality of small-diameter plates having an outer diameter smaller than an outer diameter of the lamination plates, the lamination plates and the small-diameter plates being stacked in an axial direction of the rotor shaft and integrated, wherein
the plurality of small-diameter plates forms each of a pair of bosses, the pair of bosses projecting from both sides of the plurality of lamination plates along the axial direction of the rotor shaft to abut on the pair of bearing members, the pair of bosses being secured to the rotor shaft,
each of the pair of bearing members includes an outer rotator and an inner rotator which is rotatable inside the outer rotator, and
the outer diameter of the plurality of small-diameter plates is smaller than an outer diameter of the outer rotators.

US Pat. No. 10,367,383

STRUCTURE FOR FIXING PERMANENT MAGNET AND MOTOR AND METHOD OF FIXING PERMANENT MAGNET

MABUCHI MOTOR CO., LTD., ...

1. A fixing structure for a permanent magnet, comprising:a cylindrical housing;
a permanent magnet housed inside the housing; and
an adhesive layer formed in a gap between the housing and the permanent magnet and having an adhesive for fixing the permanent magnet to the housing, wherein
the adhesive layer is formed such that a filling rate of the adhesive is higher in the gap at another axial end of the permanent magnet than at one axial end of the permanent magnet, and
the permanent magnet is configured such that a density at said other axial end of the permanent magnet is higher than the density at said one axial end of the permanent magnet.

US Pat. No. 10,367,368

WIRELESS POWER TRANSFER METHOD AND WIRELESS POWER TRANSMITTER

LG ELECTRONIC INC., Seou...

1. A wireless power transmitter for performing communication with a wireless power receiver, the wireless power transmitter comprising:a power conversion unit configured to transmit a wireless power signal transferred in a form of an energy field; and
a power transmission control unit configured to transfer power to the wireless power receiver using the wireless power signal,
wherein the power transmission control unit is configured to control the power conversion unit to transmit a near-field communication (NFC) detection signal, other than the wireless power signal, when a preset condition is satisfied,
wherein the power transmission control unit controls the power conversion unit in a different manner according to whether or not a response signal to the NFC detection signal is detected,
wherein the wireless power transmitter further comprises a frequency divider configured to generate the wireless power signal using the NFC detection signal based on the control of the power transmission control unit,
wherein the power conversion unit comprises a coil, and
wherein one of the wireless power signal and the NFC detection signal is selectively transmitted through the coil.

US Pat. No. 10,367,347

ARC FAULT CIRCUIT INTERRUPTER

Leviton Manufacturing Com...

1. A circuit interrupter, comprising:a first conductive path and a second conductive path;
a first arc fault detection circuit including a low frequency sensor, wherein the first conductive path passes through the low frequency sensor, the low frequency sensor including a first coil;
a second arc fault detection circuit including a high frequency sensor wherein the first and second conductive paths pass through the high frequency sensor and the high frequency sensor is configured to sense a difference in magnitude of currents respectively flowing in the first and second conductive paths, the high frequency sensor including a second coil and a third coil; and
a test block configured to perform a test of the high frequency sensor, the test block including:
a current supply configured to provide flow of a test current through the third coil;
a measuring circuit configured to measure a current flowing through the second coil;
logic configured to determine, based on the current flowing through the second coil, that the test current was detected by the second coil; and
an indicator configured to indicate a result of the test.

US Pat. No. 10,367,331

POINTING DEVICES, APPARATUS, SYSTEMS AND METHODS FOR HIGH SHOCK ENVIRONMENTS

1. A pointing support device for high shock environments, comprising:a housing having a base, a front stationary wall and a rear stationary wall, the front stationary wall with an opening;
a one piece shaped beam consisting of a cylindrical shaped first end rigidly mounted and fixed directly to the rear stationary wall, and a cylindrical shaped second end aligned with and adjacent to the opening in the front stationary wall, and a section intermediate the first end and the second end that has an elliptical shaped profile;
a pointing payload rigidly and fixed attached to the second end of the one piece shaped beam, wherein the one piece shaped beam provides accurate linear and angular positioning of the payload and maintains initial precise pointing of the payload relative to the surface the pointing device is attached to during and after exposure of the housing to shock and vibration; and
an externally accessible vertical and lateral adjustment mechanism consisting of only one single vertical adjustment component and only one single lateral adjustment component, the adjustment mechanism directly coupled to the pointing payload for adjusting vertical and lateral position of the payload be deflecting the one piece shaped beam along vertical and lateral orientations.

US Pat. No. 10,367,318

MODULAR FIXTURE FOR SUPPLYING POWER, CONTROL SIGNALS, AND/OR DATA COMMUNICATION TO VARIOUS DEVICES

1. A modular fixture, comprising:a housing;
a plurality of fixture connectors coupled to the housing;
a plurality of conductors coupled to each of the plurality of fixture connectors;
a first device including a first device connector operative to mate with each of the plurality of fixture connectors for coupling of the plurality of conductors to the first device; and
a second device including a second device connector operative to mate with each of the plurality of fixture connectors for coupling of the plurality of conductors to the second device;
wherein the first device and the second device are each of a device type selected from the group consisting of: a lighting device, a camera, a wireless communication device, a speaker device, a microphone device, a combination speaker-microphone device, a solar energy device, a wind energy device, a motion sensor, a speed monitoring device, and an unmanned aerial vehicle charging device; and
wherein the first device type is different than the second device type.

US Pat. No. 10,367,294

ELECTRICAL DEVICE HAVING A GROUND TERMINATION COMPONENT WITH STRAIN RELIEF

TE CONNECTIVITY CORPORATI...

1. An electrical device, comprising:a substrate having a plurality of signal contacts and a ground contact along a surface of the substrate;
a communication cable including a differential pair of signal conductors, a grounding element that surrounds the signal conductors, and a cable jacket surrounding the signal conductors and the grounding element; wherein each of the signal conductors has a wire-terminating end that is terminated to a corresponding signal contact of the substrate, the wire-terminating end projecting beyond a jacket edge of the cable jacket; and
a ground termination component having a main panel electrically coupled with the ground contact, and a strain relief element engaged with at least a portion of the communication cable; wherein the strain relief element includes a connective terminal electrically coupled to the grounding element.

US Pat. No. 10,367,291

MAGNETIC CONNECTOR ARRANGED IN A BENDABLE HOUSING IN AN ELECTRICALLY CONDUCTIVE CONNECTOR ASSEMBLY

SMK Corporation, Tokyo (...

1. A connector configured to be mated with a mating connector, the connector comprising:a plate-shaped housing;
an electrically conductive contact arranged on the housing; and
a plurality of retainer members which are formed from a magnetic substance or magnet and arranged in the housing, and when the connector is mated with the mating connector, attracted to a magnet the mating connector has so as to hold a mating state, wherein
the housing is formed from a bendable insulator,
the plurality of retainer members are spaced apart from each other in a predetermined direction parallel to one plate surface of the housing, and
the electrically conductive contact is formed from an electrically conductive rubber that penetrates through the housing.

US Pat. No. 10,367,290

CONNECTOR DEVICE AND MALE CONNECTOR

AutoNetworks Technologies...

1. A connector device, comprising:a male connector;
at least one male terminal fitting being part of the male connector, the male terminal fitting having a tab substantially projecting forward from a terminal body portion and having a leading end;
a terminal holding portion being part of the male connector, the terminal holding portion being capable of holding the terminal body portion;
a cover to be mounted on the terminal holding portion, a frame that is formed as a front part of the cover and surrounding the tab, the cover being displaceable between a protection position for where the frame at least partly coverings the tab and a retracted position displaced from the protection position to at least partly expose the leading end of the tab, at least one lock projecting in on the frame;
a female connector connectable to the male connector;
at least one female terminal fitting forming part of the female connector, the female terminal fitting being connectable to the tab by connecting the male connector and the female connector;
at least one pushing portion forming part of the female connector, the pushing portion being configured to be inserted into the frame and to displace the cover from the protection position toward or to the retracted position in the process of connecting the female connector to the male connector; and
at least one locking recess formed in an outer surface of the pushing portion and being configured to engage the locks projecting in on the frame and being configured to displace the cover from the retracted position toward or to the protection position by being locked to each other while separating the female connector from the male connector.

US Pat. No. 10,367,289

TERMINAL CONNECTING STRUCTURE AND CONNECTOR DEVICE

AutoNetworks technologies...

1. A connector device, comprising:a male terminal including a male connecting portion;
a female terminal formed from a conductive material and including a female connecting portion with opposite front and rear ends and opposite bottom and top plates extending rearward from the front end of the female connecting portion, the male connecting portion being insertable into and retractable from the front end of the female connecting portion, the inserted male connecting portion being placed on the bottom plate of the female connecting portion;
a movable portion supported in an electrically connected state to the female connecting portion by a support provided on the top plate at the front end of the female connecting portion, the movable portion being displaceable between the top and bottom plates with the support as a supporting portion;
a female contact provided on the movable portion, the female contact being displaceable between a non-pressing state where the female contact does not press the male connecting portion being inserted into the front end of the female connecting portion and a pressing state where the female contact presses the male connecting portion placed on the bottom plate of the female connecting portion in a direction intersecting an inserting/retracting direction of the male connecting portion and toward the bottom plate of the female connecting portion;
a pressed portion pressably provided at a position of the movable portion where a distance from the support to the pressed portion is longer than a distance between the support and the female contact, the pressed portion displacing the female contact from the non-pressing state to the pressing state with the support as a supporting portion by being pressed; and
a pressing portion displaceable toward the front end of the female connecting portion from an initial position where the pressing portion does not press the pressed portion to an end position where the pressing portion presses the pressed portion and causes the female contact to displace toward the bottom plate of the female connecting portion relative to the support provided on the top plate at the front end of the female connecting portion.

US Pat. No. 10,367,277

MULTI-EARTH TERMINAL ASSEMBLY

HYUNDIA MOTOR COMPANY, S...

1. A multi-earth terminal assembly comprising:two or more multi-earth terminals, wherein each of the two or more multi-earth terminals comprising:
a body having a hook piece and a hook rib on an outer edge of the body;
a barrel coupled with a wire;
a connector interconnecting the body with the barrel;
an engagement hole open toward an outer edge of the connector at one side of the connector; and
a hook boss protruding from a surface of the connector,
wherein two or more bodies are stacked vertically and coupled to each other, and
wherein when the two or more bodies are stacked vertically and coupled to each other, each of the two or more bodies includes the hook rib and the hook piece so that the hook rib of a first body that is located at an upper side of the vertically stacked bodies is inserted into and engaged with the hook piece of a second body that is located at a lower side of the vertically stacked bodies,
wherein, when the vertically stacked bodies rotate relative to each other, the hook boss of the second body is inserted into and engaged with the engagement hole of the first body,
wherein the engagement hole has an engagement step along an edge of the engagement hole and having a thickness which is relatively smaller than the connector,
wherein the hook boss has an engagement jaw at an upper end of the hook boss, the engagement jaw having a diameter larger than a diameter of the hook boss, and
wherein, when the hook boss is inserted into the engagement hole, the engagement jaw on the hook boss located at the lower side is seated on and engaged with the engagement step in the engagement hole.

US Pat. No. 10,367,276

CONDUCTIVE COMPONENT STRUCTURE OF WIRE CONNECTION TERMINAL

Switchlab Inc., New Taip...

1. A conductive component structure of wire connection terminal, comprising:a main body made of an electro-conductive material in the form of a plate body; and
a restriction body integrally formed on the main body or assembled/disposed on the main body, the restriction body defining a mouth section and having an oblique wall connected with the mouth section, the oblique wall extending from the mouth section to form a securing section in combination with the main body, the securing section narrowing both horizontally and vertically from the mouth section to thereby guide and secure a conductive wire plugged into the wire connection terminal.

US Pat. No. 10,367,273

SYSTEM AND METHOD FOR SEALING ELECTRICAL TERMINALS

TE CONNECTIVITY CORPORATI...

1. A system for sealing an electrical terminal, comprising:(a) a device for sealing a plurality of electrical wires to a wire attachment portion of an electrical terminal, wherein the device further includes:
(i) a shrinkable tubing having a predetermined length, wherein the shrinkable tubing has been placed over the plurality of electrical wires such that one end thereof extends over the wire attachment portion of the electrical terminal;
(ii) a sealant/adhesive, placed within the shrinkable tubing, the sealant/adhesive having a first portion proximate to an edge of the shrinkable tubing;
(iii) the sealant/adhesive having a strip of high viscosity sealant/adhesive proximate a strip of low viscosity sealant/adhesive;
(b) wherein upon an application of heat to the device after installation of the device over the electrical terminal, the shrinkable tubing starts to recover, the first portion of the sealant/adhesive flows and seals free ends of the plurality of electrical wires to seal the free ends of the electrical wires.

US Pat. No. 10,367,252

BROADBAND ANTENNA

Apple Inc., Cupertino, C...

1. An electronic device having opposing front and rear faces, comprising:a housing having a metal housing wall that forms an antenna ground for an antenna and having a window at the rear face;
a light-based component aligned with the window;
a coil that surrounds the light-based component;
wireless power receiver circuitry that uses the coil to receive wireless power signals through the rear face; and
radio-frequency transceiver circuitry configured to transmit and receive signals through the rear face using an antenna resonating element for the antenna.

US Pat. No. 10,367,243

MINIATURE LTCC COUPLED STRIPLINE RESONATOR FILTERS FOR DIGITAL RECEIVERS

BAE Systems Information a...

1. A low temperature co-fired ceramic stripline resonator filter comprising:a first layer configured as a ground layer comprising a metal;
a second layer comprising a dielectric material;
a third layer configured as a conductor layer comprising the metal and the dielectric material, the metal comprising a plurality of resonators comprising a first half of a stripline resonator pair arranged with an interdigital topology;
a fourth layer comprising the dielectric material;
a fifth layer configured as a conductor layer comprising the metal and the dielectric material, the metal comprising a plurality of resonators comprising a second half of the stripline resonator pair arranged with an interdigital topology;
a sixth layer comprising the dielectric material;
a seventh layer configured as a ground layer comprising the metal;
wherein the first, second, third, fourth, fifth, sixth and seventh layers are assembled to form the stripline filter having a width, a length, a thickness, a first end and a second end, and a first side and a second side;
a narrowband filter transformer loading structure launches an input and an output to a first and a second resonator of the stripline resonator pair, respectively;
a plurality of perimeter through plated vias being spaced apart along the length of the first side and along the length of the second side of the stripline filter and extending through the stripline filter from the first layer to the seventh layer creating a series of electric walls to contain electromagnetic fields inside the stripline filter; and
a plurality of through plated vias located between adjacent resonators of the stripline resonator pair and extending through the stripline filter from the first layer to the seventh layer to create a series of further electric walls thereby reducing the coupling between the adjacent resonators thereby forming a narrowband filter with a bandwidth of about 0.3 GHz to less than 1 GHz.

US Pat. No. 10,367,238

SPACE EFFICIENT BATTERY PACK DESIGNS

FORD GLOBAL TECHNOLOGIES,...

1. A battery pack, comprising:a first side oriented battery assembly;
a second side oriented battery assembly;
a vent chamber arranged between said first side oriented battery assembly and said second side oriented battery assembly; and
a heat exchanger device positioned axially between one of said first side oriented battery assembly and said second side oriented battery assembly and a third side oriented battery assembly,
wherein said heat exchanger device extends along a first longitudinal axis that is parallel to a second longitudinal axis of said vent chamber,
wherein said vent chamber is an enclosed space established by a top plate, a bottom plate, and two end plates,
wherein said top plate and said bottom plate rest against ledge strips that are attached to said first side oriented battery assembly or said second side oriented battery assembly,
wherein said top plate is contiguous with an enclosure lid and said bottom plate is contiguous with an enclosure base.

US Pat. No. 10,367,232

LOCALIZED SUPERCONCENTRATED ELECTROLYTES FOR STABLE CYCLING OF ELECTROCHEMICAL DEVICES

Battelle Memorial Institu...

1. An electrolyte, comprising:an active salt comprising lithium bis(fluorosulfonyl)imide (LiFSI), lithium bis(trifluoromethylsulfonyl)imide (LiTFSI), sodium bis(fluorosulfonyl)imide (NaFSI), sodium bis(trifluoromethylsulfonyl)imide (NaTFSI), lithium bis(oxalato)borate (LiBOB), sodium bis(oxalato)borate (NaBOB), LiPF6, LiAsF6, LiN(SO2CF3)2, LiN(SO2F)2, LiCF3SO3, LiClO4, lithium difluoro oxalato borate anion (LiDFOB), LiI, LiBr, LiCl, LiOH, LiNO3, LiSO4, or any combination thereof;
a solvent comprising dimethoxyethane (DME), dimethyl carbonate (DMC), 1,3-dioxolane (DOL), ethyl methyl carbonate (EMC), diethyl carbonate (DEC), dimethyl sulfoxide (DMSO), ethyl vinyl sulfone (EVS), tetramethylene sulfone (TMS), ethyl methyl sulfone (EMS), ethylene carbonate (EC), vinylene carbonate (VC), fluoroethylene carbonate (FEC), 4-vinyl-1,3-dioxolan-2-one, dimethyl sulfone, methyl butyrate, ethyl propionate, trimethyl phosphate, triethyl phosphate, gamma-butyrolactone, 4-methylene-1,3-dioxolan-2-one, methylene ethylene carbonate (MEC), 4,5-dimethylene-1,3-dioxolan-2-one, allyl ether, triallyl amine, triallyl cyanurate, triallyl isocyanurate, water, or any combination thereof, wherein the active salt is soluble in the solvent and a molar ratio of the active salt to the solvent is within a range of from 0.7 to 1.5; and
a diluent comprising 1,1,2,2-tetrafluoroethyl-2,2,2,3-tetrafluoropropyl ether (TTE), bis(2,2,2-trifluoroethyl) ether (BTFE), 1,1,2,2,-tetrafluoroethyl-2,2,2-trifluoroethyl ether (TFTFE), methoxynonafluorobutane (MOFB), ethoxynonafluorobutane (EOFB), or any combination thereof, wherein the active salt has a solubility in the diluent at least 10 times less than a solubility of the active salt in the solvent.

US Pat. No. 10,367,226

NA BASED SECONDARY BATTERY

SK INNOVATION CO., LTD., ...

1. A Na based secondary battery comprising:an anode containing sodium or a sodium alloy;
a cathode containing metal halide, wherein the metal halide comprises sodium metal halide and a halide of at least one metal selected from a group consisting of transition metals, and Groups 12 to 14 metals, a solvent dissolving the metal halide, anda sodium ion conductive solid electrolyte separating the cathode and the anode from each other,wherein the secondary battery is charged by a charge reaction according to the following Reaction Formula 1 and discharged by a discharge reaction according the following Reaction Formula 2
mNaX+M?mNa+MXm  (Reaction Formula 1)
mNaX+M?mNa+MXm  (Reaction Formula 2)
wherein M is at least one metal selected from a group consisting of a group consisting of the transition metals and Groups 12 to 14 metals, X is a halogen atom, and m is a natural number of 1 to 4,
in which sodium halide (NaX) and metal halide (MXm) of Reaction Formula 1 and 2 are dissolved by the solvent at the time of charging and discharging; andthe cathode further comprises excess NaX (naq)(con) wherein the halide ion X is the same or different from the halide ion of Reaction Formula 1 or 2, andwherein (naq) means the NaX is dissolved in the solvent, and (con) means the NaX does not participate in the charge and discharge reaction of Formulas 1 and 2.

US Pat. No. 10,367,218

ELECTRODE CATALYST LAYER FOR FUEL CELL, METHOD FOR PRODUCING THE SAME, AND MEMBRANE ELECTRODE ASSEMBLY AND FUEL CELL USING THE CATALYST LAYER

NISSAN MOTOR CO., LTD., ...

1. An electrode catalyst layer for fuel cell comprising a catalyst containing a catalyst carrier and a catalytic metal carried on the catalyst carrier and an electrolyte, wherein the electrolyte is a proton-conducting polymer,wherein the catalyst is partially coated with the proton-conducting polymer,
a specific surface area of the catalytic metal which a reactant gas of the fuel cell can reach without passing through the electrolyte is 50% or more, with respect to the total specific surface area of the catalytic metal, the catalytic metal is formed to have a total specific surface area of between 5 and 60 m2/g related to the catalyst carrier,
the catalyst has mesopores with a radius of 1 nm or more and less than 5 nm, a part of mesopore openings of the mesopores is not coated with the electrolyte, and at least a part of the catalytic metal is carried inside the mesopores, whose openings are not coated with the electrolyte, and
the difference between the volume of mesopores of the catalyst carrier before carrying the catalytic metal and the volume of mesopores of the catalyst after carrying the catalytic metal is 0.02 cc/g carrier or more.

US Pat. No. 10,367,206

METHOD FOR PREPARING METAL CATALYST SUPPORTED IN POROUS CARBON SUPPORT USING PLANT

Korea Institute of Scienc...

1. A method for preparing a metal catalyst supported on a porous carbon support using a plant, comprising:(a) providing a plant having roots and stems;
(b) preparing a metal precursor-absorbed plant by soaking the plant in a solution comprising a metal precursor;
(c) preparing a catalyst precursor by drying the metal precursor-absorbed plant;
(d) preparing a char by charring the catalyst precursor, wherein the preparing the char step comprises:
(d-1) preparing a primary char by charring the catalyst precursor under an air condition;
(d-2) preparing a secondary char by charring the primary char under an inert gas condition; and
(d-3) preparing a tertiary char by charring the secondary char under an ammonia gas condition; and
(e) preparing a metal catalyst supported on a porous carbon support by treating the char with an acid.

US Pat. No. 10,367,191

TIN SILICON ANODE ACTIVE MATERIAL

StoreDot Ltd., Herzeliya...

1. An anode, comprising anode active material particles which comprise 5-80% tin, wherein the anode active material particles further comprise nanoparticles attached thereto, wherein the nanoparticles are at least one order of magnitude smaller than the anode active material particles.

US Pat. No. 10,367,186

SECONDARY BATTERY INCLUDING AN INSULATING MEMBER

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:an electrode assembly comprising a first electrode and a second electrode;
a case containing the electrode assembly;
a cap plate sealing an opening of the case;
a collector terminal electrically connected to the first electrode of the electrode assembly and protruding through the cap plate to an outside of the case;
a coupling plate on the cap plate;
an insulating member on at least one area of the coupling plate; and
a terminal plate on the coupling plate and coupled to the collector terminal at the outside of the case, the insulating member being between the terminal plate and an outer surface of the cap plate,
wherein, in a normal operating state in which the first electrode and the second electrode are not short circuited, the terminal plate is electrically connected to the first electrode of the electrode assembly through the collector terminal and is electrically connected to the cap plate through at least a portion of the coupling plate that is in contact with the cap plate, and the second electrode of the electrode assembly is electrically insulated from the cap plate.

US Pat. No. 10,367,180

BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A battery pack, comprising:a battery holder comprising a cell holder accommodating a plurality of battery cells and a flange formed on a lateral side of the cell holder, wherein at least one coupling hole is formed in the flange;
a lead terminal comprising a lead plate and a lead tab, wherein the lead plate covers electrodes of the battery cells, wherein the lead tab extends from the lead plate toward the flange, wherein the lead tab includes a first portion downwardly extending from an end of the lead plate and a second portion outwardly extending from the first portion, wherein the first and second portions are formed on different planes, wherein at least one coupling hole is formed in the second portion of the lead tab, and wherein the second portion of the lead tab does not vertically overlap the lead plate;
a bus bar configured to form an electrical path between the lead tab and an external terminal, wherein at least one coupling hole is formed in the bus bar; and
a pack case comprising a coupler, wherein the external terminal is formed on the pack case, wherein a fastener is inserted into the at least one coupling hole of the bus bar, the at least one coupling hole of the second portion of the lead tab, and the at least one coupling hole of the flange, and wherein the fastener is engaged with the coupler.

US Pat. No. 10,367,164

FOLDABLE DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A foldable display apparatus that is adjustable between a folded configuration and an unfolded configuration, the foldable display apparatus comprising:a flexible display panel that is foldable;
a case comprising:
a first case that supports a first side of the flexible display panel; and
a second case that supports a second side of the flexible display panel;
an elastic piece connecting the first case to the second case, the elastic piece being substantially flat in the unfolded configuration;
a link member connecting the first case to the second case and comprising a concave-convex type single body metal sheet; and
a locking unit configured to prevent rotation of the first case and the second case in a folding direction when the foldable display apparatus is in the unfolded configuration.

US Pat. No. 10,367,156

ORGANIC METAL COMPLEX, AND ORGANIC LIGHT EMITTING DEVICE AND DISPLAY APPARATUS USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a device, the method comprising:preparing a substrate provided with one of an anode or a cathode;
forming an organic compound layer;
forming the other of the anode or the cathode;
wherein the organic compound layer comprises a metal complex having a structure represented by the following general formula (1):
MLmL?n  (1)
wherein L and L?, which are different from each other, each represent a bidentate ligand;
wherein m represents an integer of 1 to 3 and n represents an integer of 0 to 2, provided that m+n is 3;
wherein M represents Ir;
wherein the partial structure MLm has a structure represented by the following general formula (8):

wherein the benzene ring with R41-R44 attached thereto in the formula (8) is further represented by any one of the following formulae:

wherein *1 shows the connection to the Ir;
wherein *2 shows the connection to the benzo[f]isoquinoline ring represented in the formula (8);
wherein R88 to R102, which may be identical to or different from each other, each represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryloxy group, a substituted or unsubstituted aralkyl group, an amino group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group;
wherein the partial structure ML?n has a structure represented by any one of the following general formulae (10) to (12):

wherein R45 to R52, which may be identical to or different from each other, each represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryloxy group, a substituted or unsubstituted aralkyl group, an amino group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group, and R47 and R48 may be bonded to form a benzene ring that is fused with the benzo[f]isoquinoline ring represented in the formula (8); and
wherein R65 to R79, which may be identical to or different from each other, each represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group, an alkoxy group, an aralkyl group, a substituted amino group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heterocyclic group, and adjacent substituents among R65 to R68 may be bonded to form a ring that is fused with the benzene ring represented in the formula (10), and adjacent substituents among R77 to R79 may be bonded to form a ring that is fused with the backbone represented in the formula (12).

US Pat. No. 10,367,143

ORGANIC SEMICONDUCTING COMPOUNDS

MERCK PATENT GMBH, Darms...

1. A compound comprising one or more divalent units of formula I
wherein
R1 on each occurrence identically or differently, denotes H or straight chain, branched or cyclic alkyl group with 1 to 30 C atoms in which one or more non-adjacent CH2 groups are optionally replaced, in each case independently from one another, by —O—, —S—, —C(O)—, —C(O)O—, —O—C(O)—, —O—CO(O)—O—, —SO2—, —SO3—, —NR0—, —SiR0R00—, —CF2—, —CR0?CR00—, —CY1?CY2— or —C?C— in such a manner that O and/or S atoms are not linked directly to one another, and in which one or more H atoms are optionally replaced by F, Cl, Br, I or CN, or denotes monocyclic or polycyclic aryl or heteroaryl, each of which is optionally substituted with one or more groups RS and has 4 to 30 ring atoms
X is O or S,
A1 denotes a
group,A2 denotes a group from the following formulae:

wherein V is on each occurrence identically or differently CR1 or N, W is O, S, NR1, C(R1)(R2), Si(R1)(R2), C?C(R1)(R2), C?O or Se, R1 has the meanings given above, and R4 and R5 independently of each other have one of the meanings given for R1,
A3 denotes a group selected from the following formulae:

wherein V is on each occurrence identically or differently CR1 or N, W is O, S, NR1, C(R1)(R2), Si(R1)(R2), C?C(R1)(R2), C?O or Se, R1 has the meanings given above, and R6, R7, R8 and R9 independently of each other have one of the meanings given for R1,
RS denotes, on each occurrence identically or differently, F, Br, Cl, —CN, —NC, —NCO, —NCS, —OCN, —SCN, —C(O)NR0R00, —C(O)X0, —C(O)R0, —C(O)OR0, —NH2, —NR0R00, —SH, —SR0, —SO3H, —SO2R0, —OH, —NO2, —CF3, —SF5, optionally substituted silyl, carbyl or hydrocarbyl with 1 to 40 C atoms that is optionally substituted and optionally comprises one or more hetero atoms,
R1, R00 independently of each other denote H or optionally substituted C1-40 carbyl or hydrocarbyl,
Y1, Y2 independently of each other denote H, F, Cl or CN,
X0 denotes halogen,
r, s are independently of each other 0, 1, 2, 3 or 4.

US Pat. No. 10,367,139

METHODS OF MANUFACTURING MAGNETIC TUNNEL JUNCTION DEVICES

Spin Memory, Inc., Fremo...

1. A method of manufacturing a Magnetic Tunnel Junction (MTJ) device comprising:forming portions of MTJ pillars including a free magnetic layer;
forming a conformal first insulating layer on the portion of MTJ pillars;
etching the conformal first insulating layer to form first sidewall insulators self-aligned to the MTJ pillars;
forming a first metal layer;
forming a conformal second insulating layer;
etching the conformal second insulating layer to form second sidewall insulators self-aligned to the MTJ pillars; and
selectively etching the first metal layer and the free magnetic layer to further form the MTJ pillars including pillar contacts coupled to the free magnetic layer.

US Pat. No. 10,367,138

MAGNETIC TUNNEL JUNCTION DEVICE

JAPAN SCIENCE AND TECHNOL...

1. A magnetic tunnel junction (MTJ) device, comprising:a first electrode comprising a first ferromagnetic material layer that includes Co, Fe, and B;
a barrier layer disposed over the first electrode, the barrier layer comprising a magnesium oxide (MgO) layer that is formed of a poly-crystalline MgO in which a (001) crystal plane is preferentially oriented; and
a second electrode disposed over the barrier layer and comprising a second ferromagnetic material layer that includes Co, Fe, and B, and
wherein each of the first and second ferromagnetic material layers is entirely crystallized,. and
wherein a value of x in MgOx for the MgO layer is greater than 0 and less than 1.

US Pat. No. 10,367,137

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY HAVING A VARIABLE RESISTANCE ELEMENT INCLUDING TWO FREE LAYERS

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory comprising a variable resistance element exhibiting different resistance states for storing data, the variable resistance element comprising:a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein the free layer includes:
a first free layer adjacent to the tunnel barrier layer and including CoFeB alloy; and
a second free layer spaced apart from the tunnel barrier layer by the first free layer and including at least one of CoFeBCd alloy or CoFeBSb alloy;
the variable resistance element further comprises: a seed layer under the free layer; and a capping layer on the pinned layer, wherein the first free layer is closer to the capping layer than the second free layer, and the second free layer is closer to the seed layer than the first free layer.

US Pat. No. 10,367,136

METHODS FOR MANUFACTURING A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (P-MTJ) MRAM HAVING A PRECESSIONAL SPIN CURRENT INJECTION (PSC) STRUCTURE

SPIN MEMORY, INC., Fremo...

9. The method as in claim 1, further comprising, adjusting a thickness of the MgO spin current coupling layer to achieve a spin polarization of at least 15-30%.

US Pat. No. 10,367,134

SHADOW MASK SIDEWALL TUNNEL JUNCTION FOR QUANTUM COMPUTING

INTERNATIONAL BUSINESS MA...

1. A tunnel junction device comprising:a first conducting layer having a height dimension greater than a width dimension, wherein a bottom of the first conducting layer is nearest to a substrate and a top of the first conducting layer is farthest from the substrate, wherein the height dimension extends vertically from the bottom to the top;
an oxide layer formed on the first conducting layer; and
a second conducting layer on the oxide layer covering a side portion of the first conducting layer, such that the oxide layer forms a sidewall tunnel junction between the second conducting layer and the side portion of the first conducting layer, wherein an angled portion of the second conducting layer is formed on a top of the first conducting layer such that an angled tunnel junction is formed, wherein the angled portion having a triangular shaped surface positioned to the angled tunnel junction.

US Pat. No. 10,367,133

EPITAXIAL SUPERCONDUCTING DEVICES AND METHOD OF FORMING SAME

The United States of Amer...

1. A method forming a superconducting region comprising the steps of:a. providing monolayers of a crystal;
b. cleaning the surface of said crystal;
c. introducing a plurality of molecules containing acceptor atoms to an uppermost monolayer of the crystal, thereby allowing said acceptor atoms to bind with said crystal;
d. allowing said acceptor atoms to incorporate into said crystal to provide a doped region of said crystal;
e. growing at least one monolayer of crystal over said doped region to form a new uppermost layer;
f. repeating steps c-e until a density of said acceptor atoms in said doped region is sufficient to allow the doped region to function as a superconductor at a desired critical temperature; and
g. encapsulating said superconducting region by growing a monolayer of crystal over said superconducting region.

US Pat. No. 10,367,132

NANOSCALE DEVICE COMPRISING AN ELONGATED CRYSTALLINE NANOSTRUCTURE

University of Copenhagen,...

1. A nanoscale device comprisingan elongated crystalline semiconductor nanostructure having a plurality of substantially plane side facets, and
a crystalline structured first facet layer of a superconductor material covering at least a part of at least one of said side facets,wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

US Pat. No. 10,367,131

EXTENDED AREA OF SPUTTER DEPOSITED N-TYPE AND P-TYPE THERMOELECTRIC LEGS IN A FLEXIBLE THIN-FILM BASED THERMOELECTRIC DEVICE

1. A method of a thin-film based thermoelectric module, comprising:forming the thin-film based thermoelectric module by sputter depositing pairs of N-type thermoelectric legs and P-type thermoelectric legs electrically in contact with one another on corresponding electrically conductive pads on a flexible substrate such that an area of each sputter deposited N-type thermoelectric leg and another area of each sputter deposited P-type thermoelectric leg is more than an area of the corresponding electrically conductive pad to allow for extension thereof outside the corresponding electrically conductive pad, the flexible substrate being one of: aluminum (Al) foil, a sheet of paper, teflon, plastic, a single-sided copper (Cu) clad laminate sheet, and a double-sided Cu clad laminate sheet, and the flexible substrate having a dimensional thickness less than or equal to 25 ?m;
rendering the formed thin-film based thermoelectric module flexible and less than or equal to 100 ?m in dimensional thickness based on choices of fabrication processes with respect to layers of the formed thin-film based thermoelectric module including the sputter deposited N-type thermoelectric legs and the P-type thermoelectric legs; and
encapsulating the formed thin-film based thermoelectric module with an elastomer to render the flexibility thereto, the elastomer encapsulation having a dimensional thickness less than or equal to 15 ?m, the flexibility enabling an array of thin-film based thermoelectric modules, each of which is equivalent to the thin-film based thermoelectric module formed on the flexible substrate with the elastomer encapsulation, to be completely wrappable and bendable around a system element from which the array of the thin-film based thermoelectric modules is configured to derive thermoelectric power, and a layer of the formed thin-film based thermoelectric module including the sputter deposited N-type thermoelectric legs and the P-type thermoelectric legs having a dimensional thickness less than or equal to 25 ?m.

US Pat. No. 10,367,129

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a mounting board comprising:
a base part, and
one or more wiring structures, each of which includes:
one or more first wiring layers located on an upper surface of the base part, and
one or more second wiring layers located on an upper surface of the one or more first wiring layers,
wherein a lower surface of the one or more second wiring layers contacts an upper surface of the one or more first wiring layers,
wherein, in a plan view, an area of each of the one or more second wiring layers is smaller than an area of each of the one or more first wiring layers;
one or more light emitting elements bonded to the second wiring layers via bonding members; and
a reflective member covering at least a portion of the bonding members and at least a portion of the one or more wiring structures,
wherein a reflectance of the one or more first wiring layers is higher than a reflectance of the bonding members,
wherein the one or more second wiring layers and the bonding members comprise the same material at their outermost surfaces,
wherein one or more outermost surfaces of the one or more first wiring layers comprise a metal selected from the group consisting of Al, Ag, Rh, Pt, Pd, and Ru, and an alloy containing at least one of these metals.

US Pat. No. 10,367,128

PIXEL STRUCTURE AND METHOD FOR THE FABRICATION THEREOF

Shenzhen China Star Optoe...

1. A method for fabricating a pixel structure for improving the utilization ratio of micro light emitting diodes, comprising:providing a substrate;
forming a black photoresist layer having a receiving cavity and an isolation region on the substrate;
coating a polyelectrolyte solution on the surface of the black photoresist layer except the isolation region, and air-drying the polyelectrolyte solution to form a polyelectrolyte layer;
coating a metal nanoparticle solution on the surface of the polyelectrolyte layer, and air-drying the metal nanoparticle solution to form a metal nanoparticle layer; and
aligning and transferring a micro light emitting diodes to the isolation region of the black photoresist layer.

US Pat. No. 10,367,127

LEAD FRAME INCLUDING HANGER LEAD, PACKAGE, AND LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A lead frame adapted to be incorporated in a package as being integrally formed with a supporting member, the package having a depression which is open on an upper side and in which a light-emitting element is to be mounted, side walls of the depression being mainly constituted of the supporting member, the lead frame comprising:at least one electrode arranged in a supporting member forming region to be supported by the supporting member and to define at least a part of a bottom surface of the depression, the supporting member forming region having an approximately rectangular shape in plan view, with the at least one electrode overlapping a first side of the approximately rectangular shape of the supporting member forming region in the plan view;
an outer frame connected to the at least one electrode and arranged outside of the supporting member forming region; and
at least one hanger lead extending from the outer frame so as to reach a second side of the approximately rectangular shape of the supporting member forming region with the second side being adjacent to the first side, the at least one hanger lead being arranged outside of the supporting member forming region, the at least one hanger lead being separated from the at least one electrode, the at least one hanger lead including at least one chamfered surface arranged on at least a part of an upper side corner of an end of the at least one hanger lead facing the supporting member forming region.

US Pat. No. 10,367,124

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A light emitting device comprising:a first film;
a first insulating layer over the first film;
a semiconductor layer over the first insulating layer;
a second insulating layer over the first insulating layer;
a gate electrode;
an interlayer insulating layer over the gate electrode and the second insulating layer;
an organic film over the interlayer insulating layer;
a light emitting element over the interlayer insulating layer, the light emitting element being electrically connected to the semiconductor layer; and
a sealant over the organic film,
wherein the gate electrode and the semiconductor layer overlap with each other with the second insulating layer provided therebetween,
wherein the sealant is in direct contact with a top surface of the organic film and an outermost side surface of the organic film, and
wherein the sealant is in direct contact with an upper surface of the first insulating layer in a region between an edge of the first film and the outermost side surface of the organic film.

US Pat. No. 10,367,123

LIGHT EMITTING DEVICE HAVING A DAM SURROUNDING EACH LIGHT EMITTING REGION AND A BARRIER SURROUNDING THE DAM AND FABRICATING METHOD THEREOF

Samsung Display co., Ltd....

1. A light emitting device comprising:a base substrate; and
a plurality of pixel regions on the base substrate, each of the pixel regions comprising:
a light emitting region, the light emitting region comprising a plurality of LEDs;
a barrier on the base substrate and defining the each of the pixel regions;
a dam on the base substrate to be spaced apart from the barrier, the dam being disposed in the each of the pixel regions to surround the light emitting region;
a plurality of first electrode lines disposed in the light emitting region; and
a plurality of second electrode lines disposed in the light emitting region, each of the second electrode lines spaced apart from each of the first electrode lines,
wherein at least one of the LEDs is electrically connected to one of the first electrode lines and one of the second electrode lines.

US Pat. No. 10,367,121

PACKAGE AND LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A package having a recess comprising:a pair of leads forming a surface of a bottom portion on the recess;
a first resin body forming a lateral wall on the recess;
a second resin body arranged between the pair of leads; and
a reflective film covering an inner surface of the lateral wall on the recess and an upper surface and a lower surface of the second resin body.

US Pat. No. 10,367,120

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A light-emitting diode, comprising:a light-emitting epitaxial laminated layer including:
a first semiconductor layer;
an active layer; and
a second semiconductor layer;
an ohmic contact layer over an upper surface of the light-emitting epitaxial laminated layer;
an expanding electrode over the ohmic contact layer;
a transparent insulating layer that covers the expanding electrode and an exposed ohmic contact layer and having a hole through the transparent insulating layer in a position corresponding to the expanding electrode; and
a welding wire electrode over the transparent insulating layer and coupled to the expanding electrode via the hole.

US Pat. No. 10,367,119

METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light-emitting device, the method comprising:providing a light-emitting element including a first region in a plan view thereof and a second region other than the first region, the second region not having an active layer disposed in the plan view of the light-emitting element, the light-emitting element including a layered semiconductor comprising the active layer located on the first region but not on the second region in the plan view of the light-emitting element, wherein the active layer is not visible from outside in a top view;
mounting the light-emitting element on a supporting member;
forming a phosphor layer so as to cover the light-emitting element;
determining a surplus portion of the phosphor layer; and
removing the phosphor layer at least partially from the second region in the light-emitting element.

US Pat. No. 10,367,117

APPARATUS AND METHOD FOR TRANSFERRING MICRO LIGHT-EMITTING DIODES

SHENZHEN CHINA STAR OPTOE...

1. An apparatus for transferring micro light-emitting diodes, which comprises: a main body, and a spraying module, a cooling module and a heating module disposed on said main body;said spraying module applied for spraying metallic adhesive liquid onto the micro light-emitting diodes that wait to transfer;
said cooling module applied for cooling the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes, thereby curing the metallic adhesive liquid to adhesively bond the main body with the wait-to-transfer micro light-emitting diodes together; and
said heating module applied for heating the cured metallic adhesive liquid, thereby melting the metallic adhesive liquid to separate the main body from the wait-to-transfer micro light-emitting diodes;
wherein said main body comprises a number of sequentially arranged transfer heads each disposed with a spraying nozzle on a bottom portion thereof, said spraying module sprays the metallic adhesive liquid onto the wait-to-transfer micro light-emitting diodes by the spraying nozzle;
wherein each neighboring pair of the transfer heads are disposed with a gas-blowing hole on therebetween, said cooling module blows gas outwardly via the gas-blowing hole, for cooling the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes.

US Pat. No. 10,367,116

METHOD OF REDUCING SODIUM CONCENTRATION IN A TRANSPARENT CONDUCTIVE OXIDE LAYER OF A SEMICONDUCTOR DEVICE

BEIJING APOLLO DING RONG ...

1. A semiconductor device manufacturing apparatus, comprising:at least one semiconductor deposition module configured to form a semiconductor material stack including a p-n junction on a substrate;
a conductive oxide deposition module configured to deposit a transparent conductive oxide layer over the semiconductor material stack; and
a fluid treatment module configured to contact a physically exposed surface of the transparent conductive oxide layer with a fluid to remove sodium from the transparent conductive oxide layer.

US Pat. No. 10,367,113

PHOTOELECTRIC CONVERSION DEVICE, IMAGING ELEMENT, AND IMAGING DEVICE

CANON KABUSHIKI KAISHA, ...

1. A device comprising a plurality of photoelectric conversion elements containing a light-emitting material disposed at light incident side of the photoelectric conversion element, the plurality of photoelectric conversion elements, which convert light having color different from each other, comprises:an upper and a lower electrode;
at least one first photoelectric conversion portion between the upper electrode and the lower electrode, the first photoelectric conversion portion including a photoelectric conversion layer;
at least one second photoelectric conversion portion;
a first readout circuit connected to the first photoelectric conversion portion;
a second readout circuit connected to the second photoelectric conversion portion;
an incoming light-blocking member between the first photoelectric conversion portion and the second photoelectric conversion portion; and
a wavelength limiter disposed closer than the first photoelectric conversion portion to the light-incident side, the wavelength limiter limiting the wavelength of light in a range from a minimum wavelength ?L1 to a maximum wavelength ?L2,
wherein the incoming light-blocking member blocks light in a wavelength region from a minimum wavelength ?S1 to a maximum wavelength ?S2, and the incoming light-blocking member and the wavelength limiter satisfy the following relationship (A):
?S1??L1??L2??S2  (A), and
wherein the second photoelectric conversion portion converts light emitted from the light-emitting material into electrical charges.

US Pat. No. 10,367,112

DEVICE FOR DIRECT X-RAY DETECTION

Nokia Technologies Oy, E...

1. An apparatus comprising:a plurality of substantially parallel conductive channels separated from one another by a quantum dot material comprising a plurality of quantum dots separated from one another by ligands having a chain length which is sufficiently short to facilitate transfer of an electron or a hole between neighboring quantum dots,
source and drain electrodes configured to enable a flow of electrical current through the conductive channels, and
a substrate configured to support the conductive channels, quantum dot material and source and drain electrodes, the conductive channels extending substantially perpendicular to the surface of the substrate,
wherein the quantum dot material is configured to generate an electron-hole pair on exposure to incident electromagnetic radiation, and
wherein the conductive channels and quantum dot material are configured such that another one of the electron or the hole of the electron-hole pair is transferred to one of the conductive channels leaving the remaining charge carrier in the quantum dot material, a diffusion length of the remaining charge carrier is limited by a dimension of the conductive channels rather than a thickness of the quantum dot material, the remaining charge carrier exhibiting an electric field which causes a change in electrical current passing through at least one of the conductive channels, the change in electrical current indicative of one or more of the presence and magnitude of the incident electromagnetic radiation.

US Pat. No. 10,367,110

PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING

First Solar, Inc., Tempe...

1. A process for manufacturing a photovoltaic device having a front contact layer stack and a semiconductorer stack, the process comprising:plasma cleaning an exposed surface of the semiconductor stack by exposing it to a plasma of ionized gases, wherein the plasma cleaning step removes from about 5 to about 500 angstroms at the surface of the exposed surface;
exposing the exposed surface of the semiconductor stack to an atmosphere that contains from about 1% to about 60% oxygen in an otherwise inert atmosphere to form an oxide layer on the exposed surface; and
forming a back contact layer stack on the oxide layer.

US Pat. No. 10,367,109

BACK SHEET OF SOLAR CELL MODULE, AND SOLAR CELL MODULE

DAIKIN INDUSTRIES, LTD., ...

1. A back sheet for a solar cell module, comprising:a water-impermeable sheet; and
a film,
the film being disposed on at least one side of the water-impermeable sheet and being formed from a coating containing a fluorine-containing copolymer,
the fluorine-containing copolymer containing:
(a) a C2-C3 perhaloolefin structural unit;
(b) a vinyl acetate structural unit;
(c) a hydroxy-containing vinyl monomer structural unit represented by the formula (1):
CH2?CH—(CH2)l—O—(CH2)m—OH,wherein 1 is 0 or 1, and m is an integer of 2 or greater; and(d) a carboxy-containing monomer structural unit represented by the formula (2):
R1R2C?CR3—(CH2)n—COOHwherein R1, R2, and R3 are the same as or different from each other, and are each a hydrogen atom or a C1-C10 linear or branched alkyl group, and n is 0 or 1.

US Pat. No. 10,367,108

PHOTODETECTION DEVICE AND IMAGING DEVICE

PANASONIC INTELLECTUAL PR...

1. A photodetection device, comprising:a photoelectric converter that generates charge;
a first charge transfer channel that has a first end and a second end, the first end being connected to the photoelectric converter, charge from the photoelectric converter being transferred in the first charge transfer channel in a first direction from the first end toward the second end;
a second charge transfer channel that diverges from the first charge transfer channel at a first position of the first charge transfer channel;
a third charge transfer channel that diverges from the first charge transfer channel at a second position of the first charge transfer channel, the second position being further than the first position from the first end in the first direction;
a first charge accumulator that accumulates charge transferred from the first charge transfer channel through the second charge transfer channel;
a second charge accumulator that accumulates charge transferred from the first charge transfer channel through the third charge transfer channel;
a first gate electrode that switches between transfer and cutoff of charge in the first charge transfer channel; and
at least one second gate electrode that switches between transfer and cutoff of charge in the second charge transfer channel, and that switches between transfer and cutoff of charge in the third charge transfer channel, wherein
a width of the third charge transfer channel is greater than a width of the second charge transfer channel in a plan view.

US Pat. No. 10,367,106

INTEGRATED PHOTODETECTOR WAVEGUIDE STRUCTURE WITH ALIGNMENT TOLERANCE

INTERNATIONAL BUSINESS MA...

1. A sensor structure, comprising:a photodetector with a window exposing a portion of a waveguide structure; and
an encapsulating material of a single material fully encapsulating and surrounding the photodetector, wherein the encapsulating material extends across and directly contacts an uppermost surface of the photodetector, and the encapsulating material is within divots or recesses in shallow trench isolation (STI) structures.

US Pat. No. 10,367,105

SOLAR CELL, SOLAR CELL MODULE, AND MANUFACTURING METHOD FOR SOLAR CELL

Panasonic Intellectual Pr...

1. A solar cell comprising:a photoelectric converter that includes a light receiving surface and a back surface opposed to the light receiving surface and includes n-type regions and p-type regions which are alternately arranged in a first direction on the back surface; and
an electrode layer that is provided only on the back surface, wherein
the photoelectric converter includes a plurality of sub-cells arranged in a second direction intersecting with the first direction and an isolation region provided between adjacent sub-cells,
the electrode layer includes an n-side electrode which is provided on the n-type regions in a first sub-cell at an end of the plurality of sub-cells and disposed within the first sub-cell, a p-side electrode which is provided on the p-type regions in a second sub-cell at the other end of the plurality of sub-cells and disposed within the second sub-cell, and a plurality of sub-electrodes which are provided over two adjacent sub-cells,
each sub-electrode of the plurality of sub-electrodes comprises:
a plurality of n-side parts which are provided on the n-type regions in one sub-cell of the two adjacent sub-cells;
a plurality of p-side parts which are provided on the p-type regions in the other sub-cell of the two adjacent sub-cells; and
a plurality of connection parts, each connecting one of the plurality of n-side parts and one of the plurality of p-type parts, and
in plan view, the plurality of connection parts are arranged along the first direction and spaced apart from each other over the isolation region, wherein
the photoelectric converter further includes:
a first conductivity type layer on the back surface, which forms the n-type regions;
a second conductivity type layer on the back surface, which forms the p-type regions; and
a third conductivity type layer on the light receiving surface, the third conductivity type layer having a first surface facing the light receiving surface of the substrate, and a second surface opposite to the first surface, and
the isolation region extends from the second surface of the third conductivity type layer to the back surface of the substrate through the third conductivity type layer and the substrate.

US Pat. No. 10,367,104

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell, comprising:a semiconductor substrate;
a conductive region on or at the semiconductor substrate;
an electrode electrically connected to the conductive region; and
a passivation layer on a light incident surface of the semiconductor substrate,
wherein the passivation layer comprises a first layer in contact with the light incident surface of the semiconductor substrate and formed of silicon oxynitride for ultraviolet stability,
wherein the first layer comprises a plurality of phases of the silicon oxynitride,
wherein the plurality of phases are formed of the same material of the silicon oxynitride having different compositions,
wherein the plurality of phases comprises a plurality of first phases and a plurality of second phases,
wherein the plurality of first phases have a higher oxygen content and a lower nitrogen content than that of the plurality of the second phases, and
wherein the plurality of first phases and the plurality of second phases are alternatively positioned in a thickness direction of the first layer,
wherein the plurality of first phases are in contact with the semiconductor substrate, and
wherein the plurality of first phases have different oxygen and nitrogen content from each other, or the plurality of second phases have different oxygen and nitrogen content from each other.

US Pat. No. 10,367,103

PHOTOELECTRIC CONVERSION ELEMENT

Ricoh Company, Ltd., Tok...

1. A photoelectric conversion element comprising:a first electrode having opaqueness to light and formed of a metal;
a hole blocking layer provided on the first electrode;
an electron transport layer provided on the hole blocking layer;
a hole transport layer provided on the electron transport layer; and
a second electrode provided on the hole transport layer and having transmissivity to light,
wherein
the hole blocking layer comprises an oxide of the metal in the first electrode, and the hole transport layer comprises a basic compound of formula (1):

wherein R1 and R2 represent a substituted or unsubstituted alkyl group or aromatic hydrocarbon group and may be identical or different, and R1 and R2 may bind with each other to form a substituted or unsubstituted heterocyclic group comprising a nitrogen atom.

US Pat. No. 10,367,102

ELECTRONIC COMPONENT AND EQUIPMENT

CANON KABUSHIKI KAISHA, ...

1. An electronic component comprising:a support member in which a recess part having a bottom face and a side face is provided; and
a device unit that includes a substrate and fixed to the support member so that a primary face of the substrate faces the recess part,
wherein an opening width of the recess part is, on a side of a bottom of the recess part with respect to the primary face, narrower than a width of the device unit and, on an opposite side of the bottom of the recess part with respect to the primary face, wider than the width of the device unit,
wherein an end face of the substrate overlaps with the side face of the recess part in a direction perpendicular to the primary face of the substrate, and
wherein a photoelectric conversion element is arranged on the primary face of the substrate.

US Pat. No. 10,367,101

SCHOTTKY DIODE AND METHOD OF MANUFACTURING THE SAME

GPOWER SEMICONDUCTOR, INC...

1. A Schottky diode, comprising:a substrate;
a first semiconductor layer located on the substrate;
a second semiconductor layer located on the first semiconductor layer, two-dimensional electron gas being formed at an interface between the first semiconductor layer and the second semiconductor layer;
a cathode located on the second semiconductor layer and forming an ohmic contact with the second semiconductor layer;
a first passivation dielectric layer located on the second semiconductor layer;
a field plate groove formed in the first passivation dielectric layer; and
an anode covering the field plate groove and a portion of the first passivation dielectric layer,
wherein a distance between a bottom surface of the field plate groove and the two-dimensional electron gas in a height direction is greater than 5 nm.

US Pat. No. 10,367,099

TRENCH VERTICAL JFET WITH LADDER TERMINATION

United Silicon Carbide, I...

1. A vertical JFET, comprising:a) a substrate, the substrate having a top and a bottom vertically, the substrate having a perimeter horizontally;
b) an active cell region, the active cell region being on the top of the substrate and comprising source regions, gate regions, active region trenches, and active region mesas;
c) a backside drain connection, the backside drain connection being on the bottom of the substrate;
d) a termination region, the termination region being on the top of the substrate and comprising termination region trenches and termination region mesas;
e) in each mesa of the termination region, a region with source doping, the region with source doping being at the top of the mesa and having an N doping type and a doping concentration that is the same as the doping concentration of the source regions, wherein the regions with source doping are ohmically isolated from each other and from the source regions; and
f) in each termination region mesa, a region with gate doping, the region with gate doping being on each wall of the mesa and having a P doping type and a doping concentration that is the same as the doping concentration of the gate regions, wherein the regions with gate doping are ohmically isolated from each other and from the gate regions,
g) such that in each mesa of the termination region, the regions with gate doping on each wall of the mesa abut and form a PNP structure with the region with source doping.

US Pat. No. 10,367,098

VERTICAL JFET MADE USING A REDUCED MASKED SET

United Silicon Carbide, I...

1. A vertical JFET, comprising:a) a substrate, the substrate having a top and a bottom vertically, the substrate having a perimeter horizontally;
b) a backside drain connection, the backside drain connection being on the bottom of the substrate; and
c) on the top of the substrate, an active cell region and a termination region, the active cell region and the termination region each comprising a plurality of mesas and a plurality of trenches;
d) wherein each mesa comprises gate-doped regions on the sides of the mesa, a source-doped region at the top of the mesa, and, between the gate-doped regions and below the source-doped region, a channel region;
e) wherein each mesa further comprises, atop the source-doped region, a source contact silicide region; and
f) wherein each trench comprises, at the bottom of the trench, a gate-doped region connecting to the gate-doped regions of the mesa, and atop the gate-doped region of the trench, a gate contact silicide region;
g) the vertical JFET further comprising a gate buss connecting the gate contact silicide regions of the active cell region, and a source buss connecting the source contact silicide regions of the active cell region;
h) wherein the gate contact silicide regions and the source contact silicide regions of the termination region are individually ohmically isolated from each other, from the gate buss, and from the source buss; and
i) wherein the doping levels of the gate-doped regions, the source-doped regions, and the channel regions, and the width of the mesas in the termination region, are selected such that a punch through voltage of the mesas of the termination region is less than a breakdown voltage of a P-N junction between the gate-doped region and the source-doped region of each mesa of the termination region, such that an off-state blocking voltage of the vertical JFET is the sum of the punch-through voltages of the P-N junctions of the gate-doped regions and the source-doped regions of the termination region.

US Pat. No. 10,367,097

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A liquid crystal display device, comprising:a first substrate and a second substrate spaced apart from each other;
a liquid crystal layer between the first substrate and the second substrate;
a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate;
a first switching element connected to the gate line, the data line, and the first sub-pixel electrode; and
a second switching element connected to the gate line, the first sub-pixel electrode, and the second sub-pixel electrode,
wherein the first switching element has a threshold voltage that is lower than a threshold voltage of the second switching element, and
wherein the first switching element includes a semiconductor layer having a thickness that is 1/y times a thickness of a semiconductor layer of the second switching element, y being a rational number greater than or equal to 3.

US Pat. No. 10,367,096

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, MODULE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductor;
a second conductor;
a third conductor;
a fourth conductor;
a fifth conductor;
a first insulator;
a second insulator;
a third insulator;
a fourth insulator;
a fifth insulator;
a semiconductor; and
an opening,
wherein the second insulator is over the first insulator,
wherein the semiconductor is over the second insulator,
wherein the first conductor and the second conductor are over the semiconductor,
wherein the third conductor is over the first conductor,
wherein the fourth conductor is over the second conductor,
wherein the third insulator is over the first insulator, the semiconductor, the first conductor, the second conductor, the third conductor, and the fourth conductor,
wherein the opening exposes part of the first insulator, part of the semiconductor, part of the first conductor, part of the second conductor, part of the third conductor, and part of the fourth conductor,
wherein the fourth insulator is along a side surface and a bottom surface of the opening,
wherein the fifth insulator is over the fourth insulator,
wherein the fifth conductor comprises a region overlapping with the semiconductor with the fourth insulator and the fifth insulator therebetween, the region being included in the opening,
wherein the first conductor has a shape such that an end portion of the first conductor inwardly extends beyond an end portion of the second third conductor in the opening, and
wherein the second conductor has a shape such that an end portion of the second conductor inwardly extends beyond an end portion of the fourth conductor in the opening.

US Pat. No. 10,367,094

SOURCE/DRAIN STRUCTURE HAVING MULTI-FACET SURFACES

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a semiconductor substrate having a source/drain region and a gate region;
a fin structure disposed over the semiconductor substrate, the fin structure including a first portion having a first height in the source/drain region and a second portion having a second height in the gate region, the second height being different than the first height;
a gate structure disposed over the first portion of the fin structure, the gate structure including a gate dielectric physically contacting the first portion of the fin structure;
a plurality of isolation regions over the semiconductor substrate; and
a source/drain feature disposed over the second portion of the fin structure in the source/drain region, the source/drain feature including:
multiple lower portions that are isolated from each other by a lateral separation; and
a single upper portion over the isolation regions, wherein the single upper portion is merged from the multiple lower portions, wherein the single upper portion has a top surface facing away from a top surface of the isolation regions, wherein the top surface of the single upper portion includes a first flat surface connected to a first multi-facet surface and a second flat surface connected to the first multi-facet surface.

US Pat. No. 10,367,093

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

1. An apparatus comprising:a substrate comprising Si;
a fin comprising Si on the substrate;
a gate electrode having a work function metal comprising: W, Ta, Ti, and N;
a first spacer;
a second spacer, wherein the first and second spacers comprise N;
a gate dielectric between: the gate electrode and the fin, the gate electrode and the first spacer, and the gate electrode and the second spacer, wherein the gate dielectric comprises Hf and O,
a source; and
a drain;
wherein:
a portion of the fin under the gate electrode has a first width,
a portion of the fin outside the gate electrode and closer to the drain or source regions has a second width, and
the second width is greater than the first width.

US Pat. No. 10,367,090

SILICON CARBIDE SEMICONDUCTOR DEVICE, POWER MODULE, AND POWER CONVERSION DEVICE

Hitachi, Ltd., Tokyo (JP...

1. A silicon carbide semiconductor device comprising:a semiconductor substrate which includes an n-type substrate containing silicon carbide and an n-type semiconductor layer containing silicon carbide formed over the n-type substrate, the semiconductor substrate having an element region and a first region surrounding the element region in plan view;
a p-type first semiconductor region formed on an upper surface of the semiconductor substrate within the element region;
an n-type source region formed on an upper surface of the first semiconductor region;
a p-type first contact region formed on the upper surface of the first semiconductor region;
a p-type second semiconductor region formed on the upper surface of the semiconductor substrate within the first region and surrounding the element region in plan view;
a p-type second contact region formed on an upper surface of the second semiconductor region and surrounding the element region in plan view;
an n-type drain region formed on a lower surface of the semiconductor substrate;
a gate electrode formed on the upper surface of the first semiconductor region adjacent to the source region via an insulating film;
a first electrode formed on the second contact region; and
a conductive connecting portion formed on the second contact region and electrically connecting the first electrode and the second contact region to each other,
wherein the gate electrode, the source region and the drain region configure a field effect transistor, and
the second semiconductor region and the semiconductor substrate configure a diode.

US Pat. No. 10,367,089

SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY

GENERAL ELECTRIC COMPANY,...

1. A semiconductor device, comprising:a semiconductor substrate comprising silicon carbide, said substrate having a first surface and a second surface;
a contact layer disposed on the first surface of the substrate covering a portion of a source contact region;
a gate electrode disposed on a portion of the first surface of the substrate;
a drain electrode disposed on the second surface of the substrate;
a dielectric layer disposed on the gate electrode and extending in a direction normal to the first surface;
a remedial layer disposed on the dielectric layer, wherein said remedial layer is configured to mitigate negative bias temperature instability such that a change in threshold voltage is in a range of between 100 millivolts to 1 volt, wherein said change in threshold voltage occurs under a gate to source voltage bias and when a drain current is about 10 microamps with a VDS=0.1 V, wherein said remedial layer has a thickness of less than about 300 nm; and
a source electrode disposed on said remedial layer, wherein said source electrode is electrically coupled to the source contact region of the semiconductor substrate,
wherein said remedial layer comprises titanium and is configured to provide a continuous conformal coverage of the dielectric layer including in the direction normal to the first surface.

US Pat. No. 10,367,087

TRANSISTOR STRUCTURE INCLUDING A SCANDIUM GALLIUM NITRIDE BACK-BARRIER LAYER

1. A transistor comprising:a substrate;
a buffer layer disposed on the substrate;
a back-barrier layer on the buffer layer, the back-barrier layer including scandium gallium nitride;
a channel layer disposed on the back-barrier layer; and
a barrier layer disposed on the channel layer.

US Pat. No. 10,367,084

CASCODE HETEROJUNCTION BIPOLAR TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A structure formed using a device layer of a silicon-on-insulator substrate, the structure comprising:a first heterojunction bipolar transistor including a first emitter in the device layer, a first base layer with an intrinsic base portion on the first emitter, and a first collector on the intrinsic base portion of the first base layer, the intrinsic base portion of the first base layer arranged in a vertical direction between the first emitter and the first collector; and
a second heterojunction bipolar transistor including a second collector in the device layer, a second base layer with an intrinsic base portion on the second collector, and a second emitter on the intrinsic base portion of the second base layer, the intrinsic base portion of the second base layer arranged in the vertical direction between the second emitter and the second collector,
wherein the first emitter is coupled with the second collector, and the first emitter and the second collector each extend vertically in the device layer to a buried oxide layer of the silicon-on-insulator substrate.

US Pat. No. 10,367,080

METHOD OF FORMING A GERMANIUM OXYNITRIDE FILM

ASM IP Holding B.V., Alm...

1. A method of forming a germanium oxynitride film comprising:providing a substrate for processing in a reaction chamber;
using a germanium precursor and an oxygen precursor, performing an atomic layer deposition cycle of an oxide comprising germanium onto the substrate; and
before or after performing the atomic layer deposition cycle of the oxide, using a germanium precursor and a nitrogen precursor, performing an atomic layer deposition cycle of a nitride comprising germanium onto the substrate;
wherein the atomic layer deposition cycle of the oxide and the atomic layer deposition cycle of the nitride are repeated as desired in order to form the germanium oxynitride film of a desired thickness and stoichiometry, and
wherein the oxygen precursor and the nitrogen precursor are different.

US Pat. No. 10,367,079

METHOD AND STRUCTURE FOR FINFET COMPRISING PATTERNED OXIDE AND DIELECTRIC LAYER UNDER SPACER FEATURES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate having a fin projecting upwardly through an isolation structure over the substrate;
a gate stack over the isolation structure and engaging the fin;
a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack;
a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity; and
a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials, wherein the second dielectric layer is in physical contact with the gate spacer.

US Pat. No. 10,367,078

SEMICONDUCTOR DEVICES AND FINFET DEVICES HAVING SHIELDING LAYERS

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate; and
a gate structure over the substrate and comprising:
a high-k layer over the substrate;
a shielding layer over the high-k layer; and
an N-type work function metal layer over the shielding layer,
wherein a dielectric constant of the shielding layer is less than a dielectric constant of the high-k layer.

US Pat. No. 10,367,077

WRAP AROUND CONTACT USING SACRIFICIAL MANDREL

International Business Ma...

15. A semiconductor structure comprising at least:a plurality of unmerged fin structures;
a separate source/drain in contact with each unmerged fin structure of the plurality of unmerged fin structures, wherein the source/drain comprises a rectangular shape; and
a contact layer formed on sidewalls and a top surface of each source/drain.

US Pat. No. 10,367,076

AIR GAP SPACER WITH CONTROLLED AIR GAP HEIGHT

INTERNATIONAL BUSINESS MA...

1. A method for fabricating an air gap spacer in a FinFET, the method comprising:depositing a sacrificial gate structure in a gate region, the sacrificial gate structure having an upper sacrificial layer, a lower sacrificial layer, and an etch stop layer between the upper sacrificial layer and the lower sacrificial layer;
removing the upper sacrificial layer selective to the etch stop layer to expose a sidewall spacer region; and
depositing an airgap spacer material in the exposed sidewall spacer region to form an upper portion of a sidewall spacer, the upper portion having the air gap.