US Pat. No. 10,770,769

ION CONDUCTING HYBRID MEMBRANES

International Business Ma...

1. A device, comprising:a membrane comprising a polymer that is: (i) impermeable to oxygen, and (ii) insoluble in at least one polar solvent; and
Li ion conducting particles in the membrane, wherein at least a portion of the particles have a first exposed surface projecting from a first side of the membrane and a second exposed surface projecting from an opposed second side of the membrane, wherein the exposed surfaces of the conducting particles are substantially free of the polymer, and wherein the thickness of the membrane is 15 ?m to 100 ?m.

US Pat. No. 10,770,768

METAL-AIR BATTERY AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A metal-air battery comprising:an anode portion comprising a metal;
a cathode portion comprising a porous layer, wherein the porous layer comprises a reduced non-stacked graphene oxide; and
an electrolyte disposed between the anode portion and the cathode portion,
wherein adjacent layers of the reduced non-stacked graphene oxide of the porous layer which are separated by an interval of about 1 nanometer to about 0.15 micrometer,
wherein the porous layer has a porosity of 70 volume percent to 99 volume percent, and
wherein the reduced non-stacked graphene oxide has mesopores and nanopores that are smaller than the mesopores.

US Pat. No. 10,770,767

LITHIUM-AIR BATTERY SYSTEM USING VORTEX TUBE

Hyundai Motor Company, S...

1. A lithium-air battery system using a vortex tube, comprising:a lithium-air battery;
a gas supply device configured to supply a reaction gas for electricity production to the lithium-air battery;
the vortex tube disposed between the lithium-air battery and the gas supply device to divide the gas, supplied from the gas supply device, into a high-temperature gas and a low-temperature gas;
a first 3-way valve disposed between the gas supply device and a compressed-air supply port formed in a main body of the vortex tube; and
a second 3-way valve disposed on a side of a gas outlet and a cooling path outlet of the lithium-air battery,
wherein the high-temperature gas, produced in the vortex tube, is supplied to the lithium-air battery, and simultaneously, the low-temperature gas is supplied to a cooling path in the lithium-air battery.

US Pat. No. 10,770,766

HEATING CONTROL DEVICE

HONDA MOTOR CO., LTD., T...

1. A heating control device comprising:a storage battery that supplies electric power to an electric motor as a driving source of an electric vehicle;
a heat generation portion that heats the storage battery using heat generated by current flowing;
an effective capacity estimation portion that estimates a change in effective capacity when the heat generation portion heats the storage battery to a target temperature using heat generated by current flowing due to electric power supplied from the storage battery based on an effective capacity of the storage battery corresponding to a temperature of the storage battery and a state of charge of the storage battery;
a first controller that causes a current to flow from the storage battery to the heat generation portion only in a case where the effective capacity estimated by the effective capacity estimation portion is expected to be improved; and
a second controller that lowers a lower limit temperature of the storage battery stepwise depending on a duration time during which the electric vehicle is not operated and that controls current flowing from the storage battery to the heat generation portion every time the temperature of the storage battery decreases up to the lower limit temperature.

US Pat. No. 10,770,765

BATTERY MODULE WITH IMPROVED FRAME STRUCTURE AND FRAME ASSEMBLY FOR THE BATTERY MODULE

LG Chem, Ltd., Seoul (KR...

1. A battery module, comprising:(1) a cell assembly including a plurality of cells adjacently arranged along a length direction; and
(2) a frame assembly having
(2a) a bottom plate supporting the cell assembly from a lower portion,
(2b) a side plate perpendicular to the bottom plate and extending in the length direction to be in direct contact with the cells at an outermost side of the cell assembly, and
(2c) a top plate covering an upper portion of the cell assembly,
wherein an external air inflow space is provided in the length direction between the side plate and the cell assembly, and
wherein the external air inflow space has ends open to an outside of the battery module such that an entirety of a flow path through the external air inflow space between the ends is straight.

US Pat. No. 10,770,764

BATTERY PACK

TOYOTA JIDOSHA KABUSHIKI ...

1. A battery pack comprising:a plurality of batteries that include heat dissipation surfaces respectively;
a cooler that cools each of the plurality of the batteries through each of the heat dissipation surfaces; and
a viscous layer that is interposed between each of the heat dissipation surfaces and the cooler, the viscous layer containing a filler having a negative thermal expansion coefficient,
wherein a ratio of a mass of the filler to a mass of all constituents in the viscous layer other than the filler is equal to or larger than 0.4 wt % and is equal to or smaller than 1.25 wt %.

US Pat. No. 10,770,763

BATTERY CELL TO WHICH BUS BAR IS APPLIED

LG Chem, Ltd., (KR)

1. A battery cell comprising:an electrode assembly including a positive electrode plate and a negative electrode plate with a separator interposed therebetween;
a first positive electrode tap and a second positive electrode tap which are connected to the positive electrode plate and provided to protrudingly extend from opposite ends of the positive electrode plate;
a first negative electrode tap and a second negative electrode tap which are connected to the negative electrode plate and provided to protrudingly extend from opposite ends of the negative electrode plate;
a cell cover configured to surround the electrode assembly so that at least portions of the first and second positive electrode taps and the first and second negative electrode taps are exposed outside of the cell cover;
a first busbar facing an outer surface of the positive electrode plate, and having protrusion parts at positions respectively facing the first positive electrode tap and the second positive electrode tap, the protrusion parts respectively being connected to the first positive electrode tap and the second positive electrode tap;
a second busbar facing an outer surface of the negative electrode plate, and having protrusion parts at positions respectively facing the first negative electrode tap and the second negative electrode tap, the protrusion parts respectively being connected to the first negative electrode tap and the second negative electrode tap;
a positive electrode lead connected to one of the first positive electrode tap and the second positive electrode tap;
a negative electrode lead connected to one of the first negative electrode tap and the second negative electrode tap; and
a pouch case accommodating the electrode assembly and the first and second busbars so that at least portions of the positive electrode lead and the negative electrode lead are exposed outside of the pouch case.

US Pat. No. 10,770,760

REPLENISHED NEGATIVE ELECTRODES FOR SECONDARY BATTERIES

ENOVIX CORPORATION, Frem...

1. A method for activating a secondary battery, the secondary battery comprising a negative electrode, a positive electrode, a microporous separator between the negative and positive electrodes permeated with a carrier ion-containing electrolyte in ionic contact with the negative and positive electrodes, and a control unit programmed with a predefined cell end of discharge voltage Vcell,eod value, the negative electrode comprising anodically active silicon or an alloy thereof and having a coulombic capacity for the carrier ions, the positive electrode comprising a cathodically active material and having a coulombic capacity for the carrier ions, the negative electrode coulombic capacity exceeding the positive electrode coulombic capacity, the method comprising:(i) transferring carrier ions from the positive electrode to the negative electrode to at least partially charge the secondary battery wherein a solid electrolyte interphase is formed on a surface of the negative electrode during the transfer, and
(ii) transferring carrier ions from an auxiliary electrode to the positive electrode, to provide the secondary battery with a positive electrode end of discharge voltage Vpos,eod and a negative electrode end of discharge voltage Vneg,eod when the cell is at the predefined Vcell,eod value, wherein the value of Vpos,eod corresponds to a voltage at which the state of charge of the positive electrode is at least 95% of its coulombic capacity and Vneg,eod is at least 0.4 V (vs Li) but less than 0.9 V (vs Li).

US Pat. No. 10,770,759

METHOD OF MANUFACTURING LITHIUM ION SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A method of manufacturing a lithium ion secondary battery, the lithium ion secondary battery including a positive electrode that includes a positive electrode active material layer containing positive electrode active material particles, a negative electrode, and a nonaqueous electrolytic solution that contains a compound containing fluorine, the positive electrode active material particles having a surface on which a film containing fluorine and phosphorus is formed, the positive electrode active material layer including particles of at least one of a metal phosphate and a metal pyrophosphate, and the method comprising:initially charging the lithium ion secondary battery, the initial charging including:
a first step of charging the lithium ion secondary battery such that a voltage of the lithium ion secondary battery is increased to a first voltage which is in a lower decomposition range of the nonaqueous electrolytic solution;
a second step of applying a voltage to the lithium ion secondary battery so as to hold the voltage of the lithium ion secondary battery at the first voltage for a predetermined holding period in a range of 10 to 90 minutes; and
a third step of charging the lithium ion secondary battery to a second voltage, which is higher than the first voltage, after the second step,
wherein negative electrode active material of the negative electrode includes graphite while the initial charging occurs.

US Pat. No. 10,770,758

CABLE-TYPE SECONDARY BATTERY INCLUDING WINDING CORE HAVING GUIDE PORTIONS

LG Chem, Ltd., (KR)

1. A cable-type secondary battery, comprising:a winding core having guide portions formed by intaglio or relief in a spiral shape on a surface thereof;
a sheet-shaped first inner electrode formed on the outside of the winding core surface between the guide portions by spiral winding;
a sheet-shaped first separation layer formed on the outside of the first inner electrode by spiral winding;
a sheet-shaped second inner electrode formed on the outside of the first separation layer by spiral winding;
a second separation layer formed on the outside of the second inner electrode by spiral winding; and
an outer electrode formed on the outside of the second separation layer by spiral winding.

US Pat. No. 10,770,757

MANUFACTURING METHOD OF ELECTRODE ASSEMBLY

SEIKO EPSON CORPORATION, ...

1. A manufacturing method of an electrode assembly, the method comprising:a first step of forming an active material formed body including a communication hole;
a second step of providing a solid material including Li2+XC1?XBXO3 (X represents a real number exceeding 0 and equal to or smaller than 1) on the active material formed body without using a solvent;
a third step of melting the solid material; and
a fourth step of rapidly cooling and solidifying a molten material of the solid material,
wherein the communication hole is filled with the molten material in the third step, and
a cooling speed for rapidly cooling the molten material of the solid material is 102 degree/sec to 105 degree/sec in the fourth step.

US Pat. No. 10,770,756

METHOD OF MANUFACTURING A LITHIUM BATTERY

1. A method of manufacturing a battery with a substrate current collector, wherein the method comprises:forming an elongate and aligned electrically conductive structures on a substrate face with the electrically conductive structures having upstanding walls in relation to the substrate face; wherein the upstanding walls are formed with a first electrode layer covering said upstanding walls, a solid state electrolyte layer is provided on the first electrode layer; and wherein a second electrode is formed by covering the solid state electrolyte layer; and
forming a top current collector layer in electrical contact with the second electrode,
wherein the second electrode is shielded from the electrically conductive structures by an insulator covering a part of the electrically conductive structures adjacent an end side the electrically conductive structures to prevent an ion transport path between the first electrode layer and the second electrode, thereby mitigating stress build up near the end side of the electrically conductive structures.

US Pat. No. 10,770,755

PARTIALLY AND FULLY SURFACE-ENABLED TRANSITION METAL ION-EXCHANGING ENERGY STORAGE DEVICES

Global Graphene Group, In...

1. A partially or fully surface-enabled, metal ion-exchanging battery device comprising (a) a cathode, (b) an anode, (c) a porous separator disposed between said cathode and said anode, and (d) an electrolyte in physical contact with said cathode and said anode, wherein said electrolyte comprises a metal ion salt and a metal ion that is exchanged between said cathode and said anode during an operation of said battery device and said metal ion or metal ion salt is selected from transition metals, wherein at least one of said cathode and said anode comprises therein a source of said metal ion prior to a first charge or a first discharge cycle of the battery device and at least the cathode comprises a functional material having a surface-borne metal ion-capturing functional group or a nanostructured material having a metal ion-storing surface in direct contact with said electrolyte to reversibly capture or store said metal ion during charge-discharge operations of said battery, wherein the functional material comprises nanographene selected from single-layer graphene sheets or multi-layer graphene platelets, wherein said transition metal is selected from scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), zinc (Zn), cadmium (Cd), and combinations thereof.

US Pat. No. 10,770,753

ELECTROLYTE FOR FLUORIDE ION BATTERY AND FLUORIDE ION BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A fluoride ion battery comprising a cathode active material layer, an anode active material layer, and an electrolyte layer formed between the cathode active material layer and the anode active material layer, whereinthe cathode active material layer includes a cathode active material comprising at least one kind of metal simple substance, alloy, metal oxide, carbon material, and fluorides thereof, and the cathode active material is an active material that is defluoridated during discharge,
the anode active material layer includes an anode active material comprising at least one kind of metal simple substance, alloy, metal oxide, and fluorides thereof, and the anode active material is an active material that is fluoridated during discharge,
the electrolyte layer includes an electrolyte containing a fluoride complex salt as at least one of LiPF6 and LiBF4, and one or more organic solvents, and the electrolyte layer does not contain a fluoride salt having a fluoride ion as an anion component, and
B/A is 0.125 or more and 1 or less in the case when a total amount of all organic solvents in the electrolyte layer is regarded as A (mol) and a total amount of all the fluoride complex salt in the electrolyte layer is regarded as B (mol).

US Pat. No. 10,770,751

SOLID STATE LITHIUM-ION CONDUCTOR

SAMSUNG ELECTRONICS CO., ...

1. A compound of Formula 1 in a positive electrode, negative electrode or electrolyte, comprising:Li(6+(4?a)x+c)M4+(2?x)Aa+xO(7?c)N?c  (1)whereinM is a tetravalent cationic element,
A is a divalent or trivalent cationic element,
N? is an anion Group 15 element,
wherein when A is Y3+, In3+, Zn2?, or a combination thereof, 0.15 0?x?0.5, 0?c?2, and
((4?a)x+c)>0.

US Pat. No. 10,770,749

ELECTROLYTE ADDITIVE AND LITHIUM SECONDARY BATTERY COMPRISING THE SAME

1. A non-aqueous electrolyte comprising:a lithium salt;
a non-aqueous organic solvent; and
an electrolyte additive comprising:
a salt of an anion represented by Chemical Formula 1 below with Cs+ or Rb+:

wherein A is O or S, and R1 and R2 are each independently a C1-C10 alkyl group in which all or some of the hydrogen atoms are substituted with halogen atoms.

US Pat. No. 10,770,746

METHOD FOR PRODUCING A LITHIUM ION SECONDARY BATTERY

Envision AESC Japan Ltd.,...

1. A method for producing a lithium ion secondary battery in which a positive electrode, a heat-resistant insulating layer provided separator having a heat-resistant insulating layer formed of oxide particles on one surface of a resin porous substrate, and a negative electrode are laminated on one another, and a nonaqueous electrolyte is impregnated in the heat-resistant insulating layer provided separator, comprising:drying the heat-resistant insulating layer provided separator before laminating so that a water content in the heat-resistant insulating layer provided separator remains in a predetermined range,
wherein, in the drying, the water content in the heat-resistant insulating layer provided separator is decreased to the predetermined range by controlling a dew point and maintaining the predetermined range after reaching the predetermined range of the water content, and
wherein, in the drying, the heat-resistant insulating layer provided separator is dried by setting the dew point so as to attain a water content decrease rate such that a shape of the heat-resistant insulating layer provided separator after the drying defined by a length ratio Y that is a ratio of a length of the resin porous substrate to a length of the heat-resistant insulating layer satisfies an equation:
1?4?X?Y?1+4?X,
wherein D represents a thickness of the separator, L represents a length of the separator, and X represents a ratio (D/L) of the thickness D to the length L of the separator,
wherein, in the drying, the water content is decreased such that a water decrease rate ((1?W)/T) satisfies an equation:
((1?W)/T)?1.2, and
wherein W is a water content ratio W=w2/w1, T is a drying time of 0.5 hour, w1 is a water content before starting the drying, and w2 is a water content that is measured when T elapses after starting the drying.

US Pat. No. 10,770,745

MONOLITHICALLY INTEGRATED THIN-FILM SOLID STATE LITHIUM BATTERY DEVICE HAVING MULTIPLE LAYERS OF LITHIUM ELECTROCHEMICAL CELLS

Sakti3, Inc., Ann Arbor,...

1. A monolithically integrated thin-film solid-state lithium battery device comprising:a stacked arrangement of a plurality of layers of lithium electrochemical cells, each of the lithium electrochemical cells having a spatial region of less than 100 square centimeters, the stacked arrangement comprising:
a substrate having a layer thickness of less than 10 micrometers;
a first barrier layer formed over the substrate, the first barrier layer having a thickness of less than 0.1 micrometers and configured to inhibit lithium from reacting with moisture from the substrate;
a cathode current collector formed over the first barrier layer, the cathode current collector having an electrical conductivity of at least 107 S/m and a layer thickness of between about 0.1 and about 2 micrometers;
a cathode comprising a vanadium based oxide formed over the cathode current collector and having a layer thickness of between about 0.2 and about 2 micrometers;
a glassy electrolyte material formed over the cathode and having a layer thickness of between about 0.1 and about 1 micrometers;
an anode formed over the glassy electrolyte material and configured for electrochemical insertion or ion plating and having a layer thickness between about 0.2 and about 3 micrometers;
an anode current collector formed over the anode and having an electrical conductivity of at least 107 S/m and a layer thickness of between about 0.1 and about 2 micrometers; and
a second barrier layer formed over the anode current collector, the second barrier layer having a thickness of less than 0.1 micrometers and configured to prevent oxidation of the anode.

US Pat. No. 10,770,742

ELECTRICAL POWER DISTRIBUTION SYSTEM AND METHOD FOR A GRID-TIED REVERSIBLE SOLID OXIDE FUEL CELL SYSTEM

THE BOEING COMPANY, Chic...

1. A method for controlling a Reversible Solid Oxide Fuel Cell (RSOFC) system, comprising:selectively operating a fuel cell unit of a Reversible Solid Oxide Fuel Cell (RSOFC) system in either electrolysis mode or in fuel cell mode, wherein the RSOFC system is coupled to a power distribution system having a common bus that includes:
a power circuit breaker coupled to a bi-directional alternating-current-direct-current (AC/DC) converter that is coupled to the fuel cell unit; and
a plurality of subsystem circuit breakers coupled to a plurality of RSOFC subsystems;
providing power to the fuel cell unit from a power grid coupled to the RSOFC system via the common bus through the power circuit breaker and the AC/DC converter, when operating in electrolysis mode;
distributing power from the fuel cell unit to the power grid via the common bus through the power circuit breaker and the bi-directional AC/DC converter, when operating in fuel cell mode; and
powering the plurality of RSOFC subsystems via the common bus through the plurality of subsystem circuit breakers when the fuel cell unit operates in either electrolysis mode or fuel cell mode.

US Pat. No. 10,770,740

METHOD OF SHUTTING DOWN OPERATION OF FUEL CELL VEHICLE

HYUNDAI MOTOR COMPANY, S...

1. A method of shutting down operation of a fuel cell vehicle, the method comprising:an air supply blocking step of blocking, by a controller, an air supply to a fuel cell stack when an operation shutting down command of the fuel cell vehicle is applied;
a voltage raising step of increasing, by the controller, a voltage at a rear end of a stack main relay connected to the fuel cell stack such that the voltage at the rear end of the stack main relay is higher than a voltage at the fuel cell stack; and
a stack voltage blocking step of opening, by the controller, the stack main relay when the voltage at the rear end of the stack main relay is higher than a stack voltage by a predetermined voltage or more.

US Pat. No. 10,770,739

METHOD OF INSPECTING OUTPUT OF FUEL CELL

HONDA MOTOR CO., LTD., T...

1. A method of inspecting an output of a fuel cell, the fuel cell comprising an electrolyte membrane of solid polymer, an anode provided on one surface of the electrolyte membrane, and a cathode provided on the other surface of the electrolyte membrane,the method comprising:
an oxidation step of applying oxidation treatment to an electrode catalyst contained in the anode and the cathode;
and
a measurement step of measuring the output of the fuel cell after the oxidation treatment is applied to the electrode catalyst, by applying a measurement current which is smaller than a rated current of the fuel cell to the anode and the cathode;
wherein in the oxidation step, a fuel qas is supplied to the anode and an oxygen-containing gas is supplied to the cathode to cause a voltage between the anode and the cathode to be not less than a reduction potential of the electrode catalyst.

US Pat. No. 10,770,738

VEHICLE WITH FUEL CELL SYSTEM MOUNTED THEREON

Toyota Jidosha Kabushiki ...

1. A vehicle with a fuel cell system mounted thereon, the fuel cell system comprising:a fuel cell;
a plurality of tanks configured to store fuel gas to be used for power generation of the fuel cell, each tank having an opening/closing valve for switching over between execution and halt of supply of the fuel gas;
a plurality of supply flow paths connected to the opening/closing valves in the plurality of tanks, each supply flow path being configured to feed the fuel gas supplied from a respective one of the plurality of tanks;
a merging flow path configured to merge together the plurality of supply flow paths to feed the fuel gas to the fuel cell;
a fastening part situated at a fastening position and configured to fasten the merging flow path to a vehicle body of the vehicle; and
a controller configured to control opening and closing of the opening/closing valves, wherein
the merging flow path is fastened to the vehicle body at the fastening position, and
at a start-up of the fuel cell system, the controller is configured to exert such control as to:
select one of the opening/closing valves having a longest total flow path length out of the opening/closing valves, the total flow path length of each opening/closing valve being a sum of:
a length of the supply flow path connected to the opening/closing valve, and
a length of a portion of the merging flow path extending between the fastening position and a downstream end of the supply flow path that is connected to the opening/closing valve; and
open the one of the opening/closing valves having the longest total flow path length.

US Pat. No. 10,770,736

VIA DESIGNS FOR REMOVING WATER IN FUEL CELL STACKS

Daimler AG, Stuttgart (D...

1. A solid polymer electrolyte fuel cell comprising:a solid polymer electrolyte;
a cathode and an anode on opposite sides of the electrolyte;
an oxidant flow field plate for an oxidant reactant on the side of the cathode opposite the electrolyte; and
a fuel flow field plate for a fuel reactant on the side of the anode opposite the electrolyte;
wherein at least one of the oxidant and fuel flow field plates comprises a plurality of reactant flow field channels, a reactant transition region, at least one reactant via having first and second ends, and a reactant port; and wherein the plurality of reactant flow field channels is fluidly connected to the reactant transition region, the reactant transition region is fluidly connected to the first end of the at least one reactant via, and the second end of the at least one reactant via is fluidly connected to the reactant port;characterized in that:the surface of the at least one reactant via in the reactant flow field plate is superhydrophobic; and
the fuel cell comprises at least one additional via having first and second ends wherein:
the surface of the additional via is hydrophilic;
the hydrophilic additional via is fluidly connected in parallel to the superhydrophobic reactant via such that the first end of the hydrophilic additional via is fluidly connected directly to the reactant transition region and the second end or at least one branch from the hydrophilic additional via is fluidly connected directly to the superhydrophobic reactant via; and
the dimensions of the hydrophilic additional via are such that water appearing at its second end or the at least one branch will flow into the hydrophilic additional via by capillary action.

US Pat. No. 10,770,734

LITHIUM AIR BATTERY AND MANUFACTURING METHOD THEREFOR

LG CHEM, LTD., Seoul (KR...

1. A lithium air battery comprising:a positive electrode, which comprises a laminate on a gas diffusion layer, and which uses oxygen as a positive electrode active material,
wherein the laminate is formed by laminating carbon black secondary particles and consists of carbon black primary particles and graphene on the gas diffusion layer,
wherein pores in the positive electrode have a pore size range of exceeding 100 nm formed between the carbon black secondary particles, and
wherein the carbon black secondary particles comprise 7.4 to 44.4 wt % graphene;
a negative electrode disposed to face the positive electrode; and
a separator disposed between the positive electrode and the negative electrode,
wherein the carbon black secondary particles are spherical and have a diameter greater than 500 nm to 10 ?m or less.

US Pat. No. 10,770,732

CABLE-TYPE SECONDARY BATTERY INCLUDING SPACED SPRING INNER ELECTRODE SUPPORT WOUND ON OUTSIDE OF WINDING CORE

LG Chem, Ltd., (KR)

1. A cable-type secondary battery, comprising:a winding core;
an inner electrode support wound on the outside of the winding core in the form of a spaced spring so that the winding core may be exposed partially;
a sheet-shaped first inner electrode formed on the outside of the exposed winding core by spiral winding;
a sheet-shaped first separation layer formed on the outside of the first inner electrode by spiral winding;
a sheet-shaped second inner electrode formed on the outside of the first separation layer by spiral winding;
a second separation layer formed on the outside of the second inner electrode by spiral winding; and
an outer electrode formed on the outside of the second separation layer by spiral winding.

US Pat. No. 10,770,731

POSITIVE ELECTRODE CURRENT COLLECTOR AND PREPARATION METHOD AND USE THEREOF

1. A positive electrode current collector, having a multilayered structure and comprising a plastic thin film, wherein upper and lower surfaces of the plastic thin film are coated with a bonding force enhancement layer, an aluminum metal coating layer and an anti-oxidization layer in sequence, wherein the plastic thin film is OPP, PI, PET, CPP, or PVC.

US Pat. No. 10,770,730

THROUGH-WALL CURRENT COLLECTOR FOR A POUCH CELL

Robert Bosch Battery Syst...

1. An electrochemical cell includingan electrically-neutral cell housing formed of a flexible metal laminated polymer film sheet, the cell housing having a first housing portion, and a second housing portion that is joined to the first housing portion along a sealed joint to form a pouch,
an electrode assembly disposed in the cell housing, the electrode assembly including positive electrode portions alternating with negative electrode portions, the positive electrode portions and the negative electrode portions being separated by at least one separator and stacked along a stack axis, and
a current collector device that is electrically connected to one of the positive electrode portions and the negative electrode portions and exits the cell housing via an opening formed in the cell housing, wherein
the first housing portion comprises a base and a sidewall that protrudes from a perimeter of the base and surrounds the base to form an open-ended container,
the stack axis extends in a direction perpendicular to the base,
the opening is formed in the sidewall at a location spaced apart from the sealed joint and at a location facing the stack axis, and
the current collector device includes
a current collecting plate that is disposed between the sidewall and the one of the positive electrode portions and the negative electrode portions, is electrically connected to the one of the positive electrode portions and the negative electrode portions, is oriented parallel to the sidewall, and overlies the opening and,
a terminal plate that is oriented parallel to the sidewall, overlies the opening and is disposed outside the cell housing, the terminal plate directly contacting the current collecting plate via the opening so as to form an electrical connection with the current collecting plate.

US Pat. No. 10,770,729

ELECTRODE, POWER STORAGE DEVICE, AND ELECTRONIC EQUIPMENT

Semiconductor Energy Labo...

1. An electrode comprising:a stack comprising a current collector, an active material layer, and a friction layer,
wherein the stack includes a first portion, a second portion, and a third portion connected to the first portion and the second portion,
wherein the stack is curved in the third portion so that the first portion faces the second portion,
wherein the active material layer is in contact with a first surface of the current collector, and a second surface of the current collector is in contact with a first surface of the friction layer,
wherein the friction layer is curved in the third portion so that a second surface of the friction layer included in the first portion is in contact with the second surface of the friction layer included in the second portion, and
wherein a coefficient of static friction between the second surface of the friction layer included in the first portion and the second surface of the friction layer included in the second portion is smaller than a coefficient of static friction between the second surface of the current collector included in the first portion and the second surface of the current collector included in the second portion, wherein the coefficient of static friction between the friction layer included in the first portion and the friction layer included in the second portion is less than or equal to 0.05.

US Pat. No. 10,770,726

METHOD FOR MANUFACTURING ELECTRODE, ELECTRODE MANUFACTURED BY SAME, ELECTRODE STRUCTURE INCLUDING ELECTRODE, FUEL CELL OR METAL-AIR SECONDARY BATTERY, BATTERY MODULE INCLUDING CELL OR BATTERY, AND COMPOSITION FOR MANUFACTURING ELECTRODE

LG CHEM, LTD., Seoul (KR...

1. A method for manufacturing a battery or a fuel cell electrode, the method comprising:forming a film by applying a composition comprising a precursor of a composite metal oxide onto a base material,wherein the precursor of the composite metal oxide comprises:a first precursor comprising one to three first metals selected among lanthanum (La), strontium (St), gadolinium (Gd), samarium (Sm), barium (Ba), and bismuth (Bi); and
a second precursor comprising one to three second metals selected among manganese (Mn), cobalt (CO), iron (Fe), nicel (Ni), and calcium (Ca);wherein the base material is an electrolyte membrane; andmanufacturing an electrode by firing the film,
wherein in the firing, the film is sintered while the precursor of the composite metal oxide undergoes a chemical transformation to form a composite metal oxide.

US Pat. No. 10,770,725

ALKALINE BATTERY CATHODE STRUCTURES INCORPORATING MULTIPLE CARBON MATERIALS AND ORIENTATIONS

Energizer Brands, LLC, S...

1. A method of making a cathode structure for an alkaline battery comprising:a first mixing step including dispersing a first conductive material in a particulate active material and forming agglomerates in which the first conductive material is entrained within the agglomerates, wherein the active material comprises manganese dioxide; and
a second mixing step including adhering a second conductive material with at least a portion of a surface of the agglomerates; and
wherein the second conductive material comprises particles of a larger size in comparison to particles of the first conductive material.

US Pat. No. 10,770,724

POSITIVE ELECTRODE MATERIAL FOR LITHIUM SECONDARY BATTERIES

TOYOTA JIDOSHA KABUSHIKI ...

1. A positive electrode material for lithium secondary batteries, the material comprising:positive electrode active material particles each having a layered structure;
an electronic conductor disposed on a surface of the positive electrode active material particles; and
optionally a lithium conductor disposed on the surface of the positive electrode active material particles,
wherein the electronic conductor is a perovskite-type oxide represented by ABO3-? where A is the combination of La and at least one element selected from the group consisting of Ca, Sr and Ba; B is a combination of Co and at least one element selected from the group consisting of Mn and Ni, and ? is an oxygen deficiency value for achieving electrical neutrality,
wherein in a case where the positive electrode material contains the lithium conductor, the proportion of the lithium conductor disposed at planes other than the (003) plane of the positive electrode active material particles, with respect to a total amount of the lithium conductor disposed on the surface of the positive electrode active material particles, is not less than 50% and not more than 100%;
the proportion of the electronic conductor disposed at the (003) plane of the positive electrode active material particles, with respect to at total amount of the electronic conductor disposed on the surface of the positive electrode active material particles, is not less than 50% and not more than 100%.

US Pat. No. 10,770,721

LITHIUM METAL SECONDARY BATTERY CONTAINING ANODE-PROTECTING POLYMER LAYER AND MANUFACTURING METHOD

Global Graphene Group, In...

1. A lithium secondary battery comprising a cathode, an anode, and an electrolyte or separator-electrolyte assembly disposed between said cathode and said anode, wherein said anode comprises:a) a foil or coating of lithium or lithium alloy as an anode active material; and
b) a layer of polymer having a recoverable tensile strain no less than 5%, a lithium ion conductivity no less than 10?6 S/cm at room temperature, and a thickness from 1 nm to 10 ?m, wherein said polymer contains an ultrahigh molecular weight polymer having a molecular weight from 0.5×106 to 9×106 grams/mole and is disposed between said lithium or lithium alloy and said electrolyte or separator-electrolyte assembly, wherein said ultrahigh molecular weight polymer is a thermoplastic and is selected from polyacrylonitrile, polyethylene oxide, polypropylene oxide, polyethylene glycol, polyvinyl alcohol, polyacrylamide, poly(methyl methacrylate), poly(methyl ether acrylate), a copolymer thereof, a sulfonated derivative thereof, a chemical derivative thereof, or a combination thereof.

US Pat. No. 10,770,719

NEGATIVE ELECTRODE ACTIVE MATERIAL AND BATTERY

PANASONIC INTELLECTUAL PR...

1. A negative electrode active material comprising:a carbon material including boron; and
a silicon material including at least one selected from silicon and silicon oxide, wherein:
the silicon material does not include boron,
a peak of a B1s spectrum of the carbon material occurs at a binding energy of 187.0 eV or more and 188.5 eV or less, a B1s spectrum being measured by X-ray photoelectron spectroscopy,
the silicon oxide is SiOx, where 0.1?x?1.2,
a ratio of an amount of the silicon oxide included in the silicon material to a total amount of the negative electrode active material is 0.5% by weight or more and 50% by weight or less, and
a ratio of the area of the peak of the B1s spectrum of the carbon material which occurs at a binding energy of 187.0 eV or more and 188.5 eV or less to the total area of peaks of the B1s spectrum which occur at a binding energy of 184.0 eV or more and 196.5 eV or less is 50% or more.

US Pat. No. 10,770,718

LITHIUM-SULFUR SECONDARY BATTERY

Institute For Basic Scien...

1. A lithium-sulfur secondary battery comprising:a cathode current collector; and
a cathode electrode on the cathode current collector,
wherein the cathode electrode comprises:
a cathode active material sheet including sulfur-based active material particles including sulfur, a binder, and a conductive material,
a porous carbon interlayer electrode including a plurality of carbon fibers,
metal sulfide catalyst particles dispersed and positioned on the porous carbon interlayer electrode,
wherein the metal sulfide catalyst particles are also dispersed on the cathode active material sheet,
wherein the metal sulfide catalyst particles comprise tungsten disulfide (WS2).

US Pat. No. 10,770,714

ELECTRODE MANUFACTURING METHOD FOR IMPROVING BATTERY CAPACITY AND ELECTRODE MANUFACTURED THEREBY

LG CHEM, LTD., Seoul (KR...

1. A method for manufacturing an electrode, the method comprising the steps of:forming a collector having a first side edge, a second side edge, a bottom edge and a top edge;
applying a coating of an electrode active material onto the collector, the coating extending from the bottom edge of the collector to an upper edge spaced from the top edge of the collector; and
radiating a laser onto an area of the coating such that the end of an electrode active material layer, which has been obtained by applying the electrode active material, becomes straight, thereby removing the electrode active material, the area having a straight bottom edge located between the bottom edge of the collector and the upper edge of the coating.

US Pat. No. 10,770,713

FABRICATING METHOD OF ELECTRODE ASSEMBLY AND ELECTROCHEMICAL CELL CONTAINING THE SAME

LG Chem, Ltd., (KR)

1. A fabricating method of an electrode assembly comprising:forming a radical unit having a four-layered structure obtained by stacking a first electrode, a first separator, a second electrode, and a second separator one by one, wherein forming the radical unit includes:
step 1, coating the first and second separators with a coating material having adhesiveness by coating both sides of the first separator and coating both sides of the second separator;
step 2, cutting the first electrode and the second electrode;
step 3, attaching the first electrode, the first separator, the second electrode, and the second separator to each other simultaneously by bringing the first electrode, the first separator, the second electrode and the second separator into a parallel orientation such that the coated sides of the first separator face the first electrode and the second electrode and that one of the coated sides of the second separator faces the second electrode; and
step 4, cutting the first separator and the second separator so as to be longer than the first electrode and the second electrode; and
stacking at least two radical units one by one to form a unit stack part.

US Pat. No. 10,770,710

CONNECTION MODULE FOR A POWER STORAGE ELEMENT GROUP

AUTONETWORKS TECHNOLOGIES...

1. A connection module that is to be mounted on a power storage element group including power storage elements having a positive electrode terminal and a negative electrode terminal, the connection module comprising:bus bars each including a plate member that connects the positive electrode terminal and the negative electrode terminal of adjacent power storage elements among the power storage elements;
a first sheet member that is expandable and includes an adhesive member on a surface thereof; and
second sheet members disposed on the first sheet member at intervals and formed of a hard insulation member that is not expandable, each of the second sheet members having a fixing portion that fixes each of the bus bars independently, wherein
each of the bus bars includes a fitting portion that extends from one edge of the plate member with respect to a width direction thereof and fits in the fixing portion of each second sheet member,
the first sheet member holds each of the second sheet members with the adhesive member, each of the bus bars is fixed to each second sheet member, and whereby the first sheet member commonly holds the bus bars, and
the first sheet member is formed of a flexible insulation member such that the flexible insulation member is expandable at sections between adjacent second sheet members in a longitudinal direction of the first sheet member, and the flexible insulation member is expandable at least in a distance of a maximum value of tolerance that is a total value of tolerances of an electrode pitch with respect to an arrangement direction in which the adjacent power storage elements are arranged.

US Pat. No. 10,770,709

CONNECTION MODULE

AUTONETWORKS TECHNOLOGIES...

1. A connection module to be attached to a power storage element group in which a plurality of power storage elements with positive and negative electrode terminals are aligned, the connection module comprising:a plurality of bus bars that connect the positive and negative electrode terminals of adjacent power storage elements of the plurality of power storage elements; and
a sheet member that holds the plurality of bus bars arranged in an alignment direction of the plurality of power storage elements,
wherein the sheet member includes:
a plurality of holders that hold the bus bars; and
an extension and contraction structure that is positioned between adjacent holders and has an extension and contraction distance equal to or longer than an electrode pitch tolerance between the positive and negative electrode terminals of the adjacent power storage elements in the alignment direction, the extension and contraction structure being extendable and contractible from a state of the extension and contraction structure that is without extension and contraction, wherein
each of the bus bars has a protrusion portion that protrudes from one end as seen in a width direction, and
each of the bus bars is held by a holder of the holders via the protrusion portion.

US Pat. No. 10,770,708

BUSBAR AND BATTERY MODULE HAVING SUCH A BUSBAR

VOLTLABOR GmbH, Bad Leon...

1. A busbar for connecting battery cells, the busbar comprising:an electrically conductive metal sheet;
at least one sheet metal connector piece, which is incorporated into the metal sheet with the aid of a cutting method and which protrudes from the metal sheet;
wherein the sheet metal connector piece has a contacting part for electrically connecting to a pole of a battery cell and a safety part which is a coiled helical spring embodied in the form of a fuse.

US Pat. No. 10,770,707

BATTERY SEPARATOR AND METHOD OF MANUFACTURING SAME

Toray Industries, Inc., ...

12. A method of producing the battery separator according to claim 1, the method comprising steps (a) to (g) in the following order:(a) a step of melt-kneading a polyolefin resin and a forming solvent, thereby preparing a polyolefin resin solution;
(b) a step of extruding the polyolefin resin solution into a sheet shape via an extruder and cooling an extrudate thereof, thereby forming an unstretched gel-like sheet;
(c) a step of passing the unstretched gel-like sheet between at least two pairs of longitudinal stretching roller groups and stretching the sheet in a longitudinal direction based on a peripheral speed ratio of the two pairs of roller groups, thereby forming a longitudinally stretched gel-like sheet, wherein a longitudinal stretching roller and a nip roller parallelly contacting therewith are designated as a pair of longitudinal stretching roller group, and a contact pressure of the nip roller to the longitudinal stretching roller is 0.05 MPa or more and 0.5 MPa or less;
(d) a step of stretching the longitudinally stretched gel-like sheet in a transverse direction while holding the sheet to allow a clip-to-clip distance to be 50 mm or less at a tenter outlet, thereby obtaining a biaxially stretched gel-like sheet;
(e) a step of extracting the forming solvent from the biaxially stretched gel-like sheet and drying the sheet;
(f) a step of heat-treating the dried sheet, thereby obtaining a polyolefin microporous membrane; and
(g) a step of coating the polyolefin microporous membrane with a coating solution containing a fluorine-based resin and an inorganic particle by a reverse gravure coating method, passing the membrane through a coagulation bath, and then, subjecting to water washing and drying, thereby laminating a porous layer on the polyolefin microporous membrane.

US Pat. No. 10,770,706

BINDER FOR ELECTRICITY STORAGE DEVICE AND BINDER COMPOSITION FOR ELECTRICITY STORAGE DEVICE

ASAHI KASEI KABUSHIKI KAI...

1. A binder for an electricity storage device comprising a copolymer having an ethylenic unsaturated monomer having a polyalkyleneglycol group (P) and a monomer without a polyalkyleneglycol group that is copolymerizable with the ethylenic unsaturated monomer having a polyalkyleneglycol group (P) as a monomer unit,wherein the average number of repeating units (n) of said polyalkyleneglycol group of the ethylenic unsaturated monomer having a polyalkyleneglycol group (P) is 3 or greater,
wherein the monomer without a polyalkyleneglycol group comprises ethylenic unsaturated monomers with an amide group (b2) at 0.1 to 10 weight % with respect to 100 weight % of the copolymer,
wherein the monomer without a polyalkyleneglycol group further comprises an ethylenic unsaturated monomer with a cycloalkyl group (A) and a (meth)acrylic acid ester monomer (b5), and
wherein the total amount of the ethylenic unsaturated monomer with a cycloalkyl group (A) and the (meth)acrylic acid ester monomer (b5) is 50 to 98 weight % with respect to 100 weight % of the copolymer.

US Pat. No. 10,770,705

OLEFIN SEPARATOR FREE LI-ION BATTERY

APPLIED MATERIALS, INC., ...

1. A method of forming a separator for a battery, comprising:exposing a metallic material to be deposited on a surface of an electrode structure positioned in a processing region to an evaporation process to form an evaporated metallic material;
flowing a reactive gas into the processing region, comprising:
exposing oxygen to water vapor to form moist oxygen; and
introducing the moist oxygen into the processing region; and
reacting the reactive gas and the evaporated metallic material to deposit a ceramic separator layer on the surface of the electrode structure.

US Pat. No. 10,770,704

SEPARATORS FOR VRLA BATTERIES AND METHODS RELATING THERETO

Daramic, LLC, Charlotte,...

1. A battery separator comprising:at least one microporous polyolefin separator layer, said microporous polyolefin separator layer having a first surface and a second surface;
at least said first surface comprising at least one of the list consisting of ribs, embossments, acid filling channels, and a combination thereof;
at least said second surface comprising at least one of the list consisting of ribs, embossments, acid filling channels, mini cross ribs, and a combination thereof;
said microporous polyolefin separator layer comprises first areas comprising a first set of pores and a compressed pore structure; and further comprises second areas comprising a second set of pores and a pore structure less compressed than the pore structure of the first areas;
optionally at least one first Absorptive Glass Mat (“AGM”) layer adjacent to one of said first surface or said second surface.

US Pat. No. 10,770,702

JIG SET INCLUDING HANDLE FOR MOUNTING ENERGY STORAGE SYSTEM

LG CHEM, LTD., Seoul (KR...

1. A jig set for mounting an energy storage system (ESS) pack, which is used to mount an ESS pack to a wall or a structure corresponding to the wall, the jig set comprising:a plurality of fasteners, each fastener having a partially protruding portion capable of being coupled to one surface of an ESS pack case;
a handle comprising a handlebar to be grasped by an operator, and a locking bar, which is integrally connected to the handlebar and is attachable to and detachable from the protruding portion of each of the fasteners, the locking bar having a first edge and a second edge spaced from the first edge in a first direction; and
a plurality of catches extending from the first edge of the locking bar and spaced from each other in a second direction, each catch configured to receive one of the plurality of fasteners,
wherein the handlebar comprises a plurality of first sections extending from the locking bar in a third direction and spaced from each other along the locking bar in the second direction and a second section extending in the second direction and connected to the plurality of first sections.

US Pat. No. 10,770,700

BATTERY PACK

YAZAKI CORPORATION, Toky...

1. A battery pack comprising:a plurality of battery cells, each of which comprises a positive terminal and a negative terminal formed on and protruding from one surface, and the plurality of battery cells being arranged such that the positive terminals and the negative terminals are alternately arranged;
a plurality of bus bars, each of which electrically connects the positive terminal and the negative terminal of the adjacent battery cells;
an insulating cover which is attachable to the plurality of battery cells and covers the positive terminals and the negative terminals which are connected by the respective bus bars;
a monitor substrate in which a monitor circuit is mounted to monitor a state of the plurality of battery cells; and
a plurality of detection terminals which are electrically connected to the monitor substrate and electrically connected to the plurality of bus bars, respectively, to detect the state of the battery cell,
wherein the monitor substrate and the plurality of detection terminals are disposed integrally to an inner surface of the insulating cover,
wherein the plurality of detection terminals are electrically connected to the plurality of bus bars, respectively, in a state in which the insulating cover is attached to the plurality of battery cells,
wherein the insulating cover comprises a detection terminal mounting portion at which the plurality of detection terminals are mounted,
wherein the detection terminal mounting portion is formed such that the detection terminals are disposed immediately above the plurality of bus bars in the state in which the insulating cover is attached to the plurality of battery cells, and
wherein the insulating cover further includes a plurality of insulating walls extending from the inner surface of the insulating cover toward the battery cells, and each of the insulating walls extends between a respective pair of the detection terminals and between a respective pair of the bus bars.

US Pat. No. 10,770,698

MINIATURE ELECTROCHEMICAL CELL HAVING A CASING COMPRISING OPPOSED CERAMIC SUBSTRATES SECURED TOGETHER USING A PRECIOUS METAL BRAZE

Greatbatch Ltd., Clarenc...

1. An electrochemical cell, comprising:a) a casing, comprising:
i) a first ceramic substrate comprising opposed first substrate inner and outer surfaces;
ii) a second ceramic substrate comprising opposed second substrate inner and outer surfaces; and
iii) a precious metal disc hermetically sealing the first and second ceramic substrates together to provide the casing; and
b) an electrode assembly housed inside the casing, the electrode assembly comprising:
i) an anode active material contacting an anode current collector;
ii) a cathode active material contacting a cathode current collector; and
iii) a separator disposed between the anode and cathode active materials; and
c) a first conductive pathway extending through the first ceramic substrate and comprising first conductive pathway inner and outer surfaces located at or adjacent to the respective first ceramic substrate inner and outer surfaces;
d) a second conductive pathway extending through the second ceramic substrate and comprising second conductive pathway inner and outer surfaces located at or adjacent to the respective second ceramic substrate inner and outer surfaces,
e) wherein the first conductive pathway inner surface is in an electrically conductive relationship with one of the anode and cathode current collectors, and wherein the second conductive pathway inner surface is in an electrically conductive relationship with the other of the anode and cathode current collectors, and
f) wherein the respective first and second conductive pathway outer surfaces are configured for electrical connection to a load; and
g) an electrolyte inside the casing in contact with the electrode assembly.

US Pat. No. 10,770,697

BATTERY CELL, BATTERY MODULE, AND METHOD FOR PRODUCING THE SAME

Robert Bosch GmbH, Stutt...

1. A battery module having a battery cell, wherein the battery cell has a housing, wherein the housing comprises a first housing element which holds electrochemical components of the battery cell which comprise at least an anode, a cathode, and a separator, and furthermore has an opening, wherein the housing also comprises a second housing element which has a voltage tap connected to the anode of the battery cell or the cathode of the battery cell in an electrically conductive fashion, wherein the voltage tap is furthermore arranged to be accessed from a first surface of the second housing element, wherein the second housing element furthermore closes off the opening formed in the first housing element in such a way that a first part region of a second surface of the second housing element, which is opposite the first surface, is immediately adjacent to the interior space of the first housing element, and that a second part region of the second surface of the second housing element, which is opposite the first surface, protrudes beyond the first housing element, characterized in that the second housing element comprises a sealing element connected to at least one of the first surface and the second part region of the second surface, and wherein the battery module has a battery cell holder which comprises an interior space through which a temperature-control fluid can flow, characterized in that the battery cell is held in the battery cell holder in such a way that the sealing element seals the interior space in fluid-tight fashion from the surroundings, and that the first sealing element is arranged so that temperature-control fluid can flow around it.

US Pat. No. 10,770,696

TOP COVER ASSEMBLY OF SECONDARY BATTERY AND SECONDARY BATTERY

CONTEMPORARY AMPEREX TECH...

1. A top cover assembly of a secondary battery, comprising:a first electrode terminal, a conduction member, a second electrode terminal, and a top cover plate,
wherein the top cover plate is insulated from the first electrode terminal, and the top cover plate is electrically connected to the second electrode terminal,
wherein the secondary battery further comprises a contact plate, and the contact plate is attached to the top cover plate, and the conduction member is insulated from the top cover plate,
wherein the conduction member comprises an electrode terminal connection portion, a first fuse member, and a contact plate connection portion, wherein the electrode terminal connection portion is electrically connected to the first electrode terminal, the first fuse member is electrically connected between the electrode terminal connection portion and the contact plate connection portion, and a melting point of the first fuse member is lower than a melting point of the electrode terminal connection portion and a melting point of the contact plate connection portion,
wherein the contact plate is configured to deform under an internal pressure of the secondary battery and to be electrically connected to the contact plate connection portion when the internal pressure of the secondary battery exceeds a reference pressure, for forming an electric connection path passing through the first electrode terminal and the second electrode terminal, and
wherein the conduction member further comprises a connection layer, wherein the first fuse member is electrically connected to the electrode terminal connection portion via the connection layer, and the connection layer is configured to enhance a connection strength between the first fuse and the electrode terminal connection portion; and/or the first fuse member is electrically connected to the contact plate connection portion via the connection layer, and the connection layer is configured to enhance a connection strength between the first fuse and the contact plate connection portion.

US Pat. No. 10,770,695

BATTERY

GS YUASA INTERNATIONAL LT...

1. A lithium ion battery, comprising:an outer package comprising a laminated film comprising one or more resin layers;
an electrolyte solution held in the outer package;
a terminal;
a metal plating layer disposed on the terminal; and
a melt-bonding assisting member comprising a thermoplastic resin and extending along the terminal,
wherein the outer package comprises a melt-bonded region at which the terminal is sandwiched between the one or more resin layers via the melt-bonding assisting member,
wherein the terminal comprises an inner part, a sandwiched part, and an outer part arranged in a first direction,
wherein the melt-bonding assisting member internally and externally extends in the first direction beyond contact with the outer package,
wherein the metal plating layer comprises a single layer,
wherein the metal plating layer internally and externally extends in the first direction beyond the melt-bonded region, and
wherein the battery has a discharge capacity of 10 Ah or more.

US Pat. No. 10,770,693

APPARATUS COMPRISING BATTERY CELLS AND A METHOD OF ASSEMBLING

JAGUAR LAND ROVER LIMITED...

1. An apparatus comprising:a plurality of battery cells, each of the battery cells comprising a layer of positive electrode material, a layer of electrolyte material and a layer of negative electrode material; and
a container for the battery cells, the container formed of an electrically conductive material and having a plurality of cavities, each cavity containing at least one of the battery cells,
wherein the container is in direct contact with at least one of the layer of positive electrode material and the layer of electrolyte material of each battery cell, or alternatively the container is in direct contact with at least one of the layer of negative electrode material and the layer of electrolyte material of each battery cell,
wherein each cavity has a first end closed by a combination of an insulating element and an electrical connector, the insulating element providing electrical insulation between the electrical connector and the container, and
wherein the insulating element comprises a single insulating element that extends over one or more of the cavities.

US Pat. No. 10,770,691

PRODUCTION METHOD OF ORGANIC EL DEVICE

SUMITOMO CHEMICAL COMPANY...

1. A method for producing an organic EL device having an anode, a cathode, at least one organic functional layer disposed between the anode and the cathode, and a sealing layer, comprisinga step of forming the anode, a step of forming the cathode, a step of forming the at least one organic functional layer and a step of forming the sealing layer,
wherein an average concentration: A (ppm) of ammonia to which the organic EL device during production is exposed from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer and an exposure time thereof: B (sec) satisfy the formula (1-1):
0?A×B?105  (1-1),
wherein the device is a red-light emitting device,
wherein from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer the organic EL device is under a sealed atmosphere, and
wherein the at least one organic functional layer contains a polymer compound.

US Pat. No. 10,770,690

OLED WITH MINIMAL PLASMONIC LOSSES

The Regents of The Univer...

1. A top-emitting organic light emitting device (OLED) comprising:a substrate having an inward side and an outward side;
a non-metallic, diffuse reflective layer with a roughened top surface and a bottom surface disposed over the substrate with the roughened top surface disposed over the bottom surface;
a high refractive index waveguide layer disposed over the reflective layer; and
an OLED body disposed over the reflective layer, the OLED body comprising:
a transparent bottom electrode disposed over high refractive index waveguide layer,
an organic emissive layer disposed over the transparent bottom electrode, and
a transparent top electrode disposed over the organic emissive layer;
wherein a majority of light emitted by the OLED during operation is emitted through the transparent top electrode.

US Pat. No. 10,770,686

ORGANIC LIGHT EMITTING DEVICE WHICH EMITS WHITE LIGHT

Cambridge Display Technol...

1. An organic light emitting device which emits white light, comprising:a reflective anode,
a first light emitting layer which emits red light located over said reflective anode,
a second light emitting layer which emits blue light and green light located over said first light emitting layer, and
a cathode structure located over said second light emitting layer comprising:
a first semi-reflecting semi-transparent layer; and
a second semi-reflecting semi-transparent layer with a layer of light transmissive material between the first and second semi-reflecting semi-transparent layers,
wherein a first distance between the reflective anode and the first semi-reflecting semi-transparent layer is selected to form a first micro-cavity which enhances blue light emission and red light emission from the organic light emitting device, and
wherein a second distance between the reflective anode and the second semi-reflecting semi-transparent layer is selected to form a second micro-cavity which enhances green light emission from the organic light emitting device.

US Pat. No. 10,770,685

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A manufacturing method of a display device, comprising:forming a flexible substrate on a sacrificial substrate;
forming a display element unit on a first surface of the flexible substrate, the display element unit comprising a TFT and an organic light-emitting element;
separating the sacrificial substrate from the flexible substrate; and
forming a protective layer by depositing an organic material on a second surface of the flexible substrate, the second surface being opposite to the first surface,
wherein the protective layer has a structure in which more than one first layer and more than one second layer having a lower density than the first layer are alternately stacked.

US Pat. No. 10,770,684

DISPLAY DEVICE INCLUDING A STRESS NEUTRALIZING LAYER

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate having a first area, a second area, and a bending area between the first area and the second area;
a display element disposed in the first area of the substrate; and
a stress neutralizing layer disposed in the first area, the second area and the bending area,
wherein a thickness of the stress neutralizing layer in the entire bending area is less than about ½ of a thickness of the stress neutralizing layer in at least one of the first area or the second area.

US Pat. No. 10,770,683

ORGANIC EL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

JOLED INC., Tokyo (JP)

2. The organic EL display panel of claim 1, whereinthe protection member is made of an ultraviolet-curing resin material or a thermosetting resin material.

US Pat. No. 10,770,678

COVER FOR FLEXIBLE DISPLAY PANEL, FLEXIBLE DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A cover for a flexible display panel, the cover comprising:an organic film including a recessed portion;
a reinforcing layer disposed in the recessed portion; and
a first rigid structure and a second rigid structure adjacent to each other disposed on the organic film, wherein the first rigid structure includes a first joint portion, wherein the second rigid structure includes a second joint portion, and wherein the first joint portion and the second joint portion are configured to be separated from each other when the reinforcing layer is bent, and to be joined to form a one-piece structure when the reinforcing layer is not bent, the first rigid structure and the second rigid structure are transparent.

US Pat. No. 10,770,677

DISPLAY APPARATUS

LG DISPLAY CO., LTD., Se...

1. A display apparatus comprising:a flexible display panel including at least one bending area;
a first mid-frame disposed on a rear surface of the flexible display panel at a central area of the flexible display panel based on the at least one bending area;
a second mid-frame disposed on the rear surface of the flexible display panel at an edge area of the flexible display panel based on the at least one bending area, the second mid-frame being spaced apart from the first mid-frame; and
a bending guide configured to maintain a bent angle between the first mid-frame and the second mid-frame.

US Pat. No. 10,770,676

FLEXIBLE DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A flexible display apparatus comprising:a substrate having a bending portion;
a display over the substrate; and
a cover over the substrate and covering the display,
wherein the cover comprises:
a first film having a first surface and a second surface opposite the first surface;
a second film over the first film; and
an adhesive layer between the first film and the second film and attaching the first film to the second film, and
the first film comprises at least one division line in at least some regions thereof in a direction from the first surface toward the second surface, wherein the at least one division line penetrates from the first surface to the second surface of the first film, wherein the cover is bent towards the first film such that tensile stress is applied to the first film.

US Pat. No. 10,770,675

ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING AN ENCAPSULATING SUBSTRATE OF HIGH THERMAL CONDUCTIVITY

LG DISPLAY CO., LTD., Se...

1. An organic light-emitting display device comprising:a device substrate including a display area and a non-display area;
a light-emitting element on the display area of the substrate;
an encapsulation layer overlying the light-emitting element, the encapsulation layer being in the display area;
a bead holding encapsulation layer overlying a portion of the encapsulation layer, the bead holding encapsulation layer overlapping with the display area of the substrate;
a plurality of metal beads within the bead holding encapsulation layer; and
an encapsulating substrate overlying the bead holding encapsulation layer,
wherein the metal beads within the bead holding encapsulation layer are comprised of a ferrous metal.

US Pat. No. 10,770,674

OLED LIGHTING APPARATUS

LG DISPLAY CO., LTD., Se...

1. An OLED lighting apparatus having an active area and a non-active area, comprising:a buffer layer;
an auxiliary wire disposed on the buffer layer;
an organic light emitting device including a first electrode disposed on the auxiliary wire and connected to the auxiliary wire and a second electrode stacked on the first electrode, and an organic light emitting layer between the first and second electrodes;
a pad connected to the first electrode and the second electrode and disposed in the non-active area; and
an encapsulation layer disposed over the buffer layer to cover the second electrode and the pad.

US Pat. No. 10,770,673

HIGHLY RELIABLE STACKED WHITE ORGANIC LIGHT EMITTING DEVICE

The Regents of the Univer...

1. An organic light emitting device (OLED) comprising:a cathode and an anode;
a blue emitting layer;
at least two hybrid red/green emitting layers, wherein a first one of the at least two hybrid red/green emitting layers is disposed between the cathode and the blue emitting layer, and the second of the at least two hybrid red/green emitting layers is disposed between the blue emitting layer and the anode, wherein the OLED emits white light; and
an additional one or two hybrid red/green emitting layers disposed between the blue emitting layer and the anode, wherein a red/green charge generating layer separates each of the hybrid red/green emitting layers disposed between the blue emitting layer and the anode.

US Pat. No. 10,770,671

DISPLAY PANEL, DISPLAY DEVICE, AND MANUFACTURING METHOD OF THE DISPLAY PANEL

BOE Technology Group Co.,...

1. A display panel, comprising:a light emitting unit;
a color filter layer located on a light emission side of the light emitting unit; and
a bonding structure located between the light emitting unit and the color filter layer configured to bond the light emitting unit and the color filter layer,
wherein, the bonding structure comprises a quantum dot material configured to convert ultraviolet light into visible light.

US Pat. No. 10,770,669

MANUFACTURING METHOD OF FLEXIBLE OLED PANEL, FLEXIBLE OLED DISPLAY PANEL, AND DISPLAY

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of a flexible OLED panel, comprising: providing a rigid substrate;fabricating a flexible base substrate, a first inorganic layer, a TFT device, a second inorganic layer, an OLED device, and an encapsulation layer on the rigid substrate to form a first flexible large OLED panel;
wherein the first inorganic layer is formed between the flexible base substrate and a semiconductor layer of the TFT device; the second inorganic layer covers the semiconductor layer, a gate of the TFT device and the first inorganic layer, a source and a drain of the TFT device both penetrate into the second inorganic layer and are connected to the semiconductor layer, and the second inorganic layer is isolated from the gate, the source, and the drain; the OLED device is formed on the TFT device; the encapsulation layer encapsulates the OLED device and the TFT device for encapsulation; the first flexible large OLED panel comprises a display area, a frame area surrounding a periphery of the display area, and a cutting area surrounding the frame area, the frame area includes a first area and a second area connecting to each other, a side of the first area away from the second area is connected to the display area, a side of the second area away from the first area is connected to the cutting area; the TFT device and the encapsulation layer are both distributed in the display area and the first area; the OLED device is distributed in the display area; the rigid substrate, the flexible base substrate, and the first inorganic layer are all distributed in the display area, the first area, the second area, and the cutting area; and the second inorganic layer is distributed at least in the display area, the first area, and the second area;
forming at least two rows of opening holes in a portion of the second inorganic layer located in the second area, wherein a connection line of each of the opening holes of each of the rows extends in a surrounding direction of the frame area, and two of the rows of the opening holes adjacent to each other are arranged in a dislocation manner in the surrounding direction so as to distribute at least one of the opening holes on a line connecting any position on a boundary between the second area and the cutting area to any position of the display area;
wherein the opening holes are disposed on the inorganic layer and are blind holes such that the flexible base substrate is prevented from being exposed through the opening holes;
cutting off the cutting area in the first flexible large OLED panel to obtain a second flexible large OLED panel; and
removing the rigid substrate in the second flexible large OLED panel by using a LLO technique.

US Pat. No. 10,770,668

FLEXIBLE FIBER SUBSTRATE AND FLEXIBLE DISPLAY DEVICE INCLUDING THE SAME

HEFEI XINSHENG OPTOELECTR...

1. A flexible display device comprising:a flexible fiber substrate, wherein the flexible fiber substrate comprises:
an insulating body woven from an insulating fiber and a patterned conductive member made of a conductive fiber, wherein the conductive member and the insulating body are fixed to each other by interlacing, and the conductive member is touchable from outside of the flexible fiber substrate;
a plurality of woven layers connected to each other and at least partially overlapping each other, the plurality of woven layers comprises a first outermost woven layer, a second outermost woven layer and at least one intermediate woven layer between the first outermost woven layer and the second outermost woven layer,
the conductive member comprises a first portion located in the at least one intermediate woven layer, and a portion of the insulating body located in the first outermost woven layer overlaps the first portion of the conductive member;
a pixel unit on the flexible fiber substrate, comprising a display electrode for displaying an image,
wherein the display electrode is electrically connected to the conductive member of the flexible fiber substrate, wherein the pixel unit is a pixel unit comprising an electrophoretic microcapsule, and the electrophoretic microcapsule has a sectional shape of a trapezoid, and a short base of the trapezoid is closer to the flexible fiber substrate relative to a long base of the trapezoid.

US Pat. No. 10,770,667

FLEXIBLE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A flexible display device, comprising: a display area, a bending area, and a driving printed circuit board, wherein the bending area is located between the display area and the driving printed circuit board, and the driving printed circuit board is located on a rear side of the display area by bending of the bending area, and the bending area comprises:a substrate;
an inorganic layer disposed on the substrate, wherein the inorganic layer is disposed on the substrate and distributed in a form of islands, and the inorganic layer comprises a plurality of island-shaped blocks, and two adjacent island-shaped blocks are spaced apart from each other;
a first metal layer disposed over a whole surface of the inorganic layer and the substrate, wherein the first metal layer forms a plurality of first recesses corresponding to shapes of the plurality of island-shaped blocks; and
a second metal layer disposed between the first metal layer and the substrate; and wherein the second metal layer is formed from a plurality of patterning units, and the plurality, of patterning units are spaced apart from each other, and one of the patterning units is located between two adjacent island-shaped blocks.

US Pat. No. 10,770,666

DISPLAY DEVICE HAVING PROTECTIVE FILM

Samsung Display Co., Ltd....

1. A display device comprising:a flexible display panel comprising:
a flexible substrate having a first surface and a second surface opposite to the first surface; and
an organic light emitting element over the first surface of the flexible substrate; and
a protective film comprising:
a film main body having a first surface contacting the second surface of the flexible substrate and a first recess portion recessed from the first surface of the film main body; and
a first adhesion portion in the first recess portion and contacting the second surface of the flexible substrate.

US Pat. No. 10,770,664

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. A compound having a formula Ir(LA)(LB)(LC);wherein the ligand LA, LB, and LC are each a mono-anionic bidentate ligand coordinated to Ir forming a 5-member cyclometalated ring;
wherein LA and LB are covalently linked by a linking group and are each independently selected from the group consisting of:

wherein each X1 to X13 are independently selected from the group consisting of carbon and nitrogen;
wherein X is selected from the group consisting of BR?, NR?, PR?, O, S, Se, C?O, S?O, SO2, CR?R?, SiR?R?, and GeR?R?;
wherein R? and R? are optionally fused or joined to form a ring;
wherein each Ra, Rb, Rc, and Rd may represent from mono substitution to the possible maximum number of substitution, or no substitution;
wherein R? and R? are each independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof;
wherein Ra, Rb, Rc, and Rd are each independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, C6-C9 aryl, C3-C9 heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof;
wherein one of Ra, Rb, Rc, and Rd in ligand LA is joined with one of Ra, Rb, Rc, and Rd in ligand LB;
wherein LC is not linked to LA and LB, and is selected from the group consisting of:

wherein each Ra and Rb may represent from mono substitution to the possible maximum number of substitution, or no substitution; and
wherein Ra and Rb are each independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, C6-C9 aryl, C3-C9 heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof.

US Pat. No. 10,770,663

GERMANIUM-CENTERED DENDRIMER COMPOUND, AND ORGANIC OPTOELECTRIC ELEMENT COMPRISING SAME

Chung-Ang University Indu...

1. A germanium-centered dendrimer compound having the following structure of Formula 1:
wherein:
R1, R2, R3 and R4 are each independently attached at the respective para position and represented by Formula 5:

R5 is hydrogen,
R6 is an aryl group having to 20 carbon atoms or a heteroaryl group having 2 to 20 carbon atoms,
R7 is an alkyl group having 1 to 10 carbon atoms, an aryl group having 6 to 20 carbon atoms or a heteroaryl group having 2 to 20 carbon atoms, and
one or more hydrogens in R1 to R4 and R6 to R7 are each independently a compound substituted or not substituted with one or more substituents selected from the group consisting of an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, an aryl group having 6 to 30 carbon atoms, a heteroaryl group having 2 to 30 carbon atoms, a heterocyclic group having 3 to 30 carbon atoms, an acyl group having 1 to 30 carbon atoms, an acyloxy group having 6 to 30 carbon atoms, a dialkylamino group having 2 to 30 carbon atoms, a diarylamino group having 12 to 30 carbon atoms, an alkylarylamino group having 7 to 30 carbon atoms, a dialkylphosphino group having 2 to 30 carbon atoms, a diarylphosphino group having 12 to 30 carbon atoms, an alkylarylphosphino group having 7 to 30 carbon atoms, an amine group, a halogen group, a cyano group, a nitro group, a hydroxyl group and a carboxyl group.

US Pat. No. 10,770,662

ORGANIC COMPOUND, ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic compound of following formula:
wherein R is carbazole.

US Pat. No. 10,770,661

THERMALLY ACTIVATED DELAYED FLUORESCENCE MATERIAL AND APPLICATION THEREOF IN ORGANIC ELECTROLUMINESCENCE DEVICE

KUNSHAN GP-VISIONOX OPTO-...

1. A thermally activated delayed fluorescence material, wherein the thermally activated delayed fluorescence material is a compound having a structure shown in formulas 1-2 to 1-5:

US Pat. No. 10,770,659

COMPOSITION FOR HOLE TRAPPING LAYER OF ORGANIC PHOTOELECTRIC CONVERSION ELEMENT

NISSAN CHEMICAL INDUSTRIE...

1. A composition for a hole-collecting layer in an organic photoelectric conversion device, the composition comprising a charge-transporting substance consisting of a polyaniline derivative of formula (1):
wherein R1 to R4 are each independently a hydrogen atom, a halogen atom, a nitro group, a cyano group, a sulfonic acid group, an alkoxy group of 1 to 20 carbon atoms, a thioalkoxy group of 1 to 20 carbon atoms, an alkyl group of 1 to 20 carbon atoms, an alkenyl group of 2 to 20 carbon atoms, an alkynyl group of 2 to 20 carbon atoms, a haloalkyl group of 1 to 20 carbon atoms, an aryl group of 6 to 20 carbon atoms, an aralkyl group of 7 to 20 carbon atoms or an acyl group of 1 to 20 carbon atoms, with one of the R1 to R4 moieties being a sulfonic acid group and a single one of the remaining R1 to R4 moieties being an alkoxy group of 1 to 10 carbon atoms, R5 and R6 are a hydrogen atom, and m and n are each numbers which satisfy the conditions 0?m?1, 0?n?1 and m+n =1, and a solvent.

US Pat. No. 10,770,657

HIGH RELIABILITY PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCH USING TRAP-RICH REGION

Newport Fab, LLC, Newpor...

1. A semiconductor structure comprising:a semiconductor mesa on a semiconductor substrate:
a trap-rich region adjacent to said semiconductor mesa;
a phase-change material (PCM) radio frequency (RF) switch, wherein a heating element of said PCM RF switch is situated over said semiconductor mesa;
wherein at least a portion of an interconnect segment coupled to said PCM RF switch is situated over said trap-rich region.

US Pat. No. 10,770,655

CHIP PACKAGE

Taiwan Semiconductor Manu...

1. A chip package, comprising:an integrated circuit chip comprising an active surface;
a plurality of memory chips stacked on the active surface of the integrated circuit chip and electrically connected to the integrated circuit chip;
an insulating encapsulation, laterally encapsulating the plurality of memory chips and partially covering the active surface of the integrated circuit chip; and
a redistribution circuit structure disposed on the plurality of memory chips and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the plurality of memory chips.

US Pat. No. 10,770,654

MULTIPLE SPACER ASSISTED PHYSICAL ETCHING OF SUB 60NM MRAM DEVICES

TAIWAN SEMICONDUCTOR MANU...

16. A device comprising:a first pinned layer disposed over a bottom electrode;
a first metal re-deposition layer disposed on sidewalls of the first pinned layer;
a tunnel barrier layer disposed over the first pinned layer;
a second metal re-deposition layer disposed on sidewalls of the tunnel barrier layer;
a first sidewall spacer layer covering the second metal re-deposition layer disposed on the sidewalls of the tunnel barrier layer;
a free layer disposed over the tunnel barrier layer;
a third metal re-deposition layer disposed on sidewalls of the free layer;
a second sidewall spacer layer covering the third metal re-deposition layer disposed on the sidewalls of the free layer;
a top electrode disposed over the fee layer; and
a fourth metal re-deposition layer disposed on sidewalls of the top electrode.

US Pat. No. 10,770,653

SELECTIVE DIELECTRIC DEPOSITION TO PREVENT GOUGING IN MRAM

International Business Ma...

1. A method for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region, the method comprising:forming a plurality of first conductive lines within a first dielectric at a first metal level;
forming a plurality of second conductive lines within a second dielectric at a second metal level, wherein the first and second metal levels are connected by a via;
depositing a first hardmask and a second hardmask;
etching the first and second hardmasks to expose top surfaces of one or more of the plurality of second conductive lines; and
constructing protective layers in the MRAM region to preserve integrity of underlying dielectric layers, wherein the protective layers are misaligned with respect to conductive lines of the plurality of first and second conductive lines in the first and second metal levels, respectively.

US Pat. No. 10,770,652

MAGNETIC TUNNEL JUNCTION (MTJ) BILAYER HARD MASK TO PREVENT REDEPOSITION

International Business Ma...

1. A semiconductor structure comprising:a first electrically conductive structure embedded in an interconnect dielectric material layer and located in a magnetoresistive random access memory (MRAM) device area;
a conductive landing pad located on a surface of the first electrically conductive structure in the MRAM device area;
a multi-layered magnetic tunnel junction (MTJ) stack structure located on the conductive landing pad;
a metal cap layer formed on a surface of said MTJ stack structure;
a bilayer metal hardmask structure formed on a surface of said metal cap layer, the bilayer metal hardmask structure having a first conductive metal layer of a low-sticking coefficient metal material formed above the metal cap layer and a second conductive metal layer of a high-sticking coefficient metal material formed atop the first conductive metal layer that is different from said first conductive metal layer.

US Pat. No. 10,770,650

MEMORY CELL WITH TOP ELECTRODE VIA

Taiwan Semiconductor Manu...

20. An integrated chip, comprising:a memory device surrounded by a dielectric structure over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode;
a bottom electrode via coupling the bottom electrode to a lower interconnect wire;
a top electrode via coupling the top electrode to an upper interconnect wire, wherein the top electrode via has first cross-sectional area as viewed from a top-view of the top electrode via, the first cross-sectional area having a length extending along a first direction and a width extending along a second direction that is perpendicular to the first direction, and wherein the length is larger than the width; and
a second via laterally separated from the memory device along an imaginary horizontal line that is parallel to an upper surface of the substrate, wherein the second via has a second cross-sectional area that is larger than the first cross-sectional area.

US Pat. No. 10,770,648

METHOD FOR PRODUCING COMPOSITE WAFER HAVING OXIDE SINGLE-CRYSTAL FILM

SHIN-ETSU CHEMICAL CO., L...

1. A method of producing a composite wafer having an oxide single-crystal film on a support wafer, comprising steps of:implanting hydrogen atom ions or hydrogen molecule ions into an oxide single-crystal wafer through a surface thereof, which wafer is a lithium tantalate or lithium niobate wafer, to form an ion-implanted layer inside the oxide single-crystal wafer;
subjecting at least one of the surface of the oxide single-crystal wafer and a surface of a support wafer to be laminated with the oxide single-crystal wafer to surface activation treatment;
after the surface activation treatment, bonding the surface of the oxide single-crystal wafer to the surface of the support wafer to obtain a laminate;
heat-treating the laminate at a temperature of 90° C. or higher at which cracking is not caused; and
applying ultrasonic vibration to the heat-treated laminate to split the laminate along the ion-implanted layer to obtain an oxide single-crystal film transferred onto the support wafer;wherein an implantation dose of the hydrogen atom ions is from 5.0×1016 atom/cm2 to 2.75×1017 atom/cm2 and an implantation dose of the hydrogen molecule ions is from 2.5×1016 atoms/cm2 to 1.37×1017 atoms/cm2.

US Pat. No. 10,770,647

ELECTROACOUSTIC CONVERSION FILM WEB, ELECTROACOUSTIC CONVERSION FILM, AND METHOD OF MANUFACTURING AN ELECTROACOUSTIC CONVERSION FILM WEB

FUJIFILM Corporation, To...

1. An electroacoustic conversion film comprising:a piezoelectric layer having dielectric properties;
two thin film electrodes respectively formed on both surfaces of the piezoelectric layer;
two protective layers respectively formed on the two thin film electrodes;
regions in which the piezoelectric layer, the two thin film electrodes, and the two protective layers have the same shape when viewed in a direction perpendicular to a principal surface of the piezoelectric layer and are adhered; and
regions in which the piezoelectric layer, the two thin film electrodes, and the two protective layers overlap when viewed in the direction perpendicular to the principal surface of the piezoelectric layer and the piezoelectric layer and the two thin film electrodes are not adhered.

US Pat. No. 10,770,646

MANUFACTURING METHOD FOR FLEXIBLE PMUT ARRAY

QUALCOMM Incorporated, S...

1. A method of forming a flexible array of piezoelectric micromechanical ultrasonic transducers, comprising:providing a carrier configured to support the flexible array of piezoelectric micromechanical ultrasonic transducers (PMUTs);
providing a release layer configured to adhere the flexible array of PMUTs to the carrier;
forming the flexible array of PMUTs over the release layer, comprising
for each PMUT in the flexible array of PMUTs,
laminating a first polymer layer configured to support the PMUT;
depositing a sacrificial material configured to pattern a cavity of the PMUT;
depositing a mechanical layer, wherein the mechanical layer includes a planarization layer configured to provide chemical mechanical planarization to the PMUT, or a mechanical membrane configured to provide stiffness to the PMUT and frequency response adjustment;
depositing a first electrode configured to be coupled to a circuit ground plane;
depositing a piezoelectric layer configured to separate the first electrode and a second electrode;
depositing the second electrode configured to be coupled to a signal; and
creating patterns on the first electrode, the piezoelectric material, and the second electrode configured to route control signals of the PMUT; and
removing the release layer to separate the flexible array of PMUTs from the carrier.

US Pat. No. 10,770,645

ORIENTED PIEZOELECTRIC FILM, METHOD FOR PRODUCING THE ORIENTED PIEZOELECTRIC FILM, AND LIQUID DISPENSING HEAD

CANON KABUSHIKI KAISHA, ...

1. An oriented piezoelectric film comprising a perovskite type crystal represented by general formula (1):Ba1-xCaxTi1-yZryO3(0?x?0.2, and 0?y?0.2)  (1),
wherein the oriented piezoelectric film is formed on a metallic electrode having a (111) orientation, and has the (111) orientation according to a pseudocubic crystal notation.

US Pat. No. 10,770,644

PIEZOELECTRIC DEVICE

ALPS ALPINE CO., LTD., T...

1. A piezoelectric device producing output according to deformation of a composite piezoelectric body, the piezoelectric device comprising:a substrate that is flexible and thermally deformable; and
a composite piezoelectric body disposed on the substrate, the composite piezoelectric body including:
a piezoelectric layer containing an organic binder and piezoelectric particles,
a first electrode layer stacked on a first surface side of the piezoelectric layer, and
a second electrode layer stacked on a second surface side of the piezoelectric layer,
wherein the substrate is insert molded and integrated with a molded resin body having a curved shape;
the substrate is formed of a thermoplastic resin;
the organic binder is formed of a thermoplastic resin;
the first electrode layer contains a first binder resin which is a thermoplastic resin, and first conductive particles dispersed in the first binder resin;
the second electrode layer contains a second binder resin which is a thermoplastic resin, and a second conductive particles dispersed in the second binder resin; and
the organic binder has a melt viscosity at 250° C. of 300 Pa·s or more.

US Pat. No. 10,770,643

PIEZOELECTRIC MICRO-ELECTRO-MECHANICAL ACTUATOR DEVICE, MOVABLE IN THE PLANE

STMICROELECTRONICS S.R.L....

1. A MEMS actuator device comprising:a substrate; and
a base unit, the base unit including:
a base beam element having a first end, a second end, a main extension in an extension plane and a thickness in a thickness direction that is perpendicular to the extension plane and smaller than the main extension;
a piezoelectric region on or in the base beam element;
an anchor region fixed with respect to the base beam element and to the substrate; and
a base constraint structure coupled to the second end of the base beam element, the base constraint structure including a base constraint element that is undeformable in the thickness direction and a base hinge structure arranged between the base beam element and the base constraint element, the base constraint structure being configured to allow a movement of the second end of the base beam element in the extension plane and prevent or substantially reduce a deformation of the base beam element in the thickness direction.

US Pat. No. 10,770,642

TWO-DIMENSIONAL MODE RESONATORS

CARNEGIE MELLON UNIVERSIT...

1. A MEM device forming a two-dimensional mode resonator comprising:a piezoelectric layer having a top surface and a bottom surface;
a first metallic grating disposed on said top surface, said first metallic grating comprising a plurality of electrically-coupled, parallel electrodes extending across said top surface; and
a second metallic grating disposed on said bottom surface, said second metallic grating comprising a plurality of electrically-coupled, parallel electrodes extending across said bottom surface;
wherein all parallel electrodes on the top surface are connected together and further wherein all electrodes on the bottom surface are connected together.

US Pat. No. 10,770,641

PIEZOELECTRIC ELEMENT

TDK CORPORATION, Tokyo (...

1. A piezoelectric element comprising:first and second electrodes opposing each other;
a first piezoelectric body layer disposed between the first electrode and the second electrode;
a plurality of through-holes penetrating the first piezoelectric body layer; and
a plurality of first through-hole conductors disposed in the plurality of through-holes, wherein;
each of the plurality of first through-hole conductors is (1) directly connected to the first electrode and the second electrode and (2) surrounded by material of the first piezoelectric body layer; and
the plurality of first through-hole conductors includes at least three through-hole conductors that are arrayed in a matrix when seen in an opposing direction of the first and second electrodes.

US Pat. No. 10,770,640

CAPACITIVE RF MEMS INTENDED FOR HIGH-POWER APPLICATIONS

THALES, Courbevoie (FR)

1. A capacitive radiofrequency MicroElectroMechanical System or capacitive RF MEMS for high-power applications comprising a membrane suspended above an RF transmission line and resting on ground planes, the membrane exhibiting a lower face and an upper face opposite to the lower face, wherein said membrane comprises a metallic material and in that a first layer comprising a refractory metallic material different from the metallic material of the membrane, said first layer at least partially covers the upper face of the membrane so as to prevent the heating of the membrane.

US Pat. No. 10,770,639

METHOD OF FORMING SUPERCONDUCTING WIRE

1. A method of forming a superconducting wire, the method comprising:forming a superconducting precursor film on a substrate using a deposition apparatus, the superconducting precursor film containing Re, Ba, and Cu and having a composition in which Ba is poor and Cu is rich compared to stoichiometric ReBCO (Gd1Ba2Cu3O7?y, 0?y?0.65, Re: Rare earth element); and
annealing the substrate using an annealing apparatus, such that annealing the substrate is performed for one minute to two minutes,
wherein annealing the substrate includes:
heating the substrate to melt the superconducting precursor film;
providing an oxygen gas having an oxygen partial pressure of about 10 mTorr to about 200 mTorr on the molten superconducting precursor film to form a superconducting layer including an epitaxial superconductor biaxially aligned only in the c-axis direction perpendicular to the substrate; and
cooling the substrate,
wherein the Re is Gd, and the superconducting precursor film includes Gd, Ba, and Cu in a mixing ratio of 1:1:2.5,
wherein the substrate is heated to a c-axis growth temperature determined according to the oxygen partial pressure, and
wherein the c-axis growth temperature includes a lower limit temperature and an upper limit temperature, and when the oxygen partial pressure increases to about 20 mTorr to about 150 mTorr, the lower limit temperature gradually increases from about 780° C. to about 848° C., and the upper limit temperature gradually increases from about 800° C. to about 866° C.

US Pat. No. 10,770,638

FABRICATION OF INTERLAYER DIELECTRICS WITH HIGH QUALITY INTERFACES FOR QUANTUM COMPUTING DEVICES

Google LLC, Mountain Vie...

1. A method of fabricating a device comprising:providing a first wafer comprising a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer;
providing a second wafer comprising a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer;
forming a first superconductor layer on the first dielectric layer;
forming a second superconductor layer on the second dielectric layer;
joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack at an ambient temperature below approximately 150° C.;
identifying an exposed first surface of the first dielectric layer; and
forming a third superconductor layer on the exposed first surface of the first dielectric layer.

US Pat. No. 10,770,637

ENERGY HARVESTER

SAMSUNG ELECTRONICS CO., ...

1. An energy harvester comprising:a first charging member comprising a plurality of first protruding parts; and
a second charging member comprising a plurality of second protruding parts arranged between the first protruding parts and comprising a material different from that of the first protruding parts,
wherein, when at least one of the first and second charging members moves, side surfaces of the first protruding parts and side surfaces of the second protruding parts come into contact with each other, or gaps between the side surfaces of the first protruding parts and the side surfaces of the second protruding parts are changed, thereby generating electrical energy,
wherein the second charging member comprises a second electrode including:
a plurality of first sub-electrodes arranged parallel to an arrangement direction of the first and second protruding parts and electrically connected to each other; and
a plurality of second sub-electrodes electrically isolated from the plurality of first sub-electrodes and arranged between the first sub-electrodes and electrically connected to each other,
wherein the second charging member further comprises a dielectric layer, and
wherein the second protruding parts are disposed on a first surface of the dielectric layer, and the second electrode is disposed on a second surface of the dielectric layer which is different from the first surface of the dielectric layer.

US Pat. No. 10,770,636

LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

EPISTAR CORPORATION, Hsi...

1. A light-emitting device, comprising:a light-emitting unit including a non-light-emitting element and a light-emitting diode, wherein the light emitting diode has a first electrode and a second electrode and the non-light-emitting element has a third electrode and a fourth electrode;
a reflective layer covering the non-light-emitting element;
a light-transmitting layer covering the reflective layer and the light-emitting diode; and
a metal connection layer electrically connected to the non-light-emitting element and the light-emitting diode, wherein the metal connection layer has a first connection portion covering at least part of the first electrode and at least part of the fourth electrode and a second connection portion covering at least part of the second electrode and at least part of the third electrode.

US Pat. No. 10,770,635

LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

Epistar Corporation, Hsi...

1. A light-emitting device, comprising:a light-emitting stack comprising a top surface, a bottom surface, and a side surface arranged between the top surface and the bottom surface;
a light-reflective enclosure, surrounding the light-emitting stack in a configuration exposing the top surface, and comprising an inner sidewall, a first outer sidewall, and an upper surface between the inner sidewall and the first outer sidewall, wherein the inner sidewall is arranged to face the side surface of the light-emitting stack and the upper surface comprises a first convex area protruded outward from the inner sidewall to the outer sidewall;
a contact electrode formed under the bottom surface of the light-emitting stack; and
a wavelength converting layer covering the top surface and the upper surface, and comprising a second outer sidewall,
wherein the first outer sidewall and the second outer sidewall are coplanar.

US Pat. No. 10,770,634

REFLECTORS HAVING OVERALL MESA SHAPES

FACEBOOK TECHNOLOGIES, LL...

1. An apparatus for emitting light, comprising:a mesa complement structure;
a first-type doped semiconductor;
a light emission layer;
a second-type doped semiconductor; and
a reflector,
wherein the mesa complement structure, the first-type doped semiconductor, the light emission layer, and the second-type doped semiconductor are arranged in layers and form an overall mesa-shaped, layered structure, and
wherein the reflector is formed on the overall mesa-shaped, layered structure and configured to collimate light that emits from the light emission layer and reaches the reflector through the mesa complement structure.

US Pat. No. 10,770,633

OPTOELECTRONIC COMPONENT AND METHOD OF OPERATING AN OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...

1. An optoelectronic component comprising:a first optoelectronic semiconductor chip configured to emit light comprising a wavelength from an infrared spectral range, and
a second optoelectronic semiconductor chip configured to emit light comprising a wavelength from a visible spectral range, wherein
the optoelectronic component comprises a reflector body comprising a top side and an underside,
the reflector body comprises a cavity opened toward the top side,
a wall of the cavity constitutes a reflector,
the first optoelectronic semiconductor chip is arranged at a bottom of the cavity,
wherein the optoelectronic component comprises an optical element arranged in the cavity such that light emitted by the first optoelectronic semiconductor chip and light emitted by the second optoelectronic semiconductor chip at least partly pass into the optical element, and the optical element is configured to mix light emitted by the first optoelectronic semiconductor chip and light emitted by the second optoelectronic semiconductor chip, and
the optical element comprises a light-transmissive body comprising a top side and an underside, wherein a reflective coating is arranged at least in sections at side faces of the light-transmissive body extending between the top side and the underside.

US Pat. No. 10,770,632

LIGHT SOURCE DEVICE

NICHIA CORPORATION, Anan...

1. A light source device comprising:a light-shielding member defining an opening;
a light-guide member located in the opening in a top view and including two or more divided lens portions; and
a plurality of light-emitting parts disposed such that each of the plurality of light-emitting parts corresponds to a respective one of the lens portions, each of the plurality of light-emitting parts being configured to be individually turned on,
wherein each of the light-emitting parts has an upper surface serving as a light-emitting surface,
wherein the light-shielding member covers a portion of the light-emitting surface of at least one of the plurality of light-emitting parts in the top view, and
wherein irradiation areas corresponding to the light-emitting parts are at least partially different from each other.

US Pat. No. 10,770,631

DISPLAY APPARATUS USING SEMI-CONDUCTOR LIGHT-EMITTING DEVICE

LG ELECTRONICS INC., Seo...

1. A display apparatus, comprising:a display unit;
a plurality of semiconductor light emitting elements having at least a first conductive electrode to form individual pixels of the display unit;
an adhesive layer disposed between adjacent semiconductor light emitting elements;
a thin-film transistor having a gate region disposed closer to an upper surface of the display unit than a source region and a drain region;
a via hole formed in the adhesive layer;
a via hole electrode extending in the via hole and electrically connecting the at least one conductive electrode of a corresponding semiconductor light emitting element and a source-drain electrode of the thin-film transistor; and
a connection electrode connecting the via hole electrode to the first conductive electrode,
wherein the via hole electrode extends in the via hole and to a lower surface of the adhesive layer, and
wherein the connection electrode is disposed on the lower surface of the adhesive layer and is not disposed within the via hole.

US Pat. No. 10,770,630

LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light-emitting device comprising:a substrate;
at least one light-emitting element on or above the substrate, the at least one light-emitting element having an upper surface serving as a light-emitting surface of the at least one light-emitting element;
a light-transmissive member that is plate-shaped and that has a lower surface that faces the upper surface of the at least one light-emitting element; and
a covering member that covers a lateral surface of the at least one light-emitting element and a lateral surface of the light-transmissive member,
wherein the upper surface of the at least one light-emitting element has a rectangular shape so as to have a first lateral side and a second lateral side opposite to each other, and a third lateral side and a fourth lateral side opposite to each other,
wherein a first upper surface of the light-transmissive member has a rectangular shape having a first lateral side and a second lateral side opposite to each other, and a third lateral side and a fourth lateral side opposite to each other,
wherein the light-transmissive member is disposed on or above the at least one light-emitting element such that, in a plan view from above the light-emitting device, the first lateral side of the first upper surface of the light-transmissive member is outside the first lateral side of the upper surface of the at least one light-emitting element, and the second lateral side of the first upper surface of the light-transmissive member is inside the second lateral side of the upper surface of the at least one light-emitting element,
wherein the light-transmissive member has a second upper surface located outside the second lateral side of the first upper surface of the light-transmissive member in the plan view,
wherein the second upper surface is located below the first upper surface and covered with the covering member,
wherein the lower surface of the light-transmissive member covers the entire upper surface of the at least one light-emitting element, and
wherein the light-transmissive member is disposed on or above the at least one light-emitting element such that, in the plan view, the third lateral side of the first upper surface of the light-transmissive member is outside the third lateral side of the upper surface of the at least one light-emitting element, and the fourth lateral side of the first upper surface of the light-transmissive member is outside the fourth lateral side of the upper surface of the at least one light-emitting element.

US Pat. No. 10,770,629

LIGHT EMITTING DEVICE

Sanken Electric Co., Ltd....

1. A light emitting device of a chip on board-type comprising:a substrate having a main surface on which a first arrangement region and a second arrangement region are defined;
a plurality of blue light emitting elements arranged on the main surface of the substrate;
a phosphor sheet containing a phosphor that is excited by emission light from the plurality of blue light emitting elements and emits excitation light, the phosphor sheet being disposed above the plurality of blue light emitting elements; and
an intermediate layer that covers the plurality of blue light emitting elements, the intermediate layer being disposed between the substrate and the phosphor sheet,
wherein
the plurality of blue light emitting elements includes first blue light emitting elements which emit first emission light having a first wavelength taken as a peak wavelength of a light emission spectrum, the first blue light emitting elements being arranged on the first arrangement region, and second blue light emitting elements which emit second emission light having a second wavelength taken as a peak wavelength of a light emission spectrum, the second blue light emitting elements being disposed on the second arrangement region, and the second wavelength being a longer wavelength than the first wavelength by a wavelength difference of at least 10 nm,
the first arrangement region and the second arrangement region are provided such that a difficulty of the second blue light emitting elements to absorb the first emission light is increased,
the phosphor sheet is divided into a plurality of phosphor regions when viewed from above, the plurality of phosphor regions being different from one another in at least either one of components and blending ratio of the phosphor,
a refractive index of the intermediate layer is lower than a refractive index of the phosphor sheet,
a film thickness of the intermediate layer is larger than ½ of an arrangement interval of the plurality of blue light emitting elements, andwires which sequentially connect the plurality of blue light emitting elements to one another are embedded in the intermediate layer.

US Pat. No. 10,770,628

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising: a light emitting element having an emission peak wavelength in a range of 380 nm to 420 nm; and a fluorescent member including at least one fluorescent material that is excited by light from the light emitting element for light emission,a mixture of light from the light emitting element and light from the fluorescent material having a correlated color temperature of 2000 K to 7500 K as measured according to JIS Z8725,
the light emitting device having a spectral distribution in which, when an integral value over a wavelength range of 380 nm to 780 nm is normalized to 100%, the proportion of an integral value over a wavelength range of 380 nm to 420 nm is 15% or more, and
the ratio a as defined by the following expression (1) falling within a range of 0.9 to 1.6:

wherein BS represents a maximum emission intensity in a wavelength range of 430 nm to less than 485 nm in a spectral distribution of a reference light source at the correlated color temperature of the light emitting device, Gs represents a maximum emission intensity in a wavelength range of 485 nm to 548 nm in the spectral distribution of the reference light source at the correlated color temperature of the light emitting device, and the denominator of the expression (1) is a ratio of Gs to Bs, and wherein BL represents a maximum emission intensity in a wavelength range of 430 nm to less than 485 nm in the spectral distribution of the light emitting device, GL represents a maximum emission intensity in a wavelength range of 485 nm to 548 nm in the spectral distribution of the light emitting device, and the numerator of the expression (1) is a ratio of GL to BL.

US Pat. No. 10,770,627

WAVELENGTH CONVERTING MATERIAL FOR A LIGHT EMITTING DEVICE

Lumileds Holding B.V., (...

1. A luminescent material, comprising:a host lattice crystallizing in a trigonal calcium gallogermanate structure type; and
dopants disposed in the host lattice, the dopants comprising:
trivalent chromium; and
tetravalent chromium in a concentration that is less than 1% of a total concentration of all chromium in the luminescent material.

US Pat. No. 10,770,626

LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS

EPISTAR CORPORATION, Hsi...

1. An electronic device comprising:a plurality of light-emitting elements, each light-emitting element comprising a first bottom surface and a pair of contact pads disposed on the first bottom surface;
a polymeric binder covering the plurality of light-emitting elements, exposing the pair of contact pads, and comprising a flat top surface and a second bottom surface;
a plurality of contact layers connected to the pair of contact pads and the second bottom surface;
an insulating layer disposed under the first bottom surface and connected to the plurality of contact layers; and
a plurality of contacts disposed under the insulating layer and electrically connected to the plurality of contact layers.

US Pat. No. 10,770,625

SEMICONDUCTOR DEVICE PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a first substrate having a first surface and a second surface opposite the first surface;
a heat dissipation structure disposed on the first surface of the first substrate; and
a first optical module disposed on the heat dissipation structure and comprising:
a housing;
a first optical component disposed on the housing; and
a light-emitting device disposed in the housing and capable of emitting light toward the first optical component.

US Pat. No. 10,770,624

SEMICONDUCTOR DEVICE PACKAGE, OPTICAL PACKAGE, AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a first substrate having a first surface;
a second substrate on the first surface of the first substrate, the second substrate having a first surface and a second surface connected to the first surface of the second substrate, a surface area of the first surface of the second substrate being less than a surface area of the second surface, and the first surface of the second substrate being disposed on the first surface of the first substrate; and
a light source on the second surface of the second substrate.

US Pat. No. 10,770,623

LIGHT EMITTING DIODE AND ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An emitting diode, comprising: a first electrode in a first pixel; a first emitting layer positioned on the first electrode and including a first amorphous oxide semiconductor material and a first quantum dot, wherein the first amorphous oxide semiconductor material includes an indium atom, a gallium atom and a zinc atom; and a second electrode covering the first emitting layer; wherein the first amorphous oxide semiconductor material has an energy level matching an energy level of the first quantum dot and the matched energy level enhances a charge transfer property of the emitting diode; further comprising a second emitting layer in a second pixel and including a second amorphous oxide semiconductor material and a second quantum dot, wherein the second amorphous oxide semiconductor material includes an indium atom, a gallium atom and a zinc atom.

US Pat. No. 10,770,622

LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT PACKAGE COMPRISING SAME

LG INNOTEK CO., LTD., Se...

1. A light-emitting device comprising:a substrate;
a first conductive-type semiconductor layer disposed on the substrate and including at least one first recess;
a first electrode directly contacting an upper surface of the first conductive-type semiconductor layer;
a superlattice layer disposed on the first conductive-type semiconductor layer and including at least one second recess;
an active layer disposed on the superlattice layer and including at least one third recess;
an electron blocking layer disposed on the active layer and including at least one fourth recess; and
a second conductive-type semiconductor layer disposed on the electron blocking layer,
wherein the at least one first recess, the at least one second recess, the at least one third recess, and the at least one fourth recess are overlapped with each other,
wherein the at least one first recess includes a first depth,
wherein the at least one second recess includes a second depth,
wherein the at least one third recess includes a third depth,
wherein the at least one fourth recess includes a fourth depth,
wherein the first depth is less than the fourth depth,
wherein the second conductive-type semiconductor layer includes at least one protrusion protruding toward the substrate,
wherein a height of the protrusion is less than the fourth depth,
wherein a distance between a lowest portion of the at least one first recess in the first conductive-type semiconductor layer and an upper surface of the substrate is less than a distance between a lower surface of the first electrode and the upper surface of the substrate, and
wherein a distance between a topmost portion of the at least one first recess in the first conductive-type semiconductor layer and the upper surface of the substrate is substantially equal to a distance between the lower surface of the first electrode and the upper surface of the substrate.

US Pat. No. 10,770,621

SEMICONDUCTOR WAFER

Stanley Electric Co., Ltd...

1. A semiconductor wafer comprising:an element layer comprising at least three layers including an n-type layer, an active layer, and a p-type layer on one surface of a sapphire substrate, wherein the element layer is made of a group III nitride single crystal layer,
wherein a surface of the element layer is bent in a convex way, and a curvature thereof is 530 km?1 to 800 km?1, and
wherein the group III nitride single crystal layer is made of an AlGaInN layer satisfying a composition represented by AlxInyGazN, wherein x, v, and z are rational numbers satisfying 0.3?x?1.0, 0?y 0.7, and 0?z?0.7, and x+y+z=1.0.

US Pat. No. 10,770,620

EPITAXIAL GALLIUM NITRIDE BASED LIGHT EMITTING DIODE AND METHOD OF MAKING THEREOF

GLO AB, Lund (SE)

1. A light emitting diode (LED), comprising:a n-doped region;
a p-doped region; and
a light emitting region located between the n-doped region and a p-doped region, wherein the n-doped region comprises a first GaN layer, at least one n-doped second GaN layer located over the first GaN layer, an AlGaN dislocation blocking layer located over the at least one n-doped second GaN layer, and a n-doped third GaN layer located over the AlGaN dislocation blocking film;
wherein the light emitting region comprises:
an epitaxial first strain-modulating film located on the n-type region;
an epitaxial first cap layer located on the first strain-modulating film;
an epitaxial second strain-modulating film located on the first cap layer;
an epitaxial second cap layer located on the second strain-modulating film;
an epitaxial third strain-modulating film located on the second cap layer;
an epitaxial intermediate cap located on the third strain-modulating film;
a first quantum well set located on the intermediate cap;
an epitaxial AlGaN containing cap region located on the first quantum well set;
a second quantum well set located on the AlGaN containing cap region; and
an epitaxial third cap layer located on the second quantum well set.

US Pat. No. 10,770,619

LIGHT-EMITTING DEVICES AND DISPLAYS WITH IMPROVED PERFORMANCE

SAMSUNG ELECTRONICS CO., ...

1. A light-emitting device comprising:a first electrode comprising an anode opposite a second electrode comprising a cathode;
a hole injection layer adjacent to the first electrode; and
an emissive layer of inorganic semiconductor nanocrystals disposed between the hole injection layer and the second electrode, the inorganic semiconductor nanocrystals comprising a plurality of semiconductor nanocrystals capable of emitting light upon excitation,
wherein the device has an external quantum efficiency of at least about 2.2 percent.

US Pat. No. 10,770,618

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a light emitting element that comprises a first electrode and a second electrode located at a lower surface of the light emitting element;
a covering member having an upper surface, a lower surface, and a plurality of lateral surfaces extending from the upper surface to the lower surface, wherein the covering member covers the light emitting element such that at least a portion of a lower surface of each of the first electrode and the second electrode is exposed from the lower surface of the covering member and such that the lower surface of the covering member is flush with the exposed portion of the lower surface of each of the first electrode and the second electrode;
first and second metal layers, each of which covers and directly contacts (i) the exposed portion of the lower surface of a respective one of the first and second electrodes, (ii) a respective portion of the lower surface of the covering member that is flush with the exposed portion of the lower surface of each of the first electrode and the second electrode, and (iii) at least one of the lateral surfaces of the covering member.

US Pat. No. 10,770,617

LIGHT EMISSION DIODE WITH FLIP-CHIP STRUCTURE AND MANUFACTURING METHOD THEREOF

National Chiao Tung Unive...

1. A manufacturing method of a flip-chip LED device, comprising:providing a group III-V substrate, and forming a group III-V stack layer on the group III-V substrate;
forming a transparent conductor layer on the group III-V stack layer;
coating a glue layer on the transparent conductor layer, and bonding the transparent conductor layer with a transparent protective substrate;
performing a separation process, so as to remove the group III-V substrate from the group III-V stack layer;
flipping a stacking structure formed by the group III-V stack layer, the transparent conductor layer and the transparent protective substrate once;
defining a second conductivity plat illumination region and performing a metal deposition to define a second conductivity metal electrode on the second conductivity region, then performing a reactive ion etching process to etch through the group III-V stack layer which is located on the transparent conductor layer within a non-protective region;
defining a first conductivity metal electrode region and a first conductivity metal electrode on the first conductivity metal electrode region, and coating the first conductivity metal electrode region with a first metal to form and pad the first conductivity metal electrode on the first conductivity metal electrode region;
defining a second conductivity metal electrode region on the second conductivity region, and coating the second conductivity metal electrode region with a second metal;
using a physical deposition to coat the first conductivity metal electrode, the second conductivity metal electrode and the transparent conductor layer with an insulating layer, such that the insulating layer covers the first conductivity metal electrode, the second conductivity metal electrode and the transparent conductor layer; and
defining the first conductivity metal electrode and the second conductivity metal electrode and performing an etching process to expose the first conductivity metal electrode and the second conductivity metal electrode;
wherein the glue layer is transparent optical glue layer and is in directly contact with the transparent protective substrate such that the transparent conductor layer, the glue layer and the transparent protective substrate form three successively-stacked transparent layers;
defining the first conductivity metal electrode and the second conductivity metal electrode and coating the first conductivity metal electrode and the second conductivity metal electrode with a third metal to smooth the first conductivity metal electrode and the second conductivity metal electrode; and
grinding and polishing the transparent protective substrate, and performing a cutting process to form a plurality of chip dies.

US Pat. No. 10,770,616

HETEROSTRUCTURE WITH SACRIFICIAL LAYER

Sensor Electronic Technol...

1. A heterostructure comprising:a substrate structure including:
a substrate; and
a set of group III nitride buffer layers directly adjacent to the substrate;
a set of group III nitride device layers located adjacent to the substrate structure; and
a sacrificial layer located between the substrate structure and the set of group III nitride device layers, wherein the sacrificial layer includes at least one sublayer including a first set of regions formed of a first material and a second set of regions located laterally adjacent to the first set of regions and having a composition different from the first material, wherein the first material has a bandgap smaller than a bandgap of each of the set of group III nitride buffer layers, and wherein the composition of the second set of regions is similar to a composition of a group III nitride buffer layer in the set of group III nitride buffer layers in the substrate structure.

US Pat. No. 10,770,615

AL—GA—N TEMPLATE, A METHOD FOR PREPARING AL—GA—N TEMPLATE, AND SEMICONDUCTOR DEVICE COMPRISING AL—GA—N TEMPLATE

HC SEMITEK (SUZHOU) CO., ...

1. An AlGaN template, comprising a substrate and an Al1-xGaxN crystallization thin film deposited on the substrate, wherein0 the Al1-xGaxN crystallization thin film comprises an AlGaN layer deposited on the substrate, and the AlGaN layer is doped with oxygen; and
a content of oxygen in the first AlGaN layer gradually decreases or gradually increases from an interface between the substrate and the first AlGaN layer to a surface of the first AlGaN layer.

US Pat. No. 10,770,614

MONOLITHICALLY INTEGRATED HIGH VOLTAGE PHOTOVOLTAICS AND LIGHT EMITTING DIODE WITH TEXTURED SURFACE

International Business Ma...

1. An electrical device comprising:a first conductivity type semiconductor layer of a type III-V semiconductor deposited on a substrate in a plurality of raised islands having triangular cross-sections;
a second conductivity type semiconductor layer of a type III-V semiconductor deposited on the plurality of raised islands to form a textured surface; and
a light emitting diode formed on the textured surface.

US Pat. No. 10,770,613

METHODS FOR CREATING A SEMICONDUCTOR WAFER HAVING PROFILED DOPING AND WAFERS AND SOLAR CELL COMPONENTS HAVING A PROFILED FIELD, SUCH AS DRIFT AND BACK SURFACE

1366 TECHNOLOGIES INC., ...

1. A semiconductor wafer for use as a solar collector, the wafer comprising a body having a first and a second surface, the body having a dopant concentration profile, there being a larger concentration of dopant at a first surface of the wafer, and a continuous transition to a lesser concentration of dopant at a second surface of the wafer, the larger concentration being at least three times the lesser concentration, wherein the first surface of the wafer and the second surface of the wafer are opposite surfaces of the wafer separated by the body.

US Pat. No. 10,770,612

MULTIJUNCTION SOLAR CELLS HAVING AN INDIRECT HIGH BAND GAP SEMICONDUCTOR EMITTER LAYER IN THE UPPER SOLAR SUBCELL

SolAero Technologies Corp...

1. A multijunction solar cell comprising:an upper solar subcell having an indirect band gap semiconductor emitter layer and a base layer, the emitter layer and the base layer forming a heterojunction solar subcell,
wherein the emitter layer of the upper solar subcell is an n-type AlxGa1-xAs layer with 0.7 a lower solar subcell disposed beneath the upper solar subcell, wherein the lower solar subcell has an emitter layer and a base layer forming a photoelectric junction.

US Pat. No. 10,770,611

PHOTOVOLTAIC DEVICE AND ASSOCIATED FABRICATION METHOD

ELECTRICITE DE FRANCE, P...

1. A photovoltaic device comprising:a plurality of photovoltaic cells, separated from each other;
a support receiving the cells; and
a light guide in contact with the cells and comprising a primary guide with a proximal surface that is proximal to the cells, where the proximal surface is oriented towards the cells and the support,
wherein the photovoltaic device comprises, between the cells, areas located between the support and the primary guide which comprise a material with an index of refraction less than that of the proximal surface, where the material is in contact with the proximal surface,
wherein the support and the proximal surface of the primary guide are separated by a distance between 1 ?m and 20 ?m;
wherein the light guide comprises a plurality of secondary guides separated from each other by the material where each secondary guide is interposed between the proximal surface of the primary guide and a photovoltaic cell; and
wherein each secondary guide is in direct contact with a photovoltaic cell at one extremity of each secondary guide and in direct contact with the proximal surface of the primary guide at another extremity of each secondary guide.

US Pat. No. 10,770,610

PHOTOVOLTAIC MODULE INTERCONNECT JOINTS

SunPower Corporation, Sa...

1. A photovoltaic (PV) module comprising:a plurality of PV cells, each of the plurality of PV cells having:
a first side facing the sun to collect solar radiation;
a second side facing away from the sun during normal operation of the PV module;
at least two opposite peripheral edges;
a first terminal on one peripheral edge of the PV cell, the first terminal comprising a first contact pad; and,
a second terminal on an opposite peripheral edge of the PV cell from the first terminal, the second terminal comprising a second contact pad, wherein the first and second contact pads are discrete;
at least one interconnect joint comprising:
a first bonding region comprising a first adhesive material;
a second bonding region comprising a second adhesive material, wherein the first bonding region of the interconnect joint is in physical and electrical contact with the first electrically conductive contact pad of a first of the plurality of PV cells and in physical and electrical contact with the second electrically conductive contact pad of a second of the plurality of PV cells, but the second bonding region is not in physical contact with the first contact pad of the first of the plurality of PV cells and is not in physical contact with the second contact pad of the second of the plurality of PV cells;
wherein the first and second adhesive materials are different adhesive materials; the first bonding region is electrically conductive, the second adhesive material is electrically non-conductive; and,
the interconnect joint coupling the first terminal of the first PV cell of the plurality of PV cells and the second terminal of the second PV cell of the plurality of PV cells, where both the first and second bonding regions each contact the first and second terminals of the respective PV cells to form an interconnect bond line, wherein the interconnect joint has a single thickness throughout its width;
wherein each of the PV cells has an edge portion along one of the peripheral edges and an edge portion of the first PV cell overlaps an edge portion of the second PV cell,
wherein the first side of the first PV cell faces the second side of the second PV cell; and
wherein the first PV cell overlaps the second PV cell in a shingled configuration such that the electrically conductive contact pads are not visible on the front side of the second PV cell.

US Pat. No. 10,770,609

MULTILAYERED POLYOLEFIN-BASED FILMS HAVING A LAYER COMPRISING A CRYSTALLINE BLOCK COPOLYMER COMPOSITE OR A BLOCK COPOLYMER COMPOSITE RESIN

Dow Global Technologies L...

1. A multilayer film structure comprising: a tie Layer B and a bottom Layer C;B. the tie layer B has a top facial surface and a bottom facial surface;
C. the bottom layer C comprises a propylene-based polymer having at least one melting peak greater than 125 C and has a top facial surface and a bottom facial surface, and the top facial surface of Layer C is in adhering contact with the bottom facial surface of Layer B;
wherein the Layer B consists of (1) a block composite resin (BC), (2) an optional colorant, (3) an optional stabilizer, and (4) an optional antioxidant, the BC made from monomers consisting of propylene and ethylene, and the BC has
i) an ethylene-propylene copolymer (EP) comprising at least 80 mol % polymerized ethylene;
ii) a crystalline propylene-based polymer (CPP); and
iii) a diblock copolymer comprising (a) an ethylene-propylene block comprising at least 80 mol % polymerized ethylene and (b) a crystalline propylene block.

US Pat. No. 10,770,608

SEMI-TRANSPARENT THIN-FILM PHOTOVOLTAIC MONO CELL

Garmin Switzerland GmbH, ...

1. A photovoltaic mono cell semi-transparent to light, comprising:a plurality of photovoltaic active zones separated by transparency zones,
said photovoltaic active zones being formed of a stack of thin films comprising a transparent electrode, an absorber film and a metallic electrode which are arranged in the stated order, from a first side of the stack to a second side of the stack, on a substrate transparent to light, such that the first side of the stack is closest to the substrate;
and said transparency zones being apertures made at least in the metallic electrode and in the absorber film to allow through light;
an electrically conducting collection gate arranged in contact with the transparent electrode to reduce its electrical resistance and avoid direct physical or electrical contact with the metallic electrode,
a first collection bus linked to the collection gate to collect electrical charges from the transparent electrode; and
a second collection bus linked to the metallic electrode, the second collection bus spaced apart from the first collection bus,
wherein said photovoltaic active zones furthermore contain several channels, made in the metallic electrode and the absorber film, said collection gate being separated from the metallic electrode and from the absorber film by a dielectric material, so as to reduce the series resistance of the transparent electrode while minimizing the visibility of the collection gate,
wherein the collection gate substantially covers the photovoltaic active zones.

US Pat. No. 10,770,607

INTERCONNECTED PHOTOVOLTAIC MODULE CONFIGURATION

FLISOM AG, Niederhasli (...

1. A photovoltaic module assembly, comprising:a front sheet;
a back sheet;
an array of photovoltaic modules disposed between the front sheet and the back sheet, each of the photovoltaic modules are separated from one another by a first length, wherein
each photovoltaic module comprises two or more sub-modules that each have a cathode region and an anode region, and wherein the anode region is disposed at an opposite end of the photovoltaic module from the cathode region,
adjacent sub-modules within each photovoltaic module are separated by a second length, and
the first length is greater than the second length;
a first busbar that is aligned in a first direction, and is electrically coupled to the cathode region of each sub-module; and
a second busbar that is aligned in the first direction, and is electrically coupled to the anode region of each sub-module.

US Pat. No. 10,770,606

SOLAR ARRAY SYSTEM AND METHOD OF MANUFACTURING

Sierra Nevada Corporation...

1. A method of manufacturing a space-grade solar array, comprising:dicing a multi-junction solar wafer having a plurality of solar cells to form a plurality of diced multi-junction solar cells, wherein each solar cell already has a positive electrical contact and a negative electrical contact both located on a common, back side of the solar cell;
using a pick and place robot to position the diced solar cells onto a printed circuit board with the back side of each diced solar cell in contact with a front side of the printed circuit board such that the positive electrical contact and the negative electrical contact of each diced solar cell electrically couples to a corresponding electrical contact of the printed circuit board, and wherein the printed circuit board has electrical traces that include solar cell-to-solar cell interconnect wiring and bypass and blocking diodes, and wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the electrical contact of the printed circuit board; and
after the plurality of diced solar cells are positioned on the printed circuit board, covering the plurality of diced solar cells with a coverglass material while the diced solar cells are positioned on the printed circuit board and bonding the coverglass material to the plurality of diced solar cells.

US Pat. No. 10,770,605

PHOTODIODE WITH SPINEL OXIDE PHOTOACTIVE LAYER

King Abdulaziz University...

1. A photodiode, comprising:an ohmic contact having a first work function;
an inorganic substrate layer in continuous contact with the ohmic contact;
a photoactive layer in continuous contact with the inorganic substrate layer;
a light absorption layer in continuous contact with the photoactive layer; and
a top electrode in contact with the light absorption layer, the top electrode having a second work function;
wherein the inorganic substrate layer comprises a semiconductor;
wherein the photoactive layer consists of ZnFe2O4 nanowires in N2, the ZnFe2O4 nanowires present at 80-90 vol % relative to a total volume of the photoactive layer;
wherein the ZnFe2O4 nanowires have widths of 35-45 nm and lengths of 170-350 nm;
wherein all ZnFe2O4 nanowires are physically adsorbed to the inorganic substrate layer and to the light absorption layer;
wherein the inorganic substrate layer and the photoactive layer are both p-type semiconductors forming an isotype junction between each other;
wherein the light absorption layer comprises at least one material selected from the group consisting of quantum dots, quantum rods, and quantum wires; and
wherein the second work function is higher than the first work function.

US Pat. No. 10,770,604

HYBRID PEROVSKITE BULK PHOTOVOLTAIC EFFECT DEVICES AND METHODS OF MAKING THE SAME

Alliance for Sustainable ...

1. A composition comprising:a methylammonium lead iodide perovskite crystal comprising a ferroelectric domain aligned substantially parallel to a reference axis, wherein:
the ferroelectric domain has a crystal structure consisting essentially of at least one of a tetragonal phase or an orthorhombic phase,
the ferroelectric domain has a width between 2 ?m and 40 ?m,
the ferroelectric domain has a length between one angstrom and 10 mm, and
the ferroelectric domain has a d33 value between 50 pC/N and 60 pC/N.

US Pat. No. 10,770,603

DEVICE AND METHOD FOR OPERATING CAMERAS AND LIGHT SOURCES COMPRISING CONTROLLED ILLUMINATION LIGHT WITH A PULSE DURATION CORRESPONDS TO THE EXPOSURE TIME OF A CAMERA

Symbol Technologies, LLC,...

1. A device comprising:a camera, configured to acquire images periodically according to an exposure time and at a first frequency; and
at least one light source configured to periodically provide illumination light for the camera, the illumination light having a pulse duration that corresponds to the exposure time and having a second frequency that is an integer multiple of the first frequency, wherein successive activations of the at least one light source are imperceptible to an observer when the second frequency is higher than a threshold frequency.

US Pat. No. 10,770,602

OPTICAL SENSOR AND METHOD FOR FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. An optical sensor, comprising:a plurality of pixels disposed in a substrate;
a light collimating layer disposed on the substrate, comprising:
a first light-shielding layer disposed on the substrate;
a plurality of first transparent pillars through the first light-shielding layer correspondingly disposed on the pixels;
a second light-shielding layer disposed on the first light-shielding layer and the first transparent pillars; and
a plurality of second transparent pillars through the second light-shielding layer correspondingly disposed on the first transparent pillars,
wherein a top surface area of each of the first transparent pillars is not equal to a bottom surface area of each of the second transparent pillars, wherein each of the first transparent pillars and the second transparent pillars has a total aspect ratio of between 1:1 and 30:1.

US Pat. No. 10,770,601

ELECTRO-CONDUCTIVE PASTE, SOLAR CELL AND METHOD FOR PRODUCING SOLAR CELL

NAMICS CORPORATION, Niig...

1. An electro-conductive paste set for use with solar cells comprising an electro-conductive paste for forming a bus bar electrode and an electro-conductive paste for forming a finger electrode, wherein:the electro-conductive paste for forming a bus bar electrode comprises an electro-conductive powder, a multiple oxide containing tellurium oxide, and an organic vehicle, wherein the electro-conductive paste contains 0.1 parts by weight to 10 parts by weight of the multiple oxide based on 100 parts by weight of the electro-conductive powder, and wherein a content ratio of the tellurium oxide in 100% by weight of the multiple oxide as TeO2 is 3% by weight to 30% by weight,
the electro-conductive paste for forming a finger electrode contains an electro-conductive powder, a multiple oxide in an amount of 0.1 parts by weight to 10 parts by weight based on 100 parts by weight of the electro-conductive powder, and an organic vehicle, and
a content ratio of tellurium oxide in the multiple oxide in the electro-conductive paste for forming the finger electrode is higher than a content ratio of tellurium oxide in the multiple oxide in the electro-conductive paste for forming the bus bar electrode.

US Pat. No. 10,770,600

METHOD OF USING THE PHOTODETECTING DEVICE

NATIONAL CHIAO TUNG UNIVE...

1. A method of using a photodetecting device to perform photo detection, comprising:providing a photodetecting device comprising:
a transistor comprising a source, a drain and a gate;
a polycrystalline silicon nano-channel layer connecting the source and the drain, wherein the polycrystalline silicon nano-channel layer has a light-receiving surface;
an optical filter layer over the light-receiving surface of the polycrystalline silicon nano-channel layer, wherein the optical filter layer transmits a light within a wavelength range;
an isolation layer between the gate and the polycrystalline silicon nano-channel layer; and
a solution covering the source, the drain and the optical filter layer and wrapping around the gate;
using light to irradiate the optical filter layer of the photodetecting device and rearranging positions of a plurality of electrons and a plurality of holes in the polycrystalline silicon nano-channel layer by the light with a wavelength range capable of passing through the optical filter layer;
changing a current between the source and the drain by rearranging the positions of the plurality of electrons and the plurality of holes, so as to generate a current difference; and
calculating the intensity of the light by the current difference.

US Pat. No. 10,770,599

DEEP TRENCH MOS BARRIER JUNCTION ALL AROUND RECTIFIER AND MOSFET

Champion Microelectronic ...

1. A rectifier device, comprising:a first n-type semiconductor layer;
a second n-type epitaxial semiconductor layer with lower doping concentration but larger depth than that of the first n-type semiconductor layer, deposed on top of the first n-type semiconductor layer;
a p-type semiconductor layer in continuous ring shape deposed on at least the top surface of the second n-type semiconductor layer;
a metal layer deposed above the p-type semiconductor layer and completely overlapping the p-type semiconductor layer;
at least two deep trenches comprising a first enclosed deep trench and a second enclosed deep trench, wherein
the first enclosed deep trench is etched in ring shape along periphery of the rectifier device and from top of the p-type semiconductor layer down to the bottom of the second n-type semiconductor layer; and
the second enclosed deep trench in ring shape running parallel to the first enclosed deep trench but with smaller radius, is etched from the top of the p-type semiconductor layer down to the bottom of the second n-type semiconductor layer;
wherein both the first and second enclosed deep trenches have an oxide coating on their sidewalls and bottom surfaces, and a polysilicon layer filling their centers and connected to the metal layer for operation to form a MOS-Sidewall-Plate structure; and
wherein all trenches of the rectifier device are enclosed trenches in ring shape with the same MOS-Sidewall-Plate structure, and the ring-shape p-type semiconductor layer completely covers at least the upper inner and outer rim portions of each deep trench of the rectifier device.

US Pat. No. 10,770,598

MEMORY DEVICES AND METHODS OF MANUFACTURE THEREOF

Taiwan Semiconductor Manu...

1. A method of manufacturing a memory device, the method comprising:forming a first patterned mask over a substrate;
patterning the substrate to form a first recess and a second recess using the first patterned mask as a mask;
filling the first recess and the second recess with a dielectric material to form a first isolation region and a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate;
forming a second patterned mask over the substrate;
patterning the substrate to form a third recess using the second patterned mask as a mask, wherein the third recess is in the first region;
forming a dielectric layer over the first region, the second region, and the third region of the substrate, the dielectric layer extending into the third recess; and
forming a conductive electrode over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive electrode comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.

US Pat. No. 10,770,597

LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a driving transistor; and
a light-emitting element electrically connected to the driving transistor,
wherein a channel formation region of the driving transistor comprises an oxide semiconductor,
wherein an off-state current of the driving transistor in the channel length direction is smaller than or equal to (?)×10?12 A/?m at a measurement temperature of 120° C. and a drain voltage of 6 V, and
wherein the off-state current of the driving transistor in the channel length direction is smaller than or equal to (?)×10?12 A/?m at a measurement temperature of ?30° C. and a drain voltage of 6 V.

US Pat. No. 10,770,596

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive layer and a capacitor wiring over a substrate, wherein each of the first conductive layer and the capacitor wiring comprises copper;
a first insulating layer over the first conductive layer and the capacitor wiring, wherein the first insulating layer comprises nitrogen;
a second insulating layer over the first insulating layer, wherein the second insulating layer comprises oxygen;
a semiconductor layer over the second insulating layer;
a third insulating layer over the semiconductor layer, wherein the third insulating layer comprises an opening;
a second conductive layer over the second insulating layer, wherein the second conductive layer is electrically connected to the semiconductor layer through the opening, and wherein the second conductive layer comprises at least one selected from the group consisting of W, Ta, Mo, Ti and Cr;
a third conductive layer over the second conductive layer, wherein the third conductive layer is electrically connected to the semiconductor layer, and wherein the third conductive layer comprises copper;
a fourth insulating layer over the third conductive layer; and
a fourth conductive layer over the fourth insulating layer, wherein the fourth conductive layer is electrically connected to the semiconductor layer, wherein the fourth conductive layer comprises a transparent conductive material, and wherein the fourth conductive layer overlaps the capacitor wiring.

US Pat. No. 10,770,595

THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising:a base substrate:
an active layer, comprising an active layer body and a through-hole in a center of the active layer body;
a gate electrode, insulated and spaced apart from the active layer body and surrounding the through-hole; and
a first electrode and a second electrode, both located at a side of the gate electrode distal to the base substrate; wherein the first electrode and the second electrode are insulated from each other, both coupled to the active layer body, and insulated and spaced apart from the gate electrode;
wherein at least a portion of an orthographic projection of the first electrode on the active layer is within the through-hole; and
an orthographic projection of the second electrode on the active layer surrounds the active layer body.

US Pat. No. 10,770,594

GATE-ALL-AROUND FIN DEVICE

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a doped well in a substrate of a first conductivity type;
forming a doped continuous well of a second conductivity type in the substrate of the first conductivity type; and
forming, over the doped continuous well of the second conductivity type, a floating p? fin comprising a p+ body contact formed directly on the floating p? fin,
wherein the doped well is of the first conductivity type.

US Pat. No. 10,770,593

BEADED FIN TRANSISTOR

Intel Corporation, Santa...

1. An integrated circuit including at least one transistor, the integrated circuit comprising:a gate structure including a gate dielectric and a gate electrode; and
a fin below the gate structure, the fin also between portions of the gate structure, the fin including
a first layer including a first semiconductor material, the first layer having upper, middle, and lower sections that form a continuous portion of the first layer that is between the portions of the gate structure, with the middle section below the upper section and above the lower section, wherein a smallest horizontal width of the middle section is at least 2 nanometers (nm) less than each of (i) a smallest horizontal width of the upper section and (ii) a smallest horizontal width of the lower section, and
a second layer in contact with the first layer, the second layer including a second semiconductor material compositionally different from the first semiconductor material, the second layer having a horizontal width that is higher than the smallest horizontal width of the middle section of the first layer.

US Pat. No. 10,770,592

MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a multi-gate semiconductor device, comprising:providing a substrate comprising at least a fin structure and a dummy gate structure over the fin structure and the substrate;
disposing a conductive spacer over sidewalls of the dummy gate structure, wherein portions of the fin structure are exposed from the dummy gate structure and the conductive spacer;
forming a source/drain region in the portions of the fin structure exposed from the dummy gate structure and the conductive spacer;
disposing a dielectric structure over the substrate;
removing the dummy gate structure to form a gate trench in the dielectric structure wherein the conductive spacer is exposed from sidewalls of the gate trench;
disposing at least a gate dielectric layer over a bottom of the gate trench after removing the dummy gate structure; and
disposing a gate conductive structure in the gate trench, wherein sidewalls of the gate conductive structure are in contact with the conductive spacer.

US Pat. No. 10,770,591

SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS

Intel Corporation, Santa...

1. A microelectronic device, comprising:a substrate;
a transistor on the substrate comprising a pair of gate spacers, a gate dielectric layer between the pair of gate spacers and adjacent the substrate, a gate electrode between the pair of gate spacers and adjacent the gate dielectric, and a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode;
a dielectric material on the substrate and the transistor;
a source region in the substrate;
a drain region in the substrate;
a source contact extending through the dielectric material, wherein the source contact is adjacent the source region;
a drain contact extending through the dielectric material, wherein the drain contact is adjacent the drain region;
wherein at least one of the source contact and the drain contact comprises an interface adjacent its respective source region or drain region, a contact interface layer adjacent the interface, and a conductive contact material adjacent the contact interface layer; and
wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure.

US Pat. No. 10,770,590

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor structure, comprising:providing a base substrate, including a substrate, a plurality of gate structures formed on the substrate, and a cap layer formed on the plurality of gate structures, wherein each gate structure includes a gate dielectric layer formed on the substrate, a work function layer formed on the gate dielectric layer, and a gate electrode layer formed on the work function layer;
forming a sidewall spacer is on each sidewall surface of the gate structure;
removing the cap layer, a top portion of the gate dielectric layer, a top portion of the work function layer, a portion of a top portion of the sidewall spacer to form a trench on each gate structure, wherein a top surface of a remaining portion of the gate dielectric layer, a top surface of a remaining portion of the work function layer, and a top surface of a bottom portion of the sidewall spacer are coplanar with each other; and
forming a substitution layer in the trench, wherein:
a dielectric constant of the substitution layer is smaller than a dielectric constant of the cap layer.

US Pat. No. 10,770,589

FIN FIELD EFFECT TRANSISTOR INCLUDING A SINGLE DIFFUSION BREAK WITH A MULTI-LAYER DUMMY GATE

International Business Ma...

1. A field effect transistor, comprising:a first transistor array comprising a first active gate;
a second transistor array comprising a second active gate; and
a single diffusion break formed between the first transistor array and the second transistor array, wherein the single diffusion break comprises a dummy gate comprising a layer of dielectric material, and an inactive gate structure formed over the layer of dielectric material, wherein a lateral width of the layer of dielectric material is substantially equal to a lateral width of the inactive gate structure,
wherein a sidewall spacer directly contacts and separates the layer of dielectric material from an adjacent epitaxial source drain region.

US Pat. No. 10,770,588

(110) SURFACE ORIENTATION FOR REDUCING FERMI-LEVEL-PINNING BETWEEN HIGH-K DIELECTRIC AND GROUP III-V COMPOUND SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a fin structure extending from a semiconductor substrate, wherein the fin structure has a top surface having a (100) crystallographic orientation and sidewall surfaces having a (110) crystallographic orientation, the sidewall surfaces having the (110) crystallographic orientation extending to a top surface of the semiconductor substrate having a (100) crystallographic orientation;
a gate structure traversing the fin structure, the gate structure traversing a source region and a drain region of the fin structure such that a channel region is defined between the source region and the drain region; and
a hard mask layer disposed in the channel region over the top surface of the fin structure having the (100) crystallographic orientation,
wherein the gate structure includes a gate dielectric, a gate electrode, and a sidewall spacer disposed alongside the gate dielectric and the gate electrode, the gate dielectric being disposed over the hard mask layer and the sidewall surfaces of the fin structure having the (110) crystallographic orientation, and the gate electrode being disposed over the gate dielectric, wherein the sidewall spacer is disposed on and covers a vertical side surface of the hard mask layer, wherein the fin structure includes a III-V semiconductor material.

US Pat. No. 10,770,587

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a fin comprising semiconductor material;
a gate structure on top and side surfaces of a part of the fin, the gate structure comprising a gate electrode and a gate dielectric, the gate electrode comprising metal, the gate dielectric comprising a first portion and a second portion, the first portion at least between the gate electrode and the part of the fin and comprising a high-k dielectric material, the second portion at least between the first portion and the part of the fin and comprising oxygen, and the second portion compositionally different from the first portion;
a source region laterally adjacent to and in contact with the part of the fin, the source region extending under the gate structure and also in contact with the second portion of the gate dielectric, wherein an upper surface of the source region is above a part of the gate dielectric that is between the gate electrode and the part of the fin;
a drain region laterally adjacent to and in contact with the part of the fin, such that the part of the fin is at least partly laterally between the source region and the drain region, the drain region extending under the gate structure and also in contact with the second portion of the gate dielectric, wherein an upper surface of the drain region is above the part of the gate dielectric that is between the gate electrode and the part of the fin; and
a trench isolation structure laterally adjacent to one of the source region or the drain region, wherein a sidewall of the trench isolation structure is at an acute angle with respect to, and in contact with, the one of the source region or the drain region.

US Pat. No. 10,770,586

STRESSING STRUCTURE WITH LOW HYDROGEN CONTENT LAYER OVER NISI SALICIDE

Tower Semiconductor Ltd.,...

1. A method of fabricating a metal-oxide-silicon (MOS) transistor exhibiting enhanced mobility of channel electrons, the method comprising:forming a channel region between a source region and a drain region in a semiconductor substrate such that first and second contact regions of said source region and said drain region are respectively disposed adjacent to an upper surface of the semiconductor substrate;
forming first and second nickel monosilicide (Nisi) structures on said source region and said drain region, respectively, such that said first and second Nisi structures are exposed on said upper surface of the semiconductor substrate;
forming a stressing stack across the source region and the drain region such that said stressing stack generates a tensile stress in said channel region, wherein forming said stressing stack comprises:
forming a first dielectric layer by depositing a first dielectric material having a first hydrogen content over the upper surface of the semiconductor substrate such that respective portions of said first dielectric layer contact said first and second Nisi structures, and such that said first dielectric layer includes a first residual stress that applies a first tensile stress component on said channel region;
forming a second dielectric layer on an upper surface of the first dielectric layer by depositing a second dielectric material using processes parameters that exclude an ultraviolet anneal and produce said second dielectric layer with a second thickness in the range of 500 Angstroms to 2000 Angstroms, with a second hydrogen content and with a second residual stress that applies a second tensile stress component on said channel region,
wherein said second dielectric layer is entirely separated from said first and second Nisi structures by said first dielectric layer,
wherein said first residual stress of said first dielectric layer is lower than said second residual stress of said second dielectric layer such that said first tensile stress component is at least 20 percent lower than said second tensile stress component, and
wherein said first hydrogen content of said first dielectric layer is at least 10 percent lower than said second hydrogen content of said second dielectric layer.

US Pat. No. 10,770,585

SELF-ALIGNED BURIED CONTACT FOR VERTICAL FIELD-EFFECT TRANSISTOR AND METHOD OF PRODUCTION THEREOF

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate;
an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures;
a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and
a buried contact layer between the spacer liner and in a portion of the substrate,
wherein the spacer liner comprises a top surface, a first surface and a second side surface, wherein the top surface of the spacer liner is in direct contact with the ILD, wherein a portion of the first surface of the spacer liner is in direct contact with the ILD, and wherein a portion of the second surface of the spacer liner is in direct contact with the buried contact layer, and
wherein the first, second and third HKMG structures comprise:
a high-k (HK) on sidewall portions of first, second and third fin structures;
a work function metal (WFM) layer over the HK layer;
a first spacer over the HK layer and the WFM layer and on sidewall portions of the first, second and third fin structures; and
a second spacer over the first spacer.

US Pat. No. 10,770,584

DRAIN EXTENDED TRANSISTOR WITH TRENCH GATE

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:a semiconductor substrate with a trench that extends inward from a side of the semiconductor substrate;
a body region under the trench in the semiconductor substrate, the body region including majority carrier dopants of a first type; and
a drain extended transistor, including:
a source region under the trench in the semiconductor substrate adjacent a channel portion of the body region, the source region including majority carrier dopants of a second type,
a drain region spaced from the trench in the semiconductor substrate, the drain region including majority carrier dopants of the second type,
a drift region between the channel portion of the body region and the drain region, the drift region including majority carrier dopants of the second type,
a gate structure, including: a gate dielectric layer in the trench proximate the channel portion of the body region, and a gate electrode on the gate dielectric layer in the trench, andan oxide structure in the trench between a side of the gate structure and the drift region,wherein the drain region is spaced from the gate structure by a first distance;
wherein the semiconductor substrate includes:
a second trench that extends inward from the side of the semiconductor substrate, and
a second body region under the second trench in the semiconductor substrate, the second body region including majority carrier dopants of the first type;
wherein the semiconductor device further comprises a second drain extended transistor, including:
a second source region under the second trench in the semiconductor substrate adjacent a second channel portion of the second body region, the second source region including majority carrier dopants of the second type,
a second drain region spaced from the second trench in the semiconductor substrate, the second drain region including majority carrier dopants of the second type,
a second drift region between the second channel portion of the second body region and the second drain region, the second drift region including majority carrier dopants of the second type,
a second gate structure, including: a second gate dielectric layer in the second trench proximate the second channel portion of the second body region, and a second gate electrode on the second gate dielectric layer in the second trench, and
a second oxide structure in the second trench between a side of the second gate structure and the second drift region;
wherein the second drain region is spaced from the second gate structure by a second distance; and
wherein the first distance is different than the second distance.

US Pat. No. 10,770,583

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A wide band gap semiconductor device comprising:a semiconductor layer having a first surface and a second surface;
a first trench formed on the first surface of the semiconductor layer;
a second trench formed on the first surface of the semiconductor layer;
a first region of a first conductivity type formed at the first surface of the semiconductor layer, the first region forming a part of a side surface of the first trench;
a second region of a second conductivity type formed on a side of the first region facing the second surface of the semiconductor layer, the second region forming a part of the side surface of the first trench;
a third region of the first conductivity type formed on a side of the second region facing the second surface of the semiconductor layer, the third region forming a portion of the bottom surface of the first trench;
an insulating film formed on an inner surface of the first trench; and
a first electrode embedded inside the insulating film in the first trench, wherein
the second region integrally includes a first portion arranged closer to the first surface of the semiconductor layer and a second portion arranged below the first portion, the second portion is projecting from the first portion toward the second surface of the semiconductor layer to a depth below the bottom surface of the first trench, and
the second portion of the second region defines a boundary surface with the third region, the boundary surface being at an incline with respect to the first surface of the semiconductor layer, and
a peak of depth of the second portion is placed between the first trench and the second trench, and a distance from the peak to the first trench is almost same as a distance from the peak to the second trench in plan view.

US Pat. No. 10,770,582

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
a first semiconductor layer that is of the first conductivity type, provided on a front surface of the semiconductor substrate, and has an impurity concentration lower than an impurity concentration of the semiconductor substrate;
a first semiconductor region that is of a second conductivity type and selectively provided in the first semiconductor layer;
a second semiconductor region that is of the second conductivity type and selectively provided at a first surface of the first semiconductor layer, the first surface being opposite a second surface of the first semiconductor layer, the second surface facing toward the semiconductor substrate;
a second semiconductor layer that is of the second conductivity type and provided on the first surface of the first semiconductor layer;
third semiconductor regions that are of the first conductivity type, selectively provided in the second semiconductor layer of the second conductivity type, and have an impurity concentration higher than the impurity concentration of the semiconductor substrate;
a first trench and a second trench that penetrate the third semiconductor regions of the first conductivity type and the second semiconductor layer of the second conductivity type, reach the first semiconductor layer, and have respective bottoms that are in contact with the first semiconductor regions, respectively;
a gate electrode that is provided in the first trench, via a gate insulating film;
a Schottky electrode that is provided in the second trench and that is connected to a source electrode; and
a third semiconductor region that is of the second conductivity type, provided in a side portion of the second trench, and has an impurity concentration higher than the impurity concentration of the second semiconductor layer that is of the second conductivity type.

US Pat. No. 10,770,581

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate containing a semiconductor material having a bandgap that is wider than a bandgap of silicon;
a first semiconductor layer of a first conductivity type and provided on a front surface of the semiconductor substrate, the first semiconductor layer containing the semiconductor material having the bandgap that is wider than the bandgap of silicon;
a second semiconductor layer of a second conductivity type and provided on a first side of the first semiconductor layer, the second semiconductor layer containing the semiconductor material having the bandgap that is wider than the bandgap of silicon, the first side of the first semiconductor layer being opposite a second side of the first semiconductor layer, the second side facing toward the semiconductor substrate;
a first semiconductor region of the first conductivity type and selectively provided in the second semiconductor layer;
a second semiconductor region of the second conductivity type and selectively provided in the second semiconductor layer, the second semiconductor region being in contact with the first semiconductor region along a direction parallel to the front surface of the semiconductor substrate and having an impurity concentration that is higher than an impurity concentration of the second semiconductor layer;
a third semiconductor region of the second conductivity type, the third semiconductor region being a portion of the second semiconductor layer other than the first semiconductor region and the second semiconductor region, and disposed closer to the semiconductor substrate than are the first semiconductor region and the second semiconductor region;
a trench penetrating the first semiconductor region, the second semiconductor region, and the third semiconductor region, at a boundary between the first semiconductor region and the second semiconductor region, the trench reaching the first semiconductor layer;
a gate insulating film provided along a bottom and a first side wall of the trench;
a gate electrode provided at a surface of the first side wall of the trench, via the gate insulating film, and opposing a portion of the third semiconductor region between the first semiconductor region and the first semiconductor layer;
an electrode layer provided along a second side wall of the trench and at the second side wall of the trench, forming a Schottky contact or a heterocontact with the second semiconductor region, the third semiconductor region, and the first semiconductor layer;
a fourth semiconductor region of the second conductivity type and provided in the first semiconductor layer so as to be separated from the third semiconductor region and encompass a corner formed by the bottom and the second side wall of the trench;
a first electrode electrically connected to the first semiconductor region, the second semiconductor region, the fourth semiconductor region, and the electrode layer; and
a second electrode provided at a rear surface of the semiconductor substrate.

US Pat. No. 10,770,580

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
a trench provided on a top surface of the semiconductor substrate;
a gate insulating film covering an inner surface of the trench;
a trench gate electrode adjacent to the gate insulating film and accommodated in the trench; and
a lead-out electrode provided on the top surface so as to extend along the top surface, the lead-out electrode being electrically connected to the trench gate electrode, wherein:
when the top surface of the semiconductor substrate is planarly viewed, the trench has a linear portion in which a trench side surface extends linearly, and an end portion in which the trench side surface curves, the end portion being positioned on a longitudinal end side of the linear portion;
when the top surface of the semiconductor substrate as planarly viewed from above, the lead-out electrode covers the end portion and reaches the linear portion; and
when the top surface of the semiconductor substrate is planarly viewed from above, in an adjacent range in the end portion, the adjacent range being adjacent to a boundary line positioned between the top surface and the trench side surface, the top surface and the trench side surface are covered with the gate insulating film and an interlayer insulating film.

US Pat. No. 10,770,579

SIC-MOSFET AND METHOD OF MANUFACTURING THE SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. A metal-oxide-semiconductor field-effect transistor using silicon carbide as a semiconductor material (SiC-MOSFET), comprising:a silicon carbide (SiC) substrate; and
a gate electrode located within a trench defined on the SiC substrate,
wherein the SiC substrate comprises:
an n-type drain region;
an n-type drift region located on the n-type drain region, a concentration of n-type impurities in the n-type drift region being lower than a concentration of the n-type impurities in the n-type drain region;
a p-type body region located on the n-type drift region;
a p-type contact region located on the p-type body region, the p-type contact region appearing on a surface of the SiC substrate and a concentration of p-type impurities in the p-type contact region being higher than a concentration of the p-type impurities in the p-type body region; and
an n-type source region located on the p-type body region, the n-type source region appearing on the surface of the SiC substrate and a concentration of the n-type impurities in the n-type source region being higher than the concentration of the n-type impurities in the n-type drift region,
the trench extends from the surface of the SiC substrate to the n-type drift region through the p-type body region,
the gate electrode faces the n-type source region, the p-type body region and the n-type drift region via a gate insulating film,
the p-type contact region is a layer formed by epitaxial growth and includes a portion located between the n-type source region and the p-type body region at a location apart from the trench,
the p-type body region comprises a first body region and a second body region,
a concentration of the p-type impurities in the second body region is lower than a concentration of the p-type impurities in a portion of the first body region that is in direct contact with the p-type contact region,
the second body region is in direct contact with both the n-type source region and the p-type contact region, and appears on a side surface of the trench,
the portion of the p-type contact region located between the n-type source region and the p-type body region is in direct contact with each of the first body region, the second body region and the n-type source region, and
the second body region is separated from the n-type drift region via the first body region.

US Pat. No. 10,770,578

SEMICONDUCTOR DEVICES AND METHODS FOR FORMING A SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor substrate comprising a main surface, a back surface, an outer edge side extending between the main and back surfaces, and a second conductivity type drift region disposed between the main and rear surfaces;
a cell region and an edge termination region disposed in the semiconductor substrate, the cell region being laterally separated from the outer edge side by the edge termination region;
a switchable electrical structure disposed in the cell region, the switchable electrical structure comprising a second conductivity type source region disposed at the main surface, a first conductivity type body region, a second conductivity type drain region disposed at the back surface, a conductive gate electrode that is configured to control a conductive connection between the source and drain regions, and a conductive source electrode disposed at the main surface and connected to the source region;
a first doping region of the first conductivity type that is disposed in the edge termination region; and
a feedback path connected between the source electrode and the first doping region,
wherein the feedback path is configured to permit charge carriers to flow between the source electrode and the first doping region during a transition from an off-state to an on-state of the switchable electrical structure and is configured to block a flow of charge carriers between the source electrode and the first doping region during at least part of a transition from the on-state to the off-state of the switchable electrical structure,
wherein the feedback path comprises a p-n junction diode connected between the source electrode and the first doping region.

US Pat. No. 10,770,577

RECTIFIER AND ROTATING ELECTRIC MACHINE INCLUDING RECTIFIER

DENSO CORPORATION, Kariy...

1. A rectifier for a rotating electric machine, the rotating electric machine comprising a rotating shaft, a rotor fixed on the rotating shaft to rotate together with the rotating shaft, and a stator configured to generate multi-phase alternating current therein with rotation of the rotor,the rectifier having a rectification circuit formed therein, the rectification circuit being configured as a multi-phase bridge circuit, which has an upper arm and a lower arm, to rectify the multi-phase alternating current generated in the stator into direct current,
the rectifier comprising:
a plurality of upper-arm semiconductor switching elements for respective phases included in the upper arm of the rectification circuit;
a plurality of upper-arm protection diodes for respective phases included in the upper arm of the rectification circuit, each of the upper-arm protection diodes being electrically connected in parallel with one of the upper-arm semiconductor switching elements which is of the same phase as the upper-arm protection diode;
a plurality of lower-arm semiconductor switching elements for respective phases included in the lower arm of the rectification circuit; and
a plurality of lower-arm protection diodes for respective phases included in the lower arm of the rectification circuit, each of the lower-arm protection diodes being electrically connected in parallel with one of the lower-arm semiconductor switching elements which is of the same phase as the lower-arm protection diode,
wherein each of the upper-arm and lower-arm protection diodes is configured to have, when a reverse voltage higher than a breakdown voltage of the protection diode is applied to the protection diode, an operating resistance that is higher than three times an operating resistance of any of the upper-arm and lower-arm semiconductor switching elements.

US Pat. No. 10,770,576

POWER MOSFET DEVICE AND MANUFACTURING PROCESS THEREOF

STMicroelectronics S.r.l....

1. A MOSFET device comprising:a body of semiconductor material of a first conductivity type, having a first main surface and a second main surface;
a body region, of a second conductivity type, extending within the body from the first main surface;
a source region of the first conductivity type, extending within the body region from the first main surface;
a conductive gate region extending on the first main surface of the body;
a source pad extending on the first main surface and electrically coupled to the source region;
a first gate pad extending on the first main surface, alongside the source pad, and electrically coupled to the gate region;
a drain pad extending on the second main surface and electrically coupled to the body;
a second gate pad extending on the second main surface, alongside the drain pad; and
a conductive via extending through the body and electrically coupling the gate region to the second gate pad, wherein the first main surface has a generally rectangular shape having a first corner and a second corner and a first area and a second area adjacent to the first corner and to the second corner, respectively, wherein the first gate pad extends over the first area of the first main surface and the second gate pad extends in an area of the second main surface vertically aligned to the second area of the first main surface, the MOSFET device comprising a gate connection structure extending on one of the first main surface and the second main surface, and electrically coupling one of the first gate pad and the second gate pad to the conductive via.

US Pat. No. 10,770,575

VERTICAL GROUP III-N DEVICES AND THEIR METHODS OF FABRICATION

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a doped buffer layer above a substrate;
a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface;
a drain region disposed adjacent to the doped buffer layer;
an insulator layer disposed on the drain region;
a polarization charge inducing layer disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material, wherein the first portion has a thickness and the second portion has a thickness greater than the thickness of the first portion;
a gate structure disposed on the first portion of the polarization charge inducing layer; and
a source region disposed on the second portion of the polarization charge inducing layer.

US Pat. No. 10,770,574

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

DYNAX SEMICONDUCTOR, INC....

1. A semiconductor device, wherein the semiconductor device comprises an active region and an inactive region located outside of the active region, the semiconductor device comprising:a substrate;
a semiconductor layer formed at a side of the substrate, the semiconductor layer comprising a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region;
a source, a drain, and a gate formed in the active region and located at a side of the semiconductor layer away from the substrate, the second semiconductor layer located in the inactive region close to at least one end of the source; and
a via hole penetrated through the substrate, at least a part of the first semiconductor layer, and at least a part of the second semiconductor layer.

US Pat. No. 10,770,573

APPARATUS, SYSTEM AND METHOD OF AN ELECTROSTATICALLY FORMED NANOWIRE (EFN)

TOWER SEMICONDUCTOR LTD.,...

1. An Electrostatically Formed Nanowire (EFN) comprising:a source region;
at least one drain region;
a wire region configured to drive a current between the source and drain regions via a conductive channel;
a first lateral-gate area extending along a first surface of the wire region between said source and drain regions;
a second lateral-gate area extending along a second surface of the wire region between said source and drain regions; and
a sensing area in an opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

US Pat. No. 10,770,572

LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR

CSMC TECHNOLOGIES FAB2 CO...

1. A lateral insulated-gate bipolar transistor, comprising:a P-type substrate;
a cathode terminal located on the substrate;
an anode terminal located on the substrate, the anode terminal comprising an N-type buffer region located on the substrate, a P well located in the N-type buffer region, an N+ region located in the P well, a trench located above the N+ region and partially surrounded by the P well, a polysilicon located in the trench, P+ junctions located at both sides of the trench, and N+ junctions located at both sides of the P+ junction;
a drift region located between the anode terminal and the cathode terminal; and
a gate located between the anode terminal and the cathode terminal;
wherein the trench is a structure gradually increased in width from bottom to top to form a slope and having a narrow bottom and a wide top.

US Pat. No. 10,770,571

FINFET WITH DUMMY FINS AND METHODS OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

14. A semiconductor structure comprising:a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, wherein the semiconductor fin includes a semiconductor layer;
a hybrid fin protruding from the substrate and oriented parallel to the semiconductor fin, wherein the hybrid fin includes the semiconductor layer and a first dielectric layer disposed over the semiconductor layer;
a first dielectric fin protruding from the substrate and oriented parallel to the semiconductor fin, wherein the first dielectric fin including the first dielectric layer;
a second dielectric fin protruding from the substrate and oriented parallel to the semiconductor fin, wherein the second dielectric fin includes a second dielectric layer disposed over the first dielectric layer, wherein the second dielectric layer is different from the first dielectric layer in composition, and wherein the first dielectric fin is free of the second dielectric layer; and
conductive gate stacks disposed over the semiconductor fins, the first dielectric fin, and the second dielectric fin and oriented lengthwise along a second direction normal to the first direction.

US Pat. No. 10,770,570

FINFET DEVICE AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A fin field effect transistor (finFET) device comprising:a fin extending upwards from a semiconductor substrate;
a gate stack over and along sidewalls of a channel region of the fin;
a source/drain region adjacent the fin;
a gate spacer disposed along a sidewall of the gate stack;
a first carbon-doped region disposed along a bottom surface and a sidewall of the source/drain region, wherein the first carbon-doped region is between the sidewall of the source/drain region and the channel region along a line parallel to a major surface of the semiconductor substrate; and
a second carbon-doped region under the gate spacer and between the first carbon-doped region and the channel region, wherein the first carbon-doped region and the second carbon-doped region have different concentrations of carbon.

US Pat. No. 10,770,569

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A transistor, comprising:a semiconductive fin comprising a channel portion;
a gate stack over the channel portion of the semiconductive fin;
source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, wherein the source structure has a curved top; and
a sidewall structure extending substantially along sidewalls of a body portion of the source structure, wherein the source structure has a top portion protruding over a top of the sidewall structure.

US Pat. No. 10,770,568

METHOD TO REMOVE III-V MATERIALS IN HIGH ASPECT RATIO STRUCTURES

Applied Materials, Inc., ...

1. A fin structure processing method, comprising:removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate;
performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and
performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation, wherein a temperature of the substrate is between about 300° C. and about 800° C., and a pressure of the substrate processing environment is between about 1 Torr and about 100 Torr during at least a portion of the etching operation.

US Pat. No. 10,770,567

EMBEDDED ENDPOINT FIN REVEAL

International Business Ma...

1. A semiconductor structure comprising:a plurality of fins formed from a substrate having a top surface, wherein the substrate has recessed portions in the top surface and along a portion of each sidewall of the plurality of fins;
at least one liner segment disposed on the recessed portions in the top surface of the substrate and along a portion of each sidewall of the plurality of fins;
a first dielectric layer in contact with a non-recessed portion of the top surface of the substrate and bounded by the liner segment; and
a second dielectric layer disposed within an interior of the liner segment.

US Pat. No. 10,770,566

UNIQUE GATE CAP AND GATE CAP SPACER STRUCTURES FOR DEVICES ON INTEGRATED CIRCUIT PRODUCTS

GLOBALFOUNDRIES Inc., Gr...

1. A device, comprising:an active layer;
a gate structure positioned above a channel region of the active layer;
a first sidewall spacer positioned adjacent the gate structure;
a gate cap layer positioned above the gate structure, the gate cap layer comprising an insulating material; and
an upper spacer contacting sidewall surfaces of the gate cap layer, a portion of an upper surface of the gate structure and an inner surface of the first sidewall spacer.

US Pat. No. 10,770,565

MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A memory structure, comprising:a substrate;
a first gate structure comprising:
a first gate disposed on the substrate; and
a charge storage layer disposed between the first gate and the substrate;
a second gate structure disposed on the substrate at one side of the first gate structure, wherein the second gate structure comprises a second gate, and a height of the first gate is higher than a height of the second gate;
a first spacer and a second spacer respectively disposed on one sidewall and the other sidewall of the first gate structure, wherein the first spacer is located between the first gate structure and the second gate structure; and
a third spacer disposed on a sidewall of the first spacer and covering a portion of a top surface of the second gate, wherein
a top surface of the charge storage layer is lower than the entire top surface of the second gate, and
the first spacer covers a sidewall of the charge storage layer.

US Pat. No. 10,770,564

MOS COMPONENT, ELECTRIC CIRCUIT, AND BATTERY UNIT FOR A MOTOR VEHICLE

Robert Bosch GmbH, Stutt...

1. A MOS component, comprising:a gate element;
a channel area; and
an electrically insulating layer that includes at least three individual layers situated between the gate element and the channel area, wherein:
a first individual layer of the at least three individual layers is adjacent to the gate element and is made of an electrically insulating material,
a second individual layer of the at least three individual layers abuts neither the gate element nor the channel area and is a storage layer suitable for permanently storing charges, and
a third individual layer of the at least three individual layers is adjacent to the channel area and is made of an electrically insulating material, and
an entirety of the at least three individual layers situated between the channel area and the second individual layer has an equivalent oxide thickness which is greater than an entirety of an equivalent oxide thicknesses of the at least three individual layers situated between the second individual layer and the gate area.

US Pat. No. 10,770,563

GATE STRUCTURE AND PATTERNING METHOD FOR MULTIPLE THRESHOLD VOLTAGES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and
a plurality of gate structures comprising:
an interfacial layer (IL) disposed over the plurality of channel regions;
a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region;
a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and
a third high-k dielectric layer disposed over the plurality of channel regions, wherein the first, second and third high-k dielectric layers are different from one another.

US Pat. No. 10,770,562

INTERLAYER DIELECTRIC REPLACEMENT TECHNIQUES WITH PROTECTION FOR SOURCE/DRAIN CONTACTS

International Business Ma...

1. A method for fabricating a semiconductor IC device, comprising:forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and source/drain layers;
forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device;
performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with source/drain layers of the field-effect transistor device;
depositing a semiconductor layer on the sacrificial interlayer dielectric layer and the metallic source/drain contacts;
performing a thermal anneal process to induce a reaction between the semiconductor layer and the metallic source-drain contacts to form metal-semiconductor alloy capping layers in upper surface regions of the metallic source/drain contacts;
removing unreacted portions of the semiconductor layer remaining after the thermal anneal process;
performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the metal-semiconductor alloy capping layers such that the metal-semiconductor alloy capping layers protect the metallic source/drain contacts from etch damage during the etch process; and
forming a low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer.

US Pat. No. 10,770,561

METHODS OF FABRICATING DUAL THRESHOLD VOLTAGE DEVICES

SPIN MEMORY, INC., Fremo...

1. An annular device, comprising:a cylindrical pillar, comprising:
a vertical cylindrical core; and
a plurality of layers that surround the vertical cylindrical core in succession, the plurality of layers including a first layer, a second layer, a third layer, and a fourth layer,
wherein:
the core, the first layer, and the second layer correspond to a first transistor including a first input terminal, wherein the first transistor is configured to have a first threshold voltage having a first magnitude; and
the second layer, the third layer, and the fourth layer correspond to a second transistor including a second input terminal, wherein the second transistor is configured to have a second threshold voltage having a second magnitude distinct from the first magnitude.

US Pat. No. 10,770,560

SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate having a first region and a second region horizontally separate from the first region;
a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and
a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first; horizontal direction equal to or narrower than a width of the first gate line in the first horizontal direction,
wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first horizontal direction,
wherein the first gate line further comprises a first conductive barrier layer on the first upper work function layer, and
wherein an uppermost end of the first conductive barrier layer is at a vertical level higher than the uppermost end of the first upper work function layer.

US Pat. No. 10,770,559

GATE STRUCTURE AND METHODS OF FORMING METAL GATE ISOLATION

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:removing a dummy gate structure disposed over a first fin and a second fin to form a gate trench;
forming a high-k dielectric layer in the gate trench;
forming a hard mask layer over the high-k dielectric layer to fill the gate trench;
forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through a bottom surface of the hard mask layer;
removing the hard mask layer to expose the sidewalls of the isolation feature;
forming a work function metal layer over the high-k dielectric layer, such that the work function metal layer is formed over the sidewalls and a top surface of the isolation feature;
forming a bulk conductive layer over the work function metal layer; and
removing a portion of the work function metal layer formed over the top surface of the isolation feature, such that a top surface of the work function metal layer is substantially coplanar with the top surface of the isolation feature.

US Pat. No. 10,770,558

METHOD FOR AUTO-ALIGNED MANUFACTURING OF A VDMOS TRANSISTOR, AND AUTO-ALIGNED VDMOS TRANSISTOR

STMICROELECTRONICS S.r.l....

1. A method, comprising:forming a body region in a semiconductor body having a first conductivity type, the semiconductor body having opposite first and second sides and an axis of symmetry transverse to the first and second sides, the body region having a second conductivity type at the first side;
forming a source region having the first conductivity type within the body region, the source region extending into the body region from the first side;
forming a drain electrode on the second side;
forming a gate electrode in the semiconductor body at the first side, the gate electrode laterally facing the source region and symmetrical with respect to the axis of symmetry;
forming one or more structural regions laterally with respect to the gate electrode, the one or more structural regions being symmetrical with respect to the axis of symmetry and having a surface;
forming a step between the surface of the one or more structural regions and the first side of the semiconductor body, the surface of the one or more structural regions being spaced farther apart from the second side of the semiconductor body than the first side of the semiconductor body is spaced apart from the second side of the semiconductor body;
forming a structural layer on the one or more structural regions, the step and the first side of the semiconductor body;
forming at the step one or more spacers by performing an anisotropic etching of the structural layer with a main etching direction parallel to the axis of symmetry, the one or more spacers being symmetrical with respect to the axis of symmetry and surrounding an exposed portion of the first side that includes the axis of symmetry; and
forming a source electrode in electrical contact with the source region at the exposed portion of the first side.

US Pat. No. 10,770,557

TUNABLE BREAKDOWN VOLTAGE RF FET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method, comprising:forming a first line and a second line on an underlying gate dielectric material on an underlying substrate, the second line having a width tuned to a breakdown voltage, the first line and the underlying gate dielectric material forming a gate structure;
depositing sidewall material on the first line, the second line and on an upper surface of the underlying gate dielectric material including between the first line and the second line;
forming tapered sidewall spacers on sidewalls of the first line and the second line, and forming non-tapered sidewall spacers opposing the tapered sidewall spacers on opposing sides of the first line and second line by removing the sidewall material on horizontal surfaces of the first line, the second line and portions of the upper surface of the underlying gate dielectric material;
forming source and drain regions adjacent to the outer edges of the first line and the second line by an implantation process through the underlying gate dielectric material adjacent to the non-tapered sidewall spacers;
removing the second line to form an opening between a tapered sidewall spacer of the second line a non-tapered sidewall spacer of the second line, to expose the underlying gate dielectric material;
blanket depositing a blocking material on the exposed underlying gate dielectric material within the opening and over the source and drain regions, and over the tapered sidewall spacers and the non-tapered sidewall spacers, wherein the blocking material fills in the taper of the tapered sidewall spacers;
removing the blocking material and the dielectric material from over the source and drain regions by removal of the first line between a tapered sidewall spacer of the first line and a non-tapered sidewall spacer of the first line, while leaving the blocking material and the dielectric material within the second opening between a tapered sidewall spacer of the second line and a non-tapered sidewall spacer of the second line; and
forming a silicide on the first line;
forming silicide regions in contact with the source and drain regions; and
forming contacts to the gate structure and the source and drain regions.

US Pat. No. 10,770,556

FLUORINATED GRAPHENE PASSIVATED ALGAN/GAN-BASED HEMT DEVICE AND MANUFACTURING METHOD

SHANGHAI INSTITUTE OF MIC...

1. An AlGaN/GaN HEMT based on fluorinated graphene passivation, characterized in that the HEMT comprises:a substrate;
a GaN layer located above the substrate;
an AlGaN layer bonded to the GaN layer, a two-dimensional electron gas surface formed by an interface between the AlGaN layer and the GaN layer;
a source and a drain formed at two ends of the AlGaN layer;
an insulated graphene passivation layer bonded to a surface of the AlGaN layer, wherein the insulated graphene passivation layer is fluorinated;
a gate dielectric layer bonded to a surface of the insulated graphene passivation layer; and
a gate metal layer bonded to a surface of the gate dielectric layer.

US Pat. No. 10,770,555

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate structure disposed on the semiconductor substrate, wherein the gate structure comprises:
a gate dielectric layer; and
a gate electrode formed on the gate dielectric layer, wherein the gate dielectric layer comprises nitrogen ions so that a lower portion of the gate dielectric layer comprises positive charges;
a sidewall spacer disposed on sidewalls of the gate structure;
a lightly doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure;
a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer;
a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly doped source/drain region, wherein the halo implant region is spaced apart from the source/drain region by a portion of the semiconductor substrate; and
a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly doped source/drain region and the halo implant region, the counter-doping region extending into the semiconductor substrate directly below the gate structure, wherein the entire counter-doping region is directly below the gate structure and the sidewall spacer, and wherein a dopant concentration of the counter-doping region is lower than a dopant concentration of the halo implant region, and the counter-doping region has a P-type impurity and a nitrogen ion.

US Pat. No. 10,770,554

NITRIDE SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE

SCIOCS COMPANY LIMITED, ...

1. A nitride semiconductor substrate, comprising:a substrate configured as an n-type semiconductor substrate; and
a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons,
wherein a concentration of the donors in the drift layer is 5.0×1016/cm3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and
difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually increased from a substrate side toward a surface side of the drift layer.

US Pat. No. 10,770,553

LAYERED STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING LAYERED STRUCTURE, AND SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR DEVICE

FLOSFIA INC., Kyoto (JP)...

1. A layered structure, comprising:a first semiconductor layer comprising as a major component an ?-phase oxide semiconductor crystal; and
a second semiconductor layer positioned on the first semiconductor layer and comprising as a major component an oxide semiconductor crystal with a tetragonal crystal structure.

US Pat. No. 10,770,552

EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENTS, SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD FOR EPITAXIAL SUBSTRATES FOR SEMICONDUCTOR ELEMENTS

NGK INSULATORS, LTD., Na...

1. A method of manufacturing an epitaxial substrate for semiconductor elements, comprising:a) a preparation step of preparing a first region consisting of a semi-insulating free-standing substrate formed of GaN being doped with Zn;
b) a buffer layer formation step of forming a buffer layer formed of group 13 nitride adjacent to said free-standing substrate;
c) a channel layer formation step of forming a channel layer formed of group 13 nitride adjacent to said buffer layer; and
d) a barrier layer formation step of forming a barrier layer formed of group 13 nitride in a position opposite to said buffer layer with said channel layer therebetween, wherein
a second region containing Si at a concentration of 1×1017cm?3 or more is formed through taking Si in said free-standing substrate, which has been prepared in said preparation step, from outside before said buffer layer formation step is completed, in part of a first region consisting of said free-standing substrate and said buffer layer, and
in said buffer layer formation step, Zn is diffused from said free-standing substrate, thereby forming said buffer layer in which a minimum value of a concentration of Zn is 1×1017cm?3 in said second region.