US Pat. No. 10,658,043

METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME

Samsung Electronics Co., ...

1. A method of operating a nonvolatile memory device, comprising:performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks; then
performing a soft program operation on the at least one victim sub-block; and then
performing a data erase operation on the selected sub-block within the plurality of sub-blocks.

US Pat. No. 10,658,042

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING DATA OF PARTIAL PAGE AND OVERWRITING PARTIAL PAGE WITH PREDETERMINED DATA

Sony Corporation, Tokyo ...

1. A semiconductor memory device, comprising:a block including a plurality of pages;
a controller configured to control writing, erasing, and reading of data, wherein
each of the pages includes a plurality of memory cells each being changeable to one of four or eight states, and
in a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage; and
a plurality of word lines and a plurality of bit lines, wherein
the memory cells are disposed at respective intersections of the plurality of word lines and the plurality of bit lines, and
data of a plurality of pages is stored on each one of the plurality of word lines,
wherein
the plurality of pages on each one of the word lines include first to third pages, and
the controller is configured to
overwrite all of the memory cells in the first page or all of the memory cells in the second page with data of “1” as the predetermined data in a case where the first page or the second page as the partial page is erased, and
overwrite all of the memory cells in the third page with data of “0” as the predetermined data in a case where the third page as the partial page is erased.

US Pat. No. 10,658,041

APPARATUS AND METHODS FOR SERIALIZING DATA OUTPUT

Micron Technology, Inc., ...

1. An apparatus, comprising:a first multiplexer comprising a plurality of input signal lines, a first output signal line and a second output signal line, wherein each input signal line of the plurality of input signal lines is configured to receive a data value to be output from the apparatus, and wherein the first multiplexer is configured to provide data values representative of the data values for a first subset of input signal lines of the plurality of input signal lines to the first output signal line and to provide data values representative of the data values for a second subset of input signal lines of the plurality of input signal lines to the second output signal line;
a second multiplexer comprising a first input signal line, a second input signal line and an output signal line, wherein the first input signal line of the second multiplexer is configured to receive the data values from the first output signal line of the first multiplexer, wherein the second input signal line of the second multiplexer is configured to receive the data values from the second output signal line of the first multiplexer, and wherein the second multiplexer is configured to selectively provide data values representative of the data values from its first input signal line or its second input signal line to its output signal line; and
an output node configured to receive data values from the output signal line of the second multiplexer;
wherein the first multiplexer comprises a first combinational logic connected between its first output signal line and the first subset of input signal lines, and a second combinational logic connected between its second output signal line and the second subset of input signal lines;
wherein a first level of the first combinational logic comprises a first plurality of NAND gates that are each configured to be responsive to a respective input data value of the first subset of input signal lines and a corresponding respective clock signal of a first subset of clock signals of a plurality of clock signals; and
wherein a first level of the second combinational logic comprises a second plurality of NAND gates that are each configured to be responsive to a respective input data value of the second subset of input signal lines and a corresponding respective clock signal of a second subset of clock signals of the plurality of clock signals.

US Pat. No. 10,658,040

NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE

Samsung Electronics Co., ...

1. A method for operating a storage device comprising a nonvolatile memory device and a controller, the method comprising:transmitting, by the controller, a command, first page data, second page data, and a confirm command to the nonvolatile memory device; and
after receiving the first page data, by the nonvolatile memory device, applying a first program pulse to memory cells of the nonvolatile memory device based on the first page data while receiving the second page data, wherein:
the first page data and the second page data are to be programmed to the memory cells during a single program operation for the memory cells responsive to the command, and
the memory cells are to be programmed to two or more different program states higher than an erase state in threshold voltages.

US Pat. No. 10,658,039

NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING A READ OPERATION

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a first transistor;
a second transistor;
a plurality of memory cells electrically connected in series between the first transistor and the second transistor;
a source line electrically connected to the first transistor;
a bit line electrically connected to the second transistor;
a plurality of word lines electrically connected to gates of the memory cells, respectively;
a sense amplifier including
a first node,
a third transistor having a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor having a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor having a gate electrically connected to the first node,
a sixth transistor having a first end electrically connected to a first end of the fifth transistor,
a seventh transistor having a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor, and
a controller configured to perform a read operation including a first period, a second period after the first period, a third period after the second period, and a fourth period after the third period, and
at least during the first to third periods, a first voltage being applied to one of the word lines, and a second voltage higher than the first voltage being applied to another one of the word lines,
during the first period, a third voltage being applied to a gate of the fourth transistor, and a fourth voltage higher than the third voltage being applied to a gate of the third transistor,
during the second period, a fifth voltage being applied to a gate of the sixth transistor to thereby turn on the sixth transistor,
during the third period, a sixth voltage being applied to the gate of the fourth transistor, and a seventh voltage higher than the sixth voltage being applied to the gate of the third transistor,
during the fourth period, an eighth voltage being applied to a gate of the seventh transistor to thereby turn on the seventh transistor.

US Pat. No. 10,658,038

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. An operation method for a semiconductor memory device,the semiconductor memory device comprising:
a first electrode;
a second electrode; and
a memory cell including a resistance change film provided between the first electrode and the second electrode;
the operation method including:
applying a first voltage of a first polarity to the first electrode during a first period;
applying a second voltage of the first polarity to the first electrode and applying a third voltage of a second polarity opposite from the first polarity to the second electrode at the same time after the first period;
applying the second voltage of the first polarity to the first electrode and applying a voltage of the second polarity smaller than the third voltage to the second electrode during a second period after applying the second voltage to the first electrode and applying the third voltage to the second electrode; and
applying the second voltage of the first polarity to the first electrode without applying a voltage to the second electrode during a third period after the second period.

US Pat. No. 10,658,037

REDUCED CURRENT MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A memory device, comprising:a local bit line electrically coupled to a plurality of memory cells; and
a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively;
wherein the first path is active and the second path is in an off state in at least one of a set operation or a forming operation; and
wherein the second path is active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

US Pat. No. 10,658,036

MEMORY STORAGE APPARATUS AND FORMING METHOD OF RESISTIVE MEMORY DEVICE

Winbond Electronics Corp....

1. A forming method of a resistive memory device, comprising:conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state, and measuring a first current of the resistive memory device after applying the forming voltage;
performing a thermal step on the resistive memory device after measuring the first current, and measuring a second current of the resistive memory device after performing the thermal step; and
comparing the second current to the first current, and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current,
wherein an energy of the second voltage signal is greater than an energy of the first voltage signal.

US Pat. No. 10,658,035

APPARATUSES AND METHODS OF READING MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus comprising:a memory array comprising a memory cell;
a memory controller coupled to the memory array and configured to:
determine that a first electrical response is within an overlapped electrical response region; and
determine a second electrical response of the memory cell;
a ramp generator coupled to the memory controller, wherein the ramp generator is configured to ramp a bias on the memory cell after the determination that the first electrical response is within the overlapped electrical response region; and
a comparator configured to determine a state of the memory cell based at least in part on a comparison between the first electrical response and the second electrical response.

US Pat. No. 10,658,034

DEDICATED READ VOLTAGES FOR DATA STRUCTURES

Micron Technology, Inc., ...

1. A method, comprising:reading a first data structure of an apparatus with a first read voltage dedicated to the first data structure and based on a temperature of the apparatus;
reading a second data structure of the apparatus that stores a larger quantity of data than the first data structure with a second read voltage that is dedicated to the second data structure and that is based on the temperature of the apparatus;
reading the first data structure with a third read voltage that is based on the temperature of the apparatus in response to a quantity of errors in reading the first data structure with the first read voltage being greater than or equal to a first threshold quantity; and
reading the second data structure with the third read voltage in response to a quantity of errors in reading the second data structure with the second read voltage being greater than or equal to a second threshold quantity.

US Pat. No. 10,658,033

NON-VOLATILE MEMORY CELL UTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR

CROSSBAR, INC., Santa Cl...

1. A method for operating a device including a memory circuit comprising a transistor and a volatile selector device comprising a first electrode and a second electrode, wherein the first electrode of the selector device is coupled to a gate of the transistor, and the volatile selector device is characterized by a low resistance state in response to a threshold voltage greater than zero applied across the first electrode and the second electrode and is characterized by a high resistance state in response to a voltage of smaller magnitude than the threshold voltage, and greater than zero, applied across the first electrode and the second electrode, the method comprising:applying a first voltage to the memory circuit to thereby cause the selector device to enter into the low resistance state and to thereby induce at least a first charge upon the gate of the transistor, wherein a magnitude of the first charge is in response to a magnitude of the first voltage; and
removing the first voltage from the memory circuit to thereby cause the selector device to enter into the high resistance state and to thereby trap the first charge upon the gate of the transistor;
wherein the transistor enters a first state in response to the first charge trapped upon the gate of the transistor; and
wherein the transistor is characterized by a first source to drain resistance in response to the transistor being in the first state.

US Pat. No. 10,658,032

PHASE-CHANGE MEMORY DEVICE WITH DRIVE CIRCUIT

STMICROELECTRONICS S.R.L....

1. A memory device comprising:an array of phase-change material (PCM) memory cells;
a word line coupled to the array of PCM memory cells;
a low voltage circuit comprising an output coupled to the word line;
a high voltage circuit comprising an output coupled to the word line, wherein the low voltage circuit and the high voltage circuit are formed on the same semiconductor substrate, wherein the low voltage circuit comprises a first silicon-on-insulator transistor comprising a first gate dielectric and the high voltage circuit comprises a second silicon-on-insulator transistor comprising a second gate dielectric, wherein the second gate dielectric is thicker than the first gate dielectric; and
a level-shifter circuit comprising a first output and a second output, the first output being coupled to the low voltage circuit.

US Pat. No. 10,658,031

SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL PAIRS DEFINING DATA BASED ON THRESHOLD VOLTAGES

Renesas Electronics Corpo...

1. A semiconductor memory device comprising a plurality of memory cells,wherein the memory cells have a plurality of memory cell pairs, each having a first memory cell and a second memory cell,
wherein the first memory cell is configured so as to set a first threshold voltage,
wherein the second memory cell is configured so as to set second to fourth threshold voltages, and
wherein data stored in the memory cell pairs is defined using a difference between the second threshold voltage and the first threshold voltage, a difference between the third threshold voltage and the first threshold voltage, and a difference between the fourth threshold voltage and the first threshold voltage.

US Pat. No. 10,658,030

SYNAPTIC CROSSBAR MEMORY ARRAY

International Business Ma...

1. A method of forming an Integrated Circuit (IC) chip, said method comprising:forming a plurality of transistors on a surface of a semiconductor wafer;
forming a connective layer above said plurality of transistors;
forming a bottom electrode layer on said connective layer, said bottom electrode layer including one or more bottom electrode lines of a first metal and connected to ones said plurality of transistors through said connective layer;
forming a one or more amorphous semiconductor synapses on said one or more bottom electrode lines;
forming an upper electrode layer above said one or more amorphous semiconductor synapses, said upper electrode layer including one or more upper electrode lines of a second metal oriented orthogonally to said one or more bottom electrode lines and connected to others of said plurality of transistors, each amorphous semiconductor synapse being between a bottom electrode line and an upper electrode line, said second metal being different than the first and one of said first metal and said second metal being a refractory metal; and
completing chip fabrication.

US Pat. No. 10,658,029

HIGH BANDWIDTH DOUBLE-PUMPED MEMORY

QUALCOMM Incorporated, S...

1. A method for performing memory read operations, comprising:precharging a plurality of memory columns during a precharging phase of a read access cycle;
sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle; and
sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

US Pat. No. 10,658,028

SEMICONDUCTOR STORAGE DEVICE INCLUDING MEMORY CELLS, WORD DRIVER, DUMMY WORD DRIVER

RENESAS ELECTRONICS CORPO...

1. A semiconductor storage device comprising:a memory cell formed on a semiconductor substrate;
a word line connected to the memory cell and formed in a first metal interconnection layer located over the semiconductor substrate;
a dummy word line formed in a second metal interconnection layer located over the semiconductor substrate and adjacent to the first metal interconnection layer;
a word driver circuit including a first PMOS (P-type Metal-Oxide-Semiconductor) transistor and a first NMOS (N-type Metal-Oxide-Semiconductor) transistor connected in series between a first power supply voltage and a first ground voltage lower than the first power supply voltage, and supplying the first power supply voltage to the word line corresponding to an address signal;
a dummy word driver circuit including a second PMOS transistor and a second NMOS transistor connected in series between a second power supply voltage and a second ground voltage lower than the second power supply voltage, and supplying the second power supply voltage to the dummy word line;
a first inverter which receives a control signal and outputs an inversion signal of the control signal as a first signal;
a second inverter which receives the first signal and outputs an inversion signal of the first signal as a second signal;
an address decoder which receives the address signal and outputs a decode signal;
a third inverter which receives the decode signal and outputs an inversion signal of the decode signal as a third signal; a first NAND circuit which receives the first signal and the decode signal; and
a second NAND circuit which receives the second signal and the decode signal,
wherein a gate of the first PMOS transistor is connected to an output of the first NAND circuit, and
wherein a gate of the first NMOS transistor is connected to an output of the third inverter,
wherein a gate of the second PMOS transistor and a gate of the second NMOS transistor are connected to an output of the second NAND circuit.

US Pat. No. 10,658,027

HIGH DENSITY SPLIT-GATE MEMORY CELL

Silicon Storage Technolog...

1. A method of forming a memory device, comprising:forming a plurality of separated first trenches into a surface of a semiconductor substrate, wherein the first trenches are parallel to each other and extend in a first direction and define active regions of the substrate between the first trenches;
filling the first trenches with insulation material;
forming a first insulation layer on the surface of the substrate in each of the active regions;
forming a first conductive layer on the first insulation layer in each of the active regions;
forming a second insulation layer on the first conductive layer in each of the active regions;
forming a second conductive layer on the second insulation layer in each of the active regions;
forming a third insulation layer on the second conductive layer in each of the active regions;
forming a plurality of separated second trenches through the third insulation layer, wherein the second trenches are parallel to each other and extend in a second direction perpendicular to the first direction;
extending the second trenches through the second conductive layer and the second insulation layer;
extending the second trenches through the first conductive layer, leaving side portions of the first conductive layer exposed and leaving the first insulation layer on the surface of the substrate at the bottom of the second trenches;
forming a fourth insulation layer vertically and directly on the first insulation layer at the bottom of the second trenches and along the exposed portions of the first conductive layer, wherein the fourth insulation layer is not in direct contact with the substrate;
filling the second trenches with conductive material, wherein the conductive material is insulated from the first conductive layer by the fourth insulation layer and from the substrate surface in a vertical direction by the first insulation layer and the fourth insulation layer;
forming a plurality of third trenches through the third insulation layer, wherein the third trenches are parallel to each other and extend in the second direction such that the second and third trenches alternate each other;
extending the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer;
performing an implantation to form drain regions in the substrate under the third trenches.

US Pat. No. 10,658,026

WORD LINE PULSE WIDTH CONTROL CIRCUIT IN STATIC RANDOM ACCESS MEMORY

Taiwan Semiconductor Manu...

1. A control circuit for minimizing a static noise margin of a static random access memory device comprising:a first transistor comprising a gate and a source/drain terminal;
an inverter comprising an input node coupled to the gate of the first transistor and an output node; and
a second transistor comprising a gate, a first source/drain terminal, and a second source/drain terminal, the gate of the second transistor being coupled to the output node of the inverter and the first source/drain terminal of the second transistor being coupled in series to the source/drain terminal of the first transistor, and wherein the second source/drain terminal is coupled to a decoder driver circuit,
wherein the second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.

US Pat. No. 10,658,025

APPARATUSES AND METHODS FOR DETECTING A ROW HAMMER ATTACK WITH A BANDPASS FILTER

Micron Technology, Inc., ...

1. An apparatus comprising:a row hammer control circuit configured to provide a row hammer address responsive to detection of a row hammer attack, wherein the row hammer control circuit comprises a multi-stage sampling circuit configured to detect the row hammer attack based on an output sampling signal, the multi-stage sampling circuit comprising:
a first filter stage configured to perform a first filter operation on a received row address and a first set of previously received row addresses responsive to a first sampling signal generated responsive to an activation signal to provide a second sampling signal;
a second filter stage configured to perform a second filter operation on the received address and a second set of previously received row addresses responsive to a control signal to provide a third sampling signal, wherein the output sampling signal is based on either the third sampling signal or the second sampling signal and the third sampling signal.

US Pat. No. 10,658,024

SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL VOLTAGE BOOSTING

Micron Technology, Inc., ...

1. A memory device, comprising:a memory array having at least one memory cell;
a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof;
a first bus configured to provide a first electric power to the sense amplifier circuit;
a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell; and
a global wordline circuit, wherein the global wordline circuit is configured to electrically couple the first bus with the second bus after receipt of a precharge (PRE) command to provide for the first electric power and the second electric power to the at least one memory cell, wherein the second circuit comprises a wordline driver circuit configured to provide the second electric power to a wordline of the memory array, and wherein the wordline is electrically coupled to the at least one memory cell.

US Pat. No. 10,658,023

VOLATILE MEMORY DEVICE AND ELECTRONIC DEVICE COMPRISING REFRESH INFORMATION GENERATOR, INFORMATION PROVIDING METHOD THEREOF, AND REFRESH CONTROL METHOD THEREOF

Samsung Electronics Co., ...

1. A memory system, comprising:a volatile memory device including a refresh controller connected to memory cells,
the volatile memory device being configured to perform a first refresh operation on a first portion of the memory cells while the volatile memory device performs a valid operation on a second portion of the memory cells,
the volatile memory device being configured to perform a second refresh operation in response to a refresh command from a memory controller;
the refresh controller being configured to generate refresh information using a performance indicator of the first refresh operation during a first part of a reference time; and
the memory controller,
the memory controller being configured to schedule the second refresh operation a desired number of times during a remaining part of the reference time based on the refresh information, and
the memory controller being configured to control the volatile memory device to perform the second refresh operation according to the schedule.

US Pat. No. 10,658,022

HIGH GAIN SENSE AMPLIFIER WITH OFFSET CANCELLATION FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY

International Business Ma...

1. A sense amplifier circuit for sensing a data state of a data cell, comprising:a first leg comprising a first n-channel transistor and a second leg comprising a second n-channel transistor, wherein the sense amplifier circuit is configured to perform a two-phase read comprising:
a first phase in which the first n-channel transistor is coupled to a reference resistance element and the second n-channel transistor is coupled to a data resistance element, and
a second phase in which the first n-channel transistor is coupled to the data resistance element and the second n-channel transistor is coupled to the reference resistance element;
a first active amplifier for controlling a gate voltage of the first n-channel transistor and a second active amplifier for controlling a gate voltage of the second n-channel transistor; and
a comparator circuit configured to output the data state of the data cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.

US Pat. No. 10,658,021

SCALABLE SPIN-ORBIT TORQUE (SOT) MAGNETIC MEMORY

SPIN MEMORY, INC., Wilmi...

1. A magnetic storage device, comprising:a plurality of first wires extending along a first direction;
a plurality of second wires extending along a second direction different from the first direction, forming a grid with the plurality of first wires;
a plurality of spin orbit torque magnetic random access memory (SOT-MRAM) devices, each of the plurality of SOT-MRAM devices disposed at a respective position on the grid;
write circuitry, including a transistor coupled to each respective first wire of the plurality of first wires, to apply a first write current along the respective first wire in the first direction; and
readout circuitry to read a data value stored by a respective SOT-MRAM device,
wherein the write circuitry further includes a second transistor to select an individual SOT-MRAM device and apply a second write current to the individual SOT-MRAM device, wherein the second write current is along an axis of the individual SOT-MRAM device.

US Pat. No. 10,658,020

STROBE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A strobe signal generation circuit comprising:a serializer configured to generate a pre-pull-up signal and a pre-pull-down signal by serializing signals inputted through a first data input terminal and a second data input terminal, according to a differential clock signals;
a first pre-driver configured to generate a first pull-up signal and a second pull-up signal by driving the pre-pull-up signal based on an on-die termination signal;
a second pre-driver configured to generate a first pull-down signal and a second pull-down signal by driving the pre-pull-down signal based on the on-die termination signal;
a first main driver configured to generate a differential data strobe signal in response to receiving the first pull-up signal and the first pull-down signal; and
a second main driver configured to generate an other differential data strobe signal in response to receiving the second pull-up signal and the second pull-down signal through opposite terminals compared to the first main driver, with the pull-up signal going to a ground.

US Pat. No. 10,658,019

CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY

Micron Technology, Inc., ...

1. An apparatus, comprising:a synchronization circuit configured to receive a first clock signal, and provide a second clock signal based, at least in part, on the first clock signal;
a mode register configured to store a latency value indicative of a first number of clock cycles; and
a latency control circuit coupled to the synchronization circuit and the mode register, the latency control circuit configured to receive the first clock signal, the second clock signal, the latency value, a count signal indicative of a second number of clock cycles, and a command signal, wherein the count signal is different than the latency value;
wherein the latency control circuit is further configured to latch the command signal responsive, at least in part, to the first clock signal to provide a latched command signal, hold the latched command signal for an amount of time based, at least in part, on the latency value, and provide the latched command signal responsive, at least in part, to the second clock signal.

US Pat. No. 10,658,018

QUANTIZING CIRCUITS HAVING IMPROVED SENSING

Micron Technology, Inc., ...

8. A device, comprising:a data location;
a reference current source; and
a quantizing circuit coupled to the data location and the reference current source, wherein the quantizing circuit comprises:
a combination circuit configured to combine a first signal with an analog feedback signal to produce a delta signal;
an integrator coupled to the combination circuit, wherein the integrator is configured to receive and integrate the delta signal to produce a sigma signal;
an analog-to-digital converter coupled to the integrator, wherein the analog-to-digital converter is configured to receive the sigma signal and compare the sigma signal with a reference signal to produce a digital output signal; and
a digital-to-analog convertor coupled to the analog-to-digital converter and the combination circuit, wherein the digital-to-analog converter comprises a switch configured to cooperate with the reference current source to convert the digital output signal into the analog feedback signal.

US Pat. No. 10,658,017

SHIFTING DATA

Micron Technology, Inc., ...

1. A memory device, comprising:a shift register comprising a number of stages and having a data path and a clock signal path associated therewith;
a clock driver coupled to a final output stage of the shift register and configured to assert a clock signal on the clock signal path of the shift register, wherein the data path is matched to the clock signal path.

US Pat. No. 10,658,016

SERIES CONTINUOUS TIME LINEAR EQUALIZERS

Integrated Device Technol...

1. An apparatus comprisinga first continuous time linear equalizer circuit configured to generate an intermediate signal by filtering an input signal using a first passive bandpass filter having an inductor; and
a second continuous time linear equalizer circuit configured to generate an output signal by filtering said intermediate signal, wherein said first continuous time linear equalizer circuit and said second continuous time linear equalizer circuit are implemented in one or more of (i) a double-data rate memory module, (ii) a data buffer of a memory module or (iii) a registered clock driver of said memory module.

US Pat. No. 10,658,015

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a shift register configured to generate shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length; and
a control signal generation circuit configured to generate a control signal for setting a burst operation period according to a period during which the shifted pulses are created,
wherein the burst operation period is a period during which a burst operation is performed, and data having a plurality of bits are successively inputted to the semiconductor device by a write command or successively outputted from the semiconductor device by a read command based on the mode of the burst length.

US Pat. No. 10,658,014

MEMORY DEVICE WITH MEMORY CELL BLOCKS, BIT LINE SENSE AMPLIFIER BLOCKS, AND CONTROL CIRCUIT CONNECTED TO BIT LINE SENSE AMPLIFIER BLOCKS TO CONTROL CONSTANT LEVELS OF CURRENTS SUPPLIED TO SENSING DRIVING VOLTAGE LINES

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a plurality of memory cell blocks, where each memory cell block comprises a plurality of memory cells;
a plurality of bit line sense amplifier blocks arranged between the memory cell blocks and comprising bit line sense amplifiers performing sensing operations for sensing and amplifying data of the memory cells; and
a sensing-matching control circuit connected to one or more of the bit line sense amplifier blocks and determining levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line, wherein the first sensing driving voltage line and the second sensing driving voltage line are connected to the bit line sense amplifiers of the one or more bit line sense amplifier blocks, to which the sensing-matching control circuit is connected,
wherein the bit line sense amplifiers of the one or more bit line sense amplifier blocks are driven based on the levels of currents of the first and second sensing driving voltage lines, the levels of currents being determined by the sensing-matching control circuit,
wherein the sensing-matching control circuit applies a first internal voltage to a given sensing driving voltage line among the sensing driving voltage lines during one of the sensing operations, and
wherein the sensing-matching control circuit comprises:
a first current source;
a first sensing driving voltage driver; and
a first comparator comparing a first internal voltage of a first node connected between the first current source and an input terminal of the first sensing driving voltage driver with a first reference voltage to output a first sensing driving control signal,
wherein the first sensing driving voltage driver provides the first internal voltage to the given sensing driving voltage line based on the first sensing driving control signal.

US Pat. No. 10,658,013

FEED FORWARD BIAS SYSTEM FOR MTJ VOLTAGE CONTROL

Everspin Technologies, In...

1. A magnetic memory, comprising:a first common line having a first end and a second end;
a second common line having a first end and a second end;
a memory cell that includes:
a select device having a first electrode and a second electrode, wherein the first electrode is connected to the first end of the first common line; and
a magnetic memory element coupled in series between the second electrode of the select device and the first end of the second common line;
a first voltage driver, wherein the first voltage driver is coupled to the second end of the second common line, and
a bias voltage generation circuit, wherein the bias voltage generation circuit is configured to provide a first bias voltage to the first voltage driver and includes a current reference device, wherein the current reference device includes a trimming device for controlling an amount of current flowing through the current reference device, and wherein the first voltage driver is configured to provide a first driving voltage to the second end of the second common line during an access operation.

US Pat. No. 10,658,012

APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES

OVONYX MEMORY TECHNOLOGY,...

1. A method, comprising:operating a memory device according to a first mode of operation, the memory device configured to operate in the first mode of operation and a second mode of operation different than the first mode of operation, wherein the second mode of operation is a low-latency mode;
enabling an overlay window based at least in part on the memory device operating in the first mode of operation, wherein the overlay window is configured to control a bias level of a word line associated with a memory cell; and
accessing the memory cell of the memory device according to the first mode of operation based at least in part on the bias level.

US Pat. No. 10,658,011

VOLTAGE GENERATING SYSTEM, VOLTAGE GENERATING CIRCUIT AND ASSOCIATED METHOD

TAIWAN SEMICONDUCTOR MANU...

13. A voltage generating circuit, comprising:an output node (Nout) and a control node (Nctrl);
an output circuit, arranged to generate a control signal (CTRL) at the control node according to a first clock signal (CLKH) and a reference voltage (Vref), generate an output signal (Vout) at the output node according to a second clock signal (CLKL) and the reference voltage, wherein a first amplitude (VDD2) of the first clock signal is greater than the reference voltage and a second amplitude (VDD1) of the second clock signal, and an absolute value of a third amplitude of the output signal is greater than the reference voltage while an absolute value of a fourth amplitude of the control signal is greater than the reference voltage; and
a switch circuit, arranged to selectively output the output signal to an output terminal (OUT) according to the control signal.

US Pat. No. 10,658,010

APPARATUS FOR HIGH SPEED ROM CELLS

Taiwan Semiconductor Manu...

1. An apparatus comprising:a first bit line in a first interconnect layer over a substrate;
a second bit line in the first interconnect layer;
a first electrical ground line (VSS line) in a first contact layer between the substrate and the first interconnect layer;
a second VSS line in the first interconnect layer, the second VSS line extending perpendicularly to the first VSS line and coupled to the first VSS line;
first memory cells in a first row, each of the first memory cells comprising:
a first transistor in the substrate, wherein a source of the first transistor is coupled to the first VSS line, and a drain of the first transistor is couple to the first bit line or to the second bit line;
a first word line in a second interconnect layer over the first interconnect layer and electrically coupled to a gate of the first transistor of each of the first memory cells through a first word line strap structure, the first word line strap structure comprising a first gate contact in the first contact layer, a first-level via in the first interconnect layer, a first metal line in the first interconnect layer, and a second-level via in the second interconnect layer;
second memory cells in a second row adjacent and parallel to the first memory cells; and
a second word line in the second interconnect layer and electrically coupled to the second memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.

US Pat. No. 10,658,009

COMPUTER SYSTEM AND COMPUTER CASING

Fujitsu Client Computing ...

1. A computer system comprising:a computer casing having a casing wall having a first opening to pass through a connection means and a second opening to pass through a guide pin having a U-shaped cut-out;
a circuit board having at least one edge having the connection means mounted thereon; and
the guide pin, separate from the connection means, arranged in the casing and configured to align the circuit board relative to the casing wall, wherein
the at least one edge of the circuit board comprises a cut-out having a U-shape perpendicular to the cut-out of the guide, and
wherein the cut-out of the guide pin is formed to directly engage with the cut-out of the circuit board such that the circuit board itself is centered with respect to the casing wall in a direction of the casing wall during a placing movement so that the connection means takes a predetermined position flush with respect to the opening in the casing wall and can plunge into the opening.

US Pat. No. 10,658,008

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

FUJI XEROX CO., LTD., To...

1. An information processing apparatus comprisinga receiving unit that receives, during reproduction of a video, a predetermined operation with respect to the video from a user;
an associating unit that associates the received operation with a reproduction time where the received operation has been generated in the video; and
a controller configured to display an importance degree of the reproduction location associated with the received operation in time series.

US Pat. No. 10,658,007

SMARTPHONE-BASED METHODS AND SYSTEMS

Digimarc Corporation, Be...

1. A mobile device adapted for use where a subject being imaged by a camera of the device may move relative to the camera, and thereby hinder a desired user interaction, the device including:a processor;
a memory;
a display;
means for recognizing first and second physical objects depicted in a first frame of video captured by the camera, said objects being depicted at first and second respective positions in said first frame; and
instructions in the memory that configure the device to present, at first and second locations along an edge of the display, first and second graphical indicia that respectively correspond to said recognized first and second objects, said indicia being selectable by a user to link to additional information about said objects;
wherein said instructions cause the first and second graphical indicia to remain fixed at said first and second locations, despite depiction of the first and second objects at positions different than said first and second positions in a second, subsequent, frame of video.

US Pat. No. 10,658,006

IMAGE PROCESSING APPARATUS THAT SELECTS IMAGES ACCORDING TO TOTAL PLAYBACK TIME OF IMAGE DATA, IMAGE SELECTION METHOD, AND COMPUTER-READABLE MEDIUM

CASIO COMPUTER CO., LTD.,...

1. An image processing apparatus, comprising:a processor which is configured to:
acquire a plurality of images;
calculate an evaluation value of each of the plurality of images;
evaluate the plurality of images based on the calculated evaluation value;
set a total playback time of a moving image;
set an individual playback time for each of the plurality of images, based on results of the evaluation of the plurality of images;
select a predetermined number of images corresponding to the total playback time from the plurality of images so that the sum of the evaluation value of each image is highest, based on (i) the individual playback times which have been set for each image and (ii) the evaluation value which has been calculated;
set switching time points of images in the total playback time that is set; and
select the predetermined number of images from the plurality of images so as to be within the total playback time based on the switching time points.

US Pat. No. 10,658,005

METHODS AND SYSTEMS FOR IMAGE AND VOICE PROCESSING

Neon Evolution Inc., Los...

1. An electronic image and voice processing system, comprising:a network interface;
at least one computing device;
computer readable memory including instructions operable to be executed by the at least one computing device to perform a set of actions, configuring the at least one computing device to:
use one or more microphones to generate a source voice training set, wherein the one or more microphones are used to capture a source voice speaking a plurality of words using varying speech parameters, wherein the captured source voice is captured to train autoencoders;
train an autoencoder using the source voice training set, wherein the autoencoder comprises:
an input layer;
an encoder including at least one hidden layer that has fewer nodes than the input layer to thereby constrain recreation of an input voice by the encoder, wherein the encoder is configured to output a latent voice from a corresponding input voice;
a decoder configured to attempt to reconstruct the input voice from the latent voice;
train the autoencoder using a destination voice speaking words using varying speech parameters; and
access audio/video media comprising a video track and an audio track, wherein the audio track include the destination voice speaking words and the video track includes images of a destination face having lips synchronized with the destination voice;
use the trained autoencoder to generate a modified audio track using the destination voice in the audio track as an input, where the destination voice is swapped with the source voice, while preserving the words of the destination voice, so that the source voice is speaking the words of the destination voice;
use a face swapping network to generate a modified video track wherein the face swapping network replaces the destination face likeness with a source face likeness with preserving the facial expressions of the destination face; and
generate a modified audio/video media comprising the modified video track and the modified audio track.

US Pat. No. 10,658,004

MAGNETIC DISK DEVICE AND WRITE PROCESSING METHOD

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk;
a head configured to write data to the disk and read data from the disk; and
a controller configured to control the head to write a first track based on a first error rate read immediately after writing a second track adjacent in a radial direction of the disk to the first track, wherein
the controller controls the head position to write the first track based on a first difference value between the first error rate and a maximum error rate at which the data written in the disk is readable.

US Pat. No. 10,658,003

USING DIPULSE RESPONSE TO DETECT CHANNEL PARAMETERS

Marvell International Ltd...

1. A method in a data storage system having i) a storage device that stores data and ii) a read channel device for reading data from the storage device, the method comprising:receiving, at a receiver device of the data storage system, a signal via a communication channel of the data storage system, the signal (i) having been transmitted by a transmitter device of the data storage system, and (ii) corresponding to a pseudorandom bit sequence (PRBS);
correlating, at the receiver device, the received signal with a known signal to generate a correlation signal, wherein the known signal includes the PRBS;
identifying, at the receiver device, one or more characteristics of the correlation signal;
determining, at the receiver device, one or more parameters of the communication channel using the identified one or more characteristics of the correlation signal, including determining one or more of i) a frequency offset corresponding to a clock used by the receiver device, ii) a signal asymmetry parameter, and iii) a cross-track position of an optical or magnetic head of a magnetic or optical disk drive; and
using, at the receiver device, the one or more parameters corresponding to the communication channel to process subsequent signals received via the communication channel.

US Pat. No. 10,658,002

MAGNETIC DISK DEVICE, CONTROL DEVICE, AND REGULATOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a control device configured to control processing relating to a magnetic disk; and
a regulator device configured to output a voltage to the control device,
wherein
the control device and the regulator device are connected to each other through a first interface and a second interface,
the control device transmits a required voltage value to the regulator device through the first interface and transmits a correction value to the regulator device through the second interface,
the regulator device outputs a voltage to the control device on the basis of the received required voltage value and corrects a value of the voltage to be output to the control device on the basis of the received correction value, and
the correction value is generated by the control device and is based on the required voltage value and an output voltage output from the regulator device.

US Pat. No. 10,658,001

METHOD AND SYSTEM FOR SELECTING AND MOVING A SINGLE DISC IN AN OPTICAL DISC LIBRARY

International Business Ma...

1. A disc selector system comprising:a motor; and
a disc selector mechanism coupled to a bottom of a guide cage and maintained in a space below the guide cage, wherein the disc selector mechanism comprises:
a shaft;
a slide laterally slidable along the shaft in response to the motor driving the slide;
a pivot bar coupled to the slide; and
a pick blade pivotally coupled to the pivot bar;
wherein a linear motion of the slide along the shaft drives a linear translation of the pivot bar, and the linear translation drives the pick blade to move out of the space and pivot to a raised position to contact and lift a disc upwards into a disc gripper device.

US Pat. No. 10,658,000

REMOTELY CONTROLLING A MAGNETIC TAPE CARTRIDGE

International Business Ma...

1. A data storage cartridge, comprising:a housing configured to house a data storage medium, wherein the data storage medium is a magnetic recording tape;
a sensor coupled to and being positioned within the housing;
a microcontroller coupled to the sensor, the microcontroller being configured to wirelessly communicate information about the sensor; and
a leader pin coupled to a leading end of the magnetic recording tape, wherein the sensor is configured to detect a status of the leader pin.

US Pat. No. 10,657,999

PLASMA CVD DEVICE AND METHOD OF MANUFACTURING MAGNETIC RECORDING MEDIUM

ADVANCED MATERIAL TECHNOL...

1. A plasma CVD device comprising:a chamber;
an anode which is arranged within said chamber and which has an electrode surface on a front surface;
a cathode which is arranged within said chamber;
a holding portion which is arranged within said chamber and which holds a substrate to be deposited which is arranged so as to face said electrode surface of said anode and said cathode;
a plasma wall which is arranged within said chamber and which is provided so as to cover a space between said substrate to be deposited held by said holding portion and each of said electrode surface of said anode and said cathode;
an anti-adhesion member which is arranged between a first gap between said anode and said plasma wall and a first inner surface of said chamber and which is in contact with said first inner surface of said chamber;
a pedestal which is arranged between said anti-adhesion member and a back surface of said anode and between the back surface of said anode and a second inner surface of said chamber and which is electrically connected to said anode;
a spacer which is arranged between said back surface of said anode and a third inner surface of said chamber and which is in contact with said third inner surface;
a first direct-current power source which is electrically connected to said pedestal;
an alternating-current power source which is electrically connected to said cathode;
a second direct-current power source which is electrically connected to said substrate to be deposited held by said holding portion;
a gas supply mechanism which supplies a raw material gas into said chamber; and
an exhaust mechanism which exhausts said chamber,
wherein each of a maximum diameter of said first gap, a maximum diameter of a second gap between said anode and said anti-adhesion member, a maximum diameter of a third gap between said back surface of said anode and said spacer, a maximum diameter of a fourth gap between said plasma wall and said anti-adhesion member, a maximum diameter of a fifth gap between said anti-adhesion member and said pedestal and a maximum diameter of a sixth gap between said pedestal and said spacer is equal to or less than 4 mm;
said first inner surface of said chamber faces said plasma wall and said pedestal;
said second inner surface of said chamber faces said pedestal; and
said third inner surface of said chamber faces said back surface of said anode.

US Pat. No. 10,657,998

CONTACT DETECTION AND LASER POWER MONITORING SENSOR FOR HEAT-ASSISTED MAGNETIC RECORDING HEAD

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider configured for heat-assisted magnetic recording and comprising a writer, a near-field transducer, and an optical waveguide coupling the near-field transducer to a light source;
the writer situated proximate the near-field transducer at an air bearing surface of the slider and comprising:
a first return pole;
a second return pole; and
a write pole situated between and spaced apart from the first return pole and the second return pole;
a magnetic structural element at or near the air bearing surface between the write pole and one of the first and second return poles, the magnetic structural element comprising a cavity or contacting a dielectric material comprising the cavity; and
a thermal sensor disposed in the cavity and situated relative to the writer and the near-field transducer so as to negligibly impact the optical or magnetic performance of the slider, the thermal sensor configured for sensing output optical power of the light source and sensing contact between the slider and one or both of thermal asperities of a magnetic recording medium and the magnetic recording medium.

US Pat. No. 10,657,997

CHARACTERIZATION OF NONLINEARITY IN SERVO PATTERNS

International Business Ma...

1. A method, comprising:applying a static head skew to a magnetic tape head for misaligning first and second readers in a direction perpendicular to a tape travel direction thereacross;
positioning the first reader at a first y-position relative to a servo pattern in a servo band;
measuring y-positions of the second reader relative to the servo pattern in the servo band while the first reader is at the first y-position;
calculating a y-position value for the second reader based on the measured y-positions;
repeating the following process several times:
moving the first reader to a next y-position,
measuring y-positions of the second reader while the first reader is at the next y-position, and
calculating a y-position value of the second reader based on the measured y-position of the second reader while the first reader is at the next y-position;
calculating a unique nonlinearity value of the servo pattern in the servo band for each of the calculated y-position values of the second reader using the respective calculated y-position value of the second reader; and
storing and/or outputting the calculated nonlinearity values.

US Pat. No. 10,657,996

MAGNETIC RECORDING MEDIUM FOR MICROWAVE-ASSISTED RECORDING, MAGNETIC RECORDING DEVICE, AND MANUFACTURING METHOD OF MAGNETIC RECORDING MEDIUM

FUJIFILM Corporation, To...

1. A magnetic recording medium,which is a magnetic recording medium for microwave-assisted recording and comprises:
a non-magnetic support; and
a magnetic layer including a ferromagnetic powder and a binding agent on the non-magnetic support,
wherein the magnetic layer shows a natural ferromagnetic resonance frequency equal to or greater than 30.0 GHz and an anisotropic magnetic field distribution equal to or smaller than 35%,
wherein the anisotropic magnetic field distribution is measured by the following method with a vibrating sample magnetometer including detection coils in two directions orthogonal to each other;
a magnetic field is applied to a sample of the magnetic recording medium at 0° with respect to the X axis direction at +800 kA/m to cause saturation, the application magnetic field is set as zero, and residual magnetization in the X axis direction and the Y axis direction are measured;
then, a magnetic field is applied at +8 kA/m, in a state where the sample is rotated by 10°, the magnetic field is set as zero, the angle of the sample is returned to 0°, and residual magnetization in the X axis direction and the Y axis direction are measured;
in addition, in a state where the sample is rotated by 10°, a magnetic field in which +8 kA/m is added to the strength applied in the previous stage, the magnetic field is set as zero, the angle of the sample is returned to 0°, and residual magnetization in the X axis direction and the Y axis direction are measured;
the above operations are repeated until the application magnetic field reaches+800 kA/m, and values of differences of the residual magnetic field in the Y axis direction with respect to the application magnetic field are plotted on a graph;
in the graph, a quadratic curve is obtained by quadratic curve approximation by using data of 20 continuous plots, the 20 plots being selected so that the 10th or 11th plot, in a case where the plots are counted from a small side of the value of the application magnetic field (horizontal axis) among the 20 continuous plots, has a maximum value of the plot in the graph;
in the obtained quadratic curve, a magnetic field which becomes a maximum value (Hpeak) is set as a peak and a magnetic field which is ½ of the peak (a high magnetic field side is shown as “High” and a low magnetic field side is shown as “Low”) is calculated; and
the anisotropic magnetic field distribution is calculated from the following expression:
anisotropic magnetic field distribution (%)={(High?Low)/Hpeak}×100.

US Pat. No. 10,657,995

MAGNETIC DISK DEVICE AND METHOD

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device, comprising:a magnetic disk including a plurality of tracks;
a first magnetic head;
a second magnetic head different from the first magnetic head;
a first actuator that moves the first magnetic head;
a second actuator that moves the second magnetic head, the second actuator being different from the first actuator;
a buffer memory that receives first data from a host; and
a control circuit that writes, in a first track by using the first actuator, second data having a size corresponding to a first number among the first data, and writes, in a second track by using the second actuator, third data having a size corresponding to a second number among the first data, the first track being a track among the plurality of tracks, the second track being, among the plurality of tracks, a track different from the first track, the first number being a number of writable sectors included in the first track, the second number being a number of writable sectors included in the second track, the third data being data received subsequent to the second data,
wherein the control circuit writes, in a third track by using the first actuator, fourth data having a size corresponding to a third number among the first data, the third track being, among the plurality of tracks, a track different from any of the first track and the second track, the third number being a number of writable sectors included in the third track, the fourth data being data received subsequent to the third data.

US Pat. No. 10,657,994

HORIZONTAL CAVITY SURFACE EMITTING LASER INTEGRATION FEATURES FOR HEAT ASSISTED MAGNETIC RECORDING

Seagate Technology LLC, ...

1. An apparatus comprising:a slider body with a mounting surface comprising an input to an optical coupling path integrated into the slider body; and
a bonding material having at least one gap, the bonding material at least partially surrounding the input, the bonding material creating an at least partially sealed region containing an output of a laser, a mirror, and an input coupler on the slider body, the sealed region preventing the entry of particles into a region between the input coupler, the mirror, and the output of the laser.

US Pat. No. 10,657,993

DISK DEVICE WITH DUAL ACTUATOR CONFIGURATION

Kabushiki Kaisha Toshiba,...

1. A disk device comprising:a plurality of disk-shaped recording media provided to be rotatable;
a first actuator assembly comprising:
a first actuator block supported pivotably around a support shaft;
a plurality of arms each extending from the first actuator block and comprising a first surface substantially parallel to a respective one of the plurality of recording media, a second surface opposing the first surface, a side surface intersecting the first surface and the second surface, and a slit located in the side surface;
a plurality of head suspension assemblies each comprising a support plate fixed to an extending end of each of the plurality of arms, a wiring member attached to the support plate and a head supported by the wiring member; and
a first wiring board comprising a plurality of connection terminals and provided on a setting surface of the first actuator block; and
a second actuator assembly comprising:
a second actuator block supported pivotably around the support shaft and opposing the first actuator block with a gap therebetween;
a plurality of arms each extending from the second actuator block and comprising a first surface substantially parallel to a respective one of the plurality of recording media, a second surface opposing the first surface, a side surface intersecting the first surface and the second surface, and a slit located in the side surface;
a plurality of head suspension assemblies each comprising a support plate fixed to an extending end of each of the plurality of arms, a wiring member attached to the support plate and a head supported by the wiring member; and
a second wiring board comprising a plurality of connection terminals and provided on a setting surface of the second actuator block;
each of the wiring members of the first actuator assembly comprising a distal end-side portion disposed on the support plate, a rear end-side portion disposed in the slit of the respective one of the arms and extending to the first actuator block, and a connection end portion comprising a plurality of connection terminals and extending from the rear end-side portion, and, of the plurality of connection end portions, at least those adjacent to a border plane between the first actuator block and the second actuator block being provided to be offset in a direction spaced away from the border plane with respect to a central line of the respective one of the arms in its thickness direction, and
each of the wiring members of the second actuator assembly comprising a distal end-side portion disposed on the support plate, a rear end-side portion disposed in the slit of the respective one of the arms and extending to the second actuator block, and a connection end portion comprising a plurality of connection terminals and extending from the rear end-side portion, and, of the plurality of connection end portions, at least those adjacent to the border plane being provided to be offset in a direction spaced away from the border plane with respect to a central line of the respective one of the arms in its thickness direction.

US Pat. No. 10,657,992

TUNNEL VALVE MAGNETIC TAPE HEAD FOR MULTICHANNEL TAPE RECORDING

International Business Ma...

1. An apparatus, comprising:a plurality of tunnel valve read transducers arranged in an array extending along a read module,
wherein each of the tunnel valve read transducers includes:
a sensor structure having a cap layer, a free layer, a tunnel barrier layer, a reference layer and an antiferromagnetic layer;
electrically insulating layers on opposite sides of the sensor structure;
an upper magnetic shield; and
a lower magnetic shield,
wherein a separation between the upper and lower magnetic shields proximate to the sensor structure and along the intended direction of media travel is less than 120 nm,
wherein a height of the free layer measured in a direction perpendicular to a media bearing surface of the read module is less than a width of the free layer measured in a cross-track direction perpendicular to an intended direction of media travel.

US Pat. No. 10,657,991

SPLIT CONTACT SENSOR FOR A HEAT-ASSISTED MAGNETIC RECORDING SLIDER

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider comprising an air bearing surface (ABS), a leading edge, and a trailing edge opposing the leading edge;
a writer having a write pole situated at or near the ABS;
a near-field transducer (NFT) situated at or near the ABS and between the write pole and the leading edge of the slider,
an optical waveguide configured to couple light from a laser source to the NFT;
a contaminant buildup region at and near the NFT and the write pole; and
a contact sensor situated between the write pole and the trailing edge, at least a portion of the contact sensor situated at or near the ABS and comprising a gap sufficient in size to accommodate a width of the contaminant buildup region.

US Pat. No. 10,657,990

MAGNETIC HEAD AND DISK DEVICE HAVING GAP LAYERS WITH DIFFERENT MAGNETIC RELATIVE PERMEABILITIES

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic head comprising:a main magnetic pole that generates a recording magnetic field;
a write shield disposed adjacent to the main magnetic pole and separated from the main magnetic pole by a write gap;
a first side shield that is disposed on a first side of the main magnetic pole in a track width direction from the main magnetic pole and is separated from the main magnetic pole by a first side gap;
a second side shield that is disposed on a second side of the main magnetic pole in the track width direction from the main magnetic pole and is separated from the main magnetic pole by a second side gap;
a first layer that has a first magnetic relative permeability greater than zero and is disposed in the write gap between the main magnetic pole and the write shield; and
a second layer that has a second magnetic relative permeability greater than zero and is disposed in the first side gap and the second side gap,
wherein the first magnetic relative permeability is smaller than the second magnetic relative permeability,
wherein the first layer comprises a magnetic metal selected from the group consisting of Fe, Co, and Ni, and
wherein the first layer fills the write gap between the main magnetic pole and the write shield.

US Pat. No. 10,657,989

TAPE HEAD MODULE HAVING RECESSED PORTION(S) AND AIR APERTURE(S) FOR PROVIDING AN AIR BEARING BETWEEN A TAPE AND THE MODULE

International Business Ma...

1. An apparatus, comprising:a module having a tape bearing surface, and an array of transducers extending along the tape bearing surface,
the module having an aperture extending therethrough from the tape bearing surface to an opposing side of the module for permitting passage of air therethrough to the tape bearing surface,
wherein the module has a recessed portion extending into the tape bearing surface, the recessed portion extending along a length of the tape bearing surface between the array of transducers and a first end of the module, the aperture extending from the recessed portion to the opposing side for permitting passage of air therethrough into the recessed portion.

US Pat. No. 10,657,988

METHOD OF FORMING A PERPENDICULAR MAGNETIC RECORDING (PMR) WRITE HEAD WITH PATTERNED LEADING EDGE TAPER

Headway Technologies, Inc...

1. A method of forming a patterned leading shield structure in a perpendicular magnetic recording (PMR) writer, comprising:(a) providing a first leading shield (LS) layer with a top surface, a first cross-track width (w) at a first plane that is orthogonal to the first LS layer top surface, and a first height (c) between the first plane and a backside that is aligned parallel to the first plane, and wherein the first LS layer backside adjoins a front side of a dielectric layer having a top surface which is coplanar with the first LS layer top surface;
(b) forming a second leading shield (LS) layer on the first LS layer top surface, the second LS layer has the first cross-track width at the first plane, and a backside that is at the first height from the first plane, and wherein the second LS layer has a top surface with a notch formed therein, the notch comprises a first side that is recessed a second height (a) from the first plane, is formed parallel to the first plane and extends a first down-track distance from the top surface to a second notch side that is orthogonal to the first plane, and extends from an end of the first notch side to the second LS layer backside;
(c) forming a second dielectric layer on the top surfaces of the first LS layer and first dielectric layer wherein the second dielectric layer has a top surface that is coplanar with a top surface of the second LS layer and has a front side that adjoins the second LS layer backside;
(d) performing an angled ion beam etch that forms a tapered top surface on the second LS layer such that a thickness of the second LS layer at the first height is less than a thickness of the second LS layer at the first plane; and
(e) performing a lapping process that forms an air bearing surface (ABS) at the first plane, and a front side of each of the first and second LS layers at the ABS.

US Pat. No. 10,657,987

LASER BOOST AND DURATION OPTIMIZATION

Seagate Technology LLC, ...

9. A method comprising:performing a single write operation via a laser-assisted data recording system, including compensating for a higher bit error rate in a first sector of the single write operation by adjusting a laser power during the single write operation, the single write operation including:
writing a first sector of the single write operation while the laser-assisted data recording system applies a first laser power; and
writing one or more second sectors of the single write operation while the laser-assisted data recording system implements a second laser power less than the first laser power.

US Pat. No. 10,657,986

APPARATUS, METHODS, AND SYSTEMS FOR ACHIEVING LINEAR TONEARM TRACKING FOR A RECORD TURNTABLE

Koolance, Inc., Auburn, ...

1. A tonearm tracking system for use in playing a record comprising:a tonearm;
a joint member movably connected to the tonearm and movably connected to a track having a nonlinear guiding slot for guiding a guide member of the joint member, the joint member also being connected by a hitch member to a slidable pivot base to which the tonearm is pivotably connected at a rear pivot location; and
wherein the slidable pivot base is slidable in a rearward and forward direction in response to pressure applied to the hitch member by the joint member, the hitch member extending longitudinally rearward from the slidable pivot base.

US Pat. No. 10,657,985

SYSTEMS AND METHODS FOR MANIPULATING ELECTRONIC CONTENT BASED ON SPEECH RECOGNITION

Oath Inc., Dulles, VA (U...

1. A computer-implemented method comprising the following operations performed by at least one processor:detecting speaker segments within a plurality of electronic media content items, each of the plurality of electronic media content items being associated with media metadata;
determining, by the processor, at least one individual speaker associated with each of the speaker segments based on a speaker speech fingerprint;
determining, by the processor, speaker metadata associated with the at least one individual speaker;
receiving a search query from a user requesting a ranking of one or more electronic media content items;
determining, by the processor, a first ranked list comprising a first subset of the plurality of electronic media content items, based on a correspondence between the search query and the media metadata;
determining, by the processor, a second ranked list comprising a second subset of the plurality of electronic media content items, based on a correspondence between the speaker metadata and the search query;
processing, by the processor, the first ranked list and the second ranked list to determine a final ranking value for each of a third subset of the plurality of electronic media content items;
generating a third ranked list based on the final ranking value for each of the third subset of the plurality of electronic media content items; and
transmitting and displaying the third ranked list to the user.

US Pat. No. 10,657,984

REGENERATION OF WIDEBAND SPEECH

SKYPE, Dublin (IE)

1. A method for regeneration of wideband speech, comprising:receiving samples of a narrowband speech signal having a first range of frequencies, wherein a first portion of a range of frequencies in a wideband speech signal is represented in the narrowband speech signal;
identifying, based on a characteristic of the narrowband speech signal, frequencies in the first range of frequencies to translate into a target band of a regenerated speech signal, the characteristic being determined from a pitch-dependent spectral translation as approximating a harmonic structure in a second portion of the range of frequencies in the wideband speech signal, wherein the second portion of the range of frequencies is excluded from being represented in the narrowband speech signal;
modulating the identified frequencies in the first range of frequencies of the received samples of the narrowband speech signal with a modulation signal, the modulation signal having a modulating frequency adapted to upshift the identified frequencies in the first range of frequencies into the target band;
filtering the modulated samples, using a target band filter, to form the regenerated speech signal in the target band; and
combining the narrowband speech signal with the regenerated speech signal to produce a new wideband speech signal.

US Pat. No. 10,657,983

AUTOMATIC GAIN CONTROL FOR SPEECH RECOGNITION

Intel Corporation, Santa...

1. A system for automatic gain control for speech recognition, the system comprising:a sampler to obtain an audio signal;
a signal processor to derive a signal-to-noise ratio (SNR) from the audio signal;
a comparator to compare the SNR to a threshold; and
a controller to:
update a single stored gain value and refrain from applying the stored gain value when the SNR is beyond the threshold, wherein, to update the gain value, the controller stores a time-smoothed result of an addition of a gain headroom value and a previous gain value for each consecutive frame from the audio signal when the SNR is beyond the threshold; and
apply the updated stored gain value to a descendant of the audio signal when the SNR is not beyond the threshold, wherein the controller does not update the stored gain value when the SNR is not beyond the threshold.

US Pat. No. 10,657,982

CONTROL PARAMETER DEPENDENT AUDIO SIGNAL PROCESSING

Nokia Technologies Oy, E...

27. An apparatus comprising:at least one speaker comprising at least one frame configured to be worn or carried by a user;
at least two microphones on the at least one speaker;
a controller comprising a processor, where the at least one speaker and the at least two microphones are connected to the controller; and
a plurality of sensors on the at least one frame, where the plurality of sensors comprise at least one optical sensor and at least one motion sensor where the plurality of sensors are connected to the controller, where, based at least partially upon at least one signal from the plurality of sensors the controller is configured to select a context detection mode, regarding a hazard or a possible hazard to the user, from a plurality of modes, where, in the context detection mode, the controller is configured to adjust rendering of audio signals, received from the at least two microphones, to the user by the at least one speaker based upon the hazard or possible hazard to the user.

US Pat. No. 10,657,981

ACOUSTIC ECHO CANCELLATION WITH LOUDSPEAKER CANCELING BEAMFORMER

Amazon Technologies, Inc....

13. A system comprising:at least one processor; and
memory including instructions operable to be executed by the at least one processor to cause the system to:
receive first audio data associated with a first microphone;
receive second audio data associated with a second microphone;
determine a first filter coefficient value corresponding to at least one loudspeaker, the first filter coefficient value associated with the first microphone;
determine a second filter coefficient value corresponding to the at least one loudspeaker, the second filter coefficient value associated with the second microphone;
generate a first portion of third audio data based on the first audio data and the first filter coefficient value, the third audio data including a first representation of first acoustic noise generated by the at least one loudspeaker;
generate a second portion of the third audio data based on the second audio data and the second filter coefficient value;
generate fourth audio data by subtracting at least a portion of the third audio data from the first audio data; and
generate fifth audio data by subtracting at least a portion of the third audio data from the second audio data.

US Pat. No. 10,657,980

DENOISING A SIGNAL

International Business Ma...

1. A computer-implemented method, comprising:creating a clean dictionary, utilizing a clean signal, including converting the clean signal into a plurality of clean spectro-temporal building blocks;
creating a noisy dictionary, utilizing a first noisy signal;
determining a time varying projection, utilizing the clean dictionary and the noisy dictionary; and
denoising a second noisy signal, utilizing the time varying projection.

US Pat. No. 10,657,979

DECODER FOR GENERATING A FREQUENCY ENHANCED AUDIO SIGNAL, METHOD OF DECODING, ENCODER FOR GENERATING AN ENCODED SIGNAL AND METHOD OF ENCODING USING COMPACT SELECTION SIDE INFORMATION

Fraunhofer-Gesellschaft z...

1. A decoder for generating a frequency enhanced audio signal, comprising:a feature extractor configured for extracting a feature from a core signal;
a side information extractor configured for extracting a selection side information associated with the core signal;
a parameter generator configured for generating a parametric representation for estimating a spectral range of the frequency enhanced audio signal not defined by the core signal, wherein the parameter generator is configured to provide a number of parametric representation alternatives in response to the feature, and wherein the parameter generator is configured to select one of the parametric representation alternatives as the parametric representation in response to the selection side information;
a signal estimator configured for estimating the frequency enhanced audio signal using the parametric representation selected; and
a signal classifier configured for classifying a frame of the core signal,
wherein the parameter generator is configured to use a first statistical model, when a signal frame is classified to belong to a first class of signals and to use a second different statistical model, when the frame is classified into a second different class of signals
wherein one or more of the feature extractor, the side information extractor, the parameter generator, the signal estimator and the signal classifier is implemented, at least in part, by one or more hardware elements of the apparatus.

US Pat. No. 10,657,978

BROADCAST TRANSMITTING APPARATUS AND BROADCAST TRANSMITTING METHOD FOR PROVIDING AN OBJECT-BASED AUDIO, AND BROADCAST PLAYBACK APPARATUS AND BROADCAST PLAYBACK METHOD

Electronics and Telecommu...

1. A broadcast playback apparatus, comprising:a multichannel audio signal determining unit to determine whether an encoded multichannel audio signal in a bitstream is an object-based audio signal, based on audio identification information to indicate whether the multichannel audio signal is an object-based audio signal;
an audio decoder to decode the encoded multichannel audio signal, when encoded the multichannel audio signal is the object-based audio signal; and
a downmixing unit to downmix the multichannel audio signal to a stereo audio signal based on (i) mixing information selected by a user from among input mixing information or (ii) mixing information inputted by a user, when the encoded multichannel audio signal is determined to be the object-based audio signal,
wherein the mixing information is mixing ratio of a sound source related to the object-based audio signal.

US Pat. No. 10,657,977

METHOD FOR PROCESSING SPEECH/AUDIO SIGNAL AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A method for processing a speech/audio signal, wherein the method comprises:receiving a bitstream;
decoding the bitstream to obtain a speech/audio signal;
determining a first speech/audio signal according to the speech/audio signal, wherein the first speech/audio signal includes a noise component;
determining a symbol of each sample value in the first speech/audio signal and an amplitude value of each sample value in the first speech/audio signal;
determining an adaptive normalization length;
determining an adjusted amplitude value of each sample value according to the adaptive normalization length and the amplitude value of each sample value;
reconstructing the noise component of the first speech/audio signal by determining a second speech/audio signal according to the symbol of each sample value and the adjusted amplitude value of each sample value;
wherein determining an adjusted amplitude value of each sample value comprises:
calculating, according to the amplitude value of each sample value and the adaptive normalization length, an average amplitude value corresponding to each sample value and determining, according to the average amplitude value corresponding to each sample value, an amplitude disturbance value corresponding to each sample value; wherein, the average amplitude value corresponding to each sample value is the average amplitude value of the sum of values of all sample values in the subband to which the sample value belongs relative to the adaptive normalization length; and
calculating the adjusted amplitude value of each sample value according to the amplitude value of each sample value and according to the amplitude disturbance value corresponding to each sample value.

US Pat. No. 10,657,976

SIGNAL ENCODING METHOD AND APPARATUS, AND SIGNAL DECODING METHOD AND APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. A spectrum encoding method for an input signal including at least one of a speech signal and an audio signal in an encoding device, the spectrum encoding method comprising:selecting an encoding method for a band between uniform scalar quantization (USQ) and trellis coded quantization (TCQ) based on bits allocated to the band;
scaling spectral components in the band based on the bits allocated to the band;
selecting important spectral components in the band based on the scaled spectral components in the band;
encoding information about the important spectral components in the band by using the selected encoding method; and
generating a bitstream including a result of the encoding, for reconstruction of the input signal.

US Pat. No. 10,657,975

PARAMETRIC JOINT-CODING OF AUDIO SOURCES

FRAUNHOFER-GESELLSCHAFT Z...

1. A method for synthesizing a plurality of audio channels, comprising:retrieving from an audio stream at least one sum signal representing a sum of source signals,
retrieving from the audio stream statistical information about one or more source signals,
receiving from the audio stream, or determining locally, parameters describing an output audio format and source mixing parameters,
computing output mixer parameters from the received statistical information, the parameters describing an output audio format, and the source mixing parameters, and
synthesizing the plurality of audio channels from the at least one sum signal based on the computed output mixer parameters,
wherein the at least one sum signal is a mono signal and the plurality of audio channels is a stereo signal.

US Pat. No. 10,657,974

PRIORITY INFORMATION FOR HIGHER ORDER AMBISONIC AUDIO DATA

Qualcomm Incorporated, S...

1. A device configured to compress higher order ambisonic audio data representative of a soundfield, the device comprising:a memory configured to store higher order ambisonic coefficients of the higher order ambisonic audio data, the higher order ambisonic coefficients representative of a soundfield; and
one or more processors configured to:
decompose the higher order ambisonic coefficients into a sound component and a corresponding spatial component, the corresponding spatial component defining shape, width, and directions of the sound component in a spherical harmonic domain;
determine, based on one or more of the sound component and the corresponding spatial component, priority information indicative of a priority of the sound component relative to other sound components of the soundfield; and
specify, in a data object representative of a compressed version of the higher order ambisonic audio data, the sound component and the priority information.

US Pat. No. 10,657,973

METHOD, APPARATUS AND SYSTEM

SONY CORPORATION, Tokyo ...

1. A method, comprising:decomposing a magnitude part of a signal spectrum of a mixture signal into a plurality of spectral components, each spectral component of the plurality of spectral components comprising a frequency component and a time component;
applying an inverse short-time Fourier transform (ISTFT) to the plurality of spectral components to generate a plurality of time components; and
clustering the plurality of time components, in a time domain and based on an iterative algorithm, to obtain one or more clusters of time components, the iterative algorithm minimizing an energy of a compression error of estimated source signals.

US Pat. No. 10,657,972

METHOD OF TRANSLATING AND SYNTHESIZING A FOREIGN LANGUAGE

1. A method of translating and synthesizing a foreign language with original emotional and tonal characteristics using a computer comprising the steps of:separating a source video into independent source language audio and source image streams;
performing a transcription on an isolated block of said source language audio to generate a source language text;
translating said source language text into a selected target language and forming a target language text file;
generating a synthetic target language audio from said target language text file;
creating a synthetic markup language string using input parameters from said source language text coupled with said target language text file;
converting said synthetic markup language string into a target language audio stream file;
collecting data from said independent source language audio and source image stream, wherein the collecting comprises identification of a key speaker's face, measurement of the face, facial landmark detection comprising: lips and jawline orientation, and a color contour;
importing said target language audio stream file;
generate a morphological lip, tongue, teeth, and jaw synchronization movement file based on said target language audio stream file;
synchronizing the morphological lip, tongue, teeth, and jaw synchronization movement file with the collected data to generate a rendered and composited target image stream, wherein the compositing comprises using each column of color pixel values of the source image, performing a linear transformation on the pixels in each of the columns to yield a target image stream;
encoding the target language audio stream file and the target image stream onto a single target video stream.

US Pat. No. 10,657,971

SYSTEMS AND METHODS FOR DETECTING SUSPICIOUS VOICE CALLS

NortonLifeLock Inc., Tem...

1. A computer-implemented method for detecting suspicious voice calls, at least a portion of the method being performed by a computing device comprising at least one processor, the method comprising:identifying, by the computing device, an incoming voice call;
extracting, by the computing device and from audio of the incoming voice call, a plurality of characteristics of the audio of the incoming voice call;
calculating a trustworthiness score of the plurality of the characteristics based at least in part on analyzing a recipient response to the incoming voice call that was made, within the incoming voice call, by a recipient of the incoming voice call and further at least in part on individual trustworthiness scores for each of a geolocation of the call, background noise of the call, a tone of voice of a caller of the call, and keywords used by the caller; and
providing the plurality of characteristics and the trustworthiness score of the plurality of characteristics to a reputation database that:
stores the plurality of characteristics and the trustworthiness score of the plurality of characteristics;
receives a request to evaluate an additional incoming voice call, wherein the request originates from an additional computing device and includes an additional plurality of characteristics extracted from audio of the additional incoming voice call to the additional computing device;
determines that the additional plurality of characteristics matches the plurality of characteristics; and
in response to determining that the additional plurality of characteristics matches the plurality of characteristics, enables the additional computing device to perform a security action on the additional incoming voice call by sending the trustworthiness score for the plurality of characteristics to the additional computing device.

US Pat. No. 10,657,970

VOICE CONTROLLED ASSISTANT WITH COAXIAL SPEAKER AND MICROPHONE ARRANGEMENT

Amazon Technologies, Inc....

1. A device, comprising:a housing;
a speaker;
a microphone disposed at least partly within the housing;
one or more processors; and
non-transitory computer-readable media configured with instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
receiving audio data representing audio captured by the microphone;
sending the audio data to a remote system; and
receiving, from the remote system, an indication that a communication channel has been established between the device and a remote device based at least in part on the audio data.

US Pat. No. 10,657,969

IDENTITY VERIFICATION METHOD AND APPARATUS BASED ON VOICEPRINT

FUJITSU LIMITED, Kawasak...

1. An identity verification method based on a voiceprint, comprising:receiving an unknown voice;
extracting the voiceprint of the unknown voice using a neural network-based voiceprint extractor which is obtained through pre-training;
concatenating the extracted voiceprint with a pre-stored voiceprint to obtain a concatenated voiceprint; and
performing judgment on the concatenated voiceprint using a pre-trained classification model, to verify whether the extracted voiceprint and the pre-stored voiceprint are from a same person.

US Pat. No. 10,657,968

CONTROLLING DEVICE OUTPUT ACCORDING TO A DETERMINED CONDITION OF A USER

GOOGLE LLC, Mountain Vie...

1. A method implemented by one or more processors that are incorporated into a computing device or in communication with the computing device, the method comprising:receiving, from a user, a spoken utterance corresponding to a request for an automated assistant to cause media to be rendered, the media having a fixed duration with a total length of playback time;
in response to receiving the spoken utterance, causing the computing device, from which the automated assistant is accessible, to render the media in furtherance of the media reaching a final point in the total length of the playback time, wherein the computing device provides access to the automated assistant and is located in an environment;
processing, based on the media being rendered and based on the spoken utterance, data that is obtained from one or more sensors located in the environment and/or associated with the user and that characterizes one or more physiological attributes of the user when the user is located in the environment in which the media is being rendered;
determining, based on the processing of the data, that the user has progressed closer to a sleep state or to the sleep state; and
generating, subsequent to receiving the spoken utterance and in response to determining that the user has progressed closer to the sleep state or to the sleep state, a timestamp corresponding to a temporal position, within the total length of the playback time, at which the user progressed closer to the sleep state or to the sleep state during playback of the media.

US Pat. No. 10,657,967

METHOD AND APPARATUS FOR EXECUTING VOICE COMMAND IN ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:one or more microphones;
a communication module;
a display unit; and
one or more processors, wherein the one or more processors are configured to:
receive a voice signal including wakeup command, a voice command subsequent to the wakeup command, and a duration of silence between the wakeup command and the voice command through the one or more microphones while displaying a lock screen in a locked state of the display unit,
recognize the wakeup command in the voice signal,
in response to recognizing the wakeup command in the voice signal, change the lock screen to a screen for a voice command function including a visual object related to voice recognition while maintaining the locked state of the display unit, the visual object being indicative of the voice command function being activated,
transmit a signal including the voice command of the voice signal through the communication module to a server for conducting speech recognition on the voice command,
display, through the display unit and after the wakeup command and before execution of the voice command, a text, which is received from the server, the text indicating that the server is conducting the speech recognition on the voice command, and
after displaying the text, perform an operation responsive to a control signal, corresponding to the recognized voice command, received from the server.

US Pat. No. 10,657,966

BETTER RESOLUTION WHEN REFERENCING TO CONCEPTS

APPLE INC., Cupertino, C...

1. A non-transitory computer-readable storage medium storing one or more programs configured to be executed by one or more processors of an electronic device, the one or more programs including instructions for:receiving user speech input;
determining, from a plurality of domains, a primary domain corresponding to a textual representation of the user speech input;
identifying, from the textual representation, a first substring that corresponds to a first concept of the primary domain;
parsing the first substring to determine a secondary domain of the plurality of domains;
based on the secondary domain, obtaining a data item corresponding to the first substring; and
in accordance with determining that the data item is valid for resolving the first concept of the primary domain:
extracting, from the data item, a parameter value for the first concept of the primary domain;
invoking a service based on the primary domain to produce a result using the parameter value for the first concept; and
outputting the result.

US Pat. No. 10,657,965

CONVERSATIONAL AUDIO ASSISTANT

BOSE CORPORATION, Framin...

1. A speaker system comprising:at least one speaker including an acoustic transducer having a sound-radiating surface for providing an audio output;
at least one microphone for receiving an audio input from a user; and
a control system stored in a memory that is coupled with the at least one speaker and the at least one microphone, the control system comprising instructions for execution by a processor, which when executed, cause the processor to:
analyze the audio input for a non-specific request from the user; and
provide an audio sample to the user along with a prompt for feedback about the audio sample in response to the non-specific request,
wherein the control system maintains the at least one microphone in a query mode during the providing of the audio sample,
wherein the prompt for feedback comprises an audio prompt that is output through the at least one speaker, wherein the query mode comprises an optional response mode, wherein the processor maintains the at least one microphone in the optional response mode for a set period without requiring a wake word, and wherein the audio prompt that is output through the at least one speaker is provided at an equal or greater volume to the user than the audio sample.

US Pat. No. 10,657,964

METHOD FOR CONTROLLING SMART DEVICE, COMPUTER DEVICE AND STORAGE MEDIUM

BAIDU ONLINE NETWORK TECH...

1. A method for controlling a smart device, comprising:performing speech recognition on a speech signal acquired by the smart device;
determining whether a control instruction corresponding to the speech signal matches with a present operation scene of the smart device; and
adjusting an operation state of the smart device according to the control instruction when the control instruction matches with the present operation scene;
after determining whether the control instruction corresponding to the speech signal matches with the present operation scene of the smart device, further comprising:
determining whether the control instruction collides with the present operation scene when the control instruction does not match with the present operation scene;
discarding the control instruction when the control instruction collides with the present operation scene; and
executing the control instruction when the control instruction does not collide with the present operation scene;
wherein determining whether the control instruction corresponding to the speech signal matches with the present operation scene of the smart device comprises:
determining whether the control instruction corresponding to the speech signal matches with the present operation scene of the smart device in response to determining that the speech signal does not contain a preset wake-up word;
wherein determining whether the control instruction collides with the present operation scene comprises:
determining whether the control instruction needs to be executed in background or foreground;
determining that the control instruction collides with the present operation scene in response to determining that the control instruction needs to be executed in the foreground; and
determining that the control instruction does not collide with the present operation scene in response to determining that the control instruction needs to be executed in the background.

US Pat. No. 10,657,963

METHOD AND SYSTEM FOR PROCESSING USER COMMAND TO PROVIDE AND ADJUST OPERATION OF ELECTRONIC DEVICE BY ANALYZING PRESENTATION OF USER SPEECH

NAVER Corporation, Seong...

1. A non-transitory computer-readable recording medium storing instructions that, when executed by a processor of an electronic device, cause the processor to perform a user command processing method comprising:managing at least one pre-defined operation to be performed according to a user command and a plurality of options preset in relation to each of the at least one pre-defined operation for modifying a corresponding pre-defined operation, wherein the corresponding pre-defined operation modified by one of the plurality of options performs a different operation than the corresponding pre-defined operation modified by another of the plurality of options;
receiving the user command including at least a voice input received from a user;
selecting an operation from the at least one pre-defined operation corresponding to a keyword extracted from the voice input;
determining at least one option according to a presentation of the voice input; and
performing the selected operation as modified by the determined at least one option.

US Pat. No. 10,657,962

MODELING MULTIPARTY CONVERSATION DYNAMICS: SPEAKER, RESPONSE, ADDRESSEE SELECTION USING A NOVEL DEEP LEARNING APPROACH

International Business Ma...

1. A computer implemented method for modeling multi-party dialog interactions using deep learning to build automated agents for social and enterprise networking channels, the method comprising:learning, directly from data obtained from a multi-party conversational channel, to identify particular multi-party dialog threads as well as speakers in one or more conversations, by:
during training, from a multi-party dialog, converting each participant utterance to a continuous vector representation and updating a model of the multi-party dialog relative to each participant utterance in the multi-party dialog according to each participant's utterance role selected from a set of: sender, addressee, or observer;
training the model to choose a correct addressee and a correct response for each participant utterance, using a joint selection criterion;
during testing, parsing data obtained from the multi-party conversational channel to identify and classify individual participant utterances regarding whether each participant utterance belongs in a particular multi-party dialog thread, by choosing for each identified participant utterance a finite list of correct next identified participant utterance and an addressee of the correct next identified participant utterance in the particular multi-party dialog thread; and
learning, directly from the data obtained from the multi-party conversational channel, which dialog turns belong to each particular multi-party dialog thread, by:
during training, from the continuous vector representation, updating the model of the multi-party dialog on a specific dialog topic and training the model to select whether each participant utterance belongs in the dialog topic or not; andduring testing, parsing data obtained from the multi-party conversational channel to classify each participant utterance by converting the participant utterance to a continuous vector representation regarding whether each participant utterance belongs to a dialog topic or not;storing the model in a working selection model database in a storage memory repository; and
an automated agent, using and updating the model stored in the working selection model database, by:
monitoring utterances from participants in a multi-party conversation in a multi-party conversational channel;
automatically inserting the automated agent into the multi-party conversation as a participant in the multi-party conversation; and
sending, with the automated agent, one or more automated agent utterances into the multi-party conversation in response to utterances sent by other participants in the multi-party conversation, the automated agent response utterances providing answers to technical support and customer care questions that the automated agent determined were in the monitored utterances from the other participants in the multi-party conversation, the automated agent response utterances being selected, and an addressee of each automated agent response utterance being selected, by the automated agent to provide accurate answers to the questions based on a conditional probability of the selected addressee being the correct addressee given the selected response utterance and vice versa, thereby selecting the addressee and response utterance pair by maximizing a joint probability.

US Pat. No. 10,657,961

INTERPRETING AND ACTING UPON COMMANDS THAT INVOLVE SHARING INFORMATION WITH REMOTE DEVICES

Apple Inc., Cupertino, C...

1. A non-transitory computer-readable storage medium storing instructions for operating a digital assistant, the instructions, when executed by one or more processors of an electronic device, cause the processors to perform operations comprising:receiving a user utterance;
parsing a text representation of the user utterance to determine a domain corresponding to the user utterance, the domain selected from a plurality of domains of an ontology; and
in accordance with the domain corresponding to an actionable intent of sharing an information item with a third party recipient:
determining, from a first portion of the text representation, a first property value for a third party recipient property node of the domain;
determining, from a second portion of the text representation, a second property value for an information item property node of the domain; and
executing a task flow corresponding to the domain, wherein executing the task flow causes data corresponding to the second property value to be retrieved and sent to a second electronic device corresponding to the first property value,
wherein causing the data to be retrieved comprises performing a search query based on one or more search parameters corresponding to the second property value, wherein the retrieved data includes one or more results obtained from performing the search query.

US Pat. No. 10,657,960

INTERACTIVE SYSTEM, TERMINAL, METHOD OF CONTROLLING DIALOG, AND PROGRAM FOR CAUSING COMPUTER TO FUNCTION AS INTERACTIVE SYSTEM

SHARP KABUSHIKI KAISHA, ...

1. A dialog system comprising:an episode storage unit for storing episodes;
a personal information storage unit for storing user information;
a person identifying unit for identifying a user having a dialog with the dialog system based on a result of a voice recognition process and the user information stored in the personal information storage unit;
an extraction unit for extracting one or more events related to the dialog from the dialog with the user and extracting an episode related to the extracted one or more events from the episode storage unit;
an episode evaluation unit for making an evaluation of the extracted episode, the evaluation being performed in accordance with a predefined criterion;
a generation unit for generating a dialog content suitable for the identified user, based on the extracted episode, personal information of the identified user, and a result of the evaluation; and
an output unit for outputting the generated dialog content.

US Pat. No. 10,657,959

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

SONY CORPORATION, Tokyo ...

1. An information processing device comprising:circuitry configured to
control a speech output of an expression related to a function among a set of expressions by an audio output unit,
control an output of information different from the speech output of the expression and related to the function and the expression at a time synchronized with timing information indicating a timing at which the speech output of the expression is made,
control a speech output of another expression related to another function among the set of expressions by the audio output unit, and
control an output of other information different from the speech output of the another expression and related to the another function and the another expression at another time synchronized with another timing information indicating a timing at which the speech output of the another expression is made,
wherein the outputting of the information is controlled to begin an operation of the information at the time synchronized with the timing information and controlled to finish the operation of the information within a predetermined period of time after the timing at which the speech output of the expression is made,
wherein the outputting of the information is controlled to begin another operation of the information related to the expression at the another time synchronized with the another timing information simultaneously with the outputting of the other information related to the another expression, and controlled to finish the another operation of the information within a predetermined period of time after the timing at which the speech output of the another expression is made, and
wherein the another operation is opposite to the operation.

US Pat. No. 10,657,958

ONLINE TARGET-SPEECH EXTRACTION METHOD FOR ROBUST AUTOMATIC SPEECH RECOGNITION

SOGANG UNIVERSITY RESEARC...

1. A target speech signal extraction method of extracting a target speech signal from input signals input to at least two or more microphones for robust speech recognition, by a processor of a speech recognition apparatus, comprising:(a) receiving information on a direction of arrival of the target speech source with respect to the microphones;
(b) generating a nullformer for removing the target speech signal from the input signals and estimating noise by using the information on the direction of arrival of the target speech source;
(c) setting a real output of the target speech source using an adaptive vector w(k) as a first channel and setting a dummy output by the nullformer as a remaining channel;
(d) setting a cost function for minimizing dependency between the real output of the target speech source and the dummy output using the nullformer by performing independent component analysis (ICA); and
(e) estimating the target speech signal by using the cost function, thereby extracting the target speech signal from the input signals,
wherein the direction of arrival of the target speech source is a separation angle ?target formed between a vertical line in the microphone and the target speech source, and
wherein the nullformer for generating the dummy output is obtained by using the separation angle ?target and is fixed to provide noise estimation.

US Pat. No. 10,657,957

REAL-TIME VOICE PROCESSING SYSTEMS AND METHODS

Groupe Allo Media SAS, P...

1. A computer-implemented method for transcribing spoken words to text, the method comprising:electronically monitoring a telephonic interaction, the interaction comprising at least two different channels;
while monitoring the telephonic interaction, assigning a different one of a plurality of context-based speech recognition models to each of the at least two different channels; and
while monitoring the telephonic interaction, transcribing the monitored telephonic interaction from speech to text based on the different assigned models,
wherein the plurality of context-based speech recognition models are organized in a hierarchical structure and wherein the hierarchical structure comprises a language level, a role level and a term level.

US Pat. No. 10,657,956

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. An information processing device, comprising:an acquiring unit configured to acquire context information in a period related to collection of a voice, the context information including information of a speed of speech; and
a control unit configured to cause a predetermined output unit to output output information related to the collection of the voice in a mode corresponding to the acquired context information,
wherein the mode corresponding to the acquired context information is a speed-emphasized mode or an accuracy-emphasized mode, and
wherein the acquiring unit, the control unit, and the predetermined output unit are each implemented via at least one processor.

US Pat. No. 10,657,955

SYSTEMS AND METHODS FOR PRINCIPLED BIAS REDUCTION IN PRODUCTION SPEECH MODELS

Baidu USA LLC, Sunnyvale...

1. A computer-implemented method for automatic speech recognition comprising:receiving an input audio comprising an utterance;
generating a set of spectrogram frames for the utterance;
dividing a representation of the utterance related to the set of spectrogram frames into a plurality of chunks that overlap;
processing the representation of the utterance in forward recurrence in a recurrent neural network (RNN);
processing at least some of the plurality of chunks in backward recurrence in the RNN; and
using hidden states of the backward recurrences obtained from at least some of the chunks to calculate a final output of the RNN.

US Pat. No. 10,657,954

MEETING AUDIO CAPTURE AND TRANSCRIPTION IN A COLLABORATIVE DOCUMENT CONTEXT

Dropbox, Inc., San Franc...

1. A computer-implemented method comprising:storing, at a content creation system, captured meeting audio data in association with a pre-existing collaboration document including speech of one or more speakers and including additional text that existed in the pre-existing collaboration document prior to the speech being uttered;
modifying, by the content creation system, the pre-existing collaboration document to be an updated collaboration document by transcribing the captured meeting audio data into a transcript and integrating the transcript with the additional text that existed in the pre-existing collaboration document, the transcript including text representative of the speech indexed such that portions of the text representative of the speech are mapped to portions of the meeting audio data including the speech;
receiving, by the content creation system, a search query;
performing, by the content creation system, a document search of the updated collaboration document, including a search through the additional text and the transcript, based on the search query;
identifying, by the content creation system, portions of the text representative of the speech that correspond to the received search query;
receiving, by the content creation system, a selection of an identified portion of the text;
identifying, by the content creation system, a portion of the captured meeting audio data corresponding to the selected portion of the text; and
causing playback, by the content creation system, of the identified portion of the captured meeting audio data.

US Pat. No. 10,657,953

ARTIFICIAL INTELLIGENCE VOICE RECOGNITION APPARATUS AND VOICE RECOGNITION

LG ELECTRONICS INC., Seo...

1. A voice recognition apparatus comprising:a microphone configured to receive a voice command;
a memory configured to store a first voice recognition algorithm;
a communication module configured to transmit the voice command to a server system and receive update data regarding the first voice recognition algorithm from the server system; and
a controller electrically connected to the communication module and the memory, and configured to perform control to update the first voice recognition algorithm, which is stored in the memory, based on the update data regarding the first voice recognition algorithm,
wherein the memory stores the update data regarding the first voice recognition algorithm, and
wherein when the update data regarding the first voice recognition algorithm is received, the controller provides a menu for setting a start time for updating using the update data.

US Pat. No. 10,657,952

SCORE TREND ANALYSIS FOR REDUCED LATENCY AUTOMATIC SPEECH RECOGNITION

Intel IP Corporation, Sa...

1. A processor-implemented method for reduced latency automatic speech recognition (ASR), the method comprising:generating, by a processor-based system, one or more complete-phrase hypotheses from a segment of speech, each complete-phrase hypothesis associated with a likelihood score;
generating, by the processor-based system, one or more partial-phrase hypotheses from the segment of speech, each partial-phrase hypothesis associated with a likelihood score;
selecting, by the processor-based system, one of the complete-phrase hypotheses associated with a highest of the complete-phrase hypotheses likelihood scores;
selecting, by the processor-based system, one of the partial-phrase hypotheses associated with a highest of the partial-phrase hypotheses likelihood scores;
calculating, by the processor-based system, a relative likelihood score based on a ratio of the likelihood score associated with the selected complete-phrase hypothesis to the likelihood score associated with the selected partial-phrase hypothesis;
calculating, by the processor-based system, a trend of the relative likelihood score as a function of time; and
identifying, by the processor-based system, an endpoint of the speech based on a determination that the trend does not decrease over a selected time period.

US Pat. No. 10,657,951

CONTROLLING SYNTHESIZED SPEECH OUTPUT FROM A VOICE-CONTROLLED DEVICE

International Business Ma...

1. A computer-implemented method on a voice-controlled device for controlling synthesized speech output, the method comprising:detecting, with at least one sensor, whether one person or more than one person is within a first settable distance from the voice-controlled device;
determining whether audio input being received is speech; and
in response to only one person being detected within the first settable distance and the audio input being speech, initiating an output of synthesized speech based on the audio input without waiting for an attention word to be recognized and otherwise waiting for additional criteria before outputting synthesized speech.

US Pat. No. 10,657,950

HEADPHONE TRANSPARENCY, OCCLUSION EFFECT MITIGATION AND WIND NOISE DETECTION

Apple Inc., Cupertino, C...

1. An audio processing system for headphone transparency, comprising:a headphone having a driver, an internal microphone, an accelerometer, and an external microphone; and
an audio processor to:
detect increased wind noise by analyzing one or more of signals from the internal microphone, the external microphone and the accelerometer, wherein the increased wind noise is detected by analyzing a difference in low frequency components of acoustic signals picked up by the internal microphone configured to detect sound waves in an aural canal of a user of the headphone and low frequency components of vibration signals picked up by the accelerometer configured to detect vibrations of bone conduction of the user;
reduce gain of lower frequencies relative to higher frequencies in a first filter that is operating on the signal from the external microphone in a feedforward path, responsive to detecting the increased wind noise;
adjust a second filter, in a feedback path, that is operating on the signal from the accelerometer, wherein the second filter is adjusted based on detecting the increased wind noise; and
combine outputs of the feedforward path and the feedback path to produce a signal for the driver to produce sound in the aural canal of a user of the headphone.

US Pat. No. 10,657,949

SYSTEM AND METHOD FOR INTEGRATING A HOME MEDIA SYSTEM AND OTHER HOME SYSTEMS

Sound United, LLC, Vista...

1. A home entertainment system, the home entertainment system comprising:a central media controller located on a home premises and comprising:
at least one module operable to, at least:
independently manage the presentation of home entertainment media in each of a plurality of media presentation zones located throughout the home premises;
establish a communication link with a controller of another home system, the controller of the other home system being located on the home premises, the controller of the other home system being operable to independently manage a plurality of devices located throughout the home premises, wherein the presentation of the home entertainment media in each of the plurality of media presentation zones located throughout the home premises is independent of the communication link with the controller of the other home system, the other home system comprising:
a home security system; and/or
a home automation system that operates to control temperature, humidity, and/or light; and
communicate with the other home system over the communication link regarding utilization of a resource of the home entertainment system by the other home system.

US Pat. No. 10,657,948

SOUND MASKING IN OPEN-PLAN SPACES USING NATURAL SOUNDS

Rensselaer Polytechnic In...

1. A method of generating sound masking in an open-plan space, comprising:establishing acoustic criteria for the space that specifies minimum output levels at a set of specified frequencies;
selecting natural foreground sound samples and natural background sound samples for mixing as an audio output stream for the space based on sensor data from outside the space and based on an internal state of at least one occupant of the space;
mixing the natural foreground sound samples and natural background sound samples to create a natural audio output stream for use as sound masking when broadcast over at least one speaker using a power amplifier; and
processing the natural audio output stream, wherein the processing includes:
analyzing the audio output stream with a spectrum analyzer to determine if the minimum output levels at the set of specified frequencies are met; and
level adjusting the audio output stream with an equalizer to ensure that minimum output levels at the set of specified frequencies are met;
wherein the natural foreground sound samples and natural background samples include natural sounds such that the sound masking being broadcast forms a natural soundscape.

US Pat. No. 10,657,947

INTEGRATED BROADBAND ACOUSTIC ATTENUATOR

ZIN TECHNOLOGIES, INC., ...

1. An acoustic attenuation assembly comprising:a low frequency sound attenuation device including:
at least one sound attenuation chamber containing a volume and mass of air; and
first and second openings associated with each low frequency chamber and through which excited air resonates, the first and second openings extending through the first sheet into each low frequency chamber, each chamber having an open side; and
a high frequency sound attenuation device secured to the low frequency sound attenuation device and closing the open side of each chamber, the high frequency sound attenuation device including a plurality of projections and being formed from a sound absorbing material that absorbs excited air.

US Pat. No. 10,657,946

DEVICE FOR ABSORBING SOUND WITHIN THE CABIN OF VEHICLE

1. A sound absorbing mat for use within the interior compartment of a vehicle, comprising:a first polyurethane open cell polyester layer having a predefined contour, wherein the first polyurethane open cell polyester layer is at least one quarter of an inch thick, wherein the first polyurethane open cell polyester layer forms to the space of the interior compartment;
a polyvinyl chloride, wherein the polyvinyl chloride is applied to and fuses with the first polyurethane open cell polyester, wherein the polyvinyl chloride takes on the contour of the first polyurethane open cell polyester layer once hardened and is substantially a quarter of an inch thick;
a second polyurethane open cell polyester layer having a top surface and a bottom surface, wherein the bottom surface has a predetermined contour and the top surface is substantially smooth, wherein the second polyurethane open cell polyester layer is at least three quarters of an inch thick and the bottom surface of the second polyurethane open cell polyester layer is fused with the polyvinyl chloride before it is hardened; and
a urethane layer having a grip surface, wherein the urethane layer is at least a quarter inch thick and is mated to the top surface of the second polyurethane open cell polyester layer.

US Pat. No. 10,657,945

NOISE CONTROL METHOD AND DEVICE

BEIJING ZHIGU RUI TUO TEC...

1. A method, comprising:acquiring, by a device comprising a processor, noise information of an ambient environment, wherein the noise information comprises noise sampling information and a corresponding sampling time, and wherein the noise sampling information is sampled from a specific sound frequency interval in which a user has a defined sensitivity to noise; and
judging whether the noise information satisfies a predetermined condition, and in response to the noise information satisfying the predetermined condition, sending a noise control message to another device, wherein the noise control message comprises a noise intensity value, a predetermined threshold and position information of a sender of the noise control message;
the noise control message being configured to notify the other device to make a volume adjustment policy based on the noise intensity value, the predetermined threshold and the position information of the sender of the noise control message.

US Pat. No. 10,657,944

ELECTRONIC CYMBAL ASSEMBLY AND COMPONENTS THEREOF

GEWA music GmbH, Adorf (...

1. An electronic cymbal assembly comprising:a cover, said cover including a noncircular cutout, wherein said noncircular cutout includes at least two flat edges; and
a stopper abutting said cover, wherein said stopper comprises two flat edges abutting said two flat edges of said noncircular cutout.

US Pat. No. 10,657,943

SYSTEMS AND METHODS FOR CALIBRATING A MUSICAL DEVICE

SUNLAND INFORMATION TECHN...

1. A system for calibrating a musical device, comprising:a memory; and
at least one processor configured to communicate with the memory, to:
select a first intensity level from a plurality of predetermined intensity levels, the first intensity level corresponding to a first reference sensor signal according to mapping information;
energize an actuator to actuate a key using a force corresponding to the first intensity level;
obtain, from a sensor, a first sensor signal representing motion information of the key corresponding to application of the force;
calibrate the musical device based at least in part on the first sensor signal by updating the mapping information,
wherein to update the mapping information, the processor is further to:
determine a second intensity level representing a lower limit of the plurality of predetermined intensity levels;
determine a third intensity level representing an upper limit of the plurality of predetermined intensity levels; and
update the mapping information based at least in part on the second intensity level and the third intensity level.

US Pat. No. 10,657,942

SYSTEM AND METHOD FOR PACING REPETITIVE MOTION ACTIVITIES

Pacing Technologies LLC, ...

1. A pacing system comprising:a website adapted to allowing a person to pre-select an activity from a plurality of user-selectable different activity types; and
a software application adapted to running on a data storage and playback device for use in pacing a person while the person is running, wherein the software application is further adapted to at least,
displaying on the data storage and playback device the plurality of user-selectable different activity types to be selected prior to the running, wherein running is one of the displayed pre-selectable activity types;
outputting to a server a numerical value representing a running tempo or pace of the person or information for determining the running tempo or pace of the person, wherein the outputting is in response to either a manual input of a target running tempo or pace of the person or an automatically-determined running tempo or pace of the person, the manual input or the automatic determination being performed prior to the running activity, wherein the information comprises one or more of an age, a gender, a height, and a fitness level stored in a user-profile record associated with the person; and
receiving at the data storage and playback device in response to the outputting of the numerical value or the information, streaming data including at least one music song characterized by a genre or artist preference stored in the user-profile record, having a beat sensible to the person when the song is played by the data storage and playback device, the sensible beat for pacing the person during the running activity by the person matching actual steps taken or every other step taken to the beat of the music.

US Pat. No. 10,657,941

ELECTRONIC MUSICAL INSTRUMENT AND LESSON PROCESSING METHOD FOR ELECTRONIC MUSICAL INSTRUMENT

CASIO COMPUTER CO., LTD.,...

1. An electronic musical instrument, comprising:a plurality of operation elements to be played by a performer, respectively specifying a plurality of notes of different pitches;
a memory having stored thereon a musical piece data of a musical piece, the musical piece data including data of a first note or chord that is to be played by the performer at a first timing of the musical piece, data of a second note or chord that is to be played by the performer at a second timing that follows the first timing of the musical piece, and data of a third note or chord that is to be played by the performer at a third timing that follows the second timing of the musical piece, the first through third notes or chords being included in the plurality of notes that can be specified by the plurality of operation elements, the musical piece data further including data of an accompaniment that accompanies the first, second and third notes or chords to be played by the performer; and
at least one processor,
wherein the at least one processor executes an accompaniment playback process that includes the following:
determining a target melodic interval direction from the first note or chord towards the second note or chord by referencing to the musical piece data, the determined target melodic interval direction being one of ascending, descending, and equal;
determining a performed melodic interval direction by referencing to an operation element or a group of operation elements, among the plurality of operation elements, that is specified by the performer at the second timing relative to an operation element or a group of operation elements, among the plurality of operation elements, that was specified by the performer at the first timing or relative to said first note or chord that was to be played by the performer at the first timing, the determined performed melodic interval direction being one of ascending, descending, and equal;
causing musical sound of the accompaniment to output based on the musical piece data from the second timing to a point in time immediately prior to the third timing only when the performed melodic interval direction matches the target melodic interval direction; and
causing the musical sound of the accompaniment not to output from the second timing to the point in time immediately prior to the third timing when the performed melodic interval direction does not match the target melodic interval direction,
wherein in determining the target melodic interval direction, the at least one processor compares a pitch of the second note, or a representative pitch of the second chord in case of chord, with a pitch of the first note, or a representative pitch of the first chord in case of chord, so as to determine a direction of pitch change from the first note or chord to the second note or chord in the musical piece, and
wherein in determining the performed melodic interval direction, the at least one processor compares a pitch of the operation element or a representative pitch of the group of operation elements that is specified by the performer at the second timing with a pitch of the operation element, or a representative pitch of the group of operation elements, that was specified by the performer at the first timing or with the pitch of the first note, or the representative pitch of the first chord in case of chord, that was to be played at the first timing so as to determine a direction of pitch change from a note or chord that was actually specified by the performer or that should have been specified by the performer at the first timing to a note or chord that is specified by the performer at the second timing.

US Pat. No. 10,657,940

MODULAR ELECTRIC GUITAR PEDALBOARD

1. A plurality of modular pods for a pedalboard comprising,at least two bases where each of the at least two bases comprise a bottom and a sidewall defining a cavity, the sidewall having at least one channel and a slot defining a slot shape;
at least one key sized to extend from the slot of one of the at least two bases to the slot of the other of the at least two bases having a key shape where the key shape cooperatively engages the slot shape to releasably couple the at least two bases; and
a pod plate operatively coupled to the base covering the cavity, the pod plate having at least one port configured to provide access to the cavity.

US Pat. No. 10,657,939

KEYBOARD APPARATUS AND ELECTRONIC KEYBOARD INSTRUMENT

YAMAHA CORPORATION, Hama...

1. A keyboard apparatus, comprising:a plurality of keys arranged along a scale direction with the plurality of keys each extending in a longitudinal direction of the keys different from the scale direction;
at least one frame configured to support at least one key of the plurality of keys;
at least one bendable portion disposed between the at least one key and the frame and having flexibility in the scale direction; and
a coupler configured to couple the at least one bendable portion and the at least one key to each other attachably and detachably,
wherein a first coupler, which couples a first key to a first bendable portion disposed between the first key and the frame, and a second coupler, which couples a second key, adjacent to the first key, to a second bendable portion disposed between the second key and the frame, are disposed respectively at positions different from each other in the longitudinal direction of the keys,
wherein a narrow portion extends from the second coupler toward the second key in the longitudinal direction of the keys, the narrow portion having a width, in the scale direction, less than a width, in the scale direction, of the second coupler, and
wherein the first coupler is opposed to the narrow portion in the scale direction.

US Pat. No. 10,657,938

APPLIANCE WITH USER CUSTOMIZABLE ALERT TUNES

Haier US Appliance Soluti...

1. A method for customizing appliance alert tunes, comprising:downloading a user selected alert tune from a server to an appliance over a network, the user selected alert tune is data corresponding to a plurality of synthesized notes;
saving the user selected alert tune in a memory of the appliance; and
playing the user selected alert tune, rather than a default alert tune, from the memory of the appliance on a sound emitter of the appliance in response to an alert tune activation condition for,
wherein the appliance is one of a clothes dryer, a clothes washer, a dishwasher, a refrigerator, a stove, an oven, a microwave, a cooktop, a range hood, a window air-conditioning unit, and a water heater, and
wherein each note of the plurality of synthesized notes is no greater than twelve bytes within the memory of the appliance.

US Pat. No. 10,657,937

EFFICIENT COMBINED HARMONIC TRANSPOSITION

Dolby International AB, ...

1. A system configured to generate a high frequency component of a signal from a low frequency component of the signal, the system comprising:an analysis filter bank configured to provide a set of analysis subband signals from the low frequency component of the signal; wherein the set of analysis subband signals comprises at least two analysis subband signals;
a nonlinear processing unit configured to determine a set of synthesis subband signals from the set of analysis subband signals; wherein the nonlinear processing unit is configured to determine an nth synthesis subband signal of the set of synthesis subband signals from a kth analysis subband signal and a (k+1)th analysis subband signal of the set of analysis subband signals; wherein a magnitude of the nth synthesis subband signal depends on a transposition factor T; and
a synthesis filter bank configured to generate the high frequency component of the signal based on the set of synthesis subband signals.

US Pat. No. 10,657,936

ELECTRONIC MUSICAL INSTRUMENT, ELECTRONIC MUSICAL INSTRUMENT CONTROL METHOD, AND STORAGE MEDIUM

CASIO COMPUTER CO., LTD.,...

1. An electronic musical instrument comprising:a display;
a memory configured to store a plurality of song data items, each of the plurality of song data items including a plurality of event data items, the plurality of song data items not including size information of each of the plurality of event data items; and
at least one processor configured to:
read at least one song data item from among the plurality of song data items,
add an identifier to each of the plurality of event data items of the read at least one song data item,
calculate size information for each of the plurality of event data items,
associate the size information calculated for each of the plurality of event data items with the corresponding identifier,
display a content of a first event data item,
refer to the associated size information when the content of the first event data item is displayed on the display and a content of a second event data item is not displayed on the display, and
display, in accordance with the associated size information referred to, the content of the second event data item on the display, instead of displaying the content of the first event data item.

US Pat. No. 10,657,935

MAGNUM OPUS METHOD, PROGRAM, AND APP

Debra Diane Lewis, Chica...

1. A method of coding messages within musical compositions comprising of:a. writing an alphanumeric message of any length with characters, numbers, symbols, and/or punctuation marks of an alphanumeric character set;
b. providing a selection of any music scale or music mode;
c. using a C major scale as the provided music scale;
d. depicting piano keys of an 88-key piano keyboard in a diagram;
e. assigning each character, number, symbol and punctuation mark in the alphanumeric character set to a unique position on the individual piano keys of an 88-key piano keyboard in accordance with the C major scale;
f. depicting the unique position of each character, number, symbol and punctuation mark in the alphanumeric character set assigned to the piano keys of an 88-key piano keyboard in accordance with the C major scale;
g. pairing each note of the C major scale on a grand staff graphically represented by Standard Music Notation (SMN) with the piano keys of an 88-key piano keyboard labeled with each character, number, symbol and punctuation mark in the alphanumeric character set in accordance with the C major scale;
h. depicting each (SMN) music note of the C major scale on the grand staff paired with the piano keys of an 88-key piano keyboard and labeled with each character, number, symbol and punctuation mark in the alphanumeric character set in accordance with the C major scale;
i. depicting each (SMN) music note on the grand staff aligned with alphanumeric letters identifying the pitch of each note in accordance with the C major scale;
j. aligning Morse code standard time durations (dots and dashes) with each corresponding character, number, symbol and punctuation mark in the alphanumeric character set assigned to the piano keys of the 88-key piano keyboard in accordance with the C major scale;
k. depicting the Morse code standard time durations (dots and dashes) aligned with each corresponding character, number, symbol and punctuation mark in the alphanumeric character set assigned to the piano keys of the 88-key piano keyboard in accordance with the C major scale;
l. depicting the unaltered sequence of each character, number, symbol and/or punctuation mark in the written alphanumeric message;
m. locating each character, number, symbol and/or punctuation mark of the written alphanumeric message on the piano keys of the 88-key piano keyboard in accordance with the C major scale;
n. locating each (SMN) music note aligned with each piano key corresponding to an unaltered sequence of each character, number, symbol and/or punctuation mark in the written alphanumeric message;
o. depicting the unaltered sequence of each (SMN) music note that is in alignment with each piano key that corresponds to the unaltered sequence of each identical character, number, symbol and/or punctuation mark in the written alphanumeric message derives and creates a coded message melody for a coded message musical composition in accordance with the C major scale; and
p. creating, composing and/or translating (SMN) coded message musical compositions may be accomplished by conjoining any time signature, no time signature and/or Morse code rhythms with the coded message melody derived from the unaltered sequence of each (SMN) music note that is in alignment with each piano key that corresponds to the unaltered sequence of each identical character, number, symbol and/or punctuation mark in the written alphanumeric message in accordance with the C major scale.

US Pat. No. 10,657,934

ENHANCEMENTS FOR MUSICAL COMPOSITION APPLICATIONS

Electronic Arts Inc., Re...

1. A computer-implemented method, the method enabling creation of a musical score via a user interface, wherein the user interface:receives selection of a particular genre associated with the musical score, the particular genre corresponding to a musical constraint, and the musical constraint indicating one or more learned features associated with the genre, wherein receiving selection of the particular genre comprises receiving selection of one or more artists or one or more songs, wherein a system determines the musical constraint based on analyzing the selected artists or songs;
responds to user input indicating musical elements to be included in a representation of the musical score, the musical elements comprising musical notes, wherein the representation updates to present the musical notes; and
presents musical score adjustments based on the user input and particular genre, wherein a presented musical score adjustment comprises information identifying portions of the musical score which are determined to deviate from a musical constraint, and wherein for a particular portion, the user interface;
presents information identifying the particular portion of the musical score which deviates from the musical constraint, and
automatically adjusts the particular portion to correspond with the musical constraint, wherein the system determines the adjustment to one or more musical notes included in the particular portion.

US Pat. No. 10,657,932

TUNING DEVICE FOR STRINGED MUSICAL INSTRUMENT

1. A tuning assembly for tensioning strings of a stringed instrument comprising 2 or more worm gear tuners (300)wherein the worm gears (208) are in axial alignment
and, wherein said tuners are individually rotationally positioned on said worm gear axis such that finger access to the tuner keys (204) is improved.

US Pat. No. 10,657,931

LIGHTWEIGHT BODY CONSTRUCTION FOR STRINGED MUSICAL INSTRUMENTS

Fender Musical Instrument...

1. A method of making a musical instrument, comprising:providing a softwood core;
forming an opening in the softwood core;
disposing a first hardwood plug in the opening of the softwood core;
disposing a first hardwood plate over a first surface of the softwood core;
disposing a second hardwood plate over a second surface of the softwood core, wherein the first hardwood plug extends from the first hardwood plate to the second hardwood plate; and
attaching a bridge to the first hardwood plug.

US Pat. No. 10,657,930

TOPBOARD REFLECTION PREVENTER FOR GRAND PIANO

KABUSHIKI KAISHA KAWAI GA...

1. A topboard reflection preventer for a grand piano, which is attached to an openable and closable topboard formed by a topboard rear and a topboard front, so as to prevent lighting from above from being reflected by the topboard in a state in which the topboard is held open in an inclined position, comprising:a reflection preventer body configured to be attached to the topboard rear and the topboard front folded onto the topboard rear, in a state covering whole upper surfaces of the topboard rear and the topboard front; and
holding means configured to hold the reflection preventer body so as to prevent the reflection preventer body from falling off when the topboard held open in the inclined position, wherein the reflection preventer body includes:
a topboard rear cover section configured to cover the upper surface of the topboard rear, and
a topboard front cover section integrally formed with the topboard rear cover section and configured to cover the upper surface of the topboard front folded onto the topboard rear, and wherein
the topboard rear cover section has a shape substantially the same as a shape of the upper surface of the topboard rear, and wherein the topboard front cover section has a shape substantially the same as a shape of the upper surface of the topboard front and is formed such that the topboard front cover section is continuous with a right front end of the topboard rear cover section and extends rightward.

US Pat. No. 10,657,929

IMAGE DISPLAY SYSTEM WITH IMAGE ROTATION PROCESSING

SHARP KABUSHIKI KAISHA, ...

1. An image display system comprising:an image generating circuit that generates and outputs multiple images;
an image transferring circuit that converts the multiple images to an image transfer signal and outputs the image transfer signal;
an image receiving circuit that receives the image transfer signal and restores the multiple images; and
an image display unit that displays the multiple images restored by the image receiving circuit, wherein
the image receiving circuit includes an image processing circuit that rotates at least one of first and second images if the received image transfer signal includes the first and second images in which a direction in which a scan line of the first image extends is different from a direction in which a scan line of the second image extends, and
the image transferring circuit includes
a first line buffer that stores at least a portion of image data indicating the first image and arranged in the direction in which the scan line of the first image extends,
a second line buffer that stores at least a portion of image data indicating the second image and arranged in the direction in which the scan line of the second image extends, and
an image transmitting circuit that transmits, to the image receiving circuit, the image data pieces for transfer stored in the first and second line buffers.

US Pat. No. 10,657,928

PROJECTED CONTENT BASED DISPLAY DEVICE AND DISPLAY METHOD

SONY CORPORATION, Tokyo ...

1. A display device, comprising:a display screen;
a projector on a rear surface of the display screen, wherein
the projector is in a first direction intersecting with a second direction perpendicular to a display surface of the display screen; and
a central processing unit (CPU) configured to:
acquire content reservation information of first content, wherein
the content reservation information indicates a start time of the first content and a URL associated with the first content, and
the URL indicates a storage location of a text associated with the content reservation information;
determine a current time is prior to the start time of the first content;
add a first display effect on a projection screen based on a turned-off state of the display screen and the determination the current time is prior to the start time of the first content;
control, based on the turned-off state of the display screen and the determination the current time is prior to the start time of the first content, the projector to project the text associated with the content reservation information on the projection screen, wherein
the projection of the text is in a plane parallel to a display surface of the display screen, and
the projection screen is on a rear side of the display surface of the display screen;
determine the current time is equal to the start time of the first content;
turn on power of the display screen based on the determination the current time is equal to the start time of the first content; and
control, based on the determination the current time is equal to the start time of the first content, the display screen to display the first content.

US Pat. No. 10,657,927

SYSTEM FOR PROVIDING HANDS-FREE INPUT TO A COMPUTER

1. A system for providing hands-free input to a computer, comprising:a. one or more artificial cilia mounts attached to an eyelid or eyelash of a user, by which one or more of the artificial cilia extending therefrom are adapted to cause generation of an input command in response to an intentional blinking motion;
b. a computer to which blinking-derived input commands are transmittable, said computer comprising a video card interfacing with a running application on which is temporarily storable data by which output images for display are generatable, and a processor on which is executable a dedicated software module for managing operation of the system;
c. a liquid crystal display (LCD) screen, a plurality of sensors for detecting a blinking-related selection operation being associated with said LCD screen;
d. a head-mounted support structure for mounting said LCD screen within a selection-proximity distance from the artificial cilia;
e. a movement sensor in data communication with the processor of said computer and mounted on said support structure, for detecting a calibrated instantaneous head orientation of said user;
f. means for duplicating a portion of said stored video data or a representation thereof that would cause corresponding images to be viewable by said user on a computer screen in response to said instantaneous head orientation and for displaying said images corresponding to said duplicated portion on said LCD screen; and
g. means for transmitting a signal generated by a corresponding one of said LCD-associated sensors in response to said blinking-related selection operation to said dedicated software module and for converting said transmitted signal to a corresponding input command.

US Pat. No. 10,657,926

MOBILE TERMINAL AND METHOD OF CONTROLLING THE SAME

LG ELECTRONICS INC., Seo...

1. A terminal comprising:a first body and a second body, wherein the first body and the second body are positionable between an open state and a closed state, wherein in the open state a first side of the first body and a first side of the second body are exposed and in the closed state the first side of the first body faces the first side of the second body, and wherein the first body has an edge that extends from the first side of the first body and the second body has an edge that extends from the first side of the second body;
a hinge connecting the first body with the second body, wherein the hinge permits positioning of the first body and the second body;
a display comprising a first display region located on the first side of the first body and the first side of the second body, wherein the display further comprises second and third display regions which each extend from the first display region and which are respectively located at the edges of the first and second bodies; and
a controller configured to:
cause the display to display a first screen on the first display region when in the open state;
cause the display to display information associated with the first screen on the second display region in response to switching from the open state to the closed state;
cause the display to display an icon on either or both of the second or third display regions while in the closed state, wherein the icon is displayed in association with the information displayed on the second display region;
cause the display to stop displaying the information associated with the first screen on the second display region and to display the information on a combined display region that includes both the second display region and the third display region, in response to an input received with regard to the icon, and
vary display position and size of the information relative to a border of the second and third display regions, in further response to the input.

US Pat. No. 10,657,925

DISPLAY DEVICE AND CONTROL METHOD FOR CONVERSION OF LUMINANCE INFORMATION

SEIKO EPSON CORPORATION, ...

1. A display device comprising:a processor configured to generate a third image by combining, on the basis of transmittance, a first image based on first image information and a second image generated by converting luminance information of second image information including the luminance information into the transmittance; and
a display configured to display the third image, wherein
the processor is further configured to
cause the display to display an image for selection corresponding to each of a plurality of kinds of the second image information,
process the second image information corresponding to the image for selection selected from a displayed plurality of the images for selection,
select, from a selectable plurality of conversion systems, a conversion system for converting the luminance information of the second image information into the transmittance, and
combine the second image, the luminance information of which is converted into the transmittance by the conversion system selected by the processor, and the first image.

US Pat. No. 10,657,924

DISPLAY APPARATUS AND OPERATING METHOD THEREOF

InnoLux Corporation, Mia...

1. A display apparatus, comprising:a control unit outputting a first signal; and
a display module coupled to the control unit, the display module continuously displaying a first image in a first frame time based on the first signal, the first image having a first pattern, and a first ratio of an area of the first pattern to an area of the first image ranging from 5% to 30%,
wherein the first pattern at a first time point in the first frame time has a color located at a first coordinate position in a CIE 1931 chromaticity diagram, the first pattern at a second time point in the first frame time has another color located at a second coordinate position in the CIE 1931 chromaticity diagram, and the first coordinate position is different from the second coordinate position;
wherein the first pattern has a first brightness at the first time point in the first frame time, the first pattern has a second brightness at the second time point in the first frame time, the second time point is later than the first time point, and the second brightness is less than the first brightness; and
wherein the first frame time comprises a first period and a second period, the first time point and the second time point are located in the first period, the display module continuously displays the first image in the second period based on the first signal, the first pattern has a third brightness at a third time point in the second period, and the third brightness is less than the first brightness and less than the second brightness.

US Pat. No. 10,657,923

DISPLAY CONTROL CIRCUIT, DISPLAY CONTROL METHOD THEREOF, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display control circuit, comprising:a switch circuit having a first signal input terminal connected to a control terminal, a second signal input terminal connected to a power supply signal terminal, and a power supply signal output terminal; and
a display driving circuit having a first signal input terminal connected to the control terminal, a power supply signal input terminal connected to the power supply signal output terminal of the switch circuit, and a driving signal output terminal,
wherein the switch circuit is configured to receive an operating power supply voltage from the power supply signal terminal via the second signal input terminal and output the operating power supply voltage to the display driving circuit via the power supply signal output terminal under the control of the control terminal.

US Pat. No. 10,657,922

ELECTRONIC DEVICES, METHOD OF TRANSMITTING DATA BLOCK, METHOD OF DETERMINING CONTENTS OF TRANSMISSION SIGNAL, AND TRANSMISSION/RECEPTION SYSTEM

SONY CORPORATION, Tokyo ...

1. An electronic device, comprising:an information receiving unit configured to receive Enhanced Extended Display Identification Data (E-EDID) from a first external device of a plurality of external devices, wherein
the E-EDID comprises a high definition multimedia interface (HDMI) vendor specific data block (VSDB) and a vendor VSDB,
the HDMI VSDB indicates a compatibility status of the first external device,
the compatibility status of the first external device corresponds to a function associated with a conventional HDMI,
the vendor VSDB includes capability information that indicates existence of compatibility of the first external device with an extended function, and
the vendor VSDB comprises a layer field that indicates a connection layer in the vendor VSDB;
a control unit configured to:
determine content of the vendor VSDB is comprehensible, based on compatibility of the electronic device with the extended function; and
increment a value of the layer field in the vendor VSDB based on the determination the content of the vendor VSDB is comprehensible;
an information processing unit configured to:
change values of the HDMI VSDB based on a compatibility status of the electronic device, wherein the compatibility status of the electronic device corresponds to the function associated with the conventional HDMI; and
change values of the vendor VSDB based on the incremented value of the layer field; and
an information transmitting unit configured to transmit the HDMI VSDB including the changed values of the HDMI VSDB and the vendor VSDB including the changed values of the vendor VSDB to a second external device.

US Pat. No. 10,657,921

SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING DEVICE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A shift register unit, comprising:an input circuit, whose first terminal receives an input signal of the shift register unit and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node;
an output circuit, whose first terminal is connected to a first clock signal terminal, second terminal is connected to the pull-up node, and third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a first clock signal of the first clock signal terminal to the output terminal under control of the pull-up node;
a pull-down circuit, whose first terminal is connected to a pull-down node, second terminal is connected to the pull-up node, third terminal is connected to the output terminal, and fourth terminal is connected to a first power supply voltage terminal, the pull-down circuit being configured to pull down the pull-up node and the output terminal to a first power supply voltage of the first power supply voltage terminal under control of the pull-down node;
a first pull-down control circuit, whose first terminal is connected to a second clock signal terminal, second terminal is connected to a first pull-down control node, third terminal is connected to the pull-down node, fourth terminal is connected to the pull-up node, and fifth terminal is connected to the first power supply voltage terminal, the first pull-down control circuit being configured to pull down the pull-down node to the first power supply voltage of the first power supply voltage terminal under control of the pull-up node, and to output a second clock signal of the second clock signal terminal to the pull-down node under control of the first pull-down control node; and
a second pull-down control circuit, whose first terminal is connected to the second clock signal terminal, second terminal is connected to the first power supply voltage terminal, third terminal is connected to the pull-up node, fourth terminal is connected to the first pull-down control node, and fifth terminal is connected to a second power supply voltage terminal, and the second pull-down control circuit being configured to pull down the first pull-down control node to the first power supply voltage of the first power supply voltage terminal when the pull-up node is at a valid pull-up level, and to compensate for the first pull-down control node through a second power supply voltage when the pull-up node is at an invalid pull-up level and the second clock signal is at a first level, so that the first pull-down control node drives the first pull-down control circuit to output the second clock signal to the pull-down node.

US Pat. No. 10,657,920

DISPLAY PANEL, DISPLAY DEVICE AND SIGNAL TRANSMISSION DEVICE

BOE Technology Group Co.,...

1. A display panel, comprising:an array substrate;
an opposed substrate arranged opposite to the array substrate;
a circuit board, disposed on a side of the array substrate away from the opposed substrate;
a driving circuit, disposed on a side of the array substrate close to the opposed substrate;
a light emitter, disposed on a side of the circuit board close to the array substrate and electrically connected with the circuit board, in which the light emitter includes a light emitting surface which faces the array substrate; and
a light receiver, disposed on a side of the array substrate close to the opposed substrate and directly and electrically connected with the driving circuit, in which the light receiver includes a light receiving surface which faces the light emitter,
wherein the light receiver is configured to convert light intensity information received by the light receiving surface into an electrical signal and output the electrical signal to the driving circuit,
the light receiver provides the electrical signal to the driving circuit, the electrical signal is a signal which drives the display panel to display image information,
wherein the display panel further comprises a collimator, and the collimator includes a second focus which is disposed on the light emitting surface, and the collimator is selected from a group consisting of a microlens, an aspherical lens and a spherical lens, the collimator is disposed at a light-exiting side of the light emitter, the collimator is disposed between the light emitter and the light receiver, and a distance of the collimator and the light emitter is an object focal length, and
wherein the display panel further comprises a moving unit which is configured to drive the light emitter to do translational motion during displaying an image.

US Pat. No. 10,657,919

GATE DRIVING CIRCUIT, DRIVING METHOD, AND DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A gate driving circuit, comprising a multi-stage structure, wherein an nth-stage circuit comprises:a Qn node precharge unit, which is configured to control signal transmission between a high-voltage signal VGH and a Qn node under action of a first input signal Qn?1 and a second input signal Qn+1 so as to precharge the Qn node;
a Qn node pull-up unit, which is electrically connected between the Qn node and an output end Gn of a current-stage circuit for maintaining the Qn node in a high-level state;
a Qn node pull-down unit, which is electrically connected between a low-voltage signal VGL and the Qn node for controlling signal transmission between the low-voltage signal VGL and the Qn node under action of a Pn node voltage signal so as to maintain the Qn node in a low-level state;
a Pn node pull-up unit, which is electrically connected between the high-voltage signal VGH and a Pn node for controlling signal transmission between the high-voltage signal VGH and the Pn node under action of a first clock signal so as to maintain the Pn node in a high-level state;
a Pn node pull-down unit, which is electrically connected between the low-voltage signal VGL and the Pn node for controlling signal transmission between the low-voltage signal VGL and the Pn node under action of a Qn node voltage signal so as to maintain the Pn node in a low-level state;
a Gn output unit, which is electrically connected between a second clock signal and the output end Gn of the current-stage circuit for controlling signal transmission between the second clock signal and the output end Gn of the current-stage circuit under action of the Qn node voltage signal so as to output a Gn high-level signal; and
a Gn output end pull-down unit, which is electrically connected between the low-voltage signal VGL and the output end Gn of the current-stage circuit for controlling signal transmission between the low-voltage signal VGL and the output end Gn of the current-stage circuit under action of the Pn node voltage signal so as to maintain the output end Gn of the current-stage circuit in a low-level state,
wherein the first input signal Qn?1 is a Qn?1 node output signal in a previous-stage driving circuit, and the second input signal Qn+1 is a Qn+1 node output signal in a next-stage driving circuit;
wherein the Qn node precharge unit comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein the first transistor has a source connected with the high-voltage signal VGH, a gate connected with the second input signal Qn+1, and a drain connected with a source of the second transistor,
wherein the second transistor has a gate connected with the first input signal Qn?1, and a drain connected with a source of the third transistor and simultaneously connected with the Qn node,
wherein the third transistor has a gate connected with the first input signal Qn?1, and a drain connected with a source of the fourth transistor, and
wherein the fourth transistor has a gate connected with the second input signal Qn+1, and a drain connected with the high-voltage signal VGH.

US Pat. No. 10,657,918

GATE DRIVING CIRCUIT AND DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A gate driving circuit, comprising a precharging unit circuit, an output unit circuit, and a compensation charging unit circuit,wherein the output unit circuit comprises a first reference point Qn corresponding to a current-row scanning line and a first clock signal line;
wherein the precharging unit circuit is configured to input a high level to the first reference point Qn before an output period;
wherein the first reference point Qn maintains the high level during the output period, and meanwhile the first clock signal line outputs a high level, so that the output unit circuit outputs a scanning signal to the current-row scanning line; and
wherein the compensation charging unit circuit is configured to input a compensation voltage to the first reference point Qn during a previous period and a next period of the output period, so as to maintain the high level of the first reference point On;
wherein the compensation charging unit circuit comprises a high-level signal line, an eighth switch tube, and a ninth switch tube, wherein a gate of the eighth switch tube is connected to a first reference point Qn?1 corresponding to a previous-row scanning line, and a source thereof is connected to the high-level signal line; a gate of the ninth switch tube is connected to a first reference point Qn+1 corresponding to a next-row scanning line, and a drain thereof is connected to the first reference point Qn; and a drain of the eighth switch tube is connected to the source of the ninth switch tube.

US Pat. No. 10,657,917

SHIFT REGISTER AND DISPLAY DEVICE INCLUDING SAME

SHARP KABUSHIKI KAISHA, ...

1. A shift register for driving scanning signal lines, the shift register including a plurality of stages and sequentially outputting active output signals from the plurality of stages based on a plurality of clock signals that periodically repeat an on level and an off level, whereina unit circuit that forms each of the plurality of stages includes:
an output node configured to output the output signal;
an output control transistor having a control terminal, a first conduction terminal to which one of the plurality of clock signals is provided, and a second conduction terminal connected to the output node;
an output control node connected to the control terminal of the output control transistor;
an output control node setting portion configured to bring the output control node to an on level, based on an output signal outputted from a preceding stage; and
a target node control portion configured to maintain a target node at an off level during a normal operation period, the target node being at least one of the output node and the output control node,
the target node control portion includes:
at least one stabilization transistor having a control terminal, a first conduction terminal connected to a corresponding target node, and a second conduction terminal to which an off-level potential is provided;
a stabilization node connected to the control terminal of the stabilization transistor, and
a stabilization node control portion configured to control a level of the stabilization node,
the plurality of clock signals are clock signals of eight or more phases with an on-duty of less than ½, and
the stabilization node control portion brings the stabilization node to an on level for a period less than 50 percent of the normal operation period, based on two or more clock signals among the plurality of clock signals.

US Pat. No. 10,657,916

SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A shift register unit, comprising two transfer gate modules, four AND gate modules, and two capacitor modules, as well as a pulse signal input terminal, four pulse signal output terminals, and a plurality of clock signal input terminals;a first terminal of a first capacitor module is connected to a first node; a first terminal of a second capacitor module is connected to a third node;
a first input terminal of a first transfer gate module is connected to the pulse signal input terminal, a second input terminal of the first transfer gate module is connected to a first clock signal input terminal, a third input terminal of the first transfer gate module is connected to a second clock signal input terminal, and an output terminal of the first transfer gate module is connected to the first node; a first input terminal of a second transfer gate module is connected to a second node, a second input terminal of the second transfer gate module is connected to a third clock signal input terminal, a third input terminal of the second transfer gate module is connected to a fourth clock signal input terminal, and an output terminal of the second transfer gate module is connected to the third node;
each transfer gate module is configured to be turned on when a first level is inputted to the second input terminal thereof and the third input terminal thereof is at a second level, so as to write a scan signal inputted to the first input terminal thereof to a node connected to the output terminal thereof; a level of the scan signal is the first level, the second level being opposite to the first level;
a first input terminal of a first AND gate module is connected to a fifth clock signal input terminal, a second input terminal of the first AND gate module is connected to the second node, and an output terminal of the first AND gate module is connected to a first pulse signal output terminal; a first input terminal of a second AND gate module is connected to a sixth clock signal input terminal, a second input terminal of the second AND gate module is connected to the second node, and an output terminal of the second AND gate module is connected to a second pulse signal output terminal; a first input terminal of a third AND gate module is connected to a seventh clock signal input terminal, a second input terminal of the third AND gate module is connected to a fourth node, and an output terminal of the third AND gate module is connected to a third pulse signal output terminal; a first input terminal of the fourth AND gate module is connected to an eighth clock signal input terminal, a second input terminal of the fourth AND gate module is connected to the fourth node, and an output terminal of the fourth AND gate module is connected to a fourth pulse signal output terminal;
each AND gate module is configured to output the first level through an output terminal thereof when both the first input terminal thereof and the second input terminal thereof are at the first level; and
the second node is electrically connected to the first node, a level state of the second node is in synchronization with a level state of the first node; the fourth node is electrically connected to the third node, a level state of the fourth node is in synchronization with a level state of the third node,
the shift register unit further comprising a first OR gate unit and/or a second OR gate unit;
one input terminal of the first OR gate unit is connected to a clock signal line connected to the fifth clock signal input terminal in each shift register unit, the other input terminal of the first OR gate unit is connected to a clock signal line connected to the sixth clock signal input terminal in each shift register unit, and an output terminal of the first OR gate unit is connected to a clock signal line connected to the first clock signal input terminal in each shift register unit;
one input terminal of the second OR gate unit is connected to a clock signal line connected to the seventh clock signal input terminal in each shift register unit, the other input terminal of the second OR gate unit is connected to a clock signal line connected to the eighth clock signal input terminal in each shift register unit, and an output terminal of the second OR gate unit is connected to a clock signal line connected to the third clock signal input terminal in each shift register unit; and
each OR gate unit is configured to output the first level through the output terminal thereof when either one of the two input terminals thereof is inputted with the first level.

US Pat. No. 10,657,915

SCAN SIGNAL COMPENSATING METHOD AND DEVICE BASED ON GATE DRIVING CIRCUIT

XIANYANG CAIHONG OPTOELEC...

1. A scan signal compensating method base on a gate driving circuit, wherein the method comprises:acquiring a scan signal compensation voltage value in a detecting period; and
adjusting a clock signal(s) and a direct current (DC) voltage source(s) inputted to the gate driving circuit according to the scan signal compensation voltage value, in an adjusting period;
wherein acquiring a scan signal compensation voltage value comprises:
disposing a reference thin film transistor (TFT);
obtaining a driving current of the reference TFT;
acquiring a driving current drift value according to the driving current; and
finding the scan signal compensation voltage value from a second look-up table according to the driving current drift value;
wherein the reference TFT is positioned in a dummy area, and voltages applied on the source, the drain and the gate of the reference TFT are respectively set to be an average value of source voltages, an average value of drain voltages and an average value of gate voltages of all TFTs in an active area.

US Pat. No. 10,657,914

DRIVING METHOD FOR LIQUID CRYSTAL APPARATUS, LIQUID CRYSTAL APPARATUS, AND ELECTRONIC APPARATUS

SEIKO EPSON CORPORATION, ...

1. A driving method for a liquid crystal apparatus including a data line extending along a first direction, a scanning line extending along a second direction that intersects the first direction, a pixel electrode corresponding to an intersection of the data line and the scanning line, a counter electrode opposing to the pixel electrode, a liquid crystal layer between the pixel electrode and the counter electrode, an alignment film between the counter electrode and the liquid crystal layer, and an insulating film between the counter electrode and the alignment film and in contact with the alignment film, the method comprising:applying an alternating current voltage to a plurality of pixels, the alternating current voltage being set in a manner that a first region in which a center potential is offset to a high potential side and a second region in which a center potential is offset to a low potential side, with reference to a counter electrode potential applied to the counter electrode, are alternately arranged along the first direction and the second direction in a plane of a display region in which the plurality of pixels are arranged.

US Pat. No. 10,657,913

DISPLAY PANEL, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display panel, comprising:a first gate line extending in a first direction;
a first data line and a second data line extending in a second direction crossing the first direction;
a first gate control line and a second gate control line,
wherein the first and second gate control lines each comprise a first portion extending in the second direction and a second portion extending in the first direction, and the second portion of the first gate control line overlaps the first data line;
a first pixel comprising a first double-gate switching element, wherein the first double-gate switching element comprises a first gate electrode connected to the first gate line, a first source electrode connected to the first data line, and a second gate electrode connected to the first gate control line; and
a second pixel comprising a second double-gate switching element, wherein the second double-gate switching element comprises a third gate electrode connected to the first gate line, a second source electrode connected to the second data line, and a fourth gate electrode connected to the second gate control line,
wherein a first data voltage having a first polarity is applied to the first data line, a second data voltage having a second polarity different from the first polarity is applied to the second data line, a first gate control voltage is applied to the first gate control line, and a second gate control voltage is applied to the second gate control line,
wherein a level of the first gate control voltage is different from a level of the second gate control voltage,
wherein the first gate control voltage is generated independently from the second gate control voltage, and
wherein the first gate control voltage is output to the second gate electrode of the first double-gate switching element through the first gate control line, and the second gate control voltage is output to the fourth gate electrode of the second double-gate switching element through the second gate control line.

US Pat. No. 10,657,912

DISPLAY WITH PIXEL DIMMING FOR CURVED EDGES

Apple Inc., Cupertino, C...

1. An electronic device comprising:a display that includes a plurality of pixels that form an active area of the display, wherein the active area of the display has at least one rounded corner that follows an outline of the active area; and
control circuitry configured to provide image data to the display, wherein the image data comprises a brightness value for each pixel, wherein the control circuitry comprises circuitry is configured to modify the image data based on at least one dimming factor, wherein each pixel has a respective dimming factor, wherein the dimming factor associated with each pixel is associated with at least a location of that pixel relative to the outline, and wherein the dimming factor associated with pixels positioned outside of the outline at least is associated with a contour of the outline at a position on the outline that is associated with the location of that pixel.

US Pat. No. 10,657,911

VERTICAL ALIGNMENT LIQUID CRYSTAL DISPLAY

SHENZHEN CHINA STAR OPTOE...

1. A vertical alignment liquid crystal display, comprising a plurality of data lines and a plurality of scan lines, wherein the plurality of data lines and the plurality of scan lines intersect to form a plurality of pixel regions, and each pixel region is surrounded by two adjacent data lines and two adjacent scan lines;wherein each pixel region comprises a switching thin film transistor and a sub pixel, and a gate and a drain of the switching thin film transistor are respectively connected to one of the two adjacent scan lines and one of the two adjacent data lines, and a source of the switching thin film transistor is connected to the sub pixel;
in two adjacent pixel regions in the same row, a first capacitor is connected in series between the sources of the two switching thin film transistors in the two adjacent pixel regions, and the source of each of the switching thin film transistors in the two adjacent pixel regions is connected to only one of the first capacitors, wherein a previous pixel region in the two adjacent pixel regions in the same row is a main pixel region, and a next pixel region in the two adjacent pixel regions in the same row is a sub pixel region, and the main pixel region is driven with a driving voltage higher than a driving voltage of driving the sub pixel region by connecting the first capacitor in series between the sources of the two switching thin film transistors in the two adjacent pixel regions.

US Pat. No. 10,657,910

METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for driving a display device having a pixel portion, comprising:performing image analysis processing on an image to recognize a first region and a second region; and
performing super-resolution processing on the first region and the second region at a first intensity and a second intensity, respectively,
wherein the first intensity is different from the second intensity, and
wherein the super-resolution processing is processing for restoring lost data in photographing or signal transmitting.

US Pat. No. 10,657,909

LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR DRIVING SAME

SHARP KABUSHIKI KAISHA, ...

1. A liquid crystal display panel, comprising:a plurality of pixels arranged in a matrix including a plurality of rows and a plurality of columns, each of the plurality of pixels including a first subpixel and a second subpixel arranged so as to adjoin each other in a column direction;
a plurality of TFTs each connected with any of the first subpixels and the second subpixels included in the plurality of pixels;
a plurality of gate bus lines each associated with any of a plurality of pixel rows included in the plurality of pixels;
a plurality of first source bus lines and a plurality of second source bus lines each associated with any of a plurality of pixel columns included in the plurality of pixels; and
a plurality of storage capacitor bus lines each connected with any of storage capacitors of the first subpixels and the second subpixels included in the plurality of pixels,
wherein the plurality of pixels are arranged such that the first subpixel of one pixel and the second subpixel of a pixel which adjoins the one pixel in the column direction adjoin each other,
the plurality of storage capacitor bus lines include a storage capacitor bus line connected with a storage capacitor of the first subpixel of the one pixel and with a storage capacitor of the second subpixel of the pixel which adjoins the one pixel in the column direction,
in any given frame period, the plurality of pixels include a plurality of pixel row pairs each associated with two selected pixel rows among the plurality of pixel rows, the plurality of pixel row pairs being each simultaneously selected,
in each pixel column, one pixel of each of the plurality of pixel row pairs is connected with the first source bus line associated with the pixel column, and the other pixel is connected with the second source bus line associated with the pixel column, and
when the liquid crystal display panel operates over a plurality of frame periods, the plurality of frame periods include a first type frame period and a second type frame period differing in terms of combinations of two pixel rows to be associated with each of the plurality of pixel row pairs, wherein
a period with which the first type frame period and the second type frame period are switched and a period with which a polarity of a display signal voltage supplied to each of the plurality of first source bus lines and to each of the plurality of second source bus lines is inverted are equal to each other, and
a timing at which the first type frame period and the second type frame period are switched and a timing at which a polarity of a display signal voltage supplied to each of the plurality of first source bus lines and to each of the plurality of second source bus lines is inverted are different from each other.

US Pat. No. 10,657,908

DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

Japan Display Inc., Toky...

1. A display device, comprising:a display panel having a light transmission property,
the display panel comprising:
a main surface which displays an image;
a rear surface which is opposite to the main surface;
main pixels each including at least one of a first sub-pixel, a second sub-pixel, a third sub-pixel, and a dummy pixel, the first sub-pixel exhibiting a first color, the second sub-pixel exhibiting a second color, the third sub-pixel exhibiting a third color, and the dummy pixel exhibiting a fourth color having brightness lower than the first color, the second color, and the third color;
a first substrate having a light transmission property and comprising the rear surface;
a second substrate opposed to the first substrate and having a light transmission property, and comprising the main surface;
a first color filter disposed on the first sub-pixel of the second substrate to allow light of the first color to be transmitted;
a second color filter disposed on the second sub-pixel of the second substrate to allow light of the second color to be transmitted;
a third color filter disposed on the third sub-pixel of the second substrate to allow light of the third color to be transmitted;
a fourth color filter disposed on the dummy pixel of the second substrate to allow light of the fourth color to be transmitted; and
a light modulating layer located between the first substrate and the second substrate and capable of changing a light transmission property and a light scattering property of regions corresponding to the first sub-pixel, the second sub-pixel, the third sub-pixel, and the dummy pixel, respectively,
wherein
the first sub-pixel, the second sub-pixel, and the third sub-pixel display from the main surface and the rear surface,
the light modulating layer is in a scattering mode at a position corresponding to the dummy pixel in one of the main pixels when it does not contribute to the display of the image on the main surface,
the dummy pixel displays from the rear surface when not displaying from the main surface, and
the first sub-pixel, the second sub-pixel, and the third sub-pixel display from the main surface and the rear surface when the dummy pixel is displaying from the rear surface and is not displaying from the main surface.

US Pat. No. 10,657,907

CALCULATION METHOD FOR VIEWING-ANGLE COMPENSATION OF DISPLAY DEVICE, VIEWING-ANGLE COMPENSATION STRUCTURE, AND DISPLAY DEVICE

HKC CORPORATION LIMITED, ...

1. A calculation method for viewing-angle compensation of a display device, comprising:measuring tristimulus values for red, green, and blue displayed in grayscale of a display device in a viewing angle and a luminance gamma curve;
calculating a central viewing angle, a first viewing angle, and a second viewing angle of an observation viewing angle of the display device, to obtain a viewing angle range of the observation viewing angle;
obtaining a display look-up table (LUT) by using an angle of the viewing angle and the luminance gamma curve and according to a viewing angle algorithm;
obtaining a viewing-angle compensation value by using the central viewing angle and the viewing angle range and according to the display LUT; and
adjusting the corresponding tristimulus values in the display device according to the viewing-angle compensation value;
wherein the display LUT corresponding to the viewing angle is calculated by using a calculation formula of the viewing angle algorithm and by introducing related parameters of the central viewing angle and the viewing angle range into the following formulas:
Gamma_H(0-degree)+Gamma_L(0-degree)=2*Gamma2.2(0-degree), and
Min(Gamma_H(?)+Gamma_L(?)?2*Gamma2.2(0-degree)), wherein
Gamma_H is a luminance gamma curve of a high-voltage pixel, and
Gamma_L is a luminance gamma curve of a low-voltage pixel.

US Pat. No. 10,657,906

TECHNIQUES FOR DUAL MODULATION DISPLAY WITH LIGHT CONVERSION

Dolby Laboratories Licens...

1. A display system, comprising:one or more illumination sources of a backlight configured to emit first light, the first light including at least one of UV spectral components or blue light spectral components;
one or more light conversion layers configured to be stimulated by the first light and to convert at least a portion of the first light and recycled light into second light, the one or more light conversion layers including quantum dots;
logic to compute color shifts as a function of respective distances that the first light emitted from the one or more illumination sources travels before being converted into the second light by the one or more conversion layers; and
a controller to adjust drive values for one or more light modulators based on the logic.

US Pat. No. 10,657,905

METHOD AND APPARATUS FOR COMPENSATING FOR BRIGHTNESS OF DISPLAY DEVICE

BEIJING BOE OPTOELECTRONI...

1. A method for compensating for brightness of a display device, comprising:acquiring ambient temperature information and display data information of the display device;
determining compensation information corresponding to the acquired ambient temperature information and the acquired display data information; and
compensating for backlight driving signals and/or the display data information of the display device according to the compensation information to adjust the brightness of the display device,
wherein before the determining compensation information corresponding to the acquired ambient temperature information and the acquired display data information, the method further comprises:
establishing and storing correspondence relationship between ambient temperature information and display data information of the display device and compensation information, and
wherein the establishing correspondence relationship comprises:
acquiring a nominal brightness value corresponding to a test gray-scale value of the display device at a nominal temperature;
acquiring a test brightness value corresponding to the test gray-scale value of the display device at a test temperature;
determining a test compensation value corresponding to the test gray-scale value of the display device at the test temperature according to a ratio of the nominal brightness value to the test brightness value; and
determining the correspondence relationship according to the test gray-scale value, the test temperature, and a corresponding test compensation value,
wherein the display data information of the display device comprises the test gray-scale value.

US Pat. No. 10,657,904

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a base substrate having a first surface and a second surface opposite the first surface, the base substrate comprising a plurality of pixels on the first surface of the base substrate;
a protective layer on the second surface of the base substrate, the protective layer having a first opening;
a reflecting member at a side surface of the first opening in the protective layer;
a light sensor corresponding to the first opening; and
a circuit board on the protective layer, the light sensor being mounted on the circuit board.

US Pat. No. 10,657,903

DISPLAY SYSTEM AND DRIVING METHOD FOR DISPLAY PANEL

BOE Technology Group Co.,...

1. A display system, comprising:a display panel comprising a display area;
a display area dividing device configured to divide the display area of the display panel into at least a first display area and a second display area;
a display driving device configured to drive the first display area with a first refresh frequency and drive the second display area with a second refresh frequency; and
a first group of gate lines, a first group of data lines, a second group of gate lines, a second group of data lines,
wherein the first refresh frequency is greater than the second refresh frequency;
the first display area and the second display area are two display areas with fixed positions in the display panel;
the second display area encircles the first display area;
the display driving device comprises a first display driving device and a second display driving device;
the first display area connects the first display driving device via the first group of gate lines and the first group of data lines, and the second display area connects the second display driving device via the second group of gate lines and the second group of data lines;
the first group of gate lines and the second group of gate lines do not share a common gate line, and the first group of data lines and the second group of data lines do not share a common data line; and
the first display driving device is configured to drive the first display area with the first refresh frequency, and the second display driving device is configured to drive the second display area with the second refresh frequency.

US Pat. No. 10,657,902

SENSING CIRCUIT OF DISPLAY DEVICE FOR SENSING PIXEL CURRENT

Silicon Works Co., Ltd., ...

1. A sensing circuit of a display device, comprising:a current receiving unit configured to receive an input current containing at least a leakage current between a pixel current and the leakage current, convert the pixel current at a preset current ratio, and output the converted pixel current to a first node;
a current source unit configured to provide a predetermined amount of source current to the first node;
a current sinking unit configured to sink a predetermined amount of sinking current from the first node;
a current detection unit configured to provide a detected current corresponding to the leakage current to the first node; and
a detection signal output unit configured to sample an offset voltage corresponding to the leakage current using the detected current, remove the leakage current from the input current using the offset voltage, and output a detection signal corresponding to the pixel current obtained by removing the leakage current from the input current,
wherein the current detection unit provides the detected current so that the sinking current is equal to the sum of the source current, the leakage current and the detected current.

US Pat. No. 10,657,901

PULSE-WIDTH MODULATION BASED ON IMAGE GRAY PORTION

Microsoft Technology Lice...

1. A computing device comprising:a self-emitting electroluminescent display;
a pulse-width modulation (PWM) controller to calculate a gray portion of an input display signal, select a PWM duty ratio based on the calculated gray portion, and output a pulse-modulated display signal to the display; and
a display driver to select a gamma band corresponding to peak luminance of the input display signal, and apply the selected PWM duty ratio to the selected gamma band when the peak luminance exceeds a predetermined PWM threshold to create the pulse-modulated display signal output to the display.

US Pat. No. 10,657,900

PIXEL DRIVING CIRCUIT, DRIVING METHOD THEREOF AND OLED DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A pixel driving method, configured to drive a pixel driving circuit, the pixel driving circuit comprising a plurality of scanning lines, a plurality of data lines, a plurality of power lines and a data driving chip, the plurality of scanning lines and the plurality of data lines intersecting to define a plurality of pixel units, the plurality of pixel units in each row being connected to a corresponding scanning line and a corresponding power line, the plurality of pixel units in each column being connected to a corresponding data line, ends of the plurality of data lines close to the data driving chip being connected to the data driving chip, wherein the pixel driving method comprising:in a scanning period, inputting scanning signal to an end of the scanning line to drive the plurality of pixel units along a first direction, and inputting power driving signal to an end of the power line opposite to the end of the scanning line to which the scanning signal is input to drive the plurality of pixel units along a second direction, wherein the first direction and the second direction are opposite; and
providing image data signal for the plurality of data lines by the data driving chip.

US Pat. No. 10,657,899

PIXEL COMPENSATION CIRCUIT, DRIVING METHOD FOR THE SAME AND AMOLED DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. A pixel compensation circuit for using in an AMOLED display panel, comprising:a light-emitting device, a reset module, a storage capacitor, a first thin-film transistor, a second thin-film transistor, a third thin-film transistors, a fifth thin-film transistor, and a sixth thin-film transistor;
wherein both ends of the storage capacitor are respectively connected to a drain of the fifth thin-film transistor and a gate of the first thin-film transistor;
wherein a drain and a gate of the fifth thin-film transistor are respectively connected to a power supply voltage signal and the light-emitting signal, and a source of the fifth thin-film transistor is connected to a drain of the first thin-film transistor;
wherein a source of the first thin-film transistor is connected to a drain of the sixth thin-film transistor, a source of the sixth thin-film transistor is connected to an anode of the light-emitting device, and a gate of the sixth thin-film transistor is connected to the light-emitting signal, a cathode of the light-emitting device is connected to a common terminal signal;
wherein the reset module is used to reset the gate of the first thin-film transistor and the anode of the light-emitting device according to a second scanning signal, and the second scanning signal includes a pulse in one frame period;
wherein a drain and a gate of the second thin-film transistor are respectively connected to a data signal and the first scanning signal, and a source of the second thin-film transistor is connected to the drain of the first thin-film transistor;
wherein a drain of the third thin-film transistor is connected to the drain of the fifth thin-film transistor through the storage capacitor, a gate of the third thin-film transistor is connected to the first scanning signal, and a source of the third thin-film transistor is connected to the source of the first thin-film transistor;
wherein the reset module includes: a fourth thin-film transistor and a seventh thin-film transistor; and
wherein gates of the fourth thin-film transistor and the seventh thin-film transistor are both connected to the second scanning signal, and drains of the fourth thin-film transistor and the seventh thin film transistor are both connected to a reset signal, and sources of the fourth thin-film transistor and the seventh thin-film transistor are respectively connected to the gate of the first thin-film transistor and the anode of the light-emitting device.

US Pat. No. 10,657,898

PIXEL DRIVING CIRCUIT, DRIVING METHOD, ORGANIC LIGHT EMITTING DISPLAY PANEL AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A pixel driving circuit, comprising: a data writing circuit; a storage circuit; at least one first light emitting device; a first driving circuit corresponding to the respective first light emitting device one-to-one; at least one second light emitting device; and a second driving circuit corresponding to the respective second light emitting device one-to-one, wherein:the data writing circuit is respectively connected to a scanning signal terminal, a data signal terminal and a node, and the data writing circuit is configured to provide a signal of the data signal terminal to the node under control of the scanning signal terminal;
the storage circuit is respectively connected to a first reference signal terminal and the node, and the storage circuit is configured to be charged under control of a signal of the node and the first reference signal terminal, and maintain a stable voltage difference between the node and the first reference signal terminal when the node is in a floating state;
the respective first driving circuit is respectively connected to a second reference signal terminal, the node and a first terminal of the corresponding first light emitting device, and a second terminal of the respective first light emitting device is connected to the first reference signal terminal, and the respective first driving circuit is configured to drive the connected first light emitting device to emit light when a potential of the signal of the node is a first potential; and
the respective second driving circuit is respectively connected to a third reference signal terminal, the node and a second terminal of the corresponding second light emitting device, a first terminal of the respective second light emitting device is connected to the first reference signal terminal, and the respective second driving circuit is configured to drive the connected second light emitting device to emit light when a potential of the signal of the node is a second potential.

US Pat. No. 10,657,897

DRIVING COMPENSATION CIRCUIT FOR OLED DISPLAY UNIT, OLED DISPLAY CIRCUIT, AND OLED DISPLAY

Shenzhen China Star Optoe...

1. A driving compensation circuit for an organic light-emitting diode (OLED) display unit, wherein the OLED display unit comprises M rows and N columns of pixel units, wherein each column of pixel units is connected to a data line, and each row of pixel units is connected to a scanning line; and the compensation circuit comprises:N first switching transistors, each first switching transistor comprising an input end connected to a voltage input end of each pixel unit in a column of pixel units, wherein N is a positive integer;
N second switching transistors, each second switching transistor comprising an output end connected to a voltage input end of each pixel unit in a column of pixel units;
N sensing units, connected to the output ends of the N first switching transistors in a one-to-one corresponding manner, and configured to acquire first current information in sensing mode and second current information in display mode that are of a voltage input end of each pixel unit; and
a calculation and processing unit, connected to the N sensing units and the data line, and configured to calculate a mapping relationship between a data voltage of the data line and the first current information, and to calculate a data compensation voltage in a display phase according to the second current information and the mapping relationship,
wherein on/off states of a first switching transistor and a second switching transistor that are connected to a same column of pixel units are opposite;
wherein the sensing unit comprises a first PMOS transistor and a second PMOS transistor; a source of the first PMOS transistor is connected to an output end of a corresponding first switching transistor; a gate of the first PMOS transistor is connected to the source of the first PMOS transistor; a gate of the second PMOS transistor is connected to the gate of the first PMOS transistor; drains of the first PMOS transistor and the second PMOS transistor are connected to a power supply end; and a source of the second PMOS transistor is connected to the calculation and processing unit; and
the calculation and processing unit comprises a gating module, an analog to digital converter, and a processing chip; an input end of the gating module is connected to the sensing units; an output end of the gating module is connected to the analog to digital converter; and the analog to digital converter is connected to the processing chip.

US Pat. No. 10,657,896

VOLTAGE COMPENSATION METHOD, COMPENSATION CIRCUIT, AND DISPLAY APPARATUS OF OLED

SHENZHEN CHINA STAR OPTOE...

1. An OLED voltage compensation circuit, configured to compensate a driving voltage of an OLED display panel, comprising:a brightness detection unit, configured to detect and acquire a brightness value of each pixel of the OLED display panel;
an encoding unit, configured to convert the brightness value acquired by the brightness detection unit into a driving voltage code according to a Gamma curve; and
a compensation unit, configured to acquire compensation data according to the driving voltage code of the encoding unit and compensate the driving voltage code value according to the compensation data to drive display of the OLED display panel according to the compensated driving voltage code;
wherein the compensation data comprises a voltage compensation code, and an encoding step of the voltage compensation code is the same as an encoding step of the driving voltage code;
wherein the compensation data further comprises a brightness-related scale factor; the compensation unit acquires the voltage compensation code and the brightness-related scale factor corresponding to the compensation data according to the driving voltage code, so as to compensate the driving voltage code by using the voltage compensation code and the brightness-related scale factor.

US Pat. No. 10,657,895

PIXELS AND REFERENCE CIRCUITS AND TIMING TECHNIQUES

Ignis Innovation Inc., W...

1. A display system, including a plurality of pixels, comprising:a controller for receiving digital data indicative of information to be displayed on the display system;
a source driver for receiving data from the controller and for transmitting data signals to each pixel during a programming phase, and including a monitoring system integrated therewith for measuring a current or voltage associated with each pixel for extracting information indicative of a degradation of each pixel during a measurement phase;
a plurality of combined data/monitor lines extending from the source driver for transmitting both data and monitor signals during alternating programming and measurement phases, respectively;
a plurality of data lines extending to each pixel;
a plurality of monitor lines extending to each pixel for measuring a current or voltage associated with each pixel after the programming phase; and
a switching system coupled to each pixel via a data line and via a monitor line different from said data line, and coupled via a combined data/monitor line to the source driver, said switching system for alternatively connecting each combined data/monitor line with the data line and the monitor line respectively to steer to the pixel over the data line, signals received from the source driver over the combined data/monitor line, and to steer to the source driver over the combined data/monitor line, signals received from the pixel over the monitor line.

US Pat. No. 10,657,894

PIXEL CIRCUIT, METHOD FOR DRIVING THE SAME, DISPLAY PANEL, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A pixel circuit, comprising: a driver transistor, a data writing sub-circuit, a light-emission control sub-circuit, a node reset sub-circuit, and a light-emitting diode, wherein:the node reset sub-circuit is configured to reset a gate of the driver transistor in response to a first scan signal terminal in a first reset stage;
the data writing sub-circuit is configured to write a data signal of a data signal terminal into the gate of the driver transistor, and to compensate threshold voltage of the driver transistor, in response to a second scan signal terminal in a data writing stage;
the light-emission control sub-circuit is configured to provide a first electrode of the driver transistor with a signal of a first voltage terminal in response to a first light-emission control terminal in the first reset stage and a light emission stage; and to connect a second electrode of the driver transistor with an anode of the light-emitting diode in response to a second light-emission control terminal in a light emission stage;
the driver transistor is configured to drive current according to the data signal to drive the light-emitting diode to emit light; and
the first reset stage, the data writing stage, and the light emission stage are consecutive periods of time;
wherein the data writing sub-circuit comprises a second switch transistor, a third switch transistor, and a first capacitor, wherein:
the second switch transistor has a gate connected with the second scan signal terminal, a first electrode connected with the gate of the driver transistor, and a second electrode connected with the second electrode of the driver transistor;
the third switch transistor has a gate connected with the second scan signal terminal, a first electrode connected with the data signal terminal, and a second electrode connected with the first electrode of the driver transistor; and
the first capacitor has one terminal connected with the gate of the driver transistor, and another terminal connected with the first voltage terminal.

US Pat. No. 10,657,893

DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A display device including a plurality of data lines that transmit a plurality of data signals indicating an image to be displayed, a plurality of scanning lines intersecting the plurality of data lines, and a plurality of pixel circuits arranged in a matrix along the plurality of data lines and the plurality of scanning lines, the display device comprising:a data line drive circuit including a plurality of output terminals respectively corresponding to a plurality of sets of data line groups, the data line groups being obtained by grouping the plurality of data lines with a prescribed number of two or more data lines being used as a set, the data line drive circuit time-divisionally outputting a prescribed number of data signals to be transmitted from each of the plurality of output terminals through a prescribed number of data lines corresponding to the each of the plurality of output terminals;
an output selecting circuit including a plurality of demultiplexers respectively connected to the plurality of output terminals of the data line drive circuit and respectively corresponding to the plurality of sets of data line groups; and
a scanning line drive circuit selectively driving the plurality of scanning lines, wherein
each of the plurality of pixel circuits corresponds to any one of the plurality of data lines and corresponds to any one of the plurality of scanning lines,
each pixel circuit includes a display element driven by a current, a holding capacitor that holds a voltage controlling a drive current for the display element, and a driving transistor that applies the drive current corresponding to the voltage held by the holding capacitor to the display element, and applies a voltage of a corresponding data line via the driving transistor to the holding capacitor due to the driving transistor in a diode-connected state in a case where a corresponding scanning line is in a select state,
a period included in a period from or after a time point when supplying a data signal output starts in each of horizontal intervals last among the prescribed number of data signals to a time point before a time point when supplying the data signal ends is set in advance as a delay period,
each demultiplexer demultiplexes the prescribed number of data signals output in each of the horizontal intervals during the horizontal interval and supplies the demultiplexed data signals respectively to the prescribed number of data lines,
the scanning line drive circuit starts to select a scanning line corresponding to the pixel circuit to which the prescribed number of data signals are supplied, when the delay period of each of the horizontal intervals ends, and
in a case where a delay of a scanning signal is larger than a delay of the data signal, the delay period is set to be shorter as a distance from the demultiplexer to a scanning line connected to the pixel circuit into which the prescribed number of data signals are to be written is longer.

US Pat. No. 10,657,892

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a first driving transistor comprising a first gate electrode and a first semiconductor layer, the first semiconductor layer comprising a first source region and a first drain region, the first driving transistor being in a first pixel area of a substrate;
a second driving transistor comprising a second gate electrode and a second semiconductor layer comprising a second source region and a second drain region, the second driving transistor being in a second pixel area adjacent the first pixel area of the substrate;
a first electrode layer overlapping, in plan view, at least a portion of the first source region of the first driving transistor;
a second electrode layer overlapping, in plan view, at least a portion of the second source region of the second driving transistor;
a first power line electrically connected to the first electrode layer; and
a second power line electrically connected to the second electrode layer,
wherein a second overlapping area of the second source region of the second driving transistor and the second electrode layer is greater than a first overlapping area of the first source region of the first driving transistor and the first electrode layer.

US Pat. No. 10,657,891

SOURCE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A source driving circuit of a display device, comprising:a plurality of unit driving circuits configured to drive a plurality of connection nodes connected to a display panel of the display device, each of the plurality of unit driving circuits comprising:
a plurality of driver circuits configured to perform analog-conversion and amplification operations on a plurality of digital data signals to generate a plurality of analog data signals so that each connection node of the plurality of connection nodes is driven by more than one of the plurality of driver circuits; and
a plurality of output switches connected in parallel between the plurality of driver circuits and a corresponding connection node among the plurality of connection nodes, the plurality of output switches configured to transfer the plurality of analog data signals alternately to the corresponding connection node,
wherein each of the plurality of driver circuits drives only one connection node.

US Pat. No. 10,657,890

PIXEL DRIVING CIRCUIT AND DRIVING METHOD THEREOF, DISPLAY DRIVING CIRCUIT, DISPLAY SUBSTRATE AND DISPLAY DEVICE

BEIJING BOE DISPLAY TECHN...

1. A pixel driving circuit, comprising:a current control circuit configured to provide a constant current signal and an activation signal to a current switching circuit;
the current switching circuit configured to control the transmission of the constant current signal to a light-emitting device under the control of the activation signal; and
a grounding control circuit configured to control the current control circuit to provide the constant current signal and the activation signal, wherein:
an input terminal of the current control circuit is connected to a data line and a power line, respectively; a control terminal of the current switching circuit is connected to an output terminal of the current control circuit, and an output terminal of the current switching circuit is connected to an input terminal of the light-emitting device; and, a control terminal of the grounding control circuit is connected to a gate line, an input terminal of the grounding control circuit is connected to an output terminal of the light-emitting device, and an output terminal of the grounding control circuit is grounded, and
the current control circuit comprises an operational amplifier and a resistor; a first phase input terminal of the operational amplifier is connected to the data line; the power line is connected to a second phase input terminal of the operational amplifier via the resistor: an output terminal of the operational amplifier is connected to the control terminal of the current switching circuit; and, the second phase input terminal of the operational amplifier is also connected to the input terminal of the current switching circuit;
the current switching circuit comprises a first transistor and a second transistor; a control electrode of the first transistor is connected to the output terminal of the current control circuit, a first electrode of the first transistor is connected to the input terminal of the current control circuit, and a second electrode of the first transistor is connected to a control electrode of the second transistor, and, a second electrode of the second transistor is connected to the input terminal of the current control circuit, and a first electrode of the second transistor is connected to the input terminal of the light-emitting device;
the grounding control circuit comprises a third transistor; and, a control electrode of the third transistor is connected to the gate line, a second electrode of the third transistor is connected to the output terminal of the light-emitting device, and a first electrode of the third transistor is grounded.

US Pat. No. 10,657,889

PIXEL CIRCUIT, DRIVING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A driving method of a pixel circuit, wherein the driving method is used for driving the pixel circuit comprising: a reset sub-circuit, a compensation sub-circuit, a data writing sub-circuit, a storage capacitor, a driving transistor, a light emitting control sub-circuit and a light emitting sub-circuit wherein,the reset sub-circuit is respectively connected with a reset signal terminal, an initialization signal terminal, a reference signal terminal, a first node and a second node, the reset sub-circuit is configured to output an initialization signal from the initialization signal terminal to the first node and to output a reference signal from the reference signal terminal to the second node under the control of a reset signal from the reset signal terminal;
the compensation sub-circuit is respectively connected with a driving signal terminal, the first node and a third node, the compensation sub-circuit is configured to write a threshold voltage of the driving transistor into the first node under the control of a driving signal from the driving signal terminal;
the data writing sub-circuit is respectively connected with the driving signal terminal, a data signal terminal, the reference signal terminal, the second node and a second electrode of the driving transistor, for the data writing sub-circuit is configured to output a data signal from the data signal terminal to the second node and to output the reference signal to the second electrode of the driving transistor under the control of the driving signal;
one end of the storage capacitor is connected with the first node and the other end thereof is connected with the second node for adjusting a potential of the first node according to a potential of the second node;
a gate of the driving transistor is connected with the first node, a first electrode of the driving transistor is connected with the third node, and the second electrode of the driving transistor is connected with one end of the light emitting sub-circuit for outputting a drive current to the light emitting sub-circuit under the drive of the first node and the third node;
the light emitting control sub-circuit is respectively connected with an enable signal terminal, a first power terminal, the reference signal terminal, the second node and the third node, for the light emitting control sub-circuit is configured to output the reference signal to the second node and to output a first power signal from the first power terminal to the third node under the control of an enable signal from the enable signal terminal;
one end of the light emitting sub-circuit is connected with the second electrode of the driving transistor and the other end thereof is connected with a second power terminal for emitting light under the drive of the drive current; and
the driving method of the pixel circuit includes:
a reset stage, in which a reset signal provided by a reset signal terminal is at a first potential, and in which, under the control of the reset signal, the reset sub-circuit outputs an initialization signal from an initialization signal terminal to a first node and outputs the initialization signal from a reference signal terminal to a second node, the initialization signal being at a second potential;
a data writing stage, in which a driving signal provided by a driving signal terminal is at the first potential, in which the data writing sub-circuit outputs a data signal from a data signal terminal to the second node and outputs a reference signal to a second electrode of the driving transistor, and in which the compensation sub-circuit writes a threshold voltage of the driving transistor into the first node under the drive of the driving signal and a third node; and
a light emitting stage, in which the light emitting control sub-circuit outputs the reference signal to the second node and outputs a first power signal from a first power terminal to the third node, in which the storage capacitor adjusts a potential of the first node according to a potential of the second node, and in which, under the drive of the first node and the third node, the driving transistor outputs a drive current to the light emitting sub-circuit and drives the light emitting sub-circuit to emit light.

US Pat. No. 10,657,888

DRIVING METHOD FOR PIXEL DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. A driving method for a pixel driving circuit comprising a driving transistor and a light-emitting element, comprising:in response to a first scanning signal on a first scanning signal line, performing an initialization of the pixel driving circuit, wherein the first scanning signal is a low-level signal;
in response to a second scanning signal on a second scanning signal line and a third scanning signal on the first scanning signal line, compensating a threshold voltage deviation of the driving transistor, and providing a data signal voltage, wherein the third scanning signal is a low-level signal;
in response to a first light-emitting signal on a first light-emitting signal line and a second light-emitting signal on a second light-emitting signal line, generating, by the driving transistor, driving current corresponding to the data signal voltage; and
in response to the driving current, emitting light by the light-emitting element,
wherein at least one clock signal period is provided after the initialization of the pixel driving circuit is completed and before the threshold voltage deviation of the driving transistor is compensated, and
in the at least one clock signal period, a high-level is provided to the first scanning signal line, and a signal provided to the first light-emitting signal line is changed from a high-level to a low-level.

US Pat. No. 10,657,887

PROTECTION CIRCUIT AND METHOD, PIXEL CIRCUIT, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A protection circuit, comprising: a determination circuit, a first coupling circuit, a first terminal, a second terminal and a second coupling circuit;the determination circuit is coupled to the first terminal and the first coupling circuit, and is configured to determine whether a voltage at the first terminal of the protection circuit belongs to one of a first predetermined range and a second predetermined range;
the first coupling circuit is coupled to the first terminal, the second terminal and the determination circuit, and is configured to:
couple the first terminal to the second terminal in response to the voltage at the first terminal belonging to the first predetermined range; and
decouple the first terminal from the second terminal in response to the voltage at the first terminal belonging to the second predetermined range;
the second coupling circuit is connected to the first terminal of the protection circuit and configured to make the voltage at the first terminal of the protection circuit belong to the first predetermined range;
wherein the second coupling circuit comprises a second transistor; and
wherein a control electrode of the second transistor is coupled to a first control signal terminal, a first electrode of the second transistor is coupled to the first terminal of the protection circuit, and a second electrode of the second transistor is coupled to the second terminal of the protection circuit;
wherein the protection circuit further comprises a voltage detection line;
wherein the voltage detection line is configured to couple the first terminal of the protection circuit to a voltage detection device; and
wherein the second transistor is configured to be turned on in response to the voltage at the first terminal of the protection circuit belonging to a third predetermined range.

US Pat. No. 10,657,886

PIXEL COMPENSATION CIRCUIT, DRIVING METHOD THEREOF AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A pixel compensation circuit, comprising: a signal input circuit, a driving circuit, a light-emitting control circuit, a first reset circuit, a second reset circuit, a first storage capacitor, a first switching transistor, and a second switching transistor, whereinthe signal input circuit is connected with an input of the first switching transistor; a signal write control line is connected with a control end of the first switching transistor; an output of the second switching transistor, the second reset circuit, and one end of the first storage capacitor are connected with an output of the first switching transistor; the first reset circuit and the driving circuit are connected with an other end of the first storage capacitor; an output of the first reference voltage is connected with an input of the second switching transistor; a first scanning signal line is connected with a control end of the second switching transistor; a high-level output of a power supply, the driving circuit, and the light-emitting control circuit are sequentially connected with one to another; a light-emitting control signal line is connected with the light-emitting control circuit; and
when a display data is written into the signal input circuit, the signal write control line controls the first switching transistor to be switched on,
wherein the driving circuit includes a driving switching transistor and a third switching transistor, in which
a control end of the driving switching transistor is connected with an output of the third switching transistor; the control end of the driving switching transistor is connected with the first reset circuit; the control end of the driving switching transistor is connected with the other end of the first storage capacitor; an input of the driving switching transistor is connected with the high-level output of the power supply; an output of the driving switching transistor is connected with an input of the third switching transistor; the output of the driving switching transistor is connected with the light-emitting control circuit; and the first scanning signal line is connected with a control end of the third switching transistor.

US Pat. No. 10,657,885

ELECTRO-OPTICAL DEVICE, DRIVING METHOD OF ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS

SEIKO EPSON CORPORATION, ...

1. An electro-optical device comprising:a first capacitor having a first electrode and a second electrode;
a control circuit that supplies a data signal to the first electrode of the first capacitor;
a first wiring electrically connected to the second electrode of the first capacitor;
a second wiring to which a fixed potential is supplied, the second wiring extending along a direction that is parallel with a direction in which the first wiring extends;
a second capacitor having a third electrode electrically connected to the first wiring and a fourth electrode electrically connected to the second wiring;
a pixel circuit electrically connected to the first wiring, the pixel circuit having a pixel capacitor holding a first voltage according to the data signal, the pixel circuit including:
an electro-optical element;
a first transistor that controls current supplied to the electro-optical element when electrically connected to the electro-optical element, the first transistor having a gate electrode;
a second transistor which is electrically connected between the first wiring and a gate of the first transistor and which is configured to be turned on or off;
a third transistor connected between the first transistor and the light emitting element, the third transistor being configured to be turned on or off; and
a fourth transistor connected between the second wiring and the light emitting element, the fourth transistor being configured to be turned on or off, a drain of the fourth transistor being directly connected to the second wiring, and a source of the fourth transistor being directly connected between the third transistor and the light emitting element,
wherein the first voltage is generated based on the data signal and a capacitance ratio of at least the first capacitor and the second capacitor,
a capacitance of the second capacitor is greater than a capacitance of the first capacitor,
the capacitance of the first capacitor is greater than a capacitance of the pixel capacitor,
the pixel capacitor is connected to the gate electrode of the first transistor and a potential voltage change amount of the data signal is compressed at the gate electrode of the first transistor by the capacitance ratio.

US Pat. No. 10,657,884

ELECTRONIC DEVICE HAVING DISPLAY AND SENSOR AND METHOD FOR OPERATING THE SAME

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a display disposed on a surface of the housing;
a sensor mounted under the display inside the housing to sense light received through the display and light received from the display; and
a processor electrically connected with the display and the sensor,
wherein the processor is configured to:
obtain sensing data from the sensor while an image is displayed on the display,
identify a first brightness setting value of the display,
identify an image brightness ratio for the image currently displayed on the display,
identify an illuminance of outside of the housing based on the obtained sensing data from the sensor and compensation value, the compensation value corresponding to the identified first brightness setting value of the display and the identified image brightness ratio of the image among a pre-stored plurality of compensation values, and
set a brightness setting of the display to a second brightness setting value determined based at least on the identified illuminance of outside of the housing.

US Pat. No. 10,657,883

PIXEL DRIVING CIRCUIT, DRIVING METHOD, ARRAY SUBSTRATE AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. A pixel driving circuit, comprising:a data line for providing a data voltage;
a gate line for providing a scanning voltage;
a first power supply line for providing a first power supply voltage;
a second power supply line for providing a second power supply voltage;
a light emitting device having a first terminal and a second terminal, wherein the second terminal of the light emitting device is connected to the second power supply line;
a driving transistor having a gate, a source, and a drain, wherein the source of the driving transistor is connected to the first power supply line;
a storage capacitor having a first terminal and a second terminal, wherein the first terminal of the storage capacitor is connected to the gate of the driving transistor so as to transfer the data voltage to the gate of the driving transistor;
a resetting sub-circuit configured to reset voltages at the first terminal and the second terminal of the storage capacitor to a resetting signal line voltage and to the data voltage, respectively;
a data writing sub-circuit connected to the gate line, the data line, and the second terminal of the storage capacitor and configured to write the data voltage into the second terminal of the storage capacitor;
a compensating sub-circuit it connected to the gate line, the first terminal of the storage capacitor, and the drain of the driving transistor and configured to write a compensation voltage into the first terminal of the storage capacitor, wherein the compensation voltage is equal to a difference between the first power supply voltage and a threshold voltage of the driving transistor; and
a light emitting control sub-circuit connected to the second terminal of the storage capacitor, the drain of the driving transistor, and the first terminal of the light emitting device and configured to control the driving transistor to drive the light emitting device to emit light,
wherein the driving transistor is configured to control, under a control of the light emitting control sub-circuit, a magnitude of a current flowing into the light emitting device,
wherein the resetting sub-circuit, comprises a resetting control line, a resetting signal line, a first transistor, and a second transistor, wherein the first transistor has a gate, a source, and a drain, wherein the gate of the first transistor is connected to the resetting control line, the source of the first transistor is connected to the resetting signal line, and the drain of the first transistor is connected to the first terminal of the storage capacitor, wherein the first transistor is configured to write the resetting signal line voltage into the first terminal of the storage capacitor, wherein the second transistor has a gate, a source, and a drain, wherein the gate of the second transistor is connected to the resetting control line, the source of the second transistor is connected to the data line, and the drain of the second transistor is connected to the second terminal of the storage capacitor, and wherein the second transistor is configured to write the data voltage into the second terminal of the storage capacitor.

US Pat. No. 10,657,882

DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a driving transistor comprising:
a first gate electrode;
a second gate electrode over the first gate electrode;
a first oxide semiconductor layer between the first gate electrode and the second gate electrode;
a first source electrode over and electrically connected to the first oxide semiconductor layer; and
a first drain electrode over and electrically connected to the first oxide semiconductor layer;
a switching transistor comprising:
a second oxide semiconductor layer;
a third gate electrode over the second oxide semiconductor layer;
a second source electrode over and electrically connected to the second oxide semiconductor layer; and
a second drain electrode over and electrically connected to the second oxide semiconductor layer; and
an organic EL element,
wherein the switching transistor does not comprise a gate electrode under the second oxide semiconductor layer,
wherein the organic EL element comprises a first electrode, a second electrode over the first electrode, and a layer comprising an organic compound between the first electrode and the second electrode,
wherein one of the second source electrode and the second drain electrode is electrically connected to a signal line,
wherein the other of the second source electrode and the second drain electrode is electrically connected to one of the first gate electrode and the second gate electrode of the driving transistor,
wherein one of the first source electrode and the first drain electrode is electrically connected to the organic EL element,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc,
wherein a length of the first gate electrode in a channel length direction is larger than a length of the second gate electrode in the channel length direction, and
wherein each of the first source electrode and the first drain electrode overlaps with the first gate electrode.

US Pat. No. 10,657,881

DISPLAY PANEL, DISPLAY DEVICE, AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. A display panel comprising:a partition between a light emitting unit and an adjacent light emitting unit, a middle layer part of the partition is between an upper layer part of the partition and a lower layer part of the partition; and
a protective layer that covers the partition, a refractive index of the upper layer part is lower than a refractive index of the protective layer.

US Pat. No. 10,657,880

DISPLAY, METHOD FOR DRIVING DISPLAY, AND ELECTRONIC APPARATUS HAVING PARALLEL HOLDING CAPACITORS

Sony Corporation, Tokyo ...

1. A display device comprising a plurality of pixels and a driving circuit configured to drive the pixels,a respective pixel of the plurality of pixels comprising a light emitting element, a sampling transistor, a drive transistor, and a capacitor,
wherein the driving circuit is configured to drive the respective pixel within one scanning cycle such that:
a predetermined voltage is provided to the capacitor so as to set a voltage stored in the capacitor to be greater than zero, during a first period;
a first current through the drive transistor is provided to the capacitor at least within a period in which the sampling transistor is set in a conductive state, the first current being provided during a second period after the first period;
a second current is provided to the light emitting element in accordance with an image signal data sampled to the capacitor during a third period after the second period,
wherein the capacitor includes a first electrode being a portion of a first layer, a second electrode being a portion of a second layer, and a third electrode being a portion of a third layer, the first, second, and third layers being different from one another,
wherein the second electrode is disposed to face one surface of the first electrode and the third electrode is disposed to face another surface of the first electrode,
wherein at least a part of a first connection wiring from the sampling transistor to the capacitor is formed as a portion of the first layer,
wherein at least a part of a second connection wiring from the capacitor to a current electrode of the drive transistor is formed as a part of the second layer,
wherein the display device further comprises:
a first insulator layer sandwiched between the first electrode and the second electrode,
a second insulator layer sandwiched between the second electrode and the third electrode, and
a third insulator layer sandwiched between an anode electrode of the light emitting element and the second insulator layer, and
wherein the third electrode is in contact with the second insulator layer.

US Pat. No. 10,657,879

GATE DRIVING CIRCUIT, METHOD FOR DRIVING THE SAME, AND DISPLAY APPARATUS

HEFEI BOE OPTOELECTRONICS...

1. A gate driving circuit, comprising N stages of cascaded shift registers, N being an integer greater than or equal to 4, whereinin the N stages of shift registers, an output signal terminal of an nth stage of shift register is connected to an input signal terminal of an (n+I/2)th stage of shift register, and a reset signal terminal of the nth stage of shift register is connected to an output signal terminal of an (n+K)th stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N?I/2), K is an integer greater than I/2 and less than I, and I is a number of clock signal lines connected to the gate driving circuit, which is an even number greater than or equal to 4;
wherein each stage of shift register among the N stages of shift registers comprises:
an output sub-circuit connected to an output signal terminal, a clock signal input terminal for receiving a clock signal of the stage of shift register and a pull-up control node of the stage of shift register, and configured to turn on a connection between the clock signal input terminal and the output signal terminal when the pull-up control node is at an active operating level;
a reset sub-circuit connected to a reset signal terminal for receiving a reset signal, the pull-up control node and a first level terminal for providing a first level respectively, and configured to reset the pull-up control node to the first level under control of the reset signal;
an input sub-circuit connected to an input signal terminal for receiving an input signal, the pull-up control node of the stage of shift register and a second level terminal for providing a second level respectively, and configured to provide the second level to the pull-up control node under control of the input signal, wherein the second level is different from the first level; and
a control sub-circuit connected to a control signal terminal for receiving a control signal, a first fixed level terminal for providing a first fixed level, the output signal terminal and the pull-up control node respectively, and configured to turn on a connection between the first fixed level terminal and the output signal terminal under control of the control signal and the pull-up control node;
wherein the control sub-circuit comprises:
a first transistor, wherein a gate of the first transistor is connected to the pull-up control node, a first electrode of the first transistor is connected to the first fixed level terminal, and a second electrode of the first transistor is connected to a pull-down control node of the stage of shift register;
a second transistor, wherein a gate and a first electrode of the second transistor are connected commonly to the control signal terminal, and a second electrode of the second transistor is connected to the pull-down control node;
a third transistor, wherein a gate of the third transistor is connected to the pull-down control node, a first electrode of the third transistor is connected to the first fixed level terminal, and a second electrode of the third transistor is connected to the pull-up control node;
a fourth transistor, wherein a gate of the fourth transistor is connected to the pull-down control node, a first electrode of the fourth transistor is connected to the first fixed level terminal, and a second electrode of the fourth transistor is connected to the output signal terminal; and
a second capacitor, wherein a first electrode of the second capacitor is connected to the pull-down control node, and a second electrode of the second capacitor is connected to the first fixed level terminal; and
wherein the control signal is an inversion of the clock signal of the stage of shift register.

US Pat. No. 10,657,878

POWER CONTROL CIRCUIT FOR DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display panel;
a plurality of pixels arranged on the display panel;
a data driver and a gate driver which respectively apply an image data signal and a gate pulse signal to the plurality of pixels;
a timing controller which applies control signals respectively to the data driver and the gate driver; and
a power management integrated circuit which applies a driving voltage to the data driver and the gate driver,
wherein the timing controller detects an operational condition of the display panel and selects one of a plurality of stored power setting values to output the selected one of the power setting values to the power management integrated circuit, and
the power management integrated circuit comprises:
a first storage bank;
a second storage bank;
a controller which receives the power setting value from the timing controller, stores the power setting value in one of the first storage bank and the second storage bank, and calls the stored power setting value to determine the driving voltage; and
a power generator which applies the driving voltage based on the driving voltage determined by the controller,
wherein, after calling all of the power setting values stored in said one of the first storage bank and the second storage bank, the controller receives another power setting value from the timing controller and stores said another power setting value in the other of the first storage bank and the second storage bank.

US Pat. No. 10,657,877

DRIVING CIRCUIT, DRIVING METHOD AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. A driving circuit, comprising one or more shift registers, wherein each of the one or more shift registers comprises:a first input unit configured to provide a signal at an input signal terminal to a first node under control of a first clock signal terminal; provide the signal at the input signal terminal to the first node under control of the first clock signal terminal and a second clock signal terminal; provide a signal at an output signal terminal to the first node under control of a second node and the second clock signal terminal; and provide the signal at the output signal terminal to the first node under control of the second node, the second clock signal terminal and the first clock signal terminal;
a second input unit configured to provide a signal at a first constant potential terminal to the second node under control of the first clock signal terminal and provide the signal at the input signal terminal or a signal at the first clock signal terminal to the second node under control of the first node; and
an output unit configured to provide a signal at the second clock signal terminal to the output signal terminal under control of the signal at the first node and provide a signal at a second constant potential terminal to the output signal terminal under control of the signal at the second node,
wherein the output unit comprises an eighth transistor and a ninth transistor, wherein
the eighth transistor has a control terminal connected to the first node, a first terminal connected to the second clock signal terminal and a second terminal connected to the output signal terminal, and
the ninth transistor has a control terminal connected to the second node, a first terminal connected to the second constant potential terminal and a second terminal connected to the output signal terminal.

US Pat. No. 10,657,876

GATE DRIVING CIRCUIT FOR PROVIDING PRESENT VOLTAGE BY TRANSMISSION PATH IN NON-OPERATIVE STATE AND DISPLAY DEVICE

BEIJING BOE OPTOELECTRONI...

1. A gate driving circuit, comprising:N-stage gate driving units, the gate driving unit at each stage of the N-stage gate driving units having a first voltage terminal and a clock signal terminal, and a first transmission path being formed between the first voltage terminal and the clock signal terminal, wherein N is an integer greater than 1, and at each stage, the first transmission path of the gate driving unit is conductive when the gate driving unit is in a non-operative state; and
a first voltage line connected to the first voltage terminal of the gate driving unit at each stage,
wherein a preset voltage received by the clock signal terminal of the gate driving unit that is in a non-operative state is transmitted to the first voltage line through the first transmission path of the gate driving unit, so that the first voltage line provides the preset voltage for the first voltage terminal of the gate driving unit at each stage,
wherein the gate driving unit at each stage comprises an output unit, an input unit and a first pull-down unit,
in the gate driving unit at each stage, the first transmission path is formed by the output unit and the first pull-down unit,
the output unit is connected to the clock signal terminal, the input unit of the gate driving unit and an output terminal of the gate driving unit,
the first pull-down unit is connected to the first voltage terminal and the output terminal of the gate driving unit, and
the gate driving unit at each stage comprises a reset unit and a second pull-down unit, wherein in the gate driving unit at each stage, the second transmission path is formed by the reset unit and the second pull-down unit, the reset unit is connected to the second voltage terminal, the output unit, the input unit of the gate driving unit and the second pull-down unit, and the second pull-down unit is connected to the first voltage terminal and the reset unit.

US Pat. No. 10,657,875

DISPLAY DRIVING DEVICE AND A DISPLAY SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display driving device, comprising:a gate driver configured to provide a first gate selection signal to a first gate line of a display panel to select the first gate line;
a source driver configured to provide an image signal corresponding to the first gate line to a source line;
an Electrostatic Discharge (ESD) detection circuit configured to receive a power supply voltage, determine whether there is an ESD in the power supply voltage and, when the ESD is detected, generate a first detection signal; and
a controller configured to receive the first detection signal to generate a masking signal,
wherein the gate driver is configured to receive the masking signal and not provide a second gate selection signal to select a second gate line,
wherein the gate driver is configured to not provide the second gate selection signal during a first in which a first vertical synchronization signal is enabled, and
when a second vertical synchronization signal is enabled, the gate driver is configured to provide the second ate selection signal.

US Pat. No. 10,657,874

OVERDRIVE FOR ELECTRONIC DEVICE DISPLAYS

Apple Inc., Cupertino, C...

1. An electronic device comprising a display configured to show content, wherein the content comprises a plurality of frames comprising:a first frame, wherein the first frame is associated with a pre-transition value; and
a second frame, wherein the second frame is associated with a current frame value;
wherein the electronic device is configured to:
determine a preliminary compensated current frame value corresponding to a first luminance of a third frame in a transition from the first frame to the second frame to the third frame;
determine a final compensated current frame value corresponding to a second luminance of the third frame in a transition from the first frame to the second frame to the third frame in which the second frame is associated with the preliminary compensated current frame value; and
display the second frame using the final compensated current frame value.

US Pat. No. 10,657,873

SYSTEM AND METHOD FOR SUBPIXEL RENDERING AND DISPLAY DRIVER

Synaptics Japan GK, Toky...

1. A display driver comprising:subpixel rendering circuitry configured to:
generate, from input image data describing input grayscale values associated with N pixels of an input image, output image data describing output grayscale values associated with M corresponding pixels of an output image corresponding to the N pixels of the input image, N being an integer of two or more and M being an integer satisfying 1?M calculate input-side squared grayscale values which are squares of the input grayscale values for the respective N pixels of the input image;
calculate correction values associated with the M corresponding pixels from a correction parameter determined in response to a gamma value set to the display driver and the input grayscale values; and
generate the output image data by independently correcting the input-side squared grayscale values based on the correction values; and
drive circuitry configured to drive a display panel in response to the output image data.

US Pat. No. 10,657,872

DISPLAY DEVICE

AU OPTRONICS CORPORATION,...

1. A display device, comprising:a plurality of pixels, comprising a first column of pixels, a second column of pixels, a third column of pixels, a fourth column of pixels, a fifth column of pixels, a sixth column of pixels, a seventh column of pixels, an eighth column of pixels, a ninth column of pixels, a tenth column of pixels, an eleventh column of pixels, and a twelfth column of pixels that are sequentially configured from left to right;
a plurality of gate lines, configured to output corresponding scan signals to corresponding pixels;
a plurality of data lines, the plurality of data lines comprising 12 successive data lines from left to right, configured to receive a piece of display data and output corresponding pixel voltages respectively to a first column of pixels, a second column of pixels, a third column of pixels, a fourth column of pixels, a fifth column of pixels, a sixth column of pixels, a seventh column of pixels, an eighth column of pixels, a ninth column of pixels, a tenth column of pixels, an eleventh column of pixels, and a twelfth column of pixels;
a gate driver, electrically coupled to the gate lines, configured to drive the plurality of pixels; and
a data driver, electrically coupled to the data lines, configured to provide data signals to the plurality of pixels, wherein the data driver respectively provides data with polarities of: positive, negative, positive, negative, positive, negative, negative, positive, negative, positive, negative, and positive to the 12 data lines, and
each column of pixels comprises at least two of a pixel in a first form (PH) corresponding to a pixel voltage (VH), a pixel in a second form (PL) corresponding to a pixel voltage (VL), and a pixel in a third form (PI) corresponding to a pixel voltage (VI);
wherein a pixel group (Pt) comprises four pixels that display a same color: one pixel in the first form (PH), two pixels in the second form (PL), and one pixel in the third form (PI); and when the display data of the pixel in the first form (PH) of the pixel group (Pt) and that of the two pixels in the second form (PL) of the pixel group (Pt) have same gray scale, the data driver respectively provides a first pixel voltage and a second pixel voltage to the pixel in the first form (PH) of the pixel group (Pt) and the two pixels in the second form (PL) of the pixel group (Pt), and the first pixel voltage is greater than the second pixel voltage.

US Pat. No. 10,657,871

TIMING CONTROLLER, DATA DRIVER, DISPLAY DEVICE, AND METHOD OF DRIVING THE DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a display panel on which a number of data lines, a number of gate lines, and a number of subpixels defined by the number of data lines and the number of gate lines are disposed;
a data driver circuit driving the number of data lines;
a gate driver circuit driving the number of gate lines; and
a timing controller controlling the data driver circuit and the gate driver circuit,
wherein the timing controller shifts data having n gray scale into data having m gray scale greater than the n gray scale by K gray scale, where the n is a real number equal to or greater than 0, the K is a positive integer, and the m is n+K, and transfers the data having the m gray scale to the data driver circuit, and
wherein the data driver circuit receives and converts the data having the m gray scale to a data voltage for expressing the n gray scale by referring to a shift gamma look-up table, and outputs the data voltage for expressing the n gray scale to a corresponding data line among the number of data lines.

US Pat. No. 10,657,870

METHOD AND DEVICE FOR DISPLAY COLOR ADJUSTMENT

Synaptics Japan GK, Toky...

1. A method for use with a display apparatus comprising color correction circuitry and drive circuitry, the method comprising:measuring luminance coordinate data for at least:
a first color displayed when image data corresponding to a white point is supplied to the drive circuitry, wherein the white point is a white color of a maximum allowed grayscale value;
a second color displayed when image data corresponding to a white color of a first intermediate grayscale value is supplied to the drive circuitry, wherein the first intermediate grayscale value corresponds to grayscale values for a plurality of elementary colors, wherein the grayscale values for the plurality of elementary colors are equal to each other; and
respective third colors displayed when image data corresponding to respective elementary color points for each of the plurality of elementary colors is supplied to the drive circuitry;
calculating, based on the luminance coordinate data, first gamma values for the white color of the first intermediate grayscale value;
calculating, based at least on the first gamma values, second gamma values for at least one of the plurality of elementary colors;
calculating, using the second gamma values, desired values for displaying the white point and for displaying an adjustment target color; and
calculating, based on the desired values for displaying the white point and for displaying the adjustment target color, correction parameters to apply to the color correction circuitry.

US Pat. No. 10,657,869

METHODS FOR DRIVING COLOR ELECTROPHORETIC DISPLAYS

E Ink Corporation, Bille...

1. A method for reducing flashiness when addressing a color electrophoretic display having pixels, the method comprising:applying a series of voltages to effect a transition in a first pixel from a first optical state to a second optical state; and
applying the series of voltages to effect the transition in a second pixel from the first optical state to the second optical state after an offset period, wherein the offset period lasts for a duration shorter than the applying of the series of voltages,
thereby reducing the number of pixels that are transitioning between the same color states that are oscillating between extreme optical states at the same time to minimize the flashiness.

US Pat. No. 10,657,868

DISPLAY APPARATUS AND CORRECTION METHOD

Sony Semiconductor Soluti...

1. A display apparatus, comprising:a display section comprising a plurality of display units arranged in a two-dimensional array, wherein each of the display units comprises a plurality of pixels arranged in a matrix, and each of the plurality pixels comprises a plurality of light-emitting devices that each emit a different color of light; and
circuitry configured to generate a corrected image signal based on an uncorrected image signal and correction factors that correct luminance and chromaticity of the light-emitting devices, including correction factors determined by adjusting light emission intensity ratios of first light-emitting devices that emit light of a particular color and are disposed in different ones of the plurality of pixels, wherein each of the display units comprises a unit array of pixel assemblies that each comprises a plurality of adjacent pixels, the first light-emitting devices vary in light emission wavelength according to pixel positions, at least one of the correction factors is determined for each of the pixel assemblies by adjusting light emission intensity ratios of the first light-emitting devices disposed in different pixels, and the correction factor for each of the pixel assemblies is determined by performing a calculation in which the light emission intensity ratios of the first light-emitting devices in that pixel assembly are assumed to have a uniform value.