US Pat. No. 10,367,187

STORAGE BATTERY INCLUDING A DISCONNECTOR HAVING A FUSE AND AN EXPLOSIVE WITH A HEAT BRIDGE PROVIDING CONTINUITY OF SERVICE IN THE EVENT OF A MALFUNCTION

1. A storage battery, comprising:first and second stages electrically connected in series, each stage including at least first, second, and third accumulator electrically connected in parallel;
at least first and second disconnectors by which the first, second, and third accumulators of the first stage are connected in parallel and by which the first, second, and third accumulators of the second stage are connected in parallel, each of the disconnectors including a first electrode and a second electrode,
wherein each of the first and second disconnectors includes:
a fuse including a conducting link connected in series between the first and second electrodes and including a fusible portion, and
an explosive, with a heat bridge between the fuse and the explosive so that heating of the fuse forms a detonator initiating the explosion of the explosive, the explosion of the explosive causing the conducting link to open, the explosive having an explosion initiation temperature that is lower than the melting point of the fusible portion,
wherein the explosion of the explosive of one of the first and second disconnectors does not affect the status of the conducting link of the other one of the first and second disconnectors.

US Pat. No. 10,367,186

SECONDARY BATTERY INCLUDING AN INSULATING MEMBER

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:an electrode assembly comprising a first electrode and a second electrode;
a case containing the electrode assembly;
a cap plate sealing an opening of the case;
a collector terminal electrically connected to the first electrode of the electrode assembly and protruding through the cap plate to an outside of the case;
a coupling plate on the cap plate;
an insulating member on at least one area of the coupling plate; and
a terminal plate on the coupling plate and coupled to the collector terminal at the outside of the case, the insulating member being between the terminal plate and an outer surface of the cap plate,
wherein, in a normal operating state in which the first electrode and the second electrode are not short circuited, the terminal plate is electrically connected to the first electrode of the electrode assembly through the collector terminal and is electrically connected to the cap plate through at least a portion of the coupling plate that is in contact with the cap plate, and the second electrode of the electrode assembly is electrically insulated from the cap plate.

US Pat. No. 10,367,184

RECHARGEABLE BATTERY

SAMSUNG SDI CO., LTD., Y...

1. A rechargeable battery, comprising:an electrode assembly including a first electrode, a separator, and a second electrode;
a case that accommodates the electrode assembly;
a first lead terminal and a second lead terminal that are respectively connected to the first electrode and the second electrode of the electrode assembly, the first and second lead terminals being drawn out of the case; and
a fixing member that surrounds the first lead terminal and the second lead terminal,
wherein the first lead terminal includes a first region and a second region adjacent to each other along a first direction, longitudinal directions of each of the entire first and second regions extending entirely along the first direction from opposite sides of the fixing member,
wherein the second lead terminal includes a third region and a fourth region adjacent to each other along the first direction, longitudinal directions of each of the entire third and fourth regions extending entirely along the first direction from opposite sides of the fixing member, and
wherein a width of the first region and a width of the second region are different from each other along a second direction perpendicular to the first direction, and a width of the third region and a width of the fourth region are different from each other along the second direction.

US Pat. No. 10,367,182

LAMINATED BODY

SUMITOMO CHEMICAL COMPANY...

1. A laminated body, comprising: a porous base material containing a polyolefin-based resin as a main component; and a porous layer disposed on at least one surface of the porous base material, the porous layer containing a polyvinylidene fluoride-based resin,the porous base material having (i) a phase difference of not more than 80 nm with respect to light with a wavelength of 590 nm in a state where the porous base material is impregnated with ethanol and (ii) a porosity within a range of 30% to 60%,
the polyvinylidene fluoride-based resin containing crystal form ? in an amount of not less than 34 mol % with respect to 100 mol % of a total amount of the crystal form ? and crystal form ? contained in the polyvinylidene fluoride-based resin,
wherein the amount of crystal form ? is calculated from an absorption intensity at around 765 cm?1 in an IR spectrum of the porous layer, while an amount of crystal form ? is calculated from an absorption intensity at around 840 cm?1 in the IR spectrum of the porous layer.

US Pat. No. 10,367,180

BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A battery pack, comprising:a battery holder comprising a cell holder accommodating a plurality of battery cells and a flange formed on a lateral side of the cell holder, wherein at least one coupling hole is formed in the flange;
a lead terminal comprising a lead plate and a lead tab, wherein the lead plate covers electrodes of the battery cells, wherein the lead tab extends from the lead plate toward the flange, wherein the lead tab includes a first portion downwardly extending from an end of the lead plate and a second portion outwardly extending from the first portion, wherein the first and second portions are formed on different planes, wherein at least one coupling hole is formed in the second portion of the lead tab, and wherein the second portion of the lead tab does not vertically overlap the lead plate;
a bus bar configured to form an electrical path between the lead tab and an external terminal, wherein at least one coupling hole is formed in the bus bar; and
a pack case comprising a coupler, wherein the external terminal is formed on the pack case, wherein a fastener is inserted into the at least one coupling hole of the bus bar, the at least one coupling hole of the second portion of the lead tab, and the at least one coupling hole of the flange, and wherein the fastener is engaged with the coupler.

US Pat. No. 10,367,175

MULTICAVITY BATTERY MODULE

Bosch Bettery Systems LLC...

1. A battery module, the battery module including a battery module housing and an electrochemical cell disposed in the battery module housing,the battery module housing including
a first exterior wail comprising a first sheet of a first flexible laminate material,
a second exterior wall comprising a second sheet of the first flexible laminate material, the second exterior wall, together with the first exterior wall, defining an interior space therebetween, and
at least one interior wall that segregates the interior space into at least two cavities, the at least one interior wall comprising a third sheet of the first flexible laminate material, the third sheet being disposed between the first sheet and the second sheet in a stacked arrangement of the first sheet, the second sheet and the third sheet, wherein
the electrochemical cell is disposed in one of the at least two cavities, the electrochemical cell comprising a cell housing that is formed of a second flexible laminate material, and an electrode assembly that is disposed inside the cell housing, and
a peripheral edge of the first exterior wall, a peripheral edge of the second exterior wall, and a peripheral edge of the at least one interior wall are joined together at a single, common seal joint.

US Pat. No. 10,367,166

DISPLAY DEVICE HAVING DAM WITH PLATE-SHAPED FILLERS

LG Display Co., Ltd., Se...

1. A display device, comprising:a first substrate;
an emitting diode on the first substrate;
a second substrate on the emitting diode; and
a dam between the first substrate and the second substrate and surrounding the emitting diode, the dam including a resin and plate-shaped fillers,
wherein the plate-shaped fillers are arranged to be non-parallel to a surface of the first substrate, and
wherein the plate-shaped fillers in the dam at one side of the display device are arranged in a first direction, and the plate-shaped fillers in the dam at an opposite side of the display device is arranged in a second direction that is non-parallel to the first direction.

US Pat. No. 10,367,164

FOLDABLE DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A foldable display apparatus that is adjustable between a folded configuration and an unfolded configuration, the foldable display apparatus comprising:a flexible display panel that is foldable;
a case comprising:
a first case that supports a first side of the flexible display panel; and
a second case that supports a second side of the flexible display panel;
an elastic piece connecting the first case to the second case, the elastic piece being substantially flat in the unfolded configuration;
a link member connecting the first case to the second case and comprising a concave-convex type single body metal sheet; and
a locking unit configured to prevent rotation of the first case and the second case in a folding direction when the foldable display apparatus is in the unfolded configuration.

US Pat. No. 10,367,163

ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode, comprising:a first electrode and a second electrode facing each other;
an emission layer between the first electrode and the second electrode; and
a hole injection layer between the first electrode and the emission layer, the hole injection layer including a dipole material including a first component and a second component that have different polarities,
wherein the emission layer includes a red emission layer, a green emission layer, and a blue emission layer, and further includes an auxiliary layer only under the blue emission layer such that the auxiliary layer is not included between the red emission layer and the hole injection layer and the auxiliary layer is not included between the green emission layer and the hole injection layer, and
wherein the auxiliary layer includes a compound expressed by the following Chemical Formula 1:

wherein, in Chemical Formula 1, A1, A2, and A3 are each hydrogen, a phenyl group, carbazole, dibenzothiophene, dibenzofuran (DBF), and biphenyl, and a, b, and c are each an integer of zero to four, and
wherein at least one of A1, A2, and A3 is

US Pat. No. 10,367,149

ORGANIC LIGHT-EMITTING DEVICE

LG Chem, Ltd., (KR)

1. An organic light emitting device comprising:a positive electrode;
a negative electrode provided to face the positive electrode; and
an organic material layer between the positive electrode and the negative electrode,
wherein the organic material layer comprises a light emitting layer,
the organic material layer further includes an electron adjusting layer and an electron transport layer provided between the light emitting layer and the negative electrode,
the electron adjusting layer includes a compound represented by the following Chemical Formula 1, and
the electron transport layer includes a compound represented by the following Chemical Formula 11:

in Chemical Formula 1,
Ar1 and Ar2 are the same as or different from each other, and are each independently a substituted or unsubstituted aryl group; or a substituted or unsubstituted heterocyclic group, and
L1 is represented by any one of the following Chemical Formulae 2 to 5,

in Chemical Formulae 2 to 5,
a dotted line “” is each a moiety bonded to a triazine group or L2 of Chemical Formula 1,
S1 to S4 are the same as or different from each other, and are each independently hydrogen; deuterium; a halogen group; a substituted or unsubstituted alkyl group; a substituted or unsubstituted aryl group; or a substituted or unsubstituted heterocyclic group,
p and q are the same as or different from each other, and are each independently an integer of 0 to 6,
r is an integer of 0 to 8,
y is an integer of 0 to 4,
when p, q, r, and y are each an integer of 2 or more, a plurality of S1 to S4 are each the same as or different from each other,
L2 is a direct bond; or a substituted or unsubstituted arylene group,
Ar3 is represented by a substituted or unsubstituted aryl group; a substituted or unsubstituted heterocyclic group including S or O; a substituted or unsubstituted carbazole group; or any one of the following Chemical Formulae 6 to 10, when L1 is Chemical Formulae 2 to 4,
Ar3 is represented by a substituted or unsubstituted aryl group; a substituted or unsubstituted heterocyclic group including S or O; or any one of the following Chemical Formulae 6 to 10, when L1 is Chemical Formula 5,

in Chemical Formulae 6 to 10,
X1 is O, S, or NR,
at least two of X2 to X6 are N, and the others are each independently CR?,
R and R? are the same as or different from each other, and are each independently hydrogen; deuterium; a halogen group; a substituted or unsubstituted alkyl group; or a substituted or unsubstituted aryl group,
R1 to R6, R9, and R10 are the same as or different from each other, and are each independently hydrogen; deuterium; a halogen group; a substituted or unsubstituted alkyl group; a substituted or unsubstituted aryl group; or a substituted or unsubstituted heterocyclic group,
at least one of Y1 to Y4 is N, and the others are CR?,
R? is each independently hydrogen or deuterium,
R7 and R8 are directly bonded, or combine with each other to form a substituted or unsubstituted ring,
m, n, t, u, v, and x are each an integer of 0 to 4, w is an integer of 0 to 3, and when m, n, t, u, v, w, and x are each an integer of 2 or more, a plurality of R1 to R6, R9, and R10 are each the same as or different from each other,
s is an integer of 0 to 2, and when s is 2, two R3s are the same as or different from each other,
“” means a moiety bonded to L2 of Chemical Formula 1, and the bonding moiety of Chemical Formula 10 is bonded to a ring formed by bonding R6, R9, R10 or R7, and R8,

in Chemical Formula 11, at least two of X10 to X12 are N, and the other is each independently CR??,
R?? is hydrogen; deuterium; a halogen group; a substituted or unsubstituted alkyl group; or a substituted or unsubstituted aryl group,
Ar4 to Ar6 are the same as or different from each other, and are each independently a substituted or unsubstituted aryl group; or a substituted or unsubstituted heterocyclic group,
L3 is a direct bond; a substituted or unsubstituted arylene group; or a substituted or unsubstituted divalent heterocyclic group, and
l is 1 or 2, and when 1 is 2, Ar6s are the same as or different from each other.

US Pat. No. 10,367,144

STABLE ORGANIC FIELD-EFFECT TRANSISTORS BY INCORPORATING AN ELECTRON-ACCEPTING MOLECULE

THE REGENTS OF THE UNIVER...

1. One or more organic field effect transistor (OFET)s, comprising:semiconducting polymers combined with electron acceptors so as to change an ambipolar transport of the semiconducting polymers to p-type transport;
a source contact to a p-type channel including the semiconducting polymers;
a drain contact to the p-type channel; and
a dielectric between a gate contact and the p-type channel.

US Pat. No. 10,367,139

METHODS OF MANUFACTURING MAGNETIC TUNNEL JUNCTION DEVICES

Spin Memory, Inc., Fremo...

1. A method of manufacturing a Magnetic Tunnel Junction (MTJ) device comprising:forming portions of MTJ pillars including a free magnetic layer;
forming a conformal first insulating layer on the portion of MTJ pillars;
etching the conformal first insulating layer to form first sidewall insulators self-aligned to the MTJ pillars;
forming a first metal layer;
forming a conformal second insulating layer;
etching the conformal second insulating layer to form second sidewall insulators self-aligned to the MTJ pillars; and
selectively etching the first metal layer and the free magnetic layer to further form the MTJ pillars including pillar contacts coupled to the free magnetic layer.

US Pat. No. 10,367,137

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY HAVING A VARIABLE RESISTANCE ELEMENT INCLUDING TWO FREE LAYERS

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory comprising a variable resistance element exhibiting different resistance states for storing data, the variable resistance element comprising:a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein the free layer includes:
a first free layer adjacent to the tunnel barrier layer and including CoFeB alloy; and
a second free layer spaced apart from the tunnel barrier layer by the first free layer and including at least one of CoFeBCd alloy or CoFeBSb alloy;
the variable resistance element further comprises: a seed layer under the free layer; and a capping layer on the pinned layer, wherein the first free layer is closer to the capping layer than the second free layer, and the second free layer is closer to the seed layer than the first free layer.

US Pat. No. 10,367,135

METHOD OF FABRICATING A BASE PLATE FOR PIEZO ACTUATION

INTRI-PLEX TECHNOLOGIES, ...

1. A method of fabricating a base plate for a head suspension assembly that prevents interlocking of multiple base plates when packaged together and adds structural integrity during shipping, the method comprising:providing a plate;
creating at least one opening through the plate, the plate including a first spanning portion that extends from a first side of the at least one opening to a second side of the at least one opening;
lancing the first spanning portion adjacent the first side and adjacent the second side, so that the first spanning portion becomes removable by a reduced shear force where lanced;
leaving the first spanning portion in place;
packaging base plates with the first spanning portion in place for shipping to a destination; and
removing the first spanning portion from each base plate upon receipt at the destination.

US Pat. No. 10,367,134

SHADOW MASK SIDEWALL TUNNEL JUNCTION FOR QUANTUM COMPUTING

INTERNATIONAL BUSINESS MA...

1. A tunnel junction device comprising:a first conducting layer having a height dimension greater than a width dimension, wherein a bottom of the first conducting layer is nearest to a substrate and a top of the first conducting layer is farthest from the substrate, wherein the height dimension extends vertically from the bottom to the top;
an oxide layer formed on the first conducting layer; and
a second conducting layer on the oxide layer covering a side portion of the first conducting layer, such that the oxide layer forms a sidewall tunnel junction between the second conducting layer and the side portion of the first conducting layer, wherein an angled portion of the second conducting layer is formed on a top of the first conducting layer such that an angled tunnel junction is formed, wherein the angled portion having a triangular shaped surface positioned to the angled tunnel junction.

US Pat. No. 10,367,132

NANOSCALE DEVICE COMPRISING AN ELONGATED CRYSTALLINE NANOSTRUCTURE

University of Copenhagen,...

1. A nanoscale device comprisingan elongated crystalline semiconductor nanostructure having a plurality of substantially plane side facets, and
a crystalline structured first facet layer of a superconductor material covering at least a part of at least one of said side facets,wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

US Pat. No. 10,367,130

METHOD FOR PRODUCING NANOMATERIAL-DOPANT COMPOSITION COMPOSITE, NANOMATERIAL-DOPANT COMPOSITION COMPOSITE, AND DOPANT COMPOSITION

NATIONAL UNIVERSITY CORPO...

1. A method for manufacturing a dopant composition-nanomaterial composite, the method comprising the steps of:(a) putting a dopant composition in contact with a nanomaterial in a solvent; and
(b) drying a mixture obtained in the step (a) so as to remove the solvent,
wherein the dopant composition is a composition for changing a Seebeck coefficient of the nanomaterial,
wherein the dopant composition contains an anion and a cation,
wherein the anion is at least one selected from the group consisting of hydroxy ions, alkoxy ions, SH?, CH3S?, C2H5S?, cyanide ions, and carboxy ions,
wherein the cation is
an onium ion represented by formula (I):

where Y is a nitrogen atom or a phosphorus atom; and R1 through R4 are each independently an alkyl group having 1 to 16 carbon atom(s), or
an onium ion having, as a skeleton, oxonium, sulfonium, fluoronium, chloronium, carbocation, iminium, diazenium, nitronium, nitrilium, diazonium, nitrosonium, imidazolium, or pyridinium, and
wherein the dopant composition-nanomaterial composite obtained in the step (b) contains both the anion and the cation, and the anion and the cation are dissociated from one another.

US Pat. No. 10,367,121

PACKAGE AND LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A package having a recess comprising:a pair of leads forming a surface of a bottom portion on the recess;
a first resin body forming a lateral wall on the recess;
a second resin body arranged between the pair of leads; and
a reflective film covering an inner surface of the lateral wall on the recess and an upper surface and a lower surface of the second resin body.

US Pat. No. 10,367,120

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A light-emitting diode, comprising:a light-emitting epitaxial laminated layer including:
a first semiconductor layer;
an active layer; and
a second semiconductor layer;
an ohmic contact layer over an upper surface of the light-emitting epitaxial laminated layer;
an expanding electrode over the ohmic contact layer;
a transparent insulating layer that covers the expanding electrode and an exposed ohmic contact layer and having a hole through the transparent insulating layer in a position corresponding to the expanding electrode; and
a welding wire electrode over the transparent insulating layer and coupled to the expanding electrode via the hole.

US Pat. No. 10,367,118

LIGHT-EMITTING DIODE

EPISTAR CORPORATION, Hsi...

1. A light-emitting diode, comprising:an active layer;
an upper semiconductor stack on the active layer and comprising a window layer; and
a lower semiconductor stack below the active layer and comprising multiple semiconductor layers which combined have a thickness smaller than or equal to 1 ?m,
wherein the multiple semiconductor layers comprise a confining layer below the active layer, a cladding layer below the confining layer, a buffer layer below the cladding layer and a lower contact layer below the cladding layer.

US Pat. No. 10,367,117

APPARATUS AND METHOD FOR TRANSFERRING MICRO LIGHT-EMITTING DIODES

SHENZHEN CHINA STAR OPTOE...

1. An apparatus for transferring micro light-emitting diodes, which comprises: a main body, and a spraying module, a cooling module and a heating module disposed on said main body;said spraying module applied for spraying metallic adhesive liquid onto the micro light-emitting diodes that wait to transfer;
said cooling module applied for cooling the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes, thereby curing the metallic adhesive liquid to adhesively bond the main body with the wait-to-transfer micro light-emitting diodes together; and
said heating module applied for heating the cured metallic adhesive liquid, thereby melting the metallic adhesive liquid to separate the main body from the wait-to-transfer micro light-emitting diodes;
wherein said main body comprises a number of sequentially arranged transfer heads each disposed with a spraying nozzle on a bottom portion thereof, said spraying module sprays the metallic adhesive liquid onto the wait-to-transfer micro light-emitting diodes by the spraying nozzle;
wherein each neighboring pair of the transfer heads are disposed with a gas-blowing hole on therebetween, said cooling module blows gas outwardly via the gas-blowing hole, for cooling the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes.

US Pat. No. 10,367,116

METHOD OF REDUCING SODIUM CONCENTRATION IN A TRANSPARENT CONDUCTIVE OXIDE LAYER OF A SEMICONDUCTOR DEVICE

BEIJING APOLLO DING RONG ...

1. A semiconductor device manufacturing apparatus, comprising:at least one semiconductor deposition module configured to form a semiconductor material stack including a p-n junction on a substrate;
a conductive oxide deposition module configured to deposit a transparent conductive oxide layer over the semiconductor material stack; and
a fluid treatment module configured to contact a physically exposed surface of the transparent conductive oxide layer with a fluid to remove sodium from the transparent conductive oxide layer.

US Pat. No. 10,367,115

METHOD OF MANUFACTURING SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A method of manufacturing a solar cell, the method comprising:forming a silicon oxide film on a semiconductor substrate;
successively exposing the silicon oxide film to a temperature in a range of 570° C. to 700° C. to anneal the silicon oxide film; and
wherein the silicon oxide film is slowly heated from a temperature lower than 700° C. to about 700° C. for a first time period, maintained at the temperature of about 700° C. for a second time period, and then slowly cooled to the lower temperature for a third time period during annealing.

US Pat. No. 10,367,111

APD FOCAL PLANE ARRAYS WITH BACKSIDE VIAS

ARGO AI, LLC, Pittsburgh...

1. An article comprising a plurality of avalanche photodiodes (APDs), each APD comprising:a substrate layer having a first surface proximal to a back side of the APD and a second surface, wherein, in operation, input light is received at the first surface of the substrate layer and propagates toward the second surface thereof;
a buffer layer having a first surface and a second surface, wherein the first surface of the buffer layer abuts the second surface of the substrate layer;
active device layers, one surface of which abuts the second surface of the buffer layer; and
a via extending from the first surface of the substrate layer and passing at least partially through the substrate layer towards the second surface thereof extending, at most, to the first surface of the buffer layer, wherein the via is offset from the active device layers and does not deliver light to an active region of the active device layers.

US Pat. No. 10,367,110

PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING

First Solar, Inc., Tempe...

1. A process for manufacturing a photovoltaic device having a front contact layer stack and a semiconductorer stack, the process comprising:plasma cleaning an exposed surface of the semiconductor stack by exposing it to a plasma of ionized gases, wherein the plasma cleaning step removes from about 5 to about 500 angstroms at the surface of the exposed surface;
exposing the exposed surface of the semiconductor stack to an atmosphere that contains from about 1% to about 60% oxygen in an otherwise inert atmosphere to form an oxide layer on the exposed surface; and
forming a back contact layer stack on the oxide layer.

US Pat. No. 10,367,109

BACK SHEET OF SOLAR CELL MODULE, AND SOLAR CELL MODULE

DAIKIN INDUSTRIES, LTD., ...

1. A back sheet for a solar cell module, comprising:a water-impermeable sheet; and
a film,
the film being disposed on at least one side of the water-impermeable sheet and being formed from a coating containing a fluorine-containing copolymer,
the fluorine-containing copolymer containing:
(a) a C2-C3 perhaloolefin structural unit;
(b) a vinyl acetate structural unit;
(c) a hydroxy-containing vinyl monomer structural unit represented by the formula (1):
CH2?CH—(CH2)l—O—(CH2)m—OH,wherein 1 is 0 or 1, and m is an integer of 2 or greater; and(d) a carboxy-containing monomer structural unit represented by the formula (2):
R1R2C?CR3—(CH2)n—COOHwherein R1, R2, and R3 are the same as or different from each other, and are each a hydrogen atom or a C1-C10 linear or branched alkyl group, and n is 0 or 1.

US Pat. No. 10,367,106

INTEGRATED PHOTODETECTOR WAVEGUIDE STRUCTURE WITH ALIGNMENT TOLERANCE

INTERNATIONAL BUSINESS MA...

1. A sensor structure, comprising:a photodetector with a window exposing a portion of a waveguide structure; and
an encapsulating material of a single material fully encapsulating and surrounding the photodetector, wherein the encapsulating material extends across and directly contacts an uppermost surface of the photodetector, and the encapsulating material is within divots or recesses in shallow trench isolation (STI) structures.

US Pat. No. 10,367,102

ELECTRONIC COMPONENT AND EQUIPMENT

CANON KABUSHIKI KAISHA, ...

1. An electronic component comprising:a support member in which a recess part having a bottom face and a side face is provided; and
a device unit that includes a substrate and fixed to the support member so that a primary face of the substrate faces the recess part,
wherein an opening width of the recess part is, on a side of a bottom of the recess part with respect to the primary face, narrower than a width of the device unit and, on an opposite side of the bottom of the recess part with respect to the primary face, wider than the width of the device unit,
wherein an end face of the substrate overlaps with the side face of the recess part in a direction perpendicular to the primary face of the substrate, and
wherein a photoelectric conversion element is arranged on the primary face of the substrate.

US Pat. No. 10,367,099

TRENCH VERTICAL JFET WITH LADDER TERMINATION

United Silicon Carbide, I...

1. A vertical JFET, comprising:a) a substrate, the substrate having a top and a bottom vertically, the substrate having a perimeter horizontally;
b) an active cell region, the active cell region being on the top of the substrate and comprising source regions, gate regions, active region trenches, and active region mesas;
c) a backside drain connection, the backside drain connection being on the bottom of the substrate;
d) a termination region, the termination region being on the top of the substrate and comprising termination region trenches and termination region mesas;
e) in each mesa of the termination region, a region with source doping, the region with source doping being at the top of the mesa and having an N doping type and a doping concentration that is the same as the doping concentration of the source regions, wherein the regions with source doping are ohmically isolated from each other and from the source regions; and
f) in each termination region mesa, a region with gate doping, the region with gate doping being on each wall of the mesa and having a P doping type and a doping concentration that is the same as the doping concentration of the gate regions, wherein the regions with gate doping are ohmically isolated from each other and from the gate regions,
g) such that in each mesa of the termination region, the regions with gate doping on each wall of the mesa abut and form a PNP structure with the region with source doping.

US Pat. No. 10,367,095

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, OR DISPLAY DEVICE INCLUDING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor including:
a first gate electrode;
a first insulating film over the first gate electrode;
an oxide semiconductor film over the first insulating film;
a source electrode electrically connected to the oxide semiconductor film;
a drain electrode electrically connected to the oxide semiconductor film;
a second insulating film over the oxide semiconductor film;
a second gate electrode over the second insulating film; and
a third insulating film over the second gate electrode,
wherein the oxide semiconductor film includes a first oxide semiconductor film over the first insulating film, and a second oxide semiconductor film over the first oxide semiconductor film,
wherein the second gate electrode includes a third oxide semiconductor film over the second insulating film, and a fourth oxide semiconductor film over the third oxide semiconductor film,
wherein the first oxide semiconductor film, the second oxide semiconductor film, the third oxide semiconductor film, and the fourth oxide semiconductor film include In, Ga, and Zn,
wherein the first oxide semiconductor film includes a region satisfying In>Ga,
wherein the second oxide semiconductor film includes a region satisfying In?Ga,
wherein the third oxide semiconductor film includes a region satisfying In wherein the fourth oxide semiconductor film includes a region satisfying In>Ga.

US Pat. No. 10,367,089

SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY

GENERAL ELECTRIC COMPANY,...

1. A semiconductor device, comprising:a semiconductor substrate comprising silicon carbide, said substrate having a first surface and a second surface;
a contact layer disposed on the first surface of the substrate covering a portion of a source contact region;
a gate electrode disposed on a portion of the first surface of the substrate;
a drain electrode disposed on the second surface of the substrate;
a dielectric layer disposed on the gate electrode and extending in a direction normal to the first surface;
a remedial layer disposed on the dielectric layer, wherein said remedial layer is configured to mitigate negative bias temperature instability such that a change in threshold voltage is in a range of between 100 millivolts to 1 volt, wherein said change in threshold voltage occurs under a gate to source voltage bias and when a drain current is about 10 microamps with a VDS=0.1 V, wherein said remedial layer has a thickness of less than about 300 nm; and
a source electrode disposed on said remedial layer, wherein said source electrode is electrically coupled to the source contact region of the semiconductor substrate,
wherein said remedial layer comprises titanium and is configured to provide a continuous conformal coverage of the dielectric layer including in the direction normal to the first surface.

US Pat. No. 10,367,086

LATERAL FIN STATIC INDUCTION TRANSISTOR

HRL Laboratories, LLC, M...

1. A transistor comprising:source and drain regions disposed on a substrate;
a semi conductive fin disposed on the substrate between the source and drain regions;
a gate structure and a dielectric layer associated with the fin, the fin having at least one face covered by the gate structure and dielectric layer, the dielectric layer electrically insulating the gate structure from the fin; wherein
the source and drain regions comprise diamond doped with a P-type dopant, and
the semi conductive fin comprises diamond doped with a P-type dopant, wherein the P-type dopant concentration of the semi conductive fin is less than the P-type dopant concentration of the source and drain regions.

US Pat. No. 10,367,085

IGBT WITH WAVED FLOATING P-WELL ELECTRON INJECTION

Littelfuse, Inc., Chicag...

12. A semiconductor device comprising:a P type collector layer;
an N? type drift layer disposed over the P type collector layer;
a P type body region that extends into the N? type drift layer;
an N+ type emitter region, wherein the N+ type emitter region extends into the P type body region from an upper semiconductor surface;
a floating P type well region that extends into the semiconductor device from the upper semiconductor surface and that is laterally separated from the P type body region, wherein the floating P type well region has a concentric thinner portion between concentric thicker portions;
a floating N+ type well region that extends into the floating P type well region from the upper semiconductor surface;
a gate that extends over a channel, wherein the channel extends from the N+ type emitter region and to the floating N+ type well region, wherein in a device on state electrons flow from the N+ type emitter region, through the channel, into the floating N+ type well region, to the thinner portion and then down into the N? type drift layer;
a first metal terminal coupled to the P type body region and to the N+ type emitter region;
a second metal terminal coupled to the gate; and
a third metal terminal coupled to the P type collector layer.

US Pat. No. 10,367,084

CASCODE HETEROJUNCTION BIPOLAR TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A structure formed using a device layer of a silicon-on-insulator substrate, the structure comprising:a first heterojunction bipolar transistor including a first emitter in the device layer, a first base layer with an intrinsic base portion on the first emitter, and a first collector on the intrinsic base portion of the first base layer, the intrinsic base portion of the first base layer arranged in a vertical direction between the first emitter and the first collector; and
a second heterojunction bipolar transistor including a second collector in the device layer, a second base layer with an intrinsic base portion on the second collector, and a second emitter on the intrinsic base portion of the second base layer, the intrinsic base portion of the second base layer arranged in the vertical direction between the second emitter and the second collector,
wherein the first emitter is coupled with the second collector, and the first emitter and the second collector each extend vertically in the device layer to a buried oxide layer of the silicon-on-insulator substrate.

US Pat. No. 10,367,077

WRAP AROUND CONTACT USING SACRIFICIAL MANDREL

International Business Ma...

15. A semiconductor structure comprising at least:a plurality of unmerged fin structures;
a separate source/drain in contact with each unmerged fin structure of the plurality of unmerged fin structures, wherein the source/drain comprises a rectangular shape; and
a contact layer formed on sidewalls and a top surface of each source/drain.

US Pat. No. 10,367,076

AIR GAP SPACER WITH CONTROLLED AIR GAP HEIGHT

INTERNATIONAL BUSINESS MA...

1. A method for fabricating an air gap spacer in a FinFET, the method comprising:depositing a sacrificial gate structure in a gate region, the sacrificial gate structure having an upper sacrificial layer, a lower sacrificial layer, and an etch stop layer between the upper sacrificial layer and the lower sacrificial layer;
removing the upper sacrificial layer selective to the etch stop layer to expose a sidewall spacer region; and
depositing an airgap spacer material in the exposed sidewall spacer region to form an upper portion of a sidewall spacer, the upper portion having the air gap.

US Pat. No. 10,367,074

METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS

Cree, Inc., Durham, NC (...

1. A semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface opposing the first main surface;
an active epitaxial device layer on the first main surface of the silicon carbide substrate;
a via extending from the second main surface into the silicon carbide substrate toward the first main surface;
a first electrical contact over the active epitaxial device layer; and
a second electrical contact overlying the second main surface and within the via, wherein the first electrical contact is separated from the second electrical contact at the active epitaxial device layer.

US Pat. No. 10,367,072

ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE

INTERNATIONAL BUSINESS MA...

1. A gate structure comprising a gate material on an asymmetrically thick gate dielectric comprising an oxide wherein the asymmetrically thick gate dielectric is thicker on a drain side of the gate structure than a source side of the gate structure, wherein the asymmetrically thick gate dielectric includes a high-k material and an interfacial dielectric layer of fin material under the high-k material, and a damaged spacer material is on the drain side along a sidewall of the gate structure and a non-damaged spacer material is on the source side of the device along another sidewall of the gate structure.

US Pat. No. 10,367,071

METHOD AND STRUCTURE FOR A LARGE-GRAIN HIGH-K DIELECTRIC

NXP USA, INC., Austin, T...

1. A semiconductor device comprising:a metal oxide comprising a first metal, oxygen, and a catalyst, wherein the first metal has a first concentration, the catalyst has a second concentration, and first concentration is at least ten thousand times greater than the second concentration; and
a conductive layer over the metal oxide.

US Pat. No. 10,367,069

FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

INTERNATIONAL BUSINESS MA...

1. A vertical fin field effect transistor (finFET), comprising;a vertical fin on a substrate;
a bottom spacer on the substrate and a lower portion of the sidewalls of the vertical fin;
a high-K dielectric layer on the bottom spacer and a portion of the sidewalls of the vertical fin;
a work function layer on only the high-K dielectric layer;
a gauge layer on the work function layer, wherein a top surface of the gauge layer is coplanar with an edge surface of the work function layer and an edge surface of the high-K dielectric layer on a portion of the sidewalls of the vertical fin, and wherein the edge surface of the work function layer and the edge surface of the high-K dielectric layer is below the top surface of the vertical fin; and
an L-shaped oxide layer on the top surface of the gauge layer, the edge surface of the work function layer, the edge surface of the high-K dielectric layer, and an upper portion of the sidewalls of the vertical fin.

US Pat. No. 10,367,065

DEVICE ISOLATION FOR III-V SUBSTRATES

International Business Ma...

1. A method of fabricating a III-V semiconductor device, the method comprising the steps of:providing a substrate having an indium phosphide-ready layer;
forming an iron-doped indium phosphide layer on the indium phosphide-ready layer;
forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer; and
patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more fins which comprise the one or more active areas of the device.

US Pat. No. 10,367,064

SEMICONDUCTOR DEVICE WITH RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) INCLUDING A SUPERLATTICE

ATOMERA INCORPORATED, Lo...

1. A semiconductor device comprising:a substrate;
at least one memory array comprising a plurality of recessed channel array transistors (RCATs) on the substrate; and
periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate, each of the CMOS transistors comprising
spaced-apart source and drain regions in the substrate and defining a channel region therebetween,
a first superlattice extending between the source and drain regions in the channel region, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a gate over the first superlattice and between the source and drain regions.

US Pat. No. 10,367,062

CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming nanosheet semiconductor devices, comprising:forming a first stack comprising layers of a first material and layers of a second material; forming a second stack comprising layers of a third material, layers of the second material, and a liner formed around the layers of the third material;
forming a dummy gate stack over channel regions of each of the first and second stacks;
depositing a passivating insulator layer around the dummy gate stacks; etching away the dummy gate stacks;
etching away the second material after etching away the dummy gate stacks; and
forming gate stacks over and around the layers of first and second channel material to form respective first and second semiconductor devices.

US Pat. No. 10,367,061

REPLACEMENT METAL GATE AND INNER SPACER FORMATION IN THREE DIMENSIONAL STRUCTURES USING SACRIFICIAL SILICON GERMANIUM

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming stacks each of which including two or more nanosheets separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanosheets in the stacks, wherein a lower spacer material is on a periphery of the two or more nanosheets, wherein the lower spacer material is on a top surface of an upper most nanosheet of the two or more nanosheets, wherein an upper spacer material is directly on the lower spacer material such that the upper spacer material is above a top one of the two or more nanosheets; and
forming source and drain regions on sides of the stacks.

US Pat. No. 10,367,059

METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING A BURIED RAISED PORTION

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first trench and a second trench in a semiconductor substrate to define a raised portion between the first trench and the second trench;
reducing a height of the raised portion;
filling the first trench and the second trench with a flowable dielectric;
curing the flowable dielectric; and
removing the flowable dielectric after the curing such that the raised portion is buried under the flowable dielectric after the removing.

US Pat. No. 10,367,057

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGIONS

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
a first cell and a second cell, each being electrically connected to the first load terminal structure on the one side and electrically connected to a drift region of the semiconductor body on the other side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; the first cell being configured to induce a load current path in the first channel region in a conducting state;
a second mesa included in the second cell, the second mesa including: a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by a first insulation structure and exhibiting a total extension of less than 100 nm in said direction;
a further port region comprising an emitter of the second conductivity type being electrically connected to the second load terminal structure,
wherein the power semiconductor device further comprises a third cell being electrically connected to the second load terminal structure on the one side and electrically connected to the drift region on the other side; wherein the third cell includes a third mesa comprising: a third port region having the first conductivity type and being electrically connected to the second load terminal structure; a third channel region being coupled to the drift region; and a third control electrode being insulated from the third mesa by a second insulation structure.

US Pat. No. 10,367,055

EPITAXIAL STRUCTURE HAVING NANOTUBE FILM FREE OF CARBON NANOTUBES

Tsinghua University, Bei...

1. An epitaxial structure comprising:a substrate having an epitaxial growth surface;
an epitaxial layer located on the epitaxial growth surface of the substrate; and
a nanotube film located between the substrate and the epitaxial layer, wherein the nanotube film comprises a plurality of nanotubes combined with each other by ionic bonds, the nanotube film is free of carbon nanotubes, and the nanotube film is a free-standing structure; a part of the plurality of nanotubes extends from a first side of the nanotube film to a second side opposite to the first side, and a first length of the part of the plurality of nanotubes is the same as a second length or a width of the nanotube film; and adjacent two of the plurality of nanotubes are internal communicated at contacting surface, and the plurality of nanotubes extends along a direction parallel to the epitaxial growth surface; wherein a majority of the plurality of nanotubes are orderly arranged to substantially extend along the same direction, and a minority of the plurality of nanotubes are dispersed on, randomly arranged, and in direct contact with the majority of the plurality of nanotubes.

US Pat. No. 10,367,050

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel including a display area in which an image is displayed and a first non-display area in which a pad portion is located,
wherein the display panel includes:
a main area that is substantially flat, the main area including a front surface and a rear surface;
a first bending portion in the display area, the first bending portion being bent at a first curvature radius; and
a second bending portion in the first non-display area between the first bending portion and the pad portion, the second bending portion being bent at a second curvature radius that is smaller than the first curvature radius;
a first area between the first bending portion and the second bending portion; and
a second area outside the second bending portion in the first non-display area, the second area extending from the second bending portion in an extending direction that points toward the rear surface of the main area.

US Pat. No. 10,367,046

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. An organic light-emitting display device comprising:a thin-film transistor and a metal line disposed on a substrate;
a planarization layer having a pixel contact hole configured to expose the thin-film transistor;
an organic light-emitting element disposed on the planarization layer, the organic light-emitting element including an anode electrode, a cathode electrode and a first organic light-emitting layer;
a first protrusion spaced apart from the anode electrode of the organic light-emitting element and configured to protrude from the planarization layer toward the cathode electrode of the organic light-emitting element, the first protrusion has a side surface angle different in size from a side surface angle of a side surface of the planarization layer that is exposed through the pixel contact hole; and
an auxiliary connection electrode disposed on the first protrusion and connected to the cathode electrode and connected to the metal line through an auxiliary contact hole within the planarization layer,
wherein the first protrusion is disposed on the metal line.

US Pat. No. 10,367,045

ELECTROLUMINESCENCE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An electroluminescence display device comprising:a thin film transistor on a surface of a substrate facing in a first direction;
a planarization layer on the surface of the substrate, the planarization layer covering the thin film transistor, the thin film transistor disposed between the planarization layer and the substrate, the planarization layer having a first area having a first thickness along the first direction and a second area having a second thickness along the first direction, the first thickness smaller than the second thickness;
a first electrode on the first area of the planarization layer, the first electrode electrically connected to the thin film transistor;
a bank layer on a portion of the second area of the planarization layer, the bank layer including a black pigment;
an emission structure including a transport layer and a light emitting layer on a surface of the first electrode facing in the first direction; and
a second electrode on a surface of the emission structure facing in the first direction.

US Pat. No. 10,367,044

METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

Samsung Dispiay Co., Ltd....

1. An organic light-emitting display apparatus, comprising:a substrate;
a first electrode on the substrate;
a pixel defining layer on the substrate, the pixel defining layer including an opening exposing a portion of the first electrode and corresponding to a pixel;
an organic light-emitting layer disposed on the first pixel electrode in the opening;
a second electrode on the pixel defining layer and the organic light-emitting layer; and
an auxiliary electrode contacting the second electrode and disposed on the pixel defining layer,
wherein a portion of the second electrode overlapping the pixel defining layer is disposed between the pixel defining layer and the auxiliary electrode.

US Pat. No. 10,367,035

ELECTROOPTICAL DEVICE, ELECTRONIC APPARATUS, AND HEAD MOUNT DISPLAY

SEIKO EPSON CORPORATION, ...

1. An electrooptical device comprising:a first pixel including a first sub-pixel, a first region, a second sub-pixel and a second region, which are arranged in a first direction in an order of the first sub-pixel, the first region, the second sub-pixel and the second region; and
a second pixel, different from the first pixel, including a third sub-pixel, a third region, a fourth sub-pixel and a fourth region, which are arranged in the first direction in an order of the third sub-pixel, the third region, the fourth sub-pixel and the fourth region, wherein:
the first sub-pixel and the second sub-pixel have different colors from each other;
the third sub-pixel and the fourth sub-pixel have different colors from each other;
the first region is a pixel contact region of the first sub-pixel;
the second region is a pixel contact region of the second sub-pixel;
the third region is a pixel contact region of the third sub-pixel;
the fourth region is a pixel contact region of the fourth sub-pixel;
the first region, the second region, the third region, and the fourth region have a same length in the first direction; and
the first pixel includes a fifth sub-pixel having a length different from lengths of the first and second sub-pixels in the first direction.

US Pat. No. 10,367,033

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Micron Technology, Inc., ...

1. A method, comprising:forming a first conductive line and a second conductive line extending in a first direction, the first conductive line and the second conductive line separated by a space;
covering, with a liner material, sidewalls of the first conductive line and the second conductive line and a surface extending between the sidewalls;
depositing a dielectric material over the liner material, wherein a first sidewall and a second sidewall of the dielectric material are in contact with the liner material; and
forming a pillar of a memory cell stack on the first conductive line or the second conductive line after depositing the dielectric material.

US Pat. No. 10,367,028

CMOS IMAGE SENSOR INCLUDING STACKED SEMICONDUCTOR CHIPS AND IMAGE PROCESSING CIRCUITRY INCLUDING A SUPERLATTICE

ATOMERA INCORPORATED, Lo...

1. A CMOS image sensor comprising:a first semiconductor chip comprising an array of image sensor pixels and readout circuitry electrically connected thereto; and
a second semiconductor chip coupled to the first semiconductor chip in stacked relation and comprising image processing circuitry electrically connected to the readout circuitry;
the image processing circuitry comprising a plurality of transistors each comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

US Pat. No. 10,367,026

SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A solid-state imaging element, comprising:a pixel array comprising a plurality of pixels,
wherein each pixel of the plurality of pixels comprises:
a photoelectric conversion region configured to generate a charge by photoelectric conversion based on an amount of incident light;
a charge accumulation region configured to accumulate the charge generated by the photoelectric conversion region;
a charge voltage conversion region configured to convert the accumulated charge into a voltage; and
a pixel transistor configured to output a pixel signal based on the voltage converted by the charge voltage conversion region,
wherein, in a first direction, a first pitch of photoelectric conversion regions of the plurality of pixels is shifted from a second pitch of charge accumulation regions of the plurality of pixels by a substantially half pitch.

US Pat. No. 10,367,025

SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE DEVICE

Panasonic Intellectual Pr...

1. A solid-state imaging device comprising:a semiconductor region of a first conductivity type; and
unit pixels, each unit pixel including
a photoelectric converter configured to generate charge;
an impurity region of a second conductivity type forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating the charge from the photoelectric converter;
an amplifier transistor including
a gate electrode electrically connected to the impurity region, and
a source region or a drain region of the second conductivity type in the semiconductor region, and
a channel region in the semiconductor region under the gate electrode, and
a width of the channel region being wider than a width of the source region or a width of the drain region in a width direction of the gate electrode; and
a first isolation region, in the semiconductor region, consisting of an impurity doped region of the first conductivity type and surrounding the amplifier transistor, wherein
entirety of the channel region is the second conductivity type, and
the first conductivity type is different from the second conductivity type.

US Pat. No. 10,367,021

IMAGE SENSOR DEVICE AND FABRICATING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A backside illuminated (BSI) image sensor device, comprising:a substrate having a first side and a second side opposite to the first side;
a photo sensitive element on the first side of the substrate to receive incident light transmitted through the substrate;
a pixel circuit on the first side of the substrate for electrical interconnecting with the photo sensitive element;
a first dielectric layer disposed on the second side of the substrate;
a second dielectric layer directly on the first dielectric layer, wherein a refractive index of the first dielectric layer is greater than a refractive index of the second dielectric layer;
a grid on the second dielectric layer, wherein a sidewall of the grid is coplanar with a sidewall of the second dielectric layer; and
a convex dielectric lens on the first dielectric layer and provided within the second dielectric layer, the convex dielectric lens having a convex side oriented toward the incident light and a planar side oriented toward the photo sensitive element, wherein a bottom of the convex side of the convex dielectric lens is level with a bottom surface of the second dielectric layer and a refractive index of the convex dielectric lens is smaller than the refractive index of the second dielectric layer.

US Pat. No. 10,367,019

CMOS IMAGE SENSOR STRUCTURE WITH CROSSTALK IMPROVEMENT

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:forming a silicon device layer on a semiconductor substrate, wherein the silicon device layer is configured to generate photoelectrons therein, the silicon device layer has a first surface and a second surface opposite to the first surface, and the first surface is adjacent to the semiconductor substrate;
forming a grid structure in the silicon device layer, wherein the grid structure is formed to comprise a plurality of cavities in the silicon device layer;
forming a plurality of color filters in the cavities such that the plurality of color filters include:
a first color filter that is adjacent an edge of the semiconductor device; and
a second color filter that has substantially the same thickness and the same color as the first color filter; and
forming a passivation layer on the second surface of the silicon device layer and covering the grid structure and the color filters.

US Pat. No. 10,367,018

IMAGE SENSOR AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. An image sensor, comprising:a photosensitive device;
a storage device adjacent to the photosensitive device, comprising:
a storage node;
a gate dielectric layer over the storage node;
a storage gate electrode over the gate dielectric layer;
an etch stop layer covering the gate dielectric layer and the storage gate electrode;
a shielding layer over the storage gate electrode; and
a protection layer sandwiched between the etch stop layer and the shielding layer; and
a driving circuit adjacent to the storage device.

US Pat. No. 10,367,017

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A method of manufacturing an array substrate, comprising the following steps:Step S1: providing a substrate, sequentially forming a light-shielding layer, a buffer layer, an active layer, a source, a drain, a gate insulating layer, and a gate on the substrate, wherein an indium gallium zinc oxide layer and a second metal layer are continuously deposited on the buffer layer using a halftone mask, and, using the halftone mask, the indium gallium zinc oxide layer is formed into the active layer and the second metal layer is formed simultaneously into the source and the drain;
Step S2: performing a first conductorization process on a corresponding region of the active layer opposite to the source and the drain; and
Step S3: performing a second conductorization process on another corresponding region of the active layer between the source and the gate and between the drain and the gate;
wherein locations of projections of the source, the drain, and the active layer on the substrate within a projection of the light-shielding layer on the substrate cause self-aligning of the active layer; and
wherein use of the halftone mask causes the active layer, the source, and the drain to be simultaneously formed.

US Pat. No. 10,367,012

TRANSISTOR AND DISPLAY DEVICE HAVING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a gate line;
a data line;
a switching transistor connected to the gate line and the data line; and
a driving transistor connected to an anode of an organic light emitting diode,
wherein the switching transistor comprising:
a first semiconductor layer comprising a first channel portion, a first contact portion and a second contact portion;
a first floating gate facing the first channel portion of the first semiconductor layer;
a first gate electrode facing the first floating gate; and
a first source electrode and a first drain electrode contacted with the first contact portion and the second contact portion, respectively, wherein the first floating gate comprises an oxide semiconductor, and
wherein the driving transistor comprising:
a second semiconductor layer which comprises a second channel portion, a third contact portion, and a fourth contact portion, the second semiconductor layer being a material different from the first semiconductor;
a second floating gate facing the second channel portion of the second semiconductor layer;
a second gate electrode facing the second floating gate; and
a second source electrode and a second drain electrode contacted with the third contact portion and the fourth contact portion, respectively, wherein the second floating gate comprises a metal that is not the oxide semiconductor.

US Pat. No. 10,367,007

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a display device comprising:forming a first conductive layer on a substrate;
forming a second conductive layer on the first conductive layer;
forming a first photoresist pattern on a gate transmission member forming area and a second photoresist pattern on a pixel electrode pattern forming area on the second conductive layer, the second photoresist pattern having a thickness greater than a thickness of the first photoresist pattern;
removing the first and second conductive layers using the first and second photoresist patterns as masks, to thereby form a gate transmission member and a pixel electrode pattern each comprising a first conductive layer pattern and a second conductive layer pattern;
removing the first photoresist pattern to thereby form a residual pattern of the second photoresist pattern on the pixel electrode pattern;
forming an etch stop layer on the gate transmission member and the residual pattern;
removing the residual pattern to thereby form an etch stop layer pattern through which the second conductive layer pattern of the pixel electrode pattern is exposed; and
removing the second conductive layer pattern of the pixel electrode pattern using the etch stop layer pattern as a mask, to thereby form a pixel electrode.

US Pat. No. 10,367,004

VERTICAL FERROELECTRIC THIN FILM STORAGE TRANSISTOR AND DATA WRITE AND READ METHODS THEREOF

NUSTORAGE TECHNOLOGY CO.,...

1. A vertical ferroelectric thin film storage transistor, comprising:a substrate having a first surface;
a first conductive structure disposed above the first surface of the substrate;
a first insulating layer disposed above the first conductive structure;
a second conductive structure disposed above the first insulating layer;
a second insulating layer disposed above the second conductive structure;
a vertical hole penetrating through the second insulating layer, the second conductive structure, the first insulating layer, the first conductive structure and the substrate in a direction substantially perpendicular to the first surface;
a channel layer disposed on a wall surface of the vertical hole and being in electrical contact with the first conductive structure and the second conductive structure;
an inner dielectric layer disposed on one side of the channel layer in the vertical hole;
a ferroelectric layer disposed on one side of the inner dielectric layer in the vertical hole;
a gate structure disposed on one side of the ferroelectric layer in the vertical hole; and
a third conductive structure disposed above the second insulating layer or in the substrate, and being in electrical contact with the gate structure.

US Pat. No. 10,367,003

VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A vertical non-volatile memory device, comprising:a substrate including a cell region;
a lower insulating layer on the substrate;
a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer;
a plurality of vertical channel layers extending in a vertical direction relative to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction relative to the top surface of the substrate, and electrically connected to the lower wiring pattern;
a horizontal channel layer extending in the horizontal direction, the horizontal channel layer connecting bottoms of the plurality of vertical channel layers to the lower wiring pattern; and
a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and extending in a first direction along the horizontal direction.

US Pat. No. 10,367,002

VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a vertical semiconductor device, comprising:alternately forming a plurality of insulation layers and sacrificial layers on a substrate to define a structure including an alternating plurality of insulation layers and sacrificial layers;
etching the structure to form a hole in the structure that exposes the substrate;
forming a first semiconductor pattern on the substrate in a lower portion of the hole;
sequentially forming a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern on a sidewall of the hole;
forming a second channel pattern on the first channel pattern and the first semiconductor pattern;
forming a second semiconductor pattern on a portion of the second channel pattern on the first semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern;
forming a filling insulation pattern in the hole on an upper surface of the second semiconductor pattern after forming the second semiconductor pattern; and
replacing the sacrificial layers with respective ones of a plurality of gates including a conductive material.

US Pat. No. 10,367,001

3D SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a stack comprising conductive layers and insulating layers that are alternately stacked; and
a slit insulating layer passing through the stack in a stacking direction, an upper surface of the slit insulating layer comprising a first main pattern having a first edge and a second edge extending in a first direction, a first protruding pattern protruding from the first edge at a one end of the first main pattern in a second direction crossing the first direction, a second protruding pattern protruding from the second edge at the one end of the first main pattern in the second direction, a third protruding pattern protruding from the first edge at the other end of the first main pattern in the second direction, and a fourth protruding pattern protruding from the second edge at the other end of the first main pattern in the second direction,
wherein a lower surface of the slit insulating layer has a shape in which a center thereof and an end thereof have substantially the same width.

US Pat. No. 10,366,997

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate;
a device isolation layer disposed on the substrate to define a first active pattern and a second active pattern, the first and second active patterns extending in a first direction and including upper portions protruding upwardly with respect to a top surface of the device isolation layer;
a gate electrode on the upper portions of the first and second active patterns, the gate electrode extending in a second direction intersecting the first direction;
first and second source/drain regions disposed on the upper portions of the first and second active patterns, respectively, at one side of the gate electrode; and
an active contact on the first source/drain region and electrically connected to the first source/drain region,
wherein the first and second source/drain regions are electrically isolated from each other,
wherein the active contact includes a first portion vertically overlapping with the first source/drain region, and a second portion extending from the first portion toward the device isolation layer,
wherein a bottom surface of the second portion is lower than a bottom surface of the first portion, and
wherein the second portion is spaced apart from the device isolation layer and the first and second source/drain regions with an insulating material interposed therebetween.

US Pat. No. 10,366,995

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Winbond Electronics Corp....

1. A semiconductor structure, comprising:a substrate;
first isolation structures, disposed in the substrate;
at least one buried word line, disposed in the substrate, wherein the at least one buried word line intersects the first isolation structures; and
at least one second isolation structure, disposed in the substrate, wherein the at least one second isolation structure intersects the first isolation structures, a material of at least a portion of the at least one second isolation structure is different from a material of the first isolation structures, a bottom surface of the at least a portion of the at least one second isolation structure is lower than a top surface of the substrate, the material of the first isolation structures comprises oxide, and the material of the at least a portion of the at least one second isolation structure comprises nitride.

US Pat. No. 10,366,992

SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first active area of a first type, extending in a first direction;
a second active area of a second type, extending in the first direction, wherein the first type is different from the second type; and
a plurality of gates extending in a second direction different from the first direction, wherein each one of the plurality of gates is arranged above and across the first active area and the second active area in a plan view,
wherein at a first side of a first gate of the plurality of gates, a first region of the first active area is configured to receive a first voltage and a first region of the second active area is configured to receive a second voltage, and
at a second side of the first gate, a second region of the first active area is disconnected from the first voltage and a second region of the second active area is disconnected from the second voltage.

US Pat. No. 10,366,991

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a semiconductor substrate comprising fin shaped structures;
an isolation structure disposed between the fin shaped structures, wherein each of the fin shaped structures comprises:
a first portion disposed above a top surface of the isolation structure; and
a second portion disposed on the first portion, wherein a width of the second portion is smaller than a width of the first portion;
a cladding layer disposed on the first portion and the second portion of each of the fin shaped structures, wherein the cladding layer comprises a curved surface;
a gate structure disposed straddling the fin shaped structures and the cladding layer disposed on each of the fin structures; and
a gate spacer disposed directly on the cladding layer, wherein a material composition of the gate spacer comprises oxide or oxynitride.

US Pat. No. 10,366,987

METHODS AND APPARATUS FOR COMPENSATION AND CURRENT SPREADING CORRECTION IN SHARED DRAIN MULTI-CHANNEL LOAD SWITCH

Texas Instruments Incorpo...

1. An integrated circuit comprising:(a) a semiconductor substrate having a first channel region, a second channel region, an insulating region separating the first channel from the second channel, and a substrate drain region below the first channel, the insulating region, and the second channel;
(b) first transistors formed in the first channel region, a first transistor having a first source, a first gate, and a first drain, the first drain being coupled to the substrate drain region;
(c) second transistors formed in the second channel region, a second transistor having a second source, a second gate, and a second drain, the second drain being coupled to the substrate drain region;
(d) a first pilot transistor having a first pilot gate coupled to the first gate, a first pilot drain coupled to the first drain, and a first pilot source;
(e) comparing circuitry having an inverting input, a non-inverting input, and an output, the inverting input being coupled to the first pilot source and to the second drain, the non-inverting input being coupled to the first source and to the first drain; and
(f) an output transistor having a gate coupled to the output of the comparing circuitry, a drain, and a source.

US Pat. No. 10,366,986

INTEGRATED CIRCUITS AND DEVICES WITH INTERLEAVED TRANSISTOR ELEMENTS, AND METHODS OF THEIR FABRICATION

NXP USA, Inc., Austin, T...

1. A monolithic integrated circuit comprising:a semiconductor substrate with a first surface and a second surface;
a first plurality of first transistor elements proximate to the first surface of the semiconductor substrate, wherein the first transistor elements have first current carrying terminals and second current carrying terminals;
a second plurality of second transistor elements proximate to the first surface, wherein the first transistor elements are interleaved with the second transistor elements in a first row, wherein the second transistor elements have third current carrying terminals and fourth current carrying terminals; and
a first node electrically coupled to the first current carrying terminals of the first transistor elements, and electrically coupled to the third current carrying terminals of the second transistor elements,
wherein the second current carrying terminals of the first transistor elements are electrically coupled to an antenna node, and wherein the fourth current carrying terminals of the second transistor elements are electrically coupled to a ground node.

US Pat. No. 10,366,985

SEMICONDUCTOR DEVICE HAVING A SENSE IGBT FOR CURRENT DETECTION OF A MAIN IGBT

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of first IGBTs formed in a main energizing region of the semiconductor substrate;
a plurality of second IGBTs formed in a sub-energizing region of the semiconductor substrate;
a plurality of pseudo third IGBTs, which do not configure a circuit, formed in a first region around the main energizing region; and
a plurality of pseudo fourth IGBTs, which do not configure a circuit, formed in a second region around the sub-energizing region,
wherein the sub-energizing region is smaller than the main energizing region in area in plan view,
wherein a plurality of first p-type wells of a floating state are formed in a main surface of the semiconductor substrate, each first p-type well being adjacent to a first trench gate electrode which configures a respective one of the first IGBTs,
wherein a plurality of second p-type wells of a floating state are formed in the main surface of the semiconductor substrate, each second p-type well being adjacent to a second trench gate electrode which configures a respective one of the second IGBTs at an end of the sub-energizing region,
wherein an n-type semiconductor region is formed over an upper surface of each of the second p-type wells, and
wherein a number of the pseudo fourth IGBTs arranged in the second region in a lateral direction of the second trench gate electrodes is larger than a number of the pseudo third IGBTs arranged in the first region in a lateral direction of the first trench gate electrodes.

US Pat. No. 10,366,981

POWER SEMICONDUCTOR DEVICES

Semiconductor Components ...

11. A power semiconductor device, comprising:a diode part disposed in a first region of a substrate;
a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate;
an anode terminal disposed on the first region of the substrate; and
a cathode terminal disposed on the second region of the substrate,
the JFET part including:
an n-type semiconductor region disposed above a p-type base substrate,
a p-type field forming layer disposed on the n-type semiconductor region,
an entirety of the p-type field forming layer being disposed lateral to a contact of the cathode terminal with the second region of the substrate, and
an n-type buried layer disposed at an interface between the n-type semiconductor region and the p-type base substrate, the n-type buried layer having at least one part overlapping the p-type field forming layer in a direction perpendicular to an upper surface of the substrate.

US Pat. No. 10,366,978

GROUNDED GATE NMOS TRANSISTOR HAVING SOURCE PULLED BACK REGION

UNITED MICROELECTRONICS C...

1. A grounded gate NMOS transistor, comprising:a P-type substrate;
a P-well region in the P-type substrate;
a gate finger traversing the P-well region, wherein the gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall;
an N+ drain doping region in the P-type substrate and adjacent to the first sidewall of the gate finger, wherein the N+ drain doping region is contiguous with a bottom edge of the first spacer;
an N+ source doping region in the P-type substrate opposite to the N+ drain doping region, wherein the N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer, so that the N+ source doping region is not contiguous with a bottom edge of the second spacer, and a source pulled back (SPB) region is defined between edge of the N+ source doping region and the bottom edge of the second spacer; and
a P+ pick-up ring in the P-well region and surrounding the gate finger, the N+ drain doping region, and the N+ source doping region.

US Pat. No. 10,366,975

ELECTROSTATIC DISCHARGE PROTECTIVE STRUCTURES

GLOBALFOUNDRIES SINGAPORE...

1. A structure, comprising:an epitaxial layer comprising a first region, a second region and a third region;
a plurality of gate structures connecting the first region to the second region and the second region to the third region; and
a plurality of terminals connected to the first region and the third region and the gate structures.

US Pat. No. 10,366,971

PRE-APPLYING SUPPORTING MATERIALS BETWEEN BONDED PACKAGE COMPONENTS

Taiwan Semiconductor Manu...

1. A method comprising:disposing a supporting material onto a surface of a first package component, wherein the first package component comprises a plurality of electrical connectors on the surface, wherein the plurality of electrical connectors is adjacent to peripheral regions of the first package component, and wherein the supporting material is adjacent to a center region of the surface;
after the supporting material is disposed, bonding the first package component to a second package component through the plurality of electrical connectors, wherein the supporting material has a first surface in contact with the first package component, and a second surface in contact with the second package component, and the first surface and the second surface are opposite to each other; and
after the bonding encapsulating the supporting material and the plurality of electrical connectors in an encapsulating material, wherein the supporting material and the encapsulating material are different from each other, the supporting material has a sidewall surface different from the first and second surfaces, the encapsulating material is in contact with at least a portion of the sidewall surface, and a portion of the encapsulating material is between the sidewall surface and one of the plurality of electrical connectors.

US Pat. No. 10,366,964

SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENTS TO PREVENT OVERCURRENT DAMAGE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a first semiconductor switching element including a first gate pad, a plurality of first emitter pads, and a first collector pad;
a first wire for connecting adjacent pads out of the plurality of first emitter pads;
a first output wire for connecting one of the plurality of first emitter pads to an output;
a first controller for applying a gate voltage to the first gate pad;
a first emitter wire that is directly connected to a first extraction pad which is any one pad of the plurality of first emitter pads, and is directly connected to an emitter terminal attached to a case to give a ground potential of the first controller; and
a second semiconductor switching element including a second gate pad, a second emitter pad and a second collector pad connected to the output.

US Pat. No. 10,366,961

IMAGE SENSORS WITH DEEP SILICON ETCH AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor comprising:a silicon layer comprising a first side and a second side opposite the first side;
an opening extending into the silicon layer from the first side of the silicon layer toward the second side;
a via extending into the silicon layer from the second side of the silicon layer; and
a conductive pad within the opening, the conductive pad coupled to the via;
wherein the opening comprises a fill material;
wherein at least a portion of the fill material forms a plane that is substantially parallel with a plane formed by the first side of the silicon layer; and
wherein the conductive pad is exposed through an opening in the fill material.

US Pat. No. 10,366,958

WIRE BONDING BETWEEN ISOLATION CAPACITORS FOR MULTICHIP MODULES

TEXAS INSTRUMENTS INCORPO...

1. A packaged multichip device having reinforced isolation, comprising:a first integrated circuit (IC) die on a first die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, at least a first isolation capacitor (first ISO cap) utilizing said top metal layer as a first top plate having a top dielectric layer thereon with a top plate dielectric aperture and one of said plurality of lower metal layers as its first bottom plate;
a second IC die on a second die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, including at least a second ISO cap utilizing said top metal layer as a second top plate having a top dielectric layer thereon having a top plate dielectric aperture and one of said plurality of lower metal layers as its second bottom plate;
a first end of a bondwire coupled within said top plate dielectric aperture on said first top plate, and
a second end of said bondwire coupled within said top plate dielectric aperture on said second top plate,
wherein said second end of said bondwire includes a stitch bond including a wire approach angle that is not normal to said second top plate, and
wherein said stitch bond is asymmetrically placed so that a center of said stitch bond is positioned at least 5% further from an outer edge of said second top plate on a bondwire crossover side as compared to a distance of said center of said stitch bond from a side opposite to said bondwire crossover side.

US Pat. No. 10,366,955

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE STRUCTURE HAVING NUCLEATION STRUCTURE AND METHOD OF FORMING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:an insulating structure having an opening;
a conductive pattern disposed in the opening;
a barrier structure extending between the conductive pattern and side walls of the opening, the barrier structure covering a bottom surface of the conductive pattern; and
a nucleation structure disposed between the conductive pattern and the barrier structure,
wherein the nucleation structure comprises a first nucleation layer that contacts the barrier structure, and a second nucleation layer that is spaced apart from the barrier structure and contacts lateral and bottom surfaces of the conductive pattern, and
a top end portion of the second nucleation layer is above a top end portion of the first nucleation layer.

US Pat. No. 10,366,954

STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:receiving a design for an integrated circuit chip;
generating a layout design for placement of integrated circuit devices on the integrated circuit chip, wherein the layout design includes a power distribution structure for the integrated circuit devices, the power distribution structure comprising:
a first conductor in a first plane connecting a first integrated circuit device to a power source, wherein the first conductor includes a first axis defining a first side and a second side of the first conductor, the first axis being in approximately the middle of the first conductor, and
a second conductor in a second plane parallel to the first plane, wherein the second conductor is connected to the first conductor by first vias extending in a second direction perpendicular to the first plane, and wherein the first vias contact the first conductor in only the first side of the first conductor, the second conductor being perpendicular to the first conductor;
performing a placement process to place the first integrated circuit device on the integrated circuit chip based upon the layout design;
creating a modified layout design by adding a cut in the second conductor, wherein the cut is parallel to the first conductor and located in an area of the second side of the first conductor; and
fabricating an integrated circuit chip based on the modified layout design.

US Pat. No. 10,366,953

REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) package comprising:an IC die having a conductive via, wherein the conductive via has a peripheral edge; and
a routing structure having a conductive structure, coupled to the conductive via, comprising:
a cap region overlapping an area of the conductive via;
a routing region having a first width from a top-down view; and
an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via and arranged to couple the cap region to the routing region, the second width being greater than the first width.

US Pat. No. 10,366,947

FLAT NO-LEAD PACKAGES WITH ELECTROPLATED EDGES

TEXAS INSTRUMENTS INCORPO...

1. A method of forming packaged semiconductor devices, comprising:providing a lead frame sheet including a plurality of joined flat no-lead lead frames (lead frames) each having a semiconductor die including bond pads thereon mounted on a die pad of said lead frames with bond wires between said bond pads and terminals of said lead frames, and plastic encapsulation except on a back side of said lead frame sheet to expose a back side of said die pad to provide an exposed thermal die pad and to expose a back side of said terminals;
partial sawing in saw lanes beginning from said back side of said lead frame sheet through said terminals ending with saw lines having a line width terminating within said plastic encapsulation to provide exposed side walls of said terminals and exposed side walls of said plastic encapsulation;
shorting together said exposed thermal pad and said exposed back side of the terminals to form electrically interconnected metal surfaces;
electroplating said electrically interconnected metal surfaces with a stack of plating layers on said back side and on said exposed side walls of said terminals, said stack of plating layers includes nickel, palladium, and gold;
decoupling said interconnected surfaces, and
a second sawing in said saw lanes to finish sawing through said plastic encapsulation to provide singulation to form a plurality of said packaged semiconductor devices.

US Pat. No. 10,366,946

CONNECTION MEMBER WITH BULK BODY AND ELECTRICALLY AND THERMALLY CONDUCTIVE COATING

Infineon Technologies AG,...

1. A connection member for connecting an electronic chip, wherein the connection member comprises:a bulk body;
a coating at least partially coating the bulk body and comprising a material having higher electric conductivity and higher thermal conductivity than the bulk body;
wherein a ratio between a thickness of the coating and a thickness of the bulk body is at least 0.0016 at or over at least a part of the connection member;
wherein the coating comprises or consists of at least one of the group consisting of copper, a copper alloy, zinc, and zinc alloy, wherein the bulk body consists of iron.

US Pat. No. 10,366,945

LEAD FRAME, LEAD FRAME WITH RESIN ATTACHED THERETO, RESIN PACKAGE, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING RESIN PACKAGE

NICHIA CORPORATION, Anan...

1. A lead frame comprising:a plurality of first leads, and a plurality of second leads, wherein the first and second leads are arranged within a plurality of rectangular unit regions, wherein each of the plurality of unit region contains at least one of the first leads and at least one of the second leads, and wherein the plurality of unit regions includes a first unit region and a second unit region that are adjacent to each other in a first direction;
a plurality of coupling portions and a plurality of extending portions, wherein at least one of the coupling portions and at least one of the extending portions couple the first and second leads in the first unit region to the first and second leads in the second unit region, and wherein all of the plurality of coupling portions and the plurality of extending portions extend along the first direction and/or a second direction that is orthogonal to the first direction;
wherein, in a top plan view of the lead frame, in each of the plurality of unit regions, the coupling portions and extending portions do not extend directly along and over at least one of four sides of the unit region, and
wherein the plurality of coupling portions and the plurality of extending portions are disposed such that upper surfaces of the plurality of coupling portions and upper surfaces of the plurality of extending portions are coplanar.

US Pat. No. 10,366,929

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer;
forming a sacrificial gate structure over the fin structure;
etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;
forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;
etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; and
forming a source/drain epitaxial layer in the second source/drain space, wherein:
at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer,
at least one of the second semiconductor layers is separated from a bottom of the source/drain epitaxial layer by the dielectric layer, and
an upper surface of the isolation insulating layer is located at a level below a bottom of the source/drain epitaxial layer.

US Pat. No. 10,366,928

HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES

International Business Ma...

1. A semiconductor device having a uniform height across different fin densities, comprising:a semiconductor substrate having fins etched therein and including dense fin regions having respective groups of the fins and dielectric material and isolation regions including the dielectric material without fins, at least two of the isolation regions having different lengths including a first isolation region having a first length defined between a first dense fin region and a second dense fin region, and a second isolation region having a second length defined between the second dense fin region and a third dense fin region; and
one or more dielectric layers formed at a base of the fins in respective ones of the dense fin regions and the isolation regions and each having a uniform height across the dense fin regions and the isolation regions, the uniform height including a less than 2 nanometer difference across the one or more dielectric layers.

US Pat. No. 10,366,927

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

16. A semiconductor device comprising:a device isolation layer provided on a substrate, the device isolation layer defining a first sub-active pattern and a second sub-active pattern, the first and second sub-active patterns extending in a first direction and spaced apart from each other in the first direction;
a first gate electrode and a second gate electrode crossing the first sub-active pattern and the second sub-active pattern, respectively;
an isolation structure provided on the device isolation layer between the first and second sub-active patterns;
a first source/drain region provided on the first sub-active pattern between the first gate electrode and the isolation structure;
a second source/drain region provided on the second sub-active pattern between the second gate electrode and the isolation structure; and
an interlayer insulating layer covering the first and second sub-active patterns, the first and second source/drain region and the isolation structure,
wherein the device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns,
wherein the isolation structure covers a top surface of the diffusion break region,
wherein a top surface of the isolation structure is in contact with the interlayer insulating layer and disposed at a same level as or a lower level than a top surface of each of the first and second sub-active patterns,
wherein the first and second sub-active pattern each include first sidewalls, the first sidewalls of the first and second sub-active patterns being aligned together in the first direction,
wherein the isolation structure is formed on the first sidewalls of the first and second sub-active patterns, and
wherein, with respect to a cross section that is parallel to the first direction and extending vertically through the first and second fin-type active patterns, the isolation structure has an uppermost point with respect to an upper surface of the substrate, and the uppermost point is part of a planar surface of the isolation structure that is parallel to the upper surface of the substrate.

US Pat. No. 10,366,925

WAFER PROCESSING METHOD

Disco Corporation, Tokyo...

1. A method of processing a wafer that includes a substrate and a device layer formed with devices in respective regions partitioned by a plurality of division lines intersecting on a front surface of the substrate, the method comprising:a laser beam applying step of applying a laser beam of such a wavelength as to be transmitted through the wafer to the wafer along the division lines, with a focal point of the laser beam positioned in an inside of the substrate, to form modified layers along the division lines and to extend device layer splitting cracks from the modified layers to the front surface of the wafer;
after the laser beam applying step is performed, a cutting step of cutting the wafer along the division lines by a cutting blade from a back surface of the wafer, to form cut grooves while leaving uncut portions inclusive of the device layer on the front surface side of the wafer and to remove the modified layers;
after the cutting step is performed, a coating step of coating the back surface side of the wafer with a liquid die bonding agent, to form a liquid die-bonding layer on the back surface of the wafer without filling the cut grooves with the liquid die bonding agent; and
after the coating step is performed, a curing step of curing the liquid die-bonding layer.

US Pat. No. 10,366,923

METHOD OF SEPARATING ELECTRONIC DEVICES HAVING A BACK LAYER AND APPARATUS

SEMICONDUCTOR COMPONENTS ...

1. A method of singulating a wafer comprising:providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed atop the second major surface, and wherein the layer of material comprises at least one of a conductive material, a wafer-back coating, and a die-attach film adapted to remain at least in part atop surfaces of the plurality of die upon completion of the method of singulating the wafer;
placing the wafer onto a carrier substrate;
etching portions of the wafer through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material;
providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material;
placing the wafer and the carrier substrate adjacent the support structure; and
applying pressure and high frequency mechanical vibrations to the wafer to separate the layer of material in the singulation lines.

US Pat. No. 10,366,922

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device, comprising:a plurality of conductive lines including a first conductive line and a second conductive line;
a plurality of sacrificial insulating layers arranged on sidewalls of the conductive lines; and
a plurality of contact plugs including a first contact plug and a second contact plug,
the first contact plug having a first pillar portion and a first protruding portion protruding from a part of the first pillar portion overlapped with a sidewall of the first conductive line, in a horizontal direction, so as to be in alignment and contact with the sidewall of the first conductive line,
the second contact plug having a second pillar portion and a second protruding portion protruding from a part of the second pillar portion overlapped with a sidewall of the second conductive line, in the horizontal direction, so as to be in alignment and contact with the sidewall of the second conductive line,
wherein the plurality of sacrificial insulating layers include an upper sacrificial layer, a lower sacrificial layer and a first sacrificial layer disposed between the upper sacrificial layer and the lower sacrificial layer,
wherein the first protruding portion is disposed between the upper sacrificial layer and the lower sacrificial layer to be overlapped with the upper sacrificial layer and the lower sacrificial layer, and
wherein the sidewall of the first conductive line, which is not overlapped with the upper sacrificial layer and the lower sacrificial layer, contacts with the first protruding portion.

US Pat. No. 10,366,920

LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE

INTERNATIONAL BUSINESS MA...

1. A method, comprising: performing an initial partial anneal of a metal interconnect and overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer; receiving image data of a top surface of the metal interconnect and overburden layer as image data from a scanning electron microscope (SEM) equipped with electron backscatter diffraction (EBSD); detecting an orientation of an early recrystallizing grain at a specific location on the top surface of the metal overburden layer, as implemented and controlled by a processor on a computer, in a process of selectively stepping through the image data at a preset sampling interval predetermined as based on an expected overburden grain size; determining whether the detected orientation of the early recrystallizing grain is desirable or undesirable; and selectively performing a laser anneal at specific locations to at least one of promote or inhibit certain grain orientations from growing, as based on the determining of being desirable or undesirable.

US Pat. No. 10,366,917

METHODS OF PATTERNING VARIABLE WIDTH METALLIZATION LINES

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:forming a first mandrel layer over a first mask layer and a second mandrel layer underlying the first mask layer;
etching the first mandrel layer to form a plurality of first mandrel lines, the plurality of first mandrel lines having variable widths;
etching a plurality of first non-mandrel trenches in the first mask layer, the plurality of first non-mandrel trenches having variable widths;
etching a plurality of first mandrel trenches, using the plurality of first mandrel lines as an etch mask, in the first mask layer, wherein the plurality of first mandrel trenches and the plurality of first non-mandrel trenches define a mandrel pattern; and
forming a plurality of second mandrel lines in the second mandrel layer according to the mandrel pattern, the plurality of second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of first non-mandrel trenches.

US Pat. No. 10,366,916

INTEGRATED CIRCUIT STRUCTURE WITH GUARD RING

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure comprising:a substrate having a first region and a second region being adjacent each other;
a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the first patterned layer; and
a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring comprises a dielectric material, includes a first width W1 and is separated and spaced a first distance D1 from the first features, W1 being greater than D1.

US Pat. No. 10,366,915

FINFET DEVICES WITH EMBEDDED AIR GAPS AND THE FABRICATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first gate structure disposed over a substrate, the first gate structure extending in a first direction;
a second gate structure disposed over the substrate, the second gate structure extending in the first direction;
a dielectric material disposed between the first gate structure and the second gate structure;
an air gap disposed within the dielectric material; and
a high-k dielectric or a metal disposed within the dielectric material, the metal being in contact with the air gap.

US Pat. No. 10,366,913

METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND METHOD FOR FORMING MASK PATTERN OF THE SAME

Kabushiki Kaisha Toshiba,...

1. A method for forming a mask pattern of a semiconductor element, the method comprising:forming a mask pattern group based on a prescribed rule for providing the semiconductor element with a first gate threshold voltage, the mask pattern group including:
a well pattern defining a first region on a semiconductor region;
an interconnect pattern defining an interconnect including a gate portion extending in a first direction on the first region; and
a source/drain pattern defining a second region positioned in the first region, the gate portion crossing the second region in the first direction; and
modifying the mask pattern group to change the first gate threshold voltage to a second gate threshold voltage based on a correlation between a gate threshold voltage and at least one of first to fourth distances in the semiconductor element, wherein
the gate threshold voltage changes with an absolute change amount that increases as each of the first to fourth distances is shortened,
the first distance being defined as a distance to an outer edge of the first region from an outer edge of the second region proximal to the outer edge of the first region;
the second distance being defined as a distance from the outer edge of the second region to the gate portion in a second direction crossing the first direction;
the third distance being defined as a distance to the second region from a portion of the interconnect positioned outside the second region in one of the first direction or the second direction; and
the fourth distance being defined when the mask pattern group further includes an ion implantation pattern defining an opening of an ion implantation mask in which the second region is exposed, the fourth distance being a distance to a wall surface of the opening from the outer edge of the second region proximal to the wall surface of the opening.

US Pat. No. 10,366,910

PICKUP AND PLACING DEVICE AND OPERATION METHOD OF PICKING AND PLACING BY PICKUP AND PLACING DEVICE

Innolux Corporation, Mia...

1. An operation method of picking and placing by a pickup and placing device, comprising:providing a pickup and placing device comprising:
a control element;
a substrate; and
a pickup structure comprising a plurality of pickup heads used for picking up or placing a plurality of light emitting diodes respectively, wherein the substrate has an upper surface and a lower surface opposite to each other and a plurality of conductive via structures, the conductive via structures are electrically connected to the control element, the pickup structure is electrically connected to the conductive via structures, the control element provides a signal, and the signal is transmitted to the pickup structure through the conductive via structures and selects a portion of the pickup heads, and the portion of the pickup heads of the pickup structure attract the selected light emitting diodes or place the attracted light emitting diodes on an active array substrate;
wherein each of the pickup heads comprises a main body portion and a pickup portion, the main body portion comprises a first body portion and a second body portion, a channel is provided between the first body portion and the second body portion, the pickup portion is disposed on the first body portion and second body portion of the main body portion and the pickup portion exposes the channel, the pickup structure further comprises a carrier, a plurality of controllers and a plurality of valves, the carrier comprises a plurality of chambers and a plurality of conductive elements, the plurality of channels are connected to the corresponding chambers, the controllers are disposed in the carrier and connected to the conductive via structures of the substrate through the conductive elements respectively, the valves are disposed in the chambers respectively, when one of the pickup heads is going to attract one of the corresponding light emitting diodes, one of the controllers controls one of the corresponding valves, and one of the chambers and one of the corresponding channels are connected to each other for attracting one of the corresponding light emitting diodes.

US Pat. No. 10,366,908

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus for processing a substrate, comprising:a chamber lid part having a lower opening and forming a lid internal space above said lower opening;
a chamber body forming a chamber-body internal space and forming a chamber with said chamber lid part;
a chamber lid part elevator for moving said chamber lid part in up-down direction;
a substrate holder for holding an outer edge of a substrate in a horizontal position in said chamber-body internal space;
a nozzle for supplying a processing liquid to an upper surface of said substrate;
a shield plate that is arranged in said lid internal space to oppose said upper surface of said substrate and is capable of blocking said lower opening;
a housing for housing said chamber lid part, said chamber body, said substrate holder and said shield plate;
a lid nozzle for supplying gas from above said shield plate to said lid internal space in a state in which said shield plate is spaced above said lower opening of said chamber lid part in said chamber so as to make pressure in said lid internal space higher than pressure in said chamber-body internal space and send said gas in said lid internal space from a gap between said shield plate and said chamber lid part to said chamber-body internal space through said lower opening;
a discharge port provided below said substrate in said chamber-body internal space and for discharging said gas flowing from said lid internal space to the outside of said chamber by suction; wherein
said chamber has a chamber space that is an internal enclosed space including said lid internal space and said chamber-body internal space, and
said chamber space is isolated from an internal space of said housing.

US Pat. No. 10,366,896

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a gate electrode on a substrate, wherein the gate electrode comprises a metal gate;
a gate dielectric layer between the gate electrode and the substrate, wherein the gate dielectric layer comprises a top portion and a bottom portion and a width of the top portion is less than a width of the bottom portion, and the gate dielectric layer does not extend directly over the source/drain regions respectively;
a high-k dielectric layer between and directly contacts the gate dielectric layer and the gate electrode, wherein a width of the high-k dielectric layer is equal to the width of the top portion and less than the width of the bottom portion;
a first spacer on the bottom portion and directly contacting the high-k dielectric layer, the top portion, and the bottom portion; and
a second spacer adjacent to the first spacer, wherein a bottom surface of the second spacer is even with a bottom surface of the bottom portion, a large portion of the first spacer and the second spacer are substantially parallel and vertically arranged, and the first spacer and the second spacer end at tops thereof at substantially same point.

US Pat. No. 10,366,892

HYBRID III-V TECHNOLOGY TO SUPPORT MULTIPLE SUPPLY VOLTAGES AND OFF STATE CURRENTS ON SAME CHIP

International Business Ma...

1. A method of forming dual III-V semiconductor channel materials on a wafer, the method comprising the steps of:providing a wafer having a first III-V semiconductor layer on an oxide;
forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer;
using shallow trench isolation to define at least one first active area and at least one second active area in the wafer;
converting the first III-V semiconductor layer in the at least one second active area to an insulator using ion implantation; and
removing the second III-V semiconductor layer from the at least one first active area selective to the first III-V semiconductor layer,
wherein the first III-V semiconductor layer in the at least one first active area and the second III-V semiconductor layer in the at least one second active area serve as the dual III-V semiconductor channel materials on the wafer.

US Pat. No. 10,366,891

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A vertical semiconductor apparatus comprising:a gallium nitride substrate;
a gallium nitride semiconductor layer provided on the gallium nitride substrate;
a p-type impurity region that is provided in the gallium nitride semiconductor layer and has an element to function as an acceptor for gallium nitride;
an n-type impurity region that is provided in the p-type impurity region and has an element to function as a donor for gallium nitride; and
an electrode provided in contact with a rear surface of the gallium nitride substrate, wherein
the element to function as the donor in the n-type impurity region includes:
a first impurity element that enters sites of gallium atoms in the gallium nitride semiconductor layer; and
a second impurity element that is an element different from the first impurity element and enters sites of nitrogen atoms in the gallium nitride semiconductor layer, and
in the n-type impurity region, a concentration of the first impurity element is higher than a concentration of the second impurity element.

US Pat. No. 10,366,890

METHOD FOR PATTERNING A SUBSTRATE USING A LAYER WITH MULTIPLE MATERIALS

Tokyo Electron Limited, ...

1. A method of patterning a substrate, the method comprising:forming mandrels on a target layer of a substrate, the mandrels being comprised of a first material, the target layer being comprised of a third material;
forming sidewall spacers on sidewalls of the mandrels by depositing a conformal film on the substrate and removing portions of the conformal film above top surfaces of the mandrels while leaving the conformal film below top surfaces of the mandrels such that the sidewall spacers are formed on vertical sidewalls of the mandrels and such that the conformal film covers the target layer between adjacent sidewall spacers, the conformal film being comprised of a second material;
forming a first etch mask on the substrate, the first etch mask defining openings that uncover regions of both the first material and the second material
executing a first etch process that selectively etches uncovered portions of the second material until the conformal film covering the target layer between adjacent sidewall spacers is removed while the sidewall spacers remain on the substrate; and
forming a second etch mask on the substrate, the second etch mask defining openings that uncover regions of both the first material and the second material; and
executing a second etch process that selectively etches uncovered portions of the first material until uncovered mandrels are removed.

US Pat. No. 10,366,889

METHOD OF FORMING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor device, comprising:providing a material layer on a substrate;
performing a spacer patterning process to form a plurality of first mask patterns parallel with each other on the material layer, the first mask patterns extending along a first direction;
performing a pattern splitting process to remove a portion of the first mask patterns to form a plurality of second openings, the second openings parallel with each other and extending along a second direction, across the first mask patterns; and
patterning the material layer by using remaining portion of the first mask patterns as a mask, to form a plurality of patterns in an array arrangement.

US Pat. No. 10,366,886

PATTERN FORMING METHOD, SELF-ORGANIZATION MATERIAL, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS

Toshiba Memory Corporatio...

9. A method of manufacturing a semiconductor apparatus comprising:placing a self-organization material on an under layer, the self-organization material including a block copolymer which includes a first polymer, a second polymer, and a third polymer, the third polymer is bonded to the first polymer and has a molecular structure including oxygen attached to a cyclic structure;
phase separating the block copolymer on the under layer to form a phase-separation pattern;
removing the first polymer or second polymer from the phase-separation pattern; and
after removing the first polymer or second polymer from the phase-separation pattern, processing the under layer by using the phase-separation pattern as a mask.

US Pat. No. 10,366,884

METHODS FOR FORMING A GERMANIUM ISLAND USING SELECTIVE EPITAXIAL GROWTH AND A SACRIFICIAL FILLING LAYER

STRATIO, Seoul (KR)

1. A method for obtaining a semiconductor island, the method comprising:epitaxially growing one or more semiconductor structures over a substrate with one or more mask layers defining one or more regions that are not covered by the one or more mask layers over the substrate, wherein the one or more semiconductor structures are epitaxially grown over the one or more regions that are not covered by the one or more mask layers, a respective epitaxially grown semiconductor structure of the one or more epitaxially grown semiconductor structures including a first portion located adjacent to the one or more mask layers and a second portion located away from the one or more mask layers, the first portion of the respective epitaxially grown semiconductor structure having a height that is less than a height of a portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure, the second portion of the respective epitaxially grown semiconductor structure having a height that is equal to, or greater than, the height of the portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure;
forming one or more dielectric or polysilicon filling layers directly on at least the first portion of the respective epitaxially grown semiconductor structure; and,
subsequent to forming the one or more filling layers on at least the first portion of the respective epitaxially grown semiconductor structure, removing at least a portion of the respective epitaxially grown semiconductor structure that is located above the height of the portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure.

US Pat. No. 10,366,883

HYBRID MULTILAYER DEVICE

Hewlett Packard Enterpris...

1. A multilayer device, comprising:a substrate;
a first layer disposed on the substrate;
a trench extending longitudinally through at least one of the substrate and the first layer, the trench having a first sidewall spaced apart from a second sidewall, each sidewall extending from a given surface of the substrate to another surface of the first layer that is spaced apart from the given surface by the first and second sidewalls; and
an active region disposed on the first layer, both the active region and the first layer overlying the trench, and the first layer bonded to the substrate at locations laterally outward of the first and second sidewalls of the trench.

US Pat. No. 10,366,882

SYSTEM FOR PRODUCING POLYCRYSTALLINE SILICON, APPARATUS FOR PRODUCING POLYCRYSTALLINE SILICON, AND PROCESS FOR PRODUCING POLYCRYSTALLINE SILICON

Shin-Etsu Chemical Co., L...

1. A process for producing polycrystalline silicon, comprising generating steam during growth of polycrystalline silicon while keeping a temperature of an inner wall surface of a reactor at not more than 370° C., wherein the inner wall surface of the reactor which contacts a process gas comprises a steel type comprising an alloy for which a value of a relational expression in mass content percentage among chromium, nickel, and silicon, [Cr]+[Ni]?1.5 [Si], is not less than 40%,wherein water is removed and returned to said reactor via a coolant circulation path, which comprises a first pressure control section, a second pressure control section, and a coolant tank,
wherein said steam is generated by feeding hot water, having a temperature higher than a standard boiling point, to said reactor, then vaporizing a portion of said hot water,
where the pressure of said hot water is reduced so that a portion of said hot water itself is flashed into said steam,
wherein the pressure of water discharged from said reactor is controlled by said first pressure control section and the pressure in said coolant tank is controlled by said second pressure control section, and
said hot water is flashed to generate steam and to cool the hot water simultaneously by reducing the pressure of the hot water in the first pressure control section,
wherein said first pressure control section comprises a first pressure indicator controller and a first pressure control valve configured for reducing the pressure of said hot water, and said second pressure control section comprises a second pressure indicator controller and a second pressure control valve configured for controlling pressure within said coolant tank.

US Pat. No. 10,366,880

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a semiconductor device on a semiconductor wafer;
forming an electrode layer on a first main surface of the semiconductor wafer, the electrode layer being electrically connected to the semiconductor device;
forming a first protective film on the first main surface of the semiconductor wafer, the first protective film containing a first resin and having an opening that partially exposes the electrode layer;
forming an electrode film on a surface of the electrode layer exposed in the opening;
selectively applying a second resin on surfaces of the first protective film and the electrode film by an inkjet method so as to form, along a boundary between the first protective film and the electrode film, two second protective films that extend parallel to the boundary, one of the second protective films being formed on a first side of the boundary and the other second protective film being formed on an opposite side of the boundary, and
applying a third resin between the two second protective films by the inkjet method so as to form a third protective film in contact with the two second protective films, a viscosity of the third resin being lower than a viscosity of the second resin.

US Pat. No. 10,366,873

CRYOGENIC 2D LINEAR ION TRAP AND USES THEREOF

University of Florida Res...

1. A rectilinear ion trap comprising:spaced x and y pairs of flat RF electrodes disposed in the zx and zy plane to define a trap volume, wherein each of the x flat RF electrodes comprise a slit;
a pair of DC plates, wherein the DC plates are coupled to the x and y pairs of flat RF electrodes, wherein the DC plates are disposed in the xy plane, and wherein each DC plate comprises holes configured to receive a fastener;
a base plate, wherein the base pate is coupled to the DC plates, wherein the base plate is positioned on top of the spaced x and y pairs of flat RF electrodes, and wherein the base plate is disposed of in the zy plane, wherein the base plate is parallel to the Y pair of flat RF electrodes, and wherein the base plate comprises holes to receive a fastener,
sapphire spacers, wherein the sapphire spacers have two holes configured to receive a fastener, wherein the sapphire spacers are placed between the base plate and the DC plate, wherein the sapphire spacers are placed between the DC plates and the ends of the x and y flat RF electrodes; and
fasteners, wherein the fasteners are passed through the holes in the DC plates, base plates, x and y flat RF electrodes and sapphire spacers.

US Pat. No. 10,366,870

CYLINDRICAL SPUTTERING TARGET AND PROCESS FOR PRODUCING THE SAME

TOSOH CORPORATION, Shuna...

1. A process for producing a cylindrical ceramic sputtering target comprising a bonding material filled in a cavity defined by a cylindrical ceramic target material and a cylindrical base material wherein the cylindrical base material is disposed inside the cylindrical ceramic target material, wherein as observed by an X-ray radiograph of the bonding material, the total area of portions where no bonding material exists is 10 cm2 or less per 50 cm2 of X-ray radiograph area, and the maximum area of the portions where no bonding material exists is 9 cm2 or less and wherein the volume ratio of the bonding material at 25° C. that is filled in the cavity is at least 96.8% with respect to the volume of the cavity at the melting point of the bonding material, said process comprising filling a molten bonding material in a cavity, starting cooling the molten bonding material from its one end toward its other end in a cylindrical axial direction in sequence, further filling the molten bonding material in the cavity during cooling and further comprising vibrating the molten bonding material filled in the cavity when or after filling the bonding material in the cavity.

US Pat. No. 10,366,867

TEMPERATURE MEASUREMENT FOR SUBSTRATE CARRIER USING A HEATER ELEMENT ARRAY

Applied Materials, Inc., ...

1. A method to determine a temperature profile of a substrate attached to an carrier during processing, the method comprising:measuring a first combined current load of each of a plurality of heating elements in the carrier, wherein the measuring a first combined current load comprises measuring when the plurality of heating elements are in an ON state except for a first heating element of the plurality of heating elements;
changing a power status of a first heating element of the plurality of heating elements, wherein changing a power status comprises changing the first heating element to an ON state;
measuring a second combined current load of each of the plurality of heating elements after changing the power status of the first heating element;
determining the difference between the first and second combined current loads;
determining a temperature of the first heating element using the difference; and
reverting the power status of the first heating element to that before the change and repeating changing power, measuring a current load, determining a difference, and determining a temperature for each of the other heating elements of the plurality to determine a temperature at each of the heating elements of the plurality of heating elements.

US Pat. No. 10,366,864

METHOD AND SYSTEM FOR IN-SITU FORMATION OF INTERMEDIATE REACTIVE SPECIES

ASM IP Holding B.V., Alm...

1. A method for providing intermediate reactive species to a reaction chamber of a reactor, the method comprising the steps of:providing a first gas to a remote plasma unit;
controlling a pressure of the remote plasma unit;
forming a plasma in the remote plasma unit;
forming intermediate reactive species from the first gas using the remote plasma unit, while maintaining steady-state conditions for the remote plasma unit; and
while maintaining the steady-state conditions in the remote plasma unit, pulsing the intermediate reactive species from the remote plasma unit to the reaction chamber by switching flow of the intermediate reactive species between the reaction chamber and a vacuum source.

US Pat. No. 10,366,860

HIGH ASPECT RATIO X-RAY TARGETS AND USES OF SAME

FEI Company, Hillsboro, ...

1. An x-ray target, comprising:a substrate made from a soft x-ray producing material; and
a plurality of high aspect ratio structures made from a hard x-ray producing material and arranged into one or more grids or arrays,
wherein the high aspect ratio structures in one of the one or more grids or arrays are arranged as different elements of a Hadamard matrix structure.

US Pat. No. 10,366,857

MAGNETRON FOR MICROWAVE OVEN

LG ELECTRONICS INC., Seo...

1. A magnetron for a microwave oven, comprising:a yoke forming a body of the magnetron;
an anode cylinder installed inside of the yoke;
a plurality of vanes that radially extends toward an axial center of the anode cylinder;
a filament positioned at the axial center of the anode cylinder;
a lower end shield positioned at a lower end of the filament, wherein an outer diameter of the lower end shield is about 80% to about 89% of a diameter of an inscribed circle formed by the plurality of vanes;
a center lead positioned at a center of the filament, wherein a lower end of the center lead extends downward through a center portion of the lower end shield; and
a side lead having an upper end which is connected to the lower end shield and spaced apart from the center lead.

US Pat. No. 10,366,855

FUSE ELEMENT ASSEMBLIES

Micron Technology, Inc., ...

1. A fuse element assembly comprising:a cathode having a first end and an opposing second end; the cathode having a slit into the first end that spaces a first projecting portion from a second projecting portion, the first and second projecting portions being substantially parallel to each other and merging at a merge region; and
a fuse link extending from the merge region and beyond the second end of the cathode; and further comprising
a third projecting portion of the cathode and a fourth projecting portion of the cathode, the third and fourth projecting portions extending from the merge region toward the second end of the cathode on opposing sides of the fuse link.

US Pat. No. 10,366,850

ELECTRONIC DEVICE INCLUDING KEY BUTTON

Samsung Electronics Co., ...

1. An electronic device comprising:a housing including a through hole;
a key button including a first extension movably inserted into the through hole;
a sealing member disposed between the through hole and the first extension; and
a separation prevention member coupled to the housing to prevent the key button from being separated from the housing, wherein the separation prevention member comprises a fixed portion fixed to an inner face of the housing and a second extension extended from the fixed portion and coupled to one or more recesses formed on a portion of the first extension of the key button, wherein, in order for the one or more recesses to receive the second extension, a width of the one or more recesses in a moving direction of the key button is larger than a thickness of the second extension.

US Pat. No. 10,366,846

REMOTE CONTROL DEVICE FOR AN ELECTRICAL DEVICE IN AN ELECTRICAL ENCLOSURE

SCHNEIDER ELECTRIC INDUST...

1. A remote control device for an electrical device in an electrical enclosure, said electrical enclosure including a bottom wall and side walls extending at right angles to the bottom wall and delimiting a housing, an electrical device being fixed, on the bottom wall, inside the housing, said remote control device comprising:a rotary control member that is fixed onto a wall of the enclosure outside the housing at a right angle to a face of the electrical device, the rotary control member remaining at a same orientation relative to the face of the electrical device when the electrical enclosure is open and when the electrical enclosure is closed, said rotary control member being selectively movable between first and second configurations,
a transmission system that mechanically links the rotary control member to a control lever of the electrical device, said control lever movable between the first and second positions, the transmission system moving the control lever between the first and second positions based on movement of the rotary control member between the first and second configurations,
wherein:
the rotary control member is mountable on one of the side walls of the housing and is rotationally mobile,
the transmission system comprises:
a first pinion, secured in rotation with the rotary control member about a first fixed axis, at right angles to the side walls,
a second pinion, meshed with the first pinion and rotationally mobile about a second fixed axis at right angles to the first fixed axis, said second pinion being coupled mechanically with the control lever to move said control lever between the first and second positions when the second pinion is moved in rotation.

US Pat. No. 10,366,840

CAPACITOR WITH MULTIPLE ELEMENTS FOR MULTIPLE REPLACEMENT APPLICATIONS

American Radionic Company...

1. An apparatus comprising:a case having an elliptical cross-section capable of receiving a plurality of capacitive devices, one or more of the capacitive devices providing at least one capacitor having a first capacitor terminal and a second capacitor terminal, wherein a first of the plurality of capacitive devices is affixed to the case by a first bracket and a second of the plurality of capacitive devices is affixed to the case by a second bracket, wherein the first bracket includes a curved middle portion that has a shape substantially similar to a shape of an outer surface of the first of the plurality of capacitive devices, and the second bracket includes a curved middle portion that has a shape substantially similar to a shape of an outer surface of the second of the plurality of capacitive devices;
a cover assembly comprising:
a deformable cover mountable to the case,
a common cover terminal having a contact extending from the deformable cover,
at least three capacitor cover terminals, each of the at least three capacitor cover terminals having at least one contact extending from the deformable cover, wherein the deformable cover is configured to displace at least one of the at least three capacitor cover terminals upon an operative failure of at least one of the plurality of capacitive devices, and
at least four insulation structures, wherein at least one of the at least four insulation structures is associated with one of the at least three capacitor cover terminals;
a first conductor capable of electrically connecting the first capacitor terminal of a capacitor provided by one of the plurality of capacitive devices to one of the at least three capacitor cover terminals; and
a second conductor capable of electrically connecting the second capacitor terminal of the capacitor provided by the one of the plurality of capacitive devices to the common cover terminal.

US Pat. No. 10,366,834

CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A ceramic electronic component, comprising:a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other;
a first external electrode including a first electrode layer disposed on the third surface of the body and electrically connected to the first internal electrode, a first inorganic insulating layer disposed on the first electrode layer, and a first plating layer disposed on the first inorganic insulating layer;
a second external electrode including a second electrode layer disposed on the fourth surface of the body and electrically connected to the second internal electrode, a second inorganic insulating layer disposed on the second electrode layer, and a second plating layer disposed on the second inorganic insulating layer; and
a third inorganic insulating layer disposed on the first, second, fifth, and sixth surfaces of the body and connected to the first and second inorganic insulating layers,
wherein the first, second, and third inorganic insulating layers comprise at least one selected from the group of SiO2, Al2O3 and ZrO2, and the first, second, and third inorganic insulating layers have a thickness within a range from 20 nm to 150 nm, and
wherein the first and second inorganic insulating layers have an, opening formed therein, and the first and second plating layers are in direct contact with the first and second electrode layers through the opening, respectively.

US Pat. No. 10,366,833

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers including a ceramic co-material are alternately stacked,
wherein a concentration of Mg in a ceramic grain that is included in the ceramic dielectric layer and contacts to the internal electrode layer is smaller than that in the co-material.

US Pat. No. 10,366,826

DUAL-MODE CHOKE COIL AND HIGH-FREQUENCY FILTER USING SAME, AND ON-BOARD MOTOR INTEGRATED ELECTRIC POWER STEERING AND ON-BOARD CHARGING DEVICE

Mitsubishi Electric Corpo...

1. A dual mode choke coil comprising:a lower core made of a magnetic substance, in which four columnar bodies whose respective axes are upright are placed on a quadrilateral square of a flat plate, said columnar bodies being such that a first columnar body and a second columnar body are arranged in parallel to a third columnar body and a fourth columnar body;
a first coil in which the winding direction of a first coil conductor wound around said first columnar body and the winding direction of a third coil conductor wound around said third columnar body are different to each other, and said first coil conductor and said third coil conductor are connected in series;
a second coil in which the winding direction of a second coil conductor wound around said second columnar body and the winding direction of a fourth coil conductor wound around said fourth columnar body are different to each other, and said second coil conductor and said fourth coil conductor are connected in series;
a first upper core made of a magnetic substance, which is brought in contact with upper portions of said first columnar body and said second columnar body; and
a second upper core made of a magnetic substance, which is brought in contact with upper portions of said third columnar body and said fourth columnar body, wherein said first upper core and said second upper core are arranged with a gap formed there between; and
the winding direction of said first coil conductor and the winding direction of said second coil conductor are different.

US Pat. No. 10,366,825

BARRIER ARRANGEMENT BETWEEN TRANSFORMER COIL AND CORE

ABB Schweiz AG, Baden (C...

1. An insulation barrier for a transformer, comprising:an inner portion including a first cylindrical body and a radially outwardly extending flange extending from a first end of the first cylindrical body; and
an outer portion including a second cylindrical body and a radially inwardly extending flange extending from a second end of the second cylindrical body in overlapping relation with the radially outwardly extending flange of the inner portion, wherein the first and second cylindrical body portions are spaced from one another to form a space sized to receive a high voltage coil between the first and second cylindrical bodies.

US Pat. No. 10,366,823

COIL COMPONENT

TDK CORPORATION, Tokyo (...

1. A coil component comprising:a drum-shaped core including a winding core part, a first flange part provided at one end of the winding core part in an axial direction of the winding core part, and a second flange part provided at other end of the winding core part in the axial direction;
first and second terminal electrodes provided on the first flange part;
third and fourth terminal electrodes provided on the second flange part;
a first coil wound around the winding core part, one end of the first coil being connected to the first terminal electrode and other end of the first coil is connected to the third terminal electrode;
a second coil wound around the winding core part, one end of the second coil being connected to the second terminal electrode and other end of the second coil is connected to the fourth terminal electrode, wherein
the first and second coils include a winding part at which the first and second coils are substantially regularly wound around the winding core part, a first drawing part positioned between the winding part and the first flange part, and a second drawing part positioned between the winding part and the second flange part,
the first and second coils cross each other at the first drawing part,
the first coil is constituted by two or more wires, and
the second coil is constituted by a single wire; and
third and fourth coils wound around the winding core part, wherein
the third and fourth coils include a winding part at which the third and fourth coils are substantially regularly wound around the winding core part, a first drawing part positioned between the winding part and the first flange part, and a second drawing part positioned between the winding part and the second flange part,
the third and fourth coils cross each other at the second drawing part,
the third coil is constituted by two or more wires, and
the fourth coil is constituted by a single wire.

US Pat. No. 10,366,821

COMMON MODE NOISE FILTER

Panasonic Intellectual Pr...

1. A common mode noise filter comprising:a first insulating layer;
a second insulating layer formed under the first insulating layer;
a first coil including a first coil conductor and a second coil conductor, the first coil conductor being electrically connected to the second coil conductor;
a second coil including a third coil conductor and a fourth coil conductor, the third coil conductor being electrically connected to the fourth coil conductor; and
a third coil including a fifth coil conductor and a sixth coil conductor, the fifth coil conductor being electrically connected to the sixth coil conductor,
wherein the first coil, the second coil, and the third coil are electrically independent of one another,
the first coil conductor, the third coil conductor, and the fifth coil conductor are formed side by side on the first insulating layer in a spiral fashion such that the first coil conductor, the third coil conductor, and the fifth coil conductor are sequentially positioned from an outer side of the first insulating layer,
the first coil conductor, the third coil conductor, and the fifth coil conductor have regions disposed in parallel to one another,
the second coil conductor, the fourth coil conductor, and the sixth coil conductor are formed side by side on the second insulating layer such that the fourth coil conductor, the sixth coil conductor, and the second coil conductor are sequentially positioned from an outer side of the second insulating layer,
the second coil conductor, the fourth coil conductor, and the sixth coil conductor have regions disposed in parallel to one another,
the first coil conductor and the fourth coil conductor have regions overlapping each other as seen from a top view,
the third coil conductor and the sixth coil conductor have regions overlapping each other as seen from a top view, and
the fifth coil conductor and the second coil conductor have regions overlapping each other as seen from a top view.

US Pat. No. 10,366,819

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising:a preformed coil that is formed of a winding part which winds a coated conductive wire continuously and spirally in an axial direction and includes an inner circumferential surface, an outer circumferential surface, and a principle face of one end portion and a principle face of the other end portion in the axial direction, and of a pair of leader parts which extends outwardly from the winding part;
a first core member that includes a shaft part disposed inside the inner circumferential surface, a side wall portion disposed in at least a portion of the outer circumferential surface, and a connection portion which is disposed such that a first gap is formed between the principle face of the one end portion and the connection portion, and through which the shaft part is connected to the side wall portion, and that contains metal magnetic grains; and
a second core member which is disposed such that a second gap is formed between the principle face of the other end portion and the second core member which contains metal magnetic grains and is provided with an adhesive, wherein:
the pair of leader parts are disposed in a portion where the side wall portion of the first core member is not formed on the outer circumferential surface of the winding part, and the pair of leader parts are not covered by the side wall portion,
the coil component further comprises a pair of terminal electrodes formed at respective ends of the leader parts in a manner extending in a same direction and facing the principle face of the other end portion of the winding part, wherein a peripheral portion of the second core member including a portion of the second gap provided with the adhesive is in direct contact with and fitted between the principle face of the other end portion of the winding part and the pair of terminal electrodes,
the second core member is of an E-type wherein the second core member includes a second shaft part facing and axially aligned with the shaft part of the first core member, a second side wall portion facing and axially aligned with the side wall portion of the first core member, and a second connection portion connecting the second shaft part and the second side wall portion, and
the first gap formed between the principle face of the one end portion of the winding part and the connection portion of the first core member is constituted by a void.

US Pat. No. 10,366,815

PERMANENT MAGNET DRIVE ON-LOAD TAP-CHANGING SWITCH

1. A permanent magnet drive on-load tap-changing switch, comprising:a changing switch circuit, the changing switch circuit comprising an odd-numbered tap-changing circuit and an even-numbered tap-changing circuit that are structurally identical;
the odd-numbered tap-changing circuit and the even-numbered tap-changing circuit comprising working contactors and dual-contact synchronous transition contactors consisting of primary contactors and secondary contactors;
the working contactors being connected to the primary contactors through trigger transmitters and transition resistors;
a primary contactor of a tap-changing circuit being connected to a secondary contactor of another tap-changing circuit through a high-voltage thyristor;
a trigger transmitter being configured to provide a trigger current to the high-voltage thyristor connected with the secondary contactor of a same tap-changing circuit, wherein:
the working contactors and the dual-contact synchronous transition contactors directly face moving contactors;
the moving contactors are connected in parallel to each other;
moving contactor permanent magnets are bijectively connected to the moving contactors;
the moving contactor permanent magnets directly face, on an other extremity thereof, a moving contactor driving mechanism, the moving contactor driving mechanism comprising a moving permanent magnet which moves to change a force acting on the moving contactor permanent magnets to allow the moving contactors to get contact with or depart from the working contactors and the dual-contact synchronous transition contactors.

US Pat. No. 10,366,814

PERMANENT MAGNET

TDK CORPORATION, Tokyo (...

1. A permanent magnet with a composition ratio of RXT(100-X-Y)CY comprising a main phase with Nd5Fe17 crystal structure, wherein:R is one or more rare earth elements including Sm, and the rare earth elements are Sm, Y, La, Pr, Ce, Nd, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu; and
T is one or more transition metal elements including Fe or a combination of Fe and Co; and
23.2?X(at %)?37.1, 6.0?Y(at %)?14.7, 1.51?(100-X-Y)/X?2.92.

US Pat. No. 10,366,813

HIGH-PRECISION ADDITIVE FORMATION OF ELECTRICAL RESISTORS

1. A method of forming an electrical resistor having a target electrical resistance by additive manufacturing comprising the steps of:forming an electrically resistive layer on a substrate;
measuring an electrical resistance-related parameter of the electrically resistive layer and determining from the electrical resistance-related parameter a target length of the electrically resistive layer corresponding to the target electrical resistance; and
forming a first electrically conductive terminal and a second electrically conductive terminal contacting the electrically resistive layer, said first and second electrically conductive terminals being separated by a distance corresponding to the target length, such that an electrical resistance of a portion of the electrically resistive layer extending between the first electrically conductive terminal and the second electrically conductive terminal corresponds to the target electrical resistance.

US Pat. No. 10,366,804

CONDUCTIVE RESIN COMPOSITION AND DISPLAY DEVICE USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display device comprising:a display panel; and
a frame having conductivity, in which the display panel is mounted,
wherein
the frame is formed of a conductive resin composition,
the conductive resin composition comprises:
a resin comprising a polyester copolymer resin, and
carbon nanotube (CNT), and
the polyester copolymer resin comprises at least one of polyethylene terephthalate glycol (PETG) and polycyclohexylene dimethylene terephthalate glycol.

US Pat. No. 10,366,803

METAL OXIDE THIN FILM, METHOD FOR DEPOSITING METAL OXIDE THIN FILM AND DEVICE COMPRISING METAL OXIDE THIN FILM

Plansee SE, Reutte (AT)

1. A metal oxide thin film, comprising a film formed of ?-MoO3 having a monoclinic ?-MoO3 crystal structure and including at least one doping element selected from the group consisting of Re, Mn, and Ru.

US Pat. No. 10,366,802

COMPOSITIONS INCLUDING NANO-PARTICLES AND A NANO-STRUCTURED SUPPORT MATRIX AND METHODS OF PREPARATION AS REVERSIBLE HIGH CAPACITY ANODES IN ENERGY STORAGE SYSTEMS

1. A lithium-ion battery anode electrode, comprising:a current collector having a planar surface;
a plurality of a first nanomaterial selected from the group consisting of carbon nanotube, carbon nanowire, carbon nanorod and mixtures thereof, having a first end and a second end, the first end deposited on the planar surface of the current collector, each of said plurality of the first nanomaterial being vertically aligned with one another, perpendicular to the planar surface of the current collector, and exhibiting defined spacing between one another;
a plurality of a second nanomaterial deposited on a surface of each of the plurality of the first nanomaterial, the second nanomaterial composed of an element selected from the group consisting of metallic, metalloid, non-metallic and mixtures thereof, the second nanomaterial as-deposited in a form selected from the group consisting of nano-particle, nano-cluster, droplet and mixtures thereof, each of the plurality of the second nanomaterial exhibiting defined spacing between one another,
wherein the surface of the plurality of a first nanomaterial underlying the plurality of a second nanomaterial has excess amorphous carbon; and
an interfacial layer comprising the amorphous carbon, formed in-situ on the plurality of a first nanomaterial underlying said plurality of a second nanomaterial.

US Pat. No. 10,366,785

CONTROL METHOD, INFORMATION TERMINAL, RECORDING MEDIUM, AND DETERMINATION METHOD

PANASONIC INTELLECTUAL PR...

1. A method for controlling an information terminal including a display, the information terminal being connected to a case retrieval system that retrieves a medical image by referring to a medical image database, the method comprising:(a) receiving a first medical image including a plurality of pixels;
(b) calculating, if a lesion included in the first medical image is a texture lesion, a probability value indicating a probability that each of the plurality of pixels of the first medical image is included in a lesion area by inputting a pixel value of the pixel and pixel values of surrounding pixels of the pixel to an identification device for identifying a predetermined lesion area indicating the texture lesion, the texture lesion being a lesion including one of a plurality of particular shadow patterns;
(c) displaying, on the display, a second medical image obtained by superimposing a candidate area and a modification area of the candidate area upon the first medical image, the candidate area being determined on the basis of a pixel whose probability value is larger than a first threshold among the plurality of pixels, the modification area being determined on the basis of a pixel whose probability value is within a probability range among the plurality of pixels, the probability range including the first threshold;
(d) detecting an input from a user on the second medical image displayed on the display; and
(e) displaying a third medical image obtained by superimposing the lesion area upon the first medical image, the lesion area being determined by modifying the candidate area on the basis of the input from the user and the modification area.

US Pat. No. 10,366,783

IMAGING EXAMINATION PROTOCOL UPDATE RECOMMENDER

KONINKLIJKE PHILIPS N.V.,...

1. A system, comprising:a data repository configured to store a plurality of images;
a viewing station comprising:
a display monitor configured to visually present a displayed image, wherein the displayed image is selected from the plurality of images and corresponds to a scan, wherein the scan is within an electronically stored examination protocol;
at least one sensor configured evaluate a plurality of radiologist interactions reading the displayed image and to generate an output based on the evaluated radiologist interaction with the displayed image, wherein the at least one sensor is selected from the group consisting of:
a visual sensor configured to track movement of the radiologist viewing the displayed image;
an audio sensor configured to record audio uttered by the radiologist; and
an input device sensor configured to sense inputs corresponding to the displayed image; and
a computing device comprising:
a processor; and
a memory encoded with computer readable instructions which when executed by the processor cause the processor to:
determine at least one statistic based on the generated output; and
in response to determining the at least one statistic satisfies a predetermined threshold, remove the scan that corresponds to the displayed image from the examination protocol.

US Pat. No. 10,366,780

PREDICTIVE PATIENT TO MEDICAL TREATMENT MATCHING SYSTEM AND METHOD

ELLIGO HEALTH RESEARCH, I...

1. A method for matching patients with a specific medical treatment comprising:receiving specified information about a specific medical treatment from a company looking for potential candidates for said specific medical treatment at a server, wherein said specified information about said specific medical treatment is determined by a software application residing on said server and provided by said company over a network by said company's system;
accessing said specified information about said specific medical treatment on said server by the administrator of said server, wherein said administrator approves said specified information about said specific medical treatment and thereinafter creates a medical treatment specific query record based on said specified information about said specific medical treatment that includes inclusion and exclusion criteria, a medical treatment specific patient screening survey record based on said specified information about said specific medical treatment, a medical treatment specific physician consultation questionnaire record based on said specified information about said specific medical treatment, a medical treatment specific patient information record based on said specified information about said specific medical treatment, and a medical treatment specific physician information record based on said specified information about said specific medical treatment;
browsing said medical treatment specific physician information records using a browser connected to the system of a referring physician's office to connect to said server through said network, wherein said system of a referring physician's office includes a patient database;
selecting at least one said specific medical treatment;
launching an applet from said server, wherein said applet runs in said browser, connects to said patient database, and accesses said medical treatment specific query record relating to said selected medical treatment;
using the medical treatment specific query record, querying said patient database, wherein said applet runs said medical treatment specific query and compares patient records in said patient database with said inclusion and exclusion criteria of said medical treatment specific query, returning said patient records from said patient database that match said inclusion and exclusion criteria of said medical treatment specific query through said network to said server and storing said patient records on said server;
comparing said patient record with said medical treatment specific patient screening survey record and said medical treatment specific physician consultation questionnaire record and completing fields in said medical treatment specific patient screening survey record and said medical treatment specific physician consultation questionnaire record that match information from said patient record;
contacting a patient associated with said patient records stored on said server by accessing said patient records through said network on said system of referring physician's office, wherein said referring physician's office contacts said patient to inquire whether said patient is interested in learning more about said medical treatment, wherein if said patient declines, said patient record is updated by said referring physician's office through said network using said system of referring physician's office, wherein if said patient accepts, said patient is transferred to an interactive voice response system connected to said server;
completing the medical treatment specific patient screening survey, wherein said interactive voice response system accesses said medical treatment specific patient screening survey record and asks said patient unmatched questions from said medical treatment specific patient screening survey, wherein said patient answers said unmatched questions and said answers are sent through said interactive voice response system to said server, wherein said medical treatment specific patient screening survey record and said medical treatment specific physician consultation questionnaire record are updated and stored on said server;
scoring answers in said medical treatment specific patient screening survey record using said software application and scheduling said patient that has a predetermined minimum score for a consultation with said referring physician's office;
completing the medical treatment specific physician consultation questionnaire record, wherein said patient visits said referring physician's office and personnel from said referring physician's office accesses said medical treatment specific physician consultation questionnaire record using a browser connected to said system of said referring physician's office to connect to said server through said network, wherein said personnel completes answers to said medical treatment physician consultation questionnaire and sends those answers to said server using a browser connected to the system of a referring physician's office to connect to said server through said network, wherein said medical treatment specific physician consultation questionnaire record is updated and stored on said server; and
sending said patient record to said company looking for potential candidates for said specific medical treatment using said software application.

US Pat. No. 10,366,778

METHOD AND DEVICE FOR PROCESSING CONTENT BASED ON BIO-SIGNALS

SAMSUNG ELECTRONICS CO., ...

1. A method of processing content based on at least one bio-signal, the method comprising:outputting a content including at least one from among audio content and image content;
acquiring information related to the at least one bio-signal of a user with respect to the content;
determining a parameter for processing of the content, based on the acquired information related to the at least one bio-signal;
processing the content, based on the determined parameter;
outputting the processed content;
determining a concentration level of the user based on the at least one bio-signal;
obtaining information related to the content while the determined concentration level of the user is less than a reference point; and
providing to the user the obtained information related to the content if the concentration level of the user is greater than or equal to the reference point, or according to a user's input.

US Pat. No. 10,366,772

SYSTEMS AND METHODS FOR TESTING A SEMICONDUCTOR MEMORY DEVICE HAVING A REFERENCE MEMORY ARRAY

Micron Technology, Inc., ...

1. An apparatus comprising:a first memory cell array comprising a first bit-line and a plurality of normal word lines coupled to the first bit-line;
a second memory cell array comprising a second bit-line and a plurality of dummy word lines coupled to the second hit-line, the number of dummy word lines being smaller than that of the normal word lines;
a sense amplifier coupled to the first bit-line and a first end of the second bit-line;
a first word decoder configured to activate one of the plurality of normal word lines during a memory access operation to a memory cell coupled to the one of the plurality of normal word lines;
a second word decoder configured to activate two or more of the plurality of dummy word lines during the memory access operation and further configured to operate selected ones of the plurality of dummy word lines responsive to a first test signal; and
a transistor coupled to a second end of the second bit-line and operated by a second test signal.

US Pat. No. 10,366,770

BIT ERROR RATE ESTIMATION FOR NAND FLASH MEMORY

Toshiba Memory Corporatio...

1. A method comprising:performing a program operation on a multi-level cell flash memory having a plurality of threshold voltages;
for each threshold voltage:
programming a state immediately greater than the threshold voltage,
defining at least one verify threshold value,
determining a first number of cells having voltage less than the at least one verify threshold value, and
determining an estimated under-programmed bit error rate (BER) based on the first number of cells and a first BER threshold value; and
determining an overall under-programmed BER based on the estimated under-programmed BER for each threshold voltage of the plurality of threshold voltages.

US Pat. No. 10,366,769

NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD FOR FAST AND SLOW CELLS THEREOF

Samsung Electronics Co., ...

1. A programming method of a nonvolatile memory device, the method comprising the steps of:a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, based on threshold voltages from among the plurality of first memory cells, a first fast memory cell and a first slow memory cell;
a second programming loop including applying a first program pulse to the first fast memory cell and the first slow memory cell, and applying a second program pulse to the first slow memory cell and a plurality of second memory cells, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop; and
a third programming loop, and
wherein the plurality of second memory cells have a target threshold voltage greater than the first target threshold voltage.

US Pat. No. 10,366,766

POWER SHAPING AND PEAK POWER REDUCTION BY DATA TRANSFER THROTTLING

WESTERN DIGITAL TECHNOLOG...

1. An arrangement, comprising:a device configured to transmit and receive data from a host, the device comprising:
a device controller configured to interact with at least a memory array; and
a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold; and
an internal counter configured to increment for an amount of the bandwidth to be consumed, wherein any consumed bandwidth is decremented by the internal counter when a read/write command is issued.

US Pat. No. 10,366,765

ADJUSTMENT CIRCUIT FOR PARTITIONED MEMORY BLOCK

Taiwan Semiconductor Manu...

1. An adjustment circuit comprising:a controller circuit configured to output a control signal that indicates a memory type;
a timer circuit configured to output a timing signal for a read memory operation based on the control signal;
a temperature adaptive reference (TAR) generator configured to adjust a verify reference current for a verify memory operation based on temperature, wherein the verify reference current is set based on the control signal; and
an amplifier circuit configured to:
receive the timing signal, the verify current, and a current provided by a memory cell, wherein the amplifier circuit outputs a signal based on the timing signal, the verify current, and the memory cell current.

US Pat. No. 10,366,763

BLOCK READ COUNT VOLTAGE ADJUSTMENT

Micron Technology, Inc., ...

1. A NAND memory device comprising:a NAND memory array including a first pool of memory;
a controller executing instructions and performing operations comprising:
receiving a command from a host to read a value of at least one cell from the first pool of memory;
determining a read voltage to apply to the at least one cell by adding a first offset value to a base read voltage, the first offset value calculated as a stepwise function of a count of a number of previous reads during a period of time to a group of cells, the group of cells including the at least one cell; and
applying the read voltage to the at least one cell.

US Pat. No. 10,366,758

STORAGE DEVICE AND STORAGE METHOD

RENESAS ELECTRONICS CORPO...

1. A storage device, comprising:a write circuit;
a data memory circuit configured to include a pair of first flash memory cells to be read by a complementary read mode, where complementary 1-bit data is stored in the pair of first flash memory cells by the write circuit; and
a status memory circuit configured to include a plurality of second flash memory cells to be read by a reference read mode, where a status flag is stored in the flash memory cell by the write circuit,
wherein the write circuit is configured to write the complementary 1-bit data to each of the pair of first flash memory cells, and to write the status flag of a same value to each respective second flash memory cell, the status flag indicating a data write status of the first flash memory cells, and
wherein the storage device further comprises a determination circuit configured to determine a value of the status flag by comparing a sum current of currents flowing through the plurality of second flash memory cells with a reference current.

US Pat. No. 10,366,757

COMPACT NON-VOLATILE MEMORY DEVICE

STMicroelectronics (Rouss...

1. A method of erasing a memory cell, the method comprising:applying a first voltage to a control gate of the memory cell, wherein the control gate is disposed over and insulated from a floating gate of the memory cell, wherein the floating gate comprises an embedded portion disposed over and insulated from a selection gate of the memory cell, wherein the embedded portion of the floating gate is located between a first substrate region of a semiconductor substrate and a second substrate region of the semiconductor substrate, wherein the floating gate further comprises a projecting portion extending out of the semiconductor substrate and disposed over the embedded portion of the floating gate and below the control gate, wherein the selection gate is embedded in the semiconductor substrate and below the embedded portion of the floating gate, wherein the selection gate is located between the first substrate region of the semiconductor substrate and the second substrate region of the semiconductor substrate, wherein the semiconductor substrate further comprises a source region disposed below the selection gate, the first substrate region of the semiconductor substrate, and the second substrate region of the semiconductor substrate;
applying a second voltage to the first substrate region of the semiconductor substrate; and
applying a third voltage to the second substrate region of the semiconductor substrate, wherein the third voltage is different from the second voltage, wherein a potential difference between the second voltage and the first voltage is greater than an erasure threshold of the memory cell so as to perform an erasing operation on the memory cell.

US Pat. No. 10,366,753

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Arm Limited, Cambridge (...

1. A method, comprising:selectively connecting or disconnecting one or more portions of an integrated circuit to one or more other portions of the integrated circuit at least in part by selectively applying a programming voltage to one or more correlated electron switch devices to cause a transition in the one or more correlated electron switch devices from a first impedance state to a second impedance state, wherein the one or more correlated electron switch devices are respectively positioned between one or more electrodes of a first metallization layer and one or more electrodes of a second metallization layer.

US Pat. No. 10,366,746

SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE

INTERNATIONAL BUSINESS MA...

1. A memory cell, comprising:cross coupled inverters;
a bitline left (BL) which accesses a first inverter of the cross coupled inverters;
a bitline right (BR) which accesses a second inverter of the cross coupled inverters;
a wordline left (WL) which enables a first access transistor;
a wordline right (WR) which enables a second access transistor; and
a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,
wherein:
the GNDL and the GNDR are separate vertical SRAM GND buses, and
in a standby mode of the memory cell, Vdd is at an elevated GND (GNDH).

US Pat. No. 10,366,745

SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING DEVICE

HITACHI, LTD., Tokyo (JP...

1. A semiconductor device which performs a non-linear operation, comprising:a memory;
a reading unit that reads data from the memory;
a majority circuit coupled to a plurality of spin value signal lines that inputs a result of a predetermined operation on the data read by the reading unit;
a write circuit that receives an output of the majority circuit; and
a control unit that controls the memory, the reading unit, the majority circuit, and the write circuit,
wherein the control unit has a step of calculation using a parameter T determined by the control unit regardless of a value in the memory, and
wherein in the step,
the value of the predetermined signal in the semiconductor device is stochastically inverted based on a result of the calculation, and
“1” is randomly output with a probability f(x,T) given by function

which includes a hyperbolic tangent function with an argument as a value x determined by the value in the memory, and
wherein a value of a predetermined signal is stochastically inverted at a preceding stage of the majority circuit.

US Pat. No. 10,366,744

DIGITAL FILTERS WITH MEMORY

Micron Technology, Inc., ...

1. An electronic device, comprising:a quantizing circuit configured to be coupled to an internal data storage location via an electrical conductor, the quantizing circuit comprising:
an analog-to-digital converter having an input and an output; and
a digital filter coupled to the output of the analog-to-digital converter, wherein the digital filter comprises memory distinct from filtering circuitry of the digital filter, and wherein the digital filter is configured to store a preset value in the memory, wherein the preset value is utilized to initialize the digital filter to mitigate a downward bias or rounding error introduced by the filtering circuitry to an output of the filtering circuitry.

US Pat. No. 10,366,743

MEMORY WITH A REDUCED ARRAY DATA BUS FOOTPRINT

Micron Technology, Inc., ...

1. A memory device, comprising:a memory array including two or more memory bank groups;
I/O gating circuitry;
a local data bus electrically coupling the I/O gating circuitry to the two or more memory bank groups; and
one or more data latches electrically coupled to the local data bus,
wherein—
the local data bus includes a plurality of array data lines shared between the two or more memory bank groups,
the plurality of shared array data lines is configured to transfer data between the I/O gating circuitry and each of the two or more memory bank groups,
data transferred over the plurality of shared array data lines between the I/O gating circuitry and a first memory bank group in the two or more memory bank groups has a first propagation delay,
data transferred over the plurality of shared array data line between the I/O gating circuitry and a second memory bank group in the two or more memory bank groups has a second data propagation delay different than the first propagation delay,
the memory device is configured to match column select generations for the first and the second memory bank groups with the first and the second propagation delays, and
the data latches are configured to transfer first data corresponding to a first access operation off of the local data bus to free up the local data bus to transfer second data corresponding to a second access operation.

US Pat. No. 10,366,741

BIT PROCESSING

ARM Limited, Cambridge (...

1. Circuitry comprising:a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array;
each bit processing circuitry for a given bit position within the ordered bit array comprising:
bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and
bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals;
in which:
the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.

US Pat. No. 10,366,739

STATE DEPENDENT SENSE CIRCUITS AND SENSE OPERATIONS FOR STORAGE DEVICES

SanDisk Technologies LLC,...

1. A circuit comprising:a sense circuit coupled to a bit line, the sense circuit comprising:
a charge-storing circuit configured to generate a sense voltage; and
an input circuit configured to:
supply a first pulse to the charge-storing circuit in response to the bit line comprising a selected bit line; and
supply a second pulse to the charge-storing circuit with a lower magnitude than the first pulse in response to the bit line comprising an unselected bit line.

US Pat. No. 10,366,737

MANAGEMENT OF STROBE/CLOCK PHASE TOLERANCES DURING EXTENDED WRITE PREAMBLES

Micron Technology, Inc., ...

1. A memory device comprising:a command decoder configured to receive a command signal, wherein the command decoder is configured to provide a write command signal when the received command signal indicates a write operation;
an input/output (I/O) interface configured to receive the write command signal, a data strobe signal that comprises a first preamble of a plurality of preambles, and a data signal, wherein the I/O interface comprises preamble decoding circuitry configured to:
receive a preamble signal associated with the first preamble;
capture a preamble feature of the data strobe signal based on the preamble signal, wherein the preamble feature comprises a rising edge, a falling edge, a high logic value, a low logic value, or a first combination thereof; and
cause the I/O interface to capture a first bit of the data signal based on a data strobe feature that follows the preamble feature, wherein the data strobe feature comprises the rising edge, the falling edge, the high logic value, the low logic value, or a second combination thereof.

US Pat. No. 10,366,734

PROGRAMMABLE WRITE WORD LINE BOOST FOR LOW VOLTAGE MEMORY OPERATION

Advanced Micro Devices, I...

1. A computing system comprising:a memory configured to operate with each of a plurality of operational voltages, each of said operational voltages corresponding to a different power-performance state (P-state);
a processing unit configured to generate access requests for the memory; and
a system management unit configured to:
set a cross-over region comprising a range of operating voltages for the memory;
determine a target P-state different than a current P-state based on feedback information received from one or more of the processing unit and the memory; and
enable boosting of word line voltage levels in the memory as a transitioning operational voltage of the memory transitions from the current operational voltage to the target operational voltage responsive to determining:
the current operational voltage is greater than the target operational voltage; and
the transitioning operational voltage of the memory is less than a lower limit of the range.

US Pat. No. 10,366,733

WORD LINE CACHE MODE

Micron Technology, Inc., ...

1. A semiconductor device comprising:a plurality of memory cells;
a plurality of word lines that controls operations of the plurality of memory cells;
a plurality of word line drivers that each controls a respective word line of the plurality of word lines, wherein each word line driver of the plurality of word line drivers comprises:
a pull-up transistor to transition a corresponding word line to a logic high voltage; and
a pull-down transistor to transition the corresponding word line to a logic low voltage, wherein the pull-down transistor comprises an n-channel transistor that is activated during an inactive period for the corresponding word line; and
local controls that each controls a respective word line driver of the plurality of word line drivers, wherein the local controls are configured to:
assert a voltage on the corresponding word line of the plurality of word lines;
start an internal timer responsive, at least in part, to assertion of the voltage, wherein the internal timer is configured to provide additional settling of the corresponding word line before activation to reduce channel hot carrier issues for the n-channel transistor;
determine whether the internal timer has elapsed; and
after the internal timer has elapsed, de-assert the voltage from the corresponding word line as a row address strobe timer (tRAS) lockout.

US Pat. No. 10,366,732

SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a buffer control circuit for receiving a power-down mode signal and a detection pulse to generate a buffer control signal;
a first buffer circuit for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal, in a power-down mode; and
a detection pulse generation circuit for receiving the first internal chip select signal to generate the detection pulse.

US Pat. No. 10,366,722

LASER MODE HOP DETECTION IN A HEAT-ASSISTED MAGNETIC RECORDING DEVICE USING A SLIDER SENSOR AND LASER MODULATION

Seagate Technology LLC, ...

1. A method, comprising:while writing to a magnetic recording medium using a slider configured for heat-assisted magnetic recording:
supplying a modulated current to a laser diode of or near the slider to produce modulated light, the modulated current having a mean amplitude that varies or is constant;
supplying power to a writer heater of the slider, the power having a magnitude that varies or is constant;
producing, by a sensor of the slider, a sensor signal representative of output optical power of the laser diode while writing to the medium;
measuring a change in the sensor signal; and
detecting a laser mode hop using the measured sensor signal change.

US Pat. No. 10,366,721

HEAD POSITIONING OF TIMING-BASED SERVO SYSTEM FOR MAGNETIC TAPE RECORDING DEVICE

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support,
wherein the magnetic layer includes a timing-based servo pattern,
the ferromagnetic powder is ferromagnetic hexagonal ferrite powder having an activation volume equal to or smaller than 1,600 nm3,
an intensity ratio Int(110)/Int(114) of a peak intensity Int(110) of a diffraction peak of a (110) plane with respect to a peak intensity Int(114) of a diffraction peak of a (114) plane of a hexagonal ferrite crystal structure obtained by an X-ray diffraction analysis of the magnetic layer by using an In-Plane method is 0.5 to 4.0,
a vertical direction squareness ratio of the magnetic tape is 0.65 to 1.00, and
an edge shape of the timing-based servo pattern specified by magnetic force microscope observation is a shape in which a difference (L99.9?L0.1) of a value L99.9 of a cumulative distribution function of 99.9% of a position shift width from an ideal shape in a longitudinal direction of the magnetic tape and a value L0.1 of the cumulative distribution function of 0.1% is equal to or smaller than 180 nm.

US Pat. No. 10,366,716

CHARACTERIZATION OF NONLINEARITY IN SERVO PATTERNS

International Business Ma...

1. A method, comprising:applying a static head skew to a magnetic tape head for misaligning first and second readers in a direction perpendicular to a tape travel direction thereacross;
positioning the first reader at a first y-position relative to a servo pattern in a servo band;
measuring y-positions of the second reader relative to the servo pattern in the servo band while the first reader is at the first y-position;
averaging the measured y-positions;
repeating the following process several times:
moving the first reader to a next y-position,
measuring y-positions of the second reader while the first reader is at the next y-position,
averaging the y-positions measured by the second reader while the first reader is at the next y-position;
calculating a unique nonlinearity value of the servo pattern in the servo band for each of the average y-position values using the respective average y-position value; and
storing and/or outputting the calculated nonlinearity values.

US Pat. No. 10,366,715

SLIDER WITH HEAT SINK BETWEEN READ TRANSDUCER AND SUBSTRATE

Seagate Technology LLC, ...

1. A slider, comprising:a substrate;
a read transducer comprising first and second shields surrounding a read sensor, the first shield facing the substrate, a first end of the reader stack at a media-facing surface of the slider and a second end of the reader stack facing away from the first end;
a heater located farther away from the media-facing surface than the second end of the read transducer, the heater configured to control a thermal protrusion of the read transducer from the media-facing surface;
a heat sink between and in contact with both the first shield and the substrate, the heat sink configured to conduct heat from the first shield to the substrate while minimizing heat transfer between the heater and the substrate.

US Pat. No. 10,366,713

DESIGNS FOR MULTIPLE PERPENDICULAR MAGNETIC RECORDING (PMR) WRITERS AND RELATED HEAD GIMBAL ASSEMBLY (HGA) PROCESS

Headway Technologies, Inc...

1. A head gimbal assembly (HGA), comprising:(a) a slider on which a PMR writer structure is formed;
(b) the PMR writer structure, comprising:
(1) a first writer with a first main pole that is formed between a first bucking coil and a first driving coil; and
(2) a second writer with a second main pole that is formed between a second bucking coil (DC) and a second driving coil (DC);
(c) a plurality of nW+ pads on the slider, and comprised of a W1+ pad that is connected to the first DC, and a W2+ pad connected to the second DC, and a plurality of nW? pads formed on the slider, and comprising a W1? pad that is connected to the first BC, and a W2? pad connected to the second BC; and
(d) a first trace line (TL1) from a preamp where the TL1 is formed on a flexure in the HGA and has a plurality of nTL1? arms wherein one TL1 arm is connected to one of the plurality of W? pads, and a second trace line (TL2) from the preamp where the TL2 is formed on the flexure and has a plurality of nTL2? arms wherein one TL2 arm is connected to one of the plurality of W+ pads thereby enabling only the first writer to be functional when the one TL1 arm is connected to the W1? pad and the one TL2 arm is connected to the W1+ pad, or only the second writer to be functional when the one TL1 arm is connected to the W2? pad and the one TL2 arm is connected to the W2+ pad.

US Pat. No. 10,366,711

APPLYING A PRE-ERASE OR PRE-CONDITION FIELD TO A HARD DISK BEFORE WRITING DATA TO THE HARD DISK

Seagate Technology LLC, ...

1. A method, comprising:detecting an event during field operation of a hard drive that causes at least part of a track of the hard drive to be selected for pre-erase or preconditioning;
in response to the event, pre-writing a pattern using a pre-erase or pre-conditioning magnetic field applied within at least part of the selected track via a first write transducer prior to the selected track being written; and
subsequent to the pre-writing, writing target user data over the pattern pre-written to the part of the selected track.

US Pat. No. 10,366,710

ACOUSTIC MEANINGFUL SIGNAL DETECTION IN WIND NOISE

NXP B.V., Eindhoven (NL)...

1. A method of distinguishing, within a received acoustic signal, a meaningful acoustic signal from low frequency acoustic noise, comprising:a first step of dividing the acoustic signal into frames,
a second step of calculating a power spectral density of the acoustic signal for each frame and finding an envelope curve of the power spectral densities,
a third step of finding a predefined number of dominant peaks in the envelope curve,
a fourth step of applying a linear regression algorithm to the dominant peaks to obtain a linear regression line for each frame of the acoustic signal and extracting a slope value of each linear regression line,
a fifth step of defining those intervals within the acoustic signal that include the meaningful signal as intervals which correspond to higher values of the slope value.

US Pat. No. 10,366,703

METHOD AND APPARATUS FOR PROCESSING AUDIO SIGNAL INCLUDING SHOCK NOISE

SAMSUNG ELECTRONICS CO., ...

1. A method of processing an audio signal in a terminal device, the method comprising:acquiring an audio signal of a frequency domain for a current frame;
dividing a frequency band into a plurality of sections;
acquiring energies of a first section and a second section from among the plurality of sections;
determining whether the audio signal of the current frame includes noise based on an energy difference between the first section and the second section; and
applying a suppression gain to the audio signal of the current frame and outputting the audio signal of the current frame applied the suppression gain, based on a result of determining,
wherein the first section and the second section are non-overlapped in the frequency band, and
wherein at least one of the first section and the second section is determined as a shock noise section based on the energy difference.

US Pat. No. 10,366,702

DIRECTION DETECTION DEVICE FOR ACQUIRING AND PROCESSING AUDIBLE INPUT

LOGITECH EUROPE, S.A., L...

1. A method of determining a direction from which an audible signal is received, comprising:defining an audible signal detection region by dividing a first angular distance created between a first microphone and a second microphone that are disposed on an electronic device into at least two regions, wherein one of the at least two regions comprise a second angular distance that is formed between a first direction and a second direction that each extend from a vertex point;
determining, by use of an electronic device, a first relative time delay created by the delivery of a first portion of an audible signal to the first microphone and the second microphone from an external audible source, wherein the first relative time delay is calculated by determining a difference between a time when the second microphone received the first portion of the audible signal and a time when the first microphone received the first portion of the audible signal;
comparing, by use of the electronic device, the first relative time delay with a plurality of stored time delays, wherein the plurality of stored time delays comprise:
a first stored time delay that is associated with the external audible source being positioned a distance from the first and second microphones along the first direction; and
a second stored time delay that is associated with the external audible source being positioned a distance from the first and second microphones along the second direction; and
determining, by use of the electronic device, that the external audible source is positioned in a third direction by determining that the first portion of the audible signal was received from a direction that is closer to the third direction that is positioned between the first and second directions versus a fourth direction that is positioned outside of the second angular distance formed between the first and second directions based on the comparison of the first relative time delay with the first and second stored time delays.

US Pat. No. 10,366,701

ADAPTIVE MULTI-MICROPHONE BEAMFORMING

QOSOUND, INC., San Cleme...

1. A method for producing an amplified enhanced audio signal for an output device from audio signals received by a first and a second microphone in close proximity to each other, said method comprising the steps of:receiving a first input audio signal from the first microphone;
digitizing said first input audio signal to produce a first digitized audio input signal;
receiving a second input audio input signal from the second microphone;
digitizing said second input audio input signal to produce a second digitized audio input signal;
using said first digitized audio input signal as a input to a first adaptive prediction filter and as reference to a second adaptive prediction filter;
using said second digitized audio input signal as an input to said second adaptive prediction filter and as reference to said first adaptive prediction filter;
adding a prediction result signal from said first adaptive prediction filter to said second digitized audio input signal to produce a second enhanced audio signal; and
adding a prediction result signal from said second adaptive prediction filter to said first digitized audio input signal to produce a first enhanced audio signal
applying said first enhanced audio signal as input to a third adaptive prediction filter;
applying said second enhanced signal as reference to said third adaptive prediction filter;
adding a prediction result from said third adaptive prediction filter to said second enhanced signal to form said amplified enhanced audio signal; and
outputting said enhanced audio signal to an output device.

US Pat. No. 10,366,690

SPEECH RECOGNITION ENTITY RESOLUTION

Amazon Technologies, Inc....

1. A computing system, comprising:at least one processor; and
at least one memory including instructions that, when executed by the at least one processor, cause the computing system to:
receive text data corresponding to a command executable by the computing system;
determine, based at least in part on the text data, an intent corresponding to the command;
determine first text string data of the text data, the first text string data corresponding to an entity;
determine a lexicon associated with the intent;
determine, in the lexicon, second text string data corresponding to the entity, wherein the second text string data is different from the first text string data and the second text string data corresponds to a recognized format for referring to the entity with respect to the intent; and
cause an action to be executed for the intent using the second text string data.

US Pat. No. 10,366,687

SYSTEM AND METHODS FOR ADAPTING NEURAL NETWORK ACOUSTIC MODELS

Nuance Communications, In...

1. A method for adapting a trained neural network acoustic model, the method comprising:using at least one computer hardware processor to perform:
generating speaker information values for a speaker;
generating speech content values from speech data corresponding to an utterance spoken by the speaker;
processing the speech content values and the speaker information values using the trained neural network acoustic model, the trained neural network acoustic model comprising a neural network and the processing comprising inputting the speaker information values to a partial layer of nodes of the neural network that is positioned in the neural network before a hidden layer of nodes of the neural network, the partial layer of nodes being configured to apply a transformation to the speaker information values based on parameters with which the partial layer of nodes are configured; and
generating updated parameters for the partial layer of nodes based on the processing.

US Pat. No. 10,366,684

INFORMATION PROVIDING METHOD AND INFORMATION PROVIDING DEVICE

YAMAHA CORPORATION, Hama...

1. An information providing method comprising the steps of:sequentially identifying a performance speed at which a user performs a piece of music;
identifying, in the piece of music, a performance position at which the user is performing the piece of music;
setting an adjustment amount in accordance with a temporal variation in the identified performance speed;
providing the user with music information corresponding to a time point that is later, by the set adjustment amount, than a time point that corresponds to the performance position identified in the piece of music;
calculating, from a time series consisting of a prescribed number of performance speeds that are identified, a variation degree, which is an indicator of a degree and a direction of the temporal variation in the performance speed,
wherein the setting step sets the adjustment amount in accordance with the variation degree.

US Pat. No. 10,366,683

PERCUSSION INSTRUMENT PLAYING DEVICE

UTSUWA INC., Kyoto (JP)

1. A percussion-instrument playing apparatus comprising:a main body to be detachably fixed in front of or above a percussion instrument having, in a front surface or an upper surface, a striking surface, the main body including two fixing portions to be detachably fixed to both sides of the striking surface of the percussion instrument and an arm attachment member that bridges a space between the two fixing portions, and the arm attachment member facing the striking surface with a predetermined space from the striking surface when the two fixing portions are respectively fixed to both sides of the striking surface of the percussion instrument;
an arm supporter fixed to the arm attachment member;
one or more arms each having one end fixed to the arm supporter;
an arm head detachably fixed to the other end of the arm; and
a drive unit for driving the one or more arms under electronic control,
wherein the arm head of each of the one or more arms strikes the same striking surface of the percussion instrument to cause sounds to be emitted from the percussion instrument.

US Pat. No. 10,366,680

ANTI-LOOSENING DEVICE FOR DRUM TENSION BOLT

HOSHINO GAKKI CO., LTD., ...

1. An anti-loosening device for a drum tension bolt that is configured to be attached to a tension bolt for adjusting tension of a drumhead, the anti-loosening device comprising a main body configured to be in contact with a drum when attached to the tension bolt, whereinthe main body includes
a fitting hole, into which a bolt head of the tension bolt is to be fitted, and
a holding section, which is configured to laterally hold the tension bolt, and
the holding section is configured to open about a center line of the fitting hole and elastically grip the bolt head of the tension bolt, and wherein
the holding section includes
a flexible section, which extends in a thickness direction of the main body, and
a jaw, which projects from a distal end of the flexible section toward the center line of the fitting hole.

US Pat. No. 10,366,678

PICK FOR USE WITH A STRINGED INSTRUMENT

1. A pick for use with a stringed instrument, said pick being constructed of a material comprising:a polyimide material characterized by a ring-shaped molecular structure containing nitrogen, and additionally comprising graphite.

US Pat. No. 10,366,669

ELECTRONIC DEVICE AND METHOD FOR DRIVING DISPLAY THEREOF

Samsung Electronics Co., ...

1. An electronic device comprising:a display;
a processor configured to generate a plurality of encoded frame images, including a first encoded frame image, to be provided to the display; and
a display driving circuit including an image-process circuit, a memory, and at least one decoder, the image-process circuit being downstream of the memory,
the display driving circuit being configured to drive the display using the first encoded frame image provided from the processor,
wherein the display driving circuit is further configured to:
receive the first encoded frame image, provided from the processor, and store the first encoded frame image in the memory;
generate a first decoded frame image by decoding the first encoded frame image after receiving and storing the first encoded frame image,
generate a first image-processed frame image by image-processing the first decoded frame image after generating the first decoded frame image,
cause to display, through the display, the first image-processed frame image as a first frame,
generate a second encoded frame image by encoding the first image-processed frame image, and store the second encoded frame image in the memory,
generate a second decoded frame image by decoding the second encoded frame image after storing the second encoded frame image,
after generating the second decoded frame image, cause to display the second decoded frame image as a second frame through the display, without image-processing the second decoded frame image, while the processor is in a low-power state.

US Pat. No. 10,366,668

DATA DRIVER AND A DISPLAY APPARATUS HAVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A data driver which drives a display panel comprising a data line, a gate line and a common voltage line, the data driver comprising:a digital-to-analog converter configured to convert a data signal to a data voltage;
an output buffer configured to amplify the data voltage, wherein the output buffer comprises an output channel through which an amplified data voltage is output to the data line and a dummy channel through which a feedback voltage corresponding to a common voltage from the common voltage line is received;
a feedback line connected to the dummy channel,
wherein the output buffer further comprises a switching element configured to connect the dummy channel to the feedback line.

US Pat. No. 10,366,666

DISPLAY APPARATUS AND METHOD FOR CONTROLLING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display apparatus comprising:a display panel configured to include a plurality of pixels arranged at intersections of data lines and gate lines;
a source driver integrated circuit (IC) disposed on one side surface of the display panel and configured to apply a data voltage to the data lines;
a gate driver IC disposed on one of two side surfaces of the display panel that are adjacent to the one side surface of the display panel and configured to apply a gate driving voltage to the gate lines; and
a controller configured to receive, as a feedback signal, information on a gate driving voltage, applied to at least one pixel on a gate line from among the gate lines, detect a distortion of the gate driving voltage applied to the at least one pixel of the gate line based on the feedback signal, identify a degree of the distortion of the gate driving voltage, increase a level of the gate driving voltage applied to the gate lines according to the identified degree of the distortion for compensating the detected distortion of the gate driving voltage, and apply the increased gate driving voltage to the gate lines,
wherein the at least one pixel is located at a position farthest away from the gate driver IC on the gate line.

US Pat. No. 10,366,665

DISPLAY DEVICE AND METHOD FOR EXPANDING COLOR SPACE

SHARP KABUSHIKI KAISHA, ...

1. A display device provided with a display panel for displaying an image, the display device comprising:an expanded video signal generation unit configured to perform an expansion process for increasing a signal value of an input video signal, and output data obtained by the expansion process as an expanded video signal;
an expansion coefficient decision unit configured to decide an expansion coefficient to be used for the expansion process by the expanded video signal generation unit; and
an output video signal generation unit configured to generate an output video signal to be outputted to the display panel based on the expanded video signal, wherein
the expansion coefficient decision unit
decides the expansion coefficient based on a first function, which is a function representing an inverse of saturation obtained based on the input video signal, for a pixel with the saturation not smaller than a predetermined value, and
decides the expansion coefficient based on a second function that is a quadratic function, in which saturation obtained based on the input video signal is set to a parameter and a coefficient of a quadratic term is a negative value, for a pixel with the saturation not larger than the predetermined value, and
the expanded video signal generation unit multiplies the expansion coefficient, decided by the expansion coefficient decision unit, by a signal value of the input video signal for each pixel, to generate the expanded video signal.