US Pat. No. 10,249,598

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Intel Corporation, Santa...

1. A method of forming an integrated circuit (IC) package comprising:providing a first encapsulation layer having a first die and a plurality of electrical routing features at least partially embedded therein, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer on a first side of the first die, wherein the first die has a second side opposite the first side, wherein the plurality of electrical routing features electrically couple the first side of the first encapsulation layer with a second side of the first encapsulation layer, and wherein the first side of the first encapsulation layer is disposed opposite the second side of the first encapsulation layer, wherein the first encapsulation layer at least partially covers an electrically insulative material layer, wherein the plurality of electrical routing features fully extend through the electrically insulative material layer;
coupling a second die with the second side of the first encapsulation layer, wherein the second die includes a second plurality of die-level interconnect structures, and wherein the first encapsulation layer covers the second side of the first die;
electrically coupling the second plurality of die-level interconnect structures with at least a subset of the plurality of electrical routing features by bonding wires; and
forming a second encapsulation layer over the second die and the bonding wires to encapsulate at least a portion of the second die and the bonding wires in the second encapsulation layer, wherein the second encapsulation layer is in direct contact with the first encapsulation layer.

US Pat. No. 10,249,595

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) providing an arrangement having a semiconductor chip mounted on a die pad, a suspension lead connected to the die pad, and a lead spaced apart from the die pad and the suspension lead;
(b) sealing the semiconductor chip, the lead, and the suspension lead;
(c) after the step (b), cutting the lead with a punch;
(d) after the step (c), making a mark on a front surface of a sealing body formed by the step (b); and
(e) after the step (d), cutting the suspension lead with a punch.

US Pat. No. 10,249,594

DISPLAY DEVICE AND METHOD FOR ASSEMBLING THE SAME

BOE Technology Group Co.,...

1. A display device, comprising an electronic device and a flexible printed circuit board which are detachably connected,wherein the electronic device comprises a lead region and a port located at the lead region, the flexible printed circuit board comprises a first portion and a second portion,
wherein the first portion is a connector, the second portion comprises connecting fingers through which the flexible printed circuit board is connected to the port,
wherein the second portion of the flexible printed circuit board is arranged at a predetermined region, the predetermined region comprises the lead region and an extension region which is arranged outside the lead region and in a same plane where the lead region is located, and the extension region is a region extending outwards from the lead region until reaching other components and is within a surface of the electronic device where the lead region located,
wherein the flexible printed circuit board is provided with a hollow part, configured to allow a component which is arranged at the lead region to be exposed when the flexible printed circuit board is attached onto the lead region, a driving chip is arranged at the lead region, the flexible printed circuit board is provided with the hollow part located at a region corresponding to the driving chip to allow the driving chip to be exposed at the hollow part when the flexible printed circuit board is attached onto the lead region.

US Pat. No. 10,249,593

METHOD FOR BONDING A CHIP TO A WAFER

Agency for Science, Techn...

1. A method for chip on wafer bonding, comprising:forming posts on a wafer;
forming contacts on a chip such that the posts and the contacts align upon inversion of the chip onto the wafer;
planarizing each of the posts to have a contact surface with a surface roughness height less than 20 nanometers;
depositing, to the contact surface of the posts, a bonding material with a thickness not greater than the surface roughness height of the contact surface; and
temporarily bonding the posts to the contacts using the bonding material to stabilize a position of the chip relative to the wafer before subsequently permanently diffusion bonding of the chip to the wafer,
wherein the surface roughness height is a difference in height between a lowest point on a surface of the contact surface and a highest point on the surface of the contact surface.

US Pat. No. 10,249,590

STACKED DIES USING ONE OR MORE INTERPOSERS

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and
an interposer which includes interconnects that aligns to and electrically connects at least one functional via interconnect and a redundant functional via interconnect of a different die when the interposer is oriented in a predetermined orientation, wherein the interconnects of the interposer are directly connected by solder bumps to the at least one functional via interconnect of the at least one die and the redundant functional via interconnect of the different die.

US Pat. No. 10,249,589

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LAYER AND CONDUCTIVE PILLAR DISPOSED ON CONDUCTIVE LAYER AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor layer formed over the semiconductor substrate and including a first upper surface and a first lower surface;
a conductive pillar disposed on the first upper surface of the conductor layer and including a second upper surface, a second lower surface, and a sidewall;
a first insulating film covering the first upper surface of the conductor layer and including an opening which exposes the second upper surface and the sidewall of the conductive pillar;
a protection film covering the sidewall of the conductive pillar,
wherein, in a plan view, the opening is wider than the second upper surface and exposes an entire region of the second upper surface, and
wherein the second lower surface of the conductive pillar is in contact with the first upper surface of the conductor layer in an entire region of the conductive pillar; and
a second insulating film formed under the conductor layer in such a manner as to overlap with the entire region of the conductive pillar in the plan view,
wherein, in the plan view, the first upper surface of the conductor layer is exposed from the protection film and the conductive pillar.

US Pat. No. 10,249,588

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Intel Corporation, Santa...

1. A method of forming an assembly, comprising:providing a substrate, the substrate having a metal pad including aluminum, a base layer metal (BLM) disposed on the metal pad, the BLM including titanium, a bump disposed on the BLM, the bump including copper, and a first solder layer disposed on the bump, the first solder layer including tin and having a first material composition;
providing a die package, the die package having a first side and an opposing second side, and a second solder layer disposed on the first side of the die package, the second solder layer including tin and having a second material composition different from the first material composition, wherein one of the first solder layer or the second solder layer comprises an element not included in the other of the first solder layer or the second solder layer;
connecting the second solder layer of the die package to the first solder layer of the substrate to enable electrical current to flow between the die package and the substrate.

US Pat. No. 10,249,587

SEMICONDUCTOR DEVICE INCLUDING OPTIONAL PAD INTERCONNECT

Western Digital Technolog...

1. A semiconductor die, comprising:a plurality a die bond pads, comprising:
a first die bond pad, and
a second die bond pad configured to provide functional redundancy to the first die bond pad; and
a metal interconnect having a first end connected to the first die bond pad and a second end, opposite the first end, connected to at least a portion of the second die bond pad.

US Pat. No. 10,249,586

MIXED UBM AND MIXED PITCH ON A SINGLE DIE

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first set of micro under-bump metallizations (UBMs) on a surface of a photosensitive polyimide (PSPI) layer in a first region of a die comprising a first pitch constraint, each micro UBM comprising a via electrically coupling the respective UBM to a contact region of the die;
forming a second set of micro UBMs on a surface of the PSPI layer in a second region of the die comprising a second pitch constraint, each micro UBM comprising a via electrically coupling the respective UBM to a contact region of the die, the second pitch constraint higher than the first pitch constraint, wherein the first region and the second region are configured to have a matching plateable surface areas;
forming a single solder bump electrically shorting the first set of micro UBMs to a single contact region of a laminate, wherein the single solder bump has an elliptical shape; and
forming individual solder bumps electrically shorting each of the second set of micro UBMs to a contact region of a laminate.

US Pat. No. 10,249,585

STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A stackable semiconductor package, comprising:a carrier having a first surface, at least one sidewall substantially perpendicular to the first surface, and a plurality of through holes penetrating through the first surface, the through holes including a plurality of terminal holes and a chip-accommodating hole, wherein the carrier is only made of a rigid plate having no electrical transmission function;
a first redistribution layer (RDL) formed directly on and in physical contact with the first surface of the carrier, wherein the first RDL comprises a plurality of first pads and a plurality of second pads, the terminal holes correspondingly expose a portion of each of the second pads, and the chip-accommodating hole exposes the first pads;
an encapsulation layer formed directly on and in physical contact with the first surface of the carrier, the encapsulation layer encapsulating the first RDL, wherein the encapsulation layer has an outer surface and at least one sidewall substantially perpendicular to the outer surface of the encapsulation layer and the first surface of the carrier, the at least one sidewall of the encapsulation layer being correspondingly coplanar to the at least one sidewall of the carrier;
a plurality of vertical interposers disposed in the encapsulation layer, wherein the vertical interposers are electrically connected to the first RDL;
a second RDL formed on the outer surface of the encapsulation layer to electrically connect with the vertical interposers, the second RDL comprising a plurality of third pads; and
a chip disposed in the chip-accommodating hole, and electrically connected to the first pads.

US Pat. No. 10,249,583

SEMICONDUCTOR DIE BOND PAD WITH INSULATING SEPARATOR

Infineon Technologies AG,...

1. A semiconductor die, comprising:a last metallization layer above a semiconductor substrate;
a bond pad above the last metallization layer;
a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad;
an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad; and
an electrically conductive interconnection structure that extends from the bond pad to the last metallization layer outside the contact area of the bond pad.

US Pat. No. 10,249,581

TRANSMISSION LINE FOR 3D INTEGRATED CIRCUIT

Taiwan Semiconductor Manu...

1. A semiconductor transmission line substructure comprising:a first semiconductor substrate;
a first signal line over said first semiconductor substrate;
a first ground line over said first semiconductor substrate;
a second semiconductor substrate over said first semiconductor substrate, wherein each of said first semiconductor substrate, said first signal line, said first ground line and said second semiconductor substrate are vertically spaced apart from one another, wherein said second semiconductor substrate is between said first signal line and said first ground line.

US Pat. No. 10,249,579

ACTIVE SHIELD FOR PROTECTING A DEVICE FROM BACKSIDE ATTACKS

NUVOTON TECHNOLOGY CORPOR...

1. An electronic apparatus, comprising:a substrate comprising active devices;
one or more routing layers, which are electrically connected to the active devices and are configured to route electrical signals to and from the active devices;
an active shield layer, which is disposed within a routing layer nearest to the substrate, wherein the active shield layer comprises metallic traces configured to conduct active-shield signals that provide an indication of an attack on the apparatus; and
protection circuitry, which is connected to the metallic traces of the active-shield layer and is configured to drive the active-shield signals and to detect the attack based on the active-shield signals.

US Pat. No. 10,249,578

CORE-SHELL PARTICLES FOR ANTI-TAMPERING APPLICATIONS

International Business Ma...

1. A method of making a tamper resistant apparatus, comprising:disposing a core-shell particle on a first surface of a tampering sensor, the first surface including a first conductive portion and a second conductive portion spaced from each other, wherein
the core-shell particle has a liquid metallic core and a shell surrounding the liquid metallic core, and
the tampering sensor is configured to trigger a security response when the first conductive portion and the second conductive portion are electrically connected to each other.

US Pat. No. 10,249,575

RADIO-FREQUENCY ISOLATION USING CAVITY FORMED IN INTERFACE LAYER

Skyworks Solutions, Inc.,...

1. A method for fabricating a semiconductor device, the method comprising:providing a transistor device;
forming one or more electrical connections to the transistor device;
forming one or more dielectric layers over at least a portion of the electrical connections;
applying an interface material over at least a portion of the one or more dielectric layers;
removing at least a portion of the interface material to form a trench; and
covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

US Pat. No. 10,249,574

METHOD FOR MANUFACTURING A SEAL RING STRUCTURE TO AVOID DELAMINATION DEFECT

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a semiconductor substrate;
forming a plurality of integrated circuit (IC) devices on the semiconductor substrate; and
forming a seal ring structure surrounding each of the IC devices, wherein forming the seal ring structure comprises:
forming a plurality of interlayer dielectric layers on the semiconductor substrate; and
forming a plurality of hollow through-hole structures within the interlayer dielectric layers, wherein forming a plurality of hollow through-hole structures within the interlayer dielectric layers comprises:
performing an etching process on each of the interlayer dielectric layers at a location of a cutting channel in the semiconductor substrate to form one or more through-holes;
sequentially forming a diffusion barrier layer and a seed layer at a bottom portion and sidewalls of the one or more through-holes, wherein the diffusion barrier layer and the seed layer seal an opening at a top portion of the one or more through-holes.

US Pat. No. 10,249,573

SEMICONDUCTOR DEVICE PACKAGE WITH A STRESS RELAX PATTERN

POWERTECH TECHNOLOGY INC....

1. A method of forming a semiconductor device package, the semiconductor device package comprising:a die;
a plurality of metal contacts electrically connected to the die;
a continuous pattern of dielectric material formed on an active surface of the die, the continuous pattern of dielectric material forming contours of at least one opening, each of the at least one opening surrounding at least one of the metal contacts electrically connected to the die;
a mold compound formed around the pattern, the die and the metal contacts, wherein at least a space between the metal contacts and the pattern is filled with the mold compound; and
a redistribution layer, formed on a grinded surface of the mold compound, and electrically connected to the metal contacts;the method comprising:disposing the die on a carrier;
forming the pattern of dielectric material on the active surface of the die to surround the plurality of metal contacts electrically connected to the die;
forming the mold compound around the die, the metal contacts and the pattern, wherein the dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound;
grinding the mold compound to expose the metal contacts;
removing the carrier; and
forming the redistribution layer on the grinded surface of the mold compound to electrically connect the metal contacts.

US Pat. No. 10,249,571

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL

BOE Technology Group Co.,...

1. A thin film transistor comprising:an active layer, and a light-protection layer disposed above the active layer and/or disposed beneath the active layer,
wherein the light-protection layer is configured to absorb light having a predetermined wavelength, and
wherein a forbidden band gap of the light-protection layer is greater 1.1 eV and less than 2.3 eV with a transmissivity lower than 70%.

US Pat. No. 10,249,570

OVERLAY MARK

TAIWAN SEMICONDUCTOR MANU...

1. An overlay mark, comprising:a first feature in a first layer, wherein the first feature comprises a plurality of first alignment segments extending along a first direction;
a second feature in a second layer over the first layer, wherein the second feature comprises a plurality of second alignment segments extending along a second direction different from the first direction; and
a third feature in a third layer over the second layer, wherein the third feature comprises a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction,
wherein, in a plan view, each first alignment segment of the plurality of first alignment segments is adjacent to a corresponding third alignment segment of the plurality of third alignment segments along the first direction, and each second alignment segment of the plurality of second alignment segments is adjacent to a corresponding fourth alignment segment of the plurality of fourth alignment segments along the second direction.

US Pat. No. 10,249,569

SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A system-on-chip, comprising:a processor; and
a hardware component connected to the processor,
wherein at least one of the processor and the hardware component comprises:
a semiconductor substrate; and
a plurality of metal layers formed above the semiconductor substrate,
wherein a first metal layer among the plurality of metal layers comprises:
a plurality of first power rails which extend in a first direction and transmit a first voltage;
a plurality of second power rails which extends in the first direction and transmit a second voltage; and
a first conductor which is coupled to one end of each of the first power rails and extends in a second direction,
wherein a second metal layer placed over the first metal layer comprises:
a third power rail transmitting the first voltage; and
a fourth power rail transmitting the second voltage, and
wherein the third power rail and the fourth power rail are spaced apart from the first conductor in the first direction.

US Pat. No. 10,249,567

REDISTRIBUTION LAYER STRUCTURE OF SEMICONDUCTOR PACKAGE

Industrial Technology Res...

17. A redistribution layer structure of a semiconductor package, comprising:a dielectric layer having a thickness, and the dielectric layer having a first surface and a second surface opposite to the first surface;
an upper conductive wire disposed on the first surface of the dielectric layer and having a first width;
a lower conductive wire disposed on the second surface of the dielectric layer and having a second width, wherein the upper conductive wire and the lower conductive wire are separated by the dielectric layer; and
a single via penetrating the dielectric layer and connecting the upper conductive wire and the lower conductive wire, wherein the single via has a cross-section at the upper conductive wire, and the cross-section has a third width, wherein a ratio of the third width of the cross-section of the single via to the thickness of the dielectric layer is less than or equal to 1.

US Pat. No. 10,249,566

SEMICONDUCTOR DEVICE INCLUDING FUSE STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a first region and a second region;
an eFuse structure formed in the first region; and
an interconnect structure formed in the second region, wherein:
the eFuse structure includes a first metal pattern formed at a first vertical level on the substrate, a second metal pattern formed at a second vertical level between the first vertical level and the substrate, a third metal pattern formed at a third vertical level between the second vertical level and the substrate, a first via physically connecting the first metal pattern to the second metal pattern, and a second via physically connecting the second metal pattern to the third metal pattern,
the first metal pattern includes a first bent portion in a U shape, and a first auxiliary pattern extending in a first direction and being adjacent to and electrically isolated from the first bent portion,
the first bent portion includes a first portion which extends in the first direction and is electrically connected to the first via, and a second portion extending in the first direction and being adjacent to the first portion,
the second portion is disposed between the first portion and the first auxiliary pattern, and
a first distance between the first portion and the second portion spaced apart from the first portion is greater than a width of the second portion in a second direction perpendicular to the first direction.

US Pat. No. 10,249,565

SEMICONDUCTOR DEVICE THAT TRANSFERS AN ELECTRIC SIGNAL WITH A SET OF INDUCTORS

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate of a substantially rectangular shape having a first surface and a second surface opposite the first surface, a first side, a second side opposite the first side, a third side and a fourth side, which intersect the first and second sides, a plurality of electrode pads formed on the first surface, and a plurality of soldering balls formed on the second surface;
the plurality of electrode pads including a plurality of first electrode pads closer to the first side than the second side and a plurality of second electrode pads closer to the second side than the first side;
the second surface having a first area which is closer to the first side than the second side and which is contiguous to the first, third and fourth sides, a second area which is closer to the second side than the first side and which is contiguous to the second, third and fourth sides, and a third area which is contiguous to the first and second areas, and the third and fourth sides;
the plurality of soldering balls including a plurality of first soldering balls which are shaped in a form of a lattice and which are on the first area, and a plurality of second soldering balls which are shaped in a form of a lattice and which are on the second area;
the plurality of first soldering balls electrically connected with the plurality of the first electrode pads of the wiring substrate;
the plurality of second soldering balls electrically connected with the plurality of the second electrode pads of the wiring substrate;
a first semiconductor chip of a substantially rectangular shape having a first main surface, a first side surface, a second side surface opposite the first side surface, and a first inductor which is closer to the first side surface than the second side surface and which is on the first main surface;
the first semiconductor chip being mounted on the first surface of the wiring substrate and closer to the first side of the wiring substrate than the second side of the wiring substrate;
a second semiconductor chip of a substantially rectangular shape having a second main surface, a third side surface, a fourth side surface opposite the third side surface, and a second inductor which is closer to the third side surface than the fourth side surface and which is on the second main surface;
the second semiconductor chip being mounted side by side with the first semiconductor chip on the first surface of the wiring substrate and closer to the second side of the wiring substrate than the first side of the wiring substrate such that the third side surface faces the first side surface of the first semiconductor chip;
a plurality of bonding wires including a plurality of first bonding wires by which the first main surface of the first semiconductor chip is connected with the plurality of first electrode pads of the wiring substrate, and a plurality of second bonding wires by which the second main surface of the second semiconductor chip is connected with the plurality of second electrode pads of the wiring substrate; and
a sealed resin body covering the first surface of the wiring substrate, the first semiconductor chip, the second semiconductor chip, and the plurality of bonding wires,
wherein, in the plan view, the plurality of first soldering balls include a first ball that is most proximate to the second side of the wiring substrate in the plurality of first soldering balls,
wherein, in the plan view, the plurality of second soldering balls include a second ball that is most proximate to the first side of the wiring substrate in the plurality of second soldering balls,
wherein a shortest distance between the first and second soldering balls is greater than a shortest distance from the first side surface of the first semiconductor chip and the third side surface of the second semiconductor chip in the plan view,
wherein, in the plan view, an area between the first side surface of the first semiconductor chip and the third side surface of the second semiconductor chip on the first surface of the wiring substrate is within the third area of the wiring substrate,
wherein a soldering ball is not in the third area of the wiring substrate;
wherein the first inductor of the first semiconductor chip is not electrically connected with the second inductor of the second semiconductor chip,
wherein the first semiconductor chip is not electrically connected with the second semiconductor chip via a bonding wire in the plan view, and
wherein the first soldering ball is not electrically connected with the second soldering ball.

US Pat. No. 10,249,564

ELECTRONIC COMPONENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

KYOCERA CORPORATION, Kyo...

1. An electronic component mounting substrate comprising:an insulating base having a rectangular shape in plan view and comprising a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface;
a band-shaped metal layer on a sidewall of the recess; and
an electrode extending from a bottom surface of the recess into the insulating base,
the electrode comprising an end disposed in the insulating base, the end comprising an inclined portion inclined toward the second main surface, the inclined portion having a tip, a part of which is closer to the second main surface than the bottom surface of recess when viewed in longitudinal section.

US Pat. No. 10,249,563

MULTILAYER WIRING SUBSTRATE

FUJIFILM Corporation, Mi...

1. A multilayer wiring substrate comprising:an anisotropic conductive member including an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each conductive path has a protrusion protruding from the surface of the insulating base; and
a wiring substrate having a substrate and one or more electrodes to be formed on the substrate,
wherein the multilayer wiring substrate is formed by laminating the anisotropic conductive member and the wiring substrate,
the wiring substrate has a resin layer which covers at least a part of the substrate,
the electrode is formed to be flush with the resin layer,
the resin layer is a layer that allows the protrusion to penetrate therein when pressure is applied at 20 MPa,
at least a part of the protrusions of the conductive paths other than the conductive paths which come in contact with the electrode among the plurality of conductive paths penetrates into the resin layer, and
conductive paths which come into contact with the electrode among the plurality of conductive paths are deformed so that adjacent conductive paths come into contact with each other.

US Pat. No. 10,249,562

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. A package structure, comprising:a carrier having opposite first and second surfaces, wherein at least a recess is formed on the first surface of the carrier;
at least an electronic element disposed in the recess of the carrier;
an insulating layer formed in the recess to encapsulate the electronic element and on the first surface of the carrier to cover the first surface, with a plurality of through holes penetrating the first and second surfaces of the carrier and the insulating layer, wherein the insulating layer is made of a material different from a material of the carrier;
a circuit structure formed on the first surface of the carrier and electrically connected to the electronic element; and
a plurality of conductors formed in the through holes, wherein the conductors are conductive columns and penetrate the first and second surfaces of the carrier and the insulating layer and are electrically connected to the circuit structure.

US Pat. No. 10,249,561

PRINTED WIRING BOARD HAVING EMBEDDED PADS AND METHOD FOR MANUFACTURING THE SAME

IBIDEN CO., LTD., Ogaki ...

1. A printed wiring board, comprising:a support plate; and
a build-up wiring layer comprising a plurality of resin insulating layers and a plurality of conductor layers and having a first surface and a second surface on an opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer,
wherein the plurality of resin insulating layers in the build-up wiring layer includes a first resin insulating layer that forms the second surface of the build-up wiring layer, the build-up wiring layer includes a plurality of first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer, and a plurality of via conductors formed in the plurality of resin insulating layers such that diameters of the via conductors are reducing from the first surface toward the second surface of the build-up wiring layer, each of the first conductor pads comprises a dissimilar metal layer comprising a plurality of metal layers such that the metal layers are formed of different metals with respect to each other, and the dissimilar metal layer comprises a copper plating layer and a corrosion resistant plating layer formed on the copper plating layer.

US Pat. No. 10,249,559

BALL GRID ARRAY AND LAND GRID ARRAY ASSEMBLIES FABRICATED USING TEMPORARY RESIST

International Business Ma...

1. A structure comprising:a substrate including a front side, a back side, and electrically conductive contact pads on the back side;
a patterned resist film directly contacting the back side of the substrate, the resist film including channels exposing a plurality of the contact pads;
a plurality of solder bumps, each of the solder bumps being within one of the channels in the patterned resist film and electrically contacting one of the contact pads;
a plurality of contact elements on the front side of the substrate configured for electrical connection to a chip;
a chip electrically and mechanically connected to the contact elements; and
one or more stand-off elements within one or more of the channels of the patterned resist film and solder material encasing the one or more stand-off elements, the one or more stand-off elements having substantially higher melting points than the solder material and the solder bumps.

US Pat. No. 10,249,558

ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE

NSK LTD., Tokyo (JP)

22. An electronic part mounting heat-dissipating substrate which comprises: a conductor plate which is formed on lead frames of wiring pattern shapes to mount an electronic part; and an insulating member which is provided between said lead frames of said wiring pattern shapes on said conductor plate; in which a plate surface of an electronic part arrangement surface of said conductor plate and a plate surface of an electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane, and a plate surface of a back surface of said electronic part arrangement surface of said conductor plate and a plate surface of a back surface of said electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane,wherein said lead frames of said wiring pattern shapes have different thicknesses of at least two types or more, a thickness of the lead frames being measured in a direction parallel to the mounting direction of the electronic part, and a thick lead frame is used for a large current signal and a thin lead frame is used for a small current signal,
wherein said plate surface of said back surface of said electronic part arrangement surface of said lead frames of said wiring pattern shapes and said plate surface of said back surface of said electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane to meet said plate surface of said back surface of said electronic part arrangement surface of a thickest lead frame among said lead frames, and
wherein plural pin-shape cavities are disposed on a substrate surface that is a different surface on which a thin lead frame of said electronic part arrangement surface is provided, and are extended from a back surface side of said substrate of said thin lead frame to said different surface side of said substrate.

US Pat. No. 10,249,555

COMPOSITE HEAT SINK STRUCTURES

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:a composite heat sink structure including:
a thermally conductive base, the thermally conductive base including a main heat transfer surface to couple to at least one component to be cooled;
a compressible, continuous sealing member;
a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base;
a one-piece member molded over and affixed to the thermally conductive base, and molded over and securing in place the sealing member retainer, wherein a coolant-carrying compartment resides between the thermally conductive base and the one-piece member and wherein the one-piece member contacts a surface of the thermally conductive base opposite to the main heat transfer surface and wraps around at least a portion of the thermally conductive base to secure the one-piece member to the thermally conductive base absent use of separate fasteners; and
a coolant inlet and a coolant outlet, the coolant inlet and coolant outlet being in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow therethrough.

US Pat. No. 10,249,554

HEAT TRANSFER ASSEMBLY FOR A HEAT EMITTING DEVICE

GENERAL ELECTRIC COMPANY,...

1. A heat transfer assembly coupled to a heat emitting device for dissipating heat from the heat emitting device, the heat transfer assembly comprising:a module inlet for receiving a coolant;
at least one module comprising a first part having a recess to receive a portion of the heat emitting device, and a second part having a shaped cutout portion and a solid portion;
a sealing component disposed between the heat emitting device and the at least one module;
a module outlet for discharging a heat absorbed coolant after absorbing heat from the heat emitting device, wherein the at least one module is connected to the module inlet and the module outlet,wherein the second part allows a uniform compression of the seal component, and wherein the first part and the second part are mechanically connected to each other; andwherein the at least one module is flexible to achieve a convex curvature or a concave curvature for load balance for leak-proof sealing.

US Pat. No. 10,249,553

COOLING APPARATUS FOR A HEAT-GENERATING ELEMENT

Nissan Motor Co., Ltd., ...

1. A cooling apparatus for a heat-generating element, comprising:a heat sink having a main surface on which the heat-generating element is mounted and a heat radiation surface from which heat generated by the heat-generating element is radiated;
a cooling component having a recess and an interior gap,
the recess having an outer sidewall extending in a substantially perpendicular direction to the heat sink,
the interior gap being defined by an interior gap plane and an exterior gap plane, the interior gap plane being coplanar with the outer sidewall,
the cooling component and the heat sink facing and joining each other so that the recess forms a coolant passage in which a coolant flows; and
a sealing member provided between the heat sink and the cooling component so as to seal the coolant passage and separate an interior and exterior of the coolant passage, the sealing member having an internal side and an external side, the internal side being adjacent to the coolant passage, wherein
the sealing member is provided outside a plane which is coplanar with a first sidewall of the recess such that the internal side of the sealing member is coplanar with the interior gap plane,
a first distance is longer than a second distance with regard to a distance between facing surfaces of the heat sink and the cooling component near the sealing member,
the first distance is a distance between the facing surfaces within the interior gap between the sealing member and the first sidewall of the recess at an interior side of the coolant passage separated by the sealing member, the first distance having a minimal value at a point of the cooling component closest to the sealing member, and
the second distance is a distance between the facing surfaces at an exterior side of the coolant passage separated by the sealing member.

US Pat. No. 10,249,550

POWER MODULE WITH LEAD COMPONENT AND MANUFACTURING METHOD THEREOF

DELTA ELECTRONICS, INC., ...

1. A power module comprising:a carrier board; and
at least one lead component, stacked and disposed on the carrier board, and comprising:
at least one initial plane, wherein the initial plane includes at least one pad, and a vertical projection of the initial plane at least partially overlaps with the carrier board;
at least one first pin electrically connected to the carrier board, wherein the first pin is vertical to the initial plane;
at least one second pin electrically connected to the carrier board, wherein the second pin is vertical to the initial plane; and
at least one isolation gap disposed in the initial plane and located between the first pin and the second pin, wherein the initial plane is separated into a first plane and a second plane by the isolation gap, so as to electrically isolate the first pin and the second pin from each other.

US Pat. No. 10,249,549

CERAMIC CIRCUIT BOARD, ELECTRONIC CIRCUIT MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC CIRCUIT MODULE

MURATA MANUFACTURING CO.,...

1. A ceramic circuit board comprising: a ceramic insulator layer; at least one grounding pattern conductor, the at least one grounding pattern conductor containing a metal and an oxide of at least one metal element contained in the ceramic insulator layer, the at least one grounding pattern conductor including a pattern main portion disposed within the ceramic circuit board and an extended portion having a first end thereof connected to the pattern main portion and a second end thereof exposed at a side surface of the ceramic circuit board, and a first metal content of the extended portion is lower than a second metal content of the pattern main portion; a connection land disposed on a first surface of the ceramic board; and a grounding electrode disposed on a second surface of the ceramic board and connected to the grounding pattern conductor, wherein the first metal content of the extended portion is 30 to 60 percent by volume, and the second metal content of the pattern main portion is 80 percent by volume or more.

US Pat. No. 10,249,548

TEST CELL FOR LAMINATE AND METHOD

INTERNATIONAL BUSINESS MA...

1. A method of designing a laminate comprising:forming a test laminate that includes:
a plurality of buildup layers disposed on a core; and
one or more unit cells defined in the buildup layers, each unit cell including:
at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and
two or more dummy vias;
wherein the dummy vias are arranged in the unit cell at one of a plurality of distances from the test via;
subjecting test laminate to a stress;
testing at least one of the one more unit cells;
determining that at least one of the one or more unit cells is a failed cell; and
designing the laminate such that it does not include a via configuration from the failed cell in a location under a computer chip where the failed cell was located.

US Pat. No. 10,249,547

METHOD FOR USING A TEST WAFER BY FORMING MODIFIED LAYER USING A LASER BEAM AND OBSERVING DAMAGE AFTER FORMING MODIFIED LAYER

DISCO CORPORTATION, Toky...

1. A test wafer using method for using a test wafer including a test substrate and a metal foil formed on a front side of said test substrate, said test wafer using method comprising:a modified layer forming step of applying a laser beam having a transmission wavelength to said test substrate from a back side of said test wafer in the condition where a focal point of said laser beam is set inside said test substrate, thereby forming a modified layer inside said test substrate;
a damage detecting step of observing a front side of said test wafer after performing said modified layer forming step, thereby detecting damage to said metal foil; and
a processing conditions adjusting step of adjusting at least one of the laser processing conditions adopted in said modified layer forming step according to the result of detection of said damage obtained in said damage detecting step, said at least one of the laser processing conditions being selected from the group consisting of the wavelength of said laser beam, average power of said laser beam, repetition frequency of said laser beam, pulse width of said laser beam, numerical aperture of a focusing lens for focusing said laser beam, focal position of said laser beam, and relative feed speed of said test wafer.

US Pat. No. 10,249,546

REVERSE DECORATION FOR DEFECT DETECTION AMPLIFICATION

KLA-Tencor Corporation, ...

1. A method comprising:applying a layer of a material on a surface of a plurality of NAND stacks such that a bridge structure between two of the NAND stacks is covered with the layer, wherein the material has a refractive index different from that of the surface thereby amplifying detection of the bridge structure; and
removing a first portion of the layer from the plurality of NAND stacks, wherein a second portion of the layer remains disposed on the bridge structure after the removing.

US Pat. No. 10,249,543

FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:an n-type field effect transistor (nFET) gate stack arranged over a first channel region of the device, the n-type gate stack comprising:
a dielectric layer arranged on a substrate;
a first nitride layer arranged on the dielectric layer, the first nitride layer comprising TaN;
a niobium aluminum carbonitride stack arranged on the first nitride layer:
a scavenging layer arranged on the niobium aluminum carbonitride stack, the scavenging layer comprising NbAlC or TiAlC;
a second nitride layer arranged on the scavenging layer, the second nitride layer comprising TiN or TaN; and
a gate electrode arranged on the second nitride layer; and
a p-type field effect transistor (pFET) gate stack arranged over a second channel region of the device, the p-type gate stack comprising:
the dielectric layer arranged on the substrate;
the first nitride layer arranged on the dielectric layer;
the scavenging layer arranged on the first nitride layer;
the second nitride layer arranged on the scavenging layer; and
the gate electrode arranged on the second nitride layer.

US Pat. No. 10,249,542

SELF-ALIGNED DOPING IN SOURCE/DRAIN REGIONS FOR LOW CONTACT RESISTANCE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first semiconductor fin formed in a pFET region of a substrate and a second semiconductor fin formed in a nFET region of the substrate;
a first gate formed over a first channel region of the first semiconductor fin and a second gate formed over a first channel region of the second semiconductor fin;
a first doped region formed on the first semiconductor fin and adjacent to the first gate, the first doped region comprising p-type dopants doped silicon germanium (SiGe), said p-type dopants selected from the group consisting of gallium (Ga), boron (B), difluoroboron (BF2), and aluminum (Al); and
a second doped region formed on the second semiconductor fin and adjacent to the second gate, the second doped region embedded below a surface of the second semiconductor fin, wherein the first doped region comprises an upper doped part and a bottom doped part, the first and second doped regions being adjacent to the first semiconductor fin but not in the first semiconductor fin, wherein the upper doped part has more dopants than the bottom doped part.

US Pat. No. 10,249,541

FORMING A HYBRID CHANNEL NANOSHEET SEMICONDUCTOR STRUCTURE

International Business Ma...

1. A method for fabricating a nanosheet semiconductor structure, the method comprising:forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material;
wherein the first material is different than the second material, and
further wherein forming the first nanosheet FET structure and the second nanosheet FET structure comprises:
creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region; and
creating a second inner spacer formation within a second SiGe channel, wherein the second SiGe channel is comprised in a second channel region of a second FET region,
forming a first stack on the first FET region and a second stack on the second FET region, wherein the first stack comprises a first substrate, the one or more first Si nanosheets, and the one or more first SiGe nanosheets, and wherein the second stack comprises the second substrate, the one or more second Si nanosheets, and the one or more second SiGe nanosheets;
forming a first pad insulator on the first channel region and a second pad insulator on the second channel region;
forming a first gate on the first pad insulator and a second gate on the second pad insulator;
forming a first hard mask on the first gate and a second hard mask on the second gate;
forming a first spacer on the first channel region, the first gate, and the first hard mask, and a second spacer on the second channel region, the second gate, and the second hard mask, wherein each spacer comprises silicon mononitride (SiN); and
forming the first channel region from the first stack and the second channel region from the second stack.

US Pat. No. 10,249,539

NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first sacrificial layer between a first nanosheet and a second nanosheet;
forming a second sacrificial layer between a third nanosheet and a fourth nanosheet;
doping the first nanosheet;
forming another nanosheet over of the first nanosheet having been doped and the second nanosheet, subsequent to doping the first nanosheet;
wherein the first, second, another nanosheets are vertically stacked nanosheets in a first nanosheet stack and the third and fourth nanosheets are vertically stacked nanosheets in a second nanosheet stack;
concurrently removing the first sacrificial layer, the first nanosheet, and the second sacrificial layer, such that the first nanosheet is no longer present.

US Pat. No. 10,249,538

METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming, on a semiconductor substrate, a first lower source/drain region with a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region and a second lower source/drain region with a second semiconductor fin extending upward from a top surface of the second lower source/drain region,
wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and
wherein the first semiconductor fin and the second semiconductor fin are patterned from a monocrystalline epitaxial semiconductor layer and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively; and,
forming a first transistor with the first lower source/drain region and a second transistor with the second lower source/drain region.

US Pat. No. 10,249,537

METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a first fin of a first transistor in a substrate;
forming a second fin of a second transistor in the substrate;
disposing a first doped oxide layer comprising a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant;
disposing a mask over the first fin and removing the first doped oxide layer from the second fin;
removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first fin and directly onto the second fin, the second doped oxide layer comprising an n-type dopant or a p-type dopant that is different than the first dopant;
etching to recess the first doped oxide layer and the second doped oxide layer, leaving a layer of the first doped oxide layer on the first fin as a first doped oxide spacer and a layer of the second doped oxide layer on the second fin as a second doped oxide spacer;
annealing, after etching to recess, by a thermal process and under conditions sufficient to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin, and to drive the first dopant into the substrate beneath the first fin and the second dopant into the substrate beneath the second fin;
removing the first doped oxide spacer from the first fin and the second doped oxide spacer from the second fin;
depositing an oxide between the first fin and the second fin; and
forming a first gate on the first fin and a second gate on the second fin.

US Pat. No. 10,249,535

FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming two gates across and perpendicular to first and second pairs of fins on a substrate;
forming first and second pairs of raised source/drain (RSD) between the two gates on the first and second pairs of fins, respectively;
forming a planar self-aligned contact (SAC) cap on each of the two gates;
forming a metal layer over the substrate coplanar with an upper surface of the SACs;
forming an oxide layer over the substrate subsequent to forming the metal layer;
forming a nitride layer over the oxide layer;
patterning the oxide and nitride layers, forming first and second oxide and nitride stacks above the first and second pairs of RSD, respectively, the first and second oxide and nitride stacks formed perpendicular to the two gates and each having with a width equal to or less than an overall width of a pair of fins;
etching the metal layer proximate to the oxide and nitride stacks forming trench silicide (TS) structure upper portions above the first and second pairs of RSD, and forming the TS structure in the metal layer over and perpendicular to the fins, the TS structure having first and second upper portions over the first and second pairs of RSD, respectively, each upper portion having a width equal to or less than an overall width of a pair of fins;
forming first and second spacers on opposite sides of the first and second upper portions, respectively;
removing the metal layer between adjacent first and second spacers;
forming an interlayer dielectric (ILD) over the substrate; and
forming a source/drain contact (CA) on each upper portion and a gate contact (CB) on one of the two gates through the ILD.

US Pat. No. 10,249,533

METHOD AND STRUCTURE FOR FORMING A REPLACEMENT CONTACT

International Business Ma...

1. A method for manufacturing a semiconductor device, comprising:forming a plurality of gate structures spaced apart from each other on a fin;
forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures;
forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures;
forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion;
removing a portion of the OPL to expose the inorganic plug portion;
selectively removing the inorganic plug portion; and
forming a contact on the fin in place of the removed inorganic plug portion.

US Pat. No. 10,249,532

MODULATING THE MICROSTRUCTURE OF METALLIC INTERCONNECT STRUCTURES

International Business Ma...

1. An apparatus, comprising:a single platform semiconductor processing chamber comprising a first sub-chamber, a second sub-chamber, a third sub-chamber, and a fourth sub-chamber, which is configured to process a substrate comprising a dielectric layer disposed on an upper surface of a substrate, wherein the dielectric layer comprises an opening etched in a surface of the dielectric layer;
wherein the first sub-chamber is configured to deposit a layer of metallic material to fill the opening and cover the surface of the dielectric layer with the metallic material;
wherein the second sub-chamber is configured to perform a furnace anneal process to reflow the layer of metallic material;
wherein the third sub-chamber is configured to deposit a stress control layer on the layer of metallic material subsequent to the furnace anneal process; and
wherein the fourth sub-chamber comprises a programmable hot plate, wherein the fourth sub-chamber is configured to perform a controlled thermal anneal process using the programmable hot plate to modulate a microstructure of the layer of metallic material from a first microstructure to a second microstructure while the stress control layer is disposed on the layer of metallic material, wherein the programmable hot plate is programmed to perform a controlled thermal anneal cycle with active heating and active cooling stages.

US Pat. No. 10,249,531

METHOD FOR FORMING METAL WIRING

Toshiba Memory Corporatio...

1. A method for forming a metal wiring, comprising:forming a first insulating layer on a substrate;
forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer;
patterning the second insulating layer to form a mask pattern;
etching the first insulating layer by a wet etching method using the mask pattern as a mask;
forming selectively a catalyst layer in a region where the first insulating layer is etched; and
forming a metal layer on the catalyst layer by an electroless plating method.

US Pat. No. 10,249,530

INTERLAYER DIELECTRIC FILM IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a fin on a substrate;
a gate structure disposed over the fin;
a doped strained region adjacent to the gate structure; and
a high temperature (HT) doped interlayer dielectric (ILD) layer disposed over the doped strained region, the HT doped ILD layer comprising dopant materials with a non-linear doping density throughout the HT doped ILD layer.

US Pat. No. 10,249,528

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. An integrated circuit, comprising:a first insulation layer, wherein a first trench penetrates the first insulation layer;
a bottom plate partly disposed on the first insulation layer and partly disposed in the first trench;
a first patterned dielectric layer disposed on the bottom plate, wherein at least a part of the first patterned dielectric layer is disposed in the first trench;
a medium plate disposed on the first patterned dielectric layer, wherein at least a part of the medium plate is disposed in the first trench, and wherein the bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor;
a second patterned dielectric layer disposed on the medium plate; and
a top plate disposed on the second patterned dielectric layer, wherein the medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor, and the bottom plate is electrically connected with the top plate, wherein the top plate is electrically separated from the medium plate, and the bottom plate is electrically separated from the medium plate.

US Pat. No. 10,249,527

METHOD OF MANUFACTURING FLEXIBLE DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a flexible display device, comprising:providing a flexible substrate;
forming a first bonding layer on an entire surface of the flexible substrate;
patterning the first bonding layer to form a first bonding pattern by a photolithographic process, the first bonding pattern enclosing a display area without touching a boundary of the flexible substrate and being a multilayer;
forming a second bonding layer on an entire surface of a rigid substrate;
patterning the second bonding layer to form a second bonding pattern by a photolithographic process, the second bonding pattern corresponding to the first bonding pattern and being a multilayer;
bonding the first and second bonding patterns together to provide a bonding pattern between the flexible substrate and the rigid substrate such that at least a portion of the flexible substrate is in contact with the rigid substrate in the display area;
forming at least one display device on the display area of the flexible substrate; and
removing the bonding pattern by a cutting process performed so as to separate the flexible substrate having the display device thereon from the rigid substrate.

US Pat. No. 10,249,526

SUBSTRATE SUPPORT ASSEMBLY FOR HIGH TEMPERATURE PROCESSES

Applied Materials, Inc., ...

1. An electrostatic chuck comprising:a ceramic body having a top surface and a bottom surface;
one or more heating elements disposed in the ceramic body;
one or more electrodes disposed in the ceramic body; and
a plurality of adapter objects bonded to the bottom surface of the ceramic body by a metal bond, wherein collectively the plurality of adapter objects form a plurality of distributed over the bottom surface of the ceramic body at a plurality of different distances from a center of a circle defined by the bottom surface of the ceramic body, and wherein the plurality of openings comprise a first opening that is to couple to a fastener to secure a base plate against the bottom surface of the ceramic body.

US Pat. No. 10,249,525

DYNAMIC LEVELING PROCESS HEATER LIFT

APPLIED MATERIALS, INC., ...

1. A substrate support assembly, comprising:a support member that supports a pedestal having a substrate support surface;
a carrier plate attached to the support member; and
a positioning system comprising:
a base plate; and
two or more servo motor assemblies that each comprise a motor and a linear actuator, the servo motor assemblies each having a first end coupled to the base plate, wherein each of the linear actuators move the carrier plate in a direction that is non-parallel to the substrate supporting surface.

US Pat. No. 10,249,524

CASSETTE HOLDER ASSEMBLY FOR A SUBSTRATE CASSETTE AND HOLDING MEMBER FOR USE IN SUCH ASSEMBLY

ASM IP Holding B.V., Alm...

1. A cassette holder assembly for holding a cassette for storing at least one semiconductor material substrate in an interior space accessible from a front end of the cassette, the cassette holder assembly comprising:a base plate for receiving the cassette; and,
a right and a left holding member supported by the base plate to position the cassette on the right and left respectively seen from the front,
wherein the right and left holding members are substantially identical to each other,
wherein each of the holding members has at least two end surface to engage with the cassette to limit a position of the cassette in the front to the back direction substantially parallel to the base plate, the at least two end surfaces comprising at least one right end surface and at least one left end surface whereby the right end surface is located at the right of the holding member and the left end surface is located at the left of the holding member seen from the front, and
wherein the right end surface of the right holding member and the left end surface of the left holding member are arranged for engagement with the cassette.

US Pat. No. 10,249,523

OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC

KLA-Tencor Corporation, ...

1. A method for sorting wafers utilizing a slope of shape metric, comprising:receiving a plurality of wafers;
acquiring a set of wafer shape values from a surface of each wafer at a selected process level;
generating a set of residual slope shape metrics for each wafer by calculating a residual slope shape metric at each of a plurality of points of each wafer;
determining a neutral surface of each wafer in a chucked state;
calculating a neutral surface factor (NSF) for each wafer utilizing the determined neutral surface for each wafer and a plurality of positions associated with a plurality of patterns of each wafer;
determining a set of pattern placement error (PPE) residual values for each wafer, the PPE residual value for each point for each wafer being a product of at least the calculated NSF for each wafer, the residual slope shape metric for the point, and a thickness of the wafer;
determining one or more thresholds for the set of residual shape metrics suitable for maintaining the set of PPE residuals below one or more selected levels;
monitoring each of the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer; and
modifying one or more wafer fabrication processes, responsive to the monitoring of each of the plurality of wafers, in order to maintain the generated set of residual slope shape metrics for each wafer below the one or more thresholds.

US Pat. No. 10,249,522

IN-SITU TEMPERATURE MEASUREMENT IN A NOISY ENVIRONMENT

APPLIED MATERIALS, INC., ...

1. A lift pin for a semiconductor processing chamber, the lift pin comprising:a light pipe disposed within a body of the lift pin; and
a cover over an end of the light pipe and configured to contact a substrate to transmit thermal energy from the substrate to the light pipe, wherein the cover is a thermally conductive material.

US Pat. No. 10,249,520

TRANSFER PRINTING USING ULTRASOUND

INNOVASONIC, Inc., Dubli...

1. A method of transferring an object from a donor substrate surface to a receiving substrate surface comprising:providing a transfer device having a one or more ultrasonic transducers and an elastomeric material disposed over said transducers;
providing a donor substrate having a donor surface, said donor surface having at least one or more objects;
contacting at least a portion of said transfer device with at least a portion of said donor substrate, said portion having an object;
separating said transfer device from a donor surface at a separation rate required for transfer of said object from the donor substrate surface to the transfer device, thereby forming said transfer surface having said object deposited thereon;
contacting at least a portion of said object disposed on said transfer surface with said receiving surface of said receiving substrate,
directing a pulse of ultrasonic energy from one or more ultrasonic transducers located in close vicinity of said object, and separating said transfer surface from said object, thereby transferring said object to said receiving substrate.

US Pat. No. 10,249,519

LIGHT-IRRADIATION HEAT TREATMENT APPARATUS

SCREEN Holdings Co., Ltd....

1. A heat treatment apparatus for heating a disk-shaped substrate by irradiating the substrate with light, comprising:a chamber that houses a substrate;
a holder that holds said substrate in said chamber;
a light irradiation part in which a plurality of rod-shaped lamps are arranged in a light source region that is larger than a major surface of said substrate held by said holder and that faces the major surface;
a cylindrical louver that is provided between said light irradiation part and said holder, with a central axis of said louver passing through a center of said substrate, and that is impervious to light emitted from said light irradiation part, and an outer diameter of said louver being smaller than said light source region; and
a light-shielding member that is provided between said light irradiation part and said holder and that is impervious to the light emitted from said light irradiation part,
wherein said light-shielding member has a cut-out portion that allows light to reach a region of said substrate that is shielded from the light emitted from said light irradiation part by said louver.

US Pat. No. 10,249,517

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus for processing a substrate, comprising:a substrate holder for holding a substrate in a horizontal position;
an opposing member that opposes an upper surface of said substrate and has an opposing-member opening in a central part;
an opposing-member moving mechanism for holding said opposing member and moving said opposing member relative to said substrate holder in an up-down direction between a first position and a second position that is below said first position;
a substrate rotation mechanism for rotating said substrate along with said substrate holder about a central axis pointing in said up-down direction;
a processing liquid nozzle for supplying a processing liquid to said upper surface of said substrate through said opposing-member opening; and
a gas supply part for supplying a treatment atmospheric gas to a space between said opposing member and said substrate,
wherein said opposing member includes:
an opposing-member body that opposes said upper surface of said substrate and has said opposing-member opening in the central part;
an opposing-member tubular part that has a tubular shape and protrudes upward from a periphery of said opposing-member opening of said opposing-member body and in which said processing liquid nozzle is inserted;
an opposing-member flange part that annularly extends radially outward from an upper end of said opposing-member tubular part and is held by said opposing-member moving mechanism; and
a first uneven part in which a recessed portion and a raised portion are alternately disposed concentrically on an upper surface of said opposing-member flange part,
said opposing-member moving mechanism includes:
a holder lower part that opposes a lower surface of said opposing-member flange part in said up-down direction;
a holder upper part that opposes said upper surface of said opposing-member flange part in said up-down direction; and
a second uneven part in which a recessed portion and a raised portion are alternately disposed concentrically on a lower surface of said holder upper part,
in a state in which said opposing member is located at said first position, said opposing-member flange part is supported from below by said holder lower part, and said opposing member is held by said opposing-member moving mechanism and spaced above said substrate holder, and
in a state in which said opposing member is located at said second position, said opposing member is spaced from said opposing-member moving mechanism, is held by said substrate holder, and is rotatable along with said substrate holder by said substrate rotation mechanism, a labyrinth is formed as a result of the raised portion of one of said first uneven part and said second uneven part being disposed within the recessed portion of the other of said first uneven part and said second uneven part with a gap therebetween, and a seal gas is supplied to said labyrinth to seal a nozzle gap from a space located on the radially outer side of said labyrinth, said nozzle gap being a space between said processing liquid nozzle and said opposing-member tubular part.

US Pat. No. 10,249,516

UNDERFILL DISPENSING USING FUNNELS

International Business Ma...

1. A method for underfilling an array of objects on a substrate, comprising:forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate; and
curing the void-free layer of underfill material to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

US Pat. No. 10,249,515

ELECTRONIC DEVICE PACKAGE

Intel Corporation, Santa...

1. An electronic device package, comprising:a substrate;
an electronic component disposed on the substrate and electrically coupled to the substrate; and
an underfill material disposed at least partially between the electronic component and the substrate, wherein a lateral portion of the underfill material comprises an exposed lateral surface extending away from the substrate and intersecting a meniscus surface extending between the lateral surface and the electronic component, wherein a height of the lateral surface from the substrate is greater than a length of the meniscus surface, and wherein the lateral surface comprises an irregular surface that has a concavity from an upper surface of the substrate.

US Pat. No. 10,249,512

TUNABLE TIOXNY HARDMASK FOR MULTILAYER PATTERNING

INTERNATIONAL BUSINESS MA...

1. A multilayer lithographic structure comprisingan organic planarizing layer;
a titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride layer has an extinction coefficient less than 1.0 over a wavelength range from 400 nm to 800 nm and is configured to have an etch rate greater than 2 nm per minute in a wet etch solution comprising ammonium hydroxide, hydrogen peroxide and water at a temperature of 20° C.; and
a photosensitive resist layer on the titanium oxynitride layer.

US Pat. No. 10,249,511

CERAMIC SHOWERHEAD INCLUDING CENTRAL GAS INJECTOR FOR TUNABLE CONVECTIVE-DIFFUSIVE GAS FLOW IN SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS

LAM RESEARCH CORPORATION,...

1. An inductively coupled plasma processing apparatus comprising:a vacuum chamber;
a vacuum source adapted to exhaust the vacuum chamber;
a substrate support comprising a lower electrode on which a single semiconductor substrate is supported in an interior of the vacuum chamber;
a ceramic showerhead which forms an upper wall of the vacuum chamber wherein the ceramic showerhead includes a gas plenum in fluid communication with a plurality of showerhead gas outlets in a plasma exposed surface thereof for supplying a process gas as a diffusive gas flow to the interior of the vacuum chamber, a central opening in the ceramic showerhead that extends an entire thickness of the ceramic showerhead and the ceramic showerhead including a lower vacuum sealing surface which surrounds the plasma exposed surface and forms a vacuum seal with a vacuum sealing surface of the vacuum chamber;
a central gas injector disposed in the central opening of the ceramic showerhead, wherein the central gas injector includes one or more gas injector outlets, in a surface thereof that is exposed inside the vacuum chamber, for supplying the process gas as a convective gas flow to the interior of the vacuum chamber at least in a direction towards a center of the semiconductor substrate, wherein
the one or more gas injector outlets include a plurality of central gas outlets, wherein the plurality of central gas outlets are arranged to supply the process gas as the convective gas flow directly from the central gas injector into the vacuum chamber without passing through the gas plenum of the ceramic showerhead, and
the one or more gas injector outlets include a plurality of radial gas outlets arranged radially outward of the plurality of central gas outlets, wherein the plurality of radial gas outlets are arranged to supply the process gas as the diffusive gas flow radially outward from the central gas injector into the gas plenum of the ceramic showerhead and through the plurality of showerhead gas outlets;
an RF energy source which inductively couples RF energy through the ceramic showerhead and into the vacuum chamber to energize the process gas into a plasma state to process the semiconductor substrate; and
a control system configured to (i) control supply of the process gas as the convective gas flow through the central gas outlets via a first gas line at a first flow rate and (ii) control supply of, independently of the convective gas flow, the process gas as the diffusive gas flow through the showerhead gas outlets via a second gas line at a second flow rate, wherein the convective gas flow and the diffusive gas flow are supplied simultaneously, and wherein, to control the supply of the convective gas flow and the diffusive gas flow, the control system is further configured to select and control a pressure within the vacuum chamber, the first flow rate, and the second flow rate based on a desired eddy current above the semiconductor substrate, wherein, to achieve the desired eddy current, the control system is configured to independently control the first flow rate and the second flow rate.

US Pat. No. 10,249,508

METHOD FOR PREVENTING EXCESSIVE ETCHING OF EDGES OF AN INSULATOR LAYER

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:forming a first semiconductor layer on a semiconductor substrate;
forming a first insulator layer on the first semiconductor layer exposing an edge portion of the first semiconductor layer;
forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer;
forming a second insulator layer as a spacer on the exposed portion of the first insulator layer;
performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer.

US Pat. No. 10,249,507

METHODS FOR SELECTIVE ETCHING OF A SILICON MATERIAL

Applied Materials, Inc., ...

1. A method for etching features in a silicon material, the method comprising:performing a remote plasma process in a processing chamber formed from an etching gas mixture including chlorine containing gas to remove a silicon material disposed on a substrate, wherein the remote plasma process is configured to generate a remote plasma externally from an interior volume defined in the processing chamber without applying a RF source power to the processing chamber.

US Pat. No. 10,249,504

ETCHING AND MECHANICAL GRINDING FILM-LAYERS STACKED ON A SEMICONDUCTOR SUBSTRATE

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:wet-etching a first film layer of a plurality of film layers stacked on a first side of a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, wherein the first film layer is an outermost film layer stacked on the semiconductor substrate;
wet-etching a second film layer of the plurality of film layers using a second chemical; and
using a mechanical grinding wheel to grind the semiconductor substrate from the first side to reduce a thickness of the semiconductor substrate.

US Pat. No. 10,249,501

SINGLE PROCESS FOR LINER AND METAL FILL

International Business Ma...

1. A semiconductor structure comprising a gate structure, the gate structure comprising:a gate dielectric located along inner sidewalls of a gate spacer and a top surface and sidewalls of a channel region of a semiconductor fin located over a substrate;
a workfunction metal liner located on, and in direct physical contact with, the gate dielectric;
a first metal liner located on, and in direct physical contact with, the workfunction metal liner;
a second metal liner located on, and in direct physical contact with, the first metal liner; and
a metal gate electrode located on, and in direct physical contact, with the second metal liner, wherein the metal gate electrode is composed entirely of an alloy selected from the group consisting of MgAl, MgTi, MgV and AlV, the first metal liner is composed entirely of a carbide of the alloy that forms the metal gate electrode and the second metal liner is composed entirely of a nitride of the alloy that forms the metal gate electrode.

US Pat. No. 10,249,499

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A THIN SEMICONDUCTOR WAFER

ABB Schweiz AG, Baden (C...

1. A method for manufacturing a vertical power semiconductor device, wherein the method comprises the following steps:(a) providing a semiconductor wafer having a first main side and a second main side opposite to the first main side;
(b) applying a first impurity onto the first main side;
(c) forming a first oxide layer on at least the first main side of the semiconductor wafer;
(d) after step (c) bonding a carrier wafer to the first oxide layer on the first main side of the semiconductor wafer;
(e) after the bonding step (d) front-end-of-line processing on the second main side of the semiconductor wafer;
(f) after the front-end-of-line processing step (e) at least partially removing the carrier wafer and the first oxide layer on the first main side of the semiconductor wafer; and
(g) after the removing step (f) forming a back metallization layer on the first main side of the semiconductor wafer to form an Ohmic contact to the semiconductor wafer,
wherein
in step (c) partially doping the first oxide layer formed on the first main side of the semiconductor wafer with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer,
in step (e) diffusing the second impurity from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing,
in step (f) completely removing the carrier wafer and the first oxide layer on the first main side of the semiconductor wafer.

US Pat. No. 10,249,497

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device comprising:a silicon carbide semiconductor base of a first conductivity type;
a gate insulating film provided on a front surface of the silicon carbide semiconductor substrate and including any one or a plurality of an oxide film, a nitride film, and an oxynitride film; and
a gate electrode containing poly-silicon and provided on the gate insulating film, wherein
the gate insulating film has an interface state terminated by hydrogen or hydroxyl groups, wherein the hydrogen or the hydroxyl groups terminating the interface state is replaced with fluorine, and
a concentration of fluorine in the silicon carbide semiconductor device has a first peak and a second peak,
the first peak is in the gate electrode and is equal to or lower than 1×1018 atoms/cm3 and the second peak is in the gate insulating film and is equal to or higher than 1×1019 atoms/cm3.

US Pat. No. 10,249,496

NARROWED FEATURE FORMATION DURING A DOUBLE PATTERNING PROCESS

GLOBALFOUNDRIES Inc., Gr...

1. An interconnect structure comprising:a first interconnect having a first width and a cut extending through the first interconnect across the first width; and
a second interconnect having a first section with the first width, a second section with the first width, and a third section arranged between the first section and the second section,
wherein the third section of the second interconnect has a second width that is less than the first width.

US Pat. No. 10,249,495

DIAMOND LIKE CARBON LAYER FORMED BY AN ELECTRON BEAM PLASMA PROCESS

Applied Materials, Inc., ...

1. A method of forming a diamond like carbon layer, comprising:generating an electron beam plasma above a surface of a substrate disposed in a processing chamber, generating the electron beam plasma comprising:
applying a first RF source power to an electrode disposed in the processing chamber; and
bombarding the electrode to provide secondary electrons and a secondary electron beam flux to the surface of the substrate; and
forming a diamond like carbon layer on the surface of the substrate disposed in the processing chamber.

US Pat. No. 10,249,494

FREE-STANDING SUBSTRATE, FUNCTION ELEMENT AND METHOD FOR PRODUCING SAME

NGK INSULATORS, LTD., Na...

1. A self-supporting substrate comprising:a first nitride layer grown by a hydride vapor deposition method or an ammonothermal method and comprising a nitride of one or more elements selected from the group consisting of gallium, aluminum and indium; and
a second nitride layer grown by a sodium flux method on said first nitride layer and comprising a nitride of one or more elements selected from the group consisting of gallium, aluminum and indium;
wherein said first nitride layer comprises a plurality of single crystal grains arranged therein and extending between a pair of main faces of said first nitride layer;
said second nitride layer comprises a plurality of single crystal grains arranged therein and extending between a pair of main faces of said second nitride layer; and
said first nitride layer has a thickness larger than a thickness of said second nitride layer.

US Pat. No. 10,249,491

METHOD AND APPARATUS FOR FORMING DEVICE QUALITY GALLIUM NITRIDE LAYERS ON SILICON SUBSTRATES

Ultratech, Inc., San Jos...

1. A method comprising:supporting a silicon substrate inside a deposition chamber, the silicon substrate including a silicon substrate coating surface;
applying an aluminum nitride nucleation layer onto the silicon substrate coating surface using a first atomic layer deposition method;
applying a transition layer over the aluminum nitride nucleation layer using a second atomic layer deposition method, wherein applying the transition layer comprises applying a plurality of different material layers wherein each of the plurality of different material layers comprises an AlxGa1-xN compound and wherein each of the plurality of different AlxGa1-xN compounds is applied by a different atomic layer deposition method; and
applying a gallium nitride device layer over the transition layer using a third atomic layer deposition method.

US Pat. No. 10,249,490

NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:an insulating layer having a trench therein;
a semiconductor fin having a lower fin portion in the trench and an upper fin portion extending above the insulating layer, wherein the lower fin portion comprises a first semiconductor material, the upper fin portion having a top and sidewalls and comprising a second semiconductor material, and wherein the second semiconductor material meets the first semiconductor material at a non-planar interface; and
a third semiconductor material directly on the top and sidewalls of the upper fin portion and on a portion of the insulating layer, wherein the second semiconductor material is different than the first and third semiconductor materials.

US Pat. No. 10,249,489

USE OF SILYL BRIDGED ALKYL COMPOUNDS FOR DENSE OSG FILMS

VERSUM MATERIALS US, LLC,...

1. A chemical vapor deposition method for depositing an organosilicate film on at least a part of a substrate, the process comprising the steps of:providing a substrate within a vacuum chamber;
introducing into the vacuum chamber a gaseous structure forming composition comprising at least one organosilicon precursor selected from the group consisting of Formula (I) and Formula (II):
wherein,R1, R2, R3, R4, R5, and R6 are each independently selected from the group consisting of —CH3 and —OR8, wherein R8 is a C1-C4 alkyl group;
R7 is H or —CH3;
x is 1 or 2; and
n is 1, 2, 3, or 4, wherein at least one R7 is —CH3 when n is 1;
applying energy to the gaseous structure forming composition in the vacuum chamber to induce reaction of the at least one organosilicon precursor to deposit a film on at least a portion of the substrate.

US Pat. No. 10,249,487

SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate processing method comprising:a substrate holding step of holding a substrate in a horizontal orientation by means of a substrate holding unit;
a liquid film forming step of supplying a processing liquid to an upper surface of the substrate held by the substrate holding unit to form a liquid film;
an upper surface covering step of discharging, above the liquid film formed on the upper surface of the substrate held by the substrate holding unit, an inert gas radially and parallel to the upper surface of the substrate from a center toward a peripheral edge of the substrate to form an inert gas stream flowing parallel to the upper surface of the substrate and covering the upper surface of the substrate; and
a liquid film removing step of discharging an inert gas toward the upper surface of the substrate to remove the liquid film, formed by the liquid film forming step, from the upper surface of the substrate during a time period in which the upper surface covering step is performed;
wherein the liquid film removing step includes
a perpendicular gas discharging step of rectilinearly discharging the inert gas perpendicular to the upper surface toward the center of the substrate so as to form a hole at a center of the liquid film and to spread the hole, and
an oblique gas discharging step of radially discharging the inert gas in an outwardly-directed oblique direction with respect to the upper surface of the substrate toward an intermediate position between the center and the peripheral edge of the substrate upper surface as a discharge target position, thereby generating an outwardly-directed oblique direction inert gas flow that further spreads the hole of the liquid film to push away the liquid film to the outer side of the substrate,
wherein, in the oblique gas discharging step, the inert gas is discharged toward a periphery of a central axis which extends perpendicular to the upper surface of the substrate, along a conical surface that is inclined with respect to the axis, to form the outwardly-directed oblique direction inert gas discharge having a conical profile that is obliquely incident on the upper surface of the substrate.

US Pat. No. 10,249,484

ELECTROSPRAY IONIZATION INTERFACE TO HIGH PRESSURE MASS SPECTROMETRY AND RELATED METHODS

The University of North C...

1. A method of analyzing a sample, comprising:providing a mass spectrometer comprising a vacuum chamber, a mass analyzer positioned in the vacuum chamber, and a sealing member positioned in a wall of the vacuum chamber in proximity to an entrance aperture;
positioning an electrospray ionization (ESI) device so that a portion of at least one emitter of the ESI device extends through the sealing member and into the vacuum chamber;
electrospraying ions of the sample from the ESI device directly into the vacuum chamber, wherein a gas pressure in the vacuum chamber is 50 mTorr or greater;
ejecting the ions from the mass analyzer;
detecting electrical signals corresponding to the ejected ions using at least one detector; and
generating mass spectral information based on the detected electrical signals to determine information about the sample.

US Pat. No. 10,249,483

ULTRA-COMPACT MASS ANALYSIS DEVICE AND ULTRA-COMPACT PARTICLE ACCELERATION DEVICE

1. A mass spectroscope, comprising:a main substrate having a first face and a second face,
a first substrate adhered to the first face of the main substrate,
a second substrate adhered to the second face of the main substrate,
a plurality of cavities penetrating from the first face of the main substrate to the second face of the main substrate,
at least one of the cavities penetrating from the first face of the main substrate to the second face of the main substrate is a mass spectroscopic cavity, and
a voltage or magnetic field generator configured to make orbits of charged particles change in the mass spectroscopic cavity for performing mass analysis.

US Pat. No. 10,249,482

TIME OF FLIGHT MASS SPECTROMETER

KRATOS ANALYTICAL LIMITED...

1. A time of flight mass spectrometer, comprising:an ion source including:
a first electrode, wherein the first electrode includes a sample plate for carrying a sample; and
a second electrode that has an aperture formed therein and is spaced apart from the first electrode;
a sample plate carrier on which the sample is mounted; and
a mechanism configured to translate the sample plate carrier laterally with respect to an ion optic axis so as to laterally offset the sample plate carrier with respect to the ion optic axis, wherein the ion optic axis extends between the first and second electrodes and through the aperture in the second electrode;
wherein the ion source is configured to apply voltages to the first and second electrodes to produce an extraction electric field in an extraction region between the first and second electrodes so as to extract ions from the extraction region through the aperture in the second electrode when the mass spectrometer is in use;
wherein a shield is formed on the first electrode and/or second electrode, wherein the shield is a raised element formed on a surface of one of the first and second electrodes that faces the other of the first and second electrodes so that the shield extends towards the other of the first and second electrodes, wherein the shield is configured to inhibit an electric field formed between edges of the first and second electrodes from penetrating into the extraction region between the first and second electrodes so as to inhibit changes in the extraction electric field in the extraction region when the sample plate is laterally offset with respect to the ion optic axis when the mass spectrometer is in use.

US Pat. No. 10,249,481

SYSTEM AND METHOD FOR FUSING CHEMICAL DETECTORS

Leidos, Inc., Reston, VA...

1. A chemical agent detector comprising:an ionization chamber including dual inlet ports and at least one ion source for generating unfiltered positive and negative ions from at least one sample received therein from a first direction, the ionization chamber further including a first gasket and first bracket on a first side thereof and a second gasket and a second bracket on a second side thereof for attaching to a first and second ion mobility spectrometry cell;
wherein the first ion mobility spectrometry cell is integrated with the ionization chamber via the first gasket and the first bracket for receiving at least a first portion of the unfiltered positive ions emanating therefrom in a second direction;
further wherein the second ion mobility spectrometry cell is integrated with the ionization chamber via the second gasket and the second bracket for receiving at least a first portion of the unfiltered negative ions emanating therefrom in a third direction;
a differential ion mobility spectrometry cell integrated with the ionization chamber for receiving at least a second portion of the unfiltered positive ions and at least a second portion of the unfiltered negative ions emanating therefrom in the first direction,
wherein the dual inlet ports for the sample are located on a front face of the ionization chamber and the differential ion mobility spectrometry cell is located on a back face of the ionization chamber opposite the front face and the first and second ion mobility spectrometry cells are on opposite sides of the ionization chamber and separated thereby, and further wherein the at least a first portion of the unfiltered positive ions and the at least a first portion of the unfiltered negative ions pass directly to the first ion mobility spectrometry cell and the second ion mobility spectrometry cell from the ionization chamber; and
a processor for separately receiving first detection data from the first ion mobility spectrometry cell, second detection data from the second ion mobility spectrometry cell, and third detection data from the differential ion mobility spectrometry cell and processing the first, second and third detection data to determine presence of one or more chemical agents in the sample; and
further wherein an exit port to the differential ion mobility spectrometry cell further includes at least one side port for allowing a first portion of a drift gas to exit prior to entering the differential ion mobility spectrometry cell.

US Pat. No. 10,249,480

TANDEM MASS SPECTROMETRY DATA PROCESSING SYSTEM

SHIMADZU CORPORATION, Ky...

1. A tandem mass spectrometry data processing system for processing MSn spectrum data obtained by performing a mass spectrometry for product ions obtained by dissociating ions collectively selected as precursor ions, the precursor ions originating from a plurality of different compounds and having mass-to-charge ratios within a predetermined mass-to-charge-ratio width, the system comprising:a) a compound database in which at least information on standard MSn spectra related to known compounds is stored;
b) a peak information collector for collecting peak information from an MSn spectrum created based on the MSn spectrum data obtained by an actual measurement;
c) a database searcher for finding a candidate compound for each of the ions of the plurality of compounds selected as the precursor ions, by performing a database search over the compound database based on a mass-to-charge-ratio value of the ion concerned and the peak information collected from an MSn spectrum by the peak information collector; and
d) a similarity calculator for retrieving, from the compound database, the standard MSn spectra for the candidate compounds selected for each of the ions of the plurality of compounds, for assuming a combination of the candidate compounds for the plurality of compounds, for creating a virtual MSn spectrum in which the standard MSn spectra corresponding to the candidate compounds included in the assumed combination are integrated with each other, and for calculating a degree of similarity between the virtual MSn spectrum and the measured MSn spectrum for each combination of the candidate compounds,
wherein the plurality of compounds is identifiable using the degree of similarity obtained by the similarity calculator.

US Pat. No. 10,249,479

MAGNET CONFIGURATIONS FOR RADIAL UNIFORMITY TUNING OF ICP PLASMAS

Applied Materials, Inc., ...

1. A plasma processing apparatus, comprising:a plasma source assembly, wherein the plasma source assembly comprises:
a first coil;
a second coil surrounding the first coil, the first coil and the second coil being electrically coupled in parallel;
a first magnetic device disposed outside the first coil and inside the second coil;
a third coil surrounding the second and first coils;
a second magnetic device disposed outside of the second coil and inside of the third coil; and
a permanent magnet distinct from the first and second magnetic devices disposed at a center of the first and second coils.

US Pat. No. 10,249,478

SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A substrate processing apparatus, comprising:a chamber including a process space for performing a process on a substrate by a gas introduced thereto and an exhaust space for evacuating the gas in the process space, the exhaust space being arranged outside the process space, the chamber including a side wall with a through hole having a first diameter;
a pipe provided outside the chamber and connected to the side wall of the chamber so as to be in communication with the through hole of the chamber, the pipe being connected to a pressure gage outside the chamber;
a shield member for separating the process space from the exhaust space provided in a vicinity of the side wall of the chamber, an upper part of the exhaust space extending between the shield member and the side wall of the chamber, the shield member including a through hole and a first step portion formed around the thorough hole of the shield member; and
a hollow relay member connecting the through hole of the chamber to the through hole of the shield member to be in communication with the pipe connected to the pressure gauge outside the chamber and the process space, the hollow relay member including a cylindrical portion having a second diameter that is smaller than the first diameter of the through hole of the chamber and a second step portion having a third diameter that is larger than a diameter of the through hole of the shield member, the second diameter being an outer diameter of the cylindrical portion and the third diameter being an outer diameter of the second step portion, the cylindrical portion being provided in the through hole of the chamber, the hollow relay member forming a first flow passage therein that is in communication with the process space and fixed by the shield member, a gap between an outer surface of the cylindrical portion and an inner surface of the through hole of the chamber forming a second flow passage that is in communication with the exhaust space such that the cylindrical portion is not in contact with the inner surface of the thorough hole of the chamber, the second step portion of the relay member being engaged with the first step portion of the shield member.

US Pat. No. 10,249,475

COOLING MECHANISM UTLIZED IN A PLASMA REACTOR WITH ENHANCED TEMPERATURE REGULATION

Applied Materials, Inc., ...

1. A cooling mechanism for a processing chamber comprising:a processing chamber;
a coil antenna enclosure disposed above the processing chamber;
perforations formed through a bottom portion of the coil antenna enclosure;
a coil antenna assembly disposed in the coil antenna enclosure;
a plurality of air circulating elements disposed in the coil antenna enclosure adjacent to the coil antenna assembly; and
a baffle plate disposed in the coil antenna enclosure below and adjacent to the coil antenna assembly, the baffle plate disposed between the coil antenna assembly and the perforations, the baffle plate has a central opening that allows fluid communication from the perforations disposed below the baffle plate to the coil antenna assembly disposed above the baffle plate, wherein the baffle plate has a circular body defining a horizontal plane substantially parallel to a horizontal surface of a substrate support disposed in the processing chamber.

US Pat. No. 10,249,474

CHARGED PARTICLE BEAM DEVICE

Hitachi High-Technologies...

1. A charged particle beam device, comprising:a deflector which scans a sample with a charged particle beam emitted from a charged particle source;
an image memory which stores signals obtained by a scan of the charged particle beam for the sample; and
a control device which controls the deflector,
wherein the control device controls the deflector so that scan for sequentially irradiating the charged particle beam for generating an image at a sample position corresponding to each pixel of the image stored in the image memory is performed so that an interval between individual pixels is changed, thereby generating a plurality of images corresponding to a changed interval between the individual pixels, and thus determines a deflection condition of the deflector based on evaluation of the plurality of images.

US Pat. No. 10,249,471

COMPOSITE CHARGED PARTICLE BEAM APPARATUS AND CONTROL METHOD THEREOF

Hitachi High-Technologies...

1. A composite charged particle beam apparatus comprising:a CFE-SEM that uses a CFE electron source for irradiating a sample with an electron beam;
a FIB device that irradiates the sample with an ion beam; and
a controller configured to control an automatic sequence for repeatedly performing sample observation using the CFE-SEM and sample processing using the FIB device,
wherein, in the automatic sequence, during each sample processing using the FIB device, or during each transition time between the sample observation using the CFE-SEM and the sample processing using the FIB device, the controller is further configured to perform flushing while an extraction voltage is applied to the CFE electron source.

US Pat. No. 10,249,470

SYMMETRICAL INDUCTIVELY COUPLED PLASMA SOURCE WITH COAXIAL RF FEED AND COAXIAL SHIELDING

Applied Materials, Inc., ...

1. A plasma reactor comprising:a window assembly;
concentric inner and outer coil antennas adjacent said window assembly;
inner and outer current distributors each comprising an inverted bowl-shaped conductor coupled to said inner and outer coil antennas, respectively, and wherein said outer current distributor concentrically surrounds said inner current distributor, and wherein each inverted bowl-shaped conductor comprises an axially symmetric hollow body comprising a bottom edge facing and terminated at a supply end of the corresponding one of said inner and outer coil antennas;
a ceiling plate overlying said window assembly and first and second RF power terminals at said ceiling plate;
a plenum plate between said ceiling plate and said inner and outer current distributors, the plenum plate comprising a central opening, the central opening being coaxial with said inner and outer coil antennas;
first and second axial RF power feeds connected at respective connections between respective ones of said first and second RF power terminals and respective ones of said inner and outer current distributors, wherein said first axial RF power feed coincides with an axis of symmetry of said coil antennas, the respective connection corresponding to said inner current distributor being located on said axis of symmetry, and wherein said second axial RF power feed extends downwardly through said central opening with a gap between said plenum plate and said second axial RF power feed, and said second axial RF power feed includes outwardly extending portions that project past an edge of said central opening and axially extending portions projecting downward from the outwardly extending portions to contact a top of the inverted bowl-shaped conductor of said outer current distributor.

US Pat. No. 10,249,469

FABRICATION METHODS AND MODAL STIFFINING FOR NON-FLAT SINGLE/MULTI-PIECE EMITTER

GENERAL ELECTRIC COMPANY,...

1. An electron emitter assembly comprising:a plurality of thermionic anisotropic polycrystalline X-ray emitter structures comprising one or more non-removable modal stiffness structures connecting the plurality of thermionic anisotropic polycrystalline X-ray emitter structures; and
a removable structure connected to, and fixing a positional relationship among, individual ones of the plurality of anisotropic polycrystalline X-ray emitter structures.

US Pat. No. 10,249,468

HIGH-POWERED MAGNETRON

KOREA ELECTROTECHNOLOGY R...

1. A high-powered magnetron comprising:a diode including a cathode and an anode; and
a tuner unit varying an electric field in the diode,
wherein the tuner unit includes a plurality of tuners,
wherein a frequency and power of the high-powered magnetron are determined by a gap between internal structures of at least one of the plurality of tuners,
wherein at least one of the plurality of tuners adjust the gap between internal structures during an operation of the high-powered magnetron, and
wherein a frequency variation range by the plurality of tuners is greater than a frequency variation range by a single tuner.

US Pat. No. 10,249,467

LASER PLASMA LENS

ECOLE POLYTECHNIQUE, Pal...

11. A method for emitting a bunch of collimated or focused relativistic electrons, comprising:emitting a laser pulse focused in a first gas cloud to create therein a wave of electrical and magnetic fields for accelerating electrons present in the first gas cloud and thus form a bunch of relativistic electrons which is propagated out of the first gas cloud, the laser pulse also being focused in a second gas cloud remote from the first gas cloud to create therein a wave of focusing electrical and magnetic fields, the first gas cloud being remote from the second gas cloud; and
subjecting the bunch of relativistic electrons to the wave of focusing electrical and magnetic fields, wherein
the width of the second gas lies between 10 ?m and 2 mm, and
the bunch of relativistic electrons is propagated in a vacuum in a space between the first and second gas clouds.

US Pat. No. 10,249,466

FUSE ARC GAS BAFFLE WITH ARC RESISTANT FUSE ASSEMBLY

EATON INTELLIGENT POWER L...

1. A baffle assembly for an electrical apparatus, said electrical apparatus including a number of electrical components and a conductor assembly, said electrical components including a number of terminals, said electrical component terminals disposed in a plurality of aligned sets, said conductor assembly including a number of conductors, said conductors extending laterally over a number of aligned sets, said baffle assembly comprising:a number of generally planar sidewalls, each said sidewall including a number of edge surfaces;
said sidewalls disposed in a spaced, generally parallel configuration defining a number of channels;
at least two of said sidewall edge surfaces extending in generally different directions; and
a number of end walls, each said end wall sealingly coupled to one said sidewall edge surface.

US Pat. No. 10,249,464

MODULAR CIRCUIT BREAKER AND METHOD OF ASSEMBLING

EATON INTELLIGENT POWER L...

1. A primary assembly for use with a module assembly in a modular circuit breaker, the primary assembly comprising:a primary housing having a first end structured to engage the module assembly;
a pair of separable contacts disposed in the primary housing;
a first terminal conductor disposed in or on the primary housing and structured to engage a line terminal, the first terminal conductor being electrically connected to one of the separable contacts;
a conductive tab electrically connected to another one of the separable contacts, the conductive tab extending outward from the first end of the primary housing;
an operating mechanism disposed in the primary housing for selectively opening and closing the separable contacts; and
a trip mechanism disposed in the primary housing cooperative with the operating mechanism to trip open the separable contacts.

US Pat. No. 10,249,462

POWER RELAY FOR A VEHICLE

1. A power relay for a vehicle, the power relay comprising:a housing formed from a connection socket and a housing pot that is disposed on said connection socket, said connection socket having a receiving arrangement and connecting conductors; and
two connection bolts inserted into said connection socket so as to make contact with a load current circuit, said connection bolts each having a screw with a threaded shaft and a screw head, each of said connection bolts having said screw head disposed loosely in said receiving arrangement of said connection socket so that said threaded shaft protrudes outwards from said connection socket, each said screw head is encompassed on an outer face by one of said connecting conductors of said connection socket and consequently is held in a secure manner in said receiving arrangement.

US Pat. No. 10,249,460

HIGH THERMAL STABILITY THERMAL CUTOFF DEVICE PELLET COMPOSITION

Therm-O-Disc, Incorporate...

1. A pellet composition in a thermally-actuated, current cutoff device, the pellet composition comprising dibenzosuberenone is in a solid phase and maintains its structural rigidity up to a transition temperature (Tf) of greater than or equal to about 80° C. in the thermally-actuated, current cutoff device.

US Pat. No. 10,249,456

APPARATUS WITH MEMBRANE PANEL HAVING CLOSE-PROXIMITY COMMUNICATION ANTENNA

Illinois Tool Works Inc.,...

20. A membrane panel user interface comprising:a first layer that includes a close-proximity communication antenna embedded within the membrane panel, wherein the first layer of the membrane panel is connected to a controller via a first electrical connector; and
a second layer that includes a membrane switch circuit, the second layer of the membrane panel connected to the controller via a second electrical connector.

US Pat. No. 10,249,455

IN-WALL ELECTRICAL CONTROL UNIT WITH OPENABLE SWITCH COVER

JASCO PRODUCTS COMPANY LL...

1. An in-wall electrical control unit with openable switch cover comprising:an electrical control unit;
a switch cover;
an attachment mechanism;
the electrical control unit comprising a user interface and a housing;
the housing being connected around the user interface;
the switch cover being hingedly engaged with the housing through the attachment mechanism;
the switch cover being selectively positioned in between an opened position and a closed position through the attachment mechanism;
the switch cover being positioned adjacent to the user interface in response to the switch cover being positioned in the closed position;
the switch cover comprising a body, an inner surface, an outer surface and an interface actuation knob;
the inner surface being positioned opposite the outer surface across the body;
the inner surface being positioned adjacent to the user interface in response to the switch cover being positioned in the closed position;
the interface actuation knob being positioned on the inner surface without being positioned on the outer surface;
the attachment mechanism comprising a first hinge portion and a second hinge portion;
the first hinge portion being connected to the housing;
the second hinge portion being connected to the switch cover;
the first hinge portion and the second hinge portion being hingedly engaged with each other so as to form a hinge joint; and
the switch cover being swingable in between the opened position and the closed position at the hinge joint by the first hinge portion and the second hinge portion being hingedly engaged with each other.

US Pat. No. 10,249,454

KEY STEM FOR A KEY MODULE OF A KEY FOR A KEYBOARD, KEY MODULE OF A KEY FOR A KEYBOARD, AND METHOD FOR MANUFACTURING A KEY MODULE FOR A KEY FOR A KEYBOARD

1. A key stem for a key module of a key for a keyboard comprising:a coupling section for coupling a key button thereto;
a guidance section for guiding the key stem into a receiving section of the key module when the key stem is actuated between a standby position and an actuation position;
at least one elastically deformable end stop element, which is disposed on the guidance section and is designed to bear against at least one end stop section of the key module when the key stem is actuated into the actuation position;
at least one elastically deformable return stop element, which is disposed in the guidance section and is designed to bear against at least one return stop section of the key module when the key stem is actuated back to the standby position; and
wherein the key stem comprises a material for the at least one end stop element having a lower hardness than a material for the guidance section, and a material for the at least one return stop element having a lower hardness than the material for the guidance section.

US Pat. No. 10,249,453

SWITCHES FOR USE IN MICROELECTROMECHANICAL AND OTHER SYSTEMS, AND PROCESSES FOR MAKING SAME

Harris Corporation, Melb...

1. A process for making a switch, comprising:selectively depositing a first layer of an electrically-conductive material on a substrate to form at least a portion of a ground plane and an actuator;
selectively depositing a second layer of the electrically-conductive material on the first layer and the substrate to form at least a portion of each of the actuator, a housing, and a mount for a contact element configured to electrically connect a first and a second electrical conductor on a selective basis when actuated by the actuator; and
selectively depositing a third layer of the electrically-conductive material on the first and second layers and the substrate to form at least a portion of each of the housing, the actuator, the mount, the contact element, and the first and second electrical conductors.

US Pat. No. 10,249,452

ARRANGEMENT WITH A HEAT-INSULATING SWITCH AND A HEAT INSULATION

ROBERT BOSCH GMBH, Stutt...

1. An assemblage, comprising:a thermally insulating switch and a thermal insulator for constituting an electrical conductor passthrough through the thermal insulator for electrical connection of a thermally insulated electrochemical battery to a load, the thermal insulator thermally insulating an inner space from an outer space the assemblage having inner connector on a side of the inner space, the assemblage having outer connector on a side of the outer space, and the switch, in a closed state electrically conductively connecting the inner connector to the outer connector, and in an open state electrically disconnecting the inner connector from the outer connector; and
a control unit to control the thermally insulating switch, a current flowing through the switch being detectable by the control unit, the switch being controllable by the control unit in such a way that the switch is actuatable only in a substantially zero-current state;
wherein the switch is disposed in the thermal insulator in such a way that thermal insulation between the inner connector and the outer connector is accomplished by way of the switch in the open state.

US Pat. No. 10,249,451

PERMANENT MAGNET DRIVE ON-LOAD TAP-CHANGING SWITCH

1. A permanent magnet drive on-load tap-changing switch, characterized in that: comprising a changing switch circuit and a high-speed mechanism, wherein the said changing switch circuit comprises an odd-numbered tap-changing circuit and an even-numbered tap-changing circuit that are structurally identical, wherein the tap-changing circuits are constituted by working contactors, and dual-contact synchronous transition contactors consisting of primary contactors and secondary contactors, and the working contactor is connected with the primary contactor by trigger transmitter and transition resistance, and a primary contactor of a tap-changing circuit is connected to the secondary contactor of another tap-changing circuit by a high-voltage thyristor, while the said trigger transmitter provides the high-voltage thyristor connected to the secondary contactor of the same tap-changing circuit with trigger current, wherein the said high-speed mechanism comprises a traveling mechanism used for bearing a moving contactor, a moving magnet group connected with the traveling mechanism, and a fixed magnet group producing an attracting force/repelling force with respect to the moving magnet group; wherein the said moving magnet group comprises a first permanent magnet and a second permanent magnet connected together at homonymic magnetic poles, an exposed homonymic magnetic pole of the first permanent magnet and that of the second permanent magnet face directly the fixed magnet group; wherein the said fixed magnet group comprises a rotating permanent magnet that rotates to change a force applied to the moving magnet group and thereby allowing the moving contactors to either come into contact with or be separated from working contactors and dual-contact synchronous transition contactors.

US Pat. No. 10,249,450

SWITCH FOR A SEAT BELT BUCKLE

AUTOLIV DEVELOPMENT AB, ...

1. A switch for a belt buckle of a seatbelt device, the belt buckle receiving a belt tongue, the switch comprising;at least two contact elements abutting on each other or reaching into abutment on each other in a cavity of the switch, wherein at least one of the contact elements is configured as a movable contact spring,
an insertion channel into which a portion of one or more of the belt tongue, a locking part, and an ejector is insertable into the belt buckle during a locking movement and removed from the belt buckle during an unlocking movement of the belt tongue,
a movably supported coupling member, which protrudes with a first section into the insertion channel and includes a second section coupled with the contact spring, and the movably supported coupling member second section abuts the contact spring,
wherein the coupling member and the contact spring are movably guided with respect to each other by an interlocking engagement for preventing a slippage of the contact spring from the coupling member.

US Pat. No. 10,249,449

ELECTROLYTE FORMULATIONS FOR ENERGY STORAGE DEVICES

Maxwell Technologies, Inc...

1. An energy storage device comprising:a cathode;
an anode;
a separator between the cathode and the anode; and
an electrolyte comprising a solvent, a lithium salt, and one or more additives;
wherein the one or more additives is selected from the group consisting of vinylene carbonate (VC), vinyl ethylene carbonate (VEC), a hydro fluorinated ether ethylene carbonate (HFEEC), dimethyl acetamide (DMAc), a hydro fluorinated ether (HFE), hydro fluorinated ether branched cyclic carbonate, and a fluorinated ethylene carbonate (FEC), and combinations thereof;
wherein the electrolyte comprises each of the one or more additives in about 0.5 wt % to about 5 wt %; and
wherein the solvent comprises EC (ethylene carbonate)/PC (propylene carbonate)/DEC (diethylcarbonate) in a ratio of about 3:1:4 by volume, EC/DEC/DMC (dimethylcarbonate)/EB (ethyl butyrate) in a ratio of about 1:1:1:1 by volume, EC/EMC (ethyl methyl carbonate) in a ratio of about 3:7 by volume, EC/EMC/MP (methyl propionate) in a ratio of about 1:1:8 by volume, EC/DEC/DMC/EMC in a ratio of about 1:1:1:2 by volume, or EC/DMC/EB in a ratio of about 1:1:1 by volume.

US Pat. No. 10,249,447

PROCESS FOR MANUFACTURING AN ALKALINE-BASED HYBRID SUPERCAPACITOR TYPE BATTERY, BATTERY OBTAINED BY THIS PROCESS AND PROCESS FOR RECYCLING AN ANODE MATERIAL OF AN ALKALI-ION BATTERY

1. A process for recycling a negative electrode B of a used alkali metal-ion battery which has lost at least a portion of initial capacity, comprising using negative electrode B as a negative electrode A of a hybrid supercapacitor based on an alkali metal.

US Pat. No. 10,249,446

STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

APAQ TECHNOLOGY CO., LTD....

1. A stacked-type solid electrolytic capacitor package structure, comprising:a capacitor unit including a plurality of first stacked capacitors stacked on top of one another and electrically connected with each other, wherein each first stacked capacitor includes a first positive portion and a first negative portion, the first positive portion of each first stacked capacitor has at least one first through hole formed on a lateral side thereof, and the first through holes of the first positive portions of the first stacked capacitors are in communication with each other to form a first communication hole;
a solder unit including at least one first connection solder for filling the first communication hole, wherein the first positive portions of the first stacked capacitors are connected with each other by the at least one first connection solder;
a package unit including a package body for enclosing the capacitor unit and the solder unit; and
a conductive unit including a first conductive terminal and a second conductive terminal separated from the first conductive terminal, wherein the first conductive terminal has a first embedded portion electrically connected to the first positive portion of the first stacked capacitor and enclosed by the package body, and a first exposed portion connected to the first embedded portion and exposed outside the package body, wherein the second conductive terminal has a second embedded portion electrically connected to the first negative portion of the first stacked capacitor and enclosed by the package body, and a second exposed portion connected to the second embedded portion and exposed outside the package body.

US Pat. No. 10,249,445

DYE-SENSITIZED SOLAR CELL INCLUDING A POROUS INSULATION SUBSTRATE AND A METHOD FOR PRODUCING THE POROUS INSULATION SUBSTRATE

Exeger Operations AB, St...

1. A method for producing a porous insulation substrate and a porous conducting layer formed on the insulation substrate for a solar cell, the method comprising:a) producing the porous insulation substrate by
providing a fabric of woven microfibers comprising yarns with holes formed between them,
preparing a fiberstock solution by mixing liquid and microfibers,
covering a first side of the fabric with the fiberstock solution,
draining liquid from the fiberstock solution through the holes in the fabric, and
drying the wet fabric with the microfibers disposed on the fabric,
b) depositing an ink comprising conductive particles on one side of the insulation substrate to form a porous conducting layer, and
c) forming a solar cell comprising the porous insulation substrate and the porous conducting layer.

US Pat. No. 10,249,444

METHOD OF FABRICATING AN ELECTROCHEMICAL DOUBLE-LAYER CAPACITOR

Georgia Tech Research Cor...

1. A method of fabricating an electrochemical double-layer capacitor comprising:providing a bottom substrate;
etching a first cavity within the bottom substrate;
growing a first plurality of substantially aligned carbon nanotubes within the first cavity;
providing a top substrate;
etching a second cavity within the top substrate;
growing a second plurality of substantially aligned carbon nanotubes within the second cavity;
providing a gap between the first plurality of substantially aligned carbon nanotubes and the second plurality of substantially aligned carbon nanotubes, wherein a gap height prevents contact between the first plurality of substantially aligned carbon nanotubes and the second plurality of substantially aligned carbon nanotubes; and
capping the bottom substrate with the top substrate to provide the gap between the first plurality of substantially aligned carbon nanotubes and the second plurality of substantially aligned carbon nanotubes.

US Pat. No. 10,249,440

PHASE CHANGE TUNABLE CAPACITOR

The United States of Amer...

1. A variable capacitor device comprising:a substrate;
a plurality of insulated wells on said substrate;
a plurality of capacitors on said substrate, wherein each well of said plurality of insulated wells contains a phase change material; and
a plurality of thermal resistance components that cause a change in a dielectric constant of the phase change material in each insulated well,
wherein the phase change materials in each of the plurality of insulated wells are configured to have different phase change properties.

US Pat. No. 10,249,437

MULTILAYER ELECTRONIC COMPONENT WITH SIDE PARTS ON EXTERNAL SURFACES, AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a multilayer structure in which pluralities of first internal electrode patterns and second internal electrode patterns different from the first internal electrode patterns are alternately stacked and containing a dielectric material; and
first and second side parts and first and second external electrodes disposed on respective first, second, third, and fourth outer surfaces of the multilayer structure,
wherein each of the plurality of first internal electrode patterns extends to the first, second, and third outer surfaces of the multilayer structure, and each of the plurality of second internal electrode patterns extends to only the fourth outer surface of the multilayer structure,
the second external electrode extends from the fourth outer surface directly onto the first and second outer surfaces by a first length measured from edges common with the fourth outer surface,
the first internal electrode patterns are exposed only on first portions of the first and second outer surfaces spaced apart from the edges common with the fourth outer surface by a distance larger than the first length, and
the first and second side parts are disposed only on the first portions of the first and second outer surfaces, respectively.

US Pat. No. 10,249,435

ELECTRONIC COMPONENT HAVING A CONNECTION ELEMENT

Robert Bosch GmbH, Stutt...

1. An electronic component (2, 40), comprising an electrical structural part (3, 27) having two electrical connections (4, 5, 28, 29) formed respectively on mutually opposite surfaces of the structural part (3, 27), wherein the component (2, 40) has an electrically conductive connection element (8, 9, 30, 31) for each of the connections (4, 5, 28, 29), wherein the connection element has a securing foot (14, 15, 38, 39) for cohesive electrical connection to a circuit carrier (22), wherein the connection element (8, 9, 30, 31) is cohesively connected to the electrical connection (4, 5, 28, 29) and is configured to carry the component (2, 40),wherein the connection element (8, 9, 30, 31) has at least two metal layers (10, 12, 11, 13, 32, 33, 34, 35, 36, 37) cohesively connected to one another, respectively formed from mutually different metals, wherein a base layer (10, 11, 32, 33) of the metal layers is connected to the electrical connection (4, 5, 28, 29) and in a region of the securing foot (14, 15, 38, 39) is configured for soldering connection to a circuit carrier (22), such that a further one (12, 13, 34, 35) of the metal layers is thermally connected in parallel with the base layer (10, 11, 32, 33), and wherein the further metal layer (12, 13, 34, 35) has a greater thermal conductivity than the base layer (10, 11, 32, 33), wherein the connection element (8, 9, 30, 31) has a further metal layer (36, 37), which is formed from the metal of the base layer (10, 11, 32, 33), wherein the metal layer having the greater thermal conductivity is enclosed between the base layer (10, 11, 32, 33) and the further metal layer (36, 37) composed of the metal of the base layer (10, 11, 32, 33).

US Pat. No. 10,249,434

CAPACITOR

MURATA MANUFACTURING CO.,...

1. A capacitor comprising:a conductive porous substrate having a porous portion;
an upper electrode; and
a dielectric layer between the upper electrode and the porous portion and containing an oxygen element and at least one metal element; and
wherein the porous portion has a path integral value of 1 ?m/?m2 to 16 ?m/?m2, and a porosity of 20% to 90%, and wherein a ratio Z expressed by (1) is 0.79 or more,

where Od and Md respectively represent signal intensities of the oxygen element and the at least one metal element when the dielectric layer is analyzed by energy dispersive X-ray spectroscopy, and
where Or and Mr respectively represent signal intensities of the oxygen element and the metal element when a reference material having stoichiometric composition of the oxygen element and the at least one metal element constituting the dielectric layer is analyzed by the energy dispersive X-ray spectroscopy.

US Pat. No. 10,249,433

ANTENNA DEVICE AND ELECTRONIC APPARATUS

Dexerials Corporation, S...

1. An antenna device comprising:a power transmission antenna including
a magnetic core including two magnetic plates that face each other, a magnetic material-containing connecting portion that connects at least part of an end section of each of the two magnetic plates, and a space between the two magnetic plates, and
a power transmission coil disposed on at least one of the two magnetic plates at a side thereof that faces the space; and
a power reception antenna including a power reception coil, wherein
the power reception antenna is positionable in the space.

US Pat. No. 10,249,431

ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a substrate which includes a first main surface and a second main surface each having substantially a rectangular shape;
a first outer electrode, a second outer electrode, a third outer electrode, and a fourth outer electrode which are provided on the second main surface to correspond to four corners of the second main surface;
a fifth outer electrode which is provided on the second main surface;
a multilayer body which includes a third main surface and a fourth main surface, the third main surface being arranged facing the first main surface, and which has a structure in which a plurality of insulating layers are laminated in a normal direction of the first main surface;
a first inductor which is provided at the multilayer body, which has substantially a helical shape circulating in a first predetermined direction when viewed from the normal direction, and which includes a first end portion and a second end portion; and
a first surface mounted electronic component which is mounted on the fourth main surface and which includes a sixth outer electrode and a seventh outer electrode,
wherein the first end portion is electrically connected to the first outer electrode,
wherein the second end portion is electrically connected to the second outer electrode and the sixth outer electrode,
wherein the seventh outer electrode is electrically connected to the fifth outer electrode,
wherein the sixth outer electrode, the seventh outer electrode, and the fifth outer electrode are arranged in a line when viewed from the normal direction, and
wherein the first surface mounted electronic component does not overlap a center of the first inductor when viewed from the normal direction.

US Pat. No. 10,249,430

TRANSFORMER AND SWITCHED-MODE POWER SUPPLY APPARATUS

TAMURA CORPORATION, Toky...

1. A transformer, comprising:a core having a linear center leg portion in a center portion thereof;
a primary winding that is provided around the linear center leg portion of the core and is configured to be electrically connected to an external power source, wherein the primary winding creates a varying flux in the core in response to an input voltage applied from the external power source;
at least two secondary windings provided around the linear center leg portion of the core and having a winding axis which is the same as a winding axis of the primary winding, wherein each of the at least two secondary windings is configured to induce a voltage in response to the created varying flux in the core in order to provide the induced voltage to a load; and
at least two auxiliary windings provided around the linear center leg portion of the core and having a winding axis which is the same as the winding axis of the primary winding, the auxiliary windings respectively neighboring the secondary windings, wherein each of the at least two auxiliary windings is configured to induce a voltage in response to the created varying flux in the core, the auxiliary windings being connected with each other in a parallel electric connection,
wherein the auxiliary windings are electrically connected with a control circuit for controlling a switching element which is electrically connected with the primary winding and the auxiliary windings provide the control circuit with the induced voltage for driving the switching element, and
wherein the secondary windings are disposed at both sides of the primary winding in a winding axis direction of the primary winding and are disposed closer to the primary winding than the auxiliary windings, in the winding axis direction of the primary winding.

US Pat. No. 10,249,429

COIL DEVICE

TDK CORPORATION, Tokyo (...

1. A coil device comprising a coil part having a wire wound around in a coil form,a core part having a magnetic material and a resin and covering entire said coil part including an inside of said coil part, and
a terminal electrode installed at an outer face of said core part, wherein
a lead part of said wire projects out from the outer face of said core part and a bonding part between said lead part and said terminal electrode is formed at a position spaced apart from said outer face,
said terminal electrode comprises a terminal body installed along the outer face of said core body, and a lead supporting part bent from said terminal body towards said bonding part at the position near where said lead part projects out from the outer face of said core part, and
a crossing angle ?1 of said lead supporting part with respect to an inner face of said terminal electrode is less than 90 degrees.

US Pat. No. 10,249,428

REACTOR

DAIKIN INDUSTRIES, LTD., ...

1. A reactor comprising:a coil;
a reactor body;
a support base; and
a terminal block that is fixed to a plurality of conductor wires that lead out from both ends in a winding core direction of the coil,
wherein the terminal block includes:
an input-side terminal block that is fixed to an input-side conductor wire that leads out from one end of the coil; and
an output-side terminal block that is fixed to an output-side conductor wire that leads out from another end of the coil,
wherein the input-side terminal block and the output-side terminal block are disposed on different levels in the winding core direction based on lead-out positions in the winding core direction of the input-side conductor wire and the output-side conductor wire,
wherein the reactor body and the terminal block are fixed, respectively, onto the front side and the rear side of the support base, at a distance from each other,
the input-side terminal block holds a tip of the input-side conductor wire in parallel with a tip of the output-side conductor wire that is held by the output-side terminal block, and
a terminal connection portion of the input-side terminal block and a terminal connection portion of the output-side terminal block that connect the reactor to electric components are respectively disposed, in a winding core direction of the coil, outside the tip of the input-side conductor wire and the tip of the output-side conductor wire.

US Pat. No. 10,249,426

TUNABLE INDUCTOR ARRANGEMENT, TRANSCEIVER, METHOD AND COMPUTER PROGRAM

TELEFONAKTIEBOLAGET LM ER...

1. A multi-band radio receiver comprising:a receiver path configured for operating in a selected frequency band, as selected between a high-frequency band and a low-frequency band in a pairing of high- and low-frequency bands;
an inductor-capacitor (LC) resonator configured to tuning the receiver path to a selected frequency in the selected frequency band;
a tunable inductor arrangement arranged on a chip or substrate and operative as an inductor in the LC resonator, the tunable inductor arrangement being configured for selective switching between a first self-resonant frequency corresponding to the high-frequency band and a second self-resonant frequency corresponding to the low-frequency band, and comprising:
a first winding part connected at a first end to a first input of the tunable inductor arrangement;
a second winding part connected at a first end to a second end of the first winding part;
a third winding part connected at a first end to a second input of the tunable inductor arrangement;
a fourth winding part connected at a first end to a second end of the third winding part and at a second end connected towards a second end of the second winding part; and
a switch arrangement switchable between:
a first switch setting that connects the first and third winding parts in series between the first and second inputs, thereby tuning the tunable inductor arrangement for the first or the second self-resonant frequency; and
a second switch setting that connects the first, second, fourth and third winding parts in series between the first and second inputs, thereby tuning the tunable inductor arrangement for the other one of the first and second self-resonant frequency; and
control circuitry configured to control the switch arrangement of the tunable inductor arrangement in dependence on the selected frequency band;
wherein the first and third winding parts are arranged on the chip or substrate such that magnetic fields of the first and third winding parts are essentially common, and the second and fourth winding parts are arranged to cancel electro-magnetic coupling with the first and third winding parts.

US Pat. No. 10,249,425

COIL DEVICE

TDK CORPORATION, Tokyo (...

1. A coil device comprising:a core member extending in a longitudinal direction;
a bobbin with a longitudinal concave portion (1) having a side surface opening portion and (2) housing the core member;
a coil portion comprising a wire wound around the bobbin and the core member;
an outer case with a housing concave portion that houses an assembly of the bobbin, the core member, and the coil portion;
a potting resin between (1) the housing concave portion and (2) the bobbin and the coil portion; and
an easily deformable member arranged between an outer wall of the bobbin and a bottom wall of the housing concave portion;
wherein:
an opening port of the housing concave portion and the side surface opening portion are open in the same direction;
the easily deformable member is capable of being deformed before the bobbin and the outer case are deformed when the outer case receives an impact; and
a longitudinal elasticity of the easily deformable member is larger than that of the potting resin.

US Pat. No. 10,249,423

FLUID RESISTANT SOLENOID AND RELATED METHOD

Norgren, Inc., Littleton...

1. A solenoid assembly (100) comprising:a frame (104);
a coil (106) positioned proximate the frame (104);
a core (114) defined by the coil (106);
a plunger (108) actuatable between at least a first position and a second position;
a guide (109) at least partially disposed within the core (114), and the guide (109) being prevented from rotating independently of the frame (104), wherein the plunger (108) is disposed at least partially within the guide (109); and
a housing (102) that at least partially houses the frame (104), the coil (106), the guide (109) and the plunger (108), wherein the guide (109) is prevented from rotating independently of the housing (102), wherein the solenoid assembly (100) further comprises:
a flat mating portion (136) defined in a threaded region (130) of the guide (109); and
an aperture (132) defined by the frame (104), wherein the aperture (132) has a mating surface (108) which is configured to receive the flat mating portion (136) of the threaded region (130) of the guide (109) and is configured to prevent the guide (109) from independently rotating within the aperture (132) of the frame (104) by engaging the flat mating portion (136) with the mating surface (108).

US Pat. No. 10,249,420

CONTINUOUS WINDING MAGNETS USING THIN FILM CONDUCTORS WITHOUT RESISTIVE JOINTS

UChicago Argonne, LLC, C...

1. An undulator comprising:a magnetic core having a plurality of parallel grooves at least partially circumferentially about the core;
a plurality of turnaround pins affixed to the core, a first group of more than one turnaround pin of the plurality of turnaround pins positioned along one side of the core and a second group of more than one turnaround pin of the plurality of turnaround pins positioned along the other side of the core, each of the plurality of pins associated with one of the plurality of parallel grooves;
a continuously wound tape, comprised of a conductor or superconductor material, wound about each of the plurality of pins and the associated one of the plurality of parallel grooves, forming a winding stack having a plurality of magnetic coils with alternating polarity;
the continuously wound tape further having a plurality of transition tape portions, each of the plurality of transition tape portions extending from one of the turnaround pins to a succeeding pin,
wherein the continuously wound tape is without joints throughout the winding stack.

US Pat. No. 10,249,418

PERMANENT MAGNET MATERIAL AND METHOD FOR PREPARING THE SAME

YANSHAN UNIVERSITY, Qinh...

1. A method for preparing a permanent magnet material, the method comprising:i) subjecting a hot press unit to hot press deformation, wherein the hot press unit consists of a permanent magnet blank and a mold in which the permanent magnet blank is placed; and
ii) during the hot press deformation, subjecting the hot press unit to a cooling treatment at both ends along a hot press pressure direction, and the hot press unit has an axis being parallel to the hot press pressure direction;
the mold is made of a metal;
the mold is a cylindrical body having two open ends, and has an outer wall with a generatrix that is a concave curve, a straight line or a convex curve;
the hot press unit after the hot press deformation has a deformation in a direction parallel to the hot press pressure direction of 60-90%.

US Pat. No. 10,249,412

COMPOSITE CABLE

HITACHI METALS, LTD., To...

1. A composite cable, comprising:a twisted wire formed by twisting a plurality of signal lines; and
a plurality of power lines that are arranged on a circumference of a circle concentric with the twisted wire so as to surround an outer circumference of the twisted wire and are twisted around the twisted wire,
wherein each signal line of the signal lines comprises a conductor, an insulation layer provided around the conductor, a shield provided around the insulation layer, and a jacket provided around the shield,
wherein each power line of the power lines comprises a conductor and an enamel layer comprising one or more of enamels selected from the group consisting of polyimide (PI), polyamide-imide (PAI), polyesterimide (PEsI), polyetherimide (PEI), polyimide hydantoin-modified polyester, polyamide (PA), formal, polyurethane, polyester (PEst), polyvinyl formal, epoxy and polyhydantoin,
wherein said each power line has a smaller diameter than said each signal line, and
wherein a ratio of a twist pitch of the power lines to a pitch diameter of a layer formed of the power lines is smaller than a ratio of a twist Ditch of the signal lines to a pitch diameter of a layer formed of the signal lines.

US Pat. No. 10,249,409

COATED CONDUCTORS

SCHLUMBERGER TECHNOLOGY C...

1. An assembly comprising:a housing that comprises opposing ends, a longitudinal axis, an axial length defined between the opposing ends, a maximum transverse dimension that is less than the length and an interior space;
circuitry disposed at least in part in the interior space; and
a coated electrical conductor electrically coupled to the circuitry wherein the coated electrical conductor comprises an electrical conductor that comprises copper and a length defined by opposing ends, a polymeric electrical insulation layer disposed about at least a portion of the length of the electrical conductor, and a barrier layer disposed about at least a portion of the polymeric electrical insulation layer,
wherein the barrier layer comprises a sol-gel layer.

US Pat. No. 10,249,408

ELECTRICAL CABLE, TERMINAL-EQUIPPED ELECTRICAL CABLE, AND METHOD OF MANUFACTURING TERMINAL-EQUIPPED ELECTRICAL CABLE

AutoNetworks Technologies...

1. An electrical cable, comprising:an electrical cable portion having a plurality of linear conductors configured to be connected to a common connection point;
a shield portion configured to cover at least one side of a periphery of the electrical cable portion; and
a flexible insulation member configured to cover the periphery of the electrical cable portion;
wherein a middle portion between both ends of the electrical cable portion has a non-twisted portion where at least some among the plurality of linear conductors are provided in a state spaced apart from each other,
the shield portion does not completely surround the non-twisted portion of the electrical cable portion, and
the insulation member covers a periphery of the non-twisted portion of the electrical cable portion, fills gaps between the plurality of linear conductors in the non-twisted portion, and covers a periphery of the shield portion.

US Pat. No. 10,249,406

CABLE HARNESS

Robert Bosch GmbH, Stutt...

1. A battery module comprising a plurality of battery cells and at least one cable harness (10), wherein the at least one cable harness (10) comprises a plurality of electrical conductors (12) for contacting the plurality of battery cells of the battery module as well as a film-shaped carrier element (14), wherein the electrical conductors (12) are arranged for at least a portion in parallel with each other on the carrier element (14) and are joined to the carrier element (14), characterized in that a flexible elongated hollow body (16) is arranged in parallel for at least a portion with at least one of the electrical conductors (12) and is joined to the carrier element (14), wherein at least one of the electrical conductors (12) of the cable harness (10) is integrally bonded to a terminal of a battery cell of the battery module.

US Pat. No. 10,249,404

CERAMIC PASTE COMPOSITION USING CARBON NANOTUBE OR CARBON NANOTUBE-METAL COMPLEX, AND CONDUCTIVE FILM CONTAINING SAME

BIONEER CORPORATION, Dae...

1. A ceramic paste composition, comprising, based on 100 wt % of the ceramic paste composition:1 to 50 wt % of carbon nanotubes or a carbon nanotube-metal composite;
1 to 30 wt % of a silicone adhesive, wherein the silicone adhesive comprises 0.1 to 10 wt % of a silanol group, based on 100 wt % of the silicone adhesive, and wherein a molar ratio of a phenyl group to a methyl group present in the silicone adhesive ranges from 0.3:1 to 2.5:1;
3 to 15 wt % of an organic binder, wherein a viscosity of the organic binder ranges from 10 cps to 50000 cps at 25° C.;
2 to 10 wt % of a dispersant, wherein a number average molecular weight of the dispersant ranges from 2000 to 20000; and
40 to 80 wt % of an organic solvent.

US Pat. No. 10,249,401

ALUMINUM ALLOY WIRE, ELECTRIC WIRE, CABLE AND WIRE HARNESS

YAZAKI CORPORATION, Toky...

1. An aluminum alloy wire comprising:(A) a metallic microstructure of a cross section of the wire having an average crystal grain size of 3 ?m or more to 20 ?m or less,
(B) the metallic microstructure includes precipitations, and each precipitation has a precipitation size in a cross section of the aluminum alloy wire of 100 nm or less, and
(C) the number density of the precipitations in the cross section of the aluminum alloy wire being one or more per square micrometer,
wherein a constituent component of the aluminum alloy wire is magnesium, silicon, and aluminum and inevitable impurities as the balance such that a proportion of the impurities is 0.07% or less by mass and a resulting proportion of the constituent component of magnesium, silicon, and aluminum is 99.93% or more by mass, and
wherein the content (M) by atomic percentage (at %) of the magnesium in the wire and the content (S) by atomic percentage (at %) of the silicon satisfy the following expressions (1) and (2):
[Mathematical Formula 1]
0.2?M?1.19  (1); and
?0.81M+1.44?S??1.54M+2.31  (2), and
wherein the aluminum alloy has a tensile strength of 150 MPa or more, a tensile elongation of 10% or more, and an electroconductivity of 50% IACS or more.

US Pat. No. 10,249,395

CLEANING DEVICE FOR BOTTOM SURFACES

Ingenieria y Marketing, S...

1. A floor cleaner, comprising:an outer casing which forms a suction bell,
an upper suction mouth on said casing,
a pulling arrangement set on opposite sides of the casing, the pulling arrangement fitted with independent drive motors and corresponding transmission mechanisms on each side, and
cleaning rollers, the cleaning rollers including:
an assembly of interior cleaning rollers placed close to a center of the casing, and having a width substantially equal to a distance between lateral side elements of said casing, and
an assembly of outer cleaning rollers placed in a zone close to front and rear edges of the casing of the cleaner, and having a total width greater than a width of said casing.

US Pat. No. 10,249,394

PASSIVE NITROGEN INJECTING DEVICE FOR NUCLEAR REACTOR COOLANT PUMP

1. A passive nitrogen injection device for a nuclear reactor coolant pump, comprising:a nitrogen supply unit configured to supply nitrogen;
a pressure control valve configured to control supply of the nitrogen of the nitrogen supply unit according to a pressure;
an electronic control valve configured to selectively supply the nitrogen supplied through the pressure control valve;
an accumulator filled with the nitrogen supplied through the pressure control valve at a preset pressure and configured to supply the filled nitrogen when a loss-of-coolant accident occurs;
an isolation valve configured to control supply of the nitrogen of the accumulator to inside of a seal housing of a nuclear reactor coolant pump; and
a pressure gauge configured to detect a pressure of the accumulator, wherein the pressure gauge automatically fills the accumulator with nitrogen supplied by the nitrogen supply unit in a nitrogen injection system by opening the pressure control valve and the electronic control valve such that the pressure of the accumulator filled with nitrogen is maintained at a set pressure when a pressure of the accumulator detected by the pressure gauge is equal to or lower than the set pressure,
wherein when a loss-of-coolant accident (LOCA) occurs and external power is not supplied, the nitrogen filled in the accumulator is supplied to the inside of the seal housing by the pressure of the accumulator itself, the isolation valve being opened and the electronic control valve being closed when an LOCA occurs and external power is not supplied.

US Pat. No. 10,249,393

MODULAR REACTOR STEAM GENERATOR CONFIGURED TO COVER A REACTOR OUTER WALL CIRCUMFERENCE

1. An apparatus comprising:a nuclear reactor comprising an upper head, a reactor vessel shell coupled to the upper head, the reactor vessel shell comprises a cylindrical shape, a lower head provided on a lower portion of the reactor vessel shell, and a core located within an interior of the nuclear reactor; and
a steam generator surrounding a circumference of the reactor vessel shell, the steam generator comprising a first penetration hole and a second penetration hole, the first penetration hole in fluid communication with the interior of the nuclear reactor such that a fluid flows between the interior of the nuclear reactor and an interior of the steam generator, the second penetration hole being separate from the first penetration hole and in fluid communication with the inside of the nuclear reactor, such that a fluid flows between the interior of the nuclear reactor and an interior of the steam generator, wherein the steam generator further comprises:
a steam generator inner shell connected to or formed in one piece with the reactor vessel shell and surrounding 360 degrees the circumference of the reactor vessel shell, wherein the steam generator inner shell shares a portion with the reactor vessel shell and extends in a longitudinal direction of the reactor vessel shell; and
a steam generator outer shell spaced apart from the steam generator inner shell and surrounding 360 degrees the circumference of the reactor vessel shell, wherein the steam generator outer shell extends in the longitudinal direction of the reactor vessel shell,
wherein the first penetration hole and the second penetration hole are provided in a region in which the reactor vessel shell and the steam generator inner shell are connected to or formed in one piece with each other.

US Pat. No. 10,249,392

METHOD OF FORMING A SUPPORT STRUCTURE FOR A CONTROL ROD ASSEMBLY OF A NUCLEAR REACTOR

BWXT mPower, Inc., Charl...

10. A method comprising:forming a plurality of columnar elements defining a central passage having a constant cross-section;
constructing a control rod guide frame including the plurality of columnar elements by stacking the columnar elements end-to-end;
providing a control rod assembly comprising a plurality of control rods parallel aligned with the central passage of the control rod guide frame;
wherein the plurality of control rods is movable into and out of the central passage of the control rod guide frame, and wherein any portion of the at least one control rod disposed in the central passage is guided by the central passage over the entire length of the portion of the at least one control rod that is disposed in the central passage, and
wherein the control rod assembly comprises the plurality of control rods connected with a spider or other coupling element, and the spider or other coupling element is disposed in the central passage of the control rod guide frame and moves along the central passage as the plurality of control rods move into or out of the central passage.

US Pat. No. 10,249,390

METHOD FOR DETERMINING A PROACTIVITY SCORE FOR HEALTH

1. A method for determining a health proactivity score of a human, comprising steps of:receiving, into a computing device at a first instance, a first set of at least two characteristics associated with the human, wherein the at least two characteristics are selected from the group consisting of a height, a weight, a percentage of body fat, a waist circumference, a waist and hip ratio, and a neck size, and
wherein the at least two characteristics associated with the human are measured at a clinical center based on an appointment;
calculating, by the computing device, a first value of a health-related metric based upon the first set of the at least two characteristics received at the first time instance;
receiving, into the computing device at a second time instance, a second set of the at least two characteristics associated with the human;
calculating, by the computing device, a second value of the health-related metric based upon the second set of the at least two characteristics received at the second time instance;
storing, in a database, the first set of the at least two characteristics, the second set of the at least two characteristics, the first value of the health-related metric, and the second value of the health-related metric;
determining, by the computing device, a change between the second value of the health-related metric and the first value of the health-related metric;
determining, by the computing device, a category for the second value of the health-related metric from a plurality of pre-defined categories, wherein each pre-defined category is associated with a pre-defined range of a plurality of values of the health-related metric;
dynamically determining, by the computing device, an overall proactivity score of the human based upon (1) the determined category and, (2) the change between the second value of the health-related metric and the first value of the health-related metric, wherein the overall proactivity score increases in response to improvement of health of the human;
storing, in the database, the overall proactivity score of the human;
automatically decaying, by the computing device, the overall proactivity score over time based on both a lapse of pre-defined time period in response to no further reception of the at least two characteristics at a third time instance, wherein the third time instance is subsequent to both the first time instance and the second time instance and a current value of the health-related metric; wherein the decaying is executed from the predefined time period away from a date associated with the calculating of the second health-related metric; and
displaying, by the computing device, on a display of the computing device, the overall proactivity score.

US Pat. No. 10,249,389

INDIVIDUAL AND COHORT PHARMACOLOGICAL PHENOTYPE PREDICTION PLATFORM

THE REGENTS OF THE UNIVER...

1. A computer-implemented method for identifying pharmacological phenotypes using statistical modeling and machine learning techniques, the method executed by one or more processors programmed to perform the method, the method comprising:obtaining, at one or more processors, a set of training data including for each of a plurality of first patients:
panomic data indicative of biological characteristics of the first patient,
sociomic data indicative of risk factors associated with adverse cultural, childhood, acute or chronic traumatic events, or chronic stress resulting from adverse conditions,
environmental data indicative of experiences of the first patient collected over time, and
phenomic data indicative of at least one of: a response to one or more drugs, whether the first patient experiences substance abuse, or one or more chronic diseases of the first patient;
generating, by the one or more processors, a statistical model for determining pharmacological phenotypes based on the set of training data;
receiving, at the one or more processors, a set of panomic data, and sociomic and environmental data for a second patient collected over a period of time;
applying, by the one or more processors, the panomic data, and the sociomic and environmental data for the second patient to the statistical model to determine one or more pharmacological phenotypes for the second patient; and
providing, by the one or more processors, the one or more pharmacological phenotypes for the second patient for display to a health care provider, wherein the health care provider recommends a course of treatment to the second patient according to the pharmacological phenotypes.

US Pat. No. 10,249,387

METHOD FOR MANAGING AN ELECTRONIC MEDICAL RECORD AND AN EMR MANAGEMENT SYSTEM

1. A method for managing an electronic medical record (EMR), the method to be implemented by an EMR management system for writing an EMR entry into a data storage device possessed by a patient, the EMR management system including a server, an attendance management device that is coupled to the server and that is disposed in proximity of a location where a health care service is to be performed for recording attendance of a health professional, and a computer that is coupled to the server and that is disposed at the location and that is separate from the attendance management device, the EMR management system storing in advance a schedule that contains information associated with the health professional and the location, the method comprising the steps of:generating, by the attendance management device, information associated with the health professional who provides the health care service that results in the EMR entry, and the location which is related to the health care service when the attendance management device is operated for attendance registration by the health professional;
determining, by the server, whether or not to permit writing of the EMR entry into the data storage device by comparing the information generated by the attendance management device and the information contained in the schedule;
the server giving the computer permission to write the EMR entry into the data storage device when it is determined that the information generated by the attendance management device conforms to the information contained in the schedule;
determining, by the computer when the data storage device is used to be connected to the computer, whether or not the patient agrees with writing of the EMR entry into the data storage device according to input of the patient;
writing, by the computer, the EMR entry into the data storage device when writing of the EMR entry is permitted by the server of the EMR management system and is agreed upon by the patient; and
withdrawing, by the server, the permission to write the EMR entry into the data storage device when departure registration, which is made by the health professional by punching out using the attendance management device, has completed for achieving secure circulation of medical records.

US Pat. No. 10,249,382

DETERMINATION OF FAST TO PROGRAM WORD LINES IN NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. An apparatus, comprising:a word line;
a plurality of memory cells connected to the word line;
a programming circuit connected to the plurality of memory cells, the programming circuit configured to apply a series of voltage pulses to the word line during a programming operation;
a sensing circuit connected to the plurality of memory cells, the sensing circuit configured to perform a first verify operation for a first data state after a voltage pulse of the series of voltage pulses; and
a test circuit configured to determine a number of memory cells that satisfy the first verify operation and that are programmed above a reference voltage level and configured to signal an alert in response to the number of memory cells targeted for the first data state that are programmed above the reference voltage level exceeding a threshold number.

US Pat. No. 10,249,380

EMBEDDED MEMORY TESTING WITH STORAGE BORROWING

QUALCOMM Incorporated, S...

1. An integrated circuit comprising:a functional logic block including multiple storage units, the functional logic block configured to store functional data in the multiple storage units during a regular operational mode, each storage unit of the multiple storage units comprising:
multiplexer circuitry including a first input configured to receive the functional data, a second input configured to receive scan input data, and a third input configured to receive memory test result data;
a memory block; and
test logic configured to perform a test on the memory block to generate the memory test result data, the test logic configured to retain the memory test result data in the multiple storage units of the functional logic block using the third input of the multiplexer circuitry during a testing mode.

US Pat. No. 10,249,377

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a memory cell;
a bit line coupled to the memory cell;
a sense amplifier coupled to the bit line;
a word line coupled to a gate of the memory cell; and
a row decoder coupled to the word line,
wherein a write operation repeats a program loop including a program operation, a first verify operation performed after the program operation, and a second verify operation performed after the first verify operation,
the row decoder applies a first read voltage to the word line in the first and second verify operations,
when the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation,
when the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation, and
the sense amplifier senses the voltage of the bit line for a third sense period longer than the first sense period in the second verify operation.

US Pat. No. 10,249,376

FLASH MEMORY STORAGE DEVICE AND OPERATING METHOD THEREOF

Winbond Electronics Corp....

1. A flash memory storage device, comprising:a memory cell array, comprising a plurality of memory blocks and a redundant memory block, wherein the memory blocks are configured to store data; and
a memory control circuit, coupled to the memory cell array and configured to perform an erase operation to a current memory block of the memory blocks and record an erase retry count of the current memory block;
wherein the memory control circuit determines whether the erase retry count exceeds a first threshold value, and the memory control circuit replaces the current memory block by the redundant memory block erased in advance during a time interval of the erase operation if the erase retry count exceeds the first threshold value.

US Pat. No. 10,249,375

FLASH MEMORY ARRAY WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE

Silicon Storage Technolog...

1. A memory device, comprising:a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region,
a control gate disposed over and insulated from the floating gate,
a select gate disposed over and insulated from a second portion of the channel region adjacent the drain region, and
an erase gate disposed over and insulated from the source region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates for the row of memory cells; and
each of the columns of memory cells includes an erase gate line that electrically connects together all the erase gates for the column of memory cells and is not electrically connected to erase gates in others of the columns of the memory cells.

US Pat. No. 10,249,373

CIRCUIT AND METHOD FOR READING A MEMORY CELL OF A NON-VOLATILE MEMORY DEVICE

STMICROELECTRONICS S.R.L....

1. A method for reading a memory cell of a non-volatile memory device provided with a memory array with memory cells arranged in wordlines and bitlines, the bitlines including a first bitline associated with the memory cell to be read and a second bitline distinct from the first bitline, wherein a first circuit branch is associated with the first bitline and a second circuit branch is associated with the second bitline, the memory cell being activatable via a wordline coupled to a control terminal of the memory cell, each of the first and second circuit branches having a local node and a global node, each local node coupled to a first dividing capacitor, each global node coupled to a second dividing capacitor, the method comprising:pre-charging the global nodes and the local nodes to a pre-charging voltage, wherein the memory cell is deactivated during the pre-charging;
equalizing the global nodes by coupling the global nodes of the first circuit branch and the second circuit branch so that the global nodes reach a common initial voltage, wherein the memory cell is deactivated during the equalizing; and
reading data stored in the memory cell by:
activating the memory cell via the wordline so that a respective voltage value at the local node of the first circuit branch discharges as a function of the data stored in the memory cell;
coupling, while the memory cell is activated via the wordline, the local node of the first circuit branch to the global node of the first circuit branch to generate a charge division between the first dividing capacitor of the first circuit branch and the second dividing capacitor of the first circuit branch so that the voltage of the global node of the first circuit branch goes to a value that is different from the common initial voltage as a function of the data stored in the memory cell; and
generating, while the memory cell is activated via the wordline, an output signal based upon a comparison between a first comparison voltage that is a function of the voltage of the global node of the first circuit branch, and a second comparison voltage that is a function of the voltage of the global node of the second circuit branch.

US Pat. No. 10,249,372

REDUCING HOT ELECTRON INJECTION TYPE OF READ DISTURB IN 3D MEMORY DEVICE DURING SIGNAL SWITCHING TRANSIENTS

SanDisk Technologies LLC,...

1. An apparatus, comprising:a plurality of memory strings arranged in a selected sub-block and an unselected sub-block, each memory string comprising select gate transistors and memory cells between the select gate transistors;
a plurality of word lines connected to the memory cells;
an unselected word line control circuit configured to apply a voltage at a read pass level to unselected word lines among the plurality of word lines;
a selected word line control circuit configured to apply a voltage at one or more control gate read levels to a selected word line among the plurality of word lines; and
a select gate control circuit associated with the unselected sub-block, configured to provide one or more transitions of at least some of the select gate transistors in the unselected sub-block from a non-conductive state to a conductive state and back to the non-conductive state while the voltage at the one or more control gate read levels is applied on the selected word line and while the voltage at the read pass level is applied to the unselected word lines.

US Pat. No. 10,249,369

SEMICONDUCTOR MEMORY DEVICE WITH FAST AND SLOW CHARGE AND DISCHARGE CIRCUITS

LAPIS Semiconductor Co., ...

1. A semiconductor memory including a memory cell, a pair of bit lines connected to said memory cell to transmit a data signal, and a sense amplifier connected to said pair of bit lines and to amplify the potentials of said pair of bit lines, said semiconductor memory comprising:a first discharge circuit configured to discharge electric charge stored in said pair of bit lines;
a second discharge circuit configured to discharge the electric charge stored in said pair of bit lines; and
a control part configured to selectively execute a low-speed discharge mode for operating only said second discharge circuit of said first and second discharge circuits, a high-speed discharge mode for operating both of said first and second discharge circuits, and a stop mode for stopping both of said first and second discharge circuits.

US Pat. No. 10,249,368

SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY COMPRISING RESISTIVE CHANGE MATERIAL AND METHOD OF OPERATING

Zeno Semiconductor, Inc.,...

1. A semiconductor memory array comprising:a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a floating body region;
a non-volatile memory comprising a bipolar resistive change element;
wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell;
wherein said array is configured to perform a restore operation on said at least two of said memory cells in parallel.

US Pat. No. 10,249,367

SEMICONDUCTOR APPARATUS COMPRISING A PLURALITY OF CURRENT SINK UNITS

SK hynix Inc., Icheon-si...

1. A processor, comprising:a processor configured to interpret a command input from the outside and control an operation of information according to an interpretation result of the command;
an auxiliary storage device configured to store a program for interpretation of the command, and the information;
a main storage device configured to transfer the program and information from the auxiliary storage device and store the program and the information so that the processor performs the operation using the program and information when the program is executed; and
an interface device configured to perform communication between the outside and one or more among the processor, the auxiliary storage device, and the main storage device,
wherein at least one of the auxiliary storage device and the main storage device includes a semiconductor memory apparatus comprising:
a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements in response to a column select signal;
a plurality of current sink units configured to flow current from one of the plurality of resistive memory elements to a ground terminal in response to a plurality of word line select signals; and
a sink current control unit configured to control the plurality of current sink units to flow different amounts of current from the plurality of current sink units to the ground terminal.

US Pat. No. 10,249,366

INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF

Sony Semiconductor Soluti...

1. A memory device comprising:a memory array configured to include a plurality of memory cells;
a controller configured to connect to the memory array via a plurality of word lines;
an interface configured to connect to the memory array via a plurality of bit lines and detect whether a memory cell is in a low resistive state or a high resistive state during a memory read operation; and
a limiter configured to connect to the plurality of bit lines and to limit or clamp a voltage to a predetermined threshold level when the interface detects that the memory cell is in the high resistive state,
wherein the interface includes a set/reset driver connected to the limiter,
wherein the set/reset driver is disabled during the memory read operation, and
wherein the limiter does not limit or clamp the voltage when the interface detects that the memory cell is in the low resistive state.

US Pat. No. 10,249,365

TWO-PART PROGRAMMING METHODS

Micron Technology, Inc., ...

1. A memory device, comprising:control logic;
wherein the control logic is configured to set a first start program voltage and a first stop program voltage for a write operation on a plurality of memory cells;
wherein the control logic is configured to cause the memory device to load actual first data for each memory cell of the plurality of memory cells to be programmed to a respective level greater than or equal to a first particular level;
wherein the control logic is configured to cause the memory device to load inhibit data for each memory cell of the plurality of memory cells to be programmed to a respective level less than a second particular level;
wherein the control logic is configured to cause the memory device to program each memory cell of the plurality of memory cells to be programmed to a respective level greater than or equal to the first particular level with the actual first data using program pulses in a first range from the first start program voltage to the first stop program voltage;
wherein the control logic is configured to set a second start program voltage and a second stop program voltage for the write operation on the plurality of memory cells;
wherein the control logic is configured to cause the memory device to load inhibit data for each memory cell of the plurality of memory cells programmed to a respective level greater than or equal to the first particular level;
wherein the control logic is configured to cause the memory device to load actual second data for each memory cell of the plurality of memory cells to be programmed to a respective level less than the second particular level;
wherein the control logic is configured to cause the memory device to program each memory cell of the plurality of memory cells to be programmed to a respective level less than the second particular level with the actual second data using program pulses in a second range from the second start program voltage to the second stop program voltage; and
wherein the first particular level is one level higher than the second particular level.

US Pat. No. 10,249,364

WORD LINE OVERDRIVE IN MEMORY AND METHOD THEREFOR

Everspin Technologies, In...

1. A method for writing to a magnetic memory cell that includes a selection transistor coupled in series with a magnetic tunnel junction, the method comprising:applying a de-select voltage to a gate of the selection transistor while a voltage at a second end of the selection transistor is a low standby voltage, wherein:
a first end of the magnetic memory cell corresponds to a first end of the selection transistor;
the second end of the magnetic memory cell corresponds to a second end of the magnetic tunnel junction; and
a second end of the selection transistor is coupled to a first end of the magnetic tunnel junction;
applying a first word line voltage to the gate of the selection transistor, wherein a difference between the first word line voltage and the low standby voltage is below a predetermined stress voltage level for the selection transistor;
while applying the first word line voltage, enabling an initial voltage across the memory cell such that the voltage at the second end of the selection transistor is raised from the low standby voltage to a raised source voltage that includes a voltage across the magnetic tunnel junction;
after the voltage at the second end of the selection transistor is raised to the raised source voltage, applying a second word line voltage to the gate of the selection transistor, wherein the second word line voltage is greater than the first word line voltage;
while applying the second word line voltage, applying a voltage across the magnetic memory cell that forces a free portion of the magnetic memory cell to a first state as a part of a first writing operation.

US Pat. No. 10,249,363

CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT SRAM

STMicroelectronics Intern...

1. A memory controller for a memory array having word lines and bit lines, the memory controller comprising:a row decoder;
a row pre-decoder configured to output an address for use by the row decoder:
a read-write clock generator configured to generate a hold clock signal;
an address clock generator configured to receive a read address and a write address, and which is operable in a single port mode and in a dual port mode; and
wherein the address clock generator, when operating in the dual port mode, is configured to:
in a read mode, latch the read address and output the read address to the row pre-decoder as the address as a function of the hold clock signal, and
in a write mode, latch the write address and output the write address to the row pre-decoder as the address as a function of the hold clock signal.

US Pat. No. 10,249,362

COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS

GSI Technology, Inc., Su...

1. A memory computation cell, comprising:a storage cell;
at least one read bit line;
an isolation circuit that buffers the storage cell from signals on the at least one read bit line, the isolation circuit having a read word line and a complementary read word line; and
wherein the memory cell is capable of performing an exclusive logic function when the memory cell is connected to the at least one read bit line with another memory cell and by turning on read word line or complementary read word line of one memory cell to have the exclusive logic result between the read word line and the storage cell data of the memory cell on the read bit line; and
wherein the read bit line is configured to provide read access to storage cell data.

US Pat. No. 10,249,361

SRAM WRITE DRIVER WITH IMPROVED DRIVE STRENGTH

NVIDIA CORPORATION, Sant...

1. A subsystem, comprising:a first bit line driver that drives a single bit line of a memory cell, writes a data bit to the memory cell, and includes:
a first field effect transistor (FET) that includes:
a first FET gate terminal that receives a first write select line as an input,
a first FET first data terminal that transmits a first data line that transports the data bit, and
a first FET second data terminal directly coupled to the first data line;
a second FET that includes:
a second FET pate terminal that receives the first write select line as an input, and
a second FET data terminal that is directly coupled to the first FET first data terminal; and
a first circuit element that includes:
a first input terminal directly coupled to the first FET first data terminal and the second FET data terminal, and
a first circuit data terminal that is directly coupled to the single bit line of the memory cell.

US Pat. No. 10,249,360

METHOD AND CIRCUIT FOR GENERATING A REFERENCE VOLTAGE IN NEUROMORPHIC SYSTEM

NATIONAL TSING HUA UNIVER...

1. A method for generating a reference voltage adapted for an artificial neural network system connected to a storage device with a memory cell array comprising a plurality of neurons arranged in a matrix and connected to a plurality of word-lines, respectively, the method comprising the steps of:arranging a first column of dummy neurons with weight 0 and a second column of dummy neurons with weight 1 with a number corresponding to a number of a row of the memory cell array;
connecting the plurality word-lines to the dummy neurons in the first and second columns, respectively;
disposing a bit-line connecting to a clamping circuit and the first column of dummy neurons;
disposing a complementary bit-line connecting to an adaptive header and the second column of dummy neurons;
connecting the clamping circuit and the adaptive header to a voltage source; and
connecting the bit-line to the complementary bit-line at an output end of the reference voltage;
wherein when the artificial neural network system is operated to sense the neurons of the memory cell array, one or more of the plurality of word-lines are activated, and the corresponding dummy neurons of the first column and the second column are activated to generate the reference voltage at the output end for sensing the neurons of the memory cell array.

US Pat. No. 10,249,357

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having a memory region and a peripheral region defined thereon, wherein the peripheral region comprises at least one transistor, the memory region comprises a plurality of memory cells, and each memory cell comprises at least one gate structure and a capacitor structure;
a mask layer disposed on the capacitor structure in the memory region; and
a dielectric layer disposed on the substrate within the peripheral region, wherein a top surface of the dielectric layer is aligned with a top surface of the mask layer.

US Pat. No. 10,249,356

MEMCAPACITIVE CROSS-BAR ARRAY FOR DETERMINING A DOT PRODUCT

HEWLETT PACKARD ENTERPRIS...

1. A memcapacitive cross-bar array for determining a dot product, comprising:a number of row lines;
a number of column lines intersecting the row lines to form a number of junctions;
a number of capacitive memory devices coupled between the row lines and the column lines at the junctions, the capacitive memory devices to:
receive a number of programming signals, the programming signals defining a number of values within a matrix, and
receive a number of vector signals as voltages inputted into the row lines, the vector signals defining a number of vector values to be applied to the capacitive memory devices; and
a charge collection line to collect charges as an output from the respective column lines of the capacitive memory devices, the collected charges equaling a dot product of the matrix values and vector values, wherein the collected charges are returned from the voltages inputted into the row lines.

US Pat. No. 10,249,355

APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS TO A COMMAND PATH CIRCUIT

Micron Technology, Inc., ...

1. An apparatus comprising:a command path circuit configured to receive a first command signal, the first command signal and a chip select signal provided to the apparatus, the command path circuit further configured to provide an output command responsive, at least in part, to a clock signal, and wherein the first command signal is provided during a command cycle, wherein the command cycle is a first number of clock cycles of the clock signal; and
a command path clock circuit coupled to the command path circuit and configured to, starting at a first clock cycle of the command cycle, provide the clock signal for a second number of clock cycles of the clock signal to the command path circuit responsive, at least in part, to the chip select signal and stopping provision of the clock signal after the second number of clock cycles, and wherein the second number of clock cycles of the clock signal is less than the first number of clock cycles of the clock signal.

US Pat. No. 10,249,353

MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS

Rambus Inc., Sunnyvale, ...

1. An Apparatus comprising:an interface circuit comprising:
a pad for coupling the apparatus to a data bus;
a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one first clock output to output a first phase adjusted clock signal; and
a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least one second clock output to output a second phase adjusted clock signal,
wherein the interface circuit uses the first phase adjusted clock signal to read data via the pad during a first read operation and uses the second phase adjusted clock signal to read data via the pad during a second read operation after the first read operation.

US Pat. No. 10,249,352

MEMORY DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory device comprising:a memory cell;
a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell;
a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse;
a hold circuit configured to hold a peak value of the second signal; and
a sense amplifier circuit configured to read data from the memory cell based on the peak value,
wherein the filter circuit comprises a high pass filter circuit, and
the first frequency domain is higher than a cutoff frequency of the filter circuit in the first signal.

US Pat. No. 10,249,351

MEMORY DEVICE WITH FLEXIBLE INTERNAL DATA WRITE CONTROL CIRCUITRY

Intel Corporation, Santa...

1. A memory controller, comprising:command logic to generate a write pattern command to trigger an associated dynamic random access memory (DRAM) device to write data to a memory array of the DRAM device without having to send the data to the DRAM device; and
I/O (input/output) circuitry including an interface to a command bus and to a data bus to the DRAM device, wherein the I/O circuitry is to drive the write pattern command to trigger the DRAM device to internally generate a write pattern to write, instead of data bits from the data bus, including to trigger the DRAM device to access the write pattern from a mode register, wherein the I/O circuitry is to send a mode register write command to the DRAM device to program the write pattern.

US Pat. No. 10,249,350

APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells;
a controller configured to operate sensing circuitry to:
perform a first XOR operation on a data value stored in a first memory cell and a data value stored in a second memory cell of a number of memory cells coupled to a sense line of the array that results in a first resultant value; and
perform a second XOR operation on the first resultant value and a data value stored in a third memory cell of the number of memory cells resulting in a second resultant value, wherein the second resultant value protects the data stored in the first memory cell, the data stored in the second memory cell, and the data stored in the third memory cell.

US Pat. No. 10,249,349

CONTROL SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a memory device including a first cell transistor; and
a controller configured to:
store information on a first temperature associated with a temperature of the memory device upon a write of data into the first cell transistor,
obtain a second temperature of the memory device,
determine an adjustment based on a combination of the first temperature and the second temperature, and
instruct the memory device to use a first parameter to read data from the first cell transistor, the first parameter being based on the determined adjustment.

US Pat. No. 10,249,348

APPARATUSES AND METHODS FOR GENERATING A VOLTAGE IN A MEMORY

Micron Technology, Inc., ...

1. An apparatus, comprising:a pull-up circuit configured to be coupled to a power supply and coupled to an output node at which an output voltage is provided;
a capacitance coupled to the output node and to a gate node of the pull-up circuit;
a pull-down circuit configured to be coupled to a reference voltage and coupled to the output node;
an input circuit coupled to the output node and to a gate node of the pull-down circuit, the input circuit configured to receive an input voltage;
a first transistor coupled to the gate node of the pull-up circuit and to the gate node of the pull-down circuit, the first transistor configured to receive a first bias signal; and
a second transistor coupled to the gate node of the pull-up circuit and to the gate node of the pull-down circuit, the second transistor configured to receive a second bias signal.

US Pat. No. 10,249,346

POWER SUPPLY AND POWER SUPPLYING METHOD THEREOF FOR DATA PROGRAMMING OPERATION

Winbond Electronics Corp....

1. A power supply for data programming operation, adapted for a memory apparatus, comprising:a plurality of charge pump circuits, commonly generating an output voltage for programming a write data to the memory apparatus, wherein each of the charge pump circuits comprises:
a plurality of charge pump units coupled in series; and
a switch, coupled between a last stage charge pump unit and output ends of the charge pump circuits, and controlled by a corresponding bit of the write data to be turned-on or cut-off, wherein the output voltage is output to the output ends of the charge pump circuits when the switch is turned on, and the output voltage is not output to the output ends of the charge pump circuits when the switch is cut off,
wherein number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.

US Pat. No. 10,249,345

MEMORIES HAVING SELECT DEVICES BETWEEN ACCESS LINES AND IN MEMORY CELLS

Micron Technology, Inc., ...

1. A memory, comprising:a first bi-directional diode connected between a first access line and a second access line;
a second bi-directional diode connected between a third access line and a fourth access line; and
a plurality of memory cells;
wherein each memory cell of the plurality of memory cells comprises a respective third bi-directional diode, of a plurality of third bi-directional diodes, and a respective programmable element, of a plurality of programmable elements, connected in series;
wherein each memory cell of a first subset of the plurality of memory cells is connected between the second access line and a respective fifth access line of a plurality of fifth access lines;
wherein each memory cell of a second subset of the plurality of memory cells, mutually exclusive of the first subset of the plurality of memory cells, is connected between the fourth access line and a respective fifth access line of the plurality of fifth access lines; and
wherein the first bi-directional diode, the second bi-directional diode, and each third bi-directional diode of the plurality of third bi-directional diodes are configured to be biased in a same direction in response to a particular bias applied to the first access line and to the third access line and a different bias applied to each fifth access line of the plurality of fifth access lines.

US Pat. No. 10,249,344

TAPE DRIVE CORROSION PROTECTION

International Business Ma...

1. A method for corrosion protection of a tape drive based on a tape drive corrosion protection system, the system comprising the tape drive, a temperature sensor, a heating entity and a controller for activating the heating entity, said method comprising:determining, via a humidity sensor, humidity information;
establishing, via the temperature sensor, temperature information indicative of a temperature in an area of, or within, the tape drive;
receiving the temperature information at the controller; and
activating the heating entity in a manner dependent on the temperature information established via the temperature sensor in order to prevent corrosion within the tape drive, said activating the heating entity being in response to a determination that the humidity information determined via the humidity sensor indicates that the relative humidity is above a specified relative humidity threshold value and the established temperature information indicates a temperature drop above a specified temperature drop value within a specified period of time.

US Pat. No. 10,249,343

HARD DISK DRIVE HOLDER

Lite-On Electronics (Guan...

1. A hard disk drive holder, comprising:a bottom plate, wherein a plurality of gaps and a first bending line define a bendable portion and an unbendable portion on the bottom plate;
a first side plate, having a plurality of first positioning portions; and
a second side plate, having a plurality of second positioning portions, wherein the first side plate and the second side plate are respectively and integrally connected to opposite sides of the bottom plate, and the first positioning portions and part of the second positioning portions are correspondingly disposed to be adapted to install a first hard disk drive,
wherein the bendable portion has a plurality of third positioning portions, the third positioning portions and part of the second positioning portions are correspondingly disposed to be adapted to install at least one second hard disk drive, and a size of the at least one second hard disk drive is less than a size of the first hard disk drive.

US Pat. No. 10,249,342

BASE UNIT, DISK DRIVE APPARATUS, AND METHOD OF MANUFACTURING BASE UNIT

NIDEC CORPORATION, Kyoto...

1. A base unit comprising:a connector electrically connected to a motor having a central axis extending in a vertical direction, the connector including a board portion and an electrode terminal;
a motor support portion arranged to support the motor; and
a connector support portion arranged to support the board portion of the connector; wherein
the connector support portion includes:
a bottom plate portion arranged to extend perpendicularly to the central axis, and arranged to support a lower surface of the board portion;
a window portion arranged to pass through the bottom plate portion in an axial direction, and arranged to cover or overlap with the electrode terminal of the connector when viewed in the axial direction;
a first recessed portion defined in an upper surface of the bottom plate portion around the window portion, and arranged to overlap with the lower surface of the board portion when viewed in the axial direction; and
a second recessed portion defined in the upper surface of the bottom plate portion, and arranged to be spaced apart from the first recessed portion;
the first recessed portion has a thermosetting adhesive arranged therein to fix the bottom plate portion and the board portion to each other; and
the second recessed portion has a temporarily fixing adhesive arranged therein to temporarily fix the bottom plate portion and the board portion to each other.

US Pat. No. 10,249,340

VIDEO GENERATION DEVICE, VIDEO GENERATION PROGRAM, AND VIDEO GENERATION METHOD

1. A video generation device comprising:a memory storing a video generation program; and
a central control unit for performing a control to extract multiple occurrences of valid line-of-sight information included in a reproduction sequence upon executing the video generation program, to select a plurality of frames relating to the multiple occurrences of line-of-sight information, so that a constant number of frames will exist between a pair of the occurrences of line-of-sight information, to extract multiple occurrences of stroke information relating to the selected frames in a number adjusted so as to keep constant the number of frames between the pair of occurrences of line-of-sight information, to renew an omnidirectional image based on the line-of-sight information and drawing attribute where the stroke information includes the drawing attribute, to generate new line-of-sight information in an interpolated manner based on the extracted line-of-sight information, adjacent line-of-sight information, and the position of the extracted frame, upon completion of extraction of the entire stroke information relating to the selected frame, to make drawing the omnidirectional image on a screen image based on the interpolated line-of-sight information, and to write the screen image as an image of the selected frame.

US Pat. No. 10,249,339

READ-AFTER-WRITE METHODOLOGY USING MULTIPLE ACTUATORS MOVEABLE OVER THE SAME MAGNETIC RECORDING DISK SURFACE

Seagate Technology LLC, ...

1. An apparatus, comprising:one or more magnetic recording disks coupled to a spindle motor, each of the disks having opposing recording surfaces;
two or more actuators that independently move over at least a first recording surface of the one or more disks;
a first actuator of the two or more actuators comprising a first write head and a first read head;
a second actuator of the two or more actuators comprising at least a second read head; and
a controller coupled to the two or more actuators and configured to:
write data to a track on the first recording surface using the first write head;
within one revolution of the first recording surface after the data is written to the track, perform a read operation on the data written to the track using the second read head; and
verify that the data was successfully written to the track by the first write head in response to the read operation performed by the second read head.

US Pat. No. 10,249,338

SHINGLED MAGNETIC RECORDING STORAGE SYSTEM DURING VIBRATION

SEAGATE TECHNOLOGY, LLC, ...

1. A method comprising:receiving a write command to write data on a first track in a band of a storage medium;
skipping the first track responsive to determining a number of vibration events is above a vibration predetermined threshold;
seeking to a second track adjacent to the first track; and
increasing an on-cylinder limit (OCLIM) on the second track adjacent to the first track from a default OCLIM to an increased OCLIM.

US Pat. No. 10,249,336

ARCHITECTURE FOR METAL-INSULATOR-METAL NEAR-FIELD TRANSDUCER FOR HEAT-ASSISTED MAGNETIC RECORDING

Western Digital Technolog...

1. A heat-assisted magnetic recording (HAMR) device, comprising:a waveguide; and
a near-field transducer (NFT) coupled to the waveguide in a direct-fire configuration, the NFT comprising an insulator core encased in a metal portion, the metal portion comprising a plasmonic metal,
wherein:
the insulator core comprises a rectangular portion and a tapered portion, and
the rectangular portion is between the waveguide and the tapered portion.

US Pat. No. 10,249,335

COMPOSITE HAMR MEDIA STRUCTURE FOR HIGH AREAL DENSITY

Seagate Technology LLC, ...

1. An apparatus comprising a data storage medium having an exchange coupled composite (ECC) structure comprising a coupling layer (ECL) contacting and disposed between a storage layer and a write layer, the storage layer having a lower Curie temperature and a higher anisotropy than the respective ECL and write layers, the ECL coupling the write layer to the storage layer with a coupling strength from 0.1 Jex/Jo to 0.6 Jex/Jo.

US Pat. No. 10,249,333

SINGLE RH LAYER OPTICAL FIELD ENHANCER WITH PRE-FOCUSING STRUCTURES

Headway Technologies, Inc...

1. A TAMR (Thermally Assisted Magnetic Recording) write head comprising:a magnetic writer structure having a tapered main write pole section emerging at a distal ABS (Air-Bearing Surface) and configured to write on a magnetic recording medium when said magnetic recording medium has been properly activated thermally by plasmon near-field energy; and
a structure comprising small, weakly plasmonic elements, wherein said elements are not subject to thermal deformations and recessions from said ABS yet are an efficient source of said plasmon near-field energy when excited by pre-focused optical energy provided by a system comprising:
a waveguide, having a horizontally (x-y plane) tapered dielectric waveguide core, formed adjacent to and aligned along (y-direction) said main write pole and configured for directing pre-focused optical energy at a configuration of weakly plasmonic patterned layers comprising an upper layer and a lower layer; wherein
a stratified, highly plasmonic film is formed between said waveguide and said tapered main pole and is separated from said main pole by a weakly plasmonic layer that extends distally to contact said upper layer of said configuration of weakly plasmonic patterned layers and wherein said stratified, highly plasmonic film is separated from said waveguide core by a dielectric layer, wherein a distal edge of said stratified, highly plasmonic film terminates at a distance from said ABS and is thereby recessed from said ABS; wherein
said configuration of weakly plasmonic patterned layers formed between said distal edge of said stratified film and said ABS includes said upper layer and, beneath said upper layer is a lower layer contacting said upper layer and wherein said distal edge of said stratified highly plasmonic film contacts a proximal edge of said upper layer of said patterned configuration; wherein
a downward sloping distal face of said waveguide conformally abuts a complementary sloped edge of a waveguide blocker formed of weakly plasmonic material; and wherein
said downward sloping distal face of said waveguide is separated from said complementary sloped edge of said waveguide blocker by a uniform layer of dielectric material; and
a pair of optical side shields formed of weakly plasmonic material is laterally and symmetrically disposed to either side of said waveguide, and wherein;
said lower layer of said configuration of weakly plasmonic patterned layers is an optical field enhancer (OFE) with a distally emerging peg, said OFE having a patterned shape that coincides with a shape of said pre-focused electromagnetic field.

US Pat. No. 10,249,332

MICROWAVE-ASSISTED MAGNETIC RECORDING APPARATUS AND METHOD

Seagate Technology LLC, ...

1. An apparatus, comprising:a magnetic recording medium having a recording surface comprising a first recording layer having a first ferromagnetic resonant frequency and a second recording layer having a second ferromagnetic resonant frequency, the first recording layer configured for storing user data and the second recording layer configured for storing servo data; and
a recording head arrangement configured for microwave-assisted magnetic recording (MAMR) and writing user data to the first recording layer, the recording head arrangement comprising:
a write pole configured to generate a write magnetic field;
a write-assist arrangement proximate the write pole, the write-assist arrangement configured to generate a radiofrequency assist magnetic field at a frequency that corresponds to the first ferromagnetic resonant frequency; and
a reader configured to read combined signals from the first and second recording layers.

US Pat. No. 10,249,331

METHOD OF MANUFACTURING A WIRING STRUCTURE OF A HEAD SUSPENSION

NHK SPRING CO., LTD., Ka...

1. A method of manufacturing a wiring structure of a head suspension including a flexure that supports a head used to write and read data to and from a recording medium and is attached to a load beam applying load onto the head, the wiring structure comprising write wiring and read wiring formed on the flexure and connected to the head, each having wires of opposite polarities and a stacked interleaved part provided at least for the write wiring, the stacked interleaved part including segments electrically connected to the respective wires of the write wiring at both ends in each segment, the segments stacked on and facing the wires of the write wiring through an intermediate insulating layer so that the facing wire and segment have opposite polarities to interleave at least the write wiring at the stacked interleaved part, the method comprising:a wiring step of forming the wires of the opposite polarities of the write wiring on a base insulating layer and forming a respective wire side-arm branching from each of the wires formed on the base insulating layer;
an insulating layer forming step of forming the intermediate insulating layer on the wires and the wire side-arms and forming the conductors on the wires and the wire side-arms, respectively so that the conductors pass through the intermediate insulating layer and are exposed at a surface of the electrical insulating layer; and
a stacked interleaved part forming step of forming segments of opposite polarities of the stacked interleaved part on the electrical insulating layer so that each segment spans between the conductors on the wire side-arm and the wire having a same polarity and electrically connected to said conductors.

US Pat. No. 10,249,330

METHODS AND SYSTEMS FOR DETECTING ESD EVENTS IN CABLED DEVICES

International Business Ma...

1. An audit device, comprising:a substrate;
at least one test element coupled to the substrate;
a connector configured to couple the at least one test element to leads of a cable; and
a probe for detecting voltage across and/or current through the at least one test element,
wherein one test element is coupled to a group of leads of the connector, the group of leads comprising a plurality of positive polarity leads and a plurality of negative polarity leads,
wherein all positive polarity leads of the group of leads are electrically coupled together on the substrate, and
wherein all negative polarity leads of the group of leads are electrically coupled together on the substrate,
such that the test element is coupled across the positive and the negative polarity leads of the group of leads of the connector,
wherein the test element is coupled across pairs of leads of the cable when the cable is coupled to the connector,
wherein the at least one test element is a resistor or a resistance-inductance-capacitance (RLC) circuit having an equivalent circuit value to a device under test, and
wherein the at least one test element is tunable such that the at least one test element is capable of matching the equivalent circuit value in a predetermined frequency range.

US Pat. No. 10,249,327

DISK DEVICE, CONTROLLER CIRCUIT, AND CONTROL METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A disk device comprising:a recording medium on which data is recorded;
a decoding circuit configured to decode data read from the recording medium; and
a control circuit configured to cause first data associated with a target sector referenced in a read request to be read from a target track of the recording medium, second data associated with a non-target sector that is not referenced in the read request to be read from the recording medium after the first data is read from the recording medium, and decoding of the first data to be completed by the decoding circuit after the second data is read from the recording medium, wherein
the decoding circuit is configured to execute a first decoding process on the first data based on data from the target sector and not on data from any other sector of the target track and a second decoding process on the first data based on data from each sector of the target track, and
the control circuit is configured to perform the second decoding process on the first data when the first decoding process fails to decode the first data.

US Pat. No. 10,249,325

PITCH DETECTION ALGORITHM BASED ON PWVT OF TEAGER ENERGY OPERATOR

OmniSpeech LLC, College ...

1. A method of a pitch detection comprising:sampling a signal to generate a first discrete time signal;
applying a Teager Energy Operator (TEO) to the first discrete time signal to generate a second discrete time signal;
generating a first complex valued signal from the first discrete time signal;
generating a second complex valued signal from the second discrete time signal;
computing a Pseudo Weigner Ville Transformation (PWVT) on the first complex valued signal to generate a first spectral representation of the signal;
computing a PWVT on the second complex valued signal to generate a second spectral representation of the signal;
generating a combined spectral representation from the first spectral representation and the second spectral representation;
computing, to generate a pitch candidate, a harmonic summation on at least one of the combined spectral representation and the first spectral representation; and
deciding the pitch candidate as a pitch value if the pitch candidate is larger than a threshold.

US Pat. No. 10,249,324

SOUND PROCESSING BASED ON A CONFIDENCE MEASURE

Cochlear Limited, Macqua...

1. A method, comprising:receiving a plurality of input signals each representing a spectral component of one or more sounds;
determining a speech importance of each of a plurality of the spectral components;
determining confidence measures for each of a plurality of noise-component estimates generated for each of the plurality of spectral components;
based on the speech importance of each of the plurality of the spectral components and based on the confidence measures generated for each of a plurality of noise-component estimates, selecting one or more of the input signals as selected input signals; and
processing the selected input signals to generate stimulation for delivery to a recipient of a hearing prosthesis.