US Pat. No. 10,193,203

STRUCTURES AND METHODS FOR INTERCONNECTS AND ASSOCIATED ALIGNMENT AND ASSEMBLY MECHANISMS FOR AND BETWEEN CHIPS, COMPONENTS, AND 3D SYSTEMS

NUVOTRONICS, INC, Radfor...

13. A microstructure, comprising:a first microstructural element having a plurality of fused layers of a material, each layer parallel to an upper surface of the first microstructural element, the first microstructural element having a first mating edge;
a second microstructural element having a plurality of fused layers of a material, each layer parallel to an upper surface of the second microstructural element, the second microstructural element having a second mating edge, the second mating edge disposed adjacent the first mating edge; and
a jumper having a plurality of fused layers of a material, the jumper disposed at the upper surfaces of the first and second microstructural elements at a location spanning the first and second mating edges and attached to each of the first and second microstructural elements to join the first and second microstructural elements to one another, wherein the first microstructural element includes an opening disposed therein in registration with a corresponding feature of the jumper.

US Pat. No. 10,193,201

SYSTEM AND METHOD FOR CONTROLLING OPERATION OF A METAL-AIR BATTERY

PHINERGY LTD., Lod (IL)

1. A method of controlling operation of a metal-air battery, the method comprising:controlling a current drawn from the metal-air battery and a temperature of the metal-air battery by controlling a temperature of electrolyte included in the metal-air battery and by controlling a circulation of the electrolyte included in the metal-air battery until the metal-air battery operates according to a profile,
wherein the profile defines at least one of: an energetic utilization ratio, power, an electrolyte utilization value and a corrosion rate.

US Pat. No. 10,193,200

BATTERY MODULE AND BATTERY PACK COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A battery module, comprising:a cell assembly including a plurality of secondary batteries and having a fluid path formed between the secondary batteries, the cell assembly having a bottom surface, an upper surface, and side surfaces extending between the bottom surface and the upper surface;
an inlet duct located at one side surface of the cell assembly so as to cover the one side surface of the cell assembly, and having an inlet port such that the fluid introduced through the inlet port flows into the fluid path;
an outlet duct located at another side surface of the cell assembly so as to cover the another side surface of the cell assembly, and having an outlet port such that the fluid discharged from the fluid path flows out through the outlet port; and
an entrance cover installed to at least one of the inlet port and the outlet port, and having a plurality of ribs formed in a plate shape and slantly arranged relative to the bottom surface of the cell assembly so that the ribs are inclined with a predetermined angle from a direction parallel to the bottom surface of the cell assembly, the plurality of ribs extending from one side of an opening in the entrance cover to another side of the opening in the entrance cover,
wherein at least one of inner ends closest to the cell assembly and outer ends furthest from the cell assembly of at least one rib of the plurality of ribs is bent in a direction perpendicular to the bottom surface of the cell assembly, and
wherein the inner and outer ends of the rib are bent in opposite directions.

US Pat. No. 10,193,199

BATTERY SYSTEM

ARCIMOTO, INC., Eugene, ...

1. A battery enclosure, comprising:a pair of opposing enclosure portions that collectively define a battery region, each enclosure portion including:
a first segment that includes a plurality of fluid pathways spaced apart from each other, the first segment forming a notched region at a distal end of the first segment;
a second segment that joins the first segment at an interface opposite a distal end of the first segment, the second segment being orthogonal to the first segment, the second segment forming a flange at a distal end of the second segment opposite the interface;
a first wall interfacing with a first edge of the pair of opposing enclosure portions to further collectively define the battery region, an inner face of the first wall including a first set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of a first enclosure portion of the pair of enclosure portions along the first edge, the first wall including a second set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of a second enclosure portion of the pair of enclosure portions along the first edge, at least some of the first set of the plurality of openings and at least some of the second set of the plurality of openings joining each other within the first wall via fluid pathways formed therein; and
a second wall interfacing with a second edge of the pair of opposing enclosure portions opposite the first edge to further collectively define the battery region, an inner face of the second wall including a third set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of the first enclosure portion of the pair of enclosure portions along the second edge, the second wall including a fourth set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of the second enclosure portion of the pair of enclosure portions along the second edge, at least some of the third set of the plurality of openings and at least some of the fourth set of the plurality of openings joining each other within the second wall via fluid pathways formed therein;
wherein each notched region of each enclosure portion accommodates the flange of the other enclosure portion.

US Pat. No. 10,193,197

BATTERY DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A battery device, comprising:a battery for supplying electric power to a motor for driving a vehicle;
a first cooling system having a first cooling fan for supplying cooling air to a first cooling channel of the battery and a first temperature sensor for detecting first cooling air temperature at an inlet of the first cooling channel;
a second cooling system having a second cooling fan for supplying cooling air to a second cooling channel of the battery and a second temperature sensor for detecting second cooling air temperature at an inlet of the second cooling channel; and
a controller for receiving a detection value from each of the first and second temperature sensors,
wherein the controller makes abnormality determination of determining that temperature characteristic of the first or second temperature sensor is abnormal when a difference between the first cooling air temperature and the second cooling air temperature, detected by the first temperature sensor and the second temperature sensor, respectively, after elapse of a predetermined set period after a start switch of the vehicle is turned off while the first cooling fan and the second cooling fan remain stopped, is equal to or greater than a predetermined amount.

US Pat. No. 10,193,196

INTERNAL BATTERY CELL COOLING WITH HEAT PIPE

MAINSTREAM ENGINEERDING C...

1. A battery cooling system, comprising at least one battery cell within a case, and a two-phase flow device having evaporator portion located centrally within and electrically isolated from the at least one battery cell, wherein the at least one battery cell wraps completely around an entire perimeter of the evaporator portion.

US Pat. No. 10,193,195

CHARGING CONDITION CONTROL APPARATUS AND BATTERY PACK

KABUSHIKI KAISHA TOSHIBA,...

1. A charging condition control apparatus, comprising:a measurement unit configured to measure a present battery capacity of a secondary battery;
an estimation unit configured to estimate a present end-of-charge potential of an anode of the secondary battery based on the present battery capacity and an open circuit potential curve of the anode;
a calculation unit configured to calculate a differential potential between the present end-of-charge potential and an initial end-of-charge potential of the anode; and
a control unit configured to control a charging condition of the secondary battery according to the differential potential,
wherein the estimation unit estimates the present end-of-charge potential by calculating a depth of charge of the anode based on the present battery capacity and an initial battery capacity and by retrieving a potential corresponding to the depth of charge from the open circuit potential curve.

US Pat. No. 10,193,193

STRUCTURE OF BATTERY PROTECTION CIRCUIT MODULE PACKAGE COUPLED WITH HOLDER, AND BATTERY PACK HAVING SAME

ITM SEMICONDUCTOR CO., LT...

1. A structure of a battery protection circuit module package coupled with a holder, the structure comprising:a basic package comprising a lead frame consisting of a plurality of leads spaced apart from each other, and protection circuit elements provided on the lead frame without use of a printed circuit board; and
an encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a melt of resin into the first injection mold to perform an insert injection molding process,
wherein the encapsulant encapsulates the protection circuit elements to expose part of the lead frame,
wherein the encapsulant and the basic package configure the battery protection circuit module package, and
wherein the holder is coupled to the battery protection circuit module package by the insert injection molding process.

US Pat. No. 10,193,192

STRUCTURE FOR MODULATING THE VOLTAGE OF A BATTERY AND THE ACTIVE EQUILIBRATION THEREOF

RENAULT s.a.s., Boulogne...

1. An assembly comprising:a motor;
an accumulator battery comprising:
a plurality of electrical energy storage cells that convert chemical energy to electrical energy by way of an electrochemical oxidation-reduction reaction, the cells being grouped together as composite cells of an even number of cells and the composite cells connected in series with one another; and
an electrical network which connects the cells to one another, the electrical network comprising:
means of connection of the cells of each composite cell in parallel and in series, and
means for controlling the means of connection, configured to connect the cells of each composite cell in parallel or in series; and
a controller including a database register,
wherein the controller acquires a rotation speed and a current for the motor corresponding to an optimal voltage based on the database register and controls the electrical network so that a voltage across terminals of the accumulator battery is equal to the optimal voltage.

US Pat. No. 10,193,191

ELECTRICAL SYSTEM WITH BATTERY MODULE AND COVER ASSEMBLY PROVIDING BUILT-IN CIRCUIT PROTECTION

GM Global Technology Oper...

9. An electrical system comprising:a battery module having a pack section and a cover assembly connected to the pack section;
a direct current (DC) voltage bus; and
at least one high-voltage component connected to the battery module via the DC voltage bus;
wherein the pack section includes an interconnect board, a plurality of conductive channels each forming an elongated U-shape or L-shaped bus bar, and a plurality of battery cells each having at least one electrode cell tab extending orthogonally through the interconnect board, each of the battery cells being disposed behind the interconnect board, the at least one electrode cell tab joined to a corresponding one of the conductive channels, and wherein the cover assembly includes a cover plate and a plurality of conductive interconnect members, a plurality of electrical fuses, and a plurality of sense lines built into or integral with the cover plate, the conductive interconnect members protruding orthogonally outward from the cover plate and forming part of an electrical circuit between the conductive channels of the pack section and the fuses and sense lines of the cover plate when the cover assembly is connected to the pack section.

US Pat. No. 10,193,189

BATTERY CELL

HYUNDAI MOTOR COMPANY, S...

1. A battery cell comprising:an electrode assembly;
a pouch which wraps around the electrode assembly;
an electrode tab extending from the electrode assembly;
a lead tab attached to the electrode tab; and
a current interrupt device comprising a fusing unit and an insulating layer wrapping around the fusing unit,
wherein the fusing unit comprises a top surface and a bottom surface, wherein the top surface of the fusing unit is attached to a bottom surface of the lead tab, and the bottom surface of the fusing unit is attached to a top surface of the electrode tab, wherein the top surface of the fusing unit has a bond strength greater than that of the bottom surface of the fusing unit.

US Pat. No. 10,193,186

ELECTROLYTE ADDITIVE FOR LITHIUM-ION BATTERY

1. An electrolyte for a lithium-ion battery comprising at least one block copolymer, wherein said block copolymer comprises at least one polymeric segment A which is soluble in said electrolyte and at least one polymeric segment B having a temperature for dissolution “T” in said electrolyte, the polymeric segments A and B being present in amounts sufficient to make possible an increase in the viscosity of the electrolyte at a temperature greater than or equal to the temperature “T”, and then the return of the electrolyte to a liquid state when the temperature of the electrolyte falls back below T,wherein the block copolymer comprises at least one polymeric segment A chosen from the following polymers: polyacrylates, polymethacrylates, polycarbonates, polyester carbonates, polylactones, polylactams, polyesters, polyethers, soluble homopolymers and random copolymers of polyethers,
wherein the block copolymer comprises at least one polymeric segment B obtained from at least one monomer chosen from the following monomers: acrylic and methacrylic acids, N-alkylacrylamides or N-alkylmethacrylamides saccharides, vinylidene fluoride or hexafluoropropylene,
wherein the at least one polymeric segments B/ the at least one polymeric segments A molar ratio being greater than 0.5, and
wherein the electrolyte comprises at least one lithium salt and at least one organic solvent chosen from ethylene carbonate, propylene carbonate, dimethyl carbonate, ethyl methyl carbonate, diethyl carbonate, tetrahydrofuran, tetraethylene glycol dimethyl ether, dimethyl ether, dioxolane, dioxane, polyethylene glycol dimethyl ether and/or nitriles or their mixture(s).

US Pat. No. 10,193,185

SULFIDE SOLID ELECTROLYTE MATERIAL AND LITHIUM SOLID STATE BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A sulfide solid electrolyte material comprising an ion conductor having an anion structure of an ortho-composition with a ratio of 70 mol % or more to all anion structures, and LiI,wherein the ion conductor contains oxygen, and
the sulfide solid electrolyte material contains substantially no Li2S and cross-linking sulfur, and
the sulfide solid electrolyte material does not have a peak of Li2S in an XRD measurement using a Cuk? ray.

US Pat. No. 10,193,184

LITHIUM ION SECONDARY BATTERY AND METHOD FOR MANUFACTURING SAME

NEC ENERGY DEVICES, LTD.,...

1. A method for manufacturing a lithium ion secondary battery, the lithium ion secondary battery comprising a positive electrode and a negative electrode disposed with a separator sandwiched therebetween and contained together with an electrolytic solution in an outer case including a flexible film, whereina quantity of dissolved nitrogen in the electrolytic solution in injecting the electrolytic solution into the outer case is 100 ?g/mL or less, the quantity being 5 ?g/mL or more.

US Pat. No. 10,193,182

NON-AQUEOUS ELECTROLYTE AND LITHIUM SECONDARY BATTERY COMPRISING SAME

LG Chem, Ltd., (KR)

1. A non-aqueous electrolyte solution for a lithium secondary battery, comprising an electrolyte salt and an organic solvent,wherein the non-aqueous electrolyte solution further comprises a cyano group-containing pyrimidine-based compound represented by the following formula 1, and
the cyano group-containing pyrimidine-based compound is present in an amount of 1 to 20 parts by weight per 100 parts by weight of the organic solvent:

where R1, R2, R3 and R4 are each independently hydrogen, a cyano group, halogen, a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, or a substituted or unsubstituted alkoxy group having 1 to 10 carbon atoms, in which at least one of R1, R2, R3 and R4 is a cyano group.

US Pat. No. 10,193,181

PRESSURIZATION DEVICE FOR BATTERY CELLS

Nissan Motor Co., Ltd., ...

1. A pressurization device for battery cells, comprising:battery cells stacked in a thickness direction, wherein each of the battery cells has a flat shape in the thickness direction, and wherein each of the battery cells includes:
an exterior body made of a laminated film; and
a power generation element sealed with a liquid electrolyte inside the exterior body;
a housing accommodating the battery cells;
spacers arranged in the thickness direction, supported by the housing and forming bag shapes which have an expanded state and a contracted state in at least the thickness direction in accordance with fluid pressure of fluid sealed inside the spacers, wherein each of the battery cells contacts at least a portion of an adjacent spacer; and
a pressure supply passage used for supplying the fluid to the spacers from a fluid pressure source;
wherein when the spacers are in the contracted state, a space exists between adjacent battery cells, each space having a dimension in the thickness direction that is larger than a thickness of each of the battery cells; and
when the spacers are in the expanded state, each of the battery cells are pressurized in the thickness direction.

US Pat. No. 10,193,180

METHOD FOR MANUFACTURING LAMINATED ELECTRICAL STORAGE DEVICE

MURATA MANUFACTURING CO.,...

1. A method for manufacturing a laminated electrical storage device, the method comprising:heating an external terminal by a heater that is not in contact with the external terminal and is provided so as to be opposed to a first principal surface of the external terminal that extends from a laminated case, wherein the terminal has principal surfaces and secondary surfaces, the principal surfaces being wider than the secondary surfaces; and
pressing opposed laminate films of the laminate case with a heated thermocompression bonding jig so as to thermocompression-bond each of the opposed laminate films to the external terminal and seal the laminate case.

US Pat. No. 10,193,179

FUEL CELL STACK

NISSAN MOTOR CO., LTD., ...

1. A fuel cell stack, comprising:a stacked plurality of single cells each comprising a frame supporting a periphery of a membrane electrode assembly and a pair of separators holding the frame therebetween; and
a sealing member disposed between the plurality of single cells,
wherein the pair of separators comprises respective supporting portions which are in contact with the frame, in which a sealing member is disposed on one of the supporting portions, a supporting portion of one separator has a different size from a supporting portion of the other separator,
an overlapped portion is formed in which a base surface where the supporting portion of one separator is in contact with the frame is overlapped with a top surface where the supporting portion of the other separator is in contact with the frame in a stacking direction, and
the overlapped portion receives and transmits reaction force of the sealing member between the single cells.

US Pat. No. 10,193,178

REDOX FLOW BATTERY FRAME BODY, REDOX FLOW BATTERY, AND CELL STACK

Sumitomo Electric Inductr...

1. A frame body for a redox flow battery comprising a window,wherein the expressions A>C, B>D, and (B/A)?0.2 are satisfied, where A represents the length of a long side of a rectangle that envelops the window, B represents the width of a horizontal frame of the frame body corresponding to the long side, C represents the length of a short side of the rectangle, and D represents the width of a vertical frame of the frame body corresponding to the short side,
wherein the expression (D/C)?0.2 is satisfied.

US Pat. No. 10,193,177

FUEL CELL SYSTEM AND OPERATING METHOD THEREFOR

NISSAN MOTOR CO., LTD., ...

1. A residual water purge control system for a fuel cell system having a fuel cell stack that generates electrical power by electrochemical reaction of fuel and oxidant, a residual water estimating apparatus, and a residual water purge control device, the residual water estimating apparatus comprising:a total generated electrical energy storage device that stores a value representing the total generated electrical energy of the fuel cell stack in the period from start-up to shutdown of power generation; and
a controller that is programmed to estimate a residual water volume that can be absorbed by a membrane electrode assembly of the fuel cell stack from a first control map that indicates a relationship between the residual water volume and said stored value in said total generated electrical energy storage device;
wherein when the stored value in said total generated electrical energy storage device is below a first prescribed level corresponding to a maximum of the residual water volume, said controller is programmed to estimate the residual water volume to be proportional to said stored value; and, when said stored value exceeds the first prescribed level, said controller is programmed to estimate the residual water volume to be inversely proportional to an increase in said stored value with respect to the first prescribed level; and
wherein when said stored value exceeds a second prescribed level larger than the first prescribed level, said controller estimates the residual water volume to be substantially constant; and
wherein the residual water purge control device is programmed to control a purging volume of the residual water purge control system based on the estimated residual water volume after the residual water has been estimated by the controller.

US Pat. No. 10,193,176

SYSTEM AND METHOD FOR PRODUCTION OF ULTRA-PURE HYDROGEN FROM BIOMASS

The Research Foundation f...

1. An ultra-pure hydrogen synthesis system which comprises:a gasifier;
an oils and tars filtration system;
a steam generator;
a water gas shift reactor containing a catalyst, comprising oxides of copper, zinc and aluminum, that facilitates one or more chemical reactions between carbon monoxide and water in a temperature range of approximately 200° C. to approximately 250° C.;
a heat-exchange two-phase water condenser and separator;
a liquid-based, bubbling scrubber wherein a liquid contained within the scrubber includes
a methanol suspension of copper (I) chloride particles;
a hydrogen separator;
one or more fluid conduits, wherein the one or more fluid conduits connect to and establish fluid communication between each of the gasifier, the oils and tars filtration system, the steam generator, the water gas shift reactor, the scrubber, and the hydrogen separator.

US Pat. No. 10,193,175

PROCESS FOR SUPPLYING A FUEL CELL HAVING ALTERNATE SUPPLY AND PURGE PHASES

1. A process for supplying a fuel cell comprising a stack of electrochemical cells divided into N groups of cells, where N?2, with reactive species diluted in a carrier gas, the process comprising:(I) supplying a selected group of cells from the N groups with the reactive species diluted in the carrier gas, wherein the reactive species not consumed in the selected group of cells circulates in the other groups of cells via distribution lines that ensure fluidic communication among the N groups of cells and that are arranged so as to form a fluidic pathway for the reactive species to go from the selected group of cells to one or more last groups of cells forming an end of the fluidic pathway,
(II) purging the N groups of cells after the supplying (I) by simultaneously supplying each of the N groups of cells with the reactive species, wherein each group of cells communicates with an outlet orifice of the fuel cell that enables fluidic discharging of the N groups of cells, and
(III) subsequently repeating the supplying (I) followed by the purging (II) so that the purging (II) is performed between two successive supplyings (I), wherein selected groups of cells in the two successive supplyings (I) are different.

US Pat. No. 10,193,174

FUEL CELL INTERNAL STATE DETECTION SYSTEM AND STATE DETECTION METHOD

NISSAN MOTOR CO., LTD., ...

1. A fuel cell internal state detection system for detecting an internal state of a fuel cell on the basis of an impedance value of the fuel cell, comprising a controller programmed to:set an estimation object state quantity as an index of the internal state;
obtain the impedance value of the fuel cell;
judge whether or not the obtained impedance value is usable for a calculation of the estimation object state quantity;
calculate the estimation object state quantity set by the controller on the basis of the obtained impedance value when the impedance value is judged to be usable for the calculation of the estimation object state quantity by the controller;
perform an unusable-scene process when the impedance value is judged not to be usable for the calculation of the estimation object state quantity by the controller;
obtain impedance values based on three or more frequencies; and
determine whether at least one of three or more obtained impedance values belongs to an arc region or to a non-arc region in an impedance curve on a complex plane and judging whether or not the impedance value is usable according to the determination result.

US Pat. No. 10,193,173

ELECTROCHEMICAL HYDROGEN SENSOR FOR GLOBAL/LOCAL HYDROGEN STARVATION DETECTION IN PEM FUEL CELLS

GM Global Technology Oper...

1. A fuel cell system hydrogen starvation detection device, the device comprising:at least one sensor signally cooperative with at least one of an anode and cathode flowpaths within the system, the sensor comprising:
a first electrode configured to generate a first signal that corresponds to a substantially pure concentration of hydrogen; and
a second electrode configured to receive a second signal that corresponds to local hydrogen concentration within the anode flowpath such that a comparison of the first and second signals provides indicia to a controller of a hydrogen starvation condition within a fuel cell stack; and
a voltage source cooperative with the first electrode, the voltage source configured to provide a voltage sufficient to promote at least one reaction that generates the substantially pure concentration of hydrogen within the cell.

US Pat. No. 10,193,172

METHOD FOR STARTING UP A FUEL CELL

Robert Bosch GmbH, Stutt...

1. A method (40) for starting a fuel cell (11), wherein hydrogen is supplied to an anode chamber (15) of the fuel cell (11) and, at the beginning of starting the fuel cell, oxygen is present in the anode chamber (15) of the fuel cell (11), the method comprisingat the beginning of supplying the hydrogen, supplying enough hydrogen to the anode chamber (15) that the hydrogen is at most in a stoichiometric ratio with the amount of oxygen present in the anode chamber (15),
wherein, at the beginning of supplying the hydrogen, the molar fraction of the hydrogen within a volume segment of an anode inlet stream prior to entry into the fuel cell (11) lies below the molar fraction of the oxygen present in the anode chamber (15), wherein the molar faction of the hydrogen within the volume segment of the anode inlet stream lies between 0.09 and 0.13, and wherein an inlet valve (22) for metering a supply of hydrogen is not opened any further as long as oxygen is present in the anode chamber.

US Pat. No. 10,193,170

FUEL CELL MODULE

HONDA MOTOR CO., LTD., T...

1. A fuel cell module comprising:a fuel cell stack comprising a plurality of fuel cells stacked, the fuel cells being configured to generate electrical energy by electrochemical reactions of a fuel gas and an oxygen-containing gas;
a reformer configured to reform raw fuel chiefly containing hydrocarbon to thereby produce the fuel gas supplied to the fuel cell stack;
an evaporator configured to evaporate water and supply water vapor to the reformer;
an exhaust gas combustor configured to combust the fuel gas discharged from the fuel cell stack as a fuel exhaust gas and the oxygen-containing gas discharged from the fuel cell stack as an oxygen-containing exhaust gas to thereby produce a combustion exhaust gas;
a start-up combustor configured to combust the raw fuel and the oxygen-containing gas to thereby produce a combustion gas; and
an air preheater configured to heat the oxygen-containing gas by heat exchange with one of the combustion gas and the combustion exhaust gas and supply the heated oxygen-containing gas to the fuel cell stack,
wherein the fuel cell module further comprises:
an oxygen-containing gas supply channel configured to supply the oxygen-containing gas to the air preheater and thereafter supply the oxygen-containing gas from the air preheater to the fuel cell stack;
a first fuel supply channel configured to supply the raw fuel to the start-up combustor;
a second fuel supply channel configured to supply the raw fuel to the evaporator and thereafter supply the raw fuel and the water vapor from the evaporator to the reformer;
a channel switching unit configured to selectively supply the raw fuel to either one of the first fuel supply channel and the second fuel supply channel;
a reactant exhaust gas channel configured to supply the fuel exhaust gas and the oxygen-containing exhaust gas discharged from the fuel cell stack, to the exhaust gas combustor; and
an exhaust gas channel extending from a combustion exhaust gas outlet of the exhaust gas combustor, wherein in the exhaust gas channel, the start-up combustor and the air preheater are arranged in an order of the start-up combustor and then the air preheater toward downstream side in a flow direction of the combustion exhaust gas,
wherein after the reformer is heated to a temperature at which the reformer can perform steam reforming and while the fuel cell stack is in a start-up operation before the fuel cell stack starts power generation, the channel switching unit, the reformer, the exhaust gas combustor, and the start-up combustor cause
the raw fuel and the water vapor to be supplied to the reformer through the second fuel supply channel to generate the fuel gas,
the oxygen-containing gas and the fuel gas discharged from the fuel cell stack to be supplied to the start-up combustor through the exhaust gas combustor,
a mixed gas of the oxygen-containing gas and the fuel gas to be ignited at the start-up combustor,
the combustion gas to be supplied to the air preheater to be produced, and
among the exhaust gas combustor and the start-up combustor, the oxygen-containing gas and the fuel gas discharged from the fuel cell stack to be combusted by only the start-up combustor.

US Pat. No. 10,193,169

FLUIDIC INTERFACE MODULE FOR A FUEL CELL SYSTEM

Intelligent Energy Limite...

1. A valve comprising:an inlet, an outlet, a diaphragm,
a biasing member that urges the diaphragm toward the inlet or outlet to a sealing position to close the valve,
a slider that moves the biasing member to an open position to allow the diaphragm to move away from the inlet or outlet to open the valve, and,
a shape memory alloy (SMA) actuator connected to the biasing member and is actuated by an electrical current to move the biasing member to the open position;
wherein the slider comprises a main body and two forked legs extending from the main body, the two forked legs each having a hooked end having a first ramp on a distal end of the forked leg, wherein the two forked legs form a spring and store energy when the two forked legs are pressed toward each other in a first direction, wherein each of the two forked legs has a second ramp extending in a second direction orthogonal to the first direction;
wherein the valve further comprises a valve body having a plurality of notches defined thereon, each of the plurality of notches sized and dimensioned to receive one of the hooked ends in a retained engagement created by the spring force of the associated forked leg expanding away from the other of the two forked legs;
wherein the biasing member comprises a shoulder configured to catch a second ramp of one of the two forked legs of the slider to hold the slider in a position that keeps the biasing member in the open position.

US Pat. No. 10,193,168

FUEL CELL SYSTEM

NISSAN MOTOR CO., LTD., ...

1. A fuel cell system that generates electric power by supplying anode gas and cathode gas to a fuel cell, comprising:a control valve adapted to control a pressure of the anode gas to be supplied to the fuel cell;
a buffer unit adapted to store an anode-off gas to be discharged from the fuel cell; and
a controller programmed to:
control the control valve in order to periodically increase and decrease the pressure of the anode gas at a specific width of a pulsation; and
correct the width of the pulsation based on a temperature of an upstream buffer volume comprising an anode gas flow passage from the control valve to the fuel cell.

US Pat. No. 10,193,167

POWER CONDITIONING SYSTEM AND CONTROL METHOD THEREFOR

NISSAN MOTOR CO., LTD., ...

1. A power conditioning system, comprising:a fuel cell connected to a load;
a fuel cell converter connected between the fuel cell and the load, the fuel cell converter converting an output voltage of the fuel cell at a predetermined required voltage ratio;
a battery connected to the load in parallel to the fuel cell, the battery serving as a power supply source different from the fuel cell;
an impedance measuring device configured to measure an impedance of the fuel cell by outputting alternating currents between a positive electrode and an intermediate point of the fuel cell and between the intermediate point and a negative electrode of the fuel cell;
a current bypass path configured to couple the fuel cell and the load while bypassing the fuel cell converter; and
a current cut-off unit configured to provide on the current bypass path, the current cut-off unit electrically cutting off the current bypass path when the impedance of the fuel cell is measured by the impedance measuring device.

US Pat. No. 10,193,166

FUEL CELL SYSTEM

1. A fuel cell system, as an auxiliary power supply unit of a motor vehicle, the fuel cell system comprising:a reformer for generating a reformate gas from reformer air and fuel;
a fuel cell for generating electric current from cathode air and reformate gas, said fuel cell comprising a cathode side and an anode side;
an air delivery means for delivering air;
a reformer air line;
a cathode air line;
an air supply means for receiving ambient air from the surrounding area of the fuel cell system by said air delivery means and for splitting the air at least into reformer air and cathode air and sending the reformer air via said reformer air line in the direction of said reformer and sending the cathode air via said cathode air line in the direction of said cathode side;
a recirculating line connecting said anode side to said reformer and recycling anode waste gas from said fuel cell to said reformer;
a hot gas delivery means, said hot gas delivery means being arranged in said recirculating line for driving the anode waste gas, wherein:
said hot gas delivery means contains a hot gas path, through which the anode waste gas flows, said hot gas delivery means delivering said anode waste gas exclusively to said reformer;
said hot gas delivery means contains a cooling air path, said cooling air path being integrated into said reformer air line or into said cathode air line and the reformer air or the cathode air passing through said cooling air path, wherein a flow of said reformer air or said cathode air through an interior of said hot gas delivery means is separate from a flow of said anode waste gas through said interior of said hot gas delivery means; and
said cooling air path is sealed against said hot gas path.

US Pat. No. 10,193,165

SEPARATOR AND FUEL CELL

Toyota Jidosha Kabushiki ...

1. A separator used in a fuel cell, whereinthe separator has a recess-projection shape formed by press working,
the separator has one surface as a gas circulation surface and an opposite surface as a cooling surface, the gas circulation surface having a reactive gas flow path including a plurality of reactive gas flow path grooves resulting from the recess-projection shape, the cooling surface having a cooling water flow path including a plurality of cooling water flow path grooves resulting from the recess-projection shape,
the cooling water flow path includes:
an intersection flow path portion including cooling water flow path grooves adjacent to each other with a reactive gas flow path groove of the reactive gas flow path therebetween, and a communication flow path groove formed at the cooling surface side of the reactive gas flow path groove between the adjacent cooling water flow path grooves, the communication flow path groove being shallower than the cooling water flow path grooves; and
a cooling water turn portion where a direction of the cooling water flow path grooves changes,
wherein a reactive gas turn portion is formed at the gas circulation surface such that the reactive gas turn portion turns along the cooling water turn portion,
the reactive gas turn portion is formed of a groove portion having a constant depth, and
the groove portion of the reactive gas turn portion having the constant depth is a shallow groove portion having the same depth as a depth at the gas circulation surface in a position at a backside of a specific part of the cooling surface where the communication flow path groove is formed.

US Pat. No. 10,193,164

FLOW FIELDS FOR ELECTROCHEMICAL CELL

Hydrogenics Corporation, ...

1. A set of flow field plates for an electrochemical cell comprising,a first flow field plate having a flow field wherein 50% or more of the area of the flow field of the first flow field plate is defined by a plurality of elongate ridges, and
a second flow field plate having a flow field wherein 50% or more of the area of the flow field of the second flow filed plate is defined by a plurality of discontinuous lines of short ridges, wherein the short ridges are less than 10 times as long as an average gap between successive elongate ridges, the gap measured perpendicular to the elongate ridges.

US Pat. No. 10,193,163

FUEL CELL

NGK INSULATORS, LTD., Na...

1. A fuel cell comprising:an anode,
a cathode containing a perovskite oxide as a main component, the perovskite oxide expressed by the general formula ABO3, the A site including at least one selected from the group consisting of La and Sr, and the B site including at least one selected from the group consisting of Fe, Co, Mn and Ni, and
a solid electrolyte layer disposed between the anode and the cathode, wherein:
the cathode includes a surface region which is within 5 micrometers from a surface opposite the solid electrolyte layer,
the surface region contains a main phase comprising the perovskite oxide and a secondary phase comprising strontium oxide,
an occupied surface area ratio of the strontium oxide in a cross section of the surface region is greater than or equal to 0.05% and less than or equal to 3%, the cross section of the surface region being parallel to a thickness direction of the cathode, and
an average equivalent circle diameter of the strontium oxide in the cross section of the surface region is greater than or equal to 10 nm and less than or equal to 500 nm.

US Pat. No. 10,193,162

ELECTRODE CATALYST AND METHOD FOR PRODUCING THE SAME

Kumiai Chemical Industry ...

1. An electrode catalyst obtained by calcining a metal phthalocyanine polymer comprising a repeating structural unit obtained by the amide bonding of a structural unit represented by general formula (1a) to a structural unit represented by general formula (2a) to form a calcined body, then treating the calcined body with an acid,
(wherein L is a divalent or trivalent metal ion belonging to Period 3 to Period 5 on the long-form periodic table),

(wherein M is a divalent or trivalent metal ion belonging to Period 3 to Period 5 on the long-form periodic table).

US Pat. No. 10,193,161

ANODE FOR SOLID OXIDE FUEL CELL AND PRODUCTION METHOD THEREFOR, AND METHOD FOR PRODUCING ELECTROLYTE LAYER-ELECTRODE ASSEMBLY FOR FUEL CELL

SUMITOMO ELECTRIC INDUSTR...

1. A method for producing an anode for a solid oxide fuel cell, the method comprising:a first step of shaping a mixture that contains a perovskite oxide having proton conductivity and a nickel compound; and
a second step of firing a shaped product, which has been obtained in the first step, in an atmosphere containing 50% by volume or more of oxygen at 1100° C. to 1350° C. so as to generate an anode.

US Pat. No. 10,193,160

COMPOSITE CURRENT COLLECTOR FOR ENERGY STORAGE DEVICE ELECTRODE, AND ELECTRODE

NISSAN CHEMICAL INDUSTRIE...

1. An electrically conductive bonding layer-forming composition characterized by comprising a polymer having repeating units of formula (1) or formula (2) below and carbon nanotubes
wherein Ar1 to Ar3 are each independently a divalent organic group of any one of formulas (3) to (7) below

wherein R5 to R38 are each independently a hydrogen atom, a halogen atom, an alkyl group of 1 to 5 carbons which may have a branched structure, an alkoxy group of 1 to 5 carbons which may have a branched structure, or a carboxyl group, sulfo group, phosphoric acid group, phosphonic acid group or salt of any thereof;
wherein Z1 and Z2 are each independently a hydrogen atom, an alkyl group of 1 to 5 carbons which may have a branched structure, or a monovalent organic group of any one of formulas (8) to (11) below

wherein R39 to R62 are each independently a hydrogen atom, a halogen atom, an alkyl group of 1 to 5 carbons which may have a branched structure, a haloalkyl group of 1 to 5 carbons which may have a branched structure, a phenyl group, OR63, COR63, NR63R64, COOR65;
wherein R63 and R64 being each independently a hydrogen atom, an alkyl group of 1 to 5 carbons which may have a branched structure, a haloalkyl group of 1 to 5 carbons which may have a branched structure, or a phenyl group; and R65 being an alkyl group of 1 to 5 carbons which may have a branched structure, a haloalkyl group of 1 to 5 carbons which may have a branched structure, or a phenyl group, or a carboxyl group, sulfo group, phosphoric acid group, phosphonic acid group or salt of any thereof;
with the proviso that Z1 and Z2 are not both alkyl groups at the same time;
wherein R1 to R4 in formula (2) are each independently a hydrogen atom, a halogen atom, an alkyl group of 1 to 5 carbons which may have a branched structure, an alkoxy group of 1 to 5 carbons which may have a branched structure, or a carboxyl group, sulfo group, phosphoric acid group, phosphonic acid group or salt of any thereof; and
wherein said polymer contains one or more of R1 to R62 that are independently an acidic group selected from the group consisting of the carboxyl group, the sulfo group, the phosphoric acid group, the phosphonic acid group and the salts thereof.

US Pat. No. 10,193,159

CURRENT COLLECTOR FOR SECONDARY BATTERY AND SECONDARY BATTERY USING THE SAME

NISSAN MOTOR CO., LTD., ...

1. A current collector for a secondary battery, comprising:a film resin layer having electrical conductivity; and
an ion barrier layer provided on a surface of the film resin layer, the ion barrier layer consisting of ion trapping particles in which metal compounds are provided on surfaces of metal containing particles, the ion trapping particles being continuously provided from an interface between the film resin layer and the ion barrier layer toward a surface of the ion barrier layer,
wherein a diameter of primary particles of the ion trapping particles is within a range of 0.1 nm or more and less than 500 nm,
wherein a thickness of the ion barrier layer is within a range of 50 nm to 1000 nm.

US Pat. No. 10,193,158

ELECTROLYTIC COPPER FOIL FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY COMPRISING THE SAME

KCF TECHNOLOGIES CO., LTD...

1. An electrolytic copper foil for a lithium secondary battery, which is applied as a negative electrode current collector of a lithium secondary battery,wherein the electrolytic copper foil for a lithium secondary battery has yield strength of 30 kgf/mm2 to 60 kgf/mm2, a surface area ratio of 1 to 3, and a weight deviation of 3% or below.

US Pat. No. 10,193,157

NEGATIVE ELECTRODE FOR LITHIUM ION SECONDARY BATTERY, AND LITHIUM ION SECONDARY BATTERY USING THE SAME

TDK CORPORATION, Tokyo (...

1. A negative electrode for a lithium ion secondary battery, comprising:a negative electrode active material including 5 wt % or more of at least one silicon component selected from the group consisting of silicon oxide, elemental silicon, an alloy of silicon, and a compound of silicon other than silicon oxide;
a binder that is a polyacrylate obtained by a reaction of a polyacrylic acid and magnesium, an alkaline earth metal, a compound of magnesium, or a compound of an alkaline earth metal, and whose 1% or more of carboxylic groups at terminals of side chains of the polyacrylic acid are cross-linked with magnesium or alkaline earth metal; and
a negative electrode current collector.

US Pat. No. 10,193,156

HIGH-DENSITY AND HIGH-HARDNESS GRAPHENE-BASED POROUS CARBON MATERIAL, METHOD FOR MAKING THE SAME, AND APPLICATIONS USING THE SAME

Graduate School at Shenzh...

1. A method for making graphene-based porous carbon material comprising steps of:forming a sol by dispersing a graphene-based component and an auxiliary component in a solvent, the auxiliary component selected from the group consisting of polyvinyl alcohol, sucrose, glucose, and combinations thereof;
adjusting a pH value of the sol to 8 or less;
preparing a graphene-based gel by reacting the sol in a reacting container at a temperature of about 20° C. to about 500° C. for about 0.1 hours to 100 hours; and
evaporative drying the graphene-based gel at a temperature of about 0° C. to about 200° C. to obtain the graphene-based porous carbon material.

US Pat. No. 10,193,155

MANUFACTURING CATHODE MATERIAL, CATHODE, AND LITHIUM ION BATTERY

SUMITOMO OSAKA CEMENT CO....

1. A cathode material including a cathode active material,wherein the cathode active material is expressed by Li1+xAyDzPO4, wherein A represents one or more metal elements selected from the group consisting of Co, Mn, Ni, Fe, Cu, and Cr, D represents one or more metal elements selected from the group consisting of Mg, Ca, Sr, Ba, Ti, Zn, B, Al, Ga, In, Si, Ge, Sc, Y, and rare earth elements, 0 when a temperature of the cathode material is raised to a temperature range of 100° C. to 300° C. at a temperature-increase rate of 10° C/min, a weight loss ratio in the temperature range due to evaporation of water of crystallization is 0.03% by weight to 0.3% by weight, wherein the weight loss ratio is measured in a thermogravimetric analysis, which is carried out under the following measurement conditions using a differential thermogravimetric analyzer:
specimen amount: 15 mg
temperature-increase rate: 10° C. /minute
atmosphere: N2
gas flow rate: 200 ml/minute
measurement temperature range: 100 to 300° C.

US Pat. No. 10,193,153

POSITIVE ELECTRODE ACTIVE MATERIAL FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A positive electrode active material for a nonaqueous electrolyte secondary battery, comprising:primary particles formed of a lithium transition metal oxide,
a secondary particle formed by aggregation of the primary particles,
the secondary particle having a plurality of recesses, each recess of the plurality of recesses being formed between at least two of the primary particles adjacent to each other on a surface of the secondary particle,
particles formed of a rare-earth compound,
rare-earth compound secondary particles formed by aggregation of the particles formed of the rare-earth compound;
wherein rare-earth compound secondary particles adhere within recesses of the plurality of recesses respectively so as to adhere to the at least two of the primary particles adjacent to each other, and
a tungsten-containing compound adheres to an interface of the primary particles inside the secondary particle.

US Pat. No. 10,193,151

LOW POROSITY ELECTRODES FOR RECHARGEABLE BATTERIES

Umicore, Brussels (BE) U...

1. A positive electrode for a rechargeable battery comprising at least 95 wt % active cathode material with an electrode loading of at least 6 mg/cm2, and an electrode porosity of less than 2 vol %, wherein the active cathode material comprises a bimodal powder mixture composition wherein at least 70 wt % consists of a first lithium cobalt based oxide powder having an average particle size (D50) of more than 25 ?m, and a BET value <0.2m2/g.

US Pat. No. 10,193,149

BATTERY ACTIVE MATERIAL, NONAQUEOUS ELECTROLYTE BATTERY AND BATTERY PACK

KABUSHIKI KAISHA TOSHIBA,...

1. A battery active material, comprising a complex oxide of formula LixTiNb2-yMyO7+? (0?x?5, 0?y?0.5, ?0.3???0.3) and an element M,wherein:
a molar ratio (M/Ti) of the element M to Ti in the active material satisfies the following formula (I):
0.1?M/Ti?0.5  (I);
a molar ratio (Nb/Ti) of Nb to Ti in the complex oxide containing Nb and Ti satisfies the following formula (II):
1?Nb/Ti?5  (II); and
M comprises Mg and at least one element selected from the group consisting of V, B, Na, Al, Si, S, P, K, Ca, Mo, W, Cr, Mn, Co, Ni, and Fe.

US Pat. No. 10,193,148

CARBON-SILICON COMPOSITE AND MANUFACTURING METHOD THEREOF

OCI COMPANY LTD., Seoul ...

11. A carbon-silicon composite comprising:silicon-carbon-polymer carbonized matrix structure particles, comprising:
a polymer matrix having a network structure consisting of knots and chains connecting the knots with a cross-linking point;
carbon particles dispersed in the polymer matrix; and
silicon dispersed in the silicon-carbon-polymer carbonized matrix structure particles, wherein the silicon is bound to the carbon particles; and
a first carbon body, wherein the first carbon body is carbonized, and the silicon-carbon-polymer carbonized matrix structure particles are captured and dispersed in the first carbon body;
wherein the carbon particles are connected to each other and to the first carbon body to form inner pores,
wherein at least a portion of the silicon is in the inner pores,
wherein the silicon-carbon-polymer carbonized matrix structure particle has a porosity higher than a porosity of the first carbon body.

US Pat. No. 10,193,147

LIQUID SILICON POUCH ANODE AND CELL

The United States of Amer...

1. An electrochemical cell comprising:a cathode pouch;
a membrane having a first side sealed against said cathode pouch and defining a cathode volume therebetween and a second side, said membrane allowing communication of lithium ions between the first and second sides;
a catholyte positioned in said cathode volume, said catholyte comprising a lithium bearing material and an electrolyte;
a cathode current collector positioned within said cathode volume in electrical communication with said catholyte for providing a positive electrical charge on discharge of the electrochemical cell;
an anode pouch sealed against said membrane second side and defining an anode volume therebetween wherein said anode volume is responsive to pressure changes therein;
an anolyte positioned in said anode volume, said anolyte comprising a silicon-based lithium ion insertion material, an electrolyte, and conductive particles; and
an anode current collector positioned within said anode volume in electrical communication with said anolyte for providing a negative electrical charge on discharge of the electrochemical cell.

US Pat. No. 10,193,145

CARBON-COATED ACTIVE PARTICLES AND PROCESSES FOR THEIR PREPARATION

HYDRO-QUEBEC, Montreal, ...

1. A process for producing carbon-coated particles, the process comprising the steps of:a. forming an emulsion by mixing particles, acrylonitrile monomers, and an aqueous solvent, said particles comprising an electrochemically active material;
b. polymerizing the acrylonitrile monomers in the mixture of step (a) by emulsion polymerization;
c. drying the particles from step (b) to form a nano-layer of poly(acrylonitrile) at the surface of the particles; and
d. thermally treating the dried particles of step (c) to form the carbon-coated particles, said carbon consisting in a nano-layer of carbon comprising fibers on the surface of the particles.

US Pat. No. 10,193,142

LITHIUM-ION BATTERY ANODE INCLUDING PRELOADED LITHIUM

CF Traverse LLC, San Fra...

1. A battery anode comprising:a substrate;
a plurality of support structures attached to the substrate;
an active layer configured to receive lithium from an electrolyte with nanoparticles interspersed within the active layer; and
an under-layer disposed between the active layer and the support structures, the under-layer including lithium;
wherein the under-layer contains active material catalyzers which are disposed in a concentration gradient in the under-layer.

US Pat. No. 10,193,140

POSITIVE ACTIVE MATERIAL FOR RECHARGEABLE LITHIUM BATTERY AND RECHARGEABLE LITHIUM BATTERY

Samsung SDI Co., Ltd., Y...

1. A positive electrode for a rechargeable lithium battery, comprising:a positive active material consisting of LiCoO2 or LiaCoGbO2 (0.90?a?1.8, 0.001?b?0.1, G is Al, Cr, Mn, Fe, Mg, La, Ce, Sr, V, or a combination thereof); and
activated carbon having an average particle diameter larger than an average particle diameter of the positive active material and in a range of about 122% to about 160% relative to 100% of the average particle diameter of the positive active material,
wherein the positive active material and activated carbon are present in a mixed ratio in a range of about 98:2 to about 94:6.

US Pat. No. 10,193,139

REDOX AND ION-ADSORBTION ELECTRODES AND ENERGY STORAGE DEVICES

The Regents of the Univer...

1. An energy storage device comprising:a first electrode comprising:
a layered double hydroxide;
a three-dimensional graphene based conductive scaffold; and
a first current collector;
a second electrode comprising:
a hydroxide; and
a second current collector;
a separator; and
an electrolyte;
wherein the energy storage device stores energy through both redox reactions and ion adsorption; and
wherein the layered double hydroxide comprises a metallic layered double hydroxide comprising a zinc-based layered double hydroxide, an iron-based layered double hydroxide, an aluminum-based layered double hydroxide, a chromium-based layered double hydroxide, an indium-based layered double hydroxide, a manganese-based layered double hydroxide, or any combination thereof.

US Pat. No. 10,193,137

LITHIUM-ION BATTERIES WITH NANOSTRUCTURED ELECTRODES

WASHINGTON STATE UNIVERSI...

1. A method to produce an anode suitable for a lithium-ion battery, the method comprising:preparing a surface of an anode substrate, the anode substrate being at least partially compliant and having a compliance of about 3.0×10?7 to 8×10?12 l/Pa, wherein preparing the surface of the anode substrate comprises polishing the anode substrate, treating the anode substrate with a basic solution, treating the anode substrate with an acidic solution, or combinations thereof;
forming a plurality of conductive nanostructures on the surface of the anode substrate via electrodeposition; and
controlling at least one operating condition of the electrodeposition based on a target profile for the plurality of conductive nanostructures formed on the surface of the anode substrate, the target profile including the conductive nanostructures forming a plurality of freestanding structures.

US Pat. No. 10,193,136

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

AUTOMOTIVE ENERGY SUPPLY ...

1. A nonaqueous electrolyte secondary battery comprising:an electrode body;
an electrolyte solution; and
a laminate film package container housing the electrode body and the electrolyte solution, wherein
the laminate film package comprises a metal layer, a heat-seal layer, and a protective layer;
the electrode body includes a positive electrode, a negative electrode, and a separator disposed between the positive electrode and the negative electrode,
the positive electrode includes a positive electrode current collector, and a positive electrode active material layer formed on the positive electrode current collector,
the negative electrode includes a negative electrode current collector, and a negative electrode active material layer formed on the negative electrode current collector,
the positive electrode active material layer includes secondary particles of a lithium nickel cobalt manganese composite oxide,
the secondary particle includes a group of primary particles of a lithium nickel cobalt manganese composite oxide with a layered crystal structure,
the primary particle has an average cross-sectional area of 0.80 ?m2 or greater and 1.20 ?m2 or less,
the layered crystal structure has a lattice constant “c” of 14.240 ? or less, and
the lithium nickel cobalt manganese composite oxide is represented by the following Formula (1):
Li1-xNiaCobMncO2   (1)
wherein “x” satisfies 0?x?1, “a” satisfies 0.4?a?0.8, “b” satisfies 0.1?b?0.4, and “c” satisfies 0.1?c?0.5.

US Pat. No. 10,193,135

POSITIVE ELECTRODE ACTIVE MATERIALS WITH COMPOSITE COATINGS FOR HIGH ENERGY DENSITY SECONDARY BATTERIES AND CORRESPONDING PROCESSES

Zenlabs Energy, Inc., Fr...

1. A particulate material comprising a core of lithium cobalt oxide, a partial coating with domains of a lithium manganese nickel cobalt oxide, and a distinct inert stabilization nanocoating, and having from about 2 weight percent to about 19 weight percent lithium manganese nickel cobalt oxide evaluated according to weight of added metal during coating formation.

US Pat. No. 10,193,133

METHOD FOR MANUFACTURING OF METAL OXIDE NANOPARTICLES AND METAL OXIDE NANOPARTICLES THEREBY

KOREA ADVANCED INSTITUTE ...

1. A method for preparing metal oxide nanoparticles, the method comprising:dipping a cathode and an anode, each of the cathode and the anode being a different metal, in an inorganic electrolyte solution containing a halogen salt (step 1); and
applying a DC voltage between the anode and the cathode so as to oxidize the metal of the anode, to form, on the anode, a metal oxide forming an anode surface (step 2), whereby the metal oxide formed is an oxide of the metal of the anode,
wherein the anode is formed of at least one selected from the group consisting of indium, tin, zinc, zirconium, aluminum, titanium, nickel, iron and copper, and
wherein the cathode is formed of platinum.

US Pat. No. 10,193,131

RECHARGEABLE BATTERY

Samsung SDI Co., Ltd., Y...

1. A rechargeable battery comprising:an electrode assembly;
a case accommodating the electrode assembly;
a cap plate covering the case and having a first surface facing the electrode assembly and a second surface opposite the first surface, the cap plate including an injection hole extending from the first surface to the second surface and being sealed by a ball, the second surface having a recess depressed toward the first surface, the injection hole being arranged in the recess; and
a terminal plate covering the injection hole and the ball, the terminal plate including a first region in the recess below the second surface of the cap plate.

US Pat. No. 10,193,130

RECHARGEABLE BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A rechargeable battery pack including:a battery cell including an electrode terminal in a cap plate and configured to perform charging and discharging operations;
a protection element connected to the electrode terminal via a first connecting tab;
a protection management package connected to a second connecting tab of the protection element and connected to the cap plate via an electrode tab;
a molding portion fully enclosing the protection element and the protection management package; and
an adhesive member disposed between the molding portion and the battery cell to attach them, wherein the adhesive member is not enclosed by the molding portion and wherein the first connecting tab has a bending portion with a bend between the electrode terminal and the protection element so as to set a height difference.

US Pat. No. 10,193,129

PARALLEL BATTERY MODULE

CONTEMPORARY AMPEREX TECH...

1. A parallel battery module, comprising:a plurality of battery cells in parallel connection, each battery cell comprising:
a conducting top cover plate;
a first terminal that is assembled to be insulated from the conducting top cover plate;
a conducting connector that is electrically connected to the first terminal and insulated from the conducting top cover plate;
a second terminal that has an opposite polarity to the first terminal and is assembled to be electrically connected to the conducting top cover plate;
a bare cell that is electrically connected to the first terminal and the second terminal;
a fuse that is connected between the first terminal and the bare cell or connected between the second terminal and the bare cell; and
a conducting deformable piece that is electrically connected to the conducting top cover plate and is disposed below the conducting connector, wherein the conducting deformable piece deforms and becomes electrically connected to the conducting connector such that the first terminal and the second terminal are electrically connected to form an external short circuit when an internal gas pressure of a battery cell reaches a certain level;
a first current collection connector disposed on top of said plurality of battery cells and is electrically connected to the first terminals of said plurality of battery cells, wherein the first current collection connector comprises:
a plurality of first connection parts, a total number of the plurality of first connection parts being the same as a total number of the plurality of battery cells, each first connection part being electrically connected to the first terminal of a corresponding battery cell;
a first current collection part; and
one or more first fusing parts connected between the first current collection part and a corresponding first connection part for each of the plurality of first connection parts; and
a second current collection connector disposed on the top of said plurality of battery cells and is electrically connected to the second terminals of said plurality of battery cells,
wherein, when the conducting deformable piece of the battery cell deforms and is electrically connected to the conducting connector, an electrical connection between said battery cell and other battery cells of the plurality of battery cells is broken by blowing the one or more first fusing parts corresponding to said battery cell of the first current collection connector to electrically isolate said battery cell from the other battery cells.

US Pat. No. 10,193,128

SWITCHING DEVICE FOR A BATTERY, AND BATTERY COMPRISING SAID SWITCHING DEVICE

Robert Bosch GmbH, Stutt...

1. A switching device (1) for a battery (2), wherein the switching device (1) is configured to be operated by an acoustic resonance effect in order to interrupt an electrical line of the battery (2) to a device located outside of the battery, wherein the switching device (1) has at least one container (12) which is prestressed by a spring element (11) and is configured to be destroyed by acoustic resonance.

US Pat. No. 10,193,127

BATTERY TERMINAL UNIT WITH CURRENT SENSOR

YAZAKI CORPORATION, Mina...

1. A battery terminal unit with a current sensor, the battery terminal unit comprising:a bus bar for a battery terminal, the bus bar including:
an attachment part configured to attach to a battery post;
an extension part extended from the attachment part; and
a connection part which continues from the extension part and is configured to connect to a wire harness; and
a current sensor including a board having a magnetic detection element and a shield plate having a U shape so that both ends of the shield plate are connected to the board so as to define two opening portions oppositely opening,
wherein the extension part is inserted through the openings and extends inside the current sensor,
wherein the board is opposed to a surface of the extension part inside the current sensor,
wherein the attachment part, the extension part, and the connection part are integrally formed, and are configured in a unity member, and
wherein the connection part is connected to one end of the extension part at an opposite side to the attachment part and extends in a transverse direction substantially perpendicular to an overhang direction of the extension part, so that a part of the connection part configured to be connect to the wire harness is disposed on a position offset from the extension part in the transverse direction, and
wherein the connection part includes an extending portion which is bent from the one end of the extension part in a vertical direction perpendicular to both of the overhang direction and the transverse direction so as to be erected in the vertical direction.

US Pat. No. 10,193,125

ELECTRODE ASSEMBLY AND SECONDARY BATTERY INCLUDING THE SAME

Samsung SDI Co., Ltd., Y...

1. An electrode assembly, comprising:a jelly roll comprising a first electrode plate wound together with a second electrode plate, the second electrode plate having a different polarity from the first electrode plate,
wherein the first electrode plate includes a plurality of non-coated portions spaced apart from each other; and
a plurality of tabs attached to the plurality of non-coated portions, respectively,
wherein the plurality of non-coated portions includes a first non-coated portion having a first width, and a second non-coated portion having a second width different from the first width of the first non-coated portion, and
wherein the first non-coated portion is between a winding center of the jelly roll and the second non-coated portion and spaced apart from the winding center, and the second non-coated portion is between the first non-coated portion and an end of the first electrode plate opposite to the center of the jelly roll and spaced apart from the end of the first electrode plate.

US Pat. No. 10,193,124

BATTERY CONNECTING BODY AND POWER SUPPLY DEVICE

YAZAKI CORPORATION, Mina...

1. A battery connecting body comprising:a plurality of connecting members that each connect electrodes of adjacent ones of a plurality of batteries arranged such that the electrodes thereof are arranged on a straight line to electrically connect the plurality of batteries; and
a casing that houses the plurality of connecting members, wherein
the casing includes a plurality of connecting member housing portions that each house each of the connecting members and cover portions that each cover an opening of each of the connecting member housing portions, and
the cover portions are each retained by protruding portions inside of the cover portions inserted into the connecting members wherein at least one of the connecting members is a bus bar.

US Pat. No. 10,193,123

BATTERY PACK BUS BAR ASSEMBLY WITH ENLARGED INTERCONNECT MOUNTING PLATFORMS

ATIEVA, INC., Menlo Park...

1. A battery assembly, comprising:a plurality of batteries, each battery of said plurality of batteries comprising a first terminal at a first end portion of said battery and a second terminal at said first end portion of said battery, wherein said plurality of batteries are divided into a plurality of battery groups, wherein said batteries within each battery group are electrically connected in parallel, and wherein said battery groups of said plurality of battery groups are electrically connected in series; and
a plurality of non-overlapping bus bars configured in an alternating pattern with said plurality of battery groups, wherein said alternating pattern alternates a single bus bar of said plurality of non-overlapping bus bars with a single battery group of said plurality of battery groups, each single bus bar of said plurality of non-overlapping bus bars comprising:
a plurality of first coupling segments extending from a first edge of said single bus bar, said plurality of first coupling segments electrically connecting said single bus bar to a plurality of first interconnect mounting platforms, wherein each of said plurality of first interconnect mounting platforms is electrically connected to a first subset of said plurality of batteries via said first terminals of said first subset of said plurality of batteries;
a plurality of second coupling segments electrically connecting said plurality of first interconnect mounting platforms to a plurality of second interconnect mounting platforms, wherein each of said plurality of second interconnect mounting platforms is electrically connected to a second subset of said plurality of batteries via said first terminals of said second subset of said plurality of batteries;
a plurality of third coupling segments extending from a second edge of said single bus bar, said plurality of third coupling segments electrically connecting said single bus bar to a plurality of third interconnect mounting platforms, wherein each of said plurality of third interconnect mounting platforms is electrically connected to a third subset of said plurality of batteries via said second terminals of said third subset of said plurality of batteries; and
a plurality of fourth coupling segments electrically connecting said plurality of third interconnect mounting platforms to a plurality of fourth interconnect mounting platforms, wherein each of said plurality of fourth interconnect mounting platforms is electrically connected to a fourth subset of said plurality of batteries via said second terminals of said fourth subset of said plurality of batteries.

US Pat. No. 10,193,122

NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A non-aqueous electrolyte secondary battery comprising:a separator; and
an electrode,
the separator including a base material layer and a heat resistance layer arranged on a surface of the base material layer,
the heat resistance layer containing inorganic particles and a resin binder,
the electrode facing the heat resistance layer,
the heat resistance layer including, in a direction of thickness of the heat resistance layer, a central portion and a first end portion and a second end portion between which the central portion lies,
the first end portion including an interface with the electrode,
the second end portion including an interface with the base material layer,
a content of the resin binder in the first end portion being not lower than 8 mass % and not higher than 30 mass % based on a total content of the resin binder and the inorganic particles in the heat resistance layer being 100 mass %;
a content of the resin binder in the second end portion being not lower than 8 mass % and not higher than 30 mass % based on the total content of the resin binder and the inorganic particles in the heat resistance layer being 100 mass %; and
a content of the resin binder in the central portion being not lower than 2 mass % and not higher than 7 mass % based on the total content of the resin binder and the inorganic particles in the heat resistance layer being 100 mass %.

US Pat. No. 10,193,121

SEPARATOR FOR LITHIUM SECONDARY BATTERY, LITHIUM SECONDARY BATTERY USING THE SEPARATOR, AND METHOD OF MANUFACTURING THE LITHIUM SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A separator for a lithium secondary battery, the separator comprising:a porous base, at least a portion of the porous base comprising at least one selected from polyethylene terephthalate, polybutylene terephthalate, polyester, polyacetal, polyamide, polycarbonate, polyimide, polyether ether ketone, polyether sulfone, polyphenylene oxide, polyphenylene sulfide, polyvinylidene fluoride, polyethylene oxide, polyacrylonitrile, a polyvinylidene fluoride-hexafluoropropylene copolymer, polyethylene, and polypropylene; and
a first coating layer directly on a surface of the portion of the porous base and a second coating layer on a surface of the porous base opposite to the first coating layer, the first coating layer and the second coating layer each comprising a (meth)acrylic acid ester-based polymer having a glass transition temperature of about 10° C. to about 60° C.,
wherein the (meth)acrylic acid ester-based polymer is a polymerization product of an ethylenically unsaturated carboxylic acid ester and a monomer that is copolymerizable with the ethylenically unsaturated carboxylic acid ester,
wherein the ethylenically unsaturated carboxylic acid ester is a mixture of 2-ethylhexyl acrylate, isobornyl acrylate, and hydroxyethyl acrylate, or a mixture of methyl acrylate, ethyl acrylate, and hydroxyethyl acrylate, and
the monomer that is copolymerizable with the ethylenically unsaturated carboxylic acid ester is a mixture of acrylonitrile, methacrylic acid, acrylic acid, and ethylene dimethacrylate.

US Pat. No. 10,193,120

METHOD FOR FORMING ADHESION LAYER FOR SECONDARY BATTERY

LG CHEM, LTD., Seoul (KR...

1. A method for forming an adhesion layer, comprising:preparing a mask having openings which are open vertically;
etching a photosensitive film through the mask to form grooves corresponding to the openings of the mask in the photosensitive film;
pouring polydimethylsiloxane onto the photosensitive film having the grooves, curing the polydimethylsiloxane, and separating the cured polydimethylsiloxane from the photosensitive film to manufacture a polydimethylsiloxane mold having a concavo-convex part;
coating a polymer binder slurry on the polydimethylsiloxane mold having the concavo-convex part; and
transferring only the polymer binder slurry directly from the polydimethylsiloxane mold onto a surface of a separator or an electrode of a secondary battery to form an adhesion layer having a cavity part on the surface of the separator or the electrode, the cavity part being open vertically.

US Pat. No. 10,193,119

COMPOSITION FOR NON-AQUEOUS SECONDARY BATTERY FUNCTIONAL LAYER, FUNCTIONAL LAYER FOR NON-AQUEOUS SECONDARY BATTERY, AND NON-AQUEOUS SECONDARY BATTERY

ZEON CORPORATION, Chiyod...

1. A composition for non-aqueous secondary battery functional layer, comprising:non-conductive inorganic particles; and
organic particles, wherein
a difference in density calculated by subtracting the organic particles' density from the non-conductive inorganic particles' density is 1.5 g/cm3 or more, and
the organic particles each have a core-shell structure having a core and a shell that partially covers an outer surface of the core, wherein the core is made of polymer having a degree of swelling in electrolysis solution of 5 times to 30 times, and the shell is made of polymer having a degree of swelling in electrolysis solution of greater than 1 time to 4 times,
wherein the degree of swelling of polymer in electrolysis solution is calculated by W1/W0, where W0 indicates a weight of a film fabricated using the polymer, and W1 indicates a weight of the film after immersing into an electrolysis solution at 60° C. for 72 hours, the electrolysis solution being obtained by dissolving LiPF6 into a mixture solvent of 68.5% by volume of ethylene carbonate, 30 vol % of diethyl carbonate, and 1.5 vol % of vinylene carbonate at a concentration of 1 mol/L.

US Pat. No. 10,193,118

HYDROXIDE-ION-CONDUCTIVE DENSE MEMBRANE AND COMPOSITE MATERIAL

NGK Insulators, Ltd., Na...

1. A separator for a zinc secondary battery comprising a composite material including a porous alumina substrate and a hydroxide-ion-conductive dense membrane disposed on at least one surface of the porous alumina substrate, the hydroxide-ion-conductive dense membrane consisting of a layered double hydroxide dense membrane and having a He permeability per unit area of 10 cm/min·atm or less,wherein the porous alumina substrate has a water-permeable structure and an average pore size of 0.001 ?m to 1.5 ?m, and
wherein the layered double hydroxide dense membrane is formed from a stock solution containing at least two cations that are different from one another.

US Pat. No. 10,193,115

BATTERY COVER

East Penn Manufacturing C...

1. A battery cover, comprising:a lower battery cover, and
an upper battery cover matable with the lower battery cover to form a labyrinth and a plurality of battery cover sides including a terminal side and an opposite side, the labyrinth defined by a plurality of walls formed by the lower battery cover and the upper battery cover and having
a plurality of labyrinth cell passageways each extending only between one of a plurality of cell openings and one of a plurality of mixing areas positioned on the terminal side,
a plurality of exhaust passageways extending along an entirety of the opposite side of the upper battery cover, and
a channel disposed between the plurality of mixing areas and the plurality of exhaust passageways, the channel connecting the plurality of mixing areas to the plurality of exhaust passageways by extending from a lower end of each of the plurality of mixing areas at the terminal side and splitting into the plurality of exhaust passageways, the plurality of labyrinth cell passageways each extending to a position directly adjacent one of the plurality of exhaust passageways at the opposite side before leading to the one of the plurality of mixing areas at the terminal side, each of the plurality of labyrinth cell passageways is separated only by one of the plurality of walls from one of the plurality of exhaust passageways at the position directly adjacent one of the plurality of exhaust passageways.

US Pat. No. 10,193,109

PRISMATIC ELECTROCHEMICAL CELL

Bosch Battery Systems LLC...

1. An electrochemical cell comprising:a rigid cell housing having the shape of a rectangular prism, the cell housing including
an elongated rectangular first end,
an elongated rectangular second end, and
a sidewall that connects the first end to the second end, the sidewall having the form of a tube that has a rectangular cross-sectional shape, the sidewall including a pair of major sides joined by a pair of minor sides, where each side of the pair of major sides is larger in area than each side of the pair of minor sides;
an electrode assembly disposed in the cell housing, the electrode assembly comprising positive electrode plates alternating with negative electrode plates and separated by at least one separator to form an electrode stack;
a terminal that protrudes through the cell housing, the terminal being electrically connected to the positive plates or the negative plates via a weld free, electrically conductive snap-fit connection, and
a connector disposed in the cell housing between the electrode assembly and the first end, the connector comprising an electrically conductive strip of material that is folded over on itself so as to provide a U shaped configuration that includes a first leg portion that faces a second leg portion,whereinthe electrode assembly defines a stack axis that extends parallel to a stacking direction of the positive electrode plates, the negative electrode plates and the at least one separator,
the stack axis extends in a direction that is normal to, and passes through, the first minor side and the second minor side,
the terminal is disposed on an outer surface of the cell housing first end,
the first leg portion is electrically connected to the terminal and the second leg portion is electrically connected to one of the positive electrode plates and the negative electrode plates, and
the connector is folded over on itself along a first connector fold line and along a second connector fold line so as to provide an S shaped configuration that includes the first leg portion that faces one side of the second leg portion and a third leg portion that faces an opposed side of the second leg portion, wherein the second leg portion is electrically connected to one of the positive electrode plates and the negative electrode plates via the third leg portion.

US Pat. No. 10,193,107

ELECTRIC STORAGE DEVICE AND ELECTRIC STORAGE APPARATUS PROVIDED WITH THE ELECTRIC STORAGE DEVICE

GS YUASA INTERNATIONAL LT...

4. An electric storage device, comprising:an electrode assembly comprising a positive electrode plate and a negative electrode plate that are insulated from each other;
a case constituted by a partition wall, the case housing the electrode assembly;
a rivet member comprising a first insert part provided on one end and a body part joined to the first insert part, the rivet member being fixed to the partition wall; and
a first conductive member comprising a first insert-receiving part through which the first insert part is inserted, the first conductive member being electrically connected to the rivet member,
wherein the body part has a larger width in a direction intersecting an insertion direction of the first insert part than the first insert-receiving part, and is in contact with the first conductive member,
wherein the body part has a higher Vickers hardness than a region of the first conductive member in contact with the body part,
wherein the first insert part comprises, at a distal end of the first insert part, a swaged part that is swaged while the first insert part is inserted through the first conductive member, and
wherein a peripheral region of the first insert-receiving part of the first conductive member includes a tapered portion that is compressed and deformed in the insertion direction, and sandwiched between the swaged part and the body part of the rivet member.

US Pat. No. 10,193,106

METHOD FOR MANUFACTURING OLED DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing an OLED device, comprising steps of:a. providing a substrate and manufacturing an anode and a buffer layer in sequence on the substrate;
b. subjecting the substrate with the anode and the buffer layer thereon to an acid treatment;
c. drying the substrate and manufacturing a liquid light emitting layer on the buffer layer;
d. providing a cover plate and manufacturing a cathode and an electron transport layer in sequence on the cover plate;
e. subjecting the cover plate with the cathode and the electron transport layer thereon to the acid treatment; and
f. bonding the cover plate and the substrate together by lamination to obtain the OLED device.

US Pat. No. 10,193,105

ULTRAVIOLET IRRADIATION DEVICE FOR PACKAGE OF LIGHT-EMITTING DIODE

WUHAN CHINA STAR OPTOELEC...

1. An ultraviolet irradiation device for package of a light-emitting diode, wherein the ultraviolet irradiation device comprises:a sealed shell, wherein the light-emitting diode to he packaged is arranged in the shell, and a UV mask that is movable in the shell is arranged below the light-emitting diode;
a UV lamp, which is arranged below the UV mask; and
to a sealed chamber which is in communication with the shell, wherein the chamber is arranged at a side of the shell, wherein a first rolling unit configured to deliver the light-emitting diode is arranged in the chamber, and a first gate and a second gate are respectively arranged at two ends of the chamber, and wherein the chamber is further in communication with an air exhaust unit and a first gas source respectively.

US Pat. No. 10,193,104

ORGANIC LIGHT-EMITTING DIODE STRUCTURE AND FABRICATION METHOD THEREOF, RELATED DISPLAY PANEL, AND RELATED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode device (OLED) structure for compensating blue light emission, comprising:a substrate with a thin-film transistor (TFT) layer, the substrate being substantially transparent;
a first electrode layer on the substrate, the first electrode being substantially transparent;
a first light-emitting layer on the first electrode layer with one or more light-emitting portions for emitting light for compensating blue light;
a charge generation layer (CGL) with a reflective portion, the CGL being on the first light-emitting layer, the reflective portion of the CGL having a transmission rate for light emitted by the first light-emitting layer;
a second light-emitting layer on the CGL with one or more light-emitting portions for emitting the blue light; and
a second electrode layer with a reflectivity on the second light-emitting layer, wherein:
the OLED structure includes a microcavity structure having the CGL, the second electrode layer, and the second light-emitting layer;
the first light-emitting layer includes a green light-emitting portion for emitting green light and a red light-emitting portion for emitting red light; and
a portion of the green light and a portion of the red light transmit into the microcavity to be converted into a second portion of blue light.

US Pat. No. 10,193,103

ORGANIC LIGHT EMITTING DEVICE HAVING PROTRUSION FORMED OF TRANSPARENT MATERIAL AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting device, comprising an array substrate and a package substrate, wherein on a side of the package substrate facing the array substrate, there is provided a protrusion formed of a first transparent material, a surface of the protrusion is covered with a transparent layer formed of a second transparent material, and a refractive index of the second transparent material is larger than a refractive index of the first transparent material;a recess is disposed between the protrusions covered with the transparent layer of the second transparent material, and a side face of the recess is covered with the transparent layer of the second transparent material having the refractive index larger than that of the first transparent material of the protrusion, so that a part of light irradiated to the side face is totally reflected and changed in optical paths;
wherein the array substrate comprises a pixel defining layer formed thereon, and the transparent layer is directly contacted with the pixel defining layer.

US Pat. No. 10,193,102

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a substrate;
a plurality of pixels above the substrate, each of the pixels including a light emitting element;
a display region including the plurality of pixels;
a thin film transistor which each of the plurality of pixels includes;
a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element;
a sealing film including a second inorganic insulating material and covering the light emitting element; and
at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film,
wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

US Pat. No. 10,193,101

ELECTRONIC DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An electronic device comprising:a flexible substrate, a device portion supported on the flexible substrate, and a driver circuit portion;
a first flexible tube having a water vapor transmission rate of less than 10?3 g/(m2·24 h) and an oxygen transmission rate of less than 10?2 ml/(m2·24 h·MPa); and
a second flexible tube provided on an inner side of the first flexible tube and having a water vapor transmission rate of less than 10?3 g/(m2·24 h) and an oxygen transmission rate of less than 10?2 ml/(m2·24 h·MPa), wherein:
a first seal structure at one end of the first flexible tube and the second flexible tube and a second seal structure at another end of the first flexible tube and the second flexible tube define a sealed space between the first flexible tube and the second flexible tube;
the sealed space is defined by an inner surface of the first flexible tube, an outer surface of the second flexible tube, an inner surface of the first seal structure, and an inner surface of the second seal structure;
a portion of the flexible substrate and the device portion are inside the sealed space; and
a remainder of the flexible substrate, other than the portion of the flexible substrate that is inside the sealed space, is outside the sealed space.

US Pat. No. 10,193,100

ARRAY SUBSTRATE, FABRICATING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising: a thin film transistor, an auxiliary electrode, and a transparent cathode which is electrically connected with the auxiliary electrode, wherein both the auxiliary electrode and an active layer of the thin film transistor are directly arranged on a gate insulating layer of the thin film transistor, the active layer comprises an oxide semiconductor, and the auxiliary electrode is an electric conductor comprising a modified oxide semiconductor,wherein the array substrate further comprises a first etch-stopping layer which is arranged on the auxiliary electrode, and a passivation layer which is arranged on the gate insulating layer and covers the first etch-stopping layer,
wherein a via hole is arranged in the passivation layer, a via hole is arranged in the first etch-stopping layer, and the transparent cathode is electrically connected with the auxiliary electrode through the via hole in the first etch-stopping layer and the via hole in the passivation layer.

US Pat. No. 10,193,099

TRANSFORMABLE DEVICE AND METHOD OF MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. A display device, comprising:a display panel; and a transformable device wherein the transformable device includes:
an electro-active layer;
a first electrode inside the electro-active layer; and
a second electrode inside the electro-active layer on the first electrode and at a distance from the first electrode,
wherein the electro-active layer includes impurities, and
wherein a concentration of the impurities in the electro-active layer increases closer to the first electrode and the second electrode.

US Pat. No. 10,193,098

LIGHT EMITTING DEVICE MANUFACTURING METHOD AND APPARATUS THEREOF

INT TECH CO., LTD., Hsin...

1. A method of manufacturing a light emitting device, comprising:providing a substrate;
forming a plurality of photosensitive bumps over the substrate;
forming a photosensitive layer over the plurality of photosensitive bumps;
patterning the photosensitive layer to form a recess through the photosensitive layer to expose a surface;
disposing an organic emissive layer on the surface;
removing the patterned photosensitive layer; and
forming a buffer layer between the photosensitive layer and the plurality of photosensitive bumps.

US Pat. No. 10,193,096

ORGANIC LIGHT-EMITTING DIODE ARRAY SUBSTRATE AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. An organic light-emitting diode (OLED) array substrate, comprising a plurality of OLEDs,wherein each of the OLEDs comprises: an anode, a light-emitting layer configured for emitting light of a color, and a cathode which are provided in this order,
wherein a forming material of the light-emitting layer of each of the OLEDs comprises a host material and a guest material which is doped in the host material, and light-emitting layers of the OLEDs are configured for emitting light of a plurality of colors,
wherein each of the OLEDs further comprises an exciton barrier layer which is provided between the anode and the light-emitting layer and in contact with the light-emitting layer, and a forming material of the exciton barrier layer comprises a host material of one light-emitting layer that has a maximum highest occupied molecular orbital energy level amongst the host materials of all of the light-emitting layers of the OLEDs, and
wherein the light-emitting layers of the OLEDs comprise a red light-emitting layer, a green light-emitting layer and a blue light-emitting layer; the forming material of the exciton barrier layer comprises a host material of the blue light-emitting layer; and
HOMO energy levels of the host materials of the blue light-emitting layer, green light-emitting layer and red light-emitting layer gradually decrease, and LUMO energy levels of the host materials of the blue light-emitting layer, green light-emitting layer and red light-emitting layer gradually increase.

US Pat. No. 10,193,095

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:first and second guide plates facing each other;
a pair of first guide rails disposed in the first and second guide plates, respectively;
a pair of second guide rails disposed in the first and second guide plates, respectively;
a first supporting plate disposed between the first guide rails and the second guide rails at the first guide plate and the first and second guide rails at the second guide plate, wherein the first supporting plate has opposite end portions fixed to a first position of the first and second guide plates;
a second supporting plate configured to have opposite end portions coupled to the pair of first guide rails;
a third supporting plate configured to have opposite end portions coupled to the pair of second guide rails; and
a display panel supported by at least one of the first to third supporting plates,
wherein the pair of first guide rails are respectively formed to extend from the first position to a second position, and
the pair of second guide rails are respectively formed to extend from the first position to a third position, wherein the first position is disposed between the second position and the third position.

US Pat. No. 10,193,093

RADIATION DETECTOR

Kabushiki Kaisha Toshiba,...

1. A radiation detector, comprising:a first conductive layer;
a second conductive layer; and
an intermediate layer provided between the first conductive layer and the second conductive layer, the intermediate layer comprising an organic semiconductor region and a plurality of particles which comprise zinc selenide, the organic semiconductor region comprising a portion provided around the particles, a diameter being not less than 1 nanometer and not more than 20 nanometers for at least a portion of the particles, a first bandgap energy of the plurality of particles being larger than a second bandgap energy of the organic semiconductor region.

US Pat. No. 10,193,091

SCHOTTKY DIODE INCLUDING AN INSULATING SUBSTRATE AND A SCHOTTKY DIODE UNIT

Tsinghua University, Bei...

1. A Schottky diode comprising:a first electrode, wherein the first electrode comprises a first metal layer and a second metal layer, the first metal layer covers the second metal layer, one end of the second metal layer is extended with respect to the first metal layer to form a step structure in the first electrode;
a second electrode located apart from the first electrode, wherein the second electrode comprises a third metal layer and a fourth metal layer, the third metal layer covers the fourth metal layer, one end of the third metal layer protrudes with respect to the fourth metal layer to form an inverted step structure in the second electrode; and
a semiconductor structure comprising a first end and a second end, wherein the first end of the semiconductor structure is sandwiched by the first metal layer and the second metal layer, the second end of the semiconductor structure is sandwiched by the third metal layer and the fourth metal layer, a portion of the semiconductor structure between the first end and the second end is defined as a middle portion, the step structure of the first electrode and the inverted step structure of the second electrode are both located between the first end and the second end of the semiconductor structure, and near the middle portion of the semiconductor structure, the semiconductor structure is a carbon nanotube structure.

US Pat. No. 10,193,085

DELAYED FLUORESCENCE COMPOUND, AND ORGANIC LIGHT EMITTING DIODE AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. A delayed fluorescence compound of Formula 1:
wherein n is 1 or 0, wherein L2 is selected from Formula 2, X2 is selected from Formula 3, and Y is selected from Formula 4:

wherein each of R5 and R6 in the Formula 2 is independently selected from hydrogen or C1 alkyl through C10 alkyl.

US Pat. No. 10,193,082

CONDENSED-CYCLIC COMPOUND AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A condensed-cyclic compound represented by Formula 1:
wherein, in Formula 1,
Ar11 is represented by one of Formulae 10-1 to 10-4:

wherein, in Formulae 1 and 10-1 to 10-4,
X1 is N or C(R1), X2 is N or C(R2), X3 is N or C(R3), X4 is N or C(R4), X5 is N or C(R5), X6 is N or C(R6), X7 is N or C(R7), X8 is N or C(R8), X11 is N or C(R11), X12 is N or C(R12), X13 is N or C(R13), X14 is N or C(R14), X15 is N or C(R15), X16 is N or C(R16), X17 is N or C(R17), and X18 is N or C(R18);
Y11 is O, S, N(R101), C(R101)(R102), or Si(R101)(R102);
Z11 is selected from N and C(A12);
Z12 to Z14 are each independently selected from C(A11) and C(A12); and at least one of Z12 to Z14 is C(A11); and
A11 comprises at least one cyano group (CN); and A11 is represented by one of Formulae 2-1 to 2-10:

wherein, in Formulae 2-1 to 2-10,
X21 is N or C(R21), X22 is N or C(R22), X23 is N or C(R23), X24 is N or C(R24), and X25 is N or C(R25);
A12, R1 to R8, R11 to R18, R101, R102, R21 to R25, and R201 to R203 are each independently selected from
a hydrogen, a deuterium, —F, a hydroxyl group, a cyano group (CN), a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group;
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one selected from a deuterium, —F, a hydroxyl group, a cyano group (CN), a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof;
a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group;
a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group, each substituted with at least one selected from a deuterium, —F, a hydroxyl group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, a dibenzothiophenyl group, and —Si(Q1)(Q2)(Q3); and
—Si(Q11)(Q12)(Q13),
b201 is selected from 1, 2, 3, 4, and 5;
b202 and b203 are each independently selected from 1, 2, 3, and 4; and
* indicates a carbon atom in Formula 1,
wherein Q1 to Q3 and Q11 to Q13 are each independently selected from a hydrogen, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group.

US Pat. No. 10,193,079

MATERIALS FOR ELECTRONIC DEVICES

Merck Patent GmbH, (DE)

1. A compound of the formula (I)
or a compound containing exactly two or three units of the formula (I) joined to one another via a single bond or an L group,
where:
L is any divalent or trivalent organic group;
A is a group of the formula (A)

bonded via the dotted bond;
Ar1 is the same or different at each instance and is an aromatic or heteroaromatic ring system which has 5 to 30 aromatic ring atoms and may be substituted by one or more R1 radicals;
Y is the same or different at each instance and is a single bond, BR1, C(R1)2, Si(R1)2, NR1, PR1, P(?O)R1, O, S, S?O or S(?O)2;
B is the same or different at each instance and is selected from H, a straight-chain alkyl group having 1 to 10 C atoms or a branched or cyclic alkyl group having 3 to 10 C atoms, each of which may be substituted by one or more R1 radicals, or an aryl group having 6 to 14 aromatic ring atoms, each of which may be substituted by one or more R1 radicals;
RA is the same or different at each instance and is CF3, CN, and an E group, which is an aryl or heteroaryl group which has 6 to 14 aromatic ring atoms and may be substituted by one or more R1 radicals, and which contains one or more V groups as constituents of the aromatic ring, where the V groups are the same or different at each instance and are selected from ?N—, ?C(F)—, ?C(CN)— and ?C(CF3)—, and where the heteroaryl group is not bonded via a nitrogen atom;
RB is selected from H, a straight-chain alkyl group having 1 to 10 carbon atoms or a branched or cyclic alkyl group having 3 to 10 carbon atoms, each of which may be substituted by one or more R1 radicals, and an aryl group having 6 to 14 aromatic ring atoms, which may be substituted by one or more R1 radicals;
R1 is the same or different at each instance and is H, D, F, C(?O)R2, CN, Si(R2)3, N(R2)2, P(?O)(R2)2, OR2, S(?O)R2, S(?O)2R2, a straight-chain alkyl or alkoxy group having 1 to 20 carbon atoms or a branched or cyclic alkyl or alkoxy group having 3 to 20 carbon atoms, where the abovementioned groups may each be substituted by one or more R2 radicals and where one or more CH2 groups in the abovementioned groups may be replaced by —R2C?CR2—, —C?C—,Si(R2)2, C?O, C?NR2, —C(?O)O—, —C(?O)NR2—, NR2, P(?O)(R2), —O—, —S—, SO or SO2, or an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, each of which may be substituted by one or more R2 radicals, where two or more R1 radicals may be joined to one another and may form a ring;
R2 is the same or different at each instance and is H, D, F or an aliphatic, aromatic or heteroaromatic organic radical having 1 to 20 carbon atoms, in which one or more hydrogen atoms may also be replaced by D or F; at the same time, two or more R2 substituents may be joined to one another and may form a ring.

US Pat. No. 10,193,077

BISCARBAZOLE DERIVATIVE, MATERIAL FOR ORGANIC ELECTROLUMINESCENCE DEVICE AND ORGANIC ELECTROLUMINESCENCE DEVICE USING THE SAME

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device comprising:a cathode;
an anode; and
a plurality of organic thin-film layers provided between the cathode and the anode, wherein
at least one of the organic thin-film layers is an emitting layer comprising a first host material, a second host material and a phosphorescent material that exhibits a phosphorescence,
the first host material is a compound represented by a formula (4) below, and
the second host material is a compound represented by a formula (5) below,

where
A1 represents a substituted or unsubstituted nitrogen-containing heterocyclic group having 1 to 30 ring carbon atoms,
when A1 has a substituent, the substituent of A1 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
A2 represents a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted nitrogen-containing heterocyclic group having 1 to 30 ring carbon atoms,
when A2 has a substituent, the substituent of A2 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
X1 and X2 are each a linking group and independently represent a single bond, substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms,
when X1 has a substituent and/or X2 has a substituent, the substituent for X1 and X2 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
Y1, Y3 and Y4 each independently represent a hydrogen atom, a fluorine atom, a cyano group, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted alkylsilyl group having 1 to 10 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 30 carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, a substituted or unsubstituted aromatic heterocyclic group having 2 to 30 ring carbon atoms, or a substituted or unsubstituted fused aromatic heterocyclic group having 2 to 30 ring carbon atoms,
Y2 represents a hydrogen atom, a fluorine atom, a cyano group, an unsubstituted alkyl group having 1 to 20 carbon atoms, an unsubstituted alkoxy group having 1 to 20 carbon atoms, an unsubstituted haloalkyl group having 1 to 20 carbon atoms, an unsubstituted haloalkoxy group having 1 to 20 carbon atoms, an unsubstituted alkylsilyl group having 1 to 10 carbon atoms, an unsubstituted arylsilyl group having 6 to 30 carbon atoms, an unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, an unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, an unsubstituted aromatic heterocyclic group having 2 to 30 ring carbon atoms, or an unsubstituted fused aromatic heterocyclic group having 2 to 30 ring carbon atoms,
adjacent ones of Y1 to Y4 are optionally bonded to each other to form a ring structure,
p and q represent an integer of 1 to 4, and r and s represent an integer of 1 to 3, and
when p and q are an integer of 2 to 4 and r and s are an integer of 2 to 3, a plurality of Y1 to Y4 may be the same or different,
(Cz?)aA3  (5)
where:
Cz represents a substituted or unsubstituted arylcarbazolyl group or carbazolylaryl group;
A3 represents a group represented by a formula (7A) below; and
a represents an integer of 1 to 3,
(M1)c?(L5)d?(M2)e  (7A)
where:
M1 and M2 each independently represent a substituted or unsubstituted nitrogen-containing fused aromatic heterocyclic ring having 2 to 40 ring carbon atoms, M1 and M2 being optionally the same or different;
L5 represents a single bond, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 carbon atoms, a substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 carbon atoms, a substituted or unsubstituted cycloalkylene group having 5 to 30 carbon atoms, or a substituted or unsubstituted fused aromatic heterocyclic group having 2 to 30 carbon atoms; and
c represents an integer of 0 to 2, d represents an integer of 1 to 2, and e represents an integer of 0 to 2 with a proviso that c+e is 1 or more.

US Pat. No. 10,193,075

ANILINE DERIVATIVE AND USE THEREOF

NISSAN CHEMICAL INDUSTRIE...

1. An aniline compound characterized by having formula (1)
wherein R1 to R5 are each independently a hydrogen atom, a halogen atom, a nitro group, a cyano group, or an alkyl group of 1 to 20 carbon atoms, alkenyl group of 2 to 20 carbon atoms, alkynyl group of 2 to 20 carbon atoms, aryl group of 6 to 20 carbon atoms or heteroaryl group of 2 to 20 carbon atoms which may be substituted with a halogen atom;
each Ph1 is independently a group of formula (P1)

(R6 to R9 being each independently a hydrogen atom, a halogen atom, a nitro group, a cyano group, or an alkyl group of 1 to 20 carbon atoms, alkenyl group of 2 to 20 carbon atoms, alkynyl group of 2 to 20 carbon atoms, aryl group of 6 to 20 carbon atoms or heteroaryl group of 2 to 20 carbon atoms which may be substituted with a halogen atom);
each Ar1 is independently a group having any of formulas (A1) to (A14);

and m is an integer from 3 to 5.

US Pat. No. 10,193,072

PYRENE-BASED COMPOUND AND ORGANIC LIGHT-EMITTING DIODE COMPRISING THE SAME

Samsung Display Co., Ltd....

1. A pyrene-based compound represented by Formula 1;or a pyrene-based compound being one of Compounds 5, 7, 15, 17, 36, 37, and 45 below:


wherein, in Formula 1,
L1 and L2 are each independently selected from
a phenylene group, a pentalenylene group, an indenylene group, a naphthylene group, an azulenylene group, a heptalenylene group, an indacenylene group, an acenaphthylene group, a fluorenylene group, a spiro-fluorenylene group, a phenalenylene group, a phenanthrenylene group, an anthrylene group, a fluoranthenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a naphthacenylene group, a picenylene group, a perylenylene group, a pentaphenylene group, a hexacenylene group, a pyrrolylene group, an imidazolylene group, a pyrazolylene group, a pyridinylene group, a pyrazinylene group, a pyrimidinylene group, a pyridazinylene group, an isoindolylene group, an indolylene group, an indazolylene group, a purinylene group, a quinolinylene group, a benzoquinolinylene group, a phthalazinylene group, a naphthyridinylene group, a quinoxalinylene group, a quinazolinylene group, a cinnolinylene group, a phenanthridinylene group, an acridinylene group, a phenanthrolinylene group, a phenazinylene group, a benzooxazolylene group, a furanylene group, a benzofuranylene group, a thiophenylene group, a benzothiophenylene group, a thiazolylene group, an isothiazolylene group, a benzothiazolylene group, an isoxazolylene group, an oxazolylene group, a tetrazolylene group, a triazinylene group, a benzooxazolylene group, a benzocarbazolylene group, and a dibenzosilolylene group; each optionally substituted with at least one selected from
a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group,
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof,
a C6-C20 aryl group, and
a C6-C20 aryl group each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group;
R1 is one of the groups represented by Formulae 4-1(3), 4-2(1), 4-4(2), 4-4(3), 4-6(1), and 4-6(2):

wherein, in Formulae 4-1(3), 4-2(1), 4-4(2), 4-4(3), 4-6(1), and 4-6(2), Z11 and Z21 and Z21 to Z26 are each independently selected from
a hydrogen atom, a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group,
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a guinolinyl group, and an isoguinolinyl group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group, and
—Si(Q13)(Q14)(Q15) (where Q13 to Q15 are each independently a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, or an isoquinolinyl group);
R2 is selected from
a hydrogen atom, a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group,
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, an isoquinolinyl group, a quinoxalinyl group,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, an isoquinolinyl group, a quinoxalinyl group, a dibenzopuranyl group, and a dibenzothiophenyl group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group, and
?Si(Q3)(Q4)(Q5),
wherein Q3 to Q5 are each independently a C1-C20 alkyl group, a alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridatinyl group, a triatinyl group, a quinolinyl group, or an isoquinolinyl group;
a1 and b1 are each independently an integer from 1 to 5; and
a2 and b2 are each independently an integer from 0 to 5.

US Pat. No. 10,193,066

APPARATUS AND TECHNIQUES FOR ANISOTROPIC SUBSTRATE ETCHING

VARIAN SEMICONDUCTOR EQUI...

12. A method of etching a substrate to form a surface feature, comprising:providing a chlorine-containing gas to a plasma chamber;
generating a plasma in the plasma chamber, the plasma comprising an etchant species derived from the chlorine-containing gas;
extracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to the substrate, the pulsed ion beam comprising an ON portion and an OFF portion; and
pulsing a level of RF power of the plasma in concert with the pulsed ion beam, wherein the plasma comprises a first RF power level during the ON portion and a second RF power level during the OFF portion, wherein the first RF power level is higher than the second RF power level,
wherein a duration of the OFF portion is less than a transit time of the etchant species from the plasma chamber to the substrate.

US Pat. No. 10,193,063

SWITCHING DEVICE FORMED FROM CORRELATED ELECTRON MATERIAL

ARM Ltd., Cambridge (GB)...

1. A method of constructing a switching device, comprising:forming, in a chamber, one or more voids between adjacent conductive traces of a plurality of conductive traces formed over an insulating substrate; and
converting localized portions of at least some of the adjacent conductive traces of the plurality of conductive traces to a correlated electron material (CEM), the CEM comprising an atomic concentration of at least 85.0% of an oxide of a d-block element or of an oxide of an f-block element, or an alloy of two or more oxides of d-block or f-block elements.

US Pat. No. 10,193,062

MGO INSERTION INTO FREE LAYER FOR MAGNETIC MEMORY APPLICATIONS

Headway Technologies, Inc...

29. A method of forming a magnetic element exhibiting interfacial perpendicular anisotropy at a first interface between a composite free layer and a first oxide layer or a first non-magnetic metal or alloy (NM1) layer, at a second interface between the composite free layer and a second oxide layer or a second non-magnetic metal or alloy (NM2) layer, and at a plurality of interfaces where the composite free layer contacts a plurality of metal oxide regions in two metal layers each having a non-stoichiometric oxidation state that are formed within the composite free layer, comprising:(a) providing the first oxide layer or the NM1 layer on a substrate;
(b) depositing a first free layer (FL1) on the first oxide layer or the NM1 layer;
(c) depositing a first metal layer (M) or a first alloy (MQ) layer on FL1 where M is a first metal and Q is a second metal;
(d) depositing a second free layer (FL2) on the first M layer or first MQ layer;
(e) depositing a second metal layer (M2) or a second alloy layer (M2Q2) on the FL2;
(f) depositing a third free layer (FL3) on the M2 layer or M2Q2 layer to give the composite free layer comprising a FL1/M/FL2/M2/FL3, FL1/M/FL2/M2Q2/FL3, FL1/MQ/FL2/M2Q2/FL3, or FL1/MQ/FL2/M2/FL3 stack of layers;
(g) depositing the second oxide layer or the NM2 layer on a top surface of the composite free layer that faces away from the first oxide or NM1 layer; and
(h) performing an annealing step such that during one or more of steps (f), (g), and (h) a plurality of M and/or Q metal atoms in the M, M2, MQ, and M2Q2 layers scavenge oxygen from one or more layers in the magnetic element, and react with the scavenged oxygen to form a plurality of metal oxide regions on the M or MQ layer that interface with portions of the FL1 and the FL2, and a plurality of metal oxide regions on the M2 or M2Q2 layer that interfaces with portions of the FL2 and the FL3 thereby enhancing perpendicular magnetic anisotropy (PMA) in the composite free layer.

US Pat. No. 10,193,061

SPIN-ORBIT TORQUE MAGNETIZATION ROTATIONAL ELEMENT

TDK CORPORATION, Tokyo (...

1. A spin-orbit torque magnetization rotational element comprising:a ferromagnetic metal layer, a magnetization direction of which is configured to be changed;
a spin-orbit torque wiring bonded to the ferromagnetic metal layer; and
an interfacial distortion supply layer bonded to a surface of the spin-orbit torque wiring on a side opposite to the ferromagnetic metal layer,
wherein a degree of lattice mismatching between the spin-orbit torque wiring and the interfacial distortion supply layer is 5% or more.

US Pat. No. 10,193,060

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A magnetoresistive random access memory (MRAM) device, comprising:an insulating interlayer on a substrate, the insulating interlayer including an opening therethrough;
a first electrode in a lower portion of the opening, the first electrode having a pillar shape;
a second electrode on a sidewall of the opening, the second electrode contacting an edge portion of the first electrode and vertically protruding from an upper surface of the first electrode, and an upper surface of the second electrode having a ring shape;
an insulation pattern on the second electrode, the insulation pattern filling an upper portion of the opening; and
a variable resistance structure on the second electrode and the insulation pattern, the variable resistance structure including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked, wherein
the variable resistance structure includes a plurality of variable resistance structures,
an upper surface of the insulating interlayer between the plurality of variable resistance structures is lower than the upper surface of the second electrode, and is higher than the upper surface of the first electrode, and
an upper surface of the insulating interlayer under the variable resistance structure is higher than the upper surface of the insulating interlayer between the plurality of variable resistance structures.

US Pat. No. 10,193,056

MINIMAL THICKNESS SYNTHETIC ANTIFERROMAGNETIC (SAF) STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY FOR STT-MRAM

Headway Technologies, Inc...

1. A synthetic antiferromagnetic free layer structure, comprising:(a) a FL2 layer with intrinsic perpendicular magnetic anisotropy that is comprised of an (A1/A2)n laminate where n is an integer less than 6, A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Mg, Si, V, NiCo, and NiFe, or A1 is Fe and A2 is V, and wherein a magnetization direction thereof is perpendicular-to-plane of the FL2 layer;
(b) a CoFeB layer with perpendicular magnetic anisotropy in which a magnetization direction in said CoFeB layer is perpendicular-to-plane of the CoFeB layer and is established by antiferromagnetic coupling with the FL2 layer through an antiferromagnetic coupling layer formed between the FL2 layer and CoFeB layer; and
(c) the antiferromagnetic coupling layer that is made of a non-magnetic material to give an FL2 layer/antiferromagnetic coupling/CoFeB configuration or a CoFeB/antiferromagnetic coupling/FL2 layer configuration in a magnetic tunnel junction.

US Pat. No. 10,193,054

PIEZOELECTRIC CERAMIC, METHOD FOR PRODUCING PIEZOELECTRIC CERAMIC, AND PIEZOELECTRIC CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A piezoelectric ceramic comprising an alkali niobate compound as a main ingredient, the alkali niobate compound having a perovskite crystal structure represented by AmBO3 and containing at least one alkali metal, whereinSn exists in part of site A and Zr exists in part of site B.

US Pat. No. 10,193,052

DEVICE AND INSPECTION METHOD OF THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A device comprising:a substrate;
an element provided on the substrate;
a film on the substrate, the film and the substrate constituting a cavity in which the element is housed; and
a member provided outside the cavity, and capable of generating heat,
wherein the member generates the heat when current flows through the member.

US Pat. No. 10,193,050

HANDLE FOR A COOKING VESSEL, COMPRISING A LATENT HEAT SINK

SEB S.A., Ecully (FR)

1. A handle for a cooking vessel or lid that comprises at least one thermoelectric generator, wherein the thermoelectric generator comprises at least one first contact surface connected thermally to a heat sink, and the heat sink is comprised of a material that undergoes a phase transition when the material is heated to temperatures of 50° C. to 70° C.,wherein the heat sink fills a cavity of the handle with a heat diffuser comprising one or more rods that extend through the heat sink.

US Pat. No. 10,193,049

THERMOELECTRIC GENERATOR UNIT

FAURECIA EMISSIONS CONTRO...

1. A thermoelectric generator unit, in particular for coupling to an exhaust gas pipe of an internal combustion engine, comprising:at least one inner tube having gas flowing therein and an outer circumference that comprises at least one flat portion,
an oval outer housing completely surrounding at least one the inner tube in a circumferential direction, and wherein the outer housing comprises two housing shells which meet each other at a short axis area of the outer housing and are fastened to each other in this area,
a plurality of thermoelectric modules arranged on the at least one flat portion of the at least one inner tube,
at least one cooling element comprising a cooling channel having an outer wall with a flat side on which the thermoelectric modules are arranged, wherein a first portion of an outer circumference of the outer wall substantially corresponds to a curvature of the outer housing and a second portion of the outer circumference of the outer wall is substantially flat,
an assembly unit made up of the at least one inner tube, the plurality of thermoelectric modules, and the at least one cooling element, the assembly unit being surrounded by an elastic compensation element that rests on an inner side of the outer housing and is retained in the outer housing by clamping, and
wherein at least one gas-carrying channel and a bypass channel are provided in an interior of the other housing, and wherein hot gas can be selectively directed through the at least one gas-carrying channel and/or the bypass channel.

US Pat. No. 10,193,045

LIGHT EMITTING DEVICE HAVING HEAT DISIPATION TERMINAL ARRANGED ON SUBSTRATE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate having a first main surface, a second main surface that is opposite from the first main surface, and a mounting surface that is adjacent to at least the second main surface, the substrate including an insulating base material and a pair of connection terminals;
a plurality of light emitting elements mounted on the first main surface of the substrate;
a sealing member that is in contact with at least a part of a side surface of each of the light emitting elements, is formed substantially in the same plane as the substrate on the mounting surface, and a width of the sealing member between adjacent ones of the light emitting elements is larger than a width of the sealing member on an outside of an outermost one of the light emitting elements;
a light transmissive member that covers upper surfaces of the light emitting elements and a part of an upper surface of the sealing member, side surfaces of the light transmissive member being covered with the sealing member; and
a heat dissipation terminal that is arranged generally in the center on the second main surface of the substrate and that has a recess portion as viewed along a direction normal to the second main surface.

US Pat. No. 10,193,043

LIGHT EMITTING DEVICE PACKAGE WITH REFLECTIVE SIDE COATING

LUMILEDS LLC, San Jose, ...

1. A light-emitting device, comprising:a substrate;
a semiconductor structure disposed on the substrate, the semiconductor structure having an active region disposed between an n-type layer and a p-type layer;
a wavelength converter formed above the substrate;
an insulating side coating formed around the semiconductor structure; and
a reflective side coating formed around the wavelength converter and the substrate, the reflective side coating being stacked over the insulating side coating, the reflective side coating having a top surface that is flush with a top surface of the wavelength converter, and the reflective side coating having a bottom surface that is disposed above a top surface of the insulating side coating.

US Pat. No. 10,193,042

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a driving circuit disposed on the substrate;
a light-emitting unit disposed on the driving circuit and electrically connected to the driving circuit, wherein the light-emitting unit comprises:
a first semiconductor layer;
a quantum well layer disposed on the first semiconductor layer; and
a second semiconductor layer disposed on the quantum well layer, and the second semiconductor layer comprises a first top surface; and
a first protective layer disposed on the driving circuit and adjacent to the light-emitting unit, and the first protective layer comprises a second top surface and a plurality of conductive elements formed therein,
wherein an elevation of the first top surface is higher than an elevation of the second top surface.

US Pat. No. 10,193,040

LED PACKAGE WITH A PLURALITY OF LED CHIPS

Rohm Co., Ltd., Kyoto (J...

1. An LED package comprising:a substrate having a substrate main surface and a substrate back surface, which face opposite sides in a thickness direction;
a main surface electrode which is disposed on the substrate main surface, the main surface electrode including:
a first pad and a first die pad separated from each other, and
a second pad and a second die pad connected to each other;
a first LED chip which is mounted on the first die pad and has an electrode pad formed on a first chip main surface facing the same direction as the substrate main surface;
a first wire connecting the first pad and the electrode pad;
a second LED chip which is mounted on the second die pad and has a first electrode pad formed on a second chip main surface facing the same direction as the substrate main surface; and
a second wire connecting the second pad and the first electrode pad,
wherein the substrate main surface has a first side along a first direction perpendicular to the thickness direction of the substrate and a second side along a second direction perpendicular to both the thickness direction of the substrate and the first direction,
the first pad has a first base portion in contact with both the first side and the second side of the substrate main surface, and a first pad portion having one end connected to the first base portion,
the first pad portion of the first pad extends from the first base portion toward the first die pad, obliquely with respect to both the first direction and the second direction,
the second pad has a second base portion in contact with the first side of the substrate main surface, and a second pad portion having one end connected to the second base portion, and
the second pad portion of the second pad extends along the second direction.

US Pat. No. 10,193,039

METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEM

NICHIA CORPORATION, Anan...

1. A light emitting element mounting base member comprising:recesses formed on at least one surface of the light emitting element mounting base member;
a plurality of electrical conductor cores;
a plurality of light-reflecting insulating members that each cover a lateral surface of each of the electrical conductor cores; and
a light blocking resin that is disposed between the insulating members,
wherein the light blocking resin exposes one or more upper surfaces of the electrical conductor cores, one or more lower surfaces of the electrical conductor cores, and the insulating members disposed around the one or more upper surfaces and the one or more lower surfaces of the electrical conductor cores, and
the light blocking resin serves as lateral surfaces of recesses.

US Pat. No. 10,193,033

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements each having a pair of electrodes on a lower surface thereof;
a light-transmissive member disposed on an upper surface of each of the light emitting elements to transmit light from the light emitting elements;
a first member disposed on one or more lateral surfaces of the light-transmissive member, and constituting part of an upper surface of the light emitting device with an upper surface of the light-transmissive member being exposed from the first member; and
a second member surrounding an outer periphery of each of the light emitting elements, and constituting part of a bottom-most surface of the light emitting device,
wherein lower surfaces of the electrodes are exposed from the second member to constitute part of the bottom-most surface of the light emitting device,
the first member and the second member respectively constitute parts of an outermost lateral surface of the light emitting device, and
the second member is in contact with a part of each of the light emitting elements.

US Pat. No. 10,193,032

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a light emitting device comprising:providing a substrate including a placement region for placing a light emitting element on a top surface;
mounting the light emitting element in the placement region; and
forming a frame body surrounding the placement region on the substrate by
arranging a first frame body by discharging a resin material on the substrate to surround the placement region, and
successively arranging a second frame body having a larger diameter than the first frame body on the first frame body and having the same thickness as the first frame body by continuously discharging the resin material from the arranging of the first frame body.

US Pat. No. 10,193,029

LIGHT CONVERSION DEVICE AND DISPLAY DEVICE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A light conversion device, comprising:a light source; and
a light conversion film provided on one surface of the light source,
wherein the light conversion film includes a first light conversion film containing one first organic fluorescent dye, and a second light conversion film disposed to be closer to the light source than the first light conversion film and containing one second organic fluorescent dye, and a maximum light emission wavelength of the second light conversion film is smaller than a maximum light emission wavelength of the first light conversion film when the light is irradiated from the light source,
wherein the second organic fluorescent dye of the second light conversion film is a green emission fluorescent dye having a maximum emission wavelength of 500 to 550 nm and the first organic fluorescent dye of the first light conversion film is a red emission fluorescent dye having a maximum emission wavelength of 600 to 660 nm, and
wherein the organic fluorescent dye has a full width at half maximum (FWHM) of 60 nm or less and a molecular absorption coefficient of 50,000 to 150,000 M?1 cm?1.

US Pat. No. 10,193,027

LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a resin package comprising:
a plurality of leads that includes:
a first lead having an upper surface, and
a second lead having an upper surface,
a first resin portion having at least one inner lateral wall surface,
a second resin portion, and
a third resin portion having an upper surface,
the plurality of leads and the at least one inner lateral wall surface of the first resin portion defining a recess,
the third resin portion being located between the first lead and the second lead,
the upper surface of the first lead, the upper surface of the second lead and the upper surface of the third resin portion located at a bottom of the recess, and
the second resin portion disposed surrounding an element mounting region at the bottom of the recess; and
at least one light emitting element disposed on the element mounting region at the bottom of the recess of the resin package,
wherein at least one of the at least one inner lateral wall surface of the recess has at least one protruding portion that protrudes toward the at least one light emitting element, and
wherein a region of the recess between the at least one inner lateral wall surface and the second resin portion is covered by a light-reflective member.

US Pat. No. 10,193,023

LIGHT-EMITTING DIODE CHIP

PlayNitride Inc., Tainan...

1. A light-emitting diode chip, comprising:a p-type semiconductor layer;
a light-emitting layer;
an n-type semiconductor layer, the light-emitting layer being disposed between the p-type semiconductor layer and the n-type semiconductor layer, and the n-type semiconductor layer comprising:
a first n-type semiconductor sub-layer;
a second n-type semiconductor sub-layer; and
an ohmic contact layer, disposed between the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer, wherein the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer are separated by the ohmic contact layer; and
a first metal electrode, disposed on the first n-type semiconductor sub-layer, wherein a region of the first n-type semiconductor sub-layer located between the first metal electrode and the ohmic contact layer contains metal atoms diffusing from the first metal electrode, such that ohmic contact is formed between the first metal electrode and the ohmic contact layer.

US Pat. No. 10,193,013

LED STRUCTURES FOR REDUCED NON-RADIATIVE SIDEWALL RECOMBINATION

Apple Inc., Cupertino, C...

1. A light emitting diode (LED) comprising:a p-n diode layer including:
a top doped layer doped with a first dopant type;
a bottom doped layer doped with a second dopant type opposite the first dopant type; and
an active layer between the top doped layer and the bottom doped layer; and
p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer; and
a semiconductor passivation layer formed on the p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer, wherein the semiconductor passivation layer spans underneath the bottom doped layer and completely covers a bottom surface of the bottom doped layer.

US Pat. No. 10,193,012

TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED

Goertek, Inc., Shandong ...

1. A method for transferring micro-LED, comprising:transferring at least one micro-LED from an original substrate to a support body;
transferring the at least one micro-LED from the support body to a backup substrate; and
transferring the at least one micro-LED from the backup substrate to a receiving substrate, wherein:
the original substrate is laser-transparent;
the support body is transparent;
transferring the at least one micro-LED from the original substrate to the support body comprises:
mounting the original substrate onto the support body, wherein micro-LEDs are formed on the original substrate, the support body has light-release adhesive on a surface of the support body, and the micro-LEDs are adhered to the support body via the light-release adhesive,
irradiating the original substrate with a laser from the original substrate side, to selectively lift-off the at least one micro-LED from the original substrate, and
irradiating light from the support body side, to release un-lifted-off micro-LEDs; and
transferring the at least one micro-LED from the support body to the backup substrate comprises:
bonding the support body with the at least one micro-LED to the backup substrate, and
fully irradiating light from the support body side, to release the at least one micro-LED.

US Pat. No. 10,193,007

SOLAR CELL MODULE AND METHOD FOR MANUFACTURING SAME

KANEKA CORPORATION, Osak...

1. A solar cell module comprising:a solar cell;
and a wiring member, wherein
the solar cell includes a photoelectric conversion section, a collecting electrode provided on a light-receiving side of the photoelectric conversion section, and a back electrode provided on a back side of the photoelectric conversion section,
the collecting electrode includes a plurality of finger electrodes each extending in a first direction, and a bus bar electrode extending in a second direction;
the bus bar electrode includes a first collecting electrode and a second collecting electrode stacked in this order from a photoelectric conversion section side, the second collecting electrode covering an entire length of the first collecting electrode,
the back electrode includes a first back electrode and a second back electrode stacked in this order from the photoelectric conversion section side,
the second collecting electrode and the second back electrode each have two or more layers,
a surface roughness Ral of the first collecting electrode and a surface roughness Ra2 of the second collecting electrode are configured to satisfy Ral>Ra2 and Ra2=1.0 pm to 10.0 ?m,
at least an outermost part of the second collecting electrode and at least an outermost part of the second back electrode are mainly composed of same electroconductive material,
the wiring member is composed of a core material and a conductor that covers a surface of the core material
the bus bar electrode of the solar cell and the conductor of the wiring member are electrically connected to each other, and
the solar cell is electrically connected to another solar cell via the wiring member.

US Pat. No. 10,192,998

ANALOG FLOATING-GATE ATMOMETER

TEXAS INSTRUMENTS INCORPO...

1. A method of measuring evaporation rate, comprising:applying a drain-to-source voltage to a floating-gate transistor in an integrated circuit;
capacitively coupling a voltage to a floating-gate electrode in the floating-gate transistor, to establish a gate-to-source voltage at that transistor;
then dispensing moisture at a surface of the integrated circuit at which an electrode in electrical contact with the floating-gate electrode and at least one reference electrode are exposed;
then monitoring current conducted by the floating-gate transistor to measure an elapsed time at which the current stabilizes; and
determining an evaporation rate responsive to the measured elapsed time.

US Pat. No. 10,192,996

THIN FILM TRANSISTOR, DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising:a base substrate;
an active layer on the base substrate comprising a channel region, a source electrode contact region, and a drain electrode contact region;
an etch stop layer on a side of the channel region distal to the base substrate covering the channel region;
a source electrode on a side of the source electrode contact region distal to the base substrate; and
a drain electrode on a side of the drain electrode contact region distal to the base substrate;
wherein the active layer is made of a semiconductor material comprising M1OaNb, wherein M1 is a single metal or a combination of metals, a>0, and b?0;
the source electrode and the drain electrode are made of a metal material;
the etch stop layer is made of a doped semiconductor material comprising M1OaNb doped with a dopant; the doped semiconductor material being substantially resistant to an etchant for etching the metal material; and
a thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.

US Pat. No. 10,192,995

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first insulator comprising a first region and a second region thinner than the first region;
a second insulator on and in contact with the first region of the first insulator;
a third insulator on and in contact with the second region of the first insulator;
a semiconductor over the second insulator;
a fourth insulator over the semiconductor; and
a first conductor overlapping the semiconductor with the fourth insulator interposed therebetween,
wherein the third insulator comprises fluorine,
wherein the amount of hydrogen released from the third insulator when converted into hydrogen molecules is less than or equal to 6×1014 molecules/cm2 in thermal desorption spectroscopy analysis at a surface temperature of a film of higher than or equal to 100° C. and lower than or equal to 700° C., and
wherein the third insulator does not overlap with the semiconductor.

US Pat. No. 10,192,994

OXIDE SEMICONDUCTOR FILM INCLUDING INDIUM, TUNGSTEN AND ZINC AND THIN FILM TRANSISTOR DEVICE

Sumitomo Electric Industr...

1. An oxide semiconductor film composed of nanocrystalline oxide or amorphous oxide, whereinthe oxide semiconductor film includes indium, tungsten and zinc,
a content rate of tungsten to a total of indium, tungsten and zinc in the oxide semiconductor film is higher than 0.5 atomic % and equal to or lower than 5 atomic %, and
an electric resistivity of the oxide semiconductor film is equal to or higher than 10?1 ?cm; wherein
an atomic ratio of zinc to tungsten (Zn/W ratio) in the oxide semiconductor film is equal to or higher than 3 and equal to or lower than 30.

US Pat. No. 10,192,993

THIN FILM TRANSFER, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor (TFT), comprising a substrate, a poly-silicon (p-Si) active layer arranged on the substrate, a first amorphous silicon (a-Si) layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate, and a buffer layer arranged on a surface of the substrate at a side adjacent to the first a-Si layer, wherein an orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate, a groove is formed in the buffer layer, and the first a-Si layer is arranged in the groove.

US Pat. No. 10,192,988

FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a fin structure having a top surface with substantially rounded corners, wherein upper portions of the fin structures have a surface profile including a top surface of the fin structure having corners with a radius of curvature R, where 0.1 W an isolation region formed over the substrate and in contact with at least a sidewall of the fin structure, the isolation region having a top surface with a substantially flat step height (?H?) based on a thermal hydrogen treatment, the substantially flat step height being defined by a downward slope from the sidewalls of the fin structure toward the top surface of the isolation region, the substantially flat step height (?H?) being defined by 0.1H1

US Pat. No. 10,192,985

FINFET WITH DOPED ISOLATION INSULATING LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming one or more fins over a substrate;
forming a mask layer over the one or more fins;
forming an isolation insulating layer over the one or more fins so that top surfaces of the one or more fins and mask layer are buried inside the isolation insulating layer, and the isolation insulating layer contacts side surfaces of the one or more fins and mask layer;
introducing an oxygen reactive dopant into the isolation insulating layer;
annealing the isolation insulating layer containing the dopant and oxidizing the dopant; and
removing a portion of the doped isolation insulating layer so as to expose a portion of the one or more fins.

US Pat. No. 10,192,983

LDMOS WITH ADAPTIVELY BIASED GATE-SHIELD

Silanna Asia Pte Ltd, Si...

1. A system, comprising:a lateral diffusion field effect transistor comprising:
a source region of doped semiconductor material that is electrically coupled to a metallic source contact,
a first drain region of doped semiconductor material that has a lower dopant concentration than the source region,
a second drain region of doped semiconductor material that has a higher dopant concentration than the first drain region and forms an electrically conductive path between the first drain region and a metallic drain contact,
an active region between the source region and the first drain region,
a gate dielectric between a gate electrode and the active region, wherein the active region is responsive to a control signal applied to the gate electrode, and
an electrically conductive shield plate separated from the source contact and respective portions of the gate electrode and the first drain region by an interlayer dielectric; and
a control circuit electrically coupled to the shield plate and configured to apply to the shield plate a variable voltage that is temporally offset from the control signal applied to the gate electrode, wherein the variable voltage is applied to the shield plate at a first level that increases conductivity in the first drain region in a turn-on transition of the lateral diffusion field effect transistor, and the variable voltage is applied to the shield plate at a second level that decreases conductivity in the first drain region in a turn-off transition of the lateral diffusion field effect transistor.

US Pat. No. 10,192,972

SEMICONDUCTOR FERROELECTRIC STORAGE TRANSISTOR AND METHOD FOR MANUFACTURING SAME

NATIONAL INSTITUTE OF ADV...

17. A semiconductor ferroelectric memory transistor comprising a semiconductor body which has a source region and a drain region on which an insulator and a gate electrode conductor are stacked in that order, whereinthe insulator comprises a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and the oxide of strontium, calcium, bismuth, and tantalum is represented by Sr-Ca-Bi-Ta-O.

US Pat. No. 10,192,966

SEMICONDUCTOR DEVICES INCLUDING RECESSED GATE ELECTRODE PORTIONS

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first active pattern and a second active pattern on a substrate;
a first gate electrode and a second gate electrode respectively extending across the first active pattern and the second active pattern;
an insulation pattern located between the first and second gate electrodes to separate the first and second gate electrodes from one another, and
a device isolation layer filling a trench between the first and second active patterns and covering lower sidewalls of the first and second active patterns,
wherein the first gate electrode, the insulation pattern, and the second gate electrode are arranged along a first direction, and
wherein the first gate electrode comprises:
a first part extending in the first direction; and
a second part between the first active pattern and the insulation pattern, the second part including a top surface having a height lower than a height of a top surface of the first part closest to the second part,
wherein the second part vertically overlaps with the device isolation layer, and
wherein the height of the top surface of the second part decreases with approaching the insulation pattern from the first part and then increases again after reaching an inflection point in the top surface of the second part.

US Pat. No. 10,192,965

SEMICONDUCTOR DEVICE INCLUDING FIRST AND SECOND GATE ELECTRODES AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate;
a first gate electrode formed on a main surface of the semiconductor substrate;
a first gate insulating film formed between the first gate electrode and the semiconductor substrate;
a second gate electrode formed on the semiconductor substrate and adjacent to the first gate electrode; and
a second gate insulating film formed between the second gate electrode and the semiconductor substrate and between the second gate electrode and the first gate electrode and having a charge accumulating portion therein,
wherein the semiconductor substrate includes a first region, a second region, and a third region on the main surface side,
the second region is arranged closer to a first side than the first region in a first direction in a plan view,
the third region is arranged between the first region and the second region,
the first gate electrode is formed on a first upper surface of the first region,
the second gate electrode is formed on a second upper surface of the second region,
the second upper surface is lower than the first upper surface,
the third region has a first connection surface connecting the first upper surface and the second upper surface,
the second gate insulating film is formed on the first connection surface and the second upper surface,
a first end of the first connection surface is connected to the second upper surface,
a second end of the first connection surface which is on the opposite side to the first end is connected to the first upper surface,
the first end is arranged closer to the first side than the second end in the first direction, and is arranged lower than the second end, and
the first connection surface has a constant slope between the first end and the second end wherein the semiconductor substrate includes a fourth region on the main surface side, the fourth region is arranged closer to the opposite side to the first side than the first region in the first direction in a plan view, a third upper surface of the fourth region is lower than the first upper surface, and the second upper surface is lower than the third upper surface.

US Pat. No. 10,192,964

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

FUJITSU LIMITED, Kawasak...

1. A compound semiconductor device comprising:a carrier transit layer;
a carrier supply layer over the carrier transit layer;
a source electrode and a drain electrode above the carrier supply layer;
a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and
a first insulating film, a second insulating film, and a third insulating film above the carrier supply layer between the gate electrode and the drain electrode, wherein
the gate electrode includes a portion above the third insulating film,
a first concentration of electron traps in the first insulating film is higher than a second concentration of electron traps in the second insulating film,
a third concentration of electron traps in the third insulating film is higher than the second concentration of the electron traps in the second insulating film, and
the third insulating film has a lamer size than the first insulating film in planar view.

US Pat. No. 10,192,963

COMPOSITE GATE DIELECTRIC LAYER APPLIED TO GROUP III-V SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

INSTITUTE OF MICROELECTRO...

1. A composite gate dielectric layer for a Group III-V substrate, comprising:an AlxY2-xO3 interface passivation layer formed on the group III-V substrate by thermally treating an Al2Om passivation layer formed on the group III-V substrate and a Y2On strengthening layer formed on the Al2Om passivation layer in situ to mix the Al2Om passivation layer and the Y2On strengthening layer; and
a high-k dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9.

US Pat. No. 10,192,961

SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; and
a gate insulating film provided on the first main surface,
the silicon carbide substrate including
a first body region being in contact with the gate insulating film at the first main surface and having a first conductivity type,
a second body region being in contact with the gate insulating film at the first main surface and having the first conductivity type, and
a JFET region provided between the first body region and the second body region and having a second conductivity type different from the first conductivity type,
the JFET region having both a first impurity capable of providing the first conductivity type and a second impurity capable of providing the second conductivity type,
a concentration of the second impurity being higher than a concentration of the first impurity,
the first conductivity type being p type and the second conductivity type being n type, and
the concentration of the first impurity increases from the second main surface toward the first main surface.

US Pat. No. 10,192,960

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide layer having a first main surface and a second main surface opposite to said first main surface; and
a metal region,
said silicon carbide layer including
a drift region that constitutes said first main surface and that has a first conductivity type,
a body region that is provided on said drift region and that has a second conductivity type different from said first conductivity type, and
a source region that is provided on said body region to be separated from said drift region, that constitutes said second main surface, and that has the first conductivity type,
said silicon carbide layer being provided with a trench including a first side wall portion and a first bottom surface, said first side wall portion extending from said second main surface to said drift region through said source region and said body region, said first bottom surface being in said drift region,
said silicon carbide layer including a second conductivity type region that is embedded in said drift region to face said first bottom surface and that has said second conductivity type,
said second conductivity type region being separated from said body region,
said second conductivity type region being electrically connected to said source region,
said metal region being in contact with said source region,
said source region and said second conductivity type region being electrically connected to each other via said metal region,
said silicon carbide layer being provided with a stepped portion including a second bottom surface and a second side wall portion, said second bottom surface being between said first main surface and said second main surface, said second side wall portion connecting said second bottom surface and said second main surface to each other,
said metal region being in contact with said source region in said second main surface and is in contact with said second bottom surface,
said second conductivity type region being arranged in a plane, and
said metal region being directly in contact with said second conductivity type region.

US Pat. No. 10,192,954

JUNCTIONLESS NANOWIRE TRANSISTOR AND MANUFACTURING METHOD FOR THE SAME

Wuhan China Star Optoelec...

1. A junctionless nanowire transistor, comprising:an active layer, a barrier layer, a source region, a source electrode, a drain region, a drain electrode, a gate electrode, first insulation medium and at least two channel nanowires;
wherein, the source region and the drain region are disposed on the active layer; the at least two channel nanowires are disposed above the active layer in a stacked arrangement, and two terminals of each of the at least two channel nanowires are respectively connected with the source region and the drain region; the barrier layer is located at a side of the active layer away from the source region and the drain region; the source electrode and the drain electrode are respectively disposed on the source region and the drain region; the first insulation medium is disposed between the at least two channel nanowires and the gate electrode;
the source region, the drain region and the at least two channel nanowires uses a same doping material; and
the source electrode, the drain electrode and the gate electrode are manufactured by a same material; and
the junctionless nanowire transistor further comprises a second insulation medium having a first part, a second part and a third part, wherein the first part of the second insulation medium is disposed on the active layer and surrounds bottoms of the source region, the drain region and the gate electrode so as to expose tops of the source region and the drain region, the second part and the third part of the second insulation medium are disposed at two sides of the gate electrode.

US Pat. No. 10,192,953

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to said first main surface;
an epitaxial layer formed on said first main surface, said epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which said silicon carbide substrate is located;
a trench which is formed in said epitaxial layer and includes side walls intersecting with said third main surface and a bottom portion connected to said side walls; and
an embedded region, which is formed in said trench and has a second conductivity type different from said first conductivity type, said trench being filled with said embedded region;
an opening of said trench being wider than said bottom portion, and said epitaxial layer adjacent to said embedded region and said embedded region constituting a superjunction structure, said silicon carbide semiconductor device further comprising:
an impurity region formed on said embedded region and having said second conductivity type;
a first electrode provided on said impurity region; and
a second electrode in contact with said second main surface.

US Pat. No. 10,192,948

AMOLED DISPLAY DEVICE AND ARRAY SUBSTRATE THEREOF

SHENZHEN CHINA STAR OPTOE...

1. An array substrate of an AMOLED display device, comprising a baseplate, a surface-shaped power line, a point-shaped power line, and a plurality of insulating layers arranged between the surface-shaped power line and the point-shaped power line,wherein the surface-shaped power line and the point-shaped power line are configured to provide a positive polarity power source to a light-emitting diode; and
wherein the surface-shaped power line is formed on the baseplate, the point-shaped power line is formed on the plurality of insulating layers, and the surface-shaped power line and the point-shaped power line are electrically connected to each other through a via hole;
further comprising a metal lead wire formed on an edge area thereof, wherein the metal lead wire is used for leading a power source signal to the surface-shaped power line;
wherein the metal lead wire and the point-shaped power line are arranged in a same layer, and the metal lead wire and the surface-shaped power line are electrically connected to each other through a via hole.

US Pat. No. 10,192,939

DISPLAY DEVICE AND FABRICATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising:a thin film transistor array and an organic light emitting diode (OLED) pixel array on a base substrate;
an encapsulation film encapsulating the thin film transistor array and the OLED pixel array;
a protection film over the encapsulation film, the protection film including a first retardation film;
a touch film on the protection film, the touch film including a second retardation film; and
a polarizer film on the touch film,
wherein each of the first and second retardation films includes a ?? retardation film.

US Pat. No. 10,192,937

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a display area and a non-display area;
a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels which displays a different color from a color of the first pixel column; and
data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column,
wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines,
in the non-display area, the sub lines connected to the first pixel column are connected with one another through at least one first contact hole, the sub lines connected to the second pixel column are connected with one another through at least one second contact hole, and the sub lines connected to the second pixel column are connected through the at least one second contact hole having a larger area than an area of the at least one first contact hole, through which the sub lines connected to the first pixel column are connected with one another, and
wherein a resistance of the data line connected to the first pixel column is provided to be relatively larger than a resistance of the sub lines connected to the second pixel column.

US Pat. No. 10,192,934

LIGHT-EMITTING DEVICE HAVING LIGHT EMISSION BY A SINGLET EXCITON AND A TRIPLET EXCITON

Semiconductor Energy Labo...

1. An active matrix type light emitting device comprising a pixel portion comprising:a first pixel which emits red light comprising:
a first EL element comprising a hole injecting layer and a light emitting layer between a first electrode and a second electrode;
a first current controlling TFT electrically connected to the first electrode, wherein the first current controlling TFT is configured to control a current flowing in the first EL element;
a first switching TFT configured to control a signal to be input to a gate electrode of the first current controlling TFT; and
a first capacitor electrically connected to the gate electrode of the first current controlling TFT, wherein the first capacitor is configured to maintain a voltage applied to the gate electrode of the first current controlling TFT;
a second pixel which emits green light comprising:
a second EL element comprising a hole injecting layer and a light emitting layer between a third electrode and a fourth electrode;
a second current controlling TFT electrically connected to the third electrode, wherein the second current controlling TFT is configured to control a current flowing in the second EL element;
a second switching TFT configured to control a signal to be input to a gate electrode of the second current controlling TFT; and
a second capacitor electrically connected to the gate electrode of the second current controlling TFT, wherein the second capacitor is configured to maintain a voltage applied to the gate electrode of the second current controlling TFT;
a third pixel which emits blue light comprising:
a third EL element comprising a hole injecting layer and a light emitting layer between a fifth electrode and a sixth electrode;
a third current controlling TFT electrically connected to the fifth electrode, wherein the third current controlling TFT is configured to control a current flowing in the third EL element;
a third switching TFT configured to control a signal to be input to a gate electrode of the third current controlling TFT; and
a third capacitor electrically connected to the gate electrode of the third current controlling TFT, wherein the third capacitor is configured to maintain a voltage applied to the gate electrode of the third current controlling TFT;
an insulating film over the first current controlling TFT, the second current controlling TFT, and the third current controlling TFT,
wherein the insulating film comprises a first opening, a second opening, and a third opening,
wherein the first electrode overlaps with the first opening,
wherein the third electrode overlaps with the second opening,
wherein the fifth electrode overlaps with the third opening,
wherein an upper surface of the insulating film is provided over an upper surface of the first electrode, an upper surface of the third electrode, and an upper surface of the fifth electrode,
wherein the hole injecting layer included in the first EL element, the hole injecting layer included in the second EL element, and the hole injecting layer included in the third EL element are provided as a common layer,
wherein the second electrode, the fourth electrode, and the sixth electrode are provided as a common layer,
wherein the first EL element included in the first pixel which emits red light is configured to emit light by a triplet exciton,
wherein the third EL element included in the third pixel which emits blue light is configured to emit light by a singlet exciton, and
wherein an operation voltage of the first EL element, an operation voltage of the second EL element, and an operation voltage of the third EL element are in a range of 10 V or less.

US Pat. No. 10,192,929

THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory structures vertically extending through the alternating stack, wherein each of the memory structures includes memory elements located at levels of the electrically conductive layers;
conductive structures located between the substrate and the alternating stack; and
conductive via structures, wherein each conductive via structure contacts a top surface of a respective one of the electrically conductive layers and a top surface of a respective one of the conductive structures, and is electrically insulated from a respective subset of the electrically conductive layers that is located between the respective one of the electrically conductive layers and the conductive structures,
wherein each conductive via structure comprises an upper conductive via portion located directly on, and over, the top surface of the respective one of the electrically conductive layers, and a lower conductive via portion located between a horizontal plane including the top surface of the respective one of the electrically conductive layers and a horizontal plane including the top surface of the respective one of the conductive structures; and
wherein:
each upper conductive via portion is laterally surrounded by a respective upper insulating spacer;
each lower conductive via portion is laterally surrounded by a respective lower insulating spacer; and
the upper and lower insulating spacers comprise a same dielectric material.

US Pat. No. 10,192,923

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. A photodiode array comprising:avalanche photodiodes;
an insulating layer provided at a light incident side of a semiconductor substrate, covering the avalanche photodiodes; and
quenching resistors respectively connected to the avalanche photodiodes, each quenching resistor being provided on the insulating layer and arranged to cover an edge of a semiconductor region that forms one side of each avalanche photodiode,
wherein each of the quenching resistors includes:
an upper surface,
a lower surface, and
side surfaces extending along a surface of the insulating layer in a plan view, a strip of the quenching resistor defined by the side surfaces and forming a ring-like strip shape in the plan view.

US Pat. No. 10,192,921

SOLID STATE IMAGING DEVICE FOR REDUCING DARK CURRENT, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. A solid state imaging device, comprising:a semiconductor substrate comprising a light sensing section and comprising a first surface and a second surface opposite to the first surface, wherein the first surface is at a light incident side of the semiconductor substrate;
a wiring layer on the second surface; and
at least three layers over the first surface, the at least three layers comprising a first layer, a second layer, and a third layer,
wherein the first layer and the third layer are insulating layers, and the second layer comprises a material selected from the group including hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), hafnium nitride, aluminum nitride, hafnium oxide nitride, and aluminum oxide nitride,
wherein the second layer is disposed between the first layer and third layer,
wherein the light sensing section includes at least a first light receiving surface and a second light receiving surface and a pixel separating region,
wherein the pixel separating region is disposed between the first light receiving surface and the second light receiving surface, and
wherein at least one of the first layer, the second layer, and the third layer is disposed over the first light receiving surface, the second light receiving surface, and the pixel separating region.

US Pat. No. 10,192,918

IMAGE SENSOR INCLUDING DUAL ISOLATION AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:providing a mask over a substrate, wherein the substrate has a pixel area and a periphery area;
patterning a first opening in the pixel area and a second opening in the periphery area;
etching the mask via the first opening and the second opening;
protecting an entirety of the periphery area;
etching the substrate via the first opening to form a first STI structure having a first depth;
protecting the pixel area;
etching the substrate via the second opening to form a second STI structure having a second depth deeper than the first depth;
depositing an oxide layer in the first and the second STI structures;
removing the mask and an entirety of the oxide layer located above a top surface of the substrate, wherein after removal a surface of the oxide layer is coplanar with the top surface of the substrate;
forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices; and
forming second NMOS devices and PMOS devices in the periphery area.

US Pat. No. 10,192,908

TFT ARRAY MANUFACTURING METHOD OF OPTIMIZED 4M PRODUCTION PROCESS

SHENZHEN CHINA STAR OPTOE...

1. A thin-film transistor (TFT) array manufacturing method of an optimized 4M production process, comprising:Step 10: in a first mask-based process, making a gate layer on a glass substrate and patterning the gate layer; and then, making a gate insulation layer, an active layer, a source/drain layer, and a photoresist layer;
Step 20: in a second mask-based process, subjecting the photoresist layer to exposure and development; conducting a first wet etching operation to pattern the source/drain layer to form metal line structures of source and drain areas and an active area; conducting a first oxygen ashing operation to reduce a size of trailing of the active layer on edges of the source/drain metal layer; conducting a first dry etching operation to form an active layer island structure; conducting a second oxygen ashing operation to reduce a thickness of the photoresist layer in order to expose portions of the source/drain layer in a channel area; conducting a second wet etching operation to pattern a source and a drain; conducting a third oxygen ashing operation to reduce trailing of the contact layer; and conducting a second dry etching operation to etch the active layer so as to form a thin-film transistor structure;
Step 30: in a third mask-based process, making a passivation layer and patterning the passivation layer; and
Step 40: in a fourth mask-based process, making a transparent electrode layer and patterning the transparent electrode layer.

US Pat. No. 10,192,906

TOUCH DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a touch display substrate, comprising steps of:forming a touch signal line on a base substrate through patterning process;
depositing a photoresist layer and forming a first thickness photoresist layer, a second thickness photoresist layer, and a photoresist layer opening area through patterning process, the touch signal line being located in the photoresist layer opening area;
depositing a first insulating layer on the photoresist layer, the first insulating layer comprising a first area and a second area, wherein the first area is located on the first thickness photoresist layer, the second area is located on the second thickness photoresist layer and the photoresist layer opening area, the first area and the second area of the first insulating layer are disconnected;
removing the photoresist layer and the first insulating layer located on the photoresist layer; and
depositing a second insulating layer.

US Pat. No. 10,192,905

ARRAY SUBSTRATES AND THE MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, the method adopting four masking processes to obtain the array substrate and at least one pixel electrode within the array substrate, wherein a second masking process to form an active layer, a source electrode, and a drain electrode comprising:forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence;
applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask;
under protection of the first photo-resistor mask, applying a first wet etching process to etch a portion of the metal thin-film layer that is not covered by the first photo-resistor mask;
under the protection of the first photo-resistor mask, applying a first dry etching process to etch portions of the semiconductor thin-film layer and the N+ doping thin-film layer that are not covered by the first photo-resistor mask to obtain the active layer;
applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask, and the metal thin-film layer is exposed by a central area of the second photo-resistor mask;
under the protection of the second photo-resistor mask, applying a second wet etching process to etch away a portion of the metal thin-film layer that is not covered by the second photo-resistor mask to obtain the source electrode and the drain electrode; and
peeling off the second photo-resistor mask, applying a second dry etching process to etch away the portion of the N+ doping thin-film layer between the source electrode and the drain electrode to obtain the N+ contact layer respectively between the source electrode and the active layer and between the drain electrode and the active layer.

US Pat. No. 10,192,903

METHOD FOR MANUFACTURING TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a TFT substrate, comprising:step 101: providing a substrate and depositing a buffer layer on the substrate, wherein the substrate includes a drive TFT region and a display TFT region;
step 102: depositing a first amorphous silicon layer on the buffer layer, and performing excimer laser annealing on the first amorphous silicon layer so as to convert the first amorphous silicon layer into a first polysilicon layer through crystallization;
patterning the first polysilicon layer, to obtain a first active layer that is located in the drive TFT region;
step 103: depositing a gate insulating layer on the first active layer and the buffer layer;
depositing and patterning a first metal layer on the gate insulating layer, to form a first gate electrode at a position corresponding to position of the first active layer and form a second gate electrode at a position corresponding to position where the first active layer is not arranged;
step 104: implanting ions into the gate insulating layer taking the first gate electrode and the second gate electrode as a shading layer;
step 105: depositing an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode, depositing a second amorphous silicon layer on the interlayer insulating layer, implanting ions into the second amorphous silicon layer, and performing solid phase crystallization on the second amorphous silicon layer so as to convert the second amorphous silicon layer into a second polysilicon layer;
patterning the second polysilicon layer to form a second active layer at a position corresponding to the second gate electrode;
wherein the second amorphous silicon layer is implanted with boron (B) ions;
step 106: forming a first via hole and a second via hole in the gate insulating layer and the interlayer insulating layer corresponding to the first active layer, and forming a third via hole in the interlayer insulating layer corresponding to the second gate electrode;
step 107: depositing a source-drain electrode layer, patterning the source-drain electrode layer, and forming a channel on a surface of the second active layer at the same time;
step 108: depositing a passivation layer and patterning the passivation layer, depositing a flat layer on the passivation layer, and forming a fourth via hole in the flat layer at a position thereof in the display TFT region, the fourth via hole extending to a surface of the source-drain electrode layer; and
step 109: depositing an anode electrode on the flat layer, the anode electrode being in contact with the source-drain electrode layer through a fourth via hole, depositing a pixel definition layer, and defining a pattern, so that the TFT substrate is manufactured.

US Pat. No. 10,192,902

LTPS ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A low temperature poly-silicon (LTPS) array substrate, comprising:a substrate;
a source electrode and a drain electrode, which are arranged on the substrate;
a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode;
an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode;
a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT);
a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode;
a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate;
a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole;
a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole;
wherein the poly-silicon layer has a first region that is stacked atop and covers an inner part of each of the source electrode and the drain electrode and a portion of the substrate that is between the source electrode and the drain electrode and a second region that is integrally extended from the first region and is partly stacked atop and covers an outer part of each of the source electrode and the drain electrode; and
wherein the first region of the poly-silicon has a thickness that is greater than a thickness of the second region of the poly-silicon and the first region of the poly-silicon has a lower part in direct contact with the inner parts of the source electrode and the drain electrode and the portion of substrate between the source electrode and the drain electrode and an upper part that forms a first portion of the insulating layer; and the second region of the poly-silicon, in the entirety thereof, forms a second portion of the insulating layer that integrally extends from the first portion of the insulating layer, such that the insulating layer is integrally combined with the lower part of the poly-silicon layer and is extended to cover the source electrode and the drain electrode.

US Pat. No. 10,192,901

ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode (OLED) display comprising:a substrate;
a transistor on the substrate; and
an organic light emitting diode (OLED) connected to the transistor,
wherein the transistor includes:
a semiconductor member on the substrate,
an insulating member on the semiconductor member,
a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and
a gate electrode on the insulating member,
wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

US Pat. No. 10,192,899

DISPLAY AND MANUFACTURE METHOD THEREOF

AU OPTRONICS CORPORATION,...

1. A display, comprising:a first substrate;
a second substrate;
a plurality of pixels, disposed between the first substrate and the second substrate;
a seal disposed between the first substrate the second substrate; and
a photo-catalyst layer, disposed above a surface of the second substrate facing the first substrate or above a surface of the first substrate facing the second substrate, wherein the photo-catalyst layer and the plurality of pixels are located at two opposite sides of the seal respectively;
wherein each of the plurality of pixels comprises a transistor, and each of the transistors comprises a gate electrode, a source electrode, and an active layer, wherein the photo-catalyst layer and the gate electrode, or the photo-catalyst layer and the source electrode are belonging to a same first film layer.

US Pat. No. 10,192,898

DISPLAY DEVICE INCLUDING HYBRID TYPES OF TRANSISTORS

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a first gate electrode and a second gate electrode disposed on the substrate, wherein the first gate electrode is formed by a first conducting layer, and the second gate electrode is formed by stacking the first conducting layer and a second conducting layer on the substrate;
a gate insulating layer disposed on the substrate, the first gate electrode and the second gate electrode;
a first active layer disposed on the gate insulating layer and corresponding to the first gate electrode, wherein the first active layer comprises a polysilicon layer;
a first insulating layer disposed on the first active layer and the gate insulating layer, and the first insulating layer comprising a first bottom insulating layer and a first top insulating layer;
a second active layer disposed on the first insulating layer and corresponding to the second gate electrode, wherein the second active layer comprises a metal oxide layer;
a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, wherein the first source electrode and the first drain electrode are disposed on the first insulating layer and electrically connect to the first active layer, and the second source electrode and the second drain electrode are disposed on the second active layer and electrically connect to the second active layer; and
a fourth conducting layer, wherein the fourth conducting layer partially covers at least one of the second source electrode and the second drain electrode,
wherein, the first gate electrode, the gate insulating layer, the first active layer, the first insulating layer, the first source electrode, and the first drain electrode form a first transistor, the second gate electrode, the gate insulating layer, the first insulating layer, the second active layer, the second source electrode, and the second drain electrode form a second transistor; and
a display medium layer disposed on the substrate.

US Pat. No. 10,192,897

ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

HON HAI PRECISION INDUSTR...

1. An array substrate comprising:a substrate;
a first TFT formed on the substrate, the first TFT comprising a first channel layer formed on the substrate, a first gate insulator layer formed on the substrate and covering the first channel layer, a first gate electrode formed on the first gate insulator layer, a first dielectric layer formed on the first gate insulator layer and covering the first gate electrode, a second dielectric layer formed on the first dielectric layer, and a first source electrode and a first drain electrode formed on the second dielectric layer; the first source electrode and the first drain electrode electrically coupled to the first channel layer;
a second TFT formed on the substrate, the second TFT comprising a second gate insulator layer formed on the substrate, a second gate electrode formed on the second gate insulator layer, a third dielectric layer formed on the second gate insulator layer and covering the second gate electrode, a second channel layer formed on the third dielectric layer, and a second source electrode and a second drain electrode formed on the third dielectric layer; the second source electrode and the second drain electrode electrically coupled to the second channel layer; and
a third TFT formed on the substrate, the third TFT comprising a third gate insulator layer formed on the substrate, a third gate electrode formed on the third gate insulator layer, a fourth dielectric layer formed on the second gate insulator layer and covering the third gate electrode, a third channel layer formed on the fourth dielectric layer, and a third source electrode and a third drain electrode formed on the fourth dielectric layer; the third source electrode and the third drain electrode electrically coupled to the third channel layer;
wherein the first channel layer is made of a semiconducting material containing polycrystalline silicon; the second channel layer and the third channel layer are made of a semiconducting material containing metal oxide; the third dielectric layer is positioned between the second gate electrode and the second channel layer, and is in direct contact with the second gate electrode and the second channel layer; the fourth dielectric layer is positioned between the third gate electrode and the third channel layer, and is in direct contact with the third gate electrode and the third channel layer; the first dielectric layer is made of silicon nitride; the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are made of silicon oxide.

US Pat. No. 10,192,896

DISPLAY DEVICE WITH OVERLAPPING PADS SPACED APART FROM AN INSULATING LAYER

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a display area to display an image and a non-display area provided on at least one side of the display area;
a plurality of pixels disposed on the substrate and provided in an area corresponding to the display area;
a first insulating layer having an opening in a first area of the non-display area;
a second insulating layer filling the opening of the first insulating layer, wherein the second insulating layer contacts the substrate in the opening of the first insulating layer;
first lines provided on the substrate and connected to the plurality of pixels; and
second tines provided on the first and second insulating layers, and connected to the first lines,
wherein an area in which the first lines overlap with the second lines is spaced apart from an edge of the second insulating layer when viewed in a plan view.

US Pat. No. 10,192,895

DISPLAY DEVICE

JAPAN DISPLAY INC., Mina...

1. A display device comprising:a transparent substrate;
a plurality of thin film transistors provided in the transparent substrate;
a source electrode and a drain electrode formed above or below a semiconductor layer via an insulating film;
a first contact hole for connecting the semiconductor layer and the source electrode, a second contact hole for connecting the semiconductor layer and the drain electrode; and
a first light shielding film and a second light shielding film provided between the plurality of thin film transistors and the transparent substrate,
wherein each thin film transistor includes:
a semiconductor layer; and
a first gate electrode and a second gate electrode formed above or below the semiconductor layer via an insulating film,
the first light shielding film overlaps with the semiconductor layer in a plan view from a part of the first gate electrode to the first contact hole, and the second light shielding film overlaps with the semiconductor layer in a plan view from a part of the second gate electrode to the second contact hole,
wherein the semiconductor layer includes, in a plan view:
a source region formed in a first portion of the semiconductor layer which is positioned on an opposite side to the second gate electrode across the first gate electrode when seen in a plan view,
a drain region formed in a second portion of the semiconductor layer which is positioned on an opposite side to the first gate electrode across the second gate electrode when seen in a plan view,
a first semiconductor region formed in a third portion which is positioned between the first gate electrode and the source region, and
a second semiconductor region formed in a fourth portion which is positioned between the second gate electrode and the drain region,
the first light shielding film includes a first end portion on the source electrode side and a second end portion on the drain electrode side, and the second light shielding film includes a third end portion on the source electrode side and a fourth end portion on the drain electrode side,
a distance from the first end portion of the first light shielding film to an overlapping region with the first semiconductor region is L1 in the plan view, and an interlayer distance from the first light shielding film to the semiconductor layer is H1, the distance L1 is formed to be equal to or greater than the interlayer distance H1,
a distance from the fourth end portion of the second light shielding film to an overlapping region with the second semiconductor region is L2 in the plan view, and an interlayer distance from the second light shielding film to the semiconductor layer is H1, the distance L2 is formed to be equal to or greater than the interlayer distance H1.

US Pat. No. 10,192,894

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor comprising, successively from the bottom up, a gate, a first common electrode located in a same layer as the gate, a gate insulating layer, an active layer, a pixel electrode, a source-drain electrode layer and a passivation layer located above the layer where the gate is located, and a second common electrode located on the passivation layer, wherein,the thin film transistor further comprises at least one connection electrode located in a same layer as the pixel electrode, wherein at least two via holes are provided between the first common electrode and the second common electrode so as to connect the first common electrode and the second common electrode through the connection electrode.

US Pat. No. 10,192,893

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, in a peripheral region outside a display region, comprising a plurality of signal lines, a plurality of connecting lines above the signal lines, and a driving module, the connecting lines being configured for connecting the signal lines and the driving module, to transmit signals from the signal lines to the driving module, wherein, each of the signal lines comprises a first electrode line layer and a second electrode line layer above the first electrode line layer,wherein, a first insulating layer is arranged between the first electrode line layer and the second electrode line layer, a second insulating layer is arranged above the second electrode line layer,
wherein, at least one of the signal lines is insulated from and intersected with the at least one of the connecting lines in a plan view of the array substrate; the second electrode line layer of the at least one of the signal lines is discontinuous at an intersection of the at least one of the signal lines and the at least one of the connecting lines in the plan view of the array substrate; and the second electrode line layer of at least one of the signal lines is not overlapped with the at least one of the connecting lines in the plan view of the array substrate.

US Pat. No. 10,192,892

ACTIVE MATRIX BACKPLANE FORMED USING THIN FILM OPTOCOUPLERS

Palo Alto Research Center...

1. A device comprising:a backplane, comprising:
multiple output terminals arranged on an output surface of the backplane;
an optocoupler active matrix array, comprising:
thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals, the optical switches and the output terminals arranged in an array; and
storage capacitors coupled respectively to the output terminals; and
a pixelated light source configured to provide pixelated light that controls the optical switches.

US Pat. No. 10,192,891

THIN FILM TRANSISTOR AND DISPLAY DEVICE COMPRISING THE SAME

JOLED INC., Tokyo (JP)

1. A thin film transistor comprising:an oxide semiconductor layer provided above an insulating substrate and including a source region, a drain region and a channel region between the source region and the drain region;
a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region;
a gate electrode provided on the first insulating film;
a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal;
a second protective film provided on the first protective film; and
a third protective film provided on the second protective film, as an insulating film containing a metal, wherein the first protective film directly contacts sidewalls and a top surface of the gate electrode, wherein the third protective film is thicker than the first protective film.

US Pat. No. 10,192,890

TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THEREOF

Samsung Display Co., Ltd,...

1. A transistor display panel comprising:a substrate; and
a transistor disposed on the substrate,
wherein the transistor comprises:
a gate electrode disposed on the substrate;
a semiconductor that overlaps the gate electrode;
an upper electrode disposed on the semiconductor and overlapping the gate electrode;
a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor;
a source electrode connected with the source connection member and the upper electrode; and
a drain electrode connected with the drain connection member.

US Pat. No. 10,192,889

DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first substrate including a display area and a non-display area;
a gate line and a gate electrode in the display area;
a data line connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a drain electrode and a source electrode on the semiconductor layer;
a first passivation layer on the drain electrode and the source electrode;
a color filter on the first passivation layer;
a common electrode on the first passivation layer;
a second passivation layer on the common electrode; and
a pixel electrode on the second passivation layer,
wherein the gate insulating layer has substantially a same shape as a shape of the gate electrode,
wherein the gate insulating layer has a width wider than a width of the gate electrode,
wherein the gate insulating layer is spaced apart from the first substrate, and
wherein a side surface of the gate electrode is exposed below a bottom surface of the gate insulating layer.

US Pat. No. 10,192,888

METALLIZED JUNCTION FINFET STRUCTURES

International Business Ma...

1. A FinFET structure comprising:a substrate;
a plurality of vertically extending, parallel semiconductor fins mounted to the substrate;
a plurality of parallel gate structures on and extending perpendicularly with respect to the semiconductor fins;
a plurality of first sidewall spacers on the gate structures;
a plurality of pairs of unmerged epitaxial source/drain structures, each pair of unmerged epitaxial source/drain structures including a first portion extending laterally from first and second sidewall surfaces of one of the semiconductor fins and operatively associated with the one of the semiconductor fins and a second portion integral with the first portion;
a plurality of parallel, vertically oriented, fin-shaped cavities between each pair of source/drain structures in each second portion thereof, each of the fin-shaped cavities being in linear alignment, respectively with each of the semiconductor fins and extending perpendicularly with respect to the plurality of gate structures, and
a metal silicide layer adjoining the source/drain structures and filling the plurality of fin-shaped cavities, the second portion of each pair of unmerged epitaxial source/drain structures extending laterally from one of the fin-shaped cavities and adjoining the metal silicide layer filling the one of the fin-shaped cavities.

US Pat. No. 10,192,885

SEMICONDUCTOR ON INSULATOR (SOI) BLOCK WITH A GUARD RING

NXP USA, Inc., Austin, T...

1. A method for forming a semiconductor device, comprising:delineating a portion of a bulk substrate having a first conductivity type as a first semiconductor on insulator (SOI) block;
forming a first doped well of the first conductivity type in the first SOI block;
forming a second doped well of a second conductivity type in the first SOI block;
forming a first guard ring of the first conductivity type around at least a portion of a periphery of and laterally spaced apart from the first SOI block such that the first guard ring and the first SOI block do not touch;
forming a first electronic device directly over the first doped well;
forming a first electrically conductive trace between the first guard ring and a first current electrode of the first electronic device to electrically connect the first guard ring and the first current electrode of the first electronic device.

US Pat. No. 10,192,884

BUTTED BODY CONTACT FOR SOI TRANSISTOR

pSemi Corporation, San D...

1. A semiconductor structure comprising:a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;
a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;
a first drain region adjacent to the first body region having a second conductivity type;
a first source region adjacent to the first body region having the second conductivity type;
a second source region adjacent to the second body region having the second conductivity type;
a second drain region adjacent to the second body region having the second conductivity type,
the first source region and the second drain region defining a first common source/drain region having the second conductivity type;
a first non-conductive isolation region configured to form an interruption in the second body region to divide the second body region in two separate second body regions;
at least one first body contact region of the first conductivity type formed within the first common source/drain region separate from the first and the second body regions and abutting the first non-conductive isolation region; and
at least one first body tab of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,
wherein the first non-conductive isolation region, the at least one first body contact region and the at least one first body tab define a first butted body tie structure.

US Pat. No. 10,192,883

VERTICAL MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A memory device, comprising:a first region including a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a protective layer disposed in the first insulating layer; and
a second region including a second substrate disposed on the first insulating layer, wherein the second substrate includes a first impurity region, a channel region extending in a first direction substantially perpendicular to an upper surface of the second substrate, and a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, wherein the protective layer is disposed below the first impurity regions, and includes a plurality of regions separated from each other.

US Pat. No. 10,192,882

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of conductive layers stacked with an insulator interposed;
a columnar portion extending through the stacked body in a stacking direction of the stacked body; and
a first air gap extending through the stacked body in the stacking direction,
the insulator including
an insulating layer provided at a periphery of a side surface of the columnar portion, and
a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap,
the insulating layer having a protrusion at an end adjacent to the second air gap.

US Pat. No. 10,192,881

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate comprising a source region portion;
gate stacks disposed on the substrate and spaced apart from each other in a first direction, with a separation region directly contacting the source region portion of the substrate and interposed between the gate stacks, the source region portion of the substrate being disposed between the separation region and regions of the substrate not within the source region portion;
channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and
a guide region adjacent to the separation region, penetrating through at least a portion of one of the gate stacks, and having a bent portion that is bent toward the separation region;
wherein the channel regions are disposed in channel openings that penetrate through the gate stacks,
the guide region is disposed in a guide opening that penetrates through at least the portion of the one of the gate stacks,
the separation region is disposed in a separation opening that penetrates through the gate stacks, and
a width of the separation opening is greater than a width of each of the guide opening and the channel openings,
wherein the guide opening is closer to the separation region than the channel openings, and an upper portion of the guide opening is spaced apart from an upper portion of the separation region.

US Pat. No. 10,192,880

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:gate stacked structures surrounding channel layers;
a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, wherein the first concave portions are arranged in a first direction crossing a lengthwise direction of the channel layer; and
a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

US Pat. No. 10,192,879

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device having a memory cell of a nonvolatile memory, comprising:a semiconductor substrate;
a first gate electrode formed over the semiconductor substrate via a first gate insulating film; and
a second gate electrode formed over the semiconductor substrate via a multi-layer insulating film, and adjacent to the first gate electrode via the multi-layer insulating film,
wherein the multi-layer insulating film includes a first insulating film, a second insulating film over the first insulating film, and a third insulating film over the second insulating film,
wherein the second insulating film has a charge storing function,
wherein the second gate electrode has a lower surface facing the semiconductor substrate, a first side surface adjacent to the first gate electrode via the multi-layer insulating film, and a second side surface opposite to the first side surface, and
wherein a fourth insulating film is formed between the lower surface of the second gate electrode and the semiconductor substrate and is in contact with the first, second and third insulating films such that the fourth insulating film is located closer to a first end portion of the second side surface of the second gate electrode than to a second end portion of the first side surface of the second gate electrode.

US Pat. No. 10,192,878

THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED MULTI-LEVEL DRAIN SELECT GATE ELECTRODES

SANDISK TECHNOLOGIES LLC,...

12. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
a first conductive connector spacer connected to each of first strip portions of two or more uppermost layers among the electrically conductive layers; and
a second conductive connector spacer connected to each of second strip portions of the two or more uppermost layers among the electrically conductive layers,
wherein each of the first and second conductive connector spacers includes an alternating sequence of conductive non-concave sidewall portions and conductive concave sidewall portions.

US Pat. No. 10,192,877

THREE-DIMENSIONAL MEMORY DEVICE WITH LEVEL-SHIFTED STAIRCASE STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack is composed of, from bottom to top, a first contiguous subset of layers within the alternating stack and a second contiguous subset of layers;
a mesa structure located over the substrate;
memory stack structures extending through the alternating stack in a memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
a first terrace region located above the mesa structure at a first side of the memory array region, and including first stepped surfaces of the first contiguous subset;
a second terrace region located at a second side of the memory array region, and including second stepped surfaces of the second contiguous subset;
first contact via structures contacting respective electrically conductive layers within the first contiguous subset in the first terrace region;
second contact via structures contacting respective electrically conductive layers within the second contiguous subset in the second terrace region;
a first retro-stepped dielectric material portion contacting the first stepped surfaces;
a second retro-stepped dielectric material portion contacting the second stepped surfaces, wherein the second retro-stepped dielectric material portion has a greater maximum height than the first retro-stepped dielectric material portion;
a contact level dielectric material layer overlying the alternating stack;
a first support pillar structure located in the first terrace region and extending through the contact level dielectric material layer and the first retro-stepped dielectric material portion, not extending through any layer within the second contiguous subset, and directly contacting a horizontal portion of an electrically conductive layer within the first contiguous subset, a horizontal portion of an insulating layer within the first contiguous subset, and a vertically extending portion of another electrically conductive layer within the first contiguous subset, wherein the vertically extending portion extends vertically over a vertical extent of multiple electrically conductive layers within the memory array region; and
a second support pillar structure located in the second terrace region and extending through the contact level dielectric material layer and the second retro-stepped dielectric material portion, and directly contacting a respective horizontal portion of each electrically conductive layer within the first contiguous subset and a horizontal portion of at least one electrically conductive layer within the second contiguous subset and does not directly contact any vertically extending portion of the electrically conductive layers within an entirety of the alternating stack.

US Pat. No. 10,192,876

TRANSISTOR, MEMORY, AND MANUFACTURING METHOD OF TRANSISTOR

Toshiba Memory Corporatio...

1. A transistor comprising:a gate electrode;
a gate insulating layer provided on the gate electrode;
an oxide semiconductor layer provided on the gate insulating layer;
an oxygen supply layer provided on the oxide semiconductor layer;
a first oxygen barrier layer including a first portion, the first portion provided on the oxygen supply layer;
a source electrode provided to include a source extending portion that extends through the oxygen supply layer and the first portion in a stacking direction of the layers, and connected to the oxide semiconductor layer; and
a drain electrode spaced apart from the source electrode, provided to include a drain extending portion that extends through the oxygen supply layer and the first portion in the stacking direction, and connected to the oxide semiconductor layer,
wherein the first oxygen barrier layer further includes a second portion between the oxygen supply layer and a side of the source extending portion, and a third portion between the oxygen supply layer and a side of the drain extending portion.

US Pat. No. 10,192,875

NON-VOLATILE MEMORY WITH PROTECTIVE STRESS GATE

eMemory Technology Inc., ...

1. A non-volatile memory, comprising:a substrate;
a floating gate transistor, a select transistor and a stress-releasing transistor, disposed on the substrate and coupled in series with each other, wherein the stress-releasing transistor is located between the floating gate transistor and the select transistor, and
the stress-releasing transistor has a stress release ratio represented by formula (1):
the stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor  (1)
wherein a lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed,
an upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed, and
the channel length under a stress-releasing gate of the stress-releasing transistor is smaller than a minimum channel length of a design rule of an input/output device; and
a first capacitor and a second capacitor, wherein the first capacitor, the second capacitor and the floating gate transistor are disposed in separation and are coupled to each other.

US Pat. No. 10,192,873

MEMORY CELL, AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR WITH THE ARRAY COMPRISING ROWS OF ACCESS LINES AND COLUMNS OF DIGIT LINES, A 2T-1C MEMORY CELL, AND METHODS OF FORMING AN ARRAY OF CAPACITORS AND ACCESS TRANSISTORS

Micron Technology, Inc., ...

1. A memory cell having a total of only two transistors and a total of only one capacitor, comprising:a capacitor comprising a laterally-outer electrode having an upwardly-open container shape;
a laterally-inner electrode;
a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode;
a lower vertical transistor having an upper source/drain region thereof electrically coupled to the laterally-outer electrode having the upwardly-open container shape; and
an upper vertical transistor having a lower source/drain region thereof electrically coupled to the laterally-inner electrode.

US Pat. No. 10,192,872

MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region; and
a back-bias region configured to maintain a charge in said floating body region;
wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;
wherein said back bias region is commonly connected to at least two of said memory cells,
wherein said back bias region has a lower band gap than a band gap of said floating body region; and
a control circuit configured to provide electrical signals to said back bias region.

US Pat. No. 10,192,871

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a first circuit,
wherein the transistor includes a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a semiconductor layer positioned therebetween,
wherein the first circuit includes a temperature sensor and a comparator,
wherein the temperature sensor is configured to obtain temperature information, and
wherein the first circuit is configured to apply, to the second gate, a voltage depending on the temperature information.

US Pat. No. 10,192,870

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor substrate of a first conductivity type;
a first semiconductor region of a second conductivity type, selectively provided in one main surface of the semiconductor substrate;
an isolating structure formed by a pn junction of the semiconductor substrate and the first semiconductor region, the isolating structure isolating regions of differing potentials;
a semiconductor element having: a second semiconductor region of the second conductivity type, selectively provided in the one main surface of the semiconductor substrate so as to be separated from the first semiconductor region and electrically connected to an electrode of a minimum potential through a first resistor; a third semiconductor region of the second conductivity type selectively provided inside the first semiconductor region and having a higher impurity concentration than the first semiconductor region; a gate insulating film provided along the semiconductor substrate between the first semiconductor region and the second semiconductor region; and a gate electrode provided along the gate insulating film, the semiconductor element converting a signal referenced to the minimum potential into a signal referenced to a potential differing from the minimum potential; and
a fourth semiconductor region of the first conductivity type selectively provided in the one main surface of the semiconductor substrate so as to be separated from the second semiconductor region at a prescribed distance and electrically connected to the electrode of the minimum potential, the fourth semiconductor region having a higher impurity concentration than the semiconductor substrate,
wherein the second semiconductor region is electrically connected to the fourth semiconductor region through a second resistor, and
wherein the second resistor comprises a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region.

US Pat. No. 10,192,868

SEMICONDUCTOR DEVICE AND OPERATION THEREOF

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate;
an active area on the substrate, wherein the active area comprises:
a first active area; and
a second active area positioned along an extension direction of the first active area, wherein the first active area comprises a first component, a second component, and a connection component, and the first component and the second component each directly contact a side of the connection component, wherein the second active area comprises a third component and a fourth component being separated by a groove isolation, and wherein the groove isolation in the second active area corresponds to the connection component in the first active area; and
a first pseudo gate covering the connection component and the groove isolation.

US Pat. No. 10,192,865

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, comprising:a second conductive-type SiC base layer having a first surface and a second surface, the second surface of the second conductive-type SiC base layer being on a second conductive-type SiC substrate, the second conductive-type SiC substrate having a first surface facing the second surface of the SiC base layer and a second surface opposite the first surface of the SiC substrate and defining a drain region of the SiC-MOSFET;
a trench etched in the second surface of the SiC substrate;
first conductive-type impurities implanted in a bottom surface of the trench so as to form a collector region in the bottom surface, the collector region having a first surface extending along the second surface of the SiC base layer and a second surface extending along a thickness direction of the SiC base layer;
first conductive-type impurities implanted in the first surface of the SiC base layer so as to form a channel region in a surficial portion of the SiC base layer; and
second conductive-type impurities implant into the first surface of the SiC base layer so as to form an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET, wherein
the SiC base layer includes a first region having a first impurity concentration in contact with the channel region and a second region having a second impurity concentration higher than the first impurity concentration and surrounding the collector region such that the second region is in contact with both the first surface and the second surface of the collector region, and
the second region of the SiC base layer is independent from the drain region.

US Pat. No. 10,192,863

SERIES CONNECTED ESD PROTECTION CIRCUIT

Texas Instruments Incorpo...

1. An electrostatic discharge (ESD) protection circuit, comprising:a substrate;
an n-type buried layer formed below a surface of the substrate;
a first terminal formed on the surface of the substrate;
a second terminal formed on the surface of the substrate;
a first ESD protection device having a first current path connecting between the first terminal and the n-type buried layer, the first ESD protection device including a first NPN bipolar transistor having a collector positioned in the n-type buried layer; and
a second ESD protection device having a second current path connecting between the second terminal and the n-type buried layer, the second current path arranged in series with the first current path, the second ESD protection device including a second NPN bipolar transistor having an emitter positioned in the n-type buried layer,
wherein the first NPN bipolar transistor has a first base that is electrically isolated from a second base of the second NPN transistor.

US Pat. No. 10,192,862

SEMICONDUCTOR DEVICE

Murata Manufacturing Co.,...

1. A semiconductor device comprising:an amplifier circuit including a semiconductor element formed on a substrate;
a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and
a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein
the pad conductive layer and the protection circuit at least partially overlap each other in plan view, and
at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

US Pat. No. 10,192,861

OPC METHOD FOR A SHALLOW ION IMPLANTING LAYER

SHANGHAI HUALI MICROELECT...

1. An OPC method for a shallow ion implanting layer, providing a shallow ion implanting original layout and other layers corresponding to the shallow ion implanting original layout include an active area layer, a contact hole layer and a poly-silicon layer, wherein the active area layer includes an active region pattern, the contact hole layer includes a contact hole pattern and the poly-silicon layer includes a ploy-silicon pattern; wherein the method comprising the following steps of:S01: selecting a valid device region in an implanting active region of the shallow ion implanting original layout; wherein a portion other than an active region pattern in an active area layer is a STI region, the shallow ion implanting original layout includes a shallow ion implanting region and a non-shallow ion implanting region, and a portion overlapped between the shallow ion implanting region and the active region pattern in the active area layer is the implanting active region; a portion to remain the implanting active region which touches to the contact hole pattern in the contact hole layer is a valid device region, and anther portion to remain the implanting active region which does not touch to the contact hole pattern in the contact hole layer is a non-device invalid region;
S02: selecting a region in the valid device region which is contacted with a poly-silicon pattern in a poly-silicon layer, as a poly-silicon contacting region, and selecting a region in the valid device region which is not contacted with the poly-silicon pattern in the poly-silicon layer, as a non poly-silicon contacting region;
S03: extending the length and width of the poly-silicon contacting region and the non poly-silicon contacting region, to form a new poly-silicon contacting region and a new non poly-silicon contacting region; wherein the new poly-silicon contacting region and the new non poly-silicon contacting region are located in any region except the active region pattern touching with the contact hole pattern in the non-shallow ion implanting region;
S04: combining one gap portion or more gap portions which an interval between any two new poly-silicon contacting regions and/or new non poly-silicon contacting regions after extending is smaller than or equal to G, with the poly-silicon contacting regions and the non poly-silicon contacting regions after extending, to form a correction target layer, wherein G is an interval safe value determined according to the actual process capability;
S05: performing a model-based OPC correction on the correction target layer, and to obtain a mask layer.