US Pat. No. 10,658,229

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A method of manufacturing a semiconductor device comprising:laminating a first semiconductor wafer including a first substrate and a first insulating layer which is formed so as to come into contact with one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer which is formed so as to come into contact with one surface of the second substrate and bonding the first semiconductor wafer and the second semiconductor wafer to each other;
forming a third insulating layer on the other surface of a side opposite to the one surface of the first substrate; penetrating the third insulating layer, the first substrate, and the first insulating layer, performing etching so as that the second insulating layer remains on a second wiring layer which is formed in the second insulating layer, and forming a first connection hole;
forming an insulating film on the first connection hole;
performing etching of the second insulating layer on the second wiring layer and the insulating film, forming a second connection hole, and exposing the second wiring layer; and
forming a first via which is formed in inner portions of the first and the second connection holes and is connected to the second wiring layer,
wherein a diameter of the first connection hole which is formed on the other surface of the first substrate is greater than a diameter of the first connection hole which is formed on the third insulating layer.

US Pat. No. 10,658,228

SEMICONDUCTOR SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:a substrate;
an oxide layer disposed over the substrate;
a first epitaxial layer disposed over the oxide layer and having a first conductivity type;
a second epitaxial layer disposed over the first epitaxial layer and having a second conductivity type that is opposite to the first conductivity type;
a third epitaxial layer disposed over the second epitaxial layer and having the first conductivity type;
a fourth epitaxial layer disposed between the second epitaxial layer and the third epitaxial layer, and having the first conductivity type; and
a fifth epitaxial layer disposed between the fourth epitaxial layer and the third epitaxial layer, and having the second conductivity type.

US Pat. No. 10,658,227

METHOD OF DEPOSITING CHARGE TRAPPING POLYCRYSTALLINE SILICON FILMS ON SILICON SUBSTRATES WITH CONTROLLABLE FILM STRESS

GlobalWafers Co., Ltd., ...

1. A method of preparing a multilayer structure, the method comprising:forming a semiconductor oxide layer, a semiconductor nitride layer, or a semiconductor oxynitride layer in interfacial contact with a front surface of a single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
annealing the single crystal semiconductor handle substrate comprising the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer in interfacial contact with the front surface thereof in an ambient atmosphere comprising a gas selected from the group consisting of hydrogen, hydrogen chloride, chlorine, and any combination thereof, wherein the anneal of the single crystal semiconductor handle substrate comprising the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer forms a textured semiconductor oxide layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers, a textured semiconductor nitride layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers, or a textured semiconductor oxynitride layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers;
depositing a polycrystalline silicon layer on the textured semiconductor oxide layer, the textured semiconductor nitride layer, or the textured semiconductor oxynitride layer in interfacial contact with the front surface the single crystal semiconductor handle substrate, wherein the polycrystalline silicon layer is deposited by chemical vapor deposition; and
bonding a dielectric layer on a front surface of a single crystal semiconductor donor substrate to the polycrystalline silicon layer of the single crystal semiconductor handle substrate to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

US Pat. No. 10,658,226

METHOD FOR PREPARING SOI WAFER BY USING RAPID THERMAL PROCESSING

Shenyang Silicon Technolo...

1. A method for preparing an SOI wafer by using rapid thermal processing, comprising:taking a silicon wafer as a raw material, sequentially performing process steps of oxidation, H+ implantation and bonding to obtain a bonded wafer with an H+ implantation layer; and splitting the bonded wafer by using the rapid thermal processing and microwaves to obtain a required SOI wafer, wherein the wafer splitting process further comprises, by using a rapid thermal processing single-wafer process, heating the wafer to a required temperature not greater than 480° C., and maintaining the temperature for 30 seconds to 10 minutes, wherein a temperature increase and decrease rate is 10-200° C./second; and
after or during the rapid thermal processing, applying a microwave process to the bonded wafer for 10 seconds to 20 minutes, wherein a microwave power of the microwave process is required to be adjusted within a range of greater than 0 W and less than or equal to 5000 W.

US Pat. No. 10,658,225

FINFET DEVICES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A FinFET device, comprising:a plurality of first fins and a plurality of second fins disposed on a substrate;
a first gate strip disposed across the first fins;
a second gate strip disposed across the second fins; and
a comb-like insulating structure disposed between the first gate strip and the second gate strip and having a plurality of comb tooth parts, wherein each of the plurality of comb tooth parts has a middle-wide profile.

US Pat. No. 10,658,224

METHOD OF FIN OXIDATION BY FLOWABLE OXIDE FILL AND STEAM ANNEAL TO MITIGATE LOCAL LAYOUT EFFECTS

INTERNATIONAL BUSINESS MA...

1. A method of forming an integrated chip, comprising:oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer; and
forming a semiconductor device on each of the active regions.

US Pat. No. 10,658,223

APPARATUS FOR PREVENTION OF BACKSIDE DEPOSITION IN A SPATIAL ALD PROCESS CHAMBER

Applied Materials, Inc., ...

1. A susceptor assembly comprising:a susceptor having a body with a top surface and bottom surface, the top surface having a plurality of recesses therein; and
a support post connected to the bottom surface of the susceptor to rotate the susceptor assembly, the support post including
a support post vacuum plenum in fluid communication with a susceptor vacuum plenum in the body of the susceptor, and
a purge gas line extending through the support post to a purge gas plenum in the body of the susceptor.

US Pat. No. 10,658,222

MOVEABLE EDGE COUPLING RING FOR EDGE PROCESS CONTROL DURING SEMICONDUCTOR WAFER PROCESSING

LAM RESEARCH CORPORATION,...

1. A substrate processing system, comprising:a processing chamber;
a pedestal arranged in the processing chamber, the pedestal including a baseplate and at least one plate arranged on the baseplate;
an edge coupling ring arranged adjacent to a radially outer edge of the pedestal, wherein an inner portion of the edge coupling ring overlaps the at least one plate;
a lifting ring, wherein an outer portion of the edge coupling ring overlaps the lifting ring; and
a first actuator configured to selectively move the edge coupling ring to a raised position and a lowered position relative to the pedestal, wherein, when the edge coupling ring is in the raised position, a bottom surface of the edge coupling ring is above an uppermost surface of the pedestal to define a clearance gap between the bottom surface of the edge coupling ring and the uppermost surface of the pedestal, wherein the gap is directly below the bottom surface of the edge coupling ring and above an upper surface of the at least one plate, and wherein, when the edge coupling ring is in the lowered position, the bottom surface of the edge coupling ring is supported by the upper surface of the at least one plate.

US Pat. No. 10,658,221

SEMICONDUCTOR WAFER CLEANING APPARATUS AND METHOD FOR CLEANING SEMICONDUCTOR WAFER

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor wafer cleaning apparatus, comprising:a spin base rotatable about a central axis; and
a plurality of chuck pins positioned on the spin base and arranged around the center axis, wherein each of the chuck pins comprises:
a supporter configured to support a semiconductor wafer over the spin base;
a clamping member positioned over the supporter and configured to secure the semiconductor wafer, wherein the clamping member has a lateral surface, and a groove is formed on the lateral surface for receiving an outer edge of the semiconductor wafer; and
a guiding member positioned over a top of the groove of the clamping member and configured to guide the semiconductor wafer while the semiconductor wafer is moved relative to the supporter,
wherein the supporter has an inner edge, and a recessed segment of the inner edge is separated from an outer edge of the semiconductor wafer when the semiconductor wafer is secured by the clamping member,
wherein the supporter has a first supporting region and a second supporting region arranged at two sides of the recessed segment, and the first supporting region and the second supporting region are located below the semiconductor wafer when the semiconductor wafer is secured by the clamping member.

US Pat. No. 10,658,220

DEVICE TRANSFERRING METHOD

DISCO CORPORATION, Tokyo...

1. A device transferring method for transferring a plurality of devices to a mounting substrate provided with a plurality of electrodes, the device transferring method comprising:a tape adhering step of adhering an expandable tape to the plurality of devices formed on a front surface side of a substrate through a buffer layer;
a buffer layer breaking step of applying a laser beam of such a wavelength as to be transmitted through the substrate and to be absorbed in the buffer layer to the buffer layer from a back surface side of the substrate, to break the buffer layer, after the tape adhering step is performed;
a transfer step of moving the tape in a direction for spacing away from the substrate to separate the substrate and the plurality of devices from each other, thereby transferring the plurality of devices having been formed on the substrate to the tape, after the buffer layer breaking step is performed;
a tape expanding step of expanding the tape in such a manner that a layout of the plurality of devices adhered to the tape corresponds to a layout of the plurality of electrodes, after the transfer step is performed; and
a die bonding step of bonding the plurality of devices adhered to the expanded tape to the plurality of electrodes at once, after the tape expanding step is performed.

US Pat. No. 10,658,219

WORKPIECE HOLDER, INSPECTION APPARATUS, AND WORKPIECE POSITION CORRECTION METHOD

SCREEN HOLDINGS CO., LTD....

1. A workpiece holder that rotates a workpiece about a rotary axis while holding the workpiece having an outer peripheral portion rotationally symmetric about a symmetry axis, the holder comprising:a holding table including: a chuck configured to hold the workpiece; a positioning mechanism, comprising an X-Y table, configured to move the chuck in a direction orthogonal to the rotary axis while supporting the chuck to locate the workpiece; and a rotary mechanism, comprising a motor, configured to rotate the positioning mechanism about the rotary axis to rotate the workpiece held by the chuck about the rotary axis;
a first camera configured to capture an image of the outer peripheral portion of the workpiece held by the chuck; and
a processor configured to:
detect misalignment of the symmetry axis with respect to the rotary axis on the basis of the image captured by the first camera while the workpiece is rotated by the rotary mechanism; and
correct the position of the workpiece in such a manner as to match the symmetry axis with the rotary axis by moving the chuck using the positioning mechanism so as to eliminate the misalignment.

US Pat. No. 10,658,218

CUTTING METHOD OF WORKPIECE

DISCO CORPORATION, Tokyo...

1. A cutting method of a workpiece that has, in a surface, a device region in which a device is formed in each of regions marked out by a plurality of planned dividing lines formed in a lattice manner and a peripheral surplus region that surrounds the device region, and in which laser-processed grooves are formed in the planned dividing lines by irradiation with a laser beam,by use of a cutting apparatus including a chuck table holding the workpiece by a holding surface, a cutting unit cutting the workpiece held by the chuck table by a cutting blade, a processing feed unit carrying out processing feed in an X-axis direction parallel to the holding surface of the chuck table, an indexing feed unit carrying out indexing feed of the cutting unit in a Y-axis direction that is parallel to the holding surface and is orthogonal to the X-axis direction, and a photographic unit including a camera that photographs the workpiece held by the chuck table and an epi-illumination part that emits light along an optical axis of the camera,
the cutting method comprising:
a half-cut groove forming step of forming a half-cut groove having a bottom that reflects the light of the epi-illumination part in a range of the peripheral surplus region of the planned dividing line;
a detection step of photographing the half-cut groove by the photographic unit and detecting the half-cut groove with discrimination from the laser-processed groove that diffusely reflects the light of the epi-illumination part and is darkly displayed;
a correction step of correcting deviation between the laser-processed groove and the half-cut groove; and
a cutting step of positioning the cutting blade at a center of the laser-processed groove and carrying out cutting.

US Pat. No. 10,658,217

TRANSFER CHAMBER

SINFONIA TECHNOLOGY CO., ...

1. A transfer chamber for transferring a transferred object to or from a processing device by using a transfer robot disposed thereinside, comprising:a circulation path formed in an inside of the transfer chamber by dividing an inner space of the transfer chamber with an inner wall, and circulating gas;
a chemical filter provided in a midstream of the circulation path, and comprising an acid removal filter removing acid components by a hydrolysis reaction and an alkali removal filter removing alkali components by a hydrolysis reaction;
a humidity detector configured to detect internal humidity;
a gas supply line supplying the gas from a gas supply source to the inside of the transfer chamber;
a moisture supply line supplying moisture content from a water supply source to the inside of the transfer chamber; and
a pressure sensor configured to detect pressure to the inside of the transfer chamber.

US Pat. No. 10,658,216

TRANSFER SYSTEM AND TRANSFER METHOD

KABUSHIKI KAISHA YASKAWA ...

1. A transfer system comprising:a transfer chamber having transfer positions;
a first robot provided in the transfer chamber to transfer articles between the transfer positions;
a second robot provided in the transfer chamber to transfer articles between the transfer positions;
a controller configured to execute operation control of one robot among the first robot and the second robot;
a determining unit configured to determine that the one robot has error information indicating that the one robot is broken down; and
a lift configured to move the one robot to a retreat position by changing a height of the one robot such that the one robot does not interfere with an operating range of another robot among the first robot and the second robot, the lift being configured to move the one robot to the retreat position when the determining unit determines that the one robot is broken down.

US Pat. No. 10,658,215

RETICLE TRANSPORTATION CONTAINER

TAIWAN SEMICONDUCTOR MANU...

1. A transportation container, comprising:a container body constructed of a top wall, a bottom wall, a rear wall, and two sidewalls forming a front opening for loading or unloading a reticle pod into or out of the container body;
a lid for opening and closing the front opening;
a lift plate above the container body configured to connect to a carrier of an overhead hoist transfer (OHT) system; and
a latch mechanism inside the container body configured to latch the reticle pod, the latch mechanism being drivable by the lid to shift between a latching condition when the lid is closed and an unlatching condition when the lid is opened, wherein the latch mechanism includes a drive plate and a latch tab coupled to the drive plate, the drive plate being drivable by the lid to shift the latch tab between the latching condition and the unlatching condition, wherein the drive plate and the latch tab move relative to the container body when the drive plate is driven by the lid, wherein the drive plate and the latch tab move relative to each other when the drive plate is driven by the lid.

US Pat. No. 10,658,214

WAFER PROCESSING DEVICE AND METHOD THEREFOR

SHANGHAI MICRO ELECTRONIC...

1. A wafer processing apparatus for pre-alignment and edge exposure of a wafer, comprising:a rotary table, for carrying the wafer;
a motion module comprising, from top down, a rotation module, a lifting module and a translation module interconnected to one another, the rotation module being connected at a top thereof to the rotary table and configured to drive the rotary table to rotate together with the wafer, the lifting module being configured to drive the rotation module and the rotary table to move vertically and enabling the wafer to move at least between a first height and a second height, the translation module being configured to drive the lifting module and the rotation module to move in only one horizontal direction;
a pre-alignment module, configured to collect positional information of the wafer when the wafer is located at a pre-alignment height;
an edge exposure module, configured to perform edge exposure on the wafer, wherein the pre-alignment module and the edge exposure module are positioned at opposing sides of the wafer;
a control module, electrically connected to the pre-alignment module, the edge exposure module and the motion module and configured to receive the positional information of the wafer and to control, based on the received information, the motion module to adjust a position of the rotary table so as to accomplish pre-alignment of the wafer, the control module being further configured to control the edge exposure module to accomplish the edge exposure of the wafer, wherein the control module is configured to perform centering operation using only rotation and a single-axis linear movement in a plane of the wafer; and
a positioning table positioned between the first height and the second height, wherein the positioning table allows the rotary table but not the wafer to vertically pass therethrough, and wherein the positioning table is configured to retain the wafer by suction when the wafer is in proximity thereto.

US Pat. No. 10,658,213

STORAGE FACILITY

Daifuku Co., Ltd., Osaka...

1. A storage facility comprising:N accommodating sections each for accommodating an article, where N is a positive integer, the N accommodating sections being supplied with an inert gas;
M main pipes through which the inert gas flows, where M is a positive integer of 2?M M flow control devices that are respectively connected to the M main pipes, and are configured to control a flow rate of the inert gas flowing through the main pipes;
M branch pipe groups respectively provided for the M main pipes; and
a plurality of switching valves;
wherein each of the branch pipe groups includes N branch pipes that are branched from the main pipe and are in communication with the respective N accommodating sections,
wherein the switching valves are respectively provided on the branch pipes included in at least (M?1) of the branch pipe groups, and are configured to selectively block a flow of the inert gas through the branch pipe, and
wherein each of the flow control devices is configured to control the flow rate of the inert gas flowing through the main pipe to which this flow control device is connected, based on a flow-through pipe count, which is the number of the branch pipes for which the flow of the inert gas is not blocked by the switching valve, out of the N branch pipes of the branch pipe group that corresponds to this main pipe.

US Pat. No. 10,658,212

RING SPACER

ACHILLES CORPORATION, To...

1. A combination, comprising: a pair of ring spacers, and a plate-shaped object,the pair of ring spacers comprising:
an upper ring spacer and a lower ring spacer arranged in an up-and-down direction, and sandwiching the plate-shaped object therebetween in a container for storing and transporting the plate-shaped object when the plate-shaped object is stored in the up-and-down direction, each of the upper ring spacer and the lower ring spacer including
a ring-shaped abutment portion having an upper face, and a lower face,
a control portion integrally formed with the abutment portion and arranged outside the abutment portion to control a lateral movement of the plate-shaped object when the plate-shaped object is stored in the up-and-down direction, the control portion having a control portion upper face located above the upper face of the abutment portion, a control portion lower face located between the upper face and the lower face of the abutment portion, and an outer side face extending between the control portion upper face and the control portion lower face in a direction substantially perpendicular to the upper face and the lower face of the abutment portion and the control portion upper face and the control portion lower face of the control portion, and
a suction portion arranged inside the abutment portion,
wherein each of the upper face and the lower face of the abutment portion has a flat shape, and the control portion is circumferentially formed in a discontinuous state and a length of the control portion in the discontinuous state is 10 to 50 percent relative to a perimeter of the abutment portion,
the upper face of the abutment portion of the lower ring spacer abuts against a lower face of a peripheral edge portion of the plate-shaped object, and is a support face for supporting the lower face of the peripheral edge portion of the plate-shaped object,
the lower face of the abutment portion of the upper ring spacer abuts against an upper face of the peripheral edge portion of the plate-shaped object, and is a pressing face for pressing the upper face of the peripheral edge portion of the plate-shaped object,
the control portion upper face of the lower ring spacer is arranged to be spaced from the control portion lower face of the upper ring spacer without contacting each other,
the control portion further includes
an inner side face extending between the control portion upper face and the upper face of the abutment portion at a side opposite to the outer side face, and
the abutment portion further includes another outer side face extending between, the control portion lower face and the lower face of the abutment portion in the up-and-down direction,
the plate-shaped object is supported on the upper face of the abutment portion of the lower ring spacer and pressed by the lower face of the abutment portion of the upper ring spacer,
the control portion upper face of the lower ring spacer is located at a position higher than the plate-shaped object in the up-and-down direction, and the inner side face of the control portion of the lower ring spacer entirely holds an outer peripheral face of the plate-shaped object in the up-and-down direction so that a horizontal movement of the plate-shaped object is restricted inside the inner side face of the control portion of the lower ring spacer, and
the lower face of the abutment portion of the upper ring spacer is located between the control portion upper face and the upper face of the abutment portion of the lower ring spacer in the up-and-down direction so that a horizontal movement of the upper ring spacer is restricted when the upper ring spacer is stacked on the lower ring spacer.

US Pat. No. 10,658,211

DATA STRUCTURES FOR SEMICONDUCTOR DIE PACKAGING

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die;
mechanical equipment configured to test packaged die; and
a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.

US Pat. No. 10,658,210

APPARATUS AND METHOD FOR DETECTING OVERLAY MARK WITH BRIGHT AND DARK FIELDS

SEMICONDUCTOR MANUFACTURI...

1. An apparatus for detecting a plurality of marks on a substrate, each of the marks having a first stripe group and a second stripe group spaced apart from each other and disposed in parallel to each other, the apparatus comprising:at least one detection module moveable over a surface of the substrate along a first direction and a second direction perpendicular to the first direction, the at least one detection module comprising:
at least one detection unit configured to obtain data from a mark and operable to perform repeated acquisition operations on the first stripe group and the second stripe group of the mark, each of the acquisition operations acquiring data associated with the first stripe group or the second stripe group of the mark;
at least one positioning unit comprising at least one support rail and configured to align the at least one detection unit with the mark in the first direction;
a frame comprising a first bracket and a second bracket disposed opposite to each other; and
an air cushion guide comprising:
a first rail extending in the second direction;
a first slider engaged with the first rail and configured to support the first bracket;
a second rail extending in the second direction; and
a second slider engaged with the second rail and configured to support the second bracket,
wherein the first slider when moving along the first rail drives the first bracket along the second direction and the second slider when moving along the second rail drives the second bracket along the second direction, so that the detection module moves above the surface of the substrate in the first direction and in the second direction,
wherein the at least one positioning unit further comprises a positioning mechanism configured to move the at least one detection unit along the at least one support rail to a desired position to align the at least one detection unit with a mark,
wherein the at least one detection unit comprises first and second holes arranged vertically with respect to each other and a third hole disposed between the first and second holes, the third hole having an internal thread, and a screw rod having an external thread engaging the internal thread of the third hole, the screw rod passing through the third hole drives the at least one detection unit along the at least one support rail when rotating, and
wherein the at least one support rail is mounted to the frame and comprises a first support rail passing through the first hole and a second support rail passing through the second hole and suspended between the first and second brackets.

US Pat. No. 10,658,209

APPARATUS AND METHOD FOR COMPONENT POSITINING

Stora Enso, OYJ, Helsink...

1. An apparatus for component positioning, comprising:a receptacle configured to receive a number of components to be placed on a target substrate,
agitator configured to exert force impulses on the receptacle so as to cause the components to change their position including turning over inside the receptacle;
inspection equipment configured to verify the position of the components inside the receptacle to identify one or more components that fulfill a predefined position criterion from the remaining components to be agitated more; and
pick and place equipment configured to pick said identified one or more components from the receptacle that fulfill the predefined position criterion and place the picked components on the target substrate while leaving the remaining components in the receptacle for further agitation.

US Pat. No. 10,658,208

POLYIMIDE COMPOSITION FOR PACKAGE STRUCTURE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A polyimide composition for a package structure, comprising:a polyimide precursor;
a cross-linker;
a photosensitizer;
a first additive, wherein the first additive comprises a polyether based compound;
a second additive, wherein the second additive comprises a siloxane based compound; and
a solvent;
wherein the polyimide composition has more than 98% cyclization of the polyimide precursor when the polyimide composition is cured at a temperature range of 160° C. to 200° C.

US Pat. No. 10,658,207

PLATEN FOR REDUCING PARTICLE CONTAMINATION ON A SUBSTRATE AND A METHOD THEREOF

Varian Semiconductor Equi...

10. A ground pin for connecting a substrate to ground, the ground pin comprising:a pin body in contact with a ground electrode, the ground electrode disposed within a first cavity, wherein the pin body extends from the first cavity to a fluid region; and
a sleeve supporting the pin body, the sleeve including a fluid channel transporting a fluid, wherein the fluid channel is a groove disposed on the sleeve, extending between an upper surface of the sleeve and a lower surface of the sleeve, wherein the groove is in communication with the fluid region and the first cavity, and wherein the groove includes a concave surface extending toward a center of the sleeve.

US Pat. No. 10,658,206

METHOD OF FORMING A COMPOSITE SUBSTRATE FOR LAYERED HEATERS

Watlow Electric Manufactu...

1. A method of forming a heater assembly for use in semiconductor processing comprising the following steps in sequence:individually forming a heater substrate and an application substrate such that the heater substrate is separated from the application substrate when the heater substrate is formed;
securing the heater substrate to the application substrate at an elevated temperature using a thermal bonding process to form a bonding layer after the heater substrate and the application substrate are formed;
applying a first dielectric layer onto the heater substrate by a layered process after the heater substrate is secured to the application substrate; and
applying a resistive heating layer onto the first dielectric layer by the layered process after the first dielectric layer is applied onto the heater substrate,
wherein the layered process is selected from a group consisting of thick film, thin film, thermal spray, and sol-gel processes and at a temperature lower than the elevated temperature at which the heater substrate is secured to the application substrate using the thermal bonding process, and
wherein the heater substrate defines a material having a coefficient of thermal expansion that is matched to a coefficient of thermal expansion of a material of the first dielectric layer, the material of the first dielectric layer not being capable of withstanding the elevated temperature of the thermal bonding process.

US Pat. No. 10,658,205

CHEMICAL DISPENSING APPARATUS AND METHODS FOR DISPENSING A CHEMICAL TO A REACTION CHAMBER

ASM IP Holdings B.V., Al...

1. A chemical dispensing apparatus for providing a chlorine vapor to a reaction chamber comprising:a chemical storage vessel configured for storing a chlorine-containing chemical species as a liquid or solid;
a reservoir vessel in fluid communication with the chemical storage vessel, the reservoir vessel configured for converting the chlorine-containing chemical species to the chlorine vapor;
a reaction chamber for semiconductor device fabrication in fluid communication with the reservoir vessel;
a vapor storage unit for storing the chlorine vapor, the vapor storage unit disposed between the reservoir vessel and the reaction chamber; and
one or more heating units configured for heating the chlorine-containing chemical species stored in the chemical storage vessel,
wherein the chlorine vapor from the reservoir vessel is introduced into the reaction, and
wherein the chemical storage vessel comprises an inner surface coated with a fluorine based film, wherein the fluorine based film comprises at least one of polytetrafluoroethylene (PTFE), fluorinated ethylene propylene copolymer (FEP), perfluoroalkoxy (PFA), polyethylene terephthalate copolymer (PETG), or polyamide based copolymers.

US Pat. No. 10,658,204

SPIN CHUCK WITH CONCENTRATED CENTER AND RADIAL HEATING

LAM RESEARCH AG, Villach...

1. A substrate processing system to treat a substrate, comprising:a spin chuck configured to hold and rotate a substrate;
a heating assembly configured to heat an opposite surface of the substrate and including:
a main heater assembly including a first plurality of light emitting diodes (LEDs) arranged on a first printed circuit board (PCB) in a first plane that is spaced from and parallel to a second plane including the substrate; and
a nozzle stack cap assembly including:
at least one nozzle to dispense liquid onto a center of a first surface of the substrate; and
a radiant heat source that is arranged closer to the substrate than the first plane and that is configured to heat the center of the first surface of the substrate.

US Pat. No. 10,658,203

SUBSTRATE PROCESSING APPARATUS AND PROCESSING CUP CLEANING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus comprising:a substrate holding unit, rotating a substrate around a vertical rotational axis passing through a central portion of the substrate while holding the substrate horizontally;
a chemical liquid nozzle, discharging a chemical liquid toward the substrate held by the substrate holding unit;
a guard of cylindrical shape, including a cylindrical portion that surrounds the substrate held by the substrate holding unit, and catching liquid scattered outward from the substrate holding unit;
a cup of annular shape, defining a liquid receiving groove of annular shape positioned below the cylindrical portion, and catching liquid, guided downward by the guard, by the liquid receiving groove;
a guard elevating/lowering unit, moving the guard in an up/down direction;
a cleaning liquid supplying unit, including a first cleaning liquid nozzle that discharges a cleaning liquid, differing from the chemical liquid, from a discharge port disposed above or below the substrate held by the substrate holding unit, and supplying the cleaning liquid, discharged from the first cleaning liquid nozzle, to the liquid receiving groove via the substrate holding unit and the guard;
a cleaning liquid draining unit, draining the cleaning liquid, in the liquid receiving groove, via a drain port provided in the liquid receiving groove;
a liquid amount control unit, controlling the cleaning liquid supplying unit and the cleaning liquid draining unit to accumulate the cleaning liquid in the liquid receiving groove and to cause the cleaning liquid in the liquid receiving groove to overflow from an entrance of the liquid receiving groove at least either when a lower end portion of the cylindrical portion is immersed in the cleaning liquid in the liquid receiving groove or when the lower end portion of the cylindrical portion is not immersed in the cleaning liquid in the liquid receiving groove;
a vat, positioned below the cup and catching the cleaning liquid that overflowed from the entrance of the liquid receiving groove;
a lower drain piping, guiding the cleaning liquid, drained from the vat via a lower drain port provided in the vat; and
a guard position control unit, controlling the guard elevating/lowering unit to cause the lower end portion of the cylindrical portion to be immersed in the cleaning liquid in the liquid receiving groove.

US Pat. No. 10,658,202

SEMICONDUCTOR PACKAGE WITH REDUCED PARASITIC COUPLING EFFECTS AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a silicon-on-insulator (SOI) structure including an epitaxial layer, a buried oxide (BOX) layer over the epitaxial layer, and a silicon handle layer over the BOX layer, wherein:
the epitaxial layer has a first sacrificial epitaxial section, a first active epitaxy section and an isolation region; and
the isolation region surrounds the first active epitaxy section and separates the first active epitaxy section from the first sacrificial epitaxial section;
forming at least one first etchable structure that extends through the first sacrificial epitaxial section and the BOX layer to the silicon handle layer;
integrating a first active device in or on the first active epitaxy section, such that the epitaxial layer is formed as a device layer; and
forming a (back-end-of-line) BEOL layer underlying the device layer, wherein:
the BEOL layer has an upper surface including a first surface portion and a second surface portion surrounding the first surface portion;
the first sacrificial epitaxial section is over the first surface portion and not over the second surface portion;
the first epitaxy section and the isolation region are over the second surface portion and not over the first surface portion; and
the BEOL layer comprises a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion.

US Pat. No. 10,658,201

CARRIER SUBSTRATE FOR A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A CARRIER SUBSTRATE FOR A SEMICONDUCTOR DEVICE

Intel IP Corporation, Sa...

1. A method for forming a carrier substrate for a semiconductor device, the method comprising:providing a substrate layer with at least a first area, the first area comprising conductive particles embedded in an electrically insulating material; and
localized heating of the first area along a desired trace by a laser to form a conductive trace of merged particles along the desired trace wherein a remainder of the first area that is not subjected to the localized heating remains electrically insulating.

US Pat. No. 10,658,200

THIN FILM COMPONENT SHEET, BOARD WITH BUILT-IN ELECTRONIC COMPONENT, AND METHOD OF MANUFACTURING THE THIN FILM COMPONENT SHEET

TDK CORPORATION, Tokyo (...

1. A thin film component sheet comprising:an interconnection layer formed of a conductor;
an insulating layer laminated on the interconnection layer and formed of an insulating material; and
a plurality of thin film electronic components, each of the plurality of thin film electronic components (1) having a pair of electrode layers and a dielectric layer between the pair of electrode layers, (2) being spaced from all other of the plurality of thin film electronic components, (3) being positioned on the insulating layer, and (4) having a through-hole extending in a thickness direction of the each of the plurality of thin film electronic components, wherein:
one of the pair of electrode layers of the each of the plurality of thin film electronic components includes a flat surface that is a part of an exterior surface of the thin film component sheet;
each of the through-holes is (1) separate and spaced from all other through-holes and (2) completely surrounded by one of the pair of electrode layers and the dielectric layer; and
the insulating material of the insulating layer is in the through-holes.

US Pat. No. 10,658,199

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

16. A method of manufacturing a semiconductor device, the method comprising:attaching a die to a substrate;
forming vias over the substrate;
forming an encapsulant over the die and the vias, the encapsulant contacting sidewalls of the vias and sidewalls of the die;
forming a polymer layer over the die, the vias, and the encapsulant, comprising:
disposing a polymer raw material over the die, the vias, and the encapsulant, the polymer raw material comprising a polymer precursor, a photosensitizer, and an additive;
patterning the polymer raw material to form a polymer material, the patterning comprising exposing the polymer raw material to radiation; and
curing the polymer material at a temperature of less than 230° C., the curing forming above about 98% cyclization in the polymer layer; and
after forming the polymer layer, forming a redistribution layer over the polymer layer.

US Pat. No. 10,658,198

SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME

Intel Corporation, Santa...

1. A microelectronic structure, comprising:a microelectronic package having a plurality of interconnects on an active surface thereof, and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the microelectronic substrate includes a conductive structure extending through the solder resist structure and wherein the microelectronic substrate includes an opening extending into the solder resist structure;
wherein the conductive structure electrical connects a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, wherein the opening prevents a second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer, and wherein the second interconnect of the plurality of interconnects does not physically contact with the microelectronic substrate, and
wherein the solder resist structure comprises an upper solder resist material layer formed on a lower solder resist material layer, wherein the conductive structure extends through the upper solder resist material layer and the lower second solder resist material layer, and wherein the opening extends through the upper solder resist material layer and terminates at the lower solder resist material layer.

US Pat. No. 10,658,197

METHOD FOR PRODUCING LOW-PERMITTIVITY SPACERS

STMICROELECTRONICS SA, M...

1. A method for manufacturing a transistor using a stack comprising at least one gate pattern comprising at least one flank and being located above an underlying layer made of a semi-conductor material, the method comprising the following successive steps:forming, at least partially, at least one gate spacer by depositing at least one layer made of a non-carbon material on the at least one flank of the at least one gate pattern;
after the depositing of the at least one layer made of a non-carbon material, performing at least one step of exposing the stack to a temperature greater than or equal to 600° C.;
after the at least one step of exposing, performing at least one step of reducing of a dielectric permittivity of the at least one gate spacer, the reducing comprising at least one ion implantation in a portion at least of a thickness of the at least one gate spacer,
wherein parameters of the at least one ion implantation including species implanted, energy, and implantation dose, being chosen such that the at least one ion implantation reduces the dielectric permittivity of the at least one gate spacer, and
wherein, during the at least one ion implantation, the at least one gate spacer is present only on the at least one gate pattern; and
at least one step of forming at least one source/drain zone in a peripheral zone surrounding the at least one gate pattern and located above the underlying layer, wherein the at least one step of forming of the at least one source/drain zone comprises
the at least one step of exposing the stack to the temperature greater than or equal to 600° C., and
a step of epitaxy of the at least one source/drain zone.

US Pat. No. 10,658,195

METAL OXIDE LAYERED STRUCTURE AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:depositing a dielectric layer over a semiconductor die encapsulated in an encapsulant;
depositing a conductive material over the dielectric layer;
forming a first native oxide on the conductive material;
exposing the first native oxide to an oxygen-containing plasma to form a metal oxide layer with a metal to oxygen ratio that is substantially 1:1, the metal oxide layer being at least 50 ? thick; and
depositing a dielectric material over the metal oxide layer.

US Pat. No. 10,658,194

SILICON-BASED DEPOSITION FOR SEMICONDUCTOR PROCESSING

Lam Research Corporation,...

1. A method for processing a substrate in a processing chamber, wherein a stack of a plurality of alternating layers is over the substrate, and wherein at least one of the alternating layers is silicon oxide, comprising:partially etching features in the plurality of alternating layers of the stack;
after partially etching features, forming a deposition on sidewalls of the partially etched features in the plurality of alternating layers, comprising:
flowing a silicon containing gas into the processing chamber;
flowing a COS containing gas into the processing chamber;
providing RF power into the processing chamber from at least one transformer coupled plasma (TCP) coil; and
forming a plasma from the silicon containing gas and the COS containing gas in the processing chamber using the RF power, wherein the plasma provides the deposition on sidewalls of the partially etched features in the plurality of alternating layers; and
after forming the deposition on sidewalls of the partially etch features is completed, further etching the partially etched features in the plurality of alternating layers of the stack, wherein the deposition protects sidewalls of the partially etched features from the further etching.

US Pat. No. 10,658,193

ETCHING METHOD AND ETCHING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. An etching method of etching a processing target object having a silicon-containing film thereon and a photoresist formed on a surface of the silicon-containing film, the etching method comprising:a first etching process of etching, by using the photoresist as a mask, the silicon-containing film of the processing target object placed in a processing vessel; and
a second etching process of etching the photoresist by supplying a first processing gas containing oxygen and halogen into the processing vessel, or supplying a third processing gas containing the oxygen into the processing vessel after supplying a second processing gas containing the halogen into the processing vessel,
wherein the first etching process and the second etching process are repeated a multiple number of times.

US Pat. No. 10,658,192

SELECTIVE OXIDE ETCHING METHOD FOR SELF-ALIGNED MULTIPLE PATTERNING

Tokyo Electron Limited, ...

1. A method of etching, comprising:providing a substrate having a first material containing silicon oxide material and a second material that is different from the first material;
forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas and at least one additional gas selected from the group consisting of He and H2;
exposing the first material on the substrate to the first chemical mixture to modify a first region of the first material;
thereafter, forming a second chemical mixture by plasma-excitation of a second process gas containing an inert gas and an additional gas containing C, H, and F; and
exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material and remove the modified first material from the first region of the substrate.

US Pat. No. 10,658,190

EXTREME ULTRAVIOLET LITHOGRAPHY PATTERNING WITH DIRECTIONAL DEPOSITION

International Business Ma...

1. An extreme ultraviolet lithographic patterning method, comprising:depositing a hard mask material on a substrate structure using directional deposition, the hard mask material forming a hard mask layer that covers patterning features of an extreme ultraviolet resist mask of the substrate structure;
etching the hard mask material selective to a layer underlying the extreme ultraviolet resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the extreme ultraviolet resist mask; and
patterning at least one layer of the substrate structure based on the extreme ultraviolet resist mask and the hard mask layer.

US Pat. No. 10,658,189

ETCHING METHOD

TOKYO ELECTRON LIMITED, ...

1. An etching method comprising: a) providing a target object in a processing chamber, the target object including a first region, a second region and a mask, the first region being made of a first silicon-containing material, the second region being made of a second material different from the first silicon-containing material, the first region being disposed on the second region, the second region having a recess, the recess being filled with the first region, the mask being disposed on the first region, the mask having an opening, the opening having a width larger than a width of the recess; b) generating a plasma from a fluorocarbon containing gas supplied into the processing chamber to form a fluorocarbon containing deposit on the target object; and c) applying a pulsed power to the processing chamber, thereby causing the first region to be etched with fluorocarbon radicals in the fluorocarbon containing deposit; and d) repeating b) and c), wherein the pulsed power includes a first power having a first frequency ranging from 27 MHz to 100 MHz and a second power having a second frequency ranging from 400 kHz to 40 MHz, wherein, in c), the pulsed power is generated by applying the first power for plasma generation to an upper electrode provided above the target object within the processing chamber; applying the second power for ion attraction to a lower electrode provided under the target object; and performing a modulation of alternately switching a period during which the first power and the second power are ON and a period during which the first power and the second power are OFF.

US Pat. No. 10,658,188

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

ABLIC INC., Chiba (JP)

1. A method of manufacturing a semiconductor device in which a trench is formed on a semiconductor substrate, comprising:forming a mask of an inorganic substance on a front surface of a semiconductor substrate so that the mask has an opening in a portion in which a trench is formed;
controlling a temperature of a sample stage in a reaction container of an etching machine so as to keep the sample stage at constant predetermined temperature of 5° C. to 30° C.;
putting the semiconductor substrate on the sample stage;
introducing an etching gas including oxygen and sulfur hexafluoride to an interior of the reaction container while maintaining a flow rate ratio of oxygen to sulfur hexafluoride between 70% and 100%; and
performing plasma etching of the semiconductor substrate with the etching gas to form the trench, while maintaining the constant predetermined temperature.

US Pat. No. 10,658,187

METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND A SEMICONDUCTOR COMPONENT

FRAUNHOFER-GESELLSCHAFT Z...

1. A method for manufacturing a semiconductor component, the method comprising:providing a flat carrier with an upper side and a lower side, wherein the carrier comprises an opening that runs between the upper side and the lower side;
providing a semiconductor arrangement that comprises a semiconductor chip, wherein the semiconductor chip comprises electrically and/or optically active regions on a lower side and the semiconductor arrangement comprises a sacrificial layer on an upper side, the sacrificial layer comprising metallic or semi-conductive material;
arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane;
casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier, wherein the semiconductor arrangement with the carrier and with the potting compound forms a semiconductor system; and
thinning out the semiconductor system by way of grinding from above, the sacrificial layer being thinned out on grinding, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

US Pat. No. 10,658,186

METHOD OF FORMING SEMICONDUCTOR DEVICE USING TITANIUM-CONTAINING LAYER AND DEVICE FORMED

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, the method comprising:depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D; and
annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

US Pat. No. 10,658,185

LASER IRRADIATION APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR OPERATING LASER IRRADIATION APPARATUS

THE JAPAN STEEL WORKS, LT...

1. A laser irradiation apparatus comprising:a laser oscillator configured to generate a laser beam;
a conveying stage configured to float and convey a workpiece to be irradiated with the laser beam; and
a measuring instrument configured to measure a beam profile of the laser beam, wherein
the conveying stage includes a conveying surface opposed to the workpiece, and a bottom surface on the side opposite to the conveying surface,
the measuring instrument is positioned below the bottom surface of the conveying stage,
the conveying stage includes a detachable part in a part of the conveying stage, the detachable part being configured to be detachable from the conveying stage,
an opening is formed in the conveying stage by detaching the detachable part from the conveying stage, the opening extending from the conveying surface to the bottom surface, and
the measuring instrument is configured to measure the beam profile of the laser beam through the opening.

US Pat. No. 10,658,184

PATTERN FIDELITY ENHANCEMENT WITH DIRECTIONAL PATTERNING TECHNOLOGY

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor manufacturing, comprising:providing a substrate and a patterning layer over the substrate, wherein the patterning layer has substantial uniform thickness across the entire substrate;
removing a first portion of the patterning layer to form a hole in the patterning layer;
applying a first directional etching along a first direction to two opposing inner sidewalls of the hole to remove a second portion of the patterning layer; and
applying a second directional etching along a second direction to another two opposing inner sidewalls of the hole to remove a third portion of the patterning layer, wherein the second direction is different from the first direction.

US Pat. No. 10,658,183

IMPURITY ADDING APPARATUS, IMPURITY ADDING METHOD, AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD

FUJI ELECTRIC CO., LTD., ...

7. A method of manufacturing a semiconductor device, comprising:disposing a wall-like block, having a recess, above a semiconductor substrate of a first or second conductivity type so that the wall-like block is suspended above the semiconductor substrate and the recess is facing the semiconductor substrate so as to form a space between the wall-like block and the semiconductor substrate, the wall-like block including
a first feeding canal connected to the recess and located on a first side of the wall-like block,
a second feeding canal connected to the recess and located on a second side of the wall-like block opposite to the first side,
a first ejecting canal located on the second side, the first ejecting canal extending vertically from an upper surface to a lower surface of the wall-like block, and
a second ejecting canal located on the first side, the second ejecting canal extending vertically from the upper surface to the lower surface of the wall-like block;
forming a solution region where a layer of solution containing impurity elements of a first conductivity type is localized, inside the space, on a part of a surface of the semiconductor substrate defined by the recess so that the impurity elements are selectively in contact with the semiconductor substrate, the space between the wall-like block and the semiconductor substrate being selected such that the surface tension inhibits the solution from leaking beyond the wall-like block;
moving the solution on the surface of the semiconductor substrate, the moving the solution including
flowing the solution out of the first feeding canal and collecting the solution into the first ejecting canal while maintaining the flow of the solution between the first feeding canal and the first ejecting canal, while the semiconductor substrate is being moved in a first direction and a valve controlling flow of the solution out of the second feeding canal is closed, and
flowing the solution out of the second feeding canal and collecting the solution into the second ejecting canal while maintaining the flow of the solution between the second feeding canal and the second ejecting canal, while the semiconductor substrate is being moved in a second direction and a valve controlling flow of the solution out of the first feeding canal is closed; and
irradiating a laser beam onto the semiconductor substrate through the solution region to form a first semiconductor region of the first conductivity type in the surface of the semiconductor substrate.

US Pat. No. 10,658,182

CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION

International Business Ma...

1. A method for integrating electronic elements into an electronic package assembly, comprising:obtaining a semiconductor structure including a device wafer comprising an array of singulated electronic elements, a handle wafer, and a release layer, the device wafer being bonded to the handle wafer, and the release layer being positioned between the device wafer and the handle wafer;
aligning a carrier with the device wafer, the carrier including a rigid body portion and a plurality of discrete raised regions extending from the rigid body portion, each of the discrete raised regions corresponding to one of a targeted plurality of the singulated electronic elements;
depositing a further release layer on a top surface of the device wafer or on the raised regions of the carrier;
attaching the targeted plurality of singulated electronic elements to the discrete raised regions of the carrier;
subsequent to attaching the targeted plurality of the singulated electronic elements to the discrete raised regions of the carrier and while maintaining attachment of the of the targeted plurality of singulated electronic elements to the discrete raised regions of the carrier, directing electromagnetic radiation through the handle wafer, thereby causing ablation of discrete, selected portions of the release layer beneath the targeted plurality of the singulated electronic elements;
aligning the targeted plurality of singulated electronic elements attached to the carrier with a plurality of targeted bonding sites of an electronic package assembly;
integrating the targeted plurality of singulated electronic elements into the electronic package assembly at the targeted bonding sites, and
detaching the targeted plurality of singulated electronic elements from the discrete raised regions of the carrier.

US Pat. No. 10,658,181

METHOD OF SPACER-DEFINED DIRECT PATTERNING IN SEMICONDUCTOR FABRICATION

ASM IP Holding B.V., Alm...

1. A method of spacer-defined direct patterning in semiconductor fabrication, comprising:(i) presetting a target width of lines to be patterned in a template using photoresist structures formed by photolithography on the template;
(ii) providing the template having the photoresist structures patterned thereon;
(iii) trimming the photoresist structures such that a width of each trimmed photoresist structure is smaller than the target width;
(iv) depositing an oxide film on the template, thereby entirely covering with the oxide film an exposed top surface of the template and the trimmed photoresist structures;
(v) etching the oxide film-covered template to remove an unwanted portion of the oxide film without removing the trimmed photoresist structures so as to form vertical spacers isolated from each other on the template which is referred to as a spacer-formed template, each vertical spacer substantially maintaining the target width and being constituted by the trimmed photoresist structures and a vertical portion of the oxide film covering sidewalls of the trimmed photoresist structures; and
(vi) etching the spacer-formed template to transfer a pattern constituted by the vertical spacers in their entireties to the template to form lines with the target width.

US Pat. No. 10,658,180

EUV PATTERN TRANSFER WITH ION IMPLANTATION AND REDUCED IMPACT OF RESIST RESIDUE

International Business Ma...

1. A method for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist scumming in a semiconductor structure, the method comprising:forming a top hardmask over an organic planarization layer (OPL);
depositing a photoresist over the top hardmask;
patterning the photoresist using EUV lithography;
performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist scumming;
stripping the photoresist; and
selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material,
wherein an ion implantation energy is selected to be high enough for ions to penetrate through the resist scumming and into the top hardmask but low enough for the ions to be stopped in the photoresist.

US Pat. No. 10,658,179

METHOD AND STRUCTURE OF MIDDLE LAYER REMOVAL

Taiwan Semiconductor Manu...

1. A method, comprising:providing a substrate having a structure formed on the substrate;
forming a spacer layer on the structure;
forming a mask layer over the spacer layer, the mask layer comprising a first layer, a second layer over the first layer, and a third layer over the second layer;
patterning the third layer of the mask layer;
etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form a first opening through the first layer and a second opening through the second layer, wherein an overhang of the second layer is directly above the first opening and surrounds the second opening, and a portion of the spacer layer is exposed through the first opening and the second opening; and
removing the second layer using a wet etchant before a formation of a backfill material layer in the first opening and over the first layer.

US Pat. No. 10,658,178

PATTERNING METHOD UTILIZING DUMMY MANDREL

UNITED MICROELECTRONICS C...

1. A patterning method, comprising:forming a bulk mandrel and a plurality of strip mandrels on a mask layer;
forming spacers on sidewalls of the bulk mandrel and the strip mandrels, wherein top surfaces of the spacers are higher than a top surface of the bulk mandrel at end of step of forming the spacers;
removing the strip mandrels while reserving the bulk mandrel;
filling a dielectric material between the spacers and on the bulk mandrel; and
forming a patterned photoresist covering the bulk mandrel and a part of the spacers that is disposed directly next to the bulk mandrel but exposing the other part of the spacers after filling the dielectric material.

US Pat. No. 10,658,177

DEFECT-FREE HETEROGENEOUS SUBSTRATES

Hewlett Packard Enterpris...

1. A method, comprising:applying a dielectric mask on a heterogeneous substrate having an air gap formed in each one of a plurality of air trenches except a portion of the heterogeneous substrate over a first air trench of the plurality of air trenches;
growing a first active region on the portion of the heterogeneous substrate over the first air trench;
applying the dielectric mask on top of the first active region;
removing the dielectric mask over another portion of the heterogeneous substrate over another air trench of the plurality of air trenches;
growing another active region on the another portion of the heterogeneous substrate over the another air trench;
applying the dielectric mask on top of the another active region; and
repeating the removing, the growing the another active region, and the applying the dielectric mask on top of the another active region until an active region is grown over each portion of the heterogeneous substrate that is over a respective air trench of the plurality of air trenches.

US Pat. No. 10,658,176

METHODS OF MITIGATING COBALT DIFFUSION IN CONTACT STRUCTURES AND THE RESULTING DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a first dielectric layer;
forming first and second conductive structures comprising cobalt embedded in the first dielectric layer;
forming a second cap layer above and directly contacting an uppermost surface of the first dielectric layer after forming the first and second conductive structures, wherein the first dielectric layer and the second cap layer comprise different materials, and a portion of the second cap layer comprises a second concentration carbon or nitrogen; and
forming a first cap layer above the first and second conductive structures and the second cap layer, wherein the first cap layer comprises a first concentration of carbon or nitrogen and the first cap layer is an extension of the second cap layer, and wherein the first concentration of carbon or nitrogen in the first cap layer is less than the second concentration of the carbon or nitrogen in the second cap layer.

US Pat. No. 10,658,175

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device comprising:forming in a semiconductor substrate a trench used for a source/drain region; and
forming a single SiGe seed layer simultaneously on an entirety of a sidewall and bottom of the trench,
wherein the single SiGe seed layer on the sidewall of the trench has an uneven thickness and has a maximum thickness at a location corresponding to a channel region in the semiconductor substrate, and
completing the forming of the single SiGe seed layer when a ratio of the maximum thickness of the SiGe seed layer on the sidewall of the trench to the thickness of the SiGe seed layer on the bottom of the trench is in the range from about 1:2.5 to about 1:1.

US Pat. No. 10,658,174

ATOMIC LAYER DEPOSITION AND ETCH FOR REDUCING ROUGHNESS

Lam Research Corporation,...

1. A method comprising:etching, in a plasma chamber, to a first depth of a substrate to form a plurality of features at the first depth;
depositing, in the plasma chamber, a first passivation layer on sidewalls of the plurality of features by atomic layer deposition (ALD), wherein a step coverage of the first passivation layer in the plurality of features is greater than about 95%; and
etching, in the plasma chamber, the plurality of features to a second depth greater than the first depth, wherein the first passivation layer is configured to substantially prevent lateral etching of the sidewalls and substantially limit sidewall roughness after etching to the second depth.

US Pat. No. 10,658,173

METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE ON A SEMICONDUCTOR WAFER

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor structure on a semiconductor wafer, comprising:providing a semiconductor wafer comprising a first region, a second region, and a wafer bevel region, wherein the wafer bevel region comprises a silicon surface;
forming a first semiconductor structure in the first region and a second semiconductor structure in the second region;
subjecting the semiconductor wafer to a bevel plasma treatment to form a blocking layer only in the wafer bevel region; and
performing a silicidation process to form a silicide layer only in the first region and the second region;
depositing a conductive layer only in the first region and the second region; and
patterning the conductive layer in the first region into a storage node pad and patterning the conductive layer in the second region into a contact plug and M0 metal layer, while revealing the silicon surface of the wafer bevel region.

US Pat. No. 10,658,172

DIELECTRIC GAPFILL OF HIGH ASPECT RATIO FEATURES UTILIZING A SACRIFICIAL ETCH CAP LAYER

Lam Research Corporation,...

1. A method of filling a feature on a substrate, the method comprising:providing the substrate comprising the feature to a process chamber, the feature comprising a feature opening and sidewalls, the sidewalls having sidewall topography comprising stubs on a surface of the sidewall and regions between the stubs;
depositing a first amount of a material into the feature conformally over the sidewall topography for a duration insufficient to fill the feature using a precursor and a second reactant to form the first amount of the material having the sidewall topography;
exposing the first amount of the material to an etchant to etch some of the first amount of the material to smoothen the sidewall topography of the first amount of the material and form an etched first amount of the material; and
after etching the first amount of the material, depositing a second amount of the material over the etched first amount of the material,
the material selected from the group consisting of silicon carbide, silicon nitride, silicon, tungsten, ruthenium, copper, cobalt, and molybdenum.

US Pat. No. 10,658,171

WAFER PROCESSING APPARATUS

DISCO CORPORATION, Tokyo...

1. A laser processing apparatus comprising:a chuck table for holding a wafer;
laser beam applying means for applying a laser beam to said wafer held on said chuck table; and
a feeding mechanism for relatively feeding said chuck table and said laser beam applying means;
said laser beam applying means including
a laser oscillator for oscillating said laser beam, and
a condenser having a focusing lens for focusing said laser beam oscillated by said laser oscillator and applying said laser beam focused to said wafer held on said chuck table;
said condenser having a lens configured to realize spherical aberration such that a focal point to be formed by said laser beam passing through a radially inner portion of said condenser is continuously changed in position toward said chuck table from a focal point to be formed by said laser beam passing through a radially outer portion of said condenser;
said laser beam being applied to said wafer in the condition where the focal point of said laser beam is set inside said wafer so as to be continuously changed in position along the thickness of said wafer to account for changes in the thickness of said wafer, thereby forming a shield tunnel inside said wafer, said shield tunnel being composed of a fine hole and an amorphous region surrounding said fine hole.

US Pat. No. 10,658,170

HIGH-POWER ULTRAVIOLET (UV) AND VACUUM ULTRAVIOLET (VUV) LAMPS WITH MICRO-CAVITY PLASMA ARRAYS

Eden Park Illumination, ...

1. A plasma lamp comprising:two or more internal plates, each having an interior surface and an exterior surface; the internal plates positioned approximately parallel to one another;
at least two different arrays of microcavities formed in the interior surface of at least one of the internal plates, such that the microcavities in the different arrays exhibit a different geometric shape, at least one different spatial dimension, microcavity center-to-center spacing (pitch), or a combination thereof;
a gas or mixture of gases in which a glow discharge (plasma) is produced; the gas occupying the fixed volume between the internal plates and being in contact with the array of microcavities; and
a plurality of electrodes connected to a power supply designed to deliver a time-varying voltage; at least one electrode being located on the exterior surface of at least one of the internal plates;
wherein the time-varying voltage interacts with the gas, such that spatially uniform, glow discharge (plasma) is formed both within the microcavities and the fixed volume between the internal plates, the glow discharge (plasma) emitting radiation in the UV/VUV spectral region that is at least partially transmitted by at least one of the internal plates and the electrodes, such that the radiation is extracted from the lamp;
wherein, the different arrays of microcavities are spatially separated on the interior surface of the internal plate, or interlaced or interwoven, such that the microcavities in one array are alternated or staggered with the microcavities of another array.

US Pat. No. 10,658,169

METHODS, APPARATUS, AND SYSTEM FOR MASS SPECTROMETRY

Massachusetts Institute o...

1. A mass spectrometer comprising:a vacuum housing defining a vacuum cavity;
a substrate disposed within the vacuum cavity;
an electrode, disposed on the substrate, to control acceleration of an ion beam propagating through the vacuum cavity; and
an adjustable mechanical filter, disposed within the vacuum cavity, to spatially filter the ion beam, the filter including an adjustable flexure integrally formed with the substrate.

US Pat. No. 10,658,168

MULTIPLE GAS FLOW IONIZER

PerkinElmer Health Scienc...

1. An ionizer comprising:an outer gas transport tube having an outlet in flow communication with an inlet to a mass analyser;
an inner gas transport tube extending into said outer gas transport tube;
an innermost analyte supply tube extending into said inner gas transport tube, and upstream of said outlet of said outer gas transport tube, the innermost analyte supply tube configured to provide droplets of solvated analyte, received by the innermost analyte supply tube from an analyte source, from a tip of said innermost analyte supply tube into said inner gas transport tube; and
at least one voltage source interconnected with said outer gas transport tube, said inner gas transport tube, and said innermost analyte supply tube, wherein the voltage source is configured to provide a voltage to said innermost analyte supply tube to transport and guide solvated analyte to the tip of said innermost analyte tube to provide the solvated analyte into the inner gas transport tube, wherein the voltage source is configured to provide a voltage to said inner gas transport tube to spray, in a first gas, the solvated analyte received from the innermost analyte supply tube into the outer gas transport tube, and wherein the voltage source is configured to provide a voltage to said outer gas transport tube to ionize, in a second gas, the sprayed analyte received from the inner gas transport tube, and wherein said at least one voltage source is operable to maintain said outer gas transport tube, said inner gas transport tube and said innermost analyte supply tube at about equal potential offset from a potential of said inlet to the mass analyzer, to guide the ionized analyte from said ionizer to said inlet of said mass analyzer.

US Pat. No. 10,658,167

OFF-AXIS IONIZATION DEVICES AND SYSTEMS USING THEM

PerkinElmer Health Scienc...

1. An ion source comprising:a chamber comprising a sample inlet configured to receive a sample comprising an analyte, the chamber further comprising an ion outlet configured to provide ions from the chamber; and
an electron source comprising a conductive helical coil configured to provide a magnetic field that accelerates electrons into the chamber as an accelerated electron beam along a longitudinal axis of the conductive helical coil, wherein the chamber further comprises an electron inlet and an electron collector opposite the electron inlet, wherein the electron collector and the electron inlet are arranged to direct the accelerated electron beam from the electron source through the electron inlet and along a path transverse to a path between the sample inlet and the ion outlet of the chamber.

US Pat. No. 10,658,166

SPECTROMETRIC ANALYSIS

Micromass UK Limited, Wi...

1. A method of spectrometric analysis comprising:obtaining one or more background reference sample spectra for one or more samples;
deriving one or more background noise profiles for the one or more background reference sample spectra, wherein the one or more background noise profiles comprise one or more background noise profiles for each class of one or more classes of sample; and
storing the one or more background noise profiles in electronic storage for use when pre-processing and analysing one or more sample spectra obtained from a different sample to the one or more samples.

US Pat. No. 10,658,165

ISOTOPIC PATTERN RECOGNITION

Thermo Fisher Scientific ...

1. A method of mass spectrometry analysis, comprising:(a) calculating, for a selected element of interest, an exact mass difference between a principal isotope and a heavier first isotope of the selected element;
(b) calculating, using the calculated exact mass differences and for each of one or more charge states of each one of a plurality of ion species comprising the selected element, an expected difference between a mass-to-charge ratio (m/z) of an A0 mass-spectral peak of said each ion species and an m/z of an A1 isotopic variant mass-spectral peak of said each ion species, wherein the difference corresponds to replacement of one atom of the principal isotope of the selected element by an atom of the heavier first isotope of the selected element within said each ion species;
(c) determining a required minimum instrument resolution necessary to resolve the A1 isotopic variant mass-spectral peak from expected interfering peaks corresponding to isotopic variants of other elements within said each ion species;
(d) acquiring chromatographic mass spectrometry data at or above the required minimum instrument resolution for sample ions;
(e) determining a trace of an abundance of the selected element versus time from the chromatographic mass spectrometry data; and
(f) selecting one or more chromatographic peaks in the trace for qualitative and/or quantitative analysis,
wherein abundance values of the trace are derived by combining measured intensities only of identified mass spectral peaks within a plurality of peak groups identified from the analyses, each identified peak group corresponding to a charge state of one of the ion species and comprising at least two identified mass spectral peaks that contribute to the combined measured intensities,
wherein the identified mass spectral peaks of each identified peak group do not include mass spectral peaks that correspond to an isotopic variant of an ion species that differs from the respective monoisotopic ion species only by substitution of one or more isotopic variants of one or more elements other than the selected element, and
wherein the identification of a pair of identified mass spectral peaks of each peak group depends at least on identifying a match between an expected in/z difference, as calculated in step (b), and a measured m/z difference between the mass spectral peaks of said identified pair.

US Pat. No. 10,658,164

THERMIONIC ENERGY CONVERSION WITH RESUPPLY OF HYDROGEN

1. A thermionic energy conversion system comprising:a containment vessel;
an electrically and thermally conductive anode positioned inside the containment vessel;
a cathode comprising substantially diamond and having a non-electron emitting surface and an electron emitting surface, at least a portion of the electron emitting surface positioned inside the containment vessel and separated from the anode by a gap;
a hydrogen source positioned outside the containment vessel and configured to supply hydrogen to the non-electron emitting surface of the cathode whereby hydrogen can be caused to diffuse through the cathode to the electron emitting surface during electron emission;
the gap is configured to sustain a vacuum whereby when hydrogen is supplied by the hydrogen source, an average partial pressure of hydrogen at the non-electron emitting surface of the cathode is greater than an average partial pressure of hydrogen at the electron emitting surface of the cathode, and whereby electrons emitted from the electron emitting surface of the cathode can cross the gap for collection by the anode;
a heat source thermally coupled to the cathode; and
an electric circuit comprising an electrical load, the electric circuit coupled to the anode and cathode so that electrons emitted from the cathode and collected at the anode can be supplied to the electrical load.

US Pat. No. 10,658,163

TANTALUM SPUTTERING TARGET, AND PRODUCTION METHOD THEREFOR

1. A tantalum sputtering target, wherein orientations of crystal grains constituting the tantalum sputtering target observed via an electron backscatter diffraction pattern method in relation to a direction normal to a sputtering surface of the tantalum sputtering target, ND, along a cross section of the tantalum sputtering target perpendicular to the sputtering surface are such that:a total area of areas of crystal grains having a {100} plane oriented in the ND direction observed in the cross section of the tantalum sputtering target has an area ratio of 30% or more relative to a total area of the cross section of the tantalum sputtering target observed; and
A{100}/A{111} is 1.5 or more, where A{100} represents an area ratio of the total area of areas of crystal grains having a {100} plane oriented in the ND direction observed in the cross section of the tantalum sputtering target relative to the total area of the cross section of the tantalum sputtering target observed and A{111} represents an area ratio of a total area of areas of crystal grains having a {111} plane oriented in the ND direction observed in the cross section of the tantalum sputtering target relative to a total area of the cross section of the tantalum sputtering target observed.

US Pat. No. 10,658,162

SEMICONDUCTOR MANUFACTURING APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:a vacuum chamber configured to contain a substrate and a target located opposite to the substrate;
a rotary member having a first surface located on a back side of the target outside the vacuum chamber;
a first magnet provided on the first surface;
a second magnet having a magnetic pole opposite to a magnetic pole of the first magnet and provided on an inner side of the first magnet on the first surface; and
a magnetic body provided between the first magnet and the second magnet and configured to be movable backward and forward in a direction orthogonal to the first surface,
wherein the rotary member has a recess portion containing a portion of the magnetic body,
wherein the magnetic body has a head portion in a disk shape or a cylindrical shape, and
wherein the recess portion is configured to contain the head portion.

US Pat. No. 10,658,161

METHOD AND APPARATUS FOR REDUCING PARTICLE DEFECTS IN PLASMA ETCH CHAMBERS

Applied Materials, Inc., ...

1. A plasma processing method comprising:depositing, with a first plasma process that includes at least a silicon-containing source gas combined with an oxidizing source gas, and wherein no fluorine containing gas is included in the first plasma process, a coating comprising SiOx onto a chamber surface of a chamber, wherein x is greater than zero;
etching a workpiece in the chamber that comprises a conductor with a second plasma process, wherein the second plasma process is different than the first plasma process, wherein the second plasma process is a conductor etching process, and wherein the coating comprising SiOX deposited with the first plasma process is still on the chamber surface of the chamber at the beginning of etching the workpiece and after the completion of etching the workpiece, wherein the conductor is formed over a top surface of the workpiece, and wherein the second plasma process has an etching selectivity of over 10:1 to the SiOx coating relative to the conductor on the workpiece that is intended to be etched;
removing the workpiece from the chamber; and
performing a clean of the chamber surface with a third plasma process after removing the workpiece, wherein the third plasma process comprises a plasma clean utilizing a first process gas including NF3.

US Pat. No. 10,658,160

STAGE AND SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A stage comprising:a plate having a top surface on which a substrate is mounted and a bottom surface;
a plurality of first tubes extending toward different regions of the bottom surface, each of the first tubes having an opening end facing the bottom surface;
a partition wall defining a plurality of spaces, each of spaces surrounding a respective first tube, each of the spaces respectively forming a flow passage through which a heat exchange medium discharged from the respective first tube flows;
a plurality of second tubes connected to the partition wall, each of the second tubes configured to communicate with the respective flow passage; and
a plurality of adjusting mechanisms, each of the adjusting mechanisms provided in the respective flow passage and configured to be deformed depending on a temperature of the heat exchange medium in the respective flow passage to adjust a conductance of the flow passage in accordance with the temperature,
wherein each of the adjusting mechanisms includes:
a first annular plate provided between the first tube and the partition wall to be rotatable about a central axis of the first tube, the first annular plate having a first throughhole formed at a position radially spaced from the central axis by a predetermined distance;
a second annular plate fixed to face the first annular plate, the second annular plate having a second through-hole formed at a position radially spaced from the central axis by the predetermined distance; and
a deformation member configured to be deformed depending on a temperature of the heat exchange medium to rotate the first annular plate about the central axis such that a relative distance between the first through-hole and the second through-hole in a circumferential direction with respect to the central axis varies, wherein at least a part of the deformation member has a bimetal structure in which two plates having different thermal expansion coefficients are bonded.

US Pat. No. 10,658,159

PLASMA REACTOR VESSEL HAVING IMPROVED PLASMA UNIFORMITY COMPRISED OF A FIRST ELECTRODE, A SECOND ELECTRODE OPPOSED TO THE FIRST ELECTRODE, AND A THIRD ELECTRODE BETWEEN A SUBSTRATE CARRIER AND THE SECOND ELECTRODE

INDEOTEC SA, Neuchatel (...

1. Plasma reactor vessel, comprisinga vacuum chamber;
a first electrode in the vacuum chamber;
a second electrode in the vacuum chamber, opposed to the first electrode and spaced from the first electrode;
a means for providing reactive process gases in the vacuum chamber;
a power source electrically connected to one of the first or second electrodes, for applying a main RF voltage to one of the first and second electrodes, the other electrode being grounded;
a substrate carrier comprising an electrically conductive material, the substrate carrier being configured to be in electrical contact with the second electrode and to hold a substrate such that at least the majority of upper and lower surfaces of the substrate are untouched by any part of the plasma reactor and can be exposed to the plasma;
the reactor vessel further comprising a third electrode beneath the substrate carrier and between the substrate carrier and the second electrode, wherein the third electrode is electrically insulated from said second electrode; and
wherein the third electrode and the substrate carrier are arranged such that, when the substrate carrier holds a substrate, a first clearance gap is comprised between the substrate and the third electrode.

US Pat. No. 10,658,158

APERTURE SET FOR MULTI-BEAM

NuFlare Technology, Inc.,...

1. An aperture set for multi-beam comprising:a shaping aperture array in which a plurality of first openings are formed, and which receives irradiation of a charged particle beam discharged from a discharge unit in an area including the plurality of first openings, and forms a multi-beam by allowing part of the charged particle beam to pass through corresponding ones of the plurality of first openings;
a blanking aperture array in which a plurality of second openings are formed, through each of which a beam is passed, corresponding to part of the multi-beam, the plurality of second openings each including a pair of blanking electrodes that perform blanking deflection of a beam, the pair of blanking electrodes being provided oppositely across the second opening; and
an electric field shield plate that is disposed to be opposed to the blanking aperture array and includes a plurality of third openings, through each of which a beam is passed, corresponding to part of the multi-beam,
wherein the electric field shield plate has a substrate, and a high resistance film provided on a surface of the substrate, the surface being opposed to the blanking aperture array, and the high resistance film has a higher electric resistance than an electric resistance of the substrate.

US Pat. No. 10,658,157

EXPOSURE APPARATUS AND EXPOSURE METHOD, LITHOGRAPHY METHOD, AND DEVICE MANUFACTURING METHOD

NIKON CORPORATION, Tokyo...

1. An exposure apparatus that irradiates a plurality of beams of charged particles to expose a target, comprising:a stage that is movable and holds the target;
an irradiation device that has a multibeam optical system which emits the plurality of beams to be irradiated on the target and in which an irradiation state of each of the plurality of beams can be individually set; and
a controller that controls relative movement between the stage and the multibeam optical system, and also adjusts an irradiation position of the plurality of beams with respect to the target, wherein
the irradiation position of the plurality of beams with respect to the target is adjusted by controlling irradiation timing of the plurality of beams based on information concerning change in an irradiation position of a second beam of the plurality of beams, the change occurring based on an irradiation state of at least a first beam of the plurality of beams in accordance with change in a relative position between the stage and the multibeam optical system.

US Pat. No. 10,658,156

SYSTEM AND METHOD FOR IMPROVED SCANNED SPOT BEAM

Applied Materials, Inc., ...

1. A method of scanning a spot beam to achieve a desired implant pattern, comprising:creating a Desired Implant Pattern array based on the desired implant pattern;
scanning the spot beam, using a scanner, in an X-direction at a constant speed;
monitoring beam current as a function of position in the X-direction using a beam profiler;
creating a Linear Uniformity array, where values of elements in the Linear Uniformity array are indicative of beam current at a respective position in the X-direction;
measuring a current profile of the spot beam in the X-direction and a Y-direction, perpendicular to the Y-direction;
creating a Spot Beam Current Profile array, where values of elements in the Spot Beam Current Profile array are indicative of a current of the spot beam at a location in the X-direction and the Y-direction;
using the Linear Uniformity array and the Desired Implant Pattern array to create a Composite Pattern array, where the Composite Pattern array incorporates non-uniformity of the scanned spot beam in the X-direction;
creating a final set of scan profiles to achieve the Composite Pattern array based on the Spot Beam Current Profile array; and
applying the final set of scan profiles to the scanner to achieve the desired implant pattern.

US Pat. No. 10,658,155

PHASE CONTRAST TRANSMISSION ELECTRON MICROSCOPE DEVICE

Inter-University Research...

1. A phase contrast transmission microscope apparatus, comprising:an electron source configured to radiate an electron beam in a propagating direction;
an object lens;
a first condenser lens to focus the electron beam radiated from said electron source, positioned between said electron source and said object lens;
a specimen holder base configured to hold a specimen thereon, positioned between said first condenser lens and said object lens;
an image forming optical system positioned downstream of said object lens in the propagating direction;
an electron beam sensor configured to detect a specimen image that corresponds to a distribution of intensities of the electron beam from the image forming optical system;
a first laser beam irradiating device configured to irradiate a first laser beam, having a direction of an electric field which is parallel with the propagating direction of the electron beam, onto said electron beams beam at a focal plane of said object lens which is downstream from said object lens in the propagating direction; and
a second laser beam irradiating device configured to irradiate a second laser beam, having a direction of an electric field which is parallel with the propagating direction of the electron beam, onto said electron beam at a focal plane of said first condenser lens.

US Pat. No. 10,658,154

SYSTEM AND METHOD FOR PERFORMING NANO BEAM DIFFRACTION ANALYSIS

INTERNATIONAL BUSINESS MA...

1. A system for performing diffraction analysis, comprising:a broad beam ion mill for removing a surface portion from plural parallel sides of a sample to expose an underlying surface of the sample; and
an analyzer for performing diffraction analysis on the underlying surface of the sample.

US Pat. No. 10,658,153

PRECISION SUBSTRATE MATERIAL MULTI-PROCESSING USING MINIATURE-COLUMN CHARGED PARTICLE BEAM ARRAYS

1. A charged particle beam tool, comprising:multiple charged particle beam columns, individual ones of said columns configured to produce an individual charged particle beam, said columns configured to write features to and/or image the substrate;
a shared vacuum space within which said columns are located; and
one or more column controllers storing instructions in a nontransitory medium that, when executed, cause said column controllers to:
control said beams to write multiple previous-layer features on the substrate, control said beams to image said previous-layer features,
calculate beam offsets and/or beam parameters in dependence on said image action, and
control said beams, using said calculated offsets and/or parameters, to write multiple new-layer features on the substrate;
wherein said column controllers are configured to control said columns to perform said previous-layer write action and said new-layer write action differently and independently and without the substrate being transferred out of said shared vacuum space.

US Pat. No. 10,658,152

METHOD FOR CONTROLLING A PARTICLE BEAM DEVICE AND PARTICLE BEAM DEVICE FOR CARRYING OUT THE METHOD

Carl Zeiss Microscopy Gmb...

1. A method for controlling a particle beam device for imaging, analyzing and/or processing an object, comprising:identifying at least one control parameter of a unit of the particle beam device using an eye tracker by tracking at least one eye of a user of the particle beam device;
changing the at least one control parameter of the unit of the particle beam device;
providing a representation using signals of the unit of the particle beam device, the unit of the particle beam device being a detector of the particle beam device; and
identifying the representation using the eye tracker, thereby identifying the at least one control parameter.

US Pat. No. 10,658,151

STAGE DEVICE AND CHARGED PARTICLE BEAM DEVICE

HITACHI HIGH-TECH CORPORA...

1. A stage device, comprising:a chuck that is loaded with a sample;
an XY stage that moves in X and Y directions; and
a Z stage that moves in a Z direction,
wherein the Z stage includes one or more slope mechanisms which each include:
an inclined part that is fixed to the XY stage and includes an inclined surface inclined with respect to an XY plane;
a movement part that opposes to the inclined surface of the inclined part;
a drive motor that is fixed to the XY stage and configured to move the movement part along the inclined surface; and
a guide that is provided only between the movement part and the inclined surface of the inclined part and to guide the movement part along the inclined surface, and
wherein the Z stage further includes a table that is fixed to the movement part and is provided with an upper surface which is parallel to the XY plane.

US Pat. No. 10,658,150

CRYOSTATION SYSTEM

Hitachi High-Technologies...

1. A cryostation system which stores a sample in a cooled state, comprising:a main body for storing the sample; and
a lid unit mounted on the main body,
wherein the main body has an insertion opening from which a sample holder for introducing a sample is inserted from the outside,
wherein the insertion opening is formed at a side surface of the main body,
wherein the main body has an inner wall and an outer wall, having a vacuum space between the inner and outer wall of the main body,
wherein the main body is divided into a first space and a second space, divided by a partition member, and a sample storing unit,
wherein the main body has a sample conveyance mechanism for conveying the sample to the sample holder inserted from the insertion opening while the sample and sample holder remain below the lid unit,
wherein the first space accommodates a first cooling medium for cooling a second cooling medium and the sample,
wherein the second space has, disposed therein, a heating unit for heating the first cooling medium accommodated in the first space,
wherein the sample storing unit contains the second cooling medium for cooling the sample, which second cooling medium may be the same or different from the first cooling medium,
wherein the second cooling medium is not gasified, and
wherein the first cooling medium contacts the sample storing unit in a liquid state, and
the lid unit has, formed therein, a discharge port for discharging a gas generated by the heating of the cooling medium from inside the cryostation system to outside the cryostation system.

US Pat. No. 10,658,149

ION SOURCE HEAD STRUCTURE OF SEMICONDUCTOR ION IMPLANTER

Powerchip Semiconductor M...

1. An ion source head structure of a semiconductor ion implanter, comprising:a filament;
a filament clamp, clamping the filament;
a cathode, presenting a shell shape and having a receiving space, wherein the filament is located in the receiving space;
a cathode clamp, clamping the cathode; and
an insulation assembly, disposed between the filament clamp and the cathode clamp such that the filament clamp is insulated from the cathode clamp, the insulation assembly having a first surface, a second surface opposite to the first surface, and an outer surface between the first surface and the second surface, wherein the first surface of the insulation assembly is in contact with the filament clamp, the second surface of the insulation assembly is in contact with the cathode clamp, and a step difference exists on the outer surface of the insulation assembly.

US Pat. No. 10,658,148

ATTOMICROSCOPY: ATTOSECOND ELECTRON IMAGING AND MICROSCOPY

ARIZONA BOARD OF REGENTS ...

1. A method for generating an electron pulse having an attosecond duration, the method comprising:irradiating an object with an auxiliary femtosecond electron pulse; and
illuminating the object, that has been irradiated with said auxiliary electron pulse, with an optical pulse having a sub-femtosecond duration to cause the object to emit the electron pulse having the attosecond duration.

US Pat. No. 10,658,147

CHARGED PARTICLE BEAM APPARATUS

HITACHI HIGH-TECH SCIENCE...

1. A charged particle beam apparatus which automatically prepares a sample piece from a sample, the charged particle beam apparatus comprising:a charged particle beam irradiation optical system configured to perform irradiation of a charged particle beam;
a sample stage configured to move, the sample being placed on the sample stage;
a sample piece relocation unit configured to hold and transport the sample piece which is separated and picked up from the sample;
a holder fixing stage which holds a sample piece holder to which the sample piece is relocated; and
a computer which performs positional control in relation to a target object based on a template and positional information which is obtained from an image of the target object, the template being generated based on an absorption current image of the target object which is acquired using the irradiation of the charged particle beam.

US Pat. No. 10,658,146

TRANSMISSION TYPE TARGET, TRANSMISSION TYPE TARGET UNIT, XRAY TUBE, X-RAY GENERATING APPARATUS, AND RADIOGRAPHY SYSTEM

Canon Kabushiki Kaisha, ...

1. A transmission type target for an X-ray tube comprising:a diamond substrate including an inner region which contains sp3 bonds and an outer region which contains a higher amount of sp2 bonds than the inner region; and
a target layer located on the diamond substrate and configured to generate an X-ray in response to irradiation with electrons.

US Pat. No. 10,658,145

HIGH BRIGHTNESS X-RAY REFLECTION SOURCE

Sigray, Inc., Concord, C...

1. An x-ray target comprising:a thermally conductive substrate comprising a surface; and
a plurality of structures separate from one another and on or embedded in at least a portion of the surface, the plurality of structures comprising:
a thermally conductive first material in thermal communication with the substrate, the first material having a length along a first direction parallel to the portion of the surface in a range greater than 1 millimeter and a width along a second direction parallel to the portion of the surface and perpendicular to the first direction, the width in a range of 0.2 millimeter to 3 millimeters; and
at least one layer over the first material, the at least one layer comprising at least one second material different from the first material, the at least one layer having a thickness in a range of 2 microns to 50 microns, the at least one second material configured to generate x-rays upon irradiation by electrons having energies in an energy range of 0.5 keV to 160 keV.

US Pat. No. 10,658,144

SHADOWED GRID STRUCTURES FOR ELECTRODES IN VACUUM ELECTRONICS

Modern Electron, LLC, Be...

1. A vacuum electronics device comprising:an electrically conductive substrate having a plurality of pillars patterned therein;
a plurality of grid supports disposed on the plurality of pillars that are defined in the electrically conductive substrate, each of the plurality of grid supports having a first width; and
a plurality of grid lines, each of the plurality of grid lines being supported on an associated one of the plurality of grid supports, each of the plurality of grid lines having a second width that is wider than the first width.

US Pat. No. 10,658,143

METHOD OF MANUFACTURING EMITTER

HITACHI HIGH-TECH SCIENCE...

1. A method of manufacturing a sharpened needle-shaped emitter, the method comprising:performing an electrolytic polishing process of polishing a front end of a conductive emitter material so that a diameter of the front end is gradually reduced toward a tip;
performing a first etching process by irradiating a processing portion of the emitter material processed by the electrolytic polishing process with a charged particle beam to form a pyramid-shaped pointed portion with the tip as an apex;
performing a sputtering process by irradiating the pointed portion formed by the first etching process with a focused ion beam using rare gas as an ionizing gas; and
performing a secondary etching process of further sharpening the tip by an electric field induced gas etching processing while observing a crystal structure of the tip of the pointed portion processed by the sputtering process with a field ion microscope, thereby making a number of atoms constituting the tip to be equal to or less than a predetermined number.

US Pat. No. 10,658,142

SNAP FIT CIRCUIT BREAKER AND LOAD CENTER SYSTEM

Leviton Manufacturing Co....

1. A load center comprising:a base pan having a plurality of circuit breaker spaces, each of the circuit breaker spaces being configured to receive a circuit breaker; and
a plurality of base pan electrical connections disposed within each circuit breaker space, the plurality of base pan electrical connections including line phase, line neutral, load phase, and load neutral electrical connections;
wherein the base pan line phase, line neutral, load phase, and load neutral electrical connections are arranged and configured to mechanically and electrically contact respective line phase, line neutral, load phase, and load neutral electrical connections of the circuit breaker when the circuit breaker is received within the circuit breaker space.

US Pat. No. 10,658,141

ELECTROMAGNETIC RELAY

FUJITSU COMPONENT LIMITED...

1. An electromagnetic relay comprising:an electromagnet;
a movable spring having a movable contact;
a first terminal to which one end of the movable spring is connected;
a second terminal having a fixed contact opposite to the movable contact;
an actuator that rotates by excitation of the electromagnet, rotates the movable spring, and causes the movable contact to come in contact with the fixed contact or to separate from the fixed contact;
a nonmagnetic card to be attached to the actuator;
a plurality of magnetic members that sandwich the movable contact and the fixed contact, and apply a magnetic flux to the movable contact and the fixed contact to extend an arc; and
a permanent magnet attached between the plurality of magnetic members.

US Pat. No. 10,658,140

CONTACT MECHANISM AND ELECTROMAGNETIC RELAY USING THE SAME

Omron Corporation, Kyoto...

1. A contact mechanism comprising:a base;
a pair of fixed contact terminals provided side by side on the base;
a first contact mechanism comprising:
a first fixed contact provided in one of the pair of fixed contact terminals, and
a first movable contact that contactably and separably faces the first fixed contact;
a second contact mechanism comprising:
a second fixed contact provided in another of the pair of fixed contact terminals, and
a second movable contact that contactably and separably faces the second fixed contact; and
a magnetic field generation unit comprising a permanent magnet disposed between the first contact mechanism and the second contact mechanism such that magnetic fields in opposite directions are generated respectively between contacts of the first contact mechanism and between contacts of the second contact mechanism when currents in opposite directions flow in the first contact mechanism and the second contact mechanism,
wherein the magnetic field generation unit is disposed in the base so as to induce arcs generated in the first contact mechanism and the second contact mechanism in directions moving away from the base.

US Pat. No. 10,658,139

INPUT DEVICE AND METHOD FOR CONTROLLING INPUT DEVICE

ALPS ALPINE CO., LTD., T...

1. An input device, comprising:a first part and a second part configured to move relative to each other according to an input operation;
a magnetic viscous fluid whose viscosity changes according to a magnetic field; and
a magnetic-field generator that generates the magnetic field applied to the magnetic viscous fluid, wherein
the second part includes a first surface and a second surface that are arranged in a direction orthogonal to a direction of relative movement between the first part and the second part;
gaps are formed between the first surface and the first part and between the second surface and the first part;
the magnetic viscous fluid is present in at least a part of the gaps;
the second part is configured to rotate relative to the first part; and
the gaps are sandwiched between the first surface and the first part and between the second surface and the first part in a direction along a central axis of rotation between the first part and the second part.

US Pat. No. 10,658,138

LOCKING SYSTEM FOR USE WITH A TRIGGER ASSEMBLY OF AN ELECTRICAL DEVICE

DEFOND ELECTECH CO. LTD.,...

1. A locking system for use with a trigger assembly of an electrical device, said electrical device having:an electrical switch housing with an electrical switch unit disposed therein;
a trigger member configured for movement relative to the housing;
an actuator member operably-connected to the trigger member and, responsive to movement of the trigger member relative to the housing, said actuator member being movable in a first direction relative to the housing from an OFF position in which the electrical switch is operably-opened by the actuator towards an ON position in which the electrical switch is operably-closed by the actuator, and movable in a second direction relative to the housing from the ON position towards the OFF position;
said locking system including:
a lock-on mechanism including a first locking member mounted proximate to the trigger member and a second locking member mounted proximate to the housing, wherein when the actuator member is moved in to the ON position, said first and second locking members are selectably movable relative to each other into at least one of a locked configuration whereby the actuator member is locked in the ON position, and, an unlocked configuration whereby the actuator member is not locked in the ON position;
a lock-off mechanism including a lock-off member disposed on the trigger member, said lock-off member being selectably movable between at least one of a locked-off position in which the lock-off member restricts movement of the trigger member relative to the housing and whereby the actuator member is restricted from being moved from the OFF position in to the ON position, and, a non-locked-off position in which the lock-off member does not restrict movement of the trigger member relative to the housing and whereby the actuator member is not restricted from being moved from the OFF position in to the ON position; and
said lock-off member of the lock-off mechanism being slidably mounted to the trigger member and configured for slidable movement relative to the trigger member along a sliding axis between the locked-off and non-locked-off positions, said sliding axis being substantially parallel to a rotation axis of the first locking member, and wherein said lock-on mechanism and lock-off mechanism are separate and independently operable of each other.

US Pat. No. 10,658,137

KEY STRUCTURE

PRIMAX ELECTRONICS LTD., ...

1. A key structure, comprising:a support shaft comprising an accommodation space and a hollow part, wherein the hollow part is in communication with the accommodation space, wherein the hollow part comprises a first opening and a second opening;
a resilience sheet disposed within the accommodation space, wherein the resilience sheet comprises a resilience part, and a portion of the resilience part is penetrated through the hollow part, wherein the resilience sheet comprises a first resilience arm and a second resilience arm, wherein the resilience arm is penetrated through the first opening, and the second resilience arm is penetrated through the second opening;
a pedestal comprising a sliding groove and a push part, wherein the support shaft is movable within the sliding groove, the push part is disposed on an inner surface of the sliding groove, and the push part is aligned with the resilience part; and
a keycap combined with the support shaft,
wherein when an external force is applied to the keycap, the resilience part is pushed by the push part and subjected to deformation, wherein after the resilience part is moved across the push part, the resilience part is elastically restored and swung, so that the resilience part collides with the inner surface of the sliding groove to generate a click sound.

US Pat. No. 10,658,136

BUTTON STRUCTURE AND ELECTRONIC DEVICE USING SAME

Chiun Mai Communication S...

1. A button structure, comprising:a button; and
a fixing portion comprising:
a first latching portion; and
a second latching portion;
wherein the fixing portion is configured for securing the button, and the first latching portion comprises a first latching opening, and the second latching portion comprises a second latching opening, and the first latching opening has an opening direction substantially perpendicular to an opening direction of the second latching opening, and the first latching opening and the second latching opening are engaged with the button;
wherein the button comprises a key portion and two tongues, the two tongues protrude from the key portion, and the first latching opening is engaged with one said tongue, and the second latching opening is engaged with the other said tongue;
wherein each said tongue is a cylindrical structure defining a first groove and a second groove, the first groove and the second groove of each said tongue are coaxially defined around a peripheral surface of the tongue, the first groove and the second groove are spaced apart from each other, the first grooves of the two tongues are configured for respectively receiving the first latching opening and the second latching opening, and the second groove of each said tongue is configured for receiving a sealing element.

US Pat. No. 10,658,135

KEYBOARD KEY STRUCTURE THAT GENERATES AN OPERATION SOUND

PRIMAX ELECTRONICS LTD., ...

1. A key structure, comprising:a sleeve comprising a sliding groove and a stopping structure, wherein the stopping structure is disposed within the sliding groove;
a plunger-type support shaft, wherein a first end of the plunger-type support shaft is inserted into the sliding groove, and the plunger-type support shaft is movable upwardly or downwardly relative to the sliding groove;
a keycap connected with a second end of the plunger-type support shaft; and
a resilience element disposed on the plunger-type support shaft and movable with the plunger-type support shaft, wherein the resilience element comprises a first end part, a second end part and a swinging part, and the swinging part is arranged between the first end part and the second end part, wherein the first end part and the second end part are fixed on the plunger-type support shaft, wherein while the plunger-type support shaft is moved upwardly or downwardly relative to the sliding groove, the swinging part interferes with the stopping structure, so that the swinging part is swung,
wherein while the plunger-type support shaft is moved upwardly or downwardly relative to the sliding groove, the resilience element and the stopping structure interfere with each other, so that the key structure generates an operating sound.

US Pat. No. 10,658,134

KEYBOARD

Chicony Electronics Co., ...

1. A keyboard, comprising:a bottom plate; and
a plurality of keyswitch devices each comprising:
a keycap over the bottom plate;
a first supporting member connected between the bottom plate and the keycap and comprising a first magnetic attraction portion, the first magnetic attraction portion having a first abutting surface; and
a second supporting member connected between the bottom plate and the keycap and comprising a second magnetic attraction portion configured to attract the first magnetic attraction portion, the second magnetic attraction portion having a second abutting surface,
wherein when the first abutting surface abuts against the second abutting surface, the keycap is at a highest position relative to the bottom plate, and when the keycap moves toward the bottom plate from the highest position, the first abutting surface is at least partially separated from the second abutting surface.

US Pat. No. 10,658,133

CONTROL DEVICE OF PUSH-BUTTON TYPE WITH FLAT ARCHITECTURE

Schneider Electric Indust...

1. A device of push-button type comprising:a body comprising a casing comprising a receptacle and a cover plate fixed on the receptacle;
an actuating button that is actuatable in translation along a main axis with respect to the body between at least two positions, a rest position and a pushed-in position, the cover plate being arranged at a periphery of the actuating button;
guiding means for guiding the actuating button in translation between the two positions thereof; and
return means for returning the actuating button from the pushed-in position toward the rest position, wherein:
the guiding means comprise at least a pin comprising a bent rod shaped to have a first part pivotally mounted on a fastening unit of the actuating button, at least a second part pivotally mounted on a fastening unit of the cover plate, and a free end,
an axis of the first part of the pin and an axis of the second part of the pin are oriented along a first plane,
an axis of the free end of the pin is oriented along a second plane that is inclined with respect to the first plane, and
the return means are rigidly connected to the body and designed to act on the pin by mechanical or magnetic effect.

US Pat. No. 10,658,132

SWITCHING DEVICE

ABB Schweiz AG, Baden (C...

1. A switching device for low or medium voltage electric power distribution networks, said switching device comprising one or more electric poles, each electric pole comprising:an insulating housing extending along a longitudinal axis and having, along said longitudinal axis, a bottom end, at which said housing is fixed to a main support structure of said switching device, and a top end opposite to said bottom end;
a first pole terminal and a second pole terminal electrically connectable with a corresponding phase conductor of an electric power source and with a corresponding load conductor of an electric load, respectively;
a movable contact and a fixed contact, which are coupleable or decoupleable one with or from another, said fixed contact being electrically connected with said first pole terminal, said movable contact being electrically connectable with said second pole terminal;
a stack of semiconductor devices adapted to switch in a conduction state or in an interdiction state depending on the voltage provided thereto, said semiconductor devices being electrically connected in series one to another in such a way that a current can flow according to a predefined conduction direction when said semiconductor devices are in a conduction state, said stack of semiconductor devices including first and second stack terminals electrically connected with said semiconductor devices, said first stack terminal being electrically connected with said fixed contact, said first and second stack terminals being electrically coupleable with or decoupleable from said movable contact when said movable contact reaches different positions during a movement towards or away from said fixed contact, said semiconductor devices and said fixed contact being arranged at the top end of said insulating housing, respectively in a proximal position and in a distal position relative to the top end of said insulating housing.

US Pat. No. 10,658,131

REMOTE-CONTROL DEVICE COMPRISING A PORTABLE REMOTE CONTROL AND A WALL MOUNTING

SOMFY ACTIVITES SA, Clus...

1. A remote-control device comprising a portable remote control and a wall mounting, the portable remote control comprising a housing having a rear surface and a front surface, located on either side of and at a distance from a median plane (M) of the housing, the housing including a recess open at least on the rear surface, the wall mounting having a surface for bearing against a wall along a bearing plane (P) and a head projecting from the bearing plane (P), the head penetrating into the recess in an anchoring position of the portable remote control so as to pass through the median plane (M) of the housing, characterized in that the recess is shaped so as to match the shape of the head, in that the head projects in an upward oblique direction (D) relative to the bearing plane (P), and has at least one first oblique surface, which, in the anchoring position, is in surface contact with at least one first oblique wall of the recess.

US Pat. No. 10,658,130

ELECTROMECHANICAL ACTUATION SYSTEM FOR MOMENTARY CONTACT CONTROL SWITCHES

Schweitzer Engineering La...

1. An electronic actuation system for a switch, comprising:a shaft configured to rotate between a first rotational position and a second rotational position, wherein each of the first and second rotational positions of the shaft correspond to unique mechanical states of the switch;
a manually operable handle coupled to the shaft to allow for manual rotation of the shaft between the first rotational position and the second rotational position;
a first rotary arm that, when rotated, causes the shaft to rotate from the first rotational position to the second rotational position;
a pull arm selectively engageable with the first rotary arm;
a push arm moveable between a first push position that engages the pull arm with the first rotary arm and a second push position that disengages the pull arm from the first rotary arm;
an auxiliary solenoid electronically actuatable to move the push arm between the first push position and the second push position; and
a master solenoid electronically actuatable to move the pull arm between an unactuated position and an actuated position,
wherein, when the pull arm is electronically actuated to move to the actuated position and the pull arm is engaged, the pull arm causes the first rotary arm to rotate, which rotates the shaft from the first rotational position to the second rotational position.

US Pat. No. 10,658,129

DEVICE FOR CONTROLLING THE CONTACTS OF AN ELECTRICAL SWITCH

Schneider Electric Indust...

1. A portable control device designed to control contacts of an electrical switch, the control device comprising a main drive shaft, a holding shaft, a motor for driving the main shaft and a microcontroller for controlling the motor, wherein the control device is designed such that:in a first direction of insertion, the main shaft is able to be inserted into a first manoeuvring recess of the switch in order to perform a movement for opening/closing the contacts of the switch, the holding shaft then being housed in a first holding orifice,
in a second direction of insertion, the main shaft is able to be inserted into a second manoeuvring recess of the switch in order to be able to perform a movement for grounding the contacts of the switch, the holding shaft then being housed in a second holding orifice,
wherein the control device includes a detector of the direction of insertion of the control device into the switch, the detector of the direction of insertion being linked to the microcontroller.

US Pat. No. 10,658,128

ELECTRIC DOUBLE-LAYER DEVICE

Nesscap Co., Ltd., Gyeon...

1. An electric double layer device comprising:an electrode unit;
a first terminal and a second terminal outwardly extending from the electrode unit;
a case accommodating the electrode unit; and
a closure covering the case and having first and second through holes through which the first and second terminals respectively pass to be exposed to the environment, the closure comprising:
a lower surface and an upper surface opposing each other, wherein the lower surface faces the electrode unit;
a first pocket disposed along the upper surface and surrounding the first through hole;
a second pocket disposed along the upper surface and surrounding the second through hole; and
a urethane resin filling in the first pocket and the second pocket,
wherein the electric double layer device further comprises a volume protrusion protruding upwardly from the upper surface of the closure and at least partially surrounding the first and second pockets, wherein the first and second pockets are lower in position than the volume protrusion, and wherein the volume protrusion has a concave portion on a top surface thereof, a height of which gradually decreases toward a center thereof, the concave portion being configured to become flat when the case is beaded.

US Pat. No. 10,658,127

NONAQUEOUS ELECTROLYTE FOR AN ULTRACAPACITOR

AVX Corporation, Fountai...

1. An ultracapacitor comprising:a first electrode that comprises a first current collector electrically coupled to a first carbonaceous coating comprising activated carbon particles, a water-insoluble organic binder, and a water-soluble organic binder, wherein the combined weight percentage of the water-insoluble organic binder and the water-soluble organic binder in the first carbonaceous coating is less than 10 wt. %;
a second electrode that comprises a second current collector electrically coupled to a second carbonaceous coating comprising activated carbon particles, a water-insoluble organic binder, and a water-soluble organic binder, wherein the combined weight percentage of the water-insoluble organic binder and the water-soluble organic binder in the second carbonaceous coating is less than 10 wt. %,
wherein the activated carbon particles of the first carbonaceous coating, the second carbonaceous coating, or both have a total pore volume of from 0.2 cm3/g to 1.5 cm3/g and a median pore width of about 8 nanometers or less;
wherein the activated carbon particles of the first carbonaceous coating, the second carbonaceous coating, or both contain a plurality of pores, wherein the amount of pores having a size of about 2 nanometers or less is about 50 vol. % or less of the total pore volume, the amount of pores having a size of from about 2 nanometers to about 50 nanometers is about 20 vol. % to about 80 vol. % of the total pore volume, and the amount of pores having a size of about 50 nanometers or more is from about 1 vol. % to about 50 vol. % of the total pore volume;
wherein the first current collector and the second current collector each contain a substrate that includes a conductive metal, and the substrate of the first current collector, the substrate of the second current collector, or both has a thickness of about 200 micrometers or less;
a separator positioned between the first electrode and the second electrode;
a nonaqueous electrolyte that is in ionic contact with the first electrode and the second electrode, wherein the nonaqueous electrolyte contains an ionic liquid that is dissolved in a nonaqueous solvent at a concentration of 1.0 mole per liter or more, wherein the nonaqueous solvent has a boiling temperature of about 150° C. or more; and
a housing within which the first electrode, the second electrode, the separator, and the electrolyte are retained, wherein the housing contains a metal container,
wherein the capacitor exhibits an equivalence series resistance of about 150 mohms or less as determined at a temperature of 23° C., frequency of 100 kHz, and without an applied voltage.

US Pat. No. 10,658,125

ELECTROCHEMICAL DEVICE AND METHOD OF MANUFACTURING ELECTROCHEMICAL DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electrochemical device comprising:a negative electrode which is a metal foil constituted by a negative electrode collector having a first principal face and a second principal face on an opposite side of the first principal face, and also by negative electrode active material layers formed on the first principal face and second principal face;
wherein the negative electrode active material layers include a first negative active material layer and a second negative active material layer;
a positive electrode which is a metal foil constituted by a positive electrode collector having a third principal face and a fourth principal face on an opposite side of the third principal face, and also by positive electrode active material layers formed on the third principal face and fourth principal face;
separators that insulate the positive electrode and negative electrode; and
electrolytic solution that immerses the positive electrode, negative electrode and separators;
where the positive electrode, negative electrode, and separators are stacked and wound in such a way that the first principal face and third principal face are on an inner side of winding, and the second principal face and fourth principal face are on an outer side of winding, with the separators separating the positive electrode and negative electrode; wherein:
the first principal face of the negative electrode collector faces toward the fourth principal face of the positive electrode collector via the separator; and
the second principal face of the negative electrode collector has:
a first region facing toward the third principal face of the positive electrode collector via the separator, and
a second region, other than the first region, on an outermost side of winding and not facing toward the third principal face of the positive electrode collector, wherein the second region includes a first uncoated region where the negative electrode active material layers are not formed, and the first uncoated region has a metal lithium joined thereto and is immersed in the electrolytic solution to pre-dope lithium ions into the negative-electrode active layer,
wherein the negative electrode includes the first negative electrode active material layer formed in the first region, as well as the second negative electrode active material layer formed in the second region at an end of the negative electrode collector away from the first negative electrode active material layer; and
the first uncoated region is provided between the first negative electrode active material layer and the second negative electrode active material layer.

US Pat. No. 10,658,124

ELECTROCHEMICAL DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electrochemical device, comprising:a winding structure having;
a negative electrode having a negative-electrode collector, and a negative-electrode active material layer provided on a principle face of the negative-electrode collector;
a positive electrode having a positive-electrode collector, and a positive-electrode active material layer provided on a principle face of the positive-electrode collector; and
separators insulating the negative electrode and the positive electrode;
wherein, the negative electrode, the positive electrode, and the separators are stacked and wound together, with the negative electrode and the positive electrode separated by the separators;
a negative-electrode terminal which is electrically connected to the negative-electrode collector, extends in the winding structure along a center axis of winding of the winding structure, and projects from the winding structure;
a positive-electrode terminal which is electrically connected to the positive-electrode collector, extends in the winding structure along the center axis of winding, projects from the winding structure, and is separated from the negative-electrode terminal by a first distance which is defined as a distance in a straight line between a center of the positive-electrode terminal and a center of the negative-electrode terminal;
a first protective tape covering the negative-electrode terminal and the negative-electrode active material layer;
a second protective tape covering the positive-electrode terminal and the positive-electrode active material layer;
a lithium ion supply source being placed along a winding direction of the winding structure solely at a position further away from the central axis than are positions of the negative-electrode terminal and the positive-electrode terminal as viewed in a direction of the central axis, said lithium ion supply source being sole lithium ion supply source contained in the electrochemical device; and
electrolyte immersing the positive electrode, the negative electrode, the lithium ion supply source, and the separators;
wherein, a width corresponding to the sum of a first width (W1) of the first protective tape along a winding direction of the winding structure, and a second width (W2) of the second protective tape along the winding direction, is smaller than a value obtained by multiplying the first distance (D) by pi (?).

US Pat. No. 10,658,123

MULTI-ANODE SOLID ELECTROLYTIC CAPACITOR ASSEMBLY

AVX Corporation, Fountai...

1. A capacitor assembly comprising:a housing that defines an interior cavity having a gaseous atmosphere that contains an inert gas;
multiple capacitor elements comprising at least a first capacitor element juxtaposed adjacent to a second capacitor element positioned in the interior cavity, wherein each of the capacitor elements has a front surface and a major surface, wherein the front surfaces of the multiple capacitor elements are all generally coplanar, wherein the major surfaces of the multiple capacitor elements are in a horizontal configuration and are generally coplanar, each of the capacitor elements comprising an anode formed from an anodically oxidized, sintered porous body and a solid electrolyte overlying the anode, wherein each capacitor element further comprises an anode lead that extends in a lateral direction from the front surface, wherein the anode lead is positioned within the interior cavity of the housing, and wherein the capacitor elements occupy about 30 vol. % to about 97 vol. % of the interior cavity of the housing;
an anode termination that is in electrical connection with the anode lead of each of the capacitor elements;
a cathode termination that is in electrical connection with the solid electrolyte of each of the capacitor elements.

US Pat. No. 10,658,122

CAPACITOR PACKAGE STRUCTURE WITH FUNCTIONAL COATING AND METHOD FOR MANUFACTURING THE SAME

APAQ TECHNOLOGY CO., LTD....

1. A method for manufacturing a capacitor package structure having a functional coating, comprising:a preparing step including preparing a surface treating solution including a silane coupling agent and a solvent, wherein the silane coupling agent has a general formula of Y(CH2)nSiX3, wherein n is an integer of 0 to 3, X is same or different substituent selected from the group consisting of: chloride, methoxy group, ethoxy group, methoxyethoxy group and acetoxy group, and Y is a vinyl group, an amino group, an epoxy group, a methacryloyloxy group, a thiol group, a uramino group or an isobutyl group;
a first coating step including coating the surface treating solution onto a capacitor element, wherein the surface treating solution is disposed on a surface of the capacitor element and a part of the surface treating solution enters a plurality of voids of the capacitor element;
a first drying step including drying the surface treating solution for forming the functional coating;
a second coating step including coating a conductive dispersion onto the functional coating; wherein the conductive dispersion includes a polymer composite material; the polymer composite material is PEDOT:PSS composite having a surface modified by carbon nano material; and the polymer composite material has a D50 average particle size ranging from 1 to 25 nanometers; and
a second drying step including drying the conductive dispersion for forming a conductive polymer layer, wherein a conductive polymer in the conductive polymer layer is connected to the surface of the capacitor element through the silane coupling agent in the functional coating.

US Pat. No. 10,658,121

PROCESS FOR FORMING A SOLID ELECTROLYTIC CAPACITOR

KEMET Electronics Corpora...

1. A process for forming a solid electrolyte capacitor comprising:providing an anodized anode; and
forming a conductive polymer layer on said anodized anode wherein said conductive polymer layer comprises first particles comprising conductive polymer and polyanion and second particles comprising said conductive polymer and said polyanion wherein said first particles have an average particle diameter of at least 1 micron to no more than 10 microns and said second particles have an average particle diameter of at least 1 nm to no more than 600 nm.

US Pat. No. 10,658,120

SOLID ELECTROLYTIC CAPACITOR

TOKIN CORPORATION, Senda...

1. A solid electrolytic capacitor comprising a capacitor element, an anode terminal, a cathode terminal, an ion trapping member and an external insulation member, wherein:the capacitor element comprises an anode body, an anode lead wire extending outward from inside the anode body, a dielectric layer and a cathode layer including a solid electrolytic layer;
the dielectric layer is positioned between the anode body and the solid electrolytic layer;
the anode lead wire has a lead out portion protruding outward from the anode body;
the lead out portion is covered with the dielectric layer at least in part;
the solid electrolytic layer has an edge portion near a root of the lead out portion;
the anode terminal is connected to the lead out portion at a position away from the root;
the cathode terminal is connected to the cathode layer;
the ion trapping member comprises a first resin and an ion trapping agent dispersed in the first resin;
the ion trapping member covers a whole periphery of at least a part of the lead out portion directly or via the dielectric layer between the edge portion of the solid electrolytic layer and the anode terminal;
part of the ion trapping member directly contacts the lead out portion;
the external insulation member comprises a second resin which has a high affinity for the first resin; and
the external insulating member envelops the capacitor element and covers at least a part of the ion trapping member, a part of the anode terminal and a part of the cathode terminal.

US Pat. No. 10,658,119

MULTIELECTRODE POWER CAPACITOR WITH REDUCE NOISE VIBRATION

ABB Schweiz AG, Baden (C...

1. A power capacitor comprising:a casing,
a first bushing,
a second bushing or an earthing stud having the same electric potential as the casing,
wherein the first bushing and the second bushing extend through the casing,
a dielectric liquid, and
a plurality of wound capacitor elements, each wound capacitor element including:
a first electrode having two first layers of electrically conducting material connected to the first bushing, the two first layers being arranged movable towards and from each other,
a second electrode having two second layers of electrically conducting material connected to the second bushing or to the earthing stud, the two second layers being arranged movable towards and from each other, and
a dielectric layer arranged between the first electrode and the second electrode,
wherein the two first layers, the two second layers and the dielectric layer are together wound in a plurality of turns to obtain a plurality of layers of the first electrode of the second electrodes and of the dielectric layer,
wherein the wound capacitor elements are arranged in a stacked manner in the casing, adjacent wound capacitor elements being in direct contact with each other, wherein the capacitor elements are submerged in the dielectric liquid.

US Pat. No. 10,658,118

ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component, comprising:a capacitor body;
first and second external electrodes disposed, and spaced apart from each other, on a mounting surface of the capacitor body;
first and second, connection terminals respectively connected to the first and second external electrodes, the first and second connection terminals including first and second cutouts, respectively;
a first plating layer covering the first external electrode and the first connection terminal; and a second plating layer covering the second external electrode and the second connection terminal.

US Pat. No. 10,658,117

MULTILAYER CAPACITOR HAVING EXTERNAL ELECTRODE INCLUDING CONDUCTIVE RESIN LAYER

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a body including dielectric layers and internal electrodes; and
an external electrode disposed on one surface of the body, respectively,
wherein the external electrode includes:
a first electrode layer disposed on the one surface of the body and contacting the internal electrodes; and
a conductive resin layer disposed on the first electrode layer and including a plurality of metal particles, a conductive connecting part surrounding the plurality of metal particles, a base resin, and an intermetallic compound contacting the first electrode layer and the conductive connecting part;
the metal particles of the conductive resin layer are composed of at least one material selected from a group consisting of copper, nickel, silver, copper coated with silver, and copper coated with tin,
the intermetallic compound is composed of copper-tin,
the body includes first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other,
the internal electrodes are alternately exposed from the third and fourth surfaces of the body,
the first electrode layers are disposed on the third and fourth surfaces of the body to be connected to exposed portions of the internal electrodes, respectively,
the external electrodes include connection parts disposed on the third and fourth surfaces of the body and band parts extended from the connection parts to portions of the first and second surfaces of the body, respectively, and
t2/t1?0.05 and t3/t1?0.5, in which t1 is a thickness of a central portion of the connection part, t2 is a thickness of a corner portion, and t3 is a thickness of a central portion of the band part.

US Pat. No. 10,658,116

MULTILAYER CAPACITOR HAVING EXTERNAL ELECTRODE INCLUDING CONDUCTIVE RESIN LAYER

SAMSUNG ELECTRO-MECHANICS...

1. A method of manufacturing a multilayer capacitor, comprising:preparing a body including dielectric layers and internal electrodes;
forming a first electrode layer by applying a paste including a conductive metal and glass to one surface of the body to be electrically connected to one end of the internal electrodes and then firing the paste;
applying a conductive resin composite to the first electrode layer, the conductive resin composite including metal particles, a thermosetting resin, and a low-melting-point metal having a melting point lower than a hardening temperature of the thermosetting resin;
forming a conductive resin layer so that a melted low-melting-point metal becomes a conductive connecting part surrounding the metal particles and an intermetallic compound is formed between the first electrode layer and the conducive connecting part by hardening the conductive resin composite; and
forming a second electrode layer on the conductive resin layer by plating,
wherein the first electrode layer includes copper,
the metal particles of the conductive resin layer are formed of at least one selected from the group consisting of copper, nickel, silver, copper coated with silver, and copper coated with tin,
the intermetallic compound is formed of copper-tin,
low-melting-point metal particles included in the thermosetting resin are composed of Sn—Bi, and a content (x) of Sn in Snx—Biy is 10 wt % or more with respect to a total content of metal,
the forming of the conductive resin layer includes:
removing oxide films from surfaces of metal particles and the low-melting-point metal particles included in the thermosetting resin; and
forming the conductive connecting part by a reaction between the metal particles from which the oxide films are removed and the low-melting-point metal particles from which the oxide films are removed and forming the intermetallic compound contacting the first electrode layer by allowing the low-melting-point metal particles having flowability to flow into the surroundings of the first electrode layer, and
after removing the oxide films, a content of carbon in the low-melting-point metal particles formed of Sn—Bi is 0.5% to 1.0%.

US Pat. No. 10,658,115

CAPACITOR COMPONENT AND METHOD FOR MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body including a dielectric layer and first and second internal electrodes opposing each other with the dielectric layer interposed therebetween, and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; and
first and second external electrodes disposed on an outer side of the body and electrically connected to the first and second internal electrodes, respectively,
wherein the body includes a capacitance forming portion including the first and second internal electrodes opposing each other with the dielectric layer interposed therebetween to form capacitance, cover portions disposed in upper and lower surfaces of the capacitance forming portion and including a plurality of pores, and margin portions disposed on side surfaces of the capacitance forming portion, and
80% or higher of the plurality of pores are filled with glass, wherein a diameter of each of the plurality of pores is in the range of 1-2 ?m.

US Pat. No. 10,658,114

CERAMIC CAPACITOR HAVING METAL OXIDE IN SIDE MARGIN PORTIONS, AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. A multilayer ceramic capacitor comprising:a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces opposing each other and connecting the first and second surfaces to each other, and fifth and sixth surfaces opposing each other and connected to the first to fourth surfaces;
a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one end exposed to the third or fourth surface; and
a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body,
wherein a metal oxide including nickel (Ni) and magnesium (Mg) is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal oxide to a thickness of each of the dielectric layers is 0.8 or less.

US Pat. No. 10,658,113

CERAMIC DIELECTRIC AND CERAMIC ELECTRONIC COMPONENT AND DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A ceramic dielectric comprisinga composite comprising a first dielectric and a second dielectric,
wherein each of the first dielectric and the second dielectric comprises strontium and niobium and has a different crystal system.

US Pat. No. 10,658,112

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

Samsung Electro-Mechanics...

1. A multilayer capacitor, comprising:a capacitor body including a first internal electrode and a second internal electrode disposed alternately in a width direction, and further including a dielectric layer interposed therebetween;
first and second external electrodes spaced apart from each other on a mounting surface of the capacitor body; and
a first insulating layer disposed between the first and second external electrodes on the mounting surface of the capacitor body,
wherein the first internal electrode includes a first body portion, a first lead portion extending from the first body portion toward the mounting surface of the capacitor body to be electrically connected to the first external electrode, and a second lead portion extending from the first body portion toward a surface of the capacitor body opposing the mounting surface,
the second internal electrode includes a second body portion overlapping the first body portion in the width direction, a third lead portion partially overlapping the first lead portion in the width direction and extending from the second body portion toward the mounting surface of the capacitor body to be electrically connected to the second external electrode, and a fourth lead portion extending from the second body portion toward the surface of the capacitor body opposing the mounting surface, and
the first and second lead portions extend from the first body portion in a first diagonal direction opposite to each other with respect to a center of the first body portion, and the third and fourth lead portions extend from the second body portion in a second diagonal direction opposite to each other with respect to a center of the second body portion.

US Pat. No. 10,658,110

CAPACITIVE BLOCK INCLUDING A HEAT SINK

Valeo Siemens eAutomotive...

1. A capacitive block, notably for an electrical equipment, comprising:a case,
a capacitive element housed in the case,
a substance filling the space between the case and the capacitive element so as to ensure leak tightness of the capacitive element,
a heat sink against which the capacitive element is in direct contact,capacitive block in which the heat sink is different from the filling substance,a face of said heat sink, designated free face, forming an outer face of the capacitive block and being devoid of said filling substance.

US Pat. No. 10,658,109

SYSTEM AND METHOD FOR ELECTROMAGNET COIL CONSTRUCTION AND OPERATION

SYNAPTIVE MEDICAL (BARBAD...

1. A method of manufacturing electromagnet coils for use in a magnetic resonance imaging (MM) system, the method comprising:forming a coil representation of a coil surface for the electromagnet coils;
setting a plurality of performance metric requirements for a plurality of performance metrics for the electromagnet coils, the plurality of performance metrics including a magnetic field-shape metric and an eddy-field metric;
forming a performance functional, based on the coil representation and the plurality of performance metrics, for generating a current density pattern over the coil surface;
optimizing the performance functional based on the plurality of performance metric requirements;
generating a current density pattern over the coil surface based on the minimized performance functional;
obtaining coil windings from the current density pattern;
wherein the MM system further comprises correction coils;
wherein the eddy-field metric is a predetermined eddy field shape;
wherein optimizing the performance functional further comprises constraining an eddy current density representation over an eddy-field producing structure surface such that eddy fields predicted by the eddy-current density representation conform to said predetermined eddy field shape; and
obtaining further coil windings for said correction coils from said eddy-current density representation thereby enabling the correction coils to compensate for said eddy fields.

US Pat. No. 10,658,108

METHOD FOR PRODUCING R-T-B BASED SINTERED MAGNET

HITACHI METALS, LTD., To...

1. A method for producing an R-T-B based sintered magnet comprising:a step of preparing an R-T-B based sintered magnet material, which is represented by the following formula (1):
uRwBxGayCuzAlqM(100-u-w-x-y-z-q)T  (1)
where
R is composed of light rare-earth element(s) RL and a heavy rare-earth element(s) RH, RL is Nd and/or Pr, RH is at least one of Dy, Tb, Gd and Ho, T is a transition metal element and includes Fe, M is Nb and/or Zr, and u, w, x, y, z, q, and 100-u-w-x-y-z-q are expressed in terms of % by mass;
the RH accounts for 5% by mass or less of the R-T-B based sintered magnet, the following inequality expressions (2) to (5) and (12) being satisfied:
0.20?x?0.70  (2)
0.07?y?0.2  (3)
0.05?z?0.5  (4)
0?q?0.1  (5)
0.844?w ?0.93  (13)
v=u?(6?+10?+8?), where the amount of oxygen (% by mass) of the R-T-B based sintered magnet is ?, the amount of nitrogen (% by mass) is ?, and the amount of carbon (% by mass) is ?;
when 0.40?x?0.70, v and w satisfy the following inequality expressions (6) and (7):
50w?18.5?v?50w?14  (6)
?12.5w+38.75?v??62.5w+86.125  (7)
and, when 0.20?x?0.40, v and w satisfy the following inequality expressions (8) and (9), and x satisfies the following inequality expression (10):
50w?18.5?v?50w?15.5  (8)
?12.5w+39.125?v??62.5w+86.125  (9)
?(62.5w+v?81.625)/15+0.5x?x ?(62.5w+v?81.625)/15+0.8  (10).
wherein in the step of preparing the R-T-B based sintered magnet material , R-T-B based sintered magnet material is obtained by sintering;
a high-temperature heat treatment step of heating the R-T-B based sintered magnet material to a temperature of 730° C. or higher and 1,020° C. or lower, and then cooling to 300° C. at a cooling rate of 25° C./min or more; and
a low-temperature heat treatment step of heating the R-T-B based sintered magnet material, after the high-temperature heat treatment step, to a temperature of 440° C. or higher and 550° C. or lower;
wherein Hcj of the R-T-B based sintered magnet satisfies the following expression:
Hcj (kA/m) ?1,360 +160 [Dy]+240[Tb], where the amount of Dy (% by mass) is [Dy]) and the amount of Tb (% by mass) is [Tb]).

US Pat. No. 10,658,107

METHOD OF MANUFACTURING PERMANENT MAGNET

Senju Metal Industry Co.,...

1. A method of manufacturing a permanent magnet, the method comprising the steps of:positioning a permeating material including Nd-based metal particles and a flux containing a thixotropic agent on a surface of a magnet;
positioning the magnet on which the permeating material is positioned within a furnace that is drawn to vacuum or filled with inert gas;
heating the magnet positioned in the furnace at a first temperature to form reticulated carbon by the flux, and
melting the metal particles in the permeating material by heating the magnet positioned in the furnace at a second temperature which is higher than the first temperature to permeate the melted metal particles into the magnet through the reticulated carbon.

US Pat. No. 10,658,106

STATIONARY INDUCTION ELECTRICAL APPARATUS

Hitachi, Ltd., Tokyo (JP...

1. A stationary induction electrical apparatus comprising:an iron core including a left leg, a middle leg, a right leg and a yoke portion magnetically coupling the left leg, the middle leg, and the right leg, wherein the left leg, the middle leg and the right leg are formed by stacking steel sheets made of a magnetic material and are aligned along a first axis with the middle leg located between the left leg and right leg;
one or more first windings that are wound around the left leg;
one or more second windings that are wound around the middle leg;
one or more third windings that are wound around the right leg;
a first magnetic shunt located at upper and lower ends of the one or more first windings on the left leg, wherein the first magnetic shunt includes a first radial gap in a circumferential direction of the first magnetic shunt;
a second magnetic shunt located at upper and lower ends of the one or more second windings on the middle leg, wherein the second magnetic shunt includes two second radial gaps in a circumferential direction of the second magnetic shunt; and
a third magnetic shunt located at upper and lower ends of the one or more third windings on the middle leg, wherein the third magnetic shunt includes a third radial gap in a circumferential direction of the third magnetic shunt.

US Pat. No. 10,658,105

REACTOR HAVING IRON CORES AND COILS

FANUC CORPORATION, Yaman...

1. A reactor, comprising:a core body, wherein
the core body comprises an outer peripheral iron core composed of a plurality of outer peripheral iron core portions, at least three iron cores arranged inside the outer peripheral iron core, each of the at least three iron cores are coupled to a respective one of the plurality of outer peripheral iron core portions at a location midway between two ends of the respective one the plurality of outer peripheral iron core portions, and coils which are wound around the at least three iron cores,
the radially inner end of each iron core converges toward the center of the outer peripheral iron core,
gaps are formed between one of the at least three iron cores and another iron core adjacent thereto through which gaps the iron cores are magnetically connectable, a point of intersection of the gaps is positioned in the center of the core body, and the core body is rotationally-symmetrically formed about the center thereof, and
the reactor further comprises a single temperature detection part arranged in the center of the core body at the point of intersection of the gaps.

US Pat. No. 10,658,103

COIL COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A coil component, comprising:a magnetic body of rectangular solid shape, constituted by a metal magnetic material with an oxide material or synthetic resin material;
a coil with N turns, where N is a positive number of 2 or greater, provided inside the magnetic body, which has: a first conductor layer having a first multiple winding part which is wound around one axis with a first spacing in ?m denoted by “g”; a second conductor layer having a second multiple winding part which is wound around the one axis with the first spacing and faces the first conductor layer; and
an inter-layer connection part that inter-connects an inner periphery end of the first multiple winding part and an inner periphery end of the second multiple winding part;
an insulating intermediate part which is provided inside the magnetic body and forms, between the first conductor layer and second conductor layer, wherein a second spacing in ?m denoted by “T” corresponding to a thickness of the insulating intermediate part satisfies T?0.8(g·(N?1)), said insulating intermediate part having an electrical resistance higher than that of the magnetic body and having a thickness of 30 ?m or less, wherein a resistivity of the insulating intermediate part is 108 ?·cm or more, and a resistivity of the magnetic body is 106 ?·cm or more, wherein the insulating intermediate part is constituted by spherical oxide grains of 10 to 500 nm in average grain size; and
external electrodes provided on the magnetic body and connected, respectively, to outer periphery ends of the first and second multiple winding parts.

US Pat. No. 10,658,102

ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF

CYNTEC CO., LTD., Hsinch...

1. An electronic device, comprising:a first magnetic powder;
a second magnetic powder, mixed with the first magnetic powder, wherein the mean particle diameter of the first magnetic powder is larger than the mean particle diameter of the second magnetic powder and the Hardness of the first magnetic powder is greater than the Hardness of the second magnetic powder, for reducing strains of the magnetic powders; and
a conducting wire, buried in the mixture of the first magnetic powder and the second magnetic powder, wherein the conducting wire comprises an insulating encapsulant and a conducting metal encapsulated by the insulating encapsulant;
wherein the mixture of the first magnetic powder and the second magnetic powder and the conducting wire buried therein are combined to form an integral magnetic body, wherein the strains of the magnetic powders are reduced so as to form the integral magnetic body at a temperature lower than the melting point of the insulating encapsulant.

US Pat. No. 10,658,101

TRANSFORMER AND POWER SUPPLY DEVICE INCLUDING THE SAME

SOLUM CO., LTD., Yongin-...

1. A transformer, comprising:a magnetic core;
a first coil unit disposed in the magnetic core and including a laminated board having layers laminated therein and conductive patterns for forming a primary coil, the conductive patterns being disposed on the laminated layers;
a second coil unit including a conductive wire for forming a secondary coil spaced apart from the conductive patterns of the laminated board by an insulating distance; and
a based disposed on a main board,
wherein the base includes a plurality of terminal pins electrically connecting the laminated board and the main board
wherein the laminated board includes a first layer on which a conductive pattern is disposed, a second layer on which a shielding pattern is disposed, and a third layer on which a Vcc pattern for forming an induction current is disposed,
wherein the conductive pattern, the shielding pattern, and the Vcc pattern of the laminated board are disposed around a through hole allowing a middle leg of the magnetic core to be inserted thereinto,
wherein the conductive pattern be laminated to form an inductor pattern having a coil shape, and
wherein the base includes an accommodation portion comprising a seating part having the coil unit seated therein and a side wall protruding from the seating part, wherein the side wall of the accommodation portion has a coil outlet as a passage through which the second coil unit is led out to an external surface of the accommodation portion.

US Pat. No. 10,658,100

COIL UNIT HAVING COOLING APPARATUS

Toyota Jidosha Kabushiki ...

1. A coil unit comprising:a ferrite plate including a coil carrying surface and a rear surface opposite to the coil carrying surface;
a coil arranged on a side of the coil carrying surface of the ferrite plate;
a device arranged on a side of the rear surface of the ferrite plate; and
a cooling apparatus which feeds a coolant between the ferrite plate and the device.

US Pat. No. 10,658,099

MAGNETIC LATCH FOR A DISPLAY MODULE

Daktronics, Inc., Brooki...

1. A display module comprising:a module support structure;
a plurality of light-emitting elements coupled to the module support structure; and
one or more latch assemblies configured to removeably couple the module support structure to a support chassis, wherein each of the one or more latch assemblies comprises;
a first magnet movably coupled to the module support structure at a first location, the first magnet being rotatable relative to the module support structure between a first position and a second position;
a second magnet movably coupled with the module support structure at a second location, the second magnet being rotatable relative to the module support structure between a first corresponding position and a second corresponding position; and
a shaft connecting the first magnet and the second magnet wherein the first magnet, the shaft, and the second magnet are configured to rotate together such that the second magnet is in the first corresponding position when the first magnet is in the first position and is in the second corresponding position when the first magnet is in the second position;
wherein a magnetic attraction between the second magnet and a corresponding third magnet attached to the support chassis is stronger when the second magnet is in the first corresponding than when the second magnet is in the second corresponding position.

US Pat. No. 10,658,098

ELECTRONIC COMPONENT SURFACE-MOUNTABLE ON CIRCUIT BOARD

Taiyo Yuden Co., Ltd., T...

1. An electronic component surface-mountable on a circuit board, comprising:an insulating base member having a mounting surface and first and second end surfaces, the electronic component being surface-mountable on the circuit board such that the mounting surface faces the circuit board, the first and second end surfaces being opposed to each other and connected with each other via the mounting surface;
a coil portion provided in the base member, the coil portion having an axis parallel to the circuit board;
a first external electrode provided on the mounting surface of the base member so as to be electrically connected to the coil portion; and
a second external electrode provided on the mounting surface of the base member so as to be electrically connected to the coil portion,
wherein the first external electrode includes a first electrode portion extending along the mounting surface, the second external electrode includes a second electrode portion extending along the mounting surface,
wherein the first external electrode has a first protrusion, and the second external electrode has a second protrusion,
wherein the first protrusion is configured to protrude away from the first electrode portion and the second protrusion is configured to protrude away from the second electrode portion.

US Pat. No. 10,658,097

METHOD OF MANUFACTURING SUPERPARAMAGNETIC NANOCOMPOSITE AND SUPERPARAMAGNETIC NANOCOMPOSITE MANUFACTURED USING THE SAME

AMOLIFESCIENCE CO., LTD.,...

1. A method of manufacturing a superparamagnetic nanocomposite, comprising:mixing an iron precursor, a solvent, a stabilizing agent and a reducing agent;
subjecting a mixed solution in the mixing step to hydrothermal synthesis at a temperature of 150 to 300° C. and a pressure of 1.5 to 10 bar to synthesize a superparamagnetic nanocomposite in a nanocluster form; and
separating the synthesized superparamagnetic nanocomposite,
wherein the stabilizing agent is a compound having a carboxyl group,
wherein the superparamagnetic nanocomposite comprises a magnetic nanocrystal having a diameter of from more than 0 to 10 nm, wherein a surface of the magnetic nanocrystal is stabilized by carboxylate (COO?) group, and wherein the superparamagnetic nanocomposite has a plurality of magnetic nanocrystals clustered therein, has a nanoclustered shape having a diameter of 100 nm to 450 nm and has hydrophilicity so as to be dispersed in an aqueous solution.

US Pat. No. 10,658,096

MAGNETIC MULTILAYER SHEET

3M Innovative Properties ...

1. A sheet of magnetic material having a multilayer structure, the multilayer structure comprising:a plurality of stacked magnetic component layers separated by first electrically insulating layers,
wherein each of the plurality of magnetic component layers comprises a plurality of isolated magnetic sublayers and inorganic insulating layers disposed between each of the isolated magnetic sublayers, wherein the plurality of isolated magnetic sublayers are substantially planar and parallel and each of the isolated magnetic sublayers has a magnetic layer thickness that is less than one micron, and wherein each of the first electrically insulating layers has a first insulating layer thickness of between about 0.5 microns and about 20 microns and each inorganic insulating layer has an insulating sublayer thickness of less than about 200 nm, and
where the magnetic material sheet has a magnetic fraction between about 5% and about 80%; a total magnetic thickness of greater than or equal to 5 microns; and a relative composite permeability of greater than about 20.

US Pat. No. 10,658,095

SM-FE-N MAGNET MATERIAL AND SM-FE-N BONDED MAGNET

DAIDO STEEL CO., LTD., N...

1. An Sm—Fe—N magnet material, comprising:7.0-12 at % of Sm;
0.1-1.5 at % of at least one element selected from the group consisting of Hf, Zr, and Sc;
0.1-0.5 at % of Mn;
10-20 at % of N,
0-35 at % of Co; and
0.1-0.5 at % of Si,
with a remainder being Fe and unavoidable impurities.

US Pat. No. 10,658,093

EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE

3M Innovative Properties ...

1. A cable comprising:a plurality of substantially parallel conductors extending along a length and arranged along a width of the cable;
first and second electrically conductive shielding layers disposed on opposite first and second sides of the conductors; and
a dielectric unitary block disposed between the first and second shielding layers at a longitudinal edge, and extending along the length, of the cable, the unitary block comprising a step portion covering a longitudinal edge of at least one of the first and second conductive shielding layers.

US Pat. No. 10,658,092

ELECTRIC WIRE CONDUCTOR, COVERED ELECTRIC WIRE, AND WIRING HARNESS

AUTONETWORKS TECHNOLOGIES...

1. An electric wire conductor comprising a wire strand comprising a plurality of elemental wires twisted together, the conductor having a flat portion where a cross-section of the wire strand intersecting an axial direction of the wire strand has a flat shape, the flat portion having a vacancy ratio of 17% or higher, the vacancy ratio defined as a ratio of vacancies not occupied by the elemental wires or any other substance in the cross-section of the flat portion,wherein deformation ratios of the elemental wires at peripheral end parts in a width direction are 70% or lower of deformation ratios of the elemental wires at center parts.

US Pat. No. 10,658,091

CERAMIC ELECTRICAL INSULATION COATING

The Florida State Univers...

1. A green coated wire for superconducting applications, the green coated wire comprising:a Bi-2212 wire comprising an Ag-alloy sheath;
a base coat surrounding the Ag-alloy sheath of the Bi-2212 wire, the base coat comprising:
15% by weight TiO2 powder,
5% by weight polyvinyl butyral,
1% by weight polysilicate sol-gel,
78% by weight xylene ethanol=1:1,
0.5% by weight butyl benzoyl phthalate, and
0.5% by weight polyalkylene glycol; and
a top coat surrounding the base coat, the base coat surrounding the Ag-alloy sheath of the Bi-2212 wire, wherein the top coat comprises a polyacrylic binder, wherein the top coat does not dissolve in the base coat and a decomposing temperature of the top coat is substantially equal to, or lower than, a decomposing temperature of the first binder and the second binder.

US Pat. No. 10,658,090

CONDUCTIVE PASTE FOR SEMICONDUCTOR DEVICE AND PREPARATION METHOD

Soltrium Advanced Materia...

1. A front-side conductive paste for a crystalline silicon solar cell chip, comprising, based on 100 parts by weight,85.0-93.0 parts of a silver-based metal powder;
6.0-10.0 parts of an organic carrier;
1.0-5.0 parts of an oxide etching agent,
wherein based on 100% by mole, the oxide etching agent comprises at least 25-40% of MgO, 0.1-5.0% of B2O3, 0.1-5% of PbO, and 5.0˜30.0% of Li2O, with the mole ratio of MgO:PbO being 25:5˜40:0.1, and the mole ratio of MgO:Li2O, being 25:30˜40:5;
wherein the oxide etching agent is configured, as the conductive paste is printed and sintered on a surface of an insulating film overlying a front side of the crystalline silicon solar cell chip, to dissolve silver from the metal powder and etch through the insulating film to form a front-side electrode in a good ohmic contact to silicon beneath the insulating film with a metal-silicon adhesion characterized by a lateral tensile force greater than 4 Newtons per 1 mm width.

US Pat. No. 10,658,089

MOTION GUIDANCE ASSEMBLY FOR A COLLIMATOR DEVICE

UIH AMERICA, INC., Husto...

1. A motion guidance assembly for guiding the motion of a collimator device, comprising:a first pair of flexible plates connected to the collimator device, wherein
the first pair of flexible plates are deformable in a direction perpendicular to an opening of the collimator device, and
a deformation of the first pair of flexible plates, based on a driving force, guides the motion of the collimator device.

US Pat. No. 10,658,088

COLLIMATOR AND INSPECTION SYSTEM HAVING THE SAME

TSINGHUA UNIVERSITY, Bei...

1. A collimator comprising:a collimator body comprising a first part, a second part, and a collimating slit formed between the first part and the second part, the collimating slit having a first end and a second end in a longitudinal direction thereof; and
a shielding member which is movable relative to the collimator body in a direction perpendicular to a beam profile such that a beam divergent angle of a ray beam propagating through the collimating slit is varied or both a beam divergent angle and an elevation angle of a ray beam propagating through the collimating slit are varied.

US Pat. No. 10,658,087

DETECTION APPARATUS AND METHOD OF DETECTING THE NEUTRON ABSORPTION CAPABILITY OF A CONTROL ELEMENT OF A NUCLEAR INSTALLATION

Westinghouse Electric Com...

1. A detection apparatus usable to detect a neutron absorption capability of a control element of a nuclear installation, the detection apparatus comprising:a number of manipulators;
a neutron radiograph apparatus comprising an neutron emission source, a detector array, and a mask apparatus, the neutron radiograph apparatus being structured to receive the control element generally between the neutron emission source and the detector array; and
the mask apparatus being movable by at least a first manipulator of the number of manipulators among a number of positions, the number of positions comprising a plurality of different positions disposed at least partially between the neutron emission source and the detector array.

US Pat. No. 10,658,086

OPTIMIZED FUEL ASSEMBLY CHANNELS AND METHODS OF CREATING THE SAME

1. A reactor core in a commercial nuclear power plant, the reactor core comprising:a plurality of fuel assemblies, each of the fuel assemblies including an outer channel with four sidewalls,
a first fuel assembly, of the plurality of fuel assemblies, including at least one first reinforced sidewall,
a second fuel assembly, of the plurality of fuel assemblies, including at least one first non-reinforced sidewall,
wherein an entirety of the at least one first reinforced sidewall as a whole is at least one of thicker or made from a material that is more resistant to radiation-induced deformation as compared to an entirety of the at least one first non-reinforced sidewall.

US Pat. No. 10,658,085

METHOD FOR DETERMINING PATIENT-SPECIFIC BLOOD VESSEL INFORMATION

KNU-INDUSTRY COORPORATION...

1. A method for determining cardiovascular information using a computer system, the method comprising the steps of:receiving image data including a plurality of coronary arteries originating from an aorta;
processing the image data to generate three-dimensional shape models of the coronary arteries;
simulating a blood flow for the generated three-dimensional shape models of the coronary arteries; and
determining a fractional flow reserve (FFR) of the coronary arteries based on a blood flow simulation result,
wherein, in the step of simulating the blood flow, a computational fluid dynamics model is applied to the three-dimensional shape models of the coronary arteries, a lumped parameter model is combined with the computational fluid dynamics model, and a simplified coronary artery circulation model including the coronary arteries, capillaries of the coronary arteries and coronary veins is used as the lumped parameter model,
wherein the step of simulating the blood flow includes
a step of finding lengths of centerlines of the three-dimensional shape models of the coronary arteries,
resistance values of the capillaries of the coronary arteries are set based on a ratio of blood flow rates in the coronary arteries when combining the simplified coronary artery circulation model with the computational fluid dynamics model, and
the ratio of the blood flow rates in the coronary arteries is set based on a ratio of the lengths of the centerlines of the three-dimensional shape models of the coronary arteries, and
wherein the ratio of the blood flow rates in the coronary arteries is determined by the following mathematical formula:
where QLAD is a blood flow rate of a left anterior descending coronary artery, lLAD is a length of the left anterior descending coronary artery, QLCX is a blood flow rate of a left circumflex coronary artery, lLCX is a length of the left circumflex coronary artery, QRCA is a blood flow rate of a right coronary artery, lRCA is a length of the right coronary artery, (lRCA)RV is a length of a portion of the right coronary artery for supplying blood to a right ventricle, is a length of a portion of the right coronary artery for supplying blood to a left ventricle, and ? is a correction coefficient of a blood vessel for supplying blood to the right ventricle.

US Pat. No. 10,658,084

BASAL INSULIN MANAGEMENT

Insulet Corporation, Act...

1. A device, comprising:a display device;
an input device;
a memory storing computer-executable instructions; and
a processor coupled to the display device, the input device, and the memory, the processor operable to execute the computer-executable instructions, wherein, when the processor is executing the computer-executable instructions, the processor is operable to:
receive, via the input device, a numerical value for a temporary basal rate adjustment and a numerical value for a duration of the temporary basal adjustment rate;
determine, based on a current time and the numerical value for the duration of the temporary basal rate adjustment, a portion of a basal insulin program during which a temporary basal rate adjustment is to be administered;
determine a temporary basal rate adjustment for a first time segment of a basal insulin program based on a difference between a basal rate and the temporary basal rate adjustment;
determine a numerical value of a new basal rate for the first time segment based on the basal rate and the temporary basal rate adjustment; and
present a user interface on the display device, the user interface including:
a first portion configured to display the numerical value for the duration of the temporary basal rate adjustment and a numerical value for the temporary basal rate adjustment for the determined portion of the basal insulin program, wherein the determined portion of the basal insulin program overlaps the first time segment of the basal insulin program, and
a second portion configured to graphically represent the temporary basal rate adjustment for the first time segment with the numerical value of the new basal rate for the first time segment is further displayed.

US Pat. No. 10,658,083

GRAPHICAL USER INTERFACES INCLUDING TOUCHPAD DRIVING INTERFACES FOR TELEMEDICINE DEVICES

INTOUCH TECHNOLOGIES, INC...

1. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, are configured to cause the processor to perform operations comprising:retrieving a list of patients;
selectively displaying the list of patients;
receiving a selection of a patient from the patient list;
automatically selecting a remote presence device from a plurality of remote presence devices, wherein automatically selecting comprises:
connecting to an admissions, discharges, and transfers (ADT) data source for a facility;
determining using the ADT data source a current location of the selected patient within the facility; and
selecting a remote presence device nearest the current location of the selected patient within the facility;
communicatively connecting an electronic device to the selected remote presence device;
displaying a live video feed from a camera of the remote presence device in a video panel on an electronic display of the electronic device; and
updating the live video feed as the selected remote presence device moves to the selected destination.

US Pat. No. 10,658,082

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND METHOD FOR PROVIDING INFORMATION

Ricoh Company, Ltd., Tok...

1. An information processing apparatus connected with an external server apparatus via a network, the external server apparatus storing identification information of a plurality of wireless apparatuses in a facility, and information about a plurality of detector apparatuses that detect identification information of the wireless apparatuses, the information processing apparatus comprising a circuitry, in communication with a memory, executing steps of:storing, in a memory that is located in a local area network of the facility, the identification information of a wireless apparatus attached to a patient in the facility and medical information including a schedule of treatment for the patient and a condition of the patient so as to associate the identification information of the wireless apparatus with the medical information;
obtaining detection information including the identification information of the wireless apparatus, a time when the identification information of the wireless apparatus is received and the information including identification information of the detector apparatus from the external server apparatus that is configured to store detection history information including the identification information of the wireless apparatus, identification information of the detector apparatus, and the time when the identification information of the wireless apparatus is received;
generating, based on floor information that associates a floor layout of a facility, the identification information of the detector apparatus, and a location of the detector apparatus in the floor layout, and the obtained detection information, positional information of the wireless apparatus that associates a time when the patient corresponding to the wireless apparatus is detected with a detection location of the wireless apparatus in the floor layout; and
providing information that is generated at a predetermined time of a detection of the wireless apparatus so as to associate a location of the patient corresponding to the identification information of the wireless apparatus with the medical information of the patient in the floor layout, based on the generated information and the medical information, to an apparatus connected to the information processing apparatus via the network,
wherein the information processing apparatus is located in the local area network of the facility and connected with the external server apparatus located outside the local area network via the network, and
the external server apparatus stores only the identification information of the wireless apparatus, the time when the identification information of the wireless apparatus is received and the information about the detector apparatus.

US Pat. No. 10,658,081

PATIENT DEVICE FOR ADVANCED PATIENT COMMUNICATION

Eloquence Communications,...

1. A computer-implemented method, comprising:providing a patient communication mechanism by which a patient communicates a first message within a healthcare facility; receiving one or more messages at a central processing server, a first message reflecting a patient request or need;
processing the first message to identify an urgency level of the first message, a lapse in time and a provider skill level or role best suited to respond to the first message; generating one or more additional messages based on the first message; and transmitting the one or more additional messages to at least one specific provider device of specific providers expected to respond, wherein the one or more additional messages are routed to at least one specific provider device based on a context of the first message;
presenting the one or more additional messages via a display with a selection input mechanism;
enabling a provider to select at least one of the presented messages via touching the display or at least one display control button of the selection input mechanism, which enables transferring of the one or more additional messages or generation and transmission of a second message.

US Pat. No. 10,658,080

METHOD FOR MONITORING BEHAVIOUR OF A PATIENT IN REAL-TIME USING PATIENT MONITORING DEVICE

Wipro Limited, Bangalore...

1. A method for monitoring behaviour of a patient in real-time, the method comprising:receiving, by a patient monitoring device comprising a processor and a memory, data related to an activity performed by the patient from one or more sources;
classifying, by the patient monitoring device, the received data into one or more categories based on one or more rules,
wherein the one or more rules categorize the received data into the one or more categories that comprise an audio category, a video category, an image category, and a medical category, and wherein the one or more rules further define different formats in which the one or more categories of the received data are to be processed by the patient monitoring device;
filtering, by the patient monitoring device, the classified data based on one or more rules to identify one or more relevant data required for monitoring the behaviour of the patient in real-time,
wherein the filtering of the data comprises processing the classified data based on the one or more rules to discard data indicative of an expected activity, and
wherein the one or more rules are dynamically updated based on the activity performed by the patient and a time consumed to perform the activity;
converting, by the patient monitoring device, the one or more relevant data from the different formats into a text format based on predefined configuration information stored in the memory;
correlating, by the patient monitoring device, the one or more relevant data in the text format to identify one or more activity patterns corresponding to the patient, by performing text analytics technique in combination with one or more machine learning algorithms, wherein each of the one or more activity patterns are associated with the activity performed by the patient at predefined time intervals;
detecting, by the patient monitoring device, abnormal behaviour that affect recovery of the patient if the one or more identified activity patterns are different from one or more predefined activity patterns corresponding to the patient;
identifying, by the patient monitoring device, one or more remedies for the detected abnormal behaviour of the patient; and
generating, by the patient monitoring device, an alert notification of the detected abnormal behavior, wherein the alert notification along with the one or more remedies are provided to one or more receiving entities for taking an immediate remedy action on the patient.

US Pat. No. 10,658,079

CROWD-BASED RECOMMENDATIONS OF A VERSION OF FIRMWARE FOR MEDICAL DEVICES

Medigate Tech Ltd., Tel-...

1. A system configured to recommend a version of firmware for medical devices, comprising:a computer configured to:
receive packets transmitted over communication networks of medical facilities, wherein the packets comprise data related to medical device activity;
perform deep packet inspection (DPI) of the packets;
extract, from results of the DPI, versions of firmware installed on the medical devices;
calculate, based on the versions of firmware, extents to which different versions of firmware were installed on the medical devices;
identify a latest version of firmware, from among the different versions, whose extent of installation reaches a predetermined threshold; and
recommend an update to firmware installed on one or more medical devices at a certain medical facility to said latest version.

US Pat. No. 10,658,078

NONRESONANT ENCLOSURE FOR SCANNING MEDICAL ARTICLES

MEPS Real-Time, Inc., Ca...

1. A medical storage container re-supply system for reading a data carrier that is attached to a medical storage container and data carriers attached to medical articles located in the storage container to manage the inventory of the storage container, each of the data carriers being responsive to electromagnetic (EM) energy having a frequency falling within a predetermined frequency range in response to which each data carrier provides identification data, the system comprising:an enclosure having an internal storage area, the enclosure further having electrically-conductive walls that surround the internal storage area and any storage container and medical article with associated data carrier placed therein, the enclosure having a natural frequency of resonance that is different from the predetermined frequency range to which the data carriers are operationally responsive;
a probe disposed at an electrically-conductive wall within the enclosure, the probe configured to inject EM energy of a frequency falling within the predetermined range of frequencies into the enclosure;
a medical storage container having a data carrier identifying the container, the storage container being located within the internal storage area of the enclosure and containing medical articles, each with an associated data carrier identifying that medical article, the data carriers being responsive to EM energy having a frequency falling within the predetermined range of frequencies, but which are not responsive to the natural resonance frequency of the enclosure;
a predetermined required inventory list of medical articles for the storage container;
a non-volatile memory on which is stored the predetermined required inventory list of the storage container;
a processor programmed to receive the identification data of the storage container and the identification data of the articles in the storage container, locate the predetermined required storage container inventory list in the memory through the identification of the storage container, locate the details of the medical articles identified in the storage container in the memory through the identification data of the medical articles, and compare the details of the medical articles against the required inventory list of the storage container to manage the inventory of the storage container.

US Pat. No. 10,658,077

ENCLOSED RFID TRACKING SYSTEM FOR IDENTIFYING MEDICAL ARTICLES

MEPS Real-Time, Inc., Ca...

1. A system for tracking medical articles, each of which has a radio frequency identification (RFID) tag attached, wherein each RFID tag is configured to transmit an identification code in response to receiving electromagnetic energy (EM) having a frequency within a predetermined frequency range f1, the system comprising:an enclosure in which medical articles with their respective attached RFID tags are stored, wherein all surfaces of the enclosure surrounding the stored medical articles are electrically conductive, the enclosure have a natural frequency of resonance f2 that differs from the frequencies within the predetermined frequency range of f1 whereby the enclosure is non-resonant at all frequencies within the frequency range of f1; and
a first probe inductively coupled to the enclosure, the probe configured to inject electromagnetic (EM) energy into the enclosure at a frequency within the f1 range of frequencies to establish a transverse magnetic (TM) mode in the enclosure;
whereby, the injected energy in the f1 frequency range activates the RFID tags within the enclosure to transmit their respective identification codes.

US Pat. No. 10,658,076

SYSTEM AND METHOD FOR INCREASING EFFICIENCY OF MEDICAL LABORATORY DATA INTERPRETATION, REAL TIME CLINICAL DECISION SUPPORT, AND PATIENT COMMUNICATIONS

1. A method for automated medical diagnostic analysis, comprising:a computing system with one or more processors performing the steps of:
receiving laboratory test results in numerical and textual form for one or more routine diagnostic laboratory tests performed on a patient as ordered by a clinician;
receiving protected health information for said patient, where said protected health information includes patient demographic data including the patient's address;
storing said laboratory test results and said protected health information for said patient in a secure data storage system, wherein said secure data storage system stores the test results and protected health information in a cryptographic blockchain ledger;
determining a region and country where the patient is located from the patient's address;
comparing said laboratory test results for said patient with reference information contained in a knowledge base in numerical and textual form and creating one or more initial diagnostic interpretations for said patient based on the laboratory results comparison;
comparing the reference information with reference ranges specific to the region and country where the patient is located and modifying the one or more initial diagnostic interpretations for said patient based on the reference ranges comparison, wherein the modifying produces one or more modified diagnostic interpretations different from the one or more initial diagnostic interpretations, and wherein the reference ranges specific to the region and country are contained in the knowledge base;
analyzing said one or more modified diagnostic interpretations with one or more machine learning algorithms to produce one or more determined medical diagnoses, the severity level for each of said one or more determined medical diagnoses, one or more clinical recommendations and an overall priority level for said patient, wherein the one or more machine learning algorithms utilize weighted nodes, and wherein said one or more determined medical diagnoses are produced in patient-appropriate language and clinician-appropriate language;
storing in said secure data storage system said one or more modified diagnostic interpretations, said one or more determined medical diagnoses, said severity level for each of said one or more determined medical diagnoses, said one or more clinical recommendations, and said overall priority level for said patient;
providing a clinician diagnostic report to said clinician comprising said laboratory test results, said one or more modified diagnostic interpretations, said one or more determined medical diagnoses in the clinician-appropriate language, said severity level for each of said one or more determined medical diagnoses, said one or more clinical recommendations and said overall priority level for said patient;
providing a patient diagnostic report to said patient comprising said laboratory test results, said one or more determined medical diagnoses in the patient-appropriate language, said severity level for each of said one or more determined medical diagnoses, an overall score, and one or more recommended actions for said patient;
receiving diagnosis feedback from said clinician in the form of a numerical diagnosis weighting scale for at least one of said one or more modified diagnostic interpretations and at least one of said one or more determined medical diagnoses for said patient, wherein the diagnosis feedback is specific to the region and country where the patient is located;
receiving clinical recommendation feedback from said clinician in the form of a numerical clinical recommendation weighting scale for at least one of said one or more clinical recommendations for said patient, wherein the clinical recommendation feedback is specific to the region and country where the patient is located;
modifying said one or more machine learning algorithms used for subsequent determination of diagnostic interpretations and determined medical diagnoses bar increasing or decreasing the weights applied to the weighted nodes of each of the one or more machine learning algorithms according to the received diagnosis feedback that is specific to the region and country where the patient is located; and
modifying said one or more machine learning algorithms used for subsequent determination of clinical recommendations by increasing or decreasing the weights applied to the weighted nodes of each of the one or more machine learning algorithms according to the received recommendation feedback that is specific to the region and country where the patient is located.

US Pat. No. 10,658,075

RAPID REPORTING OF MEANINGFUL USE IN ELECTRONIC HEALTH RECORDS

ALLSCRIPTS SOFTWARE, LLC,...

1. A processor-based method of optimizing the generation of electronic reports of meaningful use in an electronic health records (EHR) computer system, comprising:receiving patient encounter data in a database, wherein the patient encounter data comprises Boolean values;
pre-calculating first data related to a first meaningful use measure associated with at least a portion of the patient encounter data;
storing the pre-calculated first data in a first small staging table;
pre-calculating second data related to a second meaningful use measure associated with at least a portion of the patient encounter data;
storing the pre-calculated second data in a second small staging table;
processing the pre-calculated first data of the first small staging table to generate a first data column representing the first meaningful use measure without Boolean values, wherein a value of true is represented by a unique patient identifier, and a value of false is represented by a null value;
compiling the processed first small staging table and second small staging table into a single table;
accessing the single table via reporting software to calculate a meaningful use metric related to the first data column of the first meaningful use measure, the calculation comprising determining a number of unique values contained in the first data column; and
generating an electronic report for the EHR computer system comprising the meaningful use metric.

US Pat. No. 10,658,074

MEDICAL TRANSCRIPTION WITH DYNAMIC LANGUAGE MODELS

Zeus Data Solutions, Inc....

1. A computer-implemented method for transcribing spoken input into text, the method comprising:identifying a role that indicates a type of medicine performed by a particular healthcare provider, the role being identified automatically by identifying an electronic record that assigns an identifier for the healthcare provider to the role;
using the identified role for the particular healthcare provider to select, with a computerized speech recognition system, a particular statistical language model from among a group of available statistical language models that (a) are each directed to a different particular medical specialty from others of the language models, and (b) each provide probabilities of word distributions for converting audio spoken input to textual output, which probabilities differ from those in others of the statistical language models, and further wherein the particular statistical language model is selected based on identifying a match between the role of the healthcare provider and a particular medical specialty to which the particular statistical language model is directed;
receiving spoken input from the healthcare provider; and
passing the spoken input through the selected electronic language model to produce textual output that is the spoken input in text form.

US Pat. No. 10,658,072

METHOD AND SYSTEM FOR INTERACTION ANALYSIS

GE Healthcare Bio-Science...

1. A method for screening a sample in respect of the presence of at least one specific analyte possibly present in a fluid sample by evaluating data from interaction between the specific analyte, if present, and its ligand or binding partner, which comprises the steps of:a) providing a biosensor defining a sensor surface comprising at least one immobilized ligand, wherein each ligand is known to bind and interact with a specific analyte;
b) obtaining a plurality of different reference binding curves, each representing a specific binding behavior between a specific analyte of a plurality of specific analytes and its ligand, or binding partner known to interact with the specific analyte of the plurality of specific analytes, for a predetermined acquisition cycle;
c) acquiring, using the biosensor, a sample binding curve for interaction between the specific analyte possibly present in the fluid sample and its ligand or binding partner for the same predetermined acquisition cycle;
d) registering the deviation of the sample binding curve from the reference binding curves to form at least two reference interaction windows including a stable binding reference interaction window associated with more than 96% of sensor response remaining after 180 seconds of dissociation and a less stable binding reference interaction window associated with less than 96% of sensor response remaining after 180 seconds of dissociation;
e) assigning the interaction between the specific analyte and its ligand or binding partner from step c) to reference interaction window of the at least two reference interaction windows to which it shows the smallest registered deviation; and
f) optionally repeating steps c)-e) with additional fluid samples.

US Pat. No. 10,658,071

SCALABLE PIPELINE FOR LOCAL ANCESTRY INFERENCE

23andMe, Inc., Sunnyvale...

1. A system, comprising:one or more processors configured to:
train a learning machine using a training set comprising genetic information of a plurality of individuals with known ancestries;
obtain unphased genotype data of an individual whose ancestry composition is to be determined;
phase the unphased genotype data of the individual to generate phased haplotype data of the individual;
use the trained learning machine to classify portions of the phased haplotype data of the individual as corresponding to specific ancestries and generate initial ancestry classification results;
correct one or more errors in the initial ancestry classification results to generate modified ancestry classification results, wherein the modified ancestry classification results include ancestry assignments and posterior probabilities association with the ancestry assignments;
recalibrate the modified ancesry classification results to establish confidence levels associated with the ancestry assignments;
determine if the confidence levels associated with the ancestry assignments meet a threshold level; and
one or more memories coupled with the one or more processors, configured to provide the one or more processors with instructions.

US Pat. No. 10,658,067

MANAGING DATA DISTURBANCE IN A MEMORY WITH ASYMMETRIC DISTURBANCE EFFECTS

MICRON TECHNOLOGY, INC., ...

1. A computer-implemented method, comprising:determining that a group of memory cells of a first memory device has an elevated error rate, wherein the group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension;
in response to determining that the group of memory cells of the first memory device has the elevated error rate:
identifying a spare group of memory cells, wherein the spare group of memory cells also spans the first dimension and the second dimension, and
reading a portion of a logical unit from the group of memory cells along the first dimension of the group;
determining that the group of memory cells has a strong disturb effect in the first dimension and that the spare group of memory cells has a strong disturb effect in the second dimension; and
in response to determining the strong disturb effect of the group of memory cells and the strong disturb effect of the spare group of memory cells are in different dimensions, writing the portion of the logical unit to the spare group of memory cells along the second dimension of the spare group.

US Pat. No. 10,658,066

FIRST-PASS CONTINUOUS READ LEVEL CALIBRATION

Micron Technology, Inc., ...

1. A system comprising:a memory component; and
a processing device, operatively coupled with the memory component, to:
determine that a first programming pass of a programming operation has been performed on a memory cell of the memory component; and
perform a continuous read level calibration (cRLC) operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell, wherein, to perform the cRLC operation, the processing device is further to:
calculate a center bit error count;
calculate a difference error count; and
adjust the read level threshold of the memory cell based on the center bit error count and the difference error count.

US Pat. No. 10,658,065

FAILURE MODE DETECTION METHOD AND ERROR CORRECTION METHOD FOR SOLID STATE STORAGE DEVICE

SOLID STATE STORAGE TECHN...

1. A failure mode detection method for a solid state storage device, the failure mode detection method comprising steps of:changing a first default read voltage to a first read retry voltage by a first increment, and changing a second default read voltage to a second read retry voltage by a second increment, wherein when a memory cell array of the solid state storage device is read according to the first read retry voltage and the second read retry voltage, an accurate read data is generated;
if an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, judging that the memory cell array of the solid state storage device is in a data retention failure mode; and
if the absolute value of the first increment minus the absolute value of the second increment is not larger than the predetermined voltage value, judging that the memory cell array of the solid state storage device is in a low temperature write high temperature read failure mode.

US Pat. No. 10,658,064

MEMORY DEVICE AND TEST METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A test method for a memory device, comprising:performing a first write operation of writing test data provided from an external device to first regions of a normal cell region and a parity cell region, and storing parity bits generated based on the test data in a temporary storage circuit;
performing a second write operation of writing the parity bits stored in the temporary storage circuit to a second region of the parity cell region, wherein the parity cell region stores both of the test data and the parity bits after the second write operation;
performing a first read operation of reading the parity bits from the second region of the parity cell region, and storing the parity bits into the temporary storage circuit; and
performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bits stored in the temporary storage circuit, and outputting error-corrected test data.

US Pat. No. 10,658,063

SEMICONDUCTOR MEMORY DEVICE INCLUDING A CORRECTING CIRCUIT

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:first and second memory cells;
a read circuit configured to read first data from the first memory cell by receiving a first command;
a correcting circuit configured to generate second data by correcting an error included in the first data;
a storage circuit configured to store third data and the second data by receiving a second command; and
a write circuit configured to, in response to receiving a third command, perform a first writing for writing the second data to the first memory cell, and to perform a second writing for writing the third data to the second memory cell,
wherein the first writing and the second writing are started in parallel in response to receiving the third command.

US Pat. No. 10,658,062

SIMULTANEOUS SCAN CHAIN INITIALIZATION WITH DISPARATE LATCHES

International Business Ma...

1. A method, comprising:determining that an integrated circuit is in a test mode, the integrated circuit including an initialization circuit and two or more disparate latches, the initialization circuit comprising a multiplexor and an OR gate, wherein:
a reset is electrically connected to a select line of the multiplexor and a first input of the OR gate;
a clock is electrically connected to a second input of the OR gate,
wherein the OR gate is electrically connected to a clock input of a first latch, wherein the first latch includes the clock input, a scan enable input, a data input, and a data output; and
a first regular logic data path is electrically connected to the multiplexor, wherein the multiplexor is further electrically connected to a data port of the first latch;
enabling, in response to determining that the integrated circuit is in the test mode, a data stream to be shifted from one latch of the two or more latches to another latch of the two or more latches;
setting a reset pin; and
initializing the two or more latches.

US Pat. No. 10,658,061

SHIFT REGISTER CIRCUIT, METHOD FOR DRIVING SHIFT REGISTER CIRCUIT, GATE ELECTRODE DRIVING CIRCUIT AND DISPLAY DEVICE

HEFEI BOE OPTOELECTRONICS...

1. A shift register circuit, comprising a clock signal adjustment circuit and a self-control conduction circuit, whereinthe clock signal adjustment circuit comprises a first clock signal input terminal, a second clock signal input terminal and a clock signal adjustment output terminal; the self-control conduction circuit is coupled to the clock signal adjustment output terminal and a pull-up node;
the first clock signal input terminal is configured to load a first clock signal, the second clock signal input terminal is configured to load a second clock signal, wherein both the first clock signal and the second clock signal have a first level and a second level, wherein the first level is an active operating level and is higher than a reference level;
the clock signal adjustment circuit is configured to, in the case that the first clock signal and the second clock signal are both at the second level, output the first level via the clock signal adjustment output terminal, wherein the second level is lower than the reference level;
the self-control conduction circuit is configured to, in the case that the pull-up node is at the first level, control the clock signal adjustment output terminal to connect with the pull-up node, or the self-control conduction circuit is configured to, in the case that the pull-up node is at the second level, disconnect the clock signal adjustment output terminal from the pull-up node,
wherein a duty ratio of the first clock signal and a duty ratio of the second clock signal are both less than 50%; a period of the first clock signal is the same as a period of the second clock signal, and a phase difference between the first clock signal and the second clock signal is 180°.

US Pat. No. 10,658,060

SHIFT REGISTER CIRCUIT AND SHIFT REGISTER UNIT

Wuhan China Star Optoelec...

1. A shift register circuit, used for connecting with a pixel-compensating circuit corresponding to a GOA unit, wherein the shift register circuit comprises:an input module connecting with a signal input terminal, the input module is adapted for generating an output control signal based on an input signal supplied by the signal input terminal;
a shift register module connecting with the input module, the shift register module is adapted for inverting the output control signal, so as to output an emission control signal toward the pixel-compensating circuit corresponding to the GOA unit; and
wherein the shift register module comprises a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor;
wherein a first source of the first transistor is coupled with a high level, a first gate of the first transistor connects with an output terminal of the input module, and a first drain of the first transistor connects with a first terminal of the second capacitor;
wherein a second source of the second transistor connects with the high level, a second gate of the second transistor connects with an output terminal of the input module, a second drain of the second transistor connects with a fourth source of the fourth transistor, and the first capacitor is jointed between the second gate and the second source;
wherein a third source of the third transistor connects with the first drain, a third gate of the third transistor connects with an output terminal of the shift register module, and a third drain of the third transistor is coupled with a low level; and
wherein the fourth source of the fourth transistor further connects with an output terminal of the shift register module, a fourth gate of the fourth transistor connects with the first drain, and a fourth drain of the fourth transistor is coupled with the low level.

US Pat. No. 10,658,059

PERFORMANCE EVALUATION OF SOLID STATE MEMORY DEVICE

INTERNATIONAL BUSINESS MA...

1. A method for performance testing of solid state memory devices, the method comprising:selecting a period of time to operate a first solid state memory device for the first solid state memory device to reach a desired preconditioned state;
operating, by a processor, the first solid state memory device for the period of time;
capturing state information of the first solid state memory device after the period of time, wherein the state information includes only a program-erase cycle count and a logical to physical mapping table and wear leveling data;
storing the state information in a control file;
loading the control file onto a second solid state memory device; and
performing performance testing on the second solid state memory device without preconditioning the second solid state memory device.

US Pat. No. 10,658,058

BIT ERROR RATE ESTIMATION FOR NAND FLASH MEMORY

Toshiba Memory Corporatio...

1. A method comprising:performing a program operation on a multi-level cell flash memory having a plurality of threshold voltages associated with a plurality of program states;
in connection with performing the program operation, estimating a bit error rate (BER) of the multi-level cell flash memory by, for a given threshold voltage of the plurality of threshold voltages:
programming a state greater than the associated program state for the given threshold voltage,
determining a number of cells having a programmed state less than a verify threshold value, and
determining the estimated BER based on the number of cells and a BER threshold value.

US Pat. No. 10,658,057

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a first semiconductor region of p-type;
n word lines from a first word line to an nth word line stacked on the first semiconductor region in a first direction;
a second semiconductor region of n-type;
a semiconductor layer provided between the first semiconductor region and the second semiconductor region, the semiconductor layer extending in the first direction, and the semiconductor layer intersecting with the n word lines;
a bit line electrically connected to the second semiconductor region; and
a control circuit configured to perform a first verify operation and a second verify operation after the first verify operation,
wherein, to verify whether or not a kth (4 a first voltage is applied between the first semiconductor region and the second semiconductor region in the first verify operation, and
a second voltage different from the first voltage is applied between the first semiconductor region and the second semiconductor region in the second verify operation.

US Pat. No. 10,658,056

INTERNAL COPY TO HANDLE NAND PROGRAM FAIL

Intel Corporation, Santa...

1. An electronic processing system, comprising:a processor;
nonvolatile memory communicatively coupled to the processor; and
logic communicatively coupled to the processor and the nonvolatile memory to:
attempt to program data in a first portion of the nonvolatile memory,
store the data in a cache of the nonvolatile memory prior to the attempt,
determine if the attempt was successful,
determine if the data stored in the cache of the nonvolatile memory is valid prior to recovery of the data, and
recover the data from the cache of the nonvolatile memory to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful.

US Pat. No. 10,658,055

MEMORY SYSTEM AND METHOD FOR CONTROLLING MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a nonvolatile memory comprising a first cell transistor, a second cell transistor, a first word line, and a second word line,
the first word line and the second word line respectively being connected to the first cell transistor and the second cell transistor,
the nonvolatile memory being configured to write any one data value among one or more data values into each of the first cell transistor and the second cell transistor; and
a controller configured to:
instruct the nonvolatile memory to apply a first verify voltage to the first word line for determining whether writing of a first data value into the first cell transistor by using a first programming voltage has been completed, the first data value being one of the one or more data values; and
instruct the nonvolatile memory to apply a second verify voltage to the second word line for determining whether writing of the first data value into the second cell transistor by using the first programming voltage has been completed, the second verify voltage being different in a voltage level from the first verify voltage.

US Pat. No. 10,658,054

METHODS FOR READ THRESHOLD VOLTAGE SHIFTING IN NON-VOLATILE MEMORY

International Business Ma...

2. A computer-implemented method for optimizing a read threshold voltage shift value in a NAND flash memory, said method comprisingselecting a group of at least one memory pages, each of said memory pages comprising a plurality of memory cells,
determining a current threshold voltage shift value (gTVS),
determining a positive threshold voltage shift offset value (?1) and a negative threshold voltage shift offset value (?2),
repeating a loop process comprising
reading all memory pages in said selected group with read threshold voltage shift values of gTVS, gTVS+?1, gTVS+?2,
determining for each of said read threshold shift values said maximum raw bit error rates for said group of memory pages being read,
determining a direction of change for said current threshold voltage shift value using said maximum raw bit error rates obtained from reading said memory pages in said selected group with said read threshold voltage shift values gTVS, gTVS+?1, and gTVS+?2,
determining a new current threshold voltage shift value by applying a function to said current threshold voltage shift value using as parameters said current threshold voltage, said direction of change and said positive threshold voltage shift value and said negative threshold voltage shift value,until a stop condition is fulfilled such that said optimizing a read threshold voltage shift value is determined to generate a lowest possible number of read errors per group of memory pages, wherein a read operation of a memory page is skipped if said memory page has been read with said same threshold voltage shift values in a previous iteration, and said raw bit error rate from said previous read with said same threshold voltage shift values is used.

US Pat. No. 10,658,053

RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING

Intel Corporation, Santa...

1. A memory device comprising:one or more arrays of non-volatile memory cells; and
circuitry to perform read and program operations on the one or more arrays of non-volatile memory cells, the circuitry to:
apply a program voltage pulse (Vpgm) to a selected wordline; and
apply a first voltage to an unselected wordline and ramp up from the first voltage at a constant positive slope to a second voltage while the selected wordline is biased to Vpgm, the ramp up to begin prior to the application of Vpgm to the selected wordline and continue until at least the end of the program voltage pulse.

US Pat. No. 10,658,052

SEMICONDUCTOR DEVICE

Winbond Electronics Corp....

1. A semiconductor device, comprising:an internal voltage generation part generating an internal voltage based on a power supply voltage supplied from outside and receiving a trimming signal for trimming the internal voltage, wherein a range of the internal voltage be able to be changed by the trimming signal is ±Vt;
a determination part comparing the internal voltage with a reference voltage, and generating an enablement signal when detecting that the internal voltage is greater than the reference voltage;
an internal circuit operable in response to the enablement signal;
wherein the determination part comprises:
a drop part lowering the reference voltage in response to generation of the enablement signal;
a first resistor;
a second resistor,
a comparator for comparing the internal voltage with the reference voltage, and wherein the drop part lowers the reference voltage with a drop amount in response to an output of the comparator, and the drop amount is larger than or equal to Vt,
wherein the drop part, the first resistor and the second resistor are connected in series between the reference voltage and ground, a first terminal of the first resistor is connected to the reference voltage, a first terminal of the second resistor is connected to ground, the drop part is connected between the first resistor and the second resistor,
wherein the drop part comprises a first transistor and a third resistor, the first transistor is connected in parallel to the third resistor, a first terminal of the third resistor is connected to a second terminal of the first resistor, a second terminal of the third resistor is connected to a second terminal of the second resistor, the first transistor is switched in response to the enablement signal,
wherein the second terminal of the third resistor is connected to an inverting input terminal of the comparator to input the reference voltage lowered by the drop part.

US Pat. No. 10,658,051

MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A memory system comprising:a memory device including a plurality of memory cells; and
a controller configured to:
select a page of the memory device, the page including a plurality of memory cells;
sense threshold voltages for the plurality of memory cells;
select memory cells among the plurality of memory cells;
determine a number of memory cells among the selected memory cells for each of a plurality of voltage intervals corresponding to the threshold voltages; and
determine an optimal read voltage based on the voltage interval, among the plurality of voltage intervals, in which the number of select memory cells is smallest.

US Pat. No. 10,658,050

MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A method of operating a memory controller to control a read operation of a semiconductor memory device, the method comprising:sensing threshold voltages of memory cells included in a selected page of the semiconductor memory device using a plurality of sensing voltages within a determined range;
selecting first and second subsets of memory cells to be used to determine an optimal read voltage from among the memory cells included in the selected page;
detecting a number of memory cells in the first subset and a number of memory cells in the second subset corresponding to each of the plurality of threshold voltage intervals based on results of sensing of the threshold voltages;
determining a voltage corresponding to a threshold voltage interval, in which the number of memory cells in the first subset is smallest, as a first intermediate read voltage, and determining a voltage corresponding to a threshold voltage interval, in which the number of memory cells in the second subset is smallest, as a second intermediate read voltage; and
determining the optimal read voltage based on the first and second intermediate read voltages.

US Pat. No. 10,658,049

MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A method of operating a memory controller to control a read operation of a semiconductor memory device, the method comprising:sensing threshold voltages of memory cells included in a selected page of the semiconductor memory device using a plurality of sensing voltages within a determined range;
selecting memory cells to be used to determine an optimal read voltage from among the memory cells in the selected page;
detecting a number of the selected memory cells having threshold voltages corresponding to each of a plurality of threshold voltage intervals based on results of sensing of the threshold voltages; and
determining a voltage corresponding to a threshold voltage interval, in which the number of selected memory cells is smallest, as an optimal read voltage.

US Pat. No. 10,658,048

FLOATING BOOSTED PRE-CHARGE SCHEME FOR SENSE AMPLIFIERS

STMICROELECTRONICS S.R.L....

1. A sense structure comprising:a sense amplifier core configured to compare a measurement current with a reference current;
a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load;
a switch coupled between a bias voltage node and a control terminal of the cascode transistor;
a local capacitor having a first terminal coupled to the control terminal of the cascode transistor;
a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and
a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.

US Pat. No. 10,658,047

IMPLEMENTING STICKY READ USING ERROR CONTROL SUCCESS RATE ASSOCIATED WITH A MEMORY SUB-SYSTEM

Micron Technology, Inc., ...

1. A system comprising:a memory component; and
a processing device, operatively coupled with the memory component, to:
determine that a memory sub-system is operating within a target operating characteristic based on a threshold success rate associated with a plurality of error control operations using a particular parameter;
upon determining that the memory sub-system is operating within the target operating characteristic, enter a sticky read mode by performing subsequent read operations using the particular parameter;
determine that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode; and
upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, exit the sticky read mode by performing further read operations using a default parameter associated with the memory sub-system.

US Pat. No. 10,658,046

MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A memory device, comprising:a memory array;
a logic circuit, coupled to the memory array, the logic circuit configured to perform a corresponding operation in response to an operation command from a controller; and
a sense amplifier circuit, coupled to the logic circuit and the memory array;
wherein when an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit is further configured to output the memory status to the controller in response to a status read command from the controller; and
wherein the operation command is a read command, the corresponding operation is a read operation, the sense amplifier circuit is configured to read a second data sequence from the memory array, and the memory status includes a continued read address.

US Pat. No. 10,658,045

ENHANCED SOLID-STATE DRIVE WRITE PERFORMANCE WITH BACKGROUND ERASE

Western Digital Technolog...

1. A method for programming memory blocks in a memory system, the method comprising:identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system;
performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks;
storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks;
identifying, using the pre-erase table, at least one memory block to be programmed; and
programming the at least one memory block by:
performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and
performing a write operation on the at least one memory block.