US Pat. No. 10,560,103

FLUX-TUNABLE QUBIT DEVICE WITH MULTIPLE JOSEPHSON JUNCTIONS

1. A qubit device comprising:an inductor connected between a first circuit node and a second circuit node;
a first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and
a second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node,
wherein the qubit device is configured to receive, during operation of the qubit device, a magnetic flux that controls a qubit frequency of the qubit device, and the qubit frequency as a function of the magnetic flux comprises multiple flux sweet spots.

US Pat. No. 10,560,101

COUNT VALUE GENERATION CIRCUIT, PHYSICAL QUANTITY SENSOR MODULE, AND STRUCTURE MONITORING DEVICE

Seiko Epson Corporation, ...

1. A count value generation circuit comprising:a first counter that counts edges of a reference signal in synchronization with an input signal to generate a first count value;
a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal;
a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value; and
a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

US Pat. No. 10,560,100

APPARATUSES AND METHODS INCLUDING CONFIGURABLE LOGIC CIRCUITS AND LAYOUT THEREOF

Micron Technology, Inc., ...

1. An apparatus, comprising:a first P-channel transistor;
a second P-channel transistor;
a first N-channel transistor;
a second N-channel transistor;
a first node coupled to a gate of the first P-channel transistor and a gate of the first N-channel transistor;
a second node coupled to a gate of the second P-channel transistor and a gate of the second N-channel transistor;
a third node coupled to a source of the first P-channel transistor;
a fourth node coupled to a drain of the first P-channel transistor and a source of the second P-channel transistor;
a fifth node coupled to a drain of the second P-channel transistor;
a sixth node coupled to a drain of the first N-channel transistor;
a seventh node coupled to a source of the first N-channel transistor and a drain of the second N-channel transistor; and
an eighth node coupled to a source of the second N-channel transistor;
wherein the second node, the third node, the fifth node, and the seventh node are arranged along a first line;
wherein the first node, the fourth node, the sixth node, and the eighth node are arrange along a second line, wherein the second line is parallel to the first line.

US Pat. No. 10,560,099

SEMICONDUCTOR APPARATUS USING SWING LEVEL CONVERSION CIRCUIT

SK hynix Inc., Icheon-si...

1. A semiconductor apparatus comprising:an input selection circuit configured to select one of a first input signal and a second input signal in response to a control signal and configured to output the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different from one another; and
a conversion circuit configured to generate an output signal, in response to the selection signal, wherein the output signal swings to a level substantially identical to a level of the second input signal,
wherein the input selection circuit comprises:
a first input circuit configured to transfer the first input signal to an output circuit;
a second input circuit configured to transfer the second input signal to the output circuit based on the control signal; and
the output circuit configured to perform at least one of an inverting operation and a resistive feedback inverting operation on the first and second input signals, received from the first and second input circuits, based on the control signal and output a result of the operation as the selection signal.

US Pat. No. 10,560,098

MECHANICAL RESONATOR BASED CASCADABLE LOGIC DEVICE

KING ABDULLAH UNIVERSITY ...

1. An apparatus, comprising:a resonator, including a beam having a first fixed end, a second fixed end, and a length between the first and second fixed ends;
a first electrode and a second electrode aligned along a first side of the beam;
a third electrode and a fourth electrode aligned along a second side of the beam and opposite the first and second electrodes;
a DC voltage source coupled to one of the first and second fixed ends of the beam;
wherein at least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.

US Pat. No. 10,560,095

IMPEDANCE-BASED PHYSICAL UNCLONABLE FUNCTION

Analog Devices, Inc., No...

1. An apparatus for providing an impedance based physically unclonable function (PUF), comprising:a first pair of resistors electrically connected in a first current path, the first pair of resistors having a first impedance ratio;
a second pair of resistors electrically connected in a second current path, the second pair of resistors having a second impedance ratio;
an analog-to-digital converter (ADC), configured to generate a plurality of bits based on:
a first voltage signal from the first current path that indicates the first impedance ratio; and
a second voltage signal from the second current path that indicates the second impedance ratio; and
processing circuitry configured to generate a PUF value based on the plurality of bits.

US Pat. No. 10,560,094

ISOLATION MODULE FOR USE BETWEEN POWER RAILS IN AN INTEGRATED CIRCUIT

Intel Corporation, Santa...

1. A system comprising:a processor circuit;
a power converter circuit coupled to the processor circuit and configured to provide, to the processor circuit, regulated DC power supply signals including first and second voltage signals;
wherein the processor circuit comprises a semiconductor die, the semiconductor die including first and second power domains configured to receive the first and second voltage signals, respectively, and wherein the processor circuit further comprises a first integrated inductor circuit and a first integrated capacitor circuit;
wherein each of the first and second power domains includes at least one power rail, and wherein each of the power rails is configured to provide different power signals to respective consumer circuits, and
wherein a first power rail in the first power domain is coupled to a second power rail using the first integrated inductor circuit and the first integrated capacitor circuit.

US Pat. No. 10,560,093

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first mode register configured to store a first selection termination control signal and a second selection termination control signal when a mode register write operation is performed;
a first termination circuit comprising an impedance value and configured to control the impedance value of the first termination circuit based on the first selection termination control signal and a termination control signal; and
a second termination circuit comprising an impedance value and configured to control the impedance value of the second termination circuit based on the second selection termination control signal and the termination control signal,
wherein the impedance values of the first and second termination circuits are controlled to be substantially equal to each other according to a logic level combination of the termination control signal.

US Pat. No. 10,560,091

SWITCH ASSEMBLY OF REACTIVE POWER COMPENSATION APPARATUS

LSIS CO., LTD., Anyang-s...

1. A switch assembly of a reactive power compensation apparatus, the switch assembly comprising:a support module;
a first switching module having a first stack structure perpendicular to the supporting module; and
a second switching module having a second stack structure perpendicular to the supporting module, the second switching module being connected in parallel with the first switching module,
wherein each of the first and second switching modules comprises:
a plurality of cooling plates stacked along a vertical direction with respect to the supporting module; and
a plurality of switches disposed between the plurality of cooling plates, and
wherein each of the plurality of cooling plates comprises: an engagement portion disposed on one side of an upper surface of each of the plurality of cooling plates to be located at a normal position by guiding the plurality of switches,
wherein the engagement portion comprises at least one or more engagement protrusions having a circular shape, and
wherein the at least one or more engagement protrusions are spaced apart by a radius of each of the plurality of switches from a center of each of the plurality of cooling plates.

US Pat. No. 10,560,088

TOTEM-POLE CIRCUIT DRIVER

FUJI ELECTRIC CO., LTD., ...

1. A totem-pole circuit driver for driving a totem-pole circuit including a high-side power device and a low-side power device which are cascade-connected, the totem-pole circuit driver comprising:a high-side drive circuit which drives the high-side power device;
a low-side drive circuit which drives the low-side power device;
a pulse generation circuit which receives a high-side input logic signal that has a first edge and a second edge, and generates a set signal for turning on the high-side power device and a reset signal for turning off the high-side power device, based respectively on the first edge and the second edge;
a level shift circuit which transmits the set signal and the reset signal to the high-side drive circuit;
a high-side potential detection circuit which detects a high-side reference potential;
a high-side potential determination circuit which
compares a value of the high-side reference potential detected by the high-side potential detection circuit with a reference voltage, and
outputs an event signal upon detecting that the value of the high-side reference potential exceeds the reference voltage; and
an on-pulse stop circuit which receives a low-side input logic signal, and validates or invalidates the low-side input logic signal based on the high-side input logic signal and the event signal, wherein
when the high-side input logic signal is at a low level, by which the high-side power device is turned off, and upon receiving the event signal,
the pulse generation circuit regenerates the reset signal, and
the on-pulse stop circuit invalidates the low-side input logic signal and outputs a signal at a low level, by which the low-side power device is turned off.

US Pat. No. 10,560,087

PASSIVE LEAKAGE MANAGEMENT CIRCUIT FOR A SWITCH LEAKAGE CURRENT

GE Aviation Systems Limit...

1. A passive leakage management circuit for a switch leakage current comprising:a switch that includes an input electrically coupled with a source of alternating current (AC) and an output electrically coupled with an electrical load, and is operable in a first operating mode, wherein the output supplies an AC output current provided to the input and having a first AC voltage, and in a second operating mode, wherein the output supplies an AC leakage current from the input and having a second AC voltage lower than the first AC voltage;
a rectifying module electrically coupled with the switch output and that rectifies the AC output current to a direct current (DC) output current during the first operating mode and the second operating mode;
a first current path that receives the DC output current and includes a first transistor that conducts current along the first current path based on the switch output; and
a leakage current path that receives the DC output current and includes a second transistor that conducts current along the leakage current path based on the first transistor not conducting current;
wherein at least one of the first current path or leakage current path conducts current based on the switch output, without an additional power source beyond the switch output, and independent of the first or second operating mode of the switch, and wherein only one of the first current path or leakage current path conducts current when the switch is coupled with the source of alternating current.

US Pat. No. 10,560,085

APPARATUSES FOR REDUCING OFF STATE LEAKAGE CURRENTS

Micron Technology, Inc., ...

1. An apparatus comprising:a switch including first through fourth transistors,
the first and second transistors configured to be in an off state when the switch is in the off state based on the first transistor controlled by a first reference voltage and the second transistor controlled by a second reference voltage,
the third and fourth transistors configured to be in a first conductive state when the switch is in the off state based on the third and fourth transistors controlled by a third reference voltage that is less than the first reference voltage and greater than the second reference voltage,
wherein the first reference voltage is coupled to a gate of the fourth transistor when the switch is in an on state, and
wherein the third reference voltage is coupled to the gate of the fourth transistor when the switch is in the off state.

US Pat. No. 10,560,084

LEVEL SHIFT CIRCUIT

Toshiba Memory Corporatio...

1. A level shift circuit comprising:a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;
a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain;
a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain;
a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain;
a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;
a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and
a potential adjusting circuit that is electrically connected to at least the second node, and
wherein the potential adjusting circuit is a charging circuit electrically connected to the second node,
the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node,
the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period.

US Pat. No. 10,560,083

CONTROL DEVICE FOR POWER SUPPLY LINE

1. A control device to be arranged between two portions of an electrical power supply line, the device comprising:a bipolar transistor comprising a wide bandgap semiconductor material and having its emitter connected to one portion of the power supply line, its collector connected to another portion of the power supply line; and
a control circuit connected to the base of said transistor and configured to operate in an open loop without feedback.

US Pat. No. 10,560,081

METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTERCONNECT

Intel Corporation, Santa...

1. An interconnect apparatus, comprising:a clock signal generator to generate a clock signal;
a reference voltage shifter to:
shift a reference voltage of the clock signal by a first test voltage at an operational speed of the interconnect; and
shift the reference voltage by a second test voltage;
an error rate detector to:
measure an error rate of the first test voltage;
compare the error rate of the first test voltage to an error rate of the second test voltage; and
select an optimal test voltage; and
an operational voltage selector to select an operational reference voltage of the clock signal based at least in part on the optimal test voltage.

US Pat. No. 10,560,080

DUTY CYCLE CORRECTION

NXP B.V., Eindhoven (NL)...

1. A duty cycle correction circuit, comprising:an input stage to reduce rise time or fall time of an input signal;
an output stage amplifier to amplify an output signal from the input stage to a preselected voltage swing and a target common voltage, wherein an input of the output stage is coupled to a fix voltage reference; and
a feedback component including a feedback amplifier and a low pass filter to filter noise and to correct duty cycle of the signal from an output of the output stage amplifier.

US Pat. No. 10,560,078

ELECTRONIC DEVICE

SK hynix Inc., Gyeonggi-...

1. An electronic device comprising:a ramp signal generation block configured to generate a ramp signal on a basis of a ramp code signal;
a slope adjustment block configured to adjust a slope of the ramp signal so that the ramp signal has a second slope decreased by the first level from a first slope corresponding to an analog gain, on a basis of a gain code signal, the second slope corresponding to decreasing the first slope by the first level;
a first slope correction block configured to basically increase the slope of the ramp signal by the first level and optionally decrease the slope of the ramp signal in a range corresponding to the first level, on a basis of a first correction code signal; and
a second slope correction block configured to optionally increase the slope of the ramp signal by a second level on a basis of a second correction code signal,
wherein the second slope correction block includes at least one second resistor part electrically coupled in parallel to an output terminal of the ramp signal, and
the second resistor part reflects a second resistance value corresponding to the second level in the output terminal on the basis of the second correction code signal.

US Pat. No. 10,560,077

CR OSCILLATOR

TOSHIBA MEMORY CORPORATIO...

1. A CR oscillator comprising:a first logic inversion unit including odd-number stages of logic inversion elements connected in series;
a second logic inversion unit including odd-number stages of logic inversion elements connected in series, the second logic inversion unit being connected to a latter stage of the first logic inversion unit; and
two or more resistors and a capacitor connected in series between an output node of the first logic inversion unit and an output node of the second logic inversion unit,
wherein an electric potential in accordance with an electric potential of an intermediate node between the two or more resistors is supplied to an input node of the first logic inversion unit,
wherein the two or more resistors comprise a first resistor and a second resistor connected in series between the output node of the first logic inversion unit and one terminal of the capacitor,
the electric potential of the intermediate node is an electric potential of a connection node of the first resistor and the second resistor,
a ratio of a resistance value of the first resistor and a resistance value of the second resistor is set so that an electric potential of the input node of the first logic inversion unit is equal to or lower than a power-supply electric potential of the first logic inversion unit but equal to or higher than a ground electric potential of the first logic inversion unit, and
the ratio is set so that expressions (1) and (2) are established, wherein the ratio is X, the power-supply electric potential of the first logic inversion unit and the second logic inversion unit is V, and a threshold voltage of the first logic inversion unit is Vth:

US Pat. No. 10,560,076

FREQUENCY GENERATION IN A QUANTUM CONTROLLER

Quantum Machines, (IL)

1. A system comprising:a quantum controller comprising quantum control pulse generation circuitry, phase parameter generation circuitry, time-tracking circuitry, and signal generation circuitry, wherein:
the quantum control pulse generation circuitry is operable to generate a sequence of two quantum control pulses;
the phase parameter generation circuitry is operable to determine, based on an output of the time-tracking circuitry, a value of a phase parameter that corresponds to a phase of an oscillating signal relative to a reference time;
the signal generation circuitry is operable to:
at the reference time, begin generation of the oscillating signal at a first frequency for modulation of a first of the two quantum control pulses;
at a second time after the reference time, change the oscillating signal to a second frequency for modulation of the second quantum control pulse, wherein the phase of the oscillating signal at the second time is determined by the value of the phase parameter such that the phase of the oscillating signal is as it would have been if the oscillating signal had been oscillating at the second frequency continuously since the reference time.

US Pat. No. 10,560,075

FPGA CONFIGURED VECTOR NETWORK ANALYZER FOR MEASURING THE Z PARAMETER AND S PARAMETER MODELS OF THE POWER DISTRIBUTION NETWORK IN FPGA SYSTEMS

1. A method for measuring the phase of periodic variations of the voltage of a power supply domain of a programmable logic device containing configurable blocks powered from the power supply domain, comprising:configuring the programmable logic device to implement a current load generator that consumes a periodic varying electric current from a power supply domain the said periodic varying electric current having an activate feature and a frequency programming feature;
configuring the programmable logic device to implement a ring oscillator containing configurable blocks powered from said power supply domain;
configuring the programmable logic device to implement a phase and phase modulation measurement function for said ring oscillator;
programming a frequency value of said periodic varying electric current, activating said periodic varying electric current, measuring the phase and phase modulation of said ring oscillator, calculating the phase of the voltage variation of the power supply domain by computations including the measured phase and phase modulation of said ring oscillator.

US Pat. No. 10,560,071

RADIO FREQUENCY SIGNAL ATTENUATOR AND METHOD OF OPERATION THEREOF

STMICROELECTRONICS SA, M...

1. An attenuator, comprising:a plurality of capacitors including a plurality of circuits coupled in series, wherein a respective circuit comprises:
a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and
a second capacitor connected between the output node of the respective circuit and a reference node, wherein the output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit, and
a third capacitor directly connected between the output node of the last circuit and the reference node; and
a plurality of selectors, wherein the respective circuit is associated with a respective selector, wherein the respective selector is coupled between the output node of the respective circuit and an output node of the attenuator, wherein attenuation values of the attenuator depend only on the capacitance values of the plurality of capacitors.

US Pat. No. 10,560,069

ELASTIC WAVE APPARATUS

MURATA MANUFACTURING CO.,...

1. An elastic wave apparatus comprising:a multilayer substrate including a plurality of wiring layers;
a plurality of filter devices disposed on the multilayer substrate and connected to a common node;
an antenna terminal to be connected to an antenna and to the common node;
a first inductor connected to the antenna terminal; and
a second inductor connected between one of the plurality of filter devices and the common node; wherein
the first inductor is disposed on at least one of the plurality of wiring layers;
the second inductor is disposed on a wiring layer which is different from the at least one of the plurality of wiring layers on which the first inductor is disposed; and
the first and second inductors overlap each other at least partially as viewed from above.

US Pat. No. 10,560,068

MULTIPLEXER

TAIYO YUDEN CO., LTD., T...

1. A multiplexer comprising:a first substrate having a first surface;
a second substrate having a second surface facing the first surface across an air gap;
a first filter including a plurality of first resonators, the plurality of first resonators being located on the first surface and connected between a common terminal and a first terminal;
a second filter including a plurality of second resonators, the plurality of second resonators being located on the second surface and connected between the common terminal and a second terminal, at least a part of a first resonator connected in series between the common terminal and the first terminal and closest to the common terminal among the plurality of first resonators overlapping in plan view with at least a part of a second resonator connected in series between the common terminal and the second terminal and closest to the common terminal among the plurality of second resonators, at least one of first resonators other than the first resonator closest to the common terminal of the plurality of first resonators not overlapping with the plurality of second resonators in plan view, at least one of second resonators other than the second resonator closest to the common terminal of the plurality of second resonators not overlapping with the plurality of first resonators in plan view.

US Pat. No. 10,560,065

PIEZOELECTRIC RESONATOR MANUFACTURING METHOD AND PIEZOELECTRIC RESONATOR

MURATA MANUFACTURING CO.,...

1. A piezoelectric resonator comprising:a piezoelectric thin film;
a support substrate located at a back surface side of the piezoelectric thin film;
an adhesive layer located at a surface side of the support substrate that faces the back surface side of the piezoelectric thin film; and
a support layer that fixes the piezoelectric thin film to the support substrate so as to provide a space between the piezoelectric thin film and the support substrate; wherein
a corner portion of the support layer at a side of the support substrate, which is exposed to the space, includes a recess defined by a cut in the corner portion;
the support substrate includes an adhered portion at which the support layer and the support substrate are adhered to one another, and a non-adhered portion at which the support layer and the support substrate are not adhered to one another; and
a thickness of a portion of the adhesive layer located at the adhered portion is thinner than a thickness of another portion of the adhesive layer located at the non-adhered portion.

US Pat. No. 10,560,064

DIFFERENTIAL AMPLIFIER INCLUDING CANCELLATION CAPACITORS

TEXAS INSTRUMENTS INCORPO...

1. An operational amplifier input stage comprising:a differential amplifier comprising:
a pair of driver metal oxide semiconductor field effect transistors (MOSFETs);
a first current source including a first pair of bipolar junction transistors (BJTs);
a parasitic capacitor coupled to a voltage source and to a common emitter node, the common emitter node coupled to emitters of the BJTs in the second pair of BJTs; and
a translinear loop coupled to the first current source and including a second pair of BJTs, a first diode coupled to the second pair of BJTs, a first resistor coupled to the first diode, a second diode coupled to the first resistor, a third pair of BJTs coupled to the second diode, a third diode coupled to the third pair of BJTs, a second resistor coupled to the third diode, and a fourth diode coupled to the second resistor;
a transconductance linearization circuit, comprising:
a second current source comprising a fourth pair of BJTs, the fourth pair of BJTs in a cascoded configuration;
at least one translinear loop coupled to the second current source and comprising a plurality of BJTs; and
a BJT positioned between the at least one translinear loop and the first current source, a base of the BJT coupled to bases of the BJTs in the first pair of BJTs; and
a cancellation capacitor coupled to the second current source and to the common emitter node.

US Pat. No. 10,560,060

LINEAR CMOS PA WITH LOW QUIESCENT CURRENT AND BOOSTED MAXIMUM LINEAR OUTPUT POWER

Qorvo US, Inc., Greensbo...

1. A power amplifier (PA) system comprising:a transmit path configured to amplify an input radio frequency (RF) signal, the transmit path comprising:
a first tank circuit; and
a PA stage; and
control circuitry configured to:
detect a power level associated with the input RF signal;
control a quality factor (Q) of the first tank circuit based on a first function of the power level; and
control a first bias signal provided to the PA stage based on a third function of the power level;
wherein the first function and the third function of the power level are polynomial functions.

US Pat. No. 10,560,059

POWER AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A power amplifier module comprising:an amplifier that amplifies an input signal and outputs an amplified signal from an output terminal;
a matching circuit disposed between the output terminal of the amplifier and a subsequent circuit;
a choke inductor, wherein a power supply voltage is applied to a first end of the choke inductor; and
a first attenuation circuit disposed between the output terminal of the amplifier and a second end of the choke inductor, the first attenuation circuit attenuating a second harmonic of the amplified signal, wherein:
the first attenuation circuit includes:
a first inductor, wherein a first end of the first inductor is connected to the output terminal of the amplifier and a second end of the first inductor is connected to the second end of the choke inductor, and
a first capacitor, wherein a first end of the first capacitor is connected to the second end of the first inductor and a second end of the first capacitor is grounded,
the matching circuit includes:
a second attenuation circuit that attenuates frequencies greater than a fundamental frequency of the amplified signal; and
a filter, and
the second attenuation circuit is a low pass filter,
the first attenuation circuit and the second attenuation circuit are not included as part of a chip of the amplifier.

US Pat. No. 10,560,058

METHOD OF EQUALIZING CURRENTS IN TRANSISTORS AND FLOATING CURRENT SOURCE

1. A current equalizing circuit comprising:a first supply voltage (VDD) and a second supply voltage (VSS);
a first P-channel Metal Oxide Silicon Field Effect Transistor (PMOSFET) having a first PMOSFET gate terminal coupled with a first node, a first PMOSFET source terminal coupled with VDD, and a first PMOSFET drain terminal coupled with a third node;
a second PMOSFET having a second PMOSFET gate terminal coupled with a fifth node, a second PMOSFET source terminal coupled with the third node, and a second PMOSFET drain terminal coupled with a fourth node;
a first N-channel Metal Oxide Silicon Field Effect Transistor (NMOSFET) having a first NMOSFET gate terminal coupled with a second node, a first NMOSFET source terminal coupled with VSS, and a first NMOSFET drain terminal coupled with the fourth node;
a second NMOSFET having a second NMOSFET gate terminal coupled with a sixth node, a second NMOSFET source terminal coupled with the fourth node, and a second NMOSFET drain terminal coupled with the third node;
a first regulating circuit comprising a first regulating circuit input port, and a first regulating circuit output port;
a second regulating circuit comprising a second regulating circuit input port, and a second regulating circuit output port;
wherein the first regulating circuit input port communicates with the third node, and wherein the first regulating circuit output port communicates with the first node and the fifth node; and
wherein the second regulating circuit input port communicates with the fourth node, and where in the second regulating circuit output port communicates with the second node and the sixth node.

US Pat. No. 10,560,056

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a differential circuit;
a bias circuit configured to supply a bias current to the differential circuit;
a reference voltage generation circuit configured to output a reference voltage to the bias circuit;
a switch configured to control supply of a power supply voltage to the reference voltage generation circuit; and
a holding circuit configured to hold the reference voltage,
wherein the holding circuit comprises a first transistor and a capacitor,
wherein the bias circuit comprises a second transistor,
wherein the first transistor comprises an oxide semiconductor film comprising a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the reference voltage generation circuit,
wherein the other of the source and the drain of the first transistor is electrically connected to the bias circuit,
wherein the capacitor is electrically connected to the other of the source and the drain of the first transistor,
wherein the first transistor is configured to be turned off while the differential circuit operates and a current flows in the second transistor, and
wherein the switch is configured to stop the supply of the power supply voltage to the reference voltage generation circuit while the differential circuit operates and the current flows in the second transistor.

US Pat. No. 10,560,055

VOLTAGE MODE POWER COMBINER FOR RADIO FREQUENCY LINEAR POWER AMPLIFIER

Skyworks Solutions, Inc.,...

1. A radio frequency power combining amplifier circuit with a circuit input and a circuit output, comprising:a first amplifier connected to the circuit input and to a first bias input;
a first output matching network connected to an output of the first amplifier and to the circuit output, the first output matching network and the first amplifier being optimized for small signal linearity;
a second amplifier connected to the circuit input and to a second bias input, the first and second bias inputs being set such that, when a voltage of an input signal to the circuit input is at a first level, the first amplifier is on and the second amplifier is off and, when a voltage of the input signal is at a second level, the first amplifier is saturated and the second amplifier is on; and
a second output matching network connected to an output of the second amplifier and to the circuit output, the second output matching network and the second amplifier being optimized for maximum linear output power.

US Pat. No. 10,560,054

CIRCUIT SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A circuit system, comprising an operational amplification circuit, whereinthe operational amplification circuit comprises:
N stages of operational amplification units that are cascaded, N being greater than or equal to 2, wherein each of the N stages comprises an input terminal and an output terminal and the N stages include a 1st stage, an Nth stage, and an ith stage, wherein
an input terminal of the 1st stage is an input terminal of the operational amplification circuit and is configured to receive an initial input signal,
an output terminal of the Nth stage is an output terminal of the operational amplification circuit, and
the output terminal of the ith stage is connected to the input terminal of the (i+1)th stage, so as to provide an input signal for the (i+1)th stage, wherein i is 1, 2, . . . , or N?1; and
a feedback channel from the output terminal of the Nth stage to the input terminal of each of the N stages of operational amplification units exists, wherein the feedback channel is configured to facilitate a transmission of an output signal of the Nth stage of operational amplification unit to the input terminal of each of the N stages; and, wherein
the operational amplification circuit is a dual-input and single-output operational amplification circuit for receiving a differential signal and driving a single-terminal load circuit;
the Nth stage comprises an operational amplifier, and
the Nth stage further comprises a phase inverter disposed on the feedback channel, the phase inverter and the operational amplifier in the Nth stage of operational amplification unit constituting a pseudo-differential structure.

US Pat. No. 10,560,053

DIGITAL FRACTIONAL FREQUENCY DIVIDER

Qorvo US, Inc., Greensbo...

1. Frequency synthesizer circuitry comprising:multi-phase clock generator circuitry configured to:
receive an input clock signal; and
generate a plurality of multi-phase clock signals based on the input clock signal such that a frequency of each one of the plurality of multi-phase clock signals is equal to a frequency of the input clock signal, a duty cycle of each one of the plurality of multi-phase clock signals is equal to a duty cycle of the input clock signal, and each one of the plurality of multi-phase clock signals has a different phase shift with respect to the input clock signal;
frequency divider circuitry coupled to the multi-phase clock generator circuitry and configured to:
receive the input clock signal; and
generate a reference signal based on the input clock signal such that a frequency of the reference signal is lower than the frequency of the input clock signal and a duty cycle of the reference signal is different from the duty cycle of the input clock signal;
signal retiming circuitry coupled to the multi-phase clock generator circuitry and the frequency divider circuitry and configured to:
receive the reference signal and the plurality of multi-phase clock signals; and
generate a plurality of retiming signals, each based on the reference signal and a different one of the plurality of multi-phase clock signals such that a frequency of each one of the plurality of retiming signals is equal to the frequency of the reference signal, a duty cycle of each one of the plurality of retiming signals is equal to the duty cycle of the reference signal, and a phase of each one of the plurality of retiming signals is shifted with respect to the reference signal by an amount determined by the one of the plurality of multi-phase clock signals used to generate the retiming signal; and
signal combining circuitry configured to combine two retiming signals of the plurality of retiming signals to generate an output clock signal such that a frequency of the output clock signal is equal to the frequency of the reference signal and a duty cycle of the output clock signal is equal to the duty cycle of the input clock signal.

US Pat. No. 10,560,052

PHOTOVOLTAIC MODULE CAPABLE OF OUTPUTTING AC VOLTAGE WITHOUT CONVERTING LEVEL OF DC VOLTAGE

LG ELECTRONICS INC., Seo...

1. A photovoltaic module, comprising:a solar cell module including a plurality of solar cells;
a capacitor unit to receive a direct current (DC) voltage from the solar cell module and to store the DC voltage output from the solar cell module;
an inverter unit to convert the DC voltage stored in the capacitor unit into an alternating current (AC) voltage without converting a level of the DC voltage received from the solar cell module;
a controller to control the inverter unit;
an input current detector to detect an input current flowing into the capacitor unit; and
an input voltage detector to detect an input voltage of both terminals of the capacitor unit,
wherein the solar cell module outputs the DC voltage having a level higher than a peak value of a grid voltage,
wherein the controller calculates a maximum power for the solar cell module and controls the inverter unit to output the AC voltage using a DC voltage corresponding to the maximum power, and
wherein the plurality of solar cells include multi-cutting cells, respectively.

US Pat. No. 10,560,051

PHOTOVOLTAIC APPARATUS

Sumitomo Electric Industr...

1. A photovoltaic apparatus configured to cause a photovoltaic panel to perform operation of tracking the sun, the photovoltaic apparatus comprising:a position changeable part configured to change a position of the photovoltaic panel so as to cause the photovoltaic panel to perform the tracking operation; and
a function part, which has a housing accommodating electronic components therein, located in an area of a back surface side opposite to a light receiving surface of the photovoltaic panel where sunlight is blocked, the function part being supported by an arm extending away from the back surface side whereby a relative positional relation between the function part and the photovoltaic panel is fixed via the arm, wherein the arm includes an arm part which is hollow, wherein
with respect to a direction perpendicular to the light receiving surface, a moment of the photovoltaic panel by gravity centering on the position changeable part and a moment of the function part by gravity centering on the position changeable part are configured to act in reverse directions to each other, and
a wire passing through a hollow portion of the arm part, the wire connecting the position changeable part and the function part with each other, connecting the function part and the photovoltaic panel with each other, or connecting the photovoltaic panel and the position changeable part with each other.

US Pat. No. 10,560,050

INNOVATIVE ENERGY GENERATING PHOTOVOLTAIC AWNING

EvoluSun, Inc., San Jose...

21. A photovoltaic awning comprising:a plurality of photovoltaic panels, each photovoltaic panel coupled to adjacent photovoltaic panels and arranged between a first and a last photovoltaic panel;
a base of the awning, providing support to permit mounting of the awning from the base at a single end, coupled to the first photovoltaic panel;
a lead arm of the awning coupled to the last photovoltaic panel;
a rotating drum, comprising at least one wire interconnected among the photovoltaic panels and an anchoring support mechanism anchored to the awning, so as to facilitate deploying the awning solely from the base, wherein as the lead arm moves away from and toward the base, the rotating drum simultaneously rotates to wind and unwind, respectively, the wire through the panels ensuring constant tension and allowing the photovoltaic panels to stay substantially in a specified plane.

US Pat. No. 10,560,048

PHOTOVOLTAIC ROOFING SYSTEMS WITH BOTTOM FLASHINGS

CertainTeed Corporation, ...

1. A photovoltaic roofing system disposed on a roof deck having a top end, a bottom end, a first lateral side and a second lateral side opposing the first lateral side, the photovoltaic roofing system comprising:a plurality of contiguously-disposed, discrete photovoltaic roofing elements, the photovoltaic roofing elements being photovoltaic roofing shingles, photovoltaic roofing tiles, photovoltaic roofing shakes or photovoltaic roofing slates, each of the photovoltaic roofing elements being disposed directly against the roof deck or directly against one or more sheets of membrane or underlayment disposed against the roof deck, the contiguously-disposed plurality of photovoltaic roofing elements defining a bottom edge, the contiguously-disposed photovoltaic roofing elements including one or more bottom end photovoltaic roofing elements disposed in a row at the bottom edge thereof, each of the bottom end photovoltaic roofing elements having a bottom end;
one or more bottom flashing elements disposed along the bottom edge of the contiguously-disposed plurality of photovoltaic roofing elements such that the one or more bottom flashing elements extend along the entire bottom edge of the contiguously-disposed plurality of photovoltaic roofing elements, each of the one or more bottom flashing elements having an upward-facing surface, a top end and a bottom end, and a first lateral end and a second lateral end, the top end of each of the one of more bottom flashing elements being substantially disposed under at least one of the bottom end photovoltaic roofing elements at the bottom end thereof such that each of the bottom end photovoltaic roofing elements is disposed on one or more of the bottom flashing elements, and such that the bottom end of each of the one or more bottom flashing elements protrudes beyond the bottom edge of the contiguously-disposed photovoltaic roofing elements, and such that the entire bottom edge of the contiguously-disposed photovoltaic roofing elements is disposed over the one or more bottom flashing elements, wherein each of the one or more bottom flashing elements comprises
a top end piece having a top end forming the top end of the bottom flashing element, the top end piece being affixed to the roof; and
a bottom end piece separate from the top end piece, the bottom end piece having a bottom end forming the bottom end of the bottom flashing element, the bottom end piece not being affixed to the roof or to the top end piece, the bottom end piece being removably interlocked with the top end piece so as to hold it in position relative to the top end piece, wherein the plurality of photovoltaic roofing elements do not extend to the bottom end piece of any of the bottom end flashing elements; and
a plurality of non-photovoltaic roofing elements disposed in a row extending along the entirety of the bottom end of the one or more bottom flashing elements, each non-photovoltaic roofing element having an exposure zone at a bottom end thereof and a headlap zone at a top end thereof, the headlap zone of each non-photovoltaic roofing element being disposed under one or more of the bottom end flashing elements at the bottom end thereof, such that each of the bottom flashing elements is disposed on the headlap zone of one or more of the non-photovoltaic roofing elements, and each of the non-photovoltaic roofing elements of the row is overlapped by one or more of the bottom end flashing elements, wherein the one or more non-photovoltaic roofing elements disposed along the bottom end of the one or more bottom flashing elements are affixed to the roof deck by one or more fasteners, the one or more fasteners being disposed under bottom end piece(s) of the one or more bottom end flashing elements.

US Pat. No. 10,560,046

MOTOR CONTROL DEVICE

JTEKT CORPORATION, Osaka...

1. A motor control device that controls an electric motor that has three-phase motor coils in two systems with a phase difference of 60 degrees, 180 degrees, or 300 degrees between the two systems via a first drive circuit that drives three-phase motor coils in a first system, which is one of the two systems, and a second drive circuit that drives three-phase motor coils in a second system, which is the other system, the first drive circuit and the second drive circuit each having sets of upper and lower switching elements for three phases, the motor control device comprising:a setting unit that sets a two-phase current command value corresponding to a target current value for a current that is to flow through the electric motor;
an actual current value computation unit that computes an actual two-phase current value that matches a current that flows through the electric motor;
a first PWM count computation unit that computes a first PWM count for each of three phases in the first system in each PWM cycle on the basis of the two-phase current command value and the actual two-phase current value; and
a second PWM count computation unit that computes a second PWM count for each of three phases in the second system in each PWM cycle in accordance with the phase difference on the basis of the first PWM count for each of the three phases in the first system, wherein
the upper and lower switching elements for each phase in one of the first system and the second system are controlled in accordance with a first pattern in which the upper and lower switching elements are varied in an order of an upper on state, a lower on state, and the upper on state from a time of start of PWM cycles, and the upper and lower switching elements for each phase in the other system are controlled in accordance with a second pattern in which the upper and lower switching elements are varied in an order of a lower on state, an upper on state, and the lower on state from a time of start of PWM cycles.

US Pat. No. 10,560,045

DRIVING DEVICE FOR MULTI-AXIS COMMON-MODE VOICE COIL MOTOR

INDUSTRIAL TECHNOLOGY RES...

1. A driving device for multi-axis common-mode voice coil motor, comprising:a control signal processing interface, configured to generate a plurality of control signals and a plurality of command signals; and
a plurality of drive-stage circuits, configured to receive the control signals and the command signals respectively, and each of the drive-stage circuits being connected to one end of one of coils of a voice coil motor and comprising a half-bridge switch circuit, wherein the drive-stage circuit controls the half-bridge switch circuit to generate a driving current to drive the coil according to the control signal;
wherein the drive-stage circuit implements a current feedback mechanism to compare a feedback signal of the driving current for driving the coil with the command signal to generate an adjustment signal and adjusts the driving current according to the adjustment signal, whereby the driving current tracks the command signal.

US Pat. No. 10,560,043

FLOATING DEVICE GENERATOR

1. A floating power generator, comprising:a boat or vessel having at least one hull;
a frame connected to the boat or vessel and extending upwardly from the boat or vessel;
a paddle wheel supported by the frame at an elevated position of rotation above the at least one hull of the boat or vessel;
an electrical system for generating electrical power and providing a power source, the electrical system located on the boat or vessel, the electrical system comprising:
an electrical generator connected to and driven by the paddle wheel, the electrical generator being located on a side of the paddle wheel and support by the frame at the elevated position above the at least one hull of the boat or vessel;
a generator controller connected to the electrical generator to control the operation of the electrical generator;
a rotational speed sensor configured for detecting the rotational speed of the paddle wheel;
a water flow speed sensor configured for detecting a water flow speed relative to the floating power generator;
a power meter connected to the electrical generator, the power meter serving as a power output for the electrical system; and
a computer for receiving inputs from the rotational speed sensor, the water flow speed sensor, and the power meter, and generating an output signal controlling the generator controller.

US Pat. No. 10,560,042

TURBOCOMPRESSOR COMPRISING A COMPRESSOR MOTOR GENERATING REGENERATIVE ELECTRIC POWER BY REGENERATIVE DRIVING CAPABLE OF DRIVING A COMPRESSOR MOTOR

PANASONIC INTELLECTUAL PR...

1. A turbocompressor apparatus that is connectable to a power source, comprising:a turbocompressor including:
a rotary shaft;
a shaft bearing that supports the rotary shaft;
a compression mechanism that compresses and discharges a cooling medium by rotation of the rotary shaft;
a compressor motor that rotates the rotary shaft; and
a lubricant supply passage through which a lubricant is supplied to the shaft bearing,
a lubrication pump including a pump motor that generates driving force for supplying the lubricant to the shaft bearing through the lubricant supply passage;
a converter that performs electric power conversion between a voltage of the power source and a direct-current voltage of a direct-current voltage unit in a case where electric power is being supplied from the power source to the converter;
a first inverter that performs electric power conversion between the direct-current voltage and a first alternating-current voltage vector of the compressor motor; and
a second inverter that performs electric power conversion between the direct-current voltage and a second alternating-current voltage vector of the pump motor,
the compressor motor generating regenerative electric power by regenerative driving and the pump motor being driven by the regenerative electric power in a case where supply of electric power from the power source to the converter is being cut off,
wherein the turbocompressor apparatus performs a normal operation in which the pump motor is driven by using the voltage of the power source in a case where electric power is being supplied from the power source to the converter;
the turbocompressor apparatus performs a first decelerating operation in which an amplitude of the first alternating-current voltage vector is set equal to or smaller than a value that is R1 times the direct-current voltage in a case where supply of electric power from the power source to the converter is being cut off and where the amplitude of the first alternating-current voltage vector is equal to or larger than a first threshold amplitude; and
the first threshold amplitude is equal to or larger than an amplitude of the second alternating-current voltage vector in the normal operation, R1 is an upper limit value of a ratio of the amplitude of the first alternating-current voltage vector to the direct-current voltage obtained in a case where the first inverter operates in a linear region, and the linear region of the first inverter is an operation region in which the amplitude of the first alternating-current voltage vector linearly changes in theory relative to the direct-current voltage.

US Pat. No. 10,560,040

HARVESTING ENERGY FROM FLUID FLOW

Saudi Arabian Oil Company...

1. An elastic bluff body, comprising:an elastic mount with a central axis;
a conical bluff body with a central axis, the conical bluff body fixedly attached to the elastic mount, the central axis of the elastic mount and the central axis of the conical bluff body being aligned, the conical bluff body being configured to generate vortex shedding when the elastic mount orients the conical bluff body in a flow-line traverse to a fluid flow and vibrates in response to the vortex shedding, wherein the conical bluff body comprises a permanent magnet or electromagnet; and
a harvester coupled to the conical bluff body and aligned with the central axis of the conical bluff body, the harvester comprising a cylinder arranged outside of and aligned with the central axis of the conical bluff body, and a metallic coil circling a circumference of the cylinder, the harvester configured to generate power above a specified threshold in response to the vibration.

US Pat. No. 10,560,038

HIGH TEMPERATURE DOWNHOLE POWER GENERATING DEVICE

Saudi Arabian Oil Company...

1. A high temperature power generating device, the device comprising:a power generator including a first material of one polarity and a second material that is fixed in position relative to the first material and is of opposite polarity of the first material, wherein the first material is configured to be propelled toward the second material based on motion of the high temperature downhole power generator so that the two materials have a maximized point of contact to generate maximum power;
at least one electrode that is connected to the first material or second material;
a bridge rectifier connected to the at least one electrode to transform the power generated into direct current from alternating current;
a storage unit for storing the power generated by the power generator;
a first housing for housing the power generator, the electrode, and the bridge rectifier, wherein the first housing comprises a polymeric material; and
a second housing for housing the storage unit, wherein the second housing comprises a material selected from the group consisting of certain solids, transition metals, as well as high strength alloys and/or compounds of the transition metals, and high temperature dewars.

US Pat. No. 10,560,036

POWER CONVERSION DEVICE FOR RELIABLE CONTROL OF CIRCULATING CURRENT WHILE MAINTAINING VOLTAGE OF A CELL

MITSUBISHI ELECTRIC CORPO...

1. A power conversion device which converts power between a DC circuit and an AC circuit, the power conversion device comprising:a plurality of leg circuits which correspond to respective phases of the AC circuit and are connected in parallel between common first and second DC terminals,
each leg circuit including:
a plurality of converter cells cascaded to one another and each including an energy storage; and
at least one inductor connected in series to the plurality of converter cells,
each of a plurality of specified converter cells which are some of the plurality of converter cells included in each leg circuit including:
a capacitor as the energy storage;
first and second switching elements connected in parallel to the capacitor and connected in series to each other; and
third and fourth switching elements connected in parallel to the capacitor and connected in series to each other,
the capacitor being capable of being charged and discharging through a connection node of the first and second switching elements and a connection node of the third and fourth switching elements; and
a control device which controls operations of the plurality of converter cells included in each leg circuit,
the control device controlling operations of the first and second switching elements of each specified converter cell based on a circulating current which circulates through each leg circuit, wherein the first and the second switching elements are exclusively used to control the circulating current,
the control device controlling operations of the third and fourth switching elements of each specified converter cell based on a voltage of the capacitor of each specified converter cell, wherein the third and fourth switching elements are exclusively used to control a difference between a voltage of the cell capacitor and a command value thereof to zero.

US Pat. No. 10,560,034

AC-TO-DC CHARGE PUMP HAVING A CHARGE PUMP AND COMPLIMENTARY CHARGE PUMP

RFMicron, Inc., Austin, ...

1. An AC-to-DC charge pump comprising:a charge pump operable to convert an AC (alternating current) input voltage into a DC (direct current) voltage, wherein the charge pump includes a current-source-biased N-channel MOSFET diode and a current-source-biased P-channel MOSFET diode, wherein the current-source-biased N-channel MOSFET diode includes:
a first N channel MOSFET;
a second N channel MOSFET; and
a capacitor, wherein:
gates of the first and second N channel MOSFETs are coupled together,
sources of the first and second N channel MOSFETs are coupled together to provide a cathode of the current-source-biased N-channel MOSFET diode;
a drain of the first N channel MOSFET is coupled to a common connection of the gates to receive a bias current,
a drain of the second N channel MOSFET provides an anode of the current-source-biased N-channel MOSFET diode; and
the capacitor is coupled between the drain of the second N channel MOSFET and the common connection of the gates; and
a complimentary charge pump operable to convert the AC input voltage into a complimentary DC voltage, wherein a magnitude of the DC voltage is substantially equal to a magnitude of the complimentary DC voltage, wherein the charge pump is coupled to the complimentary charge pump to add the DC voltage and the complimentary DC voltage to produce an output voltage, which has a middle rail that is coupled to a negative leg (VINN) of the AC input voltage, wherein the middle rail has a common-mode voltage (VMID), and wherein the common: mode voltage is shared by the negative leg and a positive leg (VINP) of the AC input voltage.

US Pat. No. 10,560,033

SOLAR HYBRID SOLUTION FOR SINGLE PHASE STARTING CAPACITOR MOTOR APPLICATIONS

SunTech Drive, LLC, Boul...

1. A system comprising:an induction-type AC electric motor having a starting winding, and a run winding;
an AC input connection;
a multiphase variable frequency motor (VFD) drive having at least a first and a second phase output;
a switching apparatus having at least a first and a second position;
wherein with the switching apparatus in the first position, a first output of a variable frequency motor drive is coupled to the run winding of the AC electric motor, and a second output of the variable frequency motor drive is coupled to the start winding of the AC electric motor; and
with the switching apparatus in the second position, the run winding of the AC electric motor is coupled to the AC input connection and the start winding of the AC electric motor is coupled through a capacitor and start switch to the AC input connection;
wherein, with the switching apparatus in the first position, the second output of the VFD is configured to discontinue driving the start winding of the motor after the motor begins rotating.

US Pat. No. 10,560,031

BI-DIRECTIONAL DC TO DC SIGNAL CONVERSION USING OBSERVER BASED ESTIMATED CURRENT SENSOR

Hamilton Sundstrand Corpo...

1. A bi-directional DC to DC converter, comprising:a DC to DC conversion circuit; and
a controller operatively connected to the conversion circuit to control a voltage output of the conversion circuit, the controller including an observer based estimated current sensor module configured to simulate a physical current sensor by inputting an estimated output current feedback inner state signal ??o into a voltage output command feedback loop of the controller.

US Pat. No. 10,560,030

CABLE COMPENSATION CIRCUIT AND POWER SUPPLY INCLUDING THE SAME

SEMICONDUCTOR COMPONENTS ...

1. A compensation circuit for compensating for a voltage drop in a cable coupled between a power supply and a load, the compensation circuit comprising:a sensing resistive-capacitive (RC) filter including a first capacitor and configured to receive a voltage from an auxiliary winding of the power supply and generate a sense voltage by RC filtering the received voltage; and
an averaging filter including a second capacitor and configured to generate an average voltage by averaging the sense voltage,
wherein the power supply comprises a transformer including a primary winding, a secondary winding, and the auxiliary winding, a power switch coupled through the primary winding to an input voltage, a rectifying diode coupled between the secondary winding and the output voltage, and a feedback circuit comprising a shunt regulator having a reference end, the shunt regulator configured to control a sink current according to a voltage of the reference end,
wherein the compensation circuit further comprises a third resistor coupled between the average voltage and the reference end of the shunt regulator of the feedback circuit of the power supply, and
wherein the power supply uses the average voltage to control the power switch.

US Pat. No. 10,560,029

CONTROLLER FOR INCREASING EFFICIENCY OF A POWER CONVERTER AND A RELATED METHOD THEREOF

Leadtrend Technology Corp...

1. A controller for increasing efficiency of a power converter, the controller comprising:an enable signal generation unit electrically connected to a direct current (DC) input terminal of a primary side of the power converter through a high voltage pin of the controller, wherein the enable signal generation unit is used for generating an enable signal corresponding to a duty cycle of a gate control signal according to a DC input voltage of the DC input terminal and a feedback voltage corresponding to a secondary side of the power converter, and the feedback voltage corresponds to an output voltage of the secondary side of the power converter; and
a gate signal generation unit having two transistors in parallel, wherein a first terminal of a first transistor of the two transistors and a first terminal of a second transistor of the two transistors are coupled to ground, a second terminal of the first transistor is coupled to a gate pin of the controller through a switch comprised in the gate signal generation unit, a second terminal of the second transistor is directly coupled to the gate pin, and a control terminal of the first transistor and a control terminal of the second transistor receive a pulse width modulation signal;
wherein the gate signal generation unit utilizes the enable signal to control turning-on and turning-off of the switch to change a sink current flowing through the gate pin of the controller, wherein the gate pin is coupled to a power switch of the primary side of the power converter, and the gate signal generation unit is further used for generating a gate control signal to the power switch.

US Pat. No. 10,560,024

BIDIRECTIONAL DC/DC CONVERTER FOR A CHARGING SYSTEM

Conductive Holding, LLC, ...

1. A bidirectional direct current/direct current (DC/DC) converter comprising:a direct current/alternating current (DC/AC) inverter coupled to a first direct current (DC) bus and to a primary winding of a transformer, the DC/AC inverter including active switches;
a secondary side AC/DC rectifier coupled to a secondary winding of the transformer and a second DC bus, the secondary side AC/DC rectifier including:
a capacitor that performs DC-bias current blocking, and
a bridge configuration of active switches coupled to the capacitor and the secondary winding, and to a second DC bus; and
a microcontroller coupled to the active switches of the secondary side AC/DC rectifier, and configured to provide control signals thereto according to a control algorithm, the control algorithm configured to:
when power is to flow from the first DC bus to the second DC bus, send control signals at a switching frequency having a first initial value to operate the active switches of the DC/AC inverter at a duty cycle and disable the active switches of the secondary side AC/DC rectifier, determine if power at the second DC bus is substantially equal to a first target, and increase the switching frequency of the control signals that operate the active switches of the DC/AC inverter to decrease the power at the second DC bus or decrease the switching frequency of the control signals that operate the active switches of the DC/AC inverter to increase the power at the second DC bus until the power at the second DC bus is substantially equal to the first target, and
when power is to flow from the second DC bus to the first DC bus, send control signals to disable the active switches of the DC/AC inverter and at a switching frequency having a second initial value to operate the active switches of the secondary side AC/DC rectifier at the duty cycle, determine if power supplied from the second DC bus is substantially equal to a second target, and increase the switching frequency of the control signals that operate the active switches of the secondary side AC/DC rectifier to decrease the power supplied from the second DC bus or decrease the switching frequency to increase the power supplied from the second DC bus until the power supplied from the second DC bus is substantially equal to the second target.

US Pat. No. 10,560,023

MULTI-PHASE POWER REGULATOR

Texas Instruments Incorpo...

1. A circuit for use in system with a multi-phase power regulator to supply power to an electrical load, the multi-phase power regulator including a power stage including a first phase and a second phase, the circuit comprising:phase management circuitry to couple to the first phase and the second phase to control the first phase and the second phase;
a first comparator to couple to an output node of the multi-phase power regulator to compare a first output voltage level at the output node of the multi-phase power regulator to a first threshold value to produce a first comparison result; and
a second comparator to couple to the output node of the multi-phase power regulator to compare the first output voltage level to a second threshold value to produce a second comparison result, wherein the second threshold value is less than the first threshold value;
current detection circuitry to detect:
first electrical characteristics associated with providing a first amount of current to the load at the first output voltage level, the first electrical characteristics indicative of an increased current draw by the load; and
second electrical characteristics associated with providing a second amount of current to the load at the first output voltage level, the second electrical characteristics indicative of a decreased current draw by the load;
a load line to lower the first output voltage level based on an increase in current draw by the load; and
phase shedding circuitry coupled to the first comparator and the second comparator, and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result and the second comparison result.

US Pat. No. 10,560,022

SETTING OPERATING POINTS FOR CIRCUITS IN AN INTEGRATED CIRCUIT CHIP USING AN INTEGRATED VOLTAGE REGULATOR POWER LOSS MODEL

ADVANCED MICRO DEVICES, I...

1. An apparatus that controls voltages, comprising:an integrated circuit chip comprising a set of circuits;
an external voltage regulator separate from the integrated circuit chip;
a plurality of integrated voltage regulators fabricated on the integrated circuit chip, the external voltage regulator providing an output voltage that is received as an input voltage by each of the plurality of integrated voltage regulators, and each integrated voltage regulator of the plurality of integrated voltage regulators providing a local output voltage that is received as a local input voltage by a respective subset of circuits in the set of circuits; and
a controller that:
determines a first combination of operating points for the subsets of the circuits, the first combination of operating points comprising a respective operating point for each of the subsets of the circuits;
determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for the first combination of operating points;
determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits, the adjustment to the operating point compensating for an electrical power loss of the integrated voltage regulator that provides the local input voltage to the at least one of the subsets of the circuits; and
set an operating point of each of the subsets of the circuits to a respective operating point from the second combination of operating points.

US Pat. No. 10,560,021

DC-DC CONVERTER AND DISPLAY APPARATUS HAVING THE SAME

Samsung Display Co., Ltd....

1. A DC-DC converter comprising:a first switch;
a second switch connected to the first switch;
an input terminal for receiving an input voltage;
an output terminal for outputting an output voltage;
an inductor;
a mode selecting circuit configured to select a converting mode from one of at least a first converting mode and a second converting mode based on the input voltage; and
a controller configured to generate a first switching control signal for controlling the first switch based on the selected converting mode, and a second switching control signal for controlling the second switch based on the selected converting mode,
wherein the mode selecting circuit is configured to select the converting mode from one of at least the first converting mode, the second converting mode, and a third converting mode,
wherein, in the first converting mode, the first switch is configured to be repeatedly turned on and off in response to the first switching control signal, and the second switch is configured to be repeatedly turned on and off in response to the second switching control signal,
wherein, in the second converting mode, the first switch is configured to be repeatedly turned on and off in response to the first switching control signal, and the second switch is configured to maintain a turned off state in response to the second switching control signal,
wherein, in the third converting mode, the first switch is configured to be repeatedly turned on and off in response to the first switching control signal, and the second switch is configured to maintain a turned on state in response to the second switching control signal,
wherein in the third converting mode, the second switching control signal is the input voltage,
wherein the second switch is coupled between one end of the first switch and the output terminal, and
wherein the inductor is coupled between the input terminal and the first and second switches.

US Pat. No. 10,560,020

METHOD OF VOLTAGE DROP COMPENSATION ON A CABLE AND CORRESPONDING CIRCUIT

STMICROELECTRONICS (ALPS)...

1. A method for compensating a voltage drop on a cable connected between a source device and a receiver device, the method comprising:increasing, by the source device, a voltage on a channel configuration pin of the source device to a chosen reference voltage by increasing an offset current on the channel configuration pin of the source device;
storing the offset current in the source device as a stored offset current after increasing the voltage to the chosen reference voltage;
absorbing, by the source device, an absorption current originating from the channel configuration pin of the source device, the absorption current depending on the stored offset current and on the voltage drop; and
generating, by the source device, a compensated supply voltage on a power supply pin of the source device, the compensated supply voltage equal to a reference supply voltage increased by the voltage drop to within a first tolerance.

US Pat. No. 10,560,019

BIPOLAR HIGH-VOLTAGE NETWORK AND METHOD FOR OPERATING A BIPOLAR HIGH-VOLTAGE NETWORK

Airbus Operations GmbH, ...

1. A bipolar high-voltage network for an aircraft or spacecraft, comprising:a DC voltage converter comprising two unipolar input connections, two bipolar output connections and a single reference potential connection;
at least one unipolar device having only two electrical connections, each one of the two electrical connections being coupled to one of the two unipolar input connections,
a first DC voltage intermediate circuit which is coupled between the unipolar input connections of the DC voltage converter;
a second DC voltage intermediate circuit which is coupled between the bipolar output connections of the DC voltage converter,
the DC voltage converter comprising a first DC voltage converter module, comprising circuitry comprising two capacitors, two switches and a choke, wherein a first of the two capacitors is connected in series between the module input connection and the reference potential connection, a second of the two capacitors is connected in series between the module output connection and the reference potential connection, the first DC voltage converter model being coupled to a first of the unipolar input connections of the DC voltage converter via a module input connection, to the reference potential connection of the DC voltage converter via a module reference potential connection, and to a first of the bipolar output connections of the DC voltage converter via a module output connection, and
the DC voltage converter comprising a second DC voltage converter module, comprising circuitry comprising two capacitors, two switches and a choke, wherein a first of the two capacitors is connected in series between the module input connection and the reference potential connection, a second of the two capacitors is connected in series between the module output connection and the reference potential connection, the second DC voltage converter module being coupled to a second of the unipolar input connections of the DC voltage converter via a module input connection, to the reference potential connection of the DC voltage converter via a module reference potential connection, and to a second of the bipolar output connections of the DC voltage converter via a module output connection; and
six additional switches, two additional capacitors, and four zero diodes,
wherein two sets of series-connected switches are connected in parallel with the unipolar input connections and the bipolar output connections,
wherein two of the capacitors are coupled between the two unipolar input connections and two of the capacitors are connected in series between a tapping terminal and a reference potential terminal,
wherein the four zero diodes are connected in parallel with four of the additional six switches, and,
wherein the two unipolar input connections and the reference potential connection are different connections.

US Pat. No. 10,560,017

CHARGE PUMP, SWITCH DRIVER DEVICE, LIGHTING DEVICE, AND VEHICLE

Rohm Co., Ltd., Kyoto (J...

1. A charge pump comprising:a flying capacitor;
an output capacitor;
a switch group arranged to switch connection states of the capacitors so as to generate an output voltage from an input voltage; and
a feedback control unit arranged to adjust an interterminal voltage of the flying capacitor to a predetermined target value when charging the flying capacitor, wherein
the switch group includes:
a first switch connected between a first terminal of the flying capacitor and an input terminal of the input voltage,
a second switch connected between a second terminal of the flying capacitor and the input terminal of the input voltage,
a third switch connected between the first terminal of the flying capacitor and an output terminal of the output voltage,
a fourth switch connected between the second terminal of the flying capacitor and a ground terminal, and
a fifth switch connected between the first terminal of the flying capacitor and an input terminal of a power supply voltage, wherein
in a low input case where the input voltage is lower than the power supply voltage, the flying capacitor is charged using the power supply voltage,
in a high input case where the input voltage is higher than the power supply voltage, the flying capacitor is charged using the input voltage.

US Pat. No. 10,560,012

ZVS CONTROL CIRCUIT FOR USE IN A FLYBACK POWER CONVERTER

RICHTEK TECHNOLOGY CORPOR...

1. A zero voltage switching (ZVS) control circuit, configured to operably control a flyback power converter including a power transformer having a primary side and a secondary side, the ZVS control circuit comprising:a primary side controller circuit, configured to operably generate a switching signal according to a feedback signal, wherein the switching signal controls a power transformer through a power transistor at the primary side to generate an output voltage at the secondary side; and
a secondary side controller circuit, configured to operably generate the feedback signal, and generate an SR signal to control a synchronous rectifier transistor at the secondary side, wherein the SR signal includes an SR-control pulse and a ZVS pulse, wherein the SR-control pulse controls the synchronous rectifier transistor in response to a demagnetizing period of the power transformer, and wherein the ZVS pulse controls the power transformer through the synchronous rectifier transistor to determine a timing for starting the switching signal to achieve zero voltage switching for the power transistor;
wherein the secondary side controller circuit generates the ZVS pulse after a delay time from an end of a demagnetizing period of the power transformer, wherein within the demagnetizing period, the power transformer is substantially demagnetized, and the delay time is determined according to a time length of the demagnetizing period, wherein the delay time is increased as the time length of the demagnetizing period of the power transformer is decreased.

US Pat. No. 10,560,009

VIBRATION MOTOR

NIDEC SEIMITSU CORPORATIO...

1. A vibration motor comprising:a stationary portion including a casing and a coil;
a vibrating body including a weight and a magnet, the vibrating body being supported so as to be vibratable in one direction relative to the stationary portion;
an elastic member located between the stationary portion and the vibrating body; and
a top plate portion that is disposed above the vibrating body in an up-down direction that is perpendicular to the one direction, wherein
the magnet is disposed above the coil,
the top plate portion faces the magnet in the up-down direction,
the magnet includes a set of first magnets that generate magnetic forces that are opposite to each other in the up-down direction and one or more second magnets that are interposed between the first magnets and each generate a magnetic force in the one direction,
the weight includes a first weight portion that is disposed above the coil and a second weight portion whose lower surface is located below a lower surface of the first weight portion,
the second weight portion faces the coil in the one direction,
the stationary portion further includes a substrate,
the substrate includes a substrate body on which the coil is disposed and an extension portion that extends from the substrate body in the one direction toward an outside of the casing,
the second weight portion includes a groove that extends in the one direction and in which the extension portion is disposed,
the casing includes a base,
the substrate is disposed on the base, and
a relationship HA>HL>HB>HP is satisfied, where HA is a height from the base to the lower surface of the first weight portion, HB is a height from the base to the groove, HL is a height from the base to an upper surface of the coil, and HP is a height from the base to an upper surface of the substrate.

US Pat. No. 10,560,007

MOTOR

MABUCHI MOTOR CO., LTD., ...

1. A motor comprising:a cylindrical housing that houses a rotor;
a first member mounted to an opening of the housing; and
a second member sandwiching the first member as mounted between the second member and the housing, wherein
the housing includes, at an end of the housing that faces the second member, a first locking part that locks a first locked part of the second member, and
the second member is elastically deformed by the first locking part and locked to the housing accordingly and is configured such that a gap is formed between the second member and the housing when the second member is locked to the housing.

US Pat. No. 10,560,005

APPARATUS FOR MANUFACTURING LAMINATED IRON CORE

MITSUI HIGH-TEC, INC., F...

1. An apparatus for manufacturing a laminated iron core, the apparatus comprising:a conveyance jig on which a laminated iron core body is placed, wherein the laminated iron core body is lamination of a plurality of iron core pieces;
a die unit including a lower die and an upper die upwardly and downwardly movable with respect to the lower die, which holds the laminated iron core body placed on the conveyance jig from both sides in a lamination direction of the plurality of iron core pieces between the lower die and the upper die;
an injector injecting a resin into a through hole formed through the laminated iron core body held by the die unit in the lamination direction of the plurality of iron core pieces from the lower die through the conveyance jig or from the upper die; and
a lift configured to selectively move the conveyance jig upwardly and downwardly with respect to and separately from the lower die, wherein the lift is mounted so as to be unaffixed to both the die unit and the conveyance jig, and
wherein the lower die is configured to come into contact with the conveyance jig.

US Pat. No. 10,560,002

COOLANT FLOW DISTRIBUTION USING COATING MATERIALS

FORD GLOBAL TECHNOLOGIES,...

1. An electric machine comprising:a stator core, within a transaxle housing, having a channel-less outer surface portion;
one or more layers of an oleophobic or hydrophobic patterned coating defining boundaries wrapping around a perimeter of the stator core; and
one or more layers of an oleophilic or hydrophilic coating on the portion within the boundaries configured to direct coolant flow over the oleophilic or hydrophilic coating within the boundaries.

US Pat. No. 10,560,001

COOLING TOWER HAVING THERMALLY MANAGED MOTOR

Prime Datum Development C...

1. A cooling tower comprising:a cooling tower structure;
fill material supported by the cooling tower structure and configured to receive heated process fluid;
a motor mounted to the cooling tower structure, the motor comprising a casing and a rotatable shaft, the casing having an exterior surface and an interior, the motor being sealed to prevent fluids, moisture, foreign particles and contaminants from entering the casing, the motor further comprising at least one temperature sensor for outputting sensor signals that represent temperature;
a fan connected to the rotatable shaft of the motor, wherein rotation of the rotatable shaft rotates the fan thereby inducing an upward moving mass flow of cool air through the fill material;
a basin attached to the cooling tower structure for collecting cooled fluid;
a temperature-controlled fluid distribution system to distribute cooled fluid from the basin onto the motor to cause a transfer of heat from the casing of the motor to the fluid, the temperature-controlled fluid distribution system being responsive to the sensor signals and configured to distribute cooled fluid from the basin onto the motor when the sensor signals indicate a temperature that exceeds a predetermined threshold and to cease distributing the cooled fluid onto the motor when the sensor signals indicate a temperature that is below the predetermined threshold.

US Pat. No. 10,559,998

MOTOR AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A motor, comprising:a stationary unit including a stator, a base, and a flexible wiring substrate board;
a rotary unit including a rotor magnet; and
a bearing mechanism that supports the rotary unit so as to rotate with respect to the stationary unit about a center axis extending in an axial direction; wherein
the stator is positioned radially inward of the rotor magnet;
the base is positioned axially below the stator and the rotor magnet and includes a hole extending therethrough;
the hole is positioned in a region of the base, the region of the base has an axial height which varies at different locations within the region of the base;
the flexible wiring substrate board extends completely through the hole and supplies electric power to the stator;
the flexible wiring substrate board extends beneath both of the rotor magnet and the stator;
the stator includes at least one stator coil and the flexible wiring substrate board extends beneath a majority of an entire radial dimension of the at least one stator coil;
the flexible wiring substrate includes an electrically conductive solder portion on a lower surface thereof to cover a portion of a lead wire extending from a coil of the stator; and
at least a portion of the solder portion is positioned within an additional hole defined in the base.

US Pat. No. 10,559,997

BRUSH DEVICE, ELECTRIC MOTOR WITH BRUSH DEVICE, AND MANUFACTURING METHOD OF BRUSH DEVICE

DENSO CORPORATION, Kariy...

1. A brush device comprising:a positive side brush sub-assembly having a positive side brush for feeding a commutator, a positive side brush holder for holding the positive side brush, and a positive side plate to which the positive side brush holder is attached, and
a negative side brush sub-assembly having a negative side brush for feeding the commutator, a negative side brush holder for holding the negative side brush, and a negative side plate to which the negative side brush holder is attached, wherein
the positive side brush holder has a positive convex portion engaging with the negative side plate,
the negative side brush holder has a negative convex portion engaging with the positive side plate,
the positive side plate has a positive slit engaging with the negative convex portion,
the negative side plate has a negative slit engaging with the positive convex portion, and
the positive side brush sub-assembly and the negative side brush sub-assembly are combined with each other by the positive convex portion and the negative slit being engaged and the negative convex portion and the positive slit being engaged.

US Pat. No. 10,559,995

MOTOR HAVING A COVER MEMBER FOR GUIDING WATER DROPLETS AWAY FROM ROTARY ENCODER

FANUC CORPORATION, Yaman...

1. A motor comprising:a motor main body having a rotating shaft member; and
a rotary encoder, wherein
the rotary encoder has a cover member, and
an inner surface of the cover member has a first top surface formed having an inclined portion that is inclined relative to a horizontal direction so as to guide a droplet of water when the rotating shaft member is disposed to extend in a vertical direction, and a second top surface formed having an inclined portion that is inclined relative to a horizontal direction so as to guide a droplet of water when the rotating shaft member is disposed to extend in a horizontal direction,
wherein a groove for guiding a droplet of water is formed in the first top surface and/or the second top surface, the groove being linear and extending in a predetermined direction when viewing the first top surface and the second top surface from inside the cover member, and
a hygroscopic material is disposed to be bonded to the first top surface and the second top surface at the boundary between the first top surface and the second top surface of the inner surface of the cover member, and absorbs the droplets of water guided by the first top surface and the second top surface.

US Pat. No. 10,559,990

STRUCTURES UTILIZING A STRUCTURED MAGNETIC MATERIAL AND METHODS FOR MAKING

Persimmon Technologies Co...

1. A motor, comprising:a stator comprising at least one core and an outer wall, the outer wall extending in an axial direction;
a coil wound on the at least one core of the stator such that an edge of the outer wall extending in the axial direction is below, even with, or extends beyond a surface of the coil facing in the axial direction and such that the outer wall extends radially beyond an outer edge of the coil;
a rotor having a rotor pole and being rotatably mounted relative to the stator;
at least one magnet disposed between the rotor and the stator; and
a conical air gap between the stator and the at least one magnet;
wherein a separation plane normal to an axis of rotation extends through the stator and the rotor, and wherein the coil, the at least one magnet, and the conical air gap are together configured to allow flux flow between the stator and the rotor in a three-dimensional flux pattern such that the flux flow does not cross the separation plane.

US Pat. No. 10,559,989

ROTOR CARRIER AND LOCKING DIAPHRAGM SPRING

11. A carrier hub of a hybrid drive module including a torque converter and an electric motor including a rotor, the carrier hub comprising:a carrier hub surface including a retention groove configured to interlock the carrier hub to one or more fingers of a diaphragm spring and inhibit rotation and axial movement of the diaphragm spring relative to the carrier hub, wherein the retention groove includes a first and second passageway connected by a third passageway, wherein the first, second, and third passageways extend in different directions to allow the finger to be translated along the retention groove in three different directions.

US Pat. No. 10,559,988

ROTOR FOR ROTARY ELECTRIC MACHINE

MITSUBISHI ELECTRIC CORPO...

1. A rotor for a rotary electric machine, comprising:a first rotor member; and
a second rotor member,
the first rotor member including a first core member and a first magnet group provided to the first core member,
the second rotor member including a second core member and a second magnet group provided to the second core member,
the first core member and the second core member being fixed to each other under a state of being aligned in an axial direction of the rotor,
the first magnet group and the second magnet group being adjacent to each other in the axial direction,
the first magnet group including a plurality of first magnets arrayed in a circumferential direction of the rotor,
the second magnet group including a plurality of second magnets arrayed in the circumferential direction,
the first magnet and the second magnet, which are adjacent to each other and have the same polarity, being shifted from each other in the circumferential direction so as to mutually receive a magnetic repulsive force in the circumferential direction,
one of the first core member and the second core member having a first recessed portion, and another of the first core member and the second core member having a first protruding portion to be engaged with the first recessed portion in the circumferential direction,
at least any one of the first core member and the second core member is formed as a core assembly member including a main body core block and a plurality of arc-shaped core blocks mounted to any one of an outer peripheral portion and an inner peripheral portion of the main body core block,
magnets included in the plurality of first magnets and the plurality of second magnets, which are provided to the core assembly member, are provided to the arc-shaped core blocks,
any one of the main body core block and the plurality of arc-shaped core blocks has a second recessed portion formed thereon, and another of the main body core block and the plurality of arc-shaped core blocks has a second protruding portion formed thereon to be engaged with the second recessed portion in a direction in which the first protruding portion is brought into engagement with the first recessed portion,
the second recessed portion has a second recessed-portion engagement portion having a width which continuously decreases in a direction in which the second protruding portion is brought into engagement with the second recessed portion, and
the second protruding portion has a second protruding-portion engagement portion to be fitted into the second recessed-portion engagement portion.

US Pat. No. 10,559,986

SYSTEM, METHOD, AND APPARATUS FOR WIRELESS CHARGING

CAPITAL ONE SERVICES, LLC...

1. An electronic transaction card comprising:a Near-Field Communication (NFC) antenna;
an energy storage component; and
a processor configured to:
send and receive data packets to and from a terminal system to conduct a transaction using contactless payment technology, wherein the data packets include user authentication information to authenticate payment;
transmit, via the NFC antenna, an advertising packet from the electronic transaction card to a mobile power receiving device;
receive, via the NFC antenna, a response to the advertising packet from the mobile power receiving device, wherein the response indicates a first frequency of energy transmission via the NFC antenna;
alter the first frequency of energy transmission via the NFC antenna to a second frequency of energy transmission via the NFC antenna based on a distance between the electronic transaction card and the mobile power receiving device; and
broadcast, via the NFC antenna, a signal to the mobile power receiving device using the second frequency and configured to charge the mobile power receiving device via inductive charging.

US Pat. No. 10,559,985

WIRELESS POWER TRANSFER SYSTEM, CONTROL METHOD OF WIRELESS POWER TRANSFER SYSTEM, WIRELESS POWER TRANSMITTING APPARATUS, CONTROL METHOD OF WIRELESS POWER TRANSMITTING APPARATUS, AND STORAGE MEDIUM

CANON KABUSHIKI KAISHA, ...

1. A power transmitting apparatus comprising:a member configured to mount a power receiving apparatus;
a power transmitting unit configured to wirelessly transmit power to the power receiving apparatus mounted on the member;
a communication unit configured to communicate with the power receiving apparatus mounted on the member; and
a control unit configured to control the power transmitting unit and the communication unit,
wherein the communication unit transmits information to the power receiving apparatus mounted on the member, thereby the power receiving apparatus displays, based on the information transmitted by the communication unit, a charging message representing a charging speed.

US Pat. No. 10,559,984

POWER TRANSFER SYSTEM, AND POWER RECEIVING APPARATUS, POWER TRANSMITTING APPARATUS, AND CONTROL METHOD THEREOF

CANON KABUSHIKI KAISHA, ...

1. A power receiving apparatus comprising:a first antenna for wirelessly receiving power from a power transmitting apparatus and for performing communication;
a second antenna for performing communication;
one or more memories storing instructions; and
one or more processors executing the instructions to:
perform communication regarding identification information, with the power transmitting apparatus, via the first antenna;
transmit a first signal via the second antenna;
receive a second signal indicating a request for communication via the second antenna after transmitting the first signal;
determine whether a transmission source of the second signal is the power transmitting apparatus with which the identification information is communicated via the first antenna based on identification information included in the second signal;
control to perform communication regarding power receiving control via the second antenna, based on determining the transmission source of the second signal is the power transmitting apparatus with which the identification information is communicated via the first antenna, with the transmission source of the second signal, and control not to perform communication regarding power receiving control via the second antenna, based on determining the transmission source of the second signal is not the power transmitting apparatus with which the identification information is communicated via the first antenna, with the transmission source of the second signal.

US Pat. No. 10,559,982

EFFICIENT ANTENNAS CONFIGURATIONS FOR USE IN WIRELESS COMMUNICATIONS AND WIRELESS POWER TRANSMISSION SYSTEMS

Ossia Inc., Bellevue, WA...

1. A transmitter device, comprising:multiple antennas;
a dielectric material in proximity to the multiple antennas, the dielectric material having disposed therein a non-layered distribution of a high refractive index material and a low refractive index material; and
multiple scattering elements embedded in the dielectric material,
wherein one or more of the multiple scattering elements are configured to increase a number of radiating elements per volume in the transmitter device by creating complex waveforms with increased diversity when excited by one or more signals emitted by the multiple antennas.

US Pat. No. 10,559,981

POWER LINKS AND METHODS FOR IMPROVED EFFICIENCY

Daxsonics Ultrasound Inc....

1. A method of improving transfer efficiency in an ultrasonic power link having a send transducer and configured to transmit at a transmit frequency, in which the send transducer has a fixed resonant global best operating frequency characteristic to the send transducer, the method comprising detecting changes in impedance phase as seen by the send transducer by sweeping the transmit frequency over a range of frequencies, identifying a target frequency at which the impedance phase is at a local minimum that is closest in value to the global best operating frequency, and adjusting the transmit frequency to the target frequency.

US Pat. No. 10,559,980

SIGNALING IN WIRELESS POWER SYSTEMS

WiTricity Corporation, W...

1. A source for providing power wirelessly to, or receiving power wireless from, a vehicle, the source comprising:a source resonator capable of generating a first electromagnetic field to provide power wirelessly to a device resonator configured to be mounted to the vehicle, and to receive power wirelessly via a second electromagnetic field generated by the device resonator;
power and control circuitry coupled to the source resonator and configured to control a direction of flow of the power, including a first direction of flow via the first electromagnetic field during a first time period and a second direction of flow via the second electromagnetic field during a second time period, the power and control circuitry comprising a processor configured to monitor a state of the power and control circuitry corresponding to the direction of flow; and
a user interface coupled to the power and control circuitry and configured to report information based on the monitored state of the power and control circuitry.

US Pat. No. 10,559,979

CHARGING RECHARGEABLE APPARATUS

Nokia Technologies Oy, E...

9. A method comprising:accessing a trigger event comprising a battery level threshold of a rechargeable apparatus;
linking the rechargeable apparatus with a charging apparatus for wireless communication;
determining that the trigger event has occurred and the rechargeable apparatus is outside of a charging range of the charging apparatus;
in response to a determination that the trigger event has occurred and that the rechargeable apparatus is outside of the charging range of the charging apparatus, causing transmission of a wireless communication from the rechargeable apparatus to the charging apparatus;
causing an alert associated with the rechargeable apparatus to be provided by the charging apparatus; and
in an instance the rechargeable apparatus is positioned within the charging range of the charging apparatus, causing the provision of the alert associated with the rechargeable apparatus to be stopped.

US Pat. No. 10,559,974

CONSTANT POWER OUTPUT FROM EMERGENCY BATTERY PACKS

Eaton Intelligent Power L...

1. An electrical system comprising:a power supply that provides primary power;
an electrical device comprising at least one electrical load, wherein the electrical device is coupled to the power supply, wherein the at least one electrical load operates when the electrical device receives the primary power;
an energy storage unit comprising at least one energy storage device, wherein the at least one energy storage device charges using the primary power; and
a controller that determines an initial charging period during which the at least one energy storage device is charged using a constant supply of the primary power, wherein the controller changes the constant supply of the primary power to a trickle charge of the primary power at the end of the initial charging period to maintain a minimum charge level of the at least one energy storage device,
wherein the at least one electrical load receives reserve power from the energy storage unit when the power supply ceases providing the primary power and the trickle charge,
wherein the controller further causes the reserve power delivered by the energy storage unit to be substantially constant over time,
wherein the energy storage unit comprises a boost converter,
wherein the reserve power is less than the primary power but greater than a minimum threshold value.

US Pat. No. 10,559,973

ELECTRONIC DEVICE AND POWER SUPPLY METHOD THEREOF

Wistron Corporation, New...

1. An electronic device, comprising:an auxiliary power supply device;
a detachable power supply device; and
a control circuit, coupled to a power supply terminal, wherein the power supply terminal is coupled to a system load, and the control circuit comprises:
a change-over switch, having a first terminal coupled to the power supply terminal and a second terminal coupled to a supply terminal of the auxiliary power supply device;
a first switch, having a first terminal coupled to a control terminal of the change-over switch, and a control terminal of the first switch being coupled to the supply terminal of the detachable power supply device when the detachable power supply device is assembled to the electronic device; and
a second switch, having a first terminal coupled to the control terminal of the change-over switch and a control terminal coupled to the power supply terminal, wherein
when the detachable power supply device is assembled to the electronic device, the first switch is turned on to turn on the change-over switch, the second switch maintains the change-over switch in a conducting state, and the detachable power supplies power to the system load;
wherein when the electronic device is not turned on and the detachable power supply is removed from the electronic device, the change-over switch is not in a conducting state, and the control circuit does not turn on the electronic device by using the auxiliary power supply device, and
when the electronic device is in an on state and the detachable power supply is removed from the electronic device, the changer-over switch is in the conducting state, and the second switch of the control circuit is continuously turned on to maintain the change-over switch in a conducting state, so as to keep supplying power to the electronic device by using the auxiliary power supply device.

US Pat. No. 10,559,968

CHARGE/DISCHARGE CONTROL CIRCUIT AND BATTERY APPARATUS

ABLIC INC., Chiba (JP)

1. A charge/discharge control circuit comprising:a first power supply terminal connected to a first electrode of a secondary battery;
a second power supply terminal connected to a second electrode of the secondary battery;
a discharge control terminal connected to a gate of a discharge control field effect transistor (FET) which controls discharging of the secondary battery;
a discharge control output circuit configured to output a discharge control signal to the discharge control terminal; and
a control circuit configured to control the discharge control output circuit,
the discharge control output circuit comprising:
a first clamp voltage output circuit configured to output a first clamp voltage lower than a voltage of the first power supply terminal to the discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is higher than a first prescribed voltage, and
a first power supply voltage output circuit configured to output the voltage of the first power supply terminal to the discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is equal to or less than the first prescribed voltage.

US Pat. No. 10,559,966

INFORMATION DISPLAYING METHOD AND INFORMATION DISPLAYING DEVICE

PANASONIC INTELLECTUAL PR...

1. A method for displaying information on a display, comprising:receiving a request to display, on the display, information indicating whether each of a plurality of battery packs associated with the display, is mounted on a device of a plurality of devices associated with the display, each of the plurality of battery packs being mountable on the plurality of devices; and
in response to the request, displaying, on a monitor of the display, information indicating whether or not a battery pack of the plurality of battery packs associated with the display is mounted on each device of the plurality of devices associated with the display,
wherein, in the displaying, a first image is displayed in a different manner from a second image, the first image indicating a mounted state of a battery pack on a device of the plurality of devices associated with the display, the second image indicating an unmounted state of a battery pack on a device of the plurality of devices associated with the display.

US Pat. No. 10,559,964

MOBILE TERMINAL AND BATTERY CHARGING METHOD THEREFOR

LG ELECTRONICS INC., Seo...

1. A mobile terminal, comprising:a terminal body comprising a battery;
an adaptor connector formed at one side surface of the terminal body and to which a power supply adaptor is connected;
a plurality of charging units configured to charge the battery between the adaptor connector and the battery; and
a controller configured to generate a control signal for controlling each of the plurality of charging units,
wherein any one of the plurality of charging units is configured to:
detect a level of a voltage of the battery,
compare the voltage of the battery with first to third threshold voltages, and
output first battery voltage data to the controller when the voltage of the battery is lower than the first threshold voltage, output second battery voltage data to the controller when the voltage of the battery is equal to or larger than the first threshold voltage and is lower than the second threshold voltage, and output third battery voltage data to the controller when the voltage of the battery is equal to or larger than the second threshold voltage and is lower than the third threshold voltage.

US Pat. No. 10,559,960

APPARATUS, DEVICE AND COMPUTER IMPLEMENTED METHOD FOR CONTROLLING POWER PLANT SYSTEM

GREENSMITH ENERGY MANAGEM...

1. A computer implemented method for controlling a power plant system, the power plant system including a photovoltaic power source configured to provide photovoltaic DC power to a photovoltaic DC bus, the photovoltaic power source including an inverter including a direct current (DC) power input operationally connected to the photovoltaic DC bus to receive photovoltaic DC power, and an alternating current (AC) power output for supplying AC power to an AC system, a DC-to-DC converter including a first direct current (DC) port to be operationally connected to the photovoltaic DC bus in parallel with the photovoltaic power source, an energy storage and an energy storage manager operationally connected to a second direct current (DC) port of the DC-to-DC converter, the method for controlling the power plant system comprising:receiving a target value for the AC power to be supplied by the inverter;
receiving weather forecast information, energy storage status information and photovoltaic power source parameters;
generating forecasted energy flow information for the photovoltaic power source based on the weather information and the photovoltaic power source parameters;
comparing the forecasted energy flow information and the energy storage status information; and
adjusting the target value for the AC power based on the comparison.

US Pat. No. 10,559,959

MULTI-GENERATOR POWER PLANT ARRANGEMENT, ENERGY SUPPLY NETWORK HAVING A MULTI-GENERATOR POWER PLANT ARRANGEMENT AND METHOD FOR DISTRIBUTING REACTIVE POWER GENERATION IN A MULTI-GENERATOR POWER PLANT ARRANGEMENT

1. A multi-generator power plant arrangement, comprising:a network feeding-in point, which is electrically coupled to an energy supply network;
a plurality of generators, which are in each case electrically coupled to the network feeding-in point and are designed to provide a reactive power in dependence on a first control variable, wherein at least one generator of the plurality of generators is a grid-forming generator, which is designed to provide an output voltage at a specified amplitude and a specified frequency or phase on a basis of a second control variable, wherein the reactive power to be provided by the plurality of generators is divided among the plurality of generators using a predetermined ratio or predetermined rules such that each respective generator of the plurality of generators has a designated reactive power to be fed in; and
a control device, which is designed to calculate a respective second control variable for the output voltage of the at least one grid-forming generator by using the designated reactive power to be fed in by a respective grid-forming generator of the plurality of generators, and to transmit the calculated respective second control variable to the respective grid-forming generator of the plurality of generators.

US Pat. No. 10,559,954

METHODS AND APPARATUS FOR VOLTAGE AND CURRENT CALIBRATION

SEMICONDUCTOR COMPONENTS ...

1. A calibration circuit, comprising:a battery pack comprising a negative pack terminal; and
an intermediate node;
a first protection IC coupled to a first transistor, wherein the first transistor is coupled between the negative pack terminal and the intermediate node;
a second protection IC coupled in parallel with the first protection IC and coupled to a second transistor;
a power source adapted to be coupled in parallel with the first and second protection ICs; and
a current source adapted to be coupled between the negative pack terminal and the intermediate node;
wherein:
the intermediate node is positioned between the first transistor and the second transistor; and
the power source is configured to provide a current to the first protection IC through a first current loop.

US Pat. No. 10,559,953

REDUNDANT AND FAULT-TOLERANT POWER DISTRIBUTION SYSTEM HAVING AN INTEGRATED COMMUNICATION NETWORK

Applied Invention, LLC, ...

1. A power distribution system having an integrated communication network, comprising:a plurality of nodes, wherein each of the nodes includes:
a power port and an associated port monitor;
a load port and an associated port monitor; and
a processing element;
wherein the port monitors associated with the power port and the load port are connected to the processing element, and include a current monitor for measuring current flowing into or out of the corresponding port;
a topology that enables current to flow bi-directionally between the nodes; and
a communication link for conducting data bi-directionally between the nodes;
wherein data passed on the communication link is used for any of:
enabling or disabling any of:
a power source connected to a particular power port at a corresponding node, or
a device connected to a particular load port at a corresponding node.

US Pat. No. 10,559,948

CASING, ELECTRICAL CONNECTION BOX, AND WIRE HARNESS

YAZAKI CORPORATION, Toky...

1. A casing comprising:a frame peripheral wall on which an opening portion is formed at an edge;
a cover that covers the opening portion by rotational movement; and
a packing that is assembled in a packing groove to be formed in the cover and is pressed against the edge during the rotational movement,
wherein a position adjusting portion for adjusting a position of the packing groove with respect to the edge is formed on an inner surface of the frame peripheral wall.

US Pat. No. 10,559,946

PANEL-TYPE ELECTRICAL DEVICE AND ELECTRICAL ASSEMBLY

Schneider Electric (Austr...

1. A panel-type electrical device comprising:a socket assembly adapted to be coupled to a mounting surface and including a socket body and a first pair of mounting parts;
a switch assembly adapted to be coupled to the mounting surface side by side with the socket assembly and including a switch body and a second pair of mounting parts, each of the mounting parts including a first surface facing toward the mounting surface and a second surface facing away from the mounting surface;
a socket panel adapted to cover the socket body;
a switch panel adapted to cover the switch body and move between at least two positions to control an operation state of the switch body, the switch panel being coplanar with the socket panel in one of the at least two positions;
a first pair of cushion blocks adapted to be arranged between the mounting surface and the first surface of the corresponding mounting parts of the socket assembly such that the socket body abuts the switch panel; and
a bracket coupled to the mounting parts of the socket assembly and the switch assembly and comprising windows for exposing the socket body and the switch body,
wherein each of the first pair of cushion blocks comprises a positioning part, and the bracket comprises positioning grooves adapted to receive the respective positioning part, and
wherein the first pair of cushion blocks are integrally formed on the corresponding mounting parts of the socket assembly and foldable between a first position and a second position relative to the corresponding mounting parts of the socket assembly, and the first pair of cushion blocks are in contact with the first surface of the corresponding mounting parts of the socket assembly in the first position and in contact with the second surface of the corresponding mounting parts of the socket assembly in the second position.

US Pat. No. 10,559,945

INSULATIVE BOOTS AND POWER DISTRIBUTION ASSEMBLIES

SIEMENS INDUSTY, INC., A...

1. A power distribution system comprising:a first conductor having a first conductor end and a first shape in cross-section;
a second conductor having a second conductor end and a second shape in cross-section;
a splice coupling the first conductor end to the second conductor end; and
an insulative boot comprising:
a first portion moveable relative to a second portion, the insulative boot being in a closed state when the first portion abuts the second portion, and the insulative boot being in an open state when the first portion is spaced from the second portion;
a first opening at a first end, the first opening having the first shape when the insulative boot is in the closed state, the first opening encompassing the first conductor end when the insulative boot is in the closed state,
wherein the first shape includes a first concave region, and
wherein the first end of the insulative boot includes a first flange at least partially filling the first concave region such that the first flange fits within the first concave region when the insulative boot is in the closed state so that the first concave region is made inaccessible to physical contact when the insulative boot is applied to the first conductor;
a second opening at a second end, the second opening having the second shape when the insulative boot is in the closed state, the second opening encompassing the second conductor end when the insulative boot is in the closed state; and
a cavity between the first end and the second end, wherein the cavity is configured to encompass the splice when the insulative boot is in the closed state.

US Pat. No. 10,559,944

SPARK PLUG FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. A spark plug for an internal combustion engine comprising:a cylindrical housing;
a cylindrical insulator held inside the housing;
a center electrode held inside the insulator so that a tip end portion protrudes;
a ground electrode forming a spark discharge gap between the center electrode and the ground electrode; and
a conductive glass filled in the insulator so as to be located at a base end side of the center electrode, wherein
the center electrode has a locking portion locked from the base end side to a step portion formed on an inner peripheral surface of the insulator, and an electrode head closer to the base end side than the locking portion is;
the electrode head has a base end surface on which a concave portion is partially formed; and
the concave contour, which is an outer peripheral contour of the concave portion when viewed in a plug axis direction, forms a closed curve which is spaced apart from a head contour, which is an outer peripheral contour of the base end surface of the electrode head, and surrounds the center axis of the center electrode, and
the concave contour has outward portions each protruding toward the head contour and four inward portions each protruding toward the center axis of the center electrode, and wherein
the distance between the concave contour and the head contour is 0.1 mm or more; and
the four inward portions each has an inwardly curved shape protruding toward the center axis.

US Pat. No. 10,559,943

LASER ASSEMBLY WITH SPECTRAL BEAM COMBINING

DAYLIGHT SOLUTIONS, INC.,...

1. A laser assembly that generates an assembly output beam, the laser assembly comprising:a laser subassembly that emits a plurality of spaced apart, substantially parallel laser beams;
a beam adjuster positioned in a path of the laser beams, the beam adjuster adjusting the spacing between the plurality of laser beams;
a transform lens positioned in a path of the laser beams, the transform lens collimating the laser beams and directing the laser beams to spatially overlap at a focal plane of the transform lens;
a wavelength selective beam combiner positioned at the focal plane that combines the lasers beams to provide a combination beam that is directed along a combination axis; and
an output coupler positioned on the combination axis that redirects at least a portion of the combination beam back to the beam combiner as a redirected beam, and transmits a portion of the combination beam as the assembly output beam.

US Pat. No. 10,559,942

LASER DEVICE AND INTERNAL COMBUSTION ENGINE

Ricoh Company, Ltd., Tok...

1. A laser device, comprising:a light source configured to emit light;
an optical system configured to concentrate the light emitted from the light source;
a housing configured to accommodate the optical system; and
a window disposed to the housing, to which the light passed through the optical system is incident, wherein the window includes
an optical window having an exit plane through which the light exits from the optical system, and having a side surface,
an optical window holding member configured to hold the optical window,
a joint between the side surface of the optical window and the optical window holding member to join the optical window to the optical window holding member, and
a protective layer disposed on a surface of the joint, on a side where the light is emitted from the window, wherein the protective layer is a coating.

US Pat. No. 10,559,934

MULTIFUNCTIONAL ROTARY DATA MEMORY

SHENZHEN DNS INDUSTRIES C...

1. A multifunctional rotary data memory, comprising a housing, a master control module, a memory, a first connector, and a second connector, wherein the housing comprises an upper housing having a first side wall between a first baseplate and a first cover and a lower housing having a second side wall between a second baseplate and a second cover, the upper housing and the lower housing are movably connected, and the upper housing and the lower housing can relatively and rotatably move around a pivot shaft; the first connector is mounted on the first side wall, the second connector is mounted on the second side wall, and the first connector and the second connector are both communicatively connected to the master control module; the first baseplate and the second baseplate are rotatably connected through the pivot shaft; a first through hole is arranged in a middle of the first baseplate, a second through hole is arranged in a middle of the second baseplate, and the second through hole is communicated with the first through hole for a conductor to pass through; the second baseplate is provided with a plurality of bulges standing and extending outwardly at a periphery of the second through hole, the plurality of bulges are arranged in circular and pass through the first through hole, so as to be served as the pivot shaft; and the first baseplate is provided with a shaft sleeve standing and extending inwardly at a periphery of the first through hole and corresponding to the plurality of bulges, and top portions of at least a part of the plurality of bulges are provided with reverse hooks so as to prevent the bulges from being separated from the first baseplate.

US Pat. No. 10,559,933

MANUAL DISCONNECT WITH CONNECTOR POSITION ASSURANCE ASSEMBLY

Lear Corporation, Southf...

1. A manual disconnect for an electric circuit comprising:a base including primary terminals and an interlock connector;
a plug assembly including fuse terminals and an interlock resistor assembly, the plug assembly adapted to be moved relative to the base between a disconnected position, wherein the fuse terminals are not engaged with respective primary terminals, a primary circuit engaged position, wherein the fuse terminals are engaged with respective primary terminals, and an interlock position, wherein the interlock connector is engaged with the interlock resistor assembly; and
a connector position assurance assembly including a connector position assurance button movable relative to the plug assembly between a pre-lock position and an assurance position, wherein the connector position assurance assembly prevents the plug assembly from rotating relative to the base;
wherein the plug assembly is adapted to be moved in an insertion direction relative to the base to move the plug assembly from the disconnected position to the primary circuit engaged position, and the plug assembly is adapted to be rotated about an axis relative to the base to move the plug assembly from the primary circuit engaged position to the interlock position.

US Pat. No. 10,559,931

HIGH CIRCUIT COUNT ELECTRICAL CONNECTOR

Ford Global Technologies,...

1. An electrical connector comprising: a plurality of contact traces extending along a circumference of a tapered post, on a plurality of respective planes perpendicular to a post axis; and a tapered cup positioned over the tapered post, having a plurality of inward facing terminal contacts corresponding to the plurality of contact traces, wherein the terminal contacts are configured to maintain contact as the tapered cup rotates about the post axis, wherein the tapered post comprises a plurality of channels corresponding to a number of contact traces on the plurality of respective planes, wherein the plurality of channels are positioned on an outside surface of the tapered post and configured to align wiring coupled to the plurality of contact traces, wherein the outside surface corresponds to an outer circumference of the tapered post, and wherein a first plane of the plurality of respective planes comprises a different number of contact traces than a second plane of the plurality of respective planes.

US Pat. No. 10,559,929

ELECTRICAL CONNECTOR SYSTEM HAVING A PCB CONNECTOR FOOTPRINT

TE CONNECTIVITY CORPORATI...

1. A printed circuit board (PCB) for an electrical connector having signal contacts and ground contacts extending from a mounting end of the electrical connector, the PCB comprising:a substrate having a plurality of layers, the substrate having a connector surface configured to face the electrical connector and a PCB connector footprint on the connector surface defined below a footprint of the electrical connector, the PCB connector footprint being an area defined along a longitudinal axis and a lateral axis perpendicular to the longitudinal axis, the PCB connector footprint being subdivided into PCB column grouping footprints generally arranged in columns parallel to the longitudinal axis;
signal vias at least partially through the substrate, the signal vias being arranged in pairs arranged along a signal pair axis with a plurality of pairs of signal vias in each PCB column grouping footprint, the signal pair axis being non-parallel to the longitudinal axis, the pairs of signal vias being aligned in the corresponding columns parallel to the longitudinal axis, the pairs of signal vias being arranged in corresponding rows parallel to the lateral axis, the signal pair axis being non-parallel to the lateral axis, the signal pair axis being non-parallel to the longitudinal axis, wherein the signal pair axis intersects the longitudinal axis at a greater angle than the signal pair axis intersects the lateral axis; and
ground vias at least partially through the substrate, the ground vias being arranged around each of the pairs of signal vias to provide electrical shielding around each of the pairs of signal vias, wherein at least one ground via is arranged between adjacent pairs of signal vias within the PCB column grouping footprints and wherein at least one ground via is arranged between adjacent pairs of signal vias in adjacent PCB column grouping footprints.

US Pat. No. 10,559,928

ELECTRIC CONNECTOR

DAI-ICHI SEIKO CO., LTD.,...

1. An electric connector comprising:a contact member that electrically connects a signal transmission line of a connecting object to a signal conducting path of a connected object; and
a shell member electrically connects a ground transmission line of the connecting object to a ground conducting path of the connected object;
wherein the shell member includes
a first shell, disposed in a state of facing the connected object, that entirely covers the contact member and
a second shell disposed to face the first shell and disposed between the connecting object and the connected object,
wherein the first shell has a connecting object ground contact point which comes to be electrically connected to the ground transmission line provided on the connecting object, and has a connected object ground contact point which comes to be electrically connected to the ground conducting path provided on the connected object,
the second shell has a connecting object ground contact point which comes to be electrically connected to the ground transmission line provided on the connecting object, and has a connected object ground contact point which comes to be electrically connected to the ground conducting path provided on the connected object, and
wherein the first shell is disposed in a state of entirely covering the contact member without gaps from above,
the second shell is disposed to cover the contact member from below.

US Pat. No. 10,559,927

SWITCHABLE RJ45/ARJ45 JACK

Panduit Corp., Tinley Pa...

1. A communication connector, comprising:a housing configured for receiving a communication plug;
a printed circuit board at least partially within said housing;
a rocker switch at least partially within said housing, said rocker switch configured to rotate about a pivot point for actuating said printed circuit board; and
a translating crossbar at least partially within said housing, said translating crossbar engaging said rocker switch and causing said rocker switch to rotate about the pivot point.

US Pat. No. 10,559,925

COAXIAL CABLE CONNECTOR INTERFACE FOR PREVENTING MATING WITH INCORRECT CONNECTOR

CommScope Technologies LL...

1. An interface blocking coaxial connector, interconnectable with a mating coaxial connector, comprising:an inner contact defining a longitudinal axis;
a cylindrical outer contact with an axially-extending outer body and a plurality of spring fingers positioned radially inward of the outer body, the outer body and the spring fingers forming a gap to receive an outer conductor cylinder of the mating coaxial connector; and
a dielectric sleeve positioned between the inner contact and the spring fingers, the sleeve having a stop face that is substantially aligned with distal ends of the spring fingers, such that the sleeve interferes with the outer conductor cylinder of a mismating connector.

US Pat. No. 10,559,924

CONNECTOR

YAZAKI CORPORATION, Toky...

1. A connector comprising:a tubular inner housing configured to hold connecting terminals therein;
a tubular outer housing configured to surround an outer periphery of the inner housing and to be slidable in a fitting direction;
a locking mechanism configured to lock the inner housing with a mating connector at a fitting position;
a spring member configured to bias the inner housing to a rear in the fitting direction to push back the inner housing with respect to the outer housing when a fitting operation is released in a state that the inner housing is in a half fitting position; and
a pushback regulating portion that regulates a position where the inner housing is pushed back to the rear in the fitting direction,
wherein the pushback regulating portion includes:
a claw portion that protrudes from a first sliding surface of one of the inner housing and the outer housing;
a stepped portion that is provided on a second sliding surface of the other of the inner housing and the outer housing and is configured to abut against the claw portion when the inner housing is pushed back; and
a sliding load portion that makes a sliding frictional force between the first sliding surface and the second sliding surface at a predetermined timing before the claw portion and the stepped portion abut against each other to be larger than the sliding frictional force before the predetermined timing; and
wherein the sliding load portion includes:
a first protruding portion provided at a position closer to the stepped portion than the claw portion of the first sliding surface; and
a second protruding portion provided on the second sliding surface to be capable of getting over the first protruding portion.

US Pat. No. 10,559,915

RUGGEDIZED ELECTRICAL RECEPTACLE

Amphenol Corporation, Wa...

1. A ruggedized electrical receptacle, comprising:a shell including an inner surface defining an inner receiving area having front and rear sections, the front section being configured to receive an interface of a mating connector;
a contact subassembly received in the shell, the contact subassembly comprising,
a contact printed circuit board with first and second opposing faces,
a plurality of interface contacts coupled to the first face of the contact printed circuit board and a plurality of termination contacts coupled to the second face of the contact printed circuit board, and
an overmold overmolded onto the contact subassembly, the overmold surrounding the contact printed circuit board such that free ends of the plurality of interface contacts are exposed and extend toward the front section of the shell for engaging the mating connector and tail ends of the plurality of termination contacts are exposed and extend toward the rear section of the shell for engagement with a main printed circuit board; and
an internal sealing member disposed between an outer surface of the overmold and the inner surface of the shell, thereby creating a seal therebetween.

US Pat. No. 10,559,906

SECUREMENT OF SOLDER UNIT UPON CONTACT

FU DING PRECISION COMPONE...

1. An electronic component comprising:a module sub-assembly including at least a first module a second module, the first module forming a plurality of first conductive pads, the second module forming a plurality of second conductive pads;
a connecting part including a body and a plurality of contact tails on two sides of the body to be respectively soldered upon the first conductive pads and the second conductive pads, respectively;
each of said contact tails including a mounting pad defining opposite top surface and undersurface with a through hole extending therethrough in a vertical direction; and
a plurality of solder units each secured to the corresponding mounting pad before a reflow process, and filling the corresponding through hole after the reflow process and extending below the undersurface to secure the mounting pad and the conductive pad together; whereinbefore the reflow process, the solder unit is located upon the top surface of the mounting pad and grasped by a folded section of the mounting pad.

US Pat. No. 10,559,901

ELECTRICAL CONNECTOR

LOTES CO., LTD, Keelung ...

1. An electrical connector, configured to be electrically connected to a chip module, comprising:a body, configured to carry upward the chip module, and provided with a plurality of accommodating holes; and
a plurality of terminals, respectively correspondingly accommodated in the accommodating holes, wherein each of the terminals comprises a base, a first arm and a second arm, the base is configured to be connected to a strip, the first arm is formed by extending upward from the base, and the second arm is formed by extending upward from the first arm and is configured to abut the chip module,
wherein one side of the first arm is formed by tearing from the strip, and two opposite sides of the second arm are both formed by blanking the strip, burrs formed on the two opposite sides of the second arm are located on a same surface of the second arm, and another surface of the second arm that does not have burrs is configured to abut the chip module.

US Pat. No. 10,559,899

MARKER-HOLDER DEVICE FOR A TERMINAL BLOCK

TE CONNECTIVITY SERVICES ...

1. A marker-holder system for an electrical terminal block comprising a longitudinal marker-holder device according to a direction of extension, the marker-holder device comprising a central part with a thinned portion and a first end in the direction of extension and a second end in the direction opposite to the direction of extension, the system comprising a first fastener disposed on the terminal block, the first end and/or the second end of the marker-holder device being rotatably secured to the first fastener in a removable manner so that the marker-holder device rotates between a first position in which a first face of the marker-holder device is oriented towards the terminal block and a second face of the marker-holder device is oriented in a direction opposite to the terminal block, and a second position in which the first face of the marker-holder device is oriented in a direction opposite to the terminal block and the second face of the marker-holder device is oriented towards the terminal block, so that a first marker positioned on the first face will be visible in the second position, and a second marker positioned on the second face will be visible in the first position, when the marker-holder device is rotatably secured to the first fastener, and wherein the thinned portion is divisible.

US Pat. No. 10,559,895

CONNECTION ADAPTER FOR CONNECTING AN EARTHING LINE TO A METAL PROTECTIVE HOSE

Wieland Electric GmbH, B...

2. A connection adapter for connecting an earthing line to a metal protective hose, comprising:a line contact having at least one ring segment configured to rest on an outer sheath of the earthing line, wherein the line contact is crimped on the earthing line;
a hose contact having a contact tab configured to rest on an inner sheath of the metal protective hose; and
a flange-like disc forming an opening, comprising:
a disc face, the ring sleeve extending from the disc face;
a counter-face remote from the disc face; and
a contact tab that extends from the counter-face.

US Pat. No. 10,559,894

METHOD OF MANUFACTURING CONNECTION STRUCTURE, WIRE HARNESS, AND DEVICE FOR MANUFACTURING CONNECTION STRUCTURE

FURUKAWA ELECTRIC CO., LT...

1. A method of manufacturing a connection structure, comprising:separating a crimp terminal from a terminal connecting belt coupled to a carrier formed in a band shape;
inserting, after the separating, at least an electric wire tip portion of an insulated wire into a crimping portion of the crimp terminal separated from the terminal connecting belt; and
crimping, after the inserting, the crimping portion of the crimp terminal into which the electric wire tip portion has been inserted such that a crimping blade holds and crimps the crimping portion and that a crimp connection is formed on the insulated wire,
wherein the insulated wire comprises a conductor and an insulating covering that covers the conductor such that the insulated wire has the electric wire tip portion on a tip side of the insulated wire, the carrier has a band shape, the crimp terminal is one of a plurality of crimp terminals connected to the carrier through the terminal connecting belt such that the plurality of crimp terminals is connected to the carrier along a latitudinal direction of the carrier at predetermined intervals in a longitudinal direction of the carrier, each of the crimp terminals has a closed-barrel shape, and the separating of the crimp terminal comprises separating the crimp terminal from the terminal connecting belt by a separating blade while the crimping blade pinches the crimping portion of the crimp terminal, and
wherein the method further comprises:
stripping, before the separating, the insulating covering from the tip side of the insulated wire such that the electric wire tip portion is formed;
applying, after the stripping and before the separating, a mark on the insulating covering at a predetermined position based on a length of the electric wire tip portion inserted into the crimping portion; and
testing, after the stripping, the applying, the separating, the inserting, and the crimping, a state of the crimping of the electric wire tip portion to the crimping portion using the mark.

US Pat. No. 10,559,891

FLAT PANEL ARRAY ANTENNA WITH INTEGRATED POLARIZATION ROTATOR

CommScope Technologies LL...

1. A panel array antenna, comprising:an input layer comprising a waveguide network coupling an input feed on a first side thereof to a plurality of primary coupling cavities on a second side thereof; and
an output layer on the second side of the input layer, the output layer comprising a monolithic layer including an array of horn radiators, respective horn radiator inlet ports in communication with the horn radiators, and respective slot-shaped output ports in communication with the respective horn radiator inlet ports to couple the horn radiators to the primary coupling cavities,
wherein the horn radiators, the respective horn radiator inlet ports, and the respective slot-shaped output ports comprise respective orientations that are rotated relative to one another,
wherein the respective horn radiator inlet ports are confined within edges of the horn radiators coupled thereto in plan view, and
wherein the monolithic layer is configured to provide respective output signals from the horn radiators having a polarization orientation that is rotated by a desired polarization rotation angle relative to respective input signals received at the respective slot-shaped output ports coupled thereto.

US Pat. No. 10,559,888

SATELLITE GROUND TERMINAL UTILIZING FREQUENCY-SELECTIVE SURFACE DIPLEXER

HUGHES NETWORK SYSTEMS, L...

1. A very small aperture terminal (VSAT) for a satellite communication system, comprising:a reflector having a prime focus;
a first feed located at the prime focus of the reflector and in optical communication with the reflector;
a frequency-selective surface module having a reflected focus and located at a point along a communication path between the reflector and the first feed, wherein the frequency-selective surface module is configured to be transparent to a first set of frequencies such that a first signal within the first set of frequencies transmitted on a carrier signal passes through the frequency-selective surface module; and wherein the frequency-selective surface module is configured to be reflective to a second set of frequencies such that a second signal within the second set of frequencies transmitted on a carrier signal is reflected; and
a second feed located at the reflected focus of the frequency-selective surface module and in optical communication with the frequency-selective surface module, wherein each of the first and second feed is configured to transmit uplink signals within the first set of frequencies or receive downlink signals within the second set of frequencies,
wherein the frequency-selective surface module comprises a non-metallic base with a plurality of metallic traces embodied thereon, wherein the plurality of metallic traces are arranged in a pattern designed to allow a signal within the first set of frequencies to pass through the frequency-selective surface module, wherein the pattern comprises one or more of: strip gratings having a periodic array of conductive strips, mesh patterns, and cross-mesh patterns, and wherein the frequency-selective surface module comprises a horizontal adjustment support for adjusting a position of a surface of the frequency-selective surface module in a horizontal direction to ensure that the second feed is located at the reflected focus of the frequency-selective surface module.

US Pat. No. 10,559,877

INTEGRATED CAMERA AND COMMUNICATION ANTENNA

VEONEER US INC., Southfi...

1. An apparatus comprising:a windshield mount configured to mount a camera lens assembly to a windshield of a vehicle, wherein said camera lens assembly is configured to provide a forward view and an upward view through said windshield of said vehicle;
a camera lens attached to said camera lens assembly such that a field of view of said camera lens is aligned with a horizontal plane and is directed toward the front of said vehicle; and
a single printed circuit board mounted within said camera lens assembly at an angle to said camera lens, said single printed circuit board comprising an antenna, a ground plane, and an image sensor, wherein (i) said antenna is disposed on a front surface of said single printed circuit board such that said antenna is angled above said field of view of said camera lens and has open sky visibility directed towards a portion of the sky above said vehicle, (ii) said ground plane is disposed either on said front surface or within a layer of said single printed circuit board, (iii) said image sensor is mounted on a back surface of said single printed circuit board, and (iv) said camera lens assembly is configured to focus an image of the forward view through said windshield and said camera lens onto said image sensor.

US Pat. No. 10,559,866

MEASURING OPERATIONAL PARAMETERS AT THE GUIDED SURFACE WAVEGUIDE PROBE

CPG TECHNOLOGIES, INC, I...

1. An apparatus comprising:a guided surface waveguide probe configured to launch a guided surface wave along a surface of a lossy conducting medium, wherein the guided surface waveguide probe comprises:
a charge terminal elevated to a height above the lossy conducting medium;
a support structure that supports the charge terminal;
at least one section of internal coil that is supported within the support structure and is coupled to an excitation source;
a conductive tube having a first end conductively coupled to the at least one section of internal coil, wherein a second end of the conductive tube extends vertically towards the charge terminal, wherein the at least one section of the internal coil is electrically coupled to the charge terminal via the conductive tube;
at least one sensor electrically coupled to the charge terminal or the internal coil, wherein the at least one sensor measures an operational parameter of the guided surface waveguide probe; and
a non-conductive channel connected to the at least one sensor and monitoring equipment of the guided surface waveguide probe by which data associated with the operational parameter is communicated.

US Pat. No. 10,559,863

DYNAMIC METAL-ANODE FLOW BATTERY ENERGY-STORAGE SYSTEM

NATIONAL TAIPEI UNIVERSIT...

1. A dynamic metal-anode flow battery energy-storage system, comprising:a discharge module including at least one metal-air battery which includes a plurality of discharge reactants in a first electrolyte, wherein the discharge reactants react with oxygen in air to form a plurality of discharged products and discharge electric energy;
a charging module, being electrically connected to the discharge module and including at least one electrolysis device and at least one removal device, wherein the at least one electrolysis device includes a conductive member and a plurality of electrolysis reactants immersed in a second electrolyte; the electrolysis reactants are electrolyzed to form a plurality of electrolysis products which are adhered to a surface of the conductive member; the electrolysis products and the discharge reactants are of the same material; the at least one removal device includes a scraper adapted to remove the adhered electrolysis products from the surface of the conductive member; and
a delivery device adapted to deliver the electrolysis products into the first electrolyte as the discharge reactants, and deliver the discharged products into the second electrolyte as the electrolysis reactants.

US Pat. No. 10,559,856

BATTERY

AutoNetworks Technologies...

1. A battery comprising:a plurality of cells, each of which has two electrodes, the plurality of cells are arranged in two rows so that the two electrodes of each cell oppose those of another, the two adjacent cells in each row are arranged so that electrodes of different polarities are adjacent to each other, and the adjacent electrodes of different polarities are electrically connected to each other;
a control unit for controlling charge and discharge of the plurality of cells, the control unit having a circuit board; and
a housing that contains the plurality of cells and the control unit, the housing having a first side on which first and second terminals are provided;
wherein the first and second terminals are arranged on the first side, facing in the same direction;
wherein a terminal side cell of the plurality of cells is disposed closest to the first terminal is connected to the first terminal;
wherein a control unit side cell of the plurality of cells is disposed adjacent to the control unit is connected to the second terminal via the control unit;
wherein the control unit is disposed closest to the second terminal among the plurality of cells and the control unit; and
wherein a folding portion that returns a current path between the first and second terminals is provided between the terminal side cell and the control unit side cell, the folding portion is located closer to a second side of the housing than to the first side of the housing, the second side being located opposite to the first side, and the folding portion is composed of a wiring member that connects electrodes of different polarities of at least one pair of opposite cells in the different rows.

US Pat. No. 10,559,855

RECHARGEABLE ALUMINUM ION BATTERY

EVERON24 LLC, Bedford, M...

1. An aluminum-ion battery comprising:an anode comprising aluminum, an aluminum alloy or an aluminum compound;
a cathode that comprises at least one active material, wherein the at least one active material comprises a manganese oxide doped with one or more of iodine, nitrogen, boron and phosphorus;
a porous separator comprising an electrically insulating material that prevents direct contact of the anode and the cathode; and
an electrolyte comprising a solution of an aluminum salt, wherein the electrolyte is in contact with the anode and the cathode.

US Pat. No. 10,559,851

MAGNESIUM BATTERY ELECTROLYTE

TOYOTA JIDOSHA KABUSHIKI ...

1. A magnesium battery electrolytic solution comprising a solute of an organic boron magnesium salt blended with an aprotic polar solvent, wherein:the concentration of the organic boron magnesium salt is 0.2 to 1 mol/L;
the aprotic polar solvent is an ether; and
the organic boron magnesium salt is an organic boron magnesium salt complex having a structure of R3B—(R?MgX)2, where R and R? are the same or different and each represent a fluoroaryl group, an alkylated aryl group, an aryl group, an alkyl group, or a pyrrolidinyl group, and X represents a halogen, and wherein R3B is a Lewis acid with a boron center that is at least one selected from the group consisting of compounds represented by the following structural formulae:

US Pat. No. 10,559,838

OXYGEN SENSING DEVICE WITH CAPABILITY OF STORING ENERGY, RELEASING ENERGY, GENERATING SPECIFIC GAS AND REMOVING HARMFUL GAS

YUAN ZE UNIVERSITY, Taoy...

1. An electrochemical catalytic converter for a vehicle, comprising:a converting unit, comprising:
a first conductive catalyst layer;
a second conductive catalyst layer; and
a solid oxide electrolyte, disposed between the first conductive catalyst layer and the second conductive catalyst layer;
a control switch, electrically connected to the second conductive catalyst layer;
a gas storing unit, for storing a first specific gas generated by the converting unit; and
a control unit, electrically coupled to an oxygen sensing unit, comprising:
a voltmeter, for detecting a voltage of the converting unit, wherein the voltmeter is electrically connected to the first conductive catalyst layer and the second conductive catalyst layer through a first switch and the control switch;
a power output circuit, for outputting an electric power, wherein the converting unit causes a reaction of the hydrocarbons stored in the gas storing unit for generating the electric power to the power output circuit, wherein the power output circuit further comprises:
a third switch;
a resistor, electrically connected to the third switch, wherein the two ends of the resistor are connected to a backup battery;
a voltage regulator, one end of the voltage regulator being electrically connected to the converting unit, and the other end of the voltage regulator being electrically connected to the control switch;
a power source, wherein the power source is electrically connected to the first conductive catalyst layer and the second conductive catalyst layer through a second switch and the control switch; and
a judgment circuit, for adjusting the conducting status of the control switch, the first switch, the second switch and the third switch according to different states of the electrochemical catalytic converter for a vehicle;
when the control switch is turned off, the backup battery provides an electric power to boost the vehicle when a starting battery of the vehicle is discharged, and
when the control switch is turned on, the voltage regulator is used for boosting the voltage of the electric power generated by the converting unit to charge the starting battery.

US Pat. No. 10,559,830

GRAPHENE FOAM-PROTECTED METAL FLUORIDE AND METAL CHLORIDE CATHODE ACTIVE MATERIALS FOR LITHIUM BATTERIES

Global Graphene Group, In...

1. A cathode or positive electrode layer for a lithium battery, said cathode layer comprising multiple particles or coating of a cathode active material and a solid graphene foam composed of multiple pores and pore walls, whereina. said pore walls contain a pristine graphene material having less than 0.01% by weight of non-carbon elements or a non-pristine graphene material having 0.01% to 5% by weight of non-carbon elements, wherein said non-pristine graphene is selected from graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, boron-doped graphene, nitrogen-doped graphene, chemically functionalized graphene, or a combination thereof;
b. said cathode active material particles or coating is selected from a metal fluoride or metal chloride, has a size from 1 nm to 10 ?m, and is in an amount from 1% to 99.9% by weight based on the total weight of said graphene foam and said cathode active material combined; and
c. some of said multiple pores are lodged with said particles or coating of the cathode active material, and said graphene foam is sufficiently elastic to accommodate volume expansion and shrinkage of said particles or coating of the cathode active material during a battery charge-discharge cycle to avoid expansion of said cathode layer.

US Pat. No. 10,559,820

NONAQUEOUS ELECTROLYTE BATTERY, BATTERY PACK AND VEHICLE

KABUSHIKI KAISHA TOSHIBA,...

1. A nonaqueous electrolyte battery comprising:a positive electrode;
a negative electrode comprising a negative electrode active material layer comprising particles of a niobium-and-titanium-containing composite oxide;
a separator layer provided between the positive electrode and the negative electrode, the separator layer comprising insulating particles;
an intermediate region provided between the negative electrode active material layer and the separator layer, the intermediate region comprising a carbonaceous material; and
a gel nonaqueous electrolyte,
wherein at least a part of the gel nonaqueous electrolyte is held in the separator layer and the intermediate region, and
the nonaqueous electrolyte battery satisfies a volume ratio VA/VB of 5 or more,
where VA is a volume of the intermediate region, and
VB is an average volume of gaps among the particles of the niobium-and-titanium-containing composite oxide in the negative electrode active material layer, and
wherein the negative electrode active material layer comprises a recessed part which faces the separator layer, and the intermediate region is provided in the recessed part.

US Pat. No. 10,559,815

METHOD OF PRODUCING MULTI-LEVEL GRAPHENE-PROTECTED CATHODE ACTIVE MATERIAL PARTICLES FOR BATTERY APPLICATIONS

Global Graphene Group, In...

1. A method of producing a mass of graphene-embraced particulates or secondary particles directly from a graphitic material for use as a lithium-ion battery cathode active material, said method comprising:a) mixing multiple particles of a graphitic material and multiple primary particles of a solid cathode active material and optional ball-milling media to form a mixture in an impacting chamber of an energy impacting apparatus, wherein said graphitic material has never been previously intercalated, oxidized, or exfoliated and said impacting chamber contains therein no previously produced isolated graphene sheets;
b) operating said energy impacting apparatus with a frequency and an intensity for a length of time sufficient for peeling off graphene sheets from said particles of graphitic material and transferring said peeled graphene sheets to surfaces of said primary particles of said solid cathode active material and fully embrace or encapsulate said primary particles to produce graphene-embraced or graphene-encapsulated primary particles of said cathode active material inside said impacting chamber;
c) recovering said graphene-embraced or graphene-encapsulated primary particles from said impacting chamber, wherein at least one of said embraced or encapsulated primary particles contains multiple graphene sheets of a first graphene material embracing or encapsulating at least one of said primary particles; and
d) combining a mass of said recovered graphene-embraced or graphene-encapsulated primary particles, an optional conductive additive, and graphene sheets of a second graphene material into a mass of graphene-embraced particulates, wherein said particulate comprises a single or a plurality of graphene-encapsulated primary particles of an cathode active material, comprising a primary particle of said cathode active material and multiple sheets of first graphene material overlapped together to embrace or encapsulate said primary particle, and wherein said single or a plurality of graphene-encapsulated primary particles, along with an optional conductive additive, are further embraced or encapsulated by multiple sheets of a second graphene material, wherein said first graphene material is the same as or different from said second graphene material, and wherein said first graphene and said second graphene material is each in an amount from 0.01% to 20% by weight and said optional conductive additive is in an amount from 0% to 50% by weight, all based on the total weight of said particulate.

US Pat. No. 10,559,796

BATTERY CARRIER FOR A VEHICLE

Benteler Automobiltechnik...

1. A battery carrier for accommodating at least one electric battery module in a vehicle, with:at least one first wall comprising a carrier bottom or a carrier cover;
at least one second wall comprising at least one side wall, wherein the at least one second wall is arranged at a non-parallel angle with respect to the at least one first wall, wherein the second wall is joined to the first wall by a joining region and laterally limits the at least one first wall, wherein an adhesive region is formed in the joining region; and
at least one seal materially bonded to the adhesive region to fluidically seal the joining region, wherein the adhesive region is configured to condition the joining region for a materially bonded connection to the at least one seal.

US Pat. No. 10,559,786

CELL PACKAGING TECHNIQUES

Apple Inc., Cupertino, C...

1. A battery system comprising:a battery cell, wherein the battery cell comprises an electrode tab extending from an edge of the battery cell; and
a module electrically coupled with the battery cell, wherein:
the module is characterized by a first surface, a height, and a second surface opposite the first surface,
a conductive tab coupled along the first surface of the module extends from a first end parallel to a plane of the first surface,
the conductive tab is characterized by a curvature at a midpoint of the conductive tab,
a distal region of the conductive tab returns back across the first surface of the module parallel to the first surface, and
a distal portion of the electrode tab is fixedly coupled with the distal region of the conductive tab; and
a first water resistant tape extending about the module and across the first end of the conductive tab.

US Pat. No. 10,559,767

FLEXIBLE ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A flexible organic light emitting diode (OLED) display device, comprising: a housing and an OLED display panel disposed in the housing;wherein the housing comprises:
a substrate having at least one first bending section disposed in the middle of the substrate; and
an encapsulation layer covering a surface of the substrate and a surface of the first bending section;
wherein the OLED display panel is disposed on the surface of the substrate, the OLED display panel comprises at least one second bending section, the first bending section is disposed at a position corresponding to the second bending section, and the first bending section is greater than the second bending section;
wherein each of two opposite ends of the substrate is bent and defined an opposite receiving groove and ends of the flexible OLED panel are attached at the respective two receiving grooves;
wherein each of the two ends of the substrate is double-bent and defined a first bending portion and a second bending portion in sequence and the receiving groove is constructed of the first bending portion, the second bending portion, and a portion of the substrate which is adjacent to the first bending portion.

US Pat. No. 10,559,761

LIGHT-EMITTING MATERIAL, AND ORGANIC ELECTROLUMINESCENT DEVICE

Kyulux, Inc., Fukuoka (J...

1. An organic electroluminescent device comprising a pair of electrodes and one layer or plural layers including at least a light emitting layer intervening between the electrodes, the light emitting layer containing as a host material thereof a light-emitting material comprising a compound having a carbazole ring structure represented by the following general formula (1):
wherein A1 and A2 may be the same or different, and each represents a divalent group of a substituted or unsubstituted aromatic hydrocarbon or a divalent group of a substituted or unsubstituted condensed polycyclic aromatics;
A3 represents a divalent group of a substituted or unsubstituted aromatic hydrocarbon, a divalent group of a substituted or unsubstituted condensed polycyclic aromatics, or a single bond; B represents a substituted or unsubstituted pyridyl, bipyridyl, terpyridyl, pyrimidinyl, pyrazinyl, pyridazinyl, triazinyl, pyrrolyl, pyrazolyl, imidazolyl, triazolyl, oxazolyl, isoxazolyl, thiazolyl, isothiazolyl, oxadiazolyl, thiadiazolyl, fury!, thienyl, quinolyl, isoquinolyl, quinoxalinyl, quinazolinyl, naphthyridinyl, indolyl, isoindolyl, benzoimidazolyl, benzotriazolyl, benzofuranyl, benzothienyl, benzoxazolyl, benzoxadiazolyl, benzothiazolyl, benzothiadiazolyl, pyridopyrrolyl, pyridoimidazolyl, pyridotriazolyl, pteridinyl, acridinyl, phenazinyl, phenanthrolinyl, phenoxazinyl, phenothiazinyl, phenocelenazinyl, phenotellurazinyl, phenophosphinazinyl, carbolinyl, dibenzofuranyl, dibenzothienyl, or xanthenyl;
and R1 to R15 may be the same or different, and each represents a hydrogen atom, a deuterium atom, a fluorine atom, a chlorine atom, cyano, nitro, linear or branched alkyl of 1 to 20 carbon atoms that may have a substituent, cycloalkyl of 5 to 10 carbon atoms that may have a substituent, linear or branched alkenyl of 2 to 20 carbon atoms that may have a substituent, linear or branched alkyloxy of 1 to 20 carbon atoms that may have a substituent, cycloalkyloxy of 5 to 10 carbon atoms that may have a substituent, a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, a substituted or unsubstituted condensed polycyclic aromatic group, a substituted or unsubstituted aryloxy group, or a disubstituted amino group substituted with an aromatic hydrocarbon group, an aromatic heterocyclic group, or a condensed polycyclic aromatic group, and may bind to each other via a single bond, a substituted or unsubstituted methylene, an oxygen atom, or a sulfur atom, to form a ring and wherein the organic electroluminescent device emits delayed fluorescence.

US Pat. No. 10,559,749

MAGNETORESISTIVE EFFECT ELEMENT

TDK CORPORATION, Tokyo (...

1. A magnetoresistive effect element comprising:a first ferromagnetic layer as a magnetization fixed layer;
a second ferromagnetic layer as a magnetization free layer; and
a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer,
wherein the nonmagnetic spacer layer comprises an Ag alloy represented by General Formula (1), and thereby lattice mismatch between the nonmagnetic spacer layer, and the first ferromagnetic layer and/or the second ferromagnetic layer is reduced, compared to lattice mismatch when the nonmagnetic spacer layer is formed of Ag,
Ag?X1-?  (1)
where X indicates one element selected from the group consisting of Cu, Ga, Ge, As, Y, La, Sm, Yb, and Pt, and 0 wherein at least one of the first ferromagnetic layer and the second ferromagnetic layer comprises a Heusler alloy represented by General Formula (2),
Co2L?M?  (2)
where L is at least one or more elements of Mn and Fe, M indicates one or more elements selected from the group consisting of Si, Al, Ga, and Ge, 0.7

US Pat. No. 10,559,733

LIGHT-EMITTING DEVICE PACKAGE

LG INNOTEK CO., LTD., Se...

1. A light-emitting device package comprising;a body;
N (N denoting a positive integer of 5 or more) upper pads disposed on the body so as to be spaced apart from each other;
N?1 light-emitting device chips respectively disposed on N?1 upper pads, among the N upper pads; and
a plurality of first wires configured to electrically connect the N?1 light-emitting device chips and the N upper pads to each other,
wherein a first upper pad and an Nth upper pad, among the N upper pads, face each other at an outermost peripheral region of a plane of the light-emitting device package,
wherein the remaining second to N?1th upper pads, excluding the first and Nth upper pads, among the N upper pads are completely surrounded by the first and Nth upper pads in a plan view so that one of the first and Nth upper pads is between each of the remaining second to N?1th upper pads and an edge of the body, and
wherein a light-emitting device chip of the N?1 light-emitting device chips is disposed on one among the first and Nth upper pads and is not disposed on the other among the first and Nth upper pads.

US Pat. No. 10,559,732

SURFACE-MOUNTED LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTO ELECTRO...

5. A method of fabricating a surface-mounted light-emitting diode (LED) light-emitting device, the method comprising:1) epitaxial growth: form an LED epitaxial structure over a growth substrate through epitaxial growth;
2) chip fabrication:
determine P and N electrode regions and an isolating region on a surface of the LED epitaxial structure; and
fabricate P and N electrode pads and an insulator over the P and N electrode regions and the isolating region, respectively on the surface of the LED epitaxial structure,
wherein the insulator fabricated on the surface of the LED epitaxial structure has opposite a first insulator surface and a second insulator surface,
wherein the first insulator surface is adjacent to the LED epitaxial structure and the second insulator surface extrudes beyond either of the second electrode surfaces of the P and N electrode pads to prevent the P and N electrode pads from short circuiting when directly applied in the SMT packaging;
wherein the P and N electrode pads have sufficient thicknesses to support the LED epitaxial structure, and the insulator is formed between the P and N electrode pads to prevent the P and N electrode pads from a short circuit;
remove the growth substrate and unitize the LED epitaxial structure to form a LED chip;
3) Surface-Mounted Technology (SMT) packaging:
provide a supporting substrate and directly mount the P and N electrode pads of the LED chip over the supporting substrate through SMT packaging to thereby form the surface-mounted LED light-emitting device;
wherein in step 3), the supporting substrate has a surface coated with a solder layer with a thickness smaller than or equal to a height difference between the second insulator surface and either of the second electrode surfaces of the P and N electrode pads, wherein the insulator extends through the solder layer and is in contact with the solder layer and the supporting substrate, wherein a distance between edges of the P and N electrode pads beyond that of the LED epitaxial structure is D, a minimum thickness of the P and N electrode pads is T, and wherein D/T is 0.5-2.

US Pat. No. 10,559,730

COLLIMATED LED LIGHT FIELD DISPLAY

APPLIED MATERIALS, INC., ...

1. A method of forming a light field display, comprising:forming a plurality of light emitting diodes from a patterned substrate, comprising:
depositing a resist layer on a surface of a substrate, the substrate comprising:
a structural base;
an active layer stack disposed on the structural base; and
a transparent conductive oxide layer disposed on the active layer stack;
patterning the resist layer; and
transferring the pattern formed in the resist layer to the transparent conductive oxide layer and to at least a portion of the active layer stack disposed therebeneath to form the patterned substrate; and
arranging one or more of the plurality of light emitting diodes beneath a light-directing feature of a plurality of light-directing features formed on a substrate panel, wherein each of the light-directing features and at least one of the one or more light emitting diodes positioned there beneath forms a pixel of angular resolution of the light field display.

US Pat. No. 10,559,727

MANUFACTURING METHOD OF COLORFUL MICRO-LED, DISPLAY MODLUE AND TERMINALS

Shenzhen China Star Optoe...

1. A manufacturing method of colorful Micro-LEDs, comprising:providing a substrate, wherein one side of the substrate is configured with an array having a plurality of blue-light micro-LEDs; the plurality of blue-light micro-LEDs comprise first preset blue-light Micro-LEDs, second preset blue-light Micro-LEDs, and third preset blue-light Micro-LEDs; wherein the first preset blue-light Micro-LEDs are disposed between the second preset blue-light Micro-LEDs and the third preset blue-light Micro-LEDs;
configuring a light emitting surface of the blue-light Micro-LEDs of the array to face upward and immersing the whole substrate into the first-color photosensitive solution;
turning on only the first preset blue-light Micro-LEDs of the array without turning on the second preset blue-light Micro-LEDs and the third preset blue-light Micro-LEDs for conducting polymerization on the first preset blue-light Micro-LEDs to form at least one first lens, and forming a first-color pixel on the at least one first lens;
after the at least one first lens and the first-color pixel are formed, configuring the light emitting surface of the blue-light Micro-LEDs of the array to face upward and immersing the whole substrate into the second-color photosensitive solution;
turning on only the second preset blue-light Micro-LEDs of the array without turning on the first preset blue-light Micro-LEDs and the third preset blue-light Micro-LEDs for conducting the polymerization on the second preset blue-light Micro-LEDs to form at least one second lens, and forming a second-color pixel on the at least one second lens;
wherein the first-color pixel is one of a red pixel and a green pixel, and the second-color pixel is the other of the red pixel and the green pixel.

US Pat. No. 10,559,726

LAYERED STRUCTURES AND QUANTUM DOT SHEETS AND ELECTRONIC DEVICES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A quantum dot sheet comprising:a photoconversion layer comprising a polymer matrix and a plurality of quantum dots dispersed in the polymer matrix; and
a layered structure comprising a first layer comprising a polymerization product of a monomer combination comprising a first monomer having at least two thiol groups at its terminal end and a second monomer having at least two carbon-carbon unsaturated bond-containing groups at its terminal end,
wherein the first monomer comprises a first thiol compound represented by Chemical Formula 1-1 comprising a thioglycolate moiety and a second thiol represented by Chemical Formula 1-2:

wherein in Chemical Formula 1-1,
L1 is a carbon atom, a substituted or unsubstituted C1 to C30 alkylene group, a substituted or unsubstituted C6 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C3 to C30 heteroarylene group, or a substituted or unsubstituted C3 to C30 heterocycloalkylene group,
Y1 is a single bond or a substituted or unsubstituted C1 to C4 alkylene group,
R1 is same or different and each independently hydrogen or C1 to C3 alkyl group,
n is an integer of 2 to 4,
L1 has a valence of at least n,

wherein in Chemical Formula 1-2,
L1 is a carbon atom, a substituted or unsubstituted C1 to C30 alkylene group, a substituted or unsubstituted C6 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C3 to C30 heteroarylene group, or a substituted or unsubstituted C3 to C30 heterocycloalkylene group,
Y2 is a single bond; —(OCH2CH2)m— (wherein m is an integer of 1 to 10), sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), —RB— [wherein R is a C1 to C20 substituted or unsubstituted divalent linear or branched alkylene group, a C1 to C20 substituted or unsubstituted divalent linear or branched alkylene group having at least one methylene replaced with sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), or a combination thereof, or —(OCH2CH2)m— (wherein m is an integer of 1 to 10) and B is sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), or a combination thereof], or a combination thereof,
A is a C2 to C4 divalent alkylene group,
n is an integer of 2 to 4,
L1 has a valence of at least n; and
the second monomer comprises an ene compound represented by Chemical Formula 2:

wherein in Chemical Formula 2,
X is —CR?CR2 or —C?CR (wherein R is each independently hydrogen or a C1 to C3 alkyl group),
R2 is selected from hydrogen; a substituted or unsubstituted C1 to C30 linear or branched alkyl group; a substituted or unsubstituted C6 to C30 aryl group; a substituted or unsubstituted C3 to C30 heteroaryl group; a substituted or unsubstituted C3 to C30 cycloalkyl group; a substituted or unsubstituted C3 to C30 heterocycloalkyl group; a C1 to C10 alkoxy group; a hydroxy group; —NH2; a substituted or unsubstituted alkyl amine group (—NRR?, wherein R and R? are independently hydrogen or a C1 to C30 linear or branched alkyl group provided that both of R and R? cannot be hydrogen at the same time); an isocyanate group; a halogen; —ROR? (wherein R is a substituted or unsubstituted C1 to C20 alkylene group and R? is hydrogen or a C1 to C20 linear or branched alkyl group); an acyl halide (—RC(?O)X, wherein R is a substituted or unsubstituted alkylene group and X is a halogen); —C(?O)OR? (wherein R? is hydrogen or a C1 to C20 linear or branched alkyl group); —CN; —C(?O)ONRR? (wherein R and R? are independently hydrogen or a C1 to C20 linear or branched alkyl group); or a combination thereof,
L2 is a carbon atom, a substituted or unsubstituted C1 to C30 alkylene group, a substituted or unsubstituted C6 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C3 to C30 heteroarylene group, or a substituted or unsubstituted C3 to C30 heterocycloalkylene group,
Y2 is a single bond; a substituted or unsubstituted C1 to C30 alkylene group; a substituted or unsubstituted C2 to C30 alkenylene group; or a C1 to C30 alkylene group or a C2 to C30 alkenylene group wherein at least one methylene (—CH2—) group is replaced by sulfonyl (—S(?O)2—), carbonyl (—C(?O)—), ether (—O—), sulfide (—S—), sulfoxide (—S(?O)—), ester (—C(?O)O—), amide (—C(?O)NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), imine (—NR—) (wherein R is hydrogen or a C1 to C10 linear or branched alkyl group), or a combination thereof,
n is an integer of 1 or more,
k3 is an integer of 0 or more,
k4 is an integer of 1 or more, and
the sum of n and k4 is an integer of 3 or more,
provided that n does not exceed the valence of Y2, and
provided that the sum of k3 and k4 does not exceed the valence of L2, and
wherein the layered structure is disposed on at least one surface of the photoconversion layer, wherein the at least one surface of the photoconversion layer faces a surface of the first layer of the layered structure.

US Pat. No. 10,559,722

LIGHT-EMITTING DEVICE

CITIZEN ELECTRONICS CO., ...

1. A light-emitting device comprising:a planar lead frame configured from first and second metal portions which are spaced apart from each other with an insulating resin interposed therebetween;
light-emitting elements mounted on the first metal portion and electrically connected by wires to the first and second metal portions;
a first resin frame disposed on the lead frame so as to enclose the light-emitting elements;
a sealing resin containing a phosphor for converting a wavelength of light emitted from the light-emitting elements, the sealing resin being filled into a region on the lead frame enclosed by the first resin frame to seal the light-emitting elements; and
a second resin frame being harder than the first resin frame and covering an outer surface of the first resin frame at an outer edge of the lead frame.

US Pat. No. 10,559,721

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate;
a light emitting element mounted on the substrate;
a light reflecting resin member surrounding the light emitting element, and configured and arranged to reflect light emitted from the light emitting element;
a sealing member disposed in a region surrounded by the light reflecting, resin member;
an electrically conductive wiring arranged on an upper surface of the substrate such that the substrate includes an exposed region exposed from the electrically conductive wiring with at least a part of the exposed region of the substrate being embedded in the light reflecting resin member, the electrically conductive wiring being electrically connected to the light emitting element; and
a lens member disposed above the light emitting element to reach an outer edge of the substrate, the lens member being in contact with an upper surface of the sealing member and an upper surface and an outer lateral surface of the light reflecting resin member, an entire top surface of the lens member being exposed with the top surface of the lens member defining a part of an outermost surface of the light emitting device.

US Pat. No. 10,559,719

SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING AT LEAST PARTIALLY TRANSPARENT BURIED-CONTACT ELEMENTS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A light-emitting diode device, comprising:a light-emitting diode including—
a first semiconductor material,
a second semiconductor material, and
an active region between the first semiconductor material and the second semiconductor material;
a first contact electrically coupled to the first semiconductor material;
a second contact including a buried-contact element electrically coupled to the second semiconductor material, wherein the buried-contact element has an end portion directly adjacent to the second semiconductor material, and wherein the end portion of the buried-contact element is transparent; and
an optical component disposed over the second semiconductor material, the optical component including—
a transparent matrix, and
color-converting particles within the matrix, wherein the color-converting particles are configured to absorb radiation from the light-emitting diode at a first wavelength within the first wavelength range and to emit radiation at a second wavelength within the second wavelength range different than the first wavelength range,
wherein the light-emitting diode device has an average reflectivity of backscatter radiation from the color-converting particles at the buried-contact element, and wherein the average reflectivity is greater than 75%.

US Pat. No. 10,559,712

QUANTUM DOTS AND DEVICES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A core-shell quantum dot including at least two different halogens,the core-shell quantum dot comprising:
a core comprising a first semiconductor nanocrystal; and
a shell disposed on the core, the shell comprising a crystalline or amorphous material,
wherein the core-shell quantum dot does not include cadmium,
wherein a solid state photoluminescence quantum efficiency of the core-shell quantum dot, when measured at 90° C. or greater, is greater than or equal to about 95% of a solid state photoluminescence quantum efficiency of the core-shell quantum dot when measured at 25° C., and
wherein the at least two different halogens comprise fluorine and at least one of chlorine, bromine, and iodine.

US Pat. No. 10,559,711

BURIED ACTIVATED P-(AL,IN)GAN LAYERS

Gallium Enterprises Pty L...

1. A method of fabricating a semiconductor structure comprising a buried activated magnesium-doped p-(Al,In)GaN layer, comprising:(a) growing a magnesium doped p-(Al,In)GaN layer using a gaseous mixture comprising NH3, H2, or a combination thereof, wherein the gaseous mixture has a partial pressure of H2 less than 760 Torr; and
(b) growing a semiconductor layer on the magnesium-doped p-(Al,In)GaN layer in an environment wherein a partial pressure of H2 is greater than a partial pressure of N2;
to provide a semiconductor structure comprising a buried activated magnesium doped p-(Al,In)GaN layer.

US Pat. No. 10,559,705

MULTIJUNCTION SOLAR CELLS HAVING A GRADED-INDEX REFLECTOR STRUCTURE

SolAero Technologies Corp...

1. A multijunction solar cell comprising:an upper solar subcell having an emitter layer and a base layer forming a photoelectric junction;
a first graded-index reflector structure disposed beneath the base layer of the upper solar subcell; wherein the first graded-index reflector structure comprises a first plurality of pairs of alternating layers of AlxGa(1-x)As and a different semiconductor material, wherein 0 a lower solar subcell disposed beneath the first graded-index reflector structure; wherein the lower solar subcell has an emitter layer and a base layer forming a photoelectric junction;
wherein the first graded-index reflector structure is constructed such that (i) at least a portion of light of a first spectral wavelength range that enters and passes through the upper solar subcell is reflected back into the upper solar subcell by the first graded-index reflector structure; (ii) at least a portion of light of a second spectral wavelength range that enters and passes through the upper solar subcell is transmitted through the first graded-index reflector structure to layers disposed beneath the first graded-index reflector structure, wherein the second spectral wavelength range is composed of greater wavelengths than the wavelengths of the first spectral wavelength range.

US Pat. No. 10,559,704

IN-PLANE RESONANT-CAVITY INFRARED PHOTODETECTORS WITH FULLY-DEPLETED ABSORBERS

The Government of the Uni...

1. A resonant-cavity infrared detector, comprising:a substrate;
a bottom mirror formed on an upper surface of the substrate;
an n-type region formed on an upper surface of the bottom semiconductor mirror;
an absorber region having a thickness of less than 50 nm formed on an upper surface of the n-type region;
a p-type region formed on an upper surface of the absorber layer; and
a top mirror formed on an upper surface of the p-type region;
wherein each of the bottom mirror and the top mirror comprises a dielectric Bragg mirror, a semiconductor Bragg mirror, a heavily-doped semiconductor layer, a metal mirror, or a hybrid mirror incorporating dielectric, semiconductor, and/or metal layers therein;
wherein the bottom mirror, the n-type region, the absorber region, the p-type region, and the top mirror form a resonant cavity configured to increase an effective absorption path of incident light having a wavelength resonant with the cavity; and
wherein the absorber region is situated within a depletion region of a p-n junction formed by the n-type region and the p-type region.

US Pat. No. 10,559,701

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A semiconductor device, comprising:a first n? type of layer, a second n? type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate;
a trench disposed on a side surface of the second n? type of layer;
a p type of region disposed between the second n? type of layer and the trench;
a gate electrode disposed on a bottom surface of the trench;
a source electrode disposed on the n+ type of region; and
a drain electrode disposed on a second surface of the substrate,
wherein the second n? type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n? type of layer,
wherein an ion doping concentration of the second concentration layer is lower than an ion doping concentration of the first concentration layer,
wherein an ion doping concentration of the third concentration layer is lower than the ion doping concentration of the second concentration layer, and
wherein an ion doping concentration of the fourth concentration layer is lower than the ion doping concentration of the third concentration layer.

US Pat. No. 10,559,700

ZERO COST NVM CELL USING HIGH VOLTAGE DEVICES IN ANALOG PROCESS

JONKER LLC, Zephyr Cove,...

1. A programmable non-volatile memory device situated in a high voltage circuit region of a substrate comprising:a floating gate configured to store non-volatile memory data for the device;
wherein said floating gate is comprised of a conductive material that is also used as a common gate layer for a high voltage transistor device also situated in the high voltage circuit region of the substrate;
a source region coupled to a first terminal;
a drain region coupled to a second terminal and overlapping a first portion of said floating gate sufficient to support hot electron injection programming along an edge of said floating gate; and
a drift region overlapping a second portion of the floating drain region;
wherein the drift region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling.

US Pat. No. 10,559,695

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode;
a gate insulating layer over the gate electrode;
a first oxide semiconductor layer over the gate insulating layer, the first oxide semiconductor layer having a first carrier concentration;
a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer having a second carrier concentration;
a third oxide semiconductor layer over the first oxide semiconductor layer, the third oxide semiconductor layer having a third carrier concentration;
a fourth oxide semiconductor layer over the second oxide semiconductor layer, the fourth oxide semiconductor layer having a fourth carrier concentration;
a fifth oxide semiconductor layer over the third oxide semiconductor layer, the fifth oxide semiconductor layer having a fifth carrier concentration;
an insulating layer over and in contact with the first oxide semiconductor layer;
a source electrode over and in contact with the fourth oxide semiconductor layer; and
a drain electrode over and in contact with the fifth oxide semiconductor layer,
wherein an inner edge of the second oxide semiconductor layer and an inner edge of the third oxide semiconductor layer are over the insulating layer,
wherein an inner edge of the source electrode is deviated from an inner edge of the fourth oxide semiconductor layer and the inner edge of the second oxide semiconductor layer,
wherein an inner edge of the drain electrode is deviated from an inner edge of the fifth oxide semiconductor layer and the inner edge of the third oxide semiconductor layer,
wherein each of the first to fifth oxide semiconductor layers contains indium, gallium, and zinc,
wherein the second carrier concentration is higher than the first carrier concentration and lower than the fourth carrier concentration, and
wherein the third carrier concentration is higher than the first carrier concentration and lower than the fifth carrier concentration.

US Pat. No. 10,559,691

COMPACT OTP/MTP MEMORY DEVICE INCLUDING A CAVITY FORMED BETWEEN A SUBSTRATE AND A BURIED OXIDE LAYER

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate having a buried oxide (BOX) layer formed over the substrate and a cavity formed between the substrate and the BOX layer and between a pair of isolation structures formed on the substrate;
first and second silicon-on-insulator (SOT) regions formed on the BOX layer end to end with a gap in between, the first and second SOI regions formed between the pair of isolation structures;
first and second replacement metal gates (RMGs), laterally separated, formed over and perpendicular to the first and second SOI regions, respectively;
at least one third RMG formed between the first and second RMGs on the BOX layer through the gap;
a source/drain (S/D) region formed in each of the first and second SOI regions adjacent to the first and second RMGs, respectively, remote from the at least one third RMG; and
a bit line (BL) connected to the S/D region or the at least one third RMG.

US Pat. No. 10,559,690

EMBEDDED SOURCE/DRAIN STRUCTURE FOR TALL FINFET AND METHOD OF FORMATION

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure comprising:a semiconductor substrate;
a semiconductor fin disposed over the semiconductor substrate, the semiconductor fin comprising a fin base;
a shallow trench isolation layer on the substrate;
a gate on the semiconductor fin, the gate comprising a gate spacer on a surface of the shallow trench isolation layer; and
a tree shaped epitaxial region disposed on the fin base;
wherein a sidewall of the shallow trench isolation layer is recessed to form a cavity below a bottom surface of the gate spacer; and
wherein a portion of the gate fills the cavity.

US Pat. No. 10,559,689

CRYSTALLIZED SILICON CARBON REPLACEMENT MATERIAL FOR NMOS SOURCE/DRAIN REGIONS

Intel Corporation, Santa...

16. A method of forming an integrated circuit, the method comprising:forming a semiconductor body, the semiconductor body comprising one of a fin, nanowire, or nanoribbon;
forming a gate structure at least above and adjacent sides of at least a portion of the semiconductor body, the gate structure including a gate electrode and a gate dielectric between the gate electrode and the at least a portion of the semiconductor body;
forming a source trench to one side of the gate structure, the source trench corresponding to a source region;
forming a drain trench to another side of the gate structure, the drain trench corresponding a drain region;
depositing in both of the source trench and the drain trench an amorphous alloy of silicon, germanium, and carbon, wherein the carbon concentration is at least 5 atomic percent; and
crystallizing the amorphous alloy of silicon, germanium, and carbon, the crystallizing applying a tensile strain to the at least a portion of the semiconductor body.

US Pat. No. 10,559,685

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED EXTERNAL RESISTANCE

International Business Ma...

1. A method for forming a semiconductor structure, the method comprising at least:forming a structure comprising at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate;
forming a silicide in contact with and wrapping around the first source/drain layer;
forming a gate structure in contact with at least the at least one semiconductor fin; and
forming a second source/drain layer above the first source/drain layer.

US Pat. No. 10,559,681

HIGH VOLTAGE LATERAL JUNCTION DIODE DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating an integrated circuit (IC), comprising:forming in a semiconductor surface layer, doped a first conductivity type, a depletion-mode laterally diffused MOSFET (LDMOS device), including forming a source and a drain doped a second conductivity type within said substrate, a channel region between the source and the drain, a gate dielectric over the channel region, a gate over the gate dielectric, and a drift region between said channel region and said drain, wherein said drain also provides a first cathode for a lateral junction diode having a first anode adjacent the source and running in parallel with a path between said source and said drain;
forming a clamp diode including a second cathode and a second anode, wherein said clamp diode is junction-isolated from the LDMOS device by a doped region of the second conductivity type located between said second anode and said source, and
directly connecting said gate to said second anode, and directly connecting said source to said second cathode.

US Pat. No. 10,559,680

SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE

Cree, Inc., Durham, NC (...

1. A semiconductor device comprising:a substrate;
a drift layer on the substrate;
a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;
a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;
a gate contact on the gate oxide layer;
source contacts on the drift layer and above each of the at least four junction implants; and
a drain contact on the substrate; and
junction barrier Schottky bypass diodes comprising a Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts.

US Pat. No. 10,559,678

CASCODE CIRCUIT HAVING A GATE OF A LOW-SIDE TRANSISTOR COUPLED TO A HIGH-SIDE TRANSISTOR

SEMICONDUCTOR COMPONENTS ...

1. A cascode circuit comprising:a high-side transistor including a source, a gate, and a body; and
a low-side transistor including a drain, a source, and a gate; and
a first coupling element having a first terminal and a second terminal,
wherein:
the source of the high-side transistor is coupled to the drain of the low-side transistor,
the gate of the high-side transistor is coupled to the source of the low-side transistor,
the body of the high-side transistor is coupled to the gate of the low-side transistor,
the first terminal of the first coupling element is electrically connected to the gate of the high-side transistor,
the second terminal of the first coupling element is electrically connected to the source of the low-side transistor, and
the first coupling element includes an impendence element, a charge storage element, or an electrical connection.

US Pat. No. 10,559,675

STACKED SILICON NANOTUBES

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising: forming one or more stacked nanowires comprising a sacrificial material over a substrate, the sacrificial material comprising a first type of semiconductor material; forming a pull-out layer around each of the one or more stacked nanowires; reacting the pull-out layer with the first type of semiconductor material to form a silicon-rich layer on a surface of each of the one or more stacked nanowires; and removing the sacrificial material to define one or more hollow nanotubes comprising the silicon-rich layer.

US Pat. No. 10,559,674

MANUFACTURING METHOD OF A TRENCH POWER SEMICONDUCTOR DEVICE

SUPER GROUP SEMICONDUCTOR...

1. A manufacturing method of a trench power semiconductor device, comprising:forming an epitaxial layer on a substrate;
forming a protective layer on a surface of the epitaxial layer;
forming a trench in the epitaxial layer; and
forming a trench gate structure in the trench, wherein the trench gate structure includes a shielding electrode, a gate disposed on the shielding electrode and an inter-electrode dielectric layer disposed between the shielding electrode and the gate, and the step of forming the trench gate structure at least includes:
forming an insulating layer covering an inner surface of the trench; and
before the step of forming the inter-electrode dielectric layer, forming an initial spacing layer, wherein the initial spacing layer includes a first sidewall portion and a second sidewall portion respectively covering the two inner surfaces of the insulating layer, the bottom end portion of the first sidewall portion is separate from the bottom end portion of the second sidewall portion, and both of the first and second sidewall portions have an extending portion protruding from the protective layer; and
forming an inner dielectric layer and the shielding electrode at the lower portion of the trench, wherein the inner dielectric layer covers a lower portion of the initial spacing layer and surrounds the shielding electrode, and the inner dielectric layer is directly in contract with the bottom of the insulating layer.

US Pat. No. 10,559,670

NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS

INTERNATIONAL BUSINESS MA...

1. A nanosheet device, comprising:a gate structure on a substrate;
a source/drain region on each of the opposite sides of the gate structure;
at least one nanosheet channel layer extending between the source/drain region on each of the opposite sides of the gate structure, wherein the at least one nanosheet channel layer is in physical and electrical contact with the source/drain region on each of the opposite sides of the gate structure; and
four cavity fills between the substrate and a bottom nanosheet channel layer of the at least one nanosheet channel layers, wherein one of the four cavity fills is located at each of the four corners of the bottom nanosheet channel layer.

US Pat. No. 10,559,666

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A structure, comprising:a semiconductor substrate;
a semiconductor buffer layer disposed over the semiconductor substrate;
an oxide layer disposed over the buffer layer; and
a fin comprising a semiconductor material disposed over the oxide layer,
wherein the semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer, and
wherein a distance between a top surface of the oxide layer and a bottom surface of the buffer layer is more than a distance between a bottom surface of the fin and the bottom surface of the buffer layer.

US Pat. No. 10,559,664

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY REMOVING A BULK LAYER TO EXPOSE AN EPITAXIAL-GROWTH LAYER AND BY REMOVING PORTIONS OF A SUPPORTING-SUBSTRATE TO EXPOSE PORTIONS OF THE EPITAXIAL-GROWTH LAYER

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate, the semiconductor substrate further comprising a bulk layer on which the epitaxial-growth layer has been grown, the bulk layer having a bottom-surface side facing away from the epitaxial-growth layer;
forming a plurality of device structures on the plurality of chip regions, respectively;
bonding an upper supporting-substrate on a top-surface side of the epitaxial-growth layer;
after bonding the upper supporting-substrate on the top-surface side of the epitaxial-growth layer, thinning the semiconductor substrate from the bottom-surface side of the bulk layer by removing the bulk layer from the semiconductor substrate and exposing a bottom-surface side of the epitaxial-growth layer;
bonding a lower supporting-substrate on the bottom-surface side of the epitaxial-growth layer exposed by the thinning;
after bonding the lower supporting-substrate on the bottom-surface side of the epitaxial-growth layer exposed by the thinning, thinning a bottom-surface side of the lower supporting-substrate;
after thinning the bottom-surface side of the lower supporting-substrate, selectively removing portions of the thinned lower supporting-substrate so that portions of the bottom-surface side of the epitaxial-growth layer are exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively;
after selectively removing the portions of the thinned lower supporting-substrate, adhering a bottom surface of the thinned lower supporting-substrate to an adhesive tape;
applying heat or ultraviolet radiation to neutralize an adhesive force of an adhesive layer which bonds the upper supporting-substrate to the top-surface side of the epitaxial-growth layer, and separating the upper supporting-substrate from the top-surface side of the epitaxial-growth layer while the bottom surface of the thinned lower supporting-substrate is adhered to the adhesive tape;
applying heat or ultraviolet radiation to neutralize an adhesive force of the adhesive tape and separating the bottom surface of the thinned lower supporting-substrate from the adhesive tape; and
dicing the thinned semiconductor substrate having the bulk layer removed, together with the lower supporting-substrate, along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.

US Pat. No. 10,559,662

HYBRID ASPECT RATIO TRAPPING

International Business Ma...

1. A semiconductor structure comprising:a material stack consisting of a silicon germanium alloy portion that is relaxed and defect-free and a semiconductor material pillar that is defect-free, wherein the silicon germanium alloy portion is in direct physical contact with a topmost surface of a semiconductor substrate and the semiconductor material pillar is in direct physically contact with a topmost surface of the silicon germanium alloy portion, and wherein an entirety of the semiconductor substrate extends beyond outermost sidewalls of the material stack; and
a dielectric material structure located laterally adjacent to the material stack and having a bottommost surface in direct contact with physically exposed portions of the topmost surface of the semiconductor substrate, wherein the bottommost surface of the dielectric material stack is coplanar with a bottommost surface of the silicon germanium alloy portion of the material stack that forms an interface with the topmost surface of the semiconductor substrate.

US Pat. No. 10,559,659

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:a surface electrode disposed on a semiconductor substrate and through which a main current flows;
a first metal layer that is disposed on the surface electrode and is not a sintered compact; and
at least one second metal layer that is disposed on the first metal layer and is a sintered compact,
wherein the second metal layer has a size to cover all the surface electrode in plan view, and has higher heat conductivity than the first metal layer,
wherein the first metal layer is wider in the plan view than the second metal layer, and
wherein the first metal layer is disposed between the second metal layer and the surface electrode.

US Pat. No. 10,559,658

SCHOTTKY BARRIER DIODE

ROHM CO., LTD., Kyoto (J...

1. A Schottky barrier diode, comprising:a first semiconductor layer having depressions on a top surface thereof;
a guard ring arranged in an outer periphery portion of the first semiconductor layer so as to surround the depressions; and
a first metal layer covering an entire area of the top surface surrounded by the guard ring and entire surfaces of the depressions, and being in Schottky junction with the top surface as well as bottom faces of the depressions; wherein
the guard ring extends from the top surface to an inner position of the first semiconductor layer at a depth deeper than depths of the depressions.

US Pat. No. 10,559,654

NANOSHEET ISOLATION FOR BULK CMOS NON-PLANAR DEVICES

International Business Ma...

1. A semiconductor structure comprising:a semiconductor substrate including a first device region and a second device region, wherein first trench isolation structures surround said first and second device regions and extend below first and second pedestal portions of said semiconductor substrate;
a first semiconductor material fin stack located above said first pedestal portion of said semiconductor substrate;
a second semiconductor material fin stack located above said second pedestal portion of said semiconductor substrate; and
second trench isolation structures located at ends of each first semiconductor material fin stack and said second semiconductor material fin stack, wherein a portion of one of said second trench isolation structures is located directly between a bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and another of said second trench isolation structures is located directly between a bottommost surface of said second semiconductor material fin stack and said second pedestal portion of said semiconductor substrate, and wherein said first trench isolation structures have a depth that is greater than a depth of said second trench isolation structures.

US Pat. No. 10,559,651

METHOD OF FORMING MEMORY CAPACITOR

UNITED MICROELECTRONICS C...

1. A method of forming a memory capacitor, comprising:providing a substrate, which comprises a plurality of storage node contacts;
forming a patterned supporting structure on the substrate, wherein the patterned supporting structure comprises a plurality of openings, each of which corresponding to each of the storage node contacts;
forming a bottom electrode layer on the patterned supporting layer, wherein the bottom electrode layer is conformally formed on the patterned supporting layer and sidewalls and bottom surfaces of the openings, and contacting the storage node contacts;
forming a sacrificial layer on the bottom electrode layer, wherein the sacrificial layer is filled into the openings, wherein before the soft etching process, a bottom surface of the sacrificial layer is lower than a top surface of the patterned supporting layer;
performing a soft etching process for removing the bottom electrode layer on the patterned supporting layer and partials of sidewalls of the openings, wherein said soft etching process comprises using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound;
completely removing the sacrificial layer;
removing partials of the patterned supporting layer;
forming a capacitor dielectric layer on the bottom electrode layer; and
forming a top electrode layer on the capacitor dielectric layer.

US Pat. No. 10,559,650

TRENCH CAPACITOR WITH WARPAGE REDUCTION

TEXAS INSTRUMENTS INCORPO...

1. A method for forming a trench capacitor, comprising:forming a plurality of trenches in a doped semiconductor surface layer of a substrate;
forming a dielectric layer that lines a surface of the plurality of trenches;
depositing a first polysilicon layer that is undoped on the dielectric layer;
depositing a second polysilicon layer on the first undoped polysilicon layer to fill the plurality of deep trenches;
doping the second polysilicon layer;
top side polysilicon etching using a masking layer pattern to etch back the first polysilicon layer in regions lateral to the plurality of trenches; and
further comprising after the depositing the second polysilicon layer removing the first polysilicon layer and the second polysilicon layer from a back side of the substrate.

US Pat. No. 10,559,648

CHIP RESISTOR AND CHIP RESISTOR ASSEMBLY

SAMSUNG ELECTRO-MECHANICS...

1. A chip resistor, comprising:a base substrate having a first surface and a second surface opposing each other, two side surfaces connecting the first surface and the second surface, and two end surfaces connecting the first surface and the second surface;
a resistive layer disposed on the second surface of the base substrate, the resistive layer having a first surface in contact with the base substrate and a second surface opposing the first surface of the resistive layer;
a first terminal and a second terminal spaced apart from each other and each being connected to the resistive layer on the second surface of the resistive layer; and
a third terminal connected to the resistive layer on the second surface of the resistive layer, disposed between the first terminal and the second terminal, and extending to the first surface of the base substrate along the side surfaces,
wherein the third terminal includes a first surface portion disposed on the first surface of the base substrate, and the first surface portion is divided into two portions extended from the two side surfaces.

US Pat. No. 10,559,646

ORGANIC LIGHT EMITTING DIODE DISPLAY HAVING BARRIER LAYER ON AUXILIARY ELECTRODE

LG Display Co., Ltd., Se...

1. An organic light emitting diode display, comprising:a first substrate;
a second substrate; and
a conductive filler layer interposed between the first substrate and the second substrate, the conductive filler layer including a conductive medium,
wherein the first substrate includes:
an auxiliary electrode;
a first barrier disposed on the auxiliary electrode;
a cathode included in an organic light emitting diode and physically divided by the first barrier, the cathode exposing at least a portion of the auxiliary electrode, one end of the cathode directly contacting the auxiliary electrode; and
a protective layer disposed on the cathode and physically divided by the first barrier, the protective layer exposing at least a portion of the auxiliary electrode, one end of the protective layer directly contacting the auxiliary electrode,
wherein the second substrate includes:
a spacer protruding toward the first substrate and disposed adjacent to the auxiliary electrode; and
a power line covering at least a portion of the spacer and supplied with a power voltage.

US Pat. No. 10,559,645

ORGANIC LIGHT-EMITTING DIODE DISPLAY

Samsung Display Co., Ltd....

1. A pixel, comprising:an organic light-emitting diode (OLED) configured to emit light based on a driving current, the OLED including an anode and a cathode on a substrate;
a first transistor configured to generate the driving current, the first transistor including a first terminal to which a first power supply voltage is applied, a second terminal electrically connected to the anode, and a gate terminal to which a second power supply voltage is applied;
a first parasitic capacitor connected between a first power supply voltage line to which the first power supply voltage is applied and a first node;
a second transistor including a first terminal connected to a second node that connects the gate terminal of the first transistor, a second terminal connected to the first node, and a gate terminal to which a scan signal is applied;
a third transistor including a first terminal connected to the first node, a second terminal connected to the second terminal of the first transistor, and a gate terminal to which the scan signal is applied, the first node being connected to the gate terminal of the first transistor through the second transistor without passing through the second node;
a fourth transistor including a first terminal to which a data signal is applied, a second terminal connected to the first terminal of the first transistor, and a gate terminal to which the scan signal is applied;
a storage capacitor connected between the first power supply voltage line and the second node; and
fifth and sixth transistors that are connected between the second node and a second power supply voltage line to which the second power supply voltage is applied, wherein the fifth transistor includes a first terminal connected to the second node, a second terminal connected to the sixth transistor, and a gate terminal to which a data initialization signal is applied, and wherein the sixth transistor includes a first terminal connected to the second terminal of the fifth transistor, a second terminal connected to the second power supply voltage line, and a gate terminal to which the data initialization signal is applied.

US Pat. No. 10,559,644

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a pixel area with at least a top portion, a bottom portion, a first side portion, and a second side portion, wherein the top portion, the bottom portion, the first side portion, and the second side portion are disposed about a center of the pixel area in a plan view of the display device;
a plurality of pixels in the pixel area;
a first rounded corner of the pixel area between the bottom portion and the first side portion in the plan view of the display device;
a first non-pixel area, a second non-pixel area and a third non-pixel area arranged sequentially along an outer circumference of the pixel area, with the first non-pixel area being closest to the pixel area;
a first internal circuit in the first non-pixel area that includes a plurality of first stages to sequentially output a pixel control signal, the first internal circuit having a first end adjacent to the first rounded corner of the pixel area, the first end of the first internal circuit rounded in accordance with the first rounded corner; and
a plurality of routing wires extending from a data driver located in a portion of the third non-pixel area that is below the pixel area in the plan view of the display device, the routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area, the routing wires including a first routing wire connected to the pixel area that passes between a first stage and an adjacent second stage, which are both located in the first end of the first internal circuit, wherein the routing wires are data lines.

US Pat. No. 10,559,642

ORGANIC LIGHT-EMITTING DEVICE HAVING A FLUORIDE AND METAL BASED INTERMEDIATE LAYER AND PRODUCTION METHOD

JOLED INC., Tokyo (JP)

2. An organic light-emitting device, comprising:a substrate;
an anode disposed above the substrate;
a wiring disposed above the substrate, the wiring being spaced away from the anode in a direction parallel to a main surface of the substrate;
a light-emitting layer disposed above the anode and containing an organic light-emitting material;
an intermediate layer disposed on the light-emitting layer and above the wiring, the intermediate layer being continuous over the light-emitting layer and the wiring and containing a fluoride of a first metal, the first metal being an alkali metal or an alkaline earth metal;
an organic functional layer disposed on the intermediate layer, the organic functional layer being continuous over the light-emitting layer and the wiring and made of an organic material doped with a second metal, the organic material having at least one of an electron transporting property and an electron injection property, the second metal having a property of cleaving a bond between the first metal and fluorine in the fluoride of the first metal; and
a cathode disposed on the organic functional layer, the cathode being continuous over the light-emitting layer and the wiring, wherein
1?x?2, 20?y?40, and y?20x, where
x denotes a film thickness [nm] of the intermediate layer and y denotes a dope concentration [wt %] of the second metal in the organic functional layer.

US Pat. No. 10,559,641

MULTIPLE SUBTHRESHOLD SWING CIRCUIT AND APPLICATION TO DISPLAYS AND SENSORS

International Business Ma...

1. A three-terminal apparatus, comprising:a field-effect transistor (FET) comprising:
a first layer comprising silicon having a first type of carrier as its majority carrier;
a gate comprising a second layer formed on the first layer, the second layer comprising intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer, the third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier, and a conductive layer formed on the third layer; and
drain and source terminals, each of the drain and source terminals comprising a fourth layer formed on the first layer, the fourth layer comprising crystalline hydrogenated silicon having the first type of carrier as its majority carrier, and a conductive layer formed on the fourth layer; and
a set of one or more serially-connected diodes, each diode having first and second terminals, wherein the first terminal of a first diode in the set of one or more serially-connected diodes is connected to the source terminal of the FET;
wherein the gate of the FET forms a first terminal of the three-terminal apparatus, the drain terminal of the FET forms a second terminal of the three-terminal apparatus, and the second terminal of a last diode in the set of one or more serially-connected diodes forms a third terminal of the three-terminal apparatus, the first, second and third terminals of the three-terminal apparatus being independently controllable relative to one another; and
wherein a subthreshold swing of the three terminal apparatus is higher than a subthreshold swing of the FET by a factor proportional to a sum of ideality factors of the set of one or more serially-connected diodes.

US Pat. No. 10,559,640

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light emitting display device comprising:a display panel having a plurality of gate lines and data lines;
a timing controller controlling an operation timing of each pixel;
a gate driver driving the gate lines;
a data driver having a plurality of data driving integrated circuits driving the data lines; and
an embedded point-to-point interface between the timing controller and each of the data driving integrated circuits,
transmitting video/control data signal from the timing controller to each of the data driving integrated circuits and transmitting a sensing value from the data driving integrated circuits to the timing controller,
wherein the timing controller comprises;
a first transmission module transmitting video/control data signal to each of the data driving integrated circuits via the embedded point-to-point interface,
a first reception module receiving the sensing value from each of the data driving integrated circuits via the embedded point-to-point interface,
a first transmission/reception selector enabling one of the first transmission module and the first reception module, and disabling the other of non-enabled module, and
a transmission/reception timing controller controlling the first transmission/reception selector, and
wherein each of data driving integrated circuits comprises;
a second reception module receiving the video/control data signal from the timing controller through the embedded point-to-point interface;
a clock data recovery unit restoring video data, control data, and a clock signal from the video/control data signal received through the second reception module;
an oscillator generating the clock signal in accordance with the restored control signal;
an encoder encoding the sensing value sensed from the display panel in synchronization with the clock signal generated by the oscillator;
a second transmission module converting the sensing value encoded by the encoder into a transmission packet and transmitting the transmission packet to the timing controller through the embedded point-to-point interface;
a counter counting the clock signal generated from the oscillator and outputting a control signal when a counted value reaches a predetermined value; and
a second transmission/reception selector disabling the second reception module and enabling the second transmission module according to the control signal restored by the control data processing unit, and disabling the second transmission module and enabling the second reception module according to the control signal of the counter.

US Pat. No. 10,559,639

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing an organic light-emitting display device, comprising steps of:providing a substrate;
forming a first patterned metal layer on the substrate, wherein the patterned metal layer comprises a gate of a switching thin film field-effect transistor and a gate of a driving thin film field-effect transistor;
forming a gate insulating layer having a first via hole on the first patterned metal layer;
forming a first indium-gallium-zinc oxide layer on the gate insulating layer, wherein the first indium-gallium-zinc oxide layer comprises a first active layer for reducing a sub-threshold swing of a transfer characteristic curve of the switching thin film field-effect transistor;
forming a second indium-gallium-zinc oxide layer on the first active layer and the gate insulating layer, wherein the second indium-gallium-zinc oxide layer comprises a third active layer and a second active layer for increasing a sub-threshold swing of a transfer characteristic curve of the driving thin film field-effect transistor;
forming a second patterned metal layer on the second indium-gallium-zinc oxide layer, wherein the second patterned metal layer comprises a source and a drain of the switching thin film field-effect transistor and a source and a drain of the driving thin film field-effect transistor, and the source of the switching thin film field-effect transistor is connected with the gate of the driving thin film field-effect transistor through the first via hole;
forming a passivation layer having a second via hole on the second patterned metal layer; and forming a third metal layer on the passivation layer, wherein the third metal layer comprises a pixel electrode connecting with the source of the driving thin film field-effect transistor through the second via hole,
wherein an oxygen content of the second indium-gallium-zinc oxide layer is greater than that of the first indium-gallium-zinc oxide laver.

US Pat. No. 10,559,634

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode display device, comprising:a substrate;
a plurality of pixels disposed on the substrate;
a plurality of anodes corresponding to the plurality of pixels, respectively;
an organic light emitting layer disposed on the plurality of anodes;
a charge generation layer included in the organic light emitting layer;
a cathode layer disposed on the organic light emitting layer; and
a step difference compensation layer partitioning at least two adjacent pixels among the plurality of pixels,
wherein the step difference compensation layer includes:
a base layer, and
a plurality of spike patterns disposed on the base layer, the plurality of spike patterns including protrusions that extend into at least a portion of the organic light emitting layer in a region between the at least two adjacent pixels,
wherein the charge generation layer is disposed on the plurality of spiked patterns, and
wherein the charge generation layer has a wavy surface in the region between the at least two adjacent pixels or at least one of the protrusions pierces through the charge generation layer in the region between the at least two adjacent pixels.

US Pat. No. 10,559,631

METHOD OF MANUFACTURING A DISPLAY DEVICE UTILIZING PIXEL AND DUMMY PORTIONS

Samsung Display Co., Ltd....

1. A method for manufacturing a display device, the method comprising:preparing a first mother substrate;
preparing a second mother substrate having a plurality of unit areas divided by an imaginary line;
forming a pixel portion at the unit areas;
forming a dummy portion along the imaginary line;
bonding the first mother substrate and the second mother substrate with an interlayer between the first mother substrate and the second mother substrate; and
cutting the first mother substrate and the second mother substrate along the imaginary line,
wherein at least a portion of the pixel portion and at least a portion of the dummy portion are formed by a same process.

US Pat. No. 10,559,627

MEMORY DEVICE AND RECTIFIER

Toshiba Memory Corporatio...

1. A memory device comprising:a first conductive layer;
a second conductive layer;
a variable resistance layer disposed between the first conductive layer and the second conductive layer; and
an organic molecular layer disposed between the variable resistance layer and the second conductive layer, the organic molecular layer containing organic molecules, wherein:
the organic molecules are selected from structures (1), (2), (3), and (4) listed below;
each of the organic molecules selected from structures (1), (2), (3), and (4) includes a first fused polycyclic aromatic hydrocarbon having a first HOMO (highest occupied molecular orbital) level, a second fused polycyclic aromatic hydrocarbon having a second HOMO level higher in energy than the first HOMO level, and a third fused polycyclic aromatic hydrocarbon disposed between the first fused polycyclic aromatic hydrocarbon and the second fused polycyclic aromatic hydrocarbon, the third fused polycyclic aromatic hydrocarbon has a third HOMO level higher in energy than the first HOMO level and the second HOMO level, and
FP1, FP2, FP3, L1, and L2 in structures (1), (2), (3), and (4) indicate the first fused polycyclic aromatic hydrocarbon, the second fused polycyclic aromatic hydrocarbon, the third fused polycyclic aromatic hydrocarbon, a first linker, and a second linker, respectively

US Pat. No. 10,559,626

NEUROMORPHIC DEVICE INCLUDING A SYNAPSE HAVING CARBON NANO-TUBES

SK hynix Inc., Icheon (K...

1. A neuromorphic device comprising:a pre-synaptic neuron;
a row line extending in a row direction from the pre-synaptic neuron;
a post-synaptic neuron;
a column line extending in a column direction from the post-synaptic neuron; and
a synapse disposed at an intersection between the row line and the column line,
wherein the synapse comprises:
a first synapse layer including a plurality of first carbon nano-tubes;
a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and
a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes,
wherein the synapse further comprises a capping layer disposed on the first to third synapse layers,
wherein the capping layer comprises a plurality of horizontal carbon nano-tubes that are densely and horizontally arranged in the capping layer, the plurality of horizontal carbon nano-tubes being arranged denser than the pluralities of the first to third carbon nano-tubes, and
wherein the first synapse layer, the second synapse layer, the third synapse layer, and the capping layer are vertically stacked and horizontally disposed in parallel with each other.

US Pat. No. 10,559,620

SOLID-STATE IMAGING DEVICE WITH PHASE DIFFERENCE DETECTION PIXEL AND MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:an imaging pixel including a first photoelectric conversion unit that receives incident light;
a phase difference detection pixel including a second photoelectric conversion unit that receives incident light;
a light shielding member that shields the photoelectric conversion unit of the phase difference detection pixel from some light incident on the phase difference detection pixel;
a flattening film formed on an upper side of the imaging pixel, the phase difference detection pixel, and light shielding member; and
a color filter layer formed on an upper side of the flattening film,
wherein the color filter layer includes a first color filter located on the first photoelectric conversion unit and a second color filter located on the second photoelectric conversion unit, and
wherein the second color filter is thinner than the first color filter based on a sensitivity of the phase difference detection pixel.

US Pat. No. 10,559,619

IMAGING DEVICE AND METHOD OF MANUFACTURING IMAGING DEVICE

Sony Corporation, Tokyo ...

1. An imaging device comprising:a first semiconductor chip configured to include a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line, wherein the first semiconductor chip includes a transfer gate and an overflow gate disposed in a first row, the signal input transistor and the reference input transistor are disposed in a second row, and a photodiode located between the first row and the second row; and
a second semiconductor chip configured to include a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad.

US Pat. No. 10,559,615

METHODS FOR HIGH-DYNAMIC-RANGE COLOR IMAGING

OmniVision Technologies, ...

8. A method for generating high-dynamic-range images, comprising:partly absorbing first light propagating from a scene toward a plurality of first pixels of a photosensitive pixel array to attenuate the first light as compared to second light propagating from the scene toward a plurality of second pixels of the photosensitive pixel array, the plurality of second pixels being interleaved with the plurality of first pixels; and
after said partly absorbing, spectrally filtering the first light to form an attenuated color image of the scene on the photosensitive pixel array at the first pixels and spectrally filtering the second light to form a brighter color image of the scene on the photosensitive pixel array at the second pixels;
said spectrally filtering the first and second light including (a) spectrally filtering, with first color filters having a first thickness, first and second light propagating toward a first subset of the plurality of first pixels and the plurality of second pixels and (b) spectrally filtering, with second color filters having a second thickness, first and second light propagating toward a second subset of the plurality of first pixels and the plurality of second pixels, the second thickness exceeding the first thickness, the first color filters being configured to transmit longer wavelengths than the second color filters;
said partly absorbing including partly absorbing, with the same type of grey material, the first light propagating toward (a) the first pixels of the first subset and (b) the first pixels of the second subset, the grey material over the first pixels of the first subset being thinner than the grey material over the first pixels of the second subset to compensate for transmission of the grey material being an increasing function of wavelength.

US Pat. No. 10,559,614

DUAL CONVERSION GAIN CIRCUITRY WITH BURIED CHANNELS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor pixel formed on a semiconductor substrate, the image sensor pixel comprising:a photodetector that generates charge in response to incident light;
a floating diffusion node that stores the charge;
a dual conversion gain capacitor;
a dual conversion gain switch that transfers the charge from the floating diffusion node to the dual conversion gain capacitor while the dual conversion gain switch is on; and
a buried channel in the semiconductor substrate that transfers the charge from the floating diffusion node to the dual conversion gain capacitor while the dual conversion gain switch is off.

US Pat. No. 10,559,613

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
first and second recesses spaced apart from each other in a first direction within the substrate;
a first gate electrode filling the first recess and protruding above the substrate;
a second gate electrode filling the second recess and protruding above the substrate;
a first source/drain formed between the first and second recesses;
a second source/drain formed in an opposite direction to the first source/drain with respect to the first recess;
a third source/drain formed in an opposite direction to the first source/drain with respect to the second recess; and
a gate contact formed directly on the first and second gate electrodes,
wherein the first and second gate electrodes are connected to form one integral structure at a same level, are electrically connected to same node and share the gate contact.

US Pat. No. 10,559,612

SIGNAL PROCESSING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SIGNAL PROCESSING CIRCUIT

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a back gate voltage control circuit;
wherein the transistor comprises a gate, a back gate and a channel formation region,
wherein the channel formation region comprises an oxide semiconductor, wherein the gate of the transistor is electrically connected to a wiring,
wherein the back gate of the transistor is electrically connected to the back gate voltage control circuit, and
wherein the back gate voltage control circuit is configured to apply a potential corresponding to a command to the back gate of the transistor.

US Pat. No. 10,559,611

IMAGE SENSOR

STMicroelectronics (Croll...

1. An image sensor including a plurality of pixels, each pixel comprising:a semiconductor substrate doped with a first dopant type;
a first insulated vertical electrode that delimits a photosensitive area doped with a second dopant type, wherein the first insulated vertical electrode is electrically connected to receive a first bias voltage;
a second insulated vertical electrode and a third insulated vertical electrode that delimit a charge storage area doped with said second dopant type, wherein the second and third insulated vertical electrodes are physically separate from each other but electrically connected to receive a second bias voltage;
wherein said first insulated vertical electrode and said third insulated vertical electrode extend parallel to each other with a first portion of said semiconductor substrate doped with the first dopant type positioned in contact with and extending between said first and third insulated vertical electrodes;
wherein the third insulated vertical electrode extends between the charge storage area and the photosensitive area; and
wherein the second insulated vertical electrode extends perpendicular to the third insulated vertical electrode at a first end of the third insulated vertical electrode to delimit a region for charge passage between the photosensitive area and the charge storage area in response to the second bias voltage.

US Pat. No. 10,559,609

SOLID-STATE IMAGING DEVICE WITH LIGHT SHIELDING FILM AND DRIVING METHOD THEREOF, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A solid-state imaging device, comprising:a plurality of pixels, including;
a first pixel including:
a first photoelectric conversion unit;
a first charge accumulation region coupled to the first photoelectric conversion unit via a first transfer transistor; and
a first floating diffusion coupled to the first charge accumulation region,
a second pixel including:
a second photoelectric conversion unit;
a second charge accumulation region coupled to the second photoelectric conversion unit via a second transfer transistor; and
a second floating diffusion coupled to the second charge accumulation region; and
a light-shielding film covering the first charge accumulation region of the first pixel, the second charge accumulation region of the second pixel, and a part of the second photoelectric conversion unit of the second pixel.

US Pat. No. 10,559,607

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:a substrate having a main surface;
a first sensor disposed on the main surface in a first region;
a second sensor disposed on the main surface in a second region;
an insulation film between the first sensor and the second sensor, a width of the insulation film defining a width of an element separation region separating the first region from the second region;
a first filter disposed above the first sensor in the first region; and
a second filter disposed above the second sensor in the second region, the first filter and the second filter overlapping each other above the element separation region in a plan view of the semiconductor device,
wherein the first sensor comprises:
a first diffusion layer of a first conductivity type located on the main surface of the substrate;
a first diffusion region of the first conductivity type located on the main surface of the substrate at one end of the first diffusion layer, the first diffusion region located next to the insulation film; and
a second diffusion region of a second conductivity type located on the main surface of the substrate at an opposite end of the first diffusion layer from the first diffusion region,
wherein the second sensor comprises:
a second diffusion layer of the first conductivity type located on the main surface of the substrate;
a third diffusion region of the first conductivity type located on the main surface of the substrate at one end of the second diffusion layer; and
a fourth diffusion region of the second conductivity type located on the main surface of the substrate at an opposite end of the second diffusion layer from the third diffusion region, the fourth diffusion region located next to the insulation film, and
wherein the first filter extends over the fourth diffusion region of the second sensor without extending over the second diffusion layer of the second sensor.

US Pat. No. 10,559,587

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

SK hynix Inc., Gyeonggi-...

1. An electronic device, comprising:a first source layer including a trench;
a second source layer formed in the trench and over the first source layer;
a first structure formed over the second source layer and including a plurality of first conductive layers and a plurality of first insulating layers which are alternately stacked on each other; and
first channel layers each passing through the first structure and extending to the second source layer,
wherein the second source layer includes a base portion and protruding portions,
wherein the base portion couples the first channel layers to each other in the trench, and
wherein the protruding portions extend upward from the base portion to surround sidewalls of the first channel layers, respectively.