US Pat. No. 10,460,980

SEMICONDUCTOR DEVICE COMPRISING A DEEP TRENCH ISOLATION STRUCTURE AND A TRAP RICH ISOLATION STRUCTURE IN A SUBSTRATE AND A METHOD OF MAKING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a metal-oxide semiconductor (MOS) transistor on a substrate;
a deep trench isolation structure in the substrate and around the MOS transistor, wherein the deep trench isolation structure comprises a liner in the substrate and an insulating layer on the liner, wherein the liner comprises silicon oxide and the insulating layer comprises undoped polysilicon or silicon nitride; and
a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure, wherein the deep trench isolation structure and the trap rich isolation structure comprise different materials and a number of layers in the trap rich isolation structure is less than a number of layers in the deep trench isolation structure, wherein the trap rich isolation structure comprises undoped polysilicon and the undoped polysilicon of the trap rich isolation structure is in direct contact with the substrate.

US Pat. No. 10,460,979

SEMICONDUCTOR STRUCTURE CAPABLE OF IMPROVING ROW HAMMER EFFECT IN DYNAMIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor structure, comprising:providing a semiconductor substrate having a first conductivity type;
forming at least one active area on the semiconductor substrate, wherein a major axis of the active area extends along a first direction;
performing a first oblique ion implantation process to form a first doped region having a second conductivity type above a first depth on an end surface of the active area;
performing a second oblique ion implantation process to form a second doped region having a third conductivity type above a second depth on the end surface of the active area, wherein the third conductivity type and the second conductivity types are opposite to each other, so that a localized doped region having the second conductivity type is formed between the first depth and the second depth; and
forming a trench isolation structure around the active area and adjacent to the end surface of the active area.

US Pat. No. 10,460,978

BOLTLESS SUBSTRATE SUPPORT ASSEMBLY

LAM RESEARCH CORPORATION,...

1. A substrate support, comprising:a conductive baseplate arranged to support a ceramic layer, the conductive baseplate including a first cavity extending along an axis perpendicular to a horizontal plane defined by the conductive baseplate; and
a coupling assembly arranged within the first cavity, the coupling assembly comprising
a gear arranged within the first cavity and configured to rotate about the axis, and
a pin arranged within the first cavity, the pin extending along the axis through the gear and into a second cavity below the conductive baseplate, wherein rotation of the gear causes the pin to move upward or downward relative to the conductive baseplate, and wherein the pin is retained within the second cavity when the gear is rotated to cause the pin to move downward into the second cavity, and wherein the pin does not extend to an upper surface of the conductive baseplate.

US Pat. No. 10,460,977

LIFT PIN HOLDER WITH SPRING RETENTION FOR SUBSTRATE PROCESSING SYSTEMS

LAM RESEARCH CORPORATION,...

1. A lift pin holder assembly, comprising:a lift pin holder including a central bore extending in a first direction, wherein the central bore defines a first groove arranged transverse to the first direction on a radially inner surface of the central bore,
wherein the lift pin holder is made of ceramic;
a lift pin received in the central bore, extending in the first direction and including a second groove arranged transverse to the first direction on a radially outer surface thereof; and
a spring at least partially arranged in the first groove of the lift pin holder and the second groove of the lift pin to retain the lift pin in the central bore of the lift pin holder.

US Pat. No. 10,460,976

SUBSTRATE TRANSFER DEVICE AND SUBSTRATE TRANSFER METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate transfer device, comprising:at least one first supporting portion and at least one second supporting portion configured to support a substrate from below the substrate;
an elevating mechanism configured to elevate the at least one second supporting portion up and down between a first position higher than a height of the at least one first supporting portion, which is maintained fixed, and a second position lower than the height of the at least one first supporting portion;
a control unit configured to control the elevating mechanism; and
a detecting unit configured to detect an external surface of the at least one second supporting portion,
wherein the control unit determines whether the at least one second supporting portion is in a required elevation state based on a detection result of the detecting unit,
the detecting unit includes a light projecting unit configured to irradiate light, and a light receiving unit configured to receive the light irradiated from the light projecting unit, and
the control unit controls the detecting unit to overlap an optical axis of the light with the at least one second supporting portion.

US Pat. No. 10,460,975

VACUUM CHUCK, BEVELING/POLISHING DEVICE, AND SILICON WAFER BEVELING/POLISHING METHOD

SUMCO CORPORATION, Tokyo...

1. A vacuum chuck comprising:a vacuum chuck stage comprising a circular vacuum surface;
a vacuum protection pad provided to the vacuum surface;
an annular or arc-shaped concave portion dividing the vacuum surface into a central region located closer to a center of the vacuum surface and an outer circumferential region located on an outer circumferential side; and
radially-extending concave portions formed in the central region, wherein
the vacuum protection pad has through holes in communication with the radially-extending concave portions, and
the vacuum protection pad is bonded to the vacuum surface at the central region excluding the radially-extending concave portions and is unbonded to the vacuum surface in the outer circumferential region.

US Pat. No. 10,460,974

WAFER PROCESSING METHOD AND ADHESIVE TAPE

Disco Corporation, Tokyo...

1. A wafer processing method for dividing a wafer into individual chips by applying to the wafer a laser beam having such a wavelength as to be absorbed in the wafer, the laser processing method comprising:an adhesive tape attaching step of attaching the wafer to an adhesive tape that emits plasma light different from plasma light emitted by the wafer upon application of a laser beam thereto;
a holding step of holding the adhesive tape side on a chuck table so as to expose the wafer, after performing the adhesive tape attaching step;
a dividing step of dividing the wafer while relatively moving the chuck table and the laser beam, after performing the holding step; and
a plasma light detection step of detecting plasma light generated at the time of the dividing step,
wherein in the plasma light detection step, complete division of the wafer is confirmed by detecting plasma light generated upon application of the laser beam to the adhesive tape.

US Pat. No. 10,460,972

METHOD OF DETACHING SEMICONDUCTOR MATERIAL FROM A CARRIER AND DEVICE FOR PERFORMING THE METHOD

Infineon Technologies AG,...

1. A method of detaching semiconductor material from a carrier, the method comprising:providing a carrier having attached thereto a layer of semiconductor material, wherein the layer comprises an edge portion;
deflecting the carrier in an area of the carrier, on which the edge portion of the layer of semiconductor material is attached, in a direction having an angle greater than zero with respect to a surface of the layer of semiconductor material; and
guiding an air stream onto the edge portion of the layer of semiconductor material, wherein the air stream impacts on a deflected portion of the carrier, thereby removing only the edge portion of the semiconductor material from the carrier.

US Pat. No. 10,460,971

MULTI-CHIP PACKAGE ASSEMBLY

INTERNATIONAL BUSINESS MA...

1. A method of bonding chips to a substrate, comprising:applying a first adhesive layer to a chip wafer, such that the first adhesive layer is formed over and around a plurality of chips;
bonding the chip wafer to a first support wafer by the first adhesive layer;
dicing the chip wafer to separate the plurality of chips on the first support wafer;
bonding the plurality of chips to a second support wafer by a second adhesive layer;
selectively weakening regions of the first adhesive layer to decrease an adhesive strength in weakened regions, said regions corresponding to a subset of the plurality of chips;
separating the second support wafer from the first wafer, such that the subset of the plurality of chips in the weakened regions debond from the first support wafer; and
bonding the subset of the plurality of chips to a target substrate.

US Pat. No. 10,460,970

ELECTROSTATIC CHUCK

NGK Insulators, Ltd., Na...

1. An electrostatic chuck comprising:a dielectric layer including an oriented alumina sintered body having a degree of c-plane orientation of 5% or more, the degree of c-plane orientation being determined by a Lotgering method using an X-ray diffraction profile obtained by the irradiation of an X-ray in the 2? range of 20° to 70°;
a ceramic layer integrated with a surface disposed opposite a wafer placement surface of the dielectric layer; and
an electrostatic electrode between the dielectric layer and the ceramic layer,
wherein a proportion by volume of pores having a diameter of 0.2 ?m or more with respect to the volume of the oriented alumina sintered body is 130 ppm or less by volume.

US Pat. No. 10,460,969

BIPOLAR ELECTROSTATIC CHUCK AND METHOD FOR USING THE SAME

Applied Materials, Inc., ...

1. An electrostatic chuck comprising:a chuck body; and
a plurality of independently replaceable electrostatic chuck assemblies mounted in an array across the chuck body to define a substrate support surface suitable for supporting a large area substrate, at least a first electrostatic chuck assembly of the plurality of electrostatic chuck assemblies operable independent of an operation of a second electrostatic chuck assembly of the plurality of electrostatic chuck assemblies, wherein the first electrostatic chuck assembly is laterally spaced apart from the second electrostatic chuck assembly to form a gap therebetween, and wherein the chuck body comprises:
a port aligned with and configured to flow gas into the gap defined between the first and second electrostatic chuck assemblies.

US Pat. No. 10,460,968

ELECTROSTATIC CHUCK WITH VARIABLE PIXELATED MAGNETIC FIELD

Applied Materials, Inc., ...

1. An electrostatic chuck (ESC), comprising:a ceramic plate having a front surface and a back surface, the front surface for supporting a wafer or substrate;
a base coupled to the back surface of the ceramic plate, wherein the base is bonded to the ceramic plate with a perforated bonding layer; and
a plurality of discrete electromagnets disposed in the base, the plurality of discrete electromagnets configured to provide pixelated magnetic field tuning capability for the ESC, wherein individual ones of the plurality of discrete electromagnets are directly exposed to the ceramic plate through holes in the perforated bonding layer and through holes in the base, wherein the holes in the perforated bonding layer are aligned with the holes in the base, wherein the plurality of discrete electromagnets comprises discrete electromagnets arranged in a plurality of concentric circles, and wherein each of the plurality of concentric circles comprises a plurality of the plurality of discrete electromagnets.

US Pat. No. 10,460,967

OVERHEAD TRANSPORT VEHICLE SYSTEM AND TEACHING METHOD FOR OVERHEAD TRANSPORT VEHICLE

MURATA MACHINERY, LTD., ...

1. An overhead transport vehicle system comprising:a plurality of overhead transport vehicles each including:
a winding drum to wind a hoisting material, attached to a lift stage to transfer goods, by lap winding; and
a controller that controls an amount of rotation of the winding drum to control a height of the lift stage;
a storage that stores the amount of rotation of the winding drum corresponding to an overall length of the hoisting material, unique to each of the plurality of overhead transport vehicles; and
a calculator that calculates the amount of rotation of the winding drum, corresponding to a corresponding one of a plurality of transfer heights, for each of the plurality of overhead transport vehicles, from the amount of rotation unique to each of the plurality of overhead transports vehicle stored in the storage.

US Pat. No. 10,460,966

ENCAPSULATED INSTRUMENTED SUBSTRATE APPARATUS FOR ACQUIRING MEASUREMENT PARAMETERS IN HIGH TEMPERATURE PROCESS APPLICATIONS

KLA-Tencor Corporation, ...

1. An apparatus comprising:a substrate assembly including a bottom substrate and a top substrate, wherein the top substrate is mechanically coupled to the bottom substrate;
an electronic assembly;
a nested enclosure assembly including an outer enclosure and an inner enclosure, wherein the outer enclosure encloses the inner enclosure, wherein the inner enclosure encloses at least the electronic assembly;
an insulating medium disposed within a cavity between an outer surface of the inner enclosure and an inner surface of the outer enclosure; and
a sensor assembly communicatively coupled to the electronic assembly, wherein the sensor assembly includes one or more sensors, the one or more sensors disposed within the substrate assembly at one or more locations across the substrate assembly, wherein the one or more sensors are configured to acquire one or more measurement parameters at the one or more locations across the substrate assembly, wherein the electronic assembly is configured to receive the one or more measurement parameters from the one or more sensors, wherein the apparatus is disposed on a rotatable platform.

US Pat. No. 10,460,965

SUSCEPTOR

MARUWA CO., LTD., Owaria...

1. A susceptor having an upper surface on which a wafer is placed and a lower surface arranged on a side opposite to the upper surface, and configured to be rotated about a spindle which extends in a vertical direction, wherein:a bearing formed of a recessed section receiving the spindle is formed on the lower surface,
the bearing has a shape where the bearing is tip-narrowed toward the upper surface from the lower surface, and
a gap is formed in a side wall of the bearing such that the gap projects toward the outside of the bearing from a fitting surface between the bearing and the spindle in a horizontal direction perpendicular to the vertical direction,
wherein the fitting surface between the bearing and the spindle accounts for 80% or more of an area of a portion of a side surface of the spindle inserted into the bearing,
wherein a distal end portion of the spindle has a tapered shape, and
wherein the spindle engages the bearing at a downstream end of the distal end portion of the spindle where a size of the spindle agrees with a size of the bearing,
wherein the spindle is made of metal having higher thermal conductivity than a material of the susceptor.

US Pat. No. 10,460,964

SUBSTRATE LIQUID PROCESSING APPARATUS AND METHOD, AND COMPUTER-READABLE STORAGE MEDIUM STORED WITH SUBSTRATE LIQUID PROCESSING PROGRAM

Tokyo Electron Limited, ...

1. A substrate liquid processing apparatus comprising:a liquid processing chamber of which a top is opened, and configured to process a substrate with a processing liquid;
a processing liquid supply source connected to the liquid processing chamber through a processing liquid supply path provided with a first flow rate controller, and configured to supply the processing liquid to the liquid processing chamber through the processing liquid supply path;
a diluent supply source connected to the liquid processing chamber through a diluent supply path provided with a second flow rate controller, and configured to supply a diluent for diluting the processing liquid to the liquid processing chamber through the diluent supply path;
a controller configured to control the first flow rate controller and the second flow rate controller;
a concentration sensor connected to the controller, and provided on a circulation path of which both ends are connected with the liquid processing chamber, the concentration sensor being configured to detect a concentration of the processing liquid;
an atmospheric pressure sensor connected to the controller and configured to detect an atmospheric pressure,
wherein the controller is programmed to:
identify a set atmospheric pressure and a set concentration of the processing liquid, respectively;
detect the concentration of the processing liquid and the atmospheric pressure using the concentration sensor and the atmospheric pressure sensor, respectively;
when the detected atmospheric pressure is not equal to the set atmospheric pressure, correct the set concentration of the processing liquid according to the detected atmospheric pressure; and
when the detected concentration of the processing liquid is not equal to the set concentration of the processing liquid, control the second flow rate controller of the diluent supply path such that an amount of the diluent supplied from the diluent supply source to the liquid processing chamber is adjusted, thereby allowing the detected concentration of the processing liquid to become the set concentration of the processing liquid.

US Pat. No. 10,460,963

PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method of processing a processing target object, in which an organic film, a mask film and a resist film are stacked in sequence, by plasma, the plasma processing method comprising:a process of supplying a modifying gas, which is a H2 gas, a hydrogen halide gas, or a mixed gas containing a rare gas and a H2 gas or a hydrogen halide gas, into a chamber accommodating therein the processing target object in which a preset pattern is formed on the resist film;
a modifying process of modifying the resist film of the processing target object by plasma of the modifying gas at a processing temperature equal to or less than ?20° C.,
a process of supplying a first processing gas for etching into the chamber; and
a first etching process of etching the mask film with the resist film modified in the modifying process as a mask by plasma of the first processing gas at a processing temperature within a range from 0° C. to 40° C.

US Pat. No. 10,460,962

SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a holding plate provided with a first through hole and configured to hold a substrate;
a rotation driving unit configured to rotate the holding plate;
a lift pin provided above the holding plate and configured to support the substrate from below;
a liquid supply unit provided to pass through the first through hole and configured to supply a liquid to a rear surface of the substrate held by the holding plate; and
an elevating device configured to move the lift pin and the liquid supply unit up and down between at a neighboring position where the lift pin and the liquid supply unit are adjacent to the holding plate and the substrate is held and at a distanced position where the lift pin and the liquid supply unit are distanced upwards from the holding plate and the substrate is carried out,
wherein the elevating device comprises a first lifting member configured to move the lift pin to the distanced position,
the first lifting member is in a disconnected state with respect to the lift pin when the lift pin and the liquid supply unit are located at the neighboring position, and
when the lift pin and the liquid supply unit are moved from the neighboring position to the distanced position, the first lifting member is turned from the disconnected state to a connected state where the first lifting member is connected to the lift pin, and the elevating device raises only the lift pin without raising the liquid supply unit for a time during which the first lifting member is moved up to a preset position, where the lift pin comes into contact with the rear surface of the substrate, while being connected to the lift pin, and raises the lift pin and the liquid supply unit for a time during which the first lifting member is raised from the preset position to the distanced position.

US Pat. No. 10,460,961

SUBSTRATE PROCESSING APPARATUS

SHIBAURA MECHATRONICS COR...

1. A substrate processing apparatus, comprising:a processing chamber provided therein with a support part configured to support a substrate having a surface to be treated, the processing chamber being configured such that air flows from above to the surface to be treated of the substrate supported by the support part;
a heater arranged so as not to be above the support part and configured to emit light for heating; and
an optical member arranged in the processing chamber so as not to be above the support part and configured to guide the light emitted by the heater and having passed above the support part to the surface to be treated of the substrate supported by the support part.

US Pat. No. 10,460,960

GAS PANEL APPARATUS AND METHOD FOR REDUCING EXHAUST REQUIREMENTS

APPLIED MATERIALS, INC., ...

1. An apparatus for delivering gases, comprising:a gas stick to deliver to at least a portion of the apparatus at least one gas to be delivered by the apparatus;
a purge module including a purge stick and a plurality of diffusers to distribute an inert gas in at least one portion of the apparatus in which a gas to be delivered by the apparatus is present;
at least one pressure sensor to detect leaks in the apparatus; and
a controller, the controller including a processor and a memory coupled to the processor, the memory having stored therein instructions executable by the processor to configure the controller to:
communicate a signal to cause the purge module to distribute the inert gas in the at least one interior portion of the apparatus;
monitor for leaks in the at least one interior portion of the apparatus using signals received from the at least one pressure sensor; and
in response to a detected leak, communicate a signal to cause the purge module to increase the distribution of the inert gas in at least the portion of the apparatus in which the leak was detected.

US Pat. No. 10,460,959

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A manufacturing method of a package structure, comprising:providing a carrier;
bonding a semiconductor chip on the carrier, wherein the semiconductor chip comprises a plurality of conductive pads exposed at an active surface of the semiconductor chip;
forming an insulating material layer over the carrier and encapsulating the semiconductor chip after the semiconductor chip is bonded on the carrier, wherein the insulating material layer comprises a first surface and a second surface opposite to the first surface, a thickness of the insulating material layer is greater than a thickness of the semiconductor chip, and the plurality of conductive pads are covered by the insulating material layer;
patterning the first surface of the insulating material layer to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer;
forming a plurality of conductive posts in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip, and the plurality of conductive posts extend onto the first surface of the insulating layer;
forming a plurality of conductive vias in the second openings, wherein the plurality of conductive vias extend onto the first surface of the insulating layer;
forming a redistribution layer over the first surface of the insulating material layer, wherein the redistribution layer is electrically connected to the plurality of conductive posts and the plurality of conductive vias;
de-bonding the carrier; and
forming a plurality of conductive terminals on the second surface of the insulating material layer, wherein the plurality of conductive terminals is electrically connected to the redistribution layer through the plurality of conductive vias.

US Pat. No. 10,460,958

METHOD OF MANUFACTURING EMBEDDED PACKAGING WITH PREFORMED VIAS

Invensas Corporation, Sa...

1. A method of forming a microelectronic assembly, comprising:forming a structure including a microelectronic element having a front surface, edge surfaces bounding the front surface, and contacts at the front surface, and substantially rigid metal posts extending in a first direction, the posts disposed between at least one of the edge surfaces and a corresponding edge of the structure, each metal post having a sidewall separating first and second end surfaces of such metal post from one another, the sidewalls of the metal posts having a root mean square (rms) surface roughness of less than about 1 micron; and then,
forming an encapsulation having a thickness extending in the first direction between first and second surfaces of the encapsulation, the encapsulation contacting at least the edge surfaces of the microelectronic element and the sidewalls of the metal posts, wherein the metal posts extend at least partly through the thickness, and the encapsulation electrically insulates adjacent metal posts from one another;
depositing an insulation layer overlying the first surface of the encapsulation and having a thickness extending away from the first surface of the encapsulation;
forming connection elements directly adjacent and extending away from the first end surfaces of the metal posts and through the thickness of the insulation layer, wherein at least some connection elements have cross sections smaller than respective cross sections of the metal posts from which the connection elements extend;
depositing an electrically conductive redistribution structure on the insulation layer, the redistribution structure electrically connecting at least some metal posts with the contacts of the microelectronic element; and
forming terminals at a first side of the microelectronic assembly adjacent to the first surface of the encapsulation, wherein at least some of the at least some connection elements electrically connect at least some of the first end surfaces with corresponding terminals.

US Pat. No. 10,460,957

CONTROL OF UNDER-FILL USING AN ENCAPSULANT FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE

SKYWORKS SOLUTIONS, INC.,...

1. A method of fabricating a packaged radio-frequency (RF) device, the method comprising:mounting components to a first side of a packaging substrate;
coating solder balls with a fluxing agent;
attaching the solder balls to a second side of the packaging substrate;
encapsulating the solder balls with an encapsulant that forms an obtuse angle with the packaging substrate;
attaching a lower component to the second side of the packaging substrate; and
under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent such that the under-filling agent contacts the encapsulant, the encapsulant not being removed in a cleaning process following attachment of the solder balls to the packaging substrate.

US Pat. No. 10,460,956

INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES

International Business Ma...

1. A method of forming an interposer, said method comprising:creating a lattice structure having a plurality of unit cells composed of regularly repeating openings having a first dimension in a non-silicon interposer substrate;
filling an entirety of each unit cell of said plurality of unit cells with a dielectric material, wherein said dielectric material present in each unit cell has a topmost surface that is coplanar with a topmost surface of said lattice structure;
forming a plurality of holes into said topmost surface of said dielectric material present in each unit cell, wherein each hole extends downward from said topmost surface of said dielectric material, has a second dimension that is less than said first dimension and is laterally surrounded by a remaining portion of said dielectric material; and
forming a conductive structure in each hole of said plurality of holes, wherein each conductive structure has a topmost surface that is coplanar with said topmost surface of remaining portions of said dielectric material and said topmost surface of said lattice structure.

US Pat. No. 10,460,955

METHODOLOGY FOR ANNEALING GROUP III-NITRIDE SEMICONDUCTOR DEVICE STRUCTURES USING NOVEL WEIGHTED COVER SYSTEMS

The United States of Amer...

1. A method for preventing the escape of nitrogen from a Group-III nitride semiconductor covered with an annealing cap during annealing, the method comprising:covering the annealing cap on the Group-III nitride semiconductor with a weighted cover system comprising a protective cover placed on top of the capped Group-III nitride semiconductor; and
annealing the Group-III nitride semiconductor while covered with the weighted cover system at a temperate in excess of 1250° C. for at least 30 minutes,
wherein the weighted cover system provides a sufficient force for preventing the escape of nitrogen from the capped Group-III nitride semiconductor and delamination of the annealing cap from the Group-III nitride semiconductor during said annealing; and
wherein the protective cover has sufficient flexibility and sufficient force applied to permit it to conform to the bow or warpage of the capped semiconductor and to maintain intimate contact with the capped semiconductor surface during the annealing.

US Pat. No. 10,460,953

SEMICONDUCTOR MANUFACTURING APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A HIGH-K INSULATING FILM, AND A METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

HITACHI HIGH-TECHNOLOGIES...

1. A method for manufacturing a semiconductor device, the method comprising:placing, in a processing chamber, a semiconductor substrate on which a mask layer having a predetermined pattern shape is formed on a high-k insulating film;
desorbing gas or a foreign matter adsorbed on a surface of the semiconductor substrate;
supplying reactive gas to the processing chamber in a state where a temperature of the semiconductor substrate falls below a predetermined temperature;
stopping the supply of the reactive gas and heating the semiconductor substrate; and
vaporizing an organometallic complex generated by reacting with a metal element included in the high-k insulating film and exhausting the vaporized organometallic complex from the processing chamber,
wherein the reactive gas is mixed gas including complex-forming gas forming the organometallic complex by reacting with the metal element included in the high-k insulating film and complex stabilizing material gas that increases stability of the organometallic complex.

US Pat. No. 10,460,952

STRESS RELIEVING SEMICONDUCTOR LAYER

Sensor Electronic Technol...

1. A structure comprising:a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands; and
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

US Pat. No. 10,460,951

GAS REACTION TRAJECTORY CONTROL THROUGH TUNABLE PLASMA DISSOCIATION FOR WAFER BY-PRODUCT DISTRIBUTION AND ETCH FEATURE PROFILE UNIFORMITY

Lam Research Corporation,...

1. A method for delivering gases to a plasma processing chamber having a substrate support for supporting a substrate, a dielectric window disposed over the substrate support, a center region of the dielectric window includes a gas feed injector that has an inner feed and an outer feed that surrounds the inner feed, and an electrode is disposed over the dielectric window, the method comprising:convectively flowing a reactant gas into the plasma processing chamber via the inner feed of the gas feed injector;
diffusively flowing a tuning gas into the plasma processing chamber via the outer feed of the gas feed injector, the tuning gas having a different chemical composition than the reactant gas, the tuning gas is fed via the outer feed and into the plasma processing chamber at an angle that is away from the reactant gas that is fed via the inner feed and into the plasma processing chamber, wherein the angle causes a fraction of the tuning gas to flow toward the dielectric window that is under the electrode and wherein said reactant gas is flown separately into the plasma process chamber from the tuning gas;
providing radio frequency (RF) power to the electrode, wherein the fraction of the tuning gas that is diffusively flown into the plasma processing chamber is exposed to the RF power and dissociated before mixing with the reactant gas that is convectively flown into the plasma processing chamber, wherein the RF power is configured to ignite a plasma using a mixture of the tuning gas, the fraction of tuning gas that is dissociated, and the reactant gas; and
adjusting a rate of flow of one or both of the convectively flown reactant gas and the diffusively flown tuning gas to control etch uniformity across a surface of the substrate.

US Pat. No. 10,460,950

SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD

Tokyo Electron Limited, ...

1. A substrate processing system comprising:a memory including a program;
a processor configured to execute the program to operate the substrate processing system;
an etching apparatus configured to supply a gas containing fluorocarbon to generate plasma so as to perform an etching process on a film including silicon formed on a substrate, wherein the etching process is performed by using plasma through a mask formed on the film including silicon;
a film forming apparatus configured to supply a gas containing carbon so as to form a film including carbon on the etched film including silicon, wherein the film forming apparatus is provided separately from the etching apparatus;
the processor is configured to execute the program to cause the etching apparatus to perform:
a first etching step in which the film including silicon is partway etched by using plasma; and
a second etching step in which the film including silicon, on which the film including carbon is formed, is further etched by using plasma,
the processor is further configured to execute the program to cause the film forming apparatus to perform a film forming step in which the film including carbon is formed on the film including silicon on which the first etching step has been performed,
wherein the processor is configured to execute the program to cause the film forming apparatus to further perform a treatment process with any of a single gas of monosilane (SiH4) and a mixed gas containing monosilane after the film forming step and before the second etching step.

US Pat. No. 10,460,949

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus for performing a predetermined substrate process on a plurality of target substrates under a vacuum atmosphere, comprising:a plurality of processing parts installed within a single chamber and configured to perform the substrate process on the plurality of target substrates, respectively, each of the plurality of processing parts including a substrate mounting table on which one of the plurality of target substrates is mounted, a showerhead facing the substrate mounting table, and a cylindrical inner wall surrounding the substrate mounting table and the showerhead so as to define a process space located between the substrate mounting table and the showerhead;
a gas supply mechanism positioned outside the single chamber and configured to separately supply a processing gas and a pressure control gas to the plurality of processing parts, the gas supply mechanism including a processing gas supply pipe and a pressure control gas supply pipe which are connected to the showerhead of each of the plurality of processing parts, and each of the processing gas supply pipe and the pressure control gas supply pipe including flow rate controllers and on-off valves;
a single exhaust mechanism configured to collectively exhaust the processing gas and the pressure control gas within the plurality of processing parts, the single exhaust mechanism including an exhaust pipe connecting an exhaust port formed in a bottom portion of the single chamber with a vacuum pump via an automatic pressure control valve; and
a control part as a process controller configured to control the gas supply mechanism and the single exhaust mechanism,
wherein the control part performs a control to:
while the inside of the plurality of processing parts are collectively exhausted by the single exhaust mechanism,
supply the pressure control gas into the plurality of processing parts such that the internal pressure of the plurality of processing parts is stabilized to have the same level of pressure;
when the internal pressure of the plurality of processing parts is stabilized to have the same level of pressure, start supply of the processing gas into the plurality of processing parts, and supply the pressure control gas into the plurality of processing parts at a first flow rate, such that the predetermined substrate process is performed in the plurality of processing parts, the processing gas and the pressure control gas being different from each other; and
when the predetermined substrate process is terminated in at least one of the plurality of processing parts, stop the supply of the processing gas into the at least one of the plurality of processing parts, and supply the pressure control gas into the at least one of the plurality of processing parts at a second flow rate that is different from the first flow rate, while the processing gas continues to be supplied into the remaining of the plurality of processing parts and the pressure control gas continues to be supplied into the remaining of the plurality of processing parts at the first flow rate,
wherein the first flow rate and the second flow rate are non-zero and set such that a difference in internal pressure among the plurality of processing parts is prevented from occurring due to the stop of the supply of the processing gas.

US Pat. No. 10,460,948

STRESS ASSISTED WET AND DRY EPITAXIAL LIFT OFF

International Business Ma...

1. A method, comprising:providing a sacrificial release layer on a base substrate;
forming a device layer on the sacrificial release layer;
depositing a metal stressor layer on the device layer;
creating a curvature in the device layer and causing the device layer to bend away from the base substrate at a first edge of the device layer such that the device layer remains in contact with the sacrificial release layer at least at a second opposing edge of the device layer;
etching the sacrificial release layer from an end surface thereof as the device layer is caused to bend away from the first edge and as the sacrificial release layer is exposed; and
releasing the device layer and the metal stressor layer from the base substrate.

US Pat. No. 10,460,947

METHOD FOR POLISHING SILICON WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for polishing a silicon wafer, the method comprising:recovering a used slurry containing polishing abrasive grains and obtained from a slurry that had been supplied to the silicon wafer and used for polishing; and
circulating and supplying the recovered used slurry to the silicon wafer to polish the silicon wafer, wherein
a mixed alkali solution containing
a chelating agent and
either or both of a pH adjuster and a polishing rate accelerator is added to the recovered used slurry without adding unused polishing abrasive grains, and the recovered used slurry is circulated and supplied to the silicon wafer to polish the silicon wafer,
and further comprising:
measuring a concentration of the chelating agent in the recovered used slurry by an absorbance measuring method when the used slurry is circulated and supplied;
quantifying the chelating agent in the used slurry based on a result of the measurement; and
setting a mixing condition of the chelating agent in the mixed alkali solution based on a result of the quantification such that the concentration of the chelating agent in the used slurry is kept constant.

US Pat. No. 10,460,946

NATURALLY OXIDIZED FILM REMOVING METHOD AND NATURALLY OXIDIZED FILM REMOVING DEVICE

TOKYO ELECTRON LIMITED, ...

1. A method of removing a natural oxide film formed on a surface of a semiconductor layer containing a compound of indium and an element other than indium as a main ingredient, comprising:supplying a first etching gas which is ?-diketone to the semiconductor layer and heating the semiconductor layer to remove an oxide of the indium constituting the natural oxide film; and
supplying a second etching gas to the semiconductor layer and heating the semiconductor layer to remove an oxide of the element other than indium constituting the natural oxide film.

US Pat. No. 10,460,945

MACHINE SUITABLE FOR PLATING A CAVITY OF A SEMI-CONDUCTIVE OR CONDUCTIVE SUBSTRATE SUCH AS A THROUGH VIA STRUCTURE

ALCHIMER, Massy (FR)

1. A machine adapted to metallise a cavity of a semiconductive or conductive substrate, said substrate having a first active face on which said cavity is formed and a rear face opposite to said first face,wherein said machine comprises:
at least one pre-wetting module for pre-wetting the substrate,
at least one insulating dielectric layer depositing module for depositing an insulating dielectric layer,
at least one barrier layer depositing module for depositing a barrier layer to diffusion,
at least one filling module for filling said cavity by electrodeposition of a metal, and
at least one annealing module for annealing the substrate,
wherein each of said at least one pre-wetting modules, each of said at least one insulating dielectric layer depositing modules, each of said at least one barrier layer depositing modules, and each of said at least one filling modules comprises a container having a bottom and a support, each said container containing a liquid bath for immersing the substrate, said support being arranged horizontally at the bottom of each said container to receive said rear face of the substrate such that the active face of said substrate is oriented upwards in the direction opposite the bottom of each of the modules,
such that the machine completes the entire metallisation process of the cavity.

US Pat. No. 10,460,944

FULLY DEPLETED SEMICONDUCTOR ON INSULATOR TRANSISTOR WITH ENHANCED BACK BIASING TUNABILITY

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a fully depleted semiconductor on insulator device, comprising:
forming a buried dielectric layer over a substrate;
forming a partial structure in which a semiconductor layer is coupled to and over the buried dielectric layer, and a gate structure is coupled to and over the semiconductor layer; and
flipping the partial structure into a flipped orientation with the buried dielectric layer over the semiconductor layer and the semiconductor layer over the gate structure, and removing the substrate to expose buried dielectric layer;
in the flipped orientation, forming a back-gate stack coupled to the buried dielectric layer, comprising forming a back-gate conductor layer of the back-gate stack coupled to and over the buried dielectric layer, forming a ferroelectric material layer coupled to and over the back-gate conductor layer, and forming a back-gate contact layer coupled to and over the ferroelectric material layer.

US Pat. No. 10,460,943

INTEGRATED STRUCTURES HAVING GALLIUM-CONTAINING REGIONS

Micron Technology, Inc., ...

1. An integrated structure, comprising:a conductive gate;
a charge-storage region under the conductive gate;
a tunneling region under the charge-storage region;
a semiconductor-containing channel region under and directly against the tunneling region, the semiconductor-containing channel region comprising monocrystalline silicon and being part of a monocrystalline-silicon substrate that extends laterally outward beyond the charge-storage region along a cross-section; and
wherein the tunneling region includes a dielectric material consisting essentially of SiO2 directly adjacent a gallium-containing material and directly adjacent the semiconductor-containing channel region.

US Pat. No. 10,460,942

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

16. A method for manufacturing a semiconductor structure comprising:forming an active semiconductor fin;
forming a dielectric material around the active semiconductor fin;
forming a protection layer over the active semiconductor fin and the dielectric material;
forming a photoresist layer over the protection layer;
doping the dielectric material with dopants after forming the protection layer;
removing the protection layer after doping the dielectric material;
recessing the doped dielectric material after removing the protection layer, wherein recessing the doped dielectric material comprises:
forming a sacrificial layer on the doped dielectric material after removing the protection layer; and
removing the sacrificial layer; and
tuning a thickness of the doped dielectric material by repeating forming the sacrificial layer and removing the sacrificial layer.

US Pat. No. 10,460,941

PLASMA DOPING USING A SOLID DOPANT SOURCE

Varian Semiconductor Equi...

13. A method of processing a workpiece, comprising:placing a workpiece in a plasma chamber; and
creating a plasma by energizing a working gas in the plasma chamber while the workpiece is disposed in the plasma chamber; and
performing a deposition process, wherein the plasma causes dopant species that coated interior surfaces of the plasma chamber to sputter and deposit on the workpiece, wherein the working gas does not comprise the dopant species and the workpiece is not negatively biased during the deposition process.

US Pat. No. 10,460,940

MASK FORMATION BY SELECTIVELY REMOVING PORTIONS OF A LAYER THAT HAVE NOT BEEN IMPLANTED

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:forming a dielectric layer over a substrate; and
forming a mask over the dielectric layer, forming the mask comprising:
depositing a first layer over the dielectric layer;
implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy;
after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and
forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

US Pat. No. 10,460,939

PATTERNING METHOD

UNITED MICROELECTRONICS C...

1. A patterning method, comprising:forming a second mask layer on a first mask layer;
performing a patterning process to the first mask layer and the second mask layer, wherein the first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern;
performing a first trim process to the second mask pattern, wherein a width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process;
forming a cover layer covering the first mask pattern and the second mask pattern after the first trim process;
performing an etching process to the first mask pattern after the step of forming the cover layer;
removing a part of the cover layer for exposing the second mask pattern before the etching process;
removing the second mask pattern before the etching process; and
performing a second trim process to the cover layer after the step of removing the second mask pattern and before the etching process.

US Pat. No. 10,460,938

METHOD FOR PATTERNING A SUBSTRATE USING A LAYER WITH MULTIPLE MATERIALS

Tokyo Electron Limited, ...

1. A method of patterning a substrate, the method comprising:forming mandrels on a target layer of a substrate, the mandrels being comprised of at least two layers of material, the mandrels including a bottom layer comprised of a first material, and a top layer comprised of a second material different than the first material, the target layer being comprised of a fifth material;
forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers comprised of a third material;
depositing a fill material on the substrate that at least partially fills open spaces defined between the sidewall spacers, the fill material being comprised of a fourth material, wherein the first material, the third material and the fourth material have different etch resistivities compared to each other for one or more particular etch chemistries;
forming a mask on the fill material, the mask defining one or more openings providing uncovered portions of the fill material;
executing an etch process that (i) etches the one or more uncovered portions of the fill material to provide one or more uncovered portions of the top layer of the mandrels, and that (ii) etches the one or more uncovered portions of the top layer of the mandrels, and
subsequent to executing the etch process, executing a chemical-mechanical polishing step that uses the bottom layer of the mandrels as a planarization stop material layer, the chemical-mechanical polishing step removing the third material above a top surface of the bottom layer of the mandrels; and
etching the target layer using the bottom layer and the fill material as a combined etch mask.

US Pat. No. 10,460,937

POST GROWTH HETEROEPITAXIAL LAYER SEPARATION FOR DEFECT REDUCTION IN HETEROEPITAXIAL FILMS

International Business Ma...

1. A method for reducing defects in a semiconductor structure, the method comprising:epitaxially growing a first crystalline material over a crystalline substrate, the first crystalline material being substantially planar;
epitaxially growing a second crystalline material over the first crystalline material;
patterning and removing portions of the second crystalline material to form openings extending to a top surface of the first crystalline material without penetrating the first crystalline material;
converting the first crystalline material into a non-crystalline material;
depositing a thermally stable material in the openings, the thermally stable material directly contacting the top surface of the converted substantially planar first crystalline material;
depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure; and
annealing the substantially enclosed semiconductor structure.

US Pat. No. 10,460,936

PHOTO-ASSISTED DEPOSITION OF FLOWABLE FILMS

APPLIED MATERIALS, INC., ...

1. A processing chamber, comprising:a chamber lid;
a UV transparent window disposed in the chamber lid;
a chamber body defining a processing space, the processing space containing a substrate support;
a first UV transparent divider having a plurality of openings;
a gas volume formed between the UV transparent window and the first UV transparent divider, the gas volume fluidly coupled to a first flow channel through which at least one first gas enters the processing chamber;
a distribution volume separated from the gas volume by the first UV transparent divider, the distribution volume being fluidly coupled to a second flow channel through which at least one second gas enters the distribution volume; and
a source of UV radiation directed towards the gas volume, the UV transparent window disposed directly between the source of UV radiation and the gas volume.

US Pat. No. 10,460,935

ELECTRONIC DEVICE HAVING TWO-DIMENSIONAL (2D) MATERIAL LAYER AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE BY INKJET PRINTING

Samsung Electronics Co., ...

1. A method of manufacturing an electronic device, the method comprising:forming by inkjet printing a two-dimensional (2D) material layer on a substrate, the 2D material layer including a plurality of 2D nanomaterials that have semiconductor characteristics and at least some of the plurality of 2D nanomaterials overlap one another, wherein the plurality of 2D nanomaterials are planar in shape, and each of the plurality of 2D nanomaterials include one of a transition metal dichalcogenide (TMD), phosphorene, germanane, or silicene; and
forming a first electrode and a second electrode that are connected to the 2D material layer.

US Pat. No. 10,460,934

CRYSTALLINE FILM, SEMICONDUCTOR DEVICE INCLUDING CRYSTALLINE FILM, AND METHOD FOR PRODUCING CRYSTALLINE FILM

FLOSFIA INC., Kyoto (JP)...

1. A crystalline film comprising:a crystalline metal oxide as a major component;
the crystalline film comprising a corundum structure, a surface area that is 9 ?m2 or more, and a dislocation density that is less than 5×106 cm?2.

US Pat. No. 10,460,933

TWO-STEP PROCESS FOR GAPFILLING HIGH ASPECT RATIO TRENCHES WITH AMORPHOUS SILICON FILM

APPLIED MATERIALS, INC., ...

1. A method for manufacturing a semiconductor device, comprising:positioning a substrate having at least one opening formed in a substrate surface thereof in a processing chamber, wherein the at least one opening is defined by sidewalls and a bottom surface;
conformally depositing a silicon liner layer over the substrate surface and the sidewalls and the bottom surface of the at least one opening;
filling the at least one opening with a flowable silicon film; and
curing the silicon liner layer and the flowable silicon film, wherein the silicon liner layer and the flowable silicon film each comprises amorphous silicon.

US Pat. No. 10,460,932

SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON FILLED GAPS AND METHODS FOR FORMING

ASM IP Holding B.V., Alm...

1. A method for producing a semiconductor device, comprising:providing in a deposition chamber a substrate having a gap;
depositing an amorphous silicon film onto the substrate having a thickness sufficient to fill the gap, wherein depositing an amorphous silicon film comprises:
heating the substrate to a deposition temperature between 300 and 500° C.; and
providing a feed gas that comprises a first silicon reactant into the deposition chamber, wherein the first reactant deposits silicon forming the amorphous silicon film,
wherein the amorphous silicon film has a hydrogen concentration between 0.1 and 10 at. %,
wherein the amorphous silicon film filling the gap defines voids within the gap; and
reducing a size of, or eliminating, the voids by annealing the amorphous silicon film at a temperature between 500 and 700° C.

US Pat. No. 10,460,931

SEMICONDUCTOR TRANSISTOR HAVING SUPERLATTICE STRUCTURES

Robert Bosch GmbH, Stutt...

1. A transistor, comprising:a substrate of a first doping type;
an epitaxy layer of the first doping type above the substrate;
a channel layer of a second doping type, which differs from the first doping type, above the epitaxy layer;
a plurality of trenches in the channel layer, which have a gate electrode situated within the trenches and are bordered by a source terminal of the first doping type above the channel layer;
a plurality of shielding areas of the second doping type situated below the gate electrode;
wherein the shielding areas form together an interconnection of shielding areas below the trenches and several of the shielding areas are jointly guided to terminals for contacting the shielding areas,
wherein a grid is made up of first cells, which are formed from the channel terminal of the second doping type for contacting the channel layer and a source terminal bordering the channel terminal, the first cells being bordered by trenches, the grid having gaps into which second cells are inserted, which have the terminals for the shielding areas for contacting the interconnection of the shielding areas.

US Pat. No. 10,460,930

SELECTIVE GROWTH OF SIO2 ON DIELECTRIC SURFACES IN THE PRESENCE OF COPPER

Lam Research Corporation,...

1. A method of selectively depositing silicon oxide on a dielectric material relative to copper on a substrate, the method comprising:(a) providing the substrate comprising the dielectric material and exposed copper metal surface;
(b) prior to depositing the silicon oxide, exposing the substrate to a copper-blocking reagent to selectively adsorb onto the exposed copper metal surface;
(c) exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the dielectric material;
(d) exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidant to convert the adsorbed silicon-containing precursors to silicon oxide; and
(e) exposing the substrate to a reducing agent to reduce the exposed copper metal surface.

US Pat. No. 10,460,929

ORGANOAMINOSILANE PRECURSORS AND METHODS FOR DEPOSITING FILMS COMPRISING SAME

VERSUM MATERIALS US, LLC,...

1. A composition comprising at least one organoaminosilane compound represented by:
wherein R1 is selected from the group consisting of a linear or branched C1 to C10 alkyl group, a linear or branched C3 to C10 alkenyl group, a linear or branched C3 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, and a C5 to C10 aryl group; R2 is selected from the group consisting of hydrogen, a linear or branched C1 to C10 alkyl group, a linear or branched C3 to C10 alkenyl group, a linear or branched C3 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, and a C5 to C10 aryl group; R3 are each independently selected from the group consisting of a linear or branched C1 to C10 alkylene group, a linear or branched C3 to C6 alkenylene group, a linear or branched C3 to C6 alkynylene group, a C3 to C10 cyclic alkylene group, a C3 to C10 hetero-cyclic alkylene group, a C5 to C10 arylene group, and a C5 to C10 hetero-arylene group; n in Formula A equals 1; m in Formula A equals 0; and, wherein the compound is made by a method comprising the steps of:
reacting an amine having a formula selected from R1R2NH and R1NH2 wherein R1 in the amine is selected from the group consisting of a linear or branched C1 to C10 alkyl group, a linear or branched C3 to C10 alkenyl group, a linear or branched C3 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, and a C5 to C10 aryl group; R2 in the amine is selected from the group consisting of hydrogen, a linear or branched C1 to C10 alkyl group, a linear or branched C3 to C10 alkenyl group, a linear or branched C3 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, and a C5 to C10 aryl group, with a silicon source comprising at least one compound selected from the group consisting of

wherein R3 and R4 in the silicon source are independently selected from the group consisting of a linear or branched C1 to C10 alkylene group, a linear or branched C3 to C6 alkenylene group, a linear or branched C3 to C6 alkynylene group, a C3 to C10 cyclic alkylene group, a C3 to C10 hetero-cyclic alkylene group, a C5 to C10 arylene group, and a C5 to C10 hetero-arylene group in the presence of a catalyst under reaction conditions sufficient for at least a portion of the silicon source and at least a portion of the amine to react and provide the organoaminosilane, and wherein the organoaminosilane is greater than 98 wt. % pure.

US Pat. No. 10,460,928

PROCESS FOR DEPOSITION OF TITANIUM OXYNITRIDE FOR USE IN INTEGRATED CIRCUIT FABRICATION

ASM IP Holding B.V., Alm...

1. A process for depositing a titanium oxynitride thin film comprising:contacting a substrate comprising silicon with a titanium reactant;
subsequently contacting the substrate with a second reactant comprising a plurality of reactive species generated by plasma, wherein the plurality of reactive species comprises nitrogen and oxygen; and
repeating the contacting steps until a titanium oxynitride thin film having a thickness of from about 1 nm to about 50 nm has been formed on the substrate, wherein the titanium oxynitride thin film is deposited at a temperature from 70° C. to 200° C.

US Pat. No. 10,460,927

METHODS OF FABRICATING A SIOCN LAYER USING A FIRST AND SECOND CARBON PRECURSOR, THE FIRST CARBON PRECURSOR BEING DIFFERENT FROM THE SECOND CARBON PRECURSOR

SAMSUNG ELECTRONICS CO., ...

1. A method of forming a SiOCN material layer, the method comprising:providing a substrate;
providing a silicon precursor onto the substrate;
providing an oxygen reactant onto the substrate;
providing a first carbon precursor onto the substrate;
providing a second carbon precursor onto the substrate; and
providing a nitrogen reactant onto the substrate,
wherein the first carbon precursor and the second carbon precursor are different materials, and
wherein:
the nitrogen reactant and the second carbon precursor are the same material, the silicon precursor and the first carbon precursor include the same material, providing the silicon precursor and providing the first carbon precursor are performed simultaneously, and providing the nitrogen reactant and providing the second carbon precursor are performed simultaneously, or
the silicon precursor and the second carbon precursor are the same material, and providing the silicon precursor and providing the second carbon precursor are performed simultaneously.

US Pat. No. 10,460,926

METHOD AND APPARATUS FOR CHEMICAL MECHANICAL POLISHING PROCESS

Taiwan Semiconductor Manu...

1. A method for processing a semiconductor wafer, comprising:transferring the semiconductor wafer from an interface tool to a chemical mechanical polishing (CMP) tool;
polishing the semiconductor wafer with the CMP tool;
transferring the semiconductor wafer back to the interface tool from the CMP tool; and
converting a mixture into a mist spray and discharging the mist spray over the semiconductor wafer in the interface tool after the semiconductor wafer is polished by the CMP tool.

US Pat. No. 10,460,925

METHOD FOR PROCESSING SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A method for processing a semiconductor device, wherein the semiconductor device comprises a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure, the method comprising:removing the nitride spacer on the protruding structure, wherein a portion of the epitaxial layer under the nitride spacer is further exposed;
performing a dilute hydrofluoric acid (DHF) cleaning process over the substrate after removing the nitride spacer, wherein a top surficial portion of the epitaxial layer is removed; and
performing a standard clean (SC) process over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

US Pat. No. 10,460,924

PROCESS FOR PRODUCING A GALLIUM ARSENIDE SUBSTRATE WHICH INCLUDES MARANGONI DRYING

FREIBERGER COMPOUND MATER...

1. A process for producing a surface-treated gallium arsenide substrate, the process comprising the following sequence of steps:a) oxidation treatment of at least one surface of a gallium arsenide substrate in dry condition by means of UV radiation and/or ozone gas;
b-i) contacting the at least one surface of the gallium arsenide substrate with an alkaline aqueous solution;
b-ii) contacting the at least one surface of the gallium arsenide substrate with water;
b-iii) contacting the at least one surface of the gallium arsenide substrate with an acidic aqueous solution comprising ozone as an oxidizing agent, wherein the ozone concentration in the acidic aqueous solution is between 10 ppm and 100 ppm;
b-iv) contacting the at least one surface of the gallium arsenide substrate with water, wherein the water at least initially contains a pH value modifying additive comprising NH3 in an amount to make the water sufficiently basic to remove oxides or prevent oxide formation on the at least one surface; and
c) Marangoni drying of the gallium arsenide substrate.

US Pat. No. 10,460,923

APPARATUS AND METHOD FOR TREATING SUBSTRATE

SEMES CO., LTD., Chungch...

1. A method for liquid-treating a substrate, comprising:a first treatment liquid supplying operation of supplying a first treatment liquid to a treatment location of the substrate, wherein the first treatment liquid includes hydrofluoric acid; and
a wetting operation of, after the first treatment liquid supplying operation, supplying a wetting liquid onto the substrate, wherein the wetting liquid is water,
wherein the wetting operation includes:
a simultaneous supply operation of supplying the wetting liquid to a first location while the first treatment liquid is supplied, and
wherein the first location is a location spaced apart from the treatment location.

US Pat. No. 10,460,922

METHOD AND APPARATUS FOR SUBSTRATE TRANSFER IN A THERMAL TREATMENT CHAMBER

Applied Materials, Inc., ...

1. A method for managing a thermal treatment chamber, comprising:staggering transfer of a first substrate, and a second substrate to a respective first slot, and a respective second slot of a carrier in the thermal treatment chamber via a transfer opening formed in the thermal treatment chamber, the first substrate and the second substrate each having a respective specified anneal time;
moving the carrier to a lowermost position in the thermal treatment chamber using an elevator mechanism coupled to the carrier after each of the first substrate and the second substrate have been transferred; and
timing movement of the carrier from the lowermost position to a position adjacent to the transfer opening using the elevator mechanism such that each of the first substrate and the second substrate are transferred out of the thermal treatment chamber at a respective determined time period for anneal.

US Pat. No. 10,460,921

HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING

Applied Materials, Inc., ...

1. A system to manufacture an electronic device, comprising:a non-transitory machine-readable storage medium containing instructions which when executed by the system cause the system to perform operations, comprising:
etching a layer stack over a substrate using a photoresist pattern deposited on the layer stack as a first mask,
curing the photoresist pattern, wherein the curing comprises forming a hardened crust layer on a top portion of the photoresist pattern using an ultraviolet light produced by a plasma with the photoresist pattern exposed directly to the plasma without etching the photoresist pattern, wherein the plasma is generated from a process gas comprising a gas selected from a group consisting of C4F6, C4F8, SF6, CF4, and SO2,
slimming the cured photoresist pattern, and
etching the layer stack using the slimmed photoresist pattern as a second mask, wherein the curing and the etching are performed in the same plasma etch chamber.

US Pat. No. 10,460,920

FLEXIBLE ION CONDUIT

Battelle Memorial Institu...

1. An apparatus, comprising:a flexible ion conduit extending between an input end situated to receive ions and an output end to deliver ions and defining an ion passageway, the flexible ion conduit including an inner conduit portion having an inner surface facing the interior ion passageway and having a plurality of RF electrodes situated to receive RF voltages wherein each RF voltage is out of phase with respect to the RF voltage applied to a nearest RF electrode of the RF electrodes to direct the received ions away from the inner surface of the ion passageway.

US Pat. No. 10,460,919

AUTOMATED DETERMINATION OF MASS SPECTROMETER COLLISION ENERGY

THERMO FINNIGAN LLC, San...

1. A method for identifying an intact protein within a sample containing a plurality of intact proteins using a mass spectrometer, the method comprising:(a) introducing the sample to an ionization source of the mass spectrometer;
(b) using the ionization source, generating a plurality of ion species from the plurality of intact proteins, whereby each protein gives rise to a respective subset of the plurality of ion species, wherein each ion species of each subset is a multi-protonated ion species generated from a respective one of the intact proteins;
(c) performing a mass analysis of the plurality of ion species using a mass analyzer of the mass spectrometer;
(d) automatically recognizing each subset of the plurality of ion species and assigning a charge state, z, to each recognized ion species and a molecular weight, MW, to each intact protein by mathematical analysis of data generated by the mass analysis;
(e) selecting a one of the ion species;
(f) automatically calculating a collision energy, CE, to be employed for fragmentation of the selected ion species, using the relationship
CE(Dp)=c+(1/k)[ln(1/Dp)?1],where Dp is a portion of the selected ion species that is desired to remain unfragmented after the fragmentation and c and k are functions only the charge state, z, of the selected ion species and the molecular weight, MW, of the intact protein from which the selected ion species was generated;(g) isolating the selected ion species and fragmenting said species so as to form fragment ion species therefrom using the automatically calculated collision energy; and
(h) mass analyzing the fragment ion species.

US Pat. No. 10,460,918

FORMING ION PUMP HAVING SILICON MANIFOLD

COLDQUANTA, INC, Boulder...

1. An ion-pump formation process comprising:forming a silicon manifold by forming a Penning-trap aperture and a flow aperture in a block of monocrystalline silicon, the Penning trap aperture being formed between a first pair of faces of the silicon block, the flow aperture being formed between a second pair of faces of the silicon block;
coating walls of the Penning-trap aperture and the flow aperture with conductive material, the resulting coated wall of the Penning-trap aperture defining a wall anode;
positioning cathodes so that the wall anode is located between the cathodes; and
hermetically sealing a volume including the cathode aperture and the cathodes.

US Pat. No. 10,460,917

MINIATURE ION PUMP

AOSense, Inc., Sunnyvale...

1. A system for ion pumping, comprising:an anode, wherein the anode comprises one or more cylindrical anode chambers, wherein at least one cylindrical anode chamber of the one or more cylindrical anode chambers has a central axis;
a cathode, wherein the cathode surrounds the anode, and wherein the central axis of the at least one cylindrical anode chamber of the one or more anode chambers is orthogonal to a longitudinal axis of a length of the cathode; and
a magnet, wherein the magnet comprises a Halbach magnet that surrounds the cathode, and wherein the longitudinal axis of the length of the cathode is coaxial with a longitudinal axis of a length of the magnet.

US Pat. No. 10,460,916

REAL TIME MONITORING WITH CLOSED LOOP CHUCKING FORCE CONTROL

APPLIED MATERIALS, INC., ...

1. A method for minimizing chucking forces on a workpiece disposed on a electrostatic chuck within a plasma processing chamber, the method comprising:placing a workpiece on an electrostatic chuck in a processing chamber;
striking a plasma within the processing chamber;
monitoring a deflection force on the workpiece;
applying a chucking voltage at a minimum value;
applying a backside gas pressure at a minimum pressure;
adjusting the chucking voltage and or backside gas pressure such that the deflection force is less than a threshold value; and
simultaneously ramping up the chucking voltage and the backside gas pressure.

US Pat. No. 10,460,915

ROTATABLE SUBSTRATE SUPPORT HAVING RADIO FREQUENCY APPLICATOR

APPLIED MATERIALS, INC., ...

1. A plasma processing system comprising:a processing chamber comprising:
a first electrode, wherein the first electrode at least partially defines a plasma cavity within the processing chamber, and
a second electrode, wherein the second electrode defines a plurality of apertures through the second electrode, and wherein the second electrode at least partially defines the plasma cavity within the processing chamber;
a plasma source electrically coupled with the first electrode and configured to generate a plasma within the plasma cavity; and
a substrate support assembly including:
a shaft assembly comprising a rotatable shaft surrounding a central conductive shaft, and an electrically insulative shaft positioned between the central conductive shaft and the rotatable shaft,
a pedestal coupled to the central conductive shaft of the shaft assembly, and
a first rotary connector coupled to the shaft assembly, wherein the first rotary connector comprises a rotatable radio frequency applicator, the rotatable radio frequency applicator comprising:
a first coil member surrounding a rotatable shaft member that is electromagnetically coupled to the shaft assembly during operation, the first coil member being rotatable with the rotatable shaft member during operation,
a second coil member surrounding the first coil member, the second coil member being stationary relative to the first coil member, wherein the first coil member electromagnetically couples with the second coil member when the rotatable radio frequency applicator is energized and provides a radio frequency power to the pedestal through the shaft assembly;
a first ground member coupling the first coil member with a rotatable portion of the shaft assembly; and
a second ground member coupling the second coil member with a stationary portion of the shaft assembly.

US Pat. No. 10,460,914

FERRITE CAGE RF ISOLATOR FOR POWER CIRCUITRY

LAM RESEARCH CORPORATION,...

1. Apparatus for providing isolated power to a component of a plasma processing chamber that also is subject to a plurality of RF signals, the plurality of RF signals including at least a first RF signal having a first RF frequency, the apparatus comprising:first and second coils; and
a ferrite cage that surrounds said first and second coils, said ferrite cage comprising:
a first dielectric disc supporting said first coil;
a second dielectric disc supporting said second coil;
first and second pluralities of ferrite pieces disposed on a side of said first dielectric disc facing away from said second dielectric disc;
third and fourth pluralities of ferrite pieces disposed on a side of said second dielectric disc facing away from said first dielectric disc;
the first through fourth pluralities of ferrite pieces being arranged such that the first and second dielectric discs and the first and second coils are inside the first through fourth pluralities of ferrite pieces;
a fifth plurality of ferrite pieces to connect respective ones of the first and second pluralities of ferrite pieces to the third and fourth pluralities of ferrite pieces;
said fifth plurality of ferrite pieces to separate said first and second dielectric discs so that the first and second coils are spaced apart by a predetermined distance; and
said first coil to receive an input voltage signal and said second coil to provide an isolated power signal.

US Pat. No. 10,460,913

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus comprising:a processing chamber which is disposed inside a vacuum container;
a sample stage which is disposed inside the processing chamber and has a top surface for placing a wafer to be processed thereon;
an electric field generating part which generates an electric field supplied into the processing chamber;
a coil which generates a magnetic field for generating plasma inside the processing chamber by an interaction with the electric field; and
a controller which increases or decreases an intensity of the plasma inside the processing chamber by repeatedly causing the intensity of the magnetic field generated by the coil to be at a first value and a second value lower than the first value in respective predetermined intervals,
wherein the wafer is processed while the plasma is repeatedly generated and diffused.

US Pat. No. 10,460,912

RF IMPEDANCE MATCHING CIRCUIT AND SYSTEMS AND METHODS INCORPORATING SAME

RENO TECHNOLOGIES, INC., ...

1. A radio frequency (RF) impedance matching circuit comprising:an RF input configured to operably couple to an RF source;
an RF output configured to operably couple to a plasma chamber;
a first electronically variable capacitor having a first variable capacitance;
a second electronically variable capacitor having a second variable capacitance; and
a control circuit operably coupled to the first and second electronically variable capacitors to control the first variable capacitance and the second variable capacitance, wherein the control circuit is configured to:
determine a variable impedance of the plasma chamber;
determine, based on the determined variable impedance of the plasma chamber, a first capacitance value for the first electronically variable capacitor and a second capacitance value for the second electronically variable capacitor; and
generate a control signal to alter at least one of the first variable capacitance and the second variable capacitance to the first capacitance value and the second capacitance value, respectively;
wherein the alteration of the at least one of the first variable capacitance and the second variable capacitance causes RF power reflected back to the RF source to begin decreasing within 150 ?sec of the determination of the variable impedance of the plasma chamber.

US Pat. No. 10,460,911

HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT

Eagle Harbor Technologies...

1. A high voltage, high frequency switching circuit comprising:a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than 10 kHz;
an output; and
a resistive output stage electrically coupled to and in parallel with the output of the high voltage switching power supply and the output, the resistive output stage has a resistance less than about 2000 ohms, the resistive output stage has a capacitance less than about 500 pF, the resistive output stage is configured to discharge a load coupled with the output that has been charged by the pulses from the high voltage switching power supply, and the resistive output stage configured to dissipate over about 1 kilowatt of average power.

US Pat. No. 10,460,910

HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT

Eagle Harbor Technologies...

10. The high voltage, high frequency switching circuit according to claim 1, wherein the inductor has a value less than 15 ?H and 100 nH.

US Pat. No. 10,460,909

CHARGED PARTICLE BEAM WRITING METHOD AND CHARGED PARTICLE BEAM WRITING APPARATUS

NuFlare Technology, Inc.,...

1. A charged particle beam writing method using a charged particle beam writing apparatus including an emitting unit, a current limiting aperture, a blanking deflector, a blanking aperture, and an electron lens, the emitting unit emitting a charged particle beam, the current limiting aperture being provided with an opening through which part of the charged particle beam passes, the blanking deflector switching between beam ON and beam OFF so as to control an irradiation time by deflecting the charged particle beam having passed through the current limiting aperture, the blanking aperture blocking the charged particle beam deflected by the blanking deflector in such a manner that the beam OFF state is entered, the electron lens being disposed between the current limiting aperture and the blanking aperture, the method comprising:substituting a lens value into a given function and calculating an offset time, the lens value being set for the electron lens;
adding the offset time to an irradiation time for writing a pattern, and correcting the irradiation time; and
switching between the beam ON and the beam OFF by using the blanking deflector based on the corrected irradiation time.

US Pat. No. 10,460,908

MULTI CHARGED PARTICLE BEAM WRITING APPARATUS AND MULTI CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A multiple charged particle beam writing apparatus comprising:an emission source configured to emit a charged particle beam;
a shaping aperture array substrate configured to form multiple charged particle beams by being irradiated with the charged particle beam;
a combination setting circuitry configured to set, for each of a plurality of design grids being irradiation positions in design of the multiple charged particle beams, a plurality of combinations each composed of three beams whose actual irradiation positions surround a design grid concerned in the plurality of design grids, by using four or more beams whose actual irradiation positions are close to the design grid concerned;
a first distribution coefficient calculation circuitry configured to calculate, for each of the plurality of combinations, a first distribution coefficient for each of the three beams configuring a combination concerned in the plurality of combinations, for distributing a dose to irradiate the design grid concerned to the three beams configuring the combination concerned such that a position of a gravity center of each distributed dose coincides with a position of the design grid concerned and a sum of the each distributed dose coincides with the dose to irradiate the design grid concerned, where at least one the first distribution coefficient is calculated for the each of the four or more beams;
a second distribution coefficient calculation circuitry configured to calculate, for each of the four or more beams, a second distribution coefficient of the each of the four or more beams relating to the design grid concerned by dividing a total value of the at least one the first distribution coefficient corresponding to a beam concerned in the four or more beams by a number of the plurality of combinations; and
a writing mechanism configured to write a pattern on a target object with the multiple charged particle beams in which the dose to irradiate each of the plurality of design grids has been distributed to each corresponding one of the four or more beams.

US Pat. No. 10,460,907

ELECTRON BEAM SURFACE MODIFICATION APPARATUS

Sodick Co., Ltd., Kanaga...

1. An electron beam surface modification apparatus configured to perform a surface modification of a side surface of an irradiation hole being formed on an irradiated object, and the electron beam surface modification apparatus comprising:a vacuum chamber, accommodating the irradiated object;
a cathode electrode, being surrounded by the irradiation hole, and the cathode electrode having:
a base body, facing at least the side surface of the irradiation hole; and
a plurality of metal projections over a region of an outer circumferential surface of the base body; and
a conductive mesh, being arranged at least between the cathode electrode and the side surface of the irradiation hole, the conductive mesh partially contacting the irradiated object and being set to have a same potential as the irradiated object,
wherein the conductive mesh is disposed to face an entire region of the side surface of the irradiation hole.

US Pat. No. 10,460,906

METHOD FOR MONITORING ENVIRONMENTAL STATES OF A MICROSCOPE SAMPLE WITH AN ELECTRON MICROSCOPE SAMPLE HOLDER

PROTOCHIPS, INC., Morris...

1. An electron microscope sample holder comprising:a specimen tip defining a cell; and
a fiber optic sensor assembly comprising a fiber optic cable and a sensor end carried by the fiber optic cable, the sensor end positioned in the specimen tip.

US Pat. No. 10,460,905

BACKSCATTERED ELECTRONS (BSE) IMAGING USING MULTI-BEAM TOOLS

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
a beamlet control mechanism configured to produce a plurality of beamlets utilizing electrons provided by the electron source, the beamlet control mechanism further configured to deliver one of the plurality of beamlets toward a target at a time-instance, wherein the beamlet control mechanism comprises at least one of an aperture plate, an aperture array, or one or more blanking devices; and
a detector configured to produce an image of the target at least partially based on electrons backscattered out of the target, wherein the detector is further configured to receive electrons backscattered out of the target for two or more beamlets delivered toward the target at two or more time-instances, wherein the detector is further configured to produce the image of the target at least partially based on a sum of the received backscattered electrons.

US Pat. No. 10,460,904

IMAGING DEVICE FOR IMAGING AN OBJECT AND FOR IMAGING A STRUCTURAL UNIT IN A PARTICLE BEAM APPARATUS

Carl Zeiss Microscopy Gmb...

1. A particle beam apparatus for analyzing and/or processing an object, having:at least one beam generator for generating a particle beam comprising charged primary particles;
at least one objective lens for focusing the particle beam onto the object, wherein interaction particles and/or interaction radiation arise/arises during an interaction of the particle beam with the object;
at least one detector for detecting the interaction particles and/or interaction radiation, wherein the at least one detector is sensitive to light of a first spectral range and is non-sensitive to light in a second spectral range; and
at least one imaging device for imaging the object and/or for imaging a structural unit of the particle beam apparatus, the at least one imaging device having:
at least one illumination unit with a first switching state and a second switching state for illuminating the object and/or for illuminating the structural unit with illumination light, wherein, in the first switching state, the illumination light includes only light of the first spectral range and wherein, in the second switching state, the illumination light includes only light of the second spectral range,
at least one control unit for switching the illumination unit into the first switching state or into the second switching state, wherein the control unit operates the illumination unit of the imaging device in the first switching state and switches the illumination unit into the second switching state only if the at least one detector is: (i) in operation, and (ii) in a position in which the at least one detector detects light of the first spectral range in the first switching state, and
at least one camera unit for imaging the object and/or for imaging the structural unit with light of the first spectral range in the first switching state of the illumination unit or with light of the second spectral range in the second switching state of the illumination unit.

US Pat. No. 10,460,903

METHOD AND SYSTEM FOR CHARGE CONTROL FOR IMAGING FLOATING METAL STRUCTURES ON NON-CONDUCTING SUBSTRATES

KLA-Tencor Corporation, ...

1. A scanning electron microscopy apparatus comprising:a sample stage configured to secure a sample;
an electron-optical column comprising:
an electron source configured to generate a primary electron beam; and
a set of electron-optical elements configured to direct at least a portion of the primary electron beam onto one or more electrically floating metal structures disposed above insulating material of the sample;
a detector assembly configured to detect electrons emanating from a surface of the sample; and
a controller communicatively coupled to the detector assembly, the controller including one or more processors configured to execute program instructions maintained in memory, the program instructions configured to cause the one or more processors to:
direct the electron-optical column to perform, with the primary electron beam, an alternating series of image scans and flood scans of the one or more electrically floating metal structures disposed above the insulating material of the sample, wherein the image scans are performed over a first range of landing energies and the flood scans are performed at an additional landing energy lower than the first range of landing energies of the image scans, wherein the flood scans negatively charge a surface of the one or more electrically floating metal structures via absorption of electrons of the flood scans via the surface of the one or more electrically floating metal structures, wherein the image scans positively charge the surface of the one or more electrically floating metal structures via emission of electrons of the image scans, wherein the flood scans are configured to establish a dynamic equilibrium in surface charge on the one or more electrically floating metal structures such that a charging effect in a flooding state counter-balances a charging effect in a imaging state.

US Pat. No. 10,460,902

CHARGED PARTICLE BEAM WRITING APPARATUS AND METHOD FOR DIAGNOSING FAILURE OF BLANKING CIRCUIT

NuFlare Technology, Inc.,...

1. A charged particle beam writing apparatus comprising:an emitter emitting a charged particle beam;
a blanking deflector performing blanking control of the charged particle beam by deflecting the beam in accordance with an applied blanking voltage;
a blanking circuit applying the blanking voltage to the blanking deflector;
a stage on which a substrate irradiated with the charged particle beam is placed;
a mark on the stage;
a detector detecting an irradiation position of the charged particle beam based on irradiation of the mark with the charged particle beam; and
a diagnostic electric circuitry that causes the charged particle beam to enter a predetermined defocused state relative to the mark, obtains a difference between a first irradiation position detected by the detector when the mark is scanned with the charged particle beam under first irradiation conditions and a second irradiation position detected by the detector when the mark is scanned with the charged particle beam under second irradiation conditions in which at least either of irradiation time and settling time in the first irradiation conditions is varied, and determines occurrence of a failure of the blanking circuit when the difference is a predetermined value or more.

US Pat. No. 10,460,901

COOLING SPIRAL GROOVE BEARING ASSEMBLY

General Electric Company,...

1. A bearing assembly comprising:a shell;
a shaft defining a bore therein and rotatably disposed within the shell; and
a cooling tube disposed within the bore of the shaft, the cooling tube including at least one turbulence-inducing feature.

US Pat. No. 10,460,900

X-RAY TUBE DEVICE AND X-RAY CT APPARATUS

Hitachi, Ltd., Tokyo (JP...

1. An X-ray tube device comprising:an anode that is irradiated with an electron beam, thereby emitting X-rays;
a rotary bearing that rotatably supports the anode;
a solid lubrication film which is formed on a front surface of the rotary bearing so as to be mixed with a ferromagnet; and
an attractor that attracts, with a magnetic force, the solid lubrication film that peels off the rotary bearing;
wherein the attractor contains a permanent magnet and the permanent magnet is disposed at a position having a temperature that does not exceed the Curie temperature of the permanent magnet; and
wherein the attractor contains a ferromagnet that is disposed to be in contact with the permanent magnet.

US Pat. No. 10,460,899

MODIFICATION ARRANGEMENT FOR AN X-RAY GENERATING DEVICE

KONINKLIJKE PHILIPS N.V.,...

1. A modification arrangement for an X-ray device, comprisinga cathode configured to provide an electron beam;
an anode configured to rotate under impact of the electron beam, the anode being segmented by slits arranged around a circumference of the anode;
a modification device configured to modify the electron beam when the electron beam is hitting one of the slits of the anode,
wherein the modification device is configured to deflect the electron beam tangentially forward in or backward against a direction of a rotational movement of the anode, and then backward against or forward in the direction of the rotational movement of the anode to reduce time during which the electron beam hits one of the slits.

US Pat. No. 10,460,898

CIRCUIT BREAKERS

LSIS CO., LTD., Anyang-s...

1. A circuit breaker comprising a single pole breaking unit with a pressure trip device that rotates a trip bar through an arc gas and an opening/closing mechanism unit adjusted to be in a trip state as the trip bar rotates through the pressure trip device,wherein the pressure trip device comprises:
a first case connected to the single pole breaking unit and having an arc gas discharge hole;
a barrier positioned in the front of the arc gas discharge hole and bent through an arc gas discharged through the arc gas discharge hole;
a shooter seated on the first case and configured to drive the trip bar while moving through the arc gas discharged through the arc gas discharge hole; and
a second case connected to cover the first case,
wherein the shooter comprises:
an arc gas action portion disposed above the arc gas discharge hole; and
a shooter portion configured to rotate the trip bar while moving up and down in connection to a side surface of the arc gas action portion, and
wherein the shooter portion defines a vertical line, and the arc gas discharge hole is not positioned on the vertical line defined by the shooter portion.

US Pat. No. 10,460,897

MAGNETIC TRIP DEVICE FOR CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A magnetic trip device for a circuit breaker, comprising:an actuator coil part that has a plunger configured to move to an advanced position or a retracted position according to the magnetization or demagnetization of a coil;
an output plate that is rotatably provided on the movement path of the plunger to rotate in a first direction by the pressing of the plunger;
a micro switch that has an operation lever portion protruding outwardly and is configured to output an electrical signal indicating a state of the circuit breaker according to whether or not the operation lever portion is pressed;
a switch driving lever mechanism that is configured to rotate to a first position for pressing the operation lever portion or a second position for releasing the operation lever portion so as to open or close the micro switch;
a driving lever bias spring that is provided at a predetermined position to elastically bias the switch driving lever mechanism to rotate to the second position;
an automatic reset mechanism that is configured to press the plunger of the actuator coil part to the retracted position in connection with a main switching shaft of the circuit breaker subsequent to a trip operation; and
a driving lever latch that is configured to rotate to a restraining position for preventing the switch driving lever mechanism from rotating to the first position so as to allow the micro switch to maintain a trip indicating state subsequent to a trip operation even when the plunger is moved to the retracted position by the automatic reset mechanism, and a release position for allowing the switch driving lever mechanism to rotate to the first position, and the driving lever latch is provided adjacent to the switch driving lever mechanism.

US Pat. No. 10,460,896

RELAY CONTROL DEVICE

AutoNetworks Technologies...

1. A relay control device that controls switching between a conductive state and a cut-off state of an electromagnetic relay by energizing a coil, comprising:a voltage-drop DC/DC converter unit for dropping a voltage supplied from a power supply and outputting the dropped voltage to the coil;
a control unit for outputting a control signal for modulating a pulse frequency to control an operation of the voltage-drop DC/DC converter unit;
a filter unit for allowing passage of the control signal output by the control unit that has a predetermined frequency; and
a circuit unit for controlling the operation of the voltage-drop DC/DC converter unit in accordance with a signal output by the filter unit, the circuit unit being provided between the filter unit and the voltage-drop DC/DC converter unit,
wherein, if the filter unit does not allow passage of the control signal, the circuit unit performs control so that the voltage-drop DC/DC converter unit outputs the voltage supplied from the power supply without dropping the voltage, and cuts off a current path from the power supply to a ground potential within the circuit.

US Pat. No. 10,460,895

SAFETY SWITCHING DEVICE FOR FAIL-SAFELY DISCONNECTING AN ELECTRICAL LOAD

1. A safety switching device for fail-safely disconnecting an electrical load, comprising:an input part for receiving at least one safety-relevant input signal,
a logic part connected to the input part for processing the at least one safety-relevant input signal, and
an output part which comprises a relay coil and a first relay contact, a second relay contact, a third relay contact, and a fourth relay contact,
wherein the first and the second relay contacts are arranged electrically in series with one another,
wherein the third and the fourth relay contacts are arranged electrically in series with one another,
wherein the first and the third relay contacts are mechanically coupled to each other so as to form a first group of positively driven relay contacts,
wherein the second and the fourth relay contacts are mechanically coupled to each other so as to form a second group of positively driven relay contacts,
wherein the first and the third relay contacts can move mechanically separately from the second and the fourth relay contacts,
wherein the logic part is connected to the output part and redundantly controls the first group of positively driven relay contacts and the second group of positively driven relay contacts in order to selectively allow, or to interrupt in a fail-safe manner, a current flow to the electrical load, in response to the at least one safety-relevant input signal, and
wherein the relay coil comprises a single relay coil that is electromagnetically coupled to the first group and to the second group of positively driven relay contacts so that the logic part can control the first relay contact, the second relay contact, the third relay contact, and the fourth relay contact together via the single relay coil.

US Pat. No. 10,460,894

GAS CIRCUIT BREAKER

MITSUBISHI ELECTRIC CORPO...

1. A gas circuit breaker comprising:a first tank filled with an insulating gas;
a fixed contact provided inside the first tank;
a movable contact provided inside the first tank and movable between a position in contact with the fixed contact and a position separated from the fixed contact;
a nozzle that ejects the insulating gas toward the fixed contact when the movable contact moves in a first direction, the first direction being a direction in which the movable contact moves from the position in contact with the fixed contact to the position separated from the fixed contact;
a cylindrical body, provided inside the first tank, that guides the gas ejected from the nozzle in a second direction, the second direction being a direction opposite to the first direction; and
a second tank connected to the first tank in the second direction, wherein
the second tank has a cylindrical shape centering on an axis extending in a direction perpendicular to the first direction as a central axis,
the first tank includes an opening formed on one end side thereof along an axis extending in the first direction, said opening being separated from the cylindrical body, and
the insulating gas elected from the nozzle is elected in the first tank and flows into the second tank via the opening.

US Pat. No. 10,460,893

EMBEDDED POLE PART FOR MEDIUM OR HIGH VOLTAGE USE, WITH A VACUUM INTERRUPTER WHICH IS EMBEDDED INTO AN INSULATING RESIN

ABB SCHWEIZ AG, Baden (C...

1. An embedded pole part for medium or high voltage use, the part comprising:a vacuum interrupter which is embedded into an insulating resin;
a current and/or voltage sensor including a sensor housing, integrated inside the insulating resin, arranged rotationally symmetrically around a conductor of the pole part, the sensor housing having an outer circumference;
a metal grid, implemented into the insulating resin and around the outer circumference of the sensor housing.

US Pat. No. 10,460,892

SINGULATED KEYBOARD ASSEMBLIES AND METHODS FOR ASSEMBLING A KEYBOARD

APPLE INC., Cupertino, C...

1. A keyboard assembly, comprising:a feature plate;
a key assembly including a key mechanism and a keycap, the key mechanism being coupled to the keycap and facilitating translation of the keycap in response to a user input, the key mechanism defining an opening and including a protrusion extending into the opening;
a chassis affixed to the feature plate, the chassis comprising a key assembly retaining feature, the protrusion of the key mechanism being coupled to the key assembly retaining feature.

US Pat. No. 10,460,891

KEYBOARD DEVICE AND ELECTRONIC APPARATUS

NEC PERSONAL COMPUTERS, L...

1. A keyboard device comprising:a first sheet-like member;
a membrane sheet disposed on an upper surface of the first sheet-like member;
a second sheet-like member disposed on an upper surface of the membrane sheet and supports the membrane sheet between the first sheet-like member and the second sheet-like member while being movable in an in-plane direction;
a connection member connecting the first sheet-like member and the second sheet-like member;
a plurality of key tops vertically movable and supported by a guide mechanism on an upper surface side of the second sheet-like member and brings the membrane sheet into contact with the second sheet-like member or separates the contact from the second sheet-like member;
a frame member partitioning adjacent key tops and having a lower surface to which the upper surface of the second sheet-like member is bonded and fixed; and
a support between the first sheet-like member and the second sheet-like member and regulates an interval between the first sheet-like member and the second sheet-like member to a dimension larger than a plate thickness of the membrane sheet.

US Pat. No. 10,460,890

MULTI-POLE DOME SWITCH

1. A multi-pole dome switch configured to be positioned on a printed circuit board having a first circuit and a second circuit, the multi-pole dome switch comprising:a conductive dome configured to make conductive contact with a first trace and a second trace of the first circuit when depressed, the conductive dome comprises a centrally located opening that extends therethrough;
a conductive insert, the conductive insert comprises a downwardly extending feature having a contact portion, the downwardly extending feature of the conductive insert is configured to extend through the centrally located opening of the conductive dome and position the contact portion thereof to conductively connect a first trace and a second trace of the second circuit when the conductive dome is depressed; and
an insulator positioned between the conductive dome and the conductive insert, the insulator is configured to prevent contact between the conductive dome and the conductive insert.

US Pat. No. 10,460,889

LOCKOUT DEVICE

1. A lockout device comprising a first unit and a second unit; the first unit comprising a hook portion, a middle portion, and a lock portion; said middle portion located between and directly connected to the hook portion and the lock portion; and the second unit comprising a support means and a locking means; the support means connected to the locking means; the locking means disposed substantially parallel to the middle portion of the first unit; a forward element of the locking means being substantially linear; and the locking means closing with the hook portion placing the lockout device in a locked position by holding together a lever lock point of an on/off switch lever and a stub lock point of an off stub of an electrical disconnect box.

US Pat. No. 10,460,888

DEFEATER ASSEMBLY

1. A cable operated mechanical defeater, said cable operated mechanical defeater comprising in combination:A. a rod assembly, said rod assembly comprising:
a. a first rod guide, said rod guide comprising a first flat plate having a first edge, said first edge containing a top perpendicular tab with a centered opening, a middle perpendicular tab with a centered opening, and a bottom perpendicular tab with a centered opening;
b. a top rod, said top rod comprising a first L-shape, with a foot of said first L-shape perpendicular to said first flat plate said top rod having a top end and a bottom end;
c. a top extension spring, said top extension spring being attached by a first end to said top of said top rod, an opposite end of said top extension spring being releasably attached to said top perpendicular tab;
d. a bottom extension spring, said bottom extension spring being attached to said bottom of said top rod by a first end and said bottom extension spring being attached to a cable at a second end, a first end of said cable being attached to a top arm of a cam lever assembly;
B. said cam lever assembly comprising
a. a base mounting bracket comprising a second L-shaped flat plate having a first edge and a second edge, said first edge having two openings therethrough for insertion of machine screws and said second edge having a middle slot therein;
b. an adjustable mounting bracket comprising a moveable first flat plate, said first flat plate mounted on said base mounting bracket by bolts, said base mounting bracket having a top edge and a bottom edge, a first side edge and a second side edge, said adjustable mounting bracket having two perpendicular tabs at said first side edge, and at least two slotted openings in said second side edge, a stop plate centered in said first flat plate, and a mounting post projecting perpendicular to said adjustable mounting bracket, near said second side edge;
c. rotatably mounted on said mounting post, a cam lever, said cam lever having a first end and a second end, there being a pivot arm rotatably mounted on said second end, said cam lever first end having a defeater striker integrally mounted thereon;
C. an adjustable hook, said adjustable hook having
a. an adjustable hook mounting bracket, said adjustable hook mounting bracket being a third L-shaped flat plate having a first panel and a second panel, said first panel having at least two separated, elongated slots near a top edge and near a bottom edge, and said adjustable hook mounting bracket having an elongated slot near an edge of said second panel,
b. a disconnect hook, said disconnect hook being mounted on the L of said second L-shaped plate;
c. a defeater, said defeater attachable to a latch of a disconnect operating handle.

US Pat. No. 10,460,887

SYSTEM AND METHOD FOR PROVIDING FUNCTIONAL SAFETY MONITORING OF RELAY CONTACTS

1. A system for providing functional safety monitoring of relay contacts comprising:a contactless sensor circuit that includes:
an output signal antenna positioned in the contactless sensor circuit to extend between at least two contacts of a relay; and
first and second input signal antennas positioned in the contactless sensor circuit respectively adjacent the at least two contacts of the relay, such that the output signal antenna and the at least two contacts of the relay are positioned between the first and second input signal antennas; and
a processor configured to cause the output signal antenna to output a wireless signal capable of being received by the first and second input signal antennas while the processor monitors wireless signals received by the first and second input signals antennas, wherein the processor is configured to determine that the relay has a fault based on the wireless signals received by the first and second input signal antennas, and responsive thereto output at least one communication indicative of a fault with the relay being detected.

US Pat. No. 10,460,886

SINGLE PHASE UNDERGROUND FUSED TAP

1. An apparatus comprising:a first insulated interface covering a first conductive probe tip comprising a first metal conductor casing having a threaded first probe end, the first insulated interface having a first molded rubber sleeve end;
a second insulated interface covering a second conductive probe tip comprising a second metal conductor casing having a threaded second probe end, the second insulated interface having a second molded rubber sleeve end;
a fuse having a first conductive end and a second conductive end;
the first conductive end and the second conductive end comprising threaded terminals;
the first conductive end of the fuse connecting to the first conductive probe tip;
the second conductive end of the fuse connecting to the second conductive probe tip;
the second molded rubber sleeve end inserted into the first molded rubber sleeve end;
the threaded first probe end configured to electrically connect to the first conductive end by screwing into the threaded terminal of the first conductive end; and
the threaded second probe end configured to electrically connect to the second conductive end by screwing into the threaded terminal of the second conductive end.

US Pat. No. 10,460,885

ELECTRICAL SYSTEM, AND ELECTRICAL SWITCHING APPARATUS AND GUARD MEMBER THEREFOR

EATON INTELLIGENT POWER L...

1. A guard member for an electrical switching apparatus of an electrical system, said electrical system comprising at least one electrical conductor, said electrical switching apparatus being structured to move from a CLOSED position to an OPEN position in response to a trip condition, said electrical switching apparatus comprising at least one terminal end coupled to said at least one electrical conductor, said guard member comprising:a body comprising:
a receiving portion comprising a first wall portion and a tubular portion extending outwardly from said first wall portion, said tubular portion being structured to receive said at least one electrical conductor, and
a second wall portion extending from said first wall portion and being structured to be coupled to said at least one terminal end,
wherein said second wall portion has a plurality of thru holes in order to dissipate heat generated by said electrical switching apparatus moving from the CLOSED position to the OPEN position.

US Pat. No. 10,460,884

SWITCHING ARRANGEMENT FOR A CONTROL TRANSFORMER, IN PARTICULAR POLARITY SWITCHING MEANS

MASCHINENFABRIK REINHAUSE...

1. A polarity switch for a control transformer comprising a first winding for a phase to be regulated, of an alternating current mains, the polarity switch comprising:a first connection terminal connectable with the winding;
a second connection terminal connectable with a diverter;
a vacuum interrupter having a fixed contact and a movable contact;
an isolator having a stationary switching-on contact and an electrically conductive movable bearing housing selectably engageable with and disengageable from the switching-on contact;
a resistor connected in a series circuit with the vacuum interrupter and the isolator, the first connection terminal being connected with the second connection terminal by the series circuit;
a rotatable polarity rotor carrying the bearing housing and rotatable to actuate the isolator and the vacuum interrupter, the polarity rotor having a lower support plate carrying the fixed contact and an upper support plate mechanically connected to the movable contact, the vacuum interrupter being mounted vertically between the plates; and
a vertical drive shaft between the support plates for rotating the polarity rotor.

US Pat. No. 10,460,883

MULTILAYER ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

Samsung Electro-Mechanics...

1. A multilayer electronic component comprising:a ceramic body comprising stacked dielectric layers, each layer extending in a first direction and a second direction orthogonal to the first direction, stacked in a third direction orthogonal to the first direction and the second direction, to form a first capacitor part stacked in the third direction on a second capacitor part, wherein a buffer layer separates the first capacitor part from the second capacitor part;
a voltage control terminal formed on a lateral surface on a first end of the ceramic body in the first direction;
an input terminal disposed on another lateral surface on an opposite end of the ceramic body in the first direction, and corresponding to the first capacitor part; and
an output terminal disposed on the other lateral surface on the opposite end of the ceramic body, corresponding to the second capacitor part, and separated from the input terminal in the third direction by a thickness of the buffer layer,
wherein the first capacitor part comprises first and second internal electrodes disposed on the dielectric layers, the first internal electrodes are electrically connected to the voltage control terminal, and the second internal electrodes are electrically connected to the input terminal,
wherein the second capacitor part comprises third and fourth internal electrodes disposed on the dielectric layers, the third internal electrodes are electrically connected to the voltage control terminal, and the fourth internal electrodes are electrically connected to the output terminal, and
wherein the first and second internal electrodes have constant capacitance, and the third and fourth internal electrodes have variable capacitance.

US Pat. No. 10,460,881

FLEXIBLE AND CONDUCTIVE WASTE TIRE-DERIVED CARBON/POLYMER COMPOSITE PAPER AS PSEUDOCAPACITIVE ELECTRODE

UT-Battelle, LLC, Oak Ri...

1. An electrode comprising a tire-derived carbon composite comprising carbon black embedded in sulfonated rubber-derived carbon matrix comprising graphitized interface portions and being activated, and coated with a redox-active polymer to provide a redox-active polymer coated, activated tire-derived carbon composite.

US Pat. No. 10,460,880

CAPACITORS HAVING ENGINEERED ELECTRODES WITH VERY HIGH ENERGY DENSITY AND ASSOCIATED METHOD

GranBlueTech, L.L.C., Bu...

1. An apparatus comprising:a capacitor that includes:
an anode; and
a cathode,
wherein the cathode has a surface facing the anode that is covered by a first dielectric film having a dielectric constant of at least ten,
wherein the anode has a surface facing the cathode that includes a refractory material,
wherein the cathode is formed by a process that includes photolithography,
wherein the capacitor maintains a vacuum in a region that separates the surface of the anode that includes a refractory material and the first dielectric coating on the cathode, and
wherein the cathode surface maintains an operational emission current of less than one ampere per square meter.

US Pat. No. 10,460,879

PHOTOELECTRIC CONVERSION ELEMENT, DYE-SENSITIZED SOLAR CELL, METAL COMPLEX DYE, DYE SOLUTION, DYE-ADSORBED ELECTRODE, AND METHOD FOR PRODUCING DYE-SENSITIZED SOLAR CELL

FUJIFILM Corporation, To...

1. A photoelectric conversion element, comprising an electrically conductive support, a photoconductor layer containing an electrolyte, a charge transfer layer containing an electrolyte, and a counter electrode, wherein the photoconductor layer contains semiconductor fine particles carrying a metal complex dye represented by the following Formula (I):M(LA)(LD)(LX)mX·(CI)mY  formula (I)
wherein, in the formula, M represents a metal ion,
LA represents a tridentate ligand represented by the following Formula (AL),
LD represents a bidentate ligand or a tridentate ligand different from LA, in which, at least one of coordinating atoms which bond to the metal ion M in the bidentate ligand or the tridentate ligand is an anion,
LX represents a monodentate ligand; mX is 1 when LD is the bidentate ligand and mX is 0 when LD is the tridentate ligand;
CI represents a counter ion necessary for neutralizing an electric charge;
mY represents an integer of 0 to 3;

wherein, in the formula, the ring A, the ring B, and the ring C each independently represent a nitrogen-containing aromatic heterocyclic ring, herein, the bond between Z1 and the N atom and the bond between Z2 and the N atom may be a single bond or a double bond; Z1 and Z2 each independently represent a carbon atom or a nitrogen atom;
Anc1 to Anc3 each independently represent an acidic group; l1 and l3 each independently are an integer of 1 to 4, and l2 is an integer of 1 to 5, respectively;
X1 and X3 each independently represent a single bond or a linking group; each combinations of X1 and the ring A, and X3 and the ring C may bond to each other to form a fused ring; m1 and m3 each independently represent an integer of 0 to 4, and m2 represents an integer of 1 to 3;
X2 represents the following Formula (X-1):

wherein, in Formula (X-1), RX1 and RX2 are both a hydrogen atom; * represents a bonding position with the ring B, and ** represents a bonding position with Anc2;
R1 to R3 each independently represent a substituent that does not have any of Anc1 to Anc3; n1 and n2 each independently represent an integer of 0 to 3, and n3 represents an integer of 0 to 4; when a plurality of R1s, a plurality of R2s, or a plurality of R3 exist, each of these may bond with each other to form a ring.

US Pat. No. 10,460,878

MULTILAYER CAPACITOR

Palo Alto Research Center...

1. A capacitor device, comprising:a plurality of capacitors arranged into a shape, each capacitor of the plurality of capacitors having a first external electrode on a first side of the capacitor and a second external electrode on a second side of the capacitor opposing the first side;
a first plate proximate and electrically coupled to the first external electrodes of the capacitors; and
a second plate proximate and electrically coupled to the second external electrodes of the capacitors, each of the first plate and the second plate comprising:
a substrate comprising one of a semiconducting material and an insulating material, the substrate having a first side facing towards the first and second external electrodes and a second side facing away from the first and second external electrodes; and
a metal layer disposed on the first side of the substrate.

US Pat. No. 10,460,877

THIN-FILM CAPACITOR INCLUDING GROOVE PORTIONS

TDK CORPORATION, Tokyo (...

1. A thin-film capacitor comprising:a laminate having a laminated structure including a first electrode layer and a second electrode layer laminated between one end surface side of the laminate and another end surface side of the laminate along a lamination direction, and a dielectric layer interposed between the first electrode layer and the second electrode layer in the lamination direction;
a first groove portion and a second groove portion provided on the one end surface side of the laminate and each extending in the laminating direction, the first groove portion and the second groove portion each having a width in a separation direction that is perpendicular to the lamination direction and that is along a direction in which the first groove portion and the second groove portion are separated from each other, each of the width of the first groove portion and the width of the second groove portion being narrowed from the one end surface side to the other end surface side of the laminate; and
a pair of extraction electrodes configured to cross the first groove portion and the second groove portion, respectively, and provided along two side surfaces of each of the first groove portion and second groove portion, the two side surfaces of the first groove portion facing each other in the separation direction, the two side surfaces of the second groove portion facing each other in the separation direction, each of the first electrode layer and the second electrode layer extending over both sides of the first groove portion and both sides of the second groove portion and having portions exposed on both side surfaces of the first groove portion and on both side surfaces of the second groove portion,
wherein a first extraction electrode provided in the first groove portion among the pair of extraction electrodes is in contact with the first electrode layer exposed on the side surface of the first groove portion and is not in contact with the second electrode layer, and
wherein a second extraction electrode provided in the second groove portion among the pair of extraction electrodes is in contact with the second electrode layer exposed on the side surface of the second groove portion and is not in contact with the first electrode layer.

US Pat. No. 10,460,876

MULTI-LAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic capacitor, comprising:a body including
a multi-layer unit including
ceramic layers laminated in a first direction,
a first internal electrode and a second internal electrode that are alternately disposed between the ceramic layers,
an end surface that is oriented in a second direction orthogonal to the first direction, the first internal electrode being drawn from the end surface,
an end margin that is disposed between the end surface and the second internal electrode, and
a side surface that is oriented in a third direction orthogonal to the first direction and the second direction, the first internal electrode and the second internal electrode being exposed to the side surface, and
a side margin that covers the side surface of the multi-layer unit; and
an external electrode that includes an entry portion and covers the body from a side of the end surface,
the entry portion being disposed on the end margin,
the entry portion entering a gap, between the side surface and the side margin, from the end surface,
the entry portion projecting outward from the side surface towards the side margin,
the entry portion being in direct physical contact with the side surface, and
the side surface being absent in the side margin.

US Pat. No. 10,460,875

MULTILAYER ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising: a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with dielectric layers interposed therebetween having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first, second, third, and fourth surfaces, and opposing each other, wherein one end of each of the first and second internal electrodes is exposed through the third and fourth surfaces, respectively; first and second external electrodes including, respectively, first and second connected portions respectively disposed on the third and fourth surfaces of the capacitor body and first and second band portions respectively extended from the first and second connected portions to portions of the first surface of the capacitor body; a first connection terminal disposed on the first band portion to be spaced apart from the first connected portion so that a first space portion, open in directions corresponding to the third surface, the fifth surface, and the sixth surface of the capacitor body is provided on a lower surface of the first band portion; and a second connection terminal disposed on the second band portion to be spaced apart from the second connected portion so that a second space portion, open in directions corresponding to the fourth surface, the fifth surface, and the sixth surface of the capacitor body is provided on a lower surface of the second band portion, wherein BW/4?G?3BW/4 in which BW is a width of the first or second band portion of the first or second external electrode, and G is a length of the first or second space portion.

US Pat. No. 10,460,874

ELECTRONIC COMPONENT WITH METAL TERMINALS

TAIYO YUDEN CO., LTD., T...

1. An electronic component with metal terminals, constituted by an electronic component on which metal terminals are provided, wherein:the electronic component has a component body of roughly rectangular solid shape that contains internal conductors, and external electrodes provided on opposing ends of the component body, respectively;
each of the metal terminals has a first planar part and a second planar part oriented differently from the first planar part;
the first planar part of the metal terminal is connected to one of the external electrodes via a conductive bonding material provided in between in a manner facing one face of the component body; and
the second planar part of the metal terminal is positioned in a manner facing at least partially, across a clearance in closest proximity, another face adjoining the one face of the component body, while being fixed to the component body by an adhesive provided in the clearance,
wherein the metal terminal is provided only on the one face and the another face of the component body, among all of the faces of the component body, and
the adhesive and the conductive bonding material are constituted by different materials, and a thickness of the adhesive is greater than a thickness of the conductive bonding material.

US Pat. No. 10,460,873

ENHANCING DIELECTRIC CONSTANTS OF ELASTOMER SHEETS

Facebook Technologies, LL...

1. A method comprising:receiving an uncured elastomer;
depositing dielectric ceramic particulates having a value of a dielectric constant satisfying one or more conditions onto the uncured elastomer;
receiving an additional uncured elastomer;
layering the additional uncured elastomer onto the dielectric ceramic particulates deposited onto the uncured elastomer;
depositing additional dielectric ceramic particulates having an additional value of an additional dielectric constant satisfying the one or more conditions;
curing the uncured elastomer and the additional uncured elastomer for an interval of time and at a specified temperature within a mold having an anode and a cathode; and
for at least a portion of the interval of time during the curing while a temperature within the mold is within a threshold amount of a Curie temperature of the dielectric ceramic particulates or of the additional dielectric ceramic particulates, applying an electric field by applying a voltage to the anode and to the cathode of the mold including the uncured elastomer and the additional uncured elastomer such that a cured elastomer and the uncured elastomer have different dielectric constants.

US Pat. No. 10,460,872

ELECTRONIC DEVICE

Panasonic Intellectual Pr...

1. An electronic device comprising:a case;
a device element housed in the case; and
a filling resin with which the case is filled so as to embed the device element in the filling resin, wherein:
the device element includes a fixing portion that fixes the device element to the case,
the case has a support portion that supports the fixing portion, the support portion having an upper surface which faces a lower surface of the fixing portion,
the fixing portion and the support portion are in contact with each other at two contact portions in the lower surface of the fixing portion, the two contact portions sandwiching a lengthwise center portion of the lower surface of the fixing portion,
a non-contact region where the fixing portion and the support portion are not in contact with each other is provided between the lower surface of the fixing portion and the upper surface of the support portion, other than the two contact portions,
at least a part of the lower surface of the fixing portion is inclined with respect to a bottom surface of the case, and
the non-contact region is embedded in the filling resin.

US Pat. No. 10,460,871

METHOD FOR FABRICATING NON-PLANAR MAGNET

GM GLOBAL TECHNOLOGY OPER...

1. A method for fabricating a non-planar magnet, comprising:extruding a precursor material including neodymium iron boron crystalline grains into an original anisotropic neodymium iron boron permanent magnet having an original shape, wherein the original anisotropic neodymium iron boron permanent magnet has at least 90 percent neodymium iron boron magnetic material by volume;
heating the original anisotropic neodymium iron boron permanent magnet to a deformation temperature; and
deforming the original anisotropic neodymium iron boron permanent magnet into a reshaped anisotropic neodymium iron boron permanent magnet having a second shape substantially different from the original shape using heated tooling to apply a deformation load to the original anisotropic neodymium iron boron permanent magnet, wherein the original anisotropic neodymium iron boron permanent magnet and the reshaped anisotropic neodymium iron boron permanent magnet each have respective magnetic moments substantially aligned with a respective local surface normal corresponding to the respective magnetic moment.

US Pat. No. 10,460,870

INDUCTION COIL ASSEMBLY AND WIRELESS POWER TRANSFER SYSTEM

NINGBO WEIE ELECTRONICS T...

1. An induction coil assembly, comprising:at least one substrate, each including at least one through hole;
a first part of a wire of the induction coil assembly wound on a first surface of the substrate; and
a second part of the wire extended onto a second surface of the substrate via one of the through holes of the substrate and wound on the second surface of the substrate
wherein the wire forms an N-turn coil, locations of the windings on the first surface of the substrate and locations of the windings on the second surface of the substrate are mutually staggered with each other up and down.

US Pat. No. 10,460,869

MULTI-SERIES CONTINUOUS-FLOW MAGNETOELECTRIC COUPLING PROCESSING SYSTEM AND APPLICATIONS THEREOF

Jiangnan University, Wux...

1. A multi-series continuous-flow magnetoelectric coupling processing system, comprising:more than two stages of induction units, wherein each stage of the induction unit comprises:
a closed iron core,
a primary coil, wound around one side of the closed iron core, and
a secondary coil, wound around an opposite side of the closed iron core and arranged in an induction voltage chamber, wherein the secondary coil comprises an insulation pipe for circulation of a feed liquid, and two ends of the insulation pipe are exposed from the induction voltage chamber and respectively act as a feeding hole and a discharge hole;
a high frequency power supply, in connection with the primary coils of the more than two stages of the induction units and providing excitation voltage for each of the primary coils; and
a feed liquid container, in series connection with the insulation pipes of the more than two stages of the induction units to form a feed liquid circulation loop.

US Pat. No. 10,460,868

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a primary coil;
a secondary coil disposed concentrically around the outer periphery of the primary coil;
a center core disposed on the inner periphery of the primary coil;
an outer peripheral core surrounding the secondary coil, the outer peripheral core including a central opening;
a core cover including an inside cover part facing an inner surface of the outer peripheral core, a first end-side cover part facing a surface on one end of the outer peripheral core in a penetration direction, and a second end-side cover part facing a surface of the other end of the outer peripheral core in the penetration direction, the first end-side cover part and the second end-side cover part being connected by the inside cover part, the first end-side cover part of the core cover only including a wall portion that is on a high voltage side of the secondary coil such that the core cover does not include another wall portion elsewhere and that protrudes in the penetration direction, the core cover having a plurality of steps formed on at least one of an inner surface of the wall portion, an outer surface of the wall portion, and a surface on one end of the wall portion in the penetration direction of the core cover;
a case provided with an accommodation opening on a side on which the surface on the one end of the outer peripheral core in the penetration direction is located, the accommodation opening accommodating the primary coil, the secondary coil, the center core, the outer peripheral core, and the core cover; and
a filling resin filling gaps in the case, the filling resin being in contact with the steps.

US Pat. No. 10,460,867

UPRIGHT COMPOSITE COMMON MODE COIL ASSEMBLY

Yujing Technology Co., Lt...

1. An upright composite common mode coil assembly comprising:a coil carrier including two bobbins, a group of coils being wounded around the outer circumference of each of the bobbins; and
a seat including:
a base having a back plate on a surface thereof, hollow portions formed at an upper position and a lower position of the back plate, a wire slot provided at either side of the back plate, and an indentation extending from one end of each of the wire slots;
a bottom portion extending vertically from a side of the base closer to the indentations, a recessed portion formed at each of the corners of the bottom portion, and a pin inserted into each of the recessed portions;
a top portion extending vertically from another side of the base and including a flat top face; and
a separating portion extending from another surface of the base and being tapered to form a curved surface, and the separating portion forming a receiving slot with the top portion and another receiving slot with the bottom portion,
wherein some of the recessed portions are in communication with the indentations, while the rest of the recessed portions respectively form notches with adjacent regions of the bottom portion;
wherein one bobbin of the coil carrier is received in each of the receiving slots of the seat, and wires of a group of the coils are guided into some of the recessed portions through the wire slots and the indentations, and wires of another group of the coils are guided into the other recessed portions through the notches, so that the wires of the coils do not protrude out of the seat and are neatly soldered on the pins; and
wherein a wing portion extends from a side of each indentation, and a concaved portion is formed between each indentation and its corresponding wing portion.

US Pat. No. 10,460,866

REPLACEMENT TRANSFORMER WITH MODULAR CONSTRUCTION

Siemens Aktiengesellschaf...

1. A configuration for replacing a multiphase transformer, the configuration comprising:a plurality of single-phase transformers each including a housing filled with an insulating fluid and a core having a higher-voltage and a lower-voltage winding disposed in said housing;
at least one bushing socket connected by a winding connection lead extending within said housing to said higher-voltage or lower-voltage winding, said at least one bushing socket connected to the winding connection lead at an end adjacent to the insulating fluid;
at least one high-voltage bushing being insertable into said at least one bushing socket, said bushing socket being complementary in shape to an insertion end of the high-voltage bushings; and
a cooling module for cooling the insulating fluid, the cooling module detachably connected to said housing and being filled with the insulating fluid, said cooling module configured to hold said insulating fluid in said cooling module even when said cooling module is detached from said housing.

US Pat. No. 10,460,865

INDUCTOR ASSEMBLY

Ford Global Technologies,...

1. An inductor assembly comprising:a flat conductor;
a core having a pair of axially oriented elements, the elements including a post defining an axial aperture therethrough and more than two projections extending axially from a base, the projections being radially spaced from the post and angularly spaced apart to define openings between the projections and configured to receive and direct a splashed fluid toward the conductor disposed in a single layer over the post;
a pair of insulated bobbins, disposed between the conductor and the posts, each having radial flanges at an end configured to be received in the openings; and
a bolt extending through the aperture and fastened to a transmission.

US Pat. No. 10,460,864

MAGNETIC SUBSTANCE HOLDING DEVICE

1. A magnetic substance holding device, comprising:a first pole piece assembly comprising a first N-pole piece having a holding face and a contact face and being a magnetic substance, a first S-pole piece having a holding face and a contact face and being a magnetic substance, and a first permanent magnet having an N-pole to be in contact with the first N-pole piece and an S-pole to be in contact with the first S-pole piece;
a second pole piece assembly comprising a second N-pole piece having a holding face and a contact face and being a magnetic substance, a second S-pole piece having a holding face and a contact face and being a magnetic substance, and a second permanent magnet having an N-pole to be in contact with the second N-pole piece and an S-pole to be in contact with the second S-pole piece, wherein the contact face of the second S-pole piece faces the contact face of the first N-pole piece, and the contact face of the second N-pole piece faces the contact face of the first S-pole piece;
at least one coil wound around at least one of the first N-pole piece, the first S-pole piece, the second N-pole piece and the second S-pole piece; and
a control device controlling current applied to the at least one coil,
wherein at least one of the first pole piece assembly and the second pole piece assembly is configured to be movable so that a first arrangement in which the contact face of the first N-pole piece is separated from the contact face of the second S-pole piece and the contact face of the first S-pole piece is separated from the contact face of the second N-pole piece, and a second arrangement in which the contact face of the first N-pole piece is in contact with the contact face of the second S-pole piece and the contact face of the first S-pole piece is in contact with the contact face of the second N-pole piece, are switched between each other, and
wherein the control device adjusts current applied to the at least one coil so as to control magnetic fluxes passing through the at least one coil, thereby allowing the first pole piece assembly and the second pole piece assembly to switch between the first arrangement and the second arrangement, to control magnetic fluxes passing through the holding faces of the first pole piece assembly and the second pole piece assembly.

US Pat. No. 10,460,863

PARALLEL DIPOLE LINE TRAP WITH VARIABLE GAP AND TUNABLE TRAP POTENTIAL

International Business Ma...

1. A parallel dipole line (PDL) trap, comprising:a pair of dipole line magnets separated from one another by a variable gap g;
a diamagnetic object levitating above the dipole line magnets, wherein the gap g is less than a critical gap gc beyond which the diamagnetic object is no longer levitated, and wherein the gap g determines a height by which the diamagnetic object levitates above the dipole line magnets; and
a fixed or a variable gap fixture in which the dipole line magnets are affixed to separate mounts, wherein each of the dipole line magnets is cylindrical, wherein the mounts only partially surround a circumference of each of the dipole line magnets such that the mounts are in a non-contact position with the dipole line magnets at a center of the PDL trap in between the dipole line magnets, and wherein the mounts are affixed only to ends of each of the dipole line magnets and only partially surround the circumference of each of the dipole line magnets at the ends of each of the dipole line magnets.

US Pat. No. 10,460,862

MAGNESIUM DIBORIDE SUPERCONDUCTING THIN-FILM WIRE AND METHOD FOR PRODUCING SAME

HITACHI, LTD., Tokyo (JP...

1. A magnesium diboride superconducting thin-film wire, comprising:a long substrate;
a magnesium diboride thin film formed on the long substrate, wherein the magnesium diboride thin film includes magnesium diboride columnar crystal grains; and
a transition metal element layer formed on the magnesium diboride thin film, wherein the transition metal layer is diffused into grain boundaries of the magnesium diboride columnar crystal grains;
wherein:
the magnesium diboride thin film has a microtexture such that the magnesium diboride columnar crystal grains stand densely together on a surface of the long substrate, and
the transition metal element layer is formed from a predetermined transition metal element that has a body-centered cubic lattice structure.

US Pat. No. 10,460,861

HIGH SPEED ROTOR CONNECTION ASSEMBLY

HAMILTON SUNDSTRAND CORPO...

1. A resistor pack assembly comprising:a positive rail having a circular face;
a negative rail having an inner circular face and an outer circular face located radially outward from the inner circular face;
an insulator ring having a first circular face and a second circular face opposite the first circular face, the second circular face contacts the outer circular face of the negative rail;
a first DC bus bar electrically connected to the insulator ring;
a second DC bus bar electrically connected to the negative rail; and
a cylindrical suppression resistor having a first flat surface and a second flat surface opposite the first flat surface, the cylindrical suppression resistor is located radially inward of the insulator and axially between the positive rail and the negative rail, wherein the first flat surface contacts the circular face of the positive rail and the second flat surface contacts the inner circular face of the negative rail.

US Pat. No. 10,460,860

CONTROLLABLE ROTARY KNOB

ZULU OG, Villach (AT)

1. A controllable rotary knob which comprises at least one base, at least one drive unit rigidly connected to the base, at least one transmission, and an operating part, wherein the operating part is configured as a housing surrounding the drive unit and the transmission, wherein the transmission establishes a connection between the drive unit and the operating part, wherein the drive unit has an axially symmetric structure and can be arranged concentrically about a rotary knob shaft, and wherein the drive unit and the operating part being arranged coaxially to one another.

US Pat. No. 10,460,859

RESISTANCE STRUCTURE, RESISTANCE STRUCTURE UNIT, INFORMATION IDENTIFICATION DEVICE AND BIOSENSOR

VivaChek Biotech (Hangzho...

1. A resistance structure comprises:a first electrode;
a second electrode;
a plurality of first resistance elements, wherein one end of each of the first resistance elements is connected to the first electrode, and the other end of each of the first resistance elements is connected to the second electrode;
a first fracture in the first electrode, the first fracture dividing the first electrode into a first part and a second part, wherein the first fracture is located between two adjacent first resistance elements;
a third electrode, wherein the third electrode is connected to the first part of the first electrode;
a first contact, connecting with the second part of the first electrode;
a second contact, connecting with the second electrode; and
a third contact, connecting with the third electrode.

US Pat. No. 10,460,858

CAPS FOR POWER DISTRIBUTION SYSTEM COMPONENTS

HUBBELL INCORPORATED, Sh...

1. A power distribution system component comprising:a housing having a first end and a second end, wherein a first electrical terminal extends from the first end and a second electrical terminal extends from the second end;
a first end cap disposed at the first end of the housing, the first end cap being a substantially solid structure from a center aperture of the first end cap to an outer wall of the first end cap, the first end cap being made of a heat resistive material that softens when subject to high levels of heat but does not melt, flow or generate sparks when subject to high levels of heat for a predetermined period of time; and
a second end cap disposed at the second end of the housing.

US Pat. No. 10,460,857

SKIN BUTTON WITH FLAT CABLE

HeartWare, Inc., Miami L...

1. A method of forming a percutaneous connector assembly, comprising:assembling a plurality of conductors adjacent to each other, each of the plurality of conductors defining a length;
coupling a portion of the plurality of conductors to each other along the length to define a flat portion of a cable assembly;
rearranging a free length of each of the plurality of conductors to define a round portion of the cable assembly, the round portion being opposite the flat portion of the cable assembly;
applying a jacket over the round portion of the cable assembly;
connecting the cable assembly to a feedthrough assembly; and
coupling a skirt to a body of the feedthrough assembly, the skirt extending radially outwardly therefrom.

US Pat. No. 10,460,856

BUS MOUNTS, POWER DISTRIBUTION SYSTEMS, AND METHODS FOR MOUNTING BUSES IN POWER DISTRIBUTION SYSTEMS

SIEMENS INDUSTRY, INC., ...

1. A power distribution system, comprising:a bus bar;
a frame member;
a support block formed from a non-conductive material and having a first side and an opposite second side;
one or more first fasteners extending beyond the second side and mechanically coupled to the bus bar;
one or more second fasteners extending beyond the first side and mechanically coupled to the frame member; and
a first insulator located between the first side of the support block and the frame member, wherein the one or more first fasteners do not extend through the first insulator and the one or more second fasteners extend through the first insulator.

US Pat. No. 10,460,855

FLEXIBLE FLAT ROUND CONDUCTIVE CABLE AND SEGMENTAL CALENDERING DEVICE FOR FLEXIBLE FLAT CABLE

1. A flexible flat round cable, comprising:a plurality of cables, including:
a plurality of round regions each having a first distance with a first electrical clearance between every two neighboring cables therein; and
a plurality of flat regions each having a second distance with a second electrical clearance between every two neighboring cables, wherein the first distance and the second distance are different, and the first electrical clearance is greater than the second electrical clearance;
wherein the plurality of cables are parallelly arranged, and an insulation film is disposed on a surface of the plurality of cables; and
wherein the plurality of flat and round regions are alternately arranged in form of one by one cycle in longitudinal direction, and the plurality of flat regions are molded by a segmental calendering device through a sub rolling method.

US Pat. No. 10,460,854

SUPERCONDUCTING WIRE

Sumitomo Electric Industr...

1. A superconducting wire comprising:a multilayer stack including a substrate having a main surface, and a superconducting material layer formed on the main surface; and
a covering layer disposed on at least the superconducting material layer,
the covering layer located on the superconducting material layer having a front surface portion in a concave shape.

US Pat. No. 10,460,853

POWER CABLE AND BUS BAR WITH TRANSITIONAL CROSS SECTIONS

Flex-Cable, Howard City,...

1. A cable assembly comprising:a continuous electrical conductor formed of multi-strands of an electrically conductive material;
a first section of said continuous electrical conductor in which said multi-strands of electrical conductor material are twisted and together form a circular or oval cross section;
a third section of said continuous electrical conductor in which said multi-strands of electrical conductor material are untwisted and individually flattened and together form a square or rectangular cross section; and
a second section of said continuous electrical conductor forming a transitional area in which the cross section of said continuous electrical conductor changes from the circular or oval cross section of said first section to the square or rectangular cross section of said third section.

US Pat. No. 10,460,852

ELECTRODE HAVING NANO MESH MULTI-LAYER STRUCTURE, USING SINGLE CRYSTAL COPPER, AND MANUFACTURING METHOD THEREFOR

PUSAN NATIONAL UNIVERSITY...

1. An electrode having a multilayer nanomesh structure made of single-crystalline copper, the electrode comprising:a substrate;
a single-crystalline copper electrode layer formed directly on the substrate using high frequency sputtering or direct current sputtering, and having a hexagonal pattern with a nano-sized line width achieved using over-wet-etching, for providing stability of the electrode which is applicable to flexible electrodes/devices by improving said stability over electrodes comprising a poly-crystalline copper electrode layer, said stability including at least temperature and flexing stability of a sheet resistance of the electrode comprising the single-crystalline copper electrode layer; and
a metal oxide layer formed on the single-crystalline copper electrode layer.

US Pat. No. 10,460,850

THERMOELECTRIC COMPOSITE MATERIAL AND METHOD FOR PREPARING THERMOELECTRIC COMPOSITE MATERIAL

1. A thermoelectric composite material comprising:a functionalized graphene oxide including conductive metal nanoparticles on a surface of the functionalized graphene oxide, the functionalized graphene oxide being dispersed in a thermoelectric material.

US Pat. No. 10,460,849

LIGHTWEIGHT, HIGH-CONDUCTIVITY, HEAT-RESISTANT, AND IRON-CONTAINING ALUMINUM WIRE, AND PREPARATION PROCESS THEREOF

CENTRAL SOUTH UNIVERSITY,...

1. A lightweight, high-conductivity, heat-resistant, and iron-containing aluminum wire comprising the following components in percentage by weight:B 0.04-0.10 wt. %;
Zr 0.10-0.15 wt. %;
Fe 0.10-0.20 wt. %;
La 0.05-0.30 wt. %; and
inevitable titanium, vanadium, chromium, and manganese with a total content less than 0.01 wt. %, and aluminum as the remaining.

US Pat. No. 10,460,848

DEVICE FOR SUSPENDING AN X-RAY GRID, ARRANGEMENT WITH AN X-RAY GRID AND METHOD FOR OPERATING AN X-RAY GRID

Siemens Healthcare GmbH, ...

1. A device for suspending an x-ray grid, the device comprising:a first rotating frame configured to support the x-ray grid therein or thereon; and
two first flexible hinge elements connected to said first rotating frame and mounting said first rotating frame for reversible rotation about a first axis.

US Pat. No. 10,460,847

GRAVITY-BASED, NON-INVASIVE REACTOR SYSTEM AND METHOD FOR COOLANT INVENTORY MONITORING

Information Systems Labor...

1. A method of determining a loss or gain of fluid from a first and second concentric container module, the method comprising:mounting a first gravity meter proximate to one of a vertical side and a top of the second concentric container module, the second concentric container module being external to the first concentric container module, the first concentric container module normally containing a mass of fluid, the first gravity meter being mounted above the mass of fluid normally contained in the first concentric container module, the first gravity meter for measuring a first time series of gravity signals, the first time series of gravity signals measuring a change in null of the mass of fluid normally contained in the first concentric container module,
mounting a second gravity meter proximate to one of the vertical side and at the bottom of the second concentric container module, the second gravity meter mounted below the mass of fluid normally contained by the first concentric container module, the second gravity meter for measuring a second time series of gravity signals comprising a different change in pull of the mass of fluid normally contained in the first concentric container module responsive to a vertical distance between the first and second gravity meters,
determining by a computer processor a change in gravimetric pull of the mass of fluid normally contained by the first concentric container module, the change in gravitational pull of the mass of fluid comprising:
subtracting the second timer series of gravity signals from the first time series of gravity signals; result of the subtraction representing excludable changes in pull of the mass of fluid normally contained in the first concentric module measured over time due to expected changes in at least one of tides, atmosphere, a value of drift of one of the first gravity meter and the second gravity meter and groundwater levels, the subtraction eliminating noise effects of recurring events comprising at least one of the changes in tides, changes in atmosphere, changes in drift of one of the first gravity meter and the second gravity meter and changes in groundwater levels,
calculating, responsive to the subtraction, a first center of mass of the fluid in a combination of the first and second concentric container modules at a first point in time via the gravity signals output by the first and second gravity meters and calculating a second center of mass of the fluid in the first and second concentric container modules at a second point in time later in time than the first point in time,
responsive to a difference between calculations of the first center of mass and the later in time second center of mass, evaluating, responsive to the subtractions, the gravity signals over time measured by the first and second gravity meters to determine an occurrence of one of a leak from the first concentric container module to the second concentric container module and a leak to outside the second concentric container module via a value or center of mass over time falling below one or another of first and second predetermined values.

US Pat. No. 10,460,846

EXAMINATION AND TEST SYSTEM FOR NUCLEAR-GRADE CONTROL VALVE

Institute of Nuclear Ener...

1. An examination and test system for nuclear-grade control valve, used for examining and testing a control valve, said control valve comprising a valve base, a valve rod, and a driving unit, said valve base including a communicating opening therein, said valve rod including a valve plug capable of closing said communication opening, said valve rod being movable by said driving unit, said valve plug blocking said communicating opening and forming openness of various degrees according to the traveling distance of said valve rod, the examination and test system comprising:a hermetic first chamber, including a second chamber with controllable ambient conditions including at least one of temperature, pressure and humidity, and said second chamber used for accommodating said control valve;
a base, disposed outside said hermetic first chamber;
a guide unit, disposed on at least one of said control valve and said base;
a winder, disposed on said base;
a steel cable, connected with said valve rod at one end and extending out of said hermetic first chamber to connect with said winder at the other end, wound on said guide unit, wound up by said winder, and rendered taut at any time; and
a length measurement device, disposed on said base, and including a body and a measurement element, said measurement element movable with respect to said body and coupled to said steel cable, and said length measurement device displaying the displacement of said measurement element relative to said body.

US Pat. No. 10,460,844

SMALL NUCLEAR REACTOR CONTAINMENT SYSTEM

Westinghouse Electric Com...

1. A nuclear reactor containment system comprising:a nuclear reactor;
a container enclosing the nuclear reactor, the container including:
at least one heat removal system having an active state and an inactive state, wherein the at least one heat removal system dissipates heat from the container more efficiently in the active state than in the inactive state, and wherein the at least one heat removal system is structured to switch from the inactive state to the active state based on a temperature of the container,
wherein the at least one heat removal system includes a first heat removal system including:
fins disposed in an outer portion of the container and forming a plurality of cooling channels; and
a plurality of air regulating mechanisms structured to block air from flowing through the cooling channels when the first heat removal system is in the inactive state and to allow air to flow through the cooling channels when the first heat removal system is in the active state,
wherein at least one of the air regulating mechanisms includes:
a first plate structured to be disposed over a first cooling channel of the plurality of cooling channels to block airflow through the first cooling channel;
a pivot structured to support a first side of the first plate;
an electromagnetic element structured to support a second side of the first plate via an electromagnetic force and being structured to support the second side of the first plate via the electromagnetic force at a predetermined temperature,
wherein when the first heat removal system is in the inactive state, the electromagnetic element supports the second side of the first plate and the first plate blocks airflow through the first cooling channel, and
wherein when the first heat removal system is in the active state, the electromagnetic element melts and allows the second side of the plate to fall into the first cooling channel and allow airflow through the first cooling channel.

US Pat. No. 10,460,843

PROBABILISTIC PARAMETER ESTIMATION USING FUSED DATA APPARATUS AND METHOD OF USE THEREOF

1. A method for estimating state of a biomedical system, comprising the steps of: providing a cardiac stroke volume analyzer, said cardiac stroke volume analyzer comprising a system processor, said cardiac stroke volume analyzer further comprising: a probabilistic processor; and a dynamic state-space model; connecting said system processor to: (1) an auxiliary blood pressure cuff medical device and (2) an auxiliary pulse oximeter medical device; said cardiac stroke volume analyzer receiving discrete first cardiovascular input data, from said auxiliary blood pressure cuff medical device, related to a first sub-system of the biomedical system; said cardiac stroke volume analyzer receiving discrete second cardiovascular input data, from said auxiliary pulse oximeter medical device, related to a second sub-system of the biomedical system, fusing the first input data and the second input data into fused data using said system processor, said step of fusing comprising the step of said probabilistic processor converting the fused data into a probability distribution function indirectly related to an output of either of the blood pressure cuff and the pulse oximeter medical device; at least one probabilistic model, of said dynamic state-space model, operating on said probability distribution function, iteratively circulating said probability distribution function in said dynamic state-space model in synchronization with receipt of at least one of: updated first cardiovascular input data from said auxiliary blood pressure cuff medical device; and updated second cardiovascular input data from said pulse oximeter medical device; and said system processor processing the probability distribution function to generate an output related to the state of the biomedical system, said output comprising a left ventricle stroke volume of a heart of a patient and arterial compliance of the patient, said output displayed to at least one of a patient and a doctor.

US Pat. No. 10,460,842

INTERACTIVE AND ANALYTICAL SYSTEM THAT PROVIDES A DYNAMIC TOOL FOR THERAPIES TO PREVENT AND CURE DEMENTIA-RELATED DISEASES

UMETHOD HEALTH, INC., Ra...

1. A method for providing a therapy to a patient to improve cognitive health of the patient, the method comprising:using at least one processor and at least one memory for:
receiving patient information including two or more of personal and family background data, pre-existing conditions, current medications, genomic data, and diagnostic information, the diagnostic information relating to biological mechanisms that define dementia-related diseases as a medical condition or risk of dementia-related diseases;
receiving therapy plan information, the therapy plan information comprising a plurality of individual therapy plans, each individual therapy plan specifying an individual biological mechanism targeted for physiological adjustment, variations found in an effect on the targeted biological mechanism as a function of the patient information, and data quantifying a probability of success of the individual therapy plan;
generating an aggregate therapy plan, the aggregate therapy plan targeting adjustment of a plurality of biological mechanisms using a combination of the individual therapy plans, the aggregate therapy plan comprising an aggregate probability reflecting a likelihood of achieving all targeted adjustments;
receiving diagnostic and testing data associated with the patient, the diagnostic and testing data captured after the patient has undergone treatment according to the aggregate therapy plan;
for each individual therapy plan in the aggregate therapy plan:
determining a value corresponding to the individual biological mechanism in the patient based on the received diagnostic and testing data;
performing a comparison of the value to a recommended range for the value, and
based on the comparison, dynamically adjusting the individual therapy plan for the biological mechanism when the value is within the recommended range; and
generating, for the patient, an adjusted aggregate therapy based on the individual therapy plan adjustments;
administering the adjusted aggregate therapy via communicable links to a mobile device of a therapy provider, wherein the adjusted aggregate therapy enables improvement in the cognitive health of the patient; and
adjusting the therapy plan information based on success of the individual therapy plans of the patient and of other patients;
and
further administering the adjusted aggregate therapy by the therapy provider.

US Pat. No. 10,460,841

INDIVIDUAL HEALTH RECORD SYSTEM AND APPARATUS

CentrifyHealth, LLC, Nas...

1. A computer-implemented method for processing, storing and handling health care information, comprising the steps of:receiving, in a self-contained, plug-and-play appliance device adapted to be incorporated into an existing network or information technology system, data or information relating to a patient's or individual's health from one or more information sources, said data comprising data in any form;
parsing some or all of the received data or information to identify elements of the data or information;
transforming or normalizing some or all of the received data or information, and some or all of the parsed data elements, to created transformed or normalized data elements;
assigning a confidence indicator or weight to the transformed or normalized data elements, wherein said confidence indicator is a value in a non-binary range;
mapping the transformed or normalized data elements in accordance with an ontology;
obtaining a first set of matching criteria rules that identify whether the transformed or data elements sufficiently match an existing health care object as a function of one or more person or entity criteria;
automatically determining whether to create a new health care object or modify an existing health care object based on the outcome of application of the first set of matching criteria rules;
automatically modifying an existing health care object or creating anew health care object from said transformed or normalized data elements based on the outcome of said determination step, wherein said existing or new health care object is an object-oriented software environment object subject to an object hierarchy;
automatically obtaining and applying a second set of rules specifying time-dependent criteria for scheduling healthcare events every time said new health care object is created or said existing health care object is modified; and
storing the mapped data elements in a data store in accordance with a health information model, wherein said health information model associates the patient or individual with a patient or individual record, said record comprising:
identification information for one or more third parties associated with providing healthcare for the patient or individual;
health condition and health service information for the patient or individual, including timeline information;
medication information for the patient or individual;
lifestyle information for the patient or individual;
health treatment, monitoring and encounter information for the patient or individual; and
medical findings and measure data for the patient or individual.

US Pat. No. 10,460,840

DIAGNOSTICS-BASED HUMAN HEALTH EVALUATION

JIANGSU HUABEN HEALTH LIF...

1. A method of evaluating a health condition of a patient based on a diagnostic aspect of the patient, comprising:obtaining, by a diagnostics measurement device, a measurement value of the diagnostic aspect of the patient;
calculating, by a processor communicatively coupled to the diagnostics measurement device, a relative ratio by dividing the measurement value by a standard average value of the diagnostic aspect;
calculating, by the processor, a health deviation by subtracting a baseline value from the relative ratio; and
designating, by the processor, a health indicator based on the health deviation, the health indicator indicating the health condition of the patient,
wherein:
the diagnostics measurement device comprises a blood test device,
the measurement value is a result of a blood test performed by the blood test device on the patient,
the standard average value comprises an arithmetic mean of a standard upper limit and a standard lower limit that are medically defined for the diagnostic aspect,
the baseline value comprises an arithmetic sum of a medium value, a variation upper limit, a variation lower limit, and a tier size, and
the health indicator is a rounded integer of a ratio of the health deviation to the tier size.

US Pat. No. 10,460,839

DATA MINING OF DENTAL IMAGES

1. A system for providing data mining of a dental image, the system comprising:an aggregator server, wherein the aggregator server is configured to:
receive a dental image of a patient from a dental image provider, wherein the dental image provider is an e-commerce service;
process the dental image with a machine learning (ML) anatomy dataset;
match and identify an anatomy from the ML anatomy dataset to the dental image;
match and identify the dental image with a ML pathology and treatment dataset;
match a pathology and a treatment from the machine leaning pathology and treatment dataset to the dental image;
insert the dental image and the anatomy, the pathology, and the treatment associated with the dental image to a patient dataset associated with the patient;
perform a cluster analysis of the patient dataset with a cluster dataset to produce a correlated dental image information;
provide the correlated dental image information to a data mining entity and to compile a diagnostic aid for a user;
format the correlated dental image information based on another dataset associated with the data mining entity;
merge the correlated dental image information into the data mining entity dataset; and
identify and correct a discrepancy between the correlated dental image information and the data mining entity dataset.

US Pat. No. 10,460,838

AUTOMATED ANATOMICALLY-BASED REPORTING OF MEDICAL IMAGES VIA IMAGE ANNOTATION

INTERNATIONAL BUSINESS MA...

1. Non-transitory computer-readable medium including instructions that, when executed by an electronic processor, cause the electronic processor to perform a set of functions, the set of functions comprising:receiving a first annotation for a medical image;
automatically determining a location within an electronic structured report associated with the first annotation based on a predetermined mapping;
automatically populating the location of the electronic structured report based on the first annotation with medical data associated with the annotation; and
updating the first annotation displayed within the medical image to display the first annotation in a first manner different from a second manner used to display a second annotation within the medical image not mapped to any location within the electronic structured report.

US Pat. No. 10,460,837

BAGGAGE SYSTEM, RFID CHIP, SERVER AND METHOD FOR CAPTURING BAGGAGE DATA

Brain Trust Innovations I...

1. A baggage system comprising:a transfer reader device configured to communicate with a radio-frequency identification (RFID) tag associated with a baggage item, wherein the transfer reader device comprises:
an RFID antenna;
a power transmission subsystem including a power source and an antenna arranged to wirelessly transmit power from the power source to the RFID tag;
a transceiver configured to receive first data from the RFID tag, the first data including identification information;
a controller operatively coupled to the transceiver; and
one or more memory sources operatively coupled to the controller, the one or more memory sources including instructions for configuring the controller to generate one or more messages indicative of the identification information to be sent by the transceiver to a server device via a network connection,
wherein the server device comprises:
a transceiver configured to receive the one or more messages from the transfer reader device;
a controller operatively coupled to the transceiver; and
one or more memory sources operatively coupled to the controller, the one or more memory sources including instructions for configuring the controller to generate another message indicative of the identification information associated with the baggage item.

US Pat. No. 10,460,836

MEDICAL DEVICE SYSTEM AND METHOD FOR ESTABLISHING WIRELESS COMMUNICATION

1. A system for establishing wireless communication between at least one medical device having a predefined unique identification (ID) and at least one communication unit having a primary two-way wireless data communication interface, the system comprising:means for wirelessly performing primary two-way data communication including receiving and transmitting information between the medical device and the communication unit;
secondary one-way wireless communication means for communicating the predefined unique identification (ID) of the medical device through the secondary one-way wireless communication, wherein the secondary one-way wireless communication means includes means for non-encrypted wireless communication, and the means for wirelessly performing primary two-way data communication comprises an encrypted secure primary two-way wireless data communication interface;
means for ensuring that the primary two-way wireless data communication can be carried out if and only if the communication unit positively and in advance has identified the predefined unique identification (ID) of the medical device;
wherein the medical device comprises an activation member that is configured to be triggered by mechanical activation of the activation member, and secondary communication means for sending at least one signal to the communication unit upon the activation member being triggered, wherein the secondary one-way wireless communication means is for sending the at least one signal in real time, whereby the medical device is activated and sends at least one response signal to the secondary one-way wireless communication means to determine said predefined unique identification of the medical device; and
wherein the communication unit comprises means for providing interactive training of a user of the medical device on a real-time basis.

US Pat. No. 10,460,835

SYSTEM AND METHOD FOR MEDICAL DEVICE IDENTIFIER

ResMed Inc., San Diego, ...

1. A method for managing data associated with a home medical equipment (HME) device provided to a patient, the method comprising:receiving, by one or more processors, an HME device identifier associated with the HME device, the HME device identifier being a unique identifier, so as to avoid a duplicate to distinguish the HME device provided to the patient from other HME devices registered at a computer-based records management system;
searching, by the one or more processors, the records management system for a patient record that is associated with the HME device identifier, the search being performed by using a search key unique to the HME device identifier;
upon the search failing to retrieve any patient record associated with the HME device identifier, automatically generating, by the one or more processors, a new HME device associated patient record, wherein automatically generating the HME device associated patient record comprises:
automatically incorporating patient information of the patient into the HME device associated patient record; and
storing the HME device identifier into the HME device associated patient record, wherein the storing allows the patient information to be accessed via the HME device associated patient record in connection with an HME device identifier search.

US Pat. No. 10,460,834

SYSTEMS AND METHODS FOR FACILITATING HEALTH RESEARCH USING A PERSONAL WEARABLE DEVICE WITH RESEARCH MODE

Apple Inc., Cupertino, C...

1. A wearable device having an associated user ID, the device comprising:one or more sensors adapted for detecting one or more health parameters of a user when the device is worn by the user;
a wireless communication link adapted for near field/local communication with one or more computing devices including communications for pairing with the one or more computing devices and communications for transmitting one or more health parameters to the one or more computing devices;
user interface for receiving user input and for outputting information indications; and
a control unit for controlling operation of the wearable device in differing modes including:
a standard mode in which the wearable device pairs and communicates with at least one computing device associated with the user ID when within a wireless communication range of the at least one computing device to facilitate communication of a plurality of health data comprising detections of the one or more health parameters obtained from the one or more sensors, and
a health research mode in which the wearable device communicates by secure authenticated communication with at least one other computing device associated with a third party ID associated with a health researcher of a health research study in which the user is a participant, wherein in the health research mode, the wearable device communicates a first set of health data of the plurality of health data that is relevant to the health research study, wherein the communication of the first set of health data is pre-authorized by the user.

US Pat. No. 10,460,833

METHOD FOR STORING DATA OF PHOTOELECTRICALLY SYNCHRONOUS BRAIN ACTIVITY RECORDING

INSTITUTE OF AUTOMATION C...

1. A method for storing data of photoelectrically synchronous brain activity recordings, characterized in that said method comprises:generating data when a photoelectrically synchronous brain activity detection system is operating;
generating from said data a data storage file comprising a basic information data segment, a near-infrared spectrum data segment and a brain electrical activity data segment, and storing said data segments into a .neg file in binary form;
wherein the basic information data segment includes mode information, file version number, name and ID number of a tested person, doctor's name and workplace, and age and name of a tested person;
the near-infrared spectrum data segment includes:
a near-infrared data basic information field, which includes a sampling frequency of a near-infrared signal, a total number of event stimulations, a near-infrared wavelength, number of channels, number and positions of light sources, number and positions of probes, and number of samples of near-infrared signals;
a near-infrared data channel information field, which includes a valid flag bit of the channel, a light source index, a probe index, an analog magnification of each probe, a digital magnification of each probe and a reference light density;
a near-infrared data measurement data field, which includes a collected near-infrared spectral density; and
a near-infrared data event stimulation field, which includes an event stimulation name, a stimulation type, and a flag position; and
the brain electrical activity data segment includes:
a brain electrical data basic information field, which includes a brain electrical signal sampling frequency, number of channels, a total number of event stimulations, start and stop signs of low-pass filtering of an amplifier, start and stop signs of high-pass filtering of an amplifier, a reference electrode sign and the number of samples of collected brain electrical signals;
a brain electrical data channel information field, which includes a channel valid flag bit, an excitation electrode index, a measurement electrode index, an analog magnification of a measurement electrode, and a digital magnification of the measurement electrode;
a brain electrical data measurement data field, which includes the collected brain electrical signals; and
a brain electrical data event stimulation field, which includes an event stimulation name, a stimulation type, and a flag position.

US Pat. No. 10,460,831

PREDICTIVE OUTCOME ASSESSMENT FOR CHEMOTHERAPY WITH NEOADJUVANT BEVACIZUMAB

Koninklijke Philips N.V.,...

12. A method comprising:for each study subject of a population of study subjects:
initiating an oncological therapy regimen including at least a neoadjuvant therapeutic agent by administering a first dose of the neoadjuvant therapeutic agent to the study subject;
before the initiating, acquiring a baseline sample of a malignant tumor in the study subject;
after the initiating, acquiring a response sample of the malignant tumor in the study subject;
after acquiring the response sample, completing the oncological therapy regimen for the study subject;
after completing the oncological therapy regimen, determining pathological complete response (pCR) status of the study subject;
processing the baseline and response samples to generate baseline gene expression level information and response gene expression level information respectively for a plurality of genes; and
calculating differential gene expression level information for the study subject comparing the baseline gene expression level information and the response gene expression level information;
training a classifier using the differential gene expression level information calculated for the study subjects of the population as training data to generate a trained classifier that outputs a pCR prediction computed based on received differential gene expression level information for an input set of genes;
determining, by the trained classifier, a pCR prediction for an oncological patient based on differential gene expression level information from the patient;
determining, by a physician treating the oncological patient, based on the computed pCR prediction for the patient, whether to: (i) continue the oncological therapy regimen; or (ii) modify the oncological therapy regimen; and
treating the patient by: (i) continuing the oncological therapy regimen; or (ii) modifying the oncological therapy regimen;
wherein the plurality of genes comprises at least CDKN2B, ATL2, CTGF, INHBA, ID4, BMPR1A, CD1 E, TFDP1, AMIGO2, DDIT4, TGFB2, SPP1, CD28, PMEPA1, FAT4, KDM6B, MAP3K4, FAM162A, MYH11, PPP2R1B, LTBP1, COL1A1, YIPF5, VEGFA, C18orf25, FNDC3B, MYBL1, CDKN1A, ARHGEF40, LARP6, PAIP2B, RBMS1, NR2F2, ANGEL2, LEMD3, PPP2CA, NDST1, ZNF395, RNASE4, SMURF1, EDN1, SSBP3, SKIL, TBPL1, ALOX5AP, JUN, RARA, LMCD1, SERTAD2, ETS2, ABTB2, BET1L, MYC, CDK17, DOPEY1, SERPINE1, PFKFB3, TBC1D2B, PKIA, BMPR2, and NCOR2.

US Pat. No. 10,460,826

TEST METHODS OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS USED THEREIN

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:a medium controller configured to output an address that is sequentially counted in a test mode, configured to sense levels of data corresponding to the address in the test mode to determine if the data has a row error or a chip error, and configured to change a combination of a host address to generate and store a spare address if a combination of the address corresponds to the chip error in the test mode; and
a semiconductor module configured to include a plurality of semiconductor devices,
wherein each of the semiconductor devices comprises a spare area and a redundancy area,
wherein the semiconductor module repairs the address to output the data from the redundancy area of a chip if a combination of the address corresponds to the row error, and
wherein the semiconductor module outputs the data from the spare area selected by the spare address of the chip if a combination of the address corresponds to the chip error,
wherein the row error corresponds to an error which occurs in any one of the plurality of semiconductor devices; and
wherein the chip error corresponds to an error which occurs in at least two of the plurality of semiconductor devices.

US Pat. No. 10,460,825

SORTING NON-VOLATILE MEMORIES

International Business Ma...

1. A method, executed by one or more processors, for sorting non-volatile random access memories (NVRAMS), the method comprising:testing, via the one or more processors, a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS;
determining, via the one or more processors, a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data;
physically separating, via the one or more processors, the plurality of NVRAMS into routing groups based on the trend in the failure metric as a function of testing cycles; and
physically routing, via the one or more processors, the routing groups within a manufacturing environment.

US Pat. No. 10,460,824

SEMICONDUCTOR APPARATUS WITH REDUCED RISKS OF CHIP COUNTERFEITING AND NETWORK INVASION

Hiroshi Watanabe, Yokoha...

1. A semiconductor apparatus comprising:a semiconductor chip comprising:
a modular region comprising a plurality of modular areas each comprising a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses; and
a test circuit retrieving the redundant addresses intrinsic to the semiconductor chip by using a special test mode provided by a physical-chip-identification measuring device, wherein a distribution of the retrieved redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region, wherein the distribution of the retrieved redundant addresses is irreversible, wherein a random number represents physical properties intrinsic to the semiconductor chip and provides a copy protection wherein when another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction, and
wherein the test circuit outputs the random number generated from the distribution of the retrieved redundant addresses according to a specification code received from the physical-chip-identification measuring device.

US Pat. No. 10,460,823

TEST CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM USING THE TEST CONTROL CIRCUIT

SK hynix Inc., Icheon-si...

1. A test control circuit comprising:a control signal generation circuit configured to generate a normal set signal based on a test command signal in a normal mode, and generate a fast set signal regardless of the test command signal in a fast access mode; and
a test mode generation circuit configured to generate a normal test mode signal based on a mode signal, which is generated based on the test command signal, and the normal set signal in the normal mode, and generate a fast test mode signal based on the mode signal and the fast set signal in the fast access mode.

US Pat. No. 10,460,822

MEMORY WITH A CONTROLLABLE I/O FUNCTIONAL UNIT

ARM Limited, Cambridge (...

1. A circuit comprising:a controller;
a clock generator;
a bitcell array comprising a plurality of bitlines; and
a first I/O functional unit comprising:
a first multiplexer having an output port, wherein depending upon the controller, the first multiplexer selects a first input port or selects a first bitline input port that is coupled to a first bitline among a first group of bitlines in the plurality of bitlines;
a first latch having an input port and an output port, wherein the input port of the first latch is coupled to the output port of the first multiplexer, and wherein the first latch is clocked by the clock generator to latch the output port of the first multiplexer;
a second multiplexer having an output port, wherein depending upon the controller, the second multiplexer selects a second input port or selects a second bitline input port that is coupled to a second bitline among a second group of bitlines in the plurality of bitlines, wherein the second input port is coupled to the output port of the first latch; and
a second latch having an input port and an output port, wherein the input port of the second latch is coupled to the output port of the second multiplexer, and wherein the second latch is clocked by the clock generator to latch the output port of the second multiplexer, and wherein the first multiplexer, the first latch, the second multiplexer, and the second latch are coupled together in series.

US Pat. No. 10,460,821

AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:a first group of memories;
a controller to generate a test data pattern to be applied to at least the first group of memories;
a first group of comparators, each of which is associated with a respective memory of the first group of memories; and
a first delay response generator including an input to receive the test data pattern from the controller and an output to output a first expected data response corresponding to the test data pattern to the first group of comparators after a first delay, wherein the output of the first delay response generator is coupled in common to a respective input of each comparator of the first group of comparators so that the first expected data response is applied to all comparators of the first group of comparators via the output of the first delay response generator in response to the output of the first delay response generator outputting the first expected data response.

US Pat. No. 10,460,820

HIGH-SPEED TRACK-AND-HOLD DEVICE USING RF LINEARIZATION TECHNIQUE

INDUSTRY-ACADEMIC COOPERA...

1. A high-speed track-and-hold device, comprising:a buffer stage circuit comprising a PMOS source follower and a post linear circuit; and
a sampling stage circuit that is responsible for supplying a source voltage (VSS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (VSS) and a NMOS transistor of a sampling stage is turned off in hold operation.

US Pat. No. 10,460,819

NOISE REDUCTION IN VOLTAGE REFERENCE SIGNAL

Cirrus Logic, Inc., Aust...

1. An apparatus, comprising:a switched-capacitor circuit comprising a reference voltage input node, wherein the switched-capacitor circuit comprises a capacitor comprising a first terminal and a second terminal, and wherein the switched-capacitor circuit further comprises a first switch coupled to the first terminal, and wherein the switched-capacitor circuit further comprises a second switch coupled to the second terminal;
a variable resistor coupled between the reference voltage input node and components of the switched-capacitor circuit; and
a controller configured to adjust the variable resistor, wherein the controller is configured:
to set a resistance value of the variable resistor at a first level during a first time period; and
to set the resistance value of the variable resistor at a second level higher than the first level during a second time period,
wherein the first time period and the second time period are at least part of a first sampling period of the switched-capacitor circuit,
wherein the first switch and the second switch are closed for the duration of the first sampling period, and
wherein the controller is further configured to not short the resistor during a zeroth time period before the first time period, wherein the zeroth time period, the first time period, and the second time period comprise the first sampling period of the switched-capacitor circuit.

US Pat. No. 10,460,818

RETENTION-DRIFT-HISTORY-BASED NON-VOLATILE MEMORY READ THRESHOLD OPTIMIZATION

Seagate Technology LLC, ...

1. A method comprising:selecting a retention drift predictor scheme for predicting optimal read threshold voltages in a non-volatile memory (NVM) from retention drift history;
reading the retention drift history associated with reference cells of a plurality of groups of pages of the NVM; and
predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages based at least on the selected retention drift predictor scheme and the read retention drift history.

US Pat. No. 10,460,817

MULTIPLE (MULTI-) LEVEL CELL (MLC) NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS WITH MULTI-BIT INPUT VECTORS

QUALCOMM Incorporated, S...

1. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:a plurality of word lines configured to receive a multi-bit input vector represented by an input voltage on each word line among the plurality of word lines;
a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;
a plurality of source lines; and
a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of MLC NVM storage circuits; and
each MLC NVM storage circuit among the plurality of MLC NVM storage circuits comprising a plurality of NVM bit cell circuits each configured to store a respective memory state for the corresponding MLC NVM storage circuit;
each NVM bit cell circuit among the plurality of NVM bit cell circuits in a respective MLC NVM storage circuit having a resistance representing a stored memory state, and comprising:
a gate node coupled to a corresponding word line among the plurality of word lines; and
each NVM bit cell circuit configured to couple its resistance to a source line among the plurality of source lines coupled to its respective MLC NVM storage circuit in response to the input voltage applied to the corresponding word line coupled to the gate node.

US Pat. No. 10,460,816

SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS

Sandisk Technologies LLC,...

1. An apparatus, comprising:a memory structure, comprising:
a plurality of memory cells, and
a write circuit to apply a single programming pulse to a group of memory cells in response to a command; and
command processing logic configured to complete the command in response to the single programming pulse and mark the group for background verification.

US Pat. No. 10,460,815

DECODING METHOD OF SELECTING OPTIMIZED READ VOLTAGE SET BASED ON GRAY CODE COUNT DEVIATION SUMMATIONS, AND STORAGE CONTROLLER USING THE SAME

Shenzhen EpoStar Electron...

1. A decoding method for a storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of word lines, each of the word lines comprises a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different Gray codes, a total number of the Gray codes is N, N is a first predetermined positive integer greater than 2, and the method comprises:choosing a target word line of the word lines, wherein a plurality of target memory cells of the target word line are programmed;
reading the target memory cells by respectively using a plurality of different X read voltage sets to obtain X Gray code count deviation summations, wherein X is a second predetermined positive integer, the X read voltage sets and the corresponding X Gray code count deviation summations are ordered based on a first predetermined order, each of the X read voltage sets has N?1 read voltages ordered based on a second predetermined order, and an ith Gray code count deviation summation in the X Gray code count deviation summations corresponds to an ith read voltage set of the X read voltage sets, wherein i is 1 to X based on the first predetermined order; and
choosing one of the X read voltage sets as an optimized read voltage set based on the X Gray code count deviation summations.

US Pat. No. 10,460,814

NON-VOLATILE MEMORY AND METHOD FOR POWER EFFICIENT READ OR VERIFY USING LOCKOUT CONTROL

WESTERN DIGITAL TECHNOLOG...

1. A method of sensing a page of memory cells in an array, wherein each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states, comprising:providing a first series of one or more demarcation threshold voltages for demarcating between memory states in a first page read discerning a first bits of the page of memory cells, the first page read selected from a group consisting of a lower page read and a middle page read;
identifying one or more sets of memory cells demarcated between the one or more demarcation threshold voltages of the first series in the first page read;
providing a second series of one or more demarcation threshold voltages for demarcating between memory states in a second page read discerning a second bits of the page of memory cells, the second page read selected from a group consisting of the middle page read and a upper page read, the second page read is different than the first page read;
inhibiting conduction currents of the one or more sets of memory cells identified by the first series from the first page read, wherein the conduction currents are inhibited during the second series of the one or more demarcation threshold voltages in the second page read; and
identifying one or more sets of memory cells demarcated between the one or more demarcation threshold voltages of the second series in the second page read.

US Pat. No. 10,460,813

NONVOLATILE MEMORY DEVICES PROVIDING REDUCED DATA LINE LOAD

Samsung Electronics Co., ...

1. A nonvolatile memory device comprising:a memory cell array;
a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising:
a first high-voltage circuit comprising a first bit line selection circuit connected to the first plurality of bit lines;
a first bit line shut-off circuit connected to the first plurality of bit lines via the first bit line selection circuit; and
a first latch circuit configured to input and output data via a first data line; and
a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising;
a second high-voltage circuit comprising a second bit line selection circuit connected to the second plurality of bit lines;
a second bit line shut-off circuit connected to the second plurality of bit lines via the second bit line selection circuit; and
a second latch circuit configured to input and output data via a second data line,
wherein the first bit line selection circuit and the second bit line selection circuit are on a first region of a main surface of a substrate, the first bit line shut-off circuit and the second bit line shut-off circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate,
wherein the first region, the second region, and the third region are sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, and
wherein a width of the first data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines.

US Pat. No. 10,460,812

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device, comprising:a memory cell array including a first memory block,
the first memory block including a first sub block and a second sub block,
the first sub block including a first memory unit and a second memory unit,
the first memory unit including a first drain side selective transistor, a plurality of first memory cells, a first source side selective transistor, a plurality of second memory cells, and a first connecting portion that connects the first memory cells and the second memory cells in series,
the second memory unit including a second drain side selective transistor, a plurality of third memory cells, a second source side selective transistor, a plurality of forth memory cells and a second connecting portion that connects the third memory cells and the fourth memory cells in series;
the second sub block including a third memory unit and a fourth memory unit,
the third memory unit including a third drain side selective transistor, a plurality of fifth memory cells, a third source side selective transistor, a plurality of sixth memory cells and a third connecting portion that connects the fifth memory cells and the sixth memory cells in series;
the fourth memory unit including a fourth drain side selective transistor, a plurality of seventh memory cells, a fourth source side selective transistor, a plurality of eighth memory cells and a fourth connecting portion that connects the seventh memory cells and the eighth memory cells in series;
a first bit line connected to the first drain side selective transistor and the third drain side selective transistor;
a second bit line connected to the second drain side selective transistor and the fourth drain side selective transistor;
a plurality first word lines connected to gates of the first memory cells, gates of the third memory cells, gates of the fifth memory cells, and gates of the seventh memory cells, respectively,
a plurality second word lines connected to gates of the second memory cells, gates of the fourth memory cells, gates of the sixth memory cells, and gates of the eighth memory cells respectively;
a first source side select gate line connected to a gate of the first source side selective transistor and a gate of the second source side selective transistor;
a second source side select gate line connected to a gate of the third source side selective transistor and a gate of the fourth source side selective transistor; and
a control circuit which applies a first voltage to the first bit line and the second bit line, a second voltage which is lower than the first voltage to the first source side select gate line, a third voltage which is higher than the second voltage to the second source side select gate line, a fourth voltage which is lower than the second voltage to the plurality of first word lines and the plurality of second word lines, while erase operation to the first sub block is operated.

US Pat. No. 10,460,811

ARRAY OF THREE-GATE FLASH MEMORY CELLS WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE

Silicon Storage Technolog...

1. A memory device, comprising:a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells; and
each of the columns of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the column of memory cells.

US Pat. No. 10,460,810

DYNAMIC PROGRAMMING OF ADVANCED NANOMETER FLASH MEMORY

SILICON STORAGE TECHNOLOG...

9. A method of programming a memory device comprising a plurality of current mirrors, a bit line coupled to a plurality of memory cells and to a set of switches, each of the switches in the set of switches coupled to one of the plurality of current mirrors, and a controller configured to control the set of switches during a programming operation of one of the plurality of memory cells, the method comprising:turning on and off, by the controller during the programming operation, each switch in the set of switches in sequence.

US Pat. No. 10,460,809

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell, comprising:accessing a plural-level cell memory block in an N-bit cell mode;
determining a degree of disturbance of the plural-level cell memory block;
designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination; and
accessing the M-bit group in an M-bit cell mode.

US Pat. No. 10,460,808

MEMORY DEVICE AND PROGRAMMING OPERATION METHOD THEREOF WITH DIFFERENT BIT LINE VOLTAGES

MACRONIX INTERNATIONAL CO...

1. An operation method for a memory device having a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the operation method for the memory device including:applying a program voltage to at least a selected word line of the word lines; and
during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, generating and applying a plurality of different bit line voltages to the selected bit lines; the plurality of different bit line voltages generated and applied to the selected bit lines have different rising edges; and in generating the different bit line voltages, the bit line voltage having an earliest rising edge and a highest bit line voltage is generated for applying to a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, and the plurality of the different bit line voltages are not corresponding to the program voltage.

US Pat. No. 10,460,807

INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES

Conversant Intellectual P...

1. A flash memory device comprising:a memory cell array comprising a first string and a second string, each of the first and the second string comprising a plurality of erasable memory cells, each memory cell of the first string being connected to a respective word line of a first set of word lines, and each memory cell of the second string being connected to a respective word line out of a second set of word lines;
a first string select line, a first ground select line and a first local erase line each being connected to the first string;
a second string select line, a second ground select line and a second local erase line each being connected to the second string, the first and second string select line, the first and second ground select line, the first and second local erase line and each word line of the first and second sets of word lines running in a first direction;
a first pass block circuit comprising a first group of transistors located at an edge outside of the memory cell array, the first group of transistors comprising a first erase voltage pass transistor; and
a second pass block circuit comprising a second group of transistors located at one of the edge or another edge outside of the memory cell array, the second group of transistors comprising a second erase voltage pass transistor,
the first local erase line being coupled to the first erase voltage pass transistor and at least one of the first string select line being coupled to a first string select signal pass transistor of the first group of transistors, the first ground select line being coupled to a first ground select signal pass transistor of the first group of transistors, and a word line of the first set of word lines being coupled to a first word line pass transistor of the first group of transistors; and
the second local erase line being coupled to the second erase voltage pass transistor and at least one of the second string select line being coupled to a second string select signal pass transistor of the second group of transistors, the second ground select line being coupled to a second ground select signal pass transistor of the second group of transistors, and a word line of the second set of word lines being coupled to a second word line pass transistor of the second group of transistors,
wherein the first word line pass transistor is coupled to one of the first set of word lines, and the second word line pass transistor is coupled to one of the second set of word lines,
wherein the gate electrode of the first word line pass transistor and the gate electrode of the first erase voltage pass transistor are electrically in direct connection to each other,
wherein the gate electrode of the second word line pass transistor and the gate electrode of the second erase voltage pass transistor are electrically in direct connection to each other.

US Pat. No. 10,460,806

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device, comprising:a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series;
word lines connected to control gate electrodes of the nonvolatile memory cells;
bit lines connected to first ends of the NAND cell units;
a source line connected to second ends of the NAND cell units; and
a control circuit configured to perform a pre-program operation before an erasing operation for the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block,
the control circuit being configured to execute the erasing operation by applying an erasing voltage to the NAND cell units in the block, and to execute the pre-program operation by applying a certain pre-program voltage to memory cells for data storage in the NAND cell units, and by applying a voltage different from the certain pre-program voltage to two memory cells provided at the both ends of the memory string and at least one memory cell other than the two memory cells at the both ends in the NAND cell units.

US Pat. No. 10,460,805

SEMICONDUCTOR CIRCUIT, METHOD OF DRIVING SEMICONDUCTOR CIRCUIT, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor circuit, comprising:a first circuit that is able to generate, on a basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node;
a second circuit that is able to generate, on a basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node;
a first transistor that couples the first node to a third node when in an on state;
a second transistor that supplies a first direct-current voltage to the third node when in an on state;
a third transistor that includes a drain or a source to be coupled to the third node and that includes a gate coupled to the first node or the second node; and
a first storage element that includes a first terminal coupled to the third node and is able to take a first resistance state or a second resistance state,
the first circuit and the second circuit being configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

US Pat. No. 10,460,804

VOLTAGE-CONTROLLED RESISTIVE DEVICES

Massachusetts Institute o...

1. A memristive element comprising:a conductive material layer disposed in a x-y plane, the conductive material layer being configured to reversibly uptake an amount of at least one ionic species;
a first electrode coupled proximate to a first end of the conductive material layer;
a second electrode coupled proximate to a second end of the conductive material layer, opposite to the first end;
a gate dielectric layer disposed over the conductive material layer, the gate dielectric layer being configured to supply to, or receive from, the conductive material layer, an amount of the at least one ionic species; and
a gate electrode layer disposed over, and in electrical communication with, the gate dielectric material layer;
an inert metal underlayer disposed in electrical communication with the conductive material layer and coupled to the first electrode and the second electrode to shunt a portion of a current flowing between the first electrode and the second electrode;
the gate electrode layer, the gate dielectric layer, and the conductive material layer being configured such that:
a first potential difference applied in a first direction between the gate electrode layer and the conductive material layer modifies a proportionate amount of the at least one ionic species in a portion of the conductive material layer to generate a first memristive state comprising a first lateral resistive state between the first electrode and the second electrode;
a second potential difference applied in a second direction between the gate electrode layer and the conductive material layer modifies a proportionate amount of the at least one ionic species in a portion of the conductive material layer to generate a second memristive state comprising a second lateral resistive state between the first electrode and the second electrode that is different from the first lateral resistive state; and
the memristive element persists in the first memristive state or the second memristive state in response to discontinuance of the first potential difference or the second potential difference, respectively.

US Pat. No. 10,460,803

MEMORY CELL, MEMORY CELL ARRAY, MEMORY DEVICE AND OPERATION METHOD OF MEMORY CELL ARRAY

Semiconductor Manufacturi...

1. A memory cell, comprising:a first diode, comprising:
a first well region in a substrate;
a first N-type doped region adjacent to the first well region and connected to a bit line; and
a first P-type doped region adjacent to the first well region and separated from the first N-type doped region;
a second diode separated from the first diode, and comprising:
a second well region in the substrate, wherein the second well region has a conductivity type same as the first well region;
a second N-type doped region adjacent to the second well region; and
a second P-type doped region, adjacent to the second well region, connected to a reset line, and separated from the second N-type doped region;
a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively;
a top electrode connected to a word line; and
a data storage material layer located between the bottom electrode and the top electrode.

US Pat. No. 10,460,802

APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY

Ovonyx Memory Technology,...

9. An apparatus, comprising:a memory cell having a first node and a second node;
a first voltage source;
a second voltage source different than the first voltage source; and
a circuit configured to:
bias the first node of the memory cell using the first voltage source;
detect, while the first node is biased using the first voltage source, a transition of the memory cell from a first state to a second state that has a lower resistance than the first state; and
access the memory cell based at least in part on the detected transition, wherein the accessing comprises biasing the first node of the memory cell using the second voltage source.

US Pat. No. 10,460,801

MULTI-LEVEL PHASE CHANGE DEVICE

WESTERN DIGITAL TECHNOLOG...

1. A method for programming a memory cell, comprising:changing the memory cell to a first resistance state by providing a first voltage to the memory cell; and
changing the memory cell to a second resistance state by providing a second voltage to the memory cell, wherein the memory cell comprises a first phase change material layer separated from a second phase change material layer by a diffusion barrier layer wherein at least one of the first phase change material layer and the second phase change material layer comprises any of selenium tellurium (SeTe), silicon tellurium (SiTe), antimony selenide (SbSe), tin selenide (SnSe), tin tellurium (SnTe), tin antimony (SnSb), germanium antimony (GeSb) and silicon antimony (SiSb), wherein the first phase change material layer and the second phase change material layer comprise different alloys of the same phase change material, wherein altering a resistance state of the memory cell through application of the first voltage comprises setting the memory cell to a first resistance state, and altering the resistance state of the memory cell through application of the second voltage comprises transitioning the memory cell from the first resistance state to a second resistance state.

US Pat. No. 10,460,800

DATA SENSING IN CROSSPOINT MEMORY STRUCTURES

Hewlett Packard Enterpris...

1. A data storage device, comprisinga memory cell array; and
sense circuitry to detect a data value stored to a memory cell of the memory cell array;
the controller to bias the sense circuitry during a read phase of a write operation;
wherein:
the sense circuitry is to sample a sneak current and subtract the sneak current from the current measured through the memory cell; and
to bias the sense circuitry, the sneak current is further increased or decreased compared the sampled sneak current.

US Pat. No. 10,460,799

METHOD OF READING RESISTIVE MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A method of reading a resistive memory device comprising:preparing a memory cell including a selection element and a variable resistance element, the selection element exhibiting a snap-back behavior on a current-voltage sweep curve for the memory cell;
determining first and second read voltages to be applied to the memory cell within a voltage range in which the selection element maintains a turned-on state, the second read voltage being lower than the first read voltage and the second read voltage being selected in a voltage range in which the selection element exhibits the snap-back behavior;
applying the first read voltage to the memory cell to measure a first cell current;
applying the second read voltage to the memory cell to measure a second cell current; and
determining a resistance state stored in the memory cell based on the first cell current and the second cell current.

US Pat. No. 10,460,798

MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS

Micron Technology, Inc., ...

1. A method of forming memory cells, the method comprising:forming a first plug material and a second plug material;
forming a material stack on a portion of the first plug material and a portion of the second plug material, wherein the material stack includes a plurality of resistance variable materials separated by respective dielectric materials;
forming a first conductive material on the first plug material, the first conductive material serving as a first conductive contact for the plurality of resistance variable materials of a first memory cell;
forming a second conductive material that serves as a second conductive contact for the plurality of resistance variable materials of both the first memory cell and an adjacent memory cell and is separated from the first plug material by a dielectric material, wherein the second conductive material is formed subsequent to forming the first conductive material; and
forming a third conductive material on the second plug material, the third conductive material serving as a first conductive contact for the plurality of resistance variable materials of the adjacent memory cell.

US Pat. No. 10,460,797

METHOD FOR PROGRAMMING NON-VOLATILE MEMORY AND MEMORY SYSTEM

MACRONIX INTERNATIONAL CO...

1. A method for programming a non-volatile memory in a programming operation, the non-volatile memory including a plurality of cells, each of the cells stores data having at least 2 bits, the method comprising:providing at least one programming pulse for programming a target cell of the cells;
applying at least one program-verify pulse to the target cell;
setting the target cell as successfully programmed in condition that a threshold voltage of the target cell is greater than or equal to a program-verify voltage; and
performing a post-verifying operation to the target cell in condition that the target cell is set as successfully programmed, the post-verifying operation comprising applying at least one post-verifying pulse to the target cell, wherein an amplitude of the at least one post-verifying pulse is equal to an amplitude of the at least one program-verify pulse,
wherein when it is determined that the threshold voltage of the target cell is greater than or equal to a post-verifying voltage, providing the at least one post-verifying pulse at least twice to verify whether the threshold voltage of the target cell is greater than or equal to the post-verifying voltage before a post-programming pulse is provided until the threshold voltage of the target cell is determined as less than the post-verifying voltage or a number of the provided the at least one post-verifying pulses is equal to a post-verifying limit.

US Pat. No. 10,460,796

SYSTEM AND METHOD FOR CRYOGENIC HYBRID TECHNOLOGY COMPUTING AND MEMORY

SeeQC, Inc., Elmsford, N...

1. An arithmetic logic unit, comprising a multistage processing pipeline configured to process a received multibit operand through each of a plurality of stages, wherein an arithmetic processing operation within at least one stage is data-dependent on a digital value of the multibit operand, and availability of digital data at a respective stage triggers a commencement of processing within the stage, substantially without time synchronization of the plurality of stages.