US Pat. No. 10,396,170

SEMICONDUCTOR DEVICES AND METHODS FOR FORMING SEMICONDUCTOR DEVICES

Infineon Technologies AG,...

1. A semiconductor device comprising:a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate;
a plurality of graphene layer portions, wherein each of the plurality of graphene layer portions is located adjacent to a respective portion of the transistor doping region at a surface of the semiconductor substrate; and
a transistor wiring structure located adjacent to the plurality of graphene layer portions,
wherein the transistor wiring structure is in contact with the transistor doping region between neighboring graphene layer portions of the plurality of graphene layer portions.

US Pat. No. 10,396,169

NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first nanosheet stack on a substrate, the first nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a second nanosheet stack on the substrate, the second nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a dielectric layer formed over a channel region of the first nanosheet stack;
a first gate formed over the dielectric layer in the channel region of the first nanosheet stack;
a second gate formed over a channel region of the second nanosheet stack;
a first gate contact on the first gate; and
a second gate contact on the second gate;
wherein a distance between adjacent nanosheets in the first nanosheet stack is greater than a distance between adjacent nanosheets in the second nanosheet stack;
wherein spacers are formed between the adjacent nanosheets in the first nanosheet stack and between adjacent nanosheets in the second nanosheet stack;
wherein a length of the spacers between the adjacent nanosheets in the first nanosheet stack is greater than a length of at least one of the spacers between the adjacent nanosheets in the second nanosheet stack;
wherein the first gate comprises a high-k dielectric film formed on a surface of the dielectric layer in the channel region of the first nanosheet stack; and
wherein the length of a bottom most spacer of the spacers below the adjacent nanosheets in the first nanosheet stack is greater than the length of the at least one of the spacers between the adjacent nanosheets in the second nanosheet stack.

US Pat. No. 10,396,168

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first pipe gate;
a second pipe gate disposed on the first pipe gate;
an inter-gate insulating layer disposed between the first pipe gate and the second pipe gate;
first memory cells and second memory cells, disposed on the second pipe gate;
a first channel layer extending toward the first memory cells from the inside of the first pipe gate, the first channel layer connecting the first memory cells in series;
a second channel layer extending toward the second memory cells from the inside of the second pipe gate, the second channel layer connecting the second memory cells in series;
a first contact structure connected to the first pipe gate; and
a second contact structure connected to the second pipe gate.

US Pat. No. 10,396,167

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a first resistive element formed in an insulating film on a semiconductor substrate, the first resistive element including a first portion and a second portion, the first portion being at a different depth and made of a different material than the second portion; and
a second resistive element that differs from the first resistive element, and is formed in the insulating film, the second resistive element located at a different depth in the insulating film as the first portion of the first resistive element, and facing, at least in part, the first portion of the first resistive element with the insulating film therebetween, wherein
the first portion is located in a first region of the first resistive element, and the second portion is connected to the first portion and located in a second region of the first resistive element, and
the second resistive element has terminals to which external voltages are applied, and are connected with the first resistive element between the terminals.

US Pat. No. 10,396,166

SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION

MediaTek Inc., Hsin-Chu ...

1. A semiconductor device, comprising:a semiconductor substrate having a first conductivity type;
a first well doped region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type;
a source doped region formed on the first well doped region, having the second conductivity type;
a drain doped region formed on the first well doped region and separated from the source doped region, having the second conductivity type;
a first gate structure formed over the first well doped region and adjacent to the source doped region;
a second gate structure formed beside the first gate structure and close to the drain doped region; and
a third gate structure formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

US Pat. No. 10,396,165

THIN LOW DEFECT RELAXED SILICON GERMANIUM LAYERS ON BULK SILICON SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a strain relaxed silicon germanium layer having a thickness from 50 nm to 1000 nm and a defect density of less than 100 defect atoms/cm2 located directly on a surface of a silicon substrate, wherein lattices of the strain relaxed silicon germanium layer and the silicon substrate are misaligned.

US Pat. No. 10,396,164

SEMICONDUCTOR CRYSTAL SUBSTRATE WITH FE DOPING

FUJITSU LIMITED, Kawasak...

1. A semiconductor crystal substrate, comprising:a first buffer layer formed of a nitride semiconductor over a substrate;
a second buffer layer formed of a nitride semiconductor on the first buffer layer;
a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer; and
a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer,
wherein an iron (Fe) concentration of the first buffer layer is higher than a carbon (C) concentration of the first buffer layer,
a C concentration of the second buffer layer is higher than an Fe concentration of the second buffer layer throughout the second buffer layer in a thickness direction of the second buffer layer, and
the Fe concentrations of the first and second buffer layers peak at an interface between the first and second buffer layers.

US Pat. No. 10,396,163

SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide epitaxial substrate, comprising:a silicon carbide single crystal substrate having a first main surface; and
a silicon carbide layer on the first main surface,
the silicon carbide layer including a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate,
the second main surface having a maximum diameter of more than or equal to 100 mm,
the second main surface including an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region,
the central region having a haze of more than or equal to 20 ppm and less than or equal to 75 ppm.

US Pat. No. 10,396,162

SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device, comprising:a first semiconductor layer of a first conductivity type, formed on a front surface of a silicon carbide semiconductor substrate of the first conductivity type;
a first semiconductor region of a second conductivity type, selectively formed in a surface layer of the first semiconductor layer;
a second semiconductor region of the second conductivity type, selectively formed in the surface layer of the first semiconductor layer so as to be connected with the first semiconductor region, bottoms of the first semiconductor region and the second semiconductor region being located at a same depth relative to a surface of the first semiconductor layer and within the first semiconductor layer;
a first electrode forming a Schottky contact with the first semiconductor layer and the first semiconductor region; and
a second electrode forming an ohmic contact with the second semiconductor region,
wherein
a density of the second electrode per unit area of the silicon carbide semiconductor substrate in a plan view is higher at a center portion of the silicon carbide semiconductor substrate and decreases in a direction toward an outer peripheral side of the silicon carbide semiconductor substrate.

US Pat. No. 10,396,161

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising: a silicon carbide (SiC) substrate of a first conductivity type, having a front surface and a back surface; a SiC layer of the first conductivity type, formed on the front surface of the SiC substrate and having an impurity concentration lower than that of the SiC substrate; a first region of a second conductivity type, selectively formed in the SiC layer at a surface thereof; a source region of the first conductivity type formed in the first region; a contact region of the second conductivity type formed in the first region, the contact region having an impurity concentration higher than that of the first region; a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region; a first gate electrode disposed on the gate insulating film above the portion of the first region; an interlayer insulating film covering the first gate electrode; a source electrode electrically connected to the source region and the contact region; a drain electrode formed on the back surface of the SiC substrate; a first barrier film formed on and covering the interlayer insulating film, interposing the source electrode and the interlayer insulating film, the first barrier film separating the source electrode from the interlayer insulating film, so as to prevent penetration of metal atoms of the source electrode into the interlayer insulating film; and a first metal electrode formed directly on the source electrode and the first barrier film, wherein the first barrier film is formed by a single-layer structure of titanium nitride (TiN), or a layered structure of titanium (Ti) and TiN, and the first metal electrode is formed by a layered structure of Ti and aluminum (Al).

US Pat. No. 10,396,160

SEMICONDUCTOR STRUCTURE HAVING A SINGLE OR MULTIPLE LAYER POROUS GRAPHENE FILM AND THE FABRICATION METHOD THEREOF

CHANG GUNG UNIVERSITY, T...

1. A semiconductor structure having a single-layer porous graphene film with a thickness of about 0.34 nm, formed by a low pressure chemical vapor deposition (LPCVD) and a metalorganic chemical vapor deposition (MOCVD), comprising:a sapphire substrate;
wherein said single-layer porous graphene film having the thickness of about 0.34 nm is provided on said sapphire substrate, said single-layer porous graphene film being formed on a metal foil by the low pressure chemical vapor deposition (LPCVD) at 900° C. to 1100° C. via passing through methane (CH4) and hydrogen (H2),
wherein said metal foil is selected from a group consisting of a Cu foil or Ni foil; and
wherein a gallium nitride layer is formed on said single-layer porous graphene film, said gallium nitride being deposited on said single-layer porous graphene film and said sapphire substrate by using the metalorganic chemical vapor deposition (MOCVD) at 900° C. to 1100° C.

US Pat. No. 10,396,159

FINFET CASCODE LATERALLY-DIFFUSED SEMICONDUCTOR DEVICE

AVAGO TECHNOLOGIES INTERN...

1. A semiconductor device, comprising:a substrate having a first well region comprising a first dopant and a second well region comprising a second dopant;
one or more semiconductor fin structures formed on the substrate, the one or more semiconductor fin structures having a channel region along a channel axis through the first well region;
a drain region formed on the one or more semiconductor fin structures;
a source region formed on the one or more semiconductor fin structures, the first well region and the drain region being formed to operate at a first operating voltage, the second well region and the source region being formed to operate at a second operating voltage that is smaller than the first operating voltage;
a gate structure disposed on at least a portion of the one or more semiconductor fin structures;
a dummy gate disposed on at least a portion of the one or more semiconductor fin structures, the dummy gate being disposed between the gate structure and the drain region; and
a plurality of epitaxial growth structures formed on the one or more semiconductor fin structures, wherein the dummy gate is disposed between and adjacent to two epitaxial growth structures of the plurality of epitaxial growth structures, and wherein the plurality of epitaxial growth structures comprises a doping material having a doping concentration that is greater than that of at least one of the first dopant or the second dopant.

US Pat. No. 10,396,158

TERMINATION STRUCTURE FOR NANOTUBE SEMICONDUCTOR DEVICES

Alpha and Omega Semicondu...

1. A termination structure for a semiconductor device including an active area and a termination area surrounding the active area, the termination structure being formed in the termination area and comprising:a first semiconductor layer of a first conductivity type comprising a plurality of trenches formed in a top surface of the first semiconductor layer, the trenches forming mesas in the first semiconductor layer;
a first epitaxial layer of the first conductivity type formed on the sidewalls of the mesas;
a second epitaxial layer of a second conductivity type, opposite the first conductivity type, formed on the first epitaxial layer, the trenches between the second epitaxial layer formed on adjacent mesas being filled with a first dielectric layer;
a first termination cell formed in the termination area at an interface to the active area, the first termination cell being formed in a mesa of the first semiconductor layer and having a first width; and
an end termination cell being formed away from the interface to the active area in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

US Pat. No. 10,396,157

SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A semiconductor device comprising:a semiconductor layer having a first device region and a second device region;
a shallow trench isolation structure, in the semiconductor layer, located at a periphery of the first device region and the second device region;
a first insulating layer and a second insulating layer, on the semiconductor layer, respectively located in the first device region and the second device region;
a first gate structure located on the first insulating layer;
a source region and a drain region, in the semiconductor layer, located at two sides of the first gate structure;
a gate doped region in a surface region of the semiconductor layer in the second device region to serve as a second gate structure;
a channel layer located on the second insulating layer; and
a source layer and a drain layer, directly on the shallow trench isolation structure, located at two sides of the channel layer.

US Pat. No. 10,396,156

METHOD FOR FINFET LDD DOPING

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a structure that includes a substrate, a fin over the substrate, and a gate structure engaging the fin;
performing a first implantation process to implant a dopant into the fin adjacent to the gate structure;
forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin;
performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers;
after the first etching process, performing a second implantation process to implant the dopant into the fin and the fin sidewall spacers;
after the second implantation process, performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers; and
epitaxially growing a semiconductor material in the trench.

US Pat. No. 10,396,154

LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE

International Business Ma...

1. A device comprising:a dielectric pedestal including a nucleation dielectric layer;
a base region comprised of a germanium containing material in contact with the pedestal, wherein the germanium containing material is silicon free germanium; and
an emitter region and collector region present on opposing sides of the base region contacting a sidewall of the pedestal and an upper surface of the nucleation dielectric layer.

US Pat. No. 10,396,153

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer;
a third nitride semiconductor layer formed on the second nitride semiconductor layer;
a mesa-shaped fourth nitride semiconductor layer formed on the third nitride semiconductor layer;
a source electrode formed on the third nitride semiconductor layer and formed on one side of the fourth nitride semiconductor layer;
a drain electrode formed on the third nitride semiconductor layer and formed on the other side of the fourth nitride semiconductor layer;
a gate electrode formed over the fourth nitride semiconductor layer; and
an element isolation region provided in a stack body of the first to fourth nitride semiconductor layers and defining an active region,
wherein the gate electrode extends from over the active region to over the element isolation region, and
wherein in plan view, length of a border line between the active region and the element isolation region in a region overlapped with the mesa-shaped fourth nitride semiconductor layer is longer than gate length of the gate electrode.

US Pat. No. 10,396,152

FABRICATION OF PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE USING INTERFACE INTERACTION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a plurality of vertically stacked suspended nanowires extending having a gate structure being present on a channel region portion of the suspended nanowires;
a dielectric spacer having a uniform composition in direct contact with the gate structure, the dielectric spacer having a uniform length extending from a upper surface of the gate structure to the base of the gate structure, wherein a first length of the dielectric spacer positioned between adjacently stacked suspended nanowires is substantially equal to a second length of the dielectric spacer adjacent to the upper surface of the gate structure; and
source and drain regions present on source and drain region portions of the plurality of suspended nanowires, wherein the suspended nanowires are uniform in geometry along an entire length of the suspended nanowires from a channel region of the suspended nanowire to the source and drain region portions of the suspended nanowire.

US Pat. No. 10,396,151

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of forming a fin field effect transistor device, comprising:forming a vertical fin layer on a bottom source/drain layer;
forming one or more fin templates on the vertical fin layer;
forming a vertical fin below each of the one or more fin templates;
reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin; and
depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.

US Pat. No. 10,396,149

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a wide-bandgap semiconductor substrate of a first conductivity type containing a semiconductor material having a bandgap wider than that of silicon;
a first wide-bandgap semiconductor layer of the first conductivity type provided on a front surface of the wide-bandgap semiconductor substrate, the first wide-bandgap semiconductor layer containing a semiconductor material having a bandgap wider than that of silicon, an impurity concentration of the first wide-bandgap semiconductor layer being lower than that of the wide-bandgap semiconductor substrate;
a base region of a second conductivity type selectively provided in a first side of the first wide-bandgap semiconductor layer opposite to a second side of the first wide-bandgap semiconductor layer facing toward the wide-bandgap semiconductor substrate;
a second wide-bandgap semiconductor layer of the second conductivity type provided on a surface on the first side of the first wide-bandgap semiconductor layer opposite to the second side of the first wide-bandgap semiconductor layer facing toward the wide-bandgap semiconductor substrate;
a source region of the first conductivity type selectively provided in the second wide-bandgap semiconductor layer;
a plurality of trenches that are parallel to each other, each penetrating the source region and the second wide-bandgap semiconductor layer to reach the first wide-bandgap semiconductor layer;
a gate electrode provided in each of the trenches, with a gate insulating film disposed therebetween;
a source electrode contacting the second wide-bandgap semiconductor layer and the source region; and
a drain electrode on a rear surface of the wide-bandgap semiconductor substrate, wherein
the base region includes a plurality of first portions that extend in a direction perpendicular to the trench plurality of trenches, the first portions being spaced apart from each other by a same predetermined distance in a direction parallel to the trenches,
the base region is formed at a bottom end of the trenches and includes a second portion formed at a bottom end of each of the trenches, the second portion extending in a direction parallel to the trenches, the second portion connecting the plurality of first portions of the base region to each other, and
the base region is free of any portion that extends in a direction parallel to the trenches and that intersects any of the first portions of the base region between two abutting trenches except the second portion.

US Pat. No. 10,396,148

SEMICONDUCTOR DEVICE

MURATA MANUFACTURING CO.,...

1. A semiconductor device comprising:a semiconductor layer arranged on a semiconductor substrate, the semiconductor layer comprising a first active region and an element isolation region, wherein, when the semiconductor device is viewed in a plan view, the element isolation region surrounds the first active region;
a first field effect transistor formed in the first active region;
a plurality of guard ring electrodes separated from each other and configured to affect an electric potential of the first active region through the element isolation region;
an interlayer insulating film formed over the semiconductor layer, the first field effect transistor, and the guard ring electrodes; and
at least one guard ring connection wiring formed on the interlayer insulating film and configured to electrically interconnect the plurality of guard ring electrodes.

US Pat. No. 10,396,147

GRATED MIM CAPACITOR TO IMPROVE CAPACITANCE

International Business Ma...

1. A method of forming a semiconductor structure comprising:providing a metallization structure comprising a first dielectric material layer and a first lower interconnect structure embedded in a portion of the first dielectric material layer and a second lower interconnect structure embedded in another portion of the first dielectric material layer;
forming a second dielectric material layer on the metallization structure;
forming a plurality of trenches in an upper portion of the second dielectric material layer, wherein the plurality of trenches extend across the first lower interconnect structure and the second lower interconnect structure, and each trench defines a gap that is present between a neighboring pair of dielectric mesa portions of the second dielectric material layer;
forming a first metal layer along sidewall surfaces and a bottom surface of each trench of the plurality of trenches and a topmost surface of each of the dielectric mesa portions of the second dielectric material layer;
patterning the first metal layer to remove the first metal layer completely from an area where the second lower interconnect structure is located, wherein the patterning the first metal layer provides a first metal portion overlying the first lower interconnect structure, and wherein the first metal portion is continuously present on the sidewall surfaces and the bottom surface of each trench that is located above and between the first lower interconnect structure and the second lower interconnect structure, and the first metal portion has a first end wall that is vertically aligned with a sidewall of a first dielectric mesa portion of the second dielectric material that overlies the first lower interconnect structure and a second end wall that is vertically aligned with a sidewall of a second dielectric mesa portion of the second dielectric material that is laterally adjacent to, but not, directly over the second lower interconnect structure;
forming a first capacitor dielectric layer on the first metal portion and exposed surfaces of the plurality of trenches;
forming a second metal layer over the first capacitor dielectric layer;
patterning the second metal layer to remove the second metal layer completely from an area where the first lower interconnect structure is located, wherein the patterning the second metal layer provides a second metal portion overlying the second lower interconnect structure;
forming a third dielectric material layer to completely fill the plurality of trenches; and
forming a first upper interconnect structure extending through the third dielectric material layer, the first capacitor dielectric layer, the first metal portion and the second dielectric material layer to contact the first lower interconnect structure, and a second upper interconnect structure extending through the third dielectric material layer, the second metal portion, the first capacitor dielectric layer and the second dielectric material layer to contact the second lower interconnect structure, wherein the forming of the first upper interconnect structure comprises removing an entirety of the first and second mesa portions of the second dielectric material.

US Pat. No. 10,396,146

LEAKAGE CURRENT REDUCTION IN STACKED METAL-INSULATOR-METAL CAPACITORS

INTERNATIONAL BUSINESS MA...

1. A method of forming a capacitor, comprising:forming a dielectric layer on a first metal layer;
oxygenating the dielectric layer such that interstitial oxygen is implanted in the dielectric layer;
forming a second metal layer on the dielectric layer; and
heating the dielectric layer to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

US Pat. No. 10,396,145

MEMORY CELLS COMPRISING FERROELECTRIC MATERIAL AND INCLUDING CURRENT LEAKAGE PATHS HAVING DIFFERENT TOTAL RESISTANCES

Micron Technology, Inc., ...

1. A memory cell, comprising:a capacitor comprising:
a first capacitor electrode having laterally-spaced walls that individually have a top surface;
a second capacitor electrode laterally between the walls of the first capacitor electrode, the second capacitor electrode comprising a portion above the first capacitor electrode; and
ferroelectric material laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode, the capacitor comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material; and
a parallel current leakage path between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode, the parallel current leakage path being circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path.

US Pat. No. 10,396,144

MAGNETIC INDUCTOR STACK INCLUDING MAGNETIC MATERIALS HAVING MULTIPLE PERMEABILITIES

INTERNATIONAL BUSINESS MA...

1. An inductor structure, comprising:a laminated first stack including:
layers having insulating material; and
layers having a first magnetic material, the layers having insulating material alternating with the layers having the first magnetic material; and
a laminated second stack including:
layers having second insulating material; and
layers having a second magnetic materials, the second magnetic materials having at least two different permeabilities,
wherein the layers having the second insulating material alternate with the layers having the second magnetic material, the second magnetic material having a permeability larger than that of the first magnetic material, and
wherein the first and second magnetic materials are selected from the group consisting of a Co containing magnetic material, FeTaN, and FeNi.

US Pat. No. 10,396,143

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device comprising: a substrate with an active area and a pad area; a first anode electrode in the active area of the substrate; a second anode electrode on the first anode electrode, the second anode electrode being electrically connected to the first anode electrode; an organic emitting layer on the second anode electrode; a cathode electrode on the organic emitting layer; a first auxiliary electrode in a same layer as the first anode electrode; a second auxiliary electrode in a same layer as the second anode electrode, the second auxiliary electrode being electrically connected to the first auxiliary electrode and the cathode electrode, a first signal line and a second signal line in the active area; a first pad in the pad area and connected to the first signal line, wherein the first pad includes a link region electrically connected to the first signal line and a first bonding region connected to the link region, the first bonding region including one or more first contact holes for electrical connection with the link region; and a second pad in the pad area and connected to the second signal line, wherein the second pad includes a second bonding region corresponding to the first bonding region of the first pad and a contact region corresponding to the link region of the first pad, the contact region being electrically connected to the second bonding region and including one or more second contact holes for electrical connection with the second signal line.

US Pat. No. 10,396,142

ARRAY SUBSTRATE AND AMOLED DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate, comprising:a substrate;
a driver chip, located on the substrate;
a plurality of data lines, arranged in turn on the substrate and extended longitudinally to be connected electrically to the driver chip;
a plurality of high level lines, arranged in turn on the substrate, and extending longitudinally on the substrate;
a metal block, located on the substrate and electrically connected to the high level lines, so that the high level lines are at the same high level; wherein the data lines are electrically connected to the driver chip through the area which the metal block is located in, and an insulating layer exists between the metal block and the data lines, a hollow area located in the metal block overlapping the data lines to reduce parasitic capacitance formed by the metal block and the data lines, wherein the hollowed area is a plurality of derating slits, the number of the derating slits is multiple, and at least one of the data lines corresponds to at least one of the derating slits one to one,
wherein de-electrostatic slits are provided in the metal block, the de-electrostatic slits are not overlapping the data lines and are surrounded by the metal block.

US Pat. No. 10,396,141

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device, comprising:a flexible substrate including an image display area and a non-display area surrounding the image display area;
a first insulating film disposed on the flexible substrate;
a switching element disposed on the first insulating film;
a second insulating film disposed on a semiconductor layer of the switching element;
a third insulating film disposed on a gate electrode of the switching element;
a signal wiring disposed on the third insulating film and electrically connected with the switching element;
a first organic film disposed on the signal wiring;
a connection wiring disposed on the first organic film and electrically connected with the signal wiring through a first contact hole in the first organic film;
a second organic film disposed on the connection wiring and the first organic film; and
a pad electrode disposed on the second organic film and electrically connected with the connection wiring through a second contact hole in the second organic film,
wherein the connection wiring is located between the first organic film and the second organic film and is in contact with the first organic film and the second organic film,
the non-display area includes a first area adjacent to the image-display area, a second area adjacent to the first area, and a third area adjacent to the second area,
the flexible substrate is bent at the second area in which the connection wiring is located between the first organic film and the second organic film,
the first contact hole is located in the first area,
the second contact hole is located in the third area,
the connection wiring is formed continuously as one unitary wiring from the first contact hole to the pad electrode, and
the first insulating film, the second insulating film, and the third insulating film are not disposed in the second area,
the first organic film is in contact with a surface of the flexible substrate in the second area,
the first organic film has a first thickness in the first area and the third area, and a second thickness in the second area, and
the second thickness is larger than the first thickness.

US Pat. No. 10,396,140

THIN FILM TRANSISTOR INCLUDING A VERTICAL CHANNEL AND DISPLAY APPARATUS USING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor comprising:a substrate;
a gate electrode disposed over the substrate, and comprising a center part and a peripheral part configured to at least partially surround the center part, wherein the gate electrode includes an opening disposed directly between the center part and the peripheral part, and the opening at least partially surrounds the center part of the gate electrode;
a gate insulating layer disposed below the gate electrode;
a first electrode insulated from the gate electrode by the gate insulating layer, and having at least a portion thereof overlapping the center part in a direction perpendicular to an upper surface of the substrate;
a spacer disposed below the first electrode;
a second electrode insulated from the first electrode by the spacer, and having at least a portion thereof overlapping the peripheral part; and
a semiconductor layer connected to the first and second electrodes, and insulated from the gate electrode by the gate insulating layer.

US Pat. No. 10,396,139

ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY

Samsung Display Co., Ltd....

1. An organic light-emitting diode (OLED) display, comprising:a substrate;
an active pattern formed over the substrate and including: a first region, a second region, a third region, a fourth region, a fifth region, and a sixth region, wherein the second region and the sixth region are: i) electrically connected to each other and ii) formed directly adjacent each other in a first continuous region of the active pattern, and wherein the fourth region and the fifth region are: i) electrically connected to each other and ii) formed directly adjacent each other in a second continuous region of the active pattern;
a gate insulation layer formed over the active pattern;
a first gate electrode formed over the gate insulation layer, wherein the first gate electrode defines a first transistor together with the first region and the second region;
a second gate electrode formed on the same layer as the first gate electrode, wherein the second gate electrode defines: i) a second transistor together with the third region and the fourth region which are arranged in a first direction ii) a third transistor together with the fifth region and the sixth region which are arranged in a second direction, wherein the fifth region and the sixth region are on opposite sides of a gate region of the third transistor, and wherein the second direction is substantially perpendicular to the first direction;
a first insulating interlayer formed over the first gate electrode, the second gate electrode, and the gate insulation layer;
a first conductive pattern formed over the first insulating interlayer, wherein the first conductive pattern overlaps at least a portion of the fourth and fifth regions in a thickness direction of the substrate, wherein the first conductive pattern defines a parasitic capacitor together with the portion of the fourth and fifth regions; and
an OLED configured to receive a driving current from the first transistor,
wherein the second and third transistors are configured to provide an initialization voltage to the first transistor.

US Pat. No. 10,396,138

ORGANIC LIGHT EMITTING DEVICE

LG Display Co., Ltd., Se...

1. An organic light emitting device comprising:an overcoat layer disposed on a substrate and including a plurality of convex parts or a plurality of concave parts, at least one of the convex parts of the overcoat layer having a Full Width at High Maximum (“FWHM”) smaller than a radius of said at least one of the convex parts of the overcoat layer;
a first electrode disposed on the overcoat layer in a direction away from the substrate;
an organic light emitting layer disposed on the first electrode in the direction away farther from the substrate than the first electrode is from the substrate; and
a second electrode disposed on the organic light emitting layer in the direction farther away from the substrate than the organic light emitting layer is from the substrate.

US Pat. No. 10,396,137

TESTING TRANSFER-PRINT MICRO-DEVICES ON WAFER

X-Celeprint Limited, Cor...

1. A method of making and testing transfer-printable micro-devices on a source wafer, comprising:providing the source wafer comprising a plurality of sacrificial portions spatially separated by anchors, the source wafer comprising one or more test contact pads;
providing at least one micro-device disposed entirely over each of the plurality of sacrificial portions, each of the at least one micro-device physically connected to at least one of the anchors;
providing one or more electrical test connections from each of the at least one micro-device to a corresponding test contact pad;
testing the at least one micro-device disposed over each of the plurality of sacrificial portions through the one or more test connections to determine one or more functional micro-devices and one or more faulty micro-devices; and
removing at least a portion of the one or more test connections.

US Pat. No. 10,396,135

OLED SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting display (OLED) substrate, comprising a plurality of pixel regions, at least one of the plurality of pixel regions provided with a pixel driving circuit, and comprising a display region and a connection region; wherein,the OLED substrate comprises:
a base;
a reflective electrode layer disposed on the base, wherein the reflective electrode layer comprises a plurality of reflective electrodes, each of which is correspondingly disposed in one display region;
a pixel defining layer disposed on the reflective electrode layer, wherein the pixel defining layer is provided with a first opening corresponding to the display region and a second opening corresponding to the connection region;
a light-emitting material layer disposed in the first opening;
a display electrode continuously disposed on the light-emitting material layer and in the second opening, wherein the display electrodes in the respective pixel regions are electrically insulated from each other,
wherein the display electrode in each of the at least one pixel region is electrically coupled to the pixel driving circuit in the pixel region through the second opening, and
a barrier layer surrounding one pixel region provided with a pixel driving circuit is disposed on the pixel defining layer, wherein the barrier layer has a thickness of about 20 to 500 nm, and an angle between a top surface of the barrier layer away from the pixel defining layer and a side surface of the barrier layer is greater than or equal to about 60° such that the display electrode is broken at the side surface of the barrier layer to separate a display electrode in the one pixel region from a display electrode in an adjacent pixel region.

US Pat. No. 10,396,134

FLEXIBLE COLOR FILTER INTEGRATED WITH TOUCH SENSOR, ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

DONGWOO FINE-CHEM CO., LD...

1. A manufacturing method of a flexible color filter integrated with a touch sensor, the manufacturing method comprising:forming a separation layer on a carrier substrate;
forming a color filter array on one surface of the separation layer;
forming an overcoating layer on the color filter array;
forming a touch sensor array on the overcoating layer;
forming a refractive index adjusting layer between the color filter array and the touch sensor array;
forming a first protective film on the touch sensor array;
separating the carrier substrate from the separation layer;
forming a second protective film on the other surface of the separation layer;
separating the first protective film, which is formed on the touch sensor array, from the touch sensor array; and
forming a base film on the touch sensor array.

US Pat. No. 10,396,133

TWO-WAY ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A two way organic light emitting diode display device including red, green and blue sub-pixels defined at an array substrate, comprising:a plurality of driving thin film transistors each driving corresponding each of the red, green and blue sub-pixels;
an organic light emitting diode disposed at each sub-pixel and including an anode layer electrically connected to each thin film transistor at the red, green and blue sub-pixels, an organic light emitting layer disposed on the anode layer and emitting white light, and a cathode layer disposed on the organic light emitting layer;
an encapsulating substrate encapsulating the plurality of driving thin film transistors and the organic light emitting diode; and
red, green and blue color filters corresponding to each of the red, green and blue sub-pixels and disposed on the encapsulating substrate,
wherein the anode layer includes a first electrode, a first color control layer corresponding to the red sub-pixel and disposed on the first electrode, a second color control layer corresponding to the green sub-pixel and disposed on the first electrode, a third color control layer corresponding to the blue sub-pixel and disposed on the first electrode, a second electrode disposed on the first, second and third color control layers,
wherein the white light passes through the anode layer and is converted to red, green and blue light in a first direction and passes through the red, green and blue color filters and is converted to red, green and blue light in a second direction, opposite to the first direction.

US Pat. No. 10,396,132

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a display element;
a wavelength conversion element disposed on the display element and comprising a plurality of first wavelength conversion layers and a plurality of second wavelength conversion layers arranged in a first predetermined pattern;
a transparent frame disposed on the wavelength conversion element and having a plurality of air gaps defined on a surface facing the wavelength conversion element, wherein the air gaps are recessed in a thickness direction; and
a color filter element disposed on the transparent frame and comprising a plurality of first wavelength filter layers, a plurality of second wavelength filter layers, and a plurality of third wavelength filter layers arranged in a second predetermined pattern,
wherein the first and second wavelength filter layers are arranged to overlap the first and second wavelength conversion layers, respectively, and
wherein the air gaps are arranged to overlap the first and second wavelength conversion layers.

US Pat. No. 10,396,131

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a substrate;
a pixel electrode over the substrate;
a pixel-defining layer comprising an opening that exposes at least a portion of the pixel electrode;
an intermediate layer, which is over the portion of the pixel electrode exposed by the opening and comprises an organic emission layer;
a counter electrode over the intermediate layer; and
an encapsulating structure, which is over the counter electrode and comprises at least one inorganic layer and at least one organic layer, wherein the at least one inorganic layer is in the opening and extends outside the opening, and wherein the at least one organic layer comprises quantum dots and is formed in the opening such that a thickness of the encapsulating structure in the opening is greater than a thickness of the encapsulating structure outside the opening.

US Pat. No. 10,396,130

DISPLAY SUBSTRATE INCLUDING SUB-ELECTRODES HAVING TRAPEZIUM SHAPE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a display substrate, wherein the display substrate comprises a first electrode formed on a base substrate, the display substrate comprises a plurality of sub-pixels, the first electrode comprises a plurality of sub-electrodes corresponding to the plurality of sub-pixels respectively, wherein the display substrate further comprises: a pixel definition layer arranged on the base substrate on which the plurality of sub-electrodes has been formed, wherein the pixel definition layer is made of an opaque material, and comprises light-transmissible openings corresponding to the sub-electrodes respectively, and an overlapping area between an orthogonal projection of each of the openings on the base substrate and an orthogonal projection of a sub-electrode corresponding to the opening on the base substrate is within a predetermined range, wherein a distance between two crossing points of a first line and each sub-electrode changes when the first line extending in a first direction moves in a second direction within an area of each of the sub-electrodes, the first direction is perpendicular to the second direction, the overlapping area is an effective light-emitting area of each sub-pixel corresponding to a respective sub-electrode, the openings of the pixel definition layer are of an identical shape, each of the openings is a rectangle, each of two opposite sides of the rectangle is parallel to the first direction, the sub-electrodes are trapeziums, and each of two parallel sides of each of the trapeziums is parallel to the first direction, wherein the method comprises:determining a predetermined requirement of the effective light-emitting area of each sub-pixel; and
forming the pixel definition layer on the base substrate on which the plurality of sub-electrodes has been formed, wherein a location of the pixel definition layer on the display substrate is controlled in the second direction, to control the overlapping area between the orthogonal projection of each of the openings on the base substrate and the orthogonal projection of the sub-electrode corresponding to the opening on the base substrate to be within a predetermined range, and the effective light-emitting area of the sub-pixel is enabled to satisfy the predetermined requirement by the overlapping area being the effective light-emitting area of the sub-pixel corresponding to the sub-electrode.

US Pat. No. 10,396,129

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light-emitting display device comprising:a substrate;
a pixel disposed on the substrate and including a plurality of subpixels;
an overcoat layer disposed on the substrate, the overcoat layer including microlenses having a plurality of concave portions concavely formed from an upper surface of the overcoat layer;
an organic electroluminescent device disposed on the overcoat layer;
a bank pattern disposed on the overcoat layer and configured to define a light-emitting area of the plurality of subpixels; and
light filter layers respectively disposed in each of the plurality of subpixels,
wherein some of the plurality of subpixels include both microlenses and the respective light filter layer, and the remaining subpixels of the plurality of subpixels include only the light filter layer,
wherein the organic electroluminescent device disposed in the some of the plurality of subpixels is directly contacted with a surface of the microlenses, and
wherein the organic electroluminescent device disposed in the remaining subpixels is directly contacted with the overcoat layer.

US Pat. No. 10,396,128

ANTI-REFLECTIVE OPTICAL FILM AND BENDABLE DISPLAY APPARATUS INCLUDING THE OPTICAL FILM

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a display panel configured to display an image, the display panel including a folding axis extending in a first direction; and
an optical film disposed over the display panel, the optical film comprising a circular polarizer comprising at least two phase retarders and one polarizer, wherein each of the at least two phase retarders has a slow axis and a fast axis,
wherein the optical film is delineated into four quadrants by the folding axis and a virtual axis extending in a second direction perpendicular to the first direction, and
wherein slow axes of each of the at least two phase retarders are located in a same quadrant of the four quadrants of the optical film.

US Pat. No. 10,396,127

CONSTRUCTIONS COMPRISING STACKED MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a semiconductor construction, comprising:forming a first memory array deck comprising phase change memory containing first memory cells comprising a first chalcogenide, the first memory cells being laterally spaced from one another by a first dielectric material;
forming a second memory array deck over the first memory array deck, the second memory array deck containing second memory cells comprising a second chalcogenide that differs from the first chalcogenide in one or both of composition and thickness, the second memory cells being separated from one another by a second dielectric material, the first and second dielectric materials differing from another in one or more structural parameters selected from differing materials and differing material thicknesses; and
providing a first series of access/sense lines and a second series of access/sense lines, the first series of access/sense lines being disposed vertically between the first memory array deck and the second memory array deck, the lines of the first series of access/sense lines being formed of a single material; the second series of access/sense lines being disposed vertically above the second memory array deck, the lines of the second series of access/sense lines comprising multiple materials.

US Pat. No. 10,396,126

RESISTIVE MEMORY DEVICE WITH ELECTRICAL GATE CONTROL

International Business Ma...

1. A semiconductor device comprising:a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode;
a bottom dielectric layer disposed on the first side of the bottom electrode around the gate structure;
a top dielectric layer disposed on the first side of the top electrode around the gate structure; and
a gate electrode disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode to produce a conductive filament in the resistive switching medium with linear switching relative to the current flow.

US Pat. No. 10,396,125

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Micron Technology, Inc., ...

1. A method, comprising:forming a first memory cell pillar and a second memory cell pillar on a substrate, wherein the first memory cell pillar and the second memory cell pillar are separated by a first gap; and
partially filling the first gap with a gap-seal dielectric to form a seal region wherein the seal region is formed above a buried void that is in contact with at least a portion of opposing side walls of each of the first memory cell pillar and the second memory cell pillar, wherein the seal region comprises abutting portions formed in the first gap; and forming an isolation region above a bottom surface of the seal region between the abutting portions in the first gap.

US Pat. No. 10,396,124

MEMORY CELLS AND DEVICES

XEROX CORPORATION, Norwa...

1. A memory cell comprising a protective layer in the form of a crosslinked mixture of a polyether-modified acrylate oligomer; a polyester acrylic resin; a component selected from the group consisting of a silicone acrylate oligomer and a fluorinated acrylate oligomer; and a photoinitiator, wherein the polyether-modified acrylate oligomer, the polyester acrylic resin, the component, and the photoinitiator are present at a ratio in a range of from about 30/62/4/4 to about 48/49/1/2.

US Pat. No. 10,396,123

TEMPLATING LAYERS FOR PERPENDICULARLY MAGNETIZED HEUSLER FILMS

International Business Ma...

1. A device, comprising:a multi-layered structure that is non-magnetic at room temperature, the structure comprising alternating layers of Co and E, wherein E comprises at least one other element that includes Al, wherein the composition of the structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55; and
a first magnetic layer that includes a Heusler compound, the magnetic layer being in contact with the structure.

US Pat. No. 10,396,122

HALL SENSOR WITH BURIED HALL PLATE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:a substrate having a surface;
a first doped region extending from the surface to a first depth, the first doped region having a first conductivity type;
a second doped region within the first doped region, and extending from the surface to a second depth less than the first depth, the second doped region having a second conductivity type opposite of the first conductivity type;
a first transistor within the second doped region;
a second transistor outside of the first doped region and the second doped region; and
a Hall sensor having a Hall plate in the first doped region below the second depth and free of overlapping the second transistor.

US Pat. No. 10,396,121

FINFETS FOR LIGHT EMITTING DIODE DISPLAYS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming replacement fin structures with a doped core region, on doped substrate material;
forming isolation regions between the replacement fin structures;
forming quantum wells over the replacement fin structures;
forming contacts between each of the replacement fin structures and contacting the substrate material through the isolation regions;
forming a first color emitting region by depositing a first material on at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and
forming a second color emitting region by depositing a second material on another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to have the second material deposited thereon.

US Pat. No. 10,396,120

METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL WAFER AND METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE

SUMCO CORPORATION, Tokyo...

1. A method of producing a semiconductor epitaxial wafer, the method comprising:a first irradiating provided by irradiating a surface of a semiconductor wafer with cluster ions containing hydrogen as a constituent element, to form a modifying layer formed from, as a solid solution, a constituent element of the cluster ions including hydrogen in a surface portion of the semiconductor wafer;
a second irradiating, after the first irradiating, provided by irradiating the semiconductor wafer with electromagnetic waves of a frequency of 300 MHz or more and 3 THz or less, to heat the semiconductor wafer; and
after the second irradiating, forming an epitaxial layer on the modifying layer of the semiconductor wafer.

US Pat. No. 10,396,119

UNIT PIXEL OF IMAGE SENSOR, IMAGE SENSOR INCLUDING THE SAME AND METHOD OF MANUFACTURING IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a unit pixel of an image sensor, the method comprising:forming a photoelectric conversion region in a substrate;
forming, in the substrate, a first floating diffusion region spaced apart from the photoelectric conversion region of the substrate, and a second floating diffusion region spaced apart from the first floating diffusion region;
forming a first recess spaced apart from the first floating diffusion region and the second floating diffusion region by removing a portion of the substrate from a first surface of the substrate;
filling the first recess to form a dual conversion gain (DCG) gate that extends perpendicularly or substantially perpendicularly from the first surface of the substrate; and
forming a conductive layer to fill an inside of the first recess.

US Pat. No. 10,396,118

SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device, comprising:first and second semiconductor substrates;
a photoelectric conversion element outputting a pixel signal based on an incident light, wherein the photoelectric conversion element is disposed in the first semiconductor substrate,
an analog circuit that generates an analog signal based on the pixel signal, wherein a first part of the analog circuit is disposed on the first semiconductor substrate, the first part comprising a transfer transistor, a reset transistor, a select transistor, and an amplification transistor, and wherein a second part of the analog circuit is disposed on the second semiconductor substrate, the second part comprising a current supply transistor for current supply;
a digital circuit on the second semiconductor substrate, wherein the digital circuit converts the analog signal into a digital signal;
a connection connecting the first part of the analog circuit to the second part of the analog circuit; and
a light-shielding metal disposed between the current supply transistor and the photoelectric conversion element.

US Pat. No. 10,396,116

SOLID-STATE IMAGE-CAPTURING ELEMENT AND ELECTRONIC DEVICE

SONY SEMICONDUCTOR SOLUTI...

1. A solid-state image-capturing element, comprising:a floating diffusion;
a floating diffusion wiring connected to the floating diffusion; and
a wiring other than the floating diffusion wiring,
wherein at least a part of a first region between the floating diffusion wiring and the wiring other than the floating diffusion wiring is a hollow region, and
wherein the floating diffusion wiring and the hollow region are not in contact with each other.

US Pat. No. 10,396,115

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE SENSOR AND CAMERA SYSTEM

Sony Corporation, Tokyo ...

1. A light detecting device, comprising:a first substrate having a first surface and a second surface opposite the first surface;
a pixel array unit comprising a plurality of photoelectric conversion elements, wherein the pixel array unit is included in the first substrate;
a second substrate vertically integrated with the first substrate such that the second surface of the first substrate faces the second substrate;
circuitry included in the second substrate, the circuitry configured to at least (a) generate first signals to control operation of the plurality of photoelectric conversion elements, or (b) process second signals corresponding to outputs of the plurality of photoelectric conversion elements;
a first via disposed at least partially within the first substrate and located outside the pixel array unit, the first via extending from the first surface of the first substrate and positioned to establish at least a portion of a first signal path between the first substrate and the second substrate for at least one of the first signals or at least one of the second signals; and
a second via disposed at least partially within the first substrate and located outside the pixel array unit, the second via extending from the first surface of the first substrate and positioned to establish at least a portion of a second signal path between the first substrate and the second substrate for at least one of the first signals or at least one of the second signals, wherein:
the pixel array unit has a first edge side and a second edge side,
the first via is located on the first edge side,
the second via is located on the second edge side, and
the first edge side is perpendicular to the second edge side.

US Pat. No. 10,396,114

METHOD OF FABRICATING LOW CTE INTERPOSER WITHOUT TSV STRUCTURE

Invensas Corporation, Sa...

1. A microelectronic assembly comprising:a dielectric region including a plurality of pads at a first surface, a plurality of contacts at a second surface opposite the first surface, and a back-end-of-line structure;
a plurality of electrically conductive elements coupled to the pads at the first surface of the dielectric region;
a first encapsulant extending above the first surface of the dielectric region, the first encapsulant filling spaces between the plurality of electrically conductive elements and having a surface overlying and facing away from the first surface of the dielectric region, wherein ends of the plurality of electrically conductive elements are at the surface of the first encapsulant; and
a plurality of microelectronic elements each having one or more contacts, wherein each of the contacts of the plurality of microelectronic elements are connected to one or more of the plurality of contacts at the second surface of the dielectric region through an electrically conductive material; and
a second encapsulant extending above the second surface of the dielectric region, the second encapsulant filling spaces between the plurality of microelectronic elements and the dielectric region.

US Pat. No. 10,396,113

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS INCLUDING A PHOTOELECTRIC CONVERSION UNIT DISPOSED BETWEEN ANOTHER PHOTOELECTRIC CONVERSION UNIT AND A PHOTOELECTRIC CONVERSION FILM

Sony Semiconductor Soluti...

1. An imaging device comprising:a substrate having a first side and a second side as a light-incident side, the substrate including:
a first photoelectric conversion unit, and
a second photoelectric conversion unit;
a wiring layer disposed adjacent to the first side of the substrate;
a photoelectric conversion film disposed over the second side of the substrate; and
portions of a conductive material disposed between the photoelectric conversion film and the substrate,
wherein
the conductive material is electrically connected to the substrate,
at least a portion of the second photoelectric conversion unit is disposed between the first photoelectric conversion unit and the photoelectric conversion film, and
the substrate is disposed between the photoelectric conversion film and the wiring layer.

US Pat. No. 10,396,112

IMAGING APPARATUS AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging system, comprising:an optical system; and
an imaging apparatus configured to receive incident light from the optical system and generate an image signal based on the incident light,
a processor configured to perform signal processing on the image signal,
the imaging apparatus including:
an interposer;
a mold disposed on the interposer, wherein the mold includes at least one protrusion in a cross sectional view;
an image sensor disposed on the interposer; and
a translucent member having a first side that receives the incident light and a second side that opposes the first side, wherein the second side is coupled to the mold such that the image sensor is spaced apart from the translucent member,
wherein the image sensor is disposed between the translucent member and the interposer, and
wherein at least a portion of the second side of the translucent member is in direct contact with at least a portion of the at least one protrusion.

US Pat. No. 10,396,110

REDUCTION OF TFT INSTABILITY IN DIGITAL X-RAY DETECTORS

Carestream Health, Inc., ...

1. A digital radiographic detector comprising:a two-dimensional array of imaging pixels, each imaging pixel comprising a photo-sensitive element and a switching element;
read-out circuits electrically coupled to the two-dimensional array of imaging pixels to generate a radiographic image by reading out image data from the two-dimensional array of imaging pixels; and
a housing enclosing the two-dimensional array of imaging pixels and the read-out circuits,
wherein each switching element in the two-dimensional array of imaging pixels comprises an active layer formed from indium-gallium-zinc oxide having a thickness less than about 7 nm.

US Pat. No. 10,396,109

LOCAL STORAGE DEVICE IN HIGH FLUX SEMICONDUCTOR RADIATION DETECTORS AND METHODS OF OPERATING THEREOF

Redlen Technologies, Inc....

1. A detector element circuit in a CT imaging system, comprising:a plurality of radiation sensors for detecting photons attenuated by an object;
a first electronic component configured to determine an energy of photons detected by the plurality of radiation sensors and generate digitized photon count data, wherein the digitized photon count data comprises a digitized count of detected photons in one or more energy bins;
a field programmable gate array (FPGA) configured to receive the digitized photon count data from the first electronic component and generate an output representing the digitized photon count data, wherein the FPGA comprises a FPGA clock configured to control a rate at which the FPGA receives the digitized photon count data from channels of the first electronic component and at which the FPGA outputs the output representing the digitized photon count data; and
a local memory storage configured to receive the output representing the digitized photon count data from the FPGA and comprising a local storage clock configured to control a rate at which the local memory storage generates buffered output data derived from the digitized photon count data,wherein:the FPGA clock and the local storage clock are set such that the FPGA is clocked at a first clock rate and the local storage element outputs the buffered output data at a second clock rate; and
the second clock rate and the first clock rate are selected to reduce bottlenecks or data transfer issues imposed by bandwidth limitations between the local memory storage and a computer of the CT imaging system that is configured to receive the buffered output data from the local memory storage.

US Pat. No. 10,396,108

SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT MANUFACTURING METHOD, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A solid-state imaging element comprising:a photodiode that performs photoelectric conversion on a basis of an amount of incident light;
a photoelectric conversion film that performs photoelectric conversion on the basis of the amount of incident light;
a diffusion layer that has a second polarity and stores an electric charge derived from the photoelectric conversion by the photoelectric conversion film, the second polarity being different from a first polarity of the photodiode; and
an impurity layer that includes impurities having the first polarity,
wherein the photodiode and the diffusion layer are disposed on a same substrate in parallel with each other, and
wherein the impurity layer is disposed below the diffusion layer.

US Pat. No. 10,396,107

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. An avalanche photodiode array comprising a plurality of avalanche photodiodes operating under Geiger mode, each avalanche photodiode of the avalanche photodiode array comprising:a first semiconductor layer having a first conductive type;
a second semiconductor layer disposed over at least a portion of the first semiconductor layer;
a third semiconductor layer disposed over at least a portion of the second semiconductor layer, wherein the third semiconductor has a second conductive type different from the first conductive type, wherein a pn junction is formed between one of
i) the second semiconductor layer and the first semiconductor layer or
ii) the second semiconductor layer and the third semiconductor layer, and
wherein the third semiconductor layer has an impurity concentration higher than an impurity concentration of the second semiconductor layer;
an insulator disposed over at least a portion of a light incident surface of the avalanche photodiode; and
a resistor disposed over a least a portion of the insulator and that extends along a space between adjacent avalanche photodiodes of the plurality of photodiodes, wherein the resistor is connected to the avalanche photodiode, and wherein the resistor includes a linear portion.

US Pat. No. 10,396,106

METHOD FOR PRODUCING A SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP

OSRAM OPTO SEMICONDUCTORS...

1. A method for producing a semiconductor chip, wherein, during a growth process for growing a first semiconductor layer, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer, such that a lateral variation of a material composition of the first semiconductor layer is produced, the lateral variation of the material composition comprising a gradient of a proportion of one or more constituents of the first semiconductor layer.

US Pat. No. 10,396,105

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display substrate comprising:a base substrate comprising a plurality of sub-pixels;
a first switching element disposed on the base substrate and electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction;
a color filter layer disposed on the first switching element and comprising a red color filter, a green color filter, a blue color filter and a white color filter alternately disposed on the plurality of sub-pixels, respectively;
a column spacer disposed on the color filter layer and comprising the same material as that of the white color filter;
an insulation layer disposed on the base substrate on which the color filter layer and the column spacer are disposed; and
a pixel electrode disposed on the insulation layer.

US Pat. No. 10,396,104

DISPLAY SUBSTRATE COMPRISING VERTICAL STORAGE CAPACITOR WITH INCREASED STORAGE CAPACITANCE, METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising a substrate, a plurality of device layers which are formed on the substrate, and an insulating layer which is formed between the device layers,wherein the display substrate further comprises a first electrode, a second electrode, and a vertical storage capacitor which is arranged in the insulating layer;
the vertical storage capacitor comprises a first plate and a second plate which are spaced apart, the first plate is connected with the first electrode, and the second plate is connected with the second electrode; and
the first plate and the second plate are perpendicular with or tilted with respect to the substrate,
wherein the display substrate comprises a plurality of pixel units, each of the pixel units comprises a display region and a peripheral region, and the vertical storage capacitor is arranged in the peripheral region.

US Pat. No. 10,396,103

THIN-FILM NEGATIVE DIFFERENTIAL RESISTANCE AND NEURONAL CIRCUIT

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming source and drain structures of a heterojunction field effect transistor (HJFET) on a first portion of a semiconductor material located on a surface of an insulating substrate, each of the source and drain structures including a hydrogenated silicon layer, a conducting layer, and a sacrificial layer;
forming a base structure of a heterojunction bipolar transistor (HBT) on a second portion of the semiconductor material located on the surface of the insulating substrate, the base structure including a hydrogenated silicon layer, a conducting layer, and a sacrificial layer;
depositing hydrogenated silicon resulting in formation of crystalline hydrogenated silicon adjacent the semiconductor material and formation of first amorphous hydrogenated silicon over the sacrificial layer of the source and drain structures of the HJFET and over the base structure of the HBT;
depositing second amorphous hydrogenated silicon over the sacrificial layer of the source and drain structures of the HJFET and over the base structure of the HBT;
depositing and patterning another conducting layer over the second amorphous hydrogenated silicon; and
etching the exposed second amorphous hydrogenated silicon and the first amorphous hydrogenated silicon to form a gate structure for the HJFET, and emitter and collector structures for the HBT,
wherein the HJFET and the HBT are integrated to create negative differential resistance by forming a lambda diode.

US Pat. No. 10,396,102

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a first scanning line and a second scanning line which extend over a display area and a non-display area;
first semiconductors crossing the first scanning line in the non-display area, the first semiconductors being a in number;
second semiconductors crossing the second scanning line in the non-display area, the second semiconductors being b in number;
third semiconductors crossing the first scanning line in the display area, the third semiconductors being c in number;
fourth semiconductors crossing the second scanning line in the display area, the fourth semiconductors being d in number; and
an insulating film disposed between the first and second semiconductors and the first and second scanning lines, wherein
the first scanning line has a first wiring length in the non-display area,
the second scanning line has a second wiring length different from the first scanning length in the non-display area,
the first scanning line has a third wiring length in the display area,
the second scanning line has a fourth wiring length different from the third wiring length in the display area,
a and b are integers greater than or equal to 2, and a is different from b,
c and d are integers greater than or equal to 2, and c is different from d, and
the first and second semiconductors are both entirely covered with the insulating film.

US Pat. No. 10,396,101

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A method for manufacturing a thin film transistor array panel, the method comprising:forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode;
forming a semiconductor member on the gate insulating layer;
depositing a doping barrier layer on the semiconductor member;
patterning the doping barrier layer to form a barrier pattern overlapping the gate electrode and exposing at least a part of the semiconductor member;
forming an interlayer insulating layer on the barrier pattern and the exposed semiconductor member;
patterning the interlayer insulating layer to form a first hole exposing the barrier pattern;
depositing a conductive layer on the interlayer insulating layer;
patterning the conductive layer to form a data conductor;
removing the barrier pattern; and
forming a passivation layer on the data conductor.

US Pat. No. 10,396,100

ARRAY SUBSTRATE, DISPLAY PANEL AND PIXEL PATCHING METHOD

Shenzhen China Star Optoe...

1. An array substrate, comprising a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors (TFTs), a plurality of pixel electrodes, and a plurality of conductive members, wherein the plurality of data lines and the plurality of gate lines are to cross each other to enclose a plurality of pixel regions, the plurality of conductive members are insulated from each other, and each of the conductive members of the plurality of conductive members corresponds to two adjacent pixel regions of the plurality of pixel regions;in each of the pixel regions of the plurality of pixel regions, a control terminal of a respective TFT is electrically connected with a corresponding gate line of the plurality of gate lines, an input terminal of the respective TFT is electrically connected with a corresponding data line of the plurality of data lines, and an output terminal of the respective TFT is electrically connected with a corresponding pixel electrode of the plurality of pixel electrodes; the output terminal comprises a body, and a first contact and a second contact which are connected with the body, the first contact and one conductive member of the plurality of conductive members extending into a corresponding pixel region of the plurality of pixel regions are disposed to overlap each other and are insulated from each other, the second contact and another conductive member of the plurality of conductive members extending into the corresponding pixel region of the plurality of pixel regions are disposed to overlap each other and are insulated from each other.

US Pat. No. 10,396,099

COPLANAR TYPE OXIDE THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. An oxide thin film transistor (TFT) comprising:a first substrate;
a light shielding layer provided on the first substrate;
a buffer provided on the light shielding layer;
a semiconductor layer provided on the buffer, the semiconductor layer including an oxide semiconductor material and comprising an active area, a first conductor adjacent to a first end of the active area, and a second conductor adjacent to a second end of the active area;
a gate insulation layer covering the semiconductor layer and the buffer;
a gate electrode provided on the gate insulation layer and overlapping a portion of the semiconductor layer; and
a passivation layer covering the gate electrode and the gate insulation layer,
wherein a resistance of the active area is different from a resistance of the first conductor and a resistance of the second conductor,
wherein a width of the active area is substantially the same as a width of the light shielding layer, and wherein the light shielding layer does not receive a gate pulse for turning on the oxide TFT, and
wherein the gate electrode is electrically connected to a gate line of a display device, and wherein the light shielding layer is electrically isolated from the gate line.

US Pat. No. 10,396,098

THIN FILM TRANSISTOR SUBSTRATE, AND DISPLAY PANEL AND DISPLAY DEVICE INCLUDING SAME

LG INNOTEK CO., LTD., Se...

1. A thin film transistor substrate comprising:a substrate;
a switching thin film transistor disposed on the substrate, the switching thin film transistor comprising a first channel layer including a nitride-based semiconductor layer, a first source electrode electrically connected to a first region of the first channel layer, a first drain electrode electrically connected to a second region of the first channel layer, a first gate electrode disposed on the first channel layer, and a first depletion forming layer disposed between the first channel layer and the first gate electrode; and
a driving thin film transistor disposed on the substrate, the driving thin film transistor comprising a second channel layer including a nitride-based semiconductor layer, a second source electrode electrically connected to a first region of the second channel layer, a second drain electrode electrically connected to a second region of the second channel layer, a second gate electrode disposed on the second channel layer, and a second depletion forming layer disposed between the second channel layer and the second gate electrode.

US Pat. No. 10,396,097

METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising steps of:forming a gate electrode layer over an insulating surface;
forming a gate insulating layer over the gate electrode layer;
forming an oxide semiconductor layer over the gate insulating layer;
forming a silicon oxide insulating layer over the oxide semiconductor layer;
forming a first opening and a second opening in the silicon oxide insulating layer so that the silicon oxide insulating layer covers and in contact with a periphery of the oxide semiconductor layer and a first region of the oxide semiconductor layer;
forming a source electrode layer in contact with the oxide semiconductor layer through the first opening; and
forming a drain electrode layer in contact with the oxide semiconductor layer through the second opening,
wherein the first region of the oxide semiconductor layer comprises a channel formation region,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the gate electrode layer is a portion of a gate wiring layer,
wherein the source electrode layer is a portion of a source wiring layer, and
wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate wiring layer, the gate insulating layer, the silicon oxide insulating layer, and the source wiring layer are stacked in this order.

US Pat. No. 10,396,096

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel, comprisinga substrate;
a gate line and a data line on the substrate;
a transistor on the substrate; and
a pixel electrode connected to the transistor,wherein the transistor includes:a gate electrode connected to the gate line,
a semiconductor layer on the gate electrode,
a source electrode on the semiconductor layer and connected to the data line, and
a drain electrode on the semiconductor layer and connected to the pixel electrode,
wherein the semiconductor layer includes:
a first portion overlapping the source electrode,
a second portion overlapping the drain electrode, and
a third portion between the first portion and the second portion,wherein:a thickness of the first portion is a minimum thickness of a portion where the source electrode and the semiconductor layer are overlapped,
a thickness of the second portion is a minimum thickness of a portion where the drain electrode and the semiconductor layer are overlapped,
a thickness of the third portion is a minimum thickness of a portion where the semiconductor is exposed between the source electrode and the drain electrode,
the thickness of the first portion, the thickness of the second portion, and the thickness of the third portion are significantly different from one another,
the thickness of the first portion is equal to a thickness of the semiconductor layer overlapping the data line, and
the thickness of the third portion is less than the thickness of each of the first portion and the second portion.

US Pat. No. 10,396,095

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:hole source patterns;
electron source patterns located between adjacent hole source patterns;
a stack structure over the hole source patterns and the electron source patterns; and
channel layers penetrating the stack structure,
wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

US Pat. No. 10,396,093

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Samsung Electronics Co., ...

1. A three-dimensional (3D) semiconductor memory device comprising:a substrate;
an electrode structure extending in a first direction on the substrate, the electrode structure including a plurality of cell electrodes vertically stacked on the substrate;
a lower string selection electrode and an upper string selection electrode sequentially stacked on the electrode structure;
a first vertical structure penetrating the lower string selection electrodes, the upper string selection electrodes, and the electrode structure;
a second vertical structure spaced apart from the upper string selection electrode such that the second vertical structure does not extend through the upper string selection electrode, the second vertical structure penetrating the lower string selection electrode and the electrode structure; and
a first bit line extending in a second direction different than the first direction, the first bit line intersecting the electrode structure, the first bit line connected in common to the first vertical structure and the second vertical structure.

US Pat. No. 10,396,092

VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A vertical memory device comprising:a substrate;
a gate stack structure on the substrate, the gate stack structure including conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction such that cell regions and inter-cell regions are alternately arranged in the vertical direction;
a channel structure on the substrate, the channel structure penetrating through the gate stack structure in the vertical direction; and
a charge trap structure between the gate stack structure and the channel structure, the charge trap structure and the conductive structures defining memory cells at the cell regions, the charge trap structure configured to selectively store charges, the charge trap structure including an anti-coupling structure in the inter-cell regions for reducing a coupling between the memory cells that neighbor each other in the vertical direction, wherein
the charge trap structure includes a block pattern, a tunnel insulation pattern, and a charge trap pattern,
the block pattern contacts the gate stack structure and extends in the vertical direction,
the tunnel insulation pattern has a cylinder shape,
the tunnel insulation pattern encloses that channel structure and contacts the channel structure,
the charge trap pattern includes a plurality of traps for storing the charges,
the charge trap pattern is between the block pattern and the tunnel insulation pattern,
the charge trap pattern includes a first pattern covering the block pattern and a second pattern covering the tunnel insulation pattern, and
the anti-coupling structure is enclosed by the first pattern and the second pattern in the inter-cell regions.

US Pat. No. 10,396,091

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a plurality of control gate electrodes stacked in a first direction above a substrate;
a first semiconductor layer that extends in the first direction and faces the plurality of control gate electrodes;
a gate insulating layer provided between the control gate electrode and the first semiconductor layer;
a first contact connected to an upper end of the first semiconductor layer;
a second semiconductor layer connected to a lower end of the first semiconductor layer and extending in a second direction intersecting the first direction;
a second contact connected to the second semiconductor layer at its lower end and extending in the first direction, an upper end of the second contact being further from the substrate than an upper surface of the second semiconductor layer; and
a first conductive layer provided above the second contact, an upper surface of the first conductive layer being nearer to the substrate than an upper end of the first contact and a lower surface of the first conductive layer being further from the substrate than a lower end of the first contact, wherein
in the second direction, an end of the first conductive layer closest to the first contact is positioned on a closer side to the first contact than an end of the second contact closest to the first contact, and
the first conductive layer and the second contact are not connected to each other.

US Pat. No. 10,396,090

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a cell stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked over the first region of the substrate;
a channel layer penetrating the cell stack structure;
a peripheral contact plug extending in parallel to the channel layer over the second region of the substrate; and
first dummy conductive rings disposed at the same levels as the conductive patterns, the first dummy conductive rings being spaced apart from the peripheral contact plug and surrounding the peripheral contact plug.

US Pat. No. 10,396,089

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a main surface;
first and second nonvolatile memory cells formed on the main surface of the semiconductor substrate;
the first nonvolatile memory cell including a first memory MISFET for storing data, having a first memory gate electrode, and a first select MISFET for selecting the first memory MISFET, having a first select gate electrode; and
the second nonvolatile memory cell including a second memory MISFET for storing data, having a second memory gate electrode, and a second select MISFET for selecting the second memory MISFET, having a second select gate electrode;
wherein the first and second select gate electrodes extend in a first direction so as to be disposed next to each other in a second direction substantially perpendicular to the first direction in a plan view,
wherein each of the first and second select gate electrodes has a first portion and a second portion;
wherein the second portion is wider than the first portion in the second direction;
wherein the first memory gate electrode extends in the first direction so as to be disposed along a sidewall of the first select gate electrode,
wherein the second memory gate electrode extends in the first direction so as to be disposed along a sidewall of the second select gate electrode,
wherein the first and second memory gate electrodes are disposed between the first select gate electrode and the second select gate electrode,
wherein the first memory gate electrode has a first contact portion extending in the second direction to provide an electrical contact to a first interconnect, and the first contact portion is disposed adjacent the second potion of the first select gate electrode,
wherein the second memory gate electrode has a second contact portion extending in the second direction to provide an electrical contact to a second interconnect, and the second contact portion is disposed adjacent the second potion of the second select gate electrode,
wherein the first contact portion is spaced apart from the second contact portion in the first direction in the plan view, and
wherein a first portion of the first contact portion and a second portion of the second contact portion are overlapped each other in the second direction in the plan view.

US Pat. No. 10,396,088

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

19. A three-dimensional semiconductor memory device, comprising:a stack structure including insulating layers and electrodes that are alternately stacked on a substrate;
a horizontal semiconductor pattern between the substrate and the stack structure;
vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and
a first common source plug and a second common source plug at opposite sides of the stack structure, respectively,
the horizontal semiconductor pattern including a first sidewall adjacent to the first common source plug and a second sidewall adjacent to the second common source plug, and
a first distance between the first sidewall and the first common source plug being different from a second distance between the second sidewall and the second common source plug.

US Pat. No. 10,396,087

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of electrode layers stacked with an insulating body interposed along a stacking direction;
at least two first insulating layers extending in a first direction crossing the stacking direction and being provided in the stacked body from an upper end of the stacked body to a lower end of the stacked body;
at least one second insulating layer extending in the first direction and being provided in the stacked body from the upper end of the stacked body to partway through the stacked body between one of the first insulating layers and another one of the first insulating layers; and
a plurality of semiconductor layers extending in the stacking direction and being provided in the stacked body between the second insulating layer and the one of the first insulating layers and between the second insulating layer and the other one of the first insulating layers,
the semiconductor layers having a first width in the first direction at a first position of the stacking direction, a second width in the first direction at a second position of the stacking direction, and a third width in the first direction at a third position of the stacking direction,
the second position being a position between the first position and the third position,
the second width being wider than the first width and the third width, and
the second insulating layer being provided in a region including a location of a maximum width of the semiconductor layers.

US Pat. No. 10,396,086

VERTICAL NON-VOLATILE MEMORY DEVICE HAVING CHANNEL-ACCOMODATING OPENING FORMED OF ETCH STOP REGION IN LOWER STACK LAYERS

Samsung Electronics Co., ...

1. A non-volatile memory device comprising:a substrate;
a lower insulating layer disposed on the substrate;
a multilayer structure of layers comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening extending vertically from the lower insulating layer, the opening including a first open portion and a second open portion,
wherein the first open portion extends through at least one of the layers of the multilayer structure from the lower insulating layer, and the second open portion is located on the first open portion and extends vertically upwardly from the first open portion in the multilayer structure, and
the opening has a first width at the first open portion and a second width at the second open portion, the second width being less than the first width;
a gate dielectric extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively; and
a channel structure disposed on the gate dielectric within the opening as extending along the inner surface and the lower surface defining the side and the bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the substrate,
wherein the first open portion has a first height,
the second open portion has a second height,
the first height with respect to the first width is less than or equal to 1, and
the second height with respect to the second width is equal to or greater than 1.

US Pat. No. 10,396,085

CIRCULAR PRINTED MEMORY DEVICE WITH ROTATIONAL DETECTION

Xerox Corporation, Norwa...

1. A circular printed memory device, comprising:a base substrate;
a plurality of bottom electrodes arranged in a circular pattern on the base substrate;
a ferroelectric layer on top of the plurality of bottom electrodes; and
a single top electrode on the ferroelectric layer, wherein the ferroelectric layer contacts each one of the plurality of bottom electrodes and the single top electrode.

US Pat. No. 10,396,084

SEMICONDUCTOR DEVICES INCLUDING SELF-ALIGNED ACTIVE REGIONS FOR PLANAR TRANSISTOR ARCHITECTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a first plurality of first mask features from a sacrificial material layer formed above a semiconductor layer of a semiconductor device, said first plurality of first mask features having one or more first lateral spacings of a first value along a width direction, said one or more first lateral spacings being defined by a lithography process;
forming a second plurality of second mask features associated with said first plurality of first mask features by forming a mask material directly adjacent to said first plurality of first mask features, said second plurality of second mask features having one or more second lateral spacings of a second value, said second value being less than said first value;
modifying at least one of said one or more second lateral spacings of said second plurality of second mask features by forming a spacer material directly adjacent to and between associated second mask features; and
forming a plurality of active regions from said semiconductor layer by using said second plurality of second mask features including said modified at least one second lateral spacing, each of said plurality of active regions representing a semiconductor base layer for forming a planar field effect transistor.

US Pat. No. 10,396,083

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a substrate including an active region that extends in a first direction;
a bit line structure running across the active region in a second direction different from the first direction;
a first spacer on a first sidewall of the bit line structure, the first spacer including:
a first sub-spacer on the first sidewall of the bit line structure;
a second sub-spacer spaced apart from the first sub-spacer;
a first air gap between the first sub-spacer and the second sub-spacer; and
a third sub-spacer covering a portion of the first air gap; and
a storage node structure including a storage node contact contacting the active region and a landing pad on the storage node contact, and both the storage node contact and the landing pad covering the first spacer,
wherein the third sub-spacer is disposed on the second sub-spacer at a first vertical point vertically distant from the substrate by a first height, and is disposed on a sidewall of the first sub-spacer at a second vertical point vertically distant from the substrate by a second height, and the second height is higher than the first height; and
wherein a lower surface of the third sub-spacer is on an upper surface of the second sub-spacer in a direction perpendicular to the substrate.

US Pat. No. 10,396,082

MEMORY CELLS HAVING A CONTROLLED-CONDUCTIVITY REGION

Micron Technology, Inc., ...

1. A memory cell, comprising:a transistor having a channel region between a first source/drain region and a second source/drain region; the transistor having a transistor gate extending along the channel region;
a controlled-conductivity region adjacent the first source/drain region, the controlled-conductivity region being along a surface of the transistor gate and separated from the surface of the transistor gate by a dielectric material, the controlled-conductivity region being gated by said transistor gate; the controlled-conductivity region having a low-conductivity mode and a high-conductivity mode; the high-conductivity mode having a conductivity at least 106 greater than a conductivity of the low-conductivity mode; the channel region comprising a first material having a first bandgap, and the controlled-conductivity region comprising a second material having a second bandgap which is greater than the first bandgap; an insulative material over an upper surface of the transistor gate, and a conductive region over the controlled-conductivity region and along the insulative material;
a charge-storage device electrically coupled to the first source/drain region through the controlled-conductivity region; and
a bitline electrically coupled to the second source/drain region.

US Pat. No. 10,396,081

SEMICONDUCTOR DEVICE, ANTENNA SWITCH CIRCUIT, AND WIRELESS COMMUNICATION APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a compound semiconductor upper barrier layer between an insulating film and a compound semiconductor channel layer; and
a compound semiconductor first cap layer between a first electrode and a first low resistance region of the upper barrier layer,
wherein the first electrode extends through the insulating film to the first cap layer, and
wherein the first cap layer is in direct physical contact with the first low resistance region, the first cap layer is of a first electrically conductive type and the first low resistance region is of a second electrically conductive type.

US Pat. No. 10,396,080

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising a semiconductor substrate including a principal surface, whereinthe semiconductor substrate comprises:
a first shallow well of a first conductive type, a second shallow well of a second conductive type, a third shallow well of the first conductive type, and a fourth shallow well of the second conductive type formed in a part of the semiconductor substrate on a side of a principal surface in such a way that they are in regions different from one another when the semiconductor substrate is seen from the principal surface;
a deep well of the second conductive type formed in a region including the first shallow well and the second shallow well, which is a region other than the region in which the third shallow well and the fourth shallow well are formed, the deep well of the second conductive type being formed in a part deeper than the first shallow well and the second shallow well in a depth direction from the principal surface; and
a base material of the first conductive type formed in a region including the third shallow well, the fourth shallow well, and the deep well, the base material of the first conductive type being formed in a part deeper than the third shallow well, the fourth shallow well, and the deep well in the depth direction from the principal surface, the semiconductor device further comprises:
a first transistor pair comprising a field effect transistor of the second conductive type in which a diffusion layer of the second conductive type is formed in a part of the first shallow well on the side of the principal surface and the field effect transistor of the first conductive type in which the diffusion layer of the first conductive type is formed in a part of the second shallow well on the side of the principal surface;
a second transistor pair comprising the field effect transistor of the second conductive type in which the diffusion layer of the second conductive type is formed in a part of the third shallow well on the side of the principal surface and the field effect transistor of the first conductive type in which the diffusion layer of the first conductive type is formed in a part of the fourth shallow well on the side of the principal surface; and
a wire between transistor pairs configured to connect the first transistor pair and the second transistor pair, and
the second shallow well is formed in such a way as to surround a peripheral edge of the region of the first shallow well.

US Pat. No. 10,396,079

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion, the first fin of an NMOS device;
a second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion, the second fin of a PMOS device;
a first dielectric layer comprising silicon and oxygen, the first dielectric layer directly on sidewalls of the lower fin portion of the first fin;
a second dielectric layer comprising silicon and oxygen, the second dielectric layer directly on sidewalls of the lower fin portion of the second fin;
an insulating layer comprising nitrogen, the insulating layer over the first dielectric layer and over the second dielectric layer, and the insulating layer continuous over the first dielectric layer and the second dielectric layer;
a dielectric fill material directly on the insulating layer, wherein the dielectric fill material comprises silicon and oxygen;
a first gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over the dielectric fill material; and
a second gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, the second gate electrode over the dielectric fill material.

US Pat. No. 10,396,078

INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit structure comprising:a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin;
a first source/drain epitaxial region substantially surrounding at least a portion of the first fin;
a spacer substantially surrounding the first source/drain epitaxial region, the spacer including a void in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and
a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

US Pat. No. 10,396,077

PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS

International Business Ma...

1. A method for forming a plurality of semiconductor devices, comprising:forming a first channel region on a first region of a semiconductor layer, the semiconductor layer including a first semiconductor material;
forming a second channel region on a second region of the semiconductor layer by etching a trench in the second region, the trench defined on sides and a bottom by the first semiconductor material, and filling the trench with a second semiconductor material different from the first semiconductor material; and
forming a gate on a nitrogen-containing layer in one or more of the first and second regions.

US Pat. No. 10,396,076

STRUCTURE AND METHOD FOR MULTIPLE THRESHOLD VOLTAGE DEFINITION IN ADVANCED CMOS DEVICE TECHNOLOGY

International Business Ma...

1. A method of forming a semiconductor structure having multiple defined threshold voltages, the method comprising:forming a plurality of field-effect transistor (FET) devices in the semiconductor structure, each of the FET devices comprising a channel and a gate stack formed of one of at least two different work function metals, the gate stack being formed proximate the channel;
forming each gate stack in each of at least a subset of the plurality of FET devices by using a single metal patterning level and two different work function metals in a given region of a same conductivity type in the semiconductor structure; and
varying a valence band offset and a conduction band offset of the channel in each of the at least a subset of the FET devices in the given region of the same conductivity type in the semiconductor structure by controlling a percentage of one or more compositions of a material forming the channel;
wherein a threshold voltage of each of the plurality of FET devices is configured as a function of a type of work function metal forming the gate stack of the corresponding FET device and the percentage of one or more compositions of the material forming the channel.

US Pat. No. 10,396,075

VERY NARROW ASPECT RATIO TRAPPING TRENCH STRUCTURE WITH SMOOTH TRENCH SIDEWALLS

International Business Ma...

1. A semiconductor structure comprising:a plurality of epitaxial semiconductor fins located permanently on, and in direct physical contact with, a semiconductor material portion of a substrate, wherein each epitaxial semiconductor fin is inverted T-shaped having a horizontal bottom portion and a vertically extending upper portion, wherein the horizontal bottom portion is wider than the vertically extending upper portion;
a bottom spacer laterally surrounding, and directly contacting, a sidewall surface of the horizontal bottom portion of each epitaxial semiconductor fin, wherein the bottommost spacer has a bottommost surface directly contacting a topmost surface of the semiconductor material portion of the substrate; and
a semiconductor oxide insulator structure located between each pair of neighboring epitaxial semiconductor fins and neighboring bottom spacers and having a topmost surface located below a topmost surface of each epitaxial semiconductor fin, wherein the semiconductor oxide insulator structure has a horizontal bottom surface that comprises a first portion directly contacting an entirety of a topmost surface of the bottom spacer and a second portion, adjacent to the first portion, directly contacting a portion of the topmost surface of the horizontal bottom portion of each epitaxial semiconductor fin, and wherein the bottom spacer has a width that is less than a width of the semiconductor oxide insulator structure.

US Pat. No. 10,396,074

POWER SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL REGIONS

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and to a second load terminal structure and configured to conduct a load current during a conducting state of the power semiconductor device and to block a load current during a blocking state of the power semiconductor device;
a first cell and a second cell, each cell being configured for controlling the load current and each cell being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; and
a second mesa included in the second cell, the second mesa including: a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region,
wherein each of the first mesa and the second mesa has a total extension of less than 100 nm in a direction perpendicular of the load current within the respective mesa,
wherein the first and second cells are configured to fully deplete the first and second channel regions of mobile charge carriers of the second conductivity type in the conducting state,
wherein the first cell is configured to induce a current path for mobile charge carriers of the first conductivity type in the first channel region in the conducting state and no current path for mobile charge carriers of the first conductivity type in the blocking state,
wherein the power semiconductor device is configured to concurrently induce an accumulation channel for charge carriers of the second conductivity type in the second channel region and a current path for charge carriers of the first conductivity type in the first channel region in a switching state of the power semiconductor device.

US Pat. No. 10,396,073

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first gate structure in a substrate;
a second gate structure in the substrate and adjacent to the first gate structure;
a shallow trench isolation (STI) under the first gate structure, wherein the STI comprises a bottom portion and a top portion directly under the first gate structure, two sidewalls of the top portion are aligned with two sidewalls of the first gate structure, and a topmost surface of the top portion is even with or higher than a bottom surface of the second gate structure and lower than a top surface of the substrate; and
a mask on each of the first gate structure and the second gate structure, wherein a top surface of the mask is even with the top surface of the substrate.

US Pat. No. 10,396,072

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

9. A semiconductor device having a first region and a second region surrounding the first region, comprising:a first electrode;
a first semiconductor layer of a first conductivity type on the first electrode;
a second semiconductor layer of the first conductivity type on the first semiconductor layer;
a second electrode on the second semiconductor layer;
at least one first PIN diode comprising a portion of the first and second semiconductor layers located in the first region; and
at least one second PIN diode comprising a portion of the first and second semiconductor layers located in the second region, wherein
the at least one second PIN diode surrounds the first region,
the at least one PIN diode further comprises:
a third semiconductor layer of a second conductivity type on the second semiconductor layer;
a fourth semiconductor layer of the second conductivity type on the third semiconductor layer; and
a fifth semiconductor layer of the first conductivity type extending inwardly of the second semiconductor layer from the third semiconductor layer, and
the fifth semiconductor layer surrounds at least a portion of the second semiconductor layer contacting the third semiconductor layer, wherein the first conductivity type is different from the second conductivity type.

US Pat. No. 10,396,071

SEMICONDUCTOR DEVICE HAVING A SENSE DIODE PORTION

FUJI ELECTRIC CO., LTD., ...

8. The semiconductor device according to claim 1, further comprising:an edge termination structure portion that is provided surrounding the main transistor portion and the main diode portion on the upper surface of the semiconductor substrate, wherein
the sense diode portion is arranged on an outer side of the edge termination structure portion on the upper surface of the semiconductor substrate.

US Pat. No. 10,396,070

FIN-SHAPED FIELD EFFECT TRANSISTOR AND CAPACITOR STRUCTURES

AVAGO TECHNOLOGIES INTERN...

1. A semiconductor device, comprising:a first semiconductor substrate;
a second semiconductor substrate located within a first region of the first semiconductor substrate, the second semiconductor substrate having a doping concentration different from that of the first semiconductor substrate;
a first fin structure formed on the second semiconductor substrate;
a first insulation layer disposed on the first fin structure and in contact with the second semiconductor substrate, the first insulation layer comprising one or more dielectric layers;
an isolation layer disposed adjacent to sidewalls of the first insulation layer, the isolation layer being in contact with the second semiconductor substrate and the first semiconductor substrate; and
a first conductor structure disposed on the first insulation layer and within the sidewalls of the first insulation layer, the one or more dielectric layers of the first insulation layer being in direct contact with the first conductor structure and a top surface of the second semiconductor substrate.

US Pat. No. 10,396,068

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

ALi Corporation, Hsinchu...

1. An electrostatic discharge protection device, comprising:an electrostatic discharge protection unit, coupled between a signal input terminal and a system voltage terminal, wherein when a voltage level of a signal received by the signal input terminal reaches an electrostatic discharge protection level, the electrostatic discharge protection unit transmits the signal from the signal input terminal to the system voltage terminal; and
a control circuit, coupled to a control terminal of the electrostatic discharge protection unit, and controlling a conduction state between the signal input terminal and the system voltage terminal through the electrostatic discharge protection unit, wherein the control circuit comprises:
a first voltage providing circuit comprising a first transistor and a first impedance providing circuit, wherein a first terminal, a second terminal and a control terminal of the first transistor are respectively coupled to the first impedance providing circuit, the signal input terminal and the control terminal of the electrostatic discharge protection unit, wherein a first terminal of the first impedance providing circuit is coupled to the system voltage terminal and a second terminal of the first impedance providing circuit is coupled to the first terminal of the first transistor and the control terminal of the electrostatic discharge protection unit; and
a second voltage providing circuit comprising a second transistor and a second impedance providing circuit, wherein a first terminal, a second terminal and a control terminal of the second transistor are respectively coupled to the system voltage terminal, a first terminal of the second impedance providing circuit and the control terminal of the electrostatic discharge protection unit, wherein the first terminal of the second impedance providing circuit is further coupled to the control terminal of the electrostatic discharge protection unit and a second terminal of the second impedance providing circuit is coupled to the signal input terminal,
wherein the control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the electrostatic discharge protection unit, and to make the electrostatic discharge protection unit not transmit the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the electrostatic discharge protection level.

US Pat. No. 10,396,067

SEMICONDUCTOR DEVICE HAVING A LOAD CURRENT COMPONENT AND A SENSOR COMPONENT

Infineon Technologies AG,...

1. A semiconductor device comprising a semiconductor body having a first surface and a second surface opposite to the first surface, the semiconductor body comprising:a load current component comprising a load current transistor area; and
a sensor component comprising a sensor transistor area,
wherein the load current transistor area and the sensor transistor area share a same transistor unit construction,
wherein the load current transistor area comprises first and second transistor area parts and the sensor transistor area comprises a third transistor area part,
wherein the first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part,
wherein the second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.

US Pat. No. 10,396,066

ELECTRO-STATIC DISCHARGE TRANSISTOR ARRAY APPARATUS

SEMICONDUCTOR MFG. INTL. ...

1. An electro-static discharge (ESD) transistor array apparatus, comprising:a semiconductor substrate, the semiconductor substrate comprising:
a semiconductor layer,
a doped region on the semiconductor layer, and
a substrate contact region,
wherein the doped region and the substrate contact region are isolated, and the substrate contact region comprises at least a first contact region part separately disposed on two sides of the doped region;
multiple gates arranged in parallel on the doped region, where a direction of extension of the multiple gates is in parallel with a direction of extension of the first contact region part; and
a dissipation layer contact member disposed on each gate of the multiple gates along the direction of extension of the gate, wherein a density of the dissipation layer contact member decreases with a decrease in a distance from the gate on which the dissipation layer contact member is located to the first contact region part on a corresponding side.

US Pat. No. 10,396,065

SEMICONDUCTOR DEVICE HAVING A TEMPERATURE-DETECTING DIODE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:an insulated gate semiconductor element that makes a current flow in a thickness direction of a semiconductor substrate;
a temperature detecting diode that detects a temperature of the insulated gate semiconductor element and is provided in an active region of the insulated gate semiconductor element;
an anode metal wiring line that is provided on a first main surface side of the semiconductor substrate and is connected to an anode of the temperature detecting diode;
a cathode metal wiring line that is provided on the first main surface side of the semiconductor substrate and is connected to a cathode of the temperature detecting diode, the anode metal wiring line and the cathode metal wiring line each being not connected to the insulated gate semiconductor element;
a first semiconductor region of a second conductivity type, formed on the semiconductor substrate;
a first insulating film that is formed on the first semiconductor region between the anode and cathode metal wiring lines and the semiconductor substrate;
a first semiconductor layer that is formed directly between the first insulating film and the anode metal wiring line and spaced apart from the temperature detecting diode, and is connected to the anode metal wiring line;
a second semiconductor layer that is formed directly between the first insulating film and the cathode metal wiring line and spaced apart from the temperature detecting diode, and is connected to the cathode metal wiring line;
a first capacitor that has the first insulating film, as a first capacitive component region, between the first semiconductor layer and the semiconductor substrate;
a second capacitor that has the first insulating film, as a second capacitive component region, between the second semiconductor layer and the semiconductor substrate; and an interlayer insulating film disposed directly on the first semiconductor region in a gap in the first insulating film.

US Pat. No. 10,396,064

LAYOUT PATTERN FOR SRAM AND MANUFACTURING METHODS THEREOF

UNITED MICROELECTRONICS C...

1. A static random access memory (SRAM), comprising:a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern comprising:
a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second pull-up transistor (PL2) and a second pull-down transistor (PD2);
a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the second access transistor has a second gate length, and the first gate length is different from the second gate length; and
a first read port transistor (RPD) and a second read port transistor (RPG) connected to each other, wherein the first read port transistor is connected to the latch circuit, and a gate of the first read port transistor is electrically connected to a gate of the first pull-down transistor, wherein the gate of the first pull-down transistor (PD1) directly contacts the gate of the first read port transistor (RPD), and wherein the gate of the first pull-down transistor (PD1) and the gate of the first read port transistor (RPD) are arranged along a same symmetry axis.

US Pat. No. 10,396,063

CIRCUIT WITH COMBINED CELLS AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming an integrated circuit, comprising:providing a first design layout having a first cell layout and a second cell layout using electronic design automation software;
the step of providing the first cell layout comprising forming:
a first higher power line and a first lower power line;
a first output pin;
at least one first up transistor formed to electrically couple the first output pin to the first higher power line; and
at least one first down transistor formed to electrically couple the first output pin to the first lower power line;
the step of providing the second cell layout comprising forming:
a second higher power line and a second lower power line;
a second output pin;
at least one second up transistor formed to electrically couple the second output pin to the second higher power line;
at least one second down transistor formed to electrically couple the second output pin to the second lower power line;
the at least one second up transistor and the at least one second down transistor comprising a first gate line;
generating a third cell layout according to the first cell layout and the second cell layout using the electronic design automation software, comprising:
non-selectively electrically coupling the first gate line to the first output pin to form a first node; and
generating a second design layout by replacing the first cell layout and the second cell layout in the first design layout with the third cell layout using the electronic design automation software; and
generating a netlist for fabricating the integrated circuit according to the second design layout using the electronic design automation software to minimize at least one of routing resources, wire lengths, via counts and layout area required for fabricating the integrated circuit;
wherein the step of generating of the third cell layout further comprises:
combining a first source or drain region of one of the at least one first up transistor and the at least one first down transistor with a second source or drain region of one of the at least one second up transistor and the at least one second down transistor of a same conductivity type as the first source or drain region,
during the combining, the first higher power line and the second higher power line being combined into a higher power line and the first lower power line and second lower power line being combined into a lower power line; and
forming a second node by forming: a first conductive line overlapped with one of the first source or drain region and the second source or drain region and non-selectively electrically coupled to the one of the first source or drain region and the second source or drain region and to one of the higher power line and lower power line corresponding to the one of the first source or drain region and the second source or drain region, and a second conductive line in substantially the same direction as the first conductive line and non-selectively electrically coupled to the one of the higher power line and the lower power line; and
forming a plurality of gate finger lines non-selectively electrically coupled to each other, one of the plurality of gate finger lines being adjacent to the one of the first source or drain region and the second source or drain region so as to enable forming of the second node; and
wherein the first source or drain region and the second source or drain region are combined through joining, the first source or drain region and the second source or drain region are joined to opposite sides of a second gate line, and the second conductive line overlaps with the other of the first source or drain region and the second source or drain region.

US Pat. No. 10,396,062

MICRO LIGHT EMITTING DIODE DISPLAY PANEL

PlayNitride Inc., Tainan...

1. A micro light emitting diode display panel, comprising:a substrate including a plurality of pixel regions arranged in a display area;
a plurality of control elements, disposed on the substrate and in the display area; and
a plurality of light emitting units, disposed on the substrate and in the display area, wherein each of the light emitting units is electrically connected to one of the control elements, and each of the light emitting units comprises a plurality of micro light emitting diodes, wherein the plurality of micro light emitting diodes at least have a red micro light emitting diode, a green micro light emitting diode and a blue micro light emitting diode, and a shortest distance between the green micro light emitting diode and the one of the control elements is less than a shortest distance between the blue micro light emitting diode and the one of the control elements,
wherein the pixel regions comprise a plurality of first pixel regions and a plurality of second pixel regions, the first pixel regions are sequentially arranged in a first direction, the second pixel regions are sequentially arranged in the first direction, and the first pixel regions and the second pixel regions are alternately arranged in a second direction perpendicular to the first direction, wherein an arrangement between one of the control elements and one of the light emitting units in each of the first pixel regions is different from an arrangement between one of the control elements and one of the light emitting units in each of the second pixel regions.

US Pat. No. 10,396,061

TRANSPARENT ELECTRONICS FOR INVISIBLE SMART DUST APPLICATIONS

International Business Ma...

1. A transparent semiconductor nanochip comprising:a transparent substrate;
a transparent semiconductor material layer located on a surface of the transparent substrate and comprising one or more transparent semiconductor devices disposed thereon; and
a transparent back-end-of-the-line (BEOL) structure disposed entirely above the transparent semiconductor material layer and the one or more transparent semiconductor devices, wherein the transparent BEOL structure comprises at least one interconnect level containing at least one electrically conductive and transparent metallic structure embedded in a transparent interconnect dielectric material layer, and wherein the transparent semiconductor nanochip is invisible to visible light and cannot be seen by a human eye.

US Pat. No. 10,396,060

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:an interconnect layer;
an electrical element, a direction from the interconnect layer toward the electrical element being a first direction;
an optical element, a direction from the interconnect layer toward the optical element being aligned with the first direction, a second direction from the electrical element toward the optical element crossing the first direction; and
a resin portion including a first partial region, the first partial region being between the electrical element and the optical element,
at least a portion of the optical element not overlapping the resin portion in the first direction,
the first partial region having a first resin portion surface and a second resin portion surface, the second resin portion surface being opposite to the first resin portion surface and opposing the interconnect layer,
the optical element having a first optical element surface and a second optical element surface, the second optical element surface being opposite to the first optical element surface and opposing the interconnect layer, the optical element including at least one of a light emitter or a light receiver, the at least one of the light emitter or the light receiver being provided at the second optical element surface,
a distance along the first direction between the interconnect layer and the first resin portion surface being longer than a distance along the first direction between the interconnect layer and the first optical element surface,
wherein the optical element includes:
an antireflective layer; and
a transparent layer provided between the antireflective layer and the interconnect layer, and
a refractive index of the antireflective layer is greater than 1 and lower than a refractive index of the transparent layer.

US Pat. No. 10,396,059

MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A stacked system of microelectronic devices, comprising:a first microelectronic device having a first die, a first bottom side, and first metal leads coupled to the first bottom side;
a second microelectronic device having a second die, a top side, a lateral side, a second bottom side, a second bottom side bond-site, and second metal leads coupled to the second bottom side, the second leads including a lateral portion that laterally projects away from the lateral side, a tiered portion that laterally projects towards the lateral side, and an angled portion between the lateral portion and the tiered portion that positions the tiered portion above the lateral portion;
metal solder bumps between individual first leads and individual tiered portions of the second leads;
a support substrate adjacent to and spaced apart from the second bottom side, the support substrate having a substrate bond-site; and
a substrate connector attached to the substrate bond-site and to the second bottom side.

US Pat. No. 10,396,058

LIGHT-EMITTING DEVICE

EPISTAR CORPORATION, Hsi...

1. A light-emitting device comprising:a first light-emitting structure having an active layer;
a second light-emitting structure;
a third light-emitting structure;
a transparent material enclosing the first light-emitting structure, the second light-emitting structure, and the third light-emitting structure;
a first conductive structure overlapping the active layer in a cross-sectional view, and having a first connecting pad connected to the first light-emitting structure, a second connecting pad connected to the second light-emitting structure, and a connecting portion suspended in the transparent material; and
a second conductive structure not overlapping the first conductive structure, and connecting the second light-emitting structure with the third light-emitting structure,
wherein the second light-emitting structure is electrically arranged between the first light-emitting structure and the third light-emitting structure, and
wherein the first connecting pad the second connecting pad, and the connecting portion are formed by a same material.

US Pat. No. 10,396,057

HALF-BRIDGE POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME

NISSAN ARC, LTD., Kanaga...

1. A switching control half-bridge power semiconductor module comprising:an insulating wiring substrate comprising:
a single insulating plate, and
a positive electrode wiring conductor, a bridge wiring conductor, and multiple negative electrode wiring conductors disposed on or above the insulating plate while being electrically isolated from one another;
at least one high side power semiconductor device having a rear surface electrode bonded onto the positive electrode wiring conductor;
at least one low side power semiconductor device having a rear surface electrode bonded onto the bridge wiring conductor;
a stand-up multiple-legged bridge terminal connected to the bridge wiring conductor;
a stand-up multiple-legged high side terminal disposed between the high side power semiconductor device and the stand-up multiple-legged bridge terminal, and connected to the positive electrode wiring conductor;
a stand-up multiple-legged low side terminal disposed between the stand-up multiple-legged bridge terminal and the low side power semiconductor device, and connected to the negative electrode wiring conductors;
a high side connector connecting a front surface main electrode of the high side power semiconductor device to the stand-up multiple-legged bridge terminal; and
a low side connector connecting a front surface main electrode of the low side power semiconductor device to the stand-up multiple-legged low side terminal.

US Pat. No. 10,396,055

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES

Intel Corporation, Santa...

1. A method comprising:forming a stack comprising multiple integrated circuit (IC) dies including a first IC die and a second IC die;
coupling to the first IC die a first end of a first wire;
anchoring a second end of the first wire to the stack, wherein the first wire comprises the second end and a first portion including the first end;
while the first end is coupled to the first IC die and the second end is anchored to the stack, disposing a package material around the multiple IC dies and the first portion;
after disposing the package material around the multiple IC die, separating the second end from the first portion, including exposing another end of the first portion at a first surface of the package material; and
coupling the first IC die to the second IC die, including forming a redistribution layer on the first surface, wherein the redistribution layer is coupled to the second IC die and to the other end of the first portion.

US Pat. No. 10,396,054

BONDING ALIGNMENT TOOL

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus, comprising:a bonding system configured to bond at least two wafers, the bonding system having a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers;
sensors configured to detect data related to a flag-out condition of the flags of the plurality of flags, wherein the data comprises one or more time durations for removing the flags of the plurality of flags; and
at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers, wherein
a first wafer of the at least two wafers comprises at least two alignment markings, and the bonding system is configured to align the first wafer of the at least wafers with a second wafer of the at least two wafers based on the at least two alignment markings, and wherein the at least one processor is configured to:
calculate a velocity by which each alignment marker of the at least two alignment markers is removed,
generate an indicator of misalignment of the at least two wafers based on the calculated velocity, and
determine the at least two wafers are misaligned based on a difference between the velocities by which the each alignment marker of the at least two alignment markers is removed.

US Pat. No. 10,396,053

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

General Electric Company,...

1. A reconfigured semiconductor logic device comprising:a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon; and
a redistribution layer comprising:
an insulating layer disposed on the active surface of the semiconductor logic device; and
a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer, wherein the plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer, and wherein the plurality of discrete terminal pads are larger than the plurality of I/O pads;
wherein the plurality of discrete terminal pads comprise:
a plurality of signal terminal pads electrically coupled to signal I/O pads of the plurality of I/O pads;
a plurality of power terminal pads electrically coupled to power I/O pads of the plurality of I/O pads; and
a plurality of ground terminal pads electrically coupled to ground I/O pads of the plurality of I/O pads.

US Pat. No. 10,396,052

UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:a first semiconductor die having a major surface with non-overlapping first and second regions;
a second semiconductor die spaced apart from the first semiconductor die;
an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the first pillars are configured to carry electricity between the first and second semiconductor dies; and
an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the second pillars are electrically insulated from one or both of the first and second semiconductor dies,
wherein—
a minimum lateral spacing between the first pillars is different than a minimum lateral spacing between the second pillars by at least 5%, and
an average width of the first pillars is different than an average width of the second pillars by at least 2%.

US Pat. No. 10,396,049

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip; and
a first interconnection member disposed on the active surface of the semiconductor chip,
wherein the first interconnection member includes a redistribution layer electrically connected to the connection pad,
the semiconductor chip includes a passivation layer having an opening exposing, at least a portion of the connection pad,
the redistribution layer of the first interconnection member is connected to the connection pad through a via,
the via is disposed on at least a portion of the passivation layer and the connection pad, and
the passivation layer covers a side surface of the connection pad and a portion of a lower surface of the connection pad, wherein S2/S1 is within a range of 0.2 to 0.8, where S1 is an entire area of a surface of the passivation layer contacting the via while surrounding the opening of the passivation layer and S2 is an area of the via covering the passivation layer.

US Pat. No. 10,396,048

CONTACT HOLE STRUCTURE AND FABRICATING METHOD OF CONTACT HOLE AND FUSE HOLE

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a dielectric layer, comprising a silicon oxide layer and a silicon nitride layer over the silicon oxide layer;
a conductive pad disposed in the dielectric layer;
a mask layer disposed on the dielectric layer; and
a contact hole formed in the dielectric layer and the mask layer, the contact hole being directly over the conductive pad and exposing the conductive pad, wherein the contact hole comprises a first portion and a second portion, wherein the first portion is over the second portion and has a width larger than a width of the second portion.

US Pat. No. 10,396,047

SEMICONDUCTOR PACKAGE WITH PACKAGE COMPONENTS DISPOSED ON A PACKAGE SUBSTRATE WITHIN A FOOTPRINT OF A DIE

Intel Corporation, Santa...

1. An apparatus, comprising:a package substrate having a first side and a second side opposite the first side, wherein an area of the first side of the package substrate within which a die is to be disposed forms a footprint of the die;
a voltage reference plane coupled with the second side of the package substrate, wherein at least a portion of the voltage reference plane is disposed within the footprint of the die, to provide a reference voltage to one or more components to be disposed within the footprint of the die on the second side of the substrate, and to shield the one or more components from electromagnetic interference; and one or more air core inductor (ACI) structures disposed inside the package substrate within the footprint of the die, and extended substantially between the first and second sides of the substrate.

US Pat. No. 10,396,046

SUBSTRATE ASSEMBLY WITH MAGNETIC FEATURE

Intel Corporation, Santa...

1. A substrate assembly, comprising:a base substrate;
one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR); and
a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements, and wherein a portion of the magnetic feature is located between the IVR and a portion of a coil associated with the IVR, wherein the coil includes:
a first conductive element that extends from the first side of the base substrate to the second side of the base substrate, wherein the first conductive element is located on a first side of the magnetic feature;
a second conductive element that extends from the first side of the base substrate to the second side of the base substrate, wherein the second conductive element is located on a second side of the magnetic feature, the second side of the magnetic feature opposite to the first side of the magnetic feature; and
a coil element that is coupled to the first conductive element and the second conductive element on the second side of the base substrate.

US Pat. No. 10,396,045

METAL ON BOTH SIDES OF THE TRANSISTOR INTEGRATED WITH MAGNETIC INDUCTORS

Intel Corporation, Santa...

1. An apparatus comprising:a circuit structure comprising a device stratum comprising a plurality of transistor devices each comprising a first side and an opposite second side;
an inductor disposed on the second side of the structure; and
a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side, wherein the contact does not extend entirely through the device stratum.

US Pat. No. 10,396,043

TIMING BASED CAMOUFLAGE CIRCUIT

Cisco Technology, Inc., ...

1. An apparatus comprising:a first plurality of components forming a first circuit adapted to perform a first function that is dependent on a first timing behavior of the first circuit, wherein the first timing behavior of the first circuit includes a timing violation during operation, and wherein a first geometry of the first plurality of components is substantially the same as a second geometry of a second plurality of components of a second circuit adapted to perform a second function that is dependent on a second timing behavior, and wherein the second timing behavior does not include the timing violation during operation.

US Pat. No. 10,396,042

DIELECTRIC CRACK STOP FOR ADVANCED INTERCONNECTS

International Business Ma...

1. A semiconductor structure comprising:an interconnect level located on a surface of a substrate and comprising at least one wiring region comprising an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region comprising a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material and laterally surrounding the at least one wiring region, wherein an entirety of the crack stop dielectric material is devoid of an electrically conductive metal or metal alloy.

US Pat. No. 10,396,041

HIGH YIELD SUBSTRATE ASSEMBLY

Invensas Corporation, Sa...

1. An article of manufacture comprising:a reusable substrate assembly configured for formation of integrated circuit device structures thereon, said reusable substrate assembly comprising:
a plurality of substrates bonded indirectly to one another only on edges of the plurality of substrates,
crystalline layers formed on the plurality of substrates; and
trenches formed in the plurality of substrates defining bordered regions of the crystalline layers that are formed on the plurality of substrates;wherein said reusable substrate assembly is configured for use with integrated circuit manufacturing equipment designed to process wafers larger than individual instances of the plurality of substrates, wherein bonds between the plurality of substrates are operable to relieve thermal stress across the reusable substrate assembly during integrated circuit processing manufacturing, and wherein said reusable substrate assembly is in contact with bottoms of the plurality of substrates and is configured to be removed from said plurality of substrates.

US Pat. No. 10,396,040

METHOD FOR FABRICATING ELECTRONIC PACKAGE HAVING A PROTRUDING BARRIER FRAME

Siliconware Precision Ind...

1. A method for fabricating an electronic package, comprising:disposing a plurality of electronic elements and a barrier frame on a carrier with the barrier frame positioned between adjacent two of the plurality of electronic elements;
forming on the carrier an encapsulant encapsulating the plurality of electronic elements and the barrier frame with a portion of the barrier frame protruding from the encapsulant; and
disposing a shielding element on the encapsulant with the shielding element being in contact with the portion of the barrier frame protruding from the encapsulant.

US Pat. No. 10,396,039

SEMICONDUCTOR PACKAGE

Mitsubishi Electric Corpo...

1. A semiconductor package comprising:an electronic component;
a lead frame that includes a die pad, on which the electronic component is fixed, and terminals being internal wires, the die pad being formed of a material of the lead frame and connected to a terminal for heat radiation of a printed circuit board;
a wire to connect the electronic component and the terminals;
molded resin to seal the electronic component and the wire;
a second terminal that is disposed to surround the terminals on a package plane and can be grounded, the second terminal being included in the lead frame, and being a one-piece terminal having a top surface exposed from an upper surface of the molded resin, and having a bottom surface exposed from a lower surface of the molded resin opposite to the upper surface and coplanar with the lower surface of the molded resin; and
a conductive member having an upper portion that covers the upper surface of the molded resin and side portions that cover side surfaces of the molded resin, the second terminal being spaced from the side portions of the conductive member and extending such that the top surface contacts the upper portion.

US Pat. No. 10,396,038

FLEXIBLE PACKAGING ARCHITECTURE

Intel Corporation, Santa...

1. A package comprising:a plurality of silicon dies embedded in a flexible substrate;
a flexible interposer layer over the embedded dies;
a thin film thermal distribution layer over the substrate opposite the flexible interposer layer, the flexible substrate being shaped with the dies and the interposer to a curved shape and cured so that the flexible substrate holds its shape; and
a second plurality of silicon dies embedded in a second flexible substrate, the second flexible substrate being in electrical contact with the flexible interposer opposite the flexible substrate.

US Pat. No. 10,396,037

FAN-OUT SEMICONDUCTOR DEVICE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor device comprising:a fan-out semiconductor package including:
a first connection member including one or more insulating layers and having a first through-hole penetrating through the one or more insulating layer,
a semiconductor chip disposed in the first through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface,
a first encapsulant encapsulating at least portions of the semiconductor chip, and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip,
the first and second connection members including, respectively, redistribution layers electrically connected to the connection pads; and
a fan-out component package including:
a third connection member including one or more insulating layers and a distribution layer, and having a second through-hole penetrating through the one or more insulating layers of the third connection member,
a first passive component disposed in the second through-hole,
a second encapsulant encapsulating at least portions of the first passive component, and
a fourth connection member disposed on the third connection member and the first passive component, and including a redistribution layer,
the third and fourth connection members including, respectively, redistribution layers electrically connected to the connection pads,
wherein the fan-out semiconductor package is stacked on the fan-out component package so that the second connection member faces the fourth connection member,
the first connection member, the second connection member, the fourth connection member, and the third connection member are stacked in an order of the first connection member, the second connection member, the fourth connection member, and the third connection member,
the redistribution layer of the fourth connection member is disposed on an electrical path between the first passive component and one of the redistribution layer of the first connection member, the redistribution layer of the second connection member, the redistribution layer of the third connection member, or the connection pads of the semiconductor chip, and
the connection pads are electrically connected to the first passive component through the second and fourth connection members.

US Pat. No. 10,396,036

RLINK-GROUND SHIELDING ATTACHMENT STRUCTURES AND SHADOW VOIDING FOR DATA SIGNAL CONTACTS OF PACKAGE DEVICES; VERTICAL GROUND SHIELDING STRUCTURES AND SHIELD FENCING OF VERTICAL DATA SIGNAL INTERCONNECTS OF PACKAGE DEVICES; AND GROUND SHIELDING FOR ELECTRO

Intel Corporation, Santa...

1. A vertically shielded vertical data signal interconnect package device comprising:a first interconnect level having:
upper level receive data signal contacts receive contact and ground isolation contacts isolation contact forming a first shielding pattern in a first zone;
upper level transmit data signal contacts transmit contact and ground isolation contacts isolation contact forming a second shielding pattern in a second zone; and
ground isolation contacts isolation contact forming a third shielding pattern in a third zone, wherein the third zone is located beside and between the first zone and the second zone.

US Pat. No. 10,396,035

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS PENETRATING UPPER ADJACENT ELECTRODES

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional semiconductor device comprising:a substrate having a cell array region and a contact region;
a stacked structure comprising a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region;
vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string;
contact plugs in the contact region;
a bit line landing plug on each vertical structure;
a dummy landing plug on an uppermost electrode of the plurality of electrodes comprised in the stacked structure; and
a contact landing plug on each contact plug,
wherein for each pair of immediately neighboring electrodes of the plurality of electrodes including an upper electrode and a lower electrode below the upper electrode, a corresponding one of the contact plugs contacts the lower electrode and penetrates and is electrically insulated from the upper electrode.

US Pat. No. 10,396,034

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate;
a gate structure and a source/drain region disposed on the substrate;
a first etch stop layer conformally formed on the gate structure and the source/drain region;
a first interlayer insulating layer disposed on the first etch stop layer over the gate structure and the source/drain region;
a first contact plug disposed in the first interlayer insulating layer and the first etch stop layer to connect the source/drain region, with a top surface of the first contact plug and a top surface of the first interlayer insulating layer being at a first level;
a second etch stop layer disposed on the first interlayer insulating layer and the first contact plug;
a second interlayer insulating layer disposed on the second etch stop layer;
a second contact plug disposed in the first etch stop layer, the first interlayer insulating layer, the second etch stop layer and the second interlayer insulating layer to connect the gate structure, with a top surface of the second contact plug and a top surface of the second interlayer insulating layer being at a second level, higher than the first level;
a first metal line disposed on the second interlayer insulating layer, the first metal line including a metal via disposed in the second interlayer insulating layer and the second etch stop layer to connect the first contact plug, with a top surface of the metal via being at the second level; and
a second metal line disposed on the second interlayer insulating layer to directly connect the second contact plug at the second level.

US Pat. No. 10,396,033

FIRST POWER BUSES AND SECOND POWER BUSES EXTENDING IN A FIRST DIRECTION

QUALCOMM Incorporated, S...

1. An apparatus, comprising:a first plurality of first power buses extending in a first direction and within a first range, the first range extending in a second direction;
a second plurality of first power buses extending in the first direction and within the first range, the first plurality of first power buses and the second plurality of first power buses being powered at a first supply voltage;
a plurality of second power buses extending in the first direction within the first range and a second range, the second range extending in the first direction, the plurality of second power buses being powered at a second supply voltage,
wherein the first plurality of first power buses, the second plurality of first power buses, and the plurality of second power buses are in a conductive layer, and
the plurality of second power buses is between the first plurality of first power buses and the second plurality of first power buses, in the first direction.

US Pat. No. 10,396,032

SEMICONDUCTOR STRUCTURES

Semiconductor Manufacturi...

1. A semiconductor structure, comprising:a semiconductor substrate;
a plurality of first underlying metal layers and a plurality of second underlying metal layers formed in the substrate, the plurality of the first underlying metal layers being interlaced with the plurality of the second underlying metal layers;
a plurality of first metal layers formed on a surface of the substrate, a cross-sectional shape of the first metal layers having a narrower upper edge and a wider lower edge;
a plurality of second metal layers formed on the surface of the substrate, a cross-sectional shape of the second metal layers having a wider upper edge and a narrower lower edge, wherein:
the plurality of the first metal layers are interlaced with the plurality of the second metal layers;
the narrower upper edge of the plurality of first metal layers is leveled with the wider upper edge of the plurality of second underlying metal layers; and
the wider lower edge of the plurality of first metal layers is leveled with the narrower lower edge of the plurality of second underlying metal layers; and
a plurality of sidewall structures formed on the surface of the substrate, each between a first metal layer and a second metal layer.

US Pat. No. 10,396,031

ELECTRONIC DEVICE WITH DELAMINATION RESISTANT WIRING BOARD

Renesas Electronics Corpo...

1. An electronic device functioning as a wireless communication unit, comprising:a wiring board having a front surface and a back surface; and
a semiconductor device mounted over the front surface of the wiring board,
wherein the wiring board includes
a front-surface wiring layer formed at the front surface,
an internal wiring layer formed inside the wiring board, and
a back-surface wiring layer formed at the back surface,
wherein the internal wiring layer includes
a board-member exposed region from which a board member is exposed, and
a first internal wide pattern enclosing the board-member exposed region,
wherein the back-surface wiring layer includes
a back-surface wide pattern, and
a plurality of back-surface terminal patterns formed away from and around the back-surface wide pattern,
wherein a first region is formed between the back-surface wide pattern and a group of the back-surface terminal patterns in plan view, and the first region has a first distance between the back-surface wide pattern and the group of the back-surface terminal patterns,
wherein a second region is formed between the back-surface wide pattern and another group of the back-surface terminal patterns in plan view, and the second region has a second distance between the back-surface wide pattern and the another group of the back-surface terminal patterns, and
wherein the first region overlaps with the board-member exposed region in plan view.

US Pat. No. 10,396,030

SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a first electrode including a first main portion, and a first extension that extends from the first main portion; and
a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion,
wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

US Pat. No. 10,396,029

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a power MISFET which drives a load;
a driver transistor which outputs a signal to drive a gate of the power MISFET;
a signal line which electrically connects an output of the driver transistor to the gate of the power MISFET;
at least one source wiring, each source wiring being connected to a respective source region of the power MISFET and being formed in a first wiring layer; and
at least one drain wiring, each drain wiring being connected to a respective drain region of the power MISFET and being formed in the first wiring layer,
wherein the gate is formed of at least one gate electrode, each gate electrode extending in a first direction and being formed between a corresponding source region and a corresponding drain region of the power MISFET,
the corresponding source region and the corresponding drain region are adjacent to each other in a second direction perpendicular to the first direction,
the first direction is a gate width direction of the at least one gate electrode,
both ends of each gate electrode in the first direction, formed between the corresponding source region and the corresponding drain region, are electrically connected to each other by a respective first metal wiring formed in the first wiring layer, which is different from a wiring layer in which the gate electrode is formed,
the signal line includes each first metal wiring,
each first metal wiring is formed between an adjacent pair of the source wiring and the drain wiring, and
each first metal wiring, each source wiring and each drain wiring are formed in the first wiring layer.

US Pat. No. 10,396,028

SEMICONDUCTOR PACKAGE AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor package comprising:a prefabricated copper section;
two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and
a back metal coupled to the two or more MOSFETs;
wherein the prefabricated copper section is coupled directly to the back metal and is configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs;
wherein the prefabricated copper section is coupled to the back metal using one of a silver sintering paste, solder, electrically conductive epoxy, and any combination thereof.

US Pat. No. 10,396,027

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A structure, comprising:a contact structure between gate structures and which comprises:
contact trenches in interlevel dielectric material;
a liner material within the contact trenches; and
a conductive material on the liner material; and
an insulator material on a planarized surface of the conductive material, the liner material, the gate structures and exposed portions of the interlevel dielectric material;
a metal material in an opening in the insulator material and on a surface of the insulator material; and
an insulator layer within the opening and on the metal material.

US Pat. No. 10,396,026

PRECUT METAL LINES

GLOBALFOUNDRIES INC., Gr...

7. A semiconductor device, comprising:a first dielectric layer;
a plurality of first metal lines disposed within the first dielectric layer, wherein each of the plurality of first metal lines has a first orientation;
a capping layer disposed on the plurality of first metal lines;
an etch stop layer disposed above the capping layer and the first dielectric layer;
a second dielectric layer disposed on the etch stop layer;
a plurality of second metal lines disposed within the second dielectric layer, wherein each of the plurality of second metal lines has a second orientation perpendicular to the first orientation;
a dielectric region disposed between two collinear metal lines of the plurality of second metal lines;
a plurality of air gaps disposed in the second dielectric layer, wherein each air gap is disposed between two adjacent second metal lines;
a via connecting a first metal line and a second metal line; and
a plurality of third metal lines disposed within the first dielectric layer, wherein each of the third metal lines has the second orientation and a top of each of the third metal lines is below a bottom of each of the first metal lines.

US Pat. No. 10,396,024

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a first insulating layer including a first through-hole formed through the first insulating layer in a thickness direction;
a wiring layer formed on a lower surface of the first insulating layer; and
a via wiring filled in the first through-hole and connected to the wiring layer, the via wiring having such a shape that it gradually becomes thinner from one side close to the lower surface of the first insulating layer toward the other side close to an upper surface of the first insulating layer, the via wiring including a first recess formed in an upper end surface of the via wiring,
wherein
an upper end portion of the via wiring is an electrode pad for electric connection with an electronic component,
the upper end surface of the via wiring is positioned to be substantially planar with the upper surface of the first insulating layer,
the first insulating layer includes a second recess formed so as to expose an outer side surface of the upper end portion of the via wiring and overlap the first through-hole as seen in a plan view,
the upper end portion of the via wiring is formed so as to protrude upward from a bottom of the second recess, and
the upper end portion of the via wiring is surrounded by the first insulating layer forming an inner side surface of the second recess as seen in a plan view.

US Pat. No. 10,396,023

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a multi-layered substrate provided with an insulating plate and a circuit plate,
a semiconductor chip provided with a front surface and a back surface, the front surface having a main electrode and a control electrode formed thereon, and the back surface being fixed to the circuit plate,
a first wiring substrate which includes a first conductive member, is placed so as to face the main electrode, and is connected electrically to the first conductive member,
a second wiring substrate which includes a second conductive member, is placed so as to face the control electrode, and has an opening extending through the second wiring substrate so that the first wiring substrate is disposed inside the opening,
a conductive post provided with one end and another end, the one end being connected electrically and mechanically to the control electrode, and the another end being connected electrically and mechanically to the second conductive member, and
a seal resin sealing the multi-layered substrate, the semiconductor chip, the first wiring substrate, and the second wiring substrate,
wherein the first conductive member is thicker than the second conductive member,
the first wiring substrate is disposed inside the opening of the second wiring substrate so that a side surface of the first wiring substrate faces an inner side surface of the second wiring substrate defined by the opening of the second wiring substrate, and
the first conductive member of the first wiring substrate and the second conductive member of the second wiring substrate are not connected electrically to each other.

US Pat. No. 10,396,021

FABRICATION METHOD OF LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE

Siliconware Precision Ind...

1. A fabrication method of a layer structure for mounting a semiconductor device, comprising the steps of:providing a conductive layer having a first surface and a second surface opposite to the first surface;
forming a plurality of first conductive elements on the first surface of the conductive layer, forming a first encapsulant on the first surface of the conductive layer to encapsulate the first conductive elements, and forming a plurality of second conductive elements on the second surface of the conductive layer for providing a base material, wherein the base material comprises: the conductive layer having the first surface having the first conductive elements formed thereon and the second surface opposite to the first surface and having the second conductive elements formed thereon, and the first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements and having a first bottom surface adjacent to the conductive layer and a first top surface opposite to the first bottom surface;
partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and
forming a second encapsulant on the first bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, wherein the second encapsulant has a second top surface adjacent to the first encapsulant and a second bottom surface opposite to the second top surface.

US Pat. No. 10,396,019

MOLDED INTELLIGENT POWER MODULE AND METHOD OF MAKING THE SAME

ALPHA AND OMEGA SEMICONDU...

1. A method for fabricating an intelligent power module (IPM) for driving a motor, the method comprising the steps of:providing a leadframe comprising a first, second, third and fourth die paddles and a plurality of leads;
providing a first transistor attached to a top surface of the first die paddle, a second transistor attached to a top surface of the second die paddle, a third transistor attached to a top surface of the third die paddle, a fourth, fifth, and sixth transistors attached to a top surface of the fourth die paddle;
electrically connecting the first, second, third, fourth, fifth, and sixth transistors to the plurality of leads respectively;
providing a metal slug and a plurality of spacers; wherein the plurality of spacers are between the metal slug and the first, second, third and fourth die paddles; and wherein the plurality of spacers separate the metal slug from contacting the first, second, third, and fourth die paddles; and
applying a molding process to form a molding encapsulation enclosing the first, second, third, and fourth die paddles, the first, second, third, fourth, fifth, and sixth transistors and the plurality of spacers.

US Pat. No. 10,396,018

MULTI-PHASE HALF BRIDGE DRIVER PACKAGE AND METHODS OF MANUFACTURE

Infineon Technologies AG,...

1. A semiconductor package, comprising:a plurality of half bridges each comprising a first power transistor die disposed over a second power transistor die;
a separate first metal lead attached to a bottom side of the first power transistor die and to a top side of the second power transistor die of each half bridge;
a separate or single second metal lead attached to a top side of the first power transistor die of each half bridge; and
a mold compound in which each half bridge and each metal lead are embedded,
wherein each first metal lead protrudes from a side face of the mold compound to form a half bridge output terminal,
wherein each second metal lead protrudes from a side face of the mold compound to form a first half bridge power terminal,
wherein at least part of a bottom side of the second power transistor die of each half bridge is not covered by the mold compound at a first main face of the mold compound to form a second half bridge power terminal,
wherein at least part of each second metal lead is not covered by the mold compound at a second main face of the mold compound opposite the first main face,
wherein each first metal lead has a notch which exposes one or more bond pads at the top side of the second power transistor die attached to that first metal lead.

US Pat. No. 10,396,017

LEAD FRAME

SHINKO ELECTRIC INDUSTRIE...

1. A lead frame comprising:a frame part;
a lead extending inward from the frame part and having a front surface and a back surface; and
an external connection terminal formed at a part of the lead in an extension direction and protruding from the back surface of the lead,
wherein the lead includes a pentagonal shape in a cross-section where the front surface of the lead faces upward, the pentagonal shape having a quadrangular main body part and a triangular protrusion protruding from a lower surface of the main body part, and the external connection terminal is directly coupled at one end side to the frame part, and the protrusion is formed at the lead in an inner region extending inwardly relative to the frame part from another end side of the external connection terminal opposite to the one end side directly coupled to the frame part toward a tip end of the lead disposed distally relative to the frame part.

US Pat. No. 10,396,016

LEADFRAME INDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A device, comprising:a die including a circuit therein;
a first leadframe connected to the die, the first leadframe having a plurality of leads on outer edges thereof; and
a second leadframe in a form of an electrically conductive clip at least partially encompassing the die, the die being positioned between the first and second leadframes, the second leadframe having one or more turns that form at least one inductor, and the second leadframe being connected to the first leadframe to electrically couple the at least one inductor with the circuit.

US Pat. No. 10,396,015

DIE ATTACH METHODS AND SEMICONDUCTOR DEVICES MANUFACTURED BASED ON SUCH METHODS

Infineon Technologies AG,...

1. A semiconductor device, comprising:a carrier;
a semiconductor die; and
a die attach material arranged between the carrier and the semiconductor die,
wherein a fillet height of the die attach material is less than about 95% of a height of the semiconductor die,
wherein a maximum extension of the die attach material over edges of a main surface of the semiconductor die facing the die attach material is less than about 200 micrometers,
wherein a thermal conductivity of the die attach material is greater than about 0.5 W/(m ·K),
wherein the die attach material comprises a polymeric material and at least one of electrically conductive and thermally conductive filler particles, and
wherein the filler particles have a diameter of greater than 50 nm and less than 9 ?m.

US Pat. No. 10,396,013

ADVANCED THROUGH SUBSTRATE VIA METALLIZATION IN THREE DIMENSIONAL SEMICONDUCTOR INTEGRATION

International Business Ma...

1. An integrated circuit device comprising:a substrate including a device layer;
a through substrate via in the substrate, the through substrate via having vertical sidewalls and a horizontal bottom, the substrate having a horizontal field area surrounding the through substrate via;
a metallic barrier layer disposed on the sidewalls of the through substrate via, wherein a surface portion of the metallic barrier layer has been converted to a nitride surface layer;
a wetting enhancement liner layer disposed on the nitride surface layer, wherein the nitride surface layer enhances nucleation of the wetting enhancement liner layer;
a via metal layer disposed on the wetting enhancement liner layer, filling the through substrate via and having a recess in an upper portion, wherein the recess forms a bowl-like depression in the via metal layer, the via metal layer having a first height equal to a height of one of the vertical sidewalls of the through substrate via at a peripheral region and a second height less than the first height at a central region, wherein the wetting enhancement liner layer improves adhesion of the via metal layer;
a second barrier layer disposed over the recess, a top surface of the metallic barrier layer, a top surface of the nitride surface layer and a top surface of the wetting enhancement liner layer; and
a contact metal layer over the second barrier layer and in the recess and creating a contact, wherein the contact metal layer is copper and the copper has a bamboo-like grain pattern,
wherein a material of the wetting enhancement liner layer is different from a material of the second barrier layer, and
wherein a material of the second barrier layer is different from a material of the contact metal layer.

US Pat. No. 10,396,012

ADVANCED THROUGH SUBSTRATE VIA METALLIZATION IN THREE DIMENSIONAL SEMICONDUCTOR INTEGRATION

International Business Ma...

1. A method for fabricating a through substrate via structure, comprising:providing a through substrate via in a substrate, the through substrate via having vertical sidewalls and a horizontal bottom, the substrate having a horizontal field area surrounding the through substrate via;
depositing a first metallic barrier layer on the sidewalls of the through substrate via;
performing a nitridation process to convert a surface portion of the first metallic barrier layer to a nitrided surface layer, wherein the nitrided surface layer enhances a nucleation of a subsequent deposition;
depositing a wetting enhancement liner layer over the nitrided surface layer;
depositing a via metal layer over the wetting enhancement liner layer to fill the through substrate via;
performing a selective etch selective to the via metal layer to create a recess in the via metal layer in the through substrate via, wherein the recess forms a bowl-like depression in the via metal layer, the via metal layer having a first height equal to a height of each of the vertical sidewalls of the through substrate via at a peripheral region and a second height less than the first height vertical sidewalls of the through substrate via at a central region;
depositing a second barrier layer over the recess, a top surface of the first metallic barrier layer and a top surface of the nitrided surface layer and a top surface of the wetting enhancement liner layer; and
patterning a contact metal layer over the second barrier layer filling the recess and creating a contact,
wherein a material of the wetting enhancement liner layer is different from a material of the second barrier layer.

US Pat. No. 10,396,011

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package including a module substrate, a thinned flip chip die, and a mold compound component, wherein:
the thinned flip chip die comprises a device layer with electronic components, a dielectric layer over an upper surface of the device layer, and a plurality of interconnects extending from a lower surface of the device layer and coupled to an upper surface of the module substrate;
the mold compound component resides over the upper surface of the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity above the upper surface of the thinned flip chip die; and
the mold compound component is not over the thinned flip chip die;
depositing a thermally conductive film over at least the upper surface of the thinned flip chip die at a bottom of the cavity; and
applying a thermally enhanced mold compound component over at least a portion of the thermally conductive film to fill the cavity.

US Pat. No. 10,396,010

ONBOARD CONTROL DEVICE

HITACHI AUTOMOTIVE SYSTEM...

1. An onboard control device, comprising:a circuit board;
a member provided to face the circuit board;
a heat generating electronic component mounted on a side of the member;
a heat dissipating material provided between the heat generating electronic component and the member;
a sealing resin configured that when filled the sealing resin is between the circuit board and the member in a direction orthogonal to a major surface of the circuit board, and substantially seals the circuit board and the heat generating electronic component,
wherein a space between the member and the circuit board is at least a part of a range where the heat dissipating material is not provided, and narrower than a range where the heat dissipating material is provided; and
the member comprises a projecting portion projecting toward the circuit board in at least a part of the range where the heat dissipating material is not provided, wherein
the projection portion functions as a breakwater for the heat dissipating material.

US Pat. No. 10,396,009

HEAT DISSIPATION MATERIAL AND METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THEREOF

FUJITSU LIMITED, Kawasak...

1. An electronic device comprising:a heating element;
a heat dissipation element; and
a heat dissipation material configured to be placed between the heating element and the heat dissipation element, and to include
a plurality of linearly-structured objects of carbon atoms including a first terminal part and a second terminal part,
a first diamond-like carbon layer configured to cover the first terminal part of each of the plurality of linearly-structured objects,
a coating film covering a side surface for the first diamond-like carbon layer and the plurality of linearly-structured objects, and
a filler layer configured to be permeated between the plurality of linearly-structured objects.

US Pat. No. 10,396,008

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element comprising electrodes on both surfaces thereof;
a first metal plate and a second metal plate which interpose the first semiconductor element therebetween, the first metal plate and the second metal plate respectively being bonded to the electrodes of the first semiconductor element with respective first soldered portions;
a third metal plate and a fourth metal plate which interpose the second semiconductor element therebetween, the third metal plate and the fourth metal plate respectively being bonded to the electrodes of the second semiconductor element with respective second soldered portions; and
a resin package in which the first semiconductor element and the second semiconductor element are embedded, the first metal plate and the third metal plate being exposed at one surface of the resin package, and the second metal plate and the fourth metal plate being exposed at an opposite surface to the one surface of the resin package,
wherein
a first joint is provided at an edge of the first metal plate,
a second joint is provided at an edge of the fourth metal plate,
the first joint overlaps with the second joint as seen along a direction in which the first metal plate and the first semiconductor element are stacked,
the first joint and the second joint are bonded with a third soldered portion,
a total sum of thicknesses of the first soldered portions between the first metal plate and the second metal plate is different from a thickness of the third soldered portion between the first joint and the second joint, a solidifying point of a thinner one of the first soldered portions and the third soldered portion is higher than a solidifying point of a thicker one of the first soldered portions and the third soldered portion, and
a total sum of thicknesses of the second soldered portions between the third metal plate and the fourth metal plate is different from the thickness of the third soldered portion between the first joint and the second joint, a solidifying point of a thinner one of the second soldered portions and the third soldered portion is higher than a solidifying point of a thicker one of the second soldered portions and the third soldered portion.

US Pat. No. 10,396,007

SEMICONDUCTOR PACKAGE WITH PLATEABLE ENCAPSULANT AND A METHOD FOR MANUFACTURING THE SAME

Infineon Technologies AG,...

1. A package, comprising:a first encapsulant configured so that electrically conductive material is plateable thereon;
a second encapsulant configured so that electrically conductive material is not plateable thereon;
a redistribution layer at least partially encapsulated by one of the first encapsulant and the second encapsulant;wherein at least part of an exposed outer lateral sidewall of the first encapsulant is plated with the electrically conductive material for providing an electrically conductive coupling to the redistribution layer,wherein the first encapsulate comprise an active portion which is activated for enabling plating of the electrically conductive material and a non-active portion which is deactivated for disabling plating of the electrically conductive material.

US Pat. No. 10,396,006

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

NXP USA, Inc., Austin, T...

1. A method for producing a molded air cavity package, the method comprising:providing a base flange having a flange frontside, a flange backside opposite the flange frontside as taken along a centerline of the molded air cavity package, and retention posts extending from the flange frontside in a direction opposite the flange backside;
further providing a leadframe comprising retention tabs and package leads;
positioning the base flange adjacent the leadframe such that the retention posts are received through openings provided in the retention tabs; and
after positioning the base flange adjacent the leadframe, forming a molded package body bonded to the base flange and enveloping, at least in substantial part, the retention posts and the retention tabs.

US Pat. No. 10,396,005

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a semiconductor chip;
an encapsulant encapsulating the semiconductor chip; and
a connection member disposed on at least one surface of the semiconductor chip and including an insulating layer and a plurality of redistribution layers electrically connected to the semiconductor chip,
wherein at least one of the plurality of redistribution layers includes a plurality of degassing holes penetrating therethrough in a thickness direction, and
the plurality of degassing holes include a plurality of first holes, a plurality of second holes having a size smaller than that of the first holes, and a plurality of third holes having a size smaller than that of the second holes.

US Pat. No. 10,396,004

REDUCTION OF CROSS TALK IN WLCSP'S THROUGH LASER DRILLED TECHNIQUE

Dialog Semiconductor (UK)...

1. A wafer level chip scale package comprising:a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of said silicon wafer;
a plurality of underbump metal (UBM) layers each contacting one of said plurality of RDL traces through openings in a second polymer layer over said first polymer layer;
a plurality of solder bumps each on a UBM layer;
a metal plating layer under said first polymer layer and not contacting any of said plurality of RDL traces; and
at least one separator lying between at least two of said plurality of RDL traces wherein said at least one separator comprises metal fencing in an area between two neighboring RDL traces wherein said metal fencing makes electrical contact with said metal plating layer.

US Pat. No. 10,396,003

STRESS TUNED STIFFENERS FOR MICRO ELECTRONICS PACKAGE WARPAGE CONTROL

Micron Technology, Inc., ...

1. A method of forming a semiconductor device assembly, the method comprising:determining a first warpage of a first semiconductor device assembly comprised of a semiconductor device, a substrate, and a mold compound;
tuning a stiffener member based on the first warpage in order to form a second semiconductor device assembly having a second warpage, the second semiconductor device assembly comprised of the semiconductor device, the substrate, the mold compound, and the stiffener member;
forming the second semiconductor device assembly comprised of the semiconductor device positioned on the substrate, the mold compound encapsulating at least the semiconductor device, and the stiffener member;
wherein tuning the stiffener member further comprises configuring the stiffener member to have a desired coefficient of thermal expansion; and
wherein tuning the stiffener member further comprises varying a density of the stiffener member to obtain the desired coefficient of thermal expansion.

US Pat. No. 10,396,002

ELECTRONIC COMPONENT STORAGE SUBSTRATE AND HOUSING PACKAGE

KYOCERA CORPORATION, Kyo...

1. An electronic component storage substrate comprising:a substrate;
a rectangular frame-shaped substrate bank section provided on the substrate and comprising a comer portion comprising four comers; and
a metal layer provided on a top surface of the substrate bank section; wherein
an upper surface of the corner portion of the substrate bank section comprises an inclined portion slanted downward from an inner surface of the substrate bank section toward an outer surface, and a thickness of the corner portion cut along a diagonal direction in the plan view the substrate gradually increases from the top surface toward the substrate.

US Pat. No. 10,396,001

OFFSET TEST PADS FOR WLCSP FINAL TEST

Adesto Technologies Corpo...

1. A device configured for wafer level chip scale packaging (WLCSP), the device comprising:a) a first pad;
b) a test pad offset from the first pad;
c) a first redistribution layer (RDL) path that connects the first pad to the test pad with no other pad connections therebetween; and
d) a second RDL path that connects the test pad to a solder ball.

US Pat. No. 10,396,000

TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS

INTERNATIONAL BUSINESS MA...

1. A method of forming a test structure of a fin-type field effect transistor (FinFET) formed in an active region of a substrate, the method comprising:forming a first conducting layer;
electrically coupling the first conducting layer to a dummy gate of the FinFET;
forming a second conducting layer;
electrically coupling the second conducing layer to a first isolation region of the substrate, wherein the first isolation region electrically isolates the FinFET from other devices of the active region of the substrate;
electrically coupling the second conductive layer to a second isolation region of the substrate, wherein the second isolation region electrically isolates the active region of the substrate from another active region of the substrate;
forming a third conducting layer; and
electrically coupling the third conducting layer to the dummy gate of the FinFET;
wherein the formation of the first conducing layer and the second conducting layer define boundaries of the first isolation region of the substrate;
wherein the formation of the second conducting layer and the third conducting layer define boundaries of the second isolation region of the substrate;
measuring a first capacitance between the first conducting layer and the second conducting layer;
measuring a second capacitance between the second conducting layer and the third conducting layer;
classifying a type of the first isolation region as a local shallow trench isolation (STI) type or a deep STI type based on a magnitude of the first capacitance; and
classifying a type of the second isolation region as a local STI type or a deep STI type based on a magnitude of the second capacitance;
wherein the local STI type comprises a local STI type depth dimension;
wherein the deep STI type comprise a deep STI type depth dimension;
wherein the local STI type depth dimension is less than the deep STI type depth dimension.

US Pat. No. 10,395,999

METHOD FOR MONITORING FIN REMOVAL

UNITED MICROELECTRONICS C...

1. A method for monitoring fin removal, comprising:providing a substrate at least having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction;
forming a material layer on the substrate to cover the first fins and the second fins;
identically patterning the first fins and the second fins using a first pattern and a second pattern on the material layer respectively for simultaneously removing parts of the first fins and parts of the second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and
monitoring the first fin features using the second fin features.

US Pat. No. 10,395,998

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a development part configured to develop a substrate on which an exposed resist film is formed to form a pattern on a surface of the substrate;
a heat plate configured to mount and heat the substrate on which the resist film is formed on the heat plate before the development is performed;
a distribution acquisition part configured to optically acquire a size distribution of a dimension of the pattern on the surface of the substrate; and
a determination part configured to determine whether an abnormality has occurred in a mounting state of the substrate on the heat plate, based on the size distribution of the dimension of the pattern,
wherein, when it is determined that an abnormality has occurred in a mounting state of a first substrate on the heat plate, the determination part estimates a cause of the abnormality in the mounting state of the first substrate based on a size distribution of a dimension of a pattern acquired from a second substrate transferred to the heat plate.

US Pat. No. 10,395,997

SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A device, comprising:an accommodating groove defining an accommodating space, the accommodating groove including a chuck;
an upper cover disposed above the accommodating groove;
a balloon disposed on the upper cover and between the accommodating groove and the upper cover; and
an adhesive layer attached directly on to the balloon;
wherein the balloon is configured to bulge by a pressure difference between the balloon and the accommodating space.

US Pat. No. 10,395,996

METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE CONTAINING HIGH MOBILITY SEMICONDUCTOR CHANNEL MATERIALS

International Business Ma...

1. A semiconductor structure comprising:a semiconductor base substrate having semiconductor back gate pedestal portions extending upwards from a semiconductor material surface of the semiconductor base substrate, wherein the semiconductor back gate pedestal portions are in direct physical contact with the semiconductor material surface of the semiconductor base substrate:
an insulator layer portion located on each semiconductor back gate pedestal portion;
III-V compound semiconductor material portions located on a first set of the insulator layer portions; and
germanium-containing material portions located on a second set of the insulator layer portions, wherein a trench isolation structure is present between each III-V compound semiconductor material portion and each germanium-containing material portion.

US Pat. No. 10,395,995

DUAL LINER SILICIDE

INTERNATIONAL BUSINESS MA...

1. A dual silicide complementary metal oxide semiconductor (CMOS) device comprising:a P-type device including source and drain regions on opposite sides of a first gate structure and being disposed over a substrate, the source and drain regions including a horizontal portion and a vertical portion;
a first silicided liner formed over the horizontal portion and the vertical portion of the source and drain regions of the P-type device to provide a first silicided liner having only one bent portion;
an N-type device including source and drain regions on opposite sides of a second gate structure and being disposed over the substrate, the source and drain regions including a horizontal portion and a vertical portion;
a second silicided liner formed only on a portion of the horizontal portion of the source and drain regions of the N-type device adjacent to the second gate structure;
a dielectric layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the P-type device and the N-type device;
a conformal protection layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the N-type device, said at least portion of the horizontal portion of the source and drain regions being covered by the conformal protection layer being a remainder of the horizontal portion extending from the second silicided liner to the vertical portion of the source and drain regions;
first contacts connecting to the first silicided liner through the high-k dielectric layer; and
second contacts connecting to the second silicided liner through the high-k dielectric layer and the conformal protection layer.

US Pat. No. 10,395,994

EQUAL SPACER FORMATION ON SEMICONDUCTOR DEVICE

International Business Ma...

1. A method for fabricating a semiconductor device having field-effect transistors (FETs) associated with regions of the device, comprising:epitaxially growing a first semiconductor material in a first source/drain region within a first region of the device associated with a first FET;
selectively forming a capping layer on the first semiconductor material, including forming a layer over the first region and a second region of the device associated with a second FET that reacts with the first semiconductor material to form the capping layer; and
epitaxially growing a second semiconductor material in a second source/drain region within the second region of the device, the capping layer capping the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material.

US Pat. No. 10,395,993

METHODS AND STRUCTURE TO FORM HIGH K METAL GATE STACK WITH SINGLE WORK-FUNCTION METAL

International Business Ma...

8. A method comprising:forming an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening;
forming a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening;
forming a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer; and
filling the first opening and the second opening with a bulk fill material above and in direct contact with the shared work function metal.

US Pat. No. 10,395,992

VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS

International Business Ma...

1. A method for fabricating a vertical field-effect transistor (FET) structure, the method comprising:prior to depositing a gate of a first vertical FET on a semiconductor substrate, depositing a first layer of the first vertical FET on the semiconductor substrate;
prior to depositing a gate of a second vertical FET on the semiconductor substrate, depositing a second layer of the second vertical FET on the semiconductor substrate;
etching the first layer of the first vertical FET to a lower height than the second layer of the second vertical FET;
depositing a gate material of both the first vertical FET and the second vertical FET;
etching the gate material of both the first vertical FET and the second vertical FET to a co-planar height; and
wherein the first layer and the second layer comprise a source.

US Pat. No. 10,395,991

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;
transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate;
removing part of the ILD layer without exposing a top surface of the substrate between the first metal gate and the second metal gate to form a recess;
forming a first spacer and a second spacer in the recess between the first metal gate and the second metal gate;
performing a first etching process by using the first spacer and the second spacer as a mask to remove the ILD layer under the first spacer and the second spacer for forming a first contact hole; and
performing a second etching process to extend the first contact hole into a second contact hole.

US Pat. No. 10,395,990

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer;
a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and
a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction,
wherein the first gate structure includes a trench defined by the first gate spacer, and a high-k dielectric insulating film extending along a sidewall and a bottom surface of the trench, and
the high-k dielectric insulating film does not extend along a sidewall of the gate insulating support.

US Pat. No. 10,395,989

MULTI-LAYER WORK FUNCTION METAL GATES WITH SIMILAR GATE THICKNESS TO ACHIEVE MULTI-VT FOR VFETS

International Business Ma...

1. A structure for forming a device having multiple field effect transistors (FETs) with each FET having a different work function, the structure comprising:first, second, third, and fourth FETs formed over a semiconductor substrate;
an interfacial layer and a high-k dielectric layer formed over the first, second, third, and fourth FETs;
a first work function conducting layer formed over the high-k dielectric layer, where the first work function conducting layer is subsequently removed from the third FET;
a second work function conducting layer disposed in direct contact with portions of the first work function conducting layer, where the second work function conducting layer is subsequently removed from the second FET;
a third work function conducting layer disposed in direct contact with portions of the second work function conducting layer, where the third work function conducting layer is subsequently removed from the first FET;
a fourth work function conducting layer disposed in direct contact with portions of the third work function conducting layer;
a fifth work function conducting layer, where the fifth work function conducting layer is subsequently removed from the third and fourth FETs; and
first and second conducting layers formed over the first, second, third, and fourth FETs.

US Pat. No. 10,395,988

VERTICAL FET TRANSISTOR WITH REDUCED SOURCE/DRAIN CONTACT RESISTANCE

International Business Ma...

1. A method for reducing contact resistance and parasitic capacitance, the method comprising:forming a bottom source/drain region between a plurality of fins;
forming a bottom spacer over the bottom source/drain region;
forming high-k metal gates (HKMGs) over the bottom spacer;
forming a top spacer over the HKMGs and an interlayer dielectric (ILD) over the top spacer;
recessing the ILD to expose top sections of the plurality of fins;
depositing an epitaxial material over the top sections of the plurality of fins; and
forming a dielectric film over the epitaxial material such that air-gaps are created over the top spacer, the dielectric film recessed to expose top sections of the epitaxial material and to deposit a silicide metal liner and a conductive material thereon.

US Pat. No. 10,395,987

TRANSISTOR WITH SOURCE-DRAIN SILICIDE PULLBACK

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device, comprising:providing a substrate, wherein the substrate is prepared with
a low voltage (LV) device region, and
a medium voltage (MV) device region;
forming a LV gate in the LV device region;
forming LV lightly doped (LD) regions in the substrate in the LV device region adjacent to the LV gate;
forming a MV gate in the MV device region;
forming MV lightly doped (LD) regions in the substrate in the MV device region adjacent to the MV gate;
forming a spacer layer on the substrate, wherein the spacer layer lines the substrate, the LV gate and the MV gate;
patterning the spacer layer, wherein patterning the spacer layer simultaneously forms first and second non-extended spacers on first and second sidewalls of the LV gate, and a first extended L-shaped spacer on a first sidewall of the MV gate, wherein the first extended L-shaped spacer overlaps a top surface of the MV gate by an overlapping portion, and a portion of the top surface of the MV gate adjacent to the overlapping portion is exposed;
forming LV heavily doped (HD) regions in the substrate adjacent to the non-extended spacers on first and second sidewalls of the LV gate; and
forming first and second MV heavily doped (HD) regions in the substrate, wherein the first MV HD region is adjacent to the first extended L-shaped spacer on the first sidewall of the MV gate, wherein the first extended L-shaped spacer displaces the first MV HD region from the first sidewall of the MV gate by a MV distance DM which is sufficient to reduce gate induced drain leakage (GIDL) and impact ionization of a MV transistor in the MV device region.

US Pat. No. 10,395,986

FULLY ALIGNED VIA EMPLOYING SELECTIVE METAL DEPOSITION

International Business Ma...

1. A method for creating a fully-aligned via (FAV) by employing selective metal deposition, the method comprising:forming metal lines within a first inter-layer dielectric (ILD) layer;
forming a second ILD layer over the first ILD layer;
forming a lithographic stack over the second ILD layer to define areas where via growth is prevented;
recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack; and
performing metal growth over the exposed top surface of the metal lines where via growth is permitted; and
removing the lithographic stack and depositing a conformal metal nitride cap in direct contact with a top surface and an entire length of sidewalls of the metal growth.

US Pat. No. 10,395,985

SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure, comprising:a first hardmask on an insulator layer;
a planarizing layer on the first hardmask;
a second hardmask on a portion of the planarizing layer;
a third hardmask on the planarizing layer and on the second hardmask;
sacrificial mandrels on portions of the second hardmask;
a mandrel on the third hardmask; and
an organic planarizing layer on the third hardmask, on spacer material, on the sacrificial mandrels, and on a mandrel including spacer material.

US Pat. No. 10,395,984

SELF-ALIGNED VIA INTERCONNECT STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method, comprising:forming a wiring structure in a dielectric layer;
depositing a dielectric cap layer over the wiring structure and the dielectric layer;
etching an opening in the dielectric cap layer, exposing a surface of the wiring structure;
forming a self-aligned via interconnect structure in direct electrical contact with the metal material of the wiring structure by overfilling the opening with a metal or metal-alloy growth process to have the self-aligned via interconnect structure in direct electrical contact with the wiring structure and directly on a portion of a top surface of the dielectric cap layer adjacent to the opening, wherein the growth process is performed while the entire top surface of the dielectric cap layer is exposed, wherein a contact region between the self-aligned via interconnect structure and the portion of the top surface of the dielectric cap layer which the self-aligned via interconnect structure is formed on is devoid of a barrier material and liner material;
depositing an interlevel dielectric material over the self-aligned via interconnect structure and the top surface of the dielectric cap layer;
etching a trench within the interlevel dielectric material to expose one or more surfaces of the self-aligned via interconnect structure;
depositing a barrier material and liner material over the exposed one or more surfaces of the self-aligned via interconnect structure and on sidewalls of the trench; and
electroplating a metal or metal-alloy material on the liner material to complete formation of an upper wiring structure, in electrical contact with the self-aligned via interconnect structure.

US Pat. No. 10,395,983

METHOD OF FORMING TRENCHES

Taiwan Semiconductor Manu...

1. A method comprising:forming a first material layer over a substrate;
forming a first trench in the first material layer;
forming a second material layer along sidewalls of the first trench;
forming a second trench in the first material layer while the second material layer is disposed along the sidewalls of the first trench, wherein the second material layer has a tapered top surface after the forming of the second trench;
after the forming of the second trench, extending the first trench to expose a portion of the substrate within the first trench; and
forming a conductive feature within the first trench and the second trench such that the conductive feature covers the second material layer having the tapered top surface.

US Pat. No. 10,395,982

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;
an etch stop layer on the lower layer structure;
an upper layer structure on the etch stop layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the etch stop layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure;
a first contact plug filling a first opening, the upper layer structure and the etch stop layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; and
a second contact plug filling a second opening, the upper layer structure and the etch stop layer including the second opening defined therethrough on the second region, a bottom surface of the first contact plug having a first distance from a bottom surface of the etch stop layer and a bottom surface of the second contact plug having a second distance from the bottom surface of the etch stop layer, the first distance being different from the second distance.

US Pat. No. 10,395,981

SEMICONDUCTOR DEVICE INCLUDING A LEVELING DIELECTRIC FILL MATERIAL

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a dielectric fill material above and laterally adjacent to a transistor element of a semiconductor device and a circuit element, said transistor element comprising a gate electrode structure including a dielectric capping layer, said circuit element having an electrode structure covered by a further dielectric capping layer;
removing a portion of said dielectric fill material so as to expose a surface of said dielectric capping layer and a surface of said further dielectric capping layer;
removing said dielectric capping layer and said further dielectric capping layer after removing said portion of said dielectric fill material, wherein a non-removed portion of said dielectric fill material remains laterally adjacent to said transistor element and said circuit element;
masking said circuit element by a mask layer after removal of said dielectric capping layer of said gate electrode structure and said further dielectric capping layer of said electrode structure;
forming a metal semiconductor compound in a semiconductor containing electrode material of said gate electrode structure, wherein said metal semiconductor compound in said gate electrode structure is formed in the presence of said mask layer so as to prevent formation of a metal semiconductor compound in said electrode structure; and
removing a further portion of said dielectric fill material so as to expose surface areas of drain and source regions of said transistor element.