US Pat. No. 10,340,149

METHOD OF FORMING DENSE HOLE PATTERNS OF SEMICONDUCTOR DEVICES

NANYA TECHNOLOGY CORPORAT...

1. A method of forming dense hole patterns, the method comprising:forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate;
blanket forming a spacer layer on the lower hard mask layer by Atomic layer deposition to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars, and each of the first holes is enclosed by three of the second pillars;
etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars;
removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer;
etching the first portions and the second portions of the lower hard mask layer; and
removing remaining portions of the spacer layer.

US Pat. No. 10,340,148

POLYMER, ORGANIC LAYER COMPOSITION, AND METHOD OF FORMING PATTERNS

SAMSUNG SDI CO., LTD., Y...

1. A polymer comprising a structural unit represented by Chemical Formula 1 and a structural unit represented by Chemical Formula 2:
wherein, in Chemical Formula 1,
B is a divalent organic group,
* is a linking point, and
A is a substituted or unsubstituted divalent group from one of the following compounds,

wherein, in the above compounds, R0 and R1 are each independently hydrogen, a hydroxy group, a methoxy group, an ethoxy group, a halogen atom, a halogen-containing group, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, or a combination thereof, and
wherein, in Chemical Formula 2,
C is a group including a substituted or unsubstituted aromatic ring,
D is a divalent organic group, and
* is a linking point.

US Pat. No. 10,340,147

SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING CONTACT AT CURVED PORTION OF EQUIPOTENTIAL RING ELECTRODE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor body of a first conductivity type, having a first area and a second area, the first area being an active area in which transistor element including a source, a drain, and a gate is formed, the second area surrounding the first area, the semiconductor body having a quadrilateral shape in a plan view;
an insulating film formed over the semiconductor body;
an Equipotential Ring (EQR) electrode pattern formed in the insulating film to surround the active area, and having curved portions at corners of the quadrilateral shape;
a first conductive strip connected to the source and formed in the insulating film in the active area;
a first diffusion region of a second conductivity type which is opposite to the first conductivity type, formed in the semiconductor body and in the second area;
a second conductive strip connected to the first diffusion region and the EQR electrode pattern,
wherein the second conductive strip is covered with the insulating film, and is disposed in the second area of the semiconductor body,
wherein the second conductive strip comprises a first second conductive strip and a second conductive strip, and
wherein the first second conductive strip and the second second conductive strip are arranged to be in parallel or in different directions with respect to a normal direction to one of the curved portions of the EQR electrode.

US Pat. No. 10,340,146

RELIABILITY CAPS FOR HIGH-K DIELECTRIC ANNEALS

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:depositing a first layer comprised of a metal silicon nitride on a high-k dielectric material;
thermally processing the high-k dielectric material in an oxygen-containing ambient environment with the first layer arranged as a cap between the high-k dielectric material and the oxygen-containing ambient environment; and
after the high-k dielectric material is thermally processed, completely removing the first layer with a wet chemical etching process,
wherein the first layer blocks transport of oxygen from the oxygen-containing ambient environment to the high-k dielectric material.

US Pat. No. 10,340,145

INTEGRATED CIRCUIT ELEMENT AND FABRICATING METHOD THEREOF, CIRCUIT BOARD, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An integrated circuit element, comprising:a base plate, and a plurality of connection parts and a bare integrated circuit chip arranged on the base plate,
wherein the bare integrated circuit chip comprises a plurality of connection points, and the plurality of connection parts is electrically connected to the plurality of connection points according to a one-to-one correspondence;
wherein an array substrate or a color filter substrate of a liquid crystal display panel is used as the base plate, or a cover-board of an organic light emitting diode display panel is used as the base plate,
wherein the bare integrated circuit chip is arranged at a side of the array substrate facing toward the color filter substrate, or the bare integrated circuit chip is arranged at a side of the color filter substrate facing toward the array substrate, or the bare integrated circuit chip is arranged at a side of the cover-board facing toward a backboard, and
wherein the bare integrated circuit chip is of nanometer scale.

US Pat. No. 10,340,144

DOPING OF A SUBSTRATE VIA A DOPANT CONTAINING POLYMER FILM

ROHM AND HAAS ELECTRONIC ...

1. A semiconductor substrate comprising:embedded dopant domains of diameter 3 to 30 nanometers; wherein the embedded dopant domains are selected from the group consisting of boron, arsenic, antimony, aluminum, indium, and gallium, wherein the embedded dopant domains are located within 30 nanometers of the substrate surface and are periodically spaced in the substrate.

US Pat. No. 10,340,143

ANODIC ALUMINUM OXIDE AS HARD MASK FOR PLASMA ETCHING

Lam Research Corporation,...

1. A method for performing a plasma etching process, comprising:depositing a seed layer of aluminum over a top surface of a wafer;
depositing a layer of photoresist material over the seed layer of aluminum;
patterning and developing the layer of photoresist material to expose one or more portions of the seed layer of aluminum through openings in the photoresist material;
performing an electrochemical transformation process on the wafer to electrochemically transform the one or more portions of the seed layer of aluminum that are exposed through openings in the photoresist material into anodic aluminum oxide, wherein the anodic aluminum oxide includes a pattern of holes that extend through the anodic aluminum oxide to expose areas of the top surface of the wafer beneath the seed layer of aluminum;
removing the photoresist material from the wafer; and
exposing the wafer to a plasma to etch holes into the wafer at the areas of the top surface of the wafer that are exposed by the pattern of holes in the anodic aluminum oxide.

US Pat. No. 10,340,142

METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED METAL HARD MASKS

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a gate disposed on a semiconductor substrate and having a first side and a second side;
forming a metal hard mask disposed on the gate and having a first side and second side, wherein the first side of the metal hard mask is vertically aligned with the first side of the gate and the second side of the metal hard mask is vertically aligned with the second side of the gate;
forming a nitride region disposed on the metal hard mask and having a first side and second side, wherein at least a portion of the first side of the nitride region is vertically aligned with the first sides of the gate and the metal hard mask, at least a portion of the second side of the nitride region is vertically aligned with the second sides of the gate and the metal hard mask; and the nitride region is T-shaped;
forming a spacer disposed on the first sides of the gate and the metal hard mask and on the second sides of the gate and the metal hard mask, wherein a top of the spacer is above a top of the metal hard mask;
forming a first source/drain (S/D) region disposed in proximity to the first side of the gate; and
forming a second S/D region disposed in proximity to the second side of the gate.

US Pat. No. 10,340,141

PATTERNING METHOD FOR SEMICONDUCTOR DEVICE AND STRUCTURES RESULTING THEREFROM

Taiwan Semiconductor Manu...

1. A method comprising:defining a first mandrel and a second mandrel over a hard mask layer, a topmost surface of the first mandrel is disposed in a first plane;
depositing a spacer layer over and along sidewalls of the first mandrel and the second mandrel;
forming a sacrificial material over the spacer layer between the first mandrel and the second mandrel, wherein the sacrificial material comprises an inorganic oxide, wherein the sacrificial material comprises a divot at a top surface of the sacrificial material, wherein a portion of the sacrificial material in the first plane extends continuously from a first sidewall of the spacer layer to a second sidewall of the spacer layer, the second sidewall of the spacer layer facing the first sidewall of the spacer layer, the first sidewall of the spacer layer and the second sidewall of the spacer layer are both disposed between the first mandrel and the second mandrel;
removing a first horizontal portion and a second horizontal portion of the spacer layer to expose the first mandrel and the second mandrel, wherein remaining portions of the spacer layer provide spacers on sidewalls of the first mandrel and the second mandrel, wherein the sacrificial material masks a third horizontal portion and a fourth horizontal portion of the spacer layer while removing the first horizontal portion and the second horizontal portion of the spacer layer, and wherein the divot at least partially exposes a fifth horizontal portion of the spacer layer between the third horizontal portion and the fourth horizontal portion while removing the first horizontal portion and the second horizontal portion of the spacer layer;
removing the first mandrel and the second mandrel; and
patterning the hard mask layer using the spacers and the sacrificial material as an etch mask.

US Pat. No. 10,340,140

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a processing vessel configured to accommodate therein a substrate as a processing target;
a first supply unit configured to supply a first gas into the processing vessel;
a second supply unit configured to supply a second gas, having a relative humidity different from that of the first gas, into the processing vessel; and
a control unit,
wherein the control unit is configured to determine a state of a gas within the processing vessel based on a relative humidity obtained after a supply of the first gas by the first supply unit and a supply of the second gas by the second supply unit are performed,
wherein the state of the gas includes a supply ratio of the first and second gases.

US Pat. No. 10,340,139

METHODS AND MASK STRUCTURES FOR SUBSTANTIALLY DEFECT-FREE EPITAXIAL GROWTH

IMEC, Leuven (BE)

1. A mask structure comprising:a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a substrate, wherein the first trench has a first length greater than a first width of the first trench, and wherein the first trench is oriented in a first direction along the first length; and
a second level on top of the first level, wherein the second level defines a plurality of second trenches, wherein each second trench of the plurality (i) has a second width and a second length that is greater than the second width and (ii) is oriented in a second direction along the second length,
wherein the first trench extending through the first level comprises the first trench separating the first level into a first side and a second side, wherein each second trench of the plurality extends through at least a portion of the second level over the first side of the first level, the first trench, and the second side of the first level, and
wherein the second direction is different from the first direction, thereby enabling the mask structure to trap defects in multiple directions during epitaxial growth of a semiconductor material.

US Pat. No. 10,340,138

ELECTRONIC DEVICE WITH A WIRE ELEMENT EXTENDING FROM AN ELECTROCONDUCTIVE LAYER COMPRISING ZIRCONIUM CARBIDE OR HAFNIUM CARBIDE

ALEDIA, Grenoble (FR)

1. An electronic device comprising:a substrate made of silicon,
at least one semiconductor wire element formed by a nitride of a group III material, and
an electroconductive layer interposed between the substrate and the at least one semiconductor wire element,
wherein the electroconductive layer is formed directly on the substrate,
wherein the at least one semiconductor wire element extends from the electroconductive layer, and
wherein the electroconductive layer comprises a carbide of zirconium or a carbide of hafnium.

US Pat. No. 10,340,137

MONOLAYER FILM MEDIATED PRECISION FILM DEPOSITION

TOKYO ELECTRON LIMITED, ...

1. A method of forming a thin film, comprising:forming a functionalized surface by treating at least a portion of an exposed surface on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of an organic precursor;
thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film; and
forming a mixed film by exposing at least a portion of a surface of the carbon-containing film to an ion flux to mix the carbon-containing film with a material of the substrate, wherein the material of the substrate is located underneath the carbon-containing film.

US Pat. No. 10,340,136

MINIMIZATION OF CARBON LOSS IN ALD SIO2 DEPOSITION ON HARDMASK FILMS

Lam Research Corporation,...

1. A method of depositing films over a substrate received within a process chamber, comprising:processing the substrate to expose a surface of the substrate and a spin-on-hardmask (SOH) patterned thereon to a first precursor using a first plasma so that the first precursor gets partially absorbed to form Silicon-Hydrogen bonds on the surface of the substrate and on surfaces of SOH, the SOH having an initial pattern; and
processing the substrate to expose the surface of the substrate and the surfaces of the SOH to a second precursor using a second plasma, the second precursor includes a mixture of carbon-dioxide gas and an inert gas, the processing causing oxygen radicals to be released and react with the Silicon-Hydrogen bonds formed on the surface of the substrate and the surfaces of the SOH, wherein the oxygen radicals reacting with the Silicon-Hydrogen bonds form an oxide film layer on the surface of the substrate and on surfaces of the SOH, wherein the oxygen radicals reacting with the Silicon-Hydrogen bonds forms the oxide film layer without substantially consuming a surface thickness of the initial pattern of the SOH.

US Pat. No. 10,340,135

METHOD OF TOPOLOGICALLY RESTRICTED PLASMA-ENHANCED CYCLIC DEPOSITION OF SILICON OR METAL NITRIDE

ASM IP Holding B.V., Alm...

1. A method of topology-enabling selective deposition wherein a film is deposited selectively on a top surface of a substrate having a recess pattern constituted by a bottom and sidewalls in semiconductor fabrication, comprising, in sequence:(i) supplying a precursor to a reaction space in which the substrate is placed between electrodes, said precursor containing multiple elements including silicon or metal, carbon, nitrogen, and hydrogen;
(ii) conducting purging of the reaction space, without step (i), only to the extent that a greater amount of precursor than an amount of precursor chemisorbed on the top surface of the substrate remains in a vicinity of the top surface of the substrate; and then
(iii) applying RF power between the electrodes while supplying a plasma-generating gas devoid of H and O, without step (i), to generate an ion-rich anisotropic plasma to which the substrate is exposed, thereby depositing a topologically restricted layer selectively and predominantly on the top surface of the substrate wherein substantially no layer, or a substantially thinner layer than the topologically restricted layer, is deposited on the sidewalls and the bottom of the recess pattern without becoming thinner toward the bottom of the recess pattern,
wherein the topologically restricted layer is constituted by SiCN, SiN, TiCN, TiN, ZrCN, ZrN, HfCN, HfN, TaCN, TaN, NbCN, NbN, AlCN, AlN, CoCN, CoN, CuCN, CuN, WCN, WN, RuCN, RuN, NiCN, NiN LaCN, LaN, or WFN.

US Pat. No. 10,340,134

SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing:
forming a first layer containing a borazine ring skeleton by performing a set m times (where m is an integer equal to or greater than 1), the set including:
supplying a precursor to the substrate to form a precursor layer; and
supplying a borazine compound containing the borazine ring skeleton to the precursor layer; and
forming a second layer containing the borazine ring skeleton and oxygen by supplying an oxidizing agent to the first layer.

US Pat. No. 10,340,133

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A method for fabricating a semiconductor device comprising:forming a silicon oxide film having at least one opening, on a silicon substrate;
forming a structural member formed of a material less prone to be etched by hydrofluoric acid than said silicon oxide film, said structural member being provided on said silicon oxide film and reaching said silicon substrate in said opening; and
performing wet etching using hydrofluoric acid, on said silicon substrate on which said silicon oxide film and said structural member are provided, an interface between said silicon oxide film and said structural member being exposed to hydrofluoric acid in said performing wet etching,
wherein
said structural member includes an insulation film,
an interface between said silicon oxide film and said insulation film is exposed to hydrofluoric acid in said performing wet etching, and
performing said wet etching results in a portion of an upper surface of said silicon oxide film to one side of said opening being etched, and another portion of said upper surface of said silicon oxide film to another side of said opening not being etched.

US Pat. No. 10,340,132

OPTIMIZED ELECTROMAGNETIC FIELD ON SIDE-ON FT-ICR MASS SPECTROMETERS

DH Technologies Developme...

10. A side-on injection Penning trap that includes two sets of printed circuit board electrodes with radial dimensions that are optimized to apply a quadrupole field to charged particles, comprising:a first printed circuit board on which is printed a first set of two or more concentric circular or semi-circular electrodes;
a second printed circuit board on which is printed a second set of two or more concentric circular or semi-circular electrodes that correspond in size and shape to the first set of electrodes, wherein the second printed circuit board is placed in parallel with the first printed circuit board so that the second set of electrodes faces and is coaxial with the first set of electrodes, wherein the space between the first set of electrodes and the second set of electrodes is a cylindrical gap used to trap charged particles, wherein the cylindrical gap has a length d, wherein the first set of electrodes and the second set of electrodes each includes a central disk electrode with a radius of 1.1 d, a first concentric ring or segmented ring electrode of radius 1.9 d, and a second concentric ring or segmented ring electrode of radius 2.4 d, and wherein the first set of electrodes and the second set of electrodes apply a quadrupole electric field to the cylindrical gap; and
at least one permanent magnet that is placed coaxially with the first set of electrodes and the second set of electrodes but outside of the cylindrical gap that applies a first magnetic field to the cylindrical gap that is coaxial with the cylindrical gap, wherein the effects of the first magnetic field and the quadrupole electric field combine to trap charged particles in the cylindrical gap that are injected in a direction perpendicular to the first magnetic field;
at least one solenoid coil that is placed coaxially with the cylindrical gap, but outside of the cylindrical gap;
a current source electrically connected to the at least one solenoid coil that supplies current to the at least one solenoid coil to produce a second magnetic field that is applied to the cylindrical gap that is coaxial with the cylindrical gap;
at least one magnetic sensor placed in or on the first printed circuit board within the first set of electrodes that measures a combined magnetic field that is a combination of the first magnetic field and the second magnetic field; and
feedback control circuitry electrically connected to the at least one magnetic sensor and the current source that that receives over time the combined magnetic field measured by the at least one magnetic sensor and in response adjusts the current of the current source to increase or decrease the second magnetic field in order to maintain the combined magnetic field at a constant value.

US Pat. No. 10,340,131

METHODS AND APPARATUSES RELATING TO CLEANING AND IMAGING AN ION SOURCE USING REFLECTED LIGHT

KRATOS ANALYTICAL LIMITED...

1. A method of cleaning an ion source, the method including:at a first reflective surface of a mirror, reflecting ultraviolet light that has a wavelength in a first wavelength band onto a surface of the ion source so that contaminant material is desorbed from the surface of the ion source, wherein the ultraviolet light has a wavelength in the range 10 nm to 400 nm and is produced by a laser;
at a second reflective surface of the mirror, reflecting visible light that has a plurality of wavelengths in a second wavelength band and that comes from the surface of the ion source towards an imaging apparatus for producing an image of the surface of the ion source using the visible light, wherein the visible light has a plurality of wavelengths in the range 390 nm to 700 nm and is produced by a light source, separate from the laser, for illuminating the surface of the ion source with visible light, wherein the visible light passes through the first reflective surface of the mirror before being reflected at the second reflective surface of the mirror.

US Pat. No. 10,340,130

DATA INDEPENDENT ACQUISITION WITH VARIABLE MULTIPLEXING DEGREE

THERMO FINNIGAN LLC, San...

1. A method of analyzing ions by mass spectrometry, comprising:repeatedly executing a data acquisition cycle to acquire product ion data across a precursor ion mass range of interest, the data acquisition cycle including performing, for each of a plurality of isolation windows having different mass ranges, steps of: isolating precursor ions within the mass range of the isolation window, fragmenting the precursor ions to generate product ions and mass analyzing the product ions;
wherein the plurality of isolation windows collectively span the precursor ion mass range of interest, and wherein the step of mass analyzing the product ions comprises concurrently mass analyzing product ions corresponding to N isolation windows, N being an integer?1, and N being varied at least once across the data acquisition cycle.

US Pat. No. 10,340,129

MICROCHANNEL PLATE AND ELECTRON MULTIPLIER

HAMAMATSU PHOTONICS K.K.,...

1. A microchannel plate comprising:a substrate including a front surface, a rear surface, and a side surface;
a plurality of channels penetrating from the front surface to the rear surface of the substrate;
a first film provided on at least an inner wall surface of the channel;
a second film provided on the first film; and
electrode layers provided on the front surface and the rear surface of the substrate,
wherein the first film is made of Al2O3,
the second film is made of SiO2, and
the first film is thicker than the second film.

US Pat. No. 10,340,128

APPARATUS, METHOD AND NONTRANSITORY COMPUTER READABLE MEDIUM FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE

TOSHIBA MEMORY CORPORATIO...

1. An apparatus for manufacturing an integrated circuit device comprising:an etching treatment unit configured to etch a stacked body including an alternately arranged plurality of films having different compositions, the etching treatment unit including
a housing configured to define a treatment chamber,
a gas supply system configured to supply an etching gas to the treatment chamber,
a pump configured to exhaust gas in the treatment chamber,
a holding table configured to hold the stacked body in the treatment chamber,
a dielectric place provided above the holding table, and
a high frequency source configured to generate an electric field between the holding table and the dielectric place;
a sensor configured to detect light intensity of one wavelength of a light emission generated by etching reaction during the etching; and
a control unit configured to
detect extreme values from data relating to a temporal change in the light intensity detected by the sensor,
determine an end point of the etching based on the extreme values while the extreme values can be detected,
estimate an end point of the etching based on the extreme values detected so far when the extreme value cannot be detected from the data at all, and
cause the etching treatment unit to stop the etching when the end point is reached, the extreme values including at least one of a plurality of peak values and a plurality of bottom values, wherein
the control unit is configured to estimate the end point by deriving a cycle from a time interval of the plurality of extreme values, and to estimate time to the end point of the etching based on the time interval,
the control unit is configured to determine an etching amount after reaching a lower layer by estimating a time to the end point based on the temporal change in the light intensity during the etching, and
the time interval is derived based on an approximation formula derived from a relation between a number of the extreme values and time in the data.

US Pat. No. 10,340,127

USING MODELING TO DETERMINE WAFER BIAS ASSOCIATED WITH A PLASMA SYSTEM

Lam Research Corporation,...

1. A method for determining wafer bias, the method comprising:receiving, by a processor from a sensor, an output complex voltage and current, the sensor located within a generator and coupled to an output of the generator, the output of the generator coupled via a radio frequency (RF) cable to an input of an impedance matching circuit, the impedance matching circuit coupled via an RF transmission line to an electrostatic chuck (ESC) of a plasma chamber;
determining, by the processor, from the output complex voltage and current a projected complex voltage and current at a point on a path from an output of a computer-generated model of the impedance matching circuit to a computer-generated model of the ESC, the determining of the projected complex voltage and current performed using a computer-generated model for the path, the computer-generated model for the path including an RF transmission model of the RF transmission line; and
applying, by the processor, the projected complex voltage and current as an input to a function to map the projected complex voltage and current to a wafer bias value at the ESC model.

US Pat. No. 10,340,126

PLASMA SOURCE AND METHODS FOR DEPOSITING THIN FILM COATINGS USING PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION

AGC FLAT GLASS NORTH AMER...

1. A plasma source forming a coating using plasma enhanced chemical vapor deposition (PECVD) comprising:i) a first electron emitting surface and a second electron emitting surface separated by a gas containing space,
wherein a first restricted opening is disposed in the first electron emitting surface and a second restricted opening is disposed in the second electron emitting surface,
wherein the first and second restricted openings are configured to face the substrate to be coated,
wherein the first electron emitting surface and the second electron emitting surface are positioned so that a current comprising secondary electrons flows from the first electron emitting surface through the first restricted opening, through the gas containing space, and through the second restricted opening to the second electron emitting surface;
ii) at least one precursor gas manifold supplying precursor gas;
iii) at least one reactant gas manifold supplying reactant gas;
iv) a power source to which the electron emitting surfaces are electrically connected supplying a voltage that alternates between positive and negative to cause the voltage supplied to the first electron emitting surface to be out of phase with the voltage supplied to the second electron emitting surface and creating a current comprising electrons that flows between the electron emitting surfaces; and
v) one or more walls for pressure control, wherein the operating gas pressure between the first electron emitting surface and the second electron emitting surface is 1 millibar to 10?3 millibar;
wherein the current creates a plasma between the electron emitting surfaces that is substantially uniform over its length in the substantial absence of Hall current;
wherein the at least one reactant gas manifold is positioned so that reactant gas flows along the electron emitting surfaces;
wherein the at least one precursor gas manifold is positioned so that the precursor gas flows into the gas containing space separating the electron emitting surfaces; and
wherein the plasma energizes, partially decomposes, or fully decomposes the precursor gas proximate to the substrate to be coated, and
wherein the plasma source is able to produce a coating at a rate of deposition of at least 0.2 ?m/second.

US Pat. No. 10,340,125

PULSED REMOTE PLASMA METHOD AND SYSTEM

ASM IP Holding B.V., Alm...

1. A method for providing excited species to a reaction chamber of a reactor, the method comprising the steps of:providing a first gas to a remote plasma unit;
using a pressure control device located between the remote plasma unit and a vacuum source and a control valve between the remote plasma unit and the reaction chamber, controlling a pressure of the remote plasma unit located upstream of the pressure control device;
forming a plasma in a remote plasma unit; and
pulsing first excited species to the reaction chamber, while maintaining steady-state conditions for the remote plasma unit, by switching a flow of the first excited species between the reaction chamber and a vacuum source using the control valve.

US Pat. No. 10,340,124

GENERALIZED CYLINDRICAL CAVITY SYSTEM FOR MICROWAVE ROTATION AND IMPEDANCE SHIFTING BY IRISES IN A POWER-SUPPLYING WAVEGUIDE

Applied Materials, Inc., ...

1. A plasma reactor comprising:a workpiece processing chamber;
a cylindrical microwave cavity overlying the workpiece processing chamber, and a plurality of microwave input ports arranged asymmetrically about a center axis of the cylindrical microwave cavity, the plurality of microwave input ports including first and second input ports, P and Q, in a sidewall of said cylindrical microwave cavity spaced apart by an oblique azimuthal offset angle ??;
a microwave source having first microwave modules that provides a first microwave source output having a microwave frequency, and a second microwave module that provides a second microwave source output having the microwave frequency and separated by a temporal phase difference ?Ø from the first microwave source output;
a pair of respective waveguides, each of said respective waveguides having a microwave input end coupled to a respective one of said microwave source outputs and a microwave output end coupled to a respective one of said first and second input ports;
a seed signal generator having a first output signal coupled to the first microwave module and a second output signal coupled to the second microwave module, the seed signal generator configured to generate first and second output signals that generate rotating microwaves of mode TEmnl or TMmnl in said cylindrical microwave cavity, wherein m, n and l are user-selected values of a TE or TM mode.

US Pat. No. 10,340,123

MULTI-FREQUENCY POWER MODULATION FOR ETCHING HIGH ASPECT RATIO FEATURES

TOKYO ELECTRON LIMITED, ...

1. A method of etching, comprising:disposing a substrate having a surface exposing a first material and a second material in a processing space of a plasma processing system;
performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material, the modulated plasma etching process comprising a power modulation cycle that includes:
applying a first power modulation sequence to the plasma processing system, and
applying a second power modulation sequence to the plasma processing system, the second power modulation sequence being different than the first power modulation sequence; and
repeating the power modulation cycle at a power modulation frequency for a determined modulation time period,
wherein the first power modulation sequence includes repeating a first sub-power modulation cycle at a first sub-power modulation frequency, the first sub-power modulation cycle including:
applying a radio frequency (RF) signal to the plasma processing system at a first power level, and
applying the RF signal to the plasma processing system at a second power level, wherein the first and second power levels differ in value from one another;
wherein a time period of the second power modulation sequence is greater than a time period of the first sub-power modulation cycle.

US Pat. No. 10,340,122

SYSTEMS AND METHODS FOR TAILORING ION ENERGY DISTRIBUTION FUNCTION BY ODD HARMONIC MIXING

Lam Research Corporation,...

1. A radio frequency (RF) generator comprising:an odd harmonic power supply configured to generate an nth harmonic RF signal, wherein n is an odd number;
an impedance matching circuit coupled to the odd harmonic power supply, wherein the impedance matching circuit is configured to output an nth modified harmonic RF signal upon receiving the nth harmonic RF signal;
a frequency multiplier coupled to the impedance matching circuit, wherein the frequency multiplier is configured to receive the nth modified harmonic RF signal to output an (n+2)th harmonic RF signal;
a variable adjuster coupled to the frequency multiplier, wherein the variable adjuster is configured to modify a variable of the (n+2)th harmonic RF signal to output an adjusted (n+2)th harmonic RF signal; and
an adder coupled to the variable adjuster and the impedance matching circuit, wherein the adder is configured to add the nth modified harmonic RF signal and the adjusted (n+2)th harmonic RF signal to generate an added RF signal.

US Pat. No. 10,340,121

PLASMA PROCESSING SYSTEMS INCLUDING SIDE COILS AND METHODS RELATED TO THE PLASMA PROCESSING SYSTEMS

Lam Research Corporation,...

1. A method for processing a wafer with plasma in a plasma processing system, saidplasma processing system including a chamber structure for containing said plasma, said chamber structure including a cylindrical chamber wall, said chamber structure further including a dielectric member disposed above said cylindrical chamber wall and coupled with said cylindrical chamber wall, said dielectric member including a first element and a second element connected to said first element, the method comprising:
initiating, using a set of top coils disposed above said first element of said dielectric member, said plasma inside said chamber structure, said initiating including providing a first signal of a first frequency to said set of top coils;
after said initiating, affecting, using a set of side coils surrounding said second element, distribution of said plasma, said affecting including providing a second signal of a second frequency to said set of side coils, said second frequency being different from said first frequency, said second element being perpendicular to said first element; and
moving said set of side coils along an outer surface of said second element in a direction perpendicular to a top surface of said wafer when said wafer is processed in said plasma processing system, for tuning said distribution of said plasma.

US Pat. No. 10,340,120

BLANKING APERTURE ARRAY, METHOD FOR MANUFACTURING BLANKING APERTURE ARRAY, AND MULTI-CHARGED PARTICLE BEAM WRITING APPARATUS

NuFlare Technology, Inc.,...

1. A blanking aperture array for a multi-charged particle beam writing apparatus, the blanking aperture array comprising:a substrate; and
a plurality of blankers, each of the plurality of blankers including a blanking electrode and a ground electrode that are formed on a first surface of the substrate,
wherein the plurality of blankers includes at least
a normal blanker which is capable of applying a predetermined voltage between the blanking electrode and the ground electrode and for which a through hole bored through the substrate is formed, and
a defective blanker which is not capable of applying the predetermined voltage between the blanking electrode and the ground electrode and for which the through hole bored through the substrate is filled with a beam shield,
wherein, for the defective blanker, a recess is disposed on the first surface of the substrate, and
wherein a substrate body between a bottom surface of the recess and a second surface of the substrate serves as the beam shield.

US Pat. No. 10,340,119

AUTOMATED TEM SAMPLE PREPARATION

FEI Company, Hillsboro, ...

1. A method for automated sample preparation in a charged particle beam system, comprising:loading a work piece into a vacuum chamber including one or more charged particle beam columns and a sample manipulation probe;
performing charged particle beam milling operations to form from a portion of the work piece a sample for observation on a transmission electron microscope;
after performing charged particle beam milling operations to form from the portion of the work piece the sample, forming one or more fiducials on the formed sample;
attaching the sample manipulation probe to the sample;
removing the sample from the work piece; and
using the one or more fiducials on the removed sample to determine a position and/or a rotational alignment of the sample.

US Pat. No. 10,340,118

SCANNING TRANSMISSION ELECTRON MICROSCOPE AND METHOD OF IMAGE GENERATION

JEOL Ltd., Tokyo (JP)

1. A scanning transmission electron microscope adapted to produce scanned images by scanning an electron beam over a sample, said scanning transmission electron microscope comprising:an electron source for emitting an electron beam;
a scanning deflector for scanning the emitted electron beam over the sample;
an objective lens for converging the electron beam emitted from the electron source;
an imager placed at a back focal plane of the objective lens or at a plane conjugate with the back focal plane; and
a scanned image generator for generating the scanned images on the basis of images captured by the imager,
wherein the scanned image generator operates to form electron diffraction patterns from the electron beam passing through positions on the sample by scanning of the electron beam, to capture the electron diffraction patterns by the imager so that plural images are produced, to integrate the intensity of each pixel over an integration region that is set based on the size of an image of a transmitted wave within a respective one of the produced images such that the signal intensity at each position on the sample is found for each of the produced images, and to generate the scanned images on the basis of the signal intensities at the positions on the sample, wherein said scanned image generator operates to measure the size of the image of said transmitted wave from the image captured by said imager and to set said integration region on the basis of the measured size of the image of the transmitted wave.

US Pat. No. 10,340,117

ION BEAM DEVICE AND SAMPLE OBSERVATION METHOD

Hitachi, Ltd., Tokyo (JP...

1. An ion beam device comprising:an ion source configured to generate an ion beam;
a sample chamber;
an evacuation pump configured to reduce a pressure in the sample chamber to a first degree of vacuum; and
a vacuum container configured to hold a sample that is irradiated with the ion beam,
wherein the ion beam passes from the sample chamber to the sample through a passage in the vacuum container in which the first degree of vacuum changes to a second degree of vacuum lower than the first degree of vacuum, and the passage has an aspect ratio of 200 or more.

US Pat. No. 10,340,116

IMAGING AN AREA THAT INCLUDES AN UPPER SURFACE AND A HOLE

APPLIED MATERIALS ISRAEL ...

1. A method for imaging an area that includes an upper surface and hole, the method comprises:acquiring, by a charged particle imager, a first image of a first type of electrons of the area while the charged particle imager is at a first configuration; wherein the first image of the first type of electrons of the area comprises a first image of the first type of electrons of the upper surface;
acquiring, by the charged particle imager, a second image of the first type of electrons of the area and a first image of a second type of electrons of the area while the charged particle imager is at a second configuration that differs from the first configuration; wherein the first image of the second type of electrons of the area comprises a first image of the second type of electrons of a bottom of the hole;
calculating, based on a comparison between the first image of the first type of electrons of the area and the second image of the first type of electrons of the area, an inter-image offset; and
generating a hybrid image of the area based on (i) the first image of the first type of electrons of the upper surface, (ii) the inter-image offset, and (iii) the first image of the second type of electrons of the bottom of the hole.

US Pat. No. 10,340,115

CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Technologies...

1. A charged particle beam device comprising:an optical element which adjusts a charged particle beam emitted from a charged particle source;
an adjustment element which adjusts an incidence condition of the charged particle beam with respect to the optical element; and
a control device which controls the adjustment element,
wherein the control device continuously tracks or calculates a temperature fluctuation of the optical element based on a condition setting and the incidence condition of the charged particle beam with respect to the optical element.

US Pat. No. 10,340,114

METHOD OF ELIMINATING THERMALLY INDUCED BEAM DRIFT IN AN ELECTRON BEAM SEPARATOR

KLA-Tencor Corporation, ...

1. An apparatus comprising:an electron beam separator;
a ceramic divider disposed on the electron beam separator;
a set of electrostatic plates in an octupole arrangement disposed on the ceramic divider;
a first separator coil pair disposed around the ceramic divider and arranged on opposite sides of the electron beam separator;
a second separator coil pair disposed around the ceramic divider and arranged on opposite sides of the electron beam separator, orthogonal to the first separator coil pair;
a heater coil disposed around the electron beam separator; and
a power source configured to provide a heater coil current to the heater coil.

US Pat. No. 10,340,113

STUDYING DYNAMIC SPECIMEN BEHAVIOR IN A CHARGED-PARTICLE MICROSCOPE

FEI Company, Hillsboro, ...

1. A method of using a Charged Particle Microscope, comprising:a specimen holder, for holding a specimen;
a source, for producing an irradiating beam of charged particles;
an illuminator, for directing said beam so as to irradiate the specimen; and
a detector, for detecting a flux of emergent radiation emanating from the specimen in response to said irradiation,the method comprising:in said illuminator, providing an aperture plate comprising an array of apertures;
using a deflecting device to scan said beam across said array, thereby alternatingly interrupting and transmitting the beam so as to produce a train of beam pulses; and
irradiating said specimen with said train of pulses, and using said detector to perform positionally resolved detection of the attendant emergent radiation.

US Pat. No. 10,340,112

MANHOLE BASE LINER AND METHOD FOR MANUFACTURING A MANHOLE BASE LINER

Predl GmbH, Boenitz (DE)...

1. A method for producing a formed part having a base body and at least one pipe connection opening, comprising:a) creating a negative form of the formed part,
b) at least regionally wrapping the negative form with a flexible film, and
c) creating the base body by molding a material in a liquid or pasty state on the negative form,
wherein at least one transition strip and/or at least one pipe socket is arranged on the negative form and is molded to the base body.

US Pat. No. 10,340,111

FUSE

TOYODA IRON WORKS CO., LT...

1. A fuse comprising:a conductive member formed integrally with a melting portion that melts and breaks when overcurrent occurs, and with first and second bars;
two shielding portions arranged on the conductive member to hold the melting portion in between, each of the two shielding portions being comprised of a single-piece shielding member where each shielding member is situated on the conductive member between the melting portion and the first and second bars, wherein each shielding member is disk shaped and includes a holder and a slot on one side of the holder where the slot is in communication with an outer side of the holder and extends to an outer circumference of its respective shielding member and a slit on an opposite side of the holder where the slit is in communication with an opposite outer side of the holder and extends toward but not to an opposite outer side of the outer circumference of its respective shielding member; and
a case formed from an electrically-insulative material, wherein the case encloses the melting portion in cooperation with the two shielding portions.

US Pat. No. 10,340,110

SURGE PROTECTIVE DEVICE MODULES INCLUDING INTEGRAL THERMAL DISCONNECT MECHANISMS AND METHODS INCLUDING SAME

RAYCAP IP DEVELOPMENT LTD...

18. A surge protective device (SPD) module comprising:a module housing;
first and second module electrical terminals mounted on the module housing;
an overvoltage clamping element electrically connected between the first and second module electrical terminals;
a thermal disconnector mechanism positioned in a ready configuration, wherein the overvoltage clamping element is electrically connected with the second module electrical terminal, the thermal disconnector mechanism being repositionable to electrically disconnect the overvoltage clamping element from the second module electrical terminal, the thermal disconnector mechanism including:
an electrode electrically connected to the overvoltage clamping element;
a disconnect spring elastically deflected and electrically connected to the electrode in the ready configuration;
a first fail-safe mechanism including a solder securing the disconnect spring in electrical connection with the electrode in the ready configuration, wherein:
the solder is meltable in response to overheating of the overvoltage clamping element; and
the disconnect spring is configured to electrically disconnect the overvoltage clamping element from the second module electrical terminal when the solder is melted; and
a second fail-safe mechanism including a weak region in the disconnect spring, wherein the disconnect spring is configured to break at the weak region in response to a current through the disconnect spring to electrically disconnect the overvoltage clamping element from the second module electrical terminal.

US Pat. No. 10,340,109

ULTRAFAST ELECTROMECHANICAL DISCONNECT SWITCH HAVING CONTACT PRESSURE ADJUSTMENT AND SWITCHING CHAMBER

The Florida State Univers...

1. An electrical transfer or disconnect switch, comprising:a first non-movable electrical contact coupled to an insulating medium;
a second non-movable electrical contact coupled to said insulating medium;
a third non-movable electrical contact coupled to said insulating medium and positioned between said first non-movable electrical contact and said second non-movable electrical contact to provide conduction between said first non-movable electrical contact and said second non-movable electrical contact when electrically in series;
a first static gap disposed between said first non-movable contact and said third non-movable contact;
a second static gap disposed between said second non-movable contact and said third non-movable contact;
an actuator having a first mounting plate and a second mounting plate, said first mounting plate aligned with said first static gap but positioned at a spaced distance away from said first non-movable contact, said third non-movable contact, and said first static gap; said second mounting plate aligned with said second static gap but positioned at a spaced distance away from said second non-movable contact, said third non-movable contact, and said second static gap;
a first movable contact directly or indirectly coupled to said first mounting plate of said actuator and aligned with said first static gap, said first movable contact contacting said first and third non-movable contacts simultaneously to complete a first series between said first and third non-movable contacts, wherein when said actuator is prompted, said first mounting plate shifts away from said first and third non-movable contacts, such that a first variable gap is formed between said first movable contact and said first and third non-movable contacts, thus breaking or disconnecting said first series between said first and third non-movable contacts, said actuator also releasing contact pressure between said first movable contact and said first and third non-movable contacts;
a second movable contact directly or indirectly coupled to said second mounting plate of said actuator and aligned with said second static gap, said second movable contact contacting said second and third non-movable contacts simultaneously to complete a second series between said second and third non-movable contacts, wherein when said actuator is prompted, said second mounting plate shifts away from said second and third non-movable contacts, such that a second variable gap is formed between said second movable contact and said second and third non-movable contacts, thus breaking or disconnecting said second series between said second and third non-movable contacts, said actuator also releasing contact pressure between said second movable contact and said second and third non-movable contacts, wherein when said actuator is idle or unprompted, said first movable contact is contacting said first and third non-movable contacts and when said second movable contact is contacting said first and second non-movable contacts, an electrical circuit is closed within said electrical transfer or disconnect switch, such that a current flows along a path of travel within said electrical transfer or disconnect switch across said first non-movable contact, said first movable contact, said third non-movable contact, said second movable contact, and said second non-movable contact;
one or more precision adjustment screws coupled to said first, second, and third non-movable contacts for adjusting said first, second, and third non-movable contacts; and
a switching chamber that encloses at least said insulating medium, said first non-movable contact, said second non-movable contact, said third non-movable contact and said actuator, said switching chamber containing vacuum or pressurized gas.

US Pat. No. 10,340,108

ULTRAFAST SINGLE ACTUATOR ELECTROMECHANICAL DISCONNECT SWITCH

The Florida State Univers...

1. An electrical switch, comprising:a first electrical feedthrough disposed through an insulating medium, said first electrical feedthrough connected to a first non-movable electrical contact and said first non-movable electrical contact coupled to said insulating medium;
a second electrical feedthrough disposed through the insulating medium, said second electrical feedthrough connected to a second non-movable electrical contact and said second non-movable electrical contact coupled to said insulating medium;
a static gap disposed between said first non-movable contact and said second non-movable contact;
an actuator aligned with said static gap but positioned at a spaced distance away from said first and second non-movable contacts; said actuator being a piezoelectric actuator or a magnetostrictive actuator;
a movable contact directly or indirectly coupled to said actuator and aligned with said static gap, said movable contact contacting said first and second non-movable contacts simultaneously to complete a series between said first and second non-movable contacts, wherein when said actuator is prompted, said movable contact shifts away from said first and second non-movable contacts, such that a variable gap is formed between said movable contact and said first and second non-movable contacts, thus breaking or disconnecting said series between said first and second non-movable contacts, said actuator also releasing contact pressure between said movable contact and said first and second non-movable contacts, wherein when said actuator is idle or unprompted, said movable contact is contacting said first and second non-movable contacts, an electrical circuit is closed within said electrical switch, such that a current flows along a path of travel within said electrical switch across said first non-movable contact, said movable contact and said second non-movable contact.

US Pat. No. 10,340,107

ARRANGEMENT FOR AN ELECTRIC SWITCHING DEVICE

Tyco Electronics Componen...

1. An arrangement for an electric switching device, comprising:a switching unit having an armature and a contact spring and movable between a first switching position and a second switching position;
a restoring element exerting a restoring force on the switching unit in the second switching position, the restoring force directed toward the first switching position;
a non-adjustable supporting surface;
a return spring integrally formed with the contact spring and the restoring element, the return spring and the contact spring are attached to the armature, the return spring having a first planar surface contacting the non-adjustable supporting surface in both the first switching position and the second switching position and exerting a counterforce on the switching unit opposite to the restoring force, the return spring does not overlap any portion of the contact spring in a direction perpendicular to the first planar surface of the return spring, a second planar surface of the contact spring extending parallel to the first planar surface of the return spring in a state in which the contact spring and the return spring are undeflected; and
a coil body with a coil core generating a magnetic field attracting the armature, the armature is movable with respect to the coil body and is disposed between a portion of the return spring and a portion of the coil body with which the non-adjustable supporting surface is integrally formed, an end of the return spring is disposed between the coil body and the non-adjustable supporting surface.

US Pat. No. 10,340,106

LOAD DRIVER

DENSO CORPORATION, Kariy...

1. A load driver for driving a load configured to receive an electric power supply from a first power supply or from a second power supply, the load driver having a first relay disposed at a position between the first power supply and the load and a second relay disposed at a position between the second power supply and the load, the load driver comprising:a controller configured to control an open state and a closed state of the first relay and the second relay by an open-close control signal;
a first open-close switch configured to control driving the first relay to the open state and the closed state based on the open-close control signal from the controller;
a second open-close switch configured to control driving the second relay to the open state and the closed state based on the open-close control signal from the controller; and
a prohibition switch configured to prohibit driving the second relay to the closed state, when the controller outputs the open-close control signal to drive the first relay to the closed state to supply electric power from the first power supply to the load via the first relay.

US Pat. No. 10,340,105

POWER SUPPLY APPARATUS AND METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A power supply apparatus to supply power to an electronic apparatus, the power supply apparatus comprising:a first relay and a second relay to be turned on and off to control the supply of the power for the electronic apparatus; and
a processor to control a switching operation of the first relay and/or the second relay based on:
a connection detection signal indicating a connection state between the power supply apparatus and the electronic apparatus, and
a power on/off signal indicating one of a power on command and a power off command with respect to the electronic apparatus,
wherein, in response to the connection detection signal indicating the connection state of the power supply apparatus being connected to the electronic apparatus and the power on/off signal indicating the power off command with respect to the electronic apparatus, the processor controls one of the first relay and the second relay to turn on one of the first relay and the second relay.

US Pat. No. 10,340,104

PERMANENT SHORT-CIRCUIT DEVICE

ABB SCHWEIZ AG, Baden (C...

1. A permanent short-circuit device for high-voltage power transmission applications, comprising:an enclosure with a first fixed electrically conducting body and a second fixed electrically conducting body, each being connected to a respective conductor leaving the enclosure,
wherein the first body has a first and a second surface on opposite sides of the first body,
wherein the second body has a first and a second surface on opposite sides of the second body, and
where the first surface of the first body faces the first surface of the second body and is separated therefrom by a gap with width d and the second surface of the first body is provided with explosives connected to a detonator for deforming the first body in the direction towards the first surface of the second body such that the first surface of the first body galvanically connects to the first surface of the second body across the gap, wherein the first and second bodies are tubes, where the first body is an outer body encircling the second body.

US Pat. No. 10,340,103

SWITCHING ASSEMBLIES WITH INTEGRAL HANDLE AND ROTOR AND METHODS OF ASSEMBLY

SIEMENS INDUSTRY, INC., ...

1. An electrical switching assembly, comprising:an integral handle and rotor unit including a rotor portion integral with a handle portion;
one or more orientation features on the rotor portion; and
a line base comprising one or more openings configured to receive the one or more orientation features, wherein the one or more orientation features enable the rotor portion to be received within the line base when the rotor portion is in a predetermined orientation relative to the line base,
wherein the one or more orientation features are configured to retain the rotor portion within the line base without needing any additional retaining mechanisms in the electrical switching assembly,
wherein the rotor portion configured to receive one or more conductors, and
wherein the rotor portion configured to be received in the line base.

US Pat. No. 10,340,102

DEVICE FOR CONTROLLING MULTIPLE FUNCTIONS IN A MOTOR VEHICLE

1. A device for controlling multiple functions, comprising:a switch panel having at least three control panels extending along a longitudinal extension of the switch panel, the switch panel being pivotably mounted about an axis of rotation that is parallel with the longitudinal extension of the switch panel to pivot about the axis of rotation in response to manual actuation of the switch panel by manual actuation of one or more of the control panels;
wherein the switch panel is movable with respect to the longitudinal extension of the switch panel and is fixed with respect to a transverse extension of the switch panel perpendicular to the longitudinal extension of the switch panel;
the switch panel further including an actuating plate having the control panels, the actuating plate extends along the longitudinal extension of the switch panel;
the switch panel further including at least three reinforcing ribs each being respectively for a respective one of the control panels, the reinforcing ribs are respectively connected to the actuating plate at locations corresponding to the control panels and extend along the transverse extension of the switch panel between the actuating plate and the axis of rotation, the reinforcing ribs are pivotably mounted about the axis of rotation whereby the switch panel is pivotably mounted about the axis of rotation to pivot about the axis of rotation, the reinforcing ribs cause the switch panel to be fixed with respect to the transverse extension of the switch panel;
a plurality of force sensors distributed along the longitudinal extension of the switch panel and respectively associated with the control panels; and
wherein actuation of the switch panel by actuating one of the control panels triggers one of a plurality of different functions depending on which one of the control panels is actuated and the force sensors are configured to detect which one of the control panels is actuated.

US Pat. No. 10,340,101

KEYCAP WITH ACTIVE ELEMENTS

Intel Corporation, Santa...

8. A method, comprising:forming a keycap for a key, the keycap including a pocket, and the pocket includes:
a protective layer; and
an active element, wherein a height of protective layer and the active element is less than about six (6) millimeters in height.

US Pat. No. 10,340,100

KEYBOARD DEVICE

PRIMAX ELECTRONICS LTD, ...

1. A keyboard device, comprising:a key switch;
a base plate;
a connecting element disposed on the base plate and connected with the base plate; and
a replaceable key comprising:
a coupling plate located over the connecting element and connected with the connecting element, and comprising a first sliding part, wherein when the coupling plate is moved downwardly relative to the base plate, the key switch is triggered; and
a keycap exposed outside the keyboard device, and comprising a second sliding part, wherein the keycap is combined with the coupling plate and at least a portion of the coupling plate is covered by the keycap when the second sliding part is slid relative to the first sliding part, or the keycap is detached from the coupling plate when the second sliding part is slid relative to the first sliding part, wherein the first sliding part is a sliding groove, and the second sliding part is a protrusion block, wherein the protrusion block is inserted into the sliding groove and laterally slidable within the sliding groove.

US Pat. No. 10,340,099

MOUSE WITH REMOVABLE BUTTON SWITCH

Dexin Corporation, New T...

1. A mouse with a removable button switch, comprising:a release unit, comprising a bearer, mounted on a circuit board of the mouse;
a press-fixing and ejection means, provided with a press-fixing part and an ejection part; and
a press-fixing means, the press-fixing means and the press-fixing and ejection means being oppositely disposed on both sides of the bearer, and the press-fixing means being provided with the press-fixing part;
wherein the button switch is disposed between the press-fixing means and the press-fixing and ejection means, the button switch is fixed in the bearer by the press-fixing part of the press-fixing means and the press-fixing part of the press-fixing and ejection means, and the button switch in the bearer is ejected by the ejection part of the press-fixing and ejection means.

US Pat. No. 10,340,098

KEY STRUCTURE

PRIMAX ELECTRONICS LTD, ...

1. A key structure, comprising:a keycap, having a light hole;
a movable mechanism, disposed below the keycap, wherein the movable mechanism has an upper connection end and a lower connection end that are opposite to each other, and the upper connection end is pivotally connected to the keycap, wherein the movable mechanism is a scissor mechanism, and the scissor mechanism has a through hole;
a support plate, disposed below the keycap, wherein the lower connection end of the movable mechanism is pivotally connected to the support plate, and the support plate has a central opening;
a circuit board, disposed below the support plate, wherein the circuit board has at least one groove, and the groove is correspondingly located directly below the keycap;
at least one trigger switch element, disposed on the circuit board, wherein one end portion of the trigger switch element is electrically connected to the circuit board, and an other end portion of the trigger switch element passes through the central opening of the support plate to be abutted against the keycap; and
at least one indicator light-emitting element, electrically connected to the circuit board and embedded in the groove, wherein light emitted by the indicator light-emitting element sequentially travels upward through the central opening of the support plate, the through hole of the scissor mechanism, and the light hole of the keycap and is emitted outward.

US Pat. No. 10,340,097

INSTALLATION SWITCHING DEVICE HAVING A CONTACT CLAMP

ABB SCHWEIZ AG, Baden (C...

1. An installation switching device comprising:a housing; and
at least one contact clamp, which is arranged in the housing, configured to connect at least one electrical conductor through a conductor insertion opening that is provided in the housing, the contact clamp comprising a clamping frame that has a rectangular cross section and a clamping screw that is configured to engage in a first narrow end side of the clamping frame and a clamping end of the clamping screw being configured to cooperate with a section of a contact rail that is fixedly mounted in the housing of the installation switching device, the section being located within the clamping frame, so that a second narrow end side that lies opposite the first narrow end side and is connected thereto via two longitudinal sides that lie opposite one another is configured to press an inserted connecting conductor against a surface of the contact rail that is remote from the clamping screw,
wherein a clamp covering part is coupled to the clamping frame,
wherein the clamp covering part has a tub-shaped cross section having two short arms that lie opposite one another and a connecting piece that connects the two short arms to one another,
wherein a first short arm is coupled to the first narrow end side and a second short arm that lies opposite the first short arm is coupled to the second narrow side, and
wherein the second short arm supports a skirt that protrudes over the second narrow end side in a direction facing away from the clamping screw.

US Pat. No. 10,340,096

SYSTEM AND METHOD FOR AIR MOTOR RECHARGING OF SPRING MECHANISMS

MITSUBISHI ELECTRIC POWER...

1. A circuit breaker system, comprising:an electrical contact mechanism, the electrical contact mechanism movable between a closed and an open position;
an air motor, the air motor operable responsive to pressurized air supplied thereto for recharging the electrical contact mechanism following a closing operation;
an air storage tank that delivers pressurized air to the air motor, wherein air in the air storage tank is stored at a predetermined storage pressure;
a solenoid valve interposing the air motor and the air storage tank and energizable to an open state to enable pressurized air to flow to the air motor; and
a pressure regulator interposing the solenoid valve and the air storage tank to control an operating pressure of the air delivered to the air motor at a predetermined pressure level, wherein the operating pressure supplying sufficient energy to the air motor to recharge the electrical contact mechanism.

US Pat. No. 10,340,095

SAFETY-SWITCH DEVICE FOR USE ON A MOVABLE DEVICE

1. A safety-switch device for use on a movable device, the safety-switch device comprising:a switch;
an enclosure surrounding the switch, the enclosure including an impact surface which serves as an actuator for the switch and a bracket that is a flexible deformable body that is mountable on a surface of a housing of the movable device, the impact surface being a separate component that is replaceably assembled on the bracket;
wherein the impact surface is constructed as a rigid element and is flexibly suspended in the bracket, so as to be movable in a horizontal, vertical, and diagonal direction between a first resting position and a second actuation position that triggers a switch operation of the switch; and
wherein a trigger mechanism is placed between the impact surface and the switch and triggers the switch when the impact surface moves to its actuation position.

US Pat. No. 10,340,094

APPARATUS AND ASSOCIATED METHODS FOR ELECTRICAL STORAGE

Nokia Technologies Oy, E...

1. An apparatus comprising a first charge collector and an ionic layer, the ionic layer configured to absorb water from the surrounding environment to deliver said water to the apparatus, the apparatus comprising:graphene oxide provided on the first charge collector, the graphene oxide configured to generate protons in the presence of water;
a second conductive material spaced apart from the first charge collector, the second material having a lower work function than the first charge collector, the graphene oxide extending from the first charge collector to be in contact with the second material at an interface;
wherein the ionic layer is in contact with the graphene oxide and the second material; and wherein the ionic layer comprises a room temperature ionic fluid and a solidifying material which provides for the ionic layer to be a solid at room temperature.

US Pat. No. 10,340,093

SOLAR CELL SYSTEM AND METHOD FOR OPERATING SOLAR CELL SYSTEM

Panasonic Intellectual Pr...

1. A solar cell system, comprising:a solar cell that includes a first electrode, a second electrode that faces the first electrode, and a light absorbing layer that is located between the first electrode and the second electrode, and converts light into charges;
a power supply that applies voltage between the first electrode and the second electrode; and
a voltage controller, wherein the light absorbing layer contains a compound having a perovskite crystal structure represented by AMX3 where A represents a monovalent cation, M represents a divalent cation, and X represents a halogen anion, and
the voltage controller controls the voltage of the power supply so that during a first period of non-power generation, an electric current of 1 ?A/cm2 or more and 100 ?A/cm2 or less flows in the light absorbing layer in a direction opposite to a direction in which an electric current flows during power generation.

US Pat. No. 10,340,092

SOLID ELECTROLYTIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A solid electrolytic capacitor comprising: at least one capacitor element including an anode portion composed of a metal layer extending in a first direction and having an external surface with a plurality of recesses, a dielectric layer on the external surface of the metal layer, and a cathode portion having a solid electrolyte layer on the dielectric layer and a current collector layer on the solid electrolyte layer; a leading conductor layer electrically connected to the current collector layer; an insulating resin body covering the capacitor element and the leading conductor layer, the insulating resin body having a first end surface and a second end surface opposite to each other along a first direction; a first external electrode including at least one first plating layer on the first end surface, the at least one first plating layer being directly connected to the leading conductor layer; and a second external electrode including at least one second plating layer on the second end surface; the at least one second plating layer being directly connected to the metal layer: the insulating resin body including: (a) a first insulating resin body having the leading conductor layer on a surface thereof, and a second insulating resin body on the first insulating resin body so as to cover the leading conductor layer and the plurality of capacitor elements, the second insulating resin body having a different composition than the first insulating resin body; (b) a first main surface and a second main surface opposite to each other in a second direction orthogonal to the first direction, and a first side surface and a second side surface opposite to each other in a third direction orthogonal to the first direction and the second direction; (c) a first connecting portion connecting the first end surface and the first main surface, a second connecting portion connecting the first end surface and the second main surface, a third connecting portion connecting the second end surface and the first main surface, and a fourth connecting portion connecting the second end surface and the second main surface; the first connecting portion, the second connecting portion, the third connecting portion, and the fourth connecting portion each have a first chamfered portion; wherein: the first external electrode is formed along the first end surface and the first chamfered portions of the first connecting portion and the second connecting portion; and the second external electrode is formed along the second end surface and the first chamfered portions of the third connecting portion and the fourth connecting portion.

US Pat. No. 10,340,091

POLYANION COPOLYMERS FOR USE WITH CONDUCTING POLYMERS IN SOLID ELECTROLYTIC CAPACITORS

KEMET Electronics Corpora...

1. A capacitor comprising:an anode;
a dielectric on said anode; and
a cathode on said dielectric wherein cathode comprises:
a conductive polymer; and
a polyanion wherein said polyanion is a copolymer comprising groups A, B and C represented by the ratio of Formula A:
AxByCz   Formula A
wherein:
A is polystyrenesulfonic acid or a salt of polystyrenesulfonate;
B and C separately represent polymerized units substituted by a group selected from:
-Carboxyl group;
—C(O)OR6 group wherein R6 is selected from the group consisting of:
an alkyl of 1 to 20 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate, anhydride and
—(CHR7CH2O)b—R8 wherein:
R7 is selected from a hydrogen or an alkyl of 1 to 7 carbons;
b is an integer from 1 to the number sufficient to provide a molecular weight of up to 200,000 for the CHR7CH2O— group;
R8 is selected from the group consisting of hydrogen, an alkyl of 1 to 9 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
—C(O)—NHR9 group wherein:
R9 is a hydrogen or an alkyl of 1 to 20 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, alcohol, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
—C6H4—R10 group wherein:
R10 is selected from:
a hydrogen or an alkyl optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
a reactive group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate, anhydride and
—(O(CHR11CH2O)d—R12 wherein:
R11 is a hydrogen or an alkyl of 1 to 7 carbons;
d is an integer from 1 to the number sufficient to provide a molecular weight of up to 200,000 for the CHR11CH2O— group;
R12 is selected from the group consisting of hydrogen, an alkyl of 1 to 9 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
C6H4—O—R13 group wherein:
R13 is selected from:
a hydrogen, an alkyl optionally substituted with a reactive group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, alcohol, phosphate and anhydride;
a reactive group selected from the group consisting of epoxy, silane, phosphate alkene, alkyne, azide, acrylate, anhydride and
—(CHR14CH2O)e—R15 wherein:
R14 is a hydrogen or an alkyl of 1 to 7 carbons;
e is an integer from 1 to the number sufficient to provide a molecular weight of up to 200,000 for the —CHR14CH2O— group;
R15 is selected from the group consisting of a hydrogen and an alkyl of 1 to 9 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
x, y and z, taken together are sufficient to form a polyanion with a molecular weight of at least 100 to no more than 500,000 and y/x is 0.01 to 100; z is 0 to a ratio z/x of no more than 100; and
with the proviso that when z is not zero C is not the same group as B and B is not a polymerized monomer of acrylate, methacrylate or an alkoxysilane.

US Pat. No. 10,340,090

ELECTROLYTIC CAPACITOR, AND PRODUCTION METHOD THEREFOR

PANASONIC CORPORATION, O...

1. An electrolytic capacitor comprising:an anode body;
a dielectric layer formed on the anode body;
a first conductive polymer layer covering at least a part of the dielectric layer;
a second conductive polymer layer covering at least a part of the first conductive polymer layer; and
an intermediate layer formed between the first conductive polymer layer and the second conductive polymer layer; wherein:
the intermediate layer comprises a cation agent containing a cationic group, and an anion agent containing a first anionic group and a second anionic group;
the first anionic group is a sulfonate group;
the second anionic group is at least one of species selected from a phosphate group and a phosphonate group; and
in the intermediate layer, a total of a number of the first anionic group and a number of the second anionic group is larger than a number of the cationic group.

US Pat. No. 10,340,089

METHOD FOR PRODUCING ELECTROLYTIC CAPACITOR

PANASONIC INTELLECTUAL PR...

1. A method for producing an electrolytic capacitor, the method comprising:a first step of preparing a capacitor element that includes an anode body having a dielectric layer;
a second step of impregnating the capacitor element with a first treatment solution containing at least a conductive polymer and a liquid solvent including a first solvent; and
a third step of impregnating, after the second step, the capacitor element, in which at least a part of the first solvent remains, with a second treatment solution containing a coagulant to coagulate the conductive polymer,
wherein a remaining amount of the liquid solvent in the capacitor element to be subjected to the third step is 5% by mass or more relative to a mass of the of the liquid solvent contained in the first treatment solution impregnated into the capacitor element in the second step.

US Pat. No. 10,340,088

THIN-FILM CAPACITOR

TDK CORPORATION, Tokyo (...

1. A thin-film capacitor comprising:a substrate made of a metal material;
a capacitor portion formed partially on one surface of the substrate, the capacitor having a stacked structure from stacking an electrode layer and a dielectric layer alternately;
an insulating layer covering a forming region and a non-forming region, the capacitor portion formed in the forming region and not formed in the non-forming region on the one surface of the substrate;
an electrode terminal disposed on the insulating layer; and
a via conductor configured to penetrate the insulating layer in a thickness direction of the insulating layer and connect the electrode terminal to one of the substrate and the electrode layer of the capacitor portion,
wherein: the substrate is divided into a plurality of parts by a penetration portion penetrating the substrate in a thickness direction of the substrate, and includes a frame portion along an outer edge of the substrate and an electrode portion located inside the frame portion when viewed from the other surface side of the substrate, the electrode portion facing the electrode layer of the capacitor portion through the dielectric layer of the capacitor portion; and
the frame portion includes a communicating channel that extends in a direction orthogonal to the thickness direction of the substrate to connect a frame inside and a frame outside.

US Pat. No. 10,340,087

MULTILAYER ELECTRONIC COMPONENT HAVING FIRST INTERNAL ELECTRODE BASE PATTERNS EXPOSED TO AN END AND OPPOSING SIDE SURFACES OF A BODY, AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. A multilayer electronic component comprising:a body including a multilayer structure in which first internal electrode patterns and second internal electrode patterns different from the first internal electrode patterns are alternately stacked and containing a dielectric material;
first and second side parts disposed on respective outer surfaces of a first pair of opposing outer surfaces of the body; and
first and second external electrodes disposed on respective outer surfaces of a second pair of opposing outer surfaces of the body, the first and second external electrodes electrically connected to the first and second internal electrode patterns, respectively,
wherein the first internal electrode patterns are exposed to the outer surfaces of the first pair of outer surfaces of the body on which the first and second side parts are disposed, and
wherein at least one of the first or second side parts extends from an edge of a corresponding outer surface towards, without reaching, an opposing edge of the corresponding outer surface.

US Pat. No. 10,340,086

MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME

Samsung Electro-Mechanics...

1. A multilayer ceramic capacitor comprising:a ceramic body including a plurality of dielectric layers stacked therein in a width direction;
an active layer including a plurality of first and second internal electrodes alternately disposed with the respective dielectric layers interposed therebetween;
first and second lead parts formed in the first internal electrode to be extended and exposed to a mounting surface of the ceramic body, and disposed to be spaced apart from each other in a length direction of the ceramic body;
a third lead part formed in the second internal electrode to be extended and exposed to the mounting surface of the ceramic body, and disposed between the first and second lead parts;
first and second external electrodes disposed on the mounting surface of the ceramic body to be spaced apart from each other in the length direction of the ceramic body, connected to the first and second lead parts, respectively, and spaced apart from first and second end surfaces of the ceramic body opposing each other in the length direction; and
a third external electrode disposed between the first and second external electrodes, extended from the mounting surface of the ceramic body onto portions of both side surfaces of the ceramic body in the width direction, and connected to the third lead part,
wherein when a thickness of the active layer is defined as AT, and a gap between the first or second lead part and the third lead part is defined as LG, the following Equation is satisfied: 0.00044?LG*log[1/AT]?0.00150,
wherein the first to third external electrodes include conductive layers coming into contact with the lead parts disposed in positions corresponding to the conductive layers, respectively, to thereby be connected to the lead parts, nickel (Ni) plating layers formed to cover the conductive layers, and tin (Sn) plating layers formed to cover the nickel plating layers, and
wherein the conductive layers are formed of the same conductive material as that of the first and second internal electrodes.

US Pat. No. 10,340,085

MULTILAYER CAPACITOR AND INSTALLATION STRUCTURE OF MULTILAYER CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer capacitor comprising:a multilayer capacitor main body which includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction;
a first inner electrode extending in the length direction and the thickness direction and including a first effective portion, a first extending portion, and a second extending portion, the first extending portion being connected to the first effective portion and extending to the second main surface, and the second extending portion being connected to the first effective portion and extending to the second main surface;
a second inner electrode extending in the length direction and the thickness direction and including a second effective portion and a third extending portion, the second effective portion facing the first effective portion in the width direction, and the third extending portion being connected to the second effective portion, not facing the first inner electrode, and extending to the second main surface;
a first terminal electrode which is connected to an exposed portion of the first extending portion and extends across a portion of the second main surface on a side of the first end surface in the length direction, the first end surface, and the first and second side surfaces;
a second terminal electrode which is connected to an exposed portion of the second extending portion and extends across a portion of the second main surface on a side of the second end surface in the length direction, the second end surface, and the first and second side surfaces; and
a third terminal electrode which is connected to an exposed portion of the third extending portion and extends across a portion of the second main surface between the first terminal electrode and the second terminal electrode in the length direction and the first and second side surfaces; wherein
the first main surface is a concave surface which is depressed to extend inward in the thickness direction from edges of the first main surface towards a center of the first main surface in the width direction; and
in the thickness direction, a thickness of the third terminal electrode on the second main surface is larger than a thickness of at least one of the first and second terminal electrodes on the second main surface.

US Pat. No. 10,340,084

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers including a co-material are alternately stacked,
wherein a Mo concentration in the co-material is smaller than that in a ceramic grain in the ceramic dielectric layer,
wherein a Mg concentration in the ceramic grain is smaller than that in the co-material.

US Pat. No. 10,340,083

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component that is able to be mounted on a mounting substrate including a pair of first edge portions that faces each other, and a pair of second edge portions that is perpendicular or substantially perpendicular to the pair of first edge portions and faces each other, the mounting substrate including a structure that allows at least any one of the electronic component, a first electronic component, and a second electronic component to be mounted thereon;the first electronic component including:
a first laminate including a plurality of first dielectric layers and a plurality of first inner electrode layers, which are laminated, a pair of first principal surfaces facing each other in a lamination direction, a pair of first side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of first end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction; and
a pair of first external electrodes each extending from a corresponding one of the pair of first end surfaces to a portion of the pair of first principal surfaces and to a portion of the pair of first side surfaces;
the second electronic component including:
a second laminate including a plurality of second dielectric layers and a plurality of second inner electrode layers, which are laminated, a pair of second principal surfaces facing each other in a lamination direction, a pair of second side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of second end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction; and
a pair of second external electrodes each extending from a corresponding one of the pair of second end surfaces to a portion of the pair of second principal surfaces and to a portion of the pair of second side surfaces; wherein
a dimension of the first electronic component in the length direction is designated as L1, a dimension of the first electronic component in the width direction is designated as W1, a dimension of the second electronic component in the length direction is designated as L2, and a dimension of the second electronic component in the width direction is designated as W2;
a length W3 of the pair of first edge portions is a least common multiple of the W1 and the W2; and
a length L3 of the pair of second edge portions is a least common multiple of the L1 and the L2;
the electronic component including:
a third laminate including a plurality of third dielectric layers and a plurality of third inner electrode layers, which are laminated, a pair of third principal surfaces facing each other in a lamination direction, a pair of third side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of third end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction; and
a pair of third external electrodes each extending from a corresponding one of the pair of third end surfaces to a portion of the pair of third principal surfaces and to a portion of the pair of third side surfaces; wherein
a dimension of the electronic component in the width direction is any one of the W1 and the W2; and
a dimension of the electronic component in the length direction is the L2 when the dimension of the electronic component in the width direction is the W1; and
a dimension of the electronic component in the length direction is the L1 when the dimension of the electronic component in the width direction is the W2.

US Pat. No. 10,340,081

CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A ceramic capacitor comprising:a capacitor main body including first and second principal surfaces extending in a length direction and a width direction perpendicular or substantially perpendicular to the length direction, first and second side surfaces extending in the length direction and a laminating direction perpendicular or substantially perpendicular to each of the length direction and the width direction, and first and second end surfaces extending in the width direction and the laminating direction;
a plurality of internal electrodes disposed in the capacitor main body, and exposed at each of the first and second side surfaces; and
a plurality of external electrodes extending from exposed portions of the internal electrodes at the first side surface and exposed portions of the internal electrodes at the second side surface to the first and second principal surfaces; wherein
each of the plurality of internal electrodes includes:
a first internal electrode; and
a second internal electrode opposed to the first internal electrode in the laminating direction;
the first internal electrode includes:
a first opposed portion opposed to the second internal electrode;
first and second extended portions connected to the first opposed portion, and each extended to the first side surface; and
third and fourth extended portions connected to the first opposed portion, and each extended to the second side surface;
the second internal electrode includes:
a second opposed portion opposed to the first opposed portion;
a fifth extended portion connected to the second opposed portion, and extended to the first side surface; and
a sixth extended portion connected to the second opposed portion, and extended to the second side surface;
each of the plurality of external electrodes includes:
a first external electrode covering an exposed portion of the first extended portion at the first side surface and an exposed portion of the third extended portion at the second side surface, and wrapping around the first side surface, the first principal surface, the second side surface, and the second principal surface;
a second external electrode covering an exposed portion of the second extended portion at the first side surface and an exposed portion of the fourth extended portion at the second side surface, and wrapping around the first side surface, the first principal surface, the second side surface, and the second principal surface; and
a third external electrode covering an exposed portion of the fifth extended portion at the first side surface and an exposed portion of the sixth extended portion at the second side surface, and wrapping around the first side surface, the first principal surface, the second side surface, and the second principal surface; wherein
each of the first, second and third external electrodes includes a sputtered electrode film that is in direct contact with the capacitor main body;
each of outermost layers of the first, second and third external electrodes contains Cu; and
a length of a portion of the third external electrode located on the first or second principal surface in the length direction is larger than a length of a portion of the third external electrode located on the first or second side surface in the length direction.

US Pat. No. 10,340,080

METHOD OF MANUFACTURING A GREEN COMPACT

SUMITOMO ELECTRIC INDUSTR...

1. A method of manufacturing a green compact, the method comprising:a filling step of filling a compacting space with an insulated coated soft magnetic powder, the compacting space being defined by a die that has a through hole with which a part of the outer surface of the green compact is molded by the through hole, a core rod with which another part of the outer surface of the green compact is molded, and a first punch disposed so as to cover one of opening portions of the through hole, the core rod being inserted and disposed in a space of the through hole, and the core rod being penetrated through the first punch
wherein the insulation of the insulated coated soft magnetic powder insulates the soft magnetic powder from a conduction of electrical current;
a pressurizing step of pressurizing the coated soft magnetic powder in the compacting space using the first punch and a second punch disposed so as to face the first punch, and
a removing step of removing a green compact from the die, said green compact having been obtained after pressurizing the coated soft magnetic powder, from the compacting space by moving the die with respect to the formed green compact without moving the core rod with respect to the formed green compact,
wherein a surface of the through hole of the die contacts with an outer surface of the core rod, excluding end faces of the core rod.

US Pat. No. 10,340,079

CURRENT TRANSFORMER

SEARI ELECTRIC TECHNOLOGY...

1. A current transformer comprising:a closed magnetic circuit, a first part of the closed magnetic circuit completely surrounding a primary conductor;
a second part of the closed magnetic circuit forming one or more secondary windings, the second part of the closed magnetic circuit serving as a magnetic core of the one or more secondary windings;
wherein,
the closed magnetic circuit forms a plurality of branch magnetic circuits at the second part, and one secondary winding is formed on each branch magnetic circuit, each branch magnetic circuit serves as the magnetic core of the corresponding secondary winding, each secondary winding is staggered with each other in at least one of a length direction, a height direction, and a thickness direction;
the plurality of branch magnetic circuits formed at the second part of the closed magnetic circuit are mutually staggered in the length direction and the height direction, and each branch magnetic circuit forms the closed magnetic circuit with the first part; and
wherein, in the height direction, a sum of heights of the plurality of branch magnetic circuits is equal to a height of the first part of the closed magnetic circuit.

US Pat. No. 10,340,077

FEED UNIT, FEED SYSTEM, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A feed unit, comprising:a power transmission section that includes a power transmission coil configured to transmit electric power by a magnetic field; and
an auxiliary resonance section that includes at least one resonator,
wherein the at least one resonator includes an auxiliary coil of a plurality of windings,
wherein the auxiliary coil is wound such that at least one gap is created between a first winding of the plurality of windings and a second winding of the plurality of windings,
wherein the first winding is adjacent to the second winding,
wherein a first width of the at least one gap in a first axis direction is larger than a second width of the at least one gap in a second axis direction, and
wherein the second axis direction is orthogonal to the first axis direction.

US Pat. No. 10,340,076

INTEGRATED COPPER BAR FOR SECONDARY POWER CIRCUIT OF POWER ELECTRONIC CONVERTER

United Automotive Electro...

1. An integrated copper bar for a secondary power circuit of a power electronic converter, comprising a transformer primary winding copper bar, a transformer secondary winding copper bar, an inductor winding copper bar, a copper bar for connecting a detection resistor, a copper bar for connecting a drive circuit and a copper bar for connecting an output terminal;said transformer primary winding copper bar, said transformer secondary winding copper bar, said inductor winding copper bar, said copper bar for connecting a detection resistor, said copper bar for connecting a drive circuit and said copper bar for connecting an output ground terminal are fixed together via injection molding; wherein,
said transformer secondary winding copper bar comprises a secondary winding, a first drain pin, a second drain pin, an upper pin of said secondary winding and a lower pin of said secondary winding;
said secondary winding comprises a copper bar of the upper coil of said secondary winding and a copper bar of the lower coil of said secondary winding, with said copper bar of the upper coil and said copper bar of the lower coil each shaped as an open loop, the copper bar of the upper coil of the secondary winding and the copper bar of the lower coil of the secondary winding are disposed in two different planes, and connected at one end to form a central tap, with the other ends extending forward, respectively;
said first drain pin and said upper pin of said secondary winding are together formed on a forward extension of said copper bar of the upper coil of said secondary winding, with said first drain pin disposed in front of said upper pin of said secondary winding;
said second drain pin and said lower pin of said secondary winding are together formed on a forward extension of said copper bar of the lower coil of said secondary winding, with said second drain pin disposed in front of said lower pin of said secondary winding;
said first drain pin and said second drain pin are parallel to the plane on which said copper bar of the upper coil of said secondary winding and said copper bar of the lower coil of said secondary winding are formed;
said upper pin of said secondary winding and said lower pin of said secondary winding are perpendicular to the plane on which said copper bar of the upper coil of said secondary winding and said copper bar of the lower coil of said secondary winding are formed.

US Pat. No. 10,340,075

METHOD AND DEVICE FOR INSULATION OF HIGH-VOLTAGE GENERATOR TANK

SHANGHAI UNITED IMAGING H...

1. A high-voltage generator tank, comprising:a tank with a tank lid, the tank lid having an opening; and
a bellows coupled to the tank, the bellows having a guide structure configured to lead the bellows to extend or shorten axially and fix the bellows,
wherein
the bellows comprises an opening having an open end and a closed end, wherein the open end of the opening of the bellows is fixed to the opening in the tank lid.

US Pat. No. 10,340,074

TRANSFORMER

CYNTEC CO., LTD., Hsinch...

1. A transformer comprising:a first core having a central hole;
a second core disposed in the central hole, the second core having two flanges and a pillar located between the two flanges, a winding space being located among the two flanges and the pillar;
a plurality of electrodes disposed on the first core, each of the electrodes having a first platform and a second platform higher than the first platform, the first platform being protruded from a surface of the first core, the second platform being protruded from the first platform;
an inner winding wound around the pillar and located in the winding space, a first winding end of the inner winding being electrically connected to one of the electrodes, the inner winding comprising a first wire and a first insulating layer covering the first wire; and
an outer winding wound around the inner winding and located in the winding space, a second winding end of the outer winding being electrically connected to one of the electrodes, the outer winding comprising a second wire and a second insulating layer covering the second wire, second thickness of the second insulating layer being larger than first thickness of the first insulating layer.

US Pat. No. 10,340,073

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil component comprising: a body part containing a magnetic material; a coil part disposed in the body part; and an electrode part disposed on the body part, wherein the coil part includes a support member, a first coil layer directly disposed on at least one surface of the support member, a first insulating layer stacked on at least one surface of the support member, having a composition different from the support member, and covering the first coil layer, and a second coil layer directly disposed on the first insulating layer, and the first and second coil layers are electrically connected to each other, and the second coil layer has a larger number of coil turns than the first coil layer; wherein the first coil layer includes a coil pattern having an aspect ratio less than 1, and the second coil layer includes a coil pattern having an aspect ratio exceeding 1.

US Pat. No. 10,340,072

ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

Murata Manufacturing Co.,...

1. An electronic component, comprising:a body made of a material containing particles of a metallic magnetic material; and
an outer electrode disposed on a surface of the body,
wherein,
the surface of the body has a contact portion which is in direct contact with the outer electrode, and the contact portion includes particles of the metallic magnetic material which are exposed from the surface of the body,
surfaces of the particles of the metallic magnetic material are coated with respective insulating films, and
at the contact portion, the insulating films are removed to expose the particles of the metallic magnetic material.

US Pat. No. 10,340,071

MAGNETIC CIRCUIT FOR CARRYING AT LEAST ONE COIL

1. A magnetic circuit for carrying at least one coil, the circuit comprising:at least one inner leg and at least two outer legs; and
a connecting part serving to guide the magnetic flux from the inner leg to each outer leg,
each outer leg having no non-magnetic gap and the inner leg being at least partially made from one or more materials that have a relative magnetic permeability that is lower than that of the material or materials of which the outer legs are formed,
each outer leg being made as a single piece in one and the same material from one outer leg to the other and the relative magnetic permeability of the material of a portion of the inner leg being lower than the relative magnetic permeability of the material of the outer legs,
the ratio between the relative magnetic permeability of the material of said portion of the inner leg and the relative magnetic permeability of the material of the outer legs being comprised between 0.001 and 0.033, and
wherein the inner leg comprises a plurality of successive transverse sections that are homothetic images of one another, having a ratio of less than one from one section to an adjacent section of the plurality of successive transverse sections with increasing proximity to the connecting part.

US Pat. No. 10,340,070

MULTILAYER COMMON MODE FILTER

TDK CORPORATION, Tokyo (...

4. A multilayer common mode filter comprising:an element body including a pair of principal surfaces opposing each other in a first direction; and
a first coil, a second coil and a third coil disposed in the element body and configured to be magnetically coupled to each other, wherein:
the first coil includes a first coil conductor and a second coil conductor having spiral shapes and is configured by electrically connecting the first coil conductor and the second coil conductor;
the second coil includes a third coil conductor and a fourth coil conductor having spiral shapes and is configured by electrically connecting the third coil conductor and the fourth coil conductor;
the third coil includes a fifth coil conductor and a sixth coil conductor having spiral shapes and is configured by electrically connecting the fifth coil conductor and the sixth coil conductor;
the first to sixth coil conductors are disposed in order of the first coil conductor, the third coil conductor, the fifth coil conductor, the second coil conductor, the fourth coil conductor, and the sixth coil conductor in the first direction;
a total value of the number of windings of the first coil conductor and the number of windings of the second coil conductor is smaller than a total value of the number of windings of the third coil conductor and the number of windings of the fourth coil conductor; and
a total value of the number of windings of the fifth coil conductor and the number of windings of the sixth coil conductor is smaller than the total value of the number of windings of the third coil conductor and the number of windings of the fourth coil conductor.

US Pat. No. 10,340,069

CENTRAL ACTUATOR FOR CAM PHASER

ECO Holding 1 GmbH, Mark...

11. A central actuator for a magnet valve of a cam phaser, the central actuator comprising:a housing that envelops the central actuator;
a pole tube and a pole core that are arranged within at least one coil that generates a magnetic field;
an actuation plunger that is arranged at an armature that is axially movable in a direction in an armature cavity;
a closure element that closes the armature cavity,
wherein the closure element includes at least one pole core insert that includes a central bore hole and a support bushing that is arranged in the central bore hole of the at least one pole core insert,
wherein the actuation plunger is supported axially movable in the support bushing,
wherein the closure element includes a closure cover and is provided as a pre-assembled module, and
wherein the support bushing includes a shoulder on a side that is oriented towards the armature that provided a stop for the armature and limits an axial movement of the armature.

US Pat. No. 10,340,068

CURRENT FEED-THROUGH

Siemens Healthcare Limite...

1. A current feed-through for a continuous superconducting circuit having a circuit component inside a cryogen vessel and a circuit component outside of said cryogen vessel, said current feed-through comprising:a mounting fixture having an attachment structure designed to attach the mounting fixture to a wall of the cryogen vessel in order to place an exterior side of said mounting fixture in a vacuum environment and an interior side of said mounting fixture in a cryogenic environment;
a member proceeding through said mounting fixture and being accessible from both of said sides of the mounting fixture;
an electrical isolator, connecting the mounting fixture and the member in respective positions, to ensure mechanical integrity and electrical isolation between the mounting fixture and the member; and
said member having a bore therein, and a single, continuous superconducting wire proceeding through said bore so as to be accessible from both sides of the mounting fixture in order to electrically connect the respective components of said continuous superconducting circuit inside and outside of said cryogen vessel, the superconducting wire being bonded and sealed to the bore and thereby maintained in a superconducting state in said mounting fixture by said cryogenic environment.

US Pat. No. 10,340,066

METHOD AND SYSTEM FOR CONTROLLED NANOSTRUCTURING OF NANOMAGNETS

Clarkson University, Pot...

1. A composite magnetic matrix comprising: (i) a porous metal-organic framework (MOF); and (ii) a plurality of molecular magnets, wherein a plurality of pores of the MOF each comprise one of the plurality of molecular magnets, and wherein the each of the plurality of molecular magnets retains its magnetic properties in the matrix.

US Pat. No. 10,340,065

METHOD FOR MANUFACTURING ELECTRICAL STEEL SHEET

1. A method for manufacturing an electrical steel sheet, comprising: applying a treatment solution on a surface of a base iron: andbaking and drying the treatment solution,
wherein the treatment solution contains:
a first component: 100 parts by mass in solid content, the first component consisting of:
a colloidal silica having an average particle size of 5 nm to 40 nm and having an Na content of 0.5 mass % or less: 100 parts by mass; and
an emulsion of one kind selected from the group consisting of an acrylic resin, an epoxy resin and a polyester resin which have an average particle size of 0.05 um to 0.25 um, or an emulsion of a mixture or copolymer of two or three kinds selected from the group: 40 parts by mass to 400 parts by mass in resin solid content; and
a second component consisting of particles of one or more kinds selected from the group consisting of a polyolefin wax, an epoxy resin and an acrylic resin, the particles having an average particle size of 2.0 um to 15.0 um and a melting point of 60° C. to 140° C.: 5 parts by mass to 40 parts by mass in resin solid content,
wherein a solid content of the treatment solution substantially consists of the first component and the second component.

US Pat. No. 10,340,063

CHIP RESISTOR AND METHOD FOR MANUFACTURING THE SAME

PANASONIC INTELLECTUAL PR...

1. A chip resistor comprising:a resistive element made of a metal having a plate shape having an upper surface, a lowermost surface, a first edge surface connected to the upper surface and the lowermost surface, and a second edge surface connected to the upper surface and the lower surface, the second edge surface being opposite to the first edge surface, the resistive element having a first recess and a second recess therein, the first recess extending from the lowermost surface along the first edge surface and not reaching the upper surface, the second recess extending from the lowermost surface along the second edge surface and not reaching the upper surface;
a first electrode disposed on the lowermost surface of the resistive element and between the first recess and the second recess;
a second electrode disposed on the lowermost surface of the resistive element and between the first recess and the second recess;
a protective film disposed on the lowermost surface of the resistive element and between the first electrode and the second electrode;
a first plating layer disposed on the first electrode and an inner surface of the first recess; and
a second plating layer disposed on the second electrode and an inner surface of the second recess.

US Pat. No. 10,340,062

ELECTRIC WIRE BUNDLE, APPARATUS FOR MANUFACTURING ELECTRIC WIRE BUNDLE, AND METHOD FOR MANUFACTURING ELECTRIC WIRE BUNDLE

AUTONETWORKS TECHNOLOGIES...

1. An electric wire bundle comprising:an electric wire group including a bundle portion in which at least a portion of a plurality of electric wires in an extension direction is bundled together; and
a binding portion formed by supplying a fluid binding portion forming material from a nozzle that is rotated relatively around an outer circumference of the bundle portion to an outer circumferential portion of the bundle portion in strip-shape in a form in which the bundle portion can be maintained in a bundled condition, by moving the nozzle with a movement mechanism around the outer circumference of the bundle portion, and curing the binding portion forming material,
wherein the binding portion is formed in a mesh shape.

US Pat. No. 10,340,061

DATA LINE AS WELL AS METHODS FOR PRODUCING THE DATA LINE

LEONI Kabel Holding GmbH,...

1. A data line comprising:a line core extending in a longitudinal direction, the line core formed of at least one conductor and an insulation, the at least one conductor surrounded by the insulation; and
a shielding foil that surrounds the insulation,
wherein the shielding foil is formed of a non-conductive layer with a first conductive layer attached to an outer side of the non-conductive layer and a second conductive layer attached to an inner side of the non-conductive layer, the outer side of the non-conductive layer opposing the inner side of the non-conductive layer,
wherein the shielding foil surrounds the insulation such that a first free end edge of the shielding foil overlaps a second free end edge of the shielding foil in an overlap region,
wherein a region of the shielding foil directly adjacent the overlap region is an additional partial region,
wherein a distal end face of a first free end edge of the first and second conductive layers is electrically conductively connected to an outer side of the first conductive layer provided in the additional partial region by an electrically conductive connection, the distal end face of the first conductive layer extending between the outer side and an inner side of the first conductive layer and the distal end face of the second conductive layer extending between an outer side and an inner side of the second conductive layer,
wherein the electrically conductive connection is an additional conductive strip attached to the shielding foil so that the additional conductive strip is directly attached to the distal end face of the first and second conductive layers and to the additional partial region, so as to electrically connect the distal end face of the first and second conductive layers with the additional partial region, and
wherein the additional conductive strip extends over and is directly attached to a portion of the outer side of the first conductive layer at the first free end edge, such that the additional conductive strip is substantially s-shaped in cross-section.

US Pat. No. 10,340,060

OVERCURRENT PROTECTION DEVICES AND CIRCUITS FOR SHIELDED CABLES

RIMKUS CONSULTING GROUP, ...

1. A device for preventing overcurrent in one or more shielded coaxial communication cables, the device comprising:an input element having a shield input and a signal input, the input element adapted to receive a first shielded coaxial communication cable having a first shield conductor and a first signal conductor;
an output element having a shield output and a signal output, the output element adapted to receive a second shielded coaxial communication cable having a second shield conductor and a second signal conductor;
a shield breaking element coupled between the shield input of the input element and the shield output of the output element, the shield breaking element configured for electrical connection in series between the first shield conductor of the first shielded coaxial communication cable and the second shield conductor of the second shielded coaxial communication cable;
a signal breaking element coupled between the signal input of the input element and the signal output of the output element, the signal breaking element configured for electrical connection in series between the first signal conductor of the first shielded coaxial communication cable and the second signal conductor of the second shielded coaxial communication cable and;
an interlocking element communicatively coupled between the shield breaking element and the signal breaking element,
wherein the shield breaking element is configured to open upon conducting a first electrical current that exceeds an overcurrent threshold, the opening of the shield breaking element configured to prevent the first electrical current from flowing through the first shield conductor of the first shielded coaxial communication cable and the second shield conductor of the second shielded coaxial communication cable, and
wherein the signal breaking element is configured to open upon activation of the interlocking element when the shield breaking element opens, the opening of the signal breaking element configured to prevent a second electrical current from flowing through the first signal conductor of the first shielded coaxial communication cable and the second signal conductor of the second shielded coaxial communication cable.

US Pat. No. 10,340,059

SHIELDED ELECTRICAL CABLE

3M Innovative Properties ...

1. A shielded electrical cable, comprising:a plurality of differential pairs extending along a length of the cable and arranged generally in a plane along a width of the cable, each differential pair including two insulated conductors having wire diameters not greater than 24 American Wire Gauge (AWG), each differential pair substantially surrounded by a shield;
a non-conductive polymeric layer covering opposite sides of the plurality of differential pairs and including cover portions arranged such that, in transverse cross section, the cover portions of the polymeric layer substantially surrounds each differential pair; and
an adhesive layer bonding the polymeric layer to the differential pairs;
wherein a maximum separation between the cover portions of the polymeric layer is D, a minimum separation between the cover portions of the polymeric layer in a region between the conductors of each differential pair is d1, d1/D greater than 0.33;
wherein a transverse bending of the cable at a cable location of 90 degrees over an inner radius of at most 5 mm causes an insertion loss of the insulated conductors of the differential pairs proximate the cable location to vary by no more than about 0.5 dB from an initial insertion loss measured at the cable location in an unbent configuration;
wherein a high frequency electrical isolation of a first insulated conductor of a first differential pair in the plurality of differential pairs relative to a second insulated conductor of the first differential pair is substantially less than a high frequency electrical isolation of the first differential pair relative to an adjacent second differential pair in the plurality of differential pairs; and
wherein the cable has a skew of less than about 20 psec/meter.

US Pat. No. 10,340,058

CABLE WITH BRAIDED SHIELD

Hitachi Metals, Ltd., To...

1. A cable with braided shield, comprising:a conductor;
an insulation layer arranged to cover a periphery of the conductor;
a braided shield layer arranged to cover a periphery of the insulation layer; and
a sheath arranged to cover a periphery of the braided shield layer,
wherein the braided shield layer comprises an inner braided shield layer, and an outer braided shield layer provided on a periphery of the inner braided shield layer,
wherein the inner braided shield layer comprises a braided shield braided to cross metal wires,
wherein the outer braided shield layer comprise a braided shield braided to cross a copper tinsel wire and a metal wire, and
wherein the cable with braided shield satisfies D1>D2, where D1 is an outer diameter of the copper tinsel wire of the outer braided shield layer, and D2 is an outer diameter of the metal wire of the outer braided shield layer.

US Pat. No. 10,340,057

UNIFIED POWER AND DATA CABLE

CISCO TECHNOLOGY, INC., ...

1. A cable comprising:a data transmission path disposed about an axial center of the cable, the data transmission path including:
a plurality of insulated conductive paths, wherein the plurality of insulated conductive paths extend along a longitudinal axis of the cable; and
a divider that separates the plurality of insulated conductive paths from each other;
a power transmission path sheathing the data transmission path, wherein the power transmission path includes
a power layer that is a solid conductor plane as a current source path,
a ground layer that is a ground plane as a current return path for bidirectional power transmission, and
a dielectric layer located between the power layer and the ground layer, wherein a capacitance value of the power transmission path satisfies a threshold capacitance value within a predefined tolerance range at frequencies above a first frequency level based on a function of (A) a thickness of the dielectric layer that is less than a predetermined thickness threshold and (B) a permittivity value corresponding to a material of the dielectric layer that meets a predetermined permittivity threshold;
a shield layer located between the data transmission path and the power transmission path; and
a first connector terminating a first end of the cable and a second connector terminating a second end of the cable, wherein the first and the second connectors are configured to connect to first and second devices, respectively, for coupling the data transmission path between the first and the second devices for bidirectional data transmission and for coupling the power transmission path between the first and the second devices for redundant bidirectional power transmission.

US Pat. No. 10,340,056

FLAT CABLE AND WIRE HARNESS

YAZAKI CORPORATION, Mina...

1. A flat cable comprising:at least one cable portion which includes:
a plurality of conductor wires arranged in parallel at predetermined intervals on a plane; and
a coating portion that collectively covers the plurality of conductor wires arranged in parallel, the coating portion being made of an insulating resin; and
at least one rib portion provided in parallel with the cable portion on the plane and to which a bus bar is to be fixed, and the at least one rib portion is made of only the same resin as the coating portion,
wherein a body including the at least one cable portion and the at least one rib portion is substantially bilaterally symmetrical in a cross-sectional structure of the body;
wherein the at least one cable portion has a first cable portion and a second cable portion;
wherein the first cable portion, the rib portion, and the second cable portion are arranged in the body on the plane in this order;
wherein an object arranged at a center in the body in a cross-section thereof is the rib portion, a central portion of the rib portion of the body in the cross-section is set as a boundary line; and
wherein a ratio of amounts of resin in a left part and a right part of the body is 1:0.85 or more when one part of the body having a larger amount of resin is set to 1, the left part of the body being arranged at a left side from the boundary line and the right part of the body being arranged at a right side from the boundary line.

US Pat. No. 10,340,054

POLYMER COMPOSITES WITH ELECTROMAGNETIC INTERFERENCE MITIGATION PROPERTIES

3M Innovative Properties ...

1. A composite comprising:a lossy polymeric matrix, wherein the lossy polymeric matrix has a dielectric loss tangent of from 0.005 to 0.50; and
a mixture of ceramic particles comprising copper oxide (CuO) particles and conductive particles dispersed within the polymeric matrix, wherein the conductive particles are selected from the group consisting of carbon black, carbon bubbles, carbon foams, graphene, carbon fibers, graphite, carbon nanotubes, PAN fibers, conductive-coated particles, or a combination thereof; wherein the composite is an electromagnetic interference mitigating material, wherein:
the lossy polymeric matrix comprises epoxy-based polymeric matrix, and the conductive particles comprise carbon black; or
the lossy polymeric matrix is selected from the group consisting of epoxy-based polymeric matrix prepared from one or more bisphenol-A-based epoxy resins, one or more bisphenol-F-based epoxy resins, one or more phenol novolac-based epoxy resins, or a combination thereof.

US Pat. No. 10,340,053

RADIATION-IRRADIATION DEVICE

FUJIFILM CORPORATION, To...

1. A radiation-irradiation device comprising:a radiation generating unit that generates radiation;
a collimator unit that controls an irradiation range to be irradiated with the radiation generated by the radiation generating unit; and
an interval ensuring unit that includes a contact member being in contact with a subject to be irradiated with the radiation in a case in which a distance between the radiation generating unit and the subject is shorter than a preset distance, and ensures an interval between the radiation generating unit and the subject,
wherein the interval ensuring unit is detachably mounted on the collimator unit and is capable of being mounted at different rotational positions about an axis, which passes through a center of a diaphragm of the collimator unit and extends in a direction of an optical axis of the radiation, as a central axis.

US Pat. No. 10,340,052

SINGLE CELL APPARATUS AND METHOD FOR SINGLE ION ADDRESSING

Honeywell International I...

1. An apparatus for single ion addressing, comprising:a fiber bundle configured to split a laser beam into a plurality of components; and
a single optical cell configured to:
shutter a single one of the plurality of components of the laser beam;
align the shuttered single component of the laser beam to an ion in a surface ion trap such that the ion fluoresces light and/or performs a quantum operation when the ion is illuminated by the shuttered single component of the laser beam; and
detect the light fluoresced from the ion when the ion is illuminated by the shuttered single component of the laser beam.

US Pat. No. 10,340,051

RADIOISOTOPE PRODUCTION SYSTEM AND METHOD FOR CONTROLLING THE SAME

General Electric Company,...

1. A radioisotope production system comprising:an electrical field system and a magnetic field system configured to direct a particle beam of charged particles along a beam path within an acceleration chamber, the magnetic field system including a magnet yoke and an electromagnet that is energized by a drive current to generate a magnetic flux into the acceleration chamber for controlling the particle beam;
a target system configured to hold a target material and receive the particle beam;
an extraction unit, wherein the particle beam is configured to pass through the extraction unit and exit the acceleration chamber toward the target system; and
a monitoring system including a processing unit that, for a plurality of times during a production session of the radioisotope production system, is configured to:
(a) determine an operating parameter of the radioisotope production system, the operating parameter including a target current or a function of the target current, the target current being detected as the particle beam is incident upon the target material; and
(b) change the drive current, thereby changing the magnetic flux, based on the operating parameter;
wherein the monitoring system is configured to obtain data of the operating parameter at one or more drive currents, wherein the monitoring system is configured to analyze the data to identify a new drive current, the monitoring system configured to change the drive current to the new drive current;
wherein the monitoring system is configured to obtain the data by sweeping the drive current back-and-forth within a designated range such that the data of the operating parameter includes values of the operating parameter at different drive currents; and
wherein the data includes data sets, each of the data sets includes a first operating parameter and a second operating parameter for a designated drive current, the monitoring system configured to select a first sub-group of the data sets based on the first operating parameters and configured to select a second sub-group of the data sets from the first sub-group based on the second operating parameters, the new drive current being based on the designated drive currents of the data sets in the second sub-group.

US Pat. No. 10,340,047

HEALTH TREND IDENTIFICATION

International Business Ma...

1. A computer-implemented method performed on a processor executing method steps comprising:collecting a set of sequence of numbers comprising one or more digits accessed by a user;
determining a frequency for each of the one or more digits in the set of sequence of numbers;
determining a set of categories for each of the one or more digits based on either an associated utility for the sequence of numbers or a mode of entry for the sequence of numbers;
determining that the frequency of at least one of the one or more digits exceeds a threshold value, wherein the threshold value serves as a trigger to identify a first subset of categories from the determined set of categories associated with each of the one or more digits;
responsive to determining that the frequency of at least one of the one or more digits exceeds a threshold value, identifying a set of health risks associated with the first subset of categories of the determined set of categories associated with each of the one or more digits wherein identifying a set of health risks associated with the first subset of categories comprises:
determining the first subset of categories from the determined set of categories associated with a digit of a sequence of numbers of the set of sequence of numbers having a greater frequency of use for the digit of the first sequence of numbers in comparison to a second subset of categories associated with the digit of the sequence of numbers;
linking a respective behavior to the first subset based on either an associated utility for the sequence of numbers or a mode of entry for the sequence of numbers;
accessing a set of medical documentation that detail a set of health risks and a set of behaviors that cause each health risk in the set of health risks;
matching the respective linked behavior to a behavior specified in the set of medical documentation; and
identifying a set of health risks from the set of medical documentation that matches the respective linked behavior;
generating, a health risk notification that includes a health risk report based on the identified set of health risks;
issuing the generated health risk notification to a person of interest based, at least in part, on the identified set of health risks;
generating a user interactive interface that displays the issued health risk notification, wherein the generated user interactive interface includes one or more graphical icons and selectable fields that can modify the health risk report;
receiving, one or more user selected options from the generated user interactive display; and
responsive to receiving the one or more user selected options from the generated user interactive display, modifying the health risk report to increase or decrease a health risk based on the received one or more user selected options.

US Pat. No. 10,340,046

NETWORK FOR MEDICAL IMAGE ANALYSIS, DECISION SUPPORT SYSTEM, AND RELATED GRAPHICAL USER INTERFACE (GUI) APPLICATIONS

Progenics Pharmaceuticals...

1. A network-based decision support system comprising:a processor; and
a memory having instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to perform functions (i) to (v) as follows:
(i) receive and store a plurality of medical images in a database, each medical image associated with a particular patient;
(ii) access one or more of the medical images or related data associated with a particular patient from the database upon user request for transmission to the user for display on a user computing device;
(iii) automatically analyze one or more of the medical images;
(iv) generate a radiologist report for a patient according to one or more of the medical images for the patient; and
(v) apply a machine learning algorithm to update a process for automatically analyzing one or more of the medical images using accumulated image data in the database,
wherein the plurality of medical images comprise a positron emission tomography (PET) scan of a first patient obtained following administration to the first patient of an imaging agent comprising [18F]DCFPyL, and a CT scan of the first patient, wherein the instructions cause the processor to overlay the PET scan with the CT scan to create a composite image (PET-CT) of the first patient.

US Pat. No. 10,340,044

MEDICAL SCAN IMAGE ANALYSIS SYSTEM

Enlitic, Inc., San Franc...

1. A medical scan image analysis system, comprising:a processing system that includes a processor; and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations comprising:
receiving a plurality of medical scans via a network, wherein each of the plurality of medical scans represents a three-dimensional anatomical region and includes a plurality of cross-sectional image slices;
generating a plurality of three-dimensional subregions corresponding to each of the plurality of medical scans by selecting a proper subset of the plurality of cross-sectional image slices from each of the plurality of medical scans, and by further selecting a two-dimensional subregion from each proper subset of the plurality of cross-sectional image slices of the each of the medical scans;
performing a learning algorithm on the plurality of three-dimensional subregions to generate a fully convolutional neural network;
receiving a new medical scan that is not included in the plurality of medical scans;
generating inference data corresponding to the new medical scan by performing a first inference algorithm on the new medical scan by utilizing the fully convolutional neural network; and
identifying an inferred abnormality in the new medical scan based on the inference data;
wherein performing the learning algorithm includes utilizing a forward propagation algorithm on the plurality of three-dimensional subregions to generate a preliminary set of neural network parameters, and by utilizing a back propagation algorithm to generate an updated set of neural network parameters based on a calculated set of parameter errors and the preliminary set of neural network parameters, and wherein performing the first inference algorithm includes utilizing the forward propagation algorithm on the new medical scan based on the updated set of neural network parameters.

US Pat. No. 10,340,043

SYSTEM AND METHOD FOR LOGISTICAL MANAGEMENT, SUPPORT AND SUPPLY OF OBJECTS

Butterfly Healthcare Pty....

1. A system for providing logistical management, support and supply of medical supplies for consumption or use on a dynamic basis at one or more localities within a precinct or facility associated with the healthcare industry, wherein the precinct or facility sources the medical supplies from a store, the system comprising:(a) an external processing system defining an environment that is operable to allow access by a plurality of subscribers to relevant parts of a data store providing master data on medical supplies stored in the store;
(b) a plurality of mobile devices for use by a plurality of types of the plurality of subscribers to setup templates defining the prescribed use of the medical supplies in a variety of situations in a dynamically scheduled manner;
(c) a plurality of applications for operating on the plurality of mobile devices, each application being designed for a particular type of subscriber performing a prescribed task associated with the use of medical supplies in accordance with different templates and to download relevant parts of the data store to store locally on the devices;
(d) each application adapted to progress the subscriber through a range of functions prescribed for the subscriber, the range of functions involving receiving inputs for dynamically scheduling the creation or performance of a medical procedure or both the creation and performance of the medical procedure using some of the medical supplies in accordance with a particular template, wherein some or all of the medical supplies may be used or consumed in the medical procedure;
(e) at least one of the applications adapted to (i) track the use or consumption of the medical supplies in the procedure in real time, the use or consumption determined based on inputs received by one or more of the mobile devices from the subscribers, and (ii) receive a priority level associated with a category of product for stock ordering purposes, the at least one application adapted to update the external processing system and data store with status information relating to the medical supplies based on the real-time tracked use or consumption;
(f) the external processing system communicating with an inventory management system to supplement the master data with information concerning the availability and whereabouts of all medical supplies that may be specified in a template and tracked in the store;
(g) the external processing system communicating with a dynamic scheduling system to determine when a procedure defined by a particular template will occur; and
(h) the external processing system organising the fetching of medical supplies for delivery to the particular locality at a prescribed time for use or consuming in a scheduled medical procedure pursuant to communication with the dynamic scheduling system, the invoking of an application and inputs received by one or more of the mobile devices during progression of the subscribers through the specified range of functions therefor.

US Pat. No. 10,340,042

SYSTEM AND METHOD FOR CODING AND CHARGING OF CERTAIN MEDICAL PROCEDURES FOR A PATIENT USING A GRAPHICAL INTERFACE

MEDICAL ASSET MANAGEMENT,...

1. A computer implemented method for coding of a medical procedure for a vascular system of a patient, the method comprising:imaging on a graphical interface of a computer device a query box, wherein the query box displays a plurality of categories of vascular systems for identification of the category of vascular system on which the medical procedure will be performed;
receiving from a user through the graphical interface of the computer device an identification of the category of vascular system on which the medical procedure will be performed;
in response to the identification of the category of vascular system, generating and displaying on the graphical interface of the computer device a graphical representation of the identified vascular system;
generating and displaying on the graphical representation of the identified vascular system one or more access site options;
receiving from the user on the graphical representation of the identified vascular system and through the graphical interface of the computer device a selection from the one or more access site options of an access site location;
in response to the selection of the access site location, generating and displaying on the graphical interface of the computer device a graphical representation of one or more vessel orders for the identified vascular system;
receiving from the user on the graphical representation of the identified vascular system and through the graphical interface of the computer device a selection of one or more catheterization locations;
in response to the selection of the one or more catheterization locations, generating and displaying on the graphical interface of the computer device a graphical representation of the one or more catheterization locations for the identified vascular system,
wherein the one or more vessel orders and the one or more catheterization locations are generated by (i) determining an insertion site based on the selected access site location, (ii) calculating a path from the insertion site to each vessel to be catherized using a breadth first search, wherein the path contains one or more primary paths and one or more sub-paths, (iii) discarding any sub-path that is contained within a longer primary path, to produce a remaining catheterization location path, and (iv) determining the vessel order of the remaining catheterization location path based upon, when each vessel is treated as a node, the number of nodes away from the center of the graphical representation that the furthest node sits; and
generating one or more medical codes for the medical procedure using the one or more vessel orders and or one or more catheterization locations for the identified vascular system.

US Pat. No. 10,340,041

BIOPSY MAPPING TOOLS

Acupath Laboratories, Inc...

1. A computer-implemented method for anatomically plotting pathological diagnoses on a body part image, comprising executing on a processor the steps of:receiving an electronic communication containing an accession number;
in response to receiving the electronic communication, running a first query to retrieve, from a database, a plurality of biopsy marker records that include the accession number;
in response to receiving the plurality of biopsy marker records, running a second query to return a body part image ID included in the plurality of biopsy marker records;
retrieving a body part image associated with the body part image ID;
iterating through each of the plurality of biopsy marker records to identify an overlapping X,Y coordinate;
identifying a subset of biopsy marker records, each of the biopsy marker records included in the subset being associated with the overlapping X,Y coordinate;
iterating through the subset to identify a pathological diagnosis associated with each of the biopsy marker records included in the subset;
in response to identifying the diagnosis associated with the subset of biopsy marker records, querying an electronic record including a hierarchy of pathological diagnoses;
based on the hierarchy, identifying an optimized pathological diagnosis associated with each of the biopsy marker records included in the subset; and
generating a display on a graphical user interface, the display including at least a first symbol and a second symbol overlaid on the body part image, wherein:
the first symbol is associated with a first pathological diagnosis, the first pathological diagnosis being included in a biopsy marker record that is not part of the subset; and
the second symbol is associated with the optimized pathological diagnosis and is representative of the at least two biopsy marker records included in the sub set.

US Pat. No. 10,340,040

METHOD AND SYSTEM FOR IDENTIFYING DIAGNOSTIC AND THERAPEUTIC OPTIONS FOR MEDICAL CONDITIONS USING ELECTRONIC HEALTH RECORDS

BIOMED CONCEPTS INC., So...

1. A non-transitory computer-readable medium (CRM) comprising instructions that enable a system for identifying diagnostic options for medical conditions to:obtain, from a plurality of electronic health records of previously examined patients, a plurality of diagnostic action results and a plurality of diagnoses,
wherein the plurality of electronic health records is stored in an electronic health record database,
wherein the plurality of diagnostic action results, stored in the electronic health record database, comprises quantifications of the plurality of diagnostic action results;
generate, for the plurality of diagnoses, a plurality of statistical distributions of the plurality of diagnostic action results,
wherein at least one statistical distribution is generated for each of the plurality of diagnoses, and
wherein the at least one statistical distribution is specific to one of the plurality of diagnostic action results;
establish a plurality of pairs of diagnoses from the plurality of diagnoses;
obtain a plurality of overlaps from the plurality of statistical distributions by:
for each of the plurality of pairs of diagnoses, quantifying an overlap of two statistical distributions of the diagnostic action results associated with one of the plurality of pairs of diagnoses;
obtain a plurality of benefits of the plurality of diagnostic action results by:
for each of the plurality of pairs of diagnoses, obtaining, based on the overlap of two statistical distributions of the diagnostic action results associated with one of the plurality of pairs of diagnoses, a benefit of the plurality of benefits of the diagnostic action results for disambiguating the pair of diagnoses, wherein the benefit positively correlates with an inverse of the overlap;
storing the plurality of benefits of the diagnostic action results in a diagnoses statistics database; and
provide information to a user of the system regarding a patient to be diagnosed, using the plurality of benefits of the plurality of diagnostic action results stored in the diagnoses statistics database by:
obtaining an initial differential diagnosis for the patient to be diagnosed from an electronic health record of the patient to be diagnosed,
wherein the initial differential diagnosis comprises a group of the plurality of diagnoses, the group selected to have a higher associated probability of correctly identifying a condition of the patient to be diagnosed than non-selected diagnoses of the plurality of diagnoses, based on the electronic health record of the patient to be diagnosed;
selecting a subset of the plurality of diagnostic action results for which the benefit is larger than for non-selected diagnostic action results of the plurality of diagnostic action results, to disambiguate the group of the plurality of diagnoses in the initial differential diagnosis; and
providing a selection of diagnostic actions associated with the subset of the plurality of diagnostic action results to the user of the system.

US Pat. No. 10,340,039

MANAGING PATIENT DEVICES BASED ON SENSOR DATA

Hitachi, Ltd., Tokyo (JP...

1. A system comprising:one or more processors; and
one or more non-transitory computer-readable media maintaining executable instructions, which, when executed by the one or more processors, program the one or more processors to perform operations comprising:
receiving sensor data from patient devices, wherein individual patients of a plurality of patients each have a plurality of the patient devices associated therewith;
receiving caregiver records corresponding at least partially to the sensor data;
determining a vector from the caregiver records based on a selected subject;
determining a plurality of clusters from the sensor data;
determining, from the vector, a plurality of groups corresponding to the plurality of clusters;
based on the plurality of clusters and the plurality of groups, determining an indication of a discrepancy in care for a patient of the plurality of patients; and
sending at least one of:
a notification to a caregiver device;
a notification to a monitoring computing device; or
a control signal to control a patient device at a patient location associated with the patient indicated to have a discrepancy in care.

US Pat. No. 10,340,038

HEALTHCARE TRANSACTION VALIDATION VIA BLOCKCHAIN, SYSTEMS AND METHODS

Nant Holdings IP, LLC, C...

1. A computer program product comprising a non-transitory computer readable medium which comprises instructions, that when executed by one or more computer processors of one or more computers coupled to a network, to:receive health care transaction data corresponding to a plurality of health care transactions, the plurality of health care transactions including transactions corresponding to at least a first transaction participant and a second transaction participant associated with, respectively, a first historical healthcare blockchain and a second historical healthcare blockchain;
generate first validation data for a first not-previously-validated transaction of the first transaction participant;
generate second validation data for a second not-previously-validated transaction of the second transaction participant;
generate a first validity block comprising at least the first validation data, transaction data of the first not-previously-validated transaction, and a hash of at least a portion of a most recent block of the first historical blockchain;
generate a second validity block comprising at least the second validation data, transaction data of the second not-previously-validated transaction, and a hash of at least a portion of a most recent block of the second historical blockchain;
determine acceptance of the first and second validity blocks;
cause the first validity block to be appended to the historical blockchain of the first transaction participant after the first validity block has been accepted; and
cause the second validity block to be appended to the historical blockchain of the second transaction participant after the second validity block has been accepted.

US Pat. No. 10,340,037

AGGREGATING A PATIENT'S DISPARATE MEDICAL DATA FROM MULTIPLE SOURCES

Allscripts Software, LLC,...

1. A computer-implemented method for aggregating medical data from a plurality of sources, comprising:receiving medical data associated with a corresponding source into a central EHR system, the central EHR system including a medical records database storing a plurality of different types of patient medical data records, wherein each medical data record is associated with a corresponding time and a corresponding source, wherein each medical data record includes a reference to a master patient identifier, and wherein the master patient identifier is stored in a master patient data record separate from the plurality of different types of patient medical data records;
reconciling the received medical data with existing patient medical data records in the medical records database to identify a master patient to whom the received medical data relates, wherein the reconciling further comprises:
determining a list of potentially-relevant patient medical data records in the medical records database to compare with the received medical data;
iteratively performing the following steps for each data record in the list until a master patient is identified or until all data records have been visited:
determining a confidence score for the data record indicating the likelihood that the received medical data and the data record relate to the same master patient;
communicating the received medical data and the data record to a third party for verification when the confidence score for the data record is greater than or equal to a lower threshold and less than an upper threshold;
identifying the master patient to whom the data record relates as the master patient to whom the received medical data relates when a positive response is received from the third party; and
identifying the master patient to whom the data record relates as the master patient to whom the received medical data relates when the confidence score for the data record is greater than or equal to the upper threshold;
verifying that the source associated with the received medical data is authorized to add medical data related to the identified master patient;
writing a new patient medical data record to the medical records database, the new patient medical data record comprising the received medical data, a provider-specific patient identifier received from the source associated with the received medical data, and a reference to a master patient data record containing a master patient identifier corresponding to the identified master patient; and
creating, in the medical records database, a link between the provider-specific patient identifier and the master patient identifier corresponding to the identified master patient, wherein when additional medical data is received from the corresponding source, the additional medical data is correlated to the master patient identifier based upon the link.

US Pat. No. 10,340,036

DATA MANAGEMENT MECHANISM FOR WIDE-AREA DISTRIBUTED MEDICAL INFORMATION NETWORK

International Business Ma...

1. A method comprising:acquiring, by a second computer and from a third computer, address information of a plurality of first computers, wherein the address information of the plurality of first computers is associated with patient medical information for a particular patient;
storing, on the second computer, the address information of the plurality of first computers in an address list in the second computer;
transmitting, by the second computer, updated medical information from the second computer to the plurality of first computers, wherein the updated medical information is stored in a persistent storage device in the second computer;
receiving, by the second computer, receipt notifications from a portion of the plurality of first computers, wherein the receipt notifications acknowledge receipt of the updated medical information, and wherein only the portion of the plurality of first computers responded to the updated medical information from the second computer;
in response to the portion of the plurality of first computers being less than all of the plurality of first computers, sending, from the second computer, directions to one or more fourth computers to reiteratively send the updated medical information until all of the plurality of first computers that did not send receipt notifications to the second computer send receipt notifications of the updated medical information to the one or more fourth computers, wherein the first computers and the one or more fourth computers are at a same location, and wherein the second computer is in a location that is remote from the plurality of first computers and the one or more fourth computers;
receiving, by the second computer and from the one or more fourth computers, information from the one or more fourth computers indicating that all of the plurality of first computers that did not send receipt notifications to the second computer have sent receipt notifications to the one or more fourth computers indicating receipt of the updated medical information; and
in response to receiving the information from the one or more fourth computers indicating that all of the plurality of first computers have sent receipt notifications to the one or more fourth computers indicating receipt of the updated medical information, deleting the addresses of the plurality of first computers that did send receipt notifications to the one or more fourth computers from the address list on the second computer and deleting the updated medical information from the persistent storage device in the second computer.

US Pat. No. 10,340,035

MEDICAL RECORD STORAGE WITH ELECTRONIC SIGNATURE

Fenwal, Inc., Lake Zuric...

1. A system for storing an electronic medical record with an electronic signature in a database, comprising:an apheresis machine configured to perform an apheresis procedure on a patient, the apheresis machine configured to transmit an unsigned medical record; and
a server computer comprising:
a network interface circuit configured to provide communications over a network; and
a processing circuit configured to:
receive the unsigned medical record from the apheresis machine;
generate a user interface screen configured to receive an electronic signature for the unsigned medical record;
transmit the user interface screen to the apheresis machine over the network;
receive an electronic signature entered using the user interface screen; and
store the unsigned medical record and electronic signature in the database.

US Pat. No. 10,340,034

EVIDENCE-BASED HEALTHCARE INFORMATION MANAGEMENT PROTOCOLS

Elwha LLC, Bellevue, WA ...

1. A healthcare information management system comprising:at least one computing device in communication with at least one data storage device maintaining digital patient records; and
one or more instructions that, when implemented in the at least one computing device, program the at least one computing device for:
associating at least one personal mobile device with at least one patient;
detecting that the at least one personal mobile device associated with the at least one patient is local to at least one healthcare administration space;
recording the detection that the at least one personal mobile device associated with the at least one patient is local to the at least one healthcare administration space in the digital patient records;
detecting, at least partially from the digital patient records and at least partially from the recorded detection that the at least one personal mobile device associated with the at least one patient is local to the at least one healthcare administration space, a number of institutional admissions of a patient associated with a particular medical condition;
determining whether the number of institutional admissions associated with the particular medical condition are less than a pre-determined threshold number of admissions in relation to the particular condition;
assigning an incentive to the patient at least partly based on an indication that the patient has undergone less than the threshold number of institutional admissions in relation to the particular condition; and
transmitting at least one indication of the assigned incentive to at least one application running on the at least one personal mobile device associated with the at least one patient, responsive to the indication of the assigning of the incentive to the at least one patient including at least invoking circuitry configured for controlling operation of at least one device to cause the at least one device to dispense currency to the patient.

US Pat. No. 10,340,033

AUTONOMOUS LINKAGE OF PATIENT INFORMATION RECORDS STORED AT DIFFERENT ENTITIES

Koninklijke Philips N.V.,...

1. A system that links patient information records, of a same patient, that are stored at different facilities, comprising:a plurality of facilities, each facility including:
one or more patient databases comprising patient information records;
a facility specific patient identification algorithm, stored in computer memory, that matches patient information records, of the same patient, located at its facility of the plurality of facilities with the patient information records, of the same patient, located at other facilities of the plurality of facilities;
a linking subsystem, implemented via a microprocessor, that maintains a set of links between its facility and the other facilities of the plurality of facilities, and each link of the set of links represents a facility specific match and each link is stored in computer memory, wherein each link comprises an entity identifier;
wherein the linking subsystem of a first facility of the plurality of facilities links patient information records, of the same patient, located at the first facility with corresponding patient information records, of the same patient, located at a second facility of the plurality of facilities creating a first link of the set of links of the first facility in response to a first facility specific patient identification algorithm of the first facility matching the patient information record, of the same patient, located at the first facility with a corresponding patient information record, of the same patient, located at the second facility;
wherein the linking subsystem of the second facility of the plurality of facilities links patient information records, of the same patient, located at the second facility with corresponding patient information records, of the same patient, located at the first facility of the plurality of facilities creating a first link of the set of links of the second facility in response to a second facility specific patient identification algorithm of the second facility matching the patient information record, of the same patient, located at the second facility with the corresponding patient information record, of the same patient, located at the first facility,
wherein the first facility specific patient identification algorithm and the second facility specific patient identification algorithm are different,
wherein the first link of the first facility and the first link of the second facility are different links;
wherein at least the first facility locally stores a copy of at least a sub-set of the corresponding patient information records, of the same patient, located at the second facility of the plurality of facilities, and the facility specific patient identification algorithm of the first facility employs the locally stored copy to match the patient information records from the second facility; and
wherein the facility specific patient identification algorithm of the first facility matches the patient identification records between the patient information record of the same patient of the second facility and the patient record of the same patient of a third facility with at least one of a different threshold for acceptance and different weighted attributes.

US Pat. No. 10,340,032

RAPIDLY CONFIGURABLE DRUG DETECTION SYSTEM WITH ENHANCED CONFIDENTIALITY

1. A sample analysis system, said system comprising:a computerized device comprising a processor, camera, device software, memory, user interface, and a device network interface;
a test kit configured to accept a liquid sample from a sample collector, analyze said liquid sample for a plurality of analytes, and display a plurality of spatially separated optically detectable signals reporting on said plurality of analytes;
wherein said test kit comprises a lateral flow immunoassay comprising a plurality of lateral flow immunoassay tracks configured to generate at least one spatially separated optically detectable signal reporting on at least one of said plurality of analytes;
said test kit configured to display said spatially separated optically detectable signals in a manner that is obfuscated according to an obfuscation code;
said test kit further comprising a test ID code uniquely identifying said test kit;
a test reader stand configured to hold said computerized device and said test kit so that said camera can image said test kit when said test kit is present;
said device software configured to accept operator entered analysis parameters for a subset of said plurality of analytes, said device software configured to further accept test reporting information, test details, and at least some sample donor information;
said test reporting information comprising an electronic or physical address of at least one recipient (contact) for said test reporting information;
said device software further configured to use said camera to image said test kit, and obtain images of said spatially separated optically detectable signals;
said device software further configured to use said device network interface to transmit said operator entered analysis parameters for at least a subset of said plurality of analytes, said test reporting information, said test details, at least some said sample donor information, said test ID code, and images or data of said spatially separated optically detectable signals to a remote server; and
wherein said obfuscation code is stored on said remote server and is not transmitted to either said computerized device or said operator.

US Pat. No. 10,340,029

SYSTEMS AND METHODS FOR THE ANALYSIS OF PROTEIN MELT CURVE DATA

LIFE TECHNOLOGIES CORPORA...

1. A system comprising:a processor; and
a memory in communication with the processor, the memory storing instructions for:
receiving by the processor a set of initial protein melt curve data corresponding to an analysis group, wherein the analysis group comprises sample data from a plurality of sample support devices;
generating and displaying a plurality of melt curves obtained from a first set of processed protein melt curve data from the initial protein melt curve data;
displaying an analysis group window indicating the analysis group to which the initial protein melt curve data corresponds;
presenting a user interface for selecting a temperature range over which a region of the plurality of melt curves extend; and
in response to receiving input of a selected temperature range via the interface:
generating a second set of processed protein melt curve data, the second set of protein melt curve data comprising a fit of the first set of processed protein melt curve data over the selected temperature range, and
displaying the second set of protein melt curve data as a melt curve.

US Pat. No. 10,340,025

DATA-STORAGE DEVICE AND BLOCK-RELEASING METHOD

SILICON MOTION, INC., Jh...

1. A data-storage device, comprising:a flash memory, comprising a plurality of blocks, and each of the blocks comprises a plurality of pages, wherein the blocks comprise a plurality of bad blocks that are labeled as damaged; and
a controller, configured to select one of the bad blocks as a test block, and read the pages in the test block to determine whether the pages in the test block are damaged,
wherein when all the pages in the test block are undamaged, the controller labels the test block as a spare block,
wherein the controller selects as the test block one of the bad blocks that has been labeled damaged for the longest time.

US Pat. No. 10,340,024

SOLID STATE DRIVE PHYSICAL BLOCK REVECTORING TO IMPROVE CLUSTER FAILURE RATES

Intel Corporation, Santa...

1. A computing system comprising:a plurality of memory dies; and
a memory controller coupled to the plurality of memory dies, the memory controller including logic to:
identify an initial data band that spans the plurality of memory dies, wherein the initial data band is to include two or more block units that are to be located in separate memory dies of the plurality of memory dies, and
revector the plurality of memory dies to stagger the initial data band across a plurality of modified data bands, wherein a total number of modified data bands to be used for the revector is to equal a total number of block units in the initial data band.

US Pat. No. 10,340,023

METHOD AND SYSTEM FOR DETERMINING BIT VALUES IN NON-VOLATILE MEMORY

Storart Technology Co., L...

1. A method for determining bit values in a non-volatile memory having a plurality of cells each for storing a bit value, comprising the steps of:a) providing a first test sensing voltage to the cells and calculating a cell count of cells which have threshold voltages higher than the first test sensing voltage;
b) providing another test sensing voltage to the cells and calculating a difference of the cell counts between this step and previous step;
c) providing still another test sensing voltage higher than the highest test sensing voltage in previous steps to the cells if the difference of the cell counts in the previous step is positive, or lower than the lowest test sensing voltage in previous steps to the cells if the difference of the cell counts in the previous step is negative and calculating another difference of the cell counts between this step and previous step;
d) processing step c) for N times;
e) calculating differential amounts of cell counts for adjacent two test sensing voltages and assigning an index number to each group of cells having threshold voltages fallen in the same adjacent two test sensing voltages, higher than the highest test sensing voltage or below the lowest test sensing voltage;
f) choosing a voltage between the adjacent two test sensing voltages which cause the least differential amount in step e) as an updated sensing voltage; and
g) determining bit values of cells as logic 1 with the corresponding index number when the threshold voltages of the cells are lower than the updated sensing voltage or as logic 0 with corresponding index number when the threshold voltages of the cells are higher than the updated sensing voltage.

US Pat. No. 10,340,022

NONVOLATILE MEMORY INCLUDING ON-DIE-TERMINATION CIRCUIT AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY

SAMSUNG ELECTRONICS CO., ...

1. A nonvolatile memory (NVM) device comprising:a data pin;
a control pin;
an on-die termination (ODT) pin; and
a plurality of NVM chips commonly connected to the data pin, the control pin and the ODT pin,
wherein a first NVM chip among the NVM chips comprises an ODT circuit,
wherein the first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode,
wherein the control signal indicates whether one of a read operation and a write operation is to be performed, and
wherein the plurality of NVM chips commonly receives the ODT signal.

US Pat. No. 10,340,021

PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
wherein polarities of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are the same,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is directly connected to the one of the source and the drain of the third transistor,
wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the second transistor,
wherein the other of the source and the drain of the second transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the fourth transistor is directly connected to the first wiring,
wherein a gate of the fifth transistor is directly connected to a second wiring,
wherein the other of the source and the drain of the sixth transistor is directly connected to the second wiring,
wherein a ratio W/L of a channel width W to a channel length L of the third transistor is almost equal to a ratio W/L of a channel width W to a channel length L of the fifth transistor,
wherein a first clock signal is input to the other of the source and the drain of the first transistor,
wherein a second clock signal is input to a gate of the sixth transistor, and
wherein a ratio W/L of a channel width W to a channel length L of the first transistor is larger than a ratio W/L of a channel width W to a channel length L of the fourth transistor.

US Pat. No. 10,340,020

FUSE ELEMENT PROGRAMMING CIRCUIT AND METHOD

SEMICONDUCTOR COMPONENTS ...

1. A circuit for programming a fuse element comprising:a memory cell having the fuse element that includes a first semiconductor material body region and a silicide layer;
a programming circuit configured to form a programming current to program the fuse element;
a programming element configured to conduct a control current and to control a value of the programming current, the programming element having a second semiconductor material body region but not a silicide layer;
a current mirror, of the programming circuit, having a first transistor coupled at a node to a second transistor of the current mirror, the first transistor configured to conduct the control current, the second transistor configured to conduct the programming current;
a reference generation circuit configured to conduct the control current, the reference generation circuit coupled in series between the node and the programming element;
the programming circuit configured to control the programming current to a first value responsively to a resistance value of the programming element and to subsequently control the programming current to a different value responsively to a resistance value of the fuse element.

US Pat. No. 10,340,019

SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED PROGRAM VERIFICATION RELIABILITY

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a memory cell array including a first string group and a second string group, wherein the first string group and the second string group each includes memory cell strings, and
wherein each of the memory cell strings includes at least one selection transistor cell;
a peripheral circuit configured to perform a program operation comprising a program voltage application operation on both the first string group and the second string group, and to perform a half page program verification operation; and
a control logic configured to control the peripheral circuit to determine pass or fail of the program operation according to a result of the half page program verification operation,
wherein the control logic controls the peripheral circuit to select one of the first string group and the second string group for the half page program verification operation based on whether an application number of a program voltage applied to both the first string group and the second string group is even or odd.

US Pat. No. 10,340,018

MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A memory device, comprising:a plurality of memory cells connected to a word line, each of the plurality of memory cells being programmed to one of a plurality of program states;
a peripheral circuit configured to perform a program operation to the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation; and
a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells,
wherein the control logic controls the peripheral circuit to apply the bit line voltages determined based on a difference between a voltage applied to the word line and threshold voltages corresponding to target program states of the plurality of memory cells.

US Pat. No. 10,340,017

ERASE-VERIFY METHOD FOR THREE-DIMENSIONAL MEMORIES AND MEMORY SYSTEM

MACRONIX INTERNATIONAL CO...

1. An erase-verify method for a three-dimensional (3D) memory, the 3D memory including at least one memory cell string including a plurality of memory cells, the memory cells including a first group of memory cells and a second group of memory cells, each of the memory cells coupled to a word line, the erase-verify method comprising:performing a first erase-verify operation on the first group of memory cells, wherein the first erase-verify operation comprises:
applying an erase-verify voltage to the word lines coupled to a first portion of the first group of memory cells and a first pass voltage to the word lines coupled to a second portion of the first group of memory cells in a first phase of the first erase-verify operation, the second portion of the first group of memory cells is different from the first portion of the first group of memory cells; and
after the first phase of the first erase-verify operation, applying the erase-verify voltage to the word lines coupled to the memory cells in the second portion of the first group of memory cells and the first pass voltage to the word lines coupled to the memory cells in the first portion of the first group of memory cells in a second phase of the first erase-verify operation; and
after performing the first erase-verify operation on the first group of memory cells, performing a second erase-verify operation on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully, wherein the second erase-verify operation comprises:
applying the erase-verify voltage to the word lines coupled to a first portion of the second group of memory cells and a second pass voltage to the word lines coupled to a second portion of the second group of memory cells in a first phase of the second erase-verify operation, the second portion of the second group of memory cells is different from the first portion of the second group of memory cells; and
after the first phase of the first erase-verify operation, applying the verify voltage to the word lines coupled to the second portion of the second group of memory cells and the second pass voltage to the word lines coupled to the first portion of the second group of memory cells in a second phase of the second erase-verify operation.

US Pat. No. 10,340,016

METHODS OF ERROR-BASED READ DISTURB MITIGATION AND MEMORY DEVICES UTILIZING THE SAME

Micron Technology, Inc., ...

1. A memory device, comprising:a main memory comprising a plurality of memory addresses, each memory address corresponding to a single one of a plurality of word lines and being included in a tracked subset of the plurality of memory addresses, each tracked subset including memory addresses corresponding to more than one of the plurality of word lines; and
a controller operably connected to the main memory and configured to:
track, for each tracked subset, a number of read operations,
scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value corresponding to the first tracked subset, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset, and
update the first threshold value by an amount corresponding to the determined error count.

US Pat. No. 10,340,015

APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY

Micron Technology, Inc., ...

1. An apparatus comprising:a memory array including signal lines; and
a control logic circuit configured to charge at least one signal line of the memory array responsive to a pre-access command, the control logic circuit configured, responsive to the pre-access command, to control a voltage of the at least one signal line based partly on a temperature of the apparatus.

US Pat. No. 10,340,014

MONITORING ERROR CORRECTION OPERATIONS PERFORMED IN MEMORY

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory; and
circuitry configured to:
determine a bit error rate associated with an error correction operation performed on sensed data states of a number of memory cells of the memory and soft data associated with the sensed data states;
determine a high reliability error rate associated with the error correction operation; and
determine whether to take a corrective action on the sensed data states by:
plotting a data point corresponding to the bit error rate and the high reliability error rate in a two-dimensional bit error rate versus high reliability error rate space, wherein the two-dimensional bit error rate versus high reliability error rate space includes a curve corresponding to a correction limit of the error correction operation; and
determining a location of the data point relative to the curve in the two-dimensional bit error rate versus high reliability error rate space.

US Pat. No. 10,340,013

MEMORY DEVICE

Toshiba Memory Corporatio...

1. A memory device comprising:a semiconductor column extending above a substrate;
a first conductive layer on a first side of the semiconductor column;
a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer;
a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column;
a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer;
a fifth conductive layer adjacent the first conductive layer on the first side of the semiconductor column and between the first and third conductive layers;
a sixth conductive layer on the second side of the semiconductor column, opposite to the fifth conductive layer; and
a bit line connected to the semiconductor column, wherein during reading in which a positive voltage is applied to the bit line:
a first voltage is applied to the first conductive layer and a second voltage is applied to the second conductive layer;
a third voltage is applied to the third conductive layer and a fourth voltage is applied to the fourth conductive layer;
a fifth voltage is applied to the fifth conductive layer and a sixth voltage is applied to the sixth conductive layer;
the first voltage and the third voltage are higher than each of the second voltage and the sixth voltage;
the fifth voltage is higher than the first, second, third, fourth and sixth voltages; and
the third voltage is higher than the first voltage.

US Pat. No. 10,340,012

CONTROL LOGIC, SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF OPERATING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor memory device comprising:a memory cell array including a plurality of cell strings;
a read and write (read/write) circuit configured to perform a read operation or a program operation on the memory cell array; and
a control logic configured to control the read/write circuit to perform the read operation or the program operation on the memory cell array,
wherein each of the plurality of cell strings includes a plurality of memory cells coupled with corresponding word lines,
wherein, during the program operation, the control logic is configured to determine, based on a position of a selected memory cell in the cell string, a program step voltage to be applied to a selected word line coupled to the selected memory cell, and is configured to determine a pass voltage to be applied to an unselected word line based on the program step voltage, and
wherein the program step voltage has a higher value than 0V.

US Pat. No. 10,340,011

THREE-DIMENSIONAL ADDRESSING FOR ERASABLE PROGRAMMABLE READ ONLY MEMORY

1. A device for use with a print head, comprising:a plurality of memory arrays of storage units storing data for the print head; and
a plurality of flip-flop circuits connected to the plurality of memory arrays,
wherein the plurality of flip-flop circuits is to receive data signals and generate a three-dimensional address of one of the storage units in the plurality of memory arrays, the three-dimensional address comprising:
a first select signal to identify a first portion of the three-dimensional address of the storage unit in the plurality of memory arrays,
a second select signal to identify a second portion of the three-dimensional address of the storage unit in the plurality of memory arrays, and
a third select signal, generated by one of the plurality of flip-flop circuits, to identify a third portion of the three-dimensional address of the storage unit in the plurality of memory arrays.

US Pat. No. 10,340,010

METHOD AND APPARATUS FOR CONFIGURING ARRAY COLUMNS AND ROWS FOR ACCESSING FLASH MEMORY CELLS

SILICON STORAGE TECHNOLOG...

1. A non-volatile memory device comprising:an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells;
a first column decoder selectively coupled to a first sector configured to operate in dual-column mode; and
a second column decoder selectively coupled to a second sector configured to operate in single-column mode;
wherein during a read or programming operation in the first sector, the first column decoder selects two immediately adjacent columns enabling reading or programming of two immediately adjacent flash memory cells and during a read or programming operation in the second sector, the second column decoder selects no more than one column enabling reading or programming of one flash memory cell.

US Pat. No. 10,340,009

METHODS AND APPARATUSES INCLUDING A STRING OF MEMORY CELLS HAVING A FIRST SELECT TRANSISTOR COUPLED TO A SECOND SELECT TRANSISTOR

Micron Technology, Inc., ...

1. An apparatus comprising:a memory cell string, comprising,
multiple memory cells, each memory cell including a control gate transistor,
a select gate drain transistor between the multiple memory cells and a bit line, the select gate transistor having a gate;
a first select gate source transistor on the opposite side of the multiple memory cells from the select gate drain transistor, and between the multiple memory cells and a source, the first select gate source transistor having a gate;
a second select gate source transistor coupled in series with the first select gate source transistor, and between the first select gate source transistor and the source, the second select gate source transistor having a gate; and
a first drive transistor coupled to both,
the gate of the select gate drain transistor; and
the gate of either the first select gate source transistor or the gate of the second select gate source transistor; and
wherein the first or second select gate source transistor that is coupled to the first drive transistor has a shorter channel length than that of the other select gate source transistor.

US Pat. No. 10,340,008

ELECTRONIC DEVICE AND DISCHARGE METHOD

TOSHIBA MEMORY CORPORATIO...

1. An electronic device, comprising:a first switch circuit between a power supply line and a ground potential, the first switch circuit being configured to electrically connect the power supply line to the ground potential upon receipt of a first control signal that is supplied when a supply of power on the power supply line is cut off;
a capacitor connected between the power supply line and the ground potential;
a second switch circuit between the capacitor and the power supply line, the second switch circuit being configured to disconnect the capacitor from the power supply line upon receipt of the first control signal; and
a controller circuit configured to output the first control signal when the supply of power on the power supply line is cut off.

US Pat. No. 10,340,007

RESISTIVE CONTENT ADDRESSABLE MEMORY BASED IN-MEMORY COMPUTATION ARCHITECTURE

KING ABDULLAH UNIVERSITY ...

1. An associative processor system, comprising:a content addressable memory (CAM) including an array of cells, where individual cells of the array of cells comprise a memristor based crossbar;
an instruction cache configured to hold instructions to be performed by the CAM;
a controller;
a key register controlled by the controller, the controller being configured to generate key values and store the key values in the key register;
a mask register controlled by the controller, the controller being configured to generate mask values and store the mask values in the mask register;
the CAM configured to mark tag bits in a tag field for rows of the CAM that are compared and matched based on the key and mask values; and
an interconnection switch matrix circuit coupled to an output of the CAM, the interconnection switch matrix circuit comprising a gateless memristor array,
wherein the interconnection switch matrix circuit is configured to allow rows of the CAM to communicate in parallel.

US Pat. No. 10,340,006

SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY INCLUDING RESISTANCE CHANGE MATERIAL AND METHOD OF OPERATING

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;
wherein said buried layer region is commonly connected to at least two of said memory cells; and
a control circuit configured to perform said transfer operation.

US Pat. No. 10,340,005

RESISTIVE CHANGE ELEMENT ARRAYS WITH IN SITU INITIALIZATION

Nantero, Inc., Woburn, M...

1. A resistive change element memory array, comprising:a plurality of word lines;
a plurality of bit lines;
a plurality of select lines;
a plurality of initialization driver circuits;
a plurality of memory cells, said memory cells comprising:
a resistive change element having a first terminal and a second terminal, said first terminal in electrical communication with a select line and an initialization driver circuit, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first resistive state and a second resistance value corresponding to a second resistive state;
a selection device responsive to a control signal on a word line, said selection device selectively providing a conductive path between a bit line and said second terminal of said resistive change element;
wherein said plurality of initialization driver circuits are capable of applying initialization stimuli to said resistive change elements within said plurality of memory cells;
wherein said initialization stimuli enables operation of said plurality of memory cells within at least two informational states.

US Pat. No. 10,340,004

WRITE VOLTAGE GENERATING CIRCUIT COMPRISING A CURRENT MIRROR

Taiwan Semiconductor Manu...

1. A device for writing to a memory, comprising:a current mirror circuit configured to generate a mirror current that mirrors a write current flowing to the memory, the current mirror circuit including:
a first transistor having a gate terminal and a source/drain terminal coupled to each other via a coupling point and the gate terminal directly couples to a memory cell of the memory via the coupling point, and
a second transistor having (i) a gate terminal coupled to the gate terminal of the first transistor and (ii) a source/drain coupled to a current source circuit via a node;
a voltage-generating circuit selectively coupled to the current mirror circuit and configured to apply, through the current mirror circuit, a write voltage to the memory; and
a switch circuit configured to control coupling of the voltage-generating circuit to the current mirror circuit based on a voltage at the node;
wherein the current source circuit includes a constant current source configured to draw a compliance current from the node.

US Pat. No. 10,340,003

INPUT-PATTERN AWARE REFERENCE GENERATION SYSTEM AND COMPUTING-IN-MEMORY SYSTEM INCLUDING THE SAME

National Tsing Hua Univer...

1. An input-pattern aware reference generation system for a memory cell array having a plurality of word lines crossing a plurality of bit lines, the plurality of word lines being selectively activated by an input signal such that each of the plurality of bit lines generates a computational result of multiply-and-accumulate (MAC) computation, the system comprising:an input counting circuit, receiving the input signal of the memory cell array, discovering input activated word lines according to the input signal and generating a number signal representing a number of the input activated word lines;
a reference array, comprising a plurality of reference memory cells storing a predetermined set of weights; and
a reference word line control circuit, electrically connected between the input counting circuit and the reference array, the reference word line control circuit controlling the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array according to the number signal.

US Pat. No. 10,340,002

IN-CELL DIFFERENTIAL READ-OUT CIRCUITRY FOR READING SIGNED WEIGHT VALUES IN RESISTIVE PROCESSING UNIT ARCHITECTURE

International Business Ma...

1. A resistive processing unit (RPU) device, comprising:a weight storage device configured to store a weight voltage which corresponds to a weight value of the RPU device;
a read transistor comprising a gate terminal, a first source/drain terminal, and a second source/drain terminal, wherein the gate terminal is connected to the weight storage device, wherein the first source/drain terminal is connected to a first control port of the RPU device, and wherein the second source/drain terminal is connected to a second control port of the RPU device; and
a current source connected to the second source/drain terminal of the read transistor, wherein the current source is configured to generate a fixed reference current;
wherein the read transistor is configured to generate a weight current in response to the weight voltage applied to the gate terminal of the read transistor;
wherein the RPU device is configured to output a read current from the second control port, wherein the read current comprises a magnitude and sign which represents a signed weight value of the RPU device;
wherein the magnitude of the read current is equal to a difference between the weight current generated by the read transistor and the fixed reference current of the current source;
wherein the sign of the read current is deemed positive when the weight current is greater than the fixed reference current; and
wherein the sign of the read current is deemed negative when the weight current is less than the fixed reference current.

US Pat. No. 10,340,001

SINGLE-READOUT HIGH-DENSITY MEMRISTOR CROSSBAR

KING ABDULLAH UNIVERSITY ...

1. A method for reading a target memory cell located at an intersection of a target row of a high-density gateless array and a target column of the high-density gateless array, the method comprising:reading a value of the target memory cell;
calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by a sneak path current; and
calculating the component of the read value caused by the sneak path current prior to calculating the actual value of the target memory cell,
wherein calculating the component of the read value caused by the sneak path current includes:
estimating a value of an initial memory cell,
reading a value of the initial memory cell, and
calculating the component of the read value caused by the sneak path current based on the estimated value of the initial memory cell and the read value of the initial memory cell.

US Pat. No. 10,340,000

OPERATING METHOD OF MEMORY DEVICE

Samsung Electronics Co., ...

1. An operating method of a memory device, comprising:determining a resistance Rdyn of a variable resistor of a memory cell and a variation ?Rdyn of the resistance Rdyn based on a statistical model;
determining an average resistance Rdyn_avg and a beta value of the variable resistor using the resistance Rdyn and the variation ?Rdyn of the resistance Rdyn;
determining a resistance Ra of an insertion resistor, connected in series between the memory cell and a power supply generator for generating a power supply voltage VPGM, using the average resistance Rdyn_avg and the beta value;
determining, using the resistance Ra, a level of the power supply voltage VPGM according to a target amount of heat generated in the memory cell; and
providing the level of the power supply voltage VPGM to the memory cell by using the power supply generator.

US Pat. No. 10,339,999

VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTION

Rambus Inc., Sunnyvale, ...

1. A memory module with an anterior module side and a posterior module side, the memory module comprising:a first memory component on the anterior module side;
a second memory component on the posterior module side;
a data-buffer component having:
a primary data link of a first data width;
a first secondary data link, of a second data width, coupled to the first memory component; and
a second secondary data link, of the second data width, coupled to the second memory component;
the data-buffer component to time-division multiplex data from the first memory component on the first secondary data link and the second memory component on the second secondary data link onto the primary data link.

US Pat. No. 10,339,998

APPARATUSES AND METHODS FOR PROVIDING CLOCK SIGNALS IN A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a clock generating circuit configured to:
generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted relative to each other; and
generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode;
first, second, third and fourth buses on which the first, second, third and fourth clock signals are driven in the first mode; and
fifth and sixth buses on which the fifth and sixth clock signals are driven in the second mode, wherein each of the fifth and sixth buses is electrically decoupled from each of the first, second, third and fourth buses.

US Pat. No. 10,339,997

MULTI-PHASE CLOCK DIVISION

Micron Technology, Inc., ...

1. A semiconductor device comprising:memory;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises:
count detection circuitry configured to count bits received for a phase of the plurality of phases; and
phase detection circuitry configured to identify which phase of the plurality of phases received a pulse of the data strobe first.

US Pat. No. 10,339,996

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines;
a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks; and
a control logic configured to control the peripheral circuit, during the erase operation, to apply an erase permission voltage to the dummy word lines and the normal word lines for a preset time and to apply an erase prohibition voltage to the dummy word lines after the preset time,
wherein the preset time is determined based on Erase-Write (EW) cycling information and is determined regardless of a time for the erase operation, and
wherein the EW cycling information indicates a number of erase-write cycles of the selected memory block.

US Pat. No. 10,339,995

MEMORY DEVICE FOR CONTROLLING REFRESHING OPERATION

Samsung Electronics Co., ...

1. A memory device comprising:a plurality of memory cells; and
a self refresh controller configured to perform a refreshing cycle a plurality of times, the refreshing cycle including,
a burst refreshing operation performed during a first time interval, and
a power supply controlling operation performed during a second time interval, the second time interval being longer than the first time interval,
wherein the self refresh controller is configured to increase the second time interval in response to a deep sleep signal.

US Pat. No. 10,339,994

SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a row decoder configured to receive a refresh address and to selectively perform a row-copy operation, wherein during the row-copy operation data in a first word line corresponding to the refresh address is copied to a second word line in a same section of a memory as the first address, wherein the row decoder comprises a row-copy control circuit configured select a type of row-copy operation and to provide a source address corresponding to the first word line and a destination address corresponding to the second word line based on the type of row-copy operation, and wherein the row-cop control circuit is further configured to mark the region of the second word line where the data was copied as unusable for subsequent row-copy operations.

US Pat. No. 10,339,993

PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICE WITH SKYRMIONIC ASSIST LAYERS FOR FREE LAYER SWITCHING

Spin Memory, Inc., Fremo...

1. A magnetic device, comprising:a first synthetic antiferromagnetic structure in a first plane having a magnetization vector that is perpendicular to the first plane and having a fixed magnetization direction;
an antiferromagnetic coupling layer in a second plane and disposed above the first synthetic antiferromagnetic structure;
a second synthetic antiferromagnetic structure in a third plane and disposed over the antiferromagnetic coupling layer;
a magnetic reference layer in a fourth plane and disposed over the second synthetic antiferromagnetic structure, the magnetic reference layer having a magnetization vector that is perpendicular to the fourth plane and having a fixed magnetization direction;
a non-magnetic tunnel barrier layer in a fifth plane and disposed over the magnetic reference layer;
a free magnetic layer disposed in a sixth plane over the non-magnetic tunnel barrier layer, the free magnetic layer having a magnetization vector that is perpendicular to the sixth plane and having a magnetization direction that can switch between a first magnetization direction to a second magnetization direction, the magnetic reference layer, the non-magnetic tunnel barrier layer and the free magnetic layer forming a magnetic tunnel junction; and
a skyrmionic enhancement layer disposed in a seventh plane over the free magnetic layer and being formed from a heavy metal with large spin-orbit coupling such that the skyrmionic enhancement layer induces a Dzyaloshinskii-Moriya interaction at an interface between the free magnetic layer and the skyrmionic enhancement layer thereby creating a non-collinear magnetic texture in the free magnetic layer near the interface.

US Pat. No. 10,339,992

SEMICONDUCTOR SYSTEM

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:a controller configured to provide a command clock, a data clock, an external command and an external address to a semiconductor memory device; and
the semiconductor memory device configured to transmit/receive external data to/from the controller and provide a read data strobe signal to the controller,
wherein the read data strobe signal comprises a first read data strobe signal and a second read data strobe signal, and
the semiconductor memory device transmits both of the first and second read data strobe signals to the controller or transmits one of the first and second read data strobe signals to the controller, based on an operation select signal.

US Pat. No. 10,339,991

MEMORY SYSTEM HAVING OPTIMAL THRESHOLD VOLTAGE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory system comprising:a memory device; and
a memory controller including a sequence generator, a sequence analyzer, and a processor, the memory controller being coupled to the memory device and containing instructions for execution by the processor to
generate a training sequence, using the sequence generator, for analysis of user data, wherein the training sequence comprises a sequence of digital data that is randomly generated, has a length indicative of a level of accuracy of analysis and is known to the memory system,
write the training sequence with the associated user data to the memory device,
read out the training sequence and the associated user data,
analyze the training sequence, using the sequence analyzer, to understand characters of the user data and create an analysis result,
identify an optimal threshold voltage in accordance with the analysis result, and
use the optimal threshold voltage in an error correction coding process.

US Pat. No. 10,339,990

STROBE ACQUISITION AND TRACKING

RAMBUS INC., Sunnyvale, ...

1. A memory controller, comprising:an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal;
a comparison circuit to determine a current timing offset between the data strobe signal and an internally generated data strobe enable signal, internally generated by the memory controller;
data receive circuitry, including gate logic to gate the data strobe signal with the internally generated data strobe signal to generate a clean data strobe signal, and data capture logic responsive to the clean data strobe signal to capture the read data; and
a circuit to dynamically determine a mode of operation of the memory controller in accordance with the determined current timing offset, wherein the mode of operation is selected from among a set of modes of operation that include a first mode of operation in which the memory controller synchronizes the internally generated data strobe enable signal with the received read data and data strobe signal, and a second mode of operation in which the memory controller maintains synchronization between the internally generated data strobe enable signal and the received read data and data strobe signal.

US Pat. No. 10,339,989

PAGE BUFFER, A MEMORY DEVICE INCLUDING THE SAME AND A READ OPERATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A page buffer, comprising:a pre-charge unit for pre-charging a bit line of a selected memory cell of a memory cell array via a first pre-charge line and pre-charging a sensing node via a second pre-charge line, wherein the bit line of the selected memory cell and the sensing node are pre-charged during a pre-charge time;
a bit line connection unit connected between the bit line and the sensing node and comprising a connecting node directly connected to the first pre-charge line, wherein the bit line connection unit controls a voltage of the sensing node, during a develop time, based on a bit line connection control signal and a sensing node voltage control signal, wherein the bit line connection unit includes a pair of transistors connected in series between the bit line and the sensing node, and wherein the connecting node is disposed between the pair of transistors; and
a data input and output unit for generating sensing data by sensing a level of the voltage of the sensing node, during a sensing time,
wherein the pre-charge unit comprises:
a bit line pre-charge transistor comprising a first terminal, a second terminal, and a gate terminal, wherein the first terminal receives a pre-charge voltage, the second terminal is connected to the connecting node, and the gate terminal receives a bit line pre-charge control signal; and
a sensing node pre-charge transistor comprising a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second terminal of the bit line pre-charge transistor, the second terminal is connected to the sensing node, and the gate terminal receives a sensing node pre-charge control signal,
wherein the pre-charge unit controls a start time at which the bit line is pre-charged and a start time at which the sensing node is pre-charged to be different from each other, based on the bit line pre-charge control signal and the sensing node pre-charge control signal.

US Pat. No. 10,339,988

INPUT BUFFER CIRCUIT

Micron Technology, Inc., ...

1. An apparatus comprising:a first amplifier configured to be activated by a first power supply voltage to provide a first intermediate voltage on a first node and a second intermediate voltage on a second node;
a voltage switch configured to be activated by one of first and second precharge voltages from a third node; the voltage switch coupled to a fourth node; and
a second amplifier comprising first and second inverters coupled to the fourth node, the second amplifier configured to be activated by a second power supply voltage from the voltage switch to provide an output voltage when the voltage switch is activated, responsive to the one of the first and second precharge voltages,
wherein the first amplifier is configured to receive a data input signal and a reference voltage.

US Pat. No. 10,339,987

METHOD AND DEVICE FOR ADJUSTING HARDWARE REFRESH RATE OF TERMINAL

ZTE CORPORATION, Guangdo...

1. A method for adjusting a hardware refresh rate of a terminal, comprising:predicting a frame rate of currently operating software of the terminal in a future preset time period; and
adjusting the hardware refresh frequency of the terminal according to the predicted frame rate,
wherein the step of predicting the frame rate of the currently operating software of the terminal in the future preset time period comprises:
collecting at least one information of a real-time frame rate of the software, related information of a software graphic processing unit in the terminal and historical frame rate information of the software when operating in a foreground, the related information of the software graphic processing unit comprising: frequency information and load information of the software graphic processing unit; and
predicting the frame rate of the currently operating software of the terminal in the future preset time period according to at least one information of the real-time frame rate of the software, the related information of the software graphic processing unit and the historical frame rate information,
wherein;
the collecting at least one information of the real-time frame rate of the software, the related information of the software graphic processing unit in the terminal and the historical frame rate information of the software when operating in the foreground comprises:
collecting the related information of the software graphic processing unit in the terminal; and
the predicting the frame rate of the currently operating software of the terminal in the future preset time period according to at least one information of the real-time frame rate of the software, the related information of the software graphic processing unit and the historical frame rate information comprises:
judging a current frame rate scene of the software according to the frequency information and the load information; and
predicting the frame rate of the software in the future preset time period according to a judgment result.

US Pat. No. 10,339,986

DATA LATCH CIRCUIT AND PULSE SIGNAL GENERATOR THEREOF

DigWise Technology Corpor...

1. A pulse signal generator, comprising:a first buffer, receiving an input signal and a feedback signal, and generating a first buffering signal according to the input signal and the feedback signal;
a second buffer, receiving the input signal and the first buffering signal, and generating a second buffering signal according to the input signal and the first buffering signal;
a pull-up switch, coupled to an output end of the second buffer, receiving the first buffering signal, and pulling up the second buffering signal according to the first buffering signal; and
an output buffer, coupled to the first buffer and the second buffer, generating at least one output pulse signal according to the second buffering signal, the output buffer transmitting the at least one output pulse signal to the first buffer to be the feedback signal.

US Pat. No. 10,339,985

SENSE AMPLIFIER CONSTRUCTIONS

Micron Technology, Inc., ...

1. A sense amplifier construction comprising:a first n-type transistor and a second n-type transistor vertically offset above the first n-type transistor;
a third p-type transistor and a fourth p-type transistor vertically offset above the third p-type transistor;
a lower voltage activation line electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors; and
a higher voltage activation line electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

US Pat. No. 10,339,984

DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS

Micron Technology, Inc., ...

1. An apparatus comprising:a first output circuit;
a second output circuit; and
a calibration circuit coupled in parallel to the first output circuit and the second output circuit, the calibration circuit configured to perform a first calibration operation responsive to a first calibration command to produce a first calibration code, supply the first calibration code to the first output circuit responsive to a first latch command and supply the first calibration code to the second output circuit responsive to a second latch command.

US Pat. No. 10,339,983

TEMPERATURE-BASED MEMORY OPERATIONS

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device; and
a controller coupled to the memory device and configured to:
determine an operating temperature of the apparatus;
determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus, wherein the plurality of designated open blocks includes:
a first block corresponding to a first operating temperature range below a first temperature threshold;
a second block corresponding to a second operating temperature range above a second temperature threshold;
a third block corresponding to a third operating temperature range above the first temperature threshold and below the second temperature threshold; and
a fourth block corresponding to the third operating temperature range; and
write the data in the determined one of the plurality of designated blocks of the memory device.

US Pat. No. 10,339,982

MEMORY ELEMENTS AND CROSS POINT SWITCHES AND ARRAYS OF SAME USING NONVOLATILE NANOTUBE BLOCKS

Nantero, Inc., Woburn, M...

1. A circuit for routing electrical signals, said circuit comprising:a first plurality of wires;
a second plurality of wires; and
a plurality of nonvolatile nanotube block switches, wherein each nonvolatile nanotube block switch is in electrical communication with at least one wire of said first plurality of wires and at least one wire of said second plurality of wires, wherein each nonvolatile nanotube block switch is programmable to an on state and an off state, and wherein each nonvolatile nanotube block switch is dimensioned such that said on state has a resistance value suitable for electric signal flow between at least one wire of said first plurality of wires and at least one wire of said second plurality of wires.

US Pat. No. 10,339,981

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a first nonvolatile semiconductor element;
a second nonvolatile semiconductor element;
a resistive element;
a controller that controls the first nonvolatile semiconductor element and the second nonvolatile semiconductor element;
a first signal line that connects the controller to the resistive element;
a second signal line that connects the resistive element to the first nonvolatile semiconductor element;
a third signal line that branches from the second signal line, the third signal line being connected to the second nonvolatile semiconductor element, at least one of the second signal line and the third signal line including a signal line formed on a first wiring layer and a signal line formed on a second wiring layer;
a connector that allows connection to an external device; and
a substrate on which the first nonvolatile semiconductor element, the second nonvolatile semiconductor element, the resistive element, the controller, and the connector are mounted, the first nonvolatile semiconductor element and the second nonvolatile semiconductor element being disposed symmetrically on opposite sides of the substrate, the substrate including:
a front surface layer that includes a wiring pattern formed on a front surface of the substrate, the front surface layer being a layer on which the first nonvolatile semiconductor element and the resistive element are mounted,
a rear surface layer that includes a wiring pattern formed on a rear surface of the substrate, the rear surface layer being a layer on which the second nonvolatile semiconductor element is mounted, and
a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers including a wiring pattern, the first wiring layer being one of the plurality of internal wiring layers, the second wiring layer being one of the plurality of internal wiring layers, the second wiring layer being a different wiring layer from the first wiring layer.

US Pat. No. 10,339,980

APPARATUSES AND METHODS FOR CONTROLLING WORDLINES AND SENSE AMPLIFIERS

Micron Technology, Inc., ...

1. A memory array comprising:a column decoder circuit configured to provide bit line selections for the memory array;
a plurality of column selection lines coupled to the column decoder circuit; and
a plurality of bleeder transistors, each bleeder transistor configured to be coupled to a respective column selection line of the plurality of column selection lines,
wherein each bleeder transistor of the plurality of bleeder transistors further comprises:
a gate configured to receive a first voltage; and
a drain configured to receive a second voltage;
wherein the drain of each bleeder transistor is located along a word line direction of the memory array.

US Pat. No. 10,339,979

SECURE PROTECTION BLOCK AND FUNCTION BLOCK SYSTEM AND METHOD

Intel Corporation, Santa...

1. An apparatus comprising:power supply pins to couple to a power supply; and
a protection block, including a first transistor, to: (a) determine whether voltage from at least one of the power supply pins meets a predetermined condition, and (b) in response to determining whether the predetermined condition is met, communicate a first communication to at least one of first or second function blocks;
wherein the first function block, coupled to the protection block and the power supply pins, includes a second transistor and at least one fuse that corresponds to a security key;
wherein the first transistor has a first gate oxide breakdown voltage that is greater than a second gate oxide breakdown voltage of the second transistor;
wherein the protection block is configured such that when the voltage from at least one of the power supply pins exceeds the second gate oxide breakdown voltage but not the first gate oxide breakdown voltage, the protection block enters a secure mode of operation.

US Pat. No. 10,339,978

MULTI-SENSOR EVENT CORRELATION SYSTEM

BLAST MOTION INC., Carls...

1. A multi-sensor event correlation system comprising:at least one motion capture element configured to couple with a user or piece of equipment or mobile device coupled with the user, wherein said at least one motion capture element comprises
a sensor data memory;
a sensor configured to capture one or more values associated with an orientation, position, velocity, acceleration, angular velocity, and angular acceleration of said at least one motion capture element;
a first communication interface configured to receive communications, or one or more other values associated with an environmental sensor, a physiological sensor or both said environmental sensor and said physiological sensor or said communications and said one or more other values
or
at least one other sensor configured to locally capture said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor
or both said first communication interface and said at least one other sensor; and,
a microprocessor coupled with said sensor data memory, said sensor and said first communication interface, wherein said microprocessor is configured to
collect data that comprises sensor values that include said one or more values from said sensor;
store said data in said sensor data memory
or
analyze said data and recognize an event within said data to determine event data
or
store said data in said sensor data memory and analyze said data and recognize said event within said data to determine said event data; and,
transmit said data or said event data or both said data and said event data, and
process said communications
or
transmit said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor,
or
process said communications and transmit said one or more other values to
a computer, said computer comprising
a computer memory; and,
a second communication interface configured to communicate with said first communication interface to obtain
said data or said event data associated with said event or both said data and said event data
or
said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor
or both said data or said event data and
said one or more other values;
wherein said computer is coupled with said computer memory and is coupled with said second communication interface;
wherein said microprocessor is, or said computer is, or both said microprocessor and said computer are configured to
correlate said data or said event data with said one or more other values associated with said environmental sensor, said physiological sensor or both said environmental sensor and said physiological sensor to differentiate a first type of event with respect to a second type of event or a first type of activity with respect to a second type of activity or a first type of equipment with respect to a second type of equipment to determine at least one of
a type of event or true event or a false positive event selected from a plurality of types of events or
a type of equipment that said at least one motion capture element is coupled with selected from a plurality of types of equipment or
a type of activity indicated by said data or said event data selected from a plurality of types of activities.

US Pat. No. 10,339,977

INFORMATION PROCESSING APPARATUS DISPLAYING INDICES OF VIDEO CONTENTS, INFORMATION PROCESSING METHOD AND INFORMATION PROCESSING PROGRAM

KYOCERA CORPORATION, Kyo...

1. An information processing apparatus comprising:a memory configured to store video data;
a controller configured to generate first and second thumbnails by decoding respective portions of the video data; and
a display configured to display the first thumbnail or the second thumbnail,
wherein if a scroll instruction is received prior to completion of generation of the first thumbnail, the controller is configured to stop generating the first thumbnail and start generating the second thumbnail, and the display is configured to display the second thumbnail instead of the first thumbnail.

US Pat. No. 10,339,976

AUDIO DEVICE WHICH SYNCHRONIZES AUDIO DATA

Yamaha Corporation, Shiz...

1. An audio device which is configured to wirelessly receive audio data from another audio device, comprising:a memory which stores instructions and pulse data having a starting point and a predetermined length,
a clock which outputs an audio clock that indicates a timing of playback of the audio data, and
a processor that is configured to execute the instructions stored in the memory to:
wirelessly receive the audio data and a time stamp attached to the audio data from the other audio device,
output the pulse data having the starting point and the predetermined length in the audio device, the pulse data being output when the audio device receives the audio data,
detect start time of the pulse data based on the starting point by referring to the clock and end time of the pulse data by referring to the predetermined length and the start time,
compare the end time of the pulse data and the time stamp,
adjust the audio clock based on the comparing result, thereby adjusting the audio data, and
output the adjusted audio data synchronized with the other audio device, the adjusted audio data being output after the pulse data is output.

US Pat. No. 10,339,975

VOICE-BASED VIDEO TAGGING

GoPro, Inc., San Mateo, ...

1. A method for identifying an event of interest in a video, the method performed by a camera including one or more processors, the method comprising:accessing, by the camera, a captured speech pattern, the captured speech pattern captured from a user at a moment during capture of the video;
matching, by the camera, the captured speech pattern to a given stored speech pattern of multiple stored speech patterns, the multiple stored speech patterns corresponding to a command for identifying the event of interest within the video, individual ones of the multiple stored speech patterns stored based on a number of times the individual ones of the multiple stored speech patterns are captured by the camera from a user while the camera is operating in a training mode, wherein the individual ones of the multiple stored speech patterns correspond to an identification of the event of interest as occurring before, during, or after the moment; and
in response to matching the captured speech pattern to the given stored speech pattern, storing, by the camera, event of interest information associated with the video, the event of interest information identifying an event moment during the capture of the video at which the event of interest occurs, the event moment being determined to occur before, during, or after the moment based on the matching of the captured speech pattern to the given stored speech pattern.

US Pat. No. 10,339,974

AUDIO CONTROLLER DEVICE AND METHOD OF OPERATION THEREOF

MOTOROLA SOLUTIONS, INC.,...

1. An audio controller device, comprising:a memory for storing audio data;
a plurality of primary audio control interfaces; and
an electronic processor coupled to the primary audio control interfaces and the memory, the electronic processor configured to:
identify a plurality of audio segments from the audio data based on a plurality of contextual parameters associated with the audio data, wherein each of the plurality of audio segments includes a set of audio frames from the audio data, wherein each set of audio frames included in a respective one of the audio segments is uniquely identified by a combination of one or more of the contextual parameters;
associate each of the plurality of audio segments to a respective one of the primary audio control interfaces to enable each of the audio segments to be independently controlled through the respective one of the primary audio control interfaces to which the audio segment is associated; and
control a playback operation for all the audio frames included only in the respective one of the audio segments when an input is received at one or more of the primary audio control interfaces.

US Pat. No. 10,339,973

SYSTEM AND METHOD FOR AUDIO DUBBING AND TRANSLATION OF A VIDEO

International Business Ma...

1. A method of converting a first language of a soundtrack of a person speaking in a video to a second language, said method comprising:defining, by one or more processors of a computer system, outlines of shapes of mouth openings of the person speaking syllables of a word of the first language in the video;
translating, by the one or more processors of the computer system, a meaning of the word of the first language and locating one or more synonym words in the second language stored in a database of the computer system, said first and second languages being different languages;
comparing, by the one or more processors, outlines of the shapes of mouth openings of the one or more synonym words in the second language with the outlines of the shapes of mouth openings of the word of the first language; and
selecting, by the one or more processors, a synonym word of the one or more synonym words translated from the second language into the first language having mouth openings with a smallest difference from the mouth openings of the word of the first language.

US Pat. No. 10,339,972

SYSTEMS AND METHODS OF INTERACTIVE EXERCISING

OUTSIDE INTERACTIVE VISUA...

1. A computer system comprising:a memory;
at least one processor coupled to the memory; and
a user interface component executable by the at least one processor and configured to:
receive information from a sensor coupled to a user descriptive of a pace at which the user is exercising;
determine a playback speed for previously filmed video content captured contemporaneously with an audio component, the playback speed determined with reference to the pace at which the user is exercising;
present the video content at the playback speed;
generate a plurality of audio frames from the audio component, the plurality of audio frames being generated with reference to the pace at which the user is exercising; and
present the plurality of audio frames to the user.

US Pat. No. 10,339,971

SEQUENTIAL DATA STORAGE WITH REWRITE USING DEAD-TRACK DETECTION

International Business Ma...

1. A system, comprising:a magnetic head having a plurality of write transducers and a plurality of read transducers, each read transducer being configured to read data from a sequential access medium after being written thereto by a corresponding write transducer; and
a controller and logic integrated with and/or executable by the controller, the logic being configured to:
read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously;
determine that one or more tracks of the sequential access medium are dead within a sliding window; and
rewrite a set of encoded data from the one or more dead tracks to one or more live tracks in a rewrite area of the sequential access medium,
wherein a first track of the plurality of tracks is determined to be dead in response to a determination that an output from a first read transducer is insufficient, wherein the first read transducer is aligned with a first write transducer configured to store data to the first track, wherein the output of the first read transducer is produced during read-while-write, and wherein the live tracks comprise all of the plurality of tracks of the sequential access medium except for the one or more dead tracks.

US Pat. No. 10,339,970

VIDEO RECORDING APPARATUS WITH PRE-EVENT CIRCULATION RECORDING FUNCTION

IDIS Co., Ltd., Daejeon-...

1. A video recording apparatus with a pre-event circulation recording function, the video recording apparatus comprising:a video receiver configured to receive a video captured in real time by at least one camera;
a nonvolatile storage unit configured to store the received video; and
a recording controller configured to control a pre-event video generated before an event occurs to be circulation recorded on a pre-event storage region of the nonvolatile storage unit while complying with a pre-event storage period, and control a post-event video generated after the event occurs to be recorded on a post-event storage region allocated separately from the pre-event storage region,
wherein, when the pre-event storage period is temporarily not complied with due to the circulation recording of the pre-event video, the recording controller allocates a spare storage region after the pre-event storage region for complying with the pre-event storage period, and
wherein, when returning to a start of the pre-event storage region after recording the pre-event video which has a length satisfying the pre-event storage period, the recording controller records the pre-event video on the spare storage region prior to returning to the start of the pre-event storage region in order to comply with the pre-event storage period irrespective of initial data of the pre-event storage region being overwritten when returning to the start of the pre-event storage region.

US Pat. No. 10,339,969

DETERMINING BIT ASPECT RATIOS FOR PARTIALLY-OVERLAPPING MAGNETIC RECORDING TRACKS

Seagate Technology LLC, ...

1. A method, comprising:writing isolated test tracks to determine a first areal density function for top tracks of a magnetic recording medium, the first areal density function based on write-plus-erase track widths obtained using different first laser powers and first linear bit densities that achieve a first target bit error rate for the isolated test tracks;
selecting a value LDItop of the first laser powers and a value BPItop of the first linear bit densities that result in a first target value of the areal density function;
writing partially-overlapping test tracks to determine a second areal density function of bottom tracks based on squeezed track widths written using different second laser powers and second linear bit densities that achieve a second target bit error rate for bottom test tracks of the partially-overlapping test tracks, top test tracks of the partially-overlapping test tracks being written at LDItop and BPItop; and
selecting a value LDIbottom of the second laser powers and a value BPIbottom of the second linear bit densities that result in a second target value of the second areal density function, the LDItop, BPItop, LDIbottom, and BPIbottom subsequently being used to respectively record top tracks partially overlapping bottom tracks.

US Pat. No. 10,339,968

BASE UNIT, SPINDLE MOTOR, AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A base unit for use in a disk drive apparatus including a motor arranged to be capable of rotating about a central axis extending in a vertical direction, the base unit comprising:a base member arranged to extend radially to support the motor, and including a predetermined adhesion region and an outside region outside of the adhesion region; and
a connector electrically connected to a wire arranged on the base member; wherein
the connector is adhered to the base member through an adhesive at the adhesion region of the base member;
a wettability of the adhesive on the adhesion region is higher than a wettability of the adhesive on the outside region of the base member; and
the base member includes a connector housing portion recessed in an axial direction and arranged to house the connector;
the adhesion region is arranged in a bottom surface of the connector housing portion; and
a distance between a side wall of the connector housing portion and the adhesion region measured in a direction perpendicular to the axial direction is in a range of 0.1 mm to 2.0 mm inclusive.

US Pat. No. 10,339,967

REPRODUCING APPARATUS AND REPRODUCING METHOD

SONY CORPORATION, Tokyo ...

1. A reproducing apparatus comprising:an optical system that irradiates a recording medium on which signals are each recorded on a land and a groove with a light beam emitted from a light source to obtain a signal light beam reflecting each of the recording signals of the land and the groove, generates a reference light beam from the light beam emitted from the light source, and generates a set of a first signal light beam and a reference light beam which give a phase difference of approximately 0° to a superimposed light beam obtained by superimposing the signal light beam and the reference light beam, a set of a second signal light beam and a second reference light beam which give a phase difference of approximately 180° to the superimposed light beam, a set of a third signal light beam and a third reference light beam which give a phase difference of approximately 90° to the superimposed light beam, and a set of a fourth signal light beam and a fourth reference light beam which give a phase difference of approximately 270° to the superimposed light beam;
a light receiving unit that uses a first light receiving element to receive the set of the first light beam and the first reference light beam, a second light receiving element to receive the set of the second signal light beam and the second reference light beam, a third light receiving element to receive the set of the third signal light beam and the reference, and a fourth light receiving element to receive the set of the fourth signal light beam and the fourth reference light beam;
a reproduction signal generating circuit that calculates a first difference signal a which is a difference between a first light receiving signal obtained by the first light receiving element and a second light receiving signal obtained by the second light receiving element, and a second difference signal b which is a difference between a third light receiving signal obtained by the third light receiving element and a fourth light receiving signal obtained by the fourth light receiving element, and
uses the first difference signal a, the second difference signal b, a phase difference ? between a crosstalk component and an average phase of the signal light beam, and an optical path length difference ? between the signal light beam and the reference light beam to carry out an arithmetic operation of
a·sin(???(t))?b·cos(???(t))
to obtain a reproduction signal; and
a phase extraction circuit that obtains a successive change amount ?? of ? and updates ? with the successive variation ??.

US Pat. No. 10,339,966

MULTILAYER DISK DRIVE MOTORS HAVING OUT-OF-PLANE BENDING

Hutchinson Technology Inc...

1. A motor for a suspension structure, comprising:at least a first poled piezoelectric material actuator layer and a second poled piezoelectric material actuator layer positioned between a first end terminal and a second end terminal, the first end terminal and the second end terminal are configured to connect with a first connector and a second connector, respectively, to mount to the suspension structure;
a first conductive layer extending from the second connector, a third conductive layer extending from the second terminal, and a second conductive layer and a fourth conductive layer extending from the first terminal, the first and third conductive layers are not directly connected to each other, each of the conductive layers disposed on at least one of the actuator layers, the conductive layers configured to be electrically connected to one or more electrical traces on the suspension structure; and
the poled actuator layers and conductive layers are configured such that the application of a first polarity drive signal causes the motor to curl in a first direction and the application of a second polarity drive signal causes the motor to curl in a second direction.

US Pat. No. 10,339,965

THERMALLY ASSISTED MAGNETIC RECORDING HEAD HAVING PLASMON GENERATOR IN WHICH DIELECTRIC LAYER IS SURROUNDED BY METAL LAYER

TDK Corporation, Tokyo (...

1. A thermally assisted magnetic recording head, comprising:a waveguide that propagates laser light as propagating light,
a main pole that includes a first end portion on an air bearing surface (ABS) facing a magnetic recording medium and that emits a magnetic flux to the magnetic recording medium,
a metal layer that is positioned between the main pole and the waveguide, that extends from a second end portion positioned on the ABS in a height direction, that generates surface plasmons from the propagating light, and that generates near-field light (NF light) from the surface plasmons at the second end portion, and
a dielectric body layer that is surrounded on both sides of the dielectric body layer in a down-track direction by the metal layer and that extends from a third end portion positioned on the ABS in a height direction, wherein a dimension of the metal layer in a cross-track direction is greater than that of the waveguide in the cross-track direction on the ABS.

US Pat. No. 10,339,964

PERPENDICULAR MAGNETIC RECORDING (PMR) WRITE HEAD WITH PATTERNED HIGH MOMENT TRAILING SHIELD

Headway Technologies, Inc...

1. A perpendicular magnetic recording (PMR) writer, comprising:(a) a main pole (MP) with a top surface that is aligned orthogonal to an air bearing surface (ABS), and having a MP tip with a trailing side at the ABS wherein the trailing side is bisected by a center plane;
(b) a trailing shield comprised of a high moment trailing shield (HMTS) layer with a magnetization saturation value from 16 kiloGauss (kG) to about 24 kG, and having a front portion formed on a write gap at the ABS; the HMTS layer comprises:
(1) the front portion that extends to a first height (h1) from the ABS;
(2) a middle portion that adjoins a backside of the front portion at h1 and extends to a second height (h2) from the ABS where h2>h1, and the middle portion at h2 is a greater down-track distance from the MP than at h1; and
(3) a back portion that adjoins a backside of the middle portion at h2 and extends to a backend at a third height (h3) from the ABS, and has a top surface formed parallel to the MP top surface, and wherein the back portion has a first down-track (DT) thickness d1 in at least a region adjacent to an outer side thereof on each side of the center plane, and behind a first plane at a pattern height (h) where h>h2, and in regions in front of the first plane that are outside of a trapezoidal shape having a first side at the first plane, a second side at a backside of the front portion or middle portion, a first inner side formed at an angle ? with respect to a second plane that intersects the first plane at width w/2 from the center plane, and a second inner side formed at angle ? with respect to a third plane at width w/2 on an opposite side of the center plane, wherein the second and third planes are parallel and the first and second inner sides have increasing separation with decreasing height from the ABS, and wherein the back portion has a second DT thickness d within the trapezoid shape where d (c) a dielectric layer formed between the HMTS back portion and the MP top surface wherein the dielectric layer has a DT thickness g in portions thereof formed below the HMTS back portion having thickness d, and a DT thickness g1, where g>g1, below the HMTS back portion having thickness d1.

US Pat. No. 10,339,963

DETERMINING THERMAL GRADIENT OF A HAMR HOTSPOT USING PSEUDO-RANDOM BIT SEQUENCES RECORDED AT A STEPPED LASER POWER

Seagate Technology LLC, ...

1. A method, comprising:recording pseudorandom bit sequences to a heat-assisted recording medium at a laser power that is stepped while recording the pseudorandom bit sequences;
reading the pseudorandom bit sequences from the heat-assisted recording medium to determine timing differences between bits written before and after the laser power is stepped; and
determining a thermal gradient of bits written to the heat-assisted recording medium based on the timing differences.

US Pat. No. 10,339,962

METHODS AND APPARATUS FOR LOW COST VOICE ACTIVITY DETECTOR

TEXAS INSTRUMENTS INCORPO...

10. A method of detecting voice in a first input signal, the method comprising:in a noise state, sampling a second input signal to form noise samples, and computing a noise value as a covariance matrix of the noise samples, the second input signal containing noise and no voice;
in the noise state, sampling the first input signal to form first signal samples, and computing a first voice value from the first signal samples;
in the noise state, detecting potential voice activity in the first signal samples;
responsive to the detecting, transitioning to a voice state;
in the voice state, sampling the first input signal to form second signal samples, and computing a second voice value as a covariance matrix of the second signal samples;
in the voice state, computing a first ratio as a log likelihood ratio of the second voice value to the noise value;
in the voice state, if the first ratio exceeds a threshold, indicating a voice activity detection, and remaining in the voice state;
in the voice state, if the first ratio does not exceed the threshold, transitioning to an interim state;
in the interim state, sampling the first input signal to form third signal samples, and computing a third voice value from the third signal samples;
in the interim state, computing a second ratio of the third voice value to the noise value;
in the interim state, if the second ratio exceeds the threshold, transitioning to the voice state; and
in the interim state, if the second ratio does not exceed the threshold, transitioning to the noise state.

US Pat. No. 10,339,961

VOICE ACTIVITY DETECTION METHOD AND APPARATUS

ZTE CORPORATION, Shenzhe...

10. A Voice Activity Detection (VAD) apparatus, comprising a hardware processor arranged to execute the following program units:an acquisition component, arranged to acquire at least one first class feature in a first feature category, at least one second class feature in a second feature category and at least two existing VAD judgment results, wherein the first class feature and the second class feature are features used for VAD detection; and
a detection component, arranged to carry out, according to the first class feature, the second class feature and the at least two existing VAD judgment results, VAD to obtain a combined VAD judgment result;
wherein the acquisition component comprises the following program subunits:
a first acquisition unit, arranged to acquire the first class feature in the first feature category which comprises at least one of: a number of continuous active frames, an average total signal-to-noise ratio (SNR) of all sub-bands and a tonality signal flag, wherein the average total SNR of all sub-bands is an average of SNR over all sub-bands for a predetermined number of frames; and
a second acquisition unit, arranged to acquire the second class feature in the second feature category which comprises at least one of: a flag of noise type, a smoothed average long-time frequency domain SNR, a number of continuous noise frames and a frequency domain SNR.