US Pat. No. 10,249,754

PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS

International Business Ma...

1. A semiconductor device comprising:a first source region and a first drain region made of a first semiconductor material, wherein the first source region has an upper portion and a lower portion;
an etch stop layer made of a second semiconductor material different from the first semiconductor material between the upper portion and the lower portion of the first source region; and
a channel semiconductor material on an upper surface of the upper portion of the first source region, wherein the first drain region is on the channel semiconductor material.

US Pat. No. 10,249,753

GATE CUT ON A VERTICAL FIELD EFFECT TRANSISTOR WITH A DEFINED-WIDTH INORGANIC MASK

INTERNATIONAL BUSINESS MA...

1. A vertical field effect transistor (VFET) comprising:a first spacer disposed on a silicon substrate;
fins from the substrate through the spacer;
an oxide layer disposed on the fins;
a hard mask layer disposed on the oxide layer; and
a second spacer with a defined width disposed around the fins, oxide layer and hard mask layer, forming a gate around the fins.

US Pat. No. 10,249,751

HIGH-SPEED DIODE WITH CRYSTAL DEFECTS AND METHOD OF MANUFACTURING

ROHM CO., LTD., Kyoto (J...

1. A high-speed diode comprising:an n-type semiconductor layer; and
a p-type semiconductor layer which is laminated on the n-type semiconductor layer,
wherein a pn junction is formed in a boundary portion between the n-type semiconductor layer and the p-type semiconductor layer,
crystal defects are formed away from the p-type semiconductor layer and such that a frequency of appearance is gradually decreased from an upper surface of the p-type semiconductor layer toward a bottom surface of the n-type semiconductor layer,
the high-speed diode has a profile of a positive hole concentration distribution when having a low current in which a forward current density is equal to or less than 1 A/mm2,
the profile includes an inflection point spaced apart from a surface of the p-type semiconductor layer, and
a positive hole concentration of the profile decreases from the surface of the p-type semiconductor layer towards the inflection point and increases from the inflection point towards the bottom surface of n-type semiconductor layer.

US Pat. No. 10,249,750

SEMICONDUCTOR DEVICE

ELECTRONICS AND TELECOMMU...

1. A semiconductor device, comprising:a first semiconductor layer;
a second semiconductor layer disposed on the first semiconductor layer;
a structure layer disposed on the second semiconductor layer;
a metal film covering a side surface of the first semiconductor layer, a side surface of the second semiconductor layer, and an upper surface of the structure layer; and
a flexible substrate covering the metal film,
wherein a width of the first semiconductor layer is smaller than a width of the second semiconductor layer,
wherein the width of the second semiconductor layer is smaller than a width of the structure layer.

US Pat. No. 10,249,747

TURN-OFF POWER SEMICONDUCTOR DEVICE WITH IMPROVED CENTERING AND FIXING OF A GATE RING, AND METHOD FOR MANUFACTURING THE SAME

ABB Schweiz AG, Baden (C...

1. Turn-off power semiconductor device comprising:a wafer having a first main side, a second main side parallel to the first main side and extending in a lateral direction, an active region and a termination region on the first main side laterally surrounding the active region;
at least one thyristor cell in the active region between the first main side and the second main side, the at least one thyristor cell comprising in the order from the first main side to the second main side:
(a) a first cathode electrode;
(b) a cathode semiconductor layer of a first conductivity type;
(c) a base semiconductor layer of a second conductivity type different from the first conductivity type;
(d) a drift semiconductor layer of the first conductivity type;
(e) an anode semiconductor layer of the second conductivity type;
(f) a first anode electrode,
wherein the at least one thyristor cell further comprises a gate electrode which is arranged lateral to the cathode semiconductor layer and contacting the base semiconductor layer, and
wherein the at least one gate electrode of the at least one thyristor cell is electrically connected to a ring-shaped contact for contacting the at least one gate electrode of the at least one thyristor cell, wherein the ring-shaped contact is formed on the first main side of the wafer in the termination region and surrounds the active region;
the device further comprising:
a rubber ring arranged on the termination region and surrounding the active region; and
an electrically conductive gate ring for contacting the ring-shaped contact from outside, wherein the gate ring is disposed on and electrically connected to the ring-shaped contact within the rubber ring,
wherein an outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring,
wherein an upper surface of the gate ring and an upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

US Pat. No. 10,249,746

BIPOLAR TRANSISTOR WITH SUPERJUNCTION STRUCTURE

Infineon Technologies AG,...

1. A superjunction bipolar transistor, comprising:an active transistor cell area comprising active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body;
a superjunction area overlapping the active transistor cell area, the superjunction area comprising a low-resistive region and a reservoir region outside of the low-resistive region, wherein the low-resistive region comprises a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body, and wherein the reservoir region comprises no superjunction structure such that the reservoir region comprises the semiconductor body that extends from a region located at the first surface to a drain region; and
a collector structure directly electrically connected to a second load electrode at a reverse side opposite to the front side and forming a continuous layer directly adjoining a second surface of the semiconductor body opposite to the first surface, wherein the collector structure forms a pn junction with a drift structure that comprises the first superjunction structure.

US Pat. No. 10,249,744

TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING TUNNEL FIELD-EFFECT TRANSISTOR

HUAWEI TECHNOLOGIES CO., ...

1. A tunnel field-effect transistor, comprising:a substrate;
an oxide structure, wherein the oxide structure is located on a surface of the substrate;
insulation layers, wherein the insulation layers are located on the surface of the substrate and two sides of the oxide structure;
source regions, wherein the source regions are located on surfaces of the insulation layers and the two sides of the oxide structure, and an end face on an end that is of the source region and that is away from the substrate is lower than an end face on a side that is of the oxide structure and that is away from the substrate;
epitaxial layer, wherein the epitaxial layer is located on the surface of the insulation layer and a surface on a side that is of the source region and that is away from the oxide structure, and an end face on a side that is of the epitaxial layer and that is away from the substrate is flush with an end face on a side that is of the source region and that is away from the substrate;
a gate structure, wherein the gate structure is located on the surface of the insulation layer and a surface on a side that is of the epitaxial layer and that is away from the source region;
channel layers, wherein the channel layers are located on the two sides of the oxide structure and cover the source regions and the epitaxial layer, and an end face on a side that is of the channel layer and that is away from the substrate is flush with the end face on the side that is of the oxide structure and that is away from the substrate; and
a drain region, wherein the drain region covers the oxide structure and the channel layers.

US Pat. No. 10,249,743

SEMICONDUCTOR DEVICE WITH LOW BAND-TO-BAND TUNNELING

International Business Ma...

1. A semiconductor device comprising:a dielectric layer on an insulator layer over a semiconductor substrate;
a source and a drain in the dielectric layer;
a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first bandgap is larger than the second bandgap; and
a gate over the channel;
wherein the first region further comprises:
a first subregion and a second subregion;
wherein the first subregion is adjacent to the source and wherein the second subregion is adjacent to the drain.

US Pat. No. 10,249,742

OFFSTATE PARASITIC LEAKAGE REDUCTION FOR TUNNELING FIELD EFFECT TRANSISTORS

Intel Corporation, Santa...

1. A method comprising:forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate comprising a blocking material beneath the channel, the blocking material comprising a property to inhibit carrier leakage, wherein the blocking material comprises an air gap and after forming the channel, the method comprises removing a portion of the substrate beneath the channel; and
forming a gate stack on the channel, the gate stack comprising a dielectric material and a gate electrode.

US Pat. No. 10,249,740

GE NANO WIRE TRANSISTOR WITH GAAS AS THE SACRIFICIAL LAYER

Intel Corporation, Santa...

1. An apparatus comprising:a three-dimensional semiconductor body comprising a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body comprising:
a plurality of nanowires comprising a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and
a gate stack disposed on the channel region, the gate stack comprising a gate electrode disposed on a gate dielectric.

US Pat. No. 10,249,739

NANOSHEET MOSFET WITH PARTIAL RELEASE AND SOURCE/DRAIN EPITAXY

International Business Ma...

1. A method of forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure, the method comprising:forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer;
patterning the heteroepitaxial film stack;
forming a dummy gate stack and sidewall spacers;
forming a cladded or embedded epitaxial source/drain region directly contacting sidewalls of each of the at least one sacrificial layer and each of the at least one channel layer such that elastic relaxation of the at least one sacrificial layer causes tensile strain to the at least one channel layer;
removing the dummy gate stack;
partially removing sections of the at least one sacrificial layer such that remaining sections of the at least one sacrificial layer preserve the tensile strain in the at least one channel layer; and
forming a replacement gate stack directly in contact with the remaining sections of the at least one sacrificial layer.

US Pat. No. 10,249,738

NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION

INTERNATIONAL BUSINESS MA...

1. A structure used to fabricate a nanosheet semiconductor device, the structure comprising:a substrate;
two or more sets of silicon layers formed above the substrate, wherein each of the two or more sets of silicon layers is parallel to others of the two or more sets of silicon layers in a first direction and each of the two or more sets of silicon layers includes gaps between adjacent ones of the silicon layers of each respective set of silicon layers; and
a dielectric material configured to anchor each of the two or more sets of silicon layers at a first end and a second end of each of the two or more sets of silicon layer along a second direction, which is perpendicular to the first direction, wherein the dielectric material partially fills the gaps between the adjacent ones of the silicon layers of each respective set of silicon layers of the two or more sets of silicon layers and is between adjacent ones of the two or more sets of silicon layers.

US Pat. No. 10,249,737

SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:forming an amorphous silicon layer portion directly on a topmost surface of an active silicon germanium (SiGe) region of a silicon germanium-on-insulator material;
forming a gate structure on a topmost surface of said amorphous silicon layer portion, wherein said gate structure comprises a gate dielectric portion present directly on the topmost surface of said amorphous silicon layer portion and a gate conductor portion present on said dielectric portion;
forming a gate dielectric spacer on sidewalls of said gate structure and sidewalls of said amorphous silicon layer portion, wherein a bottommost surface of said gate dielectric spacer is in direct contact with said topmost surface of said active SiGe region and is coplanar with a bottommost surface of said amorphous silicon layer portion; and
forming an embedded SiGe channel region in said active SiGe region directly beneath said gate structure utilizing a thermal mixing process in which silicon atoms from said amorphous silicon layer portion intermix with germanium atoms in said SiGe active region to form said embedded SiGe channel region, wherein said thermal mixing process entirely removes the amorphous silicon layer from the semiconductor structure such that a topmost surface of said embedded SiGe channel region is in direct physical contact with a bottommost surface of said gate dielectric portion and said embedded SiGe channel region has a lower germanium content than said active SiGe region.

US Pat. No. 10,249,736

ASPECT RATIO TRAPPING IN CHANNEL LAST PROCESS

International Business Ma...

1. A method of forming the fin structure comprising:forming a replacement gate structure on a channel region of the at least one replacement fin structure, the replacement fin structure extending from a supporting substrate;
forming an encapsulating dielectric on the supporting substrate and the at least one replacement gate structure, wherein the encapsulating dielectric encapsulates the replacement fin structure and a portion of the replacement gate structure is exposed;
etching an exposed portion of the replacement gate structure to provide an opening through the encapsulating dielectric to the replacement fin structure;
etching the replacement fin structure selectively to the encapsulating dielectric to remove an entirety of the replacement fin structure and to remove a portion of underlying supporting substrate and provide a fin opening having a geometry dictated by the encapsulating dielectric that exposes a growth surface of the substrate; and
epitaxially growing functional fin structures of a second semiconductor material on the growth surface of the supporting substrate substantially filling the fin opening.

US Pat. No. 10,249,734

POLY-SILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a poly-silicon thin film transistor comprising: forming an active layer on a base substrate, and a gate insulation layer and a gate electrode above the active layer, the active layer including a first poly-silicon area, lightly doped areas located at both sides of the first poly-silicon area, and heavily doped areas located at a side of the lightly doped areas away from the first poly-silicon area,wherein forming of the lightly doped areas of the active layer includes:
forming a poly-silicon layer on the base substrate, the poly-silicon layer including the first poly-silicon area, second poly-silicon areas located at both sides of the first poly-silicon area, and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area;
with a film layer covering the first poly-silicon area and the second poly-silicon areas as a mask, the third poly-silicon areas are doped to form the heavily doped areas;
forming a barrier layer between the gate electrode and the gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and
after doping the third poly-silicon areas with the film layer covering the first poly-silicon area and the second poly-silicon areas as the mask, doping the second poly-silicon areas with the barrier layer covering the first poly-silicon area as a mask, to form the lightly doped areas,
wherein the barrier layer is a layer which serves as the mask for doping and which has an orthographic projection on the poly-silicon layer coinciding with the first poly-silicon area, and the dry etching method for directly forming the barrier layer is before etching for directly forming the gate electrode.

US Pat. No. 10,249,732

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE TO UNIFORMLY FORM THICKNESS OF GATE INSULATING LAYER

Hyundai Motor Company, S...

1. A manufacturing method of a semiconductor device, comprising:sequentially forming an n? type of layer, a p type of region, and an n+ type of region on a first surface of a substrate;
forming a preliminary trench including a lower surface upwardly convex with respect to the first surface of the substrate in the n? type of layer by performing a first etching process;
forming a preliminary gate insulating layer including a preliminary first portion disposed at a lateral surface of the preliminary trench and a preliminary second portion disposed at the lower surface of the preliminary trench by performing a first thermal oxidation process;
etching the lower surface of the preliminary trench and the preliminary second portion to form a trench by performing a second etching process; and
forming a gate insulating layer in the trench by performing a second thermal oxidation process,
wherein the gate insulating layer includes a first portion disposed at a lateral surface of the trench and a second portion disposed at a lower surface of the trench,
wherein a thickness of the preliminary first portion is greater than a thickness of the preliminary second portion,
wherein the thickness of the preliminary first portion is greater than a thickness of the first portion,
wherein the thickness of the first portion is the same as a thickness of the second portion, and
wherein the thickness of the second portion is uniform.

US Pat. No. 10,249,731

VERTICAL FET WITH SHARP JUNCTIONS

International Business Ma...

1. A method of forming a vertical field-effect transistor (VFET) device, the method comprising the steps of:forming a silicon germanium (SiGe) layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped;
forming a silicon (Si) layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped;
patterning fins in the Si layer by forming fin hardmasks on the Si layer, and etching the fins in the Si layer using the fin hardmasks;
forming sacrificial spacers along sidewalls of the fins;
forming recesses in the SiGe layer between the fins;
growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses comprises a source and drain dopant;
annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device;
removing the sacrificial spacers;
forming a bottom spacer on the bottom source and drains of the VFET device;
depositing a gate dielectric onto the fins and the bottom spacer;
depositing a gate conductor onto the gate dielectric;
depositing an organic planarizing layer (OPL) over the fins;
recessing the OPL below tops of the fins;
recessing the gate dielectric and the gate conductor to expose the fin hardmasks on the tops of the fins;
forming a top spacer on the OPL in between the tops of the fins;
removing the fin hardmasks; and
forming top source and drains of the VFET device on the tops of the fins.

US Pat. No. 10,249,730

CONTROLLING GATE PROFILE BY INTER-LAYER DIELECTRIC (ILD) NANOLAMINATES

International Business Ma...

1. A method comprising:providing a semiconductor structure including a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures;
depositing over outer surfaces of said plurality of gate structures a liner of a silicon-containing material;
depositing over said liner of silicon-containing material an inter-layer dielectric material; and
annealing said semiconductor substrate with said deposited liner of silicon-containing material and deposited inter-layer dielectric material, to at least partially consume said liner of silicon-containing material into said inter-layer dielectric material, to control residual stress such that resultant gate structures following said annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

US Pat. No. 10,249,728

AIR-GAP GATE SIDEWALL SPACER AND METHOD

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit structure comprising:a gate adjacent to a semiconductor body at a channel region, the channel region being positioned laterally between source/drain regions;
a gate contact above and immediately adjacent to the gate;
metal plugs on the source/drain regions;
plug caps above and immediately adjacent to the metal plugs; and
a dielectric spacer comprising:
a lower air-gap segment positioned laterally between the gate and the metal plugs; and
an upper solid segment positioned laterally between the gate contact and the plug caps, wherein the lower air-gap segment is wider than a top portion of the upper solid segment.

US Pat. No. 10,249,727

SEMICONDUCTOR DEVICE WITH SILICON NITRIDE FILM OVER NITRIDE SEMICONDUCTOR LAYER AND BETWEEN ELECTRODES

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a first nitride semiconductor layer formed above a substrate;
a gate electrode arranged over the first nitride semiconductor layer via a gate insulating film;
a first electrode and a second electrode that are formed above the first nitride semiconductor layer on both sides of the gate electrode, respectively;
a silicon nitride film, including:
a first portion of the silicon nitride film formed on the first nitride semiconductor layer between the first electrode and the gate electrode;
a second portion of the silicon nitride film formed on the first nitride semiconductor layer between the second electrode and the gate electrode; and
a third portion of the silicon nitride film formed between the gate electrode and the gate insulating film,
wherein a concentration of two-dimensional electron gas in the first nitride semiconductor layer below the first portion of the silicon nitride film and the second portion of the silicon nitride film is higher than that of the two-dimensional electron gas in the first nitride semiconductor layer below the gate insulating film.

US Pat. No. 10,249,725

TRANSISTOR WITH A GATE METAL LAYER HAVING VARYING WIDTH

DELTA ELECTRONICS, INC., ...

1. A semiconductor device comprising:an active layer;
at least one source electrode and at least one drain electrode present on the active layer;
at least one gate electrode present on the active layer and between the source electrode and the drain electrode;
a first insulating layer present on the source electrode, the drain electrode, and the gate electrode;
at least one gate metal layer present on the gate electrode and the first insulating layer, wherein the gate metal layer comprises a plurality of narrow portions and a plurality of wider portions arranged along a direction, at least one of the wider portions of the gate metal layer is in direct contact with two adjacent narrow portions of the gate metal layer, and the gate electrode is arranged along the direction;
a plurality of vias present between the gate metal layer and the gate electrode;
at least one first source metal layer present on the source electrode and the first insulating layer;
at least one drain metal layer present on the drain electrode and the first insulating layer; and
at least one second source metal layer present on the first insulating layer and at the same level as the gate metal layer and the drain metal layer, wherein the second source metal layer comprises a plurality of narrow portions and a plurality of wider portions, the narrow portions of the second source metal layer are adjacent respectively to the wider portions of the gate metal layer, and the wider portions of the second source metal layer are adjacent respectively to the narrow portions of the gate metal layer, and a projection of all of the gate metal layer onto the active layer in a direction normal to the upper surface of the substrate is separated from a projection of the second source metal layer onto the active layer in the direction normal to the upper surface of the substrate and a projection of the drain metal layer onto the active layer in the direction normal to the upper surface of the substrate.

US Pat. No. 10,249,724

LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES

INTERNATIONAL BUSINESS MA...

1. An electrical device comprising:at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device;
a metal semiconductor alloy region that is in direct contact with the at least one contact surface;
a conformal titanium liner present on the sidewalls of the trench and is in direct contact with the metal semiconductor alloy region that is atop the at least one contact surface; and
a metal fills the at least one trench, and is in direct contact with the conformal titanium liner, the metal is selected from the group consisting of comprising ruthenium (Ru), iridium (Ir), osmium (Os), molybdenum (Mo), copper (Cu) and a combination thereof, wherein a contact provided by a combination of the conformal titanium liner and the metal fill have a resistance of 45 micro ohms per cm or less.

US Pat. No. 10,249,723

SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

20. A semiconductor device, comprising:a semiconductor body having a surface;
a trench arranged within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body;
a first electrode and a first insulator arranged within the trench, the first insulator insulating the first electrode from the semiconductor body; and
a second electrode and a second insulator arranged within the trench, the second insulator insulating the second electrode from the first electrode,
wherein the first electrode extends deeper within the trench than the second electrode and forms a well incorporating each of the second electrode and the second insulator,
wherein at a first lateral termination area between the active region and the non-active region, each of the first electrode and the second electrode extend towards the surface such that the first electrode and the second electrode have a common lateral extension range and a common vertical extension range,
wherein a groove is formed in a lateral extremity of the second electrode, at the first lateral termination area.

US Pat. No. 10,249,722

REDUCED PARASITIC CAPACITANCE WITH SLOTTED CONTACT

International Business Ma...

1. A semiconductor device, the device comprising:a first conductor formed on a substrate, having a first top surface with a first height that is positioned above the substrate, wherein:
a first insulating material is provided over the first conductor and the substrate;
one or more openings disposed in the first insulating material defined by two opposing surfaces that are in contact with the first insulating material and a bottom surface that is in contact with the substrate; and
a thin layer of metal silicide is provided in the one or more openings of the first insulating material such that the thin layer of metal silicide is adjacent to the first conductor;
a second conductor formed on the metal silicide, the second conductor having a second top surface with a second height that is positioned above the substrate and a bottom surface that interacts directly with a first top surface of the metal silicide, wherein:
a portion of the second conductor is removed to provide a slot,
the slot is defined by opposing interior sidewalls and a bottom portion such that the bottom portion of the slot is below the first height of the first conductor,
the top of the slot is at the second height of the second conductor,
a long direction of the slot is perpendicular to a silicon fin and the silicon fin is perpendicular to and passes through the first conductor, and
a second insulating material disposed into the slot, the second insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide a space within the slot for a third conductor, wherein:
the second insulating material is different than the first insulating material, and
the third conductor is a contact metal selected from a group comprising:
tungsten, copper, and aluminum; and
the third conductor deposited into the space within the slot, the third conductor having a fourth top surface with a fourth height above the substrate, the fourth height being equal to the second height of the second conductor without the use of lithography, wherein:
the second insulating material is a six-sided feature including two faces and four sides,
the two faces of the second insulating material are in contact with the first insulating material,
three of the four sides of the second insulating material are in contact with the second conductor,
one of the four sides of the second insulating material is in contact with the third conductor, and
the third height of the second insulating material is determined at least in part by resistance requirements of the semiconductor device.

US Pat. No. 10,249,721

SEMICONDUCTOR DEVICE INCLUDING A GATE TRENCH AND A SOURCE TRENCH

Infineon Technologies Aus...

1. A semiconductor device, comprising:a source trench extending into a semiconductor body from a first surface of the semiconductor body;
a source trench dielectric and a source trench electrode in the source trench;
a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface;
a body region of a first conductivity type between the gate and source trenches;
a source region of a second conductivity type different from the first conductivity type between the gate and source trenches;
an interconnection electrically coupling the body region and the source trench electrode,
wherein the interconnection laterally extends through the source trench dielectric in a direction that is parallel to the first surface and adjoins a lateral face of the source trench electrode and of the body region, the lateral face of the source trench electrode and of the body region being perpendicular to the first surface,
and wherein an interface between the source trench dielectric and the semiconductor body at a sidewall of the source trench is step shaped at a transition between lower and upper parts of the source trench dielectric; wherein the step shaped interface between the source trench dielectric and the semiconductor body directly contacts the source trench dielectric and the semiconductor body, and
a source contact on the source trench electrode at the first surface.

US Pat. No. 10,249,720

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device that includes an active region, comprising:a semiconductor substrate having first and second principal surfaces;
a first conductive type region disposed in a first principal side of the semiconductor substrate;
a second conductive type region disposed on the first conductive type region;
a trench disposed farther outward than the active region, the trench having a width extending in a first direction, and a depth extending in a second direction, away from the first principal surface of the semiconductor substrate, the trench having first and second side walls;
a pn junction between the second conductivity type region and the first conductivity type region, the pn junction extending outwardly from the active region in the first direction and being terminated by the trench;
an insulating film embedded inside the trench;
a first field plate disposed inside the insulating film and extending in the second direction, a distance between the first side wall of the trench and the first field plate in the first direction being greater than a width of the first field plate, the first field plate curving away from the first side wall of the trench in the first direction, as a depth of the first field plate from the first principal surface of the semiconductor substrate increases;
a first electrode contacting the second conductivity type region and the first field plate; and
a second electrode disposed at the second principal surface of the semiconductor substrate.

US Pat. No. 10,249,719

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method, comprising:providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer;
etching the semiconductor layer so as to form a fin and exposing the buffer layer;
etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed; and
oxidizing the buffer layer and the fin so as to form an oxide layer under the fin,
wherein a distance between a top surface of the oxide layer and a top surface of the buffer layer is more than a distance between a bottom surface of the fin and the top surface of the buffer layer such that, a distance between a bottom surface of the substrate and the top surface of the oxide layer is more than a distance between the bottom surface of the substrate and the bottom surface of the fin.

US Pat. No. 10,249,717

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode;
a second electrode, the second electrode including a first electrode region, a second electrode region, and a third electrode region, a first direction being from the first electrode toward the first electrode region and crossing a second direction, the second direction being from the first electrode region toward the second electrode region, a position of the third electrode region in the first direction being between a position of the first electrode region in the first direction and a position of the first electrode in the first direction;
a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, the first partial region being separated from the first electrode in a third direction, the third direction crossing the first direction and the second direction, the second partial region being separated from the first electrode region in the third direction, a position of the third partial region in the first direction being between a position of the first partial region in the first direction and a position of the second partial region in the first direction, at least a portion of the third partial region being between the first electrode and the first electrode region in the first direction, the fourth partial region being separated from the second electrode region in the third direction, the fifth partial region being between the second partial region and the fourth partial region;
a second semiconductor region of a second conductivity type, the second semiconductor region including a sixth partial region, a seventh partial region, an eighth partial region, and a ninth partial region, the sixth partial region being positioned between the second partial region and the first electrode region in the third direction, a portion of the seventh partial region being positioned between the first electrode region and the at least a portion of the third partial region in the first direction, the eighth partial region being positioned between the fourth partial region and the second electrode region in the third direction, at least a portion of the ninth partial region being positioned between the first electrode region and the second electrode region in the second direction;
a third semiconductor region of the second conductivity type, the third semiconductor region being connected to the second semiconductor region, the third semiconductor region being positioned between the third electrode region and the at least a portion of the third partial region in the third direction, the third semiconductor region being positioned between the first electrode and another portion of the seventh partial region in the first direction;
a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being electrically connected to the second electrode, the fourth semiconductor region including a tenth partial region, an eleventh partial region, and a twelfth partial region, the tenth partial region being positioned between the third semiconductor region and a portion of the third electrode region in the third direction, the eleventh partial region being positioned between the seventh partial region and another portion of the third electrode region in the third direction, the twelfth partial region being positioned between the ninth partial region and the second electrode in the third direction; and
a first insulating film being provided between the first electrode and the first semiconductor region, between the first electrode and the third semiconductor region, and between the first electrode and the fourth semiconductor region.

US Pat. No. 10,249,716

IGBT ASSEMBLY HAVING SATURABLE INDUCTOR FOR SOFT LANDING A DIODE RECOVERY CURRENT

IXYS, LLC, Milpitas, CA ...

1. A method of manufacture comprising:depositing a volume of a liquid in an immediate vicinity of a conductor, wherein the liquid contains ferromagnetic particles, wherein the conductor is a part of an electronic device assembly;
causing the liquid to solidify so that the conductor and the solidified liquid together form a saturable inductor structure, wherein the saturable inductor structure has an unsaturated inductance of at least 200 nH, wherein the saturable inductor structure has a saturated inductance that is smaller than the unsaturated inductance, and wherein the solidified liquid holds the ferromagnetic particles in place with respect to the conductor; andassembling the saturable inductor structure, a diode and an insulated-gate bipolar transistor (IGBT) such that the diode and the saturable inductor structure are coupled in series between an emitter of the IGBT and a collector of the IGBT.

US Pat. No. 10,249,714

METHOD OF FORMING EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device comprising:forming a fin structure from a semiconductor substrate, wherein an upper surface of the fin structure is provided by an upper surface of the semiconductor substrate and a length of a sidewall of the fin structure extends from the upper surface of the fin structure to a recessed surface of the semiconductor substrate present at a base of the fin structure;
forming a lightly doped semiconductor material on the fin structure, wherein a portion of the lightly doped semiconductor material is formed on a recessed surface of a semiconductor substrate that is present at the base of the fin structure wherein a dopant concentration in the lightly doped semiconductor material ranges from 1×1019 to 5×1019; and
epitaxially growing a doped semiconductor material on the lightly doped semiconductor material, the doped semiconductor material having a greater dopant concentration than the lightly doped semiconductor material.

US Pat. No. 10,249,713

SEMICONDUCTOR DEVICE INCLUDING AN ESD PROTECTION ELEMENT

ABLIC Inc., (JP)

1. A semiconductor device including an ESD protection element,the semiconductor device comprising an element in an internal circuit region and having an operating voltage,
the ESD protection element comprising an N-type MOS transistor provided on one of a P well and a P-type semiconductor substrate,
the N-type MOS transistor including a gate electrode connected to one of the P well and the P-type semiconductor substrate such that the gate electrode has one of a well potential that is a potential of the P well and a ground potential that is a potential of the P-type semiconductor substrate,
the N-type MOS transistor having a drain active region in which an N-type high-concentration drain region and a P-type drain region are adjacent to each other to form a PN junction,
the P-type drain region having a potential that comprises one of the potential of the P well and the potential of the P-type semiconductor substrate,
the P-type drain region being adjacent to an end portion of the drain active region in a W direction, and another P-type drain region being provided in a region away from the end portion in the W direction, and
the ESD protection element having a withstand voltage that comprises a junction withstand voltage of the PN junction in the drain active region.

US Pat. No. 10,249,712

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate doped with impurities;
a front surface-side electrode provided on a front surface side of the semiconductor substrate; and
a back surface-side electrode provided on a back surface side of the semiconductor substrate; wherein
the semiconductor substrate has:
a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration;
a high concentration region arranged closer to a front surface than the peak region and having a gentler distribution of the impurity concentration than the one or more peaks; and
a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region,
wherein the impurity concentration at a boundary between the peak region and the high concentration region is higher than the impurity concentration in the low concentration region,
the high concentration region is adjacent to a front surface side of the peak region, and the low concentration region is adjacent to a front surface side of the high concentration region, and
the peak region, the high concentration region, and the low concentration region form a contiguous region of the semiconductor device in a depth direction.

US Pat. No. 10,249,711

FET WITH MICRO-SCALE DEVICE ARRAY

1. A field-effect transistor (FET), comprising:a substrate comprising a crystal structure on which an epitaxial active channel area has been grown;
a plurality of micro-cells uniformly distributed over said active channel area, each of said micro-cells comprising:
a source electrode;
a drain electrode; and
at least one gate electrode;
wherein one of said source or drain electrodes is at the center of said micro-cell and the other of said source or drain electrodes is along the perimeter of said micro-cell, said at least one gate electrode aligned parallel to one of the crystal planes of said substrate comprising a crystal structure;
said micro-cell arranged such that there are not gate electrodes aligned parallel to at least some of said crystal planes such that at least some of the regions around the electrode at the center of said micro-cell are electrically isolated; and
a multi-layer interconnection arrangement, wherein a first metal layer interconnects one of said drain or source electrodes, a second metal layer interconnects said gate electrodes, and a third metal layer interconnects the other of said drain or source electrodes.

US Pat. No. 10,249,709

STACKED NANOSHEET FIELD EFFECT TRANSISTOR DEVICE WITH SUBSTRATE ISOLATION

International Business Ma...

1. A semiconductor device, comprising:a nanosheet stack structure formed on a semiconductor substrate, wherein the nanosheet stack structure comprises a rare earth oxide (REO) layer formed on the semiconductor substrate, and a semiconductor channel layer disposed adjacent to the REO layer;
a metal gate structure formed over the nanosheet stack structure;
a gate insulating spacer disposed on vertical sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer; and
a first source/drain region and a second source/drain region formed in contact with a respective one of the end portions of the semiconductor channel layer exposed through the gate insulating spacer;
wherein a portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the semiconductor substrate;
wherein the first and second source/drain regions comprise an epitaxial semiconductor material that is epitaxially grown on the end portions of the semiconductor channel layer, and wherein the first and second source/drain regions are formed in contact with portions of the REO layer which extend past the gate insulating spacer such that the REO layer isolates the first and second source/drain regions from the semiconductor substrate.

US Pat. No. 10,249,708

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device having a lateral insulated gate field effect transistor portion, comprising:a semiconductor substrate having a main surface and an insulating layer formed on said main surface;
a semiconductor layer formed on said insulating layer;
a trench formed to penetrate, in order, the semiconductor layer and the insulating layer, and to reach the semiconductor substrate;
a gate electrode of said insulated gate field effect transistor portion embedded within said trench;
a first impurity region of a first conductivity type, which has first and second portions separated from each other along said trench, in said semiconductor layer, and serves as a source or an emitter;
a second impurity region, which is arranged in said semiconductor layer on a side of the first impurity region opposite to said trench, and serves as a drain of the first conductivity type or a collector of a second conductivity type; and
a back gate region of the second conductivity type, which is arranged in said semiconductor layer between said first and second portions of said first impurity region, and between the second impurity region and said first and second portions of said first impurity region.

US Pat. No. 10,249,707

LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

CSMC TECHNOLOGIES FAB2 CO...

1. A laterally diffused metal oxide semiconductor field-effect transistor, comprising:a substrate;
a source;
a drain;
a body region; and
a well region on the substrate,
wherein the well region comprises:
an inserting type well having a P-doping type, wherein the inserting type well is disposed below the drain and is in contact with the drain;
an N well disposed on both sides of the inserting type well; and
a P well disposed adjacent to the N well and in contact with the N well,
wherein the source and the body region are disposed in the P well,
the inserting type well is in direct contact with the substrate,
the N well is in direct contact with the substrate,
the P well is in direct contact with the substrate, and
wherein the well region comprises a first well region on the substrate and a second well region on the first well region; the inserting type well comprises a first inserting type well in the first well region and a second inserting type well in the second well region; the N well comprises a first N well in the first well region and a second N well in the second well region; the P well comprises a first P well in the first well region and a second P well in the second well region.

US Pat. No. 10,249,704

CAPACITOR

MURATA MANUFACTURING CO.,...

1. A capacitor comprising:a conductive porous base material with a porous part having a plurality of pores;
an upper electrode opposite the porous part, the upper electrode comprising, as a main constituent thereof, a material selected from the group consisting of ruthenium, platinum, and an alloy of ruthenium and platinum; and
a dielectric layer between the upper electrode and the conductive porous base material,
wherein the upper electrode and the dielectric layer extend into the plurality of pores of the porous part.

US Pat. No. 10,249,702

METAL RESISTORS HAVING VARYING RESISTIVITY

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing a dielectric-containing substrate comprising at least an interconnect dielectric material layer;
performing a first nitridation process to provide a first nitridized dielectric surface layer having a first nitrogen content in a first region of the dielectric-containing substrate and within a portion of the interconnect dielectric material layer;
performing a second nitridation process to provide a second nitridized dielectric surface layer having a second nitrogen content that differs from the first nitrogen content in a second region of the dielectric-containing substrate and within another portion of the interconnect dielectric material layer;
forming a metal layer on the first nitridized dielectric surface layer and the second nitridized dielectric surface layer;
forming a dielectric capping layer on the metal layer; and
patterning the dielectric capping layer, the metal layer, the first nitridized dielectric surface layer and the second nitridized dielectric surface layer to provide a first metal resistor structure spaced apart from a second metal resistor structure.

US Pat. No. 10,249,701

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a display region comprising a plurality of pixels each including a transistor, an insulating film above the transistor, a pixel electrode arranged above the insulating film and electrically connected to the transistor, and a common electrode above the insulating film; and
a peripheral region outside of the display region, the peripheral region including:
a plurality of first terminals arranged in a first direction;
a second terminal;
a third terminal; and
a first wiring connected to the second terminal and the third terminal,
wherein the first terminals are located between the second terminal and the third terminal in the first direction, and
the first wiring has a first part extending in the first direction between the display region and the first terminals, a second part connecting to the second terminal and the first part, and a third part connecting to the third terminal and the first part.

US Pat. No. 10,249,700

OLED ARRAY SUBSTRATE, DISPLAY APPARATUS AND METHOD FOR REPAIRING DARK SPOT THEREON

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode (OLED) array substrate, comprising:a base substrate;
a power line and a connection component both disposed on the base substrate;
a pixel structure disposed in a pixel region, wherein the pixel structure comprises a driving transistor and an OLED device;
wherein the driving transistor comprises a gate electrode, a first source/drain electrode and a second source/drain electrode; the first source/drain electrode is connected with the OLED device; and the second source/drain electrode is connected to the power line;
the OLED device comprises a first electrode and a second electrode, and the first electrode is electrically connected with the first source/drain electrode of the driving transistor;
the connection component is configured to electrically insulate the first electrode from the power line before repairing the OLED array substrate; and
the connection component is further configured to electrically connect the first electrode with the power line in a case of repairing the OLED array substrate.

US Pat. No. 10,249,698

TRANSPARENT OLED DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A transparent OLED display panel, comprising: a plurality of display pixels arranged in an array, each of the plurality of display pixels comprising a display region and a transparent region sequentially arranged in a vertical direction, each display region comprising a first, a second, and a third sub-pixels sequentially arranged in a horizontal direction;wherein a horizontal scanning line and a horizontal first power supply line electrically connected to a row of the display pixels are provided corresponding to each row of the display pixels, a vertical second power supply line electrically connected to the horizontal first power supply line is provided corresponding to each column of the display pixels, a first data line electrically connected to the first sub-pixel is provided corresponding to each column of the first sub-pixel, a second data line electrically connected to the second sub-pixel is provided corresponding to each column of the second sub-pixel, a third data line electrically connected to the third sub-pixel is provided corresponding to each column of the third sub-pixel;
the horizontal first power supply line and the horizontal scanning line are located in a first metal layer, the first data line and the second data line are located in a second metal layer stacked above the first metal layer, an insulating layer is provided between the first metal layer and the second metal layer;
the vertical second power supply line comprises: a first extension portion and a first bridge portion, the first extension portion is located in the first metal layer, the first bridge portion is located in the second metal layer, the first bridge portion is electrically connected to the first extension portion through a first via hole in the insulating layer, and the vertical second power supply line is insulated from and cross the horizontal scanning line by the first bridge portion; the third data line comprising a second extension portion and a second bridge portion, the second extension portion is located in the first metal layer, the second bridge portion is located in the second metal layer, the second bridge portion is electrically connected to the second extension portion through a second via hole in the insulating layer, and the third data line is insulated from and cross the horizontal first power supply line by the second bridge portion and the horizontal scanning line; and
in the transparent region, the first data line is insulated and stacked to the vertical second power supply line, and the second data line is insulated and stacked to the third data line.

US Pat. No. 10,249,696

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate including a pixel region and a peripheral region;
a plurality of pixels provided in the pixel region of the substrate;
a scan line and a data line spaced apart and intersecting each other;
a transistor provided in the pixel region, the transistor including a first transistor connected to the scan line and the data line and a second transistor connected to the first transistor;
a light emitting element connected to the transistor;
a first blocking layer disposed between the substrate and the first transistor, the first blocking layer being electrically connected to the first transistor; and
a second blocking layer disposed between the substrate and the second transistor, the second blocking layer being electrically connected to the second transistor,
wherein the first blocking layer is connected to a gate electrode of the first transistor, and the second blocking layer is connected to any one of source and drain electrodes of the second transistor.

US Pat. No. 10,249,695

DISPLAYS WITH SILICON AND SEMICONDUCTING-OXIDE TOP-GATE THIN-FILM TRANSISTORS

Apple Inc., Cupertino, C...

1. A display comprising:a semiconducting-oxide drive transistor, wherein the semiconducting-oxide drive transistor is a top-gate transistor;
a storage capacitor coupled to the drive transistor, wherein the storage capacitor comprises conductive oxide, and wherein the storage capacitor is formed in the same layer in the display as the semiconducting-oxide drive transistor;
a silicon switching transistor coupled to the semiconducting-oxide drive transistor, wherein the silicon switching transistor is formed on a substrate, and wherein the semiconducting-oxide drive transistor is formed above the silicon switching transistor;
an organic layer formed on the semiconducting-oxide drive transistor;
a metal layer laterally coupling a source-drain terminal of the semiconducting-oxide drive transistor to a source-drain terminal of the silicon switching transistor, wherein the metal layer is not formed through the organic layer; and
a conductive structure electrically coupled to a gate conductor of the top-gate transistor, wherein the conductive structure is not formed through the organic layer.

US Pat. No. 10,249,693

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a substrate;
an organic light-emitting device on the substrate;
a sealing member on the organic light-emitting device;
a phase retardation layer on a surface of the organic light emitting device; and
a linear polarization layer on another surface of the organic light-emitting device,
wherein the linear polarization layer is located to be closer to a source of external light than the phase retardation layer, and
wherein the linear polarization layer comprises a photochromic material.

US Pat. No. 10,249,688

ORGANIC LIGHT EMITTING DISPLAY DEVICE WITH BANK STRUCTURE FOR ENHANCED IMAGE QUALITY AND HEAD MOUNTED DISPLAY INCLUDING THE SAME

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:two adjacent pixels including two adjacent anode electrodes, respectively;
an organic light-emitting layer disposed on the two adjacent anode electrodes; and
red, green, and blue color filters disposed on the organic light-emitting layer,
wherein a bank is disposed between the two adjacent anode electrodes of the two adjacent pixels, and separates the two adjacent anode electrodes from each other,
wherein the bank includes at least one color changing material that changes light emitted from the organic light-emitting layer into a predetermined color corresponding to one of the red, green, and blue color filters disposed on the organic light-emitting layer and outputs the changed color light,
wherein the organic light-emitting layer is disposed between the bank and the red, green, and blue color filters.

US Pat. No. 10,249,685

HIGH RESOLUTION LOW POWER CONSUMPTION OLED DISPLAY WITH EXTENDED LIFETIME

Universal Display Corpora...

1. A full-color pixel arrangement for an OLED device, the full-color pixel arrangement comprising:a first sub-pixel comprising an emissive region of a first color and having a first optical path length;
a second sub-pixel comprising an emissive region of the first color, the second sub-pixel having a second optical path length different than the first optical path length;
a third sub-pixel comprising an emissive region of a second color;wherein the full-color pixel arrangement comprises emissive regions of exactly two different colors.

US Pat. No. 10,249,684

RESISTIVE CHANGE ELEMENTS INCORPORATING CARBON BASED DIODE SELECT DEVICES

Nantero, Inc., Woburn, M...

1. A resistive change memory element, comprising:a non-volatile resistive block switch, wherein said non-volatile resistive block switch comprises:
a first metal layer; and
a switch carbon layer in electrical contact with said first metal layer; and
a diode in a series connection with said non-volatile resistive block switch, wherein said diode comprises:
a conductive layer;
a semiconducting carbon layer in electrical contact with said conductive layer, wherein said conductive layer and said semiconducting carbon layer are configured to create a conductive path when sufficient voltage is applied; and
an intervening material layer placed between said conductive layer and said semiconducting carbon layer.

US Pat. No. 10,249,683

THREE-DIMENSIONAL PHASE CHANGE MEMORY ARRAYS AND METHODS OF MANUFACTURING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A phase change memory device containing a phase change memory material layer, the device comprising:a vertically repeating sequence of unit layer stacks located over a substrate, wherein each of the unit layer stacks comprises an insulating layer, at least one of the phase change memory material layer or a threshold switch material layer, and an electrically conductive word line layer;
a plurality of openings vertically extending through the vertically repeating sequence;
a plurality of vertical bit lines located within a respective one of the plurality of openings; and
vertical stacks of insulating spacers, wherein each of the insulating spacers laterally surrounds a respective one of the plurality of vertical bit lines, and contacts a sidewall of a respective one of the electrically conductive word line layers;
wherein the phase change memory device further comprises at least one feature selected from:
(i) a first feature in which the threshold switch material layer is located within one of the plurality of openings, contacts the vertical stack of insulating spacers and the phase change memory material layer in each unit layer stack, and laterally encloses a respective one of the plurality of vertical bit lines; and
each unit layer stack contains the phase change memory material layer which contacts a horizontal surface of the respective insulating layer and a horizontal surface of a conductive material layer within the unit layer stack; or
(ii) a second feature in which the phase change memory material layer is located within one of the plurality of openings, contacts the vertical stack of insulating spacers and the threshold switch material layer in each unit layer stack, and laterally encloses a respective one of the plurality of vertical bit lines; and
each unit layer stack contains the threshold switch material layer which contacts a horizontal surface of the respective insulating layer and a horizontal surface of the conductive material layer within the unit layer stack; or
(iii) a third feature in which the plurality of openings comprises line trenches that laterally extend along a horizontal direction;
the insulating spacers comprise insulating rail structures that laterally extend along the horizontal direction; and
the phase change memory device further comprises dielectric pillar structures located between each neighboring pair of vertical bit lines among the plurality of vertical bit lines that are laterally spaced along the horizontal direction; or
(iv) a fourth feature in which the threshold switch material layer comprises an ovonic threshold switch material layer; and
the plurality of openings comprise a plurality of discrete openings arranged as a two-dimensional array in the vertically repeating sequence of unit layer stacks.

US Pat. No. 10,249,680

THERMAL MANAGEMENT OF SELECTOR

WESTERN DIGITAL TECHNOLOG...

1. A memory device, comprising:a word line;
a bit line disposed perpendicular to the word line; and
a stack disposed between the word line and the bit line, wherein the stack comprises:
a memory element;
a selector having a plurality of sides, wherein the selector comprises alternating layers of selector elements and heat sinks;
a spacer layer disposed between the memory element and the selector;
a first insulating layer disposed between the word line and the bit line;
a second insulating layer disposed in direct contact with the first insulating layer; and
a dissipation layer disposed in direct contact with the first insulating layer;
wherein the dissipation layer is adjacent to the second insulating layer and a same width as the second insulating layer.

US Pat. No. 10,249,678

IMAGING DEVICE, METHOD OF DRIVING IMAGING DEVICE, AND IMAGING SYSTEM

CANON KABUSHIKI KAISHA, ...

1. An imaging device comprising:a plurality of pixels, each of the plurality of pixels including a photoelectric converter that generates charges by photoelectric conversion, a holding portion that holds the charges transferred from the photoelectric converter, and an amplifier unit that outputs a signal based on the charges transferred from the holding portion; and
an output line which is connected to the plurality of pixels and to which signals are output from the plurality of pixels,
wherein each of the plurality of pixels is configured to output a signal based on charges generated by the photoelectric converter during an exposure period, the exposure period including
a first period during which the photoelectric converter holds charges generated by the photoelectric converter in the first period and
a second period during which the photoelectric converter or the holding portion holds charges generated by the photoelectric converter in the second period while the holding portion is holding charges generated in the first period, and
wherein each of the plurality of pixels is further configured to reset the holding portion after outputting a signal based on charges held in the holding portion in the first period and before transferring charges generated in the first period from the photoelectric converter to the holding portion.

US Pat. No. 10,249,677

PIXEL HAVING TWO SEMICONDUCTOR LAYERS, IMAGE SENSOR INCLUDING THE PIXEL, AND IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. An image sensor comprising:a first semiconductor layer having at least one transistor;
a first interlayer insulating layer, disposed on the first semiconductor layer;
a second interlayer insulating layer disposed on the first interlayer insulating layer;
a second semiconductor layer having a photodiode that includes an T-type region and a P-type region, the second semiconductor layer being disposed on the second interlayer insulating layer;
a first conductive plug that penetrates the first interlayer insulating layer and is electrically connected to the first semiconductor layer;
a second conductive plug that penetrates the second interlayer insulating layer and is electrically connected to the second semiconductor layer; and
a conductive pattern between the first and second semiconductor layers,
wherein the first semiconductor layer is electrically connected to the second semiconductor layer by the first conductive plug, the second conductive plug, and the conductive pattern,
wherein the second semiconductor layer further comprises a transfer transistor, and at least a portion of the transfer transistor overlaps the N-type region in a plan view,
wherein the second interlayer insulating layer is disposed between the first interlayer insulating layer and the second semiconductor layer, and is in contact with at least one surface of a gate of the transfer transistor.

US Pat. No. 10,249,674

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING A SEMICONDUCTOR DEVICE HAVING BONDED SENSOR AND LOGIC SUBSTRATES

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a sensor substrate including:
a first semiconductor substrate;
a first wiring layer formed at a first main surface side of the first semiconductor substrate;
an insulating material layer formed at a second main surface side of the first semiconductor substrate;
a conductive layer, wherein a portion of the conductive layer is formed on the insulating material layer and has an upper surface side that faces away from the second main surface side of the first semiconductor substrate, and wherein the upper surface side of the portion of the conductive layer includes a concave portion;
a first film formed on the portion of the conductive layer and covering an inner face of the concave portion; and
a second film formed on the first film, wherein at least a portion of the first film and the second film are within the concave portion; and
a logic substrate including:
a second semiconductor substrate; and
a second wiring layer formed at a first main surface side of the second semiconductor substrate,
wherein the sensor substrate and the logic substrate are bonded together such that the first wiring layer faces the second wiring layer, and
wherein the conductive layer electrically connects a first wiring in the first wiring layer and a second wiring in the second wiring layer.

US Pat. No. 10,249,671

LOW-NOISE CMOS IMAGE SENSOR

1. A CMOS image sensor comprising at least one pixel comprising:a photodiode having a first terminal connected to a node of application of a first reference potential;
a first MOS transistor connecting a second terminal of the photodiode to a sense node of the pixel;
a second MOS transistor connecting the sense node to a node of application of a second reference potential; and
a third MOS transistor assembled as a source follower having its gate connected to the sense node and having its source intended to be connected to a readout circuit,
the first, second, and third transistors having a same gate insulator thickness,
wherein the third transistor has a gate length smaller than the gate lengths of the first and second transistors and/or a gate width smaller than the gate widths of the first and second transistors, wherein the difference between the first and second reference potentials is greater than the maximum voltage which may be applied between two terminals of the third MOS transistor, and wherein the body region or the drain region of the third transistor is connected to a node of application of a third reference potential between the first and second potentials,
the sensor being formed with a technological process enabling to form on a same chip MOS transistors having a first gate insulator thickness and MOS transistors having a second gate insulator thickness greater than the first thickness, wherein the first, second, and third transistors have the second gate insulator thickness.

US Pat. No. 10,249,670

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS WITH MULTIPLE LAYERS OF SIGNAL LINES AND INTERCONNECT LINES

Sony Corporation, Tokyo ...

1. A solid-state imaging device comprising:a pixel chip that generates pixel signals; and
a logic chip stacked on the pixel chip,
wherein the logic chip processes the pixel signals from the pixel chip,
wherein, in the pixel chip, first interconnect lines are laid out in a layer above vertical signal lines, the first interconnect lines being other than the vertical signal lines,
wherein the vertical signal lines are laid out in at least two layers including a first layer and a second layer,
wherein, in the pixel chip, second interconnect lines are laid out in a layer below vertical signal lines in the second layer that is below the first layer, the second interconnect lines being other than the vertical signal lines,
wherein at least one of the first interconnect lines overlaps at least one of the vertical signal lines in the first layer in a plan view,
wherein the vertical signal lines transmit the pixel signals to a column processing circuit,
wherein the first interconnect lines are control lines, ground lines, or power supply lines,
wherein the second interconnect lines are ground lines or power supply lines,
wherein the pixel chip further comprises:
a first interlayer insulating film between the first interconnect lines and the first layer of the vertical signal lines; and
a second interlayer insulating film between the first layer of the vertical signal lines and the second layer of the vertical signal lines,
wherein the first layer of the vertical signal lines is closer to the logic chip than the second layer of the vertical signal lines, and
wherein a permittivity of the second interlayer insulating film is lower than a permittivity of the first interlayer insulating film.

US Pat. No. 10,249,668

X-RAY SENSOR, X-RAY DETECTOR SYSTEM AND X-RAY IMAGING SYSTEM

PRISMATIC SENSORS AB, St...

1. An x-ray sensor comprising:an active detector region including a plurality of detector diodes at a first side of the sensor; and
a common junction termination at a second opposite side of the sensor,
wherein the first side corresponds to an anode side of the sensor and the second side with the junction termination corresponds to a cathode side of the sensor, or
wherein the first side corresponds to a cathode side of the sensor and the second side with the junction termination corresponds to an anode side of the sensor.

US Pat. No. 10,249,667

IMAGE SENSOR AND MANUFACTURING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. An image sensor comprising:a semiconductor layer having a first surface and a second surface opposite to the first surface;
a plurality of light sensing regions formed in the semiconductor layer and comprising a plurality of general pixels configured to obtain image information and a plurality of phase detection autofocusing pixels configured to detect phase;
a pixel isolation layer disposed between adjacent light sensing regions from among the plurality of light sensing regions;
a first light shielding layer formed on the second surface of the semiconductor layer and at least partially overlapping a first phase detection autofocusing pixel of the plurality of phase detection autofocusing pixels;
a second light shield layer formed on the second surface of the semiconductor layer and at least partially overlapping a second phase detection autofocusing pixel of the plurality of phase detection autofocusing pixels; and
a wiring layer formed on the first surface of the semiconductor layer,
wherein the first light shielding layer overlaps a left section of the first phase detection autofocusing pixel and the second light shielding layer overlaps a right section of the second phase detection autofocusing pixel in a plan view.

US Pat. No. 10,249,666

IMAGE SENSORS INCLUDING SHIFTED ISOLATION STRUCTURES

Samsung Electronics Co., ...

1. An image sensor comprising:a semiconductor substrate including a first pixel region and a second pixel region;
a first isolation structure in the semiconductor substrate to define the first and second pixel regions;
a first photoelectric conversion element and a second photoelectric conversion element in each of the first and second pixel regions;
a second isolation structure between the first and second photoelectric conversion elements in the first pixel region; and
an isolation dopant region between the first and second photoelectric conversion elements in the second pixel region,
wherein a center of the second isolation structure is shifted relative to a center of the first pixel region when viewed in plan view,
wherein the first pixel region is one of a plurality of first pixel regions and the second pixel region is one of a plurality of second pixel regions, and
wherein the first pixel regions and the second pixel regions are alternately arranged along a first direction.

US Pat. No. 10,249,665

SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE

Sony Corporation, Tokyo ...

1. A solid-state image pickup device comprising:an insulating layer between a first semiconductor substrate and a second semiconductor substrate, the second semiconductor substrate is between an electrode layer and the insulating layer;
an adhesive layer between the insulating layer and the first semiconductor substrate;
an electrically-insulative planarized layer between an on-chip lens and a light-receiving sensor portion of the second semiconductor substrate, the second semiconductor substrate is between the insulating layer and the planarized layer;
an electrically-insulative alignment mark between the planarized layer and the insulating layer, the insulating layer and the planarized layer touch the alignment mark; and
a metal layer between the electrode layer and the insulating layer, the insulating layer and the electrode layer touch the metal layer.

US Pat. No. 10,249,664

OPTICAL GLASS

AGC Inc., Chiyoda-ku (JP...

1. An optical glass, comprising:a glass substrate having a plate-shape comprising a first principal surface adapted to be bonded to a casing, a second principal surface being the opposite to the first principal surface and an end surface; and
a reformed region formed on the end surface at a closer position to the second principal surface than the first principal surface, made by light radiated to be focused thereto,
wherein the reformed region satisfies the expression:
0.02t<(a?b)/2<0.3t
where
a is a distance between the first principal surface and the reformed region in a plate thickness direction of the glass substrate,
b is a distance between the second principal surface and the reformed region in the plate thickness direction,
t is a plate thickness of the optical glass, and
a and b are numerical values greater than 0.

US Pat. No. 10,249,663

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND CAMERA WITH ARRANGED PIXEL COMBINATIONS ALTERNATIVELY

Sony Semiconductor Soluti...

1. A solid-state imaging device comprising:a semiconductor substrate including:
first to fourth photodiodes arranged in order from the first photodiode to the second photodiode to the third photodiode to the fourth photodiode along a first direction;
a first separation region disposed between the first photodiode and the second photodiode;
a second separation region disposed between the second photodiode and the third photodiode; and
a third separation region disposed between the third photodiode and the fourth photodiode;
a first metal disposed above the second photodiode;
a second metal disposed above the fourth photodiode;
a first color filter disposed above the first photodiode;
a second color filter disposed above the second photodiode;
a third color filter disposed above the third photodiode;
a fourth color filter disposed above the fourth photodiode;
a first on-chip lens disposed above the first color filter and configured to focus incident light on the first photodiode;
a second on-chip lens disposed above the second and third color filter and configured to focus incident light on the second and third photodiode; and
a third on-chip lens disposed above the fourth color filter and configured to focus incident light on the fourth photodiode,
wherein the second color filter and the third color filter are configured to transmit incident light with a same wavelength range.

US Pat. No. 10,249,662

MULTISPECTRAL IMAGING DEVICE AND MANUFACTURING METHOD THEREOF

1. A multispectral imaging device, comprising the following layers and components arranged along a direction of incident light:a color filter layer, comprising an array of color filters transparent selectively to specific wavebands;
a first transparent electrode layer, transparent for visible light and NIR light;
a first conversion layer, to convert visible light to electric signals, formed by an a-SiH layer lightly doped of P type;
a first continuous surface, formed by a second transparent electrode layer and a first insulating film, wherein said second transparent electrode layer comprising a plurality of pixel electrodes, collecting the electric signals of visible light and transparent for NIR light, said first insulating film arranged between said pixel electrodes, said first conversion layer arranged between said first transparent electrode layer and said first continuous surface and covering said first continuous surface continuously;
a second conversion layer, to convert NIR light to electric signals; and
circuit components, to respectively process the electric signals from said first conversion layer and said second conversion layer.

US Pat. No. 10,249,660

SPLIT-GATE CONDITIONAL-RESET IMAGE SENSOR

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit image sensor, comprising a pixel array having:a first photodetector formed within a substrate;
a floating diffusion formed within the substrate;
first and second gate elements disposed adjacent one another over a first charge transfer region of the substrate between the first photodetector and the floating diffusion, the first and second gate elements respectively controlling first and second serial sections of the first charge transfer region;
a first row line extending in a row direction within the pixel array and coupled to the first gate element;
a first column line extending in a column direction within the pixel array and coupled to the second gate element; and
circuitry to detect a level of photocharge integrated within the first photodetector and to conditionally assert a control pulse on the first column line according to whether the level of photocharge exceeds a threshold.

US Pat. No. 10,249,659

SOLID-STATE IMAGE PICKUP DEVICE

Sony Corporation, Tokyo ...

1. A solid-state image pickup device comprising:a semiconductor substrate having a first surface; and
a plurality of unit pixels,
wherein a first unit pixel in the plurality of unit pixels comprises:
a first transistor having a gate electrode including a part embedded in the semiconductor substrate from the first surface, and
a photodiode in the semiconductor substrate, and
wherein a second unit pixel in the plurality of unit pixels comprises:
a second transistor at the first surface, and
a pixel separation region disposed between the first transistor and the second transistor,
wherein the photodiode is disposed under the gate electrode and the pixel separation region.

US Pat. No. 10,249,658

IMAGING DEVICE COMPRISING A CIRCUIT HAVING DUAL REGIONS EACH WITH A TRANSISTOR ELECTRICALLY CONNECTED TO A PHOTOELECTRIC CONVERSION ELEMENT

Semiconductor Energy Labo...

1. An imaging device comprising:a circuit comprising a first region and a second region;
a first transistor over the first region;
a first photoelectric conversion element over the first transistor, the first photoelectric conversion element comprising a first photoelectric conversion layer;
a second transistor over the second region; and
a second photoelectric conversion element over the second transistor, the second photoelectric conversion element comprising the first photoelectric conversion layer,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor in a channel formation region,
wherein the first transistor is electrically connected to the first photoelectric conversion element, and
wherein the second transistor is electrically connected to the second photoelectric conversion element.

US Pat. No. 10,249,652

MANUFACTURING METHOD OF FLEXIBLE TFT SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of flexible TFT substrate, comprising the steps of:Step S1: providing a flexible base substrate, depositing a buffer layer on the flexible base substrate, depositing and patternizing to form an active layer on the buffer layer, depositing a gate insulating layer on the active layer and the buffer layer, depositing and patternizing to form a gate on the gate insulating layer;
Step S2: depositing a silicon oxide layer on the gate and the gate insulating layer, patternizing the silicon oxide layer and the gate insulating layer to form a first contact hole respectively to corresponding to above of each of two sides of the active layer and form a buffer hole above the base substrate with an interval from the first contact hole, the first contact hole penetrating the silicon oxide layer and the gate insulating layer to expose the two sides of the active layer, the buffer hole having a larger size than the first contact hole, and the buffer hole having a deeper depth than the first contact hole;
Step S3: coating an organic photo-resist material on the silicon oxide layer to form an organic photo-resist layer, the organic photo-resist material filling the buffer hole during coating, the silicon oxide layer and the organic photo-resist layer together forming an interlayer dielectric layer, patternizing the organic photo-resist layer to form connection holes above the first contact holes so as to expose the first contact holes;
Step S4: depositing and patternizing on the interlayer dielectric layer to form a source and a drain, the source and the drain contacting respectively the two sides of the active layer through the first contact holes and the connection holes.

US Pat. No. 10,249,651

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

2. A semiconductor device comprising:an insulating layer;
an oxide semiconductor film including a source region and a drain region over and in contact with the insulating layer;
a gate insulating film over the oxide semiconductor film; and
a gate electrode layer over the gate insulating film,
wherein the source region and the drain region include impurities,
wherein the oxide semiconductor film contains a crystal having a c-axis which is substantially perpendicular to a top surface of the oxide semiconductor film,
wherein an average surface roughness of a top surface of the insulating layer is greater than or equal to 0.05 nm and less than 0.5 nm, and
wherein the impurities are added into the source region and the drain region through the gate insulating film.

US Pat. No. 10,249,649

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A thin film transistor array substrate, comprising:a plurality of fan-out areas located in a non-display area of the thin film transistor array substrate, wherein a display area of the thin film transistor array substrate has a plurality of sub display areas corresponding to the fan-out areas respectively, and the sub display areas and the fan-out areas are arranged opposite each other;
a plurality of scanning lines extended along a first direction;
a plurality of data line combinations comprising a plurality of data lines extended along a second direction, wherein the first direction and the second direction are orthogonal to each other;
a plurality of common line combinations comprising a plurality of common lines crossing with the data lines, wherein a parasitic capacitor is formed on an overlapping area of the common line and the data line; and
a plurality of connecting line combinations, each of which is located in one of the fan-out areas, wherein the connecting line combinations comprise a plurality of connecting lines connecting to the data lines;
wherein a capacitance value of the parasitic capacitor formed from the data line connected to the connecting line with a larger resistance value and the corresponding common line is less than that of the parasitic capacitor formed from the data line connected to the connecting line with a smaller resistance value and the corresponding common line;
wherein the resistance value of the connecting line is gradually increased from an intermediate area of the fan-out area to two sides of the fan-out area;
wherein the connecting line located in the intermediate area of the fan-out area connects to the data line located in an intermediate area of the sub display area, and the connecting line located at the two sides of the fan-out area connects to the data line located at the two sides of the sub display area;
wherein a capacitance value of the parasitic capacitors formed from the data line combination and the common line combination are reduced from the intermediate area of the sub display area to the two sides of the sub display area;
wherein the common line comprises:
a first sub line being parallel to the data line; and
at least one second sub line being parallel to the scanning line;
wherein the second sub line and the scanning line are formed from a first metal layer, the first sub line and the data line are formed from a second metal layer, the first sub line and the second sub line are connected by a through hole, and the through hole is disposed through an insulating layer between the scanning line and the data line; and
wherein the parasitic capacitor is formed from the data line and the second sub line of the common line.

US Pat. No. 10,249,648

MANUFACTURING METHODS OF ARRAY SUBSTRATES AND ARRAY SUBSTRATES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, comprising:forming a buffer layer on a substrate, and patterning the buffer layer to form trenches defined within the patterned buffer layer;
forming a conductive layer on the patterned buffer layer and the trenches, and patterning the conductive layer such that portions of the patterned conductive layer within the trenches are used as a data line and a source respectively, and portions of the patterned conductive layer on the patterned buffer layer are used as a gate and a gate line respectively;
forming an insulation layer on the source, the data line, the gate, and the gate line, wherein at least one portion of the source and at least one portion of the gate line are exposed by the insulation layer;
forming a semiconductor layer on the source, wherein the semiconductor layer is electrically connected to the exposed portion of the source, and the semiconductor layer and the gate are electrically insulated via the insulation layer; and
forming a first pixel electrode and a second pixel electrode on the insulation layer, wherein the first pixel electrode is electrically connected to the semiconductor layer, and the second pixel electrode is electrically connected to the exposed portion of the gate line,
wherein the gate comprises a first gate electrode and a second gate electrode, and the first gate electrode and the second gate electrode are configured to be located at two sides of the source and be parallel to the source.

US Pat. No. 10,249,647

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE COMPRISING OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode layer;
a gate insulating layer;
an oxide semiconductor layer comprising a channel formation region adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium; and
source and drain electrode layers in electrical contact with the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a crystalline region including a crystal with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, and
wherein a c-axis of the crystal is oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

US Pat. No. 10,249,646

DISPLAY DEVICE FABRICATED WITH FEWER MASKS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device, comprising:a base substrate comprising a first light blocking area extending in a first direction, a second light blocking area extending in a second direction intersecting the first direction, and a pixel area defined by the first light blocking area and the second light blocking area;
a light blocking pattern on the base substrate, at least a portion of the light blocking pattern positioned at the first light blocking area;
a data line on the base substrate and positioned at the second light blocking area;
a first insulating layer on the light blocking pattern and the data line;
a semiconductor layer on the first insulating layer, the semiconductor layer overlapping the light blocking pattern on a plane;
a second insulating layer on the semiconductor layer;
a color filter on the second insulating layer, the color filter having an island shape and at least a portion of the color filter positioned at the pixel area;
a third insulating layer on the second insulating layer and the color filter;
a gate line on the third insulating layer and positioned at the first light blocking area;
a pixel electrode on the third insulating layer, at least a portion of the pixel electrode positioned at the pixel area; and
a bridge electrode on the third insulating layer, at least a portion of the bridge electrode positioned at the first light blocking area,
wherein the second insulating layer and the third insulating layer directly contact one another over the semiconductor layer.

US Pat. No. 10,249,645

SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor comprising:
an oxide semiconductor layer over a first insulating film;
a second insulating film over the oxide semiconductor layer;
a gate electrode over the second insulating film;
a third insulating film over the gate electrode;
a source electrode over the third insulating film; and
a drain electrode over the third insulating film,
wherein the source electrode is electrically connected to the oxide semiconductor layer, and
wherein the drain electrode is electrically connected to the oxide semiconductor layer, and
a capacitor comprising:
a first conductive layer;
the third insulating film over the first conductive layer; and
a second conductive layer over the third insulating film,
wherein the first insulating film comprises silicon and oxygen,
wherein the oxide semiconductor layer comprises a first portion being a channel region, a second portion, and a third portion between the first portion and the second portion,
wherein the gate electrode overlaps with the first portion,
wherein a part of the third insulating film overlaps with the third portion,
wherein a resistivity of the third portion is higher than a resistivity of the second portion.

US Pat. No. 10,249,643

HARD COPIED SEMICONDUCTOR DEVICE HAVING A RESISTANCE-VARIABLE NON-VOLATILE ELEMENT

NEC CORPORATION, Minato-...

1. A semiconductor device hard-copied so as to have a same logical operation function as a reconfigurable circuit chip, comprising a resistance-variable non-volatile element formed inside a multi-layered wiring layer on a semiconductor substrate, the resistance-variable non-volatile element having an arbitrary logical operation function being programmed, wherein a lower wiring and an upper wiring planarly overlapping with each other are short-circuited at a portion where the resistance-variable non-volatile element of the reconfigurable circuit chip is programmed to a low-resistance state, and a lower wiring and an upper wiring planarly overlapping with each other are electrically insulated at a portion where the resistance-variable non-volatile element of the reconfigurable circuit chip is programmed to a high-resistance state.

US Pat. No. 10,249,642

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a substrate;
a stacked body that is provided on the substrate and includes a plurality of electrode layers separately from each other, each of the electrode layers extending in a first direction and in a second direction, the second direction intersecting the first direction, the electrode layers being stacked in a third direction, the third direction intersecting the first direction and the second direction; and
a plurality of pillar portions that are provided in the stacked body and extend in the third direction, the pillar portions collectively passing through each of the electrode layers,
wherein the pillar portions include a first column that are arranged along the first direction while being staggered, and a second column that are arranged along the first direction apart from the first column in the second direction while being staggered,
when viewed in the third direction,
a first virtual line is defined along the first direction, such that the first virtual line passes through each of the pillar portions of the first column, and
a second virtual line is defined along the first direction apart from the first virtual line in the second direction, such that the second virtual line passes through each of the pillar portions of the second column.

US Pat. No. 10,249,641

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a stacked body provided on a first-direction side of the substrate, the stacked body including first insulating films and electrode films, each of the first insulating films and each of the electrode films being stacked alternately along the first direction;
a semiconductor member extending in the first direction; and
a charge storage film provided between the stacked body and the semiconductor member,
a recess being made in a surface of the stacked body facing the semiconductor member every one of the electrode films,
wherein one of the first insulating films includes a protrusion at the surface of the stacked body facing the semiconductor member, the protrusion protruding toward the semiconductor member, and a thickness of the protrusion in the first direction becomes thinner toward a tip of the protrusion.

US Pat. No. 10,249,640

WITHIN-ARRAY THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor structure comprising:a memory-level assembly located over a substrate and including an alternating stack of insulating layers and composite layers, wherein the insulating layers and the composite layers alternate along a vertical direction that is perpendicular to a top surface of the substrate, wherein each of the composite layers comprises:
a respective electrically conductive layer; and
a respective spacer dielectric portion, wherein the respective electrically conductive layer and spacer dielectric portion are laterally adjoined to each other, and wherein each vertically neighboring pair of the spacer dielectric portions is vertically spaced apart from each other by a thickness of an intervening one of the insulating layers;
memory stack structures vertically extending through the alternating stack and each of the memory stack structures comprising:
a respective memory film; and
a respective vertical semiconductor layer that is laterally surrounded by the respective memory film; and
at least one through-memory-level via structure that vertically extends through each of the spacer dielectric portions and the insulating layers, wherein the at least one through-memory-level via structure extends below bottommost surfaces of the memory stack structures.

US Pat. No. 10,249,639

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a semiconductor substrate extending in a second direction and a third direction;
first and second memory columnar bodies disposed above the semiconductor substrate in a first direction and aligned in the second direction, the first direction intersecting the second and third directions, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction;
a bit line disposed above the first and second memory columnar bodies in the first direction;
a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line;
a first connecting portion disposed between the first memory columnar body and the first connecting line in the first direction and electrically coupled to the semiconductor layer of the first memory columnar body and the first connecting line; and
a second connecting portion disposed between the second memory columnar body and the first connecting line in the first direction and electrically coupled to the semiconductor layer of the second memory columnar body and the first connecting line, wherein
the first connecting line extends linearly in the second direction, and a center line widthwise of the first connecting line is in a position displaced in the third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies, and
a center of the first connecting portion is in a position displaced in the third direction from the center of the first memory columnar body.

US Pat. No. 10,249,638

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a memory region arranged in a semiconductor substrate; and
a capacitive element region arranged in the semiconductor substrate,
wherein memory cells in the memory region comprise:
a plurality of first protrusions formed by parts of the semiconductor substrate, each of the first protrusions protruding from a main surface of the semiconductor substrate in a first direction and having a width in a second direction, the first protrusions extending in a third direction that intersects the second direction and being arranged along the second direction;
a plurality of first gate electrodes, each of the first gate electrodes being arranged with a first gate insulating film interposed between the first protrusion and the first gate electrode, the first gate electrodes extending in the second direction and being arranged along the third direction;
a plurality of second gate electrodes, each of the second gate electrodes being arranged with a second gate insulating film interposed between the first protrusion and the second gate electrode, each of the second gate electrodes being adjacent to a side surface of each of the first gate electrodes via the second gate insulating film, the second gate electrodes extending in the second direction and being arranged along the third direction; and
a first semiconductor region and a second semiconductor region provided in the first protrusion so as to sandwich therebetween the first gate electrode and the second gate electrode that are adjacent to each other, via the second gate insulating film,
wherein a capacitive element in the capacitive element region comprises:
a plurality of second protrusions formed by parts of the semiconductor substrate, each of the second protrusions protruding from the main surface of the semiconductor substrate in the first direction and having a width in the second direction, the second protrusions extending in the third direction and being arranged along the second direction;
a plurality of first capacitor electrodes, each of the first capacitor electrodes being arranged with an insulating film interposed between the second protrusion and the first capacitor electrode, the first capacitor electrodes extending in the second direction and being arranged along the third direction; and
a plurality of second capacitor electrodes, each of the second capacitor electrodes being arranged with a capacitive insulating film interposed between the second protrusion and the second capacitor electrode, each of the second capacitor electrodes being adjacent to a side surface of each of the first capacitor electrodes via the capacitive insulating film, the second capacitor electrodes extending in the second direction and being arranged along the third direction,
wherein the first gate electrodes and the first capacitor electrodes are formed of a first conductive film,
wherein the second gate electrodes and the second capacitor electrodes are formed of a second conductive film, and
wherein a distance between the adjacent second protrusions is smaller than a distance between the adjacent first protrusions.

US Pat. No. 10,249,637

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

MIE FUJITSU SEMICONDUCTOR...

1. A manufacturing method of a semiconductor device comprising a first transistor, a second transistor, a third transistor, and a flash memory transistor on a semiconductor substrate, the manufacturing method comprising:forming an element isolation that demarcates each of regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
forming a well and a channel in each of the regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
forming a tunnel oxide layer and a charge-storage layer in the region of the flash memory transistor;
forming a first oxide film in each of the regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
removing the first oxide film in the regions of the first transistor and the second transistor;
forming a third oxide film by adding a first oxide layer between the first oxide film and the semiconductor substrate in the region of the third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidizing the semiconductor substrate;
removing the second oxide film in the region of the first transistor;
forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidizing the semiconductor substrate, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor;
forming a gate electrode in each of the regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
forming a sidewall film on sidewalls on both sides of the gate electrode; and
forming a source region and a drain region in the semiconductor substrate at side portions on both sides of the gate electrode.

US Pat. No. 10,249,636

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a vertical memory device, the method comprising:forming a support layer on a substrate;
alternately forming sacrificial layers and insulation layers on the support layer in a first direction perpendicular to an upper surface of the substrate;
forming a channel hole and a dummy channel hole through the support layer, the sacrificial layers and the insulation layers,
the dummy channel hole exposing the upper surface of the substrate;
removing a part of the support layer exposed by the channel hole and the dummy channel hole to enlarge lower portions of the channel hole and the dummy channel holes so that the channel hole and the dummy channel hole are in communication with each other, a remaining portion of the support layer forming a support pattern;
forming a channel filling the channel hole;
forming a dummy channel filling the dummy channel hole;
forming an opening through the support pattern, the insulation layers and the sacrificial layers to expose the upper surface of the substrate, the forming the opening through the support pattern including transforming the insulation layers and the sacrificial layers into insulation patterns and sacrificial patterns, respectively;
removing the sacrificial patterns to form a plurality of first gaps; and
forming gate electrodes to fill the first gaps, respectively.

US Pat. No. 10,249,635

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a substrate;
a first insulating layer provided on the substrate;
a conductive layer provided above the first insulating layer;
a first wiring layer extending in a first direction, the first wiring layer being provided in a layer above the conductive layer;
a second wiring layer being provided in the layer, the second wiring layer being arranged apart from the first wiring layer in a second direction crossing the first direction and extending in the first direction;
a third wiring layer being provided between the conductive layer and the first wiring layer, and extending in the first direction;
a fourth wiring layer being provided between the conductive layer and the second wiring layer, and extending in the first direction;
a first signal line extending in a third direction crossing the first and second directions to electrically contact with the conductive layer;
a second signal line being arranged apart from and adjacent to the first signal line in the second direction, the second signal line extending in the third direction to electrically contact with the conductive layer;
a first select transistor being provided to the first signal line, a gate electrode of the first select transistor being electrically connected to the first wiring layer;
a second select transistor being provided to the second signal line, a gate electrode of the second select transistor being electrically connected to the second signal line;
a second insulator provided between the first signal line and the second signal line;
a first contact being electrically connected to the first wiring layer, the first contact extending in the third direction;
a second contact being electrically connected to the second wiring layer, the second contact being provided apart from the first contact via the second insulating layer in the first direction, the second contact extending in the third direction;
a third contact being electrically connected to the third wiring layer, the third contact extending in the third direction; and
a fourth contact being electrically connected to the fourth wiring layer, the fourth contact being provided apart from the third contact via the second insulating layer in the first direction, the fourth contact extending in the third direction,
wherein the first contact is provided at a different location from the second contact in the second direction.

US Pat. No. 10,249,634

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a stack;
channel layers each comprising channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern disposed below the stack and coupling the channel patterns with the dummy channel patterns;
a bit line coupled with the channel patterns;
a well pick-up line coupled with the dummy channel patterns; and
an gap fill insulating layer comprising a base part disposed below the stack, first protrusions protruding from the base part and passing through the channel patterns, and second protrusions protruding from the base part and passing through the dummy channel patterns.

US Pat. No. 10,249,632

SIMPLE INTEGRATION OF NON-VOLATILE MEMORY AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

International Business Ma...

1. A method of forming a semiconductor structure comprising:providing a structure comprising a first gate cavity exposing a channel region of a first semiconductor material portion located in a first device region of a substrate, a second gate cavity exposing a channel region of a second semiconductor material portion located in a second device region of the substrate, and a third gate cavity exposing a channel region of a third semiconductor material portion located in a third device region of the substrate, wherein the first gate cavity, the second gate cavity and the third gate cavity are laterally surrounded by an interlevel dielectric (ILD) layer;
forming a first high-k dielectric layer along sidewalls and bottom surfaces of the first, the second and the third gate cavities and on a top surface of the ILD layer;
forming a capping material layer on the first high-k dielectric layer;
patterning the capping material layer and the first high-k dielectric layer to remove a portion of each of the capping material layer and the first high-k dielectric layer from the third device region, wherein the patterning provides a patterned capping material layer and a patterned first high-k dielectric layer covering the first device region and the second device region, and a portion of the ILD layer and the third gate cavity in the third device region are exposed;
forming a second high-k dielectric layer on the patterned capping material layer, the exposed portion of the ILD layer and along the sidewall and the bottom surface of the third gate cavity;
patterning the second high-k dielectric layer and the patterned capping material layer to remove a portion of each of the second high-k dielectric layer and the patterned capping material layer from the first device region, wherein the patterning provides a patterned second high-k dielectric layer covering the second device region and the third device region and a capping material portion solely in the second device region, and a portion of the patterned first high-k dielectric layer in the first device region is exposed; and
depositing a conductive material layer on the patterned first high-k dielectric layer and the patterned second high-k dielectric layer to completely fill the first, the second and the third gate cavities.

US Pat. No. 10,249,631

SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING METAL GATES

Silicon Storage Technolog...

1. A memory device, comprising:a silicon substrate having an upper surface, wherein:
the upper surface is planar in a memory cell area of the silicon substrate,
the upper surface includes an upwardly extending silicon fin in a logic device area of the silicon substrate, and
the silicon fin includes a pair of side surfaces extending up and terminating at a top surface;
a logic device in the logic device area, comprising:
spaced apart first source and first drain regions formed in the silicon substrate with a first channel region of the silicon substrate extending there between, wherein the first channel region extends along the top surface and the pair of side surfaces, and
a conductive logic gate disposed over and insulated from the top surface, and disposed laterally adjacent to and insulated from the pair of side surfaces;
a memory cell in the memory cell area, comprising:
spaced apart second source and second drain regions formed in the silicon substrate with a second channel region of the silicon substrate extending there between,
a conductive floating gate disposed over and insulated from a first portion of the second channel region that is adjacent the second source region,
a conductive word line gate disposed over and insulated from a second portion of the second channel region that is adjacent the second drain region,
a conductive control gate disposed over and insulated from the floating gate, and
a conductive erase gate disposed over and insulated from the second source region.

US Pat. No. 10,249,630

STRUCTURE FEATURING FERROELECTRIC CAPACITANCE IN INTERCONNECT LEVEL FOR STEEP SUB-THRESHOLD COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:forming a first functional gate stack on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack on a second body region of a second semiconductor material portion located in a second region of the substrate, wherein the first functional gate stack and the second functional gate stack are laterally surrounded by an interlevel dielectric (ILD) layer;
forming a contact level dielectric layer over the ILD layer, the first functional gate stack and the second functional gate stack;
forming a gate interconnect opening extending through the contact level dielectric layer, the gate interconnect opening exposing a portion of the first functional gate stack located outside the first semiconductor material portion and a portion of the second functional gate stack located outside the second semiconductor material portion; and
forming a ferroelectric gate interconnect structure in the gate interconnect opening, wherein the ferroelectric gate interconnect structure vertically contacts the portion of the first functional gate stack located outside the first semiconductor material portion and the portion of the second functional gate stack located outside the second semiconductor material portion.

US Pat. No. 10,249,627

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

15. A semiconductor device, comprising:a first interlayer insulating layer disposed on a substrate;
a second interlayer insulating layer on the first interlayer insulating layer;
a first support layer between the first interlayer insulating layer and the second interlayer insulating layer;
a second support layer on an upper surface of the second interlayer insulating layer;
a first electrode disposed on the substrate and spaced apart from the first and second interlayer insulating layers;
a contact structure disposed on the substrate and penetrating the first interlayer insulating layer, the first support layer, the second interlayer insulating layer and the second support layer;
a dielectric conformally covering the first electrode; and
a second electrode on the dielectric; and
a space between the first electrode and a side surface of the second interlayer insulating layer opposing the first electrode,
wherein a portion of the second electrode is disposed inside the space,
wherein a portion of the dielectric surrounds the second electrode inside the space and is in contact with the side surface of the second interlayer insulating layer, and
wherein the second support layer includes a first portion covering an upper surface of the second interlayer insulating layer and surrounding an upper side surface of the contact structure, and a second portion being disposed in a same plane as the first portion and contacting a portion of an upper side surface of the first electrode.

US Pat. No. 10,249,626

SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTILAYER WIRING LAYER

Semiconductor Energy Labo...

1. A semiconductor memory device comprising:a driver circuit; and
a memory cell over the driver circuit, the memory cell comprising:
a transistor; and
a capacitor over the transistor, the capacitor comprising:
a first layer comprising a first conductive material, the first layer electrically connected to one of a source and a drain of the transistor; and
a second layer over the first layer, the second layer comprising a second conductive material,
wherein the first layer has a concave shape,
wherein the first layer comprises a first portion and a second portion,
wherein the second layer comprises a portion,
wherein the portion of the second layer overlaps with the first portion of the first layer,
wherein a bottom surface of the portion of the second layer is below a top surface of the second portion of the first layer, and
wherein the memory cell is electrically connected to the driver circuit.

US Pat. No. 10,249,623

SEMICONDUCTOR INTEGRATED CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit comprising:a semiconductor substrate having a plurality of first potential side areas, the plurality of first potential side area including a first two adjacent first potential side areas, each first potential side area including:
a high potential side circuit;
a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate;
a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, the second semiconductor region penetrating the first semiconductor region in a depth direction from the front surface of the semiconductor substrate; and
a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region, a potential of the third semiconductor region being fixed at a potential higher than a potential of the second semiconductor region, the high potential side circuit being arranged to be closer to a center of the first semiconductor region than the third semiconductor region, wherein
the first two adjacent first potential side areas includes respective first side areas that face each other, that each include the third semiconductor region thereof, and that each are free of the second semiconductor region thereof.

US Pat. No. 10,249,622

EPITAXIAL OXIDE FIN SEGMENTS TO PREVENT STRAINED SEMICONDUCTOR FIN END RELAXATION

International Business Ma...

1. A semiconductor device comprising:a plurality of fin structures having a uniform strain extending from edge to edge of each fin structure in said plurality of fin structures;
an epitaxial oxide present in a gate cut opening present between edges of said plurality of fin structures, the epitaxial oxide having a composition comprising lanthanum and yttrium;
a gate structure present on a channel region of the fin structures having the uniform strain; and
source and drain regions formed on opposing sides of the channel region.

US Pat. No. 10,249,621

DUMMY CONTACTS TO MITIGATE PLASMA CHARGING DAMAGE TO GATE DIELECTRICS

TEXAS INSTRUMENTS INCORPO...

11. A metal-oxide-semiconductor (MOS) integrated circuit (IC), comprising:a substrate having a semiconductor surface;
a plurality of MOS transistors each including a source, a drain, and a gate stack on said semiconductor surface including a gate electrode over a gate dielectric on active areas defined by a field dielectric on said substrate;
a plurality of dummy gate stacks including first dummy gate stacks and second dummy gate stacks, each of said first and second dummy gate stacks including a dummy gate electrode over a dummy gate dielectric, said first dummy gate stacks disposed on dummy portions of said active area and said second dummy gate stacks disposed on a field oxide region of said field dielectric, wherein each of said second dummy gate stacks is disposed only on said field oxide region so as to be separated from said substrate;
a pre-metal dielectric (PMD) layer over said gate electrodes of said plurality of gate stacks and over said dummy gate electrodes of said first and second dummy gate stacks;
contact openings through said PMD layer including active contacts and dummy contacts, said active contacts and said dummy contacts both filled with a plug material;
a patterned metal 1 (M1) layer including first M1 portions over said active contacts and dummy M1 portions over said dummy contacts, and
at least one patterned metal upper level above said patterned M1 layer;
a plurality of vias including first vias that connect said at least one patterned metal upper level to said first M1 portions, and dummy vias that connect said at least one patterned metal upper level to said dummy M1 portions; and
interconnects that connect said active contacts to said MOS transistors, and wherein said dummy contacts are not electrically connected by said interconnects to said MOS transistors and land on said dummy portions of said active area between adjacent ones of said first dummy gate stacks, said dummy portions of said active areas lacking source/drain implants.

US Pat. No. 10,249,620

SEMICONDUCTOR DEVICE AND POWER AMPLIFIER CIRCUIT

Murata Manufacturing Co.,...

1. A semiconductor device comprising:a semiconductor substrate including first and second main surfaces opposing each other;
a first bipolar transistor that is formed, without a resistor layer, on the first main surface of the semiconductor substrate and includes a first emitter layer; and
a second bipolar transistor that is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer, the resistor layer being stacked on the second emitter layer in a direction normal to the first main surface;
wherein:
in the first bipolar transistor, a first contact layer is stacked on the first emitter layer in the direction normal to the first main surface;
in the second bipolar transistor, a second contact layer is stacked on the second emitter layer, and a third contact layer having a multilayered structure is stacked on the resistor layer, in the direction normal to the first main surface; and
in the second bipolar transistor, a tunneling barrier layer is inserted between the second contact layer and the resistor layer.

US Pat. No. 10,249,619

POWER SEMICONDUCTOR DEVICE HAVING TRENCH GATE TYPE IGBT AND DIODE REGIONS

Mitsubishi Electric Corpo...

1. A power semiconductor device having an IGBT region and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising:a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including,
a first layer of a first conductivity type that is provided on said second surface and is at least partially included in said diode region,
a second layer of said first conductivity type that is in contact with said first layer in said diode region, and
a third layer of a second conductivity type that is provided on said first surface and away from said second surface, is at least partially included in said diode region, and is in contact with said second layer, said second conductivity type being different from said first conductivity type;
an interlayer insulating film that is provided on said first surface of said semiconductor substrate and has a diode opening that exposes part of said third layer;
a first electrode that is provided on said interlayer insulating film and is in contact with said third layer through said diode opening; and
a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said first layer,
wherein said third layer includes a first region, a second region that is disposed away from said first region, and a diffusion region that connects said first region and said second region, said second region having a higher impurity concentration than an impurity concentration of said first region and said diffusion region having a lower impurity concentration than impurity concentrations of said first region and said second region when impurities in a direction parallel to said first surface of said semiconductor substrate are compared, and
wherein said first electrode is in contact with only said second region of said third layer.

US Pat. No. 10,249,617

TUNABLE DEVICE HAVING A FET INTEGRATED WITH A BJT

Skyworks Solutions, Inc.,...

1. A continuous tunable inductive capacitive resonator comprising:a bipolar junction transistor including a base and an emitter;
a field effect transistor integrated with at least a portion of the bipolar junction transistor, at least one of a back gate or a front gate of the field effect transistor sharing an electrical connection with the base of the bipolar junction transistor, a reverse voltage applied to the at least one of the back gate or the front gate of the field effect transistor creating a continuously variable capacitance in a channel of the field effect transistor; and
an inductor arranged to experience a capacitance that varies with the reverse voltage applied to the at least one of the back gate or the front gate of the field effect transistor, the front gate of the field effect transistor electrically connected to the back gate of the field effect transistor.

US Pat. No. 10,249,616

METHODS OF FORMING A RESISTOR STRUCTURE BETWEEN ADJACENT TRANSISTOR GATES ON AN INTEGRATED CIRCUIT PRODUCT AND THE RESULTING DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a resistor on an integrated circuit product, comprising:forming first and second adjacent gates above a semiconductor substrate, each of said first and second adjacent gates comprising a gate structure and a gate cap, said first and second adjacent gates having a space there between;
forming a conductive resistor structure in said space between said first and second adjacent gates by,
depositing a layer of conductive resistor material so as to overfill said space between said first and second adjacent gates;
performing a planarization process to remove portions of said layer of conductive resistor material positioned outside of said space so as to form an initial structure that comprises said conductive resistor material in said space, said initial structure comprising an initial thickness and an initial upper surface that us substantially planar with an uppermost surface of said gate caps of said first and second adjacent gates; and
performing a recess etching process on said initial structure so as to reduce said initial thickness and thereby form said conductive resistor structure, wherein said conductive resistor structure comprises said conductive resistor material and a recessed uppermost surface that is positioned at a level that is below a level of said uppermost surface of said gate caps of said first and second adjacent gates; and
forming first and second separate conductive resistor contact structures, each of which is conductively coupled to said conductive resistor structure.

US Pat. No. 10,249,615

MISHFET AND SCHOTTKY DEVICE INTEGRATION

NXP USA, INC., Austin, T...

1. A semiconductor device comprising: a substrate; first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate; a gate comprising a second metal layer supported by the substrate and disposed in a first opening in the first dielectric layer, the second dielectric layer being disposed between the gate and the substrate to form a metal-insulator gate configuration at a surface of the substrate; an electrode comprising a first metal layer, supported by the substrate, disposed in a second opening in the first and second dielectric layers, and disposed at the surface of the substrate and configured to establish a Schottky junction with the substrate; an inter-layer dielectric layer disposed over the electrode and first and second dielectric layers, wherein the gate is disposed within an opening in the inter-layer dielectric layer; and a field plate supported by the substrate, separate and distinct from the electrode, disposed adjacent the electrode, wherein the field plate comprises the second metal layer, and wherein the inter-layer dielectric layer is disposed between the field plate and the electrode.

US Pat. No. 10,249,614

SEMICONDUCTOR DEVICE

MACRONIX International Co...

1. A semiconductor device, comprising:a gate structure located on a substrate;
a first doped region of a first conductivity type located in the substrate on a first side of the gate structure, wherein the first doped region partially overlaps with the gate structure in top view at the first side of the gate structure but not at a second side of the gate structure;
a plurality of second doped regions of a second conductivity type located in the first doped region, wherein the second doped regions are separated from each other and are aligned with each other in a first direction;
a third doped region of the first conductivity type located in the substrate on the second side of the gate structure; and
a plurality of fourth doped regions of the second conductivity type each entirely located in the third doped region in top view, wherein the third doped region has therein only a single column of the plurality of fourth doped regions, the fourth doped regions are separated from each other and are aligned with each other in the first direction, the second doped regions are not aligned with the fourth doped regions in a second direction perpendicular to the first direction, the first doped region and the second doped regions are a source region, and the third doped region and the fourth doped regions are a drain region.

US Pat. No. 10,249,612

SEMICONDUCTOR DEVICE INCLUDING SELF-PROTECTING CURRENT SENSOR

Infineon Technologies AG,...

1. A semiconductor device comprising a semiconductor body having a first surface and a second surface opposite to the first surface, the semiconductor body comprising:a load current component comprising a load current transistor area; and
a sensor component comprising a sensor transistor area,
wherein the sensor component is operable to supply a current proportional to a load current flowing through the load current component,
wherein the sensor transistor area is at least partly surrounded by the load current transistor area, or arranged at a boundary portion of one or more sides of the load current transistor area,
wherein the sensor transistor area comprises first and third transistor area parts differing from a second transistor area part between the first and the third transistor area parts by a sensor transistor area element being absent in the second transistor area part,
wherein the second transistor area part is electrically disconnected from a parallel connection of the first and the third transistor area parts by the sensor transistor area element being absent in the second transistor area part.

US Pat. No. 10,249,610

IGBT COUPLED TO A REVERSE BIAS DEVICE IN SERIES

TEXAS INSTRUMENTS INCORPO...

1. An electrostatic discharge (ESD) device comprising:an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and
at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

US Pat. No. 10,249,609

APPARATUSES FOR COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES

Analog Devices, Inc., No...

1. An integrated circuit device, comprising:a first bipolar junction transistor (BJT);
a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), wherein a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT;
a triggering device comprising a first triggering device configured to provide a triggering current to the base of the first BJT; and
a third BJT cross-coupled with the second BJT to operate as a second SCR, wherein the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

US Pat. No. 10,249,607

INTERNALLY STACKED NPN WITH SEGMENTED COLLECTOR

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:a substrate including a semiconductor material; and
a stacked NPN bipolar transistor pair (stacked NPN), including:
a first NPN bipolar transistor (first NPN), including a first collector including collector segments of a first n-type semiconductor material in the substrate; and
a second NPN bipolar transistor (second NPN), including a second collector coupled to a first emitter of the first NPN, and a second emitter including a second n-type semiconductor material in the substrate;
wherein:
each collector segment has an orientation direction that points to the second emitter;
adjacent collector segments are laterally separated by collector separators, the collector separators electrically isolating the adjacent collector segments from each other;
said each collector segment is continuous along the orientation direction of said each collector segment; and
the collector segments are located on at least two opposite sides of the second emitter.

US Pat. No. 10,249,606

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Yokohama...

1. A semiconductor device comprising:a first domain that includes a first high power source line, a first low power source line, and a first power clamp circuit provided between the first high power source line and the first low power source line;
a second domain that include a second high power source line separated from the first high power source line, a second low power source line separated from the first low power source line, and a second power clamp circuit provided between the second high power source line and the second low power source line;
a third power clamp circuit provided between the second high power source line and the first low power source line;
a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and
a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein
the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line,
wherein
the first relay circuit is a level shifter,
the first relay circuit includes a first complementary signal generation circuit that is connected to the first high power source line and the first low power source line, and that generates a complementary signal of a signal from the first domain, and
the first relay circuit includes a first differential circuit that is connected to the second high power source line and the first low power source line, that receives a complementary signal from the first complementary signal generation circuit, and that outputs a first output to the second domain.

US Pat. No. 10,249,605

INTEGRATED CIRCUIT DEVICES

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit device comprising at least one standard cell, wherein the at least one standard cell comprises:a first active region and a second active region respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction;
a first gate line and a second gate line extending parallel to each other in a second direction perpendicular to the first direction across the first active region and the second active region, wherein the first gate line comprises a first portion of the first gate line and a second portion of the first gate line, and the second gate line comprises a first portion of the second gate line and a second portion of the second gate line;
a first detour interconnection structure configured to electrically connect the first portion of the first gate line on the first active region with the second portion of the second gate line on the second active region; and
a second detour interconnection structure configured to electrically connect the first portion of the second gate line on the first active region with the second portion of the first gate line on the second active region,
wherein the first and second detour interconnection structures comprise a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via on at least one of the first active region and the second active region to connect the lower interconnection layer with the upper interconnection layer.

US Pat. No. 10,249,603

PIXEL STRUCTURE, DISPLAY DEVICE INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE

SAMSUNG DISPLAY CO., LTD....

1. A pixel structure, comprising:a base substrate;
a plurality of first electrodes arranged in an upper portion of the base substrate;
a plurality of second electrodes each having a circular shape extending along a circumferential direction around an outer edge of one first electrode such that one second electrode surrounds the at least one first electrode; and
a plurality of LED elements connected between at least one first electrode and at least one adjacent second electrode such that the at least one first electrode is closer to a center of a circle formed by the circular-shaped at least one adjacent second electrode than the plurality of LED elements and the at least one adjacent second electrode,
wherein:
each second electrode of the plurality of second electrodes includes a first sub-second electrode and a second sub-second electrode, the first sub-second electrode and second sub-second electrode each having a semicircular shape, and the first sub-second electrode and the second sub-second electrode being spaced apart from each other, and
the pixel structure further includes:
a first electrode line connecting a plurality of the first sub-second electrodes to each other; and
a second electrode line connecting a plurality of the second sub-second electrodes to each other.

US Pat. No. 10,249,602

LIGHT EMITTING DIODE DISPLAY AND MANUFACTURE METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A manufacture method of a light emitting diode display, comprising steps of:step 1, providing a TFT backplate and a light emitting diode;
the TFT backplate comprising a substrate, a TFT layer located on the substrate, a first planarization layer located on the TFT layer, a first anode located on the first planarization layer, a second planarization layer located on the first anode and the first planarization layer and a first through hole being located on the second planarization layer and exposing at least a portion of the first anode;
the light emitting diode comprising a luminous lamp and a second anode and a second cathode respectively connected to two ends of the luminous lamp;
step 2, transferring the light emitting diode into the first through hole of the TFT backplate, and connecting the second anode of the light emitting diode with the first anode of the TFT backplate;
step 3, forming an anode contact layer, which is around the light emitting diode and on the first anode, inside the first through hole of the TFT backplate; the anode contact layer contacting with the second anode and not contacting with the second cathode;
step 4, forming a cathode insulation layer, which is around the light emitting diode and on the anode contact layer, inside the first through hole of the TFT backplate;
step 5, forming a first cathode on the cathode insulation layer, the light emitting diode and the second planarization layer, and the first cathode contacting with the second cathode.

US Pat. No. 10,249,601

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

Samsung Electro-Mechanics...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package, the fan-out semiconductor package including:
a semiconductor chip having an active surface and an inactive surface opposing the active surface, connection pads being disposed on the active surface,
a first heat dissipation member disposed side by side with the semiconductor chip,
a first encapsulant encapsulating at least portions of the semiconductor chip and at least portions of the first heat dissipation member, and
a connection member disposed below the semiconductor chip and the first heat dissipation member and comprising a redistribution layer electrically connected to the connection pads of the semiconductor chip; and
a component package disposed on the fan-out semiconductor package, the component package comprising:
a wiring substrate disposed on the first encapsulant,
a plurality of electronic components disposed on the wiring substrate,
a second encapsulant encapsulating at least portions of the plurality of electronic components, and
a second heat dissipation member formed in the wiring substrate,
wherein at least one of the plurality of electronic components of the component package is connected to the first heat dissipation member through the second heat dissipation member.

US Pat. No. 10,249,600

LIGHT EMITTING APPARATUS, ILLUMINATION APPARATUS AND DISPLAY APPARATUS

SONY CORPORATION, Tokyo ...

1. A light emitting apparatus comprising:a light emitting device having an upper side and a lower side and emitting configured to emit light from an upper surface at the upper side thereof;
a first electrode at the lower side and a second electrode at the upper side;
first and second terminal electrodes provided at the lower side with the light emitting device overlying the first terminal electrode and with its first electrode electrically connected to the first terminal electrode, the second terminal electrode laterally spaced from the first terminal electrode and not overlain by the light emitting device, the first terminal electrode and the second terminal electrode are for application of power to the light emitting device;
a first metal line electrically connecting the second terminal electrode and the second electrode;
a second metal line electrically connected to the first terminal electrode but not directly connected to the light emitting device; and
a transparent insulator in which the light emitting device, the first metal line, the second metal line are embedded, wherein, in cross section, the second electrode is surrounded on three sides by the first metal line.

US Pat. No. 10,249,598

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Intel Corporation, Santa...

1. A method of forming an integrated circuit (IC) package comprising:providing a first encapsulation layer having a first die and a plurality of electrical routing features at least partially embedded therein, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer on a first side of the first die, wherein the first die has a second side opposite the first side, wherein the plurality of electrical routing features electrically couple the first side of the first encapsulation layer with a second side of the first encapsulation layer, and wherein the first side of the first encapsulation layer is disposed opposite the second side of the first encapsulation layer, wherein the first encapsulation layer at least partially covers an electrically insulative material layer, wherein the plurality of electrical routing features fully extend through the electrically insulative material layer;
coupling a second die with the second side of the first encapsulation layer, wherein the second die includes a second plurality of die-level interconnect structures, and wherein the first encapsulation layer covers the second side of the first die;
electrically coupling the second plurality of die-level interconnect structures with at least a subset of the plurality of electrical routing features by bonding wires; and
forming a second encapsulation layer over the second die and the bonding wires to encapsulate at least a portion of the second die and the bonding wires in the second encapsulation layer, wherein the second encapsulation layer is in direct contact with the first encapsulation layer.

US Pat. No. 10,249,595

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) providing an arrangement having a semiconductor chip mounted on a die pad, a suspension lead connected to the die pad, and a lead spaced apart from the die pad and the suspension lead;
(b) sealing the semiconductor chip, the lead, and the suspension lead;
(c) after the step (b), cutting the lead with a punch;
(d) after the step (c), making a mark on a front surface of a sealing body formed by the step (b); and
(e) after the step (d), cutting the suspension lead with a punch.

US Pat. No. 10,249,594

DISPLAY DEVICE AND METHOD FOR ASSEMBLING THE SAME

BOE Technology Group Co.,...

1. A display device, comprising an electronic device and a flexible printed circuit board which are detachably connected,wherein the electronic device comprises a lead region and a port located at the lead region, the flexible printed circuit board comprises a first portion and a second portion,
wherein the first portion is a connector, the second portion comprises connecting fingers through which the flexible printed circuit board is connected to the port,
wherein the second portion of the flexible printed circuit board is arranged at a predetermined region, the predetermined region comprises the lead region and an extension region which is arranged outside the lead region and in a same plane where the lead region is located, and the extension region is a region extending outwards from the lead region until reaching other components and is within a surface of the electronic device where the lead region located,
wherein the flexible printed circuit board is provided with a hollow part, configured to allow a component which is arranged at the lead region to be exposed when the flexible printed circuit board is attached onto the lead region, a driving chip is arranged at the lead region, the flexible printed circuit board is provided with the hollow part located at a region corresponding to the driving chip to allow the driving chip to be exposed at the hollow part when the flexible printed circuit board is attached onto the lead region.

US Pat. No. 10,249,593

METHOD FOR BONDING A CHIP TO A WAFER

Agency for Science, Techn...

1. A method for chip on wafer bonding, comprising:forming posts on a wafer;
forming contacts on a chip such that the posts and the contacts align upon inversion of the chip onto the wafer;
planarizing each of the posts to have a contact surface with a surface roughness height less than 20 nanometers;
depositing, to the contact surface of the posts, a bonding material with a thickness not greater than the surface roughness height of the contact surface; and
temporarily bonding the posts to the contacts using the bonding material to stabilize a position of the chip relative to the wafer before subsequently permanently diffusion bonding of the chip to the wafer,
wherein the surface roughness height is a difference in height between a lowest point on a surface of the contact surface and a highest point on the surface of the contact surface.

US Pat. No. 10,249,590

STACKED DIES USING ONE OR MORE INTERPOSERS

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and
an interposer which includes interconnects that aligns to and electrically connects at least one functional via interconnect and a redundant functional via interconnect of a different die when the interposer is oriented in a predetermined orientation, wherein the interconnects of the interposer are directly connected by solder bumps to the at least one functional via interconnect of the at least one die and the redundant functional via interconnect of the different die.

US Pat. No. 10,249,589

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LAYER AND CONDUCTIVE PILLAR DISPOSED ON CONDUCTIVE LAYER AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor layer formed over the semiconductor substrate and including a first upper surface and a first lower surface;
a conductive pillar disposed on the first upper surface of the conductor layer and including a second upper surface, a second lower surface, and a sidewall;
a first insulating film covering the first upper surface of the conductor layer and including an opening which exposes the second upper surface and the sidewall of the conductive pillar;
a protection film covering the sidewall of the conductive pillar,
wherein, in a plan view, the opening is wider than the second upper surface and exposes an entire region of the second upper surface, and
wherein the second lower surface of the conductive pillar is in contact with the first upper surface of the conductor layer in an entire region of the conductive pillar; and
a second insulating film formed under the conductor layer in such a manner as to overlap with the entire region of the conductive pillar in the plan view,
wherein, in the plan view, the first upper surface of the conductor layer is exposed from the protection film and the conductive pillar.

US Pat. No. 10,249,588

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Intel Corporation, Santa...

1. A method of forming an assembly, comprising:providing a substrate, the substrate having a metal pad including aluminum, a base layer metal (BLM) disposed on the metal pad, the BLM including titanium, a bump disposed on the BLM, the bump including copper, and a first solder layer disposed on the bump, the first solder layer including tin and having a first material composition;
providing a die package, the die package having a first side and an opposing second side, and a second solder layer disposed on the first side of the die package, the second solder layer including tin and having a second material composition different from the first material composition, wherein one of the first solder layer or the second solder layer comprises an element not included in the other of the first solder layer or the second solder layer;
connecting the second solder layer of the die package to the first solder layer of the substrate to enable electrical current to flow between the die package and the substrate.

US Pat. No. 10,249,587

SEMICONDUCTOR DEVICE INCLUDING OPTIONAL PAD INTERCONNECT

Western Digital Technolog...

1. A semiconductor die, comprising:a plurality a die bond pads, comprising:
a first die bond pad, and
a second die bond pad configured to provide functional redundancy to the first die bond pad; and
a metal interconnect having a first end connected to the first die bond pad and a second end, opposite the first end, connected to at least a portion of the second die bond pad.

US Pat. No. 10,249,586

MIXED UBM AND MIXED PITCH ON A SINGLE DIE

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first set of micro under-bump metallizations (UBMs) on a surface of a photosensitive polyimide (PSPI) layer in a first region of a die comprising a first pitch constraint, each micro UBM comprising a via electrically coupling the respective UBM to a contact region of the die;
forming a second set of micro UBMs on a surface of the PSPI layer in a second region of the die comprising a second pitch constraint, each micro UBM comprising a via electrically coupling the respective UBM to a contact region of the die, the second pitch constraint higher than the first pitch constraint, wherein the first region and the second region are configured to have a matching plateable surface areas;
forming a single solder bump electrically shorting the first set of micro UBMs to a single contact region of a laminate, wherein the single solder bump has an elliptical shape; and
forming individual solder bumps electrically shorting each of the second set of micro UBMs to a contact region of a laminate.

US Pat. No. 10,249,585

STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A stackable semiconductor package, comprising:a carrier having a first surface, at least one sidewall substantially perpendicular to the first surface, and a plurality of through holes penetrating through the first surface, the through holes including a plurality of terminal holes and a chip-accommodating hole, wherein the carrier is only made of a rigid plate having no electrical transmission function;
a first redistribution layer (RDL) formed directly on and in physical contact with the first surface of the carrier, wherein the first RDL comprises a plurality of first pads and a plurality of second pads, the terminal holes correspondingly expose a portion of each of the second pads, and the chip-accommodating hole exposes the first pads;
an encapsulation layer formed directly on and in physical contact with the first surface of the carrier, the encapsulation layer encapsulating the first RDL, wherein the encapsulation layer has an outer surface and at least one sidewall substantially perpendicular to the outer surface of the encapsulation layer and the first surface of the carrier, the at least one sidewall of the encapsulation layer being correspondingly coplanar to the at least one sidewall of the carrier;
a plurality of vertical interposers disposed in the encapsulation layer, wherein the vertical interposers are electrically connected to the first RDL;
a second RDL formed on the outer surface of the encapsulation layer to electrically connect with the vertical interposers, the second RDL comprising a plurality of third pads; and
a chip disposed in the chip-accommodating hole, and electrically connected to the first pads.

US Pat. No. 10,249,583

SEMICONDUCTOR DIE BOND PAD WITH INSULATING SEPARATOR

Infineon Technologies AG,...

1. A semiconductor die, comprising:a last metallization layer above a semiconductor substrate;
a bond pad above the last metallization layer;
a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad;
an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad; and
an electrically conductive interconnection structure that extends from the bond pad to the last metallization layer outside the contact area of the bond pad.

US Pat. No. 10,249,581

TRANSMISSION LINE FOR 3D INTEGRATED CIRCUIT

Taiwan Semiconductor Manu...

1. A semiconductor transmission line substructure comprising:a first semiconductor substrate;
a first signal line over said first semiconductor substrate;
a first ground line over said first semiconductor substrate;
a second semiconductor substrate over said first semiconductor substrate, wherein each of said first semiconductor substrate, said first signal line, said first ground line and said second semiconductor substrate are vertically spaced apart from one another, wherein said second semiconductor substrate is between said first signal line and said first ground line.

US Pat. No. 10,249,579

ACTIVE SHIELD FOR PROTECTING A DEVICE FROM BACKSIDE ATTACKS

NUVOTON TECHNOLOGY CORPOR...

1. An electronic apparatus, comprising:a substrate comprising active devices;
one or more routing layers, which are electrically connected to the active devices and are configured to route electrical signals to and from the active devices;
an active shield layer, which is disposed within a routing layer nearest to the substrate, wherein the active shield layer comprises metallic traces configured to conduct active-shield signals that provide an indication of an attack on the apparatus; and
protection circuitry, which is connected to the metallic traces of the active-shield layer and is configured to drive the active-shield signals and to detect the attack based on the active-shield signals.

US Pat. No. 10,249,578

CORE-SHELL PARTICLES FOR ANTI-TAMPERING APPLICATIONS

International Business Ma...

1. A method of making a tamper resistant apparatus, comprising:disposing a core-shell particle on a first surface of a tampering sensor, the first surface including a first conductive portion and a second conductive portion spaced from each other, wherein
the core-shell particle has a liquid metallic core and a shell surrounding the liquid metallic core, and
the tampering sensor is configured to trigger a security response when the first conductive portion and the second conductive portion are electrically connected to each other.

US Pat. No. 10,249,575

RADIO-FREQUENCY ISOLATION USING CAVITY FORMED IN INTERFACE LAYER

Skyworks Solutions, Inc.,...

1. A method for fabricating a semiconductor device, the method comprising:providing a transistor device;
forming one or more electrical connections to the transistor device;
forming one or more dielectric layers over at least a portion of the electrical connections;
applying an interface material over at least a portion of the one or more dielectric layers;
removing at least a portion of the interface material to form a trench; and
covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

US Pat. No. 10,249,574

METHOD FOR MANUFACTURING A SEAL RING STRUCTURE TO AVOID DELAMINATION DEFECT

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a semiconductor substrate;
forming a plurality of integrated circuit (IC) devices on the semiconductor substrate; and
forming a seal ring structure surrounding each of the IC devices, wherein forming the seal ring structure comprises:
forming a plurality of interlayer dielectric layers on the semiconductor substrate; and
forming a plurality of hollow through-hole structures within the interlayer dielectric layers, wherein forming a plurality of hollow through-hole structures within the interlayer dielectric layers comprises:
performing an etching process on each of the interlayer dielectric layers at a location of a cutting channel in the semiconductor substrate to form one or more through-holes;
sequentially forming a diffusion barrier layer and a seed layer at a bottom portion and sidewalls of the one or more through-holes, wherein the diffusion barrier layer and the seed layer seal an opening at a top portion of the one or more through-holes.

US Pat. No. 10,249,573

SEMICONDUCTOR DEVICE PACKAGE WITH A STRESS RELAX PATTERN

POWERTECH TECHNOLOGY INC....

1. A method of forming a semiconductor device package, the semiconductor device package comprising:a die;
a plurality of metal contacts electrically connected to the die;
a continuous pattern of dielectric material formed on an active surface of the die, the continuous pattern of dielectric material forming contours of at least one opening, each of the at least one opening surrounding at least one of the metal contacts electrically connected to the die;
a mold compound formed around the pattern, the die and the metal contacts, wherein at least a space between the metal contacts and the pattern is filled with the mold compound; and
a redistribution layer, formed on a grinded surface of the mold compound, and electrically connected to the metal contacts;the method comprising:disposing the die on a carrier;
forming the pattern of dielectric material on the active surface of the die to surround the plurality of metal contacts electrically connected to the die;
forming the mold compound around the die, the metal contacts and the pattern, wherein the dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound;
grinding the mold compound to expose the metal contacts;
removing the carrier; and
forming the redistribution layer on the grinded surface of the mold compound to electrically connect the metal contacts.

US Pat. No. 10,249,571

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL

BOE Technology Group Co.,...

1. A thin film transistor comprising:an active layer, and a light-protection layer disposed above the active layer and/or disposed beneath the active layer,
wherein the light-protection layer is configured to absorb light having a predetermined wavelength, and
wherein a forbidden band gap of the light-protection layer is greater 1.1 eV and less than 2.3 eV with a transmissivity lower than 70%.

US Pat. No. 10,249,570

OVERLAY MARK

TAIWAN SEMICONDUCTOR MANU...

1. An overlay mark, comprising:a first feature in a first layer, wherein the first feature comprises a plurality of first alignment segments extending along a first direction;
a second feature in a second layer over the first layer, wherein the second feature comprises a plurality of second alignment segments extending along a second direction different from the first direction; and
a third feature in a third layer over the second layer, wherein the third feature comprises a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction,
wherein, in a plan view, each first alignment segment of the plurality of first alignment segments is adjacent to a corresponding third alignment segment of the plurality of third alignment segments along the first direction, and each second alignment segment of the plurality of second alignment segments is adjacent to a corresponding fourth alignment segment of the plurality of fourth alignment segments along the second direction.

US Pat. No. 10,249,569

SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A system-on-chip, comprising:a processor; and
a hardware component connected to the processor,
wherein at least one of the processor and the hardware component comprises:
a semiconductor substrate; and
a plurality of metal layers formed above the semiconductor substrate,
wherein a first metal layer among the plurality of metal layers comprises:
a plurality of first power rails which extend in a first direction and transmit a first voltage;
a plurality of second power rails which extends in the first direction and transmit a second voltage; and
a first conductor which is coupled to one end of each of the first power rails and extends in a second direction,
wherein a second metal layer placed over the first metal layer comprises:
a third power rail transmitting the first voltage; and
a fourth power rail transmitting the second voltage, and
wherein the third power rail and the fourth power rail are spaced apart from the first conductor in the first direction.

US Pat. No. 10,249,567

REDISTRIBUTION LAYER STRUCTURE OF SEMICONDUCTOR PACKAGE

Industrial Technology Res...

17. A redistribution layer structure of a semiconductor package, comprising:a dielectric layer having a thickness, and the dielectric layer having a first surface and a second surface opposite to the first surface;
an upper conductive wire disposed on the first surface of the dielectric layer and having a first width;
a lower conductive wire disposed on the second surface of the dielectric layer and having a second width, wherein the upper conductive wire and the lower conductive wire are separated by the dielectric layer; and
a single via penetrating the dielectric layer and connecting the upper conductive wire and the lower conductive wire, wherein the single via has a cross-section at the upper conductive wire, and the cross-section has a third width, wherein a ratio of the third width of the cross-section of the single via to the thickness of the dielectric layer is less than or equal to 1.

US Pat. No. 10,249,566

SEMICONDUCTOR DEVICE INCLUDING FUSE STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a first region and a second region;
an eFuse structure formed in the first region; and
an interconnect structure formed in the second region, wherein:
the eFuse structure includes a first metal pattern formed at a first vertical level on the substrate, a second metal pattern formed at a second vertical level between the first vertical level and the substrate, a third metal pattern formed at a third vertical level between the second vertical level and the substrate, a first via physically connecting the first metal pattern to the second metal pattern, and a second via physically connecting the second metal pattern to the third metal pattern,
the first metal pattern includes a first bent portion in a U shape, and a first auxiliary pattern extending in a first direction and being adjacent to and electrically isolated from the first bent portion,
the first bent portion includes a first portion which extends in the first direction and is electrically connected to the first via, and a second portion extending in the first direction and being adjacent to the first portion,
the second portion is disposed between the first portion and the first auxiliary pattern, and
a first distance between the first portion and the second portion spaced apart from the first portion is greater than a width of the second portion in a second direction perpendicular to the first direction.

US Pat. No. 10,249,565

SEMICONDUCTOR DEVICE THAT TRANSFERS AN ELECTRIC SIGNAL WITH A SET OF INDUCTORS

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate of a substantially rectangular shape having a first surface and a second surface opposite the first surface, a first side, a second side opposite the first side, a third side and a fourth side, which intersect the first and second sides, a plurality of electrode pads formed on the first surface, and a plurality of soldering balls formed on the second surface;
the plurality of electrode pads including a plurality of first electrode pads closer to the first side than the second side and a plurality of second electrode pads closer to the second side than the first side;
the second surface having a first area which is closer to the first side than the second side and which is contiguous to the first, third and fourth sides, a second area which is closer to the second side than the first side and which is contiguous to the second, third and fourth sides, and a third area which is contiguous to the first and second areas, and the third and fourth sides;
the plurality of soldering balls including a plurality of first soldering balls which are shaped in a form of a lattice and which are on the first area, and a plurality of second soldering balls which are shaped in a form of a lattice and which are on the second area;
the plurality of first soldering balls electrically connected with the plurality of the first electrode pads of the wiring substrate;
the plurality of second soldering balls electrically connected with the plurality of the second electrode pads of the wiring substrate;
a first semiconductor chip of a substantially rectangular shape having a first main surface, a first side surface, a second side surface opposite the first side surface, and a first inductor which is closer to the first side surface than the second side surface and which is on the first main surface;
the first semiconductor chip being mounted on the first surface of the wiring substrate and closer to the first side of the wiring substrate than the second side of the wiring substrate;
a second semiconductor chip of a substantially rectangular shape having a second main surface, a third side surface, a fourth side surface opposite the third side surface, and a second inductor which is closer to the third side surface than the fourth side surface and which is on the second main surface;
the second semiconductor chip being mounted side by side with the first semiconductor chip on the first surface of the wiring substrate and closer to the second side of the wiring substrate than the first side of the wiring substrate such that the third side surface faces the first side surface of the first semiconductor chip;
a plurality of bonding wires including a plurality of first bonding wires by which the first main surface of the first semiconductor chip is connected with the plurality of first electrode pads of the wiring substrate, and a plurality of second bonding wires by which the second main surface of the second semiconductor chip is connected with the plurality of second electrode pads of the wiring substrate; and
a sealed resin body covering the first surface of the wiring substrate, the first semiconductor chip, the second semiconductor chip, and the plurality of bonding wires,
wherein, in the plan view, the plurality of first soldering balls include a first ball that is most proximate to the second side of the wiring substrate in the plurality of first soldering balls,
wherein, in the plan view, the plurality of second soldering balls include a second ball that is most proximate to the first side of the wiring substrate in the plurality of second soldering balls,
wherein a shortest distance between the first and second soldering balls is greater than a shortest distance from the first side surface of the first semiconductor chip and the third side surface of the second semiconductor chip in the plan view,
wherein, in the plan view, an area between the first side surface of the first semiconductor chip and the third side surface of the second semiconductor chip on the first surface of the wiring substrate is within the third area of the wiring substrate,
wherein a soldering ball is not in the third area of the wiring substrate;
wherein the first inductor of the first semiconductor chip is not electrically connected with the second inductor of the second semiconductor chip,
wherein the first semiconductor chip is not electrically connected with the second semiconductor chip via a bonding wire in the plan view, and
wherein the first soldering ball is not electrically connected with the second soldering ball.

US Pat. No. 10,249,564

ELECTRONIC COMPONENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

KYOCERA CORPORATION, Kyo...

1. An electronic component mounting substrate comprising:an insulating base having a rectangular shape in plan view and comprising a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface;
a band-shaped metal layer on a sidewall of the recess; and
an electrode extending from a bottom surface of the recess into the insulating base,
the electrode comprising an end disposed in the insulating base, the end comprising an inclined portion inclined toward the second main surface, the inclined portion having a tip, a part of which is closer to the second main surface than the bottom surface of recess when viewed in longitudinal section.

US Pat. No. 10,249,563

MULTILAYER WIRING SUBSTRATE

FUJIFILM Corporation, Mi...

1. A multilayer wiring substrate comprising:an anisotropic conductive member including an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each conductive path has a protrusion protruding from the surface of the insulating base; and
a wiring substrate having a substrate and one or more electrodes to be formed on the substrate,
wherein the multilayer wiring substrate is formed by laminating the anisotropic conductive member and the wiring substrate,
the wiring substrate has a resin layer which covers at least a part of the substrate,
the electrode is formed to be flush with the resin layer,
the resin layer is a layer that allows the protrusion to penetrate therein when pressure is applied at 20 MPa,
at least a part of the protrusions of the conductive paths other than the conductive paths which come in contact with the electrode among the plurality of conductive paths penetrates into the resin layer, and
conductive paths which come into contact with the electrode among the plurality of conductive paths are deformed so that adjacent conductive paths come into contact with each other.

US Pat. No. 10,249,562

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. A package structure, comprising:a carrier having opposite first and second surfaces, wherein at least a recess is formed on the first surface of the carrier;
at least an electronic element disposed in the recess of the carrier;
an insulating layer formed in the recess to encapsulate the electronic element and on the first surface of the carrier to cover the first surface, with a plurality of through holes penetrating the first and second surfaces of the carrier and the insulating layer, wherein the insulating layer is made of a material different from a material of the carrier;
a circuit structure formed on the first surface of the carrier and electrically connected to the electronic element; and
a plurality of conductors formed in the through holes, wherein the conductors are conductive columns and penetrate the first and second surfaces of the carrier and the insulating layer and are electrically connected to the circuit structure.

US Pat. No. 10,249,561

PRINTED WIRING BOARD HAVING EMBEDDED PADS AND METHOD FOR MANUFACTURING THE SAME

IBIDEN CO., LTD., Ogaki ...

1. A printed wiring board, comprising:a support plate; and
a build-up wiring layer comprising a plurality of resin insulating layers and a plurality of conductor layers and having a first surface and a second surface on an opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer,
wherein the plurality of resin insulating layers in the build-up wiring layer includes a first resin insulating layer that forms the second surface of the build-up wiring layer, the build-up wiring layer includes a plurality of first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer, and a plurality of via conductors formed in the plurality of resin insulating layers such that diameters of the via conductors are reducing from the first surface toward the second surface of the build-up wiring layer, each of the first conductor pads comprises a dissimilar metal layer comprising a plurality of metal layers such that the metal layers are formed of different metals with respect to each other, and the dissimilar metal layer comprises a copper plating layer and a corrosion resistant plating layer formed on the copper plating layer.

US Pat. No. 10,249,559

BALL GRID ARRAY AND LAND GRID ARRAY ASSEMBLIES FABRICATED USING TEMPORARY RESIST

International Business Ma...

1. A structure comprising:a substrate including a front side, a back side, and electrically conductive contact pads on the back side;
a patterned resist film directly contacting the back side of the substrate, the resist film including channels exposing a plurality of the contact pads;
a plurality of solder bumps, each of the solder bumps being within one of the channels in the patterned resist film and electrically contacting one of the contact pads;
a plurality of contact elements on the front side of the substrate configured for electrical connection to a chip;
a chip electrically and mechanically connected to the contact elements; and
one or more stand-off elements within one or more of the channels of the patterned resist film and solder material encasing the one or more stand-off elements, the one or more stand-off elements having substantially higher melting points than the solder material and the solder bumps.

US Pat. No. 10,249,558

ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE

NSK LTD., Tokyo (JP)

22. An electronic part mounting heat-dissipating substrate which comprises: a conductor plate which is formed on lead frames of wiring pattern shapes to mount an electronic part; and an insulating member which is provided between said lead frames of said wiring pattern shapes on said conductor plate; in which a plate surface of an electronic part arrangement surface of said conductor plate and a plate surface of an electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane, and a plate surface of a back surface of said electronic part arrangement surface of said conductor plate and a plate surface of a back surface of said electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane,wherein said lead frames of said wiring pattern shapes have different thicknesses of at least two types or more, a thickness of the lead frames being measured in a direction parallel to the mounting direction of the electronic part, and a thick lead frame is used for a large current signal and a thin lead frame is used for a small current signal,
wherein said plate surface of said back surface of said electronic part arrangement surface of said lead frames of said wiring pattern shapes and said plate surface of said back surface of said electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane to meet said plate surface of said back surface of said electronic part arrangement surface of a thickest lead frame among said lead frames, and
wherein plural pin-shape cavities are disposed on a substrate surface that is a different surface on which a thin lead frame of said electronic part arrangement surface is provided, and are extended from a back surface side of said substrate of said thin lead frame to said different surface side of said substrate.

US Pat. No. 10,249,555

COMPOSITE HEAT SINK STRUCTURES

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:a composite heat sink structure including:
a thermally conductive base, the thermally conductive base including a main heat transfer surface to couple to at least one component to be cooled;
a compressible, continuous sealing member;
a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base;
a one-piece member molded over and affixed to the thermally conductive base, and molded over and securing in place the sealing member retainer, wherein a coolant-carrying compartment resides between the thermally conductive base and the one-piece member and wherein the one-piece member contacts a surface of the thermally conductive base opposite to the main heat transfer surface and wraps around at least a portion of the thermally conductive base to secure the one-piece member to the thermally conductive base absent use of separate fasteners; and
a coolant inlet and a coolant outlet, the coolant inlet and coolant outlet being in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow therethrough.

US Pat. No. 10,249,554

HEAT TRANSFER ASSEMBLY FOR A HEAT EMITTING DEVICE

GENERAL ELECTRIC COMPANY,...

1. A heat transfer assembly coupled to a heat emitting device for dissipating heat from the heat emitting device, the heat transfer assembly comprising:a module inlet for receiving a coolant;
at least one module comprising a first part having a recess to receive a portion of the heat emitting device, and a second part having a shaped cutout portion and a solid portion;
a sealing component disposed between the heat emitting device and the at least one module;
a module outlet for discharging a heat absorbed coolant after absorbing heat from the heat emitting device, wherein the at least one module is connected to the module inlet and the module outlet,wherein the second part allows a uniform compression of the seal component, and wherein the first part and the second part are mechanically connected to each other; andwherein the at least one module is flexible to achieve a convex curvature or a concave curvature for load balance for leak-proof sealing.

US Pat. No. 10,249,553

COOLING APPARATUS FOR A HEAT-GENERATING ELEMENT

Nissan Motor Co., Ltd., ...

1. A cooling apparatus for a heat-generating element, comprising:a heat sink having a main surface on which the heat-generating element is mounted and a heat radiation surface from which heat generated by the heat-generating element is radiated;
a cooling component having a recess and an interior gap,
the recess having an outer sidewall extending in a substantially perpendicular direction to the heat sink,
the interior gap being defined by an interior gap plane and an exterior gap plane, the interior gap plane being coplanar with the outer sidewall,
the cooling component and the heat sink facing and joining each other so that the recess forms a coolant passage in which a coolant flows; and
a sealing member provided between the heat sink and the cooling component so as to seal the coolant passage and separate an interior and exterior of the coolant passage, the sealing member having an internal side and an external side, the internal side being adjacent to the coolant passage, wherein
the sealing member is provided outside a plane which is coplanar with a first sidewall of the recess such that the internal side of the sealing member is coplanar with the interior gap plane,
a first distance is longer than a second distance with regard to a distance between facing surfaces of the heat sink and the cooling component near the sealing member,
the first distance is a distance between the facing surfaces within the interior gap between the sealing member and the first sidewall of the recess at an interior side of the coolant passage separated by the sealing member, the first distance having a minimal value at a point of the cooling component closest to the sealing member, and
the second distance is a distance between the facing surfaces at an exterior side of the coolant passage separated by the sealing member.

US Pat. No. 10,249,550

POWER MODULE WITH LEAD COMPONENT AND MANUFACTURING METHOD THEREOF

DELTA ELECTRONICS, INC., ...

1. A power module comprising:a carrier board; and
at least one lead component, stacked and disposed on the carrier board, and comprising:
at least one initial plane, wherein the initial plane includes at least one pad, and a vertical projection of the initial plane at least partially overlaps with the carrier board;
at least one first pin electrically connected to the carrier board, wherein the first pin is vertical to the initial plane;
at least one second pin electrically connected to the carrier board, wherein the second pin is vertical to the initial plane; and
at least one isolation gap disposed in the initial plane and located between the first pin and the second pin, wherein the initial plane is separated into a first plane and a second plane by the isolation gap, so as to electrically isolate the first pin and the second pin from each other.

US Pat. No. 10,249,549

CERAMIC CIRCUIT BOARD, ELECTRONIC CIRCUIT MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC CIRCUIT MODULE

MURATA MANUFACTURING CO.,...

1. A ceramic circuit board comprising: a ceramic insulator layer; at least one grounding pattern conductor, the at least one grounding pattern conductor containing a metal and an oxide of at least one metal element contained in the ceramic insulator layer, the at least one grounding pattern conductor including a pattern main portion disposed within the ceramic circuit board and an extended portion having a first end thereof connected to the pattern main portion and a second end thereof exposed at a side surface of the ceramic circuit board, and a first metal content of the extended portion is lower than a second metal content of the pattern main portion; a connection land disposed on a first surface of the ceramic board; and a grounding electrode disposed on a second surface of the ceramic board and connected to the grounding pattern conductor, wherein the first metal content of the extended portion is 30 to 60 percent by volume, and the second metal content of the pattern main portion is 80 percent by volume or more.

US Pat. No. 10,249,548

TEST CELL FOR LAMINATE AND METHOD

INTERNATIONAL BUSINESS MA...

1. A method of designing a laminate comprising:forming a test laminate that includes:
a plurality of buildup layers disposed on a core; and
one or more unit cells defined in the buildup layers, each unit cell including:
at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and
two or more dummy vias;
wherein the dummy vias are arranged in the unit cell at one of a plurality of distances from the test via;
subjecting test laminate to a stress;
testing at least one of the one more unit cells;
determining that at least one of the one or more unit cells is a failed cell; and
designing the laminate such that it does not include a via configuration from the failed cell in a location under a computer chip where the failed cell was located.

US Pat. No. 10,249,547

METHOD FOR USING A TEST WAFER BY FORMING MODIFIED LAYER USING A LASER BEAM AND OBSERVING DAMAGE AFTER FORMING MODIFIED LAYER

DISCO CORPORTATION, Toky...

1. A test wafer using method for using a test wafer including a test substrate and a metal foil formed on a front side of said test substrate, said test wafer using method comprising:a modified layer forming step of applying a laser beam having a transmission wavelength to said test substrate from a back side of said test wafer in the condition where a focal point of said laser beam is set inside said test substrate, thereby forming a modified layer inside said test substrate;
a damage detecting step of observing a front side of said test wafer after performing said modified layer forming step, thereby detecting damage to said metal foil; and
a processing conditions adjusting step of adjusting at least one of the laser processing conditions adopted in said modified layer forming step according to the result of detection of said damage obtained in said damage detecting step, said at least one of the laser processing conditions being selected from the group consisting of the wavelength of said laser beam, average power of said laser beam, repetition frequency of said laser beam, pulse width of said laser beam, numerical aperture of a focusing lens for focusing said laser beam, focal position of said laser beam, and relative feed speed of said test wafer.

US Pat. No. 10,249,546

REVERSE DECORATION FOR DEFECT DETECTION AMPLIFICATION

KLA-Tencor Corporation, ...

1. A method comprising:applying a layer of a material on a surface of a plurality of NAND stacks such that a bridge structure between two of the NAND stacks is covered with the layer, wherein the material has a refractive index different from that of the surface thereby amplifying detection of the bridge structure; and
removing a first portion of the layer from the plurality of NAND stacks, wherein a second portion of the layer remains disposed on the bridge structure after the removing.

US Pat. No. 10,249,543

FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:an n-type field effect transistor (nFET) gate stack arranged over a first channel region of the device, the n-type gate stack comprising:
a dielectric layer arranged on a substrate;
a first nitride layer arranged on the dielectric layer, the first nitride layer comprising TaN;
a niobium aluminum carbonitride stack arranged on the first nitride layer:
a scavenging layer arranged on the niobium aluminum carbonitride stack, the scavenging layer comprising NbAlC or TiAlC;
a second nitride layer arranged on the scavenging layer, the second nitride layer comprising TiN or TaN; and
a gate electrode arranged on the second nitride layer; and
a p-type field effect transistor (pFET) gate stack arranged over a second channel region of the device, the p-type gate stack comprising:
the dielectric layer arranged on the substrate;
the first nitride layer arranged on the dielectric layer;
the scavenging layer arranged on the first nitride layer;
the second nitride layer arranged on the scavenging layer; and
the gate electrode arranged on the second nitride layer.

US Pat. No. 10,249,542

SELF-ALIGNED DOPING IN SOURCE/DRAIN REGIONS FOR LOW CONTACT RESISTANCE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first semiconductor fin formed in a pFET region of a substrate and a second semiconductor fin formed in a nFET region of the substrate;
a first gate formed over a first channel region of the first semiconductor fin and a second gate formed over a first channel region of the second semiconductor fin;
a first doped region formed on the first semiconductor fin and adjacent to the first gate, the first doped region comprising p-type dopants doped silicon germanium (SiGe), said p-type dopants selected from the group consisting of gallium (Ga), boron (B), difluoroboron (BF2), and aluminum (Al); and
a second doped region formed on the second semiconductor fin and adjacent to the second gate, the second doped region embedded below a surface of the second semiconductor fin, wherein the first doped region comprises an upper doped part and a bottom doped part, the first and second doped regions being adjacent to the first semiconductor fin but not in the first semiconductor fin, wherein the upper doped part has more dopants than the bottom doped part.

US Pat. No. 10,249,541

FORMING A HYBRID CHANNEL NANOSHEET SEMICONDUCTOR STRUCTURE

International Business Ma...

1. A method for fabricating a nanosheet semiconductor structure, the method comprising:forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material;
wherein the first material is different than the second material, and
further wherein forming the first nanosheet FET structure and the second nanosheet FET structure comprises:
creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region; and
creating a second inner spacer formation within a second SiGe channel, wherein the second SiGe channel is comprised in a second channel region of a second FET region,
forming a first stack on the first FET region and a second stack on the second FET region, wherein the first stack comprises a first substrate, the one or more first Si nanosheets, and the one or more first SiGe nanosheets, and wherein the second stack comprises the second substrate, the one or more second Si nanosheets, and the one or more second SiGe nanosheets;
forming a first pad insulator on the first channel region and a second pad insulator on the second channel region;
forming a first gate on the first pad insulator and a second gate on the second pad insulator;
forming a first hard mask on the first gate and a second hard mask on the second gate;
forming a first spacer on the first channel region, the first gate, and the first hard mask, and a second spacer on the second channel region, the second gate, and the second hard mask, wherein each spacer comprises silicon mononitride (SiN); and
forming the first channel region from the first stack and the second channel region from the second stack.

US Pat. No. 10,249,539

NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first sacrificial layer between a first nanosheet and a second nanosheet;
forming a second sacrificial layer between a third nanosheet and a fourth nanosheet;
doping the first nanosheet;
forming another nanosheet over of the first nanosheet having been doped and the second nanosheet, subsequent to doping the first nanosheet;
wherein the first, second, another nanosheets are vertically stacked nanosheets in a first nanosheet stack and the third and fourth nanosheets are vertically stacked nanosheets in a second nanosheet stack;
concurrently removing the first sacrificial layer, the first nanosheet, and the second sacrificial layer, such that the first nanosheet is no longer present.

US Pat. No. 10,249,538

METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming, on a semiconductor substrate, a first lower source/drain region with a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region and a second lower source/drain region with a second semiconductor fin extending upward from a top surface of the second lower source/drain region,
wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and
wherein the first semiconductor fin and the second semiconductor fin are patterned from a monocrystalline epitaxial semiconductor layer and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively; and,
forming a first transistor with the first lower source/drain region and a second transistor with the second lower source/drain region.

US Pat. No. 10,249,537

METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a first fin of a first transistor in a substrate;
forming a second fin of a second transistor in the substrate;
disposing a first doped oxide layer comprising a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant;
disposing a mask over the first fin and removing the first doped oxide layer from the second fin;
removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first fin and directly onto the second fin, the second doped oxide layer comprising an n-type dopant or a p-type dopant that is different than the first dopant;
etching to recess the first doped oxide layer and the second doped oxide layer, leaving a layer of the first doped oxide layer on the first fin as a first doped oxide spacer and a layer of the second doped oxide layer on the second fin as a second doped oxide spacer;
annealing, after etching to recess, by a thermal process and under conditions sufficient to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin, and to drive the first dopant into the substrate beneath the first fin and the second dopant into the substrate beneath the second fin;
removing the first doped oxide spacer from the first fin and the second doped oxide spacer from the second fin;
depositing an oxide between the first fin and the second fin; and
forming a first gate on the first fin and a second gate on the second fin.

US Pat. No. 10,249,535

FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming two gates across and perpendicular to first and second pairs of fins on a substrate;
forming first and second pairs of raised source/drain (RSD) between the two gates on the first and second pairs of fins, respectively;
forming a planar self-aligned contact (SAC) cap on each of the two gates;
forming a metal layer over the substrate coplanar with an upper surface of the SACs;
forming an oxide layer over the substrate subsequent to forming the metal layer;
forming a nitride layer over the oxide layer;
patterning the oxide and nitride layers, forming first and second oxide and nitride stacks above the first and second pairs of RSD, respectively, the first and second oxide and nitride stacks formed perpendicular to the two gates and each having with a width equal to or less than an overall width of a pair of fins;
etching the metal layer proximate to the oxide and nitride stacks forming trench silicide (TS) structure upper portions above the first and second pairs of RSD, and forming the TS structure in the metal layer over and perpendicular to the fins, the TS structure having first and second upper portions over the first and second pairs of RSD, respectively, each upper portion having a width equal to or less than an overall width of a pair of fins;
forming first and second spacers on opposite sides of the first and second upper portions, respectively;
removing the metal layer between adjacent first and second spacers;
forming an interlayer dielectric (ILD) over the substrate; and
forming a source/drain contact (CA) on each upper portion and a gate contact (CB) on one of the two gates through the ILD.

US Pat. No. 10,249,533

METHOD AND STRUCTURE FOR FORMING A REPLACEMENT CONTACT

International Business Ma...

1. A method for manufacturing a semiconductor device, comprising:forming a plurality of gate structures spaced apart from each other on a fin;
forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures;
forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures;
forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion;
removing a portion of the OPL to expose the inorganic plug portion;
selectively removing the inorganic plug portion; and
forming a contact on the fin in place of the removed inorganic plug portion.

US Pat. No. 10,249,532

MODULATING THE MICROSTRUCTURE OF METALLIC INTERCONNECT STRUCTURES

International Business Ma...

1. An apparatus, comprising:a single platform semiconductor processing chamber comprising a first sub-chamber, a second sub-chamber, a third sub-chamber, and a fourth sub-chamber, which is configured to process a substrate comprising a dielectric layer disposed on an upper surface of a substrate, wherein the dielectric layer comprises an opening etched in a surface of the dielectric layer;
wherein the first sub-chamber is configured to deposit a layer of metallic material to fill the opening and cover the surface of the dielectric layer with the metallic material;
wherein the second sub-chamber is configured to perform a furnace anneal process to reflow the layer of metallic material;
wherein the third sub-chamber is configured to deposit a stress control layer on the layer of metallic material subsequent to the furnace anneal process; and
wherein the fourth sub-chamber comprises a programmable hot plate, wherein the fourth sub-chamber is configured to perform a controlled thermal anneal process using the programmable hot plate to modulate a microstructure of the layer of metallic material from a first microstructure to a second microstructure while the stress control layer is disposed on the layer of metallic material, wherein the programmable hot plate is programmed to perform a controlled thermal anneal cycle with active heating and active cooling stages.

US Pat. No. 10,249,531

METHOD FOR FORMING METAL WIRING

Toshiba Memory Corporatio...

1. A method for forming a metal wiring, comprising:forming a first insulating layer on a substrate;
forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer;
patterning the second insulating layer to form a mask pattern;
etching the first insulating layer by a wet etching method using the mask pattern as a mask;
forming selectively a catalyst layer in a region where the first insulating layer is etched; and
forming a metal layer on the catalyst layer by an electroless plating method.

US Pat. No. 10,249,530

INTERLAYER DIELECTRIC FILM IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a fin on a substrate;
a gate structure disposed over the fin;
a doped strained region adjacent to the gate structure; and
a high temperature (HT) doped interlayer dielectric (ILD) layer disposed over the doped strained region, the HT doped ILD layer comprising dopant materials with a non-linear doping density throughout the HT doped ILD layer.

US Pat. No. 10,249,528

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. An integrated circuit, comprising:a first insulation layer, wherein a first trench penetrates the first insulation layer;
a bottom plate partly disposed on the first insulation layer and partly disposed in the first trench;
a first patterned dielectric layer disposed on the bottom plate, wherein at least a part of the first patterned dielectric layer is disposed in the first trench;
a medium plate disposed on the first patterned dielectric layer, wherein at least a part of the medium plate is disposed in the first trench, and wherein the bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor;
a second patterned dielectric layer disposed on the medium plate; and
a top plate disposed on the second patterned dielectric layer, wherein the medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor, and the bottom plate is electrically connected with the top plate, wherein the top plate is electrically separated from the medium plate, and the bottom plate is electrically separated from the medium plate.

US Pat. No. 10,249,527

METHOD OF MANUFACTURING FLEXIBLE DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a flexible display device, comprising:providing a flexible substrate;
forming a first bonding layer on an entire surface of the flexible substrate;
patterning the first bonding layer to form a first bonding pattern by a photolithographic process, the first bonding pattern enclosing a display area without touching a boundary of the flexible substrate and being a multilayer;
forming a second bonding layer on an entire surface of a rigid substrate;
patterning the second bonding layer to form a second bonding pattern by a photolithographic process, the second bonding pattern corresponding to the first bonding pattern and being a multilayer;
bonding the first and second bonding patterns together to provide a bonding pattern between the flexible substrate and the rigid substrate such that at least a portion of the flexible substrate is in contact with the rigid substrate in the display area;
forming at least one display device on the display area of the flexible substrate; and
removing the bonding pattern by a cutting process performed so as to separate the flexible substrate having the display device thereon from the rigid substrate.

US Pat. No. 10,249,526

SUBSTRATE SUPPORT ASSEMBLY FOR HIGH TEMPERATURE PROCESSES

Applied Materials, Inc., ...

1. An electrostatic chuck comprising:a ceramic body having a top surface and a bottom surface;
one or more heating elements disposed in the ceramic body;
one or more electrodes disposed in the ceramic body; and
a plurality of adapter objects bonded to the bottom surface of the ceramic body by a metal bond, wherein collectively the plurality of adapter objects form a plurality of distributed over the bottom surface of the ceramic body at a plurality of different distances from a center of a circle defined by the bottom surface of the ceramic body, and wherein the plurality of openings comprise a first opening that is to couple to a fastener to secure a base plate against the bottom surface of the ceramic body.

US Pat. No. 10,249,525

DYNAMIC LEVELING PROCESS HEATER LIFT

APPLIED MATERIALS, INC., ...

1. A substrate support assembly, comprising:a support member that supports a pedestal having a substrate support surface;
a carrier plate attached to the support member; and
a positioning system comprising:
a base plate; and
two or more servo motor assemblies that each comprise a motor and a linear actuator, the servo motor assemblies each having a first end coupled to the base plate, wherein each of the linear actuators move the carrier plate in a direction that is non-parallel to the substrate supporting surface.

US Pat. No. 10,249,524

CASSETTE HOLDER ASSEMBLY FOR A SUBSTRATE CASSETTE AND HOLDING MEMBER FOR USE IN SUCH ASSEMBLY

ASM IP Holding B.V., Alm...

1. A cassette holder assembly for holding a cassette for storing at least one semiconductor material substrate in an interior space accessible from a front end of the cassette, the cassette holder assembly comprising:a base plate for receiving the cassette; and,
a right and a left holding member supported by the base plate to position the cassette on the right and left respectively seen from the front,
wherein the right and left holding members are substantially identical to each other,
wherein each of the holding members has at least two end surface to engage with the cassette to limit a position of the cassette in the front to the back direction substantially parallel to the base plate, the at least two end surfaces comprising at least one right end surface and at least one left end surface whereby the right end surface is located at the right of the holding member and the left end surface is located at the left of the holding member seen from the front, and
wherein the right end surface of the right holding member and the left end surface of the left holding member are arranged for engagement with the cassette.

US Pat. No. 10,249,523

OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC

KLA-Tencor Corporation, ...

1. A method for sorting wafers utilizing a slope of shape metric, comprising:receiving a plurality of wafers;
acquiring a set of wafer shape values from a surface of each wafer at a selected process level;
generating a set of residual slope shape metrics for each wafer by calculating a residual slope shape metric at each of a plurality of points of each wafer;
determining a neutral surface of each wafer in a chucked state;
calculating a neutral surface factor (NSF) for each wafer utilizing the determined neutral surface for each wafer and a plurality of positions associated with a plurality of patterns of each wafer;
determining a set of pattern placement error (PPE) residual values for each wafer, the PPE residual value for each point for each wafer being a product of at least the calculated NSF for each wafer, the residual slope shape metric for the point, and a thickness of the wafer;
determining one or more thresholds for the set of residual shape metrics suitable for maintaining the set of PPE residuals below one or more selected levels;
monitoring each of the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer; and
modifying one or more wafer fabrication processes, responsive to the monitoring of each of the plurality of wafers, in order to maintain the generated set of residual slope shape metrics for each wafer below the one or more thresholds.

US Pat. No. 10,249,522

IN-SITU TEMPERATURE MEASUREMENT IN A NOISY ENVIRONMENT

APPLIED MATERIALS, INC., ...

1. A lift pin for a semiconductor processing chamber, the lift pin comprising:a light pipe disposed within a body of the lift pin; and
a cover over an end of the light pipe and configured to contact a substrate to transmit thermal energy from the substrate to the light pipe, wherein the cover is a thermally conductive material.

US Pat. No. 10,249,520

TRANSFER PRINTING USING ULTRASOUND

INNOVASONIC, Inc., Dubli...

1. A method of transferring an object from a donor substrate surface to a receiving substrate surface comprising:providing a transfer device having a one or more ultrasonic transducers and an elastomeric material disposed over said transducers;
providing a donor substrate having a donor surface, said donor surface having at least one or more objects;
contacting at least a portion of said transfer device with at least a portion of said donor substrate, said portion having an object;
separating said transfer device from a donor surface at a separation rate required for transfer of said object from the donor substrate surface to the transfer device, thereby forming said transfer surface having said object deposited thereon;
contacting at least a portion of said object disposed on said transfer surface with said receiving surface of said receiving substrate,
directing a pulse of ultrasonic energy from one or more ultrasonic transducers located in close vicinity of said object, and separating said transfer surface from said object, thereby transferring said object to said receiving substrate.

US Pat. No. 10,249,519

LIGHT-IRRADIATION HEAT TREATMENT APPARATUS

SCREEN Holdings Co., Ltd....

1. A heat treatment apparatus for heating a disk-shaped substrate by irradiating the substrate with light, comprising:a chamber that houses a substrate;
a holder that holds said substrate in said chamber;
a light irradiation part in which a plurality of rod-shaped lamps are arranged in a light source region that is larger than a major surface of said substrate held by said holder and that faces the major surface;
a cylindrical louver that is provided between said light irradiation part and said holder, with a central axis of said louver passing through a center of said substrate, and that is impervious to light emitted from said light irradiation part, and an outer diameter of said louver being smaller than said light source region; and
a light-shielding member that is provided between said light irradiation part and said holder and that is impervious to the light emitted from said light irradiation part,
wherein said light-shielding member has a cut-out portion that allows light to reach a region of said substrate that is shielded from the light emitted from said light irradiation part by said louver.

US Pat. No. 10,249,517

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus for processing a substrate, comprising:a substrate holder for holding a substrate in a horizontal position;
an opposing member that opposes an upper surface of said substrate and has an opposing-member opening in a central part;
an opposing-member moving mechanism for holding said opposing member and moving said opposing member relative to said substrate holder in an up-down direction between a first position and a second position that is below said first position;
a substrate rotation mechanism for rotating said substrate along with said substrate holder about a central axis pointing in said up-down direction;
a processing liquid nozzle for supplying a processing liquid to said upper surface of said substrate through said opposing-member opening; and
a gas supply part for supplying a treatment atmospheric gas to a space between said opposing member and said substrate,
wherein said opposing member includes:
an opposing-member body that opposes said upper surface of said substrate and has said opposing-member opening in the central part;
an opposing-member tubular part that has a tubular shape and protrudes upward from a periphery of said opposing-member opening of said opposing-member body and in which said processing liquid nozzle is inserted;
an opposing-member flange part that annularly extends radially outward from an upper end of said opposing-member tubular part and is held by said opposing-member moving mechanism; and
a first uneven part in which a recessed portion and a raised portion are alternately disposed concentrically on an upper surface of said opposing-member flange part,
said opposing-member moving mechanism includes:
a holder lower part that opposes a lower surface of said opposing-member flange part in said up-down direction;
a holder upper part that opposes said upper surface of said opposing-member flange part in said up-down direction; and
a second uneven part in which a recessed portion and a raised portion are alternately disposed concentrically on a lower surface of said holder upper part,
in a state in which said opposing member is located at said first position, said opposing-member flange part is supported from below by said holder lower part, and said opposing member is held by said opposing-member moving mechanism and spaced above said substrate holder, and
in a state in which said opposing member is located at said second position, said opposing member is spaced from said opposing-member moving mechanism, is held by said substrate holder, and is rotatable along with said substrate holder by said substrate rotation mechanism, a labyrinth is formed as a result of the raised portion of one of said first uneven part and said second uneven part being disposed within the recessed portion of the other of said first uneven part and said second uneven part with a gap therebetween, and a seal gas is supplied to said labyrinth to seal a nozzle gap from a space located on the radially outer side of said labyrinth, said nozzle gap being a space between said processing liquid nozzle and said opposing-member tubular part.

US Pat. No. 10,249,516

UNDERFILL DISPENSING USING FUNNELS

International Business Ma...

1. A method for underfilling an array of objects on a substrate, comprising:forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate; and
curing the void-free layer of underfill material to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

US Pat. No. 10,249,515

ELECTRONIC DEVICE PACKAGE

Intel Corporation, Santa...

1. An electronic device package, comprising:a substrate;
an electronic component disposed on the substrate and electrically coupled to the substrate; and
an underfill material disposed at least partially between the electronic component and the substrate, wherein a lateral portion of the underfill material comprises an exposed lateral surface extending away from the substrate and intersecting a meniscus surface extending between the lateral surface and the electronic component, wherein a height of the lateral surface from the substrate is greater than a length of the meniscus surface, and wherein the lateral surface comprises an irregular surface that has a concavity from an upper surface of the substrate.

US Pat. No. 10,249,512

TUNABLE TIOXNY HARDMASK FOR MULTILAYER PATTERNING

INTERNATIONAL BUSINESS MA...

1. A multilayer lithographic structure comprisingan organic planarizing layer;
a titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride layer has an extinction coefficient less than 1.0 over a wavelength range from 400 nm to 800 nm and is configured to have an etch rate greater than 2 nm per minute in a wet etch solution comprising ammonium hydroxide, hydrogen peroxide and water at a temperature of 20° C.; and
a photosensitive resist layer on the titanium oxynitride layer.

US Pat. No. 10,249,511

CERAMIC SHOWERHEAD INCLUDING CENTRAL GAS INJECTOR FOR TUNABLE CONVECTIVE-DIFFUSIVE GAS FLOW IN SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS

LAM RESEARCH CORPORATION,...

1. An inductively coupled plasma processing apparatus comprising:a vacuum chamber;
a vacuum source adapted to exhaust the vacuum chamber;
a substrate support comprising a lower electrode on which a single semiconductor substrate is supported in an interior of the vacuum chamber;
a ceramic showerhead which forms an upper wall of the vacuum chamber wherein the ceramic showerhead includes a gas plenum in fluid communication with a plurality of showerhead gas outlets in a plasma exposed surface thereof for supplying a process gas as a diffusive gas flow to the interior of the vacuum chamber, a central opening in the ceramic showerhead that extends an entire thickness of the ceramic showerhead and the ceramic showerhead including a lower vacuum sealing surface which surrounds the plasma exposed surface and forms a vacuum seal with a vacuum sealing surface of the vacuum chamber;
a central gas injector disposed in the central opening of the ceramic showerhead, wherein the central gas injector includes one or more gas injector outlets, in a surface thereof that is exposed inside the vacuum chamber, for supplying the process gas as a convective gas flow to the interior of the vacuum chamber at least in a direction towards a center of the semiconductor substrate, wherein
the one or more gas injector outlets include a plurality of central gas outlets, wherein the plurality of central gas outlets are arranged to supply the process gas as the convective gas flow directly from the central gas injector into the vacuum chamber without passing through the gas plenum of the ceramic showerhead, and
the one or more gas injector outlets include a plurality of radial gas outlets arranged radially outward of the plurality of central gas outlets, wherein the plurality of radial gas outlets are arranged to supply the process gas as the diffusive gas flow radially outward from the central gas injector into the gas plenum of the ceramic showerhead and through the plurality of showerhead gas outlets;
an RF energy source which inductively couples RF energy through the ceramic showerhead and into the vacuum chamber to energize the process gas into a plasma state to process the semiconductor substrate; and
a control system configured to (i) control supply of the process gas as the convective gas flow through the central gas outlets via a first gas line at a first flow rate and (ii) control supply of, independently of the convective gas flow, the process gas as the diffusive gas flow through the showerhead gas outlets via a second gas line at a second flow rate, wherein the convective gas flow and the diffusive gas flow are supplied simultaneously, and wherein, to control the supply of the convective gas flow and the diffusive gas flow, the control system is further configured to select and control a pressure within the vacuum chamber, the first flow rate, and the second flow rate based on a desired eddy current above the semiconductor substrate, wherein, to achieve the desired eddy current, the control system is configured to independently control the first flow rate and the second flow rate.

US Pat. No. 10,249,508

METHOD FOR PREVENTING EXCESSIVE ETCHING OF EDGES OF AN INSULATOR LAYER

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:forming a first semiconductor layer on a semiconductor substrate;
forming a first insulator layer on the first semiconductor layer exposing an edge portion of the first semiconductor layer;
forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer;
forming a second insulator layer as a spacer on the exposed portion of the first insulator layer;
performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer.

US Pat. No. 10,249,507

METHODS FOR SELECTIVE ETCHING OF A SILICON MATERIAL

Applied Materials, Inc., ...

1. A method for etching features in a silicon material, the method comprising:performing a remote plasma process in a processing chamber formed from an etching gas mixture including chlorine containing gas to remove a silicon material disposed on a substrate, wherein the remote plasma process is configured to generate a remote plasma externally from an interior volume defined in the processing chamber without applying a RF source power to the processing chamber.

US Pat. No. 10,249,504

ETCHING AND MECHANICAL GRINDING FILM-LAYERS STACKED ON A SEMICONDUCTOR SUBSTRATE

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:wet-etching a first film layer of a plurality of film layers stacked on a first side of a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, wherein the first film layer is an outermost film layer stacked on the semiconductor substrate;
wet-etching a second film layer of the plurality of film layers using a second chemical; and
using a mechanical grinding wheel to grind the semiconductor substrate from the first side to reduce a thickness of the semiconductor substrate.

US Pat. No. 10,249,501

SINGLE PROCESS FOR LINER AND METAL FILL

International Business Ma...

1. A semiconductor structure comprising a gate structure, the gate structure comprising:a gate dielectric located along inner sidewalls of a gate spacer and a top surface and sidewalls of a channel region of a semiconductor fin located over a substrate;
a workfunction metal liner located on, and in direct physical contact with, the gate dielectric;
a first metal liner located on, and in direct physical contact with, the workfunction metal liner;
a second metal liner located on, and in direct physical contact with, the first metal liner; and
a metal gate electrode located on, and in direct physical contact, with the second metal liner, wherein the metal gate electrode is composed entirely of an alloy selected from the group consisting of MgAl, MgTi, MgV and AlV, the first metal liner is composed entirely of a carbide of the alloy that forms the metal gate electrode and the second metal liner is composed entirely of a nitride of the alloy that forms the metal gate electrode.

US Pat. No. 10,249,499

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A THIN SEMICONDUCTOR WAFER

ABB Schweiz AG, Baden (C...

1. A method for manufacturing a vertical power semiconductor device, wherein the method comprises the following steps:(a) providing a semiconductor wafer having a first main side and a second main side opposite to the first main side;
(b) applying a first impurity onto the first main side;
(c) forming a first oxide layer on at least the first main side of the semiconductor wafer;
(d) after step (c) bonding a carrier wafer to the first oxide layer on the first main side of the semiconductor wafer;
(e) after the bonding step (d) front-end-of-line processing on the second main side of the semiconductor wafer;
(f) after the front-end-of-line processing step (e) at least partially removing the carrier wafer and the first oxide layer on the first main side of the semiconductor wafer; and
(g) after the removing step (f) forming a back metallization layer on the first main side of the semiconductor wafer to form an Ohmic contact to the semiconductor wafer,
wherein
in step (c) partially doping the first oxide layer formed on the first main side of the semiconductor wafer with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer,
in step (e) diffusing the second impurity from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing,
in step (f) completely removing the carrier wafer and the first oxide layer on the first main side of the semiconductor wafer.

US Pat. No. 10,249,497

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device comprising:a silicon carbide semiconductor base of a first conductivity type;
a gate insulating film provided on a front surface of the silicon carbide semiconductor substrate and including any one or a plurality of an oxide film, a nitride film, and an oxynitride film; and
a gate electrode containing poly-silicon and provided on the gate insulating film, wherein
the gate insulating film has an interface state terminated by hydrogen or hydroxyl groups, wherein the hydrogen or the hydroxyl groups terminating the interface state is replaced with fluorine, and
a concentration of fluorine in the silicon carbide semiconductor device has a first peak and a second peak,
the first peak is in the gate electrode and is equal to or lower than 1×1018 atoms/cm3 and the second peak is in the gate insulating film and is equal to or higher than 1×1019 atoms/cm3.

US Pat. No. 10,249,496

NARROWED FEATURE FORMATION DURING A DOUBLE PATTERNING PROCESS

GLOBALFOUNDRIES Inc., Gr...

1. An interconnect structure comprising:a first interconnect having a first width and a cut extending through the first interconnect across the first width; and
a second interconnect having a first section with the first width, a second section with the first width, and a third section arranged between the first section and the second section,
wherein the third section of the second interconnect has a second width that is less than the first width.

US Pat. No. 10,249,495

DIAMOND LIKE CARBON LAYER FORMED BY AN ELECTRON BEAM PLASMA PROCESS

Applied Materials, Inc., ...

1. A method of forming a diamond like carbon layer, comprising:generating an electron beam plasma above a surface of a substrate disposed in a processing chamber, generating the electron beam plasma comprising:
applying a first RF source power to an electrode disposed in the processing chamber; and
bombarding the electrode to provide secondary electrons and a secondary electron beam flux to the surface of the substrate; and
forming a diamond like carbon layer on the surface of the substrate disposed in the processing chamber.