US Pat. No. 10,771,160

LASER MODULE FOR OPTICAL DATA COMMUNICATION SYSTEM

Ayar Labs, Inc., Santa C...

1. A laser module, comprising:a plurality of lasers configured to respectively generate and output a plurality of laser beams, the plurality of laser beams having different wavelengths relative to each other, the different wavelengths distinguishable to an optical data communication system; and
an optical marshalling module configured to receive the plurality of laser beams as respectively generated and output by the plurality of lasers, the optical marshalling module configured to distribute a portion of each of the plurality of laser beams as respectively generated and output by the plurality of lasers to each of a plurality of optical output ports of the optical marshalling module, such that all of the different wavelengths of the plurality of laser beams are provided to each of the plurality of optical output ports of the optical marshalling module, wherein the optical marshalling module is a passive component,
wherein the optical marshalling module includes either a star coupler or a butterfly waveguide network or a combination of a wavelength combiner and a broadband power splitter,
wherein the star coupler is configured to receive the plurality of laser beams and distribute portions of each of the plurality of laser beams to each of the plurality of optical output ports of the optical marshalling module,
wherein the butterfly waveguide network is configured to receive the plurality of laser beams and distribute portions of each of the plurality of laser beams to each of the plurality of optical output ports of the optical marshalling module,
wherein the wavelength combiner is configured to combine the plurality of laser beams into a multi-wavelength laser beam, and the broadband power splitter is configured to distribute portions of a total power of the multi-wavelength laser beam to each of the plurality of optical output ports of the optical marshalling module.

US Pat. No. 10,771,159

FIBER OPTIC PATCH AND VOLTAGE CONDITIONING

iSenseClound, Inc., San ...

20. An apparatus, comprising:a fiber optic voltage conditioner coupled for optical communication to a fiber optic cable having a Fiber Bragg Grating sensor; and
the fiber optic voltage conditioner, including a tunable light source having a broadband light source, an optical circulator, and a tunable reflection filter, configured to provide a narrowband light signal from a broadband light signal for providing to the fiber optic cable;
wherein:
the optical circulator is coupled to the broadband light source to receive a broadband light beam and to the tunable reflection filter to receive a reflected tuned light signal; and
the optical circulator is configured to provide a narrowband light beam.

US Pat. No. 10,771,157

MOBILE TERMINAL AND METHOD FOR RECEIVING AND SENDING A LIFI SIGNAL THEREOF

Xiamen Tianma Micro-Elect...

13. The method of claim 10, wherein the first LIFI signal comprises a logic high level signal and a logic low level signal, wherein the logic high level signal corresponds to 1 in binary code and the logic low level signal corresponds to 0 in the binary code; and the method comprises:emitting, by the at least two of the plurality of light emitting elements in the display device, the logic high level signal and/or the logic low level signal at a current moment to emit the first LIFI signal, wherein the first LIFI signal corresponds to an item of binary code information in a two-dimensional space.

US Pat. No. 10,771,155

INTELLIGENT VISIBLE LIGHT WITH A GALLIUM AND NITROGEN CONTAINING LASER SOURCE

Soraa Laser Diode, Inc., ...

1. A light source configured for visible light communication, comprising:a controller comprising a modem and a driver, the modem being configured to receive a data signal, wherein the controller is configured to generate one or more control signals to operate the driver to generate a driving current and a modulation signal based on the data signal;
a light emitter configured as a pump-light device comprised of a gallium and nitrogen containing material and an optical cavity; the optical cavity comprising an optical waveguide region and one or more facet regions, wherein the optical cavity is configured with electrodes to supply the driving current based on at least one of the one or more control signals to the gallium and nitrogen containing material, wherein the driving current provides an optical gain to an electromagnetic radiation propagating in the optical waveguide region, wherein the electromagnetic radiation is outputted through at least one of the one or more facet regions as a directional electromagnetic radiation characterized by a first peak wavelength in ultra-violet or blue wavelength regime, wherein the directional electromagnetic radiation is modulated to carry the data signal using the modulation signal provided by the driver;
a pathway configured to direct, filter, or split the directional electromagnetic radiation;
a wavelength converter optically coupled to the pathway to receive the directional electromagnetic radiation from the pump-light device, wherein the wavelength converter is configured to convert at least a fraction of the directional electromagnetic radiation with the first peak wavelength to at least a second peak wavelength that is longer than the first peak wavelength and to output a white-color spectrum comprising at least the second peak wavelength and partially the first peak wavelength;
a beam shaper mechanism configured to modify an angular distribution of the white-color spectrum; and
a beam steering mechanism configured to scan the white-color spectrum for illuminating multiple target areas in a selected period of time and to direct at least the fraction of the directional electromagnetic radiation with the first peak wavelength for transmitting the data signal to receivers at the multiple target areas.

US Pat. No. 10,771,154

METHOD FOR OPERATING A NON-TRACK-BOUND COLUMN OF VEHICLES AND DRIVER ASSISTANCE SYSTEM AND NON-TRACK BOUND COLUMN

KNORR-BREMSE SYSTEME FUER...

1. A method for operating a non-track-bound convoy, the method comprising:providing that at least one vehicle, which is directly following a vehicle traveling ahead, follows the vehicle traveling ahead by an automatic open-loop/closed-loop control, wherein the convoy has the at least one vehicle traveling ahead and the at least one vehicle that is contactlessly coupled to the vehicle traveling ahead and directly following the vehicle traveling ahead, in an automated manner; and
effecting a car-to-car communication between the vehicle traveling ahead and the at least one vehicle directly following the vehicle traveling ahead for the automatic open-loop/closed-loop control;
wherein a photo-optical, an optical-waveguide-less or an optical-fiber-less car-to-car communication is effected in each case between a light wave emitter and a light wave receiver for at least part of the car-to-car communication,
wherein the automatic open-loop/closed-loop control is for speed, steering, lane keeping, and braking, and includes at least an adaptive cruise control (“ACC”) system,
wherein light signals modulated by an electro-optical modulator are generated, output into a free space between two directly successive vehicles of the convoy by the light wave emitter, received by the light wave receiver, and evaluated by an electro-optical demodulator,
wherein the at least one electro-optical modulator is integrated in an electronic control unit of the vehicle traveling ahead and the electro-optical demodulator is integrated in an electronic control unit of the at least one vehicle directly following the vehicle traveling ahead,
wherein the photo-optical communication between the vehicle traveling ahead and the at least one vehicle directly following the vehicle traveling ahead is provided bidirectionally, and
wherein a combination of at least two light spectra, including infrared, ultraviolet and/or visible light, is used in the photo-optical communication to increase a transmission bandwidth.

US Pat. No. 10,771,153

OPTICAL POWER MEASUREMENT APPARATUS

AFL TELECOMMUNICATIONS LL...

12. An apparatus for measuring optical power, the apparatus comprising:a first combination multiplexer and demultiplexer component in optical communication between a first composite optical waveguide and at least a first intermediate optical waveguide and a second intermediate optical waveguide, wherein the first intermediate optical waveguide carries a first optical signal associated with a first wavelength in a first direction, and wherein the second intermediate optical waveguide carries a second optical signal associated with a second wavelength different from the first wavelength in a second direction that is opposite to the first direction, wherein the first combination multiplexer and demultiplexer component provides isolation levels comprising a first isolation level at the first wavelength and a second isolation level different from the first isolation level at the second wavelength;
a second combination multiplexer and demultiplexer component in optical communication between a second composite optical waveguide and at least the first intermediate optical waveguide and the second intermediate optical waveguide, wherein the second combination multiplexer and demultiplexer component provides isolation levels which are complementary to the isolation levels of the first component;
a first optical coupler positioned along the first intermediate optical waveguide, the first optical coupler configured to split a portion of the first optical signal from the first intermediate optical waveguide;
a second optical coupler positioned along the second intermediate optical waveguide, the second optical coupler configured to split a portion of the second optical signal from the second intermediate optical waveguide;
a first photodetector in optical communication with the first optical coupler to receive the portion of the first optical signal split from the first intermediate optical waveguide, the first photodetector comprising a band-pass filter;
a second photodetector in optical communication with the second optical coupler to receive the portion of the second optical signal split from the second intermediate optical waveguide, the second photodetector comprising a band-pass filter;
a first measurement device configured to measure the first optical signal from the first photodetector; and
a second measurement device configured to measure the second optical signal from the second photodetector.

US Pat. No. 10,771,152

SYSTEM AND METHOD FOR OPTICAL SYSTEM MARGIN ALLOCATION

Fujitsu Limited, Kawasak...

1. A method for optical margin allocation, the method comprising:obtaining, by an optical controller, optical network topology information of an optical network;
generating, based on the optical network topology information, an optical model to represent the optical network;
provisioning, by the optical controller, a new optical connection within the optical network:
in response to provisioning the new optical connection:
determining, using the optical model, a first bit error rate (BER) of the new optical connection of the optical network;
determining, using the optical network providing the new optical connection, a second BER of the new optical connection;
determining, based on the first BER and the second BER, a BER excursion parameter of the new optical connection;
training, by the optical controller, a margin allocator comprising a recurrent neural network (RNN) based on the BER excursion parameter of the new optical connection, and the first BER of the new optical connection;
comparing the first BER of the new connection and a required optical margin to a threshold to determine a reliability of the new optical connection; and
allocating, using the margin allocator, the required optical margin for additional optical connections of the optical network.

US Pat. No. 10,771,150

PARALLEL PROCESSING APPARATUS AND REPLACING METHOD OF FAILING OPTICAL TRANSMISSION LINE

FUJITSU LIMITED, Kawasak...

1. A parallel processing apparatus comprising:information processing apparatuses coupled mutually through an optical transmission line having a plurality of channels, wherein each of the information processing apparatuses has
a plurality of processors that shares the optical transmission line having the plurality of channels allocated to the plurality of processors;
a controller coupled to the information processing apparatus; and
a display provided correspondingly to the optical transmission line,
wherein when a first processor of the plurality of processors detects a failure of a channel, the first processor notifies the channel failure to a second processor of the plurality of the processors of the another information processing apparatus by using a channel that is not failed, notifies the channel failure to the controller of the information processing apparatus and, when the first processor receives a notification of the channel failure from the another information processing apparatus, notifies the channel failure to the controller of the information processing apparatus, and
wherein the controller of each of the information processing apparatuses detects a processor of the information processing apparatus using a failing optical transmission line including the failing channel based on reception of the notification of the channel failure, causes the detected processor to stop use of the failing optical transmission line, and, based on the stop of the use of the failing optical transmission line by the detected processor, sets the display corresponding to the failing optical transmission line to have a stop indication state indicating that communication through the failing optical transmission line has stopped.

US Pat. No. 10,771,149

COMMUNICATION BYPASS APPARATUS, METHOD AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM

FUJITSU LIMITED, Kawasak...

1. An information processing apparatus comprising:a first node device;
a second node device; and
a control device configured to control data transmission between the first node device and the second node device, the control device being coupled to the first node device through a first path group including a plurality of paths and being coupled to the second node device through a second path group including a plurality of paths, the control device including:
a memory; and
a processor coupled to the memory and configured to:
perform a communication test of the first path group and the second path group; and
when a first failure is detected in a first path in the first path group in the communication test, couple a third path other than the first path in the first path group with the first node device, couple a second path in the second path group with the second node device, and couple the third path and the second path with each other;
when a second failure is detected in the second path in the communication test, couple the third path with the first node device, couple a fourth path other than the second path in the second path group with the second node device, and couple the third path and the fourth path with each other;
transmit, to the first node device, a first instruction signal instructing the first node device to couple the third path and the first node device with each other, and
transmit, to the second node device, a second instruction signal instructing the second node device to couple the fourth path and the second node device with each other.

US Pat. No. 10,771,148

SYSTEMS AND METHODS FOR PROVIDING REMOTE L-BAND SMART ANTENNAS

1. An avionics system, comprising:an antenna having at least a radio frequency function included therewith; and
a data bus connecting the antenna to a digital receiver at avionics processing hardware.

US Pat. No. 10,771,147

SATELLITE COMMUNICATION SYSTEM FOR DIVERSITY GATEWAY SWITCHING AND SATELLITE COMMUNICATION METHOD FOR DIVERSITY GATEWAY SWITCHING

HUGHES NETWORK SYSTEMS LL...

1. A satellite communication system comprising:a communication terminal;
a ground station configured to communicate with the communication terminal through a satellite communication path between the ground station and the communication terminal via a satellite, the ground station including
a diversity switch configured to switch the satellite communication path from a first satellite communication path to a second satellite communication path different from the first satellite communication path, and
an electronic controller configured to determine whether a predetermined switching condition is satisfied based on signal attenuations of the first and second satellite communication paths, the electronic controller being further configured to control the diversity switch to switch the satellite communication path upon elapsing a first predetermined time period after determining that the predetermined switching condition is satisfied;
a first radio frequency transceiver located between the ground station and the satellite on the first satellite communication path; and
a second radio frequency transceiver located between the ground station and the satellite on the second satellite communication path, the second radio frequency transceiver being located away from the first radio frequency transceiver,
the electronic controller being further configured to obtain, as the signal attenuations of the first and second satellite communication paths, signal fade of downlink beacon that has been broadcasted by the satellite and received by the first and second radio frequency transceivers on the first and second satellite communication paths, respectively.

US Pat. No. 10,771,146

REDUNDANCY FOR SATELLITE UPLINK FACILITIES USING SOFTWARE-DEFINED NETWORKING

1. A satellite network system comprising: a video collection facility; a remote uplink facility; a diverse uplink facility in direct communication with a core network; and a software-defined networking (“SDN”) controller that operates in an SDN network that provides logical SDN links to the video collection facility, the remote uplink facility, the diverse uplink facility, and the core network, wherein the SDN controller comprises a processor, and a memory that stores instructions that, when executed by the processor, cause the processor to perform operations comprising tracking a site configuration of the remote uplink facility, detecting that the remote uplink facility has been downed due to an adverse event, obtaining the site configuration of the remote uplink facility, causing a redundant remote uplink facility to be instantiated, and causing the redundant remote uplink facility to be configured in accordance with the site configuration of the remote uplink facility, wherein the site configuration comprises a network configuration of the remote uplink facility to be configured for the redundant remote uplink facility, and wherein the network configuration specifies network connectivity between the remote uplink facility, the video collection facility, the diverse uplink facility, and the core network.

US Pat. No. 10,771,145

POWER EFFICIENCY IN BEAMFORMING RF SYSTEMS

SEAKR ENGINEERING, INC., ...

1. A system for improving the power efficiency of communications satellites having an array of RF receive antenna elements, the system comprising:a beamformer configured to generate a plurality of beamformed signals based on a plurality of input signals received via the RF receive antenna elements;
a plurality of power amplifiers configured to amplify a first plurality of signals corresponding to the plurality of beamformed signals;
an array of transmit antenna elements, wherein each transmit antenna element is configured to transmit an RF signal based on an output of one of the power amplifiers; and
an intermodulation decorrelator configured to decorrelate intermodulation products of the plurality of input signals, or decorrelate intermodulation products of the plurality of beamformed signals, prior to conversion of the plurality of input or beamformed signals from linear signals to nonlinear signals.

US Pat. No. 10,771,144

CONCURRENT USES OF NON-CELLULAR INTERFACES FOR PARTICIPATING IN HYBRID CELLULAR AND NON-CELLULAR NETWORKS

M87, INC., Austin, TX (U...

1. Non-transitory computer-readable storage media encoded with a computer program including instructions when executed by a processor of a wireless device to create an application for operating the wireless device in a hybrid, multi-hopping wireless communication network, the application comprising:a) a first software module automatically and dynamically configuring common resources of a non-cellular interface to simultaneously create a first non-cellular virtual interface and a second non-cellular virtual interface for relaying a cellular communication between a downstream wireless device and an upstream wireless device, wherein configuring the common resources of the non-cellular interface comprises controlling and scheduling the common resources to simultaneously execute different tasks of the first non-cellular virtual interface and the second non-cellular virtual interface,
wherein the different tasks include: establishing by the first non-cellular virtual interface, without intermediary device, a first wireless link between the first non-cellular virtual interface and the downstream wireless device by sending a hopping request, establishing by the second non-cellular virtual interface, without intermediary device, a second wireless link between the second non-cellular virtual interface and the upstream wireless device by sending a hopping request, and relaying the cellular communication which comprises:
1) establishing and maintaining, by the first non-cellular virtual interface, the first wireless link between the first non-cellular virtual interface and the downstream wireless device using a first protocol;
2) establishing and maintaining, by the second non-cellular virtual interface, the second wireless link between the second non-cellular virtual interface and the upstream wireless device using a second protocol different from the first protocol, wherein the first protocol and the second protocol are different non-cellular wireless protocols determined based on the first virtual non-cellular virtual interface and the second virtual non-cellular virtual interface, and wherein the first protocol and the second protocol are different data link layer protocols;
3) establishing and maintaining an internal transfer between the first and the second wireless links, wherein the internal transfer comprises:
i) reassembling one or more data frames received from the downstream wireless device into a format defined by the second protocol used in the second wireless link,
ii) reassembling one or more data frames received from the upstream wireless device into a format defined by the first protocol used in the first wireless link, and
iii) forwarding one or more reassembled data frames to the downstream wireless device or the upstream wireless device; and
4) requesting, by the second non-cellular virtual interface via the second wireless link between the second non-cellular virtual interface and the upstream wireless device, the upstream wireless device to establish and maintain a cellular communication between the upstream wireless device and a cellular base station; and
b) a second software module configuring a beacon interface for transmitting or receiving one or more beacon signals.

US Pat. No. 10,771,142

SYSTEM AND METHOD FOR HIERARCHAL BEAMFORMING AND RANK ADAPTATION FOR HYBRID ANTENNA ARCHITECTURE

Futurewei Technologies, I...

1. A method comprising:receiving, by a user equipment (UE), first beamformed reference signals;
transmitting, by the UE, a first report that indicates at least one reference signal index based on the first beamformed reference signals;
receiving, by the UE, at least a second beamformed reference signal after transmitting the first report;
transmitting, by the UE, a second report that includes a precoding matrix indicator derived from the second beamformed reference signal; and
receiving, by the UE, a beamformed data signal after transmitting the second report.

US Pat. No. 10,771,141

METHOD FOR CHANNEL STATE REPORT IN WIRELESS COMMUNICATION SYSTEM, AND DEVICE THEREFOR

LG Electronics Inc., Seo...

1. A method for reporting channel state based on an aperiodic Channel State Information-Reference Signal (CSI-RS) in a wireless communication system, the method comprising:receiving a physical downlink control channel (PDCCH) for scheduling a physical uplink shared channel (PUSCH), the PDCCH including an aperiodic Channel State Information (CSI) request; and
transmitting, through the PUSCH, CSI based on the aperiodic CSI-RS at a timing corresponding to one of a plurality of candidate values according to the aperiodic CSI request,
wherein the plurality of the candidate values are selected according to a CSI relevant parameter,
wherein the CSI relevant parameter comprises at least one selected from the group consisting of a type of information included in the CSI, frequency granularity of the CSI, information about whether or not to use a codebook in case of deriving the CSI, and the number of antenna ports of the CSI-RS, and
wherein a plurality of timing groups are defined for the CSI relevant parameter each and wherein one or more candidate values are defined per timing group.

US Pat. No. 10,771,139

APPARATUS AND METHOD FOR PROVIDING EFFICIENT BEAMFORMING FEEDBACK

Samsung Electronics Co., ...

1. An apparatus for a beamformee, comprising:a first beamforming matrix device configured to generate a first beamforming matrix VWB from a channel H;
an equivalent channel device configured to generate an equivalent channel Hk based on the channel H and the first beamforming matrix VWB, where k is a number that indicates a subcarrier index;
a second beamforming matrix device configured to obtain a second beamforming matrix VSC from the equivalent channel Hk; and
a transmitter configured to transmit the first beamforming matrix VWB and the second beamforming matrix VSC.

US Pat. No. 10,771,137

SIGNAL CANCELLATION IN RADIO FREQUENCY (RF) DEVICE NETWORK

MOVANDI CORPORATION, New...

1. A system, comprising:one or more circuits in a programmable active reflector (AR) device associated with a first radio frequency (RF) device and a second RF device, wherein the one or more circuits are configured to:
receive a request and associated metadata from the second RF device via a receiver antenna array, wherein the request is based on a detected presence of noise that exceeds a threshold noise level;
receive one or more antenna control signals from the first RF device based on the received request and associated metadata,
wherein the programmable AR device is selected and controlled by the first RF device based on a set of criteria; and
transmit, via a transmitter antenna array, a controlled plurality of RF signals based on the associated metadata to the second RF device within a transmission range of the programmable AR device,
wherein the controlled plurality of RF signals are cancelled at the second RF device based on the associated metadata.

US Pat. No. 10,771,136

OVERLAID-CODED BEAMFORMING

TELEFONAKTIEBOLAGET LM ER...

1. A method for radio communication between a transmitting node and a plurality of receiving nodes, wherein said method comprises:determining a beamforming solution comprising a set of beamforming weights that define a directional beam covering respective directions associated with individual receiving nodes in a set of receiving nodes, the beamforming solution being one of an analog beamforming solution, a hybrid beamforming solution, and a constrained beamforming solution;
forming, via overlay coding, a combined signal stream from individual data streams, each individual data stream corresponding to a respective one in the set of receiving nodes, and each individual data stream encoded into the combined signal stream according to at least one of a respective code-domain overlaid code or a respective frequency-domain overlaid code, such that the individual data streams are separable from the combined signal stream in at least one of the frequency domain and the code domain; and
transmitting a beamformed radio signal according to the beamforming solution, the beamformed radio signal conveying the combined signal stream, for reception by each of the receiving nodes in the set of receiving nodes.

US Pat. No. 10,771,135

APPARATUS AND METHOD FOR ESTABLISHING AND MAINTAINING A COMMUNICATIONS LINK

The Johns Hopkins Univers...

1. An apparatus for establishing a communications link with a device transmitting a source signal, the apparatus comprising:a phased array antenna having a directional operating range;
a position sensor configured to generate position data indicative of a position of the phased array antenna, the position data including pitch, roll, and yaw data;
a radio frequency beamformer, wherein the radio frequency beamformer is in operable communication with the phased array antenna to control a direction of an antenna beam generated by the phased array antenna; and
a processor in operable communication with the radio frequency beamformer and configured to operate as an antenna controller, the processor configured to:
direct the radio frequency beamformer to steer the antenna beam in a plurality of beam directions across the directional operating range of the phased array antenna;
determine a signal strength of the source signal received by the phased array antenna for each beam direction of the plurality of beam directions;
determine a current beam direction, the current beam direction being a beam direction associated with a highest signal strength of the source signal received for the plurality of beam directions;
direct the radio frequency beamformer to steer the antenna beam to the current beam direction;
establish a communications link with the device transmitting the source signal with the antenna beam at the current beam direction; and
track movement of the source signal to maintain the communications link by directing the radio frequency beamformer to adjust the current beam direction of the phased array antenna based on the pitch, roll, and yaw data provided by the position sensor.

US Pat. No. 10,771,134

ELECTRONIC DEVICE AND WIRELESS COMMUNICATION METHOD

SONY CORPORATION, Tokyo ...

1. An electronic equipment, comprising:a processing circuit configured to select, in accordance with a channel matrix of a Multi-Input Multi-Output (MIMO) system, a modulation code book from a modulation code book cluster used for the MIMO system, wherein the modulation code book cluster comprises a plurality of modulation code books used for generating a modulated signal by a transmitting side equipment corresponding to the electronic equipment and whose number of data flows transmitted after modulation is bigger than the number of an orthogonal channel; and
a transceiver circuit configured to transmit feedback information to the transmitting side equipment, the feedback information comprising identification information of the selected modulation code book.

US Pat. No. 10,771,133

SIGNAL TRANSMISSION METHOD AND APPARATUS

GUANGDONG OPPO MOBILE TEL...

1. A method of transmitting a signal, comprising:determining, by a first device, a first numerology used to transmit a signal;
determining, by the first device, a first precoding granularity which is used to transmit the signal based on the first numerology; and
performing, by the first device, communication of the signal with a second device using the first precoding granularity,
wherein determining, by the first device, the first precoding granularity which is used to transmit the signal based on the first numerology, further comprises:
determining the first precoding granularity based on a first bandwidth and the first numerology,
wherein the first bandwidth is a system bandwidth or a bandwidth occupied for transmitting the signal; and
wherein determining the first precoding granularity based on a first bandwidth and the first numerology, comprises:
determining the first precoding granularity based on the first numerology, the first bandwidth and a second correspondence,
 wherein the second correspondence indicates an association of at least one bandwidth, at least one numerology and at least one precoding granularity.

US Pat. No. 10,771,132

TRANSMITTER, RECEIVER, AND SEMICONDUCTOR CHIP

NIPPON HOSO KYOKAI, Shib...

1. A transmitter that generates OFDM signals to be transmitted through a plurality of transmit antennas, comprising:a data distributor that distributes data to each of the transmit antennas;
a mapper that maps the data distributed by the data distributor, onto an IQ plane, to generate carrier-modulated carrier symbols;
an inter-polarization interleaver that rearranges an order of the plurality of the carrier symbols between polarizations corresponding to the plurality of the transmit antennas to generate inter-polarization interleaved data for each of the plurality of the transmit antennas;
a time interleaver that applies an interleave processing in a time direction to the inter-polarization interleaved data for each of the transmit antennas to generate time-interleaved data;
wherein the inter-polarization interleaver decomposes the plurality of carrier symbols into I data and Q data, which are respectively arranged on the I coordinate axis and the Q coordinate axis on the IQ plane, and thereafter, rearranges the orders of the I data and the Q data between the transmit antennas according to a predetermined rule, in units of the I data and the Q data to generate the inter-polarization interleaved data; and
an OFDM output processor that generates OFDM signals corresponding to the inter-polarization interleaved data.

US Pat. No. 10,771,131

SPLIT PRECODING AND SPLIT PREFILTERING BETWEEN A CENTRAL UNIT AND A DISTRIBUTED UNIT OF A GENERATION NODE-B (GNB)

Apple Inc., Cupertino, C...

1. An apparatus of a generation node B (gNB), the apparatus comprising:processing circuitry; and
memory, the gNB configured with logical nodes including a gNB central unit (gNB-CU) and a gNB distributed unit (gNB-DU), the gNB-CU configured to communicate with the gNB-DU over an F1 interface, the processing circuitry configured to:
determine, by the gNB-CU, a first precoding matrix and a second precoding matrix for a precoding of one or more data streams for transmission on a plurality of antennas coupled to the gNB-DU,
wherein the precoding is in accordance with a split functionality between the gNB-CU and the gNB-DU, and includes:
precoding by the gNB-CU with the first precoding matrix, and precoding by the gNB-DU with the second precoding matrix;
wherein the gNB-CU is configured to precode first symbols from the one or more data streams by the first precoding matrix to generate second symbols for transfer on the F1 interface to the gNB-DU;
wherein the gNB-DU is configured to precode the second symbols by the second precoding matrix to generate third symbols for transmission on the antennas,wherein:a number of rows of the first precoding matrix is equal to a configurable number of virtual ports,
a number of columns of the first precoding matrix is equal to a number of the one or more data streams,
a number of rows of the second precoding matrix is equal to a number of the antennas, and
a number of columns of the second precoding matrix is equal to the configurable number of virtual ports, and
wherein the memory is configured to store the first and second precoding matrices.

US Pat. No. 10,771,129

METHOD AND ARRANGEMENT IN A WIRELESS COMMUNICATION SYSTEM

TELEFONAKTIEBOLAGET LM ER...

1. A method in a first node for adapting a signal to be sent over a radio link from the first node to a second node in a wireless communication system, wherein the second node is configured to use a codebook comprising a set of possible information alternatives for use by the first node in adapting the signal, said method comprising:sending a message to the second node comprising a configuration request to the second node to restrict selection of information alternatives by the second node to at least one subset of the set of possible information alternatives, wherein each subset comprises at least a part of the codebook and wherein the configuration request comprises a bit map that specifies which at least one subset to restrict the selection to; and
receiving a report of an information alternative from the second node, which information alternative is selected from the at least one subset configured according to the configuration request.

US Pat. No. 10,771,128

MULTI-USER MULTIPLE INPUT MULTIPLE OUTPUT (MU-MIMO) USER EQUIPMENT (UE) GROUPING WITH GEOGRAPHIC CORRELATION FACTORS

Sprint Communcations Comp...

1. A method of operating a wireless communication network to use Multi-User Multiple Input Multiple Output (MU-MIMO), the method comprising:network circuitry storing geographic data that indicates geographic containers;
transceiver circuitry wirelessly receiving network signaling from User Equipment (UEs) that are located in the geographic containers;
the network circuitry processing the network signaling and responsively determining UE MU-MIMO correlation factors between the UEs;
the network circuitry processing the network signaling and responsively associating the UE MU-MIMO correlation factors with the geographic containers;
the network circuitry processing the UE MU-MIMO correlation factors associated with the geographic containers and responsively determining container MU-MIMO correlation factors between the geographic containers;
the network circuitry selecting other UEs for MU-MIMO based on their container MU-MIMO correlation factors; and
the transceiver circuitry wirelessly transferring MU-MIMO signals to the other UEs that were selected based on their container MU-MIMO correlation factors, wherein the transceiver circuitry wirelessly transferring the MU-MIMO signals to the other UEs comprises using same time and frequency resource blocks for groups of the other UEs.

US Pat. No. 10,771,127

METHODS OF SIGNALLING IN AN ADVANCED WIRELESS COMMUNICATION SYSTEM SUPPORTING MULTI-USER SUPERPOSITION TRANSMISSION

NEC CORPORATION, Minato-...

1. A data communication method for use in an advanced cellular wireless communication system supporting Multi-User Superposition Transmission (MUST), the method comprising:receiving, from a MUST-UE, a MUST receiver scheme;
determining a baseline size of second downlink control information according to the received MUST receiver scheme and a MUST transmission technique;
configuring the MUST-UE to operate according to a MUST configuration, the MUST configuration including the MUST transmission technique; and
transmitting, to the MUST-UE:
first downlink control information, including an indication that MUST is used;
second downlink control information including assistant information according to the determined baseline size; and
a MUST composite data signal on an associated DL shared channel, according to the MUST transmission technique.

US Pat. No. 10,771,124

VIRTUAL BEAM STEERING USING MIMO RADAR

Jun Fang, San Jose, CA (...

1. A Multiple-Input Multiple-Output (MIMO) radar for virtual beam steering, comprising:a plurality of transmit antennas;
a receive antenna array having a plurality of radiating elements; and
a digital signal processor (DSP) configured to synthesize a virtual receive array having N×M receive subarrays from the plurality of transmit antennas and the receive antenna array, where N is the number of transmit antennas and M is the number of receiving elements, and wherein the virtual receive array is represented by a manifold matrix that is a function of a geometry of the receive antenna array and a carrier frequency and direction of arrival of the plurality of transmit antennas, and the DSP is configured to apply a transformation matrix to the manifold matrix to generate the virtual receive array.

US Pat. No. 10,771,121

METHOD FOR PERFORMING BEAM SEARCH OR BEAM TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for performing beam searching or beam transmission by a first user equipment (UE) in a wireless communication system, the method. comprising:receiving location information from a second UE; and
performing either or both of the beam searching and beam transmission for an area determined based on the received location information,
wherein at least one of a beam direction, a preferential beam searching direction, and a beam width the beam searching or beam transmission is determined according to at least one of a location, a speed, a moving direction, a service, and a packet latency requirement of the first UE,
wherein a frequency band in which the location information is received is lower than a frequency band in which the either or both of the beam searching and beam transmission is performed, and
wherein as e speed of the first UE increases, the beam width for the beam searching decreases.

US Pat. No. 10,771,119

INTELLIGENT ANTENNA SYSTEM

DENSO International Ameri...

1. A vehicle communications system comprising:a pair of antennas;
a radio; and
a controller configured to enable and disable antenna diversity between communication over a safety channel and communication over a service channel, the controller being further configured to compare a vehicle speed with a threshold, identify a WAVE Service Advertisement message, analyze the WAVE Service Advertisement message for content, determine whether the content of the WAVE Service Advertisement message offers a needed service, assign a service priority based on the content of the WAVE Service Advertisement message, determine a vehicle location, add weights to the service priority, vehicle location, and vehicle speed, and selectively disable antenna diversity based on a weighted comparison of the service priority, vehicle location, and vehicle speed, wherein the weight of the service priority is multiplied by a factor within a range of 2.5 to 3.5, the weight of the vehicle location is multiplied by a factor of 1, and the weight of the vehicle speed is multiplied by a factor of within a range of 1.5 to 2.5.

US Pat. No. 10,771,118

CHANNEL STATE MEASUREMENT METHOD AND APPARATUS

Huawei Technologies Co., ...

1. A channel state measurement method, comprising:receiving channel state information (CSI) reporting mode indication information, wherein the CSI reporting mode indication information indicates to perform CSI measurement and feedback based on N pieces of CSI measurement configuration information, and N is an integer greater than 1; and
performing CSI measurement and feedback according to the CSI reporting mode indication information, wherein the performing CSI measurement and feedback comprises:
determining a precoding matrix indicator (PMI) corresponding to a channel state information-reference signal (CSI-RS) indicated by each of the N pieces of CSI measurement configuration information; and
determining, based on a downlink channel and interference that are corresponding to each of the N pieces of CSI measurement configuration information, a channel quality indicator (CQI) corresponding to each of the N pieces of CSI measurement configuration information, wherein
a downlink channel and interference that are corresponding to one piece of CSI measurement configuration information are obtained based on PMIs corresponding to CSI-RSs indicated by the N pieces of CSI measurement configuration information, and the interference corresponding to the CSI measurement configuration information comprises interference outside antenna ports specified by the N pieces of CSI measurement configuration information, and interference obtained after a CSI-RS indicated by one piece of CSI measurement configuration information other than the CSI measurement configuration information is processed based on a corresponding PMI.

US Pat. No. 10,771,116

VIBRATING MAGNET ANTENNA

The University of Vermont...

1. A vibrating magnetic antenna (VMA), the VMA comprising:a magnetic shuttle;
a Y-configured stator assembly, wherein the Y-configured stator assembly comprises:
a pair of first stators;
a second stator, wherein the second stator is positioned relative to the pair of first stators to form a Y-configuration, and wherein the magnetic shuttle is adapted to travel linearly between the pair of first stators and the second stator, and wherein the pair of first stators and the second stator project alternating magnetic fields dependent upon the relative position of the magnetic shuttle.

US Pat. No. 10,771,115

WIRELESS POWER TRANSMITTING DEVICE AND METHOD FOR CONTROLLING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A wireless power transmitting device, comprising:a plurality of patch antennas;
a plurality of phase shifters each corresponding to the plurality of patch antennas;
at least one amplifier corresponding to the plurality of patch antennas respectively;
a plurality of communication antennas; and
a processor configured to:
receive a first communication signal generated by an external electronic device through the plurality of communication antennas,
detect a direction in which the external electronic device is positioned based on the first communication signal,
control each of the plurality of phase shifters so that radio frequency (RF) waves from the plurality of patch antennas constructively interfere with each other in the detected direction, the RF waves each comprising a first magnitude,
receive, from the external electronic device, a second communication signal comprising information related to intensity of a power received at the external electronic device through at least one of the plurality of communication antennas, and
control the at least one amplifier so that the RF waves comprise a second magnitude different from the first magnitude respectively, based on the received second communication signal.

US Pat. No. 10,771,114

INDUCTIVE POWER TRANSMITTER

Apple Inc., Cupertino, C...

1. A wireless power transmitter comprising:a wireless power transfer coil;
detection circuitry configured to detect the proximity of a wireless power receiver and the proximity of an RFID device;
transmission circuitry coupled to the wireless power transfer coil and configured to generate a wireless power transfer field using the wireless power transfer coil; and
control circuitry configured to: upon detection of the wireless power receiver proximate the wireless power transfer coil and absence of the RFID device proximate the wireless power transfer coil, control the transmission circuitry to generate the wireless power transfer field using the wireless power transfer coil; and
upon detection of the RFID device proximate the wireless power transfer coil, control the transmission circuitry to stop generating the wireless power transfer field using the wireless power transfer coil;
wherein an objection detection field is frequency or magnetically decoupled from the wireless power transfer field.

US Pat. No. 10,771,113

METHOD AND APPARATUS FOR PTU DETECTION OF NFC DEVICES

Intel Corporation, Santa...

19. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors of a device comprising a power transmit unit, cause the power transmit unit to:initiate wireless charging with a transmit coil via magnetic resonant coupling;
activate a power delivery system that can excite the transmit coil;
detect, using signal processing circuitry of the device, harmonic distortion that is induced in the transmit coil by a Near Field Communication (NFC) device inside a near field of the transmit coil, wherein the NFC device is detected by operations to correlate a harmonic signature of the NFC device against a plurality of known harmonic signatures comprised within a harmonic signature database indicating an increase in harmonic content in the presence of the NFC device, and; and
lower an output power the power delivery system, using control circuitry of the device, when triggered by a detection of the NFC device;
wherein the NFC device is detected by operations of the one or more processors to correlate the harmonic signature of the NFC device against a plurality of known harmonic signatures comprised within a harmonic signature database based on an indication of an increase in 3rd and 5th harmonic content in the presence of the NFC device; and
wherein the increase in the 3rd and 5th harmonic content is associated with an odd order non-linear loading effect, and a change in the 3rd or the 5th harmonic content is at least 5 dBV greater than a change in the fundamental, the 2nd, or the 4th harmonic.

US Pat. No. 10,771,112

WIRELESS INDUCTIVE POWER TRANSFER

Koninklijke Philips N.V.,...

1. A power transmitter for transferring power to a power receiver during a power transfer phase using a wireless inductive power signal, the power transmitter comprising:an inductor that provides the power signal;
a power signal generator configured to drive the inductor to provide the power signal;
a message receiver that receives data messages from the power receiver,
wherein the data messages are communicated by load modulation of the power signal;
wherein the data messages include at least a power control message and a query message;
a power loop controller,
wherein the power loop controller operates in at least two modes;
wherein, in a first mode:
if a value of the power control message is a first value, the power loop controller increases a magnitude of the power signal; and
if a value of the power control message is a second value, the power loop controller decreases the magnitude of the power signal;
wherein, in a second mode:
if a value of the power control message is the first value, the power loop controller does not increase the magnitude of the power signal; and
if a value of the power control message is the second value, the power loop controller does not decrease the magnitude of the power signal;
wherein the power loop controller normally operates in the first mode; and
a modification processor circuit,
wherein, in response to a received query message, the modification processor circuit causes the power loop controller to temporarily enter the second mode;
wherein, in the second mode: the power loop controller modifies the power signal in accordance with a first pattern of modifications provided by the modification processor circuit; and
wherein the modification processor circuit selects the first pattern from a plurality of patterns of modifications in response to the query message, each pattern of the plurality of patterns corresponding to a different response to the query message.

US Pat. No. 10,771,111

COMMUNICATION SET-UP FOR WIRELESS COMMUNICATION AND METHOD FOR CONTROLLING SUCH A COMMUNICATION SET-UP

Robert Bosch GmbH, Stutt...

1. A communication set-up, comprising:an electronic circuit, the circuit including at least one communication unit configured for wireless communication, the communication unit including an antenna network connected to an antenna; and
an actuating unit;
wherein the circuit further includes a signal processing unit, and in response to operation of the actuating unit, the actuating unit is configured to release a signal to the signal processing unit, which, on the basis of the released signal, converts the communication set-up from a blocked state to an enabled state, or from the enabled state to the blocked state;
wherein the communication set-up is attached to a card, the card being configured to wirelessly and contactlessly receive energy to power the card from a device external and separate from to the card by an electromagnetic field emitted by the device.

US Pat. No. 10,771,110

METHOD AND APPARATUS FOR OPERATING A DIGITAL SUBSCRIBER LINE ARRANGEMENT

British Telecommunication...

1. A system for transmitting data to a first user device and a second user device within a user premises, the system comprising:a distribution point having an aggregation device comprising a plurality of access network modems and having a plurality of lines connected thereto;
a splitter device connected to the aggregation device via one of the lines connected thereto and being located within the user premises, a first connection between the splitter device and a first customer premises equipment modem, the first customer premises equipment modem being connected to the first user device, and a second connection between the splitter device and a second customer premises equipment modem, the second customer premises equipment modem being connected to the second user device,
wherein the aggregation device is operable to transmit data for the first user device via a first one of the plurality of network modems in the aggregation device, the splitter device and the first customer premises equipment modem using a Digital Subscriber Line protocol and operable to transmit data for the second user device via the first one of the plurality of modems in the aggregation device, the splitter device and the second customer premises equipment modem using a Digital Subscriber Line protocol.

US Pat. No. 10,771,108

CROSSTALK CANCELLATION IN A RECEIVER

Cadence Design Systems, I...

1. A receiver apparatus for a memory device, the receiver apparatus comprising:a crosstalk victim line configured for communications between receiver circuitry and memory;
a crosstalk aggressor line configured for communications between the receiver circuitry and the memory;
an amplifier comprising a first amplifier input coupled to the crosstalk victim line, a second amplifier input coupled to a reference voltage, and an amplifier output;
a buffering circuit comprising a crosstalk amplifier, a crosstalk capacitor coupled between the crosstalk aggressor line and a crosstalk amplifier input of the crosstalk amplifier, and a crosstalk resistor coupled between a crosstalk amplifier output and the crosstalk amplifier input, wherein the crosstalk amplifier output is coupled to the first amplifier input.

US Pat. No. 10,771,107

CIRCUIT DEVICE

Inventec (Pudong) Technol...

1. A circuit device comprising:a positive phase signal line formed on a circuit board, the positive phase signal line comprising a first positive-phase-signal-line terminal and a second positive-phase-signal-line terminal and configured to transmit a first signal;
a negative phase signal line formed on the circuit board, the negative phase signal line comprising a first negative-phase-signal-line terminal and a second negative-phase-signal-line terminal and configured to transmit a second signal; and
a single-ended signal line formed on the circuit board and disposed between the positive phase signal line and the negative phase signal line, the single-ended signal line comprising a first single-ended signal line terminal and a second single-ended signal line terminal and configured to transmit a single-ended signal;
wherein the first signal of the positive phase signal line causes a first noise on the single-ended signal line; the second signal of the negative phase signal line causes a second noise on the single-ended signal line; and the first noise and the second noise eliminate one another.

US Pat. No. 10,771,106

PROACTIVE ECHO CANCELLATION (EC) TRAINING

Cisco Technology, Inc., ...

1. A method comprising:identifying a plurality of Echo Cancelation Training Opportunities (ECTOs) in an upstream bandwidth allocation map, wherein identifying the ECTOs comprises identifying a corresponding plurality of mini-slots in a two dimensional time frequency space designated as not to be used for Upstream (US) traffic; and
conducting Echo Cancelation Training (ECT) for each of the plurality of ECTOs, wherein conducting ECT for each of the plurality of ECTOs comprises:
determining iteratively, on a frame-by-frame basis, Echo Cancelation (EC) coefficients for each subcarrier in each mini-slot of the plurality of mini-slots, the each mini-slot comprising a fraction of an upstream bandwidth, and
updating an echo canceller with the determined EC coefficients each time a frame has been completed.

US Pat. No. 10,771,104

PROCESSING DEVICE, NETWORK NODE, CLIENT DEVICE, AND METHODS THEREOF

HUAWEI TECHNOLOGIES CO., ...

1. A network node, comprising:a transceiver; and
a processing device coupled to the transceiver, the processing device being configured to generate a primary synchronization signal (PSS) sequence for a PSS and a secondary synchronization signal (SSS) sequence for an SSS,
wherein the SSS sequence is associated with a first cyclic shift m0 and a second cyclic shift m1, and wherein m0 and m1 satisfy:

wherein:
g is an integer equal to or larger than 1;
L? is 112;
NID(1)?{0, 1, 2, . . . , NID,max(1)?1}; and
NID(2)?{0, 1, . . . , NID,max(2)?1}; and
the transceiver being configured to transmit the PSS based on the PSS sequence and the SSS based on the SSS sequence.

US Pat. No. 10,771,102

TRANSMIT-AND-RECEIVE MODULE AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A transmit-and-receive module comprising:a multiplexer comprising a common terminal, a transmit terminal, a receive terminal, at least one transmit filter, and at least one receive filter, wherein:
the multiplexer is configured to receive an amplified radio-frequency transmit signal at the transmit terminal and output the amplified radio-frequency transmit signal from the common terminal, and to receive a radio-frequency receive signal at the common terminal and output the radio-frequency receive signal from the receive terminal,
a pass band of the transmit filter is a transmit band of the transmit signal and a pass band of the receive filter is a receive band of the receive signal, and
the transmit filter is connected between the common terminal and the transmit terminal, and the receive filter is connected between the common terminal and the receive terminal;
a power amplifier configured to amplify the radio-frequency transmit signal and to output the amplified radio-frequency transmit signal to the transmit terminal; and
a low-noise amplifier configured to amplify the radio-frequency receive signal received from the receive terminal, wherein:
the power amplifier and the low-noise amplifier are integrated with each other,
as graphed on a Smith chart, an impedance in the receive band of the receive filter as seen from the receive terminal intersects a line connecting a center point of noise figure circles and a center point of gain circles, the center point of the noise figure circles representing the impedance at which a noise figure of the low-noise amplifier is minimized and the center point of the gain circles representing the impedance at which gain of the low-noise amplifier is maximized,
the multiplexer further comprises a second transmit terminal, a second receive terminal, a second transmit filter, and a second receive filter, the second transmit filter being connected between the second transmit terminal and the common terminal and the second receive filter being connected between the second receive terminal and the common terminal, and
the transmit-and-receive module further comprises a transmit switch configured to selectively connect the transmit terminal or the second transmit terminal to the power amplifier, and a receive switch configured to selectively connect the receive terminal or the second receive terminal to the low-noise amplifier.

US Pat. No. 10,771,099

RADIO INTERFERENCE STATION ELIMINATION DEVICE, RECEIVER, AND RADIO INTERFERENCE STATION ELIMINATION METHOD

MITSUBISHI ELECTRIC CORPO...

1. A radio interference station elimination device comprising:a broadcast station candidate determination unit for comparing a reception condition of a radio wave with a first reception condition threshold to determine whether to set a frequency of the radio wave as a frequency of a radio broadcast station candidate;
an interference station candidate identification unit for identifying a frequency of an intermodulation interference station candidate, and
an interference station determination unit for comparing a reception condition of a radio broadcast station candidate whose frequency is same as that of an intermodulation interference station candidate identified by the interference station candidate identification unit and which is determined by the broadcast station candidate determination unit with a second reception condition threshold indicating that a reception condition is better than the first reception condition threshold to determine whether the radio broadcast station candidate is an intermodulation interference station or a radio broadcast station.

US Pat. No. 10,771,098

METHOD FOR DETERMINING PHASE NOISE IN A PERIODICALLY MODULATED SIGNAL

1. A method for determining phase noise in a periodically modulated signal, the method comprising the following steps:processing the periodically modulated signal to generate a processed signal from the periodically modulated signal;
determining at least an approximate period of a modulation of the periodically modulated signal from the processed signal;
determining a type of modulation of the periodically modulated signal from the processed signal;
demodulating the modulated signal based on the determined period and the determined type of modulation to generate a demodulated signal, wherein the demodulated signal corresponds to a continuous wave signal containing the phase noise to be quantified; and
determining the phase noise from the demodulated signal.

US Pat. No. 10,771,097

STATE-MACHINE BASED BODY SCANNER IMAGING SYSTEM

Analog Devices, Inc., No...

1. A transmitter integrated circuit for transmitting a signal within an imaging system to generate an image of a target, the transmitter integrated circuit comprising:a transmission signal processor configured to multiply an oscillator signal to generate a transmission signal within a target frequency band and to filter one or more harmonics from the transmission signal, wherein the target frequency band is one of a plurality of target frequency bands;
a transmitter configured to amplify the transmission signal to generate an amplified transmission signal and to provide the amplified transmission signal to one or more of a plurality of antennas associated with a plurality of transmission channels, wherein each antenna of the plurality of antennas is associated with a different transmission channel of the plurality of transmission channels;
a first state machine configured to control the transmission signal processor by configuring the transmission signal processor to operate within a selected target frequency band of the plurality of target frequency bands based at least in part on a current state of the first state machine; and
a second state machine configured to control the transmitter.

US Pat. No. 10,771,096

ANTENNA IMPEDANCE TUNER

Skyworks Solutions, Inc.,...

1. An impedance tuner comprising:a first node configured to be connected to a radio circuit, and a second node configured to be connected to an antenna;
a bypass path, a first series capacitance path, a second series capacitance path, and an inductance path, each path implemented between the first node and the second node, each path including a respective switch configured to allow the path to couple or uncouple the first and second nodes;
a first shunt path and a second shunt path, each shunt path implemented between the second node and ground, and including a shunt switch configured to allow the shunt path to couple or uncouple the second node and the ground; and
a switchable grounding path including a grounding switch and implemented along the inductance path and configured to allow the inductance path to provide a series inductance path when the inductance path couples the first and second nodes, or a shunt inductance path between the first node and the ground when the inductance path uncouples the first and second nodes.

US Pat. No. 10,771,094

MEMORY SYSTEM CONFIGURED TO ESTIMATE A READ VOLTAGE USING A HISTOGRAM

Toshiba Memory Corporatio...

1. A memory system comprising:a nonvolatile memory that includes a plurality of memory cells; and
a memory controller configured to determine a read voltage to be applied to the nonvolatile memory to read first data encoded by a first encoding scheme of a plurality of error mitigation encoding schemes from the nonvolatile memory, by generating a first histogram indicating the number of memory cells for each of a plurality of threshold voltage ranges, and then estimating the read voltage used for reading the first data by using:
(a) the first histogram after correction which is obtained by correcting the first histogram based on a parameter of the first encoding scheme and a parameter of a second encoding scheme of the plurality of error mitigation encoding schemes, and an estimation function for estimating a read voltage used for reading second data encoded by the second encoding scheme,
(b) the first histogram before correction, and the estimation function after correction which is obtained by correcting the estimation function based on the parameter of the first encoding scheme and the parameter of the second encoding scheme, or
(c) the first histogram after correction which is obtained by correcting a part of the first histogram based on the parameter of the first encoding scheme and the parameter of the second encoding scheme, and the estimation function after correction which is obtained by correcting a part of the estimation function based on the parameter of the first encoding scheme and the parameter of the second encoding scheme.

US Pat. No. 10,771,093

APPARATUS TO IMPROVE FLEXIBILITY OF DATA TRANSMISSION

SONY CORPORATION, Tokyo ...

1. An apparatus, comprising:circuitry configured to:
acquire an information block from transmission data, wherein the information block is subjected to an error correction coding operation; and
interleave a bit sequence of the information block, wherein
the interleave of the bit sequence is based on interleave of each of a plurality of partial sequences obtained from the bit sequence, and
a length of the bit sequence is a power of a number other than two.

US Pat. No. 10,771,092

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

HUAWEI TECHNOLOGIES CO., ...


US Pat. No. 10,771,091

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

1. A flash memory apparatus, comprising:a flash memory module comprising a plurality of first blocks and at least one second block; and
a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks;
wherein when completing program of the plurality of first blocks, controlling the flash memory module to perform an internal copy operation to program the at least one second block of the flash memory module according to the plurality of first blocks of the flash memory module; a cell of one first block is used for storing a data amount smaller than a data amount stored by a cell of one second block.

US Pat. No. 10,771,090

DATA PROCESSING UNIT HAVING HARDWARE-BASED RANGE ENCODING AND DECODING

Fungible, Inc., Santa Cl...

1. A method of context-based coding, the method comprising:determining, by a range coder implemented in circuitry of a device, a first context value for a first context for a plurality of bits of a symbol to be coded, wherein the first context value for the first context is same for the plurality of bits;
retrieving, by the range coder, speculative probability values associated with the first context value for the first context from a table of probability values;
for one or more bits of the plurality of bits of the symbol, determining, by the range coder, respective second context values for a second context;
for the one or more bits of the plurality of bits of the symbol, determining, by the range coder, respective probability values from the retrieved speculative probability values based on at least the respective second context values for the second context; and
range coding, by the range coder, the one or more bits of the plurality of bits of the symbol based on the respective determined probability values.

US Pat. No. 10,771,088

OPTIMAL MULTI-DIMENSIONAL DATA COMPRESSION BY TENSOR-TENSOR DECOMPOSITIONS TENSOR

INTERNATIONAL BUSINESS MA...

1. A computer-implemented tensor decomposition method, the method comprising:compressing multi-dimensional data by truncated tensor-tensor decompositions,
wherein the compressing is performed with respect to at least two orientations of the multi-dimensional data,
wherein the compressing is performed via a double sweep by sweeping over the two orientations with a multi-sided process and combining a result of the sweeping, and
wherein the result of the sweeping as the compressing is less dependent on orientation than a result of the compressing.

US Pat. No. 10,771,087

METHODS, DEVICES AND SYSTEMS FOR DATA CONVERSION

INFINEON TECHNOLOGIES AG,...

1. A method for monitoring a data converter, the method comprising:determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and
determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.

US Pat. No. 10,771,086

CURRENT STEERING DIGITAL-TO-ANALOG CONVERSION SYSTEMS

Jariet Technologies, Inc....

1. A digital-to-analog converter (DAC) driver apparatus, the apparatus comprising:a load network; and
a plurality of DAC driver circuits coupled to the load network, a first DAC driver circuit of the plurality of DAC driver circuits comprising:
a first set of data switches configured to be controlled by a first digital input signal of the first DAC driver circuit;
a first set of output switches;
a first set of dump switches; and
a first set of current sources,
wherein:
another DAC driver circuit of the plurality of DAC driver circuits includes a second set of output switches, a second set of dump switches and a second set of current sources, the first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the second set of current sources to the load network, and
the first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or a second set of current sources into a respective dump load.

US Pat. No. 10,771,084

DOUBLE DATA RATE INTERPOLATING ANALOG TO DIGITAL CONVERTER

HUAWEI TECHNOLOGIES CO., ...

1. A double data rate comparator device, comprising:a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REFN) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and an n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration; and
a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
a set input (S); and
a reset input (R) connected to respective outputs (PN, MN) of the double data rate comparator core.

US Pat. No. 10,771,083

TOP PLATE SAMPLING ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A DYNAMIC COMPARATOR WITH A PREAMPLIFIER AND A CLAMP CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:analog-to-digital converter (ADC) logic having outputs, wherein the ADC logic comprises:
a stage with a dynamic comparator circuit wherein the dynamic comparator circuit comprises:
a preamplifier; and
a common mode clamp circuit for the preamplifier;
a residue stage having inputs wherein the inputes of the residue stage are coupled to the outputs of the ADC logic,
wherein the dynamic comparator circuit is a differential comparator circuit, and the preamplifier is a differential preamplifier.

US Pat. No. 10,771,082

CIRCUITRY FOR LOW INPUT CHARGE ANALOG TO DIGITAL CONVERSION

STMicroelectronics Intern...

1. An input circuit for a multiplexer, the input circuit comprising:a first analog input node;
an output node;
a capacitive node connected to the output node;
a first control circuit configured to set a charge at the capacitive node to a desired voltage during a first period of time beginning in response to a start of a sampling cycle of an analog to digital converter where input to the analog to digital converter is driven by output from the multiplexer;
a second control circuit configured to set a charge at the capacitive node to a voltage at the first analog input node, modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period of time beginning in response to expiration of the first period of time; and
a first channel selection switch that closes to connect the first analog input node to the output node to thereby charge the capacitive node to the voltage at the first analog input node, the first channel selection switch being closed in response to expiration of the second period of time;
wherein the first channel selection switch opens to disconnect the first analog input node from the output node at an end of the sampling cycle of the analog to digital converter.

US Pat. No. 10,771,081

MULTI-CORE CIRCUIT WITH MIXED SIGNALING

Hewlett Packard Enterpris...

11. A mixed signaling lab-on-a-chip, comprising:a set of enterprise class central processing unit (CPU) cores coupled via an inter-core link;
a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core, and including a digital to analog (D/A) converter coupled via a separate private bus to the respective CPU core;
a set of extra D/A converters coupled to a supervisory CPU core via another separate private bus;
a field programmable gate array (FPGA) control circuit coupled to the inter-core link and the set of analog circuits to provide a predictable clock timing to the set of analog circuits and control signals to the set of CPU cores;
a field programmable analog array (FPAA) coupled to the inter-core link and having inputs coupled to the set of D/A converters and at least one output coupled to the analog input; and
an analog to digital module in at least one CPU core that includes instructions to perform an analog to digital (A/D) conversion to create digital representation of the analog input using the predictable clock timing and control signals from the FPGA.

US Pat. No. 10,771,080

SYSTEM AND METHOD FOR MODE CONTROL USING AN INPUT OF AN ANALOG-TO-DIGITAL CONVERTER

INFINEON TECHNOLOGIES AG,...

1. A method comprising:performing an analog-to-digital conversion on a signal at an input pin of an integrated circuit using an analog-to-digital converter having a first input range;
monitoring the signal at the input pin using a first comparator having a first threshold outside of the first input range, wherein the analog-to-digital converter and the first comparator are disposed on a single semiconductor substrate, and the first threshold is set using a voltage reference circuit disposed on the single semiconductor substrate;
operating the integrated circuit in a first mode when the signal at the input pin is within the first input range; and
operating the integrated circuit in a second mode different from the first mode when the signal at the input pin is outside of the first input range and crosses the first threshold.

US Pat. No. 10,771,079

AD CONVERTER

Rohm Co., Ltd., Kyoto (J...

1. An analog-digital (AD) converter for performing AD conversion on measurement target voltages for a plurality of channels, comprising:an analog processing part configured to select one of the measurement target voltages and a plurality of reference voltages for each of the channels, to output an analog voltage signal corresponding to the selected voltage;
a first selection part configured to select one of a plurality of analog voltage signals for the plurality of channels output from the analog processing part;
a first AD conversion part configured to perform AD conversion on the analog voltage signal selected by the first selection part to generate a first original digital signal;
a second selection part configured to select one of the plurality of analog voltage signals;
a second AD conversion part configured to perform AD conversion on the analog voltage signal selected by the second selection part to generate a second original digital signal;
a digital processing part configured to receive the first original digital signal and the second original digital signal; and
a controller configured to control contents selected in the analog processing part, the first selection part, and the second selection part,
wherein the plurality of reference voltages include a first reference voltage and a second reference voltage different from each other, and
wherein the digital processing part includes:
a first filter block having a first filter configured to generate a first corrected digital signal from the first original digital signal based on a first parameter, and configured to set the first parameter based on the first original digital signal obtained when the first reference voltage is selected by the analog processing part and the first original digital signal obtained when the second reference voltage is selected by the analog processing part;
a second filter block having a second filter configured to generate a second corrected digital signal from the second original digital signal based on a second parameter, and configured to set the second parameter based on the second original digital signal obtained when the first reference voltage is selected by the analog processing part and the second original digital signal obtained when the second reference voltage is selected by the analog processing part; and
an error determination part configured to output a predetermined error determination signal based on the first corrected digital signal and the second corrected digital signal.

US Pat. No. 10,771,077

HYBRID RETURN-TO-ZERO VOLTAGE-MODE DAC DRIVER

Marvell Asia Pte., LTD, ...

1. A voltage-mode digital-to-analog converter (DAC), comprising:multiple bit processing circuits to generate an output voltage responsive to a binary input, each of the multiple bit processing circuits including
a first switch circuit to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d,
a second switch circuit to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and
wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).

US Pat. No. 10,771,076

MEASURING DEVICE, CALIBRATION METHOD AND MEASURING METHOD WITH JITTER COMPENSATION

1. A measuring device with jitter compensation, the measuring device comprising:a clock source, and
at least one phase shifter,
wherein the at least one phase shifter is configured to receive a clock signal from the clock source and to adjust the respective phase of the clock source.

US Pat. No. 10,771,075

ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTER, RELATED INTEGRATED CIRCUIT, ELECTRONIC SYSTEM AND METHOD

STMICROELECTRONICS S.R.L....

1. A converter circuit configured to selectively convert an analog input voltage into a digital output signal or a digital input signal into an analog output voltage as a function of a mode signal, wherein the converter circuit comprises:a control circuit configured to generate a start-of-conversion signal;
a ramp generator configured to:
monitor the start-of-conversion signal;
when the start-of-conversion signal is set and the mode signal indicates an analog-to-digital conversion, generate a timer stop signal after a time interval that is determined as a function of a value of the analog input voltage, thereby implementing an analog-to-time conversion, the timer stop signal being generated by variation of a ramp signal applied to a comparator; and
when the start-of-conversion signal is set and the mode signal indicates a digital-to-analog conversion, vary the ramp signal until a ramp stop signal is set and, in response to the ramp stop signal, determine the analog output voltage as a function of the ramp signal, thereby implementing a time-to-analog conversion;
a timer circuit comprising a counter configured to provide a count value and a ring oscillator comprising a first delay stage, a plurality of intermediate delay stages and a last delay stage, the timer circuit configured to:
monitor the start-of-conversion signal;
when the start-of-conversion signal is set and the mode signal indicates an analog-to-digital conversion, vary the count value until the timer stop signal is set and, in response to the timer stop signal, determine the digital output signal as a function of the count value, thereby implementing a time-to-digital conversion; and
when the start-of-conversion signal is set and the mode signal indicates a digital-to-analog conversion, generate the ramp stop signal after a time interval determined as a function of a value of the digital input signal, thereby implementing a digital-to-time conversion, the ramp stop signal generated by a variation of the count value.

US Pat. No. 10,771,074

LOW POWER HIGH BANDWIDTH HIGH SPEED COMPARATOR

ANALOG DEVICES, INC., No...

1. A low power and high bandwidth comparator, comprising:a sampling network to derive a difference between an input signal and a reference;
a latch comprising a first cross-coupled pair of transistors and output nodes at respective first terminals of the first cross-coupled pair of transistors, wherein gates of the first cross-coupled pair of transistors are cross-coupled to the output nodes; and
first and second transistors to couple the difference from the sampling network to the gates of the first cross-coupled pair of transistors respectively.

US Pat. No. 10,771,073

FREQUENCY SYNTHESIZER WITH DYNAMICALLY SELECTED LEVEL SHIFTING OF THE OSCILLATING OUTPUT SIGNAL

STMicroelectronics Intern...

1. A circuit, comprising:an oscillator circuit powered at a source voltage and configured to generate an oscillating output signal with an amplitude at a level of the source voltage;
a first level shifter circuit powered by a first power supply voltage and configured to level shift the oscillating output signal to generate a level shifted oscillating output signal;
a first multiplexer circuit having a first input configured to receive the oscillating output signal and a second input configured to receive the level shifted oscillating output signal, wherein the first multiplexer circuit selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal;
a locked loop circuit configured to control a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal; and
a first voltage regulator circuit configured to generate the first power supply voltage using the source voltage as an error amplifier reference voltage.

US Pat. No. 10,771,071

REDUNDANT DCO TUNING WITH OVERLAPPING FRACTIONAL REGIONS

Apple Inc., Cupertino, C...

1. An oscillator circuit, comprising:a digitally controlled oscillator (DCO) circuit, comprising:
a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword, wherein the input tuning codeword comprises a set of integer bits and a set of fractional bits, and wherein the tuning circuit comprises:
an integer tuning circuit configured to process the integer tuning codeword based on switching a plurality of integer tuning capacitors associated therewith, in order to implement the input tuning codeword, wherein the integer tuning codeword comprises an integer tuning range associated therewith; and
a fractional tuning circuit configured to process the fractional tuning codeword based on switching a plurality of fractional tuning capacitors associated therewith, in order to implement the input tuning word, wherein the fractional tuning codeword comprises a fractional tuning range associated therewith;
wherein the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.

US Pat. No. 10,771,070

LOW VOLTAGE INVERTER-BASED AMPLIFIER

KAIKUTEK INC., Taipei (T...

1. A low voltage inverter-based amplifier, comprising:a first inverter-based amplification module, comprising a first positive input and a first negative input to receive an input signal; wherein the first inverter-based amplification module further comprises a first positive output and a first negative output to output a first output signal;
a second inverter-based amplification module, comprising a second positive input and a second negative input to be electrically connected to the first inverter-based amplification module to receive the first output signal; wherein the second inverter-based amplification module further comprises a second positive output and a second negative output to output an amplified signal;
an inverter-based feedforward module, receiving the input signal, and electrically connected to the second inverter-based amplification module to output a feedforward signal; and
an inverter-based common mode detector, electrically connected to the second positive output and the second negative output to receive the amplified signal, and electrically connected to the second inverter-based amplification module to output a feedback signal.

US Pat. No. 10,771,069

FIELD PROGRAMMABLE GATE ARRAY WITH INTERNAL PHASE-LOCKED LOOP

1. A field programmable gate array system comprising:(a) a field programmable gate array comprising:
(1) a first interface comprising:
(A) a first reference clock pin, wherein said first reference clock pin is configured to receive a first clock signal having a first frequency and a first phase;
(B) a second reference clock pin, wherein said second reference clock pin is configured to receive the first clock signal;
(C) a first plurality of data pins, wherein said first plurality of data pins is configured to receive a first serial data stream;
(D) a second plurality of data pins, wherein said second plurality of data pins is configured to transmit a second serial data stream;
(2) a deserializer operationally connected to:
(A) the first reference clock pin to receive as a first input the first clock signal and
(B) the first plurality of data pins to receive as a second input the first serial data stream,
and wherein the deserializer is configured to:
(A) convert the first serial data stream into a first plurality of parallel data streams having a first amount of data streams, and
(B) generate a first receiver side clock signal based on the first clock signal, wherein the first receiver side clock signal has a third frequency and a third phase; and
(C) transmit the first plurality of parallel data streams and the first receiver side clock signal within the field programmable gate array;
(3) computational circuitry operationally connected to the deserializer to receive the first plurality of parallel data streams and the first receiver side clock signal,
wherein the computational circuitry is configured to perform a first set of operations on the first plurality of parallel data streams to generate a second plurality of parallel processed data streams having a second amount of data streams and the computational circuitry performs the first set of operations to generate the second plurality of parallel processed data without use of a clock domain crossing circuit;
(4) a serializer operationally connected to:
(A) an adjustable transceiver phase lock loop to receive as a third input a first wire rate clock signal, wherein the first wire rate clock signal has a fourth frequency and a fourth phase;
(B) the second plurality of data pins to transmit as a first output the second serial data stream;
(C) the computational circuitry, wherein the serializer receives the second plurality of parallel processed data streams from the computational circuitry and the serializer transmits to the computational circuitry a first transmitter side clock signal including a fifth frequency and a fifth phase; and
wherein the serializer is configured to:
(A) convert the second plurality of parallel processed data streams into the second serial data stream;
(B) generate the first transmitter side clock signal based on the first wire rate signal, wherein the first transmitter side clock signal has the fifth frequency and the fifth phase, wherein the fifth frequency is different than and less than the fourth frequency; and
(C) transmit the second serial data stream to the second plurality of data pins for transmission off the field programmable gate array; and
(b) a phase control circuit, provided at least partially on the field programmable gate array, wherein the phase control circuit comprises:
(1) a phase detector configured to compare the third phase of the first receiver side clock signal to the fifth phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the third phase of the first receiver side clock signal and the fifth phase of the transmitter side clock signal;
(2) a phase controller operationally connected to the phase detector and configured to receive the phase difference indicator signal, and wherein the phase controller is configured to determine adjustment information based on the phase difference indicator signal; and
(3) the adjustable transceiver phase lock loop operationally connected to the phase controller and configured to receive the adjustment information as well as operationally connected to the second reference clock pin of the first interface of the field programmable gate array, wherein the adjustable transceiver phase lock loop is configured to generate a second clock signal including the second frequency and the second phase based on the first clock signal received via the second reference clock pin and process the second clock signal based on the adjustment information received from the phase controller to generate the first wire rate clock signal,
wherein the transmitter side clock signal and the first receiver side clock signal are phase aligned so that there is a fixed phase difference between the third phase and the fifth phase.

US Pat. No. 10,771,068

REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE ADJUSTMENT

INTERNATIONAL BUSINESS MA...

1. A method comprising:learning, by a computer system, a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary by:
running, by the computer system, a first test line sequence on the data path comprising a plurality of line test cycles;
observing, by the computer system, a comparison of data rising output from the buffer on a rising edge of the chip clock compared with an output of a pattern generator in comparison with an expected output;
in response to the comparison matching the expected output, decrementing, by the computer system, a load to unload delay across the clock boundary by advancing each of an unload pointer for controlling output from the buffer and the pattern generator by two chip clock cycles in one line test cycle of the plurality of line test cycles;
observing, by the computer system, the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
in response to the comparison not matching the expected output, incrementing, by the computer system, the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
capturing and comparing, by the computer system, the data rising output from the buffer on the rising edge of the chip clock compared with the data falling output from the buffer on the falling edge of the chip clock; and
dynamically adjusting, by the computer system, a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

US Pat. No. 10,771,067

SYSTEM AND METHOD FOR HITLESS CLOCK SWITCHING

NEWCOSEMI (BEIJING) TECHN...

1. A system for hitless clock switching, comprising a sampling circuitry group, a phase detector group, a compensator group, a signal selector and a phase-locked loop that are sequentially connected, whereinthe sampling circuitry group is configured to sample at least one set of reference clock signals to correspondingly obtain at least one set of sampling information and send the at least one set of sampling information to the phase detector group, wherein each set of reference clock signals comprises a primary reference clock signal and a secondary reference clock signal, primary reference clock signals in different sets of reference clock signals are the same, secondary reference clock signals in different sets of reference clock signals are different, and each set of sampling information comprises first sampling information corresponding to the primary reference clock signal and second sampling information corresponding to the secondary reference clock signal;
the phase detector group comprises at least one phase detector, wherein each phase detector receives a set of sampling information and processes the set of sampling information as received to obtain a phase difference, and sends the phase difference and the secondary reference clock signal to the compensator group;
the compensator group is configured to add the phase difference sent by each phase detector and a phase of the secondary reference clock signal sent by the same phase detector to obtain a backup reference clock signal, and send the backup reference clock signal to the signal selector, wherein the compensator group comprises at least one compensator;
the signal selector is configured to receive the primary reference clock signal and at least one backup reference clock signal sent by the compensator group, determine the primary reference clock signal as received as a target reference clock signal in a case that the primary reference clock signal is normal, determine one of the at least one backup reference clock signal as the target reference clock signal in a case that the primary reference clock signal is abnormal or missing, and send the target reference clock signal as determined to the phase-locked loop; and
the phase-locked loop is configured to perform loop control on the target reference clock signal as received.

US Pat. No. 10,771,066

PHASE LOCKED LOOP, PHASE LOCKED LOOP ARRANGEMENT, TRANSMITTER AND RECEIVER AND METHOD FOR PROVIDING AN OSCILLATOR SIGNAL

Telefonaktiebolaget LM Er...

1. A phase locked loop arrangement for a beamforming system having at least two phase locked loops, each phase locked loop comprising:a loop filter configured to provide a control signal to a controllable oscillator, the controllable oscillator configured to provide an oscillator signal in response to the control signal;
a frequency divider configured to provide a first feedback signal and a second feedback signal in response to the oscillator signal, the second feedback signal delayed with respect to the first feedback signal;
an interpolator configured to:
receive the first feedback signal, the second feedback signal, and a phase control word; and
provide an interpolated signal thereof between the first and second feedback signal and in response to the phase control word; and
wherein the interpolator comprises a dummy circuitry arranged such as to provide a substantially constant impedance load to at least one of the inputs of the interpolator irrespectively of the phase control word;
a comparator path configured to receive the interpolated signal and to provide a respective signal to the loop filter in response to a phase deviation between a common reference signal and the interpolated signal;
a reference signal source providing a reference signal and coupled to the comparator path of each of the at least two phase locked loops;
a phase deviation circuit configured to provide the phase control word to each of the phase locked loops to generate a phase difference between oscillator signals of the at least two phase locked loops.

US Pat. No. 10,771,065

CHARGE PUMP CIRCUITS FOR CLOCK AND DATA RECOVERY

INPHI CORPORATION, Santa...

1. A charge pump device comprising:a first switch comprises a first output and coupled to a late signal;
a second switch comprises a second output and coupled to an early signal, the second output being directly coupled to the first output;
an output resistor coupled to the first output and the second output and configured to output a charge pump current based at least on the first output and the second output; and
a first resistor coupled to the first switch;
a second resistor coupled to the second switch;
wherein the charge pump current is at a high voltage when the first switch is on.

US Pat. No. 10,771,064

INJECTION LOCKED FREQUENCY DIVIDER

NATIONAL CHI NAN UNIVERSI...

1. An injection locked frequency divider comprising:a resonator circuit including a first inductor, a second inductor, a third inductor and a fourth inductor, each of said first to fourth inductors having a first terminal and a second terminal, said second terminals of said first and second inductors being respectively coupled to said first terminals of said third and fourth inductors; and
a mixer circuit for receiving an input voltage signal with an input frequency, coupled to said second terminals of said third and fourth inductors, and cooperating with said resonator circuit to form a tank circuit that has a free-running frequency and that defines a frequency locking range which is around three times the free-running frequency, such that the input frequency falls within the frequency locking range;
wherein, by at least performing mixing with a differential first reference voltage signal pair, said mixer circuit generates a differential mixed voltage signal pair at said second terminals of said third and fourth inductors based on the input voltage signal, the differential mixed voltage signal pair having a frequency that is one-third the input frequency, and being outputted at said first terminals of said third and fourth inductors.

US Pat. No. 10,771,063

CONFIGURABLE FIRST IN FIRST OUT AND DESERIALIZER CIRCUITRY

Intel Corporation, Santa...

1. An integrated circuit device comprising:a data interface block;
a plurality of data logic blocks connected to the data interface block at least in part by vias of a via layer, wherein the vias are arranged on the via layer in a via configuration; and
the via layer, wherein the via layer causes the data interface block and the plurality of data logic blocks to operate at least in part as a deserializer circuit when the via configuration of the via layer is a first via configuration and a first-in-first-out (FIFO) circuit when the via configuration of the via layer is a second via configuration.

US Pat. No. 10,771,062

SYSTEMS AND METHODS FOR ENHANCING CONFIDENTIALITY VIA LOGIC GATE ENCRYPTION

Maxim Integrated Products...

1. A configurable logic cell to increase confidentiality via logic gate encryption, the logic cell comprising:a reconfigurable circuit comprising one or more reconfigurable logic building blocks that comprise logic gates, the reconfigurable circuit is configured to perform functions equivalent to a non-reconfigurable circuit that has been assigned key bits.

US Pat. No. 10,771,061

METHODS FOR USING A PRE-MOUNT CHASSIS TO INSTALL AN INTELLIGENT LIGHTING CONTROL SYSTEM

Racepoint Energy, LLC, O...

1. A method of using a chassis to install a lighting control system comprising:attaching the chassis to an electrical wall box, the chassis having at least one hook extending in an upward direction and at least one opening, the at least one hook positioned along a peripheral portion of the at least one opening;
hanging a base module of the lighting control system from the at least one hook in the chassis, the base module including,
a base housing forming a well and including a first electrical connector positioned in the well, the first electrical connector connected to a power circuit that is configured to receive current from an alternating current (A.C.) power supply and is configured for electrical coupling with a lighting circuit of a light fixture;
coupling a plurality of base module wires extending from the base module to a plurality of electrical wall box wires extending from the electrical wall box contemporaneously with the base module hanging from the at least one hook, the coupled wires configured to connect the A.C. power supply to the base module;
removing the base module from the at least one hook after connecting the plurality of base module wires to the plurality of electrical wall box wires; and
nesting the base module into the electrical wall box such that the well extends through the opening in the chassis and into the electrical wall box, wherein nesting includes engaging the at least one opening in the base module with the at least one hook.

US Pat. No. 10,771,060

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a transmission circuitry which converts a first signal based on an input signal into a second signal and transmits the second signal;
a reception circuitry which is electrically insulated from the transmission circuitry, receives the second signal, and outputs a third signal;
a comparison circuitry which compares a reference voltage and a comparison object signal being one of the input signal and the third signal, and outputs a fourth signal which shifts when the comparison object signal shifts to a state of being higher than a first voltage from a state of being lower than the first voltage or when the comparison object signal shifts to a state of being lower than the first voltage from a state of being higher than the first voltage;
a timer circuitry which outputs a fifth signal based on the fourth signal; and
a switch circuitry which switches and outputs the reference voltage being one of the first voltage, a second voltage, and a third voltage, based on the fifth signal, the second voltage being lower than the first voltage, the third voltage being higher than the first voltage,wherein the timer circuitry outputs the fifth signal:at a first time when the comparison object signal shifts from a state of being lower than the first voltage to a state of being higher than the first voltage;
at a second time after a first predetermined time from the first time;
at a third time when the comparison object signal shifts from a state of being higher than the first voltage to a state of being lower than the first voltage; and
at a fourth time after a second predetermined time from the third time.

US Pat. No. 10,771,059

HIGH THROW-COUNT RF SWITCH

pSemi Corporation, San D...

1. An RF switch including:(a) at least one common path;
(b) at least one common port coupled to the at least one common path;
(c) a plurality of sections each containing at least one signal port coupled to at least one common path through a series-shunt switching element; and
(d) at least one isolation switch connected to at least one common path between two adjacent sections, each isolation switch including at least one series switch configured to isolate connected adjacent sections;
wherein when a selected signal port is coupled to at least one common port through at least one common path, any isolation switches between the selected signal port and the at least one common port are configured in a conducting state.

US Pat. No. 10,771,058

AIRCRAFT HIGH CURRENT SWITCH MODULE

GE Aviation Systems Limit...

1. A switch module for connection to a power distribution system, comprising:a housing enclosing a first and a second single-pole bidirectional switch coupled in series;
the first bidirectional single-throw switch having a first input terminal;
the second bidirectional single-throw switch having a second input terminal;
a common terminal wherein the first and second input terminals are switchable to the common terminal;
a first control coupled to the first bidirectional single-throw switch; and
a second control coupled to the second bidirectional single-throw switch; and
wherein the first and second controls are configured to independently control, respectively, the first and second bidirectional single-throw switches;
wherein the first and second bidirectional switches are connected with one of a power source and an electrical load.

US Pat. No. 10,771,057

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first normally-off transistor having a first electrode, a second electrode, and a first control electrode;
a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode;
a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode;
a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode; and
a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion.

US Pat. No. 10,771,055

SWITCHING DEVICE AND POWER CONVERSION DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A switching device comprising:a cascode switch comprising at least two transistors connected in series and receiving a switching control signal; and
a third switch receiving the switching control signal,
wherein the at least two transistors comprise a first transistor receiving the switching control signal through a control terminal and a second transistor comprising a control terminal connected to a first voltage source, and
wherein the third switch is connected between the control terminal of the second transistor and a first terminal of the second transistor, is turned off when the first transistor is turned on, and is turned on when the first transistor is turned off.

US Pat. No. 10,771,053

SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND SWITCHING REGIONS RESPECTIVELY CONTROLLED BY FIRST AND SECOND CONTROL SIGNALS OUTPUT BY A CONTROLLER

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a first switching region including a first gate electrode wherein a channel current of the first switching region is controlled according to an electric charge amount supplied by a first control signal input to the first gate electrode;
a second switching region including a second gate electrode and connected in parallel with the first switching region wherein a channel current of the second switching region is controlled according to an electric charge amount supplied by a second control signal input to the second gate electrode; and
a control section outputting the first control signal for turning-on the first switching region to the first gate electrode and the second control signal for turning-on the second switching region to the second gate electrode,
wherein the control section stops outputting the second control signal after a first predetermined period elapses from a start of outputting the first and second control signals, and outputs the second control signal after a second predetermined period elapses from a stop of outputting the second control signal.

US Pat. No. 10,771,052

GATE DRIVER WITH VGTH AND VCESAT MEASUREMENT CAPABILITY FOR THE STATE OF HEALTH MONITOR

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:a current source having a current output terminal;
a pass transistor having a first terminal coupled to the current output terminal, a gate terminal, and a second terminal;
a multiplexer having a first input coupled to the first terminal of the pass transistor, a second input coupled to the second terminal of the pass transistor, and a selected output; and
an analog-to-digital converter (ADC) having an analog input coupled to the selected output, and a digital output.

US Pat. No. 10,771,051

SEMICONDUCTOR DEVICE AND METHOD OF GENERATING POWER ON RESET SIGNAL

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a voltage divider circuit dividing a power supply voltage to obtain a first voltage and a second voltage having voltage values different from each other;
a first transistor receiving the first voltage at a control electrode to generate a first current;
a second transistor receiving the second voltage at a control electrode to generate a second current, wherein the first transistor and the second transistor are metal oxide semiconductor (MOS) transistors that have aspect ratios different from each other when a ratio of a gate width to a gate length (gate width/gate length) is set as the aspect ratio;
a current comparing part comparing the first current and the second current to generate a current comparison result signal representing a comparison result; and
a reset signal generating part generating a power on reset signal having a first level that prompts reset or a second level that prompts reset cancelation based on the current comparison result signal,
wherein the current comparing part comprises:
a third transistor having a gate connected to the gate of the second transistor and causing a current corresponding to the second current to flow to a first node;
a current mirror circuit copying the current flowing to the first node and causing the copied current to flow to a second node; and
a fourth transistor having a gate connected to the gate of the first transistor and drawing a current corresponding to the first current from the second node,
wherein the current comparing part supplies a signal representing a voltage of the second node as a signal level as the current comparison result signal to the reset signal generating part, and
the reset signal generating part comprises at least one inverter that outputs a signal obtained by inverting a phase of the current comparison result signal or inverting a phase of the signal with an inverted phase as the power on reset signal.

US Pat. No. 10,771,050

GATE DRIVING CIRCUIT AND SWITCHING POWER SUPPLY APPARATUS

FUJI ELECTRIC CO., LTD., ...

1. A gate driving circuit that drives a gate of a main switching device, the gate driving circuit comprising:a first resistor that is connected between a first potential and the gate of the main switching device;
a second resistor that is connected between a second potential lower than the first potential and the gate of the main switching device;
a first switching device that is connected in series with the first resistor between the first potential and the gate of the main switching device;
a second switching device that is connected in series with the second resistor between the second potential and the gate of the main switching device; and
a control circuit that changes at least one resistance value of a resistance value of the first resistor and a resistance value of the second resistor according to a length of an ON period during which the main switching device is turned on.

US Pat. No. 10,771,049

CONTROL CIRCUIT AND METHOD FOR AVOIDING REVERSE RECOVERY OF A POWER TRANSISTOR

Dialog Semiconductor (UK)...

1. A control circuit for controlling a power transistor; wherein the power transistor exhibits a drain, a gate and a source, and wherein the power transistor exhibits a body diode; wherein the control circuit is configured topredict a time instant at which a drain potential at the drain falls below a source potential at the source of the power transistor by more than a diode threshold voltage of the body diode; and
apply a pre-bias potential and/or provide a pre-bias current to the gate of the power transistor in dependence of the predicted time instant, such that a conducting channel between the drain and the source is provided, which at least partially takes over current which would otherwise flow through the body diode.

US Pat. No. 10,771,048

MEASUREMENT OF THE DURATION OF A PULSE

STMicroelectronics (Croll...

1. A device, comprising:a first circuit providing a Vernier delay line circuit that comprises a first chain of identical stages defining first and second delay lines both coupled to a first input;
a second circuit comprising a second chain of identical stages defining third and fourth delay lines, wherein the identical stages of the second chain are identical to the identical stages of the first chain; and
a third circuit configured to selectively couple a selected one of an output of the third delay line, an output of the fourth delay line, or a first input of the third circuit to said first input of the first circuit,
wherein said first circuit is configured to generate a digital signal representative of a duration of a pulse received by said first input of the first circuit.

US Pat. No. 10,771,047

MODULATORS

Cirrus Logic, Inc., Aust...

1. A time-encoding modulator circuit comprising:a forward signal path from a modulator input for receiving an input signal and a modulator output for outputting a time encoded signal;
a feedback path forming a feedback loop with at least part of the forward signal path;
a comparator located in the forward signal path within the feedback loop;
a filter located within the feedback loop;
a variable delay element for applying a controlled variable delay within the feedback loop; and
a delay controller configured to control the delay applied by the variable delay element based on the time encoded signal so as to control a cycle period of the time encoded signal.

US Pat. No. 10,771,046

COMPARATOR AND OSCILLATOR CIRCUIT USING SAID COMPARATOR

FUJI ELECTRIC CO., LTD., ...

1. A comparator having a differential unit and a gain unit, comprising:a charge-discharge control unit configured to connect to an output of the differential unit and configured to control charge-discharge of Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and gate capacitance of the MOSFET; and
an output control unit configured to control an output of the gain unit,
a signal generated at an external terminal of the comparator being input to one of the inputs of the differential unit,
the output control unit including:
a first inverter configured to receive a signal generated at the external terminal as an input;
a first logic circuit configured to receive the output of the first inverter and the output of the gain unit as an input;
a first transistor having a drain configured to connect to the output of the gain unit, a source configured to connect to a reference potential of the comparator, and a gate configured to connect to the output of the first logic circuit; and
a first capacitor configured to connect to the input and the output of the first logic circuit.

US Pat. No. 10,771,045

APPARATUS AND METHOD FOR REDUCING OUTPUT SKEW AND TRANSITION DELAY OF LEVEL SHIFTER

Samsung Electronics Co., ...

1. An apparatus, comprising:a level-shifter circuit configured to output voltages Vo1+ and Vo1?; and
an output alignment circuit configured to output voltages Vo+ and Vo? that are triggered by an edge of a combination of Vo1+ and Vo1?, and where Vo+ and Vo? are set by high states of Vo1+ and Vo1? prior to a transition on an input of the level-shifter circuit.

US Pat. No. 10,771,044

ON-CHIP EMULATION OF LARGE RESISTORS FOR INTEGRATING LOW FREQUENCY FILTERS

Vidatronic, Inc., Colleg...

1. A system for processing of signals with poles that are low in frequency, comprising:a switching capacitor circuit network comprising two switches connected to an input and an output of a switching capacitor (Cs), respectively, in an alternating manner at a selected frequency (fSW), wherein the switching capacitor circuit network is connected to a common mode reference of the system and is used for fixing a DC bias level of the system; and
a filter capacitor (CHPF) connected between an input and the switching capacitor circuit network, wherein the filter capacitor and the switching capacitor circuit network together function as a fully integrated on-chip filter,
thereby resulting in a pole frequency depending on a ratio of capacitance of the switching capacitor circuit network and the filter capacitor (CHPF), wherein a capacitance of the filter capacitor is substantially larger than a capacitance of the switching capacitor,
wherein the system is fully integrated on chip using an advanced process node of ?20 nm.

US Pat. No. 10,771,043

TRANSMIT-RECEIVE DELAY ELEMENT APPARATUS, METHOD, AND APPLICATIONS

CORNELL UNIVERSITY, Itha...

1. An integrated delay apparatus, comprising:a substrate;
a piezoelectric transducer integrally disposed on or in the substrate,
wherein the piezoelectric transducer is adapted to generate an ultrasonic wave packet having a temporal width from 0.5 to 100 nanoseconds,
further wherein the substrate has a thickness, h, that is greater than a spatial width of the ultrasonic wave packet corresponding to the temporal width,
further wherein an interface between a bottom surface of the substrate and a medium immediately adjacent the bottom surface of the substrate exhibits an impedance mismatch whereby the bottom surface of the substrate is a reflective surface for the ultrasonic wave packet; and
further wherein the integrated delay apparatus is characterized by a delay time, ?, where ??2h/vs, where vs is a speed of sound in the substrate.

US Pat. No. 10,771,042

MICRO-ELECTRO-MECHANICAL DEVICE WITH REDUCED TEMPERATURE SENSITIVITY AND MANUFACTURING METHOD THEREOF

STMicroeletronics S.r.l.,...

1. A microelectromechanical device, comprising:a resonator that includes:
a mobile structure having a core region of a first material and a second material on the core region, the mobile structure including:
mobile arms extending in a first direction,
connecting elements connected to the mobile arms and extending in a second direction that is transverse to the first direction;
a window extending through the mobile arms and the connecting elements;
a suspension arm coupled to the connecting elements, the suspension arm extending across the window in spaced relationship with the mobile arms;
at least one anchor coupled to the suspension arm, the at least one anchor positioned inside the window; and
a fixed structure coupled to the mobile structure, the fixed structure including at least one actuating electrode and at least one detection electrode that are capacitively coupled to one of the mobile arms, one of the at least one actuating electrode and one of the at least one detection electrode being arranged inside the window and the other one of the at least one actuating electrode and the other one of the at least one detection electrode being arranged outside the window.

US Pat. No. 10,771,041

TUNABLE NARROW BANDPASS MEMS TECHNOLOGY FILTER USING AN ARCH BEAM MICRORESONATOR

KING ABDULLAH UNIVERSITY ...

1. A tunable bandpass microelectromechanical (MEMS) filter, comprising:at least one arch beam microresonator;
a first voltage source electrically coupled to a first end of the at least one arch beam to apply a static voltage bias to the arch beam microresonator; and
a second voltage source electrically coupled to both the first end and a second end of the at least one arch beam microresonator to apply an adjustable voltage bias across the arch beam microresonator.

US Pat. No. 10,771,040

SYSTEMS AND METHODS FOR REDUCING THE ACTUATION VOLTAGE FOR ELECTROSTATIC MEMS DEVICES

NUtech Ventures, Lincoln...

1. A method of actuating an electrostatic micro-electro-mechanical system (MEMS) micro-oscillator device, wherein the MEMS device has a natural mechanical resonance frequency and an internal electrical resonance frequency, the method comprising:driving the MEMS device with a first alternating current (AC) signal; and
simultaneously driving the MEMS device with a second AC signal,
wherein a frequency of the first AC signal is within the 3-db bandwidth of, or substantially the same as, the internal electrical resonance frequency and wherein a difference between the frequency of the first AC signal and a frequency of the second AC signal is near to or substantially the same as the natural mechanical resonance frequency.

US Pat. No. 10,771,039

ACOUSTIC WAVE DEVICE, HIGH FREQUENCY FRONT END CIRCUIT, COMMUNICATION APPARATUS, AND MANUFACTURING METHOD FOR ACOUSTIC WAVE DEVICE

Murata Manufacturing Co.,...

1. An end surface reflection acoustic wave device in which acoustic waves are reflected between a first end surface and a second end surface opposing each other, the acoustic wave device comprising:a piezoelectric body including the first end surface and the second end surface, and a first principal surface and a second principal surface opposing each other and connecting the first end surface and the second end surface;
a first electrode finger provided on the first principal surface of the piezoelectric body and extending in a second direction, where a direction in which the first end surface and the second end surface are connected is defined as a first direction and a direction orthogonal or substantially orthogonal to the first direction on the first principal surface is defined as the second direction; and
a second electrode finger provided on the first principal surface of the piezoelectric body, arranged separately from the first electrode finger with a gap interposed between the first electrode finger and the second electrode finger, and extending in the second direction on the first principal surface of the piezoelectric body; wherein
a portion in which the first electrode finger and the second electrode finger overlap with each other when viewed from the first direction is defined as an intersecting portion, a distance between the first end surface and the second end surface of the piezoelectric body is defined as a width of the piezoelectric body, and the piezoelectric body is provided with a different width portion having a width different from a width of the piezoelectric body at a central portion of the intersecting portion in the second direction in a region where the first end surface and the second end surface oppose each other.

US Pat. No. 10,771,038

CRYSTAL UNIT

NIHON DEMPA KOGYO CO., LT...

1. A crystal unit, comprising:an AT-cut crystal element that has a nearly-rectangular shape in a plan view and a part as a thick portion,
wherein
the AT-cut crystal element includes a first end portion, a first depressed portion, the thick portion, a second depressed portion, and a second end portion in this order from a side of one short side, in viewing a cross section taken along a longitudinal direction near a center of the short side of the AT-cut crystal element,
the first depressed portion is a depressed portion disposed from the thick portion toward a side of the first end portion, and a surface of the first depressed portion is depressed with a predetermined angle ?a and subsequently bulged, and connected to the first end portion,
the second depressed portion is a depressed portion disposed from the thick portion toward a side of the second end portion, and a surface of the second depressed portion is depressed with a predetermined angle ?b and subsequently bulged, and connected to the second end portion, and
when a dimension from a distal end of the first end portion to an edge on a side of the second depressed portion of the thick portion is defined as L, the L satisfies a following formula (1),
in the formula (1), n is a natural number, and ? is a wavelength of a flexure vibration that propagates along an X-axis of a crystal in the crystal unit,
L=?×(n/2±?)  (1).

US Pat. No. 10,771,037

PIEZOELECTRIC RESONATOR DEVICE

Daishinku Corporation, K...

1. A piezoelectric resonator device, comprising:a piezoelectric substrate including a vibrating part configured to piezoelectrically vibrate by application of a voltage and an external frame part thicker than the vibrating part and which surrounds an outer periphery of the vibrating part;
a first sealing member covering a first main surface of the piezoelectric substrate so as to seal the vibrating part;
a second sealing member covering a second main surface of the piezoelectric substrate so as to seal the vibrating part;
a first excitation electrode and a second excitation electrode on the vibrating part of the piezoelectric substrate; and
external electrodes on at least one of the first sealing member and the second sealing member, the external electrodes being connected to an external element, and wherein the external element is connected to the external electrodes at least on the external frame part of the piezoelectric substrate,
wherein a first external electrode is connected to the first excitation electrode and a second external electrode is connected to the second excitation electrode in the absence of castellation,
wherein the external electrodes are connected to the external element via metal bumps,
wherein the external electrodes include at least an external electrode for a first excitation electrode and an external electrode for a second excitation electrode connected respectively to a pair of first excitation electrode and second excitation electrode formed on the vibrating part of the piezoelectric substrate,
wherein only the metal bump connecting the external electrode for the first excitation electrode to the external element is disposed at a position superimposed to a first wiring connecting the first excitation electrode to the external electrode for the first excitation electrode in plan view, and
wherein only the metal bump connecting the external electrode for the second excitation electrode to the external element is disposed at a position superimposed to a wiring connecting the second excitation electrode to the external electrode for the second excitation electrode in plan view.

US Pat. No. 10,771,036

RF HEATING SYSTEM WITH PHASE DETECTION FOR IMPEDANCE NETWORK TUNING

NXP USA, Inc., Austin, T...

1. A system, comprising:a radio frequency (RF) signal source configured to supply an RF signal;
a transmission path electrically coupled between the RF signal source and an electrode, wherein the RF signal generates a forward signal along the transmission path;
an impedance matching network electrically coupled to an output of the RF signal source, wherein the impedance matching network is an inductor-only network that does not include capacitors, and the impedance matching network includes:
a series inductance coupled along the transmission path, wherein the series inductance includes a first terminal coupled to the RF signal source, and a second terminal coupled to an electrode,
a first shunt inductive network directly connected to the second terminal of the series inductance, wherein the first shunt inductive network includes a first variable inductance network coupled between the second terminal of the series inductance and a ground reference, and
a second shunt inductive network directly connected to the first terminal of the series inductance, wherein the second shunt inductive network includes a second variable inductance network coupled between the first terminal of the series inductance and the ground reference;
power detection circuitry configured to determine a phase angle between the forward signal and a reflected signal along the transmission path; and
a controller configured to:
cause the RF signal source to supply the forward signal at a relatively low power level;
while the RF signal source is supplying the forward signal at the relatively low power level, determine that the phase angle between the forward signal and the reflected signal is greater than a threshold phase angle value,
modify, based on the phase angle between the forward signal and the reflected signal, the first variable inductance network to reduce the phase angle between the forward signal and the reflected signal to a first phase angle that is less than the threshold phase angle value,
while the RF signal source is supplying the forward signal at the relatively low power level, determine that a ratio of a power of the reflected signal to a power of the forward signal is greater than a threshold power ratio,
modify the second variable inductance network to reduce the ratio of the power of the reflected signal to the power of the forward signal to a first power ratio that is less than the threshold power ratio, and
after modifying the first and second variable inductance networks to reduce the phase angle between the forward signal and the reflected signal and to reduce the ratio of the power of the reflected signal to the power of the forward signal, cause the RF signal source to supply the forward signal at a relatively high power level.

US Pat. No. 10,771,035

MULTILAYER LC FILTER

MURATA MANUFACTURING CO.,...

1. A multilayer LC filter comprising:a rectangular or substantially rectangular parallelepiped multilayer body including a plurality of dielectric layers laminated therein;
a plurality of line conductor patterns between layers of the plurality of dielectric layers;
a plurality of capacitor conductor patterns between layers of the plurality of dielectric layers;
at least one ground conductor pattern between layers of the plurality of dielectric layers; and
a plurality of via conductors extending through the plurality of dielectric layers; wherein
a plurality of LC resonators each including an inductor and a capacitor connected in parallel to each other are provided in the multilayer body and the inductors in adjacent LC resonators of the plurality of LC resonators are magnetically coupled to each other;
the inductor in each of the plurality of LC resonators includes: a loop inductor including one of the plurality of line conductor patterns and a pair of the plurality of via conductors connected to two ends of the one line conductor pattern, one of the pair of via conductors of the loop inductor is connected to one of the plurality of capacitor conductor patterns, and another one of the pair of via conductors of the loop inductor is connected to the at least one ground conductor pattern;
the capacitor in each of the plurality of LC resonators is defined by a capacitance between the corresponding one of the plurality of capacitor conductor patterns and the at least one ground conductor pattern;
a magnetic coupling adjustment inductor is provided for at least one LC resonator of the plurality of LC resonators;
in the at least one LC resonator for which the magnetic coupling adjustment inductor is provided, one end of the magnetic coupling adjustment inductor is connected to an intermediate point of the loop inductor and the other end of the magnetic coupling adjustment inductor is connected to the at least one ground conductor pattern; and
the loop inductor and the magnetic coupling adjustment inductor in the at least one LC resonator for which the magnetic coupling adjustment inductor is provided are magnetically coupled to the loop inductor in another adjacent LC resonator of the plurality of LC resonators.

US Pat. No. 10,771,034

CONDUCTIVE PATH WITH NOISE FILTER

AUTONETWORKS TECHNOLOGIES...

1. A conductive path with a noise filter comprising:a plurality of conductive path main bodies;
a plurality of insulating layers that surround respective outer circumferences of the plurality of conductive path main bodies;
a plurality of conductors that are provided with the plurality of insulating layers being sandwiched respectively between the corresponding plurality of conductors and the plurality of conductive path main bodies to form respective capacitors;
a plurality of inductors that are connected to the respective plurality of conductors; and
an electrical connector that includes a plurality of fitting portions into which the respective plurality of inductors are configured to be fit into, the electrical connector being attached to an electrical connection holder,
wherein each of the plurality of inductors includes a connection conductor that is configured to be fitted into a respective fitting portion of the plurality of fitting portions, and a magnetic core that surrounds each of the connection conductors in a state in which the magnetic core is attached to the electrical connection holder, and
a respective connection conductor of the connection conductors and a respective conductor of the plurality of conductors are held by a connection holder in a state in which the respective connection conductor and the respective conductor are connected.

US Pat. No. 10,771,033

ELECTRICAL FEED LINE INTEGRATED FILTERING FOR INDUCTIVE POWER TRANSFER SYSTEMS

WiTricity Corporation, W...

1. A feed line for filtering unwanted frequencies in a wireless power transfer system, the feed line comprising:a feed line for filtering unwanted frequencies in a wireless power transfer system, the feed line comprising:
a first end, wherein the first end is configured to connect to a power source that generates a driving signal having a driving signal frequency;
a second end, wherein the second end is configured to connect to a wireless power transfer element configured to wirelessly transmit power;
at least one conductor core, wherein the conductor core is configured to transfer the driving signal from the power source to the wireless power transfer element;
an integrated filter configured to attenuate at least one frequency generated by the wireless power transfer system, wherein the integrated filter comprises at least one inductor and at least one capacitor; and
a plurality of segments comprising a first segment and a second segment, wherein the first segment comprises the integrated filter, and wherein the second segment comprises a second integrated filter configured to attenuate at least one second frequency generated by the wireless power transfer system, wherein the second integrated filter comprises a second inductor and a second capacitor.

US Pat. No. 10,771,032

METHOD FOR MANUFACTURING PIEZOELECTRIC THIN-FILM ELEMENT

PIEZO STUDIO INC., Miyag...

1. A method of manufacturing a piezoelectric thin-film element, comprising:a first step of forming, on one surface of a piezoelectric single-crystal substrate made of a single crystal of a piezoelectric material, a first electrode in a predetermined planar shape with an area smaller than that of the piezoelectric single-crystal substrate;
a second step of affixing, to the first electrode, a multilayered acoustic film consisting of a plurality of layers different in acoustic impedance which are alternately piled;
a third step of thinning the piezoelectric single-crystal substrate by polishing the piezoelectric single-crystal substrate from the other surface, such that the first electrode and a piezoelectric thin film obtained by thinning the piezoelectric single-crystal substrate are piled on the multilayered acoustic film; and
a fourth step of forming, on the piezoelectric thin film, a second electrode that faces the first electrode with the piezoelectric thin film in between and has an area smaller than that of the first electrode,
wherein in the third step, an electrode formation region of the piezoelectric thin film, where the first electrode is formed, is made thinner than a non-electrode formation region, where the first electrode is not formed, by a polishing pressure difference between the electrode formation region and the non-electrode formation region.

US Pat. No. 10,771,031

METHOD FOR FABRICATING SINGLE CRYSTAL PIEZOELECTRIC RF RESONATORS AND FILTERS WITH IMPROVED CAVITY DEFINITION

Zhuhai Crystal Resonance ...

1. A method of fabricating an FBAR filter device comprising an array of resonators, each resonator comprising a single crystal piezoelectric film sandwiched between a first metal electrode and a second metal electrode, wherein the first metal electrode is supported by a support membrane over an air cavity, the air cavity embedded in a silicon dioxide layer over a silicon handle, with through-silicon via holes through the silicon handle and into the air cavity, said air cavity in the silicon dioxide layer having side walls defined by perimeter trenches that are resistant to a silicon dioxide etchant, comprising stages of:A. fabricating the support membrane over a silicon dioxide box on the silicon handle, having through support membrane filled barriers that traverse the silicon dioxide layer, and wherein the support membrane is coated with at least a first bonding layer of the first metal electrode coupled to the support membrane by a first adhesion layer;
B. fabricating a piezoelectric film coupled to a detachable carrier substrate and coated with at least a second bonding layer of the first metal electrode coupled to the piezoelectric film by a second adhesion layer;
C. bonding the support membrane to the piezoelectric film by bonding the the first and second bonding layers together to sandwich the first metal electrode between the piezoelectric film and the support membrane and creating a bonded structure having a support membrane side of the support membrane and a piezoelectric layer side of the piezoelectric film;
D. fabricating an array of filters by processing the piezoelectric film coupled to the support membrane from the piezoelectric layer side by removing the detachable carrier substrate, trimming the piezoelectric film, the first metal electrode and an exposed surface of the support membrane, surrounding the piezoelectric film with a passivation material and coating with the second metal electrode, and building up base sections of seal rings and contact stacks;
E. fabricating an array of lids having an outer surface and an inner surface, with external terminations on the outer surface and upper sections of the seal rings and contact stacks on the inner surface, such that the external terminations are coupled to the contact stacks by through lid vias, and fabricating upper sections of the seal rings and contact stacks for coupling to the base sections of the seal rings and contact stacks by another bonding layer;
F. attaching the array of filters to the array of lids by coupling the base sections of the seal rings and contact stacks to the upper sections of the seal rings and contact stacks with the another bonding layer;
G. thinning the silicon handle, drilling holes through the thinned silicon handle to the silicon dioxide layer, and etching away silicon dioxide of the silicon dioxide layer; and
H. dicing the array of filters into individual filters.

US Pat. No. 10,771,030

PHASE-LOCKED LOOP WITH ADJUSTABLE BANDWIDTH

Analog Devices Internatio...

12. A method to adjust the bandwidth of a phase-locked loop in a receiver to enhance adjacent channel rejection and blocking performance of the receiver, the phase-locked loop configured to provide an oscillator signal for demodulating a receive signal in the receiver, the method comprising:operating a loop filter of the phase-locked loop in a first configuration having a first bandwidth in response to no interferer being detected in the receive signal;
detecting an interferer in the receive signal prior to channel select filtering; and
operating the loop filter in a second configuration having a second bandwidth that is greater than the first bandwidth in response to detecting the interferer in the receive signal.

US Pat. No. 10,771,029

AMPLIFIER WITH SCALABLE IMPEDANCE ADJUSTMENTS OVER GAIN MODES

SKYWORKS SOLUTIONS, INC.,...

1. A radio-frequency (RF) signal amplifier configured to provide a plurality of gain modes, the signal amplifier comprising:a power supply configured to provide a source current that differs for individual gain modes;
a gain stage including an RF stage transistor and a cascode stage transistor, the gain stage configured to receive the source current from the power supply to operate the gain stage at corresponding gain modes, a total input impedance presented to an input RF signal associated with a transconductance of the RF stage transistor; and
an impedance adjustment circuit coupled to the gain stage and configured to provide a tailored adjustment that compensates for changes in the transconductance using switchable inductive elements.

US Pat. No. 10,771,028

PROGRAMMABLE GAIN AMPLIFIER APPARATUS AND METHOD

FutureWei Technologies, I...

1. An apparatus comprising:a plurality of selectable gain stages connected in parallel between a first supply voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises:
a first selectable signal path connected between an output of the amplification portion and a signal output terminal; and
a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

US Pat. No. 10,771,027

OPERATIONAL AMPLIFIER CIRCUIT AND CURRENT DETECTION DEVICE USING THE SAME

FUJI ELECTRIC CO., LTD., ...

1. An operational amplifier circuit comprising:a potential control circuit connected between a current detection resistor and a current sense semiconductor element connected in parallel with a main semiconductor element which is connected to a power source and configured to supply a drive current to a load, the potential control circuit being configured to control an output potential of the current sense semiconductor element to be equal to an output potential of the main semiconductor element, the potential control circuit including
a current control element connected between the current sense semiconductor element and the current detection resistor, and
an operational amplifier, the output potential of the current sense semiconductor element being input to one of a non-inverting input terminal or an inverting input terminal of the operational amplifier, the output potential of the main semiconductor element being input to another one of the non-inverting input terminal or the inverting input terminal, and the operational amplifier configured to output a control signal corresponding to a potential difference between the current sense semiconductor element and the main semiconductor element to the current control element; and
an input offset voltage polarity determination circuit configured to determine a polarity of an input offset voltage of the operational amplifier according to the potential difference between the current sense semiconductor element and the main semiconductor element,
wherein
the operational amplifier controls the polarity of the input offset voltage to be constant on a basis of a polarity determination signal of the input offset voltage polarity determination circuit.

US Pat. No. 10,771,026

ISOLATION AMPLIFIER

1. An isolation amplifier comprisingan input circuit at high voltage potential having
an input for a measurement signal to be transmitted,
an input circuit for providing a coupling section signal representing the measurement signal, and
a high-voltage-side control unit for driving the input circuit configuration,
a galvanically isolating coupling section for the potential-free transmission of the coupling section signal to
an output circuit at low-voltage potential having
an output circuit for generating an output signal representing the measurement signal from the transmitted coupling section signal,
an output for the output signal,
at least one low-voltage-side control unit for generating control signals, and
at least one of the group comprising a mechanical and electronic input elements for inputting at least one of the group comprising control commands and parameters into the high-voltage-side control unit,comprisinga low-voltage-side arrangement of all the input elements, including the input elements provided for the parameterization of the high-voltage-side control unit, exclusively in a low-voltage circuit, and
a galvanically isolated control channel for transmitting the parameters for driving the input circuit configuration, said parameters being determined for the high-voltage-side control unit and being input via the low-voltage-side input elements, to the high-voltage-side control unit,
wherein the galvanically isolated control channel for transmitting the parameters for driving the input circuit to the high-voltage-side control unit, said parameters being determined for the high-voltage-side control unit and being input via the input elements arranged in a primary current supply circuit, is realized by a repeatedly usable coupling section for the potential-free transmission of electrical energy to the input circuit.

US Pat. No. 10,771,025

RFFE LNA TOPOLOGY SUPPORTING BOTH NONCONTIGUOUS INTRABAND CARRIER AGGREGATION AND INTERBAND CARRIER AGGREGATION

pSemi Corporation, San D...

1. A low noise amplifier (LNA) circuit having at least a first, second and third circuit input and having at least a first and second circuit output, the LNA circuit comprising:(a) a first LNA comprising a first cascode amplifier stage (CAS) having a CAS input and a CAS signal output, the CAS input coupled to the first circuit input:
(b) a second LNA comprising a second CAS having a CAS input and a CAS signal output, the CAS input of the second CAS coupled to the third circuit input; and
(c) a third LNA comprising a third CAS and fourth CAS, each having a CAS input and a CAS signal output, the CAS signal output of the third CAS and the CAS signal output of the first CAS coupled to the first circuit output, the CAS signal output of the second CAS and the CAS signal output of the fourth CAS coupled to the second circuit output, and the input of the third CAS and the input of the fourth CAS coupled to the second circuit input.

US Pat. No. 10,771,024

POWER AMPLIFIER MODULES INCLUDING TRANSISTOR WITH GRADING AND SEMICONDUCTOR RESISTOR

Skyworks Solutions, Inc.,...

1. A power amplifier module comprising:a power amplifier on a substrate, the power amplifier including a bipolar transistor having a collector, a base, and an emitter, the collector having a doping concentration of at least 3×1016 cm?3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and
a semiconductor resistor on the substrate, the semiconductor resistor including a resistive layer that includes the same material as a layer of the bipolar transistor.

US Pat. No. 10,771,023

AMPLIFIER

RichWave Technology Corp....

1. An amplifier, comprising:a first signal input terminal, receiving a first input signal;
at least one signal output terminal;
a first cascode amplifier circuit, comprising a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal is coupled to the first signal input terminal to receive the first input signal;
a second cascode amplifier circuit, comprising a third input terminal, a fourth input terminal and a third output terminal, wherein the third input terminal is coupled to the first output terminal, and the third output terminal is coupled to the second input terminal;
a first capacitor, wherein two terminals of the first capacitor are respectively coupled to the fourth input terminal and the first output terminal; and
a loading circuit, comprising a first terminal and a second terminal, wherein the first terminal of the loading circuit is coupled to the third output terminal, the second terminal of the loading circuit is coupled to the second output terminal, and at least one of the first terminal and the second terminal of the loading circuit is further coupled to the at least one signal output terminal.

US Pat. No. 10,771,022

CIRCUITRY AND METHOD FOR GAN DEVICE

Alcatel Lucent, Nozay (F...

1. Circuitry for a gallium nitride (GaN) device, comprising:a negative bias circuit configured to provide a negative bias voltage for a gate of the GaN device;
a drain switch circuit configured to turn on or off a positive voltage for a drain of the GaN device; and
a control circuit configured to control the drain switch circuit based on provision of the negative bias voltage, such that the positive voltage for the drain is turned on after a voltage of the gate reaches the negative bias voltage and turned off before the negative bias voltage completely disappears.

US Pat. No. 10,771,021

THERMAL PROTECTION OF AN AMPLIFIER DRIVING A CAPACITIVE LOAD

Cirrus Logic, Inc., Aust...

1. A device, comprising:a capacitive load;
a low-pass filter configured to low-pass filter, with a variable cutoff frequency, an input signal to generate a filtered input signal;
an amplifier configured to receive the filtered input signal and amplify the filtered input signal to generate a driving signal to the capacitive load; and
a controller configured to:
receive a real-time estimate of a temperature associated with the amplifier; and
vary the variable cutoff frequency as a function of the temperature.

US Pat. No. 10,771,020

CLASS D TRANSCONDUCTANCE AMPLIFIER

Fluke Corporation, Evere...

1. A circuit comprising:an input terminal;
an output terminal;
a comparator including a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the comparator is electrically coupled to the input terminal of the circuit, and the second input terminal of the comparator is electrically coupled to the output terminal of the comparator;
a first transistor electrically coupled to the output terminal of the comparator;
a second transistor electrically coupled to the output terminal of the comparator;
an inductor electrically coupled to the first transistor and the second transistor;
a first resistor electrically coupled between the inductor and the output terminal of the circuit; and
a differential amplifier including a first input terminal electrically coupled to a first terminal of the first resistor, a second input terminal electrically coupled to a second terminal to the first resistor, and an output terminal coupled to the first input terminal of the comparator to provide a feedback signal to the comparator.

US Pat. No. 10,771,019

RF POWER TRANSISTOR CIRCUITS

NXP USA, Inc., Austin, T...

1. A radio frequency (RF) power transistor circuit comprising:a RF input terminal;
a RF output terminal;
a power transistor having a control electrode for receiving a RF input signal, and a current electrode for providing a RF output signal, wherein the control electrode is coupled to the RF input terminal, and the current electrode is coupled to the RF output terminal;
a first node coupled to the current electrode;
a second node coupled to the control electrode;
a ground terminal;
a first inductance with a first end coupled to the current electrode and a second end coupled to the first node;
a first capacitor with a first electrode coupled to the first node and a second electrode coupled to the ground terminal;
a first decoupling circuit coupled in parallel with the first capacitor between the first node and the ground terminal, wherein the first decoupling circuit includes a first resistor coupled in series with components of a first resonant circuit having a resonance that is lower than a RF frequency; and
a second decoupling circuit coupled between the second node and the ground terminal, wherein the second decoupling circuit includes a second resistor coupled in series with components of a second resonant circuit having a resonance that is lower than the RF frequency.

US Pat. No. 10,771,018

HARMONIC SUPPRESSION METHOD, CORRESPONDING LOW-NOISE AMPLIFIER, AND COMMUNICATION TERMINAL

VANCHIP (TIANJIN) TECHNOL...

1. A low-noise amplifier, wherein an isolation unit is arranged between a harmonic suppression unit and an output match network/input match network, the isolation unit comprises one or more transistors;the low-noise amplifier further comprising an input bias resistor and an output bias inductor;
wherein one end of the input bias resistor is connected to a direct current working point control end of the amplification unit, and the other end of the input bias resistor is connected to a direct current bias signal, to implement high-impedance isolation of the direct current bias signal from a radio frequency signal; and
the output bias inductor is connected between a power supply and the output match network and configured to provide a direct current bias point to the low-noise amplifier.

US Pat. No. 10,771,017

AMPLIFIER CIRCUIT WITH LOW MALFUNCTION RATE

Elite Semiconductor Memor...

1. An amplifier circuit, comprising:an input stage, coupled to a first supply voltage, the input stage arranged to receive a first voltage at a first node;
a first resistor, coupled between an input voltage and the input stage;
an output stage, coupled to a second supply voltage which is different from the first supply voltage, the output stage arranged to provide an output voltage for driving a load;
a second resistor, coupled between the input stage and the output stage;
an intermediate stage, coupled between the input stage and the output stage, the intermediate stage comprising a level shifter; and
a transconductance (gm) circuit, coupled to the input stage rather than the intermediate stage, the gm circuit arranged to compare the first voltage with a common mode voltage, and thereby generates a compensate current to the first node.

US Pat. No. 10,771,016

AMPLIFIER CIRCUIT WITH OVERSHOOT SUPPRESSION

Novatek Microelectronics ...

1. An amplifier circuit, comprising:an input amplifier;
an output amplifier coupled to the input amplifier and outputting an output voltage; and
a diode device coupled between an output end and an input end of the output amplifier, wherein when a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced,
wherein the amplifier circuit further comprises a first variable resistor.

US Pat. No. 10,771,015

METHOD AND DEVICE FOR SELECTIVELY SUPPLYING VOLTAGE TO MULTIPLE AMPLIFIERS BY USING SWITCHING REGULATOR

Samsung Electronics Co., ...

1. An electronic device comprising:an antenna;
a switching regulator;
communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal through the antenna, the amplifier being configured to receive an input signal, wherein the radio-frequency signal corresponds to the input signal of the amplifier; and
control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of the input signal,
wherein the linear regulator and the amplifier are disposed inside the communication chip, and the switching regulator is disposed outside the communication chip.

US Pat. No. 10,771,014

OSCILLATOR BIAS STABILIZATION CIRCUIT FOR SINGLE-PIN CRYSTAL OSCILLATORS

Arm Limited, Cambridge (...

1. An oscillator bias stabilization circuit, comprising:a plurality of resistive dividers responsive to a control signal in the circuit;
the plurality of resistive dividers selectably connectable in the circuit to provide an adaptable equivalent resistance in response to a control signal while keeping a bias voltage produced by the circuit substantially constant as the loop gain of an oscillator is varied, the plurality of resistive dividers coupled to a node in the oscillator that establishes the bias voltage,
the plurality of resistive dividers connected in parallel with a fixed resistive divider of the circuit.

US Pat. No. 10,771,013

OSCILLATOR, ELECTRONIC APPARATUS, VEHICLE, AND MANUFACTURING METHOD OF OSCILLATOR

SEIKO EPSON CORPORATION, ...

1. An oscillator comprising:an external terminal;
a resonator; and
an oscillation circuit that oscillates the resonator, wherein:
the oscillation circuit includes an amplification circuit and a current source which supplies a current to the amplification circuit,
the current is configured, after the oscillator has been turned on, to be set according to a first control signal which is input from the external terminal and a drive level of the resonator is configured to be changed according to the setting of the current,
the current source includes a constant current source and a current mirror circuit and is controlled by current select data to generate various current values,
the current mirror circuit includes a first transistor that is connected to the constant current source,
the current source includes two or more transistors that are each connected to a switch to be selectively turned on or off based on the current select data, and
according to the first control signal input from the external terminal, the switch for each of the two or more transistors in the current source sequentially enters into an ON state, and after reaching a maximum value of the current supplied to the amplification circuit, the switch sequentially enters into an OFF state.

US Pat. No. 10,771,012

HYBRID RC/CRYSTAL OSCILLATOR

MICROCHIP TECHNOLOGY INCO...

1. An oscillator, comprising:a tunable oscillator communicatively coupled with a first pin, the tunable oscillator configured to drive an output signal through the first pin to an external resonant element;
a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator; and
an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and an output of the external resonant element received at the input to the oscillator, wherein the oscillator controller circuit is configured to use the output of the external resonant element to adjust frequency of the tunable oscillator during the entire operation of the tunable oscillator.

US Pat. No. 10,771,011

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...

1. A circuit device comprising:an A/D conversion circuit that receives a control voltage and generates control voltage data, and receives a temperature detection voltage from a temperature sensor and generates temperature detection data;
a processing circuit that generates temperature compensation data based on the temperature detection data, and generates frequency control data by performing addition processing of the temperature compensation data and the control voltage data; and
an oscillation signal generation circuit that generates an oscillation signal of an oscillation frequency set by the frequency control data, using the frequency control data and a resonator,
wherein the processing circuit performs correction processing on addition result data of the addition processing and outputs the frequency control data after the correction processing.

US Pat. No. 10,771,010

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

Seiko Epson Corporation, ...

1. A circuit device comprising:a processing circuit that performs Kalman filter processing for a result of phase comparison between an input signal based on an oscillation signal and a reference signal, and performs loop filter processing for the result of phase comparison; and
an oscillation signal generation circuit that generates the oscillation signal of an oscillation frequency set by frequency control data which is output data of the loop filter processing by using the frequency control data and a resonator,
wherein the processing circuit estimates a truth value for an observed value of the result of phase comparison by using the Kalman filter processing, and
wherein, in response to a determination that the oscillation signal is locked to the reference signal, the processing circuit changes a cutoff frequency for the loop filter processing from a first frequency to a second frequency lower than the first frequency.

US Pat. No. 10,771,009

MAINTAINING A SOLAR POWER MODULE

Saudi Arabian Oil Company...

1. A method for cooling a solar power system, comprising:operating a solar power system that comprises a plurality of solar power cells mounted on an outer surface of a spherical frame that comprises an inner surface that defines an interior volume;
transferring heat from an outer surface of the spherical frame to the inner surface of the spherical frame and to a heat sink that comprises a hollow housing mounted and enclosed within the interior volume of the spherical frame, the hollow housing fluidly isolating an inner volume of the hollow housing from a housing volume defined between the hollow housing and the inner surface of the spherical frame the housing volume comprising an annulus cross-section;
transferring the heat from the hollow housing of the heat sink to a phase change material positioned in, and fluidly sealed within, the inner volume of the hollow housing of the heat sink such that the phase change material is fluidly isolated from the housing volume of the interior volume of the spherical frame; and
transforming at least a portion of the phase change material from a solid phase to a semi-solid or liquid phase based on the heat received from the outer surface of the spherical frame.

US Pat. No. 10,771,008

ROBOTIC SOLAR PANEL CLEANING SYSTEM

Saudi Arabian Oil Company...

1. A cleaning system for a solar panel, comprising:a frame moveable in a transverse direction over the solar panel, the frame having transverse edges oriented in the transverse direction;
a brush assembly positioned within the frame, the brush assembly including a plurality of brush holders arranged within the frame, the brush holders moveable in a longitudinal direction within the brush assembly, each brush holder being adapted to interchangeably receive a brush for cleaning the solar panel; and
a liquid spray arrangement including:
a plurality of rows of nozzles positioned within the frame and oriented in the transverse direction, the plurality of rows of nozzles configured to spray at least one of water and a water detergent mix onto the solar panel; and
at least one additional row of nozzles adjacent to at least one of the transverse edges of the frame, the at least one additional row of nozzles positioned such that as each one of the plurality of brush holders is moved in a longitudinal direction and reaches the end of the frame to be positioned adjacent to the at least one of the transverse edges of the frame, the nozzles of the at least one additional row of nozzles are configured to spray the at least one of water and the water detergent mix onto each one of the plurality of brush holders positioned adjacent to the transverse edges of the frame to directly clean the brushes or the solar panel.

US Pat. No. 10,771,007

SPRING COUNTER-BALANCE ASSEMBLIES AND SOLAR TRACKERS INCORPORATING SPRING COUNTER-BALANCE ASSEMBLIES

Array Technologies, Inc.,...

1. A solar tracker assembly comprising:a support column;
a torque tube or torsion beam connected to the support column;
a mounting mechanism attached to the torque tube or torsion beam;
a drive system connected to the torque tube or torsion beam; and
a spring counter-balance assembly connected to the torque tube or torsion beam.

US Pat. No. 10,771,006

PHOTOVOLTAIC ROOF TILES AND METHOD OF MANUFACTURING SAME

Tesla, Inc., Palo Alto, ...

1. A photovoltaic tile comprising:a light transmissive top sheet;
a base substrate, wherein the base substrate is adhered to the top sheet;
an active area of photovoltaic material between the base substrate and the top sheet; and
an inactive area of photovoltaic material between the base substrate and the top sheet; and
an adhesive material disposed between the inactive area of photovoltaic material and the top sheet forming an adhesion region,
wherein the inactive area of photovoltaic material is located between an edge of the base substrate and the active area of photovoltaic material,
wherein the inactive area of photovoltaic material is continuous and surrounds the active area of photovoltaic material on the base substrate.

US Pat. No. 10,771,005

INVERTER SYSTEM FOR VEHICLE

Hyundai Motor Company, S...

1. An inverter system for a vehicle, comprising:an energy storage device configured to store electrical energy;
a first inverter including a plurality of first switching elements, wherein the first inverter is configured to convert the electrical energy stored in the energy storage device into alternating-current (AC) electric power;
a second inverter including a plurality of second switching elements different from the plurality of first switching elements, wherein the second inverter is connected to the energy storage device in a parallel relationship with the first inverter, and is configured to convert the electrical energy stored in the energy storage device into AC power;
a motor configured to be driven by receiving AC power converted by the first inverter and the second inverter;
current sensors disposed between the first inverter and the motor and disposed between the second inverter and the motor, respectively, wherein each of the current sensor is configured to detect a current input to the motor; and
a controller configured to generate a pulse width modulation (PWM) signal for controlling driving of the motor, to determine a failure occurrence position between the first inverter and the motor or the second inverter and the motor based on the detected current, and to control the motor to be driven by the first inverter or the second inverter according to the failure occurrence position,
wherein, when a failure does not occur between the first inverter and the motor or the second inverter and the motor, the controller controls driving of the first inverter and the second inverter based on a required output amount of the motor,
wherein, when the required output amount of the motor is smaller than a reference value, the controller controls the plurality of first switching elements to drive the first inverter, and
wherein switching and conduction losses of the first inverter are smaller than those of the second inverter.

US Pat. No. 10,771,004

SYSTEM AND METHOD FOR INSTALLATION AND VERIFICATION OF FASTENERS

Newfrey LLC, New Britain...

1. A power tool, comprising:a housing;
a fastening mechanism at least partially contained in the housing, wherein the fastening mechanism includes:
a drivable sliding sleeve with an anvil, and
a collet configured to grip a deformable fastener and move the fastener in relation to the anvil, thereby performing a swaging operation;
a motor arranged in the housing and drivably connected to the fastening mechanism;
a current sensor configured to measure of current supplied to the motor of the power tool during operation of the power tool; and
a controller configured to receive a measure of current from the current sensor and determine a rate of change of the current during operation of the power tool, wherein the controller determines occurrence of the power tool engaging a fastener based on the magnitude of the current supplied to the motor, determines occurrence of the power tool swaging the fastener based on the rate of change of the current, and determines completion of the power tool swaging the fastener based on the magnitude of the current and the rate of change of the current;
wherein the controller is interfaced with the motor and alters rotation of the motor of the power tool in response to determining completion of swaging the fastener.

US Pat. No. 10,771,003

APPARATUS AND METHOD FOR CONTROLLING INVERTER FOR DRIVING MOTOR

HYUNDAI MOTOR COMPANY, S...

1. An apparatus for controlling an inverter for driving a motor, the apparatus comprising:a current controller configured to generate a d/q-axis voltage reference for allowing a d/q-axis current detection value, which is obtained by measuring a current supplied from the inverter to the motor, to converge on the d/q-axis current reference for driving the motor, and
a voltage modulator configured to control switching of the inverter by selectively applying one among a plurality of predetermined pulse width modulations (PWMs) based on a point at which the d/q-axis voltage reference is located in a hexagonal space voltage diagram,
wherein, when the d/q-axis voltage reference is located on a diagonal line passing through a center of the hexagon in the space voltage vector diagram, the voltage modulator applies a discontinuous PWM (DPWM), and
wherein, when the d/q-axis voltage reference is located inside the hexagon except for the diagonal line passing through the center of the hexagon in the space voltage vector diagram, the voltage modulator applies a space vector PWM (SVPWM).

US Pat. No. 10,771,002

DEVICE FOR STABILIZING DIRECT CURRENT (DC) DISTRIBUTION SYSTEM

LG ELECTRONICS INC., Seo...

1. A device for stabilizing a direct current (DC) distribution system, wherein the system includes a power supply stage, the device comprising:a capacitor unit charged by a DC voltage supplied from the power supply stage;
an inverter unit including two pairs of driving switching elements and a pair of common switching elements, wherein the inverter unit is configured to use the two pairs of driving switching elements to convert the voltage charged in the capacitor unit into an AC power and to provide the AC power to a motor connected to the device;
a voltage stabilization unit including the pair of common switching elements and at least one passive element, wherein the voltage stabilization unit is configured, based on a charging or discharging signal, to charge the capacitor unit with the DC voltage supplied from the power supply stage or to discharge the voltage charged in the capacitor unit to the power supply stage; and
a control unit configured to compare the DC voltage supplied from the power supply stage with a reference range, and to provide the charging or discharging signal to the voltage stabilization unit based on the comparison result.

US Pat. No. 10,771,001

CONTROLLER FOR AN INDUCTIVE LOAD HAVING ONE OR MORE INDUCTIVE WINDINGS

InvertedPower Pty Ltd, H...

1. A controller for an electric vehicle, comprising:a motor of the vehicle having one or more inductive windings;
a first drive circuit including a first half-bridge rectifier;
a second drive circuit including a second half-bridge rectifier;
a third drive circuit including a third half-bridge rectifier;
wherein the one or more inductive winding is connected across from a midpoint of one of the first, second, or third half-bridge rectifiers to a midpoint of an other of the first, second, or third half-bridge rectifiers;
a first input connected to respective like pairs of positive power rails and negative power rails of the first, second, and third drive circuits in a parallel arrangement;
a first direct current energy source or an onboard battery connected across the first input; and
a control module configured to issue control signals to reconfigure the first, second, and third drive circuits from a first state to a second state;
wherein, in the first state, in response to the control signals, the first, second, and third drive circuits are configured in a first period to drive the motor to propel the vehicle and in a second period to generate a first direct current charging current to re-charge the on-board battery;
wherein said first, second and third drive circuits are connected with the first input and are responsive to the control signals for receiving a load current and selectively energising at least one of the one or more inductive windings; and
wherein, in the second, reconfigured state, the controller comprises:
a second direct current external energy source connected across a second input, to charge the onboard battery, the second input connected across the second drive circuit;
a switch in at least one of the positive power rail and the negative power rail, between the second drive circuit and the first drive circuit; and
a first bulk capacitor across the first input and a second bulk capacitor across the second input;
wherein, in the second state, the switch is open, the second drive circuit is disconnected from the first input, and the control module is configured to operate at least one of the first, second, and third drive circuits, with at least one inductive winding, in a buck convert mode, a boost convert mode, or a buck-boost convert mode from the second direct external power source at a second potential to a first potential in order to charge the onboard battery.

US Pat. No. 10,771,000

MOTOR CONTROL SYSTEM, MOTOR CONTROL APPARATUS, AND METHOD FOR CONTROLLING MOTOR

Kabushiki Kaisha Yaskawa ...

1. A motor control system, comprising:a motor;
a motor control apparatus configured to drive the motor and comprising a first communication port and a second communication port;
an upper-level control apparatus connected to the first communication port via a first communication path;
an interface circuit connected to the second communication port via a second communication path, the interface circuit including communication controller processing circuitry; and
at least one detector configured to detect information for controlling the motor and connected to or including the interface circuit,
wherein the motor control apparatus comprises motor control processing circuitry configured to obtain the information detected by the at least one detector and exchanged between the upper-level control apparatus and the interface circuit, and control the motor based on the obtained information,
wherein the at least one detector includes a plurality of detectors and the motor control processing circuitry of the motor control apparatus is further configured to set, as a parameter, a ratio among pieces of the information detected by the plurality of detectors, add together the pieces of the information according to the ratio, and control the motor based on the pieces of the information added together.

US Pat. No. 10,770,999

BRUSHLESS, SELF-EXCITED SYNCHRONOUS FIELD-WINDING MACHINE

THE REGENTS OF THE UNIVER...

1. An electric machine, comprising:a rotor;
an AC stator configured to receive an AC drive signal and arranged adjacent to and interoperable with the rotor, wherein the AC stator is configured with four or more phases to independently produce magnetic fields at two or more spatial harmonics;
wherein the rotor includes an excitation winding and a field winding and the field winding is electrically coupled to the excitation winding, wherein the excitation winding and the field winding are configured to magnetically couple to the two or more spatial harmonics of the AC drive signal, such that the excitation winding is independently excitable from the field winding by different spatial harmonics of the AC drive signal; and
a controller electrically coupled to windings of the AC stator and independently controls the magnetic fields at the two or more spatial harmonics.

US Pat. No. 10,770,998

CONTROL APPARATUS FOR ROTATING ELECTRIC MACHINE

DENSO CORPORATION, Kariy...

1. A control apparatus for a rotating electric machine that is applied to a control system, the control system including a power conversion circuit that performs switching operations to convert direct-current power from a direct-current power supply to alternating-current power and to output the alternating-current power, a rotating electric machine to which the alternating-current power outputted from the power conversion circuit is supplied, and a capacitor that is connected in parallel to the direct-current power supply and provided on an input side of the power conversion circuit, the control apparatus comprising:a first selecting unit that selects two types of active voltage vectors that sandwich a command voltage vector applied to the rotating electric machine from the power conversion circuit and have a phase difference of 60 degrees therebetween;
a second selecting unit that selects, of two types of active voltage vectors that sandwich the command voltage vector and have a phase difference of 120 degrees therebetween, one of two types of active voltage vectors that differs from the two types of active voltage vectors selected by the first selecting unit, based on a driving state of the rotating electric machine; and
an operating unit that controls the power conversion apparatus to perform switching operations to control the rotating electric machine, based on the two types of active voltage vectors selected by the first selecting unit and the one of two types of active voltage vectors selected by the second selecting unit, wherein:
the second selecting unit selects, of two types of active voltage vectors that sandwich an active voltage vector corresponding to a phase of which an absolute value of a phase current is the largest and have a phase difference of 120 degrees therebetween, one of two types of active voltage vectors that differs from the two types of active voltage vectors selected by the first selecting unit, based on each phase current flowing to the rotating electric machine.

US Pat. No. 10,770,997

POWER SYSTEM

ROLLS-ROYCE plc, London ...

1. A power system, comprising:a synchronous electrical generator having a rotor driven by a shaft;
a permanent magnet signalling generator, coupled to the shaft; and
an angle computation unit configured to calculate a rotor angle and/or load angle based on a voltage from the permanent magnet signalling generator and a voltage from the synchronous electrical generator.

US Pat. No. 10,770,996

SYSTEM FOR ANTICIPATING LOAD CHANGES

General Electric Company,...

1. A system, comprising:a closed cycle engine having a piston body defining a hot side and a cold side and having a piston assembly movable within the piston body;
an electric machine operatively coupled with the piston assembly, wherein the electric machine is operable to generate electrical power when the piston assembly is moved within the piston chamber;
an electrical device in communication with the electric machine, the electrical device operable to receive electrical power from the electric machine; and
a control system, comprising:
one or more sensors;
a controllable device; and
a controller communicatively coupled with the one or more sensors and the controllable device, the controller being configured to:
determine whether a load change on the electric machine is anticipated based at least in part on data received indicative of a load state of the electrical device;
in response to whether the load change is anticipated, determine a control command indicative of instructions for adjusting an output of at least one of the closed cycle engine and the electric machine; and
cause the controllable device to adjust the output based at least in part on the control command.

US Pat. No. 10,770,995

CLOSED CONTROL DEVICE FOR DC BRUSH MOTOR, CONTROL SYSTEM, AND CONTROL METHOD

Kabushiki Kaisha Toshiba,...

1. A control device comprising:a drive circuit, one end of the drive circuit being electrically connected to a DC brush motor;
a detecting circuit that includes a node connectable to each of another end of the drive circuit, one end of a power supply circuit, and to one end of a smoothing circuit, and that detects changes in a current flowing between the node and the smoothing circuit; and
a control circuit that generates a control signal to control rotation speed of the DC brush motor according to the detected changes in the current,
the drive circuit driving the DC brush motor according to the generated control signal.

US Pat. No. 10,770,994

VARIABLE TORQUE ELECTRIC MOTOR ASSEMBLY

HAMILTON SUNSTRAND CORPOR...

1. An actuator assembly comprising:an electric motor including a rotor assembly and a stator assembly configured to be actuated to cause the rotor assembly to rotate based on an amount of magnetic flux in the rotor assembly;
a controllable magnetic device coupled to the rotor assembly;
an actuator coupled to the rotor assembly; and
a controller configured to apply electric current to the controllable magnetic device to adjust an amount of torque provided by the electric motor by adjusting the magnetic flux in the rotor assembly;
wherein the controller includes field coupler coupled to the rotatable member and configured to rotate with the rotor assembly.

US Pat. No. 10,770,993

POWER TOOL

Nanjing Chervon Industry ...

1. A power tool, comprising:a motor, comprising a stator and a rotor;
a transmission device, configured to connect the rotor to a tool accessory;
a drive circuit, configured to output a switch signal to drive the rotor of the motor to operate;
a control unit, configured to output a drive signal to control the drive circuit; and
a power supply device, configured to supply power to the motor, the drive circuit, and the control unit;
wherein the control unit is configured to determine a variable ?PWM of a duty ratio according to a variable ?x of a characteristic parameter of the motor, wherein the variable ?PWM of the duty ratio is obtained by a function f(?x) and is within a range of 0.01 to 0.1, and according to the variable ?PWM of the duty ratio, output the drive signal to the drive circuit to control the rotor of the motor to operate to output a driving force.

US Pat. No. 10,770,992

STABILIZER AUTO-ROTATING CONTROL METHOD

Guilin Feiyu Technology C...

1. A stabilizer auto-rotating control method, wherein the method is applicable for a stabilizer comprising:a hand-held component;
a first motor, a second motor and a third motor provided on top of the hand-held component and separated from each other by preset angles in space;
a bracket connected with the first motor and configured to fix a target object; and
a key;
a stator of the third motor being connected to the hand-held component; a rotor of the third motor being connected to a stator of the second motor; a rotor of the second motor being connected to a stator of the first motor; a rotor of the first motor being connected to the bracket;
the bracket rotating with an axis of the first motor when the first motor is started; the first motor and the bracket as a whole rotating with an axis of the second motor when the second motor is started; the first motor, the second motor and the bracket as a whole rotating with an axis of the third motor when the third motor is started;
wherein the method comprises:
a calibration step: recording initial positions and end positions of the first motor, the second motor, and the third motor in response to a calibration instruction for the stabilizer; and
a photographing step: controlling the first motor, the second motor, and the third motor to rotate from the initial positions to the end positions at preset rotation speeds according to the initial positions and the end positions of the first motor, the second motor and the third motor in response to a photographing instruction;
wherein the calibration instruction is generated in the following way:
the calibration instruction is generated when n times of successive pressing operations on the key are detected within a preset period of time; wherein n?1;
wherein recording the initial positions and the end positions of the first motor, the second motor, and the third motor in the calibration step is consisted of:
recording current positions of the first motor, the second motor, and the third motor as the initial positions respectively when a first time of pressing operation on the key is detected; and
recording current positions of the first motor, the second motor, and the third motor as the end positions respectively when a second time of pressing operation on the key is detected.

US Pat. No. 10,770,991

VIBRATOR MANUFACTURING METHOD

Canon Kabushiki Kaisha, ...

1. A method of manufacturing a vibrator including an elastic member and a hollow protrusion having a side wall portion protruding with respect to a surface of the elastic member, a contact portion configured to come into contact with a body, and a first connection portion connecting the side wall portion and the contact portion, the method comprising:forming the hollow protrusion including the side wall portion and a distal end portion by performing drawing on an elastic plate; and
forming the contact portion and the first connection portion by performing drawing or squeezing on the distal end portion,
wherein the contact portion is surrounded by the first connection portion.

US Pat. No. 10,770,990

TRIBOELECTRIC GENERATOR

Samsung Electronics Co., ...

1. A triboelectric generator comprising:a first electrode and a second electrode spaced apart from each other;
a first charging part and a second charging part,
the first charging part being on the first electrode,
the first charging part being configured to be charged a first polarity due to contact with the second charging part,
the second charging part being configured to slide on a surface of the first charging part,
the second charging part being configured to be charged with a second polarity that is opposite to the first polarity through contact with the first charging part; and
a grounding unit configured to intermittently connect the second charging part to a charge reservoir according to movement of the second charging part, and
wherein the second charging part is configured to slide on a surface of the second electrode as well as on the surface of the first charging part.

US Pat. No. 10,770,989

ELECTRODE STRUCTURE, TRIBOELECTRIC GENERATOR INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE ELECTRODE STRUCTURE

Samsung Electronics Co., ...

1. A triboelectric generator comprising:a first charging layer and a second charging layer, the first and second charging layers being configured to be in contact with, or to be spaced apart from each other, the first and second charging layers being configured to be charged with opposite polarities when in contact with each other;
a first electrode on the first charging layer; and
a second electrode spaced apart from the first electrode, at least some regions of the second electrode being embedded in the second charging layer,
wherein the second electrode is embedded in a surface of the second charging layer opposite to the surface of the second charging layer contacting the first charging layer, and electrical energy generated from the triboelectric generator depends on areal factor of the second electrode.

US Pat. No. 10,770,988

NON-LINEAR DROOP CONTROL

Virginia Tech Intellectua...

1. A power converter system, comprising:at least two power converters configured to provide power to a direct current (DC) bus over a predetermined voltage range;
a load electrically coupled to the DC bus; and
a controller configured to sense an amount of current supplied over the DC bus to the load by one of the at least two power converters and to adjust a droop resistance associated with the one of the at least two power converters according to a continuous non-linear function based on the amount of current supplied to the load.

US Pat. No. 10,770,987

MOTOR DRIVE ARCHITECTURE FOR VARIABLE FREQUENCY ALTERNATING CURRENT LOADS

HAMILTON SUNSTRAND CORPOR...

1. A three-phase active front-end motor drive system with short circuit protection, the drive system comprising:a multi-level converter having a converter neutral common point configured to transfer power from a three-phase alternating current (AC) power source to a first direct current (DC) bus, the first direct current bus having a positive terminal, a negative terminal, and a neutral common point;
a second DC bus having a positive terminal and a negative terminal, the second DC bus operably connected to the first DC bus, with the positive terminal of the second DC bus operably connected to the positive terminal of the first DC bus, and the negative terminal of the second DC bus operably connected to the negative terminal of the first DC bus;
an inverter operably connected to the second DC bus, the inverter configured to draw power from the positive terminal of the second DC bus and negative terminal of the second DC bus to provide a plurality of motor excitation signals, the inverter having an inverter neutral common point;
a neutral point selection device operably connected to the first DC bus neutral common point of the first DC bus and selectively connectable to at least one of the converter neutral common point and the inverter neutral common point, the bus selection device configured to disconnect the at least one of the converter neutral common point and the inverter neutral common point from the first DC bus neutral common point under selected conditions; and
an inrush current limiter, wherein the converter is a multilevel converter including the inrush current limiter, the inrush current limiter comprises a bypass diode and a series positive temperature coefficient thermistor selectively shunted by an active switching device.

US Pat. No. 10,770,986

POWER CONVERSION DEVICE

TOSHIBA MITSUBISHI-ELECTR...

1. A power conversion device for converting first to third-phase AC voltages supplied from an AC power supply into fourth to sixth-phase AC voltages and supplying the fourth to sixth-phase AC voltages to a load, the power conversion device comprising:first to third-phase converters configured to convert the first to third-phase AC voltages into DC voltages, respectively;
first to third DC positive buses electrically connected to the first to third-phase converters, respectively;
first to third DC negative buses electrically connected to the first to third-phase converters, respectively;
a fourth-phase inverter connected between the first DC positive bus and the first DC negative bus, and configured to convert the DC voltage into the fourth-phase AC voltage;
a fifth-phase inverter connected between the second DC positive bus and the second DC negative bus, and configured to convert the DC voltage into the fifth-phase AC voltage; and
a sixth-phase inverter connected between the third DC positive bus and the third DC negative bus, and configured to convert the DC voltage into the sixth-phase AC voltage,
the first to third-phase converters including diode rectifiers,
the power conversion device further comprising:
a first fuse connected between the AC power supply and the first-phase converter;
a second fuse connected between the AC power supply and the second-phase converter;
a third fuse connected between the AC power supply and the third-phase converter;
fourth to sixth fuses inserted into the first to third DC positive buses, respectively; and
seventh to ninth fuses inserted into the first to third DC negative buses, respectively.

US Pat. No. 10,770,985

VEHICLE AUXILIARY POWER SUPPLY DEVICE

MITSUBISHI ELECTRIC CORPO...

1. A vehicle auxiliary power supply device mounted in an electric rolling stock, the device comprising:a converter to convert first DC power supplied to the electric rolling stock from a DC power supply into second DC power, which is stepped-down from the first DC power; and
a three-phase inverter to convert the second DC power supplied from the converter into three-phase AC output power having a sinusoidal waveform and to supply the converted three-phase AC output power to a load of the electric rolling stock,
wherein a semiconductor module formed of wide bandgap semiconductor is used as a switching element, having a switching frequency of at least 60 kHz, of the three-phase inverter, and
wherein only a filter reactor or only a filter capacitor is provided on an output side of the three-phase inverter.

US Pat. No. 10,770,984

SWITCHING CONTROL DEVICE WITH REVERSE BIAS CIRCUIT

YAZAKI CORPORATION, Toky...

1. A switching control device comprising:a drive circuit that is connected to a control terminal of a switching element connected to a DC power supply to be transformed and controlled to be turned on or off, and applies a voltage to the control terminal to turn on the switching element, the switching element including an input terminal to which a current is input, an output terminal that outputs the current input from the input terminal, and the control terminal that controls the current flowing from the input terminal to the output terminal; and
a reverse bias circuit that includes a capacitor connected to the output terminal, and a coil having one end connected between the drive circuit and the control terminal and another end connected between the capacitor and the output terminal, wherein
the coil has an inductance value capable of continuously outputting a reverse bias voltage by the reverse bias circuit, and
when an inductance value of the coil is L, a voltage applied to the drive circuit is VCC2, an ON period per cycle during which the voltage is applied to the control terminal by the drive circuit is Ton, an OFF period per cycle during which the voltage is not applied to the control terminal by the drive circuit is Toff, and a current value of the control terminal which is applied by the drive circuit and predetermined as a design value is IG, according to:
L>(VCC2×Ton×Toff)/(2×IG×(Ton+Toff))   (1).

US Pat. No. 10,770,983

CIRCUITS AND METHODS FOR SECONDARY-SIDE RECTIFIED VOLTAGE SENSING IN ISOLATED SWITCHED-MODE POWER CONVERTERS

Infineon Technologies Aus...

1. A switched-mode power converter using an isolated topology for converting power from an input source into power for an output load, the switched-mode power converter comprising: a primary side including a power stage coupled to the input source and comprising one or more power switches; a transformer comprising a primary winding coupled to the power stage, and a secondary winding; and a secondary side including: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switched-mode power converter, the filter circuit configured to filter the first rectified voltage, thereby providing a filtered voltage at the output, and a voltage sensor comprising: a resistive voltage divider coupled to a secondary-side voltage node; a first sense terminal for connection to a divided voltage output from the resistive voltage divider, the first sense terminal having a first sense voltage; a first level shifter for shifting the first sense voltage, thereby providing a first level-shifted voltage; a first input buffer configured to input the first level-shifted voltage, and to provide a first buffered output having a voltage corresponding to the first level-shifted voltage and having a first buffered current which is higher than a current at the input of the first input buffer; and a tracking analog-to-digital converter (ADC) having an ADC input coupled to the first buffered output and configured to output a present digital value corresponding to the secondary-side voltage at a present sample instant, wherein a previous digital value output at a previous sample instant serves as an initial estimate for determining the present digital value.

US Pat. No. 10,770,982

ISOLATED SYNCHRONOUS RECTIFYING DC/DC CONVERTER

ROHM CO., LTD., Ukyo-Ku,...

1. An isolated synchronous rectifying DC/DC converter, comprising:a synchronous rectification transistor disposed on a secondary side of the DC/DC converter; and
a synchronous rectification controller configured to control driving of the synchronous rectification transistor,
wherein the synchronous rectification controller includes:
a drain terminal connected to a drain of the synchronous rectification transistor;
a source terminal connected to a source of the synchronous rectification transistor;
a comparator configured to compare a drain voltage of the drain terminal with a predetermined threshold voltage which is set based on a potential of the source terminal;
a first flip-flop to which an OFF signal output from the comparator is input;
a driver configured to output a gate signal to the synchronous rectification transistor based on an output signal of the first flip-flop; and
a first abnormality detection circuit including an abnormality detection comparator configured to compare a voltage of the source terminal with a detection threshold voltage, and configured to output a first abnormality detection signal based on an output of the abnormality detection comparator,
wherein the DC/DC converter is configured as an LLC converter having a first synchronous rectification transistor and a second synchronous rectification transistor,
wherein the synchronous rectification controller further includes:
a first drain terminal connected to a drain of the first synchronous rectification transistor;
a second drain terminal connected to a drain of the second synchronous rectification transistor;
a first source terminal connected to a source of the first synchronous rectification transistor;
a second source terminal connected to a source of the second synchronous rectification transistor;
a first gate terminal connected to a gate of the first synchronous rectification transistor;
a second gate terminal connected to a gate of the second synchronous rectification transistor;
a first driver configured to output a gate signal from the first gate terminal;
a second driver configured to output a gate signal from the second gate terminal;
a frequency divider to which the output signal of the first flip-flop is input; and
a selector configured to switch a path of the comparator between the first drain terminal and the second drain terminal based on an output of the frequency divider, and to switch a path of the first flip-flop between the first driver and the second driver,
wherein the predetermined threshold voltage is set based on potentials of the first source terminal and the second source terminal, and
wherein the abnormality detection comparator is configured to compare a higher one of a voltage of the first source terminal and a voltage of the second source terminal, with the detection threshold voltage.

US Pat. No. 10,770,981

VOLTAGE CONVERSION MODULE AND BOBBIN

CHICONY POWER TECHNOLOGY ...

1. A voltage conversion module comprising:a front side magneto-sensitive unit;
at least one voltage conversion unit;
a core group; and
a bobbin comprising:
a first accommodating part for accommodating the front side magneto-sensitive unit;
 a second accommodating part for accommodating the at least one voltage conversion unit, wherein the second accommodating part comprises:
a first opening disposed at an entrance side of the second accommodating part for accommodating the at least one voltage conversion unit; and
a second opening disposed at an opposite side which is opposite t the entrance side of the second accommodating part; and
 a through hole for accommodating the core group;
wherein, the first opening and the second opening are disposed opposite to each other, and a heat dissipation channel is formed between the first opening, the second opening and the at least one voltage conversion unit.

US Pat. No. 10,770,980

ELECTRONIC CONVERTER AND RELATED METHOD OF OPERATING AN ELECTRONIC CONVERTER

OSRAM GmbH, Munich (DE)

1. An electronic half-bridge converter, comprising:an input comprising two input nodes, wherein the input of the electronic half-bridge converter is configured to receive a first power signal;
an output comprising two output nodes, wherein the output of the electronic half-bridge converter is configured to provide a second power signal;
a transformer comprising a primary winding and a secondary winding;
a half-bridge comprising a first electronic switch and a second electronic switch, wherein the first electronic switch and the second electronic switch are connected in series, wherein the half-bridge is between the input of the electronic half-bridge converter and the primary winding of the transformer;
a rectifier circuit configured to convert current provided via the secondary winding into a rectified current; and
a filter circuit configured to provide the second power signal by filtering the rectified current provided by the rectifier circuit,
wherein the filter circuit comprises:
an input comprising a first input node and a second input node, wherein the input of the filter circuit is configured to receive the rectified current provided by the rectifier circuit;
a first branch connected between the first input node of the filter circuit and the second input node of the filter circuit, wherein the first branch comprises a first inductor and a first capacitor, wherein the first inductor of the first branch and the first capacitor of the first branch are connected in series; and
a second branch connected in parallel with the first branch, wherein the second branch comprises a second inductor, wherein the second inductor of the second branch and the output of the electronic half-bridge converter are connected in series,
wherein the first inductor of the first branch and the second inductor of the second branch share the first input node of the filter circuit,
wherein current provided by the rectifier circuit comprises at least one period during which the current provided by the rectifier circuit is zero, and
wherein, during the at least one period, current flowing through the first inductor of the first branch corresponds to current flowing through the second inductor of the second branch, but with an opposite polarity.

US Pat. No. 10,770,979

LLC RESONANT CONVERTER

OMRON Corporation, Kyoto...

1. An LLC resonant converter comprising:a bridge circuit configured to receive a DC input voltage and to send out a square-wave voltage by a switching operation of a switching element;
an LLC resonant circuit having at least a first capacitor and configured to resonate on receiving the square-wave voltage;
a transformer having a primary side connected to the LLC resonant circuit and a secondary side isolated from the primary side;
a rectifier element configured to convert an output from the secondary side of the transformer into a DC output voltage;
a smoothing capacitor configured to smooth the output voltage from the rectifier element;
a resonant capacitor changeover circuit having a changeover switch and a second capacitor that are connected in series to each other and connected in parallel to the first capacitor;
an input voltage detection circuit configured to detect the input voltage;
an output voltage detection circuit configured to detect the output voltage;
an output current detection circuit configured to detect an output current fed to a load;
a resonant capacitor changeover control section configured to control a state of the changeover switch in the resonant capacitor changeover circuit, based on at least one of the input voltage detected by the input voltage detection circuit, the output voltage detected by the output voltage detection circuit, and the output current detected by the output current detection circuit; and
a bridge circuit control section configured to control the switching operation of the switching element by pulse frequency modulation, and to control an operating frequency of the switching element such that the detected output voltage reaches a desired voltage or in response to a command from the resonant capacitor changeover control section,
wherein the resonant capacitor changeover control section is configured:
to turn on the changeover switch when the detected input voltage gets lower than a changeover voltage,
wherein the resonant capacitor changeover control section is configured:
when the detected input voltage exceeds the changeover voltage, to send a command to the bridge circuit control section to suspend control of the operating frequency for bringing the detected output voltage to the desired voltage and to raise the operating frequency to a changeover frequency;
then, to turn off the changeover switch; and
thereafter, to send a command to the bridge circuit control section to resume the operating frequency control for bringing the detected output voltage to the desired voltage,
wherein the changeover frequency is higher than a first resonance frequency at which a gain of the LLC resonant circuit is maximum while the changeover switch is off, the first resonance frequency being obtained from the detected output voltage and the detected output current, and
wherein a required time between the suspension and the resumption of the operating frequency control for bringing the detected output voltage to the desired voltage is shorter than at least a retention time during which an output of the LLC resonant converter can be maintained after supply of the input voltage has stopped.

US Pat. No. 10,770,978

DC POWER SUPPLY FROM A CONSTANT CURRENT SOURCE

Utah State University, L...

1. A power supply comprising:an active bridge section with input terminals that receive power from a constant current source, wherein the active bridge section operates at a fixed switching frequency;
a resonant section comprising a resonant inductor and a resonant capacitor, the resonant section connected to an output of the active bridge section;
an output rectifier that receives power from the resonant section and comprising output terminals for connection to a load; and
a controller that regulates output current to the load, wherein the controller regulates output current to the load by controlling switching of the active bridge section,
wherein the fixed switching frequency of the active bridge section matches a resonant frequency of the resonant section, and
wherein the controller regulates output current to the load as a function of current gain from the output current to current from the constant current source by controlling switching of the active bridge section as a single control variable over a range from a minimum load condition to a full load condition.

US Pat. No. 10,770,977

SYSTEMS AND METHODS OF OPERATION FOR POWER CONVERTERS HAVING SERIES-PARALLEL MODE ACTIVE CLAMPS

Apple Inc., Cupertino, C...

1. A power conversion apparatus comprising:a flyback converter, the flyback converter including a transformer having a primary winding, an auxiliary primary winding, and a secondary winding, and a first switch configured to be switched to alternately store energy in the transformer and transfer energy from the transformer to an output load; and
an active resonant clamp electrically coupled to the primary winding and the auxiliary primary winding, the active resonant clamp comprising:
a first diode coupled between the primary winding and the auxiliary primary winding and also coupled to the first switch;
a snubber capacitor coupled to the first diode and configured to receive leakage energy from the primary winding through the first diode;
a second diode coupled to the first diode and the snubber capacitor; and
a second switch coupled in series between the second diode and the auxiliary primary winding and configured to return the leakage energy from the snubber capacitor to the transformer.

US Pat. No. 10,770,976

SLEW-CONTROLLED SWITCHED CAPACITORS FOR AC-DC APPLICATIONS

pSemi Corporation, San D...

1. An apparatus comprising slew-control circuitry, a regulator, a switched-capacitor converter, and a controller, wherein said regulator is to receives a first voltage and said switched-capacitor converter is to provide a second voltage, wherein said regulator and said switched-capacitor converter are coupled to each other, wherein said controller is to control said regulator and said switched-capacitor converter, wherein said slew-control circuitry is to control a slew rate of said second voltage, wherein said switched-capacitor converter comprises a plurality of capacitors, first switches, and second switches, wherein closing said first switches and opening said second switches arranges said capacitors into a first state, wherein closing said second switches and opening said first switches arranges said capacitors into a second state, and wherein said controller causes said switched-capacitor converter to transition between said first state and said second state, thereby transferring charge between capacitors of said switched-capacitor converter.

US Pat. No. 10,770,975

RESONANT POWER CONVERTERS WITH SWITCHABLE RESONANT MODES

1. A system comprising:an input port having an input voltage;
an output port having an output voltage;
a first winding in series with a power switch, wherein the power switch is connected between the first winding and a first terminal of the input port, and wherein a second terminal of the input port is connected to the first winding;
a second winding magnetically coupled to the first winding, wherein the second winding is coupled to the output port through a switch network;
a first resonant tank comprising a first resonant capacitor and a first resonant inductor comprising the first winding, wherein the first resonant capacitor is connected between the input port and the junction point of the first winding and the power switch;
a second resonant tank comprising a second resonant capacitor and a second resonant inductor comprising the second winding, wherein the second resonant capacitor is coupled between the second winding and the switch network; and
a controller configured to adjust a switching frequency or a duty cycle of the power switch.

US Pat. No. 10,770,974

MULTI-LEVEL DC-DC CONVERTER WITH LOSSLESS VOLTAGE BALANCING

pSemi Corporation, San D...

1. A multi-level DC-to-DC converter circuit for converting an input voltage to an output voltage, including:(a) a plurality of series-coupled main switches;
(b) an inductor coupled to a node within the plurality of series-coupled main switches;
(c) at least one capacitor coupled in parallel with the plurality of series-coupled main switches and selectively couplable to the inductor, a voltage source, and/or a voltage sink through the plurality of series-coupled main switches;
(d) a control circuit coupled to the plurality of series-coupled main switches and configured to set states for the plurality of series-coupled main switches in at least two patterns defining respective zones having a corresponding range of output voltages, at least one pattern having forward order transition state changes; and
(e) a directional correction circuit, coupled to at least one capacitor and to the control circuit, configured to sense deviations in a voltage across at least one coupled capacitor and generate corresponding directional correction signals that, alone or in combination, force at least one pattern to a backward out-of-order transition state change so as to selectively steer the voltage across the at least one coupled capacitor towards a balanced voltage state.

US Pat. No. 10,770,973

FAST TRANSIENT CURRENT MODE CONTROL CIRCUIT AND METHOD

ANPEC ELECTRONICS CORPORA...

1. A fast transient current mode control circuit, which is applicable for a power converter, the power converter including an upper bridge switch, a lower bridge switch, a storage inductor and a first capacitor, the upper bridge switch being connected to the lower bridge switch, one terminal of the storage inductor being connected to a node between the upper bridge switch and the lower bridge switch, the other terminal of the storage inductor being grounded through the first capacitor, the fast transient current mode control circuit comprising:a slope detector circuit connected to or contacted with an output terminal of the power converter between the storage inductor and the first capacitor, configured to detect an output voltage signal from the output terminal of the power converter between the storage inductor and the first capacitor, and wherein when an output voltage of the output voltage signal drops sharply and a slope of the output voltage signal is larger than a slope threshold, the slope detector circuit is configured to output a transient enhanced signal having a pulse wave, a rising edge of the pulse wave is aligned with a starting point from which the output voltage signal drops sharply, and a falling edge of the pulse wave is aligned with a transition point from which the output voltage signal stops falling and turns to rise;
a switch controller circuit connected to the slope detector circuit and the upper bridge switch, and configured to output a switch control signal to the upper bridge switch to turn on the upper bridge switch during a duty cycle of the pulse wave according to the transient enhanced signal, such that an inductor current flowing through the storage inductor increases to be equal to a load current flowing through a load of a system connected to the output terminal of the power converter; and
an oscillator circuit connected to the switch controller circuit and configured to provide a clock signal to the switch controller circuit.

US Pat. No. 10,770,972

ASYMMETRIC SWITCHING CAPACITOR REGULATOR

Lion Semiconductor Inc., ...

1. A voltage regulator, configured to receive an input voltage at an input node and to provide an output voltage at an output node, comprising:an inductor;
a first capacitor;
a second capacitor;
a switch matrix that is configured to alternate between a first configuration and a second configuration, wherein, in the first configuration, the switch matrix is configured to couple the first capacitor and the second capacitor in a parallel relationship through the inductor, and wherein, in the second configuration, the switch matrix is configured to couple the first capacitor and the second capacitor in a series relationship between the input node and a ground node; and
a plurality of power switches configured to induce a current through the inductor to provide a voltage differential between the first capacitor and the second capacitor in the first configuration, wherein the plurality of switches are configured to alternate between a first state and a second state in the first configuration to provide the voltage differential between the first capacitor and the second capacitor,
wherein, in the second configuration, the second capacitor is coupled to the output node and is in parallel with a decoupling capacitor.

US Pat. No. 10,770,971

SINGLE-INPUT MULTIPLE-OUTPUT (SIMO) CONVERTER HAVING A CONTROLLER WITH SWITCHABLE REST STATES

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising: an inductor having first and second terminals; a first switch coupled between the first terminal a first end of the inductor and a voltage supply terminal node; a second switch coupled between the first terminal end of the inductor and a negative output supply terminal node; a third switch coupled between the second terminal a second end of the inductor and a positive output supply terminal node; a fourth switch coupled between the second terminal end of the inductor and a ground terminal node; and a controller coupled to the first, second, third, and fourth switches, the controller configured to provide: an inductor charge mode; a positive boost mode; a negative boost mode; a first rest state in which the controller closes the first switch and opens the second, third and fourth switches; and a second rest state in which the controller closes the fourth switch and opens the first, second and third switches.

US Pat. No. 10,770,970

FLYING CAPACITOR BASED VARIABLE VOLTAGE CONVERTER

Ford Global Technologies,...

1. A powertrain for a vehicle comprising:a variable voltage converter (VVC) including an inductor, a bus capacitor and a flying capacitor; and
a controller configured to,
in response to a power demand signal exceeding a threshold, modulate switches of the VVC such that an inductor current created by a collapsing field of the inductor is directed into the flying capacitor or the bus capacitor such that a bus capacitor voltage exceeds a flying capacitor voltage, and
in response to the power demand signal dropping below the threshold, modulate switches such that the flying capacitor and the bus capacitor are coupled in parallel.

US Pat. No. 10,770,969

DIGITAL AVERAGE CURRENT-MODE CONTROL VOLTAGE REGULATOR AND A METHOD FOR TUNING COMPENSATION COEFFICIENTS THEREOF

B. G. Negev Technologies ...

1. A digital controller for controlling an average-current-mode voltage regulator having an output connected to a load, said controller comprises:a) a digital voltage-sampling window Analog-to-Digital Converter (ADC), based on Delay-Lines (DLs) and configured to obtain a sample of a voltage error signal being the difference between the reference voltage and the output voltage, and to convert said voltage error signal from analog to digital representation;
b) a digital current-sampling window ADC, based on DLs and configured to obtain a sample of the inductor current and to convert said inductor current from analog to digital representation, wherein said window DL-ADC has a constant reference value for the voltage and fixed sampling window for the current, while sampling both the output voltage and inductor current, such that the difference between the inductor current and a constant reference represents the current error;
c) a digital compensator for voltage regulation, receiving as input the digital voltage error signal, configured to generate a current reference signal based thereupon;
d) a digital compensator for current regulation, receiving as inputs the inductor current signal and the current reference signal, configured to generate a duty-ratio command signal based thereupon; and
e) a digital hybrid High Resolution (HR) Digital Pulse Width Modulator (HR-DPWM) receiving as input the duty-ratio command signal and generating a pulse-width-modulated signal that is fed to the gates of the converter's transistors, to thereby control the current and voltage supplied to said load,
wherein the digital voltage-sampling window ADC and the digital current-sampling window ADC are a single digital window ADC based on DLs, said single digital window ADC further comprises:
f) an input multiplexer (MUX) and an output de-multiplexer for switching between voltage and current sampling.

US Pat. No. 10,770,968

SWITCHING POWER CONVERTER WITH ADAPTIVE PULSE FREQUENCY MODULATION

DIALOG SEMICONDUCTOR INC....

1. A controller for controlling a cycling of a power switch transistor in a switching power converter, the controller comprising:a feedback loop circuit including an error amplifier configured to generate an error signal responsive to an error between the output voltage and the desired value and including a loop filter configured to filter the error signal to form a control voltage signal; and
a logic circuit configured to generate a proportionality constant responsive to the control voltage signal, wherein for each cycle of the power switch transistor, the logic circuit is configured to switch on the power switch transistor for an on-time and to switch off the power switch transistor during a reset period followed by a delay period, and wherein the logic circuit is further configured to set the delay period to equal a product of a sum of the on-time and the reset period and the proportionality constant minus the sum of the on-time and the reset period.

US Pat. No. 10,770,967

PREDICTIVE POWER FACTOR CONTROL FOR ELECTRONIC SYSTEMS

Hewlett Packard Enterpris...

1. An electronic system, comprising:a load comprising one or more electronic components, the load being variable based on changes in operating states of the electronic components;
a power supply that provides power to the load;
a power factor control circuit configured to dynamically adjust a power factor of the power supplied by the power supply;
an additional load;
a hardware allocation resource, coupled to the load controller;
a power coupling circuit, coupled to the hardware allocation resource and responsive to the hardware allocation resource to selectively couple the additional load to the power supply;
the hardware allocation resource being operable to communicate a notification of a pending connection of the additional load to the power supply; and
a load controller that is responsive to the notification of the pending connection of the additional load to the power supply to provide a pending load change notification to the power factor control circuit;
wherein the power factor control circuit is responsive to the pending load change notification to predictively adjust the power factor of the power from the power supply to compensate for a change in the load indicated by the pending load change notification.

US Pat. No. 10,770,966

POWER FACTOR CORRECTION CIRCUIT AND METHOD INCLUDING DUAL BRIDGE RECTIFIERS

Emerson Climate Technolog...

1. A power factor correction circuit comprising:a first bridge rectifier configured to receive an alternating current (AC) voltage;
a power converter comprising a switch and configured to (i) receive an output of the first bridge rectifier, (ii) convert the output of the first bridge rectifier to a first direct current (DC) voltage, and (iii) supply the first DC voltage to a DC bus to power a compressor;
a second bridge rectifier configured to (i) receive the AC voltage, and (ii) bypass at least one of the first bridge rectifier, a choke and a diode of the power factor correction circuit to provide a rectified AC voltage out of the second bridge rectifier to the DC bus to power the compressor; and
a control module configured to control operation of a driver to transition the switch between an open state and a closed state to adjust a second DC voltage on the DC bus, wherein the second DC voltage, depending on the AC voltage and the second DC voltage, is based on at least one of (i) the first DC voltage, and (ii) the rectified AC voltage generated by the second bridge rectifier.

US Pat. No. 10,770,965

CONTROL OF SERIES-PARALLEL MODE (SPM) CLAMPED FLYBACK CONVERTER

Apple Inc., Cupertino, C...

1. A power conversion apparatus, comprising:a primary coil configured to receive an input voltage;
a secondary coil electromagnetically coupled to the primary coil and configured to provide an output voltage;
a first switch coupled to the primary coil and configured to control a flow of current through the primary coil;
a second switch configured to control a flow of current through an active clamp circuit, the active clamp circuit coupled in parallel with the primary coil and configured to absorb a leakage energy from a leakage inductance associated with the primary coil and the secondary coil, the active clamp circuit comprising a first capacitor and a second capacitor; and
a controller coupled to the first switch and the second switch, the controller configured to:
turn the first switch on, so as to store energy in the primary coil;
turn the first switch off, so as to charge the first and the second capacitors in series;
turn the second switch on when a voltage across the first switch approaches a peak value, so as to discharge the first and the second capacitors in parallel; and
turn the second switch off when at least one of: a voltage across the first capacitor and a voltage across the second capacitor, falls to a predetermined voltage level.

US Pat. No. 10,770,964

OVERSHOOT REDUCTION CIRCUIT FOR BUCK CONVERTER

ANPEC ELECTRONICS CORPORA...

1. An overshoot reduction circuit for a buck converter, the buck converter including an upper bridge switch, a lower bridge switch and an operational transconductance amplifier, wherein a first terminal of the upper bridge switch is connected to an input voltage source, a second terminal of the upper bridge switch is connected to a first terminal of the lower bridge switch, a second terminal of the lower bridge switch is grounded, a first input terminal of the operational transconductance amplifier is connected to a first reference voltage source, a second input terminal of the operational transconductance amplifier is connected to a node between the second terminal of the upper bridge switch and the first terminal of the lower bridge switch, and the overshoot reduction circuit comprising:an operational amplifier having a first amplification input terminal and a second amplification input terminal, wherein the first amplification input terminal of the operational amplifier is connected to a node between the first terminal of the upper bridge switch and the second terminal of the lower bridge switch to obtain a buck converted signal, an output terminal of the operational amplifier is grounded through a voltage divider circuit, the voltage divider circuit includes a first resistor and a second resistor, the second amplification input terminal of the operational amplifier is connected to a node between the first resistor and the second resistor to obtain a voltage feedback signal, and the operational amplifier is configured to output an operation amplified signal according to the buck converted signal and the voltage feedback signal;
a first sampler circuit grounded through a first capacitor and configured to sample a first capacitor voltage signal of the first capacitor according to a lower bridge conducted signal of the lower bridge switch from the buck converter;
a pulse generator circuit configured to output a pulse signal according to the lower bridge conducted signal from the buck converter;
a pulse calculator circuit connected to the first sampler circuit and the pulse generator circuit, and configured to store and output a first sample compared signal according to the first capacitor voltage signal and the pulse signal;
a second sampler circuit grounded through a second capacitor and configured to sample a second capacitor voltage signal of the second capacitor according to the lower bridge conducted signal of the lower bridge switch from the buck converter;
a first comparator having a first comparison input terminal connected to the second sampler circuit and a second comparison input terminal connected to the pulse generator circuit, and configured to compare the second capacitor voltage signal received through the first comparison input terminal with the first sample compared signal received through the second comparison input terminal to output a first comparing signal;
a second comparator having a third comparison input terminal connected to a second reference voltage source and a fourth comparison input terminal connected to an output terminal of the operational transconductance amplifier, wherein the second comparator receives a reference voltage from the second reference voltage source through the third comparison input terminal and receives an error amplified signal from the operational transconductance amplifier through the fourth comparison input terminal, the second comparator is configured to compare the error amplified signal with the reference voltage to output a second comparing signal; and
a switch driver circuit connected to the first comparator, the second comparator, and a control terminal of the lower bridge switch, and configured to output a lower bridge switching signal to the lower bridge to control the lower bridge according to the first comparing signal and the second comparing signal.

US Pat. No. 10,770,963

DC-DC CONVERTER HAVING A SWITCH ON-TIME CONTROL LOOP WITH A SWITCHED-CAPACITOR CIRCUIT FOR ERROR-BASED ADJUSTMENT

TEXAS INSTRUMENTS INCORPO...

1. A system that comprises:a direct-current to direct-current (DC-DC) converter having:
an output node;
at least one electronic switch;
a first feedback loop configured to control a voltage at the output node by adjusting a first switching parameter of the at least one electronic switch; and
a second feedback loop configured to adjust a second switching parameter of the at least one electronic switch, wherein: the second feedback loop includes a switched-capacitor circuit configured to provide a threshold signal based on an error between a reference signal and a control signal for the at least one electronic switch; the second feedback loop is configured to adjust the second switching parameter based on a comparison of an on-time signal with the threshold signal; and the switched-capacitor circuit comprises a differential integrator and a summer circuit configured to adjust the threshold signal based on the error; and
an RC filter at the output of the differential integrator, the RC filter configured to eliminate noise generated at the differential integrator, wherein the output of the RC filter corresponds to the threshold signal.

US Pat. No. 10,770,962

CONVERTER CELL COMPRISING AN ENERGY CONVERTER IN PARALLEL TO A CLAMP INDUCTOR

ABB Schweiz AG, Baden (C...

1. A modular multilevel converter cell comprising:a first terminal;
a second terminal;
a plurality of switching elements provided with respective gate units;
an energy storage element;
a clamp inductor in a serial connection with the energy storage element,
wherein the energy storage element is provided in parallel, via said clamp inductor, across a first leg of two switching elements, thereby the clamp inductor is configured to restrict a rate of change of current from the energy storage element to the switching elements; and
a first energy converter in the form of a DC, direct current, to DC converter provided in parallel to the clamp inductor, the first energy converter being configured to power the gate units by utilising energy from the clamp inductor when the converter cell changes state to be in a short circuit state.

US Pat. No. 10,770,961

POWER CONVERTER WITH ADJUSTABLE RAMP

M3 Technology Inc., Taip...

16. A converter comprising:a first switch and a second switch connected in series between an input power source and ground;
an inductor connected between a common node of the first switch and the second switch, and an output capacitor;
a control apparatus configured to generate gate drive signals for the first switch and the second switch, wherein the control apparatus comprises a feedback control apparatus and a ramp generator, wherein the ramp generator is configured to dynamically adjust an amplitude of a ramp to a different value based upon different operating conditions through providing either a supply current or a sink current to the ramp generator;
an on-time control generator; and
a latch having a set input configured to receive an output signal of the control apparatus and a reset input configured to receive an output signal of the on-time control generator.