US Pat. No. 10,714,476

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:channel patterns disposed on a substrate;
a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and
a gate electrode disposed around the channel patterns,
wherein an interface where the gate electrode meets an overlapping gate capping pattern is recessed between adjacent channel patterns,
wherein the channel patterns are spaced apart from the substrate, and
wherein the gate electrode is disposed between the substrate and the channel patterns.

US Pat. No. 10,714,475

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:first and second epitaxial structures, wherein the first and second epitaxial structures have different cross sections;
first and second top metal alloy layers respectively in contact with the first and second epitaxial structures; and
first and second bottom metal alloy layers respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers, wherein the first top metal alloy layer and the first bottom metal alloy layer are made of different materials, and the first top metal alloy layer and the first epitaxial structure comprise a same element.

US Pat. No. 10,714,474

HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:a substrate comprising a p-type semiconductor;
a drain-centered p-channel metal oxide semiconductor (PMOS) transistor having:
a first gate dielectric layer at a top surface of the substrate;
a first gate on the first gate dielectric layer, wherein the first gate does not overlap field oxide;
an n-type threshold adjustment region, said threshold adjustment region being electrically connected to an n-type buried layer;
a PMOS drain extension and a PMOS source extension, wherein the PMOS drain extension and PMOS source extension are spaced apart from the n-type threshold adjustment region by the p-type semiconductor; and
a PMOS drain in the PMOS drain extension and an PMOS source in the PMOS source extension, wherein the first gate surrounds the PMOS drain; and
a drain centered n-channel metal oxide semiconductor (NMOS) transistor having:
an n-type NMOS drain extension and an n-type NMOS source extension;
a p-type threshold adjustment region;
an NMOS drain in the NMOS drain extension and an NMOS source in the NMOS source extension;
a second gate dielectric layer at the top surface of the substrate; and
a second gate on the second gate dielectric layer, wherein the second gate surrounds the NMOS drain and the second gate does not overlap field oxide.

US Pat. No. 10,714,473

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first fin pattern extending in a first direction;
a device isolation film surrounding the first fin pattern and exposing an upper portion of the first fin pattern;
first and second gate lines being adjacent to each other and extending in a second direction intersecting the first direction on the device isolation film and the first fin pattern;
first and second gate isolations spaced apart from each other in the second direction, isolating the first and second gate lines and contacting the device isolation film;
third to fifth gate isolations sequentially disposed along the second direction between the first and second gate isolations, each of the third to fifth gate isolations isolating one of the first and second gate lines; and
an interlayer insulating film surrounding the first to fifth gate isolations on the device isolation film,
wherein the first gate line is divided into three portions between the first and second gate isolations,
wherein the second gate line is divided into two portions between the first and second gate isolations, and
wherein the interlayer insulating film has a material different from a material of the first to fifth gate isolations.

US Pat. No. 10,714,472

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A method of fabricating a semiconductor device, the method comprising:forming an insulating layer comprising a first gap region and a second gap region on a substrate, wherein the insulating layer comprises a first portion that defines an upper portion of the first gap region;
forming first and second lower work-function electrode patterns in the first and second gap regions, respectively, wherein the first lower work-function electrode pattern exposes the first portion of the insulating layer;
forming a first upper work-function electrode layer on the first lower work-function electrode pattern and on an upper surface of the insulating layer, wherein the first upper work-function electrode layer directly contacts the first portion of the insulating layer;
forming a second upper work-function electrode layer on the first upper work-function electrode layer in the first gap region, on the second lower work-function electrode pattern in the second gap region, and on the upper surface of the insulating layer, wherein the second upper work-function electrode layer comprises a first recess in the first gap region and a second recess in the second gap region;
forming hard mask patterns in the first recess and the second recess, respectively; and
forming first and second upper work-function electrode patterns in the first and second gap regions, respectively, by etching the second upper work-function electrode layer using the hard mask patterns as an etch mask,
wherein the first upper work-function electrode layer is etched during etching the second upper work-function electrode layer, and
wherein, after the first and second upper work-function electrode patterns are formed, the first upper work-function electrode layer and the first upper work-function electrode pattern expose the first portion of the insulating layer.

US Pat. No. 10,714,471

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:forming a plurality of gate structures on a base structure, a source/drain region in the base structure on each side of each gate structure, and an interlayer dielectric layer on the base structure to cover sidewall surfaces of the gate structures, wherein the plurality of gate structures are separated by a plurality of isolation areas;
forming a first mask layer to cover the interlayer dielectric layer and the gate structures and a second mask layer to cover the first mask layer, wherein the second mask layer and the first mask layer are made of different materials;
forming a plurality of first patterned layers separated by a plurality of first openings on the second mask layer, wherein a projected pattern of the plurality of first patterned layers covers at least top surfaces of the gate structures, and each first opening is formed across a source region, a drain region, and a portion of an isolation area between the source region and the drain region;
forming a patterned second mask layer by etching the second mask layer using the plurality of first patterned layers as an etch mask until a portion of the first mask layer is exposed;
forming a plurality of second patterned layers on an exposed portion of first mask layer and a remaining portion of the second mask layer, wherein the plurality of second patterned layers are formed vertically above the isolation areas between neighboring source and drain regions;
forming a patterned first mask layer by etching the first mask layer using the plurality of second patterned layers as an etch mask until a portion of the interlayer dielectric layer is exposed;
forming a plurality of contact vias to expose top surfaces of source/drain regions by etching the interlayer dielectric layer using the patterned first mask layer and the patterned second mask layer as an etch mask; and
forming a plurality of metal silicide layers on the source/drain regions exposed in the plurality of contact vias.

US Pat. No. 10,714,470

METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a substrate structure including a substrate;
a first bottom source/drain;
a first fin formed on a vertical transistor portion of the substrate;
a second bottom source/drain;
a second fin formed on a varactor portion of the substrate;
a bottom spacer formed on the first bottom source/drain and the second bottom source/drain;
depositing a gate oxide on the vertical transistor portion and the varactor portion.

US Pat. No. 10,714,469

ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE

Semiconductor Manufacturi...

1. An electrostatic discharge protection structure, comprising:a base substrate including a substrate and a fin portion on the substrate, wherein the substrate includes a first region and a second region;
a first doped layer on a surface of the fin portion in the first region; and
a second doped layer on a surface of the fin portion in the second region and on a surface of the substrate in the second region, wherein an aspect ratio of gaps between adjacent fin portions in the second region is smaller than an aspect ratio of gaps between adjacent fin portions in the first region; wherein:
the second doped layer is directly on and completely covers a top surface and side surfaces of the fin portion in the second region, and a top surface of the substrate in the second region.

US Pat. No. 10,714,468

OPTICAL INTEGRATED CIRCUIT SYSTEMS, DEVICES, AND METHODS OF FABRICATION

STMICROELECTRONICS S.R.L....

1. An optical integrated circuit device comprising:a semiconductor substrate;
a first waveguide made of a first material and disposed over the semiconductor substrate, the first waveguide comprising a parallel region and a tapered region;
a first cladding structure disposed over and surrounding the parallel region of the first waveguide;
a first extension made of the first material and disposed over the semiconductor substrate, the first extension physically contacting the parallel region of the first waveguide, wherein the first extension comprises a first portion within the first cladding structure and a second portion outside the first cladding structure; and
an electrostatic discharge (ESD) protection structure electrically coupled to the first extension.

US Pat. No. 10,714,467

INTEGRATED CIRCUIT (IC) DEVICE

Samsung Electronics Co., ...

1. An integrated circuit (IC) device comprising:a logic cell having an area defined by a cell boundary,
the logic cell including a first device region, a device isolation region, and a second device region,
the first device region and the second device region arranged apart from each other in a first direction that is perpendicular to a second direction,
the device isolation region being between the first device region and the second device region,
a first maximum length of the first device region in the second direction being less than a width of the cell boundary in the second direction, and
a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

US Pat. No. 10,714,466

LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A layout pattern for magnetoresistive random access memory (MRAM), comprising:a first magnetic tunneling junction (MTJ) pattern on a substrate;
a second MTJ pattern adjacent to the first MTJ pattern; and
a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement, the first MTJ pattern comprises a circle while the first metal interconnection pattern comprises an ellipse, and the first MTJ pattern and the second MTJ pattern are on a same level.

US Pat. No. 10,714,465

MOTOR DRIVE CIRCUIT, SEMICONDUCTOR APPARATUS, AND ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. A motor drive circuit including a first H bridge circuit that is connected to a first node to which a first power source potential is supplied, to a second node to which a second power source potential that is lower than the first power source potential is supplied, and to a third node and fourth node that are respectively connected to two terminals of a motor to be driven,wherein the first H bridge circuit includes:
a first P-channel MOS transistor that is disposed in an N-type first impurity region in a P-type semiconductor substrate and is connected between the first node and the third node;
a first N-channel MOS transistor that is disposed in an N-type second impurity region in the semiconductor substrate or is disposed directly in the semiconductor substrate having an N-type second impurity region, and that is connected between the second node and the third node;
a second P-channel MOS transistor that is disposed in an N-type third impurity region in the semiconductor substrate and is connected between the first node and the fourth node; and
a second N-channel MOS transistor that is disposed in an N-type fourth impurity region in the semiconductor substrate or is disposed directly in the semiconductor substrate and includes an N-type fourth impurity region, and that is connected between the second node and the fourth node, and
a distance between the N-type first impurity region and the N-type third impurity region is smaller than a distance between the N-type first impurity region and the N-type second impurity region, smaller than a distance between the N-type third impurity region and the N-type fourth impurity region, and smaller than a distance between the N-type second impurity region and the N-type fourth impurity region.

US Pat. No. 10,714,464

METHOD OF SELECTIVELY TRANSFERRING LED DIE TO A BACKPLANE USING HEIGHT CONTROLLED BONDING STRUCTURES

GLO AB, Lund (SE)

1. A method of transferring devices to a target substrate, comprising:providing a supply coupon comprising a combination of a source substrate and devices thereupon;
providing a target substrate that includes bonding sites;
forming first bonding material portions on one of surfaces of the devices or surfaces of the bonding sites of the target substrate;
coining the first bonding material portions to form first bonding material pads having a flatter bonding surface than that of the first bonding material portions;
bonding a first set of the first bonding material pads with respective bonding structures to form a first set of bonded material portions, wherein the first set of the first bonding material pads is located on one of a first set of devices or the first set of bonding sites of the target substrate, and the bonding structures are located on another one of the first set of devices or the first set of the bonding sites of the target substrate, wherein the step of bonding the first set of the first bonding material pads with respective the first set of bonding structures comprises selectively reflowing the first set of the first bonding pads of the first set of devices without reflowing a second set of the first bonding material pads of the second set of devices, and wherein the selective reflowing is performed by irradiating a laser beam on the first set of the first bonding material pads; and
detaching the first set of devices from the source substrate, wherein the first set of the devices is bonded to the bonding sites of the target substrate by the first set of bonded material portions, while a remaining second set of devices remains on the source substrate.

US Pat. No. 10,714,463

METHOD OF FORMING SEMICONDCUTOR DEVICE PACKAGE

Taiwan Semiconductor Manu...

1. A structure, comprising:a semiconductor die;
a semiconductor package;
a warpage adjusting component disposed on a back surface of the semiconductor package; and
an encapsulating material encapsulating the semiconductor die, the semiconductor package, and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material.

US Pat. No. 10,714,462

MULTI-CHIP PACKAGE WITH OFFSET 3D STRUCTURE

Advanced Micro Devices, I...

1. A semiconductor chip device, comprising:a reconstituted semiconductor chip package including an interposer having a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by an inorganic dielectric layer on the metallization stack, plural interconnects positioned between and electrically connecting the first semiconductor chip and the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

US Pat. No. 10,714,461

ELECTRONIC UNIT

VISHAY SEMICONDUCTOR GMBH...

1. An electronic unit comprising:at least one first electronic component and one second electronic component that are fastened to a substrate; and
a shielding arranged between the first and second electronic components, wherein the shielding comprises an elevated portion that projects from a plane defined by the substrate or extends from a surface of the substrate, and wherein the shielding acts as a shielding and is formed in one piece with the substrate, and wherein at least one of the first electronic component and the second electronic component is electrically conductively connected, by a wire, to a contact point arranged at a base section of a third recess.

US Pat. No. 10,714,460

LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

Citizen Electronics Co., ...

1. A light-emitting device comprising:a board;
a plurality of light-emitting elements mounted on a mount region of the board so that a space between adjacent light-emitting elements is 5 ?m or more and 50 ?m or less;
a rectangular resin frame formed from a white resin around the mount region, wherein the board comprises a flat region surrounding the rectangular resin frame;
a first resin free from any phosphor, injected into the space among the plurality of light-emitting elements and made to invade the space among the plurality of light-emitting elements with the aid of the capillary phenomenon so that the space among the plurality of light-emitting elements is filled with the first resin;
a second resin containing a phosphor and covering an exposed part of the plurality of light-emitting elements; and
a lens, the incident edge of which is of a circular shape of 10 mm or less in diameter, configured to condense light emitted from the plurality of light-emitting elements, the lens comprising a lower concave recessed from a bottom surface of the lens, the lens being mounted on the board with the bottom of the lens in contact with the flat region, and the second resin being placed within the lower concave, wherein there is a gap between the lens and the second resin in the lower concave.

US Pat. No. 10,714,459

LIGHT EMITTING DEVICE WITH LED STACK FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME

Seoul Viosys Co., Ltd., ...

1. A light emitting device for a display, comprising:a first substrate;
a first LED sub-unit disposed under the first substrate;
a second LED sub-unit disposed under the first LED sub-unit;
a third LED sub-unit disposed under the second LED sub-unit;
a first transparent electrode interposed between the first and second LED sub-units, and in ohmic contact with a lower surface of the first LED sub-unit;
a second transparent electrode interposed between the second and third LED sub-units, and in ohmic contact with a lower surface of the second LED sub-unit;
a third transparent electrode interposed between the second transparent electrode and the third LED sub-unit, and in ohmic contact with an upper surface of the third LED sub-unit;
at least one current spreader connected to at least one of the first, second, and third LED sub-units;
electrode pads disposed on the first substrate; and
through-hole vias formed through the first substrate to electrically connect the electrode pads to the first, second, and third LED sub-units,
wherein at least one of the through-hole vias is formed through the first substrate, the first LED sub-unit, and the second LED sub-unit.

US Pat. No. 10,714,458

MULTI-LED SYSTEM

1. A multi-LED system comprising:a carrier; and
a plurality of light-emitting diodes arranged on the carrier,
wherein the carrier has a main body, and a plurality of electrical components are embedded in the main body,
the carrier has upper metallizations arranged on a top side of the main body,
the upper metallizations comprising first upper metallizations for contact-connection of the LEDs and second upper metallizations for further contact-connection of the same one of the embedded components,
the second upper metallizations are separate from the first upper metallizations, the carrier has lower metallizations arranged on a bottom side of the main body,
the second upper metallizations connect to the lower metallizations by vias, wherein the vias are laterally offset from the embedded component that is connected to the second upper metallizations,
the second upper metallizations are not connected to any of the LEDs, and
the embedded component is only connected to the lower metallizations by the upper metallizations and the vias from the upper to the lower metallizations.

US Pat. No. 10,714,457

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A device comprising:a first integrated circuit die comprising a first conductive feature, a first insulating layer around the first conductive feature, and a bond pad on the first conductive feature and the first insulating layer;
a second integrated circuit die comprising a second conductive feature and a second insulating layer around the second conductive feature; and
a conductive bonding layer connecting the bond pad to the second conductive feature, a reflow temperature of the conductive bonding layer being lower than a reflow temperature of the bond pad,
wherein the second insulating layer is physically separated from the bond pad by a void, sidewalls of the conductive bonding layer and a top surface of the bond pad being exposed to the void.

US Pat. No. 10,714,456

DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES

Micron Technology, Inc., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a redistribution structure having a first surface and a second surface opposite the first surface, wherein forming the redistribution structure includes forming the redistribution structure without a pre-formed substrate;
mounting a first semiconductor die to the first surface of the redistribution structure and electrically coupling the first semiconductor die to the redistribution structure;
mounting a second semiconductor die to the second surface of the redistribution structure and electrically coupling the second semiconductor die to the redistribution structure; and
disposing a molded material on the first surface and the second surface of the redistribution structure and at least partially around the first semiconductor die and the second semiconductor die.

US Pat. No. 10,714,455

INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A CHIP RECESS

Intel IP Corporation, Sa...

1. A method of assembling an integrated circuit (IC) package, the method comprising:receiving an IC chip having a front side including a plurality of first metal features, and a back side separated from the front side by an initial chip z-thickness;
forming a molding compound around a perimeter of the IC chip, wherein forming the molding compound contacts a sidewall of the IC chip with the molding compound;
recessing the IC chip back side relative to a back side of the molding compound by removing a thickness of a semiconductor substrate with a process that exposes a sidewall of at least some of the molding compound that was in contact with a portion of the sidewall of the IC chip; and
stacking a component having a smaller area than that of the IC chip within a recess over the recessed back side of the IC chip and spaced apart from the sidewall of the molding compound.

US Pat. No. 10,714,454

STACK PACKAGING STRUCTURE FOR AN IMAGE SENSOR

Semiconductor Components ...

1. A semiconductor package comprising:a substrate;
a first semiconductor device coupled to a surface of the substrate, the first semiconductor device including an image signal processor (ISP) die;
a second semiconductor device coupled to the surface of the substrate;
an image sensor device coupled to the first semiconductor device and the second semiconductor device, the first semiconductor device being disposed between the surface of the substrate and the image sensor device;
a transparent member coupled to the image sensor device;
at least one bond wire connected to the image sensor device and the surface of the substrate;
an inner molding disposed between the surface of the substrate and the image sensor device, the first semiconductor device being encapsulated within the inner molding; and
an outer molding disposed on the surface of the substrate, the at least one bond wire being encapsulated within the outer molding, the outer molding being coupled to the transparent member.

US Pat. No. 10,714,453

SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP

Samsung Electronics Co., ...

1. A semiconductor package comprising:a package substrate;
a first semiconductor chip on the package substrate, the first semiconductor chip having an upper surface and a first upward pad disposed on the upper surface of the first semiconductor chip;
a second semiconductor chip disposed on the first semiconductor chip, the first semiconductor chip laterally offset relative to the second semiconductor chip, and the second semiconductor chip having a lower surface and a first downward pad disposed on the lower surface of the second semiconductor chip;
a first bonding wire extending between and electrically connecting the first upward pad and the package substrate; and
a first inter-chip connector interposed between the first upward pad and the first downward pad,
wherein a side surface of the second semiconductor chip overlies the first upward pad, and
wherein the first upward pad includes a planar upper surface connected to both the first bonding wire and the first inter-chip connector.

US Pat. No. 10,714,452

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. A package structure, comprising:a first die and a second die, both the first die and the second die comprise:
a first surface;
a second surface disposed opposite to the first surface; and
at least two sidewalls disposed between the first surface and the second surface; and
an underfill layer covering and directly contacting the first surface of the first die, the first surface of the second die and at least one sidewall of the first die, wherein at least one sidewall of the first die is and both two sidewalls of the second die are not covered by the underfill layer, wherein at least one sidewall of the underfill layer, the at least one sidewall of the first die which is not covered by the underfill layer and one of the two sidewalls of the second die which are not covered by the underfill layer are coplanar with each other along a first direction, and wherein the first direction is perpendicular to the first surface.

US Pat. No. 10,714,451

TILING STRUCTURE TYPE LIGHT APPARATUS FOR ORGANIC LIGHT EMITTING DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode (OLED) lighting apparatus of a tiling structure, comprising:a first flexible OLED panel in which a bezel area and a part of a light emitting area are bent;
a second flexible OLED panel in which a bezel area arranged adjacent to the bezel area of the first flexible OLED panel is bent;
a fastening member to couple the first and second flexible OLED panels; and
a light guide plate which is arranged on the fastening member and guides a light which is emitted from a bent side of the first flexible OLED panel upward.

US Pat. No. 10,714,450

METHOD OF BONDING TERMINAL OF SEMICONDUCTOR CHIP USING SOLDER BUMP AND SEMICONDUCTOR PACKAGE USING THE SAME

JMJ Korea Co., Ltd., Buc...

1. A method of bonding a terminal of a semiconductor chip using a solder bump, the method comprising:preparing a semiconductor chip with an aluminum (Al) pad terminal formed thereon (S-1);
forming the solder bump on the Al pad terminal through a primary solder (S-2);
attaching the solder bump and a metal structure to each other via a secondary solder with a higher melting point than a melting point of the primary solder (S-3), wherein the secondary solder is positioned between the solder bump and the metal structure;
performing a heat treatment in a state in which the solder bump and the secondary solder are attached to each other at a heat treatment temperature determined based on the melting point of the secondary solder (S-4); and
mixing the primary solder and the secondary solder that are melted during the heat treatment and converting a resulting mixture into a tertiary solder including only one solder layer having a re-melting point higher than the melting point of the primary solder (S-5),
wherein the forming the solder bump (S-2) comprises forming an intermetallic compound (IMC) on a portion of the solder bump adjacent to the Al pad terminal to be distributed by a predetermined region during formation of the solder bump,
wherein the IMC includes Al.

US Pat. No. 10,714,449

DIE PROCESSING

Invensas Bonding Technolo...

1. A method comprising:applying, to a substrate including a wafer, a protective layer to a bonding surface of the wafer;
singulating the wafer and protective layer into a plurality of semiconductor die components;
removing the protective layer to expose an individual bonding surface on each semiconductor die component of the plurality of semiconductor die components; and
preparing the individual bonding surface of one or more semiconductor die components of the plurality of semiconductor die components for bonding to a surface of another substrate.

US Pat. No. 10,714,448

CHIP MODULE WITH POROUS BONDING LAYER AND STACKED STRUCTURE WITH POROUS BONDING LAYER

UNIMICRON TECHNOLOGY CORP...

1. A chip module, comprising:a chip body;
a bump disposed on the chip body; and
a first bonding layer wrapping around an entirety of a sidewall of the bump, wherein the first bonding layer is made of porous copper and the bump is made of porous-free copper.

US Pat. No. 10,714,447

ELECTRODE TERMINAL, SEMICONDUCTOR DEVICE, AND POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. An electrode terminal, comprising:a body composed of a single length of wire and made of only a first metal material, wherein an elastic part is provided between one end of said body and an other end of said body; and
a first bonding part located on a flat surface of said one end of said body, said first bonding part composed of a second metal material other than said first metal material, the second metal material being clad directly to the first metal material with nothing in-between in cross-section, and being clad to the first metal material proximate to the first bonding part in cross-section,
said first bonding part being ultrasonically bonded directly to a first bonded member with nothing in-between in cross-section, the first bonded member being a bondable metal disposed directly on a semiconductor chip, wherein
said elastic part includes at least one of a notch and a plurality of discrete bends in the body, such that said elastic part produces a spring effect and thus is elastically deformable,
a surface, which is ultrasonically bonded to said first bonded member in said first bonding part, is provided with a groove or irregularities, and
said groove or said irregularities of said electrode terminal accommodate a protruding part provided in said first bonded member.

US Pat. No. 10,714,446

APPARATUS WITH MULTI-WAFER BASED DEVICE COMPRISING EMBEDDED ACTIVE AND/OR PASSIVE DEVICES AND METHOD FOR FORMING SUCH

Intel Corporation, Santa...

6. A method comprising:forming a substrate;
fabricating a first active device adjacent to the substrate;
forming a first set of one or more layers to interconnect with the first active device;
forming a second set of one or more layers;
fabricating a second active or passive device adjacent to the second set of one or more layers;
forming a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets;
dry etching a surface of the second wafer such that pads are exposed; and
forming solder bumps on the exposed pads.

US Pat. No. 10,714,445

THERMAL BONDING SHEET, THERMAL BONDING SHEET WITH DICING TAPE, BONDED BODY PRODUCTION METHOD, AND POWER SEMICONDUCTOR DEVICE

NITTO DENKO CORPORATION, ...

1. A thermal bonding sheet comprising a pre-sintering layer containing a mixture of copper particles and polypropylene carbonate.

US Pat. No. 10,714,444

ANISOTROPIC CONDUCTIVE FILM

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film having a regular disposition region in which conductive particles are disposed regularly in an insulating resin binder,wherein the anisotropic conductive film is formed on a release film, and
a standard region including no sections with more than a prescribed number of consecutive omissions in conductive particles is present in the regular disposition region over a prescribed width in a short-side direction of the anisotropic conductive film and at least a prescribed length in a long-side direction of the anisotropic conductive film.

US Pat. No. 10,714,443

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:a substrate including, in a central portion of a main face of the substrate, a plurality of first element formation regions each having a rectangular flat plane shape; and
a plurality of electrode pads formed above the first element formation regions,
wherein for each first element formation region from among the plurality of first element formation regions
a first row of dummy electrode pads are arrayed, above a peripheral portion of the main face, along a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion,
wherein the first row of dummy electrode pads opposes a row of the plurality of electrode pads that are arrayed above the first element formation region with the first edge therebetween,
wherein the first element formation region includes a second edge that touches a corner of the first edge, and that forms a boundary between the first element formation region and the peripheral portion,
wherein the semiconductor device further comprises a second row of dummy electrode pads arrayed above the peripheral portion of the main face along the second edge, the second row of dummy electrode pads opposing a row of the plurality of electrode pads that are arrayed above the first element formation region with the second edge therebetween, and
wherein ball shaped projecting electrodes are formed at the plurality of electrode pads and at the dummy electrode pads that are exposed in a triangular region surrounded by respective first and second edges of the plurality of first element formation regions, and the ball shaped projecting electrodes are not formed at the dummy electrode pads that are exposed in regions that do not overlap the triangular region of the peripheral portion.

US Pat. No. 10,714,442

INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

9. An interconnect structure comprising:a contact pad on a top surface of a first substrate;
a first passivation layer on the top surface of the first substrate, the first passivation layer directly adjoining a first portion of a top surface of the contact pad;
a second passivation layer on the first passivation layer, the second passivation layer directly adjoining a second portion of the top surface of the contact pad;
a post-passivation interconnect (PPI) contacting a third portion of the top surface of the contact pad and extending along a top surface of the second passivation layer;
a third passivation layer directly adjoining a top surface of the PPI;
a connector on the top surface of the PPI, the third passivation layer directly adjoining a lower portion of the connector;
a molding compound disposed on a surface of the third passivation layer and having a concave top surface adjoining the connector, the concave top surface of the molding compound having an angle from 10 degrees to 60 degrees relative to a plane parallel with a major surface of the first substrate; and
a bond pad on a first surface of a second substrate, the bond pad being bonded to the connector, the bond pad having a second width, the connector having a first width at an adjoining top surface of the molding compound.

US Pat. No. 10,714,441

FILTER AND CAPACITOR USING REDISTRIBUTION LAYER AND MICRO BUMP LAYER

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first micro-bump line electrically interposed between a first contact on a first die and a second contact on a second die;
a second micro-bump line electrically coupled to the first die; and
an underfill interposed between the first die and the second die, the underfill completely separating the second micro-bump line from all electrical components other than the first die.

US Pat. No. 10,714,440

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface on which a plurality of connection pads are disposed and an inactive surface opposing the active surface;
an encapsulant sealing at least a portion of the semiconductor chip;
a first connection member disposed on the active surface of the semiconductor chip, and including a first wiring layer and a plurality of first via, each electrically connecting the first wiring layer to one of the plurality of connection pads;
an insulating layer disposed on the first connection member; and
a second wiring layer including a plurality of external connection pads disposed on the insulating layer and a plurality of second vias, each connecting the first wiring layer to one of the external connection pads,
wherein in a direction perpendicular to the active surface of the semiconductor chip, each of the external connection pads has a circular shape, for each of the external connection pads, the first via and the second via are disposed within the external connection pad and do not overlap each other,
wherein, for each of the external connection pads, central axes of the first via, the second via, and the external connection pad are offset from one another.

US Pat. No. 10,714,439

ELECTRONIC DEVICE HAVING COBALT COATED ALUMINUM CONTACT PADS

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:forming cobalt ion liquid solution by mixing cobalt citrate, polyethylenimine, and aluminum fluoride, or by mixing cobalt sulfate, citric acid, polyethylenimine, and aluminum fluoride;
exposing an aluminum pad of each of an array of electrical devices to the cobalt ion liquid solution to chemically displace an aluminum oxide layer from each aluminum pad, wherein the aluminum oxide layer is oxidized to form an aluminum ion and free electrons, wherein the cobalt ion liquid solution combines with the free electrons to form a cobalt metal, and wherein a layer of the cobalt metal is deposited on each aluminum pad in place of the aluminum oxide layer; and
bonding an electrically conductive mechanical interconnector to the layer of cobalt metal.

US Pat. No. 10,714,438

SEMICONDUCTOR DEVICE HAVING METAL BUMP AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a metal line layer on a semiconductor substrate; and
a metal terminal on the metal line layer,
wherein the metal line layer comprises:
metal lines; and
a passivation layer having a non-planarized top surface comprising flat surfaces on the metal lines and a concave surface between the metal lines,
the metal terminal is provided on the passivation layer, and
opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

US Pat. No. 10,714,437

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;
a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; and
a first passivation layer disposed on the second interconnection member and including openings exposing portions of the redistribution layer of the second interconnection member,
wherein the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed,
a value, obtained by multiplying an elastic modulus of the passivation layer by a coefficient of thermal expansion (CTE) of the first passivation layer, is from 130 to 230 GPa ppm/° C., and
the first passivation layer is an outermost insulating layer of the semiconductor package in a stacking direction of the second interconnection member and the first passivation layer.

US Pat. No. 10,714,436

SYSTEMS AND METHODS FOR ACHIEVING UNIFORMITY ACROSS A REDISTRIBUTION LAYER

Lam Research Corporation,...

1. A method for fabricating a redistribution layer, the method comprising:depositing a dielectric layer on top of a pad located on a substrate;
creating at least one via within the dielectric layer, wherein the dielectric layer has at least two intermediate portions and the at least one via extending therebetween;
depositing a barrier and seed layer on top the dielectric layer, wherein said depositing forms a film on the at least one via and on top of the at least two intermediate portions;
providing a layer of photoresist on top of the film of the barrier and seed layer, wherein the photoresist layer extends into the at least one via;
patterning the photoresist layer over the at least one via, wherein the patterning exposes at least a portion of an upper surface of the barrier and seed layer adjacent to the at least one via;
overfilling the redistribution layer within the at least one via and laterally extending the redistribution layer on top of the exposed upper surface of the barrier and seed layer, wherein said overfilling defines a localized bump over the at least one via and the redistribution layer has a height that is less than a height of the patterned photoresist layer; and
selectively removing the localized bump of the redistribution layer, wherein the localized bump is selectively removed while the height of the patterned photoresist layer is maintained.

US Pat. No. 10,714,435

FAN-OUT ANTENNA PACKAGING STRUCTURE AND METHOD MAKING THE SAME

SJ Semiconductor (Jiangyi...

1. A method for fabricating a fan-out antenna packaging structure, comprising:step 1) providing a carrier and forming a release layer on an upper surface of the carrier;
step 2) forming a chip structure on an upper surface of the release layer, wherein the chip structure comprises an unpacked chip and a contact pad disposed on and electrically connected to the unpacked chip, wherein the contact pad is in contact with the release layer;
step 3) forming a plastic packaging layer on the upper surface of the release layer, wherein the plastic packaging layer encloses the chip structure;
step 4) removing the carrier and the release layer to expose the contact pad;
step 5) forming a single-layer antenna structure and forming a redistribution layer on the surface where the contact pad is disposed, wherein the redistribution layer is electrically connected to the contact pad and the antenna structure is electrically connected to the redistribution layer;
step 6) forming an under-bump metal layer on an upper surface of the redistribution layer; and
step 7) forming a solder ball bump on an upper surface of the under-bump metal layer.

US Pat. No. 10,714,434

INTEGRATED MAGNETIC INDUCTORS FOR EMBEDDED-MULTI-DIE INTERCONNECT BRIDGE SUBSTRATES

Intel Corporation, Santa...

1. A semiconductor device package, comprising:an inductor coil in a semiconductor package substrate;
a magnetic material in interstices of the inductor coil;
a recess that projects a footprint onto at least a portion of the inductor coil; and
an embedded multi-die interconnect bridge (EMIB) die in the recess.

US Pat. No. 10,714,433

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a wafer comprising a crystal orientation represented by a family of Miller indices comprising , wherein i2+j2+k2 =2;
a circuit layer; and
a first chip mounted on the wafer through the circuit layer, wherein a first edge of the first chip is arranged in a direction, the direction is not parallel to the crystal orientation, and the first chip includes a plurality of conductive pads facing and electrically connected to the circuit layer.

US Pat. No. 10,714,432

LAYOUT TO REDUCE NOISE IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate;
a gate disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure;
a first source/drain region disposed in the device region and on a first side of the gate;
a second source/drain region disposed in the device region and on a second side of the gate opposite the first side; and
a silicide blocking structure partially covering the gate, partially covering the first source/drain region, and partially covering the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

US Pat. No. 10,714,431

SEMICONDUCTOR PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

UTAC Headquarters Pte. Lt...

1. A method for forming a semiconductor package, comprising:providing a base carrier defined with an active region and a non-active region, the base carrier has first and second major surfaces;
forming a fan-out redistribution structure over the first major surface of the base carrier;
mounting a die having first and second major surfaces onto the base carrier over the fan-out redistribution structure after formation of the fan-out redistribution structure, the first major surface of the die is an active surface of the die and the second major surface of the die is an inactive surface of the die, wherein the die comprises elongated die contacts protruding from the active surface of the die, the die contacts corresponding to conductive pillars, wherein the die contacts are in electrical communication with the fan-out redistribution structure;
forming an encapsulant having a first major surface and a second major surface opposite to the first major surface, wherein the first major surface is proximate to the inactive surface of the die, wherein the encapsulant surrounds the die contacts and sidewalls of the die; and
forming an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer lines the first major surface and sides of the encapsulant.

US Pat. No. 10,714,430

EMI SHIELD FOR MOLDED PACKAGES

OCTAVO SYSTEMS LLC, Suga...

1. A packaged integrated circuit device encapsulated using liquid encapsulant during packaging, the packaged integrated circuit device comprising:a substrate;
a radiation-generating component disposed on the substrate; and
an electromagnetic radiation blocking element comprising (i) one or more openings and (ii) a flap disposed over at least one of said one or more openings, wherein
the electromagnetic radiation blocking element is mounted over the radiation-generating component, and
a space between the electromagnetic radiation blocking element and the radiation-generating component is filled with the liquid encapsulant during the packaging,
wherein the radiation-generating component is connected to one or more components disposed on the substrate via at least one of said one or more openings.

US Pat. No. 10,714,429

CIRCUIT SYSTEMS

Snap Inc., Santa Monica,...

1. A circuit board system comprising:a first circuit board comprising a substrate and a first component susceptible to electromagnetic interference carried by the substrate;
a second circuit board comprising a second substrate; and
a shield engaged to the substrate of the first component, the shield substantially completely encapsulating the first component to insulate the first component from electromagnetic interference, wherein the shield couples the substrate of the first circuit board to the substrate of the second circuit board.

US Pat. No. 10,714,428

SEMICONDUCTOR POWER DEVICE AND A METHOD OF ASSEMBLING A SEMICONDUCTOR POWER DEVICE

1. A method of assembling a power semiconductor device, the method comprising:obtaining a first substrate including a switching semiconductor element, the first substrate having a first surface and locally including first electrically conductive layers and a first receiving element, the switching semiconductor element being provided on the first surface;
obtaining a second substrate including a second surface facing the first surface, the second substrate including a second receiving element and locally including second electrically conductive layers;
obtaining an alignment interconnect element;
providing the alignment interconnect element to one of the first receiving element and the second receiving element to effect a partial reception of the alignment interconnect element by the receiving element; and
providing the alignment interconnect element to another one of the first receiving element and the second receiving element to effect a partial reception of the alignment interconnect element by the receiving element;
wherein the method further comprises:
obtaining data describing a required positioning of the first substrate with respect to the second substrate,
measuring characteristics of the first receiving element and of the second receiving element; and
determining characteristics of the alignment interconnect element based on of the obtained data and the measured characteristics,
wherein obtaining the alignment interconnect element comprises obtaining the alignment interconnect element on basis of the determined characteristics,
and wherein the receiving elements are holes or recesses and measuring the characteristics of the first receiving element and of the second receiving element comprises at least one of determining a radius of the receiving element and determining a depth of the receiving element.

US Pat. No. 10,714,427

SECURE CHIPS WITH SERIAL NUMBERS

ASML Netherlands B.V., V...

1. An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip:wherein the semiconductor chip is a member of a set of semiconductor chips, wherein the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets;
wherein the plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset are different from the non-common structures of the semiconductor chips in every other subset;
wherein at least a first portion of the non-common structures is adapted to store or generate a first predetermined value;
wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.

US Pat. No. 10,714,425

FLEXIBLE SYSTEM INTEGRATION TO IMPROVE THERMAL PROPERTIES

Apple Inc., Cupertino, C...

1. An apparatus comprising:an interposer;
a plurality of integrated circuits attached to a surface of the interposer, wherein:
a subset of the plurality of integrated circuits are processors;
the processors are distributed over the surface of the interposer; and
other ones of the plurality of integrated circuits that are not processors are arranged between the processors, distributing a power consumption density of the plurality of integrated circuits over the surface;
a phase change material in contact with the plurality of integrated circuits and the interposer, wherein the phase change material absorbs heat by melting and releases heat by solidifying during operation of the apparatus; and
a battery in contact with the phase change material, wherein the battery includes one or more openings through which the phase change material extends to conduct heat away from the plurality of integrated circuits.

US Pat. No. 10,714,424

METHOD OF FORMING METAL INTERCONNECTION

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a first conductor;
a dielectric layer disposed on the first conductor;
a via conductor disposed in the dielectric layer and extending to the first conductor such that the via conductor physically contacts the first conductor;
a second conductor disposed in the dielectric layer and on the via conductor; and
a barrier layer interposed between the via conductor and the dielectric layer, and between the second conductor and the dielectric layer, wherein the barrier layer includes a metal and at least two elements included in the dielectric layer.

US Pat. No. 10,714,423

THROUGH VIA STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming an opening extending through an interlayer dielectric layer over a substrate and partially through the substrate;
depositing a photoresist layer over the opening, wherein the photoresist layer partially fills the opening;
patterning the photoresist layer to remove the photoresist layer in the opening and form a metal line opening over the interlayer dielectric layer;
filling the opening and the metal line opening with a conductive material to form a via and a metal line, wherein an upper portion of the opening is free of the conductive material; and
depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the opening.

US Pat. No. 10,714,422

ANTI-FUSE WITH SELF ALIGNED VIA PATTERNING

GLOBALFOUNDRIES INC., Gr...

1. An anti-fuse structure comprising:a lower wiring layer composed of a plurality of lower wiring structures and embedded in a first insulator layer of dielectric material;
at least one via structure in contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and
an upper wiring layer composed of at least one upper wiring structure in contact with the at least one via structure,
wherein the at least one via structure and the upper wiring layer are completely embedded in a second insulator layer of the dielectric material contacting an upper surface of the first insulator layer of the dielectric material, with no intervening material therebetween, and
wherein the first insulator layer and the second insulator layer are composed of a same dielectric material, and
wherein the at least one via structure has a first width dimension and the at least one upper wiring structure has a second width dimension, different from the first width dimension, thereby forming a dual damascene metallization structure with two different width dimensions.

US Pat. No. 10,714,421

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONDUCTIVE FEATURES

Taiwan Semiconductor Manu...

16. A semiconductor device structure, comprising:a substrate;
a first conductive feature over the substrate;
a second conductive feature above the first conductive feature, wherein the second conductive feature has an upper portion and a protruding portion, the protruding portion is below the upper portion and extends towards the first conductive feature, and a bottom of the upper portion is wider than a top of the upper portion and is wider than a top of the protruding portion; and
a dielectric layer surrounding the first conductive feature and the second conductive feature; and
a closed hole in the dielectric layer.

US Pat. No. 10,714,419

NON-PLANAR METAL-INSULATOR-METAL CAPACITOR FORMATION

International Business Ma...

1. A semiconductor structure comprising:a base structure comprising:
a dielectric;
a first set of base structures disposed in the dielectric, the first set of base structures comprising at least a first base structure, a second base structure and a third base structure, wherein the first base structure comprises a first via disposed on a first metal line, the second base structure comprises a second via disposed on a second metal line, and the third base structure comprises a third metal line; and
a second set of base structures disposed on the dielectric and the first set of base structures, the second set of base structures comprising at least a fourth base structure, a fifth base structure and a sixth base structure, wherein the fourth base structure comprises a fourth via disposed on a fourth metal line, the fifth base structure comprises a fifth via disposed on a fifth metal line, and the sixth base structure comprises a sixth via disposed on a sixth metal line;
wherein the base structure has one or more recesses each comprising contours formed at two or more planar levels;
a first dielectric layer disposed over each of the fourth metal line, the fifth metal line and the sixth metal line, along sidewalls of the fourth via, the fifth via and the sixth via and on a portion of the base structure;
a first electrode disposed on a portion of the first dielectric layer disposed on the fourth base structure and on the first dielectric layer disposed on the fifth base structure;
a second dielectric layer disposed on the first dielectric layer and the first electrode; and
a second electrode disposed over a portion of the second dielectric layer;
wherein the first electrode, the second dielectric layer and the second electrode are configured to form a non-planar capacitor.

US Pat. No. 10,714,418

ELECTRONIC DEVICE HAVING INVERTED LEAD PINS

TEXAS INSTRUMENTS INCORPO...

1. An electronic device, comprising:a package having a longitudinal center line, a mounting portion on one side of the longitudinal center line and a non-mounting portion on an opposite side of the longitudinal center line;
a low voltage die attach pad embedded in a non-mounting portion of the package, the low voltage die attach pad having a first side facing toward the longitudinal center line and a second side facing away from the longitudinal center line;
a low voltage die attached to the first side of the low voltage die attach pad;
a plurality of low voltage lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package;
a high voltage die attach pad embedded in the non-mounting portion of the package, the high voltage die attach pad having a first side facing toward the longitudinal center line and a second side facing away from the longitudinal center line;
a high voltage die attached to the first side of the high voltage die attach pad; and
a plurality of high voltage lead pins extending from the package in the direction toward the mounting portion and away from the non-mounting portion of the package.

US Pat. No. 10,714,417

SEMICONDUCTOR DEVICE WITH ELECTROPLATED DIE ATTACH

TEXAS INSTRUMENTS INCORPO...

1. A method of semiconductor die attachment, comprising:providing a dielectric cover having a first repeating pattern of recesses and a metal substrate including a second repeating pattern having positions matching the first repeating pattern including center through-hole apertures having an outer ring that position match the recesses and a plurality of raised traces around the through-hole apertures comprising a metal layer on a dielectric base layer on the metal substrate;
inserting a semiconductor die having a back side metal (BSM) layer top side up into respective ones of the plurality of apertures to sit on the outer ring;
placing the dielectric cover over the semiconductor die to form a plurality of stacks;
sealing along a periphery between the dielectric cover and the metal substrate;
immersing the stacks in a metal electroplating solution within a solution container, with the metal substrate connected to a negative terminal of a power supply and an electrically conductive structure spaced apart from the metal substrate connected to a positive terminal of the power supply, and
electroplating to deposit an electroplated single metal layer to fill a volume between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment.

US Pat. No. 10,714,416

SEMICONDUCTOR PACKAGE HAVING A CIRCUIT PATTERN

SAMSUNG ELECTRONICS CO., ...

1. A printed circuit board comprising:a base layer having a first surface;
a first conductive pattern disposed on the first surface; and
a first insulation layer disposed on the first conductive pattern, the first insulation layer including first protrusions and a second protrusion, wherein the first protrusions protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the first conductive pattern and form a mesh structure, and the second protrusion protrudes from the bottom surface of the first insulation layer and penetrates the at least the portion of the first conductive pattern,
wherein the second protrusion is spaced apart from the first protrusions, and the second protrusion is formed within a first coefficient of thermal expansion (CTE) adjusting region.

US Pat. No. 10,714,415

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate including:
a first insulating layer having a first surface, a second surface opposite to the first surface, and a first through hole filled with a first through hole via,
a first wiring formed on the first surface of the first insulating layer,
a second wiring formed on the second surface of the first insulating layer, and electrically connected with the first wiring via the first through hole via,
a second insulating layer having a second through hole filled with a second through hole via, and formed on the first surface of the first insulating layer so as to cover the first wiring,
a third wiring formed on the second insulating layer, and electrically connected with the first wiring via the second through hole via,
a third insulating layer having a third through hole filled with a third through hole via, and formed on the second surface of the first insulating layer so as to cover the second wiring, and
a fourth wiring formed on the third insulating layer, and electrically connected with the second wiring via the third through hole via,
a semiconductor component mounted over the second insulating layer of on the wiring substrate; and
an external connection terminal formed over the third insulating layer of the wiring substrate,
wherein each of the first insulating layer, the second insulating layer, and the third insulating layer is a build-up substrate,
wherein a diameter of each of the first through hole, the second through hole, and the third through hole is equal to or less than 100 ?m, and
wherein each of the first insulating layer, the second insulating layer and the third insulating layer contains a glass cloth.

US Pat. No. 10,714,414

PLANARIZING RDLS IN RDL—FIRST PROCESSES THROUGH CMP PROCESS

Taiwan Semiconductor Manu...

1. A device comprising:a first dielectric layer;
a first redistribution line and a second redistribution line in the first dielectric layer;
an adhesive film over and contacting both a first top surface of the first dielectric layer and a second top surface of the first redistribution line;
a device die over and adhered to the adhesive film; and
an encapsulating material encapsulating the device die therein, wherein the encapsulating material contacts the first top surface of the first dielectric layer.

US Pat. No. 10,714,412

SEMICONDUCTOR PACKAGE WITH INTEGRATED PASSIVE ELECTRICAL COMPONENT

TEXAS INSTRUMENTS INCORPO...

1. A package, comprising:a leadframe including conductive pins;
a semiconductor die having opposite first and second sides, the first side of the semiconductor die having a contact connected to the leadframe;
a solder ball connected to the leadframe;
first and second magnetic elements, the first magnetic element on the second side of the semiconductor die;
a conductive element at least partially between the first and second magnetic elements, the conductive element connected through the solder ball to the leadframe; and
mold compound encapsulating the conductive element, the first and second magnetic elements, the solder ball, the semiconductor die and the leadframe except at least a portion of the conductive pins.

US Pat. No. 10,714,411

INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING AND METHOD OF FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a packaging substrate including a top surface and a bottom surface;
a first bond pad array on the top surface of the packaging substrate, the first bond pad array including:
a set of operable bond pads, and
a set of structural support bond pads adjacent to the set of operable bond pads,
wherein the structural support bond pads are electrical opens;
a second bond pad array on the bottom surface of the packaging substrate, the second bond pad array including:
a set of operable bond pads, and
a set of structural bond pads adjacent to the set of operable bond pads;
an interconnected chip structure including an operable region having a first device connected to the set of operable bond pads of the first bond pad array, and an inoperable region coupled to the set of operable bond pads of the second bond pad array, wherein the operable region includes a first crack stop structure surrounding the first device, and wherein a connector wire extending through an opening of the first crack stop structure electrically couples the operable region to the inoperable region; and
an interconnect structure positioned within the packaging substrate, wherein the interconnect structure electrically connects the set of operable bond pads of the first bond pad array to the set of operable bond pads of the second bond pad array.

US Pat. No. 10,714,410

SEMICONDUCTOR STRUCTURE

VANGUARD INTERNATIONAL SE...

1. A semiconductor structure comprising:a substrate having a first conductivity type;
a first well formed on the substrate and having a second conductivity type;
a field oxide layer disposed on the first well;
a first conductive line formed on the field oxide layer and in direct contact with the field oxide layer; and
a second conductive line formed on the field oxide layer and in direct contact with the field oxide layer, wherein the first conductive line is spaced apart from the second conductive line,
wherein the first conductive line is used as one passive element, and the second conductive line is used as another passive element.

US Pat. No. 10,714,409

SEMICONDUCTOR DEVICE WITH ANTENNA INTEGRATED

WIN Semiconductors Corp.,...

1. A semiconductor device, comprising:a substrate;
an active circuit portion, disposed on the substrate;
a dielectric portion, disposed on the active circuit portion, wherein a hole is formed within the dielectric portion and the hole penetrates through the dielectric portion; and
a radiating metal sheet, disposed on the dielectric portion;
wherein the active circuit portion and the radiating metal sheet are coupled through the hole.

US Pat. No. 10,714,408

SEMICONDUCTOR DEVICES AND METHODS OF MAKING SEMICONDUCTOR DEVICES

AMKOR TECHNOLOGY, INC., ...

1. An electronic package comprising:a substrate comprising an upper substrate side, and a substrate pad on the upper substrate side;
an electronic component comprising an upper component side and a lower component side, the lower component side coupled to the upper substrate side;
a wire comprising an upper wire end and a lower wire end, the lower wire end coupled to the substrate pad; and
a package body enclosing the wire and the electronic component, the package body comprising a lower package body side facing the substrate and an upper package body side facing away from the substrate, the upper package body side comprising a cavity that exposes the upper wire end from the package body.

US Pat. No. 10,714,407

AMPLIFICATION APPARATUS

TOKYO KEIKI INC., Tokyo ...

1. An amplification apparatus, comprising:a signal splitter for splitting an input radio frequency signal and outputting the resulting split radio frequency signals;
a plurality of amplifier units for amplifying the radio frequency signals outputted from the signal splitter, the amplifier units being disposed circularly to form a generally cylindrical shape;
a plurality of water cooling heat sinks disposed circularly at positions corresponding to positions of the plurality of amplifier units so as to cool the plurality of amplifier units by cooling water;
a signal combiner for combining the radio frequency signals outputted from the plurality of amplifier units, respectively, and outputting the resulting combined radio frequency signal,
an input power monitor for determining whether or not a power level of an input radio frequency signal received by the signal splitter is appropriate; and
an amplitude/phase adjuster for adjusting an amplitude and a phase of a radio frequency signal outputted from the signal splitter,
wherein the input power monitor and the amplitude/phase adjuster are disposed within a hollow space of the generally cylindrical shape.

US Pat. No. 10,714,406

ELECTRONIC POWER MODULE AND ELECTRICAL POWER CONVERTER INCORPORATING SAME

INSTITUT VEDECOM, Versai...

1. Electronic power module having an architecture with 3D stacking, comprising first and second dielectric substrates that are intended to come into thermal contact with first and second heat sinks, respectively, at least one pair of first and second stacked electronic power switching chips and a common intermediate substrate, said first and second electronic power switching chips being sandwiched between said first dielectric substrate and said common intermediate substrate and between said common intermediate substrate and said second dielectric substrate, respectively, wherein said common intermediate substrate is a metal element formed as a single piece and comprises a central portion for implanting said electronic power switching chips, and a thermal conduction portion that is in thermal contact with said first dielectric substrate and/or said second dielectric substrate.

US Pat. No. 10,714,405

SEMICONDUCTOR PACKAGES RELATING TO THERMAL REDISTRIBUTION PATTERNS

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip and a second semiconductor chip disposed side by side on a package substrate; and
a thermal redistribution pattern including a first end portion, a second end portion and an extension portion,
the first end portion disposed over a high temperature region adjacent to the first semiconductor chip,
the second end portion disposed over a low temperature region adjacent to the second semiconductor chip, and
the extension portion extending horizontally over the package substrate between the first end portion and the second end portion and passing by the second semiconductor chip to detour the second semiconductor chip.

US Pat. No. 10,714,404

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor element;
a lead electrode comprising a lower surface connected to an upper surface of the semiconductor element at one end of the lead electrode;
a cooling mechanism disposed on a lower surface side of the semiconductor element; and
a heat dissipation mechanism provided to be thermally joined between the lower surface of the lead electrode, the lower surface being more adjacent to an other-end side of the lead electrode than the one end, and the cooling mechanism, the heat dissipation mechanism comprising at least one insulating layer,
wherein the heat dissipation mechanism comprises
a first heat dissipation block connected to the lower surface of the lead electrode, the lower surface being more adjacent to the other-end side than the one end,
the insulating layer at least partly connected to a lower surface of the first heat dissipation block, and
a heat dissipation material connected to a lower surface of the insulating layer,
wherein the lead electrode comprises a hole penetrating from an upper surface of the lead electrode to the lower surface of the lead electrode, and
wherein an upper surface of the first heat dissipation block comprises a screw hole in a position superposed on the hole of the lead electrode in plan view.

US Pat. No. 10,714,403

SEMICONDUCTOR DEVICE PACKAGE WITH PATTERNED CONDUCTIVE LAYERS AND AN INTERCONNECTING STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier having a first surface and a second surface opposite to the first surface;
a first patterned conductive layer adjacent to the first surface of the carrier;
an interconnection structure disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer, the interconnection structure having a side surface and a top surface;
a first semiconductor device disposed on the interconnection structure and electrically connected to the interconnection structure;
an encapsulant disposed on the first patterned conductive layer and encapsulating the first semiconductor device, the top surface of the interconnection structure, and the side surface of the interconnection structure;
a second patterned conductive layer disposed and in direct contract with on a top surface and a side surface of the encapsulant and electrically connected to the first patterned conductive layer; and
a passivation layer disposed on the second patterned conductive layer and covering the side surface of the encapsulant.

US Pat. No. 10,714,402

SEMICONDUCTOR CHIP PACKAGE FOR IMPROVING FREEDOM OF ARRANGEMENT OF EXTERNAL TERMINALS

SONY CORPORATION, Tokyo ...

1. A semiconductor chip package, comprising:a semiconductor chip that comprises:
a first surface and a second surface opposed to the first surface;
a circuit part; and
a plurality of electrodes configured to supply a voltage to the circuit part;
a resin layer in a periphery of the semiconductor chip;
a substrate that faces the first surface of the semiconductor chip and the resin layer, wherein the substrate has optical transparency;
a rewiring layer on a side of the second surface of the semiconductor chip, wherein the rewiring layer is across an entire region of the second surface; and
a plurality of external terminals on the side of the second surface of the semiconductor chip, wherein each external terminal of the plurality of external terminals is electrically coupled to one electrode of the plurality of electrodes through the rewiring layer.

US Pat. No. 10,714,401

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor package comprising:a package substrate including a mounting region and at least one through-hole arranged in the mounting region;
a semiconductor chip mounted on the mounting region, the semiconductor chip including a first lateral side and a second lateral side, the second lateral side of the semiconductor chip being opposite to the first lateral side of the semiconductor chip, the second lateral side of the semiconductor chip being closer to the at least one through-hole of the package substrate than the first lateral side of the semiconductor chip; and
a non-conductive molding layer including an underfill part and an extension part, the underfill part between the semiconductor chip and the package substrate, the extension part filling at least a portion of the at least one through-hole.

US Pat. No. 10,714,400

METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING THIN FILM TRANSISTORS INCLUDING OXIDE SEMICONDUCTORS

Micron Technology, Inc., ...

1. A method of forming a semiconductor structure, the method comprising:forming an array of vertical thin film transistors, forming the array of vertical thin film transistors comprising:
forming a source region;
forming a channel material comprising an oxide semiconductor material over the source region;
exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures;
forming a gate dielectric material on sidewalls of the channel regions;
forming a gate electrode material adjacent to the gate dielectric material; and
forming a drain region over the channel regions.

US Pat. No. 10,714,399

GATE-LAST PROCESS FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure, comprising:forming a plurality of fins over a top surface of a substrate;
forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins comprising channels for the one or more vertical transport field-effect transistors; and
forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack comprising a gate dielectric layer, a work function metal layer, and a gate conductor layer;
wherein the gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins;
wherein the box profile in the area between the at least two adjacent fins comprises:
the gate dielectric layer formed on (i) sidewalls of the two adjacent fins, (ii) portions of a top surface of a bottom spacer extending between the at least two adjacent fins, and (iii) portions of a bottom surface of a top spacer extending between the at least two adjacent fins;
the work function metal layer formed on interior surfaces of the gate dielectric layer; and
the gate conductor layer filling a cavity defined by interior surfaces of the work function metal layer.

US Pat. No. 10,714,398

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRONIC DEVICE INCLUDING THE DEVICE

Institute of Microelectro...

1. A semiconductor device, comprising:a substrate;
a first source/drain layer, a channel layer, and a second source/drain layer stacked on the substrate in sequence, wherein the first source/drain layer is closer to the substrate than the second source/drain layer, and wherein the second source/drain layer comprises a stressed first semiconductor material; and
a gate stack surrounding a periphery of the channel layer and comprising a gate dielectric layer and a gate conductor layer, wherein upper and lower surfaces of the gate dielectric layer and the gate conductor layer are coplanar with upper and lower surfaces of the channel layer, respectively;
wherein the second source/drain layer comprises a second semiconductor material contiguous to the channel layer and having a lattice constant different from that of the first semiconductor material, and wherein the stressed first semiconductor material is formed on the second semiconductor material.

US Pat. No. 10,714,397

SEMICONDUCTOR DEVICE INCLUDING AN ACTIVE PATTERN HAVING A LOWER PATTERN AND A PAIR OF CHANNEL PATTERNS DISPOSED THEREON AND METHOD FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method for manufacturing a semiconductor device, comprising:forming an active pattern on a substrate; and
forming a gate electrode intersecting the active pattern, the gate electrode extending in a first direction,
wherein the forming of the active pattern comprises: forming a lower pattern and a pair of channel patterns on the lower pattern,
wherein the lower pattern includes a first semiconductor material,
wherein each of the pair of channel patterns includes a second semiconductor material different from the first semiconductor material,
wherein a first portion of the gate electrode is disposed between the pair of channel patterns,
wherein each of the pair of channel patterns is angled towards one another, and
wherein a width of the first portion of the gate electrode, measured along the first direction, decreases in a direction away from the substrate.

US Pat. No. 10,714,396

VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS

International Business Ma...

1. A method for fabricating a vertical field-effect transistor (FET) structure, the method comprising:prior to depositing a gate of a first vertical FET on a semiconductor substrate, depositing a first layer of the first vertical FET on the semiconductor substrate;
prior to depositing a gate of a second vertical FET on the semiconductor substrate, depositing a second layer of the second vertical FET on the semiconductor substrate;
etching the first layer of the first vertical FET to a lower height than the second layer of the second vertical FET;
depositing a gate material of both the first vertical FET and the second vertical FET; and
etching the gate material of both the first vertical FET and the second vertical FET to a co-planar height, wherein the first layer and the second layer comprises a spacer.

US Pat. No. 10,714,395

FIN ISOLATION STRUCTURE FOR FINFET AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a substrate having adjacent first and second fins protruding from the substrate;
an isolation feature between and adjacent to the first fin and the second fin; and
a fin isolation structure between the first fin and the second fin, comprising:
a first insulating layer partially embedded in the isolation feature;
a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer;
a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer; and
a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

US Pat. No. 10,714,394

FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method of forming a fin field effect transistor (finFET) on a substrate, the method comprising:forming a fin structure on the substrate;
forming a shallow trench isolation (STI) region on the substrate, wherein first and second fin portions of the fin structure extend above a top surface of the STI region;
oxidizing the first fin portion to convert a first material of the first fin portion to a second material, wherein the second material is different from the first material of the first fin portion and a material of the second fin portion;
forming an oxide layer on the oxidized first fin portion and the second fin portion; and
forming first and second polysilicon structures on the oxide layer.

US Pat. No. 10,714,393

MIDDLE OF THE LINE SUBTRACTIVE SELF-ALIGNED CONTACTS

International Business Ma...

1. A method for forming contacts on a semiconductor device, comprising:depositing conductive material in a first trench and a second trench formed through an interlayer dielectric and an etch stop layer disposed on the interlayer dielectric and over the etch stop layer to a height above the etch stop layer;
patterning a resist on the conductive material with a shape over a source/drain region in the first trench;
forming a trench line and a self-aligned contact below the shape in the first trench, including subtractively etching the conductive material based on the resist to remove the conductive material from over the etch stop layer and to recess the conductive material in the second trench; and
depositing a second interlayer dielectric to fill up to the height.

US Pat. No. 10,714,392

OPTIMIZING JUNCTIONS OF GATE ALL AROUND STRUCTURES WITH CHANNEL PULL BACK

International Business Ma...

1. A method of forming a nanosheet device, the method comprising the steps of:forming an alternating series of first nanosheets comprising a first material and second nanosheets comprising a second material as a stack on a wafer;
forming at least one dummy gate on the stack;
forming spacers along opposite sidewalls of the at least one dummy gate;
patterning the stack into at least one fin stack beneath the at least one dummy gate;
etching the at least one fin stack to selectively pull back the second nanosheets in the at least one fin stack forming pockets in the at least one fin stack;
filling the pockets with a strain-inducing material comprising an epitaxial material;
forming source and drains on opposite sides of the at least one fin stack;
burying the at least one dummy gate in a dielectric material;
selectively removing the at least one dummy gate forming at least one gate trench in the dielectric material;
selectively removing, through the at least one gate trench, either the first nanosheets or the second nanosheets from the at least one fin stack; and
forming at least one replacement gate in the at least one gate trench.

US Pat. No. 10,714,391

METHOD FOR CONTROLLING TRANSISTOR DELAY OF NANOWIRE OR NANOSHEET TRANSISTOR DEVICES

Tokyo Electron Limited, ...

1. A method of manufacturing a semiconductor device comprising:providing a substrate comprising:
a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure comprising an initial volume of first channel material provided between upper and lower portions of first sacrificial material such that the first channel material and first sacrificial material are exposed at a side of the first stacked fin structure, and
a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure comprising an initial volume of second channel material provided between upper and lower portions of second sacrificial material such that the second channel material and second sacrificial material are exposed at a side of the second stacked fin structure;
masking sidewalls of the first stacked fin structure;
reducing, after the masking, said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor via etching the second stacked fin structure to trim the initial volume of the second channel material to a trimmed volume corresponding to a predetermined delay of the second GAA transistor; and
forming first and second GAA gate structures around said first channel material and said second channel material respectively.

US Pat. No. 10,714,390

WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH

Applied Materials, Inc., ...

1. A system for dicing a semiconductor wafer comprising a plurality of integrated circuits, the system comprising:a plasma etch chamber;
a robotic transfer chamber coupled to the plasma etch chamber;
a load lock;
a laser scribe apparatus; and
a factory interface coupled to the robotic transfer chamber by the load lock, and the factory interface coupled to the laser scribe apparatus, wherein the factory interface comprises a robot with an arm or a blade, wherein a semiconductor wafer is transferred from the laser scribe apparatus to the robot of the factory interface, from the robot of the factory interface to the robotic transfer chamber through the load lock, and from the robotic transfer chamber to the plasma chamber.

US Pat. No. 10,714,389

STRUCTURE AND METHOD USING METAL SPACER FOR INSERTION OF VARIABLE WIDE LINE IMPLANTATION IN SADP/SAQP INTEGRATION

ELPIS TECHNOLOGIES, INC.,...

1. A semiconductor device comprising:a back-end-of-line (BEOL) structure formed on a semiconductor substrate, wherein the BEOL structure comprises at least one metallization layer comprising a pattern of elongated parallel metal lines, wherein the pattern of elongated metal lines comprises a first set of adjacent metal lines having a uniform first width and a second set of adjacent metal lines having a uniform second width, wherein the uniform second width is greater than the uniform first width, and further wherein the first set of adjacent metal lines comprises a first metal material and the second set of adjacent metal lines comprises a second metal material different from the first metal material.

US Pat. No. 10,714,388

METHOD AND APPARATUS FOR DEPOSITING COBALT IN A FEATURE

APPLIED MATERIALS, INC., ...

1. A method of processing a substrate, comprising:exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and
annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing;
wherein the first temperature is about 100 degrees Celsius to about 300 degrees Celsius;
wherein the second temperature is up to about 1000 degrees Celsius;
wherein annealing the substrate further comprises annealing the substrate in a hydrogen gas atmosphere; and
wherein the cobalt layer is deposited using a fluorine-free chemical vapor deposition process.

US Pat. No. 10,714,387

INTEGRATED CIRCUIT DEVICES AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit device comprising:a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate;
a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and
source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions comprising:
an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, the upper semiconductor layer including a gap; and
a gap-fill semiconductor layer, in the gap having a second impurity concentration greater than the first impurity concentration.

US Pat. No. 10,714,386

INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING METAL OXIDE ADHESIVE LAYER

Intel Corporation, Santa...

1. A microelectronic assembly, comprising:a first dielectric layer, wherein the first dielectric layer comprises 60% or more filler;
a metal oxide layer in contact with the first dielectric layer, wherein a thickness of the metal oxide layer is between 4 nanometers and 40 nanometers;
a conductive layer in contact with the metal oxide layer; and
a second dielectric layer in contact with the conductive layer, wherein the second dielectric layer comprises 60% or more filler.

US Pat. No. 10,714,385

SELECTIVE DEPOSITION OF TUNGSTEN

ASM IP Holding B.V., Alm...

1. A method of selectively forming a film comprising metal, the method comprising:providing a substrate for processing in a reaction chamber and a hot wire for contacting at least a gas;
exposing the substrate to a metal precursor; and
exposing the substrate to a gas which has been exposed to a vicinity of the hot wire;
wherein the substrate comprises at least two different materials and the metal film is selectively formed in one of the at least two different materials.

US Pat. No. 10,714,384

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming an integrated circuit comprising a first circuit and a second circuit separated from the first circuit;
forming a first dielectric layer over the first circuit and the second circuit;
forming a first metal layer comprising a first metal portion, a second metal portion, a third metal portion, a fourth metal portion, and a fifth metal portion over the first dielectric layer, wherein:
the fifth metal portion is coupled to the first circuit,
the first metal portion surrounds the fifth metal portion to define an inner ring,
the second metal portion surrounds the first metal portion to define an outer ring,
the third metal portion extends between the first metal portion and the second metal portion to define a first connector,
the fourth metal portion extends between the first metal portion and the second metal portion to define a second connector, and
the inner ring, the outer ring, the first connector, and the second connector define an electrically conductive path; and
forming a second dielectric layer over the first metal layer, wherein:
the second dielectric layer isolates the fifth metal portion from the first metal portion, the second metal portion, the third metal portion, and the fourth metal portion, and
the second dielectric layer is disposed between a sidewall of the first connector and a sidewall of the second connector facing the sidewall of the first connector.

US Pat. No. 10,714,383

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming an interconnect structure, the method comprising:depositing a first etch stop layer (ESL) over a first dielectric layer;
depositing a second dielectric layer over the first ESL;
patterning a first opening in the second dielectric layer and the first ESL, the first opening exposing the first dielectric layer, patterning the first opening forming a first damaged region in the first dielectric layer and a second damaged region in the second dielectric layer;
forming a first conductive feature in the first opening;
removing the second damaged region to form a first gap between the first conductive feature and the second dielectric layer; and
removing the first damaged region to form a second gap between the first conductive feature and the first dielectric layer.

US Pat. No. 10,714,382

CONTROLLING PERFORMANCE AND RELIABILITY OF CONDUCTIVE REGIONS IN A METALLIZATION NETWORK

INTERNATIONAL BUSINESS MA...

1. A method of forming a conductive coupling region of a metallization network associated with a substrate, the method comprising:forming a trench in a dielectric material on the substrate;
forming a first liner layer in a first portion of the trench;
forming a second liner layer in a second portion of the trench;
forming a conductive material over the second liner layer in the trench;
forming the first liner layer such that the first liner layer is not present over a bottom surface of the trench; and
forming the second liner layer such that at least a portion of the second liner is over the bottom surface of the trench, wherein the bottom surface of the trench is defined by a portion of the dielectric material; and
performing an anneal to form a copper barrier at the bottom surface of the trench, the copper barrier comprising an alloy material in the second liner layer, oxygen, and silicon in the dielectric material on the substrate.

US Pat. No. 10,714,381

SEMICONDUCTOR DEVICE HAVING COMPOSITE STRUCTURES AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:forming a first composite structure including a core region and an edge region around the core region, on a substrate, wherein the first composite structure includes a plurality of laminated layers of first composite layers;
forming a second composite structure on a first surface portion of the core region of the first composite structure, wherein the second composite structure includes a plurality of laminated layers of second composite layers and has edge regions on opposite sides of the second composite structure;
forming a first mask layer, covering a sidewall of the second composite structure and a second surface portion of the core region of the first composite structure outside of an outer peripheral of the second composite structure and exposing at least a portion of the edge region of the first composite structure;
forming a second mask layer, on a surface portion of the second composite structure, exposing at least a portion of each of the edge regions of the second composite structure, and spaced apart from the first mask layer by a first annular opening; and
etching simultaneously a top first layer of the plurality of laminated layers of the first composite layers from two opposing ends of the first composite layer in the edge region of the first composite structure and a top first layer of the plurality of laminated layers of the second composite layers from two opposing ends of the second composite layer at a bottom of the first annular opening, using the first mask layer and the second mask layer as an etch mask.

US Pat. No. 10,714,380

METHOD OF FORMING SMOOTH SIDEWALL STRUCTURES USING SPACER MATERIALS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming mandrel structures;
forming a first spacer material on each of the mandrel structures;
forming a second spacer material over the first spacer material; and
removing the first spacer material and the mandrel structures to form a sidewall structure having a sidewall smoothness greater than a sidewall smoothness of the mandrel structures,
wherein the forming the first spacer material and the second spacer material comprises a deposition process followed by an anisotropic etching process to expose the mandrel structures.

US Pat. No. 10,714,379

REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS

International Business Ma...

1. An interconnect structure comprising:a contact present within an opening having at least two widths, wherein the contact extends into contact with an electrically conductive feature, wherein a gouge is present in an upper surface of the electrically conductive feature; and
a shield liner present on the sidewalls of the opening, wherein the shield liner includes discontinuous segments on each end of opposed ends of the opening.

US Pat. No. 10,714,378

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device, comprising:a package substrate comprising:
a top substrate side comprising top pads;
a bottom substrate side comprising bottom pads; and
conductive paths connecting the top pads and the bottom pads;
an interposer die comprising:
an interposer die top side;
an interposer die bottom side; and
interposer die conductive paths that:
pass through the interposer die from the interposer die top side to the interposer die bottom side; and
are electrically connected to the top pads of the package substrate;
a first device die and a second device die that are:
coupled to the interposer die top side;
surrounded by a perimeter of the interposer die top side; and
electrically connected to the interposer die conductive paths; and
an encapsulating layer that encapsulates the first device die, the second device die, and the interposer die top side, wherein the encapsulating layer comprises an encapsulating layer top side, an encapsulating layer bottom side in contact with the interposer die top side, and an exposed encapsulating layer sidewall.

US Pat. No. 10,714,377

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER INCLUDING A POROUS LAYER AND METHOD OF MANUFACTURING

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device, the method comprising:forming an auxiliary mask comprising a plurality of mask openings on a main surface of a crystalline semiconductor substrate;
forming a porous structure in the semiconductor substrate, the porous structure comprising a porous layer at a distance to the main surface and porous columns protruding from the porous layer into a direction of the main surface and laterally separated from each other by a non-porous portion; and
forming a non-porous device layer on the non-porous portion and on the porous columns,
wherein forming the non-porous device layer comprises a heat treatment in an atmosphere containing hydrogen to form a non-porous crystalline starting layer.

US Pat. No. 10,714,376

METHOD OF FORMING SEMICONDUCTOR MATERIAL IN TRENCHES HAVING DIFFERENT WIDTHS, AND RELATED STRUCTURES

GLOBALFOUNDRIES INC., GR...

11. A semiconductor structure comprising:a dielectric material positioned above a substrate;
a first fill material in a first trench in the dielectric material, the first fill material including:
a lower portion; and
two upper portions positioned on the lower portion, wherein an uppermost extent of the two upper portions is positioned below an uppermost extent of the first trench;
a second fill material in a second trench in the dielectric material, the second fill material laterally separated from the first fill material, and the second fill material having an uppermost extent positioned below an uppermost extent of the second trench,
wherein the first fill material is positioned on a gate metal in the first trench, and wherein the second fill material is positioned on a gate metal in the second trench,
wherein a cross-sectional geometry of the gate metal in the first trench is substantially U-shaped, and wherein a cross-sectional geometry of the gate metal in the second trench is substantially rectangular,
wherein a width of the lower portion of the first fill material is greater than a width of the second fill material, and
wherein the upper surface of the lower portion of the first fill material is substantially co-planar with the uppermost extent of the second fill material;
a third fill material positioned above the first fill material in the first trench; and
a fourth fill material positioned above the second fill material in the second trench.

US Pat. No. 10,714,375

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEIKO EPSON CORPORATION, ...

1. A semiconductor device comprising:a semiconductor layer;
a first conductivity type first well that is arranged in a first region of the semiconductor layer;
a first conductivity type first impurity diffusion region that is arranged in the first well;
a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer;
a second conductivity type second well that is arranged so as to surround the second impurity diffusion region in the semiconductor layer:
an insulating film that is arranged on the second impurity diffusion region;
an electrode that is arranged on the insulating film; and
a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

US Pat. No. 10,714,374

HIGH-PRECISION PRINTED STRUCTURES

X Display Company Technol...

1. A method of making a printed structure, comprising:providing a target substrate and a structure protruding from a surface of the target substrate;
providing a transfer element and a component adhered to the transfer element, wherein the component comprises a component substrate that is separate and independent from the target substrate;
moving the transfer element with the adhered component vertically toward the surface of the target substrate and horizontally towards the structure at least until the component physically contacts the structure or is adhered to the surface of the target substrate; and
separating the transfer element from the component.

US Pat. No. 10,714,373

ELECTROSTATIC CHUCK AND WAFER PROCESSING APPARATUS

Toto Ltd., Fukuoka (JP)

1. An electrostatic chuck, comprising:a ceramic dielectric substrate including a first major surface where a processing object is placed, a second major surface on a side opposite to the first major surface, and a sealing ring, the sealing ring forming a portion of the first major surface and being provided at a peripheral edge portion of the ceramic dielectric substrate, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and
an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being sintered in the ceramic dielectric substrate as one body,
the electrode layer including a plurality of electrode components arranged to be separated from each other,
an outer perimeter of the ceramic dielectric substrate being provided to cause a spacing between the outer perimeter of the ceramic dielectric substrate and an outer perimeter of the electrode layer to be uniform when viewed from a direction orthogonal to the first major surface,
the spacing between the outer perimeter of the electrode layer and the outer perimeter of the ceramic dielectric substrate being narrower than a spacing of the plurality of electrode components when viewed from the direction,
a width of the sealing ring being not less than 0.3 millimeters and not more than 3 millimeters,
a width where the electrode layer interfaces with the sealing ring being not less than ?0.7 millimeters and not more than 2 millimeters when viewed in the direction, where a negative width corresponds to a spacing between the electrode layer and the sealing ring in a state in which the electrode layer is separated from the sealing ring without overlapping the sealing ring when viewed in the direction, and wherein a positive width corresponds to an overlapping of the electrode layer and the sealing ring when viewed in the direction.

US Pat. No. 10,714,372

SYSTEM FOR COUPLING A VOLTAGE TO PORTIONS OF A SUBSTRATE

APPLIED MATERIALS, INC., ...

1. A substrate support assembly, comprising:a substrate support configured to support a substrate;
a cooling base disposed below the substrate support;
a plurality of electrodes extending through the substrate support and exposed at an upper surface of the substrate support, wherein each electrode is configured to contact the substrate, wherein each electrode is fixed or movably coupled to the cooling base, wherein each electrode is connected to a pair of switches, and wherein each switch has a switch frequency of about 1 MHz; and
a chucking electrode planarly embedded in the substrate support.

US Pat. No. 10,714,371

METHOD AND APPARATUS FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION

TAIWAN SEMICONDUCTOR MANU...

10. A lithographic system, comprising:a vacuum vessel having a first vacuum pressure;
a housing positioned in the vacuum vessel and having a second vacuum pressure that is higher than the first vacuum pressure, wherein the housing has an opening;
a reticle chuck positioned in the housing and having an effective surface for holding a reticle, wherein the effective surface is exposed through the opening;
an exposure tool configured to generate high-brightness light toward the reticle for reflection; and
a wafer stage configured to support a semiconductor wafer so as to allow the semiconductor wafer to receive the high-brightness light reflected from the reticle;
wherein the housing comprises:
a top housing member;
a lateral housing member extending from the top housing member and terminating at a lower edge which is located on a predetermined plane, wherein the effective surface of the reticle chuck is located between the predetermined plane and the top housing member; and
a lower housing member connected to the lower edge, wherein the opening is formed on the lower housing member, and a projection of the lower housing member in a direction that is perpendicular to the effective surface is located outside of the effective surface.

US Pat. No. 10,714,370

MOUNTING TABLE AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

13. A mounting table for mounting thereon an object to be processed, comprising:a base portion having a coolant path formed therein; and
an electrostatic chuck provided on the base portion, the electrostatic chuck having a mounting surface for mounting thereon the object and serving to electrostatically attract the object,
wherein the base portion includes:
(i) a first top surface on which the electrostatic chuck is provided;
(ii) a ring-shaped second top surface provided below the first top surface at an outer side of the first top surface;
(iii) a bottom surface;
(iv) a first side surface extending in a vertical direction between the first top surface and the second top surface; and
(v) a second side surface extending in a vertical direction between the second top surface and the bottom surface;
wherein the coolant path includes:
(i) a central path configured to circulate therein a liquid coolant and extending below the first top surface; and
(ii) a L-shaped peripheral path configured to circulate therein a liquid coolant and having (a) a first portion extending below the second top surface toward the second side surface and (b) a second portion extending above the second top surface toward the first top surface along the first side surface,
wherein a distance between an upper end of the second portion of the peripheral path and the first top surface is smaller than a distance between an upper end of the central path and the first top surface,
wherein the second portion has a fin structure,
wherein the fin structure has a U-shaped cross section, and
wherein the fin structure extends from an upper end toward a lower end of the peripheral path along the first side surface.

US Pat. No. 10,714,369

MICRO DEVICE TRANSFERRING METHOD AND MICRO DEVICE TRANSFERRING APPARATUS

KAISTAR LIGHTING (XIAMEN)...

1. A micro device transferring method comprises:providing a carrier substrate, wherein the carrier substrate comprises a transparent base, a light radiation activated adhesiveness-loss layer disposed on a first surface of the transparent base, and a plurality of micro devices arranged in an array on the light radiation activated adhesiveness-loss layer;
locally irradiating the light radiation activated adhesiveness-loss layer from a second surface of the transparent base to thereby reduce adhesiveness of a plurality of target areas of the light radiation activated adhesiveness-loss layer to the micro devices respectively located in the plurality of target areas, wherein the plurality of target areas are areas are corresponding to the micro devices to be transferred, and other areas of the light radiation activated adhesiveness-loss layer located outside the plurality of target areas have a stronger adhesiveness than the plurality of target areas after the locally irradiating;
applying a pickup force to the micro devices located in the plurality of target areas as well as the micro devices located in the other areas outside the plurality of target areas, picking up the micro devices located in the plurality of target areas by the pickup force while maintaining the micro devices located in the other areas being not picked up by the pickup force owning to the stronger adhesiveness; and
aligning the micro devices being picked up with corresponding locations of a receiving substrate, and then releasing the micro devices being picked up onto the receiving substrate.

US Pat. No. 10,714,368

CEILING TRANSPORT VEHICLE SYSTEM AND TEACHING UNIT

MURATA MACHINERY, LTD., ...

1. An overhead transport vehicle system comprising:an overhead transport vehicle to convey an object; and
a teaching unit to teach transfer of the object by the overhead transport vehicle to a load port on which the object is to be placed; wherein
the teaching unit includes:
a body including a detector to be brought into contact with a positioning pin disposed on the load port to detect a position of the positioning pin; and
a flange movable up and down with respect to the body and to be held by a holder to be raised and lowered by an elevator of the overhead transport vehicle.

US Pat. No. 10,714,367

FUME-REMOVING DEVICE

Bum Je Woo, Seongnam (KR...

1. An apparatus for removing fume, comprising:a wafer cassette for stacking a plurality of wafers;
a front opening for incoming and outgoing of the wafers;
an exhaust for exhausting fume of the wafers; and
a plurality of stacking shelves provided in the wafer cassette, for stacking the wafers vertically,
wherein said plurality of stacking shelves comprise a first stacking shelf supporting a first wafer among the wafers,
wherein said first stacking shelf comprises:
a plate-shaped body;
a purge gas flow path provided in said plate-shaped body in a horizontal direction, said purge gas flow path including a main flow path and branch flow paths branched from said main flow path;
a plurality of purge gas outlets formed on a side surface of said plate-shaped body and connected with said branch flow paths, respectively, for supplying purge gas;
a pin provided on said side surface of said plate-shaped body for directly supporting said first wafer; and
a ramp portion slanted towards a side of said front opening on said side surface of said plate-shaped body,
wherein said plurality of purge gas outlets comprise:
a plurality of first purge gas outlets supplying purge gas; and
a plurality of second gas purge outlets provided in said ramp portion and supplying purge gas towards said front opening.

US Pat. No. 10,714,366

SHAPE METRIC BASED SCORING OF WAFER LOCATIONS

KLA-Tencor Corp., Milpit...

1. A system configured for shape metric based sorting of wafer locations, comprising:one or more computer subsystems configured for:
selecting shape based grouping rules for at least two locations on a wafer, wherein for one of the locations on the wafer, selecting the shape based grouping rule comprises:
determining distances between geometric primitives in a field of view centered on the one location by modifying distances between the geometric primitives in a design for the wafer with metrology data for the one location on the wafer;
determining metrical complexity scores for shape based grouping rules associated with the geometric primitives in the field of view based on the determined distances between the geometric primitives; and
selecting one of the shape based grouping rules for the one location based on the metrical complexity scores; and
sorting the at least two locations on the wafer based on the shape based grouping rules selected for the at least two locations.

US Pat. No. 10,714,365

LIQUID PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A liquid processing apparatus comprising:a processing unit that processes a substrate by using processing liquid including first and second processing liquids;
a first supply route configured to supply the first processing liquid to the processing unit;
a first device that is used for supplying the first processing liquid to the first supply route;
a second supply route configured to supply the second processing liquid to the processing unit, the second processing liquid having higher temperature than the first processing liquid;
a second device that is used for supplying the second processing liquid to the second supply route;
a housing that accommodates the processing unit; and
an external housing that accommodates the first and second devices, the external housing being adjacent to the housing, wherein
the external housing includes a partition wall between the first and second devices.

US Pat. No. 10,714,364

APPARATUS AND METHOD FOR INSPECTING WAFER CARRIERS

Taiwan Semiconductor Manu...

1. An apparatus for inspecting wafer carriers, comprising:a housing having an opening on a wall of the housing;
a load port outside the housing, wherein the load port is coupled to the wall and configured to load a wafer carrier for inspection;
a robot arm inside the housing, wherein the robot arm is configured to move a first camera connected to the robot arm, wherein the first camera is configured to capture a plurality of images of the wafer carrier; and
a processor configured to process the plurality of images to inspect the wafer carrier.

US Pat. No. 10,714,363

PICKING UP AND PLACING OF MICRO LIGHT EMITTING DIODES USING POLYGON TOOL

Facebook Technologies, LL...

1. A system comprising:a carrier stage to hold a semiconductor device carrier;
a substrate stage to hold a target substrate;
a pick and place head (PPH) having a plurality of adjoined pick-up surfaces so that a cross-section of the PPH has a polygon shape, each pick-up surface configured to mount or release one or more semiconductor devices;
one or more micromanipulators mounting the PPH to rotate or move the PPH; and
a controller configured to control one or more micromanipulators to cause the PPH to:
rotate along the semiconductor device carrier to pick up arrays of semiconductor devices with the pick-up surfaces; and
rotate along the target substrate to place the arrays of semiconductor devices from the pick-up surfaces onto the target substrate.

US Pat. No. 10,714,362

SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A substrate processing apparatus comprising:a substrate holder configured to hold a plurality of substrates in an array at respective positions at predetermined intervals and used to hold a plurality of product substrates at the positions where the substrates are allocable and not hold any dummy substrate along with the product substrates;
a tubular reactor including an opening through which the substrate holder can be carried in and out at a lower side and a ceiling with a flat inner surface and houses the substrate holder;
a furnace body surrounding an upper side and a lateral side of the tubular reactor;
a main heater provided in the furnace body and configured to heat the side portion of the tubular reactor;
a ceiling heater provided in the furnace body and configured to heat the ceiling;
a lid that closes the opening;
a cap heater arranged inside the tubular reactor and also located below the substrate holder and configured to perform heating;
and
a gas supply mechanism configured to individually supply a gas to a top side of each of the plurality of product substrates held by the substrate holder inside the tubular reactor,
wherein a volume of an upper end space partitioned from others by the top plate and interposed between the ceiling and the top plate is set to 1 time or more and 3 times or less volume of a space interposed between the product substrates adjacent to each other and held by the substrate holder.

US Pat. No. 10,714,361

METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE USING AN INSULATING POLYMER LAYER

FOUNDATION FOR RESEARCH A...

1. A method of fabricating semiconductor packages, the method comprising:forming an insulating polymer layer on a substrate to cover a plurality of conductive patterns on the substrate;
planarizing the insulating polymer layer by pressing the insulating polymer layer downward by using at least one pressure member;
patterning the planarized insulating polymer layer to expose at least parts of the plurality of conductive patterns;
wherein the at least one pressure member comprises at least one roller,
wherein the planarizing comprises locally pressing the insulating polymer layer by rolling the at least one roller on the insulating polymer layer;
wherein the forming of the insulating polymer layer is performed based on a coating process using a coating solution added with a solvent, and
wherein the planarizing is performed by rolling the at least one roller on the insulating polymer layer to expose at least a part of the insulating polymer layer to discharge the solvent from the insulating polymer layer.

US Pat. No. 10,714,360

METHOD FOR MANUFACTURING A MODULE AND AN OPTICAL MODULE

MINEBEA MITSUMI Inc., Na...

1. A method for manufacturing a module including N layers of stacked resin, where N is a natural number of two or more, the method comprising steps of:curing resin of a first layer to a degree that does not fully harden the resin of the first layer;
stacking resin of a Mth layer on resin of a (M?1)th layer, wherein M is a natural number of two or more and less than N;
curing the resin of the Mth layer to a degree that does not fully harden the resin of the Mth layer;
repeating the steps of stacking the resin of the Mth layer and curing the resin of the Mth layer; and
stacking resin of Nth layer;
fully hardening all of the N layers of stacked resin.

US Pat. No. 10,714,359

SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. A device comprising:a package substrate, wherein the package substrate comprises:
a metal-clad insulated base material core, the metal-clad insulated base material core having a topmost surface and a bottommost surface opposite the topmost surface; and
a cavity extending through the metal-clad insulated base material core;
a first die at least partially within the cavity;
a first plurality of connectors in the cavity, the first plurality of connectors coupling the first die to the package substrate, the first plurality of connectors extending below the topmost surface of the metal-clad insulated base material core toward a bottommost surface of the cavity, the first plurality of connectors directly contacting the bottommost surface of the cavity;
a second die attached to the package substrate, the package substrate being interposed between the first die and the second die; and
a second plurality of connectors electrically coupling the second die to the package substrate, wherein at least one connector of the second plurality of connectors is disposed outside of a perimeter of the second die in a plan view, the at least one connector of the second plurality of connectors being electrically interposed between the second die and the package substrate through one or more redistribution layers (RDLs) interposed between the second die and the second plurality of connectors.

US Pat. No. 10,714,358

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor layer containing indium by sputtering method;
forming a conductive film comprising a region in contact with the oxide semiconductor layer; and
etching the conductive film for forming a source electrode and a drain electrode and etching a region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,
wherein the oxide semiconductor layer comprises a region in which a c-axis of a crystal is aligned along a direction perpendicular to a surface of the oxide semiconductor layer.

US Pat. No. 10,714,357

METHODS FOR IMPROVED CRITICAL DIMENSION UNIFORMITY IN A SEMICONDUCTOR DEVICE FABRICATION PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a device layer over a substrate;
forming a hard mask layer over the device layer, wherein forming the hard mask layer over the device layer includes forming the hard mask layer directly on the device layer;
forming a patterned protector layer over the hard mask layer, wherein forming the patterned protector layer over the hard mask layer includes forming the patterned protector layer directly on the hard mask layer;
forming a patterning layer over the patterned protector layer;
removing a first portion of the patterning layer to expose a first portion of the patterned protector layer and a first portion of the hard mask layer;
removing the first portion of the hard mask layer to expose a first portion of the device layer and a first portion of the substrate;
removing a second portion of the patterning layer; and
removing the first portion of the device layer.

US Pat. No. 10,714,356

PLASMA PROCESSING METHOD

PANASONIC INTELLECTUAL PR...

1. A plasma processing method, comprising steps of:preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet;
adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier;
sagging the holding sheet in the inner region;
setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does; and
plasma processing the substrate,
wherein a sag amount Q of the holding sheet in the inner region is controlled to be greater than a distortion amount R of the frame in the sagging step.

US Pat. No. 10,714,355

PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma etching method, comprising:a recess forming process of forming a recess having a depth smaller than a thickness of a first silicon oxide film by etching the first silicon oxide film by a first plasma generated from a first processing gas, wherein a silicon-containing reaction product is formed by the first plasma and adhered to the recess in the recess forming process;
a removing process of removing the silicon-containing reaction product by a second plasma generated from a second processing gas; and
a penetrating process of forming a hole penetrating the first silicon oxide film by etching the recess, from which the silicon-containing reaction product is removed, by the first plasma until a film formed under the first silicon oxide film is exposed,
wherein the first processing gas and the second processing gas contain a fluorocarbon gas, and
a flow rate of the fluorocarbon gas of the second processing gas is larger than a flow rate of the fluorocarbon gas of the first processing gas.

US Pat. No. 10,714,354

SELF LIMITING LATERAL ATOMIC LAYER ETCH

Lam Research Corporation,...

1. An apparatus for processing a substrate, the apparatus comprising:a process chamber;
a gas box having a plurality of first outlets and a second outlet that are both fluidly connected with the process chamber via a plurality of top inlets and a side inlet;
a mixing chamber for mixing ammonia with one or more of the process gases, the mixing chamber separate from the gas box, fluidly connected to the plurality of first outlets, fluidly connected with the plurality of top inlets and the side inlet, and fluidly interposed between the first outlet, and the plurality of top inlets and the side inlet such that:
gas is configured to flow from the plurality of first outlets, through the mixing chamber, and to the plurality of top inlets and the side inlet, and
gas is configured to flow from the second outlet and to the plurality of top inlets and the side inlet without flowing through the mixing chamber;
a first set of parallel valves fluidly interposed between the mixing chamber, and the plurality of top inlets and the side inlet, and configured to control the flow of gas between the mixing chamber and the plurality of top inlets and the side inlet;
a second set of parallel valves fluidly interposed between the second outlet, and the plurality of top inlets and the side inlet, and configured to control the flow of gas between the second outlet and the plurality of top inlets and the side inlet;
a first gas source in the gas box comprising an oxidant and fluidly connected to one of the first outlets;
a second gas source in the gas box comprising a fluorine-containing etchant and fluidly connected to another one of the first outlets;
a heater configured to heat a substrate in the process chamber; and
a controller having at least one processor and a memory, wherein:
the at least one processor and the memory are communicatively connected with one another,
the memory stores non-transient, computer-executable instructions for controlling the at least one processor to control the gas box, the first set of parallel valves, and the second set of parallel valves to:
(i) cause the oxidant gas to flow to the process chamber housing a substrate to conformally oxidize surface of a feature in a semiconductor layer of the substrate to form an oxidized surface,
(ii) cause, after (i), the fluorine-containing etchant gas to flow to the process chamber housing the substrate to expose the substrate to the fluorine-containing etchant gas to isotropically etch the oxidized surface of the substrate in a self-limiting reaction selective to non-oxidized semiconductor material,
(iii) cause, after (ii), the heater to heat the substrate to remove non-volatile solid etch byproducts by sublimation, and
(iv) repeat (i), (ii), and (iii).

US Pat. No. 10,714,353

PLANARIZATION METHOD

DISCO CORPORATION, Tokyo...

1. A planarization method for planarizing a separation surface of a silicon carbide ingot after a focal point of a laser beam with such a wavelength as to be transmitted through silicon carbide is positioned at a depth corresponding to a wafer to be generated from an end surface of the silicon carbide ingot and the silicon carbide ingot is irradiated with the laser beam to form a separation layer in which silicon carbide is separated into silicon and carbon and cracks are isotropically generated along a c-plane, and the wafer is separated from the silicon carbide ingot at the separation layer, the planarization method comprising:a grinding step of holding an opposite side to the separation surface in the silicon carbide ingot by a rotatable chuck table and rotating a grinding wheel having a plurality of grinding abrasives disposed in a ring manner to grind the separation surface of the silicon carbide ingot held by the chuck table; and
a flatness detection step of irradiating the separation surface of the silicon carbide ingot exposed from the grinding wheel with light and detecting reflected light to detect a degree of flatness, wherein:
the grinding step is ended when it has been detected in the flatness detection step that the separation surface of the silicon carbide ingot has become flat,
wherein:
in the flatness detection step, detecting that the separation surface has become flat comprises irradiating the separation surface with the light at an oblique incident angle ?, and receiving the reflected light at an oblique reflection angle ?, and determining when an amount of received light surpasses a threshold, wherein said oblique incident angle ? is equal to said oblique reflection angle ?.

US Pat. No. 10,714,348

SEMICONDUCTOR DEVICE HAVING HYDROGEN IN A DIELECTRIC LAYER

Taiwan Semiconductor Manu...

1. A structure comprising:an active area on a substrate, the active area having a channel region;
a gate structure over the channel region of the active area, wherein the gate structure includes:
an interfacial layer over the active area;
a conformal dielectric layer over the interfacial layer; and
a gate electrode layer over the interfacial layer; and
wherein a ratio of a peak concentration of hydrogen in the interfacial layer to a peak concentration of hydrogen in the conformal dielectric layer is in a range from about 0.1 to about 5.

US Pat. No. 10,714,347

CUT METAL GATE PROCESSES

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:etching a gate stack to form a trench extending into the gate stack;
forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench;
etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench, wherein the first portion of the dielectric layer is directly over a portion of the gate stack, wherein a second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched;
etching a portion of the gate stack directly underlying the removed first portion of the dielectric layer;
after the portion of the gate stack is etched, removing the second portion of the dielectric layer to reveal the sidewall of the gate stack; and
filling the trench with a dielectric material to form a dielectric region, wherein the dielectric region contacts the sidewall of the gate stack.

US Pat. No. 10,714,346

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A method of manufacturing a semiconductor device comprising in a following order:a MOS structure forming step where a gate electrode is formed on a first main surface side of a semiconductor base substrate with a gate insulation film interposed therebetween and, thereafter, an interlayer insulation film is formed so as to cover the gate electrode;
a metal layer forming step where a metal layer in a state of being connected with the gate electrode is formed over the interlayer insulation film;
an electron beam irradiating step where a lattice defect is formed in the inside of the semiconductor base substrate by irradiating an electron beam to the semiconductor base substrate from the first main surface side or a second main surface side in a state where the metal layer is set to a ground potential;
a metal layer dividing step where the metal layer is divided into a plurality of electrodes; and
an annealing step where the lattice defect in the semiconductor base substrate is repaired by heating the semiconductor base substrate.

US Pat. No. 10,714,345

PLASMA ASSISTED DOPING ON GERMANIUM

LAM RESEARCH CORPORATION,...

1. A method for forming a junction in a germanium (Ge) layer of a substrate, comprising:arranging the substrate in a processing chamber;
supplying a doping plasma gas mixture to the processing chamber including a phosphorus (P) gas species and an antimony (Sb) gas species;
striking plasma in the processing chamber for a predetermined doping period; and
annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.

US Pat. No. 10,714,344

MASK FORMATION BY SELECTIVELY REMOVING PORTIONS OF A LAYER THAT HAVE NOT BEEN IMPLANTED

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:forming a dielectric layer over a substrate, the dielectric layer having a conductive region therein;
forming a mask layer over the dielectric layer;
forming a first patterned mask over the mask layer, the first patterned mask having a first opening exposing a first portion of the mask layer, the first patterned mask covering a second portion of the mask layer;
performing one or more species implant processes into the first portion of the mask layer;
removing the first patterned mask;
etching the second portion of the mask layer to form a second patterned mask, wherein an etch rate of the first portion is less than an etch rate of the second portion;
after removing the second portion, etching the dielectric layer using the second patterned mask as a mask to form a second opening; and
forming a conductive material in the second opening.

US Pat. No. 10,714,343

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base;
forming a to-be-etched material layer on the base;
forming a mask material layer on the to-be-etched material layer;
performing a first doping treatment on a partial region of the mask material layer, wherein:
the first doping treatment is suitable for increasing an etching selection ratio of the mask material layer that has not undergone the first doping treatment to the mask material layer that has undergone the first doping treatment,
after the first doping treatment is performed, the mask material layer comprises a first mask-material-layer part and a to-be-removed second mask-material-layer part, and
the first mask-material-layer part is a part that has undergone the first doping treatment in the mask material layer, or, the second mask-material-layer part is a part that has undergone the first doping treatment in the mask material layer;
after the first doping treatment is performed, forming, in the mask material layer, a first trench exposing a part of the to-be-etched material layer, wherein the first trench is at least located in the first mask-material-layer part;
after the first trench is formed, removing the second mask-material-layer part, and forming a second trench exposing a part of the to-be-etched material layer in the remaining mask material layer;
removing the to-be-etched material layer exposed from the first trench and the second trench, and forming a target pattern layer; and
after the target pattern layer is formed, removing the remaining mask material layer.

US Pat. No. 10,714,342

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate;
a gate structure over the substrate;
a plug disposed over and electrically connected to the gate structure; and
a hard mask structure over the gate structure, comprising a first hard mask layer and a second hard mask layer, wherein the first hard mask layer surrounds and is in contact with the plug, the second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

US Pat. No. 10,714,341

REACTIVE ION ETCHING ASSISTED LIFT-OFF PROCESSES FOR FABRICATING THICK METALLIZATION PATTERNS WITH TIGHT PITCH

ELPIS TECHNOLOGIES INC., ...

1. A method comprising:forming a sacrificial layer having a first thickness on a top surface of a substrate;
forming a mask layer over the sacrificial layer, wherein the mask layer comprises an opening;
isotropically etching a portion of the sacrificial layer exposed through the opening of the mask layer to form an undercut region of a second thickness in the top portion of the sacrificial layer below the mask layer, wherein the undercut region defines an overhang structure, wherein the second thickness is less than the first thickness;
anisotropically etching a remaining portion of the sacrificial layer exposed through the opening of the mask layer to form an opening through the sacrificial layer down to the top surface of the substrate;
directionally depositing a metallic material to at least partially fill the opening formed in the sacrificial layer with metallic material without coating the overhang structure with metallic material; and
dissolving the sacrificial layer to lift-off the mask layer and the metallic material deposited on the mask layer thereby leaving a metal line disposed on the top surface of the substrate;
wherein the metallic material within the opening of the sacrificial layer comprises the metal line disposed on the top surface of the substrate, wherein an upper portion of the metal line comprises a tapered profile.

US Pat. No. 10,714,340

METHOD FOR PROCESSING WORKPIECE

TOKYO ELECTRON LIMITED, ...

1. A method for processing a workpiece, comprising:providing, in a processing container, a workpiece including a layer to be etched, an organic film provided on the layer, an antireflection film provided on the organic film, and a first mask provided on the antireflection film,
conformally forming a protective film on a surface of the first mask; and
removing the antireflection film by atomic layer etching with plasma using the first mask on which the protective film is formed.

US Pat. No. 10,714,339

SELECTIVELY DEPOSITED PARYLENE MASKS AND METHODS RELATED THERETO

APPLIED MATERIALS, INC., ...

1. A method of selectivity depositing a mask layer on a patterned surface of a substrate, comprising:positioning the substrate on a substrate support in a processing volume of a processing chamber, wherein the patterned surface of the substrate comprises a dielectric layer and a plurality of first metal features disposed in the dielectric layer;
exposing the patterned surface to a parylene monomer gas;
selectively depositing a first layer comprising parylene onto surfaces of the dielectric layer; and
depositing a second layer onto the plurality of first metal features.

US Pat. No. 10,714,338

WAFER BOW REDUCTION

ANVIL SEMICONDUCTORS LIMI...

1. A method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide epitaxial layer grown on the silicon wafer, the method comprising:applying nitrogen atoms during the epitaxial growth of the silicon carbide epitaxial layer on the silicon wafer so as to generate a compressive stress within the composite wafer;
wherein the epitaxial growth occurs at an epitaxial growth rate; and
wherein the epitaxial growth takes place over a low growth rate region, a transition region, and a high growth rate region; and
wherein the nitrogen atoms are incorporated into the silicon carbide epitaxial layer at a first incorporation rate close to an interface in the low growth rate region; and
wherein the nitrogen atoms are incorporated into the silicon carbide epitaxial layer at an incorporation rate which is inversely proportional to the epitaxial growth rate in the silicon carbide epitaxial layer in the low growth rate region away from the interface and in the transition region; and
wherein the nitrogen atoms incorporated during the single crystal epitaxial growth of the silicon carbide epitaxial layer are in addition to the nitrogen of the doping concentration of the silicon carbide epitaxial layer so that the nitrogen atoms do not form part of the doping concentration of the silicon carbide epitaxial layer.

US Pat. No. 10,714,337

PROCESS FOR GROWING NANOWIRES OR NANOPYRAMIDS ON GRAPHITIC SUBSTRATES

CRAYONANO AS, Trondheim ...

1. A process for growing nanowires or nanopyramids comprising:(I) providing a graphitic substrate and depositing AlGaN, InGaN, AlN or AlGa(In)N on said graphitic substrate at an elevated temperature to form nanoscale nucleation islands of AlGaN, InGaN, AlN or AlGa(In)N; and
(II) growing a plurality of semiconducting group III-V nanowires or nanopyramids on the nanoscale nucleation islands on the graphitic substrate, wherein the plurality of semiconducting group III-V nanowires or nanopyramids are grown axially and are therefore formed from a first section and a second section, wherein the first section and the second section are each doped with a different dopant to generate a p-n junction or p-i-n junction.

US Pat. No. 10,714,336

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Kokusai Electric Corporat...

1. A method of manufacturing a semiconductor device, comprising:(a) forming a seed layer in an amorphous state on a substrate by supplying a source gas to the substrate;
(b) polycrystallizing the seed layer by processing the seed layer by heat; and
(c) performing a cycle a predetermined number of times to form an oxide film on a polycrystallized seed layer and to oxidize the polycrystallized seed layer, the cycle comprising: (c-1) supplying the source gas to the substrate; and (c-2) supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate, wherein (c-1) and (c-2) are non-simultaneously performed.

US Pat. No. 10,714,335

METHOD OF DEPOSITING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

ASM IP Holding B.V., Alm...

1. A method of depositing a thin film on a pattern structure of a semiconductor substrate, the method comprising:(a) supplying a source gas;
(b) supplying a reactive gas; and
(c) supplying plasma,
wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a frequency of at least 60 MHz or greater,
wherein the pattern structure has a top surface, a bottom surface, and a side surface that connects the top surface with the bottom surface, a length of the side surface being greater than a width of the top surface and a width of the bottom surface,
the frequency of at least 60 MHz or greater is used to form the thin film having a uniform physical thickness and uniform chemical characteristics on an entire area of the top surface, the bottom surface, and the side surface of the pattern structure,
wherein, in the step (c), the plasma is supplied in a pulse mode, and an overall amount of plasma supplied is equal to an amount of the plasma supplied in a continuous mode, and
wherein at least one material is activated during a PEALD process and has reactivity with the pattern structure, so that at least a portion of the pattern structure is damaged during the step (c), generating a difference between critical dimensions (CDs) of an inner space and an outer space of the pattern structure,
wherein, in order to decrease loss of the pattern structure, the plasma is supplied onto the semiconductor substrate at a duty ratio of 50%, and the plasma is supplied at a power amount twice that of the plasma supplied in the continuous mode.

US Pat. No. 10,714,334

CONDUCTIVE FEATURE FORMATION AND STRUCTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a conductive structure comprising:forming a dielectric layer on a semiconductor substrate, the semiconductor substrate having a source/drain region;
forming an opening through the dielectric layer to the source/drain region; and
by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process, forming a silicide region on the source/drain region and a barrier layer in the opening along sidewalls of the dielectric layer, wherein each precursor used in the same PECVD process is introduced to the dielectric layer simultaneously.

US Pat. No. 10,714,333

APPARATUS AND METHOD FOR SELECTIVE OXIDATION AT LOWER TEMPERATURE USING REMOTE PLASMA SOURCE

APPLIED MATERIALS, INC., ...

1. A method for selective oxidation of non-metal surfaces, comprising:positioning a substrate in a processing chamber, wherein the processing chamber is maintained at a pressure less than 2 Torr;
flowing activated hydrogen gas into the processing chamber through a first inlet, the activated hydrogen gas activated by a hot wire apparatus;
soaking the substrate in the activated hydrogen gas in the absence of plasma comprising oxygen;
generating a remote RF plasma comprising oxygen after soaking the substrate in the activated hydrogen gas;
flowing the remote RF plasma into the processing chamber through a second inlet, wherein the remote RF plasma mixes with the activated hydrogen gas to create an activated processing gas; and
exposing the substrate to the activated processing gas.

US Pat. No. 10,714,332

FILM FORMING METHOD AND FILM FORMING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A film forming method for forming a silicon nitride film to cover a stepped portion formed in a substrate, the stepped portion being formed by exposed surfaces of different types of first and second base films which are stacked one above another, the method comprising:forming a seed layer that includes a nitride film and covers the stepped portion so as to allow the silicon nitride film to uniformly grow on the surface of the first base film and on the surface of the second base film,
wherein the nitride film is formed by supplying, to the substrate, a silicon-free base-film nitriding gas containing nitrogen for nitriding the first and second base films, exposing the substrate to plasma to supply silicon-free radicals containing nitrogen to the surface of the stepped portion, and nitriding the surface of the stepped portion; and
subsequently, forming the silicon nitride film on the seed layer by supplying, to the substrate, a raw material gas of silicon and a silicon-nitriding gas for nitriding silicon,
wherein the act of forming the seed layer is performed in a state where an internal pressure of a vacuum container in which the substrate is received is set to be higher than that used when forming the silicon nitride film.

US Pat. No. 10,714,331

METHOD TO FABRICATE THERMALLY STABLE LOW K-FINFET SPACER

APPLIED MATERIALS, INC., ...

1. A method of forming a spacer layer, the method comprising:disposing a substrate in an internal volume of a processing chamber, the substrate having a film formed thereon, the film comprising silicon, carbon, nitrogen, and hydrogen;
introducing a process gas into the processing chamber, wherein the process gas comprises high pressure steam;
exposing the film to the process gas to form a reacted film, such that the reacted film comprises silicon, carbon, oxygen, and hydrogen; and
purging the internal volume with an inert gas.

US Pat. No. 10,714,330

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A STEP OF PERFORMING ION IMPLANTATION USING A RESIST PATTERN AS A MASK

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate;
(b) forming a resist pattern over the semiconductor substrate;
(c) forming a first film over the semiconductor substrate in such a manner as to cover the resist pattern;
(d) ion implanting an impurity into the semiconductor substrate with the resist pattern covered with the first film;
(e) after the step (d), removing the first film by wet etching; and
(f) after the step (e), removing the resist pattern, and
further comprising a step of:
(a1) after the step (a), and before the step (b), forming an insulation film over the semiconductor substrate,
wherein the insulation film and the first film are formed of mutually different materials,
wherein in the step (b), the resist pattern is formed over the insulation film,
wherein in the step (c), the first film is formed over the insulation film in such a manner as to cover the resist pattern, and
wherein in the step (e), wet etching is performed under the conditions in which the first film is more likely to be etched than the resist pattern, and the insulation film is less likely to be etched than the first film, thereby to remove the first film.

US Pat. No. 10,714,329

PRE-CLEAN FOR CONTACTS

Taiwan Semiconductor Manu...

1. A method, comprising:forming a dielectric layer over a contact region on a substrate;
etching the dielectric layer to form a contact opening to expose the contact region; and
pre-cleaning the exposed contact region to remove a residual material formed by the etching, wherein the pre-cleaning comprises:
exposing the contact region to an inductively coupled radio frequency (RF) plasma;
applying, with a direct current power supply unit (DC PSU), a bias voltage to the substrate; and
applying a magnetic field to the inductively coupled RF plasma to collimate ions from the inductively coupled RF plasma.

US Pat. No. 10,714,328

SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:a supporter configured to support a wafer;
a first member including a first portion that faces a first region on an upper face of the wafer and a second portion that intervenes between the wafer and the first portion, wherein the first portion has an annular shape, and the second portion has a cylindrical shape;
a second member including a third portion that faces a second region on the upper face of the wafer and a fourth portion that intervenes between the wafer and the third portion, wherein the second region is positioned on a side of a periphery portion of the wafer with respect to the first region, the third portion has an annular shape surrounding the first portion, and the fourth portion has a cylindrical shape surrounding the second portion;
a rotator configured to rotate the first member and to rotate the second member independently of the first member;
a first liquid feeder configured to feed a first liquid for processing the wafer to the first region;
a first gas feeder configured to feed a first gas between the wafer and the first portion;
a second gas feeder configured to feed a second gas between the wafer and the second portion; and
a second liquid feeder configured to feed a second liquid to the wafer, wherein the second liquid feeder includes an upper face feeder configured to feed the second liquid to the second region of the upper face of the wafer, and, in addition to the upper face feeder, a lower face feeder configured at a lower face of the wafer to feed the second liquid to the lower face of the wafer, and the upper and lower face feeders feed the second liquid to an edge portion of the wafer, wherein
the first and second portions are disposed to fill a space above the first region with the first gas, and
the second, third and fourth portions are disposed to fill a space above the second region with the second gas.

US Pat. No. 10,714,327

SYSTEM AND METHOD FOR PUMPING LASER SUSTAINED PLASMA AND ENHANCING SELECTED WAVELENGTHS OF OUTPUT ILLUMINATION

KLA-Tencor Corporation, ...

1. A system for pumping laser sustained plasma and enhancing one or more selected wavelengths of output illumination generated by the laser sustained plasma, the system comprising:one or more pump modules configured to generate pump illumination for the laser sustained plasma, the pump illumination directed along one or more pump illumination paths that are non-collinear to an output illumination path of the output illumination; and
one or more enhancing illumination sources configured to generate enhancing illumination at one or more selected wavelengths, the enhancing illumination directed along an illumination path that is collinear to the output illumination path of the output illumination so that the enhancing illumination is combined with the output illumination, thereby enhancing the output illumination at the one or more selected wavelengths.

US Pat. No. 10,714,326

LASER ABLATION SPECTROMETRY SYSTEM

The Regents of the Unvers...

1. A system comprising:a microscope;
a laser, the laser being positioned to emit light through an objective lens of the microscope;
a continuous flow probe coupled to a spectrometer, an end of the continuous flow probe positioned proximate a sample and between the sample and the objective lens; and
a gas confinement device, the gas confinement device defining:
a gas inlet,
a chamber, the chamber being in fluid communication with the gas inlet,
a platform, the platform operable to support a sample, the platform being outside of the chamber,
a plurality of vents, each of the plurality of vents being positioned to direct a gas substantially parallel to the platform, and
a plurality of channels, the plurality of channels operable to provide fluid communication between the chamber and the plurality of vents.

US Pat. No. 10,714,325

GLOW DISCHARGE ION SOURCE

Micromass UK Limited, Wi...

1. A mass spectrometer comprising:a first vacuum chamber;
an atmospheric pressure ion source for generating first ions, wherein first ions generated by said atmospheric pressure ion source are transmitted, in use, into said vacuum chamber via a sampling cone or first aperture, wherein the direction along which at least some of said first ions are transmitted, in use, through said sampling cone or first aperture into said first vacuum chamber defines a first axis;
a glow discharge device for generating second ions, wherein said second ions comprise lock mass or calibration ions for calibrating the mass spectrometer, wherein second ions generated by said glow discharge device are generated within said first vacuum chamber and a discharge pin of said glow discharge device is arranged orthogonally to said first axis, and wherein said second ions are transmitted into or generated within said first vacuum chamber without being transmitted through said sampling cone or first aperture; and
one or more dispensing devices for dispensing one or more reagents in proximity to said glow discharge device, wherein said one or more reagents comprise one or more lock mass or calibration reagents for mass calibrating the mass spectrometer, which lock mass or calibration reagents are ionised, in use, by a glow discharge formed or generated by said discharge pin of said glow discharge device to generate said second ions comprising lock mass or calibration ions,
wherein said second ions comprising lock mass or calibration ions and said first ions are onwardly transmitted from said first vacuum chamber through the same extraction cone or aperture and into a downstream chamber of said mass spectrometer,
wherein the first vacuum chamber comprises a central cylindrical bore or port to control the passage of the second ions, and the discharge pin of the glow discharge device is located within the central cylindrical bore or port of the first vacuum chamber.

US Pat. No. 10,714,324

INLET INSTRUMENTATION FOR ION ANALYSER COUPLED TO RAPID EVAPORATIVE IONISATION MASS SPECTROMETRY (“REIMS”) DEVICE

Micromass UK Limited, Wi...

1. An apparatus comprising:a first device for generating aerosol, smoke or vapour from one or more regions of a target;
an inlet conduit to an ion analyser or mass spectrometer, said inlet conduit having an inlet through which said aerosol, smoke or vapour passes;
a Venturi pump arrangement arranged and adapted to direct said aerosol, smoke or vapour towards said inlet, wherein said Venturi pump arrangement is arranged and adapted to direct said aerosol, smoke or vapour onto a deflection device or surface prior to said aerosol, smoke or vapour passing through said inlet, wherein said deflection device comprises a hollow member having a first side and a second side, wherein the first side is solid and the second side comprises one or more apertures arranged and adapted to allow said aerosol, smoke or vapour to pass therethrough and wherein said Venturi pump arrangement is arranged and adapted to direct said aerosol, smoke or vapour onto the first surface of said deflection device;
a matrix conduit for introducing and mixing a matrix with said aerosol, smoke or vapour prior to said aerosol, smoke or vapour passing through the inlet; and
a collision surface located within a vacuum chamber and arranged and adapted such that said aerosol, smoke or vapour is caused to impact upon said collision surface so as to generate a plurality of analyte ions.

US Pat. No. 10,714,323

ZERO VOLTAGE MASS SPECTROMETRY PROBES AND SYSTEMS

Purdue Research Foundatio...

1. A system comprising:a mass spectrometry probe comprising a porous material, wherein at least a portion of a surface of the porous material comprises one or more modified properties; and
a mass spectrometer, wherein the system operates without an application of voltage to the probe.

US Pat. No. 10,714,322

IRMS SAMPLE INTRODUCTION SYSTEM AND METHOD

Thermo Fisher Scientific ...

1. A method of introducing a sample into an Isotope Ratio Spectrometer, comprising steps of(a) generating sample ions in a solvent matrix in an ionization source;
(b) removing at least a proportion of the solvent matrix from the sample ions in a desolvation chamber, so as to produce a flow of sample ions along with non-ionized solvent and solvent ions into a separation chamber;
(c) applying voltages to electrodes in the separation chamber to apply an AC and/or a DC electric field to the flow of ions along with solvent vapors, so as to direct wanted sample ions, having a first mass to charge ratio or range of mass to charge ratios, along a first flow path towards an outlet of the separation chamber, whilst unwanted solvent ions, other ions, and non-ionized solvent are directed away from the said separation chamber outlet, the unwanted solvent ions and other ions having a second mass to charge ratio or range of mass to charge ratios, different to the said first mass to charge ratio or range of ratios; and
(d) decomposing the sample ions to molecular products once they have passed through the outlet of the separation chamber and into a reaction chamber; and
(e) providing molecular products of the decomposed sample ions to the Isotope Ratio Spectrometer.

US Pat. No. 10,714,321

SPUTTERING TARGET WITH BACKSIDE COOLING GROOVES

Applied Materials, Inc., ...

1. A sputtering target for a sputtering chamber, the sputtering target comprising:a circular sputtering plate, comprising:
a sputtering surface;
a backside surface opposite the sputtering surface, wherein the backside surface has a radially inner region, a radially middle region, and a radially outer region, the backside surface having:
a plurality of circular grooves which are spaced apart from one another; and
at least one channel cutting through the circular grooves and extending from the radially inner region to the radially outer region of the circular sputtering plate;
an annular back surface opposite the sputtering surface;
an inclined outer peripheral wall that extends from an outer edge of the sputtering surface to an outer edge of the annular back surface;
a first inner peripheral wall that extends from the backside surface to an inner edge of the annular back surface, wherein a recess that exposes the backside surface of the circular sputtering plate is defined by the backside surface and the first inner peripheral wall; and
an annular-shaped backing plate mounted to the circular sputtering plate, wherein the annular-shaped backing plate, comprises:
an annular-shaped body that defines an open annulus exposing the backside surface of the circular sputtering plate, the annular-shaped body defined by:
a front surface contacting the annular back surface of the circular sputtering plate;
an annular flange that extends beyond a radius of the circular sputtering plate, the annular flange comprising a peripheral circular surface having an outer footing operable to rest on a surface; and
a second inner peripheral wall that extends from an inner edge of the front surface to the annular flange and aligns with the first inner peripheral wall of the circular sputtering plate.

US Pat. No. 10,714,320

PLASMA PROCESSING METHOD INCLUDING CLEANING OF INSIDE OF CHAMBER MAIN BODY OF PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method including cleaning of an inside of a chamber main body of a plasma processing apparatus,wherein the plasma processing apparatus comprises:
the chamber main body which provides a chamber;
a stage, provided within the chamber, having an electrostatic chuck configured to hold a processing target object placed thereon; and
a temperature control device configured to adjust a temperature of the electrostatic chuck, and
wherein the plasma processing method comprises:
etching an etching target film of the processing target object placed on the electrostatic chuck by generating plasma of a processing gas containing a fluorocarbon gas and/or a hydrofluorocarbon gas within the chamber, the etching of the etching target film including a main etching of etching the etching target film in a state that the temperature of the electrostatic chuck is set to be equal to or lower than ?30° C. by the temperature control device, wherein the etching target film is a silicon oxide film, a silicon nitride film or a multilayered film composed of one or more silicon oxide films and one or more silicon nitride films stacked on top of each other alternately;
carrying-out the processing target object from the chamber after the etching of the etching target film is performed; and
cleaning the inside of the chamber main body by generating plasma of a cleaning gas containing oxygen within the chamber in a state that the temperature of the electrostatic chuck is set to be equal to or higher than 0° C. to reduce a deposit containing carbon and fluorine by the temperature control device after the carrying-out of the processing target object is performed,
wherein the etching of the etching target film further includes an overetching of etching the etching target film additionally after the main etching is performed, and
raising the temperature of the electrostatic chuck by the temperature control device when the overetching is being performed, in order to raise the temperature of the electrostatic chuck to be equal to or higher than 0° C. before the cleaning of the inside of the chamber main body is performed.

US Pat. No. 10,714,319

APPARATUS AND METHODS FOR REMOVING CONTAMINANT PARTICLES IN A PLASMA PROCESS

APPLIED MATERIALS, INC., ...

1. A method of operating a plasma processing chamber, the method comprising:performing a plasma process at a process pressure and a process power to generate plasma;
ramping down the process power and the process pressure substantially simultaneously to an intermediate power level and an intermediate pressure level, respectively, wherein the intermediate power level and the intermediate pressure level are selected so as to raise a plasma sheath boundary above a threshold height from a surface of a substrate;
maintaining the intermediate power level for a first time period and maintaining the intermediate pressure level for a second time period while flowing a purge gas from a showerhead assembly; and
reducing the intermediate power level and the intermediate pressure level to a zero power level and a base pressure, respectively.

US Pat. No. 10,714,318

PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method comprising:setting a position in a height direction of an upper surface of a focus ring that surrounds an edge of a substrate mounted on a supporting table in a chamber of a plasma processing apparatus;
generating plasma in the chamber to perform plasma processing on the substrate in a state where the position in the height direction of the upper surface of the focus ring is maintained; and
applying a negative DC voltage to the focus ring in a state where the position in the height direction of the upper surface of the focus ring is maintained during the generation of the plasma,
wherein in said setting, the focus ring, which has a thickness set such that the position in the height direction of the upper surface of the focus ring mounted on a mounting region of the supporting table is lower than a reference position that is a position in a height direction of an upper surface of the substrate mounted on the supporting table, is loaded into the chamber and mounted on the mounting region to surround the edge of the substrate, or the focus ring is moved in the chamber such that the position in the height direction of the upper surface of the focus ring becomes lower than the reference position.

US Pat. No. 10,714,317

REDUCTION OF CONDENSED GASES ON CHAMBER WALLS VIA HEATED CHAMBER HOUSING FOR SEMICONDUCTOR PROCESSING EQUIPMENT

Axcelis Technologies, Inc...

1. A workpiece processing system, comprising:a chamber having one or more chamber walls defining a respective one or more surfaces generally enclosing a chamber volume;
one or more chamber wall heaters associated with the one or more chamber walls, wherein the one or more chamber wall heaters are configured to selectively heat the one or more chamber walls to a chamber wall temperature;
a workpiece support positioned within the chamber and configured to selectively support a workpiece having one or more materials residing thereon, wherein each of the one or more materials has a respective condensation temperature associated therewith, above which, the one or more materials are respectively in a gaseous state;
a heater apparatus configured to selectively heat the workpiece to a predetermined temperature; and
a controller configured to heat the workpiece to the predetermined temperature via a control of the heater apparatus, thereby heating the one or more materials to respectively form one or more outgassed materials within the chamber volume, and wherein the controller is further configured to control the chamber wall temperature via a control of the one or more chamber wall heaters, wherein the chamber wall temperature is greater than a condensation temperature associated with the one or more outgassed materials, thereby preventing a condensation of the outgassed material on the one or more surfaces.

US Pat. No. 10,714,316

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:supplying a first process gas to a process space where a substrate is accommodated, and using an inert gas as a carrier gas of the first process gas; and
supplying plasma of a second process gas to the process space where the substrate is accommodated, and using an active auxiliary gas, which is different from the inert gas, as a carrier gas of the second process gas,
wherein the plasma of the second process gas is supplied without the inert gas, which is used in the act of supplying the first process gas,
wherein the inert gas is supplied in the act of supplying the first process gas without supplying the active auxiliary gas, which is used in the act of supplying the plasma of the second process gas, and
wherein the act of supplying the plasma is performed by setting an internal pressure of the process space to be lower than an internal pressure of the process space in the act of supplying the first process gas.

US Pat. No. 10,714,315

SEMICONDUCTOR REACTION CHAMBER SHOWERHEAD

ASM IP Holdings B.V., Al...

1. A showerhead comprising:a base plate comprising a least a portion of an exhaust channel and having an opening and a plurality of base plate slots;
a middle plate positioned within the opening and having a plurality of middle plate slots and protrusions, the protrusions each comprising a protrusion slot; and,
an upper plate comprising a top surface having a plurality of cooling fins formed therein, a first gas hole and a second gas hole,
wherein the first gas hole conveys a first gas into a first gas cavity and the second gas hole conveys a second gas into a second gas cavity,
wherein each of the plurality of base plate slots is concentrically aligned with the plurality of middle plate slots,
wherein the first gas cavity is defined between the upper plate and the middle plate and the second gas cavity is defined between the middle plate and the base plate,
wherein the first gas cavity and the second gas cavity are fluidly coupled to the exhaust channel,
wherein a first gas purge channel extends from the first gas cavity, wherein the first gas purge channel feeds into a first plenum, wherein the first plenum is coupled to a first valve,
wherein a second gas purge channel extends from the second gas cavity, wherein the second gas purge channel feeds into a second plenum, wherein the second plenum is coupled to a second valve,
wherein one of the first and second valves is configured to provide a purge gas into the first or second gas cavity,
wherein the other of the first and second valves is configured to provide a negative pressure to the first or second gas cavity,
wherein the first gas purge channel extends from the first gas cavity through an opening that is separate from the first gas hole,
wherein the second gas purge channel extends from the second gas cavity through an opening that is separate from the second gas hole,
wherein the first and second gas purge channels do not convey the first gas or the second gas into the first and second gas cavities,
wherein the first gas cavity is in fluid communication with the first gas hole and the second gas cavity is in fluid communication with the second gas hole,
wherein the protrusions extend into the base plate slots,
wherein a gap is formed between each protrusion and each base plate slot and the gap is in fluid communication with the second gas cavity,
wherein the protrusion slots are in fluid communication with the first gas cavity,
wherein the protrusion slots comprise a first radius extending through a portion of the protrusion and a second radius that is smaller than the first radius extending through another portion of the protrusion,
wherein the protrusions extend to at least a bottom surface of the base plate slots, and
wherein the gap terminates at the bottom surface.

US Pat. No. 10,714,313

HIGH FREQUENCY AMPLIFIER APPARATUSES

1. A high-frequency amplifier apparatus suitable for generating power for plasma excitation, the apparatus comprising:two Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors each having a drain terminal and a source terminal that is connected to a ground connection point, wherein the LDMOS transistors are embodied alike and are arranged as a package;
a circuit board that lies flat on a metal cooling plate and is connected to the cooling plate, wherein the cooling plate is connectable to ground by a plurality of ground connections, wherein the package is arranged on the circuit board;
a power transformer including a primary winding connected to the drain terminals of the two LDMOS transistors; and
a signal transformer including a secondary winding having a first end and a second end, wherein
the secondary winding is connected at the first end to a first gate terminal of one of the two LDMOS transistors by one or more first resistive elements, and
the secondary winding is connected at the second end to a second gate terminal of the other of the two LDMOS transistors by one or more second resistive elements; and
wherein each of the first gate terminal and second gate terminal is connected to ground by one or more voltage-limiters.

US Pat. No. 10,714,312

DATA PROCESSING METHOD, CHARGED PARTICLE BEAM WRITING APPARATUS, AND CHARGED PARTICLE BEAM WRITING SYSTEM

NuFlare Technology, Inc.,...

1. A data processing method for generating writing data from design data and registering the writing data in a charged particle beam writing apparatus, the method comprising:generating the writing data by performing a plurality of conversion processes on a plurality of pieces of first frame data obtained through division of the design data corresponding to one chip; and
performing a plurality of preprocessing processes on a plurality of pieces of second frame data obtained through division of the writing data of the chip, and registering the writing data of the chip in the charged particle beam writing apparatus,
wherein the plurality of conversion processes are performed in frame-basis pipeline processing, and the plurality of preprocessing processes are performed in frame-basis pipeline processing,
wherein the writing data is registered in the charged particle beam writing apparatus on a frame basis,
wherein consistency information including checksum information, mesh size for area calculation and maximum shot size for calculation of number of shots is generated in the preprocessing process, and
wherein a consistency process including a process of determining whether or not a mask accommodates the chip and checksum verification is performed by use of the consistency information in the preprocessing process.

US Pat. No. 10,714,311

INDIVIDUAL BEAM DETECTOR FOR MULTIPLE BEAMS, MULTI-BEAM IRRADIATION APPARATUS, AND INDIVIDUAL BEAM DETECTION METHOD FOR MULTIPLE BEAMS

NuFlare Technology, Inc.,...

1. An individual beam detector for multiple beams comprising:a thin film configured in which a passage hole smaller than a pitch between beams of multiple beams each being an electron beam and larger than a diameter of a beam of the multiple beams is formed, and through which the multiple beams can penetrate;
a support base configured to support the thin film, in which an opening is formed under a region including the passage hole in the thin film, and a width size of the opening is formed to have a temperature of a periphery of the passage hole in the thin film higher than an evaporation temperature of impurities adhering to the periphery in a case that the thin film is irradiated with the multiple beams; and
a sensor arranged, in a case where a surface of the thin film is scanned with the multiple beams, at a position away from the thin film by a distance based on which a detection target beam having passed through the passage hole of the thin film can be detected by the sensor as a detection value with contrast discernible from beams which have penetrated the thin film and are passing the opening without being blocked by the support base.

US Pat. No. 10,714,310

METHODS AND APPARATUS FOR HIGH THROUGHPUT SEM AND AFM FOR CHARACTERIZATION OF NANOSTRUCTURED SURFACES

NANOWEAR INC., Brooklyn,...

1. A method of forming an overlay image, comprising(a) providing an SEM image of a nanosensor sample including a plurality of vertically free standing nanostructures;
(b) AFM imaging a top portion of selected ones of the plurality of vertically standing nano structures;
(c) creating an overlaid image including an AFM imaged top portion overlayed on the SEM image.

US Pat. No. 10,714,309

USING IMAGES FROM SECONDARY MICROSCOPE DETECTORS TO AUTOMATICALLY GENERATE LABELED IMAGES FROM PRIMARY MICROSCOPE DETECTORS

FEI Company, Hillsboro, ...

1. A method for generating labeled images from a microscope detector of a first modality by leveraging detector data from a different microscope detector of a different modality:applying a focused charged beam to a sample;
generating, using an X-ray detector system and based on emissions resultant from the focused charged beam being incident on the sample, X-ray detector data;
automatically generating, by one or more processors of a computing device, a labeled first image based on the X-ray detector data, the labeled first image including composition information about at least a portion of the sample, wherein the automatically generating the labeled first image comprises:
generating, by the one or more processors and based on the X-ray detector data, a first image of the sample;
determining, by the one or more processors based on the X-ray detector data and using energy dispersive X-ray spectroscopy, composition information about a portion of the sample; and
automatically labeling, by the one or more processors, a region of the first image that is associated with the portion of the sample with the composition information;
generating, based on the emissions resultant from the focused charged beam being incident on the sample, a second image using a microscope detector system, wherein the microscope detector system is of a different modality than the X-ray detector system; and
automatically labeling, by the one or more processors and based on the second image and the first image, a region of the second image associated with the portion of the sample with the composition information from the labeled first image.

US Pat. No. 10,714,308

MEASUREMENT METHOD AND ELECTRON MICROSCOPE

JEOL Ltd., Tokyo (JP)

1. A measurement method for measuring, in an electron microscope including a segmented detector having a detection plane segmented into a plurality of detection regions, a direction of each of the plurality of detection regions in a scanning transmission electron microscope (STEM) image,the measurement method comprising:
shifting an electron beam incident on a sample under a state where the detection plane is conjugate to a plane shifted from a diffraction plane to shift the electron beam on the detection plane, and measuring a shift direction of the electron beam on the detection plane with the segmented detector; and
obtaining the direction of each of the plurality of detection regions in the STEM image from the shift direction.

US Pat. No. 10,714,307

NEUTRAL ATOM IMAGING SYSTEM

KLA-Tencor Corporation, ...

12. A neutral atom imaging system, comprising:a neutral helium imaging sub-system, wherein the neutral helium imaging sub-system comprises:
a neutral atom source configured to generate a beam of neutral atoms and direct the beam to a sample;
an ionizer configured to collect neutral atoms scattered from the surface of the sample and to ionize the collected neutral atoms to generate ionized atoms;
a selector configured to receive the ionized atoms from the ionizer and to selectively filter the ionized atoms;
one or more ion optics; and
a detector, wherein the one or more ion optics are configured to receive selected ionized atoms from the selector and focus the selected ionized atoms onto the detector, wherein the detector is configured to generate one or more images of the sample based on received selected ionized atoms; and
a controller comprising a memory and one or more processors, the controller configured to receive the one or more images from the detector and determine one or more characteristics of the sample based on the one or more images.

US Pat. No. 10,714,305

RETRACTABLE DETECTOR

Applied Materials Israel ...

1. A charged particle beam system, comprising:a chamber including a top, sidewalls, and a bottom;
a stage disposed within the chamber, the stage configured to support a specimen;
charged particle beam optics having a charged particle beam optics tip configured to output a primary charged particle beam;
a detector comprising a body and a detector tip that includes an aperture, the body of the detector comprising an upper portion disposed above the top of the chamber, a lower portion disposed below the top of the chamber, and an intermediate portion coupled between the upper portion and the lower portion and extending through an opening in the top of the chamber; and
a motion module disposed outside the chamber and configured to move the detector between a first position and a second position;
wherein, when the detector is positioned at the first position, the aperture of the detector tip is aligned with a path of the primary charged particle beam; and
wherein, when the detector is positioned at the second position, the aperture of the detector tip is not aligned with the path of the primary charged particle beam.

US Pat. No. 10,714,304

CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Tech Corpora...

1. A charged particle beam device comprising:an optical element configured to adjust a charged particle beam emitted from a charged particle source;
an adjustment element configured to adjust the charged particle beam incident on the optical element; and
a control device configured to control the adjustment element, wherein
the control device obtains an extent of deviation from an equilibrium temperature of the optical element based on a condition setting of the optical element and executes adjustment with the adjustment element when the extent of deviation satisfies a predetermined condition.

US Pat. No. 10,714,303

ENABLING HIGH THROUGHPUT ELECTRON CHANNELING CONTRAST IMAGING (ECCI) BY VARYING ELECTRON BEAM ENERGY

International Business Ma...

1. A method for electron channeling contrast imaging (ECCI) of a crystalline wafer, the method comprising the steps of:placing the crystalline wafer under an electron microscope having an angle of less than 90° relative to a surface of the crystalline wafer;
generating an electron beam, by the electron microscope, incident on the crystalline wafer;
varying an accelerating voltage of the electron microscope to access a channeling condition of the crystalline wafer;
varying the accelerating voltage of the electron microscope to access at least one different channeling condition of the crystalline wafer; and
obtaining an image of the crystalline wafer.

US Pat. No. 10,714,302

ION BEAM IRRADIATION APPARATUS

NISSIN ION EQUIPMENT CO.,...

1. An apparatus comprising:a beam current measuring device configured to be retractably moved into an ion beam trajectory so as to measure an ion beam current;
a first electrode disposed immediately upstream of the beam current measuring device in an ion beam transport channel, the first electrode being configured to serve both as a suppressor electrode for repelling secondary electrons released from the beam current measuring device, back toward the beam current measuring device while measuring the ion beam current, and as a beam optical element other than the suppressor electrode that controls the ion beam passing therethrough;
a second electrode disposed immediately upstream of the first electrode in the ion beam transport channel; and
an energy filter disposed downstream of the first electrode,
wherein a voltage difference between a second voltage potential of the second electrode and a voltage potential of a target disposed in a processing chamber determines an acceleration and deceleration of the ion beam traveling in the ion beam transport channel toward a target position of the target, and
a first voltage potential of the first electrode suppresses excessive convergence of the ion beam which would otherwise occur in the ion beam transport channel.

US Pat. No. 10,714,301

CONDUCTIVE BEAM OPTICS FOR REDUCING PARTICLES IN ION IMPLANTER

Varian Semiconductor Equi...

1. An ion implantation system, comprising:an electrostatic filter for delivering an ion beam to a wafer, the electrostatic filter comprising:
a housing having an exit proximate the wafer; and
a plurality of conductive beam optics within the housing, the plurality of conductive beam optics arranged around an ion beam-line, and the plurality of conductive beam optics comprising:
a set of entrance aperture electrodes proximate an entrance aperture of the housing;
a set of energetic electrodes downstream along the ion beam-line from the set of entrance aperture electrodes;
a set of ground electrodes downstream along the ion beam-line of the set of energetic electrodes, wherein the set of energetic electrodes is positioned farther away from the ion beam-line than the set of entrance aperture electrodes and the set of ground electrodes; and
a set of terminal electrodes positioned between the set of entrance aperture electrodes and the set of energetic electrodes; and
an electrical system in communication with the electrostatic filter, the electrical system operable to supply a voltage and a current to the plurality of conductive beam optics.

US Pat. No. 10,714,300

STATIONARY ANODE FOR AN X-RAY GENERATOR, AND X-RAY GENERATOR

SIEMENS HEALTHCARE GMBH, ...

1. A stationary anode for an X-ray generator, comprising:a main anode body; and
an internal cooling duct, running in an axial direction, to convey a cooling fluid to a heat exchange surface of the main anode body that is disposed opposite a target, wherein a nozzle, disposed at an end of the internal cooling duct, is positioned with respect to the heat exchange surface via stop elements such that, between the heat exchange surface and the nozzle, a gap is formed extending over an angular range of 360° about the axial direction, a central region of the heat exchange surface being conically shaped and forming a conically shaped region disposed opposite a funnel-shaped outlet orifice of the nozzle, wherein the conically shaped region of the heat exchange surface extends into the funnel-shaped outlet orifice.

US Pat. No. 10,714,299

THERMOELECTRICALLY-COOLED X-RAY SHIELD

The Boeing Company, Chic...

1. A system for x-ray backscatter inspection, the system comprising:an interior cavity;
a non-conductive fluid contained within the interior cavity;
a power source within the interior cavity and submerged in the non-conductive fluid;
an x-ray cathode within the interior cavity, submerged in the non-conductive fluid, and coupled to the power source;
an x-ray anode within the interior cavity, submerged in the non-conductive fluid, and positioned to receive an electron emission from the x-ray cathode to generate an x-ray emission; and
a thermoelectric cooler surrounding the interior cavity and operable to draw heat from the non-conductive fluid, wherein the thermoelectric cooler comprises a heat dissipation layer forming an exterior surface of the system and a heat absorption layer disposed opposite the heat dissipation layer.

US Pat. No. 10,714,298

X-RAY ARRANGEMENT WITH STATOR OPTIMIZED FOR MINIMAL FOCAL SPOT MOVEMENT

SIEMENS HEALTHCARE GMBH, ...

1. An X-ray arrangement, comprising:a vacuum vessel, a rotating anode and a rotor of an electrical machine being non-rotatably interconnected rotatably mounted in the vacuum vessel such that the rotating anode and the rotor are rotatable about an axis of rotation, wherein, viewed in a direction of an axis of rotation, a stator is disposed in a region of the rotor, externally enclosing the vacuum vessel in a radial manner with respect to the axis of rotation,
wherein the rotor and the stator together constitute a rotary electrical machine by which the rotating anode is rotatable about the axis of rotation,
wherein the stator includes a laminated core which, viewed orthogonally to the axis of rotation, includes a yoke running around the axis of rotation and from which stator teeth extend onto the axis of rotation, and
wherein a winding system, including a plurality of individual phases, is disposed in spaces between the stator teeth of the laminated stator core, the winding system including windings, individual turns of the windings each being configured to respectively engage over a plurality of the stator teeth, and the stator being designed such that when identical phase voltages are applied to the individual phases of the winding system, the individual phases are each respectively configured to produce stray magnetic fields of identical magnitude.

US Pat. No. 10,714,297

SPIRAL GROOVE BEARING ASSEMBLY WITH MINIMIZED DEFLECTION

General Electric Company,...

1. A bearing assembly adapted for use with an x-ray tube, the assembly comprising:a. a shaft;
b. a sleeve rotatably disposed around the shaft, the sleeve including a seating portion forming an open end of the sleeve, wherein the seating portion includes at least one axial slot formed therein; and
c. a thrust seal seated at least partially within the seating portion, the thrust seal having a central aperture through which the shaft extends.

US Pat. No. 10,714,296

ION SOURCE WITH TAILORED EXTRACTION SHAPE

Axcelis Technologies, Inc...

1. An ion source, comprising:an ion source housing defining an ion generating chamber for confining a high density concentration of ions therein; and
an extraction member associated with the ion source housing defining an extraction aperture for allowing ions to exit the ion generating chamber, wherein the extraction aperture has a tailored shape characterized by having a longitudinal axis and a lateral axis, the extraction aperture being further defined by:
a central portion having a first width dimension extending along the lateral axis: and
first and second distal portions extending from opposite sides of the central portion along the longitudinal axis, the opposed distal portions having a second width dimension extending parallel to the lateral axis that is greater than the first width dimension of the central portion;
wherein the extraction member has a side profile that is convex such that a depth dimension of the extraction member is greatest adjacent the central portion of the tailored shape extraction aperture and has a reduced depth dimension adjacent the distal portions.

US Pat. No. 10,714,295

METAL ENCAPSULATED PHOTOCATHODE ELECTRON EMITTER

KLA-Tencor Corporation, ...

1. An electron emitter comprising:a photocathode structure that includes one or more of Cs2Te, CsKTe, CsI, CsBr, GaAs, GaN, InSb, CsKSb, or a metal;
a substrate;
a protective film disposed on an exterior surface of the photocathode structure opposite the substrate, wherein the protective film includes one or more of ruthenium, nickel, platinum, chromium, copper, gold, silver, aluminum, or an alloy thereof; and
a second protective film between the substrate and the photocathode structure, wherein the second protective film includes one or more of ruthenium, nickel, platinum, chromium, copper, gold, silver, aluminum, or an alloy thereof.

US Pat. No. 10,714,294

METAL PROTECTIVE LAYER FOR ELECTRON EMITTERS WITH A DIFFUSION BARRIER

KLA-Tencor Corporation, ...

1. An apparatus comprising:an emitter, wherein the emitter has a diameter of 100 nm or less;
a protective cap layer disposed on an exterior surface of the emitter, wherein the protective cap layer includes molybdenum; and
a diffusion barrier between the emitter and the protective cap layer, wherein the diffusion barrier includes TiN, carbon, B4C, or boron.

US Pat. No. 10,714,293

CARBON NANOTUBE FIBER CARPET STRUCTURE

1. An apparatus comprisinga backing material; and
a plurality of looped carbon nanotube (CNT) fiber conductors fixed to the backing material and extending outward from the backing material in an array, wherein the CNT fiber conductor comprises a first end and a second end, the first end fixed to the backing material, and the second end fixed to the backing material a predetermined distance from the first end in order to form a loop of the CNT fiber conductor extending away from a backing material surface.