US Pat. No. 10,658,403

TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A thin-film transistor (TFT) substrate, comprising a backing plate, a light shielding layer, a buffer layer, a combination of an active layer, a source electrode and a drain electrode, a first gate insulation layer, a second gate insulation layer, a gate electrode, a first passivation layer, a planarization layer, a common electrode, a second passivation layer, and a pixel electrode, wherein the backing plate, the light shielding layer, the buffer layer, the combination, the first gate insulation layer, the second gate insulation layer, the gate electrode, the first passivation layer, the planarization layer, the common electrode, the second passivation layer, and the pixel electrode are stacked in sequence from bottom to top;wherein the source electrode and the drain electrode are respectively located at two opposite sides of the active layer, the source electrode and the drain electrode being both formed by subjecting a semiconductor to heavy ion doping, the active layer comprising two lightly-ion-doped semiconductor layers and a channel-zone semiconductor layer, wherein the two lightly-ion-doped semiconductor layers are respectively located at two ends of the active layer and connected with the source electrode and the drain electrode, and the channel-zone semiconductor layer is located between and connected to the two lightly-ion-doped semiconductor layers;
the first gate insulation layer covers the active layer, the source electrode, the drain electrode, and the buffer layer; the second gate insulation layer and the active layer overlap each other and are separated from each other by the first gate insulation layer; and the gate electrode and the channel-zone semiconductor layer overlap each other and are separated from each other by the first and second gate insulation layers; and
a first via is formed to extend through the first gate insulation layer, the first passivation layer, and the planarization layer and expose a portion of the drain electrode, a portion of the second passivation layer being located in the first via and contacting the drain electrode; and a second via extends through the portion of the second passivation layer that is located in the first via such that the second via contacts the drain electrode, the pixel electrode being connected through the second via to the drain electrode.

US Pat. No. 10,658,402

MANUFACTURING METHODS FOR LOW TEMPERATURE POLY-SILICON ARRAY SUBSTRATE AND LOW TEMPERATURE POLY-SILICON THIN-FILM TRANSISTOR

WUHAN CHINA STAR OPTOELEC...

1. A method for manufacturing a low temperature poly-silicon array substrate comprising a pixel region comprising a plurality of pixels arranged in an array, and each of the plurality of pixels comprising a first thin-film transistor and a corresponding pixel electrode and a driving region comprising a driving circuit having a CMOS circuit, the CMOS circuit comprising a second thin-film transistor and a third thin-film transistor; the first thin-film transistor and the second thin-film transistor being an n-type thin-film transistor, and the third thin-film transistor being a p-type thin-film transistor; wherein the manufacturing method comprising:providing a substrate;
forming a poly-silicon semiconductor pattern on the substrate; wherein a first channel region, a first source region and a first drain region are formed on a first portion of the poly-silicon semiconductor pattern that corresponds to the first thin-film transistor and the second thin-film transistor;
forming a gate insulation layer;
performing an activation treatment at a temperature of greater than or equal to 500 degrees Centigrade;
forming a gate from a metal material having a melting temperature less than 500 degrees Centigrade on the gate insulation layer after the activation treatment;
forming an interlayer insulation layer between the gate insulation layer and the gate;
performing a hydrogen treatment at a temperature greater than or equal to 400 degrees Centigrade and less than or equal to 500 degrees Centigrade;
forming a source/drain pattern on the interlayer insulation layer after the hydrogen treatment, and connecting the source/drain pattern to the first source region and the first drain region in the poly-silicon semiconductor pattern via a through hole.

US Pat. No. 10,658,401

CARRIER RELEASE

FLEXENABLE LIMITED, Camb...

1. A method comprising:providing an assembly temporarily adhered on at least one side to at least one carrier by an adhesive element, the assembly including at least one plastic support sheet; and
heating the assembly while mechanically compressing the assembly and the adhesive element,
wherein the strength of adhesion of at least said adhesive element to the carrier and/or to the assembly is partially reduced during said heating of the assembly and adhesive element under mechanical compression, and
wherein the strength of adhesion of the said adhesive element to the carrier and/or to the assembly is further reducible by further heating the said adhesive element after partially or completely relaxing the pressure at which the assembly and adhesive element is mechanically compressed.

US Pat. No. 10,658,400

METHOD OF MANUFACTURING DISPLAY DEVICE HAVING A MULTILAYERED UNDERCOATING LAYER OF SILICON OXIDE AND SILICON NITRIDE

Japan Display Inc., Mina...

1. A method of manufacturing a display device comprising:forming a resin layer on a glass substrate;
forming a first silicon oxide film having a thickness of 10 to 50 nm above the resin layer such that a peripheral portion of the first silicon oxide film contacts with the glass substrate;
forming a silicon nitride film above the first silicon oxide film;
forming a second silicon oxide film above the silicon nitride film;
forming an active layer of a thin-film transistor above the second silicon oxide film; and
peeling the resin layer from the glass substrate,
wherein
the resin layer, above which the active layer is formed, has a downward minimum bend radius R of 2 mm or less, wherein the downward minimum bend radius R is obtained by bending an evaluation object downward by 180° by putting the evaluation object in close contact with half a periphery of a rod.

US Pat. No. 10,658,399

TRANSISTOR AND DISPLAY DEVICE HAVING THE SAME

Samsung Display Co., Ltd....

1. A transistor comprising:a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion;
an insulating pattern covering the channel portion and exposing the first and second contact portions;
a first insulating layer covering the semiconductor layer and the insulating pattern;
a floating gate facing the channel portion of the semiconductor layer and disposed on the first insulating layer, the insulating pattern being disposed between the floating gate and the channel portion;
a gate electrode facing the floating gate; and
source electrode and drain electrode contacted with the first contact portion and the second contact portion, respectively,
wherein the floating gate comprises an oxide semiconductor.

US Pat. No. 10,658,398

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate;
a buffer layer on the substrate;
a first semiconductor layer of a first transistor on the buffer layer;
a first insulating layer on the first semiconductor layer;
a first gate electrode of the first transistor on the first insulating layer;
a second insulating layer on the first gate electrode; and
a second semiconductor layer of a second transistor on the second insulating layer, wherein
a difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms, and
the first semiconductor layer and the second semiconductor layer respectively include polysilicon.

US Pat. No. 10,658,397

FLEXIBLE DISPLAY PANEL, MANUFACTURING METHOD OF FLEXIBLE DISPLAY PANEL AND DISPLAY APPARATUS

WUHAN CHINA STAR OPTOELEC...

1. A flexible display panel comprising:a flexible base;
a barrier layer formed on the flexible base;
a buffer layer formed on the barrier layer;
an active layer and a gate insulating layer formed on the buffer layer;
a gate metal layer and a second insulating layer formed on the gate insulating layer;
a second metal layer and an interlayer insulating layer formed on the second insulating layer;
a second interlayer insulating layer formed on the interlayer insulating layer; and
a source/drain metal layer formed on the second interlayer insulating layer;
wherein a first via hole and a second contact hole are formed on the second interlayer insulating layer, the source/drain metal layer is in communication with the active layer through the first via hole, and the source/drain metal layer is in communication with the second interlayer insulating layer through the second contact hole.

US Pat. No. 10,658,396

ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

9. An array substrate, comprising:a substrate, the substrate having a binding region on one side, the binding region comprising a plurality of binding pads arranged in order, wherein at least one dummy pad is provided in a first position of the binding pads, the at least one dummy pad dividing the binding region into a plurality of binding sub-regions, each binding sub-region comprising a plurality of binding pads, the at least one dummy pad has a label, and the label is used for indicating a serial number of a binding sub-region corresponding to the dummy pad.

US Pat. No. 10,658,395

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first insulator;
a first conductor over the first insulator;
a second conductor over the first insulator;
a second insulator over the first insulator and overlapping the first conductor, with the first conductor being between the second insulator and the first insulator; and
a third insulator over the first insulator and overlapping the second conductor, with the second conductor being between the third insulator and the first insulator,
wherein the second insulator comprises the same material as the third insulator,
wherein the third insulator surrounds is spaced from the second insulator with a gap therebetween,
wherein the first conductor and the second conductor comprise a metal A,
wherein the metal A is one kind or a plurality of kinds of aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, magnesium, beryllium, indium, and ruthenium,
wherein the metal A is detected in an interface between the first insulator and the second insulator and in an interface between the first insulator and the third insulator by an energy dispersive X-ray spectroscopy (EDX), and
wherein a region of the first insulator exposed from the gap comprises a groove.

US Pat. No. 10,658,394

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a base substrate;
a first electrode layer comprising a plurality of pixel electrode pairs arranged in an array, each of the pixel electrode pairs comprising a first pixel electrode and a second pixel electrode which is adjacent to the first pixel electrode in a row direction;
a data line disposed between the first pixel electrode and the second pixel electrode of a same pixel electrode pair in the row direction and extending in a column direction; and
a first common portion, an orthographic projection of the first common portion on the base substrate being at least partially overlapped with an orthographic projection of at least one of adjacent first pixel electrode or second pixel electrode of two adjacent pixel electrode pairs in the row direction on the base substrate, the first common portion and the first electrode layer being insulated from each other,
the array substrate further comprising: at least one of a sixth common line or a seventh common line, wherein the sixth common line is disposed on a first side of the data line, and an orthographic projection of the first pixel electrode adjacent to the data line on the base substrate is at least partially overlapped with an orthographic projection of the sixth common line on the base substrate; and the seventh common line is disposed on a second side of the data line opposite to the first side, and an orthographic projection of the second pixel electrode adjacent to the data line on the base substrate is at least partially overlapped with an orthographic projection of the seventh common line on the base substrate.

US Pat. No. 10,658,393

THIN-FILM TRANSISTOR SUBSTRATE

Samsung Display Co., Ltd....

1. A thin-film transistor substrate, comprising:a first thin-film transistor disposed on a substrate, the first thin-film transistor comprising a first semiconductor layer, a first gate electrode, and a first electrode;
a second thin-film transistor comprising a second gate electrode, a second electrode electrically connected to the first electrode, and a second semiconductor layer disposed on the first semiconductor layer and overlapping at least a portion of the first semiconductor layer; and
a contact hole formed on the first semiconductor layer, the contact hole passing through the second semiconductor layer, at least a portion of the contact hole overlapping the first semiconductor layer and the second semiconductor layer, respectively,
wherein the second electrode overlaps the first electrode.

US Pat. No. 10,658,392

MICRO LIGHT-EMITTING DIODE DISPLAY DEVICE AND MICRO LIGHT-EMITTING DIODE DRIVING CIRCUIT THEREOF

MIKRO MESA TECHNOLOGY CO....

1. A micro light-emitting diode display device, comprising:a driving transistor comprising:
a substrate;
a bottom gate present on the substrate;
a gate insulator present on the bottom gate;
a semiconductor layer present on the gate insulator;
an etch stopper present on the semiconductor layer, wherein the etch stopper is ring-shaped;
a drain electrode present on the etch stopper and in contact with the semiconductor layer, wherein the drain electrode is ring-shaped and a contact portion between the drain electrode and the semiconductor layer surrounds the semiconductor layer;
a source electrode present on the etch stopper and in contact with the semiconductor layer, wherein the source electrode is enclosed by the drain electrode, and the drain electrode and the source electrode form a ring-shaped opening, and at least a portion of the etch stopper is exposed by the ring-shaped opening; and
an insulating layer present on the drain electrode, the source electrode, and the etch stopper, wherein the insulating layer has at least one via therein to expose a portion of one of the source electrode and the drain electrode, or to expose a portion of the source electrode and a portion of the drain electrode; and
a micro light-emitting diode having a lateral length less than or equal to 50 ?m electrically connected to one of the source electrode and the drain electrode, comprising:
a first type semiconductor layer;
an active layer present on and joined with the first type semiconductor layer; and
a second type semiconductor layer present on and joined with the active layer, wherein a current injection channel is extended within one of the first type semiconductor layer and the second type semiconductor layer of the micro light-emitting diode, and the current injection channel is separated from a side surface of the micro light-emitting diode.

US Pat. No. 10,658,391

HYBRID SUBSTRATE ENGINEERING IN CMOS FINFET INTEGRATION FOR MOBILITY IMPROVEMENT

International Business Ma...

1. A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device, comprising:orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI;
exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench;
forming spacers on sidewalls of the trench;
epitaxially growing the base substrate from a bottom of the trench to form an extended region;
epitaxially growing a fin material, including a material different from the base substrate, from the extended region within the trench;
restoring the mask layer and the dielectric layer over the trench; and
etching both the fin material and the extended region across their entire vertical heights to form fins therefrom of a much lesser width than the fin material to define P-type fin field-effect transistor (PFET) fins such that the fin material forms an entirety of a device channel in each of the PFET fins on the base substrate and etching fins for N-type fin field-effect transistor (NFET) fins in the semiconductor layer.

US Pat. No. 10,658,390

VIRTUAL DRAIN FOR DECREASED HARMONIC GENERATION IN FULLY DEPLETED SOI (FDSOI) RF SWITCHES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:one or more active devices on a semiconductor on insulator material which is on top of a substrate;
a virtual drain region comprising a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate, and the virtual drain region being spaced apart from a source/drain region of an adjacent device of the one or more active devices;
a shallow trench isolation region partly within the virtual drain region, wherein an edge of the virtual drain region is remote from an edge of the shallow trench isolation region; and
a doped skin on the shallow trench isolation region, facing the adjacent device of the one or more active devices.

US Pat. No. 10,658,389

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a first insulating film over the first transistor;
a second insulating film over the first insulating film;
a second transistor over the second insulating film;
a first conductive film electrically connected to the first transistor; and
a second conductive film electrically connected to the first conductive film and the second transistor,
wherein the first conductive film penetrates the first insulating film,
wherein the second conductive film penetrates one of a source electrode and a drain electrode of the second transistor, a semiconductor film of the second transistor, and the second insulating film,
wherein a channel formation region of the first transistor comprises a single crystal semiconductor,
wherein a channel formation region of the second transistor comprises an oxide semiconductor, and
wherein a width of a bottom surface of the second conductive film is 5 nm or less.

US Pat. No. 10,658,388

METHODS OF FORMING STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a first circuit element in and above a first semiconductor layer, wherein said first semiconductor layer is formed on a first buried insulating layer;
forming drain and source regions of said first circuit element at least partially in said first semiconductor layer; and
forming a layer stack above said first circuit element, said layer stack comprising a conductive layer, a second buried insulating layer formed above said conductive layer, and a second semiconductor layer formed above said second buried insulating layer, wherein said conductive layer is electrically isolated from said drain and source regions.

US Pat. No. 10,658,387

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:oxidizing at least a first exposed portion and a second exposed portion of a strained silicon germanium layer formed on top of a substrate, the oxidizing forming at least one patterned strained silicon germanium area within the strained silicon germanium layer comprising a first oxide end region and a second oxide end region corresponding to the first and second exposed portions, respectively, of the strained silicon germanium layer.

US Pat. No. 10,658,386

THERMAL EXTRACTION OF SINGLE LAYER TRANSFER INTEGRATED CIRCUITS

pSemi Corporation, San D...

1. A thermal conduction structure for an integrated circuit transistor device made using a back-side access process and mounted on a handle wafer such that a gate of the transistor device is oriented towards the handle wafer, including:(a) at least one laterally-extending thermal path fabricated in conjunction with the integrated circuit transistor device and having a near portion in close thermal contact with the transistor device, and a far portion sufficiently spaced away from the transistor device in a lateral direction from the transistor device so as to be couplable to a generally orthogonal thermal pathway, each laterally-extending thermal path being substantially electrically isolated from the transistor device; and
(b) at least one generally orthogonal thermal pathway thermally coupled to at least one laterally-extending thermal path and configured to convey heat from the at least one laterally-extending thermal path to at least one of (i) at least one externally accessible thermal pad, or (ii) the handle wafer.

US Pat. No. 10,658,385

CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED ON FOUR GATE ELECTRODE TRACKS

Tela Innovations, Inc., ...

1. A cross-coupled transistor circuit, comprising:a first PMOS transistor defined by a gate electrode extending along a first gate electrode track;
a second PMOS transistor defined by a gate electrode extending along a second gate electrode track;
a first NMOS transistor defined by a gate electrode extending along a third gate electrode track;
a second NMOS transistor defined by a gate electrode extending along a fourth gate electrode track,
wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node,
wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node,
wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor and the second PMOS transistor and the second NMOS transistor are formed by respective conductive structures physically separated from each other, and
wherein the first and second PMOS transistors are collectively separated from the first and second NMOS transistors by an inner region that does not include any of a transistor source region and a transistor drain region.

US Pat. No. 10,658,384

FERRO-ELECTRIC COMPLEMENTARY FET

INTERNATIONAL BUSINESS MA...

1. A field-effect transistor (FET), comprising:a semiconductor substrate having a first side, a second side opposite from the first side, a third side that connects the first side and the second side, and a fourth side opposite the third side that connects the first side and the second side; and
a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises
a gate insulating layer;
a ferroelectric material layer disposed on the gate insulating layer; and
a metal layer disposed on the ferroelectric material layer,
wherein a portion of the upper surface of the substrate that extends from the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first side and the second side, and
a portion of the upper surface of the substrate that extends from the third side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the fourth side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the third side and the fourth side;
self-aligned silicided contacts formed in the n-types contacts and in the p-type contacts;
sidewall spacers form along sides of a stack of the gate insulating layer, the ferroelectric material layer, and the metal layer, and
self-aligned silicided shorts between at least one n-type contact and at least one p-type contact,
wherein a presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

US Pat. No. 10,658,383

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a nonvolatile semiconductor memory device,the nonvolatile semiconductor memory device comprising:
a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction;
a selection gate electrode stacked on the stacked structural unit in the first direction;
an insulating layer stacked on the selection gate electrode in the first direction;
a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction;
a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and
a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit,
the method comprising:
forming the stacked structural unit including the insulating film alternately stacked with the electrode film on a major surface of a substrate;
forming the selection gate electrode on the stacked structural unit;
forming the insulating layer on the selection gate electrode;
making a first through-hole piercing at least the selection gate electrode and the insulating layer in the first direction perpendicular to the major surface and forming a first semiconductor film on an inner side face of the first through-hole;
forming the first core unit on an inner side of the first semiconductor film;
recessing the core unit; and
introducing an impurity into the first semiconductor film.

US Pat. No. 10,658,382

ELEVATIONALLY-EXTENDING STRING OF MEMORY CELLS INDIVIDUALLY COMPRISING A PROGRAMMABLE CHARGE STORAGE TRANSISTOR AND METHOD OF FORMING AN ELEVATIONALLY-EXTENDING STRING OF MEMORY CELLS INDIVIDUALLY COMPRISING A PROGRAMMABLE CHARGE STORAGE TRANSISTOR

Micron Technology, Inc., ...

1. A method of forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:forming an upper stack elevationally over a lower stack, the upper and lower stacks individually comprising vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material, the upper stack comprising an upper stack channel pillar extending through multiple of the vertically-alternating tiers in the upper stack, the lower stack comprising a lower stack channel pillar extending through multiple of the vertically-alternating tiers in the lower stack, a conductive interconnect comprising conductively-doped semiconductor material elevationally between and electrically coupling the upper and lower stack channel pillars together, the conductively-doped semiconductor material comprising conductivity-producing dopant therein;
thermally diffusing some of the conductivity-producing dopant elevationally out of the conductively-doped semiconductor material;
using an asymmetric diffusion barrier during the thermally diffusing to thermally diffuse more of said dopant upwardly into the upper stack channel pillar than diffusion of said dopant, if any, into the lower stack channel pillar; and
providing tunnel insulator, charge storage material, and control gate blocking insulator laterally between the respective upper and lower stack channel pillars and the control gate material.

US Pat. No. 10,658,381

MEMORY DIE HAVING WAFER WARPAGE REDUCTION THROUGH STRESS BALANCING EMPLOYING ROTATED THREE-DIMENSIONAL MEMORY ARRAYS AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A memory die comprising:a first plane including a plurality of first memory blocks; and
a second plane including a plurality of second memory blocks,
wherein:
each memory block respectively selected from the plurality of first memory blocks and the plurality of second memory blocks includes a respective set of memory stack structures that vertically extend through a respective alternating stack of insulating layers and electrically conductive layers, wherein each memory stack structure within the sets of memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;
each of the first plane includes a respective set of first bit lines that laterally extend along a first horizontal direction and electrically connected to a respective subset of vertical semiconductor channels; and
each of the second plane includes a respective set of second bit lines that are parallel with respect to one another and laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction and electrically connected to a respective subset of vertical semiconductor channels within the second plane.

US Pat. No. 10,658,380

FORMATION OF TERMINATION STRUCTURES IN STACKED MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a stacked memory array, comprising:forming a stack of alternating first and second dielectrics;
forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor;
forming a set of contacts concurrently with forming the termination structure;
forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure;
forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures and through the third dielectric over an upper surface of the termination structure so that the first opening exposes an upper surface of the conductor; and
removing the conductor from the termination structure to form a second opening lined with the dielectric liner.

US Pat. No. 10,658,379

ARRAY COMMON SOURCE STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming an alternating conductive/dielectric stack on a substrate;
forming a slit vertically penetrating the alternating conductive/dielectric stack;
forming an isolation layer on a sidewall of the slit;
forming a first conductive layer covering the isolation layer;
performing a plasma treatment followed by a first doping process to the first conductive layer;
forming a second conductive layer covering the first conductive layer and filling the slit;
performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer;
removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and
forming a third conductive layer in the recess.

US Pat. No. 10,658,378

THROUGH ARRAY CONTACT (TAC) FOR THREE-DIMENSIONAL MEMORY DEVICES

Yangtze Memory Technologi...

9. A method for forming a 3D memory device, the method comprising:forming an isolation structure on a substrate;
disposing an alternating dielectric layer stack on the substrate, the alternating dielectric layer stack comprising pairs of a first dielectric layer and a second dielectric layer different from the first dielectric layer;
disposing a staircase structure in the alternating dielectric layer stack, wherein the staircase structure comprises levels with each level having a conductor layer thereon;
forming a channel structure extending vertically in the alternating dielectric layer stack;
disposing a word line contact on the conductor layer of the each level of the staircase structure;
forming one or more slit structures extending vertically in the alternating dielectric layer stack;
forming an opening in the alternating dielectric layer stack, wherein the opening exposes the isolation structure;
filling the opening with a dielectric layer to form a dielectric structure as a through array contact (TAC) region of the 3D memory device;
removing portions of the dielectric structure and the isolation structure until the substrate is exposed to form a TAC opening that vertically extends through the dielectric structure and the isolation structure;
filling the TAC opening with a conductor to form a TAC structure in the TAC region, wherein the TAC structure is in contact with the substrate; and
disposing a local contact on the channel structure, the one or more slit structures, and the TAC structure.

US Pat. No. 10,658,377

THREE-DIMENSIONAL MEMORY DEVICE WITH REDUCED ETCH DAMAGE TO MEMORY FILMS AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A monolithic three-dimensional memory device, comprising:a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
an insulating cap layer overlying the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers overlying the insulating cap layer;
a memory opening extending through the second alternating stack, the insulating cap layer, and the first alternating stack; and
a memory stack structure located within the memory opening and comprising a semiconductor channel, a first memory film laterally surrounding the semiconductor channel and embedded within the first alternating stack, and a second memory film laterally surrounding semiconductor channel and embedded within the second alternating stack,
wherein the second memory film is not in direct contact with the first memory film;
wherein the semiconductor channel continuously vertically extends at least from a level of a second bottommost electrically conductive layer within the first alternating stack to a level of a topmost electrically conductive layer within the second alternating stack;
wherein a horizontal surface of the semiconductor channel directly contacts a bottommost second insulating layer of the second insulating layers within the second alternating stack;
wherein the horizontal surface of the semiconductor channel is coplanar with a top surface of the insulating cap layer;
wherein the semiconductor channel comprises:
a first vertically-extending portion located within the first alternating stack;
a second vertically-extending portion located within the second alternating stack; and
a ledge portion connecting the first vertically-extending portion and the second vertically-extending portion, located within the insulating cap layer, and including the horizontal surface of the semiconductor channel that contacts the bottommost second insulating layer of the second insulating layers within the second alternating stack; and
wherein the ledge portion comprises:
a cylindrical sidewall of the semiconductor channel that contacts a sidewall of the insulating cap layer;
a convex surface that adjoins a bottom end of the cylindrical sidewall and having a periphery that adjoins an outer sidewall of the first memory film; and
a cylindrical contact surface that adjoins the convex surface and contacting the outer sidewall of the first memory film.

US Pat. No. 10,658,376

SEMICONDUCTOR DEVICE INCLUDING A BLOCKING LAYER HAVING A VARYING THICKNESS

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a substrate;
a stacked body including a plurality of first conductive layers and a plurality of first insulating layers and being provided on the substrate, the first conductive layers and the first insulating layers being provided alternately along a first direction; and
a columnar portion extending through the stacked body in the first direction, the columnar portion including
a blocking layer provided on the plurality of first conductive layers and on the plurality of first insulating layers in a second direction crossing the first direction,
a charge storage layer provided on the blocking layer in the second direction,
a tunneling layer provided on the charge storage layer in the second direction, and
a semiconductor layer provided on the tunneling layer in the second direction,
the columnar portion including a first portion and a second portion, the second portion being provided on the substrate side of the first portion,
a width in the second direction of the second portion being smaller than a width in the second direction of the first portion,
a portion of the blocking layer provided at the second portion being thicker than a portion of the blocking layer provided at the first portion.

US Pat. No. 10,658,375

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A method of fabricating a three-dimensional semiconductor memory device, comprising:forming a peripheral circuit device and a peripheral interconnection structure on a substrate;
forming a lower mold insulating layer to cover the peripheral circuit device and the peripheral interconnection structure;
forming a horizontal active layer on the lower mold insulating layer, the horizontal active layer comprising first, second, and third active semiconductor layers sequentially stacked on the lower mold insulating layer;
forming a cell array structure on the horizontal active layer;
forming a pick-up region in the horizontal active layer and around the cell array structure, wherein the pick-up region is formed to have the first conductivity type; and
forming a pick-up diffusion barrier region in the third active semiconductor layer to surround at least a portion of a side surface of the pick-up region, wherein the pick-up diffusion barrier region comprises carbon,
wherein the first active semiconductor layer is doped with impurities to have a first conductivity type and a first concentration, the second active semiconductor layer comprises an impurity diffusion restraining material inhibiting diffusion of the impurities in the first active semiconductor layer into the second active semiconductor layer, and the third active semiconductor layer is doped with impurities to have the first conductivity type and a second concentration different from the first concentration, or is in an undoped state.

US Pat. No. 10,658,374

VERTICAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a vertical semiconductor device, the method comprising:forming a plurality of conductive layer patterns spaced apart from each other by a plurality of interlayer insulating layer patterns in a vertical direction on a substrate,
wherein, a first conductive layer pattern of the conductive layer patterns extends from one sidewall of adjacent interlayer insulating layer patterns and comprises a pad region, wherein the pad region includes a raised pad portion protruding from a surface of the first conductive layer pattern and one end of the raised pad portion is rounded; and
forming a contact plug to be in contact with the raised pad portion of the first conductive layer pattern.

US Pat. No. 10,658,373

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH METAL GATE MEMORY DEVICE AND METAL GATE LOGIC DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:forming a split gate stack having a charge trapping layer, a main gate, and a select gate over a semiconductor substrate, wherein forming the split gate stack is performed such that the charge trapping layer has a first portion interposed between the main gate and a top surface of the semiconductor substrate;
forming a logic gate stack having a logic gate over the semiconductor substrate; and
replacing the main gate and the logic gate respectively with a metal memory gate and a metal logic gate, wherein the main gate and the logic gate are replaced simultaneously.

US Pat. No. 10,658,372

CUTTING METAL GATES IN FIN FIELD EFFECT TRANSISTORS

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first region of a semiconductor substrate including a first metal gate structure disposed over a first plurality of fins and a first gate isolation structure in direct contact with the first metal gate structure; and
a second region of the semiconductor substrate including a second metal gate structure disposed over a second plurality of fins and a second gate isolation structure in direct contact with the second metal gate structure,
wherein the first metal gate structure includes one or more work-function metal layers and a conductive layer, wherein the second metal gate structure includes one or more work-function metal layers but does not include a conductive layer, and wherein sidewalls of the first gate isolation structure are in direct contact with the conductive layer.

US Pat. No. 10,658,371

METHOD FOR PRODUCING A PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE

UNISANTIS ELECTRONICS SIN...

1. A method for producing a pillar-shaped semiconductor device, the method comprising:forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate such that the pillars stand in a direction perpendicular to a surface of the substrate, the third semiconductor pillar having a first interlayer insulating layer in a middle part in the perpendicular direction;
forming a gate insulating layer such that the gate insulating layer surrounds each of the first semiconductor pillar, the second semiconductor pillar, and the third semiconductor pillar;
forming a gate conductor layer such that the gate conductor layer surrounds each of the gate insulating layers surrounding the first semiconductor pillar, the second semiconductor pillar, and the third semiconductor pillar;
forming, in the first semiconductor pillar, a first impurity region and a second impurity region separately from each other in the perpendicular direction, both the first impurity region and the second impurity region at the height below the first interlayer insulating layer in the third semiconductor pillar, forming, in the second semiconductor pillar, a third impurity region and a fourth impurity region separately from each other in the perpendicular direction, both the third impurity region and the fourth impurity region at the height below the first interlayer insulating layer in the third semiconductor pillar, and forming, in the third semiconductor pillar, a fifth impurity region and a sixth impurity region separately from each other in the perpendicular direction, both the third impurity region and the fourth impurity region at the height below the first interlayer insulating layer in the third semiconductor pillar;
forming, in the first semiconductor pillar, a seventh impurity region and an eighth impurity region separately from each other in the perpendicular direction, both the seventh impurity region and the eighth impurity region at the height above the first interlayer insulating layer in the third semiconductor, forming, in the second semiconductor pillar, a ninth impurity region and a tenth impurity region separately from each other in the perpendicular direction, both the ninth impurity region and the tenth impurity region at the height above the first interlayer insulating layer in the third semiconductor pillar, and forming, in the third semiconductor pillar, an eleventh impurity region and a twelfth impurity region separately from each other in the perpendicular direction, both the eleventh impurity region and the twelfth impurity region at the height above the first interlayer insulating layer in the third semiconductor pillar;
processing the gate conductor layer around the first semiconductor pillar with a portion between the first impurity region and the second impurity region and a portion between the seventh impurity region and the eighth impurity region in the perpendicular direction left unprocessed to respectively form a first gate conductor layer and a second gate conductor layer, processing the gate conductor layer around the second semiconductor pillar with a portion between the third impurity region and the fourth impurity region and a portion between the ninth impurity region and the tenth impurity region in the perpendicular direction left unprocessed to respectively form a third gate conductor layer and a fourth gate conductor layer, and processing the gate conductor layer around the third semiconductor pillar with a portion between the fifth impurity region and the sixth impurity region and a portion between the eleventh impurity region and the twelfth impurity region in the perpendicular direction left unprocessed to respectively form a fifth gate conductor layer and a sixth gate conductor layer;
connecting the first gate conductor layer, the third gate conductor layer, the seventh impurity region, the ninth impurity region, and the eleventh impurity region to one another, the impurity regions being at the same height in the perpendicular direction;
connecting the second gate conductor layer, the fourth gate conductor layer, the second impurity region, the fourth impurity region, and the sixth impurity region to one another, the impurity regions being at the same height in the perpendicular direction; and
connecting the fifth gate conductor layer and the sixth gate conductor layer to each other.

US Pat. No. 10,658,370

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate having a first semiconductor fin and a second semiconductor fin, wherein the first semiconductor fin has a first sidewall farthest from the second semiconductor fin and a second sidewall closest to the second semiconductor fin, and the second semiconductor fin has a third sidewall closest to the first semiconductor fin;
a shallow trench isolation (STI) structure around a lower part of the first semiconductor fin and a lower part of the second semiconductor fin;
a fin spacer having a first portion laterally extending along a top surface of the STI structure, a second portion extending upwardly from the first portion of the fin spacer along the second sidewall of the first semiconductor fin, and a third portion expending upwardly from the first portion along the third sidewall of the second semiconductor fin; and
an epitaxy structure over the first semiconductor fin and the second portion of the fin spacer, the epitaxy structure having an asymmetrical cross-section that extends differently beyond the first sidewall and second sidewall of the first semiconductor fin, respectively.

US Pat. No. 10,658,369

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having a memory region and a periphery region;
a first isolation structure in the substrate on the memory region, wherein the first isolation comprises:
a first liner in the substrate; and
a second liner on the first liner;
a second isolation structure adjacent to the first isolation structure, wherein a width of the second isolation structure is greater than a width of the first isolation structure, the second isolation structure comprises:
the first liner in the substrate;
the second liner on the first liner; and
a third liner on the second liner of the second isolation structure and not on the second liner of the first isolation structure.

US Pat. No. 10,658,368

DYNAMIC RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A dynamic random access memory (DRAM), comprising:a first bit line extending along a first direction;
a first buried word line extending along a second direction; and
an active region overlapping part of the first bit line and part of the first buried word line, wherein the active region comprises a V-shape, wherein the V-shape comprises:
a first portion extending along the first direction, wherein the first portion comprises a first side and a second side extending along the first direction and the first portion overlaps the first bit line without overlapping any of the first buried word line;
a second portion extending along a third direction; and
a third portion extending along a fourth direction.

US Pat. No. 10,658,367

INTEGRATED ASSEMBLIES WHICH INCLUDE METAL-CONTAINING INTERCONNECTS TO ACTIVE-REGION PILLARS, AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...

1. A method of forming an integrated assembly, comprising:providing a construction having active-region-pillars; each of the active-region-pillars having a pair of storage-element-contact-regions, and having a digit-line-contact-region between the storage-element-contact-regions of said pair; the active-region-pillars comprising semiconductor material; the construction including wordlines adjacent the active-region-pillars and extending along a first direction;
forming a patterned mold over the construction; the patterned mold having openings extending therethrough; the openings being aligned with the digit-line-contact-regions;
extending the openings into the semiconductor material of the digit-line-contact-regions;
forming carbon-containing-polymer within the extended openings;
forming trenches within the patterned mold, the trenches extending along a second direction and passing over the digit-line-contact-regions; the second direction crossing the first direction;
removing the carbon-containing-polymer from over the digit-line-contact-regions to reopen the openings; the reopened openings being at the bottoms of the trenches and extending into the semiconductor material of the digit-line-contact-regions; surfaces of the digit-line-contact-regions being exposed within the reopened openings;
forming digit-line-material within the trenches and electrically coupled with the digit-line-contact-regions; the digit-line-material being configured as digit-lines extending along the second direction; and
forming storage-elements electrically coupled with the storage-element-contact-regions of said pair.

US Pat. No. 10,658,366

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:providing a material layer having a contact pad therein;
forming a dielectric layer on the material layer and the contact pad;
forming a doped oxide layer on the dielectric layer;
forming an oxide layer on the doped oxide layer;
performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole;
performing a second etching process to remove part of the doped oxide layer to form a second contact hole after removing part of the dielectric layer and exposing the contact pad; and
forming a conductive layer in the second contact hole to form a contact plug.

US Pat. No. 10,658,365

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate, wherein at least one cell region is defined in said substrate, said cell region is provided with multiple storage nodes, and multiple word lines is provided in said substrate, each of said word lines comprises a capping layer;
mesh-type isolation structure on said cell region and defining multiple openings, wherein said mesh-type isolation structure extends downwardly into said capping layer of said word lines; and
multiple storage node contact plugs respectively in said openings and electrically connecting with said storage nodes.

US Pat. No. 10,658,364

METHOD FOR CONVERTING A FLOATING GATE NON-VOLATILE MEMORY CELL TO A READ-ONLY MEMORY CELL AND CIRCUIT STRUCTURE THEREOF

STMICROELECTRONICS S.R.L....

1. A method of making a ROM cell comprising:forming an EEPROM cell having a floating gate, a control gate, a first well and a selection gate;
forming a metal line overlying the EEPROM cell; and
converting the EEPROM cell to ROM cell by forming a contact between the metal line and the floating gate, wherein the contact connects the floating gate to the selection gate.

US Pat. No. 10,658,363

CUT INSIDE REPLACEMENT METAL GATE TRENCH TO MITIGATE N-P PROXIMITY EFFECT

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a common dielectric material over a first device area and a second device area;
cutting the common dielectric material within a gate trench between the first device area and the second device area to separate the common dielectric material into a first dielectric material over the first device area and a second dielectric material over the second device area;
forming a workfunction metal over the first dielectric material in the first device area; and
forming a common electrode over the workfunction metal of the first device area and the second dielectric material over the second device area to form a first device in the first device area and a second device in the second device area, respectively.

US Pat. No. 10,658,362

SEMICONDUCTOR COMPONENT AND FABRICATING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor component, the method comprising:forming a first epitaxial layer cladding a first fin;
forming a second epitaxial layer cladding a second fin;
removing portions of the first epitaxial layer, the first fin, the second epitaxial layer, and the second fin;
forming a germanium-containing oxide layer on the second fin and on the second epitaxial layer; and
forming an epitaxial contact portion on the first fin and the first epitaxial layer.

US Pat. No. 10,658,361

METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS

Intel Corporation, Santa...

1. A device comprising:a substrate having a plurality of semiconductor fins;
a first transistor having a first gate structure that wraps around a first semiconductor fin, wherein the first gate structure comprises a first gate dielectric structure in direct contact with the first semiconductor fin and a first gate electrode structure comprising a first metal layer, the first metal layer in direct contact with the first gate dielectric structure, wherein the first gate dielectric structure comprises a first gate dielectric layer and a second gate dielectric layer on the first gate dielectric layer, the first transistor having a first pair of n type doped source/drain regions on opposite sides of the first gate structure; and
a second transistor isolated from the first transistor, the second transistor having a second gate structure that wraps around a second semiconductor fin wherein the second gate structure comprises a second gate dielectric structure in direct contact with the second semiconductor fin and a second gate electrode structure comprising a second metal layer, the second metal layer in direct contact with the second gate dielectric structure, the second transistor having a second pair of n type doped source/drain regions on opposite sides of the second gate structure, wherein the second gate dielectric structure comprises the second gate dielectric layer but not the first gate dielectric layer, wherein the second gate dielectric structure is different in composition from the first gate dielectric structure, and wherein the second gate electrode structure is different in composition than the first gate electrode structure.

US Pat. No. 10,658,360

SEMICONDUCTOR DEVICE WITH AN INSULATED-GATE BIPOLAR TRANSISTOR REGION AND A DIODE REGION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor substrate having a drift layer of a first conductivity type;
an insulated-gate bipolar transistor region and a freewheeling diode region on the semiconductor substrate,
wherein the insulated-gate bipolar transistor region includes:
a base layer of a second conductivity type provided on a front surface side of the semiconductor substrate,
an emitter region of the first conductivity type selectively provided in the base layer,
a first insulated gate region including a first gate insulating film and a first gate electrode, provided on the front surface side of the semiconductor substrate,
an emitter electrode electrically connected to both the base layer and the emitter region,
a collector region of the second conductivity type selectively provided in a rear side of the semiconductor substrate, and
a collector electrode electrically connected to the collector region,
wherein the freewheeling diode region includes:
an anode layer of the second conductivity type provided on the front surface side of the semiconductor substrate, electrically connected to the emitter electrode,
a second insulated gate region including a first trench penetrating the anode layer and reaching the drift layer, a second gate insulating film provided along an inner wall of the first trench, and a second gate electrode provided in the first trench, via a second gate insulating film, and
a cathode region of the first conductivity type provided in the rear side of the semiconductor substrate, electrically connected to the collector electrode,
wherein a first width of the cathode region in a first direction in which the insulated-gate bipolar transistor region and the freewheeling diode region are arranged is narrower than a first width of the anode layer in the first direction, and a second width of the cathode region in a second direction orthogonal to the first direction is narrower than a second width of the anode layer in the second direction, the cathode region being a single continuous region in the first direction,
wherein a surface area of the insulated-gate bipolar transistor region is larger than a surface area of the freewheeling diode region, and
wherein a difference between the first width of the anode layer in the first direction and the first width of the cathode region in the first direction is 50 ?m or more.

US Pat. No. 10,658,359

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an n-type region and a p-type region that are disposed in a surface layer of a semiconductor substrate; and
a metal electrode in contact with both of the n-type region and the p-type region, wherein
the metal electrode includes
a first metal layer in contact with both of the n-type region and the p-type region, and
a second metal layer disposed on the first metal layer,
a contact surface between the first metal layer and the second metal layer has an oxygen concentration lower than an oxygen concentration of a contact surface between the first metal layer, and the n-type region and the p-type region,
the first metal layer is made of Al or an Al—Si alloy,
the oxygen concentration of the contact surface between the first metal layer and the n-type region and the p-type region is a value from 1/10 to 1/100 with respect to Al in the first layer, and
the oxygen concentration of the contact surface between the first metal layer and the second metal layer is 1/1000 or less with respect to Al in the first metal layer.

US Pat. No. 10,658,358

3D SEMICONDUCTOR WAFER, DEVICES, AND STRUCTURE

Monolithic 3D Inc., San ...

1. A 3D semiconductor device, the device comprising:a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a trap-rich layer disposed between said first level and said second level; and
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said plurality of connection paths comprises vertical connections connecting from said first interconnections to said second interconnections, and
wherein said vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.

US Pat. No. 10,658,357

DRIVER FOR DRIVING A CAPACITIVE LOAD

TEXAS INSTRUMENTS INCORPO...

1. A circuit, comprising:a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node;
a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node;
a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node;
a current source device connected in parallel with the capacitor in which the current source device is comprised of at least one of either a transistor or a Zener diode;
a control circuit coupled to receive a first control signal for the first base and, reciprocal to a logic state of the first control signal, to generate a second control signal for the second base; and
a programmable register set accessible to the control circuit, the programmable register set to be programmed with trim values, wherein the control circuit is to read the trim values from the register and trim a peak-to-peak voltage of the second control signal based on at least one of the trim values.

US Pat. No. 10,658,356

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a normally-off transistor having a first source, a first drain, and a first gate;
a normally-on transistor having a second source electrically connected to the first drain, a second drain, and a second gate;
a first capacitor having a first end and a second end, the second end electrically connected to the second gate;
a first diode having a first anode electrically connected between the second end and the second gate, and a first cathode;
a first resistor electrically connected between the first end and the first gate;
a second diode having a second anode electrically connected to the first end, and a second cathode electrically connected to the first gate, the second diode provided in parallel to the first resistor;
a gate drive circuit electrically connected to the first resistor and the second anode, a wiring being electrically connected to the gate drive circuit and the first source;
a second capacitor having a third end and a fourth end, the third end electrically connected to the wiring and the fourth end electrically connected to the second source; and
a second resistor electrically connected between the wiring and the third end.

US Pat. No. 10,658,355

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor integrated circuit device having an ESD (Electro Static Discharge) protection circuit, wherein:the ESD protection circuit comprises:
a first wiring electrically connected to a first terminal;
a second wiring and a third wiring electrically connected to a power supply terminal or a ground terminal;
a first region and a second region having a first conductivity type, that are connected to the first wiring, the first and second regions being separated from each other and serving as one of an anode or a cathode of a diode;
a third region having a second conductivity type different from the first conductivity type, that is connected to the second wiring and disposed so as to be opposed to the first region in a first direction;
a fourth region having the second conductivity type, that is connected to the third wiring and disposed so as to be opposed to the second region in the first direction, and the third and fourth regions serving as the other of an anode or a cathode of the diode; and
a fifth region having the second conductivity type,
the third region, the first region, the second region and the fourth region are disposed in this order in the first direction, and
the fifth region is disposed so as to be opposed to the first region in a second direction perpendicular to the first direction.

US Pat. No. 10,658,354

ELECTROSTATIC DISCHARGE HANDLING FOR LATERAL TRANSISTOR DEVICES

Semiconductor Components ...

1. A semiconductor transistor device, comprising:a source region;
a gate region having a p-type gate region and an n-type gate region;
a drain region having a p-type drain region and an n-type drain region;
a p-well formed at least partially under the gate region, and electrically shorted to the p-type gate region during an electrostatic discharge (ESD); and
an n-well formed under the source region, the gate region, the p-well, and the drain region, and electrically shorted to the n-type drain region during the ESD, wherein the p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to the ESD voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.

US Pat. No. 10,658,353

STACKED ELECTROSTATIC DISCHARGE DIODE STRUCTURES

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming a plurality of first well regions of a first conductivity type and a plurality of second well regions of a second conductivity type in a surface portion of a semiconductor substrate, wherein the second conductivity type is opposite from the first conductivity type;
forming a stack comprising a first doped semiconductor portion of the second conductivity type and a second doped semiconductor portion of the first conductivity type on each first well region of the plurality of first well regions, wherein adjacent stacks are electrically insulated from each other by a shallow trench (STI) layer;
forming a conductive strap structure on sidewalls of each of the stacks of the first doped semiconductor portion and the second doped semiconductor portion;
forming an interlevel dielectric (ILD) layer on the STI layer, the conductive strap structure and the second doped semiconductor portion;
forming an opening to expose at least a portion of the second doped semiconductor portion;
forming a third doped semiconductor portion on the exposed portion of the second doped semiconductor portion; and
forming a contact landing structure on the third doped semiconductor portion.

US Pat. No. 10,658,352

PROTECTIVE CIRCUIT, ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A protective circuit for a display panel, comprising:a control sub-circuit, having a first end electrically connected to a voltage input terminal and a second end configured to output a common voltage signal supplied by the voltage input terminal; and
a discharge sub-circuit, having a first end electrically connected to the second end of the control sub-circuit and multiple second ends each electrically connected to a data line;
wherein the discharge sub-circuit releases electric charges on the at least one data line under the control of the common voltage signal supplied from the control sub-circuit.

US Pat. No. 10,658,351

ELECTRONIC DEVICE INCLUDING A TRANSISTOR HAVING STRUCTURES WITH DIFFERENT CHARACTERISTICS

SEMICONDUCTOR COMPONENTS ...

1. An electronic device comprising:a first transistor having a first gate electrode, a first portion, and a second portion, wherein:
along the first gate electrode, the first portion of the first transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance,
along the first gate electrode, the second portion of the first transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance,
a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance, and
the first transistor comprises a first type of transistor structure, a second type of transistor structure, and a gate pad, wherein:
the first type of transistor structure has a longer channel region length or a shorter gate electrode length as compared to the second type of transistor structure,
the first transistor has a first section along a conduction path farther from the gate pad and a second section along the conduction path closer to the gate pad, and
a ratio of an area occupied by the first type of transistor structure to an area occupied by the second type of transistor structure within the first section is greater than a ratio of an area occupied by the first type of transistor structure to an area occupied by the second type of transistor structure within the second section.

US Pat. No. 10,658,350

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package, comprising:a substrate including an external terminal;
a first semiconductor chip on the substrate, the first semiconductor chip having a first region and a second region in a plan view;
at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and
at least one third semiconductor chip on the at least one second semiconductor chip,
wherein:
the first semiconductor chip includes:
a first pad electrically connected to the at least one second semiconductor chip;
a second pad electrically connected to the at least one third semiconductor chip; and
a third pad electrically connected to the external terminal,
the first pad is on the top surface of the first region, and
at least one of the second pad and the third pad is on a top surface of the second region.

US Pat. No. 10,658,349

INTERCONNECT USING EMBEDDED CARBON NANOFIBERS

Facebook Technologies, LL...

1. A device comprising:a first body comprising a first surface with nanoporous conductive structures protruding from the first surface; and
a second body comprising a second surface with an array of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

US Pat. No. 10,658,348

SEMICONDUCTOR DEVICES HAVING A PLURALITY OF FIRST AND SECOND CONDUCTIVE STRIPS

Taiwan Semiconductor Manu...

1. A semiconductor package comprising:a semiconductor device comprising a first under bump metallization (UBM) structure, wherein the first UBM structure comprises:
a plurality of first conductive strips, the first conductive strips extending in a first direction; and
a plurality of second conductive strips separated from and interleaved with the plurality of first conductive strips, the second conductive strips extending in the first direction, wherein the plurality of first conductive strips are offset in the first direction from the plurality of second conductive strips by a first offset distance; and
a substrate comprising a second UBM structure, the second UBM structure comprising a plurality of third conductive strips, each one of the plurality of third conductive strips configured to be bonded to one of the plurality of first conductive strips or one of the plurality of second conductive strips.

US Pat. No. 10,658,347

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A package comprising:a first package comprising:
a first die;
an encapsulant extending along sidewalls of the first die; and
a plurality of conductive columns extending through the encapsulant;
a second package bonded to the first package, the second package comprising a second die bonded to a first surface of a first substrate;
a first underfill between the first package and the second package, the first underfill having a first opening between the first die and the first substrate, a width of the first opening being less than a width of the second die, the width of the first opening being less than a width of the first die, at least a portion of a second surface of the first substrate being exposed in the first opening, the second surface of the first substrate being opposite the first surface of the first substrate; and
a plurality of first connectors extending through the first underfill, the plurality of first connectors electrically coupling the plurality of conductive columns to the first substrate.

US Pat. No. 10,658,346

MAKING SEMICONDUCTOR DEVICES BY STACKING STRATA OF MICRO LEDS

Hong Kong Beida Jade Bird...

1. A micro-LED display chip, comprising:a substrate supporting an array of pixel drivers; and
two or more strata stacked on top of the substrate and pixel drivers, with a planar interface between adjacent strata, each stratum containing an array of micro LEDs, wherein the arrays of micro LEDs for each stratum are electrically connected to the array of pixel drivers.

US Pat. No. 10,658,345

LED DISPLAY PANEL

PlayNitride Inc., Tainan...

1. A display panel, comprising:a substrate having a plurality of pixel units, each of the pixel units comprising a first sub-pixel region and a second sub-pixel region;
a plurality of first light emitting diodes disposed on the substrate and located in the first sub-pixel regions;
a plurality of second light emitting diodes disposed on the substrate and located in the second sub-pixel regions, wherein a dominant wavelength of each of the first light emitting diodes is different from a dominant wavelength of each of the second light emitting diodes;
a plurality of first common electrodes connected to the first light emitting diodes and forming an ohmic contact with the first light emitting diodes; and
a plurality of second common electrodes connected to the second light emitting diodes and forming an ohmic contact with the second light emitting diodes, wherein a material of the first common electrodes is different from a material of the second common electrodes.

US Pat. No. 10,658,344

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a substrate;
a metal layer on the substrate;
at least one semiconductor chip provided on the metal layer, the at least one semiconductor chip having an upper electrode and a lower electrode electrically connected to the metal layer;
a first wiring board provided on the substrate, the first wiring board being electrically connected to the upper electrode, the first wiring board including a first plate-shaped portion, a second plate-shaped portion, and a third plate-shaped portion, the first plate-shaped portion, the second plate-shaped portion, and the third plate-shaped portion being perpendicular to the substrate, the first plate-shaped portion being parallel to the second plate-shaped portion, the third plate-shaped portion being perpendicular to the first plate-shaped portion and the second plate-shaped portion, and the third plate-shaped portion being connected to one end of the first plate-shaped portion and one end of the second plate-shaped portion; and
a second wiring board provided on the substrate, the second wiring board being electrically connected to the metal layer, the second wiring board including a fifth plate-shaped portion, a sixth plate-shaped portion, and a seventh plate-shaped portion, the fifth plate-shaped portion, the sixth plate-shaped portion, and the seventh plate-shaped portion being perpendicular to the substrate, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, the seventh plate-shaped portion being perpendicular to the fifth plate-shaped portion and the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to one end of the fifth plate-shaped portion and one end of the sixth plate-shaped portion,
wherein the first plate-shaped portion and the second plate-shaped portion are provided between the fifth plate-shaped portion and the sixth plate-shaped portion, and
the at least one semiconductor chip is positioned between a plane including the fifth plate-shaped portion and a plane including the sixth plate-shaped portion.

US Pat. No. 10,658,343

SEMICONDUCTOR MODULE INCLUDING PRESSURE CONTACT ADJUSTMENT SCREWS

FUJI ELECTRIC CO., LTD., ...

1. A pressure contact-type semiconductor module, comprising:a plurality of semiconductor units disposed side-by-side, each of the semiconductor units including:
a semiconductor device substrate;
a first electrode formed below the semiconductor device substrate, the first electrode being electrically connected to the semiconductor device substrate;
a second electrode formed above the semiconductor device substrate, the second electrode being electrically connected to the semiconductor device substrate;
an electrode plate electrically connected to the second electrode; and
a pressure contact adjustment member screwed into the electrode plate, the pressure contact adjustment member having a top surface as a pressure contact-receiving surface to which a lead-out electrode plate that is common to the plurality of semiconductor units is pressure-contacted,
wherein the respective pressure contact adjustment members are screwed into the corresponding electrode plates such that levels of the respective top surfaces of the pressure contact adjustment members in the plurality of semiconductor units are adjustable to match a reference pressure contact plane so that contact pressures in the respective top surfaces applied by the lead-out electrode plate are substantially the same among the plurality of semiconductor units.

US Pat. No. 10,658,342

VERTICALLY STACKED MULTICHIP MODULES

SEMICONDUCTOR COMPONENTS ...

1. A method for producing a circuit assembly, the method comprising:coupling a first side of a first semiconductor die with a first metal layer disposed on a first side of a first insulating layer of a first substrate, the first semiconductor die being electrically coupled with the first metal layer;
coupling a first side of a second semiconductor die with a second metal layer disposed on a second side of the first insulating layer, the second side of the first insulating layer being opposite the first side of the first insulating layer, the first side of the second semiconductor die being electrically coupled with the second metal layer; and
coupling a second side of the first semiconductor die with a third metal layer disposed on a first side of a second insulating layer of a second substrate, the second side of the first semiconductor die being electrically coupled with the third metal layer, the second side of the first semiconductor die being opposite the first side of the first semiconductor die,
the first substrate including a conductive via disposed through the first insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer,
the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die, and
the second substrate including a fourth metal layer disposed on a second side of the second insulating layer, the second side of the second insulating layer being opposite the first side of the second insulating layer, the fourth metal layer being electrically isolated from the third metal layer by the second insulating layer.

US Pat. No. 10,658,341

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package comprising:a first semiconductor chip including a first through-electrode;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer; and
a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer,
wherein the first pillar structure comprises a first layer, a second layer, and a third layer, and the second pillar structure comprises a pillar layer and does not comprise a layer corresponding to the third layer,
the first layer, the second layer and the third layer are sequentially stacked on the bottom surface of the first semiconductor chip, and
the first layer comprises a material having a Young's modulus that is lower than a Young's modulus of the pillar layer.

US Pat. No. 10,658,340

SIGNAL ROUTING IN COMPLEX QUANTUM SYSTEMS

International Business Ma...

1. A method comprising:forming a plurality of quantum circuits arranged in a two-dimensional layout, wherein the plurality of quantum circuits comprises at least one interior quantum circuit that is not along a perimeter of the two-dimensional layout, the at least one interior quantum circuit comprises a plurality of layers, wherein a top layer of the plurality of layers comprises a through hole to a bottom layer of the plurality of layers; and
forming a signal wire at least partially within the through hole to connect the bottom layer to the top layer.

US Pat. No. 10,658,339

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a first redistribution layer (RDL) having a first portion and a second portion electrically isolated from the first portion of the first RDL;
a first device coupled to a first side of the first RDL;
a second device coupled to the first RDL, the second device having first terminals electrically coupled to the first pad of the first RDL, wherein the second device is defective, wherein the second device is decoupled from the first device by the electrical isolation of the first pad from the second pad; and
a semiconductor package electrically coupled to the first RDL.

US Pat. No. 10,658,338

SEMICONDUCTOR DEVICE INCLUDING A RE-INTERCONNECTION LAYER AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a re-interconnection layer;
a plurality of bumps provided on a first surface of the re-interconnection layer;
a plurality of chips stacked on a second surface of the re-interconnection layer; and
a resin member provided on the second surface, the resin member covering the chips,
the re-interconnection layer including
an insulating layer,
an interconnection provided in the insulating layer,
a first via provided in the insulating layer and connected to the interconnection,
an electrode layer provided in the insulating layer, being formed of a metal material different from a material of the first via, and being connected to the first via and the bumps, and
a second via provided in the insulating layer, the second via being connected to the interconnection and the chips,
a distance between a surface on a side of the first via of the electrode layer and the second surface being shorter than a distance between the first surface and the second surface,
a width of the first via becoming narrower from the second surface toward the first surface.

US Pat. No. 10,658,337

PACKAGES AND PACKAGING METHODS FOR SEMICONDUCTOR DEVICES, AND PACKAGED SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method of packaging a semiconductor device, the method comprising:disposing a molding compound around a plurality of integrated circuit dies;
forming a plurality of through-vias in the molding compound;
forming a first interconnect structure over a first side of the plurality of through-vias and the molding compound, the first interconnect structure comprising a metallization layer, the metallization layer comprising a plurality of conductive lines, a plurality of contact pads, and a plurality of fuses wherein the plurality of fuses lie within respective projections of outer peripheries of respective ones of the plurality of integrated circuit dies; and
forming a second interconnect structure over a second side of the plurality of through-vias and the molding compound, the second side being opposite the first side.

US Pat. No. 10,658,336

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology Inc., ...

1. A method of manufacturing a semiconductor die assembly, the method comprising:attaching a first semiconductor die to a package substrate including a plurality of bond pads arranged in a first array along a first axis and a plurality of bond pads arranged in a second array along a second axis that is transverse to the first axis;
positioning a support member on the package substrate that is spaced apart from the first semiconductor die on the package substrate; and
attaching a second semiconductor die to both the support member and the first semiconductor die such that the support member supports the second semiconductor die along a first edge of the second semiconductor die and the first semiconductor die is partially superimposed within a footprint of the second semiconductor die, wherein a first edge and a second edge of the first semiconductor die are entirely outside of the footprint, and the first edge is perpendicular to the second edge.

US Pat. No. 10,658,335

HETEROGENOUS 3D CHIP STACK FOR A MOBILE PROCESSOR

Futurewei Technologies, I...

1. An integrated circuit (IC) package, comprising:a first die, including digital base band logic and a first metal layer, formed on a first wafer utilizing a first node size;
a second die, including analog base band logic and a second metal layer, formed on a second wafer utilizing a second node size, wherein the first die is mounted on a top surface of the second die using a hybrid bonding technique;
a shielding formed by the second metal layer to reduce interference from signals in the first die, wherein the analog base band logic is positioned in the second die below the second metal layer which is disposed below the first die; and
a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die.

US Pat. No. 10,658,334

METHOD FOR FORMING A PACKAGE STRUCTURE INCLUDING A PACKAGE LAYER SURROUNDING FIRST CONNECTORS BESIDE AN INTEGRATED CIRCUIT DIE AND SECOND CONNECTORS BELOW THE INTEGRATED CIRCUIT DIE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a package structure, comprising:forming a base layer over a carrier substrate through an adhesive layer;
forming a redistribution structure over the base layer, wherein the redistribution structure comprises conductive layers embedded in passivation layers;
disposing a first integrated circuit die over the redistribution structure;
forming a package layer surrounding the first integrated circuit die, wherein the package layer and the first integrated circuit die are on the same level, and the package layer has a first filler dispersed therein;
attaching the package layer to a carrier;
removing the carrier substrate and the adhesive layer to expose the base layer after attaching the package layer to the carrier;
forming first openings and second openings in the base layer to expose the conductive layers of the redistribution structure, wherein the first openings are wider than the second openings;
forming first bumps in the first openings of the base layer over the redistribution structure so that the first bumps are in direct contact with the conductive layers of the redistribution structure;
bonding a second integrated circuit die to the redistribution structure through second bumps, wherein the second bumps are formed in the second openings of the base layer so that the second bumps are in direct contact with the conductive layers of the redistribution structure, and a shortest distance between the first bumps on a first side of the second integrated circuit die is greater than a shortest distance between the second bumps; and
filling a molding compound layer in a space between the first bumps and the second bumps to form a molding compound layer over the base layer such that bottom portions of the first bumps and bottom portions of the second bumps are separated by the base layer and upper portions of the first bumps and upper portions of the second bumps are separated by the molding compound layer, wherein the molding compound layer has a second filler in the space, and a size of the second filler is less than that of the first filler.

US Pat. No. 10,658,333

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:at least one first semiconductor die having a semiconductor substrate and a conductive post disposed on the semiconductor substrate;
an insulating encapsulant partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant;
an isolation layer disposed on the insulating encapsulant and surrounding the second portion of the conductive post; and
a redistribution layer disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

US Pat. No. 10,658,332

STACK PACKAGES INCLUDING BRIDGE DIES

SK hynix Inc., Icheon-si...

1. A stack package comprising:a first sub-package comprising a first semiconductor die, a first bridge die spaced apart from the first semiconductor die, a first inner molding layer covering the first semiconductor die and the first bridge die, and a first redistribution structure electrically connecting the first semiconductor die to the first bridge die;
a second sub-package stacked on the first sub-package;
an inner connector electrically connecting the first bridge die to the second sub-package; and
a plurality of dummy balls disposed between the first and second sub-packages to support the second sub-package,
wherein the first bridge die comprises a first body, a first through via penetrating the first body, and a first post bump connected to a first end of the first through via and protruding from a top surface of the first body,
wherein the first inner molding layer surrounds a side surface of the first post bump and reveals a top surface of the first post bump, and
wherein the first redistribution structure electrically connects the first semiconductor die to a second end of the first through via.

US Pat. No. 10,658,330

SEMICONDUCTOR DEVICE AND METHOD OF USING A STANDARDIZED CARRIER TO FORM EMBEDDED WAFER LEVEL CHIP SCALE PACKAGES

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first semiconductor wafer including a first number of semiconductor die;
providing a second semiconductor wafer including a plurality of semiconductor die;
singulating the semiconductor die from the first semiconductor wafer and second semiconductor wafer;
providing a standardized carrier;
disposing the first number of semiconductor die over the standardized carrier;
disposing a portion of the plurality of semiconductor die over the standardized carrier;
depositing an encapsulant over the semiconductor die and standardized carrier; and
singulating through the encapsulant to form a semiconductor package, wherein singulating through the encapsulant includes removing a portion of the semiconductor die.

US Pat. No. 10,658,329

METHOD OF DETERMINING CURING CONDITIONS, METHOD OF PRODUCING CIRCUIT DEVICE AND CIRCUIT DEVICE

SONY CORPORATION, Tokyo ...

1. A method of determining curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component, the method comprising:creating a curing degree curve which indicates, with respect to each of plural heating temperatures, a relationship between heating time and curing degree of the thermosetting resin using equations 1 and 2:

where ? is a curing degree,
m, n, C1, C2, A, and E are resin coefficients,
T is a temperature of the resin, heating temperature (function of time, T=f2(t)),
T is a heating time,
k1 and k2 are reaction speed constants,
A1 and A2 are frequency factors,
E1 and E2 are activation energies;
calculating a viscosity of the thermosetting resin using a Macosko equation;
calculating, on the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin at a first heating temperature which is one of the heating temperatures using equations 4 and 5:

where, in Equation 4, m is a mass of void, v is an ascent rate of the void, g is acceleration of gravity, r is a radius of the void, and ? is a density of the void, and, in Equation 5, Pv is a vapor pressure inside the void, PL is a liquid pressure around the void to be exerted on the void, and ? is a surface tension of resin; and
determining a time based on the calculated void removal time, as a heating time at the first heating temperature, the time being a time at an intersection of the during degree curve and a curve indicating the void's ascending position.

US Pat. No. 10,658,328

DETECTION OF FOREIGN PARTICLES DURING WIRE BONDING

ASM TECHNOLOGY SINGAPORE ...

1. A method of bonding wires onto surfaces, comprising the steps of:collecting operating characteristics of a bonding tool while forming a wire bond which bonds a wire to a surface;
determining whether a possible/likely/potential/suspect/suspected bonding failure of said wire bond has occurred as indicated by said operating characteristics; and
capturing an image of said wire bond to identify whether the wire bond has been bonded onto a foreign particle that is present on said surface if it is determined that a possible bonding failure has occurred.

US Pat. No. 10,658,327

CHIP BONDING APPARATUS AND BONDING METHOD

SHANGHAI MICRO ELECTRONIC...

1. A chip bonding apparatus, comprising:a chip supply unit configured to provide a chip to be bonded;
a substrate supply unit configured to provide a substrate, the substrate supply unit being disposed opposite to the chip supply unit;
a first pickup assembly disposed between the chip supply unit and the substrate supply unit and comprising a first rotating part and a first pickup head disposed on the first rotating part;
a second pickup assembly disposed between the chip supply unit and the substrate supply unit and comprising a second rotating part and a second pickup head disposed on the second rotating part, wherein the first pickup assembly is configured to pick up the chip from the chip supply unit or from the second pickup assembly and convey the chip to the substrate on the substrate supply unit to accomplish bonding; and
a vision unit configured to align the chip on the first pickup assembly with the substrate, wherein the chip supply unit, the substrate supply unit, the second pickup assembly and the vision unit are respectively located at four work positions of the first pickup head.

US Pat. No. 10,658,326

BONDING WIRE HAVING A SILVER ALLOY CORE, WIRE BONDING METHOD USING THE BONDING WIRE, AND ELECTRICAL CONNECTION PART OF SEMICONDUCTOR DEVICE USING THE BONDING WIRE

SAMSUNG ELECTRONICS CO., ...

1. A bonding wire comprising:a wire core including a silver-palladium alloy comprising silver and palladium; and
a coating layer disposed on a sidewall of the wire core,
wherein a palladium content of the silver-palladium alloy ranges from 0.1 wt % to 1.5 wt %,
wherein the bonding wire further comprises a free air ball formed on one end thereof, and
wherein the free air ball has an eccentricity, defined as a difference between a length of a long axis thereof and a length of a short axis thereof divided by the length of the short axis thereof, that is less than 0.25 and greater than 0.

US Pat. No. 10,658,325

SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS

SEIKO EPSON CORPORATION, ...

1. A semiconductor chip, comprising:a pad;
lower wiring, first and second portions of the lower wiring having different widths and being connected together at a junction;
conductive material between the junction and the pad;
a diffusion layer;
a first contact part for contacting the diffusion layer and the lower wiring;
upper wiring disposed above the lower wiring; and
a second contact part for contacting the lower wiring and the upper wiring,
wherein the pad is above the junction, the diffusion layer is below the lower wiring, and the conductive material overlaps the pad, the junction, the first contact part, and the diffusion layer in a plan view from above the pad.

US Pat. No. 10,658,324

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an insulating substrate;
an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate;
a plating formed on a surface of the aluminum pattern; and
a semiconductor element joined to the plating,
wherein a thickness of the plating is 10 ?m or more,
the plating includes first and second platings arranged side by side,
the semiconductor element includes first and second semiconductor elements joined to the first and second platings respectively,
the first semiconductor element is thinner than the second semiconductor element,
the first plating is thicker than the second plating, and
each of the first and second platings has a same material throughout an entire thickness thereof in a direction from the aluminum pattern toward the semiconductor element.

US Pat. No. 10,658,323

PACKAGE STRUCTURE WITH WARPAGE-CONTROL ELEMENT

Taiwan Semiconductor Manu...

1. A package structure, comprising:a semiconductor die;
a protective layer surrounding the semiconductor die; and
a conductive structure and a warpage-control element over a same side of the protective layer, wherein a bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure, the bottom surface of the warpage-control element is lower than a top surface of the conductive structure, and the bottom surface of the conductive structure is over a top surface of the protective layer.

US Pat. No. 10,658,322

HIGH BANDWIDTH MEMORY PACKAGE FOR HIGH PERFORMANCE PROCESSORS

Google LLC, Mountain Vie...

1. A method of assembling an integrated component package, the method comprising:directly mechanically coupling a high-bandwidth memory component to a bump pitch relaxing layer via a first set of bump bond connections;
directly electrically coupling the high-bandwidth memory component to the bump pitch relaxing layer via the first set of bump bond connections;
directly mechanically coupling the bump pitch relaxing layer to a first side of a substrate via a second set of bump bond connections;
electrically coupling the high-bandwidth memory component to the substrate via the bump pitch relaxing layer and the second set of bump bond connections, wherein the a bump pitch of the bump bond connections in the second set of bump bond connections is larger than a bump pitch of the bump bond connections in the first set of bump bond connections;
directly coupling a processor to the substrate via a third set of bump bond connections;
coupling one or more high-speed input/output (I/O) traces to the bump pitch relaxing layer and the third set of bump bond connections; and
electrically coupling the high-bandwidth memory component to the processor via the bump pitch relaxing layer.

US Pat. No. 10,658,321

SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor chip, comprising:a semiconductor substrate;
a first interconnect layer provided on the semiconductor substrate;
a pad provided on a side surface of the first interconnect layer; and
a solder layer contacting a side surface of the pad and protruding further sideward than a side surface of the semiconductor substrate and a side surface of the first interconnect layer, the solder layer being disposed above an upper surface of the semiconductor substrate
wherein,
the semiconductor substrate includes a protruding portion, the protruding portion protruding further sideward than the side surface of the first interconnect layer and being located under the solder layer,
the pad includes a lower portion disposed on the protruding portion of the semiconductor substrate, and
the solder layer is separated from the lower portion of the pad.

US Pat. No. 10,658,320

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE STRUCTURE

Winbond Electronics Corp....

1. A semiconductor device, comprising:a first pad and a second pad;
a first conductive connector and a second conductive connector, disposed over the first pad and the second pad;
a first conductive structure, electrically connecting the first pad and the first conductive connector, comprising a first conductive portion, a second conductive portion on the first conductive portion, and a connecting portion connecting the first conductive portion and the second conductive portion, wherein the first conductive portion and the second conductive portion are not overlapped in a vertical direction, and the first conductive portion, the connecting portion, and the second conductive portion are integrally formed;
a second conductive structure, electrically connecting the second pad and the second conductive connector, wherein in the vertical direction, a portion of the second conductive structure overlaps with the first conductive structure therebeneath.

US Pat. No. 10,658,319

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

11. A substrate, comprising:a trace disposed adjacent to a surface of the substrate and including a bonding pad, wherein the bonding pad is a contact pad of the trace; and
the bonding pad including:
a first end wall,
a second end wall opposite the first end wall,
a first side wall, and
a second side wall opposite the first side wall,
wherein the first side wall and the second side wall connect the first end wall to the second end wall, and
the first end wall is wider than the second end wall;
wherein the first end wall is closer to the trace than is the second end wall, and the first end wall includes a sloped portion.

US Pat. No. 10,658,318

FILM SCHEME FOR BUMPING

Taiwan Semiconductor Manu...

1. An integrated circuit comprising:a conductive pad comprising a pad material;
a conductive bump overlying the conductive pad, wherein the conductive bump comprises a first bump layer and a second bump layer covering the first bump layer;
a barrier layer configured to block movement of the pad material from the conductive pad to the second bump layer along sidewalls of the first bump layer;
a first seed layer covering the barrier layer; and
a second seed layer partially covering the first seed layer, between and directly contacting the first seed layer and the first bump layer, wherein an interface at which the second seed layer and the first bump layer directly contact is elevated above a bottom edge of the barrier layer and is recessed below a top edge of the barrier layer, and wherein the first seed layer, the second seed layer, and the first bump layer each has a different majority metal element;
wherein the conductive bump, the first seed layer, and the second seed layer are devoid of copper.

US Pat. No. 10,658,317

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a first lead including an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction;
a semiconductor element supported by the first lead; and
a sealing resin covering the semiconductor element and a part of the first lead, the sealing resin comprising a first side surface and a reverse surface, wherein:
the first lead includes portions exposed from the sealing resin, the exposed portions include a first exposed portion and a second exposed portion, the first exposed portion being exposed at the first side surface of the sealing resin, the second exposed portion being exposed at the reverse surface of the sealing resin, each of the first exposed portion and the second exposed portion being formed with a surface plating layer,
the first side surface of the sealing resin comprises a first portion and a second portion, the first portion being outwardly offset from the second portion as viewed in the thickness direction, and
the first exposed portion of the first lead is disposed at the second portion of the first side surface of the sealing resin.

US Pat. No. 10,658,316

BOND PAD RELIABILITY OF SEMICONDUCTOR DEVICES

GLOBALFOUNDRIES Singapore...

1. A semiconductor device comprising:a substrate;
at least one bond pad over the substrate;
a passivation layer having an opening over the at least one bond pad, wherein the opening is defined by end portions of the passivation layer;
a NBLoK layer covering the end portions of the passivation layer; and
a trench having sidewalls at a perimeter of the semiconductor device.

US Pat. No. 10,658,315

REDISTRIBUTION LAYER METALLIC STRUCTURE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit (IC) structure, comprising:a semiconductor substrate;
an interconnection structure formed on the semiconductor substrate and including a top metal feature within a first region;
a passivation layer disposed on the interconnection structure and having an opening within a second region being distanced away from the first region; and
a redistribution layer (RDL) metallic feature formed in the passivation layer, wherein the RDL metallic feature is landing on the top metal feature, and horizontally extends from the top metal feature in the first region to the opening in the second region, and wherein the RDL metallic feature further includes
a barrier layer disposed directly on the top metal feature, wherein the barrier layer includes a metal and nitrogen;
a diffusion layer disposed directly on the barrier layer, wherein the diffusion layer includes the metal and oxygen; and
a metallic layer disposed directly on the diffusion layer.

US Pat. No. 10,658,314

WAFER LAMINATE, METHOD FOR PRODUCTION THEREOF, AND ADHESIVE COMPOSITION FOR WAFER LAMINATE

SHIN-ETSU CHEMICAL CO., L...

1. A wafer laminate comprising a support, an adhesive layer formed on the support, and a wafer which is laminated on the adhesive layer in such a way that a surface of the wafer which has a circuit surface faces toward the adhesive layer,wherein the adhesive layer is a cured product of an adhesive composition comprising resin A and resin B, the resin A consisting of repeating units represented by the following formula (1) and having a weight-average molecular weight of 500 to 500,000, and the resin B containing a siloxane skeleton:
wherein R1 to R3 are independently a hydrogen atom, a hydroxyl group, and a monovalent organic group having 1 to 20 carbon atoms, with at least one of R1 to R3 being a hydroxyl group, and R4 is a hydrogen atom or a monovalent organic group having 1 to 30 carbon atoms, which may have a substituent.

US Pat. No. 10,658,313

SELECTIVE RECESS

Invensas Bonding Technolo...

1. A microelectronic assembly, comprising:a first substrate having a first surface, the first surface of the first substrate having a planarized topography;
a first microelectronic circuit element embedded into the first substrate;
a second substrate having a first surface, the first surface of the second substrate having a planarized topography and bonded to the first surface of the first substrate; and
a first recessed portion disposed in the first surface of the second substrate and extending a preselected depth below the first surface of the second substrate, the first recessed portion selectively located to be opposite the first microelectronic circuit element of the first substrate, wherein the first recessed portion has an area and a depth arranged to fully enclose a portion of the first microelectronic circuit element protruding above the first surface of the first substrate.

US Pat. No. 10,658,312

EMBEDDED MILLIMETER-WAVE PHASED ARRAY MODULE

Intel Corporation, Santa...

1. A method for fabricating an electronic device for generating or receiving signals comprising:fabricating a first set of substrate layers comprising a first material;
fabricating a signal generating/receiving circuit embedded in the first set of substrate layers;
fabricating a second set of substrate layers coupled to the first set of substrate layers, the second set of substrate layers comprising a second material having a lower electrical loss than the first material, the second set of substrate layers further comprising a plurality of antenna elements coupled through vias to the signal generating/receiving circuit;
fabricating a first ground plane that couples the first set of substrate layers to the second set of substrate layers; and
fabricating a second ground plane in the second set of substrate layers and separated from the first ground plane by a plurality of substrate layers that are in the second set of substrate layers, wherein the first and second ground planes are on opposite sides of a routing trace layer between the plurality of substrate layers.

US Pat. No. 10,658,311

DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY

ICTK Holdings Co., Ltd., ...

1. A method of designing a device for generating an identification key, the method comprising:disposing a plurality of conductive layers between a first plurality of nodes and a second plurality of nodes in a first region included in a semiconductor chip layout, the nodes connecting respective conductive layers to circuit elements,
a density of the plurality of conductive layers disposed in the first region being equal to or greater than a first threshold density and equal to or less than a second threshold density, and the first threshold density and the second threshold density being less than a minimum density,
the plurality of conductive layers forming shorted connections between nodes of the first and second pluralities at or below the minimum density; and
disposing a reader configured to determine whether a first conductive layer designated in advance among the plurality of conductive layers is formed and to provide the identification key based on the determination of the reader.

US Pat. No. 10,658,310

SECURE SEMICONDUCTOR CHIP BY PIEZOELECTRICITY

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a power source; and
a semiconductor chip comprising at least one circuit and a pass transistor that electrically couples the power source and the at least one circuit, wherein the pass transistor comprises a piezoelectric gate comprising a piezoelectric material that produces a voltage that causes the pass transistor to remain in an on-state based on application of a mechanical force to the piezoelectric gate,
wherein the device is an Internet of Things device.

US Pat. No. 10,658,309

SEMICONDUCTOR DEVICE WITH COMPRESSIVE INTERLAYER

Infineon Technologies AG,...

1. A semiconductor device, comprising:a substrate;
a structured interlayer on the substrate and having a defined edge; and
a structured metallization on the structured interlayer and having a defined edge which is immediately adjacent to the defined edge of the structured interlayer and faces the same direction from a plan view perspective of the semiconductor device as the defined edge of the structured interlayer,
wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer,
wherein the structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

US Pat. No. 10,658,308

TOPSIDE RADIO-FREQUENCY ISOLATION CAVITY CONFIGURATION

Skyworks Solutions, Inc.,...

1. A method for fabricating a semiconductor die, the method comprising:providing a semiconductor substrate;
forming a plurality of active devices and a plurality of passive devices over the semiconductor substrate;
forming one or more electrical connections to the plurality of active devices and the plurality of passive devices;
forming one or more dielectric layers over at least a portion of the electrical connections;
applying an interface material over at least a portion of the one or more dielectric layers;
removing portions of the interface material to form a plurality of trenches; and
covering at least a portion of the interface material and the plurality of trenches with a substrate layer to form a plurality of radio-frequency isolation cavities.

US Pat. No. 10,658,307

CONTROL OF WARPAGE USING ABF GC CAVITY FOR EMBEDDED DIE PACKAGE

Intel Corporation, Santa...

1. A semiconductor package, comprising:a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall;
a plurality of conductive contacts at the second side of the die;
a reinforcement layer having a first portion laterally adjacent to the first lateral sidewall of the die, and the reinforcement layer having a second portion laterally adjacent to the second lateral sidewall of the die, the reinforcement layer comprising glass fibers in an epoxy matrix, and the reinforcement layer having a surface co-planar with the second side of the die;
a dielectric material on the second side of the die and on the surface of the reinforcement layer;
a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts;
a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts;
a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via;
a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via;
a first solder bump coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and
a second solder bump coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die.

US Pat. No. 10,658,306

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first chip having a first surface and a second surface opposite the first surface;
a supporter surrounding an edge of the first chip, wherein the supporter includes a first segment and a second segment connected to each other, a thickness of the second segment is smaller than a thickness of the first segment, an upper surface of the second segment is recessed from an upper surface of the first segment to define a recessed portion, and two opposite sides of the recessed portion are defined by the first segment;
a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip;
an insulation layer disposed over the first surface of the first chip; and
an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

US Pat. No. 10,658,305

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a substrate;
an ?-ray shielding layer on the substrate;
a first semiconductor chip provided on the ?-ray shielding layer; and
a second semiconductor chip provided on the first semiconductor chip, whose operation is controlled by the first semiconductor chip.

US Pat. No. 10,658,304

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:an electroconductive shielding layer;
an isolation layer formed on the shielding layer and comprising a frame-shaped opening as viewed in a thickness direction;
a wiring layer disposed on the isolation layer so as to be surrounded by the opening;
a semiconductor element having an element front surface and an element back surface that are opposite to each other in the thickness direction, the semiconductor element being disposed on the wiring layer with the element back surface facing the wiring layer;
electroconductive pillars spaced apart from the semiconductor element and standing on the wiring layer in the thickness direction;
an electroconductive frame standing on a region of the shielding layer exposed through the opening in the thickness direction, the frame surrounding the semiconductor element and the electroconductive pillars as viewed in the thickness direction; and
an electrically insulating sealing resin covering the wiring layer and the semiconductor element,
wherein the frame is configured to be electrically connected to an external ground terminal.

US Pat. No. 10,658,303

HIGH ASPECT RATIO CONNECTION FOR EMI SHIELDING

NXP USA, Inc., Austin, T...

1. A packaged semiconductor device comprising:a substrate;
a semiconductor die attached to a top surface of the substrate;
a mold body formed over the substrate and surrounding the semiconductor die;
a tiered through mold via (TMV) comprising:
a first recess formed in the mold body, having a recessed surface within the mold body at a first depth, and
a second recess formed in the mold body from the recessed surface to a second depth that exposes a ground contact area on a bonding area on the top surface of the substrate, wherein the first depth is greater than the second depth; and
a metal shielding layer formed on a top surface of the mold body to form a shielded mold body, wherein the metal shielding layer makes direct contact with at least one sidewall of the first recess, with at least a portion of the recessed surface, with at least one sidewall of the second recess, and with the ground contact area,
wherein:
the substrate comprises a lead frame,
the semiconductor die is attached to a top surface of a die paddle of the lead frame, and the second recess exposes the ground contact area on a lead finger of the lead frame.

US Pat. No. 10,658,302

WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING

Invensas Corporation, Sa...

1. An apparatus for protection from electromagnetic interference, comprising:a platform having an upper surface and a lower surface opposite the upper surface and having a ground plane;
a first microelectronic device coupled to the upper surface of the platform;
a first interference shielding region for the first microelectronic device including first wire bond wires having a vertical profile coupled to the ground plane with a consistent first pitch extending away from the upper surface of the platform with upper ends of the first wire bond wires extending above an upper surface of the first microelectronic device;
a second microelectronic device coupled to the upper surface of the platform located outside of the first interference shielding region;
a second interference shielding region for the second microelectronic device including second wire bond wires coupled to the ground plane with a second pitch extending away from the upper surface of the platform with upper ends of the second wire bond wires being above an upper surface of the second microelectronic device; and
a trace extending from the first interference shielding region to the second interference shielding region between the first wire bond wires and the second wire bond wires on the upper surface of the platform for interconnection of the first microelectronic device and the second microelectronic device;
a conductive layer coupled to at least a subset of the upper ends of the first wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the first interference shielding region; and
the conductive layer defining a ring-like hole therein having a pad therein isolated from a remainder of the conductive layer by the ring-like hole.

US Pat. No. 10,658,301

IMAGE PICKUP APPARATUS AND CAMERA MODULE

Sony Corporation, Tokyo ...

1. An image pickup apparatus, comprising:a substrate having a front side that includes an optical element area and a back side, wherein the front side is configured to receive light and the back side is opposite to the front side;
a first electrode pad adjacent to the optical element area;
a sealing material above the optical element area, wherein the sealing material covers the first electrode pad;
an organic layer between the first electrode pad and the sealing material;
a second electrode pad on the substrate, wherein the organic layer is not between the second electrode pad and the sealing material; and
an electrode electrically connected to the first electrode pad,
wherein the first electrode pad is electrically connected to an external connection terminal via the electrode.

US Pat. No. 10,658,300

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor comprising:a lower chip including a lower chip body, first through silicon vias (TSVs) extending vertically through the lower chip body, and pads on an upper surface of the lower chip body, the pads being electrically connected to the first TSVs, respectively;
an upper chip on the lower chip, the upper chip including an upper chip body, and bumps on a lower surface of the upper chip body, the bumps directly bonded to corresponding ones of the pads of the lower chip, respectively, and each of the bumps including a pillar and a solder layer; and
an adhesive layer between the lower chip body and the upper chip body,
wherein each of the pillars of the bumps, the first TSVs and the pads has a centerline extending in a direction perpendicular to the upper surface of the lower chip body,
wherein the centerlines of the pillars of the bumps extend through geometric centers of the pillars, respectively, as viewed in a plan view of the semiconductor package,
wherein the centerlines of the first TSVs extend through axial centers of the first TSVs, respectively, the centerlines of the pads extend vertically through geometric centers of the pads, respectively, as viewed in a plan view of the semiconductor package,
wherein the centerlines of the pillars of the bumps are aligned with the centerlines of the first TSVs, respectively, in a peripheral region of the lower chip, the centerline of the pillar of a first bump from among the bumps is offset from the centerline of a corresponding pad from among the pads to which the first bump is bonded, and
wherein a misaligned extent of each pad from among the pads is a distance between the centerline of a pillar of a bump from among the bumps bonded to the pad and the centerline of the pad, divided by a width of the pillar of the bump bonded to the pad, and the misaligned extent for each of the pads is less than 50%;
wherein in a central region of the lower chip, the centerline of the pillar of a second bump from among the bumps and the centerline of a corresponding pad from among the pads to which the second bump is bonded are aligned with each other, and
wherein in the peripheral region of the lower chip, distances by which the centerlines of the pillars of a first plurality of bumps from among the bumps and the centerlines of a corresponding first plurality of pads from among the pads to which the first plurality of bumps are bonded are offset vary among the first plurality of bumps and the corresponding first plurality of pads bonded to each other.

US Pat. No. 10,658,299

REPLACEMENT METAL GATE PROCESSES FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure, comprising:forming a plurality of fins disposed over a top surface of a substrate; and
forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process;
wherein a gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
wherein the given VTFET comprises a given top SAC capping layer disposed over a given top source/drain contact metal layer, the given top source/drain contact metal layer being disposed over a given top source/drain region of the given VTFET; and
wherein the given VTFET comprises a bottom SAC capping layer disposed over a bottom source/drain contact metal layer, the bottom source/drain contact metal layer being disposed over a bottom source/drain region of the given VTFET.

US Pat. No. 10,658,298

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a dielectric layer having a first surface, wherein a surface uniformity of the first surface is substantially equal to or less than 5%;
a first conductive pattern disposed on the first surface of the dielectric layer, wherein the first conductive pattern comprises a first conductive trace, and a line width of the first conductive trace substantially ranges from about 0.5 ?m and about 2 ?m; and
a first semiconductor device disposed on the first surface of the dielectric layer and electrically connected to the first conductive pattern.

US Pat. No. 10,658,297

METAL-NITRIDE-FREE VIA IN STACKED MEMORY

Intel Corporation, Santa...

1. An apparatus comprising:a memory stack structure including multiple memory cells, the memory stack structure including a crosspoint architecture;
a via in parallel with the memory stack structure to provide a current path to select at least one of the memory cells;
a metal layer to couple to the via and to a top electrode of the memory stack structure; and
a metal silicon nitride layer to couple the metal layer to the top electrode, wherein the metal silicon nitride layer to be part of the memory stack structure, to be between individual pillars of the crosspoint architecture and the metal layer, and not be between the metal layer and the via.

US Pat. No. 10,658,296

DIELECTRIC FILM FOR SEMICONDUCTOR FABRICATION

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor manufacturing, comprising:receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed;
depositing a dielectric film having Si, N, C, and O directly attached to the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion, wherein the concentration of C in the first portion of the dielectric film is at least 10 times more than that in the second portion of the dielectric film; and
forming a conductive feature directly attached to the dielectric film.

US Pat. No. 10,658,295

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a first interconnect layer provided above a semiconductor substrate;
a first insulating layer and a second interconnect layer stacked in order on the first interconnect layer; and
a memory pillar penetrating the first insulating layer and the second interconnect layer so that a bottom surface of the memory pillar reaches an inner portion of the first interconnect layer, and including a second insulating layer, a charge storage layer, and a third insulating layer, which are stacked on a part of a side surface including an area in contact with the second interconnect layer and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer, which are stacked in order along a first direction perpendicular to the semiconductor substrate,
wherein, in the first direction, a height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.

US Pat. No. 10,658,294

STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:a first conductor in a first plane connecting a power source to integrated circuit devices, wherein the first conductor includes a first axis defining a first side and a second side of the first conductor;
a second conductor in a second plane parallel to the first plane, wherein the second conductor is connected to the first conductor by first vias extending in a second direction perpendicular to the first plane; and
a third conductor in a third plane parallel to the first plane, wherein the third conductor is connected to the second conductor by second vias extending in the second direction, wherein the third conductor includes a second axis defining a third side and a fourth side of the third conductor, and wherein the first side of the first conductor and the third side of the third conductor are aligned in the second direction, wherein the second side of the first conductor and the fourth side of the third conductor are aligned in the second direction, wherein the first vias contact the first conductor in only the first side, and wherein the second vias contact the third conductor in only the third side.

US Pat. No. 10,658,293

SEMICONDUCTOR DEVICE HAVING A MULTILAYER WIRING STRUCTURE

SOCIONEXT INC., Yokohama...

1. A semiconductor device comprising:a first standard cell;
a plurality of first wirings extending in a first direction in a plan view;
a plurality of second wirings formed above the first wirings and extending in a second direction different from the first direction in a plan view; and
a plurality of third wirings formed above the second wirings and extending in the first direction in a plan view, wherein:
the plurality of first wirings include a first power supply line and a second power supply line;
the plurality of third wirings include a third power supply line that is located above the first power supply line and electrically connected to the first power supply line,
the plurality of third wirings include a fourth power supply line that is located above the second power supply line and electrically connected to the second power supply line;
the plurality of second wirings include a first connection wiring that is located above the first power supply line and below the third power supply line and electrically connected to the first power supply line and to the third power supply line and extends in the second direction in a plan view;
the plurality of second wirings include a second connection wiring that is located above the second power supply line and below the fourth power supply line and electrically connected to the second power supply line and to the fourth power supply line and extends in the second direction in a plan view,
the first standard cell includes the first power supply line, the second power supply line, the third power supply line, the fourth power supply line, the first connection wiring and the second connection wiring,
the third power supply line is superposed on the first power supply line in a plan view; and
the fourth power supply line is superposed on the second power supply line in a plan view.

US Pat. No. 10,658,292

METAL PATTERNING FOR INTERNAL CELL ROUTING

Taiwan Semiconductor Manu...

7. A semiconductor structure, comprising:a first cell, including:
a first supply metal line;
a second supply metal line having a width greater than a width of the first supply metal line; and
a first pattern metal layer disposed between the first supply metal line and the second supply metal line and having a width substantially the same as a width of the first supply metal line, the first pattern metal layer comprising:
a first internal route; and
a first power route; and
a second cell formed below the first cell, including:
a third supply metal line proximal to the first supply metal line and having a width substantially the same as the first supply metal line;
a fourth supply metal line distal to the second supply metal line and having a width greater than a width of the third supply metal line; and
a second pattern metal layer disposed between the third supply metal line and the fourth supply metal line and having a width substantially the same as a width of the third supply metal line, the second pattern metal layer comprising a second internal route.

US Pat. No. 10,658,291

METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH

Intel Corporation, Santa...

1. An apparatus, comprising:an integrated circuit device layer comprising a plurality of circuit devices, the integrated circuit device layer having a first side opposite a second side;
a first plurality of interconnect layers on the first side of the device layer, wherein the interconnects of the first plurality of interconnect layers have a same thickness dimension; and
a second plurality of interconnect layers on the second side of the device layer, wherein the second plurality of interconnect layers comprises first interconnects and second interconnects, wherein the first interconnects have a different thickness dimension than the second interconnects, and wherein the first interconnects of the second plurality of interconnect layers are to contain global clock distribution, and the second interconnects of the second plurality of interconnect layers are to globally distribute power.

US Pat. No. 10,658,290

PLURALITY OF DIFFERENT SIZE METAL LAYERS FOR A PAD STRUCTURE

Taiwan Semiconductor Manu...

1. A device comprising:a first metal layer, the first metal layer comprising a first metal contact;
a contact pad substantially vertically above the first metal contact; and
a second metal layer between the contact pad and the first metal layer, the second metal layer comprising a plurality of second metal contacts, wherein the plurality of second metal contacts are disposed vertically below and within a lateral extent of the contact pad, and wherein each of the first metal contact and the plurality of second metal contacts has a shorter length and a shorter width than the contact pad in a plan view.

US Pat. No. 10,658,289

SEMICONDUCTOR DEVICES HAVING NONLINEAR BITLINE STRUCTURES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate including a field area delimiting an active area;
a word line crossing the active area; and
a bit line having a wave shape and including a first bending portion, a second bending portion, and a third bending portion between the first bending portion and the second bending portion, the third bending portion crossing the active area, the first bending portion and the second bending portion on the field area, the first bending portion and the second bending portion opposite with respect to the active area,
wherein the first bending portion includes a highest point of the wave shape and the second bending portion includes a lowest point of the wave shape.

US Pat. No. 10,658,288

SEMICONDUCTOR DEVICE HAVING A METAL VIA

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate having an active region defined by a deep trench;
an active fin protruding from the active region and defined by a shallow trench adjacent to the deep trench, the active fin extended in a first direction;
a gate structure overlapping the active fin along a direction orthogonal to an upper surface of the substrate and extended in a second direction intersecting the first direction;
a source/drain region disposed on the active fin;
a contact plug connected to the source/drain region;
a metal via positioned at a first level above the substrate, higher than an upper surface of the contact plug, and spaced apart from the active region along the direction orthogonal to the upper surface of the substrate, wherein the metal via does not overlap the contact plug along the direction orthogonal to the upper surface of the substrate;
a metal line positioned at a second level above the substrate, higher than the first level, and connected to the metal via; and
a via connection layer extended from an upper portion of the contact plug and connected to the metal via.

US Pat. No. 10,658,287

SEMICONDUCTOR DEVICE HAVING A TAPERED PROTRUDING PILLAR PORTION

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a semiconductor die;
an encapsulant laterally encapsulating the semiconductor die; and
a redistribution structure disposed on the semiconductor die and the encapsulant and electrically connected to the semiconductor die, and the redistribution structure comprising:
a dielectric layer;
a conductive via in the dielectric layer, the conductive via comprising a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall; and
a redistribution wiring covering the conductive via and a portion of the dielectric layer.

US Pat. No. 10,658,286

METAL-OXIDE-METAL CAPACITOR WITH EMBEDDED ROUTING

Nuvoton Technology Corpor...

1. A capacitor cell for a semiconductor device, said capacitor cell comprising:a capacitor having a first node and a second node;
a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor, wherein the first contact point is encompassed in a first conductive region at a first corner of the capacitor cell, and the second contact point is encompassed in a second conductive region at a second corner of the capacitor cell; and
a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor, wherein the first contact point and the third contact point are located at a first edge of the capacitor cell, and the second contact point and the fourth contact point are located at a second edge of the capacitor cell.

US Pat. No. 10,658,285

STACK OF HORIZONTALLY EXTENDING AND VERTICALLY OVERLAPPING FEATURES, METHODS OF FORMING CIRCUITRY COMPONENTS, AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS

Micron Technology, Inc., ...

1. NAND memory circuitry comprising:a memory array having a primary portion and a stair portion;
the primary portion having memory cells comprising operative structures that extend vertically in a vertical stack, the stack comprising gate lines having dielectric material vertically there-between, all of the operative structures comprising the same peripheral shape relative to one another in a horizontal cross-section of the stack;
the stair portion having stairs comprising individual of the gate lines; and
dummy structures extending vertically through the stairs.

US Pat. No. 10,658,284

SHAPED LEAD TERMINALS FOR PACKAGING A SEMICONDUCTOR DEVICE FOR ELECTRIC POWER

MITSUBISHI ELECTRIC CORPO...

1. A semiconductor device for electric power, comprising:a circuit board;
a semiconductor element for electric power having a first surface on which an electrode is formed and a second surface bonded to the circuit board;
a lead terminal having a first longitudinal end bonded to the electrode, and a second longitudinal end configured to be electrically connected externally of the semiconductor device; and
a sealing member by which the semiconductor element for electric power is sealed together with the lead terminal bonded to the electrode;
wherein, the first longitudinal end of the lead terminal is formed which becomes farther from the circuit board as it becomes closer to the terminal portion of the first longitudinal end;
wherein, the lead terminal has a thickness between a first side facing in a direction of the circuit board and a second side facing in an opposite direction that becomes thinner up to the terminal portion of the first longitudinal end.

US Pat. No. 10,658,283

METHOD FOR MANUFACTURING A DEVICE WITH INTEGRATED-CIRCUIT CHIP BY DIRECT DEPOSIT OF CONDUCTIVE MATERIAL

THALES DIS FRANCE SA, Me...

1. A method for manufacturing a device with a secure integrated-circuit chip, said device having an insulating substrate, electrically conductive surfaces on the insulating substrate electrically connected to said secure integrated-circuit chip, said electrically conductive surfaces being produced by a step of depositing or transferring conductive material, said secure integrated-circuit chip being directly soldered or brazed to the conductive material forming the electrically conductive surfaces,wherein said step of depositing or transferring conductive material is carried out by a technique of directly depositing metal microparticles, which are free of polymer or solvent, onto the insulating substrate, said deposit being obtained by coalescence of the metal microparticles forming at least one or several uniform cohesive layer(s) that rest(s) directly in contact with the insulating substrate.

US Pat. No. 10,658,282

PACKAGE SUBSTRATE STRUCTURE AND BONDING METHOD THEREOF

Unimicron Technology Corp...

1. A package substrate structure, comprising:a first substrate, comprising:
a plurality of vias, disposed on the first substrate; and
a plurality of pads, disposed on the first substrate, and disposed in the vias;
a second substrate, disposed opposite to the first substrate;
a plurality of conductive pillars, each of the conductive pillars being located between the first substrate and the second substrate, electrically connecting each of the pads and the second substrate, each of the conductive pillars filling each of the vias;
an adhesive layer, disposed between the first substrate and the second substrate, the adhesive layer filling gaps between the conductive pillars; and
a macromolecular adhesive layer, disposed on the adhesive layer, the adhesive layer and the macromolecular adhesive layer filling the gaps between the conductive pillars.

US Pat. No. 10,658,281

INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF MAKING

Intel Corporation, Santa...

1. A substrate for an integrated circuit, the substrate comprising:a dielectric layer; and
a conductive layer extending in an x or y direction and at least partially embedded within the dielectric layer, the conductive layer comprising:
a via having a first end and an opposite second end, wherein the via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end, and the via has a non-tapered profile in the z-direction;
a capture pad attached to the via having a major diameter equivalent to a major diameter of the via; and
a trace adjacent to the via and having a second height in the z-direction that is different than the first height, wherein
the via has a constant width.

US Pat. No. 10,658,280

ELECTRICAL DEVICE INCLUDING A THROUGH-SILICON VIA STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. An electrical device, comprising:a substrate having a first surface and defining a recess in the first surface;
an active circuit layer; and
a via disposed in the recess, the via comprising:
an insulation layer disposed on the first surface of the substrate and extending at least to a sidewall of the recess;
a first conductive layer disposed adjacent to the insulation layer and extending over at least a portion of the first surface of the substrate, the first conductive layer being in direct contact with the active circuit layer;
a second conductive layer disposed adjacent to the first conductive layer and extending over at least a portion of the first surface of the substrate, the second conductive layer having a negative coefficient of thermal expansion (CTE); and
a stress adjusting layer disposed on and in contact with the first surface of the substrate, and wherein a CTE of the stress adjusting layer is negative.

US Pat. No. 10,658,279

HIGH DENSITY PACKAGE INTERCONNECTS

INTEL CORPORATION, Santa...

1. An apparatus comprising:a substrate including a die side, the die side including first and second die footprint regions and an intermediate region therebetween;
a first plurality of substrate pads adapted to electrically couple with a first die to be disposed in the first die footprint region, the first plurality of substrate pads including a first group of pads and a second group of pads, the first group of pads comprising a plurality of rows of pads having a first pad size, the second group of pads comprising a plurality of rows of pads having a second pad size that is larger than the first pad size;
a second plurality of substrate pads adapted to electrically couple with a second die to be disposed in the second die footprint region, the second plurality of substrate pads including a third group of pads and a fourth group of pads, the third group of pads comprising a plurality of rows of pads having the first pad size, the fourth group of pads comprising a plurality of rows of pads having the second pad size; and
a plurality of trace lines electrically coupling the first group of pads to the third group of pads, the trace lines extending through the intermediate region;
wherein the first group of pads and the third group of pads are rectangular in shape when viewed from above, and wherein the second group of pads and the fourth group of pads are circular in shape when viewed from above.

US Pat. No. 10,658,278

ELECTRICAL DEVICE TERMINAL FINISHING

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:a terminal including a base material;
a plating stack arranged on a surface of the base material, wherein the plating stack includes breaks in the plating stack that extend from a first surface of the plating stack to a second surface of the plating stack that is arranged adjacent to the surface of the base material; and
a solder finish coated over the breaks in the plating stack.

US Pat. No. 10,658,277

SEMICONDUCTOR PACKAGE WITH A HEAT SPREADER AND METHOD OF MANUFACTURING THEREOF

UTAC Headquarters Pte. Lt...

1. A semiconductor package comprising:a package substrate comprising a top substrate surface and a bottom substrate surface, wherein the package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface;
a heat spreader disposed on the top substrate surface, the heat spreader comprises a top planar surface and a bottom planar surface, wherein the top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region, wherein the heat spreader comprises a thickness extending from the top planar surface the bottom planar surface;
a semiconductor die, wherein the semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region;
wherein the package substrate is a lead frame comprising a die-attach paddle and a plurality of lead fingers peripherally located relative to the die-attach paddle, wherein the heat spreader is directly disposed on a top surface of the die-attach paddle; and
wherein the thickness of the heat spreader is greater relative to the thickness of the package substrate.

US Pat. No. 10,658,276

DEVICE WITH TOP-SIDE BASE PLATE

Tesla, Inc., Palo Alto, ...

1. A device comprising:an integrated circuit (IC) die;
a top-side base plate to which the IC die is mounted, wherein the top-side base plate comprises one or more leads that are formed as an integral part of the top-side base plate and electrically or thermally connect the top side base plate to one or more pads of a printed circuit board (PCB); and
a body attached to the top-side base plate such that the IC die is inside the body, the body configured for attachment to the PCB such that the top-side base plate faces away from the PCB.

US Pat. No. 10,658,275

RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE

ABLIC INC., Chiba (JP)

1. A resin-encapsulated semiconductor device, comprising:a semiconductor chip;
a die pad having the semiconductor chip bonded thereon;
a plurality of heat dissipation inner leads each connected to one of four corners of the die pad, and a plurality of heat dissipation outer leads each connected to one of the plurality of heat dissipation inner leads, respectively;
a plurality of inner leads each electrically connected to the semiconductor chip through a metal wire, and a plurality of outer leads each connected to one of the plurality of inner leads, respectively, the plurality of inner leads and outer leads residing only along two opposing sides of the die pad and between the plurality of heat dissipation inner leads and outer leads
wherein the plurality of heat dissipation inner leads are not electrically connected to the semiconductor chip by the metal wires; and
an encapsulating resin encapsulating the die pad, the semiconductor chip, the plurality of inner leads, and the plurality of heat dissipation inner leads,
wherein the plurality of heat dissipation inner leads and the plurality of inner leads extend parallel with each other and are on a same lateral plane within the encapsulating resin, and the plurality of heat dissipation inner leads and plurality of heat dissipation outer leads have a uniform width from the die pad to terminal ends thereof, where the uniform width is wider than a width of the plurality of inner leads and a width of the plurality of outer leads,
a back surface of the die pad, the plurality of outer leads, and the plurality of heat dissipation outer leads being exposed from the encapsulating resin, and
the back surface of the die pad, back surfaces of the plurality of outer leads, and back surfaces of the plurality of heat dissipation outer leads being flush.

US Pat. No. 10,658,274

ELECTRONIC DEVICE

Nexperia B.V., Nijmegen ...

1. An electronic device comprising:a die;
at least one lead; and
at least one connector, the at least one connector for connecting the die to the corresponding at least one lead, the at least one connector comprising a first end disposed in bondable proximity to a complementary surface of the corresponding at least one lead and a second end disposed in bondable proximity to a complementary surface of the die;
wherein the first end has an end portion that comprises a formation comprising
a bend out of a plane of the connector so that a portion of the end portion of the first end extends in a direction out of the plane of the connector; and
a rounded apex in the bondable proximity to the complementary surface of the at least one lead that defines a first region and at least one second region between the formation and the complementary surface of the at least one lead so that the first region and the at least one second region are configured to attract by capillary action an electrically conductive bonding material to consolidate therein.

US Pat. No. 10,658,273

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Denso Corporation, Kariy...

1. A semiconductor device comprising:a first semiconductor element and a second semiconductor element;
a first insulated substrate comprising an insulator layer and a metal layer disposed on each of two faces of the insulator layer, the metal layer on one face of the first insulated substrate being connected to the first semiconductor element; and
a second insulated substrate comprising an insulator layer and a metal layer disposed on each of two faces of the insulator layer, the metal layer on one face of the second insulated substrate being connected to the second semiconductor element,
wherein
the metal layer on the one face of the first insulated substrate is electrically connected to the metal layer on the one face of the second insulated substrate via a joint;
the joint is constituted of a separate member from the first insulated substrate and the second insulated substrate; and
one end of the joint is attached to the metal layer on the one face of the first insulated substrate, and another end of the joint is attached to the metal layer on the one face of the second insulated substrate.

US Pat. No. 10,658,272

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method for manufacturing a semiconductor device, the method comprising:forming a first metal layer above a substrate of a semiconductor chip;
forming a nickel layer on the first metal layer;
performing a first cleaning treatment on the nickel layer with diluted hydrochloric acid having a concentration of less than 1% by weight;
forming a gold layer on the nickel layer; and
connecting a bonding wire to a surface of the gold layer.

US Pat. No. 10,658,271

DIE PAD INCLUDING PROJECTIONS

Mitsubishi Electric Corpo...

1. A die pad comprising:a die pad substrate;
a first projection disposed on an upper surface of said die pad substrate, said first projection having a pedestal shape;
a second projection disposed on said upper surface of said die pad substrate so as to surround at least part of said first projection in a plan view, said second projection having a bank shape; and
a third projection disposed on said upper surface of said die pad substrate so as to surround at least part of said second projection in a plan view, said third projection having a bank shape, wherein
said second projection includes a side that extends longitudinally in a direction substantially parallel to a direction in which a side of said first projection extends longitudinally, and said third projection includes a side that extends longitudinally in a direction substantially parallel to said direction in which said side of said second projection extends longitudinally,
a first length along said longitudinal direction of said side of said second projection is greater than a second length along said longitudinal direction of said side of said first projection, and
a third length along said longitudinal direction of said side of said third projection is greater than said first length along said longitudinal direction of said side of said second projection.

US Pat. No. 10,658,270

SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a semiconductor substrate and a conductive feature formed over the semiconductor substrate;
an etch stop layer formed over the conductive feature;
a dielectric layer formed over the etch stop layer;
a contact formed in a contact trench within the dielectric layer, a bottom of the contact being disposed over a top surface of the conductive feature; and
a self-aligned sealing oxide layer formed on the dielectric layer,
wherein the self-aligned sealing oxide layer directly contacts the dielectric layer from a bottom-most portion of the self-aligned sealing oxide layer to a top-most portion of the self-aligned sealing oxide layer.

US Pat. No. 10,658,269

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, comprising:providing a first substrate;
forming a hollow channel in a first portion of a first dielectric layer having a surface in contact with the first substrate;
forming a sidewall protection layer in the first dielectric layer by filling the hollow channel;
forming a first trench in the first dielectric layer; and
forming a second trench through an opening of the first trench, the second trench being in a second dielectric layer.

US Pat. No. 10,658,268

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a lower electrode;
a semiconductor chip provided on the lower electrode;
a pressure pad provided above or below the semiconductor chip;
an upper electrode provided on a structure in which the pressure pad is overlapped with the semiconductor chip; and
a connection conductor that is capable of providing a new current path between the lower electrode and the upper electrode only when a distance between the lower electrode and the upper electrode becomes larger than a predetermined value, the predetermined value based on the distance between the lower electrode and the upper electrode during a short circuit of the semiconductor device, wherein
the distance between the lower electrode and the upper electrode is capable of varying, and
the pressure pad electrically connects the lower electrode and the upper electrode together via the semiconductor chip regardless of the distance between the lower electrode and the upper electrode.

US Pat. No. 10,658,267

METAL CORED SOLDER DECAL STRUCTURE AND PROCESS

International Business Ma...

1. A method of producing metal cored solder structures on a substrate, comprising:providing a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal;
positioning a carrier beneath the bottom surface of the decal, the carrier having one or more cavities in a top surface and the cavities located in alignment with the apertures of the decal;
positioning the decal on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities,
receiving at each feature cavity a respective metal element therein, each feature cavity being configured to receive molten solder and being cooled in the feature cavity;
separating the decal from the carrier to partially expose metal core solder contacts, the partially exposed metal core solder contacts extending below the bottom surface of said decal;
combining the decal with the substrate by positioning the decal on the substrate, the substrate having receiving elements such that a bottom surface of each respective partially exposed metal core solder contact of the decal is positioned on a respective receiving element of the substrate;
heating the combined decal and substrate to reflow the solder of the solder contacts within a respective receiving element; and
removing the decal from holding the metal core solder contacts to thereby expose the metal core solder contacts on the substrate.

US Pat. No. 10,658,266

THERMOELECTRIC COOLING PACKAGES AND THERMAL MANAGEMENT METHODS THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A method for managing a temperature of a device, the method comprising:determining a temperature of a package including a circuit; and
selectively operating a thermoelectric semiconductor of the device based on the determined temperature to manage the temperature of the package,
wherein the selectively operating comprises:
not operating the thermoelectric semiconductor and maintaining a frequency of the circuit, based on the determined temperature being below a first temperature,
not operating the thermoelectric semiconductor and decreasing the frequency of the circuit, based on the determined temperature being equal to or above the first temperature and below a second temperature, and
operating the thermoelectric semiconductor and decreasing the frequency of the circuit, based on the determined temperature being equal to or above the second temperature and below a third temperature.

US Pat. No. 10,658,265

HEAT DISSIPATION STRUCTURE, METHOD FOR MAKING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME

Avary Holding (Shenzhen) ...

1. A heat dissipation structure comprising:a flexible substrate comprising a first surface and a second surface facing away from the first surface;
a graphite sheet;
a cover plate;
and a heat insulating material;
wherein the flexible substrate is disposed on the graphite sheet and the second surface of the flexible substrate faces the graphite sheet, at least one containing cavity is formed between the flexible substrate and the graphite sheet, the heat insulating material is filled in the at least one containing cavity; the cover plate is disposed on the first surface of the flexible substrate, at least one groove is formed in the flexible substrate extending from the first surface of the flexible substrate toward the second surface of the flexible substrate, the at least one groove is sealed by the cover plate to form sealed cavity, a phase changing material is filled in the sealed cavity.

US Pat. No. 10,658,264

DIAMOND-BASED HEAT SPREADING SUBSTRATES FOR INTEGRATED CIRCUIT DIES

Analog Devices, Inc., No...

1. A packaged integrated circuit (IC) device, comprising:a heat sink;
a diamond-based heat spreading substrate on the heat sink, wherein the diamond-based heat spreading substrate has an array of hollow vias formed completely therethrough; and
an integrated circuit (IC) die positioned on the diamond-based heat spreading substrate, wherein an edge of the IC die overlaps at least one of the vias.

US Pat. No. 10,658,263

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a first semiconductor die and a second semiconductor die, wherein the first and second semiconductor dies are different types of dies and are disposed side by side;
a molding compound, enclosing the first and second semiconductor dies;
a heat dissipation module, located directly on and in contact with back sides of the first and second semiconductor dies; and
an adhesive material, filled between and contacting the heat dissipation module and the molding compound,
wherein the semiconductor package has a central region and a peripheral region surrounding the central region, the first and second semiconductor dies are located within the central region,
wherein a sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are coplanar with one another,
wherein the heat dissipation module comprises a thermal interfacial pattern in contact with the back sides of the first and second semiconductor dies,
wherein the thermal interfacial pattern and the adhesive material are made of different materials, and
wherein a portion of the adhesive material that is located within the central region is sandwiched between the heat dissipation module and a central portion of the molding compound that is located between the first and second semiconductor dies.

US Pat. No. 10,658,262

PIN FLEXURE ARRAY

1. An interconnector comprising:a base;
a pin array including a plurality of pins; and
a base pedestal, wherein the base pedestal is formed on the base, wherein the pins extend from the base pedestal, wherein a surface of the base pedestal is non-planar, wherein at least some of the pins in the plurality of pins include a free end at a first distance from a surface of the base that defines a base reference plane, wherein each of the plurality of pins are spaced apart from one another, and wherein a pin near a center of the pin array has length to width ratio that is less than a length to width ratio of a pin proximal to an edge of the pin array.

US Pat. No. 10,658,261

SEMICONDUCTOR DEVICE

Denso Corporation, Kariy...

1. A semiconductor device, comprising:a first semiconductor element having an upper electrode and a lower electrode;
a first upper heat sink connected to the upper electrode; and
a first lower heat sink connected to the lower electrode, the first lower heat sink being opposed to the first upper heat sink such that the first semiconductor element is sandwiched between the first upper heat sink and the first lower heat sink,
wherein one of the first upper heat sink and the first lower heat sink is a laminated substrate having an insulator substrate and conductor layers disposed on opposite surfaces of the insulator substrate, and the other of the first upper heat sink and the first lower heat sink is a conductor plate that is a conductor having higher thermal conductivity than the insulator substrate.

US Pat. No. 10,658,260

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a connection member;
a semiconductor chip disposed on the connection member, the semiconductor chip including connection pads;
a core member disposed on the connection member and next to the semiconductor chip, the core member including a hole extending from an inner side surface of the core member facing the semiconductor chip to an external side surface of the core member opposing the inner side surface of the core member; and
an encapsulant disposed on the connection member, covering at least a portion of the semiconductor chip, and filling at least a portion of the hole,
wherein at least a portion of the hole is surrounded by the core member.

US Pat. No. 10,658,259

WAFER-LEVEL PACKAGING FOR ENHANCED PERFORMANCE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a device layer with a plurality of input/output (I/O) contacts at a top surface of the device layer;
a plurality of first bump structures formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;
a first mold compound residing over the device layer, wherein a portion of each of the plurality of first bump structures is exposed through the first mold compound;
a stop layer formed underneath the device layer, wherein:
the stop layer comprises silicon oxide; and
the plurality of first bump structures and the device layer are located at a same side of the stop layer; and
a second mold compound residing underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

US Pat. No. 10,658,258

CHIP PACKAGE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A chip package, comprising:a first semiconductor die comprising a first dielectric layer and a plurality of conductive vias, the first dielectric layer comprising a first region and a second region, the conductive vias being embedded in the first region of the first dielectric layer;
a plurality of conductive pillars disposed on and electrically connected to the conductive vias;
a support structure;
a second semiconductor die stacked over the support structure and the second region of the first dielectric layer; and
an insulating encapsulant encapsulating the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the insulating encapsulant comprises:
a first encapsulation portion laterally encapsulating the first semiconductor die and the support structure; and
a second encapsulation portion connected to the first encapsulation portion and laterally encapsulating the second semiconductor die and the conductive pillars,
wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

US Pat. No. 10,658,257

SEMICONDUCTOR PACKAGE STRUCTURE, SEMICONDUCTOR WAFER LEVEL PACKAGE AND SEMICONDUCTOR MANUFACTURING PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a semiconductor die, having an active surface;
at least one wiring structure, electrically connected to the active surface of the semiconductor die;
an encapsulant, surrounding the semiconductor die, wherein the encapsulant is formed from an encapsulating material, a Young's Modulus of the encapsulant is from 0.001 GPa to 1 Gpa, the encapsulating material includes a plurality of silicon fillers, and a content of the silicon filler in the encapsulating material is 1% to 30%; and
a plurality of conductive elements, embedded in the encapsulant, and electrically connected to the at least one wiring structure.

US Pat. No. 10,658,256

SEMICONDUCTOR MOLD COMPOUND TRANSFER SYSTEM AND ASSOCIATED METHODS

Micron Technology, Inc., ...

1. A mold compound transfer system, comprising:a sheet mold compound; and
a granular mold compound comprising a plurality of individual grains directly on the sheet mold compound and spanning across at least a portion of the sheet mold compound;
wherein:
a combined thickness of the sheet mold compound and the granular mold compound is greater than or equal to 3 millimeters.

US Pat. No. 10,658,255

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

ADVANCED SEMSCONDUCTOR EN...

1. A semiconductor device package, comprising:a supporting element;
a transparent plate disposed on the supporting element;
a semiconductor device disposed under the transparent plate; and
a lid surrounding the transparent plate,
wherein the supporting element and the transparent plate define a channel, and
wherein the channel is in fluid communication with a space external to the semiconductor device package.

US Pat. No. 10,658,254

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor chip;
first and second electrodes provided on an upper surface of the semiconductor chip and spaced apart from each other;
a wiring member including a first joint bonded to the first electrode and a second joint bonded to the second electrode; and
resin sealing the semiconductor chip, the first and second electrodes and the wiring member,
wherein a hole extending through the wiring member up and down is provided between the first joint and the second joint.

US Pat. No. 10,658,253

SEMICONDUCTOR DEVICE INCLUDING A WARPED PRINTED CIRCUIT BOARD DISPOSED IN A CASE AND METHOD OF MANUFACTURING SAME

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a printed circuit board having a rectangular shape in a plan view, and having front and rear surfaces; and
a case having an installation area in which the printed circuit board is disposed, the printed circuit board being attached to the case using an adhesive bonding member that is interposed between the rear surface of the printed circuit board and the installation area of the case, the case having at least one projection that is disposed in the installation area, and that supports the printed circuit board to maintain a gap between the installation area of the case and the printed circuit board, the printed circuit board being warped with respect to a surface of the installation area, wherein
the adhesive bonding member is interposed between an entire area of the rear surface of the printed circuit board and an entire area of the installation area of the case, and
a distance between a surface of the installation area and the front surface of the printed circuit board at a center of the printed circuit board is different from a distance between the surface of the installation area and the front surface of the printed circuit board at an outer periphery of the printed circuit board.

US Pat. No. 10,658,252

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor structure comprising:a substrate comprising an active area having a first coefficient of thermal expansion (CTE); and
a dielectric layer adjacent the active area, the dielectric layer comprising:
a first region having a second CTE, the first region comprising a first dielectric material; and
a second region having a third CTE, the second region comprising the first dielectric material doped with a first dopant, wherein a difference between the third CTE and the first CTE is less than a difference between the second CTE and the first CTE, and wherein a concentration of the first dopant in the second region reaches a maximum value within an interior of the second region.

US Pat. No. 10,658,251

PROCESS OF FORMING SEMICONDUCTOR SUBSTRATE BY USE OF NORMALIZED REFLECTIVITY

SUMITOMO ELECTRIC DEVICE ...

1. A process of forming an epitaxial substrate, said process comprising:measuring first reflectivity being the reflectivity of a semiconductor substrate made of silicon carbide (SiC) by use of a monitoring beam with a wavelength from 350 to 720 nm;
growing a nucleus forming layer made of aluminum nitride (AIN) on the semiconductor substrate by use of a metal organic chemical vapor deposition (MOCVD) technique while measuring a second reflectivity being the reflectivity of the nucleus forming layer for the monitoring beam during the growth of the nucleus forming layer; and
ending the growing of the nucleus forming layer when the second reflectivity normalized by the first reflectivity enters a preset range from 0.92 to 0.935.

US Pat. No. 10,658,250

LIGHT IRRADIATION TYPE HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS

SCREEN HOLDINGS CO., LTD....

1. A method of heating a substrate by irradiating the substrate with a flash of light, said method comprising the steps of:(a) irradiating a front surface of a substrate supported by a susceptor in a chamber with a flash of light from a flash lamp, wherein partial thermal expansion occurs in the substrate due to the flash of light, causing the substrate to vibrate, and the vibration causes the substrate to bounce on the susceptor, creating a distance between said substrate and said susceptor;
(b) measuring a temperature of the front surface of said substrate at least after the irradiation with said flash of light to acquire a temperature profile of the front surface of said substrate;
(c) determining a highest measurement temperature in said temperature profile; and
(d) calculating the distance between said substrate and said susceptor when the substrate has the highest measurement temperature,
wherein in said step (d), the distance between said substrate and said susceptor is calculated based on a table showing a correlation between (1) a difference between the highest measurement temperature of said substrate and a reference measurement temperature and (2) the distance between said substrate and said susceptor, and
wherein a highest measurement temperature of a reference substrate measured when a pressure in said chamber is equal to a reference pressure is set as the reference measurement temperature.

US Pat. No. 10,658,249

METHODS FOR FABRICATING FINFET DEVICES HAVING GATE SPACERS ON FIELD INSULATING LAYERS

Samsung Electronics Co., ...

1. A method for fabricating a semiconductor device, the method comprising:forming a fin type pattern protruding from a substrate and extending in a first direction;
forming a field insulating layer covering a limited portion of the fin type pattern on the substrate, such that the field insulating layer exposes a separate limited portion of the fin type pattern;
forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction;
forming a first barrier layer in a first region of the field insulating layer subsequently to forming the gate structure, the first region exposed by the gate structure, the first region is adjacent to the gate structure and extending in the second direction, the first barrier layer including a nitrogen element; and
forming a gate spacer on the first barrier layer and on a side wall of the gate structure, subsequently to forming the first barrier layer, such that the first barrier layer is formed subsequently to forming the gate structure and prior to forming the gate spacer.

US Pat. No. 10,658,248

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor structure, comprising:providing a base substrate;
forming a gate structure over the base substrate;
forming a mask layer on a top surface of the gate structure;
forming pocket regions in the base substrate at both sides of the gate structure;
after forming the pocket regions, forming a first protective portion covering a top surface of the mask layer, exposing sidewall surfaces of the gate structure, and protruding from the sidewall surfaces of the gate structure, wherein forming the first protective portion comprises:
forming a protective layer over the base substrate, the mask layer and sidewall surfaces of the gate structure, wherein:
the protective layer includes the first protective portion over the mask layer and a second protective portion over the base substrate and the sidewall surfaces of the gate structure,
the protective layer is made of silicon nitride, and
a thickness of the protective layer is in a range of approximately 2 nm-10 nm;
removing the second protective portion; and
after forming the first protective portion, forming doped source/drain regions in the base substrate and portions of the pocket regions at both sides of the gate structure.

US Pat. No. 10,658,247

FINFET DEVICES AND METHODS OF FORMING

Taiwan Semiconductor Manu...

17. A method comprising:forming a first dielectric layer on a portion of a substrate;
forming a first fin on the first dielectric layer;
forming a second fin, a third fin, and a fourth fin extending from portions of the substrate exposed by the first dielectric layer, the first fin, the third fin, and the fourth fin comprising a first semiconductor material, the second fin comprising a second semiconductor material;
forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack, respectively, on the first fin, the second fin, the third fin, and the fourth fin;
simultaneously etching the second fin and the third fin to form recesses in the second fin and the third fin, the second fin being etched at a greater vertical rate and a greater lateral rate than the third fin;
simultaneously etching the first fin and the fourth fin to form recesses in the first fin and the fourth fin, the first fin being etched at a lesser vertical rate than the fourth fin, the first fin being etched at a same lateral rate as the fourth fin; and
epitaxially growing a first source/drain region, a second source/drain region, a third source/drain region, and a fourth source/drain region in, respectively, the recesses of the first fin, the second fin, the third fin, and the fourth fin.

US Pat. No. 10,658,246

SELF-ALIGNED VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REPLACEMENT GATE STRUCTURE

INTERNATIONAL BUSINESS MA...

1. A method of forming a vertical field effect transistor device, comprising:forming one or more fin stacks on a substrate, wherein the fin stacks include a lower junction plate, a vertical fin on the top surface of the lower junction plate, and an upper junction plate on the top surface of the vertical fin;
removing a portion of the lower junction plate and upper junction plate to form recessed spaces;
forming an inner spacer in the recessed spaces;
forming a sacrificial layer on the exposed surfaces of the vertical fin and the substrate;
forming a protective liner on the sacrificial layer and inner spacers; and
removing the portion of the sacrificial layer on the surface of the substrate to leave a hanging portion of the protective liner extending below the inner spacer.

US Pat. No. 10,658,245

ETCH PROFILE CONTROL OF POLYSILICON STRUCTURES OF SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method of forming a fin field effect transistor (finFET) on a substrate, the method comprising:forming a fin structure of the finFET on the substrate;
forming a first oxide region with a first thickness on a top surface of the fin structure, wherein forming the first oxide region comprises:
doping the fin structure;
depositing an oxide layer on the top surface and sidewalls of the fin structure; and
annealing the fin structure and the oxide layer;
forming a second oxide region with a second thickness on sidewalls on the fin structure, wherein the first thickness is greater than the second thickness,
forming a polysilicon structure on the first and second oxide regions;
forming a source/drain region on a portion of the fin structure; and
replacing the polysilicon structure with a gate structure.

US Pat. No. 10,658,244

SEMICONDUCTOR DEVICES HAVING FIN-SHAPED ACTIVE REGIONS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate comprising a device region defined by a trench in the substrate;
a plurality of fm-shaped active regions spaced apart from each other in the device region and extending in a first direction; and
a plurality of protruding patterns extending along a bottom surface of the trench, one of the plurality of protruding patterns extending from a lower end of a sidewall of the device region,
wherein adjacent ones of the plurality of fin-shaped active regions are spaced apart from each other at a first pitch in a second direction perpendicular to the first direction,
wherein the plurality of protruding patterns and the plurality of fin-shaped active regions are spaced apart from each other at a second pitch in the second direction, the second pitch being greater than the first pitch,
wherein the lower end of the sidewall of the device region comprises a first lower end of a first sidewall of the device region, and
wherein the one of the plurality of protruding patterns extends from the first lower end of the first sidewall to a second lower end of a second sidewall of the device region.

US Pat. No. 10,658,243

METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a replacement metal gate structure for an integrated circuit, the method comprising:providing an initial structure including a substrate, a first fin formed over the substrate and a second fin formed over the substrate, the first and second fins being laterally separated from one another, a first lower source/drain region positioned in the substrate such that the first fin is positioned on the first lower source/drain region, and a second lower source/drain region positioned in the substrate such that the second fin is positioned on the second lower source/drain region, the first lower source/drain region being laterally separated from the second lower source/drain region;
forming a first portion of a sacrificial material around the first fin, a second portion of the sacrificial material around the second fin, and a first dielectric region between the first and second portions of the sacrificial material, wherein an upper surface of the first portion of the sacrificial material is positioned below an upper surface of the first fin, an upper surface of the second portion of the sacrificial material is positioned below an upper surface of the second fin, and an upper surface of the first dielectric region is positioned below the upper surface of the first portion of the sacrificial material and below the upper surface of the second portion of the sacrificial material;
forming a first extended portion of the sacrificial material around the first fin and a second extended portion of the sacrificial material around the second fin;
forming a second dielectric region above the first dielectric region, the second dielectric region positioned between the first extended portion of the sacrificial material and the second extended portion of the sacrificial material;
removing an upper portion of the first extended portion and second extended portions of the sacrificial material to expose the first portion and the second portion of the sacrificial material, respectively, and an upper portion of the first fin and an upper portion of the second fin, respectively;
forming a first upper source/drain region from the exposed upper portion of the first fin and forming a second upper source/drain region from the exposed upper portion of the second fin;
forming a first mask above a first portion of the second dielectric region between the first fin and the second fin, the first mask extending partially over the first fin adjacent to the second dielectric region and the first mask extending partially over the second fin adjacent to the second dielectric region;
removing an exposed, second portion of the second dielectric region free from the first mask;
removing a remaining portion of the first and second portions of the sacrificial material to expose a lower portion of the first fin, expose a lower portion of the second fin, and expose the first dielectric region;
and
forming a replacement metal gate structure around the first and second fins, including areas between the first fin and the first dielectric region and between the second fin and the first dielectric region, and on top of the first dielectric region.

US Pat. No. 10,658,242

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH FIN STRUCTURES

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate;
forming first spacer elements over sidewalls of the first fin structure and sidewalls of the second fin structure;
partially removing the first fin structure and the second fin structure after the formation of the first spacer elements;
forming second spacer elements over sidewalls of the third fin structure, wherein each of the second spacer elements is taller than each of the first spacer elements, and the second spacer elements are formed before the first spacer elements;
partially removing the third fin structure after the formation of the second spacer elements; and
after the first fin structure, the second fin structure, and the third fin structure are partially removed, epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and an isolated semiconductor element is formed on the third fin structure.

US Pat. No. 10,658,241

METHOD OF FABRICATING INTEGRATED CIRCUIT

UNITED MICROELECTRONICS C...

1. A method of fabricating an integrated circuit, comprising:providing a first reticle, a second reticle, a third reticle and a substrate;
forming a first pattern on the substrate by using the first reticle, wherein the first pattern comprises a first feature and a first jog part protruding from and orthogonal to the first feature;
forming a second pattern on the substrate by using the second reticle, wherein the second pattern comprises a second feature, and the first feature is between the second feature and the first jog part; and
forming a third pattern on the substrate by using the third reticle, wherein the third pattern comprises a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.

US Pat. No. 10,658,240

SEMICONDUCTOR DIE SINGULATION

TEXAS INSTRUMENTS INCORPO...

1. A method for making a semiconductor device, comprising:forming stress induced dislocations in scribe lanes between semiconductor dies on a semiconductor wafer;
mounting a first side of the semiconductor wafer on a first side of a first dicing tape having an adhesive, forming a wafer dicing assembly;
attaching a first side of a second dicing tape that has an adhesive to a second side of the semiconductor wafer and to the first side of the first dicing tape in portions of the first dicing tape spaced from the semiconductor wafer;
separating the semiconductor dies one from another by simultaneously stretching the first dicing tape and stretching the second dicing tape to open gaps in the scribe lanes by extending the stress induced dislocations formed in the semiconductor wafer in the scribe lanes;
removing the second dicing tape from the semiconductor dies which are now singulated dies spaced from one another;
removing the singulated semiconductor dies from the first dicing tape;
positioning singulated semiconductor dies on die mount portions of a substrate in a substrate strip;
coupling leads of the substrate to bond pads on the semiconductor dies;
covering the semiconductor dies and at least a portion of the leads in mold compound;
cutting the substrate strip and the mold compound along saw streets to separate the semiconductor dies covered in mold compound and mounted to the substrate, forming separate packaged semiconductor devices each including a semiconductor die.

US Pat. No. 10,658,239

WAFER DICING METHOD

Semiconductor Manufacturi...

1. A wafer dicing method, comprising:performing grooving processing on a front surface of a wafer to form a dicing line;
sticking a protection tape on the front surface of the wafer after performing the grooving processing;
performing laser stealth dicing processing on the wafer from a back surface of the wafer after sticking the protection tape, wherein a dicing path of the laser stealth dicing is aligned with the dicing line;
performing grinding and thinning processing on the back surface of the wafer after performing the laser stealth dicing processing;
sticking a dicing tape on the back surface of the wafer after performing the grinding and thinning processing;
removing the protection tape after sticking the dicing tape; and
performing separation processing on the wafer after sticking the dicing tape after removing the protection tape;
wherein a metal layer is formed on the front surface of the wafer and in the step of performing grooving processing on the front surface of the wafer, the metal layer is etched to form the dicing line.

US Pat. No. 10,658,238

SEMICONDUCTOR PACKAGES HAVING AN ELECTRIC DEVICE WITH A RECESS

STMICROELECTRONICS PTE LT...

1. A method of forming a semiconductor package comprising:placing adhesive material between a back surface of an electric device and a surface of a substrate, a front surface of the electric device including a microelectromechanical sensor, the back surface being opposite the front surface, the back surface of the electric device including a recess that extends around an entire perimeter of the back surface; and
coupling the back surface of the electric device to the surface of the substrate using the adhesive material, wherein the coupling causes the adhesive material to completely fill the recess on the back surface of the electric device and to flow up a side surface of the electric device at the recess adhering the electric device to the substrate.

US Pat. No. 10,658,237

SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate;
a first gate structure and a second gate structure over the substrate;
a first hard mask on the first gate structure and a second hard mask on the second gate structure;
a third hard mask, disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask
a source-drain region between the first gate structure and the second gate structure; and
a conductive contact, disposed on and electrically connecting the source-drain region, wherein the third hard mask surrounds the conductive contact.

US Pat. No. 10,658,236

METHOD OF MANUFACTURING DISPLAY APPARATUS AND DISPLAY APPARATUS MANUFACTURED USING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a display apparatus, the method comprising:preparing a substrate comprising a display area and a pad area outside of the display area;
forming a sacrificial layer in the pad area such that the sacrificial layer does not extend into the display area;
forming an encapsulation layer over the display area and the pad area such that the encapsulation layer covers an end surface of the sacrificial layer in a direction to the display area;
forming cracks in at least a portion of the encapsulation layer by increasing a volume of the sacrificial layer or by gasifying or evaporating at least a portion of the sacrificial layer; and
removing at least a portion of the encapsulation layer in the pad area.

US Pat. No. 10,658,235

REWORK FOR METAL INTERCONNECTS USING ETCH AND THERMAL ANNEAL

International Business Ma...

1. A method for reworking metal interconnect structures, comprising:obtaining a structure including a dielectric layer having a top surface, a plurality of open-ended trenches extending within the dielectric layer, each of the trenches having opposing sidewalls, a first metal interconnect layer within the trenches, the first metal interconnect layer including voids therein, and a first diffusion barrier liner between the first metal interconnect layer and the dielectric layer;
etching the first metal interconnect layer within the trenches, thereby opening the voids within the first metal interconnect layer;
reflowing the first metal interconnect layer subsequent to opening the voids, thereby forming a substantially void-free bottom interconnect layer portion within and partially filling each of the trenches, there being an open space within each trench above a top surface of the bottom interconnect layer portion;
depositing a conformal layer of barrier material over the dielectric layer, the top surface of the bottom interconnect layer portion, and over the opposing sidewalls of the trenches above the top surface of the bottom interconnect layer portion;
forming a second diffusion barrier liner from the conformal layer of barrier material over the opposing sidewalls of the trenches above the top surface of the bottom interconnect layer portion, wherein forming the second diffusion barrier liner includes removing selected portions of the conformal layer of barrier material;
depositing a second metal interconnect layer within the trenches, the second metal interconnect layer being deposited on the bottom interconnect layer portion and between the opposing sidewalls of each of the trenches, the second diffusion barrier liner extending between the opposing sidewalls of each of the trenches and the second metal interconnect layer; and
planarizing the second metal interconnect layer.

US Pat. No. 10,658,234

FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:forming a dielectric layer over a semiconductor substrate;
forming an opening in the dielectric layer to expose a conductive element;
forming a conductive layer over the conductive element;
modifying an upper portion of the conductive layer using a plasma operation to form a modified region, wherein plasma used in the plasma operation comprises carbon-containing plasma; and
forming a conductive plug over the modified region to fill the opening, wherein the conductive plug is substantially made of a single-element metal, the conductive plug is in direct contact with the modified region, and there is no additional layer formed on the conductive layer to occupy space in the opening before the conductive plug is formed.

US Pat. No. 10,658,233

DIELECTRIC DAMAGE-FREE DUAL DAMASCENE CU INTERCONNECTS WITHOUT BARRIER AT VIA BOTTOM

International Business Ma...

1. A method for forming a copper (Cu) interconnect structure, the method comprising the steps of:forming a via and a trench in a dielectric over a metal line M1;
depositing a first barrier layer into, and lining, the via and the trench;
removing the first barrier layer from a bottom of the via and a bottom of the trench by selectively oxidizing portions of the first barrier layer along the bottom of the via and the bottom of the trench using neutral beam oxidation that does not damage the dielectric, and removing the portions of the first barrier layer that have been oxidized including at the bottom of the via such that the first barrier layer remains along only sidewalls of the via and the trench;
depositing Cu into the via in direct contact with the metal line M1 to form a via V1;
at least partially removing the first barrier layer that remains along the sidewalls of the trench;
lining the trench with a second barrier layer that covers a top of the via V1; and
depositing Cu into the trench over the second barrier layer to form a metal line M2.

US Pat. No. 10,658,232

INTERCONNECT STRUCTURE

UNITED MICROELECTRONICS C...

1. An interconnect structure, comprising:a substrate comprising an insulating material disposed thereon;
a conductive line disposed on the substrate and covered by the insulating material, the conductive line extending lengthwisely along a first direction from a top view;
a plurality of air gaps disposed in the insulating material and arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line;
a patterned hard mask disposed on the conductive line and having an edge extending along a second direction perpendicular to the first direction and passing between adjacent air gaps from the top view; and
a via structure formed on the conductive line, and the via structure electrically connected to the conductive line, wherein the insulating material comprises a first insulating layer on two sides of the conductive line, a second insulating on the first insulating layer, the patterned hard mask and the conductive line and a third insulating layer on the second insulating material and covering the air gaps, wherein a portion of the first insulating layer between the air gaps adjacent to the same side of the conductive line is completely covered by the patterned hard mask.

US Pat. No. 10,658,231

SEMICONDUCTOR DEVICE WITH AIR GAP BETWEEN WIRES AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
a first interlayer dielectric film on the substrate;
first and second wires having longitudinal directions respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction;
a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening; and
an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping vertically with the opening, the first and second portions of the air gap being adjacent to each other in the first direction,
wherein the hard mask pattern overhangs a portion of the air gap, while exposing portions of tops of the first and second wires.

US Pat. No. 10,658,230

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a substrate including a main zone and an extension zone;
vertical channel structures on the main zone, the vertical channel structures extending in a first direction perpendicular to a top surface of the substrate;
an electrode structure including gate electrodes stacked on the substrate; and
contacts connected to the gate electrodes in the extension zone, wherein
the gate electrodes include line regions and contact regions,
the line regions extend from the main zone toward, the extension zone along a second direction that is perpendicular to the first direction,
the contact regions are on ends of the line regions,
interfaces between the line regions and the contact regions are defined by a thickness transition, from a first thickness to a second thickness at terminal regions of the gate electrodes, measured from a lower surface of the gate electrodes to an upper surface of the gate electrodes,
the second thickness is greater than the first thickness, the contact regions have the second thickness,
one of the contacts is connected to a first region and a second region of a top surface of one of the contact regions, the first region is higher than the second region, and
the line regions include a recession on portions thereof adjacent to the contact regions.

US Pat. No. 10,658,229

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A method of manufacturing a semiconductor device comprising:laminating a first semiconductor wafer including a first substrate and a first insulating layer which is formed so as to come into contact with one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer which is formed so as to come into contact with one surface of the second substrate and bonding the first semiconductor wafer and the second semiconductor wafer to each other;
forming a third insulating layer on the other surface of a side opposite to the one surface of the first substrate; penetrating the third insulating layer, the first substrate, and the first insulating layer, performing etching so as that the second insulating layer remains on a second wiring layer which is formed in the second insulating layer, and forming a first connection hole;
forming an insulating film on the first connection hole;
performing etching of the second insulating layer on the second wiring layer and the insulating film, forming a second connection hole, and exposing the second wiring layer; and
forming a first via which is formed in inner portions of the first and the second connection holes and is connected to the second wiring layer,
wherein a diameter of the first connection hole which is formed on the other surface of the first substrate is greater than a diameter of the first connection hole which is formed on the third insulating layer.

US Pat. No. 10,658,228

SEMICONDUCTOR SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:a substrate;
an oxide layer disposed over the substrate;
a first epitaxial layer disposed over the oxide layer and having a first conductivity type;
a second epitaxial layer disposed over the first epitaxial layer and having a second conductivity type that is opposite to the first conductivity type;
a third epitaxial layer disposed over the second epitaxial layer and having the first conductivity type;
a fourth epitaxial layer disposed between the second epitaxial layer and the third epitaxial layer, and having the first conductivity type; and
a fifth epitaxial layer disposed between the fourth epitaxial layer and the third epitaxial layer, and having the second conductivity type.