US Pat. No. 10,600,789

MICRO-PATTERN FORMING METHOD, CAPACITOR AND METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate;
a plurality of bottom electrodes passing through a supporting layer on the substrate;
a dielectric layer-on each of the plurality of bottom electrodes;
a top electrode on the dielectric layer,
wherein the plurality of bottom electrodes are respectively at positions of vertexes of a triangle, and
the supporting layer includes a through-hole at a position corresponding to a centroid of the triangle.

US Pat. No. 10,600,788

INTEGRATED ASSEMBLIES COMPRISING STUD-TYPE CAPACITORS

Micron Technology, Inc., ...

1. An integrated assembly, comprising:conductive pillars supported by a base and included within first electrodes of capacitors; the conductive pillars having first upper surfaces;
dielectric liners along outer surfaces of the conductive pillars; the dielectric liners having second upper surfaces;
conductive liners along the dielectric liners and included within second electrodes of the capacitors; the conductive liners having third upper surfaces;
the first upper surfaces being beneath the third upper surfaces;
insulative pads being over the first upper surfaces and having fourth upper surfaces;
the second upper surfaces, third upper surfaces and fourth upper surfaces being substantially coplanar with one another; and
a conductive plate extending across the insulative pads and laterally outwardly from the conductive liners; the conductive plate electrically coupling the conductive liners to one another.

US Pat. No. 10,600,787

SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION

Intel Corporation, Santa...

1. An apparatus comprising:a silicon substrate comprising a trench;
a gallium nitride material in the trench of the silicon substrate;
a source electrode on the gallium nitride material;
a drain electrode on the gallium nitride material;
a gate electrode on the gallium nitride material between the source electrode and the drain electrode; and
an island of oxide in the trench, the island of oxide having a long axis in a direction substantially parallel to a [11?2] direction of the silicon substrate and being adjacent to a further trench,
wherein the further trench exposes one or both of the silicon substrate and a gallium nitride seed layer on the silicon substrate, and
wherein the further trench is filled with the gallium nitride material.

US Pat. No. 10,600,786

METHOD FOR FABRICATING A DEVICE WITH A TENSILE-STRAINED NMOS TRANSISTOR AND A UNIAXIAL COMPRESSION STRAINED PMOS TRANSISTOR

STMICROELECTRONICS Inc, ...

1. A method for making a transistor device with at least a P type transistor provided with a transistor channel structure with uniaxial compressive strain, the method comprising:forming a mask on a first region of a silicon surface layer of a strained silicon-on-insulator (sSOI) type of substrate comprising a support layer, an insulating layer separating the support layer from the surface layer, the surface layer being based on a strained semiconducting silicon material, strained with a biaxial tensile strain, the mask being formed from plural elongated mask blocks located on first zones of the surface layer, the first zones and the mask blocks having a length L1 measured parallel to a first direction and a width W1 measured parallel to a second direction perpendicular to the first direction, the width W1 being such that W1 making at least one ion implantation of the surface layer through the elongated openings in the mask, so as to make the second zones amorphous and to induce a relaxation of the first zones in the second direction while keeping the first zones strained in the first direction;
recrystallising the second zones of the surface layer after making the at least one ion implantation of the surface layer; then
making a second mask formed of elements located on each side of and adjacent to the mask blocks; then
removing the mask blocks between the elements of the second mask so as to form cavities exposing the first zones; then
germanium-enriching the first zones, so as to induce a compressive strain of the first zones in the second direction and to have the first zones relaxed in the first direction; and then
forming replacement gate blocks in the cavities on the first zones of the surface layer, the pate blocks extending parallel to the second direction.

US Pat. No. 10,600,785

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

QUALCOMM Incorporated, S...

1. A complementary metal oxide semiconductor (CMOS) device including a plurality of p-type metal oxide semiconductor (PMOS) transistors each having a PMOS drain and a plurality of n-type metal oxide semiconductor (NMOS) transistors each having an NMOS drain, comprising:a first interconnect on an interconnect level connecting a first subset of the PMOS drains together;
a second interconnect on the interconnect level connecting a second subset of the PMOS drains together, the second subset of the PMOS drains being different than the first subset of the PMOS drains, the first interconnect and the second interconnect being disconnected on the interconnect level;
a third interconnect on the interconnect level connecting a first subset of the NMOS drains together;
a fourth interconnect on the interconnect level connecting a second subset of the NMOS drains together, the second subset of the NMOS drains being different than the first subset of the NMOS drains, the third interconnect and the fourth interconnect being disconnected on the interconnect level, wherein the first interconnect, the second interconnect, the third interconnect, and the fourth interconnect are coupled together through at least one other interconnect level; and
one or more additional interconnects on the interconnect level connecting at least the first interconnect to the third interconnect together, and the second interconnect to the fourth interconnect together, to provide one or more parallel current paths with a current path through the at least one other interconnect level.

US Pat. No. 10,600,784

SEMICONDUCTOR INTEGRATED CIRCUIT AND LOGIC CIRCUIT

Socionext Inc., Kanagawa...

1. A semiconductor integrated circuit comprising a standard cell having a NAND function, the standard cell comprising:first and second n-channel transistors connected together in series between an output node and a ground node, and
first and second p-channel transistors connected together in parallel between the output node and a power supply node,
wherein the first n-channel transistor is comprised of n fin transistor(s) where n is an integer equal to or greater than one, the first n-channel transistor having its gate connected to a first input node, the n fin transistor(s) forming the first n-channel transistor comprising a first fin extending in a first direction and a first gate extending in a second direction perpendicular to the first direction,
the second n-channel transistor is comprised of m fin transistors where m is an integer greater than n, the second n-channel transistor having its gate connected to a second input node, the m fin transistors forming the second n-channel transistor comprising a second fin extending in the first direction and a second gate extending in the second direction,
the first p-channel transistor having its gate connected to the first input node, and
the second p-channel transistor having its gate connected to the second input node.

US Pat. No. 10,600,783

SELF-CUT SIDEWALL IMAGE TRANSFER PROCESS

International Business Ma...

1. A semiconductor structure comprising:a set of first structures formed on a first region of a silicon substrate, wherein each of the first structures comprises a mandrel having a first hardmask disposed on a top surface thereof, wherein the mandrel has a first width and a first height;
a set of second structures formed on a second region of the silicon substrate, wherein each of the second structures comprises a mandrel having a second hardmask disposed on a top surface thereof and an oxide layer disposed on the hardmask, wherein the mandrel has a second width and a second height;
a set of third structures formed on a third region of the silicon substrate, wherein each of the third structures comprises a mandrel having a third hardmask disposed on a top surface thereof, wherein the mandrel has a third width and a third height;
wherein the set of first structures and the set of third structures are separated by the set of second structures and further wherein the second width is greater than the first width and the third width.

US Pat. No. 10,600,782

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
an upper surface electrode disposed on an upper surface of the semiconductor substrate; and
a lower surface electrode disposed on a lower surface of the semiconductor substrate,
wherein
the semiconductor substrate comprises:
a diode region; and
an IGBT region provided adjacent to the diode region,
the diode region comprises:
a first conductive-type anode region provided in a portion disposed at the upper surface of the semiconductor substrate;
a second conductive-type cathode region provided in a portion disposed at the lower surface of the semiconductor substrate; and
a second conductive-type diode drift region provided between the anode region and the cathode region,
the IGBT region comprises:
a second conductive-type emitter region provided in a portion disposed at the upper surface of the semiconductor substrate;
a first conductive-type collector region provided in a portion disposed at the lower surface of the semiconductor substrate;
a second conductive-type IGBT drift region provided between the emitter region and the collector region, and provided adjacent to the diode drift region;
a first conductive-type body region provided between the emitter region and the IGBT drift region;
a gate trench extending from the upper surface of the semiconductor substrate to a depth reaching the IGBT drift region through the emitter region and the body region;
a second conductive-type buffer region provided between the IGBT drift region and the collector region and having a higher impurity concentration than the IGBT drift region; and
a plurality of first conductive-type low concentration regions provided between the buffer region and the collector region, arranged with intervals therebetween in a direction parallel to the semiconductor substrate, and having a lower impurity concentration than the collector region,
a gate electrode is disposed in the gate trench, and
the collector region comprises a first contact portion that is in contact with the buffer region between the low concentration regions adjacent to each other.

US Pat. No. 10,600,781

MULTI-STACK THREE-DIMENSIONAL MEMORY DEVICES

Yangtze Memory Technologi...

1. A three-dimensional (3D) memory device, comprising:a first device chip, comprising:
a peripheral device; and
a first interconnect layer;
a second device chip, comprising:
a substrate;
two memory stacks disposed on opposite sides of the substrate;
two memory strings each extending vertically through one of the two memory stacks; and
a second interconnect layer; and
a bonding interface formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.

US Pat. No. 10,600,780

3D CHIP SHARING DATA BUS CIRCUIT

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate;
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate; and
a data input/output (I/O) circuit defined on the second semiconductor substrate to receive data from and to supply data to at least a first external circuit outside of the 3D circuit,
wherein data signals from the data I/O circuit are supplied from the second IC die to a first set of circuits defined on the first IC die.

US Pat. No. 10,600,779

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface, and including a transistor region forming a transistor extending from said first main surface to said second main surface and a diode region forming a diode extending from said first main surface to said second main surface; and
a first electrode disposed on said first main surface of said semiconductor substrate over said transistor region and said diode region, wherein
said semiconductor substrate includes a MOS gate structure on a first main surface side in said transistor region,
said semiconductor device includes:
an interlayer dielectric covering a gate electrode of said MOS gate structure, and having a contact hole exposing a semiconductor layer of said MOS gate structure; and
a barrier metal disposed in said contact hole,
said first electrode enters said contact hole, is in contact with the semiconductor layer of said MOS gate structure through said barrier metal in said contact hole, and is in direct contact with a semiconductor layer in said diode region of said semiconductor substrate,
said barrier metal includes titanium nitride, titanium carbide, or titanium silicide, and
no barrier metal is disposed on said first main surface of said semiconductor substrate in said diode region.

US Pat. No. 10,600,778

METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device comprising:receiving a substrate structure including a substrate, the substrate structure further including a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate, the substrate structure further including a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion;
applying a mask to the portion of the bottom spacer formed on the first bottom source/drain of the vertical transistor portion;
removing the portion of the bottom spacer formed on the second bottom source/drain of the varactor portion;
removing the mask from the portion of the bottom spacer formed on the first bottom source/drain of the vertical transistor portion; and
depositing a gate oxide on the vertical transistor portion and the varactor portion.

US Pat. No. 10,600,777

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising:a semiconductor body including a first semiconductor layer of a first conductivity type;
a first electrode provided on the semiconductor body;
a second electrode provided on the semiconductor body with a first insulating film interposed, the second electrode being provided at a position surrounded with the first electrode when viewed from above, and being separated from the first electrode;
a third electrode provided on the semiconductor body at a position surrounded with the second electrode when viewed from above, and being separated from the second electrode; and
a control electrode provided between the semiconductor body and the first electrode, the control electrode being electrically connected to the second electrode, the control electrode being electrically insulated from the semiconductor body with a second insulating film interposed, and being electrically insulated from the first electrode with a third insulating film interposed,
the semiconductor body further including a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, and a sixth semiconductor layer of the first conductivity type,
the second semiconductor layer being selectively provided between the first semiconductor layer and the first electrode,
the third semiconductor layer being selectively provided between the second semiconductor layer and the first electrode and electrically connected to the first electrode,
the fourth semiconductor layer including a major portion and an outer edge portion, the major portion being provided between the first semiconductor layer and the second electrode and between the first semiconductor layer and the third electrode, the outer edge portion being provided between the first semiconductor layer and the first electrode,
the fifth semiconductor layer being selectively provided in the fourth semiconductor layer, the fifth semiconductor layer being positioned between the outer edge portion of the fourth semiconductor layer and the first electrode, and including a portion electrically connected to the first electrode,
the sixth semiconductor layer being provided at a position away from the fifth semiconductor layer in the fourth semiconductor layer, the sixth semiconductor layer being positioned between the major portion of the fourth semiconductor layer and the third electrode, and including a portion electrically connected to the third electrode,
the control electrode being disposed at a position capable of facing the first semiconductor layer, the second semiconductor layer and the third semiconductor layer with the second insulating film interposed.

US Pat. No. 10,600,776

DEVICE AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:a first bipolar device connected to a first node;
a second bipolar device connected to the first bipolar device and to a second node; and
a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes, wherein the first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure, wherein the deep well structure comprises a deep N-well layer that is formed on top of a substrate layer and below an N-well, and wherein the N-well is in contact with the deep N-well layer and in contact with the substrate layer.

US Pat. No. 10,600,775

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Macronix International Co...

1. An electrostatic discharge protection device comprising:a semiconductor substrate;
a first N-type doped well and a second N-type doped well on the substrate, each of the first N-type doped well and the second N-type doped well comprising a first N+ region and a first P+ region;
a P-type doped well between the first N-type doped well and the second N-typed doped well on the substrate, the P-type doped well comprising a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and
a first contact and a second contact positioned above a surface of the first N-type doped well and above a surface of the second N-type doped well, respectively, between the first N+ region and the first P+ region;
a poly resistor connected between the first N-type doped well and the second N-typed doped well.

US Pat. No. 10,600,774

SYSTEMS AND METHODS FOR FABRICATION OF GATED DIODES WITH SELECTIVE EPITAXIAL GROWTH

QUALCOMM Incorporated, S...

1. An integrated circuit (IC) comprising:a logic region comprising at least one Field-Effect Transistor (FET), the at least one FET comprising a plurality of FET fins, each of the plurality of FET fins comprising a respective FET fin epitaxial bump; and
an input/output (I/O) region comprising at least one I/O gated diode, the at least one I/O gated diode comprising a plurality of diode fins, wherein at least one of the plurality of diode fins comprises a source and a drain, and wherein at least one of the source and the drain does not comprise an epitaxial bump.

US Pat. No. 10,600,773

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device manufacturing method comprising:forming a chip stacked body by stacking a second semiconductor chip on a first surface of a first semiconductor chip, a first bump electrode being between and contacting the first surface and the second semiconductor chip, and stacking a third semiconductor chip on the second semiconductor chip, a second bump electrode being between and contacting the second semiconductor chip and the third semiconductor chip;
stacking a fourth semiconductor chip on the chip stacked body;
connecting the first bump electrode to a first through silicon via of the second semiconductor chip by reflowing the first bump electrode;
connecting the second bump electrode to the first through silicon via of the second semiconductor chip and a second through silicon via of the third semiconductor chip by reflowing the second bump electrode;
connecting the chip stacked body to a first substrate by using a first adhesive such that the first surface of the first semiconductor chip faces a second surface of the first substrate;
connecting the chip stacked body to a second substrate by using a second adhesive and a third bump electrode, the second adhesive being provided between the chip stacked body and the second substrate, in a direction perpendicular to the second substrate, and between the third bump electrode and the fourth semiconductor chip in a direction parallel to the second substrate, such that a gap is left between the chip stacked body and the second substrate and between the fourth semiconductor chip and the second substrate; and
after connecting the chip stacked body to the second substrate by using the second adhesive and the third bump electrode, sealing the second surface, the first, second, third, and fourth semiconductor chips with a resin that also enters the gap left between the chip stacked body and the second substrate and between the fourth semiconductor chip and the second substrate.

US Pat. No. 10,600,772

SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Micron Technology, Inc., ...

1. An apparatus comprising:a first semiconductor chip comprising:
a first plurality of memory cell arrays, each disposed on an associated one of intersections of first and second signal lines;
a first plurality of bonding electrodes electrically connected respectively to corresponding first signal lines; and
a first plurality of switches configured to respectively couple one of the second signal lines to a corresponding one of the first plurality of bonding electrodes; and
a second semiconductor chip comprising:
a second plurality of memory cell arrays, each disposed on an associated one of intersections of third and fourth signal lines;
a second plurality of bonding electrodes respectively coupled to the first plurality of bonding electrodes of the first semiconductor chip and electrically connected respectively to corresponding third signal lines;
a third plurality of bonding electrodes electrically connected respectively to corresponding third signal lines and coupled to a logic chip; and
a second plurality of switches configured to respectively couple one of the fourth signal lines to a corresponding one of the second and third plurality of bonding electrodes;
wherein the first and second plurality of switches are configured to turn on/off so that one memory cell array of the first semiconductor chip and the second semiconductor chip is accessed through a corresponding one of the third plurality of bonding electrodes to the logic chip.

US Pat. No. 10,600,771

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first interconnection including a first extending portion that extends in a first direction, and a first curved portion that is curved with respect to the first extending portion;
a second interconnection including a second extending portion that extends in the first direction and is adjacent to the first extending portion in a second direction perpendicular to the first direction, and a second curved portion that is curved with respect to the second extending portion;
a first plug provided on the first curved portion, or provided on a first non-opposite portion that is included in the first extending portion and is not opposite to the second extending portion in the second direction; and
a second plug provided on the second curved portion, or provided on a second non-opposite portion that is included in the second extending portion and is not opposite to the first extending portion in the second direction.

US Pat. No. 10,600,770

SEMICONDUCTOR DICE ASSEMBLIES, PACKAGES AND SYSTEMS, AND METHODS OF OPERATION

Micron Technology, Inc., ...

1. An assembly, comprising:an interposer comprising a glass material;
a semiconductor die comprising a logic die having a proximity coupling on a side of the interposer; and
at least one other semiconductor die comprising a proximity coupling configured for
communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer, the at least one other die comprising a number of stacked memory dice, each of the logic die and the memory dice comprising a proximity coupling for mutual signal communication;
wherein:
the logic die is in electrically conductive communication with conductive traces of the interposer for communicating power and ground/bias;
the number of stacked memory dice comprises memory dice stacked in stair-step fashion with exposed bond pads on treads of stairs; and
further comprising wire bonds respectively extending from the exposed bond pads to conductive traces of the interposer for communicating power and ground/bias; and
the interposer comprises an optical waveguide for signal communication with an optical I/O of the logic die and extends to a socket for optical signal communication with higher level packaging.

US Pat. No. 10,600,769

ELECTRONIC COMPONENT

AIROHA TECHNOLOGY GROUP, ...

1. An electronic component, comprising:a substrate comprising a metal layer and at least one via connecting with the metal layer;
an III-V die disposed on the metal layer; and
a silicon die stacked to the III-V die, the silicon die comprises a plurality of conductive contacts on an active surface of the silicon die, and the silicon die is coupled to the III-V die in a face-down orientation and electrically connected to the III-V die via the conductive contacts,
wherein the active surface of the silicon die faces toward the substrate.

US Pat. No. 10,600,768

LIGHT EMITTING DEVICE WITH LED STACK FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME

Seoul Viosys Co., Ltd., ...

1. A light emitting device for a display, comprising:a first substrate;
a first LED sub-unit disposed under the first substrate;
a second LED sub-unit disposed under the first LED sub-unit;
a third LED sub-unit disposed under the second LED sub-unit;
a first transparent electrode interposed between the first and second LED sub-units, and in ohmic contact with a lower surface of the first LED sub-unit;
a second transparent electrode interposed between the second and third LED sub-units, and in ohmic contact with a lower surface of the second LED sub-unit;
a third transparent electrode interposed between the second transparent electrode and the third LED sub-unit, and in ohmic contact with an upper surface of the third LED sub-unit;
at least one current spreader connected to at least one of the first, second, and third LED sub-units;
electrode pads disposed on the first substrate; and
through-hole vias formed through the first substrate to electrically connect the electrode pads to the first, second, and third LED sub-units,
wherein at least one of the through-hole vias is formed through the first substrate, the first LED sub-unit, and the second LED sub-unit.

US Pat. No. 10,600,767

MAKING SEMICONDUCTOR DEVICES BY STACKING STRATA OF MICRO LEDS

Hong Kong Beida Jade Bird...

1. A method for fabricating a micro-LED display chip, comprising:providing a substrate supporting an array of pixel drivers; and
fabricating two or more strata stacked on top of the substrate and pixel drivers, with a planar interface between adjacent strata, by:
for a bottom stratum: bonding, using metal layers, an unpatterned epitaxial structure on top of the substrate and pixel drivers; and for any other stratum: bonding, using metal layers, an unpatterned epitaxial structure on top of a previous stratum;
patterning the epitaxial structure to form micro LEDs and patterning the bonding metal layers to form metal pads, some of the metal pads functioning as lower contact metal pads electrically connected to bottoms of the micro LEDs;
for all strata except a top stratum, filling and planarizing the stratum to create a planar top interface, the top interface including electrical connections to tops of the micro LEDs;
filling and planarizing the top stratum to create a planar top interface, the planar top interface including electrical connections to tops of the micro LEDs; and
fabricating a common electrode on top of the planar top interface of the top stratum, the tops of the micro LEDs electrically connected to the common electrode, wherein the common electrode is further electrically connected to one or more of the metal pads of the bottom stratum.

US Pat. No. 10,600,766

DUAL-CHANNEL HEAT-CONDUCTING ENCAPSULATION STRUCTURE AND ENCAPSULATION METHOD OF A SOLID-STATE PHOSPHOR INTEGRATED LIGHT SOURCE

FUJIAN CAS-CERAMIC OPTOEL...

1. A solid-state phosphor integrated light source, comprising a solid-state phosphor, a transparent organic silica gel, a plurality of LED chips, a plurality of heat-conducting columns, and a substrate,wherein each of the plurality of heat-conducting columns has a first end in contact with the solid-state phosphor and a second end in contact with the substrate so as to form a pap between the solid-state phosphor and the substrate, wherein the plurality of LED chips are disposed on the substrate inside the gap, the transparent organic silica gel fills a space in the gap, and
wherein each of the plurality of heat-conducting columns is located in an interspace between two or more of the plurality of LED chips.

US Pat. No. 10,600,765

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a plurality of semiconductor chips provided on a circuit pattern within a case defined by an outer frame in a plan view, said case having a longer side extending along a longer-side direction and a shorter side that is shorter than said longer side and extends along a shorter-side direction that is transverse to the longer-side direction and within the same plane as the longer-side direction;
bonding wires for electrically connecting said plurality of semiconductor chips and said circuit pattern together;
a plurality of main electrodes provided within said case and disposed to extend along the longer-side direction of said case; and
two complex elements, each of said complex elements including two of said plurality of semiconductor chips connected to each other,
wherein one of said two complex elements is configured such that said two of said plurality of semiconductor chips are connected by a plurality of the bonding wires via a via-circuit pattern provided on a place interposed between said two of said plurality of semiconductor chips in a plan view, and
wherein another one of said two complex elements is configured such that said two of said plurality of semiconductor chips of said another one of said two complex elements are connected directly by another plurality of the bonding wires,
wherein each said main electrode is disposed proximate to an edge of said longer side extending in the longer-side direction of said case and spaced away from said complex elements at a location between said edge of said longer side and said complex elements,
wherein said plurality of semiconductor chips are arranged along the longer-side direction of said case,
wherein said bonding wires are strung along the longer-side direction of said case,
wherein each said main electrode is disposed in a vicinity of one of sides extending in the longer-side direction of said case,
wherein each said main electrode and said circuit pattern are connected together by ultra-sonic bonding, soldering, or brazing,
wherein said case has a recessed portion on a top surface of said case, and
wherein each said main electrode has an edge extended from said recessed portion and bent at a bend location of said main electrode such that said edge extends from said bend location to a free end of said edge in an inward direction of said case toward said circuit pattern in a plan view in said recessed portion, and said free end of said edge overlaps said circuit pattern and said bend location is proximate to said longer side of said case.

US Pat. No. 10,600,764

SEMICONDUCTOR POWER MODULE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor power module comprising:an insulating substrate having one surface and another surface;
an output side terminal arranged at a one surface side of the insulating substrate;
a first power supply terminal arranged at the one surface side of the insulating substrate;
a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at an other surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate;
a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal; and
a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal;
wherein a direction of a current flowing through the first power supply terminal and a direction of a current flowing through the second power supply terminal are made opposite across the insulating substrate.

US Pat. No. 10,600,763

MULTI-DECK THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a first substrate;
forming a first channel structure extending vertically through the first dielectric deck;
forming a heterogeneous interface in a second substrate;
bonding the second substrate and the first substrate in a face-to-face manner;
splitting a single-crystal silicon layer from the second substrate along the heterogeneous interface in the second substrate to leave the single-crystal silicon layer bonded on the first dielectric deck;
patterning a first inter-deck plug comprising single-crystal silicon in the single-crystal silicon layer, such that the first inter-deck plug is above and in contact with the first channel structure;
forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers above the first inter-deck plug;
forming a second channel structure extending vertically through the second dielectric deck, such that the second channel structure is above and in contact with the first inter-deck plug; and
forming a first memory deck and a second memory deck each comprising interleaved conductor layers and the dielectric layers by replacing the sacrificial layers in the first dielectric deck and the second dielectric deck with the conductor layers.

US Pat. No. 10,600,762

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus comprising a first die and a second die, each of the first and second dies including a face-side and a back-side, the face-side of the first die being defined by first and second edges substantially parallel to each other, and the face-side of the second die being defined by third and fourth edges substantially parallel to each other;wherein the first die comprises, on the face-side thereof:
at least one first interconnection region between the first and second edges;
at least one first probe pad between the at least one first interconnection region and the first edge at a position that is closer to the at least one first interconnection region than the first edge;
at least one first coupling region between the at least one first interconnection region and the second edge; and
at least one first redistribution wiring including a first portion electrically coupling the at least one first interconnection region to the at least one first probe pad and a second portion electrically coupling the at least one first interconnection region to the at least one first coupling region;
wherein the second die comprises, on the face-side thereof:
at least one second interconnection region between the third and fourth edges;
at least one second probe pad between the at least one second interconnection region and the fourth side edge at a position that is closer to the at least one second interconnection region than the fourth edge;
at least one second coupling region between the at least one second interconnection region and the at least one second probe pad; and
at least one second redistribution wiring including a third portion electrically coupling the at least one second interconnection region to the at least one second coupling region and a fourth portion electrically coupling the at least one coupling region to the at least one second probe pad;
wherein a distance between the at least one first interconnection region and the at least one first probe pad is substantially equal to a distance between the at least one second interconnection region and the at least one second probe pad; and
wherein the first die is bonded to the second die in a face-to-face relationship such that the at least one first interconnection region and the at least one second interconnection region are between the at least one first probe pad and the at least one second probe pad, and the at least one first coupling region is electrically coupled to the at least one second coupling region.

US Pat. No. 10,600,761

NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;
removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;
filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;
joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;
removing the substrate from the second surface of the insulating layer;
joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer; and
forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors, wherein the plurality of nanoscale conductors are arranged without regard to a specific alignment of the plurality of nanoscale conductors to either the plurality of first element contacts or the plurality of second element contacts.

US Pat. No. 10,600,760

ULTRATHIN LAYER FOR FORMING A CAPACITIVE INTERFACE BETWEEN JOINED INTEGRATED CIRCUIT COMPONENT

Invensas Corporation, Sa...

1. A wafer-level package, comprising:first and second integrated circuit dies, each integrated circuit die
interfacing a single ultrathin layer of a first dielectric material between respective bonding surfaces of the first and second integrated circuit dies, each respective bonding surface partly comprising respective second dielectric layers of a second dielectric material;
each integrated circuit die comprising at least one conductive pad recessed from each respective bonding surface, wherein the respective conductive pads of the first and second integrated circuit dies are on opposing sides of the single ultrathin layer of the first dielectric material;
an instance of a third layer of a third dielectric material between each recessed conductive pad and each respective bonding surface of the first and second integrated circuit dies, each instance of the third layer of the third dielectric material filling-in respective recesses between the respective recessed conductive pads and the respective bonding surfaces;
a total thickness of the single ultrathin layer of the first dielectric material and two respective instances of the third layer of the third dielectric material being 25 nanometers or less, wherein the total thickness also comprises a distance between the respective recessed conductive pads on opposing sides of the single ultrathin layer;
a capacitive interface comprising the single ultrathin layer of the first dielectric material, the two respective instances of the third layer of the third dielectric material in the respective recesses, and the respective recessed conductive pads of the first and second integrated circuit dies;
a conductive power connection between the first and second integrated circuit dies, the conductive power connection disposed only through the second layer of the second dielectric material and through the single ultrathin layer of the first dielectric material; and
a conductive ground connection between the first and second integrated circuit dies, the conductive ground connection disposed only through the second layer of the second dielectric material and through the single ultrathin layer of the first dielectric material.

US Pat. No. 10,600,759

POWER AND GROUND DESIGN FOR THROUGH-SILICON VIA STRUCTURE

ADVANCED SEMICONDUCTOR EN...

11. A semiconductor package, comprising:a first substrate;
a semiconductor device on the first substrate and comprising:
a second substrate including a first surface and a second surface opposite the first surface;
active circuitry on the first surface of the second substrate;
a first conductive layer extending from the second surface of the second substrate toward the active circuitry and electrically connected to the active circuitry and defining a space in the semiconductor device; and
an encapsulation layer in the space defined in the semiconductor device,
wherein the active circuitry comprises a second conductive layer and a first dielectric layer, wherein the second conductive layer comprises a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer.

US Pat. No. 10,600,758

SEMICONDUCTOR SENSOR PACKAGE

STMICROELECTRONICS PTE LT...

1. A method, comprising: forming a plurality of through holes in a substrate, the substrate including a first surface and a second surface;forming a plurality of first trenches in the first surface of the substrate, each first trench of the plurality of first trenches being substantially parallel to each other, each first trench of the plurality of first trenches is overlapping and aligned with a number of through holes of the plurality of through holes;
forming a plurality of second trenches in the first surface of the substrate, each second trench of the plurality of second trenches being transverse to the plurality of first trenches and overlapping at least one of the through holes of the plurality of through holes; and
forming a non-conductive material in the plurality of through holes, the plurality of first trenches, and the plurality of second trenches.

US Pat. No. 10,600,757

SEMICONDUCTOR PACKAGE

Chengwei Wu, New Taipei ...

1. A semiconductor package, comprising:a first die, the first die having an active surface and a back surface, the first die comprising a first connection end and a second connection end on the active surface, the first connection end being closer to a side edge of the first die than the second connection end;
a second die, the second die having an active side and a back side, the second die comprising a third connection end and a fourth connection end on the active surface, the fourth connection end being closer to a side edge of the second die than the third connection end;
a first set of metal pillars;
a second set of metal pillars;
a first redistribution structure, the first redistribution structure comprising at least two insulating layers, a first trace, and a second trace, the first die being connected to the first redistribution structure through the first set of metal pillars, the second die being connected to the first redistribution structure through the second set of metal pillars, the first trace being connected between the first connection end and the third connection end, the second trace being connected between the second connection end and the fourth connection end; and
a first molding material, wherein the first molding material is beside the first die and the second die.

US Pat. No. 10,600,756

WIRE BONDING TECHNIQUE FOR INTEGRATED CIRCUIT BOARD CONNECTIONS

United States of America,...

1. A method for connecting a chip die to a circuit board with a capillary dispenser to deposit gold, said dispenser forming a free air ball (FAB) at a depositing tip, said method comprising:forming a first bond by depositing the gold at the FAB from the tip to a board pad on the circuit board;
forming a second bond by depositing the gold at the FAB from the tip to a die pad on the chip die;
extruding a filament of the gold by the tip in a normal direction from said second bond;
rotating said filament laterally away from said first bond along a first radius;
extruding said filament while rotating said filament towards said first bond along a second radius; and
forming a third bond by depositing the gold at the FAB by the tip on said first bond to form said third bond.

US Pat. No. 10,600,755

METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY

Amkor Technology, Inc., ...

11. A method of manufacturing an electronic device, the method comprising:providing a substrate comprising a substrate conductive interconnection structure;
providing a semiconductor die comprising a die conductive interconnection structure protruding from a first side of the die; and
pressing a first surface of the die conductive interconnection structure and a first surface of the substrate conductive interconnection structure together with an interface layer comprising at least one layer of ink at an interface between the first surface of the die conductive interconnection structure and the first surface of the substrate conductive interconnection structure,
wherein after said pressing, the interface layer has a substantially consistent thickness,
wherein said pressing comprises performing said pressing utilizing a thermocompression bonding process.

US Pat. No. 10,600,754

BONDING METHOD

KAIJO CORPORATION, Tokyo...

1. A bonding method using a bonding apparatus including a rotation drive mechanism for rotating a bonding stage about a ?-axis, the method comprising the steps of:(e) locking said bonding stage with respect to said ?-axis, and bonding a wire or bump onto a certain area of a substrate held on said bonding stage;
(f) unlocking the bonding stage with respect to said ?-axis, and rotating said bonding stage about said ?-axis with said rotation drive mechanism; and
(g) locking said bonding stage with respect to said ?-axis, and bonding a wire or bump onto a remaining region of said substrate.

US Pat. No. 10,600,753

FLIP CHIP BACKSIDE MECHANICAL DIE GROUNDING TECHNIQUES

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) package comprising:a semiconductor die including a first side and a second side opposite the first side, the first side including active circuitry;
a sheet attached to the second side, the sheet including a tip that electrically connects with the second side; and
a lid attached to a substrate, and contacting the sheet;
wherein the tip includes two parallel surfaces, and wherein each of the two parallel surfaces forms an acute angle with respect to a plane along a surface of the sheet, and wherein the tip extends from an edge of a hole in the sheet.

US Pat. No. 10,600,752

RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ABLIC Inc., (JP)

1. A method of manufacturing a resin-encapsulated semiconductor device,the resin-encapsulated semiconductor device including:
a resin encapsulation body having a first surface and a second surface that is opposite to the first surface;
a semiconductor chip embedded in the resin encapsulation body; and
an external terminal formed on an element surface of the semiconductor chip, and embedded in the resin encapsulation body,
the method comprising:
preparing a substrate having a first main surface and a second main surface that is opposite to the first main surface;
forming a conductive layer on the first main surface;
forming the external terminal by connecting a bump electrode formed on the semiconductor chip to the conductive layer;
forming the resin encapsulation body on the first main surface by covering the external terminal and the semiconductor chip with resin;
exposing a surface of the semiconductor chip that is opposite to the element surface by grinding the resin encapsulation body and the semiconductor chip from a surface of the resin encapsulation body that is opposite to a surface thereof in contact with the first main surface;
forming a metal layer on the exposed surface of the semiconductor chip;
exposing the external terminal and the first surface of the resin encapsulation body; and
performing singulation by cutting the resin encapsulation body between adjacent semiconductor chips to obtain the resin-encapsulated semiconductor device.

US Pat. No. 10,600,751

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A pillar-type connection comprising:a first conductive layer that includes a hollow core;
a second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core; and
a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,600,750

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

11. A semiconductor die, comprising:a substrate;
a contact exposed at a surface of the substrate;
an interconnect structure electrically coupled to the contact, wherein the interconnect structure includes a top surface having a first portion over the contact and a second portion laterally offset from the contact; and
a solder material disposed at least partially on the second portion of the top surface of the interconnect structure.

US Pat. No. 10,600,749

CONTACT HOLE STRUCTURE AND FABRICATING METHOD OF CONTACT HOLE AND FUSE HOLE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor structure, comprising:providing a dielectric layer having a conductive pad and a fuse formed therein, wherein the dielectric layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer;
forming a first mask covering the dielectric layer and having a first opening directly over the conductive pad;
performing a first removing process using the first mask as a mask to remove a portion of the dielectric layer to form a first trench, wherein the conductive pad is directly under the first trench and is not exposed from the first trench;
removing the first mask;
forming a second mask covering the dielectric layer and having a second opening exposing the first trench and a third opening directly over the fuse; and
performing a second removing process using the second mask as a mask to remove the dielectric layer directly under the first trench and the dielectric layer directly over the fuse thereby forming a contact hole and a fuse hole respectively, wherein the conductive pad is exposed from the contact hole.

US Pat. No. 10,600,748

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;
a second interconnection member disposed on a portion of the encapsulant and on the active surface of the semiconductor chip;
a first passivation layer disposed on the second interconnection member,
wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip,
the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and
the first passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member,
wherein the first passivation layer is an outermost insulating layer of the fan-out semiconductor package.

US Pat. No. 10,600,747

VERTICAL CAPACITORS FOR MICROELECTRONICS

Invensas Corporation, Sa...

1. An apparatus, comprising:a capacitor layer to underlie a semiconductor chip, a die, or an integrated circuit;
vertical capacitor plates in the capacitor layer interleaved with vertical dielectric layers;
electrodes of each vertical capacitor plate at a top surface and a bottom surface of the capacitor layer; and
power pass-throughs or ground pass-throughs on the top surface and the bottom surface of the capacitor layer.

US Pat. No. 10,600,746

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING GAPS AND/OR ISOLATION STRUCTURES BETWEEN GROUPS OF UNIT CELL TRANSISTORS

Cree, Inc., Durham, NC (...

1. A multi-cell transistor, comprising:a semiconductor structure; and
a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure,
wherein the unit cell transistors are spaced apart from each other along a second direction and arranged in a plurality of groups, wherein a first distance in the second direction between two adjacent unit cell transistors in a first of the groups is less than a second distance in the second direction between a first unit cell transistor that is at one end of the first of the groups and a second unit cell transistor that is in a second of the groups, where the second unit cell transistor is adjacent the first unit cell transistor,
wherein the multi-cell transistor further comprises a metal isolation structure that extends above the semiconductor structure in the first direction between the first of the groups and the second of the groups, and
wherein the metal isolation structure is electrically connected to source regions of the unit cell transistors.

US Pat. No. 10,600,745

COMPENSATING FOR MEMORY INPUT CAPACITANCE

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
an access line comprising a first portion in contact with the substrate and a second portion;
a memory die coupled with the substrate via the second portion of the access line;
a memory controller coupled with the access line and configured to transmit, through the access line to the memory die, a signal having an amplitude level and modulated with a modulation scheme having at least two levels; and
an inductive region coupled with the access line and configured to change a first noise level associated with the amplitude level of the signal to a second noise level based at least in part on altering a capacitance of the access line.

US Pat. No. 10,600,744

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a lead frame;
a transistor including a plurality of drain electrode pads, a plurality of source electrode pads, and a gate electrode pad on one surface, the plurality of drain electrode pads, the plurality of source electrode pads, and the gate electrode pad facing a front surface of the lead frame and being connected to the lead frame; and
an encapsulation resin that has a rectangular-plate shape and encapsulates the transistor and the lead frame so that a part of the lead frame is exposed from a back surface of the encapsulation resin, wherein
the lead frame includes a drain frame electrically connected to the plurality of drain electrode pads, a source frame electrically connected to the plurality of source electrode pads, and a gate frame electrically connected to the gate electrode pad,
the drain frame includes a plurality of drain frame fingers,
the plurality of drain frame fingers are spaced apart from each other in a first direction, extended in a second direction that is orthogonal to the first direction in a plan view, and each one of the plurality of the drain frame fingers is connected to a respective one of the plurality of drain electrode pads,
the source frame includes a plurality of source frame fingers,
the plurality of source frame fingers are spaced apart from each other in the first direction, extended in the second direction, and each one of the plurality of the source frame fingers is connected to a respective one of the plurality of source electrode pads,
each one of the plurality of the drain frame fingers and each one of the plurality of the source frame fingers are alternately arranged in the first direction and overlap each other as viewed in the first direction,
in a region where the plurality of drain frame fingers and the plurality of source frame fingers overlap one another as viewed in the first direction, at least either one of the plurality of drain frame fingers and the plurality of source frame fingers are not exposed from the back surface of the encapsulation resin, and
in the region where the plurality of drain frame fingers and the plurality of source frame fingers overlap one another as viewed in the first direction, either one of the plurality of drain frame fingers and the plurality of source frame fingers are exposed from the back surface of the encapsulation resin, and the other one of the plurality of drain frame fingers and the plurality of source frame fingers are not exposed from the back surface of the encapsulation resin.

US Pat. No. 10,600,743

ULTRA-THIN THERMALLY ENHANCED ELECTRO-MAGNETIC INTERFERENCE SHIELD PACKAGE

Inari Semiconductor Labs ...

1. A method of fabricating an electronic package, comprising the steps of:connecting a plurality of semiconductor chips to at least one surface of a substrate using a connect pad;
encapsulating the semiconductor chips with a non-conductive material by a first molding process;
reducing a thickness of the semiconductor chips by a process of trimming or grinding from a top encapsulation layer of the semiconductor chips to form thin semiconductor chips; and
forming an electro-magnetic interference shield layer over the thin semiconductor chips by a second molding process.

US Pat. No. 10,600,742

CHIP WITH CIRCUIT FOR DETECTING AN ATTACK ON THE CHIP

Infineon Technologies AG,...

1. A chip, comprising:a substrate region having a substrate contact;
an RS latch having two complementary nodes representing a storage state of the RS latch;
a control circuit comprising a control input connected directly to the substrate contact and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input; and
an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

US Pat. No. 10,600,741

SEMICONDUCTOR PACKAGE WITH PLATED METAL SHIELDING AND A METHOD THEREOF

Utac Headquarters PTE. LT...

1. A method of manufacturing semiconductor devices, comprising:obtaining a molded array that includes a package side and an interfacing side, wherein the molded array includes a plurality of dies coupled to a substrate and molding compound encapsulating the plurality of dies, wherein surfaces of the molding compound has have a natural surface roughness;
coupling the interfacing side of the molded array with a tape;
performing a cut through procedure from the package side to the interfacing side, thereby forming a plurality of singulated semiconductor devices on the tape;
performing an abrasion procedure to roughen all surfaces of the molding compound such that, after the abrasion procedure, all surfaces of the molding compound have an unnatural surface roughness that is rougher than the natural surface roughness, wherein the abrasion procedure comprises:
i. coating all exposed surfaces of the molding compound with an adhesion promoter material;
ii. heating the molded array with the adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film; and
iii. etching away the baked film, resulting in the molding compound having the roughened surfaces;
adhering a metal layer on the roughened surfaces; and
removing the plurality of singulated semiconductor devices from the tape.

US Pat. No. 10,600,740

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH EPITAXIAL LAYERS AND AN ALIGNMENT MARK

Infineon Technologies Aus...

1. A semiconductor substrate, comprising:an alignment mark contained within in a kerf region of a semiconductor wafer or in an inactive region of a semiconductor die, the alignment mark comprising a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m in a process surface of a semiconductor layer, and at least one fin within the groove at a distance of at least 60 ?m to a closest inner corner of the groove.

US Pat. No. 10,600,739

INTERPOSER WITH INTERCONNECTS AND METHODS OF MANUFACTURING THE SAME

HRL Laboratories, LLC, M...

1. An interposer, comprising:an interposer substrate comprising a plurality of vias, the interposer substrate having a first surface and a second surface opposite the first surface; and
a plurality of metallic interconnects in the plurality of vias,
wherein the interposer substrate comprises a dielectric material,
wherein a first pitch of the plurality of vias at a first end of the plurality of vias is different than a second pitch of the plurality of vias at a second end of the plurality of vias,
wherein the plurality of metallic interconnects are slanted at angles relative to the first surface of the interposer substrate,
wherein the angles at which the plurality of metallic interconnects are slanted relative to the first surface of the interposer substrate varies between the plurality of metallic interconnects, and
wherein the angle of at least one metallic interconnect of the plurality of metallic interconnects varies non-uniformly.

US Pat. No. 10,600,738

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
an insulating film formed to cover the semiconductor substrate;
a first electric conductor formed on the insulating film;
a second electric conductor formed on the insulating film at a distance from the first electric conductor;
an embedded body formed to fill space between the first electric conductor and the second electric conductor;
a protective film formed to cover the first electric conductor, the second electric conductor and the embedded body;
a solder layer formed to cover the protective film; and
a glass coating film covering an upper surface of each of the first electric conductor and the second electric conductor,
a position of an upper surface of the embedded body being matched to a position of an upper surface of the glass coating film, and
the first electrical conductor is electrically isolated from the second electrical conductor.

US Pat. No. 10,600,737

PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A process, comprising:forming an opening in a porous material dielectric region, said opening having a side wall and a bottom wall;
depositing a non-porous dielectric barrier on said side wall and said bottom wall;
performing an anisotropic etch to completely remove a portion of the non-porous dielectric barrier along the bottom wall, wherein performing the anisotropic etch comprises performing a plasma etch; and
filling the opening with metal material to form an electrically conductive element that is laterally separated from an upper portion of the porous material dielectric region by the non-porous dielectric barrier along the side wall but is in contact with a lower portion of the porous material dielectric region along the bottom wall.

US Pat. No. 10,600,736

SEMICONDUCTOR BACKMETAL (BM) AND OVER PAD METALLIZATION (OPM) STRUCTURES AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device, comprising:a semiconductor layer having a first side and a second side opposite the first side;
one or more electrically conductive pads coupled at the second side;
one or more electrically insulative layers coupled at the second side and having one or more openings providing access to the one or more electrically conductive pads;
an electrically conductive layer coupled on the first side of the semiconductor layer;
one or more backmetal (BM) layers coupled on the electrically conductive layer;
one or more over-pad metallization (OPM) layers coupled over the one or more electrically conductive pads, the one or more OPM layers comprising a nickel layer, and;
a diffusion barrier layer coupled over the one or more OPM layers;
wherein the semiconductor device comprises one of an insulated gate bipolar transistor (IGBT) or a diode;
wherein a perimeter of each of the one or more OPM layers is entirely within a perimeter of each of the one or more electrically conductive pads; and
wherein a largest planar surface of the electrically conductive layer and a side surface of the electrically conductive layer substantially perpendicular to the largest planar surface of the electrically conductive layer are both directly coupled to the semiconductor layer.

US Pat. No. 10,600,735

3D CHIP SHARING DATA BUS

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate; and
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, wherein at least one particular second-set interconnect layer comprises a plurality of interconnect segments that form a data bus for supplying data signals to the first IC die.

US Pat. No. 10,600,734

TRANSISTOR STRUCTURE IN LOW NOISE AMPLIFIER

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first gate line and a second gate line extending along a first direction;
a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line;
a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line; and
first contact plugs on the first gate line; and
a first doped region between the first gate line and the third gate line, a second doped region between the second gate line and the fourth gate line, and a third doped region between the third gate line and the fourth gate line, wherein the first doped region and the second doped region comprise same conductive type, the first doped region and the third doped region comprise different conductive type, wherein a first edge of the third doped region is merged in plan view with an edge of the third gate line and a second edge of the third doped region is merged in plan view with an edge of the fourth gate line.

US Pat. No. 10,600,699

APPARATUS FOR INSPECTION OF A PACKAGE ASSEMBLY WITH A THERMAL SOLUTION

Intel Corporation, Santa...

1. An apparatus for inspection of a package assembly with a thermal solution, comprising:a first fixture to house the package assembly on the apparatus;
a second fixture to house at least a portion of a thermal solution that is to be disposed on top of the package assembly;
a load actuator, to apply a load to a die of the package assembly, via the thermal solution; and
a plurality of sensors disposed around the thermal solution and the package assembly, to perform in situ at least one of thermal or mechanical measurements associated with the application of the load to the die of the package assembly,
wherein the package assembly includes a substrate, wherein the die is disposed on the substrate; and a printed circuit board (PCB), wherein the substrate is disposed on the PCB, and wherein the PCB is disposed on the first fixture.

US Pat. No. 10,600,698

SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, AND TEST METHOD FOR SEMICONDUCTOR CHIP

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device, comprising:a signal processing circuit configured to generate an output signal;
an output pad;
a shorting pad;
a line connecting the signal processing circuit to the shorting pad, the output signal from the signal processing circuit being output from the output pad through an output line; and
a switch
connected between the shorting pad and the output pad, and configured to
connect the signal processing circuit to the output pad when the switch is on, and
disconnect the signal processing circuit from the output pad when the switch is off; and
a wiring line connecting the shorting pad to the output pad.

US Pat. No. 10,600,697

LIGHT EMITTING DIODE (LED) TEST APPARATUS AND METHOD OF MANUFACTURE

Tesoro Scientific, Inc., ...

1. An apparatus for observing light emission from a light-emitting device structure disposed on a support substrate having a first face contact layer accessible from a surface and a second contact layer underlying the light-emitting device structure, the apparatus comprising:a field plate device, the field plate device having a first face and a second face opposing the first face, the second face comprising a conductive layer, and an overlying dielectric layer, the dielectric layer being positioned in close proximity to at least a portion of the first contact layer of the light-emitting device structure, a voltage source for producing a voltage, the voltage source having a first terminal and a second terminal, the first terminal being coupled to the conductive layer of the field plate device, the second terminal being coupled to a ground potential, the voltage source being capable of generating a time-varying voltage waveform to form a voltage potential between the dielectric layer of the field plate device and the light emitting device structure to inject current to the light emitting device structure to cause the light-emitting device structure to emit electromagnetic radiation in a pattern; and
a detector device coupled to the light emitting device structure to form an image of the electromagnetic radiation in the pattern derived from the light-emitting device structure,
wherein the field plate device is approximately the same areal dimension to the support substrate and is placed on the support substrate to allow substantially complete functional testing of the support substrate without step and repeat indexing of the field plate device, and
wherein the field plate device is placed in close proximity to the support substrate using a seal near the periphery of the field plate device and air is evacuated from a gap using a vacuum port.

US Pat. No. 10,600,696

IC UNIT AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME

Institute of Microelectro...

1. A method of manufacturing an Integrated Circuit (IC) unit, comprising:providing a stack of a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device on a substrate;
selectively etching the channel layer of the second device and the channel layer of the first device, so that the channel layer of the second device has its periphery recessed inwards with respect to that of the first and second source/drain layers of the second device, and that the channel layer of the first device has its periphery recessed inwards with respect to that of the first and second source/drain layers of the first device and is separated into a first portion and a second portion spaced apart from each other; and
forming a first gate stack and a second gate stack to surround the periphery of the respective channel layers of the first device and the second device, respectively.

US Pat. No. 10,600,695

CHANNEL STRAIN FORMATION IN VERTICAL TRANSPORT FETS WITH DUMMY STRESSOR MATERIALS

International Business Ma...

1. A method of forming a vertical transport field-effect transistor (VTFET) device, comprising the steps of:patterning fins in a wafer;
forming bottom source and drains at a base of the fins;
forming bottom spacers on the bottom source and drains;
growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins, wherein the at least one dummy stressor material grown along the sidewalls of a given fin is in a non-contact position with the at least one dummy stressor material grown along the sidewalls of an adjacent fin;
removing portions of the fins to form separate device fins;
surrounding the device fins with a rigid fill material;
removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the device fins by the rigid fill material;
forming replacement gate stacks in the gate trenches;
forming top spacers on the replacement gate stacks; and
forming top source and drains over the top spacers at tops of the device fins.

US Pat. No. 10,600,694

GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS

International Business Ma...

1. A method of fabricating dual work function metal gate transistors, comprising:obtaining a first structure including:
a substrate having a first region and a second region,
a first FET structure on the first region of the substrate, the first FET structure including a semiconductor channel region and a dielectric layer adjoining the semiconductor channel region,
a second FET structure on the second region of the substrate, the second FET structure including a semiconductor channel region and a dielectric layer adjoining the semiconductor channel region,
a first gate metal layer having a first portion extending over the first region of the substrate and a second portion extending over the second region of the substrate, the first gate metal layer further adjoining the dielectric layers of the first and second FET structures, and
a mask covering the first FET structure;
depositing a protective layer partially covering the first gate metal layer extending over the second region of the substrate;
subjecting the first structure to an etching process subsequent to depositing the protective layer, thereby removing the second portion of the first gate metal layer while leaving the first portion of the first gate metal layer intact;
removing the mask subsequent to removing the first gate metal layer from the second FET structure, and
forming a second gate metal layer on the first and second FET structures, the second metal gate layer adjoining the dielectric layer of the second FET structure and having a different work function value than the first metal gate layer.

US Pat. No. 10,600,693

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

Tessera, Inc., San Jose,...

1. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:forming a first array of vertical fins, a second array of vertical fins, and one or more dummy fins on a substrate, wherein the one or more dummy fins are on a dummy fin fill between the first array of vertical fins and the second array of vertical fins; and
removing the one or more dummy fins and dummy fin fill to form a step in the substrate and a gap between the first array of vertical fins and the second array of vertical fins.

US Pat. No. 10,600,692

SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having thereon a trench isolation region and a fin structure extending along a first direction, wherein the fin structure protrudes from a top surface of the trench isolation region and has a first height; and
a plurality of gate lines comprising a first gate line and a second gate line extending along a second direction and striding across the fin structure, wherein the first gate line has a discontinuity directly above a gate cut region, and the second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region, wherein the fin structure has a second height within the dummy fin region, and the second height is smaller than the first height, wherein a non-dense region and a recess are disposed above the trench isolation region, and the recess is disposed at a bottom of the non-dense region within the gate cut region partially along the first direction.

US Pat. No. 10,600,691

3D CHIP SHARING POWER INTERCONNECT LAYER

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate; and
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, wherein at least one particular second-set interconnect layer comprises a plurality of interconnect segments for supplying power signals to the first IC die.

US Pat. No. 10,600,690

METHOD FOR HANDLING A PRODUCT SUBSTRATE AND A BONDED SUBSTRATE SYSTEM

Infineon Technologies AG,...

1. A method for handling a product substrate, the method comprising:bonding a carrier to the product substrate by:
applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and
bonding the carrier to the product substrate using the applied temporary adhesive,
wherein a surface of the temporary adhesive is in direct contact to a surface of the product substrate,
wherein the temporary adhesive comprises or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.

US Pat. No. 10,600,689

VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES

Micron Technology, Inc., ...

1. A device, comprising:a semiconductor substrate having a first substrate surface and a second substrate surface;
a dielectric on the semiconductor substrate, the dielectric having a first dielectric surface and a second dielectric surface, wherein the second dielectric surface is in direct contact with the first substrate surface;
a depression in the dielectric;
an aperture through the dielectric and at least a portion of the semiconductor substrate;
a conductive material having a first portion in the depression and a second portion in the aperture;
a conductive interconnect structure positioned within the dielectric and electrically coupled to the conductive material in the aperture, wherein the conductive interconnect structure is laterally positioned between the conductive material and a trace positioned within the dielectric;
a passivation material formed on the second substrate surface, wherein the passivation material is formed with an opening;
a bond site formed through the opening; and
a conductive pillar electrically coupled to the bond site.

US Pat. No. 10,600,688

METHODS OF PRODUCING SELF-ALIGNED VIAS

Micromaterials LLC, Wilm...

1. A method to provide a self-aligned via, the method comprising:forming a seed gapfill layer on recessed first insulating layers positioned between first conductive lines, the first conductive lines extending along a first direction;
forming pillars from the seed gapfill layer, the pillars extending above the first conductive lines;
depositing a second insulating layer in gaps between the pillars on the first conductive lines;
removing the pillars to form gaps in the second insulating layer;
depositing a third insulating layer in the gaps in the second insulating layer, onto the recessed first insulating layers and on the second insulating layer to form an overburden of third insulating layer on the second insulating layer; and
selectively etching a portion of the overburden of the third insulating layer and some of the second insulating layer to expose the first conductive lines and form vias and a trench extending in a second direction different from the first direction.

US Pat. No. 10,600,687

PROCESS INTEGRATION TECHNIQUES USING A CARBON LAYER TO FORM SELF-ALIGNED STRUCTURES

TOKYO ELECTRON LIMITED, ...

11. A method of utilizing a tone inversion process step to form self-aligned contacts, the method comprising:providing a substrate having patterned structures which provide gate regions and self-aligned contact regions in which a self-aligned contact will be formed;
forming a gate liner above at least a portion of the gate regions and the self-aligned contact regions;
providing a carbon layer in a portion of the self-aligned contact regions;
forming recessed carbon layer portions in the self-aligned structure region, wherein a height of each recessed carbon layer portion is lower than a height of the self-aligned contact regions;
removing the patterned structures;
forming self-aligned contacts in the self-aligned contact regions;
providing, over the self-aligned contacts, a blocking mask above the recessed carbon layer portions in the self-aligned contact regions;
removing at least some of the recessed carbon layer portions in areas not protected by the blocking mask;
removing the blocking mask from above the self-aligned contact regions; and
removing the recessed carbon layer portions from the self-aligned contact regions.

US Pat. No. 10,600,686

CONTROLLING GRAIN BOUNDARIES IN HIGH ASPECT-RATIO CONDUCTIVE REGIONS

INTERNATIONAL BUSINESS MA...

1. A method of forming a conductive region of a metallization network associated with a substrate, the method comprising:forming a trench in a dielectric material on the substrate;
forming a conductive material in the trench, wherein the conductive material includes a first grain boundary level;
removing portions of the dielectric material to expose sidewalls of the conductive material; and
annealing the exposed sidewalls of the conductive material to reduce the first grain boundary level.

US Pat. No. 10,600,685

METHODS TO FILL HIGH ASPECT RATIO FEATURES ON SEMICONDUCTOR SUBSTRATES WITH MOCVD COBALT FILM

APPLIED MATERIALS, INC., ...

1. A method of forming a cobalt layer on a substrate disposed in a process chamber, comprising:(a) exposing the substrate to a first process gas comprising a cobalt precursor and a hydrogen containing gas to grow a smooth cobalt layer on a first surface of the substrate and on sidewalls and a bottom surface of a feature formed in the first surface of the substrate, wherein the feature has an aspect ratio of about 6:1 to about 20:1 and wherein the smooth cobalt layer has a roughness root mean square value over a layer thickness ratio of about 5% to below about 10%;
(b) purging the first process gas from the process chamber; and
(c) annealing the substrate in a hydrogen atmosphere to fill in voids within the cobalt layer to form a void-free cobalt layer.

US Pat. No. 10,600,684

ULTRA-THIN DIFFUSION BARRIERS

APPLIED MATERIALS, INC., ...

1. A method of forming a semiconductor device, comprising:positioning a device intermediate in a processing chamber, the device intermediate comprising:
a silicon substrate;
a dielectric layer disposed on the silicon substrate; and
conductive features in contact with the silicon substrate and extending through openings in the dielectric layer;
forming a barrier layer over the device intermediate;
depositing a gap fill material on the barrier layer, wherein the gap fill material is a flowable dielectric material;
removing a portion of the gap fill material to planarize an upper surface of the gap fill material; and
annealing the device intermediate at a temperature of about 400° C. to about 500° C. and a pressure of about 10 torr to about 700 torr.

US Pat. No. 10,600,683

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A semiconductor integrated circuit device, comprising:(a) a first interconnect made of a first metal and formed over a main surface of a semiconductor substrate;
(b) a first barrier insulating film formed on the first interconnect and contacted with a top surface of the first interconnect,
(c) a first interlayer insulating film formed over the first barrier insulating film;
(d) a first via hole formed in the first interlayer insulating film and the first barrier insulating film and contacted with the first interconnect;
(e) a first interconnect trench formed in the first interlayer insulating film and contacted with the first via hole;
(f) a second interconnect formed by filling a second metal in the first interconnect trench and the first via hole;
(g) a third interconnect made of a third metal and formed over the second interconnect and the first interlayer insulating film;
(h) a second barrier insulating film formed on the third interconnect and contacted with a top surface of the third interconnect;
(i) a second interlayer insulating film formed over the second barrier insulating film;
(j) a second via hole formed in the second interlayer insulating film and the second barrier insulating film and contacted with the third interconnect;
(k) a second interconnect trench formed in the second interlayer insulating film and contacted with the second via hole; and
(l) a fourth interconnect formed by filling a fourth metal in the second interconnect trench and the second via hole,
wherein the second interlayer insulating film has an etching stopper film,
wherein the etching stopper film is arranged nearer to a bottom surface of the second interconnect trench than to a top surface of the third interconnect and a top surface of the second interconnect trench,
wherein the first interlayer insulating film does not have an etching stopper film,
wherein the second interlayer insulating film is thicker than the first interlayer insulating film,
wherein a depth of the second interconnect trench is greater than a depth of the first interconnect trench,
wherein a depth of the second via hole is greater than a depth of the first via hole,
wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film,
wherein the first barrier insulating film includes silicon, carbon and nitrogen,
wherein the second barrier insulating film includes silicon, carbon and nitrogen and
wherein the second interlayer insulating film includes silicon, fluorine and oxygen.

US Pat. No. 10,600,682

SEMICONDUCTOR DEVICES INCLUDING A STAIR STEP STRUCTURE, AND RELATED METHODS

Micron Technology, Inc., ...

1. A method of forming a semiconductor structure, the method comprising:forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material;
forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material;
forming at least one liner directly contacting the sacrificial material and portions of the alternating levels of the dielectric material and the another material;
forming at least one oxide material in the opening and overlying surfaces of the at least one liner, an uppermost surface of the at least one oxide material extending more distal from a surface of a base material than the sacrificial material;
planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material; and
removing substantially all of the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the base material than the uppermost level of the alternating levels of the dielectric material and the another material.

US Pat. No. 10,600,681

METHODS OF FORMING STAIRCASE STRUCTURES

Micron Technology, Inc., ...

1. A staircase structure, comprising:opposing tiers of alternating insulative levels and conductive levels or alternating insulative levels and nitride materials, the tiers comprising a stepped profile; and
at least three portions of a fill material between the opposing tiers, the at least three portions of the fill material comprising different material compositions.

US Pat. No. 10,600,680

CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LINE TO VIA

International Business Ma...

1. An electrical communication structure comprising:metal vias in a dielectric layer;
a neutral charged di-block polymer layer on at least a portion of dielectric layer; and
metal lines present in a layer including a block copolymer composition from a self-assembled di-block copolymer layer that is present atop the neutral charged di-block polymer layer, wherein the metal lines are self-aligned to the metal vias.

US Pat. No. 10,600,679

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a core member having a through-hole;
a first semiconductor chip disposed in the through-hole and having a first active surface having first connection pads disposed thereon;
a second semiconductor chip disposed on the first semiconductor chip in the through-hole and having a second active surface having second connection pads disposed thereon;
an encapsulant encapsulating at least portions of the core member, the first semiconductor chip, and the second semiconductor chip; and
a connection member including a redistribution layer and an insulating layer, the insulating layer having a composition different than that of the encapsulant and having a substantially planar surface that has the core member and the first active surface of the first semiconductor chip disposed thereon and that faces the second active surface of the second semiconductor chip,
wherein:
the redistribution layer of the connection member is electrically connected to both the first connection pads and the second connection pads,
the second semiconductor chip is disposed on the first semiconductor chip to be mismatched to the first semiconductor chip so that the second connection pads are exposed,
the redistribution layer of the connection member is connected to the first connection pads and the second connection pads through one or more first conductors and one or more second conductors, respectively,
each second conductor of the one or more second conductors extends integrally from the redistribution layer through the insulating layer of the connection member to the second connection pads, each second conductor has a side surface that contacts the encapsulant from the substantially planar surface of the insulating layer of the connection member on which the first semiconductor chip is disposed to the second connection pads,
each second conductor of the one or more second conductors has a height greater than that of the one or more first conductors,
each second conductor of the one or more second conductors is spaced apart from the core member,
the first semiconductor chip is in contact with the insulating layer of the connection member, and
the second semiconductor chip is disposed on the first semiconductor chip to be mismatched so that at least a portion of a first inactive surface of the first semiconductor chip does not overlap with the second semiconductor chip.

US Pat. No. 10,600,678

SELF-ALIGNED ISOTROPIC ETCH OF PRE-FORMED VIAS AND PLUGS FOR BACK END OF LINE (BEOL) INTERCONNECTS

Intel Corporation, Santa...

1. A method of fabricating an integrated circuit structure, the method comprising:forming a dielectric layer above a substrate;
forming a plurality of holes or trenches in the dielectric layer;
filling the plurality of holes or trenches with a sacrificial or permanent placeholder material;
forming a patterning layer above the dielectric layer and the sacrificial or permanent placeholder material;
forming openings in the patterning layer to expose a portion of the sacrificial or permanent placeholder material of a subset of the plurality of holes or trenches, each opening smaller than the corresponding portion of the sacrificial or permanent placeholder material of the subset of the plurality of holes or trenches; and
removing the sacrificial or permanent placeholder material of the subset of the plurality of holes or trenches through the openings in the patterning layer.

US Pat. No. 10,600,677

METHOD FOR MANUFACTURING BONDED SOI WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for manufacturing a bonded SOI wafer comprising a step of performing a heat treatment to each bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere to flatten a front surface of an SOI layer,wherein, at the time of performing the heat treatment in the argon atmosphere in a batch processing heat treatment furnace, a silicon wafer is arranged as a dummy wafer between the adjacent bonded SOI wafers housed in the batch processing heat treatment furnace to perform the heat treatment.

US Pat. No. 10,600,676

GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. A group III nitride composite substrate with a diameter of 75 mm or more comprising a support substrate and a group III nitride film having a thickness of 10 ?m or more and 250 ?m or less that are bonded to each other,the support substrate being a hetero-composition substrate having a chemical composition different from a group III nitride,
the group III nitride composite substrate having a support-substrate-side main surface and a group III-nitride-film-side main surface,
a mean value mS of a root mean square roughness of the support-substrate-side main surface being 0.3 nm or more and 20 nm or less, and
a ratio sS/mS of a standard deviation sS of the root mean square roughness, to the mean value ms of the root mean square roughness of the support-substrate-side main surface, being 0.005 or more and 0.4 or less, wherein
a ratio W/D of a warp W of the support-substrate-side main surface to the diameter D is ?7×10?4 or more and 8×10?4 or less.

US Pat. No. 10,600,675

TECHNIQUES AND STRUCTURE FOR FORMING THIN SILICON-ON-INSULATOR MATERIALS

Varian Semiconductor Equi...

1. A method, comprising:providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising:
an insulator layer; and
a silicon layer, the silicon layer disposed on the insulator layer, the silicon layer, the silicon layer characterized by a non-uniform thickness, comprising a first silicon thickness variation, across the SOI substrate;
forming an oxide layer on the silicon layer across the SOI substrate, when the silicon layer has the non-uniform thickness, the oxide layer having a uniform thickness across the SOI substrate; and
selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a non-uniform oxide thickness, wherein
after thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness is configured to generate a second silicon thickness variation in the silicon layer across the SOI substrate, less than the first silicon thickness variation.

US Pat. No. 10,600,674

SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION

Efficient Power Conversio...

1. A transistor device comprising:a substrate;
at least one buffer layer comprising a compound semiconductor material;
a device layer including a current conducting region formed over the at least one buffer layer;
a source contact and a drain contact formed on a top surface of the device layer; and
a conductive well formed in the substrate and disposed laterally underneath both the source and drain contacts, wherein the conductive well is electrically isolated in at least one bias polarity from the substrate, such that a potential under the source contact and the drain contact is independent from a potential of the substrate; and
a conductive via extending from the top surface of the device layer through the device layer and through the buffer layer to penetrate and terminate within the conductive well, electrically connecting the source contact to the conductive well;
wherein the substrate has a backside opposite a side adjacent the buffer layer and the drain contact is independent in potential from the backside of the substrate; and
wherein the conductive well has a doping of opposite polarity to the substrate.

US Pat. No. 10,600,673

MAGNETIC SUSCEPTOR TO BASEPLATE SEAL

ASM IP HOLDING B.V., Alm...

1. A reaction system for processing substrates comprising:a susceptor configured to hold a substrate to be processed in the reaction system, the susceptor comprising a susceptor upper surface, a susceptor lower surface, and a susceptor radial surface spanning between the susceptor upper surface and the susceptor lower surface;
a movement element to move the subsector from a substrate loading region to a reaction region of the reaction chamber;
a baseplate that separates the reaction region from a substrate loading region, the baseplate comprising a baseplate upper surface, a baseplate lower surface, and a baseplate radial surface there between;
at least one susceptor magnet embedded within the susceptor; and
at least one baseplate magnet embedded within the baseplate;
wherein an interaction of the at least one susceptor magnet and the at least one baseplate magnet creates a repelling force to maintain a gap defined as a space between the susceptor and the baseplate and between the reaction region and a loading region, and
wherein the gap includes a space between the susceptor radial surface and the baseplate radial surface,
the reaction system further comprising a monitoring system comprising a force gauge, the at least one susceptor magnet, and the at least one baseplate magnet, wherein the force gauge measures the repelling force, wherein the monitoring system and the movement element are configured to maintain a size of the gap between the susceptor and the baseplate,
wherein a size of the gap can be adjusted to tune a process for processing the substrates.

US Pat. No. 10,600,672

BACKEND TAPING USING FLUID ASSISTED FIXATION

NEXPERIA B.V., Nijmegen ...

1. A tape packaging apparatus comprising:a transfer element for transferring a non-curable holding liquid into at least one pocket of a carrier tape, the at least one pocket comprising a recess within the carrier tape configured to receive an electronic component;
a placing element for placing an electronic component into the at least one pocket, whereby the holding liquid acts to retain the electronic component within the recess at least one pocket;
a sealing tape application element for applying a sealing tape over the carrier tape to close the at least one pocket with the electronic component therein; and
a heater for heating the at least one closed pocket to evaporate the holding liquid out of the at least one closed pocket by permeation of the holding liquid through the carrier tape or the sealing tape or both.

US Pat. No. 10,600,671

MICRO-TRANSFER-PRINTABLE FLIP-CHIP STRUCTURES AND METHODS

1. A semiconductor structure, comprising:a destination substrate comprising two or more contact pads disposed on a surface of the destination substrate;
a completed semiconductor device disposed on the surface, the completed semiconductor device comprising two or more electrical contacts disposed on a common side of the completed semiconductor device; and
connection posts, each of the connection posts (i) extending from the completed semiconductor device, (ii) electrically connected to at least one of the two or more electrical contacts, and (iii) in electrical contact with one of the contact pads,
wherein the completed semiconductor device is tilted or angled with respect to the surface of the destination substrate.

US Pat. No. 10,600,670

FRAME MOUNTING AFTER FOIL EXPANSION

Infineon Technologies AG,...

1. An apparatus, the apparatus comprising:an expansion unit configured for expanding a foil;
a mounting unit configured for subsequently mounting the expanded foil on a frame and a workpiece on the expanded foil, wherein the expansion unit comprises a fixing mechanism configured for radially symmetrically clamping a portion of the foil before expanding foil,
wherein the expansion unit, which expands the foil by at least 0.1%, is configured to apply a radially symmetrically tensile stress to the foil prior to its mounting on the frame and conserved thereafter.

US Pat. No. 10,600,669

SUBSTRATE FIXTURE AND SUBSTRATE FIXING DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A substrate fixture comprising:a monopolar chuck main body comprising an insulated plate and an electrode embedded in the insulated plate;
a tray placed on the monopolar chuck main body, having an upper surface in which a plurality of concave parts for accommodating therein a plurality of substrates is formed, and formed of an insulator having a volume resistivity equal to or lower than a volume resistivity of the insulated plate; and
an yttrium oxide layer formed on the upper surface of the tray.

US Pat. No. 10,600,668

ADSORPTION DEVICE, CONVEYANCE DEVICE, AND EL DEVICE MANUFACTURING DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An adsorption device comprising:one or more adsorption pads,
wherein the adsorption device is configured to adsorb a target object via the one or more adsorption pads,
the one or more adsorption pads are formed of a porous material having an average pore diameter of 1.0 ?m or less,
the adsorption device comprises a plurality of adsorption pads,
wherein the plurality of adsorption pads adsorb a plurality of locations of the target object, and
the adsorption device is configured to allow an adsorption force for adsorbing the target object to be individually set for each of the plurality of adsorption pads.

US Pat. No. 10,600,667

SYSTEMS AND METHODS FOR WAFER ALIGNMENT

Micron Technology, Inc., ...

1. A non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processing devices, cause the one or more processing devices to:determine a center location of each of a plurality of features on a wafer;
determine an average center location of the plurality of features;
compare the average center location with a reference location; and
generate an instruction to adjust a position of the wafer in response to the comparison.

US Pat. No. 10,600,666

ARTICLE TRANSPORT FACILITY

Daifuku Co., Ltd., Osaka...

1. An article transport facility comprising:article transport vehicles each of which is capable of traveling along any of travel paths to transport an article; and
a storage device configured to store one or more articles;
wherein the travel paths include a first path that extends by way of the storage device, and a plurality of second paths connected to the first path at mutually different locations along the first path,
wherein each of the plurality of second paths is arranged to extend by way of at least one processing device configured to process an article or one or more contents thereof;
wherein the article transport facility includes a transport device which has a connecting portion connected to the storage device, and which is configured to transport an article to be carried into, or being carried out from, the storage device,
wherein the transport device is provided separately from the article transport vehicles,
wherein, with a first side being one side, with respect to the first path, along a lateral width direction of the first path and a second side being the other side, with respect to the first path, along a lateral width direction of the first path, the connecting portion is located on the first side with respect to the first path whereas a subject path which is one of the plurality of second paths is located on the second side with respect to the first path,
wherein a transporting path of an article by the transport device is so located to cross the first path in plan view and to extend at least from the connecting portion and to the second side with respect to the first path, and
wherein a first transfer portion at which an article is transferred between the transport device and the article transport vehicle traveling along the subject path is set in a portion of the transporting path that is located on the second side with respect to the first path.

US Pat. No. 10,600,665

SUBSTRATE PROCESSING APPARATUS

BROOKS AUTOMATION, INC., ...

1. A substrate processing apparatus comprising:a frame;
a first arm connected to the frame, the first arm being a three link arm configured to extend and retract along a first radial axis and having an upper arm, a forearm and an end effector;
a second arm connected to the frame, the second arm being a three link arm configured to extend and retract along a second radial axis and having an upper arm, a forearm and an end effector, where the first and second arms have a common axis of rotation on a common base from which the first and second arms depend, and the end effectors of each of the first and second arms move along a common transfer plane; and
a drive section coupled to the first and second arms, the drive section having two degrees of freedom disposed co-axially forming a coaxial drive spindle and being configured to extend both the first and second arms with the coaxial drive spindle along respective radial axes and rotate both the first and second arms with the coaxial drive spindle about the common axis of rotation so that the extension and retraction of the first and second arms along the respective radial axes is decoupled and the first arm has at least one link of the three link arm with a different length than a corresponding link of the second arm.

US Pat. No. 10,600,664

FLUORESCENCE BASED THERMOMETRY FOR PACKAGING APPLICATIONS

APPLIED MATERIALS, INC., ...

1. Apparatus for encapsulating an electronics package, comprising:a process chamber having a chamber body enclosing a processing volume, the chamber body including one or more windows configured to allow light energy to pass therethrough during operation;
a substrate support having a support surface for receiving and supporting a substrate for forming an electronics package; and
a temperature sensor configured to measure a temperature of an epoxy resin in an electronics package while the electronics package is being encapsulated within the processing volume, the temperature sensor including:
an input apparatus including at least a light source disposed outside the chamber body to provide an excitation light energy to a portion of the epoxy resin disposed on an underside of the substrate; and
an output apparatus including at least a signal analyzer disposed outside the chamber body to detect fluorescent light energy emitted by the portion of the epoxy resin disposed on the underside of the substrate and determine a temperature of the epoxy resin based on the excitation light energy and the fluorescent light energy.

US Pat. No. 10,600,663

NOZZLE AND WORK POLISHING APPARATUS

FUJIKOSHI MACHINERY CORP....

1. A nozzle comprising:a liquid flow passage through which a liquid flows;
a gas flow passage through which a gas flows, the gas flow passage communicating with the liquid flow passage and feed the gas to the liquid flow passage; and
a plasma generating mechanism for generating plasma in the gas fed from the gas flow passage to the liquid flow passage,
wherein the plasma generating mechanism includes a first electrode provided so as to be exposed to an inside of the liquid flow passage,
a second electrode provided so as not to be exposed to the inside of the liquid flow passage and so as to be exposed to an inside of the gas flow passage, and
a power source for applying a predetermined voltage across the first electrode and the second electrode,
wherein the liquid with which the gas including the generated plasma is mixed as bubbles having a predetermined diameter is spouted, and
wherein the second electrode is provided distantly from a delivery port toward an inside of the gas flow passage, the delivery port being provided at a portion in which the gas flow passage is connected to the liquid flow passage.

US Pat. No. 10,600,662

SILICON CARBIDE SUBSTRATE HEATING

Varian Semiconductor Equi...

1. A heating system, comprising:a silicon carbide substrate; and
a heating element, wherein the heating element comprises one or more light emitting diodes (LEDs) that emits light at a wavelength between 600 nm and 650 nm, wherein the wavelength is selected based on an absorption coefficient of the silicon carbide substrate.

US Pat. No. 10,600,661

RAPID HEAT TREATMENT APPARATUS

ULTECH CO., LTD., Daegu ...

1. A rapid heat treatment apparatus, comprising:a chamber for rapid heat treatment;
a support stage which is disposed on an lower inner side of the chamber and supports and rotates a substrate for rapid heat treatment;
a heat source device which is disposed on an upper inner side of the chamber and radiates light to rapidly heat the substrate for rapid heat treatment;
a substrate for temperature measurement which is placed apart at a distance above a part of the substrate for rapid heat treatment, and is made of a same material as the substrate for rapid heat treatment;
a thermocouple for temperature measurement which is installed at the substrate for temperature measurement to measure a temperature of the substrate for temperature measurement;
a support part of a light transmitting material which supports the substrate for temperature measurement; and
a light transmitting plate which is disposed between the support part and the heat source device to isolate the two internal space parts of the chamber,
wherein the temperature of the substrate for temperature measurement measured by the thermocouple is regarded as temperature of the substrate for rapid heat treatment.

US Pat. No. 10,600,660

METHOD OF SELECTIVELY ETCHING FIRST REGION MADE OF SILICON NITRIDE AGAINST SECOND REGION MADE OF SILICON OXIDE

TOKYO ELECTRON LIMITED, ...

1. A method of etching a first region made of silicon nitride selectively against a second region made of silicon oxide, comprising:preparing a processing target object having the first region and the second region within a chamber provided in a chamber main body of a plasma processing apparatus;
generating plasma of a first gas including a gas containing hydrogen within the chamber to form a modified region by modifying a part of the first region with active species of the hydrogen; and
generating plasma of a second gas including a gas containing fluorine within the chamber to remove the modified region with active species of the fluorine,
wherein the processing target object is placed, within the chamber, on a stage including therein an electrode to which a high frequency power for attracting ions onto the processing target object is allowed to be supplied, and
the high frequency power is not supplied to the electrode in the generating of the plasma of the second gas.

US Pat. No. 10,600,659

SEMICONDUCTOR PACKAGE WITH REDUCED PARASITIC COUPLING EFFECTS AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a silicon-on-insulator (SOI) structure including an epitaxial layer, a buried oxide (BOX) layer over the epitaxial layer, and a silicon handle layer over the BOX layer, wherein:
the epitaxial layer has a first sacrificial epitaxial section, a first active epitaxy section and an isolation region; and
the isolation region surrounds the first active epitaxy section and separates the first active epitaxy section from the first sacrificial epitaxial section;
forming at least one first etchable structure that extends through the first sacrificial epitaxial section and the BOX layer to the silicon handle layer;
integrating a first active device in or on the first active epitaxy section, such that the epitaxial layer is formed as a device layer; and
forming a (back-end-of-line) BEOL layer underlying the device layer, wherein:
the BEOL layer has an upper surface including a first surface portion and a second surface portion surrounding the first surface portion;
the first sacrificial epitaxial section is over the first surface portion and not over the second surface portion;
the first epitaxy section and the isolation region are over the second surface portion and not over the first surface portion; and
the BEOL layer comprises a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion.

US Pat. No. 10,600,658

APPARATUS AND METHOD FOR BENDING A SUBSTRATE

Infineon Technologies AG,...

1. A method, comprising:placing a substrate on a first curved surface of a first tool;
arranging a semiconductor body on the substrate;
using a second tool with a second surface to apply a first pressure to the substrate and to the semiconductor body arranged on the substrate so as to press the semiconductor body onto the substrate and the substrate onto the first curved surface of the first tool, and pre-bend the substrate with the semiconductor body mounted thereon;
removing the pre-bended substrate with the semiconductor body mounted thereon from the first tool; and
after removing the pre-bended substrate with the semiconductor body mounted thereon from the first tool, mounting the pre-bended substrate with the semiconductor body mounted thereon to a bended base plate or heat sink.

US Pat. No. 10,600,657

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MONOLITHIC 3D INC, San J...

1. A 3D semiconductor device, the device comprising:a first single crystal layer comprising a plurality of first transistors and a first metal layer,
wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;
a plurality of second transistors atop, at least in part said first single crystal layer;
a plurality of third transistors overlaying, at least in part said second transistors;
a second metal layer above, at least in part said third transistors;
Input/Output pads to provide connection to external devices;
a global power grid to distribute power to said device, said global power grid overlaying, at least in part said first metal layer; and
a local power grid to distribute power to said plurality of logic gates,
wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,
wherein said first single crystal layer comprises an Serializer/Deserializer (“SerDes”) structure connected to at least one of said Input/Output pads,
wherein said global power grid is connected to said local power grid by a plurality of vias,
wherein at least one of said plurality of vias has a radius of less than 200 nm,
wherein at least one of said third transistors comprises a source, a drain, and a transistor channel,
wherein said source, said drain and said transistor channel comprise a same dopant type,
wherein at least one of said third transistors is at least partially atop at least one of said first transistors, and
wherein a memory cell comprises at least one of said third transistors.

US Pat. No. 10,600,656

DIRECTED SELF-ASSEMBLY FOR COPPER PATTERNING

International Business Ma...

1. A process of forming patterned copper lines, comprising:assembling an etch stack, wherein the etch stack includes a resist, a hardmask, an organic planarizing layer (OPL), and a copper substrate, and wherein the copper substrate has been annealed at a temperature above 200° C.;
lithographically patterning the resist to produce a template;
forming a patterned block copolymer mask layer on the etch stack by directed self-assembly, wherein the patterned block copolymer includes a first block and a second block;
etching portions of the block copolymer mask layer, wherein the etching removes the first block to produce a first pattern;
etching the first pattern into the hardmask;
partially removing the second block;
etching the first pattern into the OPL, wherein the etching the first pattern includes removing the remainder of the second block and partially removing the patterned hardmask;
coating the patterned OPL with a coating material;
etching back a layer of the coating material and the remainder of the hardmask to expose the surface of the patterned OPL;
removing the patterned OPL to produce a second pattern; and
transferring the second pattern to the copper substrate to form the patterned copper lines, wherein the patterned copper lines have a pitch that is less than 30 nm.

US Pat. No. 10,600,654

ETCHING PROCESS METHOD

Tokyo Electron Limited, ...

1. An etching process method comprising:outputting a first high frequency power of a first frequency from a first high frequency power supply, and outputting a second high frequency power of a second frequency, which is lower than the first high frequency, from a second high frequency power supply in an environment where a substrate temperature is controlled to be less than or equal to ?35° C.;
adding a hydrocarbon gas containing at least 3 carbon atoms to an etching gas containing carbon, hydrogen, and fluorine for generating a plasma; and
etching a silicon oxide film or a laminated film made up of laminated layers of silicon-containing films having different compositions using generated plasma,
wherein the hydrocarbon gas contains one double bond between carbon atoms, and
wherein the hydrocarbon gas is butene.

US Pat. No. 10,600,653

METHOD FOR FORMING A FINE PATTERN

Samsung Electronics Co., ...

14. A method for forming a fine pattern, the method comprising:sequentially forming a lower layer and an organic mask layer on a semiconductor substrate;
forming a hard mask pattern on the organic mask layer, the hard mask pattern comprising: first line portions extending in parallel in a first direction; and a first connection portion between the first line portions adjacent to each other;
anisotropically etching the organic mask layer using the hard mask pattern as an etch mask to form an organic mask pattern which comprises: second line portions under the first line portions of the hard mask pattern; and a second connection portion under the first connection portion of the hard mask pattern; and
selectively ion-beam-etching the second connection portion of the organic mask pattern,
wherein the ion-beam-etching of the second connection portion comprises: irradiating an ion beam in an incident direction which is parallel to a plane defined by the first direction and a second direction perpendicular to a top surface of the semiconductor substrate, and
wherein the incident direction of the ion beam is not perpendicular to the top surface of the semiconductor substrate.

US Pat. No. 10,600,652

SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL

Deca Technologies Inc., ...

1. A system for removing material from a substrate, comprising:a conveyor comprising rollers configured to contact the substrate and advance the substrate by friction between moving rollers and the substrate;
a first blower disposed over the conveyor, the first blower forming a first air-knife comprising a width Wa1 in a range of 1-20 millimeters (mm), a length La1 greater than 200 mm;
a second blower disposed over the conveyor and offset from the first blower by a distance D that is less than a length Ls of the substrate and is less than 300 mm, the second blower forming a second air-knife comprising a width Wa2 in a range of 1-20 mm and a length La2 greater than 200 mm; and
an etching solution dispenser disposed over the conveyor and between the first blower or first air-knife and the second blower or second air-knife, the etching solution dispenser adapted for dispensing an etching solution onto the substrate on the conveyor within an etching area A defined as an area with a length equal to distance D and a width greater than 200 mm;
wherein the system for removing material from the substrate is without a bath and without a bowl for applying the etching solution to the substrate.

US Pat. No. 10,600,651

METHOD FOR MANUFACTURING EPITAXIAL SILICON WAFER AND VAPOR PHASE GROWTH DEVICE

SUMCO CORPORATION, Tokyo...

1. A manufacturing method of an epitaxial silicon wafer by forming an epitaxial film on a silicon wafer using a vapor deposition apparatus, the vapor deposition apparatus comprising:a reaction chamber configured to grow the epitaxial film;
a wafer-transfer chamber configured to receive the silicon wafer in a manner capable of transferring the silicon wafer to the reaction chamber through a communication portion configured to hermetically close or open the reaction chamber;
an exhaust device configured to exhaust the reaction chamber through an exhaust pipe connected to the reaction chamber: and
an exhaust regulator provided in the exhaust pipe and configured to increase the pressure in the reaction chamber, the exhaust regulator comprising:
a first regulator in a form of a hollow frustum comprising a first opening near the reaction chamber and a second opening near the exhaust device, the first opening being larger than the second opening; and
a second regulator provided near the exhaust device with respect to the first regulator, the second regulator being in a form of a hollow frustum comprising a third opening near the reaction chamber and a fourth opening near the exhaust device, the third opening being larger than the fourth opening,
wherein an inner diameter of the exhaust pipe, a diameter of the first opening and a diameter of the third opening are A, a diameter of the second opening is B and a diameter of the fourth opening is C,
B/A and C/A are 0.33 or less,
at least one of B/A and C/A is 0.26 or less, and
(B+C)/A is 0.59 or less,the method comprising:opening the communication portion while a pressure in the wafer-transfer chamber is higher than a pressure in the reaction chamber and the exhaust device exhausts the reaction chamber;
subsequently transferring the silicon wafer received inside the wafer-transfer chamber to the reaction chamber;
subsequently closing the communication portion;
subsequently increasing the pressure in the reaction chamber over a pressure when the communication portion is closed and decreasing the pressure to displace a deposit present in the exhaust pipe toward the exhaust device; and
subsequently starting a formation of the epitaxial film.

US Pat. No. 10,600,650

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a substrate, comprising:
a first buried layer and a second buried layer separated from each other;
a separation region between the first buried layer and the second buried layer;
a first doped region underneath the first buried layer; and
a second doped region underneath the second buried layer, and
a semiconductor layer positioned on the substrate and comprising a diffuse portion, wherein the diffuse portion overlaps the separation region, wherein a dopant of the diffuse portion is identical to a dopant of the separation region, wherein the first and the second buried layers both have a first conductive type, while the separation region, the first doped region, and the second doped region all have a second conductive type opposite to the first conductive type.

US Pat. No. 10,600,649

SYSTEMS AND METHOD FOR CHARGE BALANCED SEMICONDUCTOR POWER DEVICES WITH FAST SWITCHING CAPABILITY

GENERAL ELECTRIC COMPANY,...

1. A method of manufacturing a semiconductor device, comprising:performing a first implantation in a semiconductor layer via ion implantation, forming a first implantation region, wherein the semiconductor layer comprises a top epitaxial (epi) layer, wherein the top epi layer is disposed upon at least one epi layer having a first conductivity type that includes a plurality of charge balance (CB) regions having a second conductivity type to form at least one CB layer; and
performing a second implantation in the semiconductor layer via ion implantation, forming a second implantation region opposite the first implantation region, wherein the first and second implantation regions overlap with one another;
wherein the first and second implantation regions combine to form a connection region extending into the semiconductor layer to at least one of the plurality of CB regions of the at least one CB layer.

US Pat. No. 10,600,648

SILICON-BASED DEPOSITION FOR SEMICONDUCTOR PROCESSING

Lam Research Corporation,...

1. A method for processing a stack with a carbon based patterned mask in-situ, comprising:placing the stack in an etch chamber;
depositing by atomic layer deposition a silicon oxide layer over the carbon based patterned mask without consuming or attacking the carbon based patterned mask by providing a plurality of cycles, wherein each of the plurality of cycles comprises:
providing a silicon precursor deposition phase, comprising:
flowing an atomic layer deposition precursor gas comprising a silicon containing component into the etch chamber, where the atomic layer deposition precursor gas is deposited over the carbon based patterned mask, while plasmaless; and
stopping the flow of the atomic layer deposition precursor gas; and
providing an oxygen deposition phase, comprising:
flowing only an oxygen deposition gas consisting essentially of ozone gas into the etch chamber, wherein the ozone gas binds with the deposited precursor gas, while plasmaless; and
stopping the flow of the oxygen deposition gas into the etch chamber;
etching part of the silicon oxide layer, comprising:
flowing a shaping gas comprising a fluorocarbon into the etch chamber;
forming the shaping gas into a plasma, which etches the silicon oxide layer; and
stopping the flow of the shaping gas; and
removing the stack from the etch chamber.

US Pat. No. 10,600,647

COATING APPARATUS

SCREEN Holdings Co., Ltd....

1. A method of adjusting a coating apparatus comprising:a nozzle dispensing chemical to a substrate;
a pipe in communication with the nozzle;
a chemical supplying unit supplying the chemical through the pipe to the nozzle;
an open/close valve on the pipe between the nozzle and the chemical supplying unit, and having an open/close drive unit that allows adjustment of opening operation and closing operation in accordance with first electric signals, the open/close valve opening/closing the pipe; and
a suck back valve on the pipe between the nozzle and the open/close valve, and having a suction/push drive unit that allows adjustment of a volume variation in a flow path in communication with an upstream side and a downstream side of the pipe in accordance with second electric signals;
the method comprising:
a selecting step of selecting any nozzle-side filter of a plurality of nozzle-side filters having different respective fineness for providing the nozzle-side filter on the pipe between the nozzle and the suck back valve;
a first changing step of changing an operating amount of the closing operation of the open/close valve in accordance with the fineness of the selected nozzle-side filter for applying the first electric signals to the open/close drive unit; and
a second changing step of changing an operating amount of the suction operation of the suck back valve in accordance with the fineness of the selected nozzle-side filter for applying the second electric signals to the suction/push drive unit.

US Pat. No. 10,600,646

METHOD OF FABRICATING DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL

Samsung Electronics Co., ...

1. A method of fabricating a device comprising a two-dimensional (2D) material, the method comprising:forming a material pattern on a substrate;
forming an amorphous transition metal oxide structure on the substrate and the material pattern;
replacing the amorphous transition metal oxide structure with a transition metal dichalcogenide structure,
wherein the transition metal dichalcogenide structure includes atomic layers that are substantially parallel to a surface of the transition metal dichalcogenide structure, and the transition metal dichalcogenide structure includes a first portion on a top surface of the material pattern, a second portion on a side surface of the material pattern, and a third portion on a main surface of the substrate; and
removing the first portion of the transition metal dichalcogenide structure by forming a cover layer on the transition metal dichalcogenide structure, and polishing an upper portion of the cover layer and the first portion of the transition metal dichalcogenide structure to expose the top surface of the material pattern.

US Pat. No. 10,600,645

MANUFACTURING METHOD OF GALLIUM NITRIDE SUBSTRATE

Samsung Electronics Co., ...

1. A method of manufacturing a gallium nitride substrate, the method comprising:forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein due to the presence of one or more impurity particles and the silicon substrate is exposed through the one or more holes in the first buffer layer;
forming a silicon nitride region in the silicon substrate at the exposed portion of the silicon substrate;
forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and
forming a GaN layer on the second buffer layer,
wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

US Pat. No. 10,600,644

MONO- AND MULTILAYER SILICENE PREPARED BY PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION

The Government of the Uni...

1. A process for making a naturally hydrogenated silicene film, comprising the steps of:placing a substrate into a plasma-enhanced chemical vapor deposition (PECVD) chamber;
setting the substrate to a temperature of about 20 to about 290° C.;
providing a starting material comprising a mixture of H2 and SiH4 having an H2:SiH4 ratio between 100:1 and 400:1; and
depositing a two-dimensional silicene film on the substrate from the H2:SiH4 starting material by means of PECVD, deposition occurring for about 10 to 25 minutes at an RF power of about 10 W to about 90 W and a chamber pressure of about 100 mTorr to about 1300 mTorr.

US Pat. No. 10,600,643

METHOD OF FORMING THIN FILM AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME

Samsung Electronics Co., ...

1. A method of forming a thin film, the method comprising:forming a first reaction inhibiting layer chemisorbed on a first portion of a lower film by supplying a reaction inhibiting compound having a carbonyl group to an exposed surface of the lower film at a temperature of about 300° C. to about 600° C.;
forming a first precursor layer of a first material chemisorbed on a second portion of the lower film at a temperature of about 300° C. to about 600° C., the second portion being exposed through the first reaction inhibiting layer; and
forming a first monolayer containing the first material on the lower film by supplying a reactive gas to the first reaction inhibiting layer and the first precursor layer and removing the first reaction inhibiting layer from the surface of the lower film, and thus exposing the first portion.

US Pat. No. 10,600,642

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Kokusai Electric Corporat...

1. A method of manufacturing a semiconductor device, comprising:forming a film containing at least Si, O and N on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing:
forming a first layer by supplying a precursor gas containing at least a Si—N bond and a Si—Cl bond and a first catalyst gas to the substrate;
exhausting the precursor gas and the first catalyst gas in the process chamber through an exhaust system;
forming a second layer by supplying an oxidizing gas and a second catalyst gas to the substrate to modify the first layer; and
exhausting the oxidizing gas and the second catalyst gas in the process chamber through the exhaust system.

US Pat. No. 10,600,641

SILICON GERMANIUM SELECTIVE OXIDATION PROCESS

APPLIED MATERIALS, INC., ...

1. A selective oxidation method, comprising:forming a gate oxide on a substrate comprising a silicon material and a silicon germanium material, comprising:
heating a process region of a process chamber to a temperature less than about 700° C.;
pressurizing the process chamber to a pressure between about 7 Torr and about 550 Torr;
generating reactive species comprising hydrogen and oxygen in the process region, the ratio of oxygen to hydrogen between 19:1 and 1:9; and
exposing the substrate to the reactive species, the silicon germanium material selectively oxidized by the reactive species preferentially to the silicon material present on the substrate at an oxidation rate of between 2 times and 16 times greater than an oxidation rate of the silicon material; and
forming a gate on the substrate, the gate surrounding the gate oxide and the gate oxide surrounding the silicon material and the silicon germanium material.

US Pat. No. 10,600,640

REDUCTION OF SURFACE ROUGHNESS IN EPITAXIALLY GROWN GERMANIUM BY CONTROLLED THERMAL OXIDATION

Stratio, Inc., Palo Alto...

1. A method for reducing surface roughness in germanium, the method comprising:obtaining a substrate that includes a layer of germanium that has a top surface having a first surface roughness;
depositing a capping layer of silicon oxide on the top surface of the layer of germanium so that the capping layer covers the entire top surface of the layer of germanium; and
subsequent to the depositing, oxidizing the top surface of the layer of germanium through thermal oxidation by diffusing oxygen through the capping layer into the layer of germanium so that the top surface of the layer of germanium is converted into a layer of germanium oxide located on top of an unoxidized layer of germanium, causing a top surface of the unoxidized layer of germanium to have a second surface roughness that is less than the first surface roughness.

US Pat. No. 10,600,639

SIN SPACER PROFILE PATTERNING

Applied Materials, Inc., ...

1. An etching method comprising:oxidizing an exposed nitride surface on a semiconductor substrate within a processing region of a semiconductor processing chamber;
forming an inert plasma within the processing region of the semiconductor processing chamber;
modifying at least part of the oxidized nitride with effluents of the inert plasma;
forming a remote plasma from a fluorine-containing precursor to produce plasma effluents;
flowing the plasma effluents to the processing region of the semiconductor processing chamber; and
removing the modified oxidized nitride from the semiconductor substrate.

US Pat. No. 10,600,638

NANOSHEET TRANSISTORS WITH SHARP JUNCTIONS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, arranged such that a topmost and a bottommost layer of the nanosheet stack is one of the plurality of sacrificial layers;
forming an oxide recess on a first and a second end of each sacrificial layer;
forming a doped extension region on a first and a second end of each nanosheet;
removing a portion of the nanosheet stack to expose a first and second end of the nanosheet stack and a first and second portion of the substrate;
forming a dielectric layer on the nanosheet stack;
forming a sacrificial gate having a first and a second gate sidewall on the dielectric layer, a top surface of the sacrificial gate covered by a hard mask;
forming a first outer spacer on the first gate sidewall and a first surface of the hard mask;
forming a second outer spacer on the second gate sidewall and a second surface of the hard mask;
forming a first and a second epitaxy on the exposed first and second portion of the substrate;
forming an interlayer dielectric (ILD) on the first and second epitaxy; and
replacing the sacrificial gate and sacrificial layers with a metal gate having a high-k dielectric liner.

US Pat. No. 10,600,637

FORMATION OF SIOC THIN FILMS

ASM IP Holding B.V., Alm...

1. A method of forming a silicon oxycarbide (SiOC) thin film on a substrate in a reaction space by a plasma enhanced atomic layer deposition (PEALD) process, wherein the PEALD process comprises at least one deposition cycle comprising:contacting a surface of the substrate with a vapor phase silicon precursor that does not comprise nitrogen, wherein the vapor phase silicon precursor comprises bis(triethoxysilyl)ethane (BTESE) or 3-methoxypropyltrimethoxysilane (MPTMS);
contacting the surface of the substrate with at least one reactive species generated by plasma formed from a second reactant comprising hydrogen, wherein the second reactant does not comprise oxygen; and
optionally repeating the contacting steps until a SiOC film of a desired thickness has been formed.

US Pat. No. 10,600,636

TOUCH SUBSTRATE AND FABRICATION METHOD THEREOF, AND ELECTRONIC DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A fabrication method of a touch substrate, comprising:providing a substrate; and
sequentially forming a first touch electrode layer, a first insulating layer, a second touch electrode layer, and a second insulating layer on the substrate, wherein the first touch electrode layer comprises a first touch electrode, and the second touch electrode layer comprises a second touch electrode; and
wherein the step of forming the first insulating layer and the step of forming the second insulating layer are performed by using a single mask.

US Pat. No. 10,600,635

METHOD AND APPARATUS FOR A SEMICONDUCTOR-ON-HIGHER THERMAL CONDUCTIVE MULTI-LAYER COMPOSITE WAFER

1. A method for fabricating a cost-effective semiconductor on higher-thermal conductive multilayer (ML) composite wafer, the method comprising the steps of: taking a semiconductor host wafer having a first and a second host wafer surface and preparing the first host wafer surface growing a transitional layer (TL) having properties of limiting diffusion on the first host wafer surface having no implantation process; depositing a uniform and low-defect additional layer (AL) on the TL; polishing the AL to prepare for bonding; taking a sacrificial semiconductor wafer, having a first and second sacrificial wafer surface, and bonding the first sacrificial wafer surface to the AL at room temperature; removing the sacrificial wafer from the AL and recycling the sacrificial wafer for future use; and grinding and polishing the second host wafer surface; whereby the second host wafer surface becomes a starting surface of the ML composite wafer for device manufacturing.

US Pat. No. 10,600,634

SEMICONDUCTOR SUBSTRATE POLISHING METHODS WITH DYNAMIC CONTROL

GlobalWafers Co., Ltd., ...

1. A method for polishing a semiconductor substrate having a front surface and a back surface generally parallel to the front surface, the method comprising:rough polishing a semiconductor substrate by contacting the semiconductor substrate with an abrasive slurry to produce a rough-polished semiconductor substrate;
analyzing the rough-polished semiconductor substrate to measure the edge roll-off of the rough-polished semiconductor substrate, the rough-polished semiconductor substrate having a central axis, the edge roll-off being measured at a reference point, the distance between the central axis and the reference point being about 98.0% or more of the radius of the rough-polished semiconductor substrate;
contacting a front surface of the rough polished semiconductor substrate or a front surface of a different semiconductor substrate with a polishing pad to finish polish the front surface;
supplying a first polishing slurry comprising silica to the polishing pad at a first polishing slurry volume;
supplying a second polishing slurry to the polishing pad at a second polishing slurry volume, the first and second polishing slurries being supplied to finish polish the front surface of the semiconductor substrate, the first polishing slurry comprising a higher concentration of silica relative to the second slurry; and
controlling an amount of at least one of the first polishing slurry and the second polishing slurry supplied to the polishing pad as a whole during the finish polish based on the measured edge roll-off,
wherein the amount of the at least one of the first polishing slurry and the second polishing slurry supplied to the polishing pad is controlled by controlling a ratio of the first polishing slurry volume to the second polishing slurry volume.

US Pat. No. 10,600,633

GAS DISCHARGE LAMP

Jelight Company, Inc., I...

1. A gas discharge lamp comprising:an elongate tubular envelope having an integrally formed partition extending axially from one end of the elongate tubular envelope and defining a pair of bores within an interior of the elongate tubular envelope disposed on opposite sides of the partition;
a pair of electrodes, with one electrode disposed within each of the pair of bores; and
an upper surface disposed at the opposite end of the elongate tubular envelope;
wherein sides of the partition contact the elongate tubular envelope, the partition contacts the upper surface, and the partition comprises a notch formed therein, the notch contacting the upper surface and forming an exclusive passageway between the pair of bores.

US Pat. No. 10,600,632

METHODS FOR OPERATING ELECTROSTATIC TRAP MASS ANALYZERS

Thermo Finnigan LLC, San...

1. A method of operating an electrostatic trapping mass analyzer, comprising:operating the electrostatic trapping mass analyzer at a maximum resolution so as to acquire a transient signal of a sample;
partitioning the transient signal into signal segments;
defining a test transient as being equal to a first one of the segments;
calculating a mathematical transform of the test transient and thereby generating a spectrum of component frequencies of the test transient;
determining a quality metric from the spectrum of component frequencies and comparing the quality metric to either a pre-determined minimum threshold value or a pre-determined maximum threshold value;
performing, while the most-recently-determined quality metric is either less than the pre-determined minimum threshold value or greater than the pre-determined maximum threshold value, the steps of;
appending a next signal segment onto the test transient;
re-defining the test transient as being the previously-defined test transient having the appended next signal segment appended thereto;
calculating a mathematical transform of the test transient and thereby generating a new spectrum of component frequencies of the test transient; and
re-determining the quality metric from the new spectrum of component frequencies; and
setting an instrumental resolution to be employed for subsequent mass spectral data acquisitions in accordance with a length of the most-recently-defined test transient.

US Pat. No. 10,600,631

ION TRAP

SHIMADZU CORPORATION, Ky...

1. An ion trap having:a segmented electrode structure having a plurality of segments consecutively positioned along an axis, wherein each segment of the segmented electrode structure includes a plurality of electrodes arranged around the axis;
a first voltage supply configured to operate in a radially confining mode in which at least some electrodes belonging to each segment are supplied with at least one AC voltage waveform so as to provide a confining electric field for radially confining ions within the segment;
a second voltage supply configured to operate in a trapping mode in which at least some of the electrodes belonging to the segments are supplied with different DC voltages so as to provide a trapping electric field that has an axially varying profile for urging ions towards and trapping ions in a target segment of the plurality of segments;
a first chamber configured to receive ions from an ion source, wherein a first subset of the segments are located within the first chamber;
a second chamber configured to receive ions from the first chamber, wherein a second subset of the segments are located within the second chamber, and wherein the target segment is one of the second subset of segments;
a gas pump configured to pump gas out from the second chamber so as to provide the second chamber with a lower gas pressure than the first chamber;
a gas flow restricting section located between the first chamber and second chamber, wherein the gas flow restricting section is configured to allow ions to pass from the first chamber to the second chamber whilst restricting gas flow from the first chamber to the second chamber,
wherein the gas flow restricting section includes a wall between the first chamber and the second chamber, with at least one aperture being formed in the wall to allow ions to pass from the first chamber to the second chamber whilst restricting gas to flow from the first chamber to the second chamber, wherein the at least one aperture in the wall of the gas flow restricting section houses one or more gas flow restricting segments of the plurality of segments, and wherein the one or more gas flow restricting segment has an inscribed radius that is smaller than the inscribed radius of a segment that is located entirely in the first chamber.

US Pat. No. 10,600,630

OVERSAMPLED TIME OF FLIGHT MASS SPECTROMETRY

Micromass UK Limited, Wi...

1. A method of mass spectrometry comprising:passing ions to a Time of Flight mass analyser operating in an oversampling mode of operation wherein ions are pulsed into a Time of Flight region with a pulse rate such that packets or groups of ions associated with multiple different pulses are simultaneously present in the Time of Flight region; and
alternately or sequentially recording ion signals for said ions on a plurality of different channels such that the channel on which the ion signals are recorded changes over time, in order to obtain a plurality of first oversampled mass spectral data sets, each containing overlapping mass spectra associated with packets or groups of ions from multiple different pulses that were simultaneously present in the Time of Flight region, each oversampled mass spectral data set being associated with one of the plurality of different channels, wherein ions arriving at the Time of Flight mass analyser during a first time period are recorded on a first channel to obtain an associated oversampled mass spectral data set and wherein ions arriving at the Time of Flight mass analyser at a second, different time period are recorded on a second channel to obtain another associated oversample mass spectral data set.

US Pat. No. 10,600,629

DETECTION OF ANALYTES USING POROUS MASS SPECTROMETRY SURFACE

THE REGENTS OF THE UNIVER...

1. A method for making a porous semiconductor substrate for ionizing a target comprising:(a) providing a semiconductor material;
(b) determining a desired length of etching time of the semiconductor material based on the molecular weight of the target, and determining a desired porosity wherein the desired porosity is determined to be no more than 40% if the target is larger than 2000 Daltons in molecular weight;
(c) etching the semiconductor material for the desired length of etching time to produce an etched semiconductor material; and
(d) contacting the etched semiconductor material with an initiator to produce the porous semiconductor substrate.

US Pat. No. 10,600,628

RESONANT TRANSMISSION LINE TO DELIVER PRECISION RF VOLTAGE

MKS Instruments, Inc., A...

22. A method of conveying a time-varying voltage signal from a signal generation, control, and analysis subsystem to a quadrupole analyzer, and for monitoring and adaptively controlling an amplitude of the time-varying voltage signal, comprising:electrically coupling the time-varying voltage signal to a first end of a transmission line, the transmission line extending from the first end at the signal generation, control, and analysis subsystem to a second end at the quadrupole analyzer,
configuring a physical length of the transmission line to correspond to an electrical length substantially equal to a positive integer multiple of one half wavelength of the time-varying voltage signal;
sampling, with a rectifier circuit, the time-varying voltage coupled to the first end to produce a feedback signal, and conveying the feedback signal to an adaptive control facility, the adaptive control facility configured to adjust a generator of the time-varying voltage signal, based on a sampling of the time-varying voltage signal at the first end, to maintain the amplitude of the time-varying voltage signal at a required level; and
increasing an amplitude of the time-varying voltage signal with at least one transformer at the second subsystem, the at least one transformer electrically coupled to the second end.

US Pat. No. 10,600,627

HYBRID MASS SPECTROMETER

Micromass UK Limited, Wi...

14. A method of mass spectrometry comprising:separating ions temporally in a first device;
analysing the mass or mass to charge ratio of ions in a mass or mass to charge ratio analyser disposed downstream of said first device;
determining the transit time of ions through an one or more intermediate regions or devices disposed between said first device and said mass to charge ratio analyser; and
switching or adjusting the operation of one or more devices disposed between said first device and said mass or mass to charge ratio analyser based on the determined transit time of ions through said one or more intermediate regions or devices.

US Pat. No. 10,600,626

MASS CALIBRATION DEVICE FOR A MASS SPECTROMETER

THERMOS FINNIGAN LLC, Sa...

1. A gas delivery apparatus for delivering a calibrant gas mixture to an ionization chamber of a mass spectrometer, comprising:(a) a plurality of separated liquid calibrants in a calibration receptacle having a common headspace, wherein the calibrant gas mixture forms;
(b) a vacuum pump operably connected with the mass spectrometer;
(c) a multiport valve for diverting the calibrant gas mixture in the common headspace to the ionization chamber or to the vacuum pump; and,
(d) a flow restrictor for metering the calibrant gas mixture from the common headspace to the ionization chamber.

US Pat. No. 10,600,625

METHOD OF CALIBRATING A MASS SPECTROMETER

Thermo Fisher Scientific ...

1. A method of operating a mass spectrometer, comprising:i) calibrating a mass analyzer at a first time t1 while operating a first quadrupole in a transmission mode in which ions are not mass selected,
ii) calibrating the first quadrupole in a mass selecting mode selecting masses in a mass filter window having a filter window width wcal at a second time t2 later than the first time t1 when the mass analyzer is operated in a mass analysing mode, wherein calibrating the first quadrupole comprises the steps of:
ii a) determining individually for each of several selected masses mcal a corresponding value of an amplitude of the RF voltage RFdet(mcal) and value of DC voltage DCdet(mcal) applied to the electrodes of the first quadrupole,
ii b) fitting a function RFfit(m, wcal) of a selected mass m to values of the amplitude of the RF voltage RFdet(mcal) corresponding to the several selected masses mcal and DCfit(m, wcal) of the selected mass m to the values of DC voltages DCdet(mcal) corresponding to the several selected masses mcal,
ii c) detecting one or more selected masses (mcheck) at a detection means via the mass analyzer operating in a mass analysing mode during scanning the first quadrupole operating as a pre-selecting analyzer in the mass selecting mode, selecting masses in the mass filter window having the filter window width wcal over a mass range ?mass_m_check assigned to the mass mcheck, comprising the mass mcheck and being larger than the filter window width wcal of the mass filter window of the mass selecting mode of the first quadrupole, the amplitude of the RF voltage applied to the electrodes of the first quadrupole given by a function RFfit(m, wcal) and a DC voltage applied to the electrodes of the first quadrupole given by a function DCfit(m, wcal);
ii d) evaluating for each of these detected masses mcheck a shift of the peak position ?m(mcheck) or a deviation of a filter window width ?w(mcheck) of the mass selecting mode of the first quadrupole selecting masses in the mass filter window having the filter window width wcal, when applying a RF voltage with an amplitude given by the function RFfit(m, wcal) and the DC voltage given by a function DCfit(m, wcal); and,
ii e) if evaluated values of the shift of the peak position ?m(mcheck) or the deviation of the filter window width ?w(mcheck) of the detected masses mcheck do not comply with a quality condition of a calibration or if another repetition condition is fulfilled, repeating calibration steps ii a) to ii e) until all quality conditions of the calibration are fulfilled and no repetition condition is fulfilled or the calibration steps ii a) to ii e) have been executed N times and
iii) after completion of the calibration steps, operating the first quadrupole to filter ions using RF and DC voltages determined respectively by the RFfit(m, wcal) and DCfit (m,wcal) functions derived in step iib).

US Pat. No. 10,600,624

SYSTEM AND METHOD FOR SUBSTRATE PROCESSING CHAMBERS

APPLIED MATERIALS, INC., ...

1. A processing chamber system, comprising:a chamber body having a chamber base, one or more sidewalls, and a chamber lid defining a processing volume,
wherein the chamber lid comprises a showerhead;
a substrate support disposed in the processing volume, the substrate support having a first surface, a second surface opposite the first surface, and a third surface connecting the first surface and the second surface around a circumference of the substrate support;
wherein the processing volume comprises:
a first volume defined by the first surface of the substrate support and a surface of the showerhead that faces the processing volume, and
a second volume defined by the second surface of the substrate support and a surface of the chamber base that faces the processing volume;
a purge gas inlet that is configured to introduce a purge gas into the second volume through one or more openings;
a precursor inlet that is configured to introduce a precursor gas into the first volume through the showerhead;
a combined gas exhaust volume that is configured to evacuate the purge gas and the precursor gas, wherein the precursor gas is evacuated from the first volume to the combined gas exhaust volume through a first gas inlet and the purge gas is evacuated from the second volume to the combined gas exhaust volume through a second gas inlet; and
one or more heaters disposed in the showerhead that are configured to heat the showerhead.

US Pat. No. 10,600,623

PROCESS KIT WITH ADJUSTABLE TUNING RING FOR EDGE UNIFORMITY CONTROL

APPLIED MATERIALS, INC., ...

1. A process kit for a substrate processing chamber, comprising:an edge ring having a first ring component and a second ring component, the first ring component interfaced with the second ring component such that the second ring component is movable relative to the first ring component forming a gap therebetween, the second ring component having an upper surface and a lower surface, the second ring component has an inner thickness and an outer thickness, the inner thickness is less than the outer thickness, and at least a portion of the upper surface of the second ring component is inwardly angled towards the first ring component;
an adjustable tuning ring positioned beneath the edge ring, the adjustable tuning ring having an upper surface and a lower surface, and the upper surface of the adjustable tuning ring contacting the lower surface of the second ring component; and
an actuating mechanism interfaced with the lower surface of the adjustable tuning ring, the actuating mechanism configured to actuate the adjustable tuning ring such that the gap between the first ring component and the second ring component is varied.

US Pat. No. 10,600,622

FOCUS RING WITH UNEVEN PATTERN AND PLASMA-PROCESSING APPARATUS INCLUDING THE SAME

SAMUSUNG ELECTRONICS CO.,...

1. A focus ring, comprising:a main body having a ring shape; and
a plurality of unit structures arranged in an uneven pattern and protruding from an upper surface of the main body, the plurality of unit structures being spaced apart from each other along an outer circumference of the main body.

US Pat. No. 10,600,621

PLASMA ELECTRODE AND PLASMA PROCESSING DEVICE

TOKYO ELECTRON LIMITED, ...

1. A plasma electrode, comprising:a first electrode plate having a plurality of cylindrical protrusions and to which high frequency power is applied;
a ground plate provided with a plurality of cylindrical first through holes having an inner diameter larger than an outer diameter of the protrusions; and
an insulating plate provided with a plurality of cylindrical second through holes having an inner diameter larger than the outer diameter of the protrusions and disposed between the first electrode plate and the ground plate,
wherein the first electrode plate, the insulating plate, and the ground plate are overlappingly arranged so that the protrusions are arranged inside the first through holes and the second through holes,
a third through hole is provided in each of the protrusions along a center axis of each of the protrusions,
a first flow path is provided between the first electrode plate and the insulating plate,
a second flow path communicating with the first flow path is provided around the protrusions,
a fourth through hole is provided in the ground plate around each of the first through holes,
one of the third through hole and the fourth through hole discharges a first processing gas to below the ground plate,
the other of the third through hole and the fourth through hole exhausts a gas existing below the ground plate,
the second flow path communicates with a gap formed between outer walls of the protrusions and inner walls of the first through holes, and supplies a second processing gas supplied via the first flow path to the gap,
the second processing gas supplied to the gap is converted into plasma in the gap by the high frequency power applied to the first electrode plate,
the third through hole discharges the first processing gas to below the ground plate,
the fourth through hole exhausts the gas existing below the ground plate, and
the fourth through hole has a center axis arranged at a position equidistant from center axes of three adjacent third through holes in the ground plate.

US Pat. No. 10,600,620

TEMPERATURE CONTROL IN RF CHAMBER WITH HEATER AND AIR AMPLIFIER

Lam Research Corporation,...

1. An apparatus, comprising:a heater for receiving and heating a flow of air;
an air amplifier coupled to pressurized gas, the air amplifier having an input that receives the flow of air from the heater, the air amplifier having an output;
a duct coupled to the output of the air amplifier;
a plenum being defined by a partial enclosure having a top surface and side walls, wherein the top surface has an inlet and an open bottom, and wherein the side walls have outlets, the duct is coupled to the inlet and the open bottom of the plenum is placed over a window of a plasma chamber so that the flow of air is distributed over the window;
a temperature sensor situated about the window of the plasma chamber; and
a controller defined to control the air amplifier and the heater based on a temperature measured by the temperature sensor.

US Pat. No. 10,600,619

PLASMA PROCESSING APPARATUS

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus, comprising:a processing chamber configured to plasma etch a wafer;
a radio-frequency power supply configured to supply radio-frequency power for generating plasma into the processing chamber;
a pulse generator configured to generate pulse for ON-OFF modulation of the radio-frequency power;
a sample stage configured to hold the wafer;
a control computer configured to control the radio-frequency power supply so as to provide a power value in a region in which plasma instability does not occur when generating plasma by continuous discharge to the processing chamber, and
control the pulse generator so as to generate the pulse of a duty ratio so as to control the time average value of the power by ON-OFF modulating the power of the power supply, setting the peak power during ON to a value which when plasma is generated by continuous discharge, instability of the plasma does not occur, and changing a duty ratio of the ON-OFF modulation.

US Pat. No. 10,600,618

PLASMA GENERATION APPARATUS, SUBSTRATE TREATING APPARATUS INCLUDING THE SAME, AND CONTROL METHOD FOR THE PLASMA GENERATION APPARATUS

Semes Co., Ltd., Chungch...

1. An apparatus for treating a substrate, the apparatus comprising:a chamber having a space therein in which the substrate is treated;
a support unit configured to support the substrate in the chamber;
a gas supply unit configured to supply gas into the chamber; and
a plasma generation unit configured to excite the gas in the chamber into a plasma state,
wherein the plasma generation unit includes:
a high-frequency power supply;
a first antenna connected to one end of the high-frequency power supply;
a second antenna connected with the first antenna in parallel; and
a current divider configured to distribute electric current to the first antenna and the second antenna,
wherein the current divider includes:
a first capacitor connected between the first antenna and the second antenna;
a second capacitor connected with the second antenna in parallel; and
a third capacitor connected with the second antenna in series, and
wherein the second capacitor and the third capacitor are implemented with a variable capacitor.

US Pat. No. 10,600,617

PLASMA PROCESSING APPARATUS

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus comprising:a vacuum chamber that is grounded, the vacuum chamber configuring a vacuum container and a cover member disposed on an upper part of the vacuum chamber;
an inner chamber disposed in the vacuum chamber, the inner chamber having an inner chamber to which a processing gas is supplied to form plasma, the inner chamber being detachable from the vacuum chamber;
a sample stage disposed at a center part in the inner chamber, the sample stage on which a wafer is placed on a top face of the sample stage;
an evacuation opening disposed on a center part of a bottom part of the inner chamber below the sample stage, the evacuation opening through which an inside of the inner chamber is evacuated;
a vacuum pump disposed below the sample stage below the vacuum chamber, the vacuum pump being configured to communicate with the evacuation opening to evacuate the inside of the inner chamber;
a sample stage ring base disposed in the inner chamber, the sample stage ring base being disposed in a ring shape around below the sample stage, the sample stage ring base being coupled to the sample stage through a support beam horizontally extending;
a suspension beam vertically disposed extending in a space between the vacuum chamber and inner chamber, the suspension beam being coupled to the sample stage ring base, the suspension beam being configured to suspend the sample stage and support the sample stage from above; and
a piping disposed on an inner side of the suspension beam and the support beam, the piping through which a liquid to be supplied to an inside of the sample stage is circulated,
wherein in a state in which the cover member is placed on the vacuum chamber and an inside of the vacuum chamber is hermetically sealed,
the inner chamber is placed on the sample stage ring base and an inside of the inner chamber is hermetically sealed to the vacuum chamber and is hermetically sealed to an outside of the vacuum chamber,
the suspension beam is vertically movably held a space sandwiched between a sample stage base plate and the cover member of the vacuum container, the sample stage base plate having an upper part configuring the upper part of the vacuum chamber, the sample stage base plate covering an inside of the vacuum container, and
the plasma processing apparatus includes a conductive connector held on the sample stage base plate being sandwiched between the sample stage base plate and an upper member made of SUS of the suspension beam.

US Pat. No. 10,600,616

APPARATUS AND TECHNIQUES TO TREAT SUBSTRATES USING DIRECTIONAL PLASMA AND POINT OF USE CHEMISTRY

Varian Semiconductor Equi...

1. A method of treating a substrate, comprising:extracting a plasma beam from a plasma in a plasma chamber, wherein the plasma beam is extracted through an extraction aperture of an extraction plate and comprises ions forming a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate; and
directing a reactive gas from a gas source to the substrate through a plurality of gas orifices extending along top and bottom sides of the extraction aperture, wherein the reactive gas does not pass through the plasma.

US Pat. No. 10,600,615

ENHANCED FIB-SEM SYSTEMS FOR LARGE-VOLUME 3D IMAGING

Howard Hughes Medical Ins...

1. A microscopy system for imaging a sample, the microscopy system comprising:a focused ion beam system configured to direct a focused ion beam onto a sample;
a scanning electron microscope system configured to direct an electron beam onto the sample; and
a plurality of charged-particle detectors, each detector being configured to monitor an electrical current on the detector, wherein the plurality of charged particle detectors includes a movable shutter located between the sample and the scanning electron microscope system, the shutter being configured to be moved automatically into a position between the sample and the scanning electron microscope system, so that when the electron beam is not irradiating the sample the shutter is positioned between the sample and the scanning electron microscope system and blocks sputtered ions produced by the focused ion beam directed onto the sample from entering a column of the scanning electron microscope system; and
a control computer configured to receive a plurality of signals indicative of the electrical currents on the plurality of charged particle detectors and configured to control automatically properties of a focused ion beam produced by the focused ion beam system in response to the received signals when the shutter is positioned between the sample and the scanning electron microscope system.

US Pat. No. 10,600,614

STAGE DEVICE AND CHARGED PARTICLE BEAM DEVICE

Hitachi High-Technologies...

1. A stage device comprising:a table loaded with a sample;
a first actuator or motor configured to move the table in an X direction;
a mirror mounted on the table;
a laser interferometer radiating a laser beam towards the mirror and receiving reflected light from the mirror to measure a position of the table in the X direction;
a second actuator or motor configured to move the table in a Z direction; and
an optical axis actuator or motor configured to move an optical axis of the laser interferometer in the Z direction.

US Pat. No. 10,600,613

PARTICLE BEAM SYSTEM

Carl Zeiss Microscopy Gmb...

1. A multi-beam apparatus for observing a surface of a sample, comprising:an electron source;
a collimating lens below said electron source;
a source-conversion unit below said collimating lens;
a primary projection imaging system below said source-conversion unit;
a deflection scanning unit below said source-conversion unit;
a sample stage below said primary projection imaging system;
a beam separator below said source-conversion unit;
a secondary projection imaging system above said beam separator; and
an electron detection device with a plurality of detection elements,
wherein said electron source, said collimating lens and said source-conversion unit are aligned with a primary optical axis of said apparatus, and said sample stage sustains said sample so that said surface faces to said primary projection imaging system,
wherein said source-conversion unit comprises a beamlet-forming means with a plurality of beam-limit openings and an image-forming means with a plurality of electron optics elements each having a micro-multipole-lens,
wherein said electron source generates a primary-electron beam along said primary optical axis, and said collimating lens collimates said primary-electron beam into said source-conversion unit,
wherein a plurality of beamlets of said primary-electron beam respectively passes through said plurality of beam-limit openings and is focused to form a plurality of parallel images of said electron source by said plurality of electron optics elements respectively, and said plurality of beam-limit openings limits currents of said plurality of beamlets,
wherein said primary projection imaging system projects said plurality of parallel images onto said surface and therefore said plurality of beamlets forms a plurality of probe spots thereon, said micro-multipole-lens of said each electron optics element compensates off-axis aberrations of one corresponding probe spot, and said deflection scanning unit deflects said plurality of beamlets to scan said plurality of probe spots respectively over a plurality of scanned regions within an observed area on said surface,
wherein a plurality of secondary electron beams is generated by said plurality of probe spots respectively from said plurality of scanned regions and directed into said secondary projection imaging system by said beam separator, said secondary projection imaging system focuses and keeps said plurality of secondary electron beams to be detected by said plurality of detection elements respectively, and each detection element therefore provides an image signal of one corresponding scanned region.

US Pat. No. 10,600,612

CHARGED PARTICLE BEAM APPARATUS

HITACHI HIGH-TECH SCIENCE...

1. A charged particle beam apparatus, comprising:a sample stage on which a sample is placed;
a sample chamber receiving the sample stage therein;
a charged particle beam column irradiating the sample with a charged particle beam;
an electrode member provided to be displaceable between an insertion position, the insertion position being between a beam emitting end portion of the charged particle beam column and the sample stage, and a withdrawal position distant from the insertion position, the electrode member being provided with a penetrating hole through which the charged particle beam passes at the insertion position;
driving means displacing the electrode member;
a power source applying negative voltage to the electrode member from outside the sample chamber to decelerate the charged particle beam with respect to the sample; and
an electrical insulation member electrically insulating the sample chamber and the driving means from the electrode member.

US Pat. No. 10,600,611

ION SOURCE CRUCIBLE FOR SOLID FEED MATERIALS

Applied Materials, Inc., ...

1. An indirectly heated cathode ion source, comprising:an arc chamber, comprising a plurality of electrically conductive side walls connecting a first end and a second end;
an indirectly heated cathode disposed on the first end of the arc chamber; and
a crucible disposed on the second end of the arc chamber, wherein the crucible comprises a target holder having a recessed cavity into which a feed material is disposed.

US Pat. No. 10,600,610

SUBSTRATE TREATMENT APPARATUS

JUSUNG ENGINEERING CO., L...

1. A substrate treatment apparatus, comprising:a chamber comprising a first side having a substrate entrance for carrying a substrate and a second side arranged on opposite sides of the chamber, said chamber providing a reaction region;
an upper electrode arranged in the reaction region;
a gas supply line connected to the upper electrode;
a substrate holder facing the upper electrode and configured to receive the substrate thereon; and
a plurality of feeding lines for applying an RF power to the upper electrode including first and second feeding lines electrically connected in parallel with each other,
wherein the first feeding line is connected to the gas supply line at a first point corresponding to a center of the upper electrode,
wherein the second feeding line is connected to the upper electrode at a second point spaced apart from the first point toward the substrate entrance,
wherein the plurality of feeding lines form an asymmetrical arrangement with respect to the upper electrode,
wherein the substrate entrance is not formed at the second side of the chamber, and
wherein the second feeding line is not arranged on one side of the upper electrode adjacent to the second side to form the asymmetrical arrangement in plan view.

US Pat. No. 10,600,609

HIGH-POWER X-RAY SOURCES AND METHODS OF OPERATION

Rapiscan Systems, Inc., ...

1. A high power radiation production target assembly comprising:a target sub-assembly having a copper body and a target positioned along a periphery of the copper body, wherein said target is configured to be impinged by a stream of particles to produce radiation;
a plurality of paddles positioned on said copper body;
a stream of liquid adapted to propel said paddles thereby causing a rotation and a cooling of said copper body; and,
at least one coupling configured to provide vacuum sealing under rotation.

US Pat. No. 10,600,608

ION SOURCE

NISSIN ION EQUIPMENT CO.,...

1. An ion source comprising:a plasma generation chamber into which a halogen-containing material is supplied;
a plate member on an end of the plasma generation chamber on a side toward which an ion beam is extracted; and
an extraction electrode disposed downstream of the plate member,
wherein the plate member is formed with a gas supply passage via which hydrogen gas is supplied to the extraction electrode.

US Pat. No. 10,600,607

SYSTEM WITH A HIGH-POWER MICROWAVE VACUUM TUBE (HPM-VT) DEVICE HAVING NON-EVAPORABLE GETTERS (NEG) INTEGRATED IN AN RF CAVITY

LOCKHEED MARTIN CORPORATI...

1. A device, comprising:an RF cavity enclosure including a conductive tubular section having a plurality of interior structures radially or axially arranged which forms an unobstructed inner hollow center within the tubular section, each interior structure of the plurality of interior structures includes side walls between which is formed an internal hollow sub-cavity;
resonating cavities within the RF cavity enclosure between adjacent interior structures to produce a resonating frequency response; and
vents formed in at least one side wall of said each interior structure for permeation of a gas into the internal hollow sub-cavity.

US Pat. No. 10,600,606

VERTICAL VACUUM CHANNEL TRANSISTOR WITH MINIMIZED AIR GAP BETWEEN TIP AND GATE

International Business Ma...

1. A semiconductor structure for controlling an electric field from a gate structure, the semiconductor structure comprising:a fin stack including a plurality of layers disposed between inner surfaces of a first dielectric layer;
a conductive material disposed in direct contact with outer surfaces of the first dielectric layer; and
an air gap defined within the fin stack with epitaxial growths disposed therein.

US Pat. No. 10,600,605

APPARATUS FOR AGING FIELD EMISSION DEVICE AND AGING METHOD THEREOF

ELECTRONICS AND TELECOMMU...

1. An apparatus for aging a field emission device configured to emit electrons based on an electric field between a first electrode and a second electrode of the field emission device, the apparatus comprising:a voltage generator configured to increase a voltage applied to the first electrode of the field emission device to a target voltage level during a first time; and
a current controller configured to increase a field emission current of the field emission device to a target current level during a second time after the first time and increase a pulse width of the field emission current having the target current level to a target pulse width during a third time after the second time.

US Pat. No. 10,600,603

SWITCHING DEVICE AND SWITCH-OFF METHOD FOR OPERATING A SWITCHING DEVICE

Siemens Aktiengesellschaf...

1. A switching device, comprising:a first conventional switching point, a second conventional switching point and a non-conventional switching point together forming a series circuit;
said series circuit configured to intentionally ignite an arc in at least one of the conventional switching points when the conventional switching points are switched off; and
said non-conventional switching point being a thyristor.

US Pat. No. 10,600,602

FUSE ELEMENT AND FUSE DEVICE

DEXERIALS CORPORATION, T...

1. A fuse element constituting a current path of a fuse device in which self-generated heat caused by a rate-exceeding current flowing therethrough causes blowout of the fuse element comprising:a low melting point metal layer; and
a high melting point metal layer laminated onto the low melting point metal layer, the high melting point metal layer having a melting point higher than a melting point of the low melting point metal layer;
wherein the fuse element is connected between two electrodes on an insulating substrate and connected onto the electrodes by a solder at a reflow temperature of the solder,
wherein the fuse element has a laminated structure in which the low melting point metal layer is an inner layer and the high melting point metal layer is an outer layer laminated on an upper surface and on a lower surface of the low melting point metal layer, and
wherein the melting point of the low melting point metal layer and a melting point of the solder are equal to or lower than 260° C., and
wherein the low melting point metal layer and the solder are melted at the reflow temperature of the solder.

US Pat. No. 10,600,601

TUNING FORK TERMINAL SLOW BLOW FUSE

Littelfuse, Inc., Chicag...

1. A fuse comprising:a housing having an upper portion and a lower portion;
a plurality of terminal portions disposed in the lower portion of the housing, each of said terminal portions having first and second prongs and a gap disposed therebetween, wherein the gap narrows from a first width adjacent an upper end of said first and second prongs to a second width adjacent a lower end of said first and second prongs, said gap configured to receive terminals therein; and
a fusible link disposed in the upper portion of the housing and between said plurality of terminal portions, said fusible link configured to interrupt current flowing between said plurality of terminal portions upon certain high current conditions; and
a partition disposed in said lower portion of said housing, wherein a distance between each of the second prongs and the partition increases from a first end of each of the second prongs proximate the upper portion to a second end of each of the second prongs distal from the upper portion for allowing the second ends to be displaced a distance toward the partition before engaging the partition.

US Pat. No. 10,600,600

ELECTROMECHANICAL POWER SWITCH INTEGRATED CIRCUITS AND DEVICES AND METHODS THEREOF

INOSO, LLC, Austin, TX (...

13. A semiconductor device comprising:a semiconductor substrate including at least one integrated circuit device on a front surface of the semiconductor substrate;
an insulating layer on the front surface including over the at least one integrated circuit device;
an electromechanical power switch on the insulating layer, wherein the electromechanical power switch includes a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer; and
a 3D multi-layer decoupling capacitor, the 3D multi-layer decoupling capacitor comprising:
a trench portion;
a first metal region on the insulating layer and adjacent to a first side of the trench portion;
a second metal region on the insulating layer and adjacent to a second side of the trench portion opposite the first side of the trench portion;
a pair of interdigitated metal electrodes disposed within the trench portion, wherein a first electrode of the pair of interdigitated metal electrodes contacts the first metal region, and wherein a second electrode of the pair of interdigitated metal electrodes contacts the second metal region;
and
a plurality of dielectric layers disposed within the trench portion and between neighboring electrodes of the pair of interdigitated metal electrodes.

US Pat. No. 10,600,599

RELAY

OMRON CORPORATION, Kyoto...

1. A relay comprising:a movable contact terminal;
a contact piece that is attached to the movable contact terminal, and includes a first divided piece and a second divided piece extending in a lengthwise direction and divided from each other;
a first movable contact attached to the first divided piece;
a second movable contact attached to the second divided piece;
a fixed contact terminal disposed at a position facing the contact piece;
a first fixed contact attached to the fixed contact terminal and disposed at a position facing the first movable contact;
a second fixed contact attached to the fixed contact terminal and disposed at a position facing the second movable contact; and
a link member capable of pressing the contact piece, wherein
at a time of contact between the contacts, the first movable contact comes into contact with the first fixed contact before the second movable contact comes into contact with the second fixed contact,
the first movable contact is located on a leading end side of the contact piece with respect to the second movable contact,
the first divided piece includes
a body that extends in the lengthwise direction, and
a projection that projects in a widthwise direction of the first divided piece from the body, and
the projection includes a contact portion pressed by the link member.

US Pat. No. 10,600,598

RELAY

ELESTA GMBH, OSTFILDERN (...

1. A relay, comprising:an electromagnetic drive having a field coil arranged around an iron core that defines a plane, and a yoke;
a movable armature operably connected to the electromagnetic drive, the movable armature held by an armature retainer that is attached to the yoke, the armature retainer having a spring that pretensions the moveable armature against an end face of the yoke;
a movable electrical contact operably connected to the armature; and
a housing having a stationary partition arranged between the electromagnetic drive and the contact, wherein the electromagnetic drive is arranged on one side of the partition, and the movable electrical contact is arranged on the other side of the partition, and the partition wall has an opening through which mechanical actuation of the contact occurs;
the movable armature pivotable about an axis of rotation perpendicular to the plane of the iron core, and having an actuating arm that passes through the opening in the partition and cooperates with an actuating member to actuate the movable electrical contact.

US Pat. No. 10,600,597

MINIATURE SAFETY SWITCH

1. A miniature safety switch for use in motor vehicle electronics, the miniature safety switch comprising:a housing having a housing base made of an insulating material and a housing cover that can be fitted, or is fitted, on said housing base, said housing base having a base side;
first and second elongate and flat contact arms embedded parallel to one another in terms of a longitudinal direction thereof in said housing base and protrude out at said base side from said housing base;
a fixed contact disposed in said housing and attached to said first contact arm;
a bimetallic snap disk having a moving contact and attached to said second contact arm;
a compression spring being supported on said first contact arm beneath said fixed contact in the longitudinal direction;
a positive temperature coefficient (PTC) resistor being electrically incorporated in such a way that, as a result of heat generated by said PTC resistor, said bimetallic snap disk remains in an open position thereof in an event of triggering, said PTC resistor being brought into direct contact with said bimetallic snap disk by means of said compression spring; and
said compression spring being a conical spring having a base-side spring end contacting said first contact arm and an apex-side spring end contacting said PTC resistor.

US Pat. No. 10,600,596

ADAPTER TO ATTACH IMPLEMENTS TO AN ACTIVELY CONTROLLED HUMAN TREMOR CANCELLATION PLATFORM

Verily Life Sciences LLC,...

1. An adapter for coupling an implement to a tremor cancellation platform, the adapter comprising:a first section attached to the tremor cancellation platform, the first section comprising an elongated tapered key having a base and a tip, the base having a first transverse dimension that is greater than a second transverse dimension at the tip and the base being attached to the tremor cancellation platform;
a second section coupled to the implement, the second section including a tapered cavity sized and shaped to receive the first section, wherein the first section has an outer surface that smoothly transitions from the first transverse dimension at the base to the second transverse dimension at the tip over an entire length of the outer surface that mates with an inner surface of the tapered cavity, wherein the first section includes a cross-sectional shape having a flat portion and a curved portion wherein the cross-sectional shape of the elongated tapered key is non-symmetric about at least one axis to prevent the implement from being attached to the tremor cancellation platform in a wrong orientation; and
a latch to lock the second section onto the first section,
wherein the elongated tapered key of the first section includes:
a first slot at the tip in the flat portion that mates with a corresponding element in the tapered cavity; and
a second slot, notch, or detent at the base in the curved portion to engage the latch when the elongated tapered key is inserted into the tapered cavity, wherein the curved portion of the cross-sectional shape extends along the elongated tapered key.

US Pat. No. 10,600,595

PRESSURE SWITCH SYSTEM

HYDRA-ELECTRIC COMPANY, ...

1. A pressure switch comprising:a spring blade;
a ram pin having an angled bottom surface, wherein movement of the ram pin in a first direction engages the spring blade such that the spring blade snap deflects to an engaged position, and wherein movement of the ram pin in a second direction engages the spring blade such that the spring blade snap deflects to an unengaged position;
an adjustment screw, wherein an inward movement of the adjustment screw relative to an outside surface of the pressure switch causes movement of the ram pin in the first direction, and wherein an outward movement of the adjustment screw relative to the outside surface of the pressure switch causes a movement of the ram pin in the second direction; and
an amplifier disposed between the ram pin and the spring blade, wherein movement of the ram pin in the first direction is amplified by the amplifier to the spring blade, and wherein movement of the ram pin in the second direction is amplified by the amplifier to the spring blade.

US Pat. No. 10,600,594

GAS-INSULATED VACUUM LOAD BREAK SWITCH

ABB Schweiz AG, Baden (C...

1. A gas-insulated vacuum load break switch, comprising:a conductive line, a control operating mechanism, a support box and a transmission apparatus, wherein
the conductive line has three phases, the three phases of the conductive line being of a same structure and independent from each other;
each phase of the conductive line comprises a load break switch unit with a vacuum interrupter, an isolating switch unit with an isolator, a plastic housing supporting the load break switch unit and the isolating switch unit, and an earthing switch unit;
the control operating mechanism comprises a load break switch operating mechanism for controlling the load break switch unit, an operating rod for controlling the isolating switch unit, and an earthing switch operating mechanism for controlling the earthing switch unit; and
the transmission apparatus comprises a load break switch transmission apparatus for the load break switch unit, an isolating switch transmission apparatus for the isolating switch unit, and an earthing switch transmission apparatus for the earthing switch unit.

US Pat. No. 10,600,593

VACUUM SWITCHING DEVICES

1. An alternating current vacuum switching device for switching an electrical circuit under load and no load conditions, and optionally short-circuit conditions, the switching device comprising:a vacuum evacuated housing;
first and second electrodes within the vacuum evacuated housing; and
an actuator for moving the first electrode relative to the second electrode to mechanically engage and disengage the electrodes to perform a switching function, wherein the first electrode is wholly located within the vacuum evacuated housing and at least a portion of the actuator is located within the vacuum evacuated housing, without the use of vacuum bellows, such that movement of the first contact relative to the second electrode consummate with a switching function occurs solely within the vacuum evacuated housing; wherein,
the actuator comprises a magnetic actuator including a E-shaped core portion disposed at least partially within the vacuum evacuated housing.

US Pat. No. 10,600,592

SINGLE BOTTLE INTERRUPTER

Hubbell Incorporated, Sh...

1. A vacuum interrupter for interrupting a voltage, the vacuum interrupter comprising:a vacuum bottle having a single pair of axially separable contacts, wherein at least one of the separable contacts is a moveable contact;
a jacket encasing the vacuum bottle, wherein the jacket has a ribbed outer surface;
a housing, having an inner surface and a circumferentially ribbed outer surface, wherein the housing encases the jacket such that the inner surface of the housing interfaces with the ribbed outer surface of the jacket;
a bi-stable mechanism including,
an actuator, and
a cam pivotable by the actuator, the cam moving the moveable contact; and
a bellows assembly positioned above the vacuum bottle and coupled to the housing, the bellows assembly including an outer cylindrical shell surrounding an opening spring, a spring plate, a contact spring, and a bellows, the bellows assembly reciprocating the moveable contact to prevent arcing between the pair of contacts and biasing the pair of contacts apart from each other.

US Pat. No. 10,600,591

LUMINOUS KEYBOARD HAVING TRANSLUCENT LIGHT DIFFUSING RUBBER DOMES

PRIMAX ELECTRONICS LTD., ...

1. A luminous keyboard, comprising:a plurality of keys, each of the keys comprising:
a key cap;
a scissors foot mechanism, located below the key cap and pivotally connected to the key cap; and
a rubber dome, disposed below the key cap and pushing the key cap upward, wherein the rubber dome is made of a translucent material doped with a plurality of light-diffusion particles, and when the rubber dome is irradiated by a light ray, a part of the light ray passes through the rubber dome, and the other part of the light ray is reflected by the rubber dome;
a thin-film circuit board, disposed below the rubber dome, wherein the rubber dome can receive an external force from the key cap to be deformed downward to trigger the thin-film circuit board to generate an input signal;
a support plate, located below the thin-film circuit board, wherein the scissors foot mechanism passes through the thin-film circuit board to be pivotally connected to the support plate, and the support plate comprises a plurality of light-transmission through holes;
a light guide plate, located below the support plate, wherein the light guide plate comprises an upper surface and a plurality of light-diffusion protrusions formed on the upper surface;
a reflector, located below the light guide plate; and
a circuit board assembly, located below the reflector, wherein the circuit board assembly comprises a printed circuit board and a plurality of light sources electrically connected to the printed circuit board, and each of the keys corresponds to at least one of the light source, so that each of the keys receives the light ray emitted from the light source, wherein
after the light ray sequentially passes through the light guide plate, the support plate, and the thin-film circuit board, the part of the light ray passes through the rubber dome and then, is emitted outward through the key cap, and the other part of the light ray is reflected for a first time as being reflected downward by the rubber dome, then is reflected for a second time as being reflected outward by the reflector, is diffused by the light-diffusion protrusions of the light guide plate, and finally, is emitted outward through the key cap.

US Pat. No. 10,600,590

DEVICE, IN PARTICULAR A KEYBOARD, FOR DATA OR COMMAND ENTRY

QUBICAAMF EUROPE S.P.A., ...

1. An entertainment unit comprising a pedestal comprising a vertical column, a foot resting on a flooring and an integral keyboard support portion at an end of the vertical column opposite to the foot, the pedestal further having a keyboard mounted to the integral keyboard support portion at an obtuse angle relative to the vertical column of the pedestal such that the keyboard is inclined, and a backlighting system controlled by an entertainment system which comprises at least a centrally located system remote from the keyboard, the backlighting system comprises LED lights mounted on a backside of the keyboard and facing downward, and the pedestal and the keyboard are oriented and structured such that the LED lights light the flooring around the pedestal including at least the vertical column and behind the pedestal in a bowling centre including the foot.

US Pat. No. 10,600,589

KEYBOARD HAVING A SWITCH DEVICE

LENOVO (SINGAPORE) PTE LT...

1. A switch device comprising:a base plate;
a push button movable orthogonal to an upper surface side of said base plate when said push button is depressed;
a pair of stabilizer members supported between said push button and said base plate, wherein each of said pair of stabilizer members includes
a first shaft portion rotatably supported on a lower surface side of said push button; and
a second shaft portion, which has a rotation axis parallel to a rotation axis of said first shaft portion, rotatably supported by a bearing provided on said upper surface side of said base plate; and
a multi-layered membrane sheet located on an upper surface of said base plate, wherein said membrane sheet includes a first sheet in contact with said base plate, a second sheet in contact with said second shaft portion, and a third sheet in contact with said first and second sheets, wherein only said first sheet is provided with a cut-out shaped portion in an area corresponding to an area within which said second shaft portion is allowed to move.

US Pat. No. 10,600,588

SWITCH HAVING AN ARC-QUENCHING DEVICE

Siemens Aktiengesellschaf...

1. A switching device for application in a vacuum switching tube or for arc quenching in gases, the switching device comprising:a contact system having a moveable contact electrically conductively connected to a first electrical contact and a fixed contact electrically conductively connected to a second electrical contact;
an arc-quenching device having:
an arrangement for generating a magnetic field which is constituted in a perpendicular plane to a direction of motion of said moveable contact, wherein said arrangement for generating the magnetic field including a U-shaped core having a base arranged between said fixed contact and an electrical connecting lead of said fixed contact which constitutes a first current loop, wherein said connecting lead connects said fixed contact to said second electrical contact in an electrically conductive manner, and said U-shaped core having two limbs that extend along said contact system, around said contact system;
two or more arc-quenching electrodes laterally offset from said contact system such that a movement of said moveable contact of said contact system is not restricted by said two or more arc-quenching electrodes;
said two or more arc-quenching electrodes, when said contact system is in an open state, being laterally offset between said moveable contact and said fixed contact;
said two or more arc-quenching electrodes being arranged perpendicularly to the direction of motion of said moveable contact; and
said two or more arc-quenching electrodes being arranged on an open side of said U-shaped core of said arrangement for generating the magnetic field, such that a Lorentz force can act on moving electrons in a plasma of an arc in the magnetic field of said arrangement for generating the magnetic field;
an electrical counter-pulse device having at least one first capacitor and/or having at least one transformer, wherein said electrical counter-pulse device:
is connected to said first electrical contact and to said second electrical contact; and
is connected to said two or more arc-quenching electrodes such that a first arc-quenching electrode of said two or more arc-quenching electrodes, in the open state of said contact system, is arranged in closer spatial proximity to said fixed contact than to said moveable contact, and such that said first capacitor and/or said at least one transformer, on a first side, is connected to said first arc-quenching electrode, wherein the first side assumes a polarity of said first electrical contact; and
is connected to said two or more arc-quenching electrodes, such that a second arc-quenching electrode of said two or more arc-quenching electrodes, in the open state of said contact system, is arranged in closer spatial proximity to said moveable contact than to said fixed contact, and such that said first capacitor and/or said at least one transformer (46?), on a second side, is connected to said second arc-quenching electrode, wherein the second side assumes a polarity of said second electrical contact.

US Pat. No. 10,600,587

ELECTRICAL SWITCHING APPARATUS AND TRANSFER ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. A transfer assembly for an electrical switching apparatus, said electrical switching apparatus comprising a first housing, a pair of separable contacts disposed internal with respect to said first housing, and an operating handle having an ON position and an OFF position, the ON position corresponding to said separable contacts being closed, the OFF position corresponding to said separable contacts being open, said transfer assembly comprising:a rotary handle;
a number of transfer components each structured to cooperate with said rotary handle, one of said transfer components being structured to engage said operating handle in order to allow said rotary handle to move said operating handle between the ON position and the OFF position; and
a support assembly comprising a second housing and a support member coupled to and disposed internal with respect to said second housing, said second housing being structured to be coupled to said first housing, said rotary handle being coupled to said second housing,
wherein each of said transfer components is coupled to said support member,
wherein said support member and said second housing are separate and distinct components,
wherein said one of said transfer components is a sliding member; and wherein said support assembly further comprises a number of coupling members extending through said support member and at least partially into said sliding member in order to couple said sliding member to said support member, and
wherein said support member comprises a first wall, a second wall disposed opposite and generally parallel to said first wall, and a third wall extending between and being disposed generally perpendicular to said first wall and said second wall; and wherein said coupling members extend through said third wall.

US Pat. No. 10,600,586

INTERLOCKING DEVICE FOR CIRCUIT BREAKER

ZHEJIANG CHINT ELECTRICS ...

1. An interlocking device for a circuit breaker, comprising a control assembly and an interlocking assembly which are connected with each other in a driving manner; the control assembly can be connected with a connecting rod assembly and a cam assembly of an energy storage operation mechanism of the circuit breaker in a latching manner, thereby controlling the energy storage operation mechanism to finish a switching-on/switching-off operation; the control assembly comprises a switching-off half-shaft, a switching-off latch, a switching-on half-shaft and a switching-on latch; the interlocking assembly comprises a switching-on guide rod, a switching-off guide rod and a driving guide rod;the control assembly further comprises a switching-on button; the switching-on latch can be connected with the cam assembly in a latching manner, the driving guide rod is connected with the switching-on button in a driving manner; in the switching-on operation, one end part of the switching-on guide rod can be arranged between the driving guide rod and the switching-on half-shaft, and after the switching-on button is pushed, the switching-on guide rod drives the switching-on latch to be tripped from the cam assembly;
the control assembly further comprises a switching-off button; one end of the switching-off latch is connected with the switching-off half-shaft in a latching manner, and the other end of the switching-off latch is connected with the connecting rod assembly in a latching and limiting manner; in the switching-off operation, after the switching-off button is pushed, the switching-off guide rod drives the switching-off half-shaft to rotate and to trip the switching-off half-shaft from the switching-off latch, and to trip the switching-off latch from the connecting rod assembly;
one end of the switching-on half-shaft is connected with the switching-on latch in a driving manner, and the other end of the switching-on half-shaft and the driving guide rod face each other;
the interlocking assembly further comprises an interlocking guide rod and an energy storage indicator; the energy storage operation mechanism of the circuit breaker comprises a rotating shaft assembly for driving the switching-on/switching-off operation; a middle part of the interlocking guide rod is rotatably mounted on the energy storage operation mechanism; one end of the interlocking guide rod is a limiting portion which corresponds to the rotating shaft assembly and the energy storage indicator, and another end of the interlocking guide rod is a driving portion which is in contact and connection with the switching-on guide rod; the rotating shaft assembly and the energy storage indicator can be in contact and matched with the limiting portion of the interlocking guide rod, such that the interlocking guide rod acts on the switching-on guide rod; when the energy storage operation mechanism is in a switching-off energy storage state, the driving portion of the interlocking guide rod does not limit a switching-on interlocking portion of the switching-on guide rod the energy storage operation mechanism further comprises a driving shaft for mounting the connecting rod assembly and the cam assembly, wherein the rotating shaft assembly and the interlocking assembly are mounted at two sides of the driving shaft respectively.

US Pat. No. 10,600,585

GEAR UNIT HOUSING COVER INTERCONNECT WITHIN A CIRCUIT BREAKER

Siemens Aktiengesellschaf...

1. A gear unit housing for a gear unit having a two-sided control lever for moving two switch contacts of a circuit breaker in mutually opposite directions, the gear unit housing comprising:a housing cassette having a housing base;
a cover plate lying opposite to said housing base;
screw connections detachably interconnecting said cover plate and said housing cassette;
a bearing shaft connected to said housing cassette and to said cover plate, said bearing shaft extending between said housing base and said cover plate for mounting the control lever rotatably about said bearing shaft; and
at least one stud element form-lockingly interconnecting said housing cassette and said cover plate.

US Pat. No. 10,600,584

TRIGGER ACTIVATED TOOLS HAVING ACTIVATION LOCKOUTS

Hubbel Incorporated, She...

1. A trigger activated tool, comprising:an activatable device;
an activation trigger depending from a handle portion for movement about a first axis between a first position and a second position, the activation trigger being configured to activate the activateable device in the second position;
a lockout depending from the activation trigger for movement about a second axis between a locked state and an unlocked state, the locked state preventing activation of the activatable device by the activation trigger; and
a drain trigger depending from the handle portion for movement about the first axis, the drain trigger being configured to relieve potential energy within the activatable device when the lockout is in both the locked and unlocked states, the drain trigger being configured to relieve potential energy within the activatable device when the activation trigger is in the first position, but not the second position, wherein the first and second axes are offset from one another.

US Pat. No. 10,600,583

METHOD OF MAKING A POROUS NITROGEN-DOPED CARBON ELECTRODE FROM BIOMASS

King Saud University, Ri...

1. A method of making a porous nitrogen-doped carbon electrode from date palm (Phoenix dactylifera L.) pollen grains, comprising the steps of:stirring a volume of date palm (Phoenix dactylifera L.) pollen grains into an aqueous solution of potassium hydroxide (KOH) for one hour to produce a precursor carbon solution;
drying the precursor carbon solution for a period of six hours at a temperature of 80° C. to produce precursor carbon;
heating the precursor carbon at a temperature of 800° C. for two hours under an argon atmosphere to produce porous nitrogen-doped graphite carbon;
washing the porous nitrogen-doped graphite carbon in an aqueous solution of HCl, deionized water, and ethanol;
drying the porous nitrogen-doped graphite carbon for 24 hours at a temperature of 80° C.;
mixing the porous nitrogen-doped graphite carbon with a polyvinylidene difluoride (PVDF) binder and carbon black in an isopropanol solvent to form a slurry; and
coating nickel foam with the slurry to form a porous nitrogen-doped carbon electrode and dried at a temperature of 100° C., wherein the dried nitrogen-doped carbon electrode has a porous, cage-type structure wherein the pore volume is at least 0.8 cm3/g, having a Brunauer-Emmett-Teller (BET) surface area within about 86-87 m2/g, a wall thickness of at least about 30.8-80.0 nm and a mean pore diameter in the range of about 50 to about 450 nm.

US Pat. No. 10,600,582

COMPOSITE ELECTRODE

FASTCAP SYSTEMS CORPORATI...

1. An energy storage apparatus comprising:an active layer comprising:
a network of carbon nanotubes defining void spaces; and
a carbonaceous material located in the void spaces and bound by the network of carbon nanotubes; and
an adhesion layer disposed between the active layer and an electrically conductive layer, wherein the adhesion layer comprises at least ninety percent single wall carbon nanotubes (SWNT) by weight;
wherein the active layer is configured to provide energy storage;
wherein the active layer is substantially free from binding agents and consists essentially of carbonaceous material;
wherein the active layer is bound together and to the adhesion layer by forces between the carbon nanotubes and the carbonaceous material;
wherein the network of carbon nanotubes makes up less than ten percent by weight of the active layer;
wherein the network of carbon nanotubes comprises an electrically interconnected network of carbon nanotubes exhibiting connectivity above a percolation threshold
wherein the interconnected network of carbon nanotubes comprises one or more highly conductive pathways, the pathways comprising a length greater than 100 ?m;
wherein the interconnected network of carbon nanotubes includes one or more structures formed of the carbon nanotubes, the structure comprising an overall length at least ten times the average length of component carbon nanotubes making up the structure.

US Pat. No. 10,600,581

ELECTRIC DOUBLE LAYER CAPACITANCE DEVICE

BASF SE, Ludwigshafen (D...

1. An electrode comprising a binder and activated carbon, wherein the activated carbon comprises:a surface area of greater than 1500 m2/g, as determined by nitrogen sorption at 77 K and BET analysis; and
a pore structure comprising mesopores having a diameter ranging from 2.0 nm to 10.0 nm and a pore volume ranging from 0.01 cc/g to 0.25 cc/g for pores having a pore diameter of 0.6 nm to 1.0 nm, as determined from N2 sorption derived DFT,
wherein the electrode has a specific capacitance of at least 100 F/g and a specific power of at least 25 W/g when each of the specific capacitance and specific power is measured in an electric double layer capacitor device comprising an electrolyte comprising equal volumes of propylene carbonate and dimethylcarbonate and further comprising 1.0 M tetraethylammonium tetrafluoroborate.

US Pat. No. 10,600,580

EXPLOSION-PROOF APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. An explosion-proof apparatus comprising:a stopper having a hollow cylindrical shape that is open at a first side and closed at a second side opposite to the first side, the stopper being configured to be combined with an electrolytic condenser by surrounding a top side of the electrolytic condenser and a lateral side of the electrolytic condenser connected to the top side, through the first side of the stopper; and
a holder provided on the stopper and configured to support the stopper to be combined to the electrolytic condenser,
wherein the first side of the stopper is spaced apart from the top side of the electrolytic condenser.

US Pat. No. 10,600,579

ELECTROLYTIC CAPACITOR INCLUDING HYDROXY COMPOUND AND MANUFACTURING METHOD THEREFOR

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising:an anode body including a dielectric layer; and
a solid electrolyte layer covering at least a part of the dielectric layer, wherein:
the solid electrolyte layer includes:
a first conductive polymer layer covering at least a part of the dielectric layer and including a first conductive polymer; and
a second conductive polymer layer covering at least a part of the first conductive polymer layer and including a second conductive polymer,
the second conductive polymer layer is a layer in which the second conductive polymer, a polymer dopant, and a hydroxy compound are mixed,
the hydroxy compound has two or more alcoholic hydroxy groups or two or more phenolic hydroxy groups, the hydroxy compound having a melting point ranging from 40° C. to 150° C., inclusive,
the first conductive polymer layer further includes the hydroxy compound, and
a concentration of the hydroxy compound included in the second conductive polymer layer is higher than a concentration of the hydroxy compound included in the first conductive polymer layer.