US Pat. No. 10,560,118

MULTIPLE LOW DENSITY PARITY CHECK (LDPC) BASE GRAPH DESIGN

Qualcomm Incorporated, S...

1. A method of low density parity check (LDPC) decoding, the method comprising:maintaining a plurality of LDPC base graphs, the plurality of LDPC base graphs comprising at least a first LDPC base graph associated with a first information block length range and a second LDPC base graph associated with a second information block length range, wherein the second information block length range comprises a subset of the first information block length range;
receiving a codeword over a wireless air interface from a transmitter;
selecting a select LDPC base graph from the plurality of LDPC base graphs for decoding the codeword based, at least in part, on an information block length associated with the codeword; and
decoding the codeword utilizing the select LDPC base graph to produce an information block comprising the information block length.

US Pat. No. 10,560,115

FLOATING POINT TO FIXED POINT CONVERSATION USING EXPONENT OFFSET

Imagination Technologies ...

1. A binary logic circuit for converting a number in floating point format having an exponent E of ew bits, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits, the binary logic circuit comprising:an offset hardware circuit configured to offset the exponent of the floating point number by an offset value equal to (iw?1?sy) to generate a shift value svof sw bits given by sv=(B?E)+(iw?1?sy), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format;
a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the right-shifter being configured to right-shift the significand input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2ew?1?1, iw?1?sy)+min(2ew?1?2, fw)]?k?sw, where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number.

US Pat. No. 10,560,111

NESTED CASCADED MIXED-RADIX DIGITAL DELTA-SIGMA MODULATOR

University College Cork-N...

1. A fractional-N frequency synthesizer comprising:a divider controller having a main nth order modulator and an auxiliary nth order modulator, wherein a noise shaping of the auxiliary nth order modulator is the same order as a noise shaping of the main nth order modulator, and wherein n is an integer value greater than one and the divider controller comprises a plurality of error feedback modulator stages connected in a two-level nested cascaded multi-stage noise shaping (MASH) digital delta-sigma modulator (DDSM) with a single error cancellation network.

US Pat. No. 10,560,107

POWER SUPPLY POWER MANAGEMENT

Apple Inc., Cupertino, C...

1. A method of operating power management circuitry, the method comprising:providing a clock signal having a first frequency to a load circuit;
providing a load current into a load, the load comprising the load circuit;
detecting whether the load current exceeds a high current limit for a first duration;
in response to the load current exceeding the high current limit for the first duration, reducing the frequency of the clock signal to a second frequency, otherwise not reducing the frequency of the clock signal;
detecting whether an average of the load current exceeds an average current limit;
in response to the average load current exceeding the average current limit, reducing the frequency of the clock signal to the second frequency, otherwise not reducing the frequency of the clock signal;
while the frequency of the clock signal is the second frequency, detecting whether an output voltage provided to the load is below a first voltage threshold; and
in response to the output voltage being below the first voltage threshold, further reducing the frequency of the clock signal to a third frequency, otherwise not further reducing the frequency of the clock signal.

US Pat. No. 10,560,105

DELAY-LOCKED LOOP WITH LARGE TUNING RANGE

QUALCOMM Incorporated, S...

1. A delay-locked loop, comprising:a first delay line;
a second delay line;
a controller configured to select between the first delay line and the second delay line based upon a phase difference between a clock signal and a data signal, wherein the controller is further configured to select for the first delay line to delay the clock signal to form a delay-locked loop output clock signal responsive to the phase difference corresponding to a delay within a delay operating range for the first delay line and to select for the second delay line to delay the clock signal to form the delay-locked loop output clock signal responsive to the phase difference corresponding to a delay within a delay operating range for the second delay line;
a clock data recovery circuit configured to produce a control signal responsive to the phase difference between the clock signal and the data signal and to control a delay for the selected delay line responsive to the control signal; and
a demultiplexer configured to receive the control signal, wherein the controller is further configured to control the demultiplexer to demultiplex the control signal to the first delay line responsive to the selection of the first delay line by the controller and to demultiplex the control signal to the second delay line responsive to the selection of the second delay line by the controller.

US Pat. No. 10,560,103

FLUX-TUNABLE QUBIT DEVICE WITH MULTIPLE JOSEPHSON JUNCTIONS

1. A qubit device comprising:an inductor connected between a first circuit node and a second circuit node;
a first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and
a second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node,
wherein the qubit device is configured to receive, during operation of the qubit device, a magnetic flux that controls a qubit frequency of the qubit device, and the qubit frequency as a function of the magnetic flux comprises multiple flux sweet spots.

US Pat. No. 10,560,101

COUNT VALUE GENERATION CIRCUIT, PHYSICAL QUANTITY SENSOR MODULE, AND STRUCTURE MONITORING DEVICE

Seiko Epson Corporation, ...

1. A count value generation circuit comprising:a first counter that counts edges of a reference signal in synchronization with an input signal to generate a first count value;
a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal;
a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value; and
a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.

US Pat. No. 10,560,093

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first mode register configured to store a first selection termination control signal and a second selection termination control signal when a mode register write operation is performed;
a first termination circuit comprising an impedance value and configured to control the impedance value of the first termination circuit based on the first selection termination control signal and a termination control signal; and
a second termination circuit comprising an impedance value and configured to control the impedance value of the second termination circuit based on the second selection termination control signal and the termination control signal,
wherein the impedance values of the first and second termination circuits are controlled to be substantially equal to each other according to a logic level combination of the termination control signal.

US Pat. No. 10,560,087

PASSIVE LEAKAGE MANAGEMENT CIRCUIT FOR A SWITCH LEAKAGE CURRENT

GE Aviation Systems Limit...

1. A passive leakage management circuit for a switch leakage current comprising:a switch that includes an input electrically coupled with a source of alternating current (AC) and an output electrically coupled with an electrical load, and is operable in a first operating mode, wherein the output supplies an AC output current provided to the input and having a first AC voltage, and in a second operating mode, wherein the output supplies an AC leakage current from the input and having a second AC voltage lower than the first AC voltage;
a rectifying module electrically coupled with the switch output and that rectifies the AC output current to a direct current (DC) output current during the first operating mode and the second operating mode;
a first current path that receives the DC output current and includes a first transistor that conducts current along the first current path based on the switch output; and
a leakage current path that receives the DC output current and includes a second transistor that conducts current along the leakage current path based on the first transistor not conducting current;
wherein at least one of the first current path or leakage current path conducts current based on the switch output, without an additional power source beyond the switch output, and independent of the first or second operating mode of the switch, and wherein only one of the first current path or leakage current path conducts current when the switch is coupled with the source of alternating current.

US Pat. No. 10,560,084

LEVEL SHIFT CIRCUIT

Toshiba Memory Corporatio...

1. A level shift circuit comprising:a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;
a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain;
a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain;
a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain;
a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;
a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and
a potential adjusting circuit that is electrically connected to at least the second node, and
wherein the potential adjusting circuit is a charging circuit electrically connected to the second node,
the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node,
the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period.

US Pat. No. 10,560,083

CONTROL DEVICE FOR POWER SUPPLY LINE

1. A control device to be arranged between two portions of an electrical power supply line, the device comprising:a bipolar transistor comprising a wide bandgap semiconductor material and having its emitter connected to one portion of the power supply line, its collector connected to another portion of the power supply line; and
a control circuit connected to the base of said transistor and configured to operate in an open loop without feedback.

US Pat. No. 10,560,065

PIEZOELECTRIC RESONATOR MANUFACTURING METHOD AND PIEZOELECTRIC RESONATOR

MURATA MANUFACTURING CO.,...

1. A piezoelectric resonator comprising:a piezoelectric thin film;
a support substrate located at a back surface side of the piezoelectric thin film;
an adhesive layer located at a surface side of the support substrate that faces the back surface side of the piezoelectric thin film; and
a support layer that fixes the piezoelectric thin film to the support substrate so as to provide a space between the piezoelectric thin film and the support substrate; wherein
a corner portion of the support layer at a side of the support substrate, which is exposed to the space, includes a recess defined by a cut in the corner portion;
the support substrate includes an adhered portion at which the support layer and the support substrate are adhered to one another, and a non-adhered portion at which the support layer and the support substrate are not adhered to one another; and
a thickness of a portion of the adhesive layer located at the adhered portion is thinner than a thickness of another portion of the adhesive layer located at the non-adhered portion.

US Pat. No. 10,560,062

PROGRAMMABLE BIASING FOR PIN DIODE DRIVERS

MACOM Technology Solution...

1. A driver circuit comprising:a substrate on which the driver circuit is assembled;
a supply voltage contact configured to receive electrical power from a power source;
a boost converter connected to the supply voltage contact and configured to convert a first voltage received from the power source to a second voltage that is greater than the first voltage and to a third voltage that is less than the first voltage;
a low-dropout regulator configured to convert the second voltage to a fourth voltage; and
a programmable register configured to receive a digital signal and output a first control signal responsive to the received digital signal that alters at least the fourth voltage within a positive voltage range that is greater than zero volts.

US Pat. No. 10,560,059

POWER AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A power amplifier module comprising:an amplifier that amplifies an input signal and outputs an amplified signal from an output terminal;
a matching circuit disposed between the output terminal of the amplifier and a subsequent circuit;
a choke inductor, wherein a power supply voltage is applied to a first end of the choke inductor; and
a first attenuation circuit disposed between the output terminal of the amplifier and a second end of the choke inductor, the first attenuation circuit attenuating a second harmonic of the amplified signal, wherein:
the first attenuation circuit includes:
a first inductor, wherein a first end of the first inductor is connected to the output terminal of the amplifier and a second end of the first inductor is connected to the second end of the choke inductor, and
a first capacitor, wherein a first end of the first capacitor is connected to the second end of the first inductor and a second end of the first capacitor is grounded,
the matching circuit includes:
a second attenuation circuit that attenuates frequencies greater than a fundamental frequency of the amplified signal; and
a filter, and
the second attenuation circuit is a low pass filter,
the first attenuation circuit and the second attenuation circuit are not included as part of a chip of the amplifier.

US Pat. No. 10,560,058

METHOD OF EQUALIZING CURRENTS IN TRANSISTORS AND FLOATING CURRENT SOURCE

1. A current equalizing circuit comprising:a first supply voltage (VDD) and a second supply voltage (VSS);
a first P-channel Metal Oxide Silicon Field Effect Transistor (PMOSFET) having a first PMOSFET gate terminal coupled with a first node, a first PMOSFET source terminal coupled with VDD, and a first PMOSFET drain terminal coupled with a third node;
a second PMOSFET having a second PMOSFET gate terminal coupled with a fifth node, a second PMOSFET source terminal coupled with the third node, and a second PMOSFET drain terminal coupled with a fourth node;
a first N-channel Metal Oxide Silicon Field Effect Transistor (NMOSFET) having a first NMOSFET gate terminal coupled with a second node, a first NMOSFET source terminal coupled with VSS, and a first NMOSFET drain terminal coupled with the fourth node;
a second NMOSFET having a second NMOSFET gate terminal coupled with a sixth node, a second NMOSFET source terminal coupled with the fourth node, and a second NMOSFET drain terminal coupled with the third node;
a first regulating circuit comprising a first regulating circuit input port, and a first regulating circuit output port;
a second regulating circuit comprising a second regulating circuit input port, and a second regulating circuit output port;
wherein the first regulating circuit input port communicates with the third node, and wherein the first regulating circuit output port communicates with the first node and the fifth node; and
wherein the second regulating circuit input port communicates with the fourth node, and where in the second regulating circuit output port communicates with the second node and the sixth node.

US Pat. No. 10,560,042

TURBOCOMPRESSOR COMPRISING A COMPRESSOR MOTOR GENERATING REGENERATIVE ELECTRIC POWER BY REGENERATIVE DRIVING CAPABLE OF DRIVING A COMPRESSOR MOTOR

PANASONIC INTELLECTUAL PR...

1. A turbocompressor apparatus that is connectable to a power source, comprising:a turbocompressor including:
a rotary shaft;
a shaft bearing that supports the rotary shaft;
a compression mechanism that compresses and discharges a cooling medium by rotation of the rotary shaft;
a compressor motor that rotates the rotary shaft; and
a lubricant supply passage through which a lubricant is supplied to the shaft bearing,
a lubrication pump including a pump motor that generates driving force for supplying the lubricant to the shaft bearing through the lubricant supply passage;
a converter that performs electric power conversion between a voltage of the power source and a direct-current voltage of a direct-current voltage unit in a case where electric power is being supplied from the power source to the converter;
a first inverter that performs electric power conversion between the direct-current voltage and a first alternating-current voltage vector of the compressor motor; and
a second inverter that performs electric power conversion between the direct-current voltage and a second alternating-current voltage vector of the pump motor,
the compressor motor generating regenerative electric power by regenerative driving and the pump motor being driven by the regenerative electric power in a case where supply of electric power from the power source to the converter is being cut off,
wherein the turbocompressor apparatus performs a normal operation in which the pump motor is driven by using the voltage of the power source in a case where electric power is being supplied from the power source to the converter;
the turbocompressor apparatus performs a first decelerating operation in which an amplitude of the first alternating-current voltage vector is set equal to or smaller than a value that is R1 times the direct-current voltage in a case where supply of electric power from the power source to the converter is being cut off and where the amplitude of the first alternating-current voltage vector is equal to or larger than a first threshold amplitude; and
the first threshold amplitude is equal to or larger than an amplitude of the second alternating-current voltage vector in the normal operation, R1 is an upper limit value of a ratio of the amplitude of the first alternating-current voltage vector to the direct-current voltage obtained in a case where the first inverter operates in a linear region, and the linear region of the first inverter is an operation region in which the amplitude of the first alternating-current voltage vector linearly changes in theory relative to the direct-current voltage.

US Pat. No. 10,560,038

HIGH TEMPERATURE DOWNHOLE POWER GENERATING DEVICE

Saudi Arabian Oil Company...

1. A high temperature power generating device, the device comprising:a power generator including a first material of one polarity and a second material that is fixed in position relative to the first material and is of opposite polarity of the first material, wherein the first material is configured to be propelled toward the second material based on motion of the high temperature downhole power generator so that the two materials have a maximized point of contact to generate maximum power;
at least one electrode that is connected to the first material or second material;
a bridge rectifier connected to the at least one electrode to transform the power generated into direct current from alternating current;
a storage unit for storing the power generated by the power generator;
a first housing for housing the power generator, the electrode, and the bridge rectifier, wherein the first housing comprises a polymeric material; and
a second housing for housing the storage unit, wherein the second housing comprises a material selected from the group consisting of certain solids, transition metals, as well as high strength alloys and/or compounds of the transition metals, and high temperature dewars.

US Pat. No. 10,560,037

APPARATUS AND METHOD FOR CONTROL OF MULTI-INVERTER POWER CONVERTER

GE Global Sourcing LLC, ...

13. A control apparatus comprising:a support structure;
a control logic circuit attached to the support structure; and
a control output terminal attached to the support structure;
wherein the control logic circuit is configured to generate, for output through the control output terminal, control signals for controlling semiconductor switches of inverters that are coupled in parallel between a direct current bus and common load terminals connected with a common load;
wherein the control logic circuit is configured to determine, based on a fixed sample rate, a terminal current that is output by at least one of the inverters to at least one of the common load terminals; and
wherein the control logic circuit is configured to generate the control signals based at least in part on the terminal current and a reference current value, at least one of the control signals generated to adjusting timing at which a drive voltage is applied to at least one of the semiconductor switches.

US Pat. No. 10,560,031

BI-DIRECTIONAL DC TO DC SIGNAL CONVERSION USING OBSERVER BASED ESTIMATED CURRENT SENSOR

Hamilton Sundstrand Corpo...

1. A bi-directional DC to DC converter, comprising:a DC to DC conversion circuit; and
a controller operatively connected to the conversion circuit to control a voltage output of the conversion circuit, the controller including an observer based estimated current sensor module configured to simulate a physical current sensor by inputting an estimated output current feedback inner state signal ??o into a voltage output command feedback loop of the controller.

US Pat. No. 10,560,029

CONTROLLER FOR INCREASING EFFICIENCY OF A POWER CONVERTER AND A RELATED METHOD THEREOF

Leadtrend Technology Corp...

1. A controller for increasing efficiency of a power converter, the controller comprising:an enable signal generation unit electrically connected to a direct current (DC) input terminal of a primary side of the power converter through a high voltage pin of the controller, wherein the enable signal generation unit is used for generating an enable signal corresponding to a duty cycle of a gate control signal according to a DC input voltage of the DC input terminal and a feedback voltage corresponding to a secondary side of the power converter, and the feedback voltage corresponds to an output voltage of the secondary side of the power converter; and
a gate signal generation unit having two transistors in parallel, wherein a first terminal of a first transistor of the two transistors and a first terminal of a second transistor of the two transistors are coupled to ground, a second terminal of the first transistor is coupled to a gate pin of the controller through a switch comprised in the gate signal generation unit, a second terminal of the second transistor is directly coupled to the gate pin, and a control terminal of the first transistor and a control terminal of the second transistor receive a pulse width modulation signal;
wherein the gate signal generation unit utilizes the enable signal to control turning-on and turning-off of the switch to change a sink current flowing through the gate pin of the controller, wherein the gate pin is coupled to a power switch of the primary side of the power converter, and the gate signal generation unit is further used for generating a gate control signal to the power switch.

US Pat. No. 10,560,027

SEMICONDUCTOR DEVICE AND METHOD THEREFOR

FAIRCHILD SEMICONDUCTOR C...

1. A power supply circuit having a control circuit comprising:configuring a PWM circuit of the control circuit to control a power switch to regulate an output voltage formed from a secondary winding of a transformer wherein the secondary winding is configured to be coupled to a synchronous rectifier;
a feedback circuit configured to receive a sense signal from an auxiliary winding of the transformer, the feedback circuit configured to allow the sense signal to increase in response to a turn-off of the power switch, to subsequently detect a second increase of the sense signal that occurs in response to a turn-off of the synchronous rectifier, and to form a feedback signal as a value of the sense signal responsively to detecting the second increase of the sense signal; and
the control circuit configured to adjust an on-time of a subsequent enabling of the power switch according to a value of the feedback signal.

US Pat. No. 10,559,998

MOTOR AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A motor, comprising:a stationary unit including a stator, a base, and a flexible wiring substrate board;
a rotary unit including a rotor magnet; and
a bearing mechanism that supports the rotary unit so as to rotate with respect to the stationary unit about a center axis extending in an axial direction; wherein
the stator is positioned radially inward of the rotor magnet;
the base is positioned axially below the stator and the rotor magnet and includes a hole extending therethrough;
the hole is positioned in a region of the base, the region of the base has an axial height which varies at different locations within the region of the base;
the flexible wiring substrate board extends completely through the hole and supplies electric power to the stator;
the flexible wiring substrate board extends beneath both of the rotor magnet and the stator;
the stator includes at least one stator coil and the flexible wiring substrate board extends beneath a majority of an entire radial dimension of the at least one stator coil;
the flexible wiring substrate includes an electrically conductive solder portion on a lower surface thereof to cover a portion of a lead wire extending from a coil of the stator; and
at least a portion of the solder portion is positioned within an additional hole defined in the base.

US Pat. No. 10,559,995

MOTOR HAVING A COVER MEMBER FOR GUIDING WATER DROPLETS AWAY FROM ROTARY ENCODER

FANUC CORPORATION, Yaman...

1. A motor comprising:a motor main body having a rotating shaft member; and
a rotary encoder, wherein
the rotary encoder has a cover member, and
an inner surface of the cover member has a first top surface formed having an inclined portion that is inclined relative to a horizontal direction so as to guide a droplet of water when the rotating shaft member is disposed to extend in a vertical direction, and a second top surface formed having an inclined portion that is inclined relative to a horizontal direction so as to guide a droplet of water when the rotating shaft member is disposed to extend in a horizontal direction,
wherein a groove for guiding a droplet of water is formed in the first top surface and/or the second top surface, the groove being linear and extending in a predetermined direction when viewing the first top surface and the second top surface from inside the cover member, and
a hygroscopic material is disposed to be bonded to the first top surface and the second top surface at the boundary between the first top surface and the second top surface of the inner surface of the cover member, and absorbs the droplets of water guided by the first top surface and the second top surface.

US Pat. No. 10,559,986

SYSTEM, METHOD, AND APPARATUS FOR WIRELESS CHARGING

CAPITAL ONE SERVICES, LLC...

1. An electronic transaction card comprising:a Near-Field Communication (NFC) antenna;
an energy storage component; and
a processor configured to:
send and receive data packets to and from a terminal system to conduct a transaction using contactless payment technology, wherein the data packets include user authentication information to authenticate payment;
transmit, via the NFC antenna, an advertising packet from the electronic transaction card to a mobile power receiving device;
receive, via the NFC antenna, a response to the advertising packet from the mobile power receiving device, wherein the response indicates a first frequency of energy transmission via the NFC antenna;
alter the first frequency of energy transmission via the NFC antenna to a second frequency of energy transmission via the NFC antenna based on a distance between the electronic transaction card and the mobile power receiving device; and
broadcast, via the NFC antenna, a signal to the mobile power receiving device using the second frequency and configured to charge the mobile power receiving device via inductive charging.

US Pat. No. 10,559,985

WIRELESS POWER TRANSFER SYSTEM, CONTROL METHOD OF WIRELESS POWER TRANSFER SYSTEM, WIRELESS POWER TRANSMITTING APPARATUS, CONTROL METHOD OF WIRELESS POWER TRANSMITTING APPARATUS, AND STORAGE MEDIUM

CANON KABUSHIKI KAISHA, ...

1. A power transmitting apparatus comprising:a member configured to mount a power receiving apparatus;
a power transmitting unit configured to wirelessly transmit power to the power receiving apparatus mounted on the member;
a communication unit configured to communicate with the power receiving apparatus mounted on the member; and
a control unit configured to control the power transmitting unit and the communication unit,
wherein the communication unit transmits information to the power receiving apparatus mounted on the member, thereby the power receiving apparatus displays, based on the information transmitted by the communication unit, a charging message representing a charging speed.

US Pat. No. 10,559,984

POWER TRANSFER SYSTEM, AND POWER RECEIVING APPARATUS, POWER TRANSMITTING APPARATUS, AND CONTROL METHOD THEREOF

CANON KABUSHIKI KAISHA, ...

1. A power receiving apparatus comprising:a first antenna for wirelessly receiving power from a power transmitting apparatus and for performing communication;
a second antenna for performing communication;
one or more memories storing instructions; and
one or more processors executing the instructions to:
perform communication regarding identification information, with the power transmitting apparatus, via the first antenna;
transmit a first signal via the second antenna;
receive a second signal indicating a request for communication via the second antenna after transmitting the first signal;
determine whether a transmission source of the second signal is the power transmitting apparatus with which the identification information is communicated via the first antenna based on identification information included in the second signal;
control to perform communication regarding power receiving control via the second antenna, based on determining the transmission source of the second signal is the power transmitting apparatus with which the identification information is communicated via the first antenna, with the transmission source of the second signal, and control not to perform communication regarding power receiving control via the second antenna, based on determining the transmission source of the second signal is not the power transmitting apparatus with which the identification information is communicated via the first antenna, with the transmission source of the second signal.

US Pat. No. 10,559,981

POWER LINKS AND METHODS FOR IMPROVED EFFICIENCY

Daxsonics Ultrasound Inc....

1. A method of improving transfer efficiency in an ultrasonic power link having a send transducer and configured to transmit at a transmit frequency, in which the send transducer has a fixed resonant global best operating frequency characteristic to the send transducer, the method comprising detecting changes in impedance phase as seen by the send transducer by sweeping the transmit frequency over a range of frequencies, identifying a target frequency at which the impedance phase is at a local minimum that is closest in value to the global best operating frequency, and adjusting the transmit frequency to the target frequency.

US Pat. No. 10,559,964

MOBILE TERMINAL AND BATTERY CHARGING METHOD THEREFOR

LG ELECTRONICS INC., Seo...

1. A mobile terminal, comprising:a terminal body comprising a battery;
an adaptor connector formed at one side surface of the terminal body and to which a power supply adaptor is connected;
a plurality of charging units configured to charge the battery between the adaptor connector and the battery; and
a controller configured to generate a control signal for controlling each of the plurality of charging units,
wherein any one of the plurality of charging units is configured to:
detect a level of a voltage of the battery,
compare the voltage of the battery with first to third threshold voltages, and
output first battery voltage data to the controller when the voltage of the battery is lower than the first threshold voltage, output second battery voltage data to the controller when the voltage of the battery is equal to or larger than the first threshold voltage and is lower than the second threshold voltage, and output third battery voltage data to the controller when the voltage of the battery is equal to or larger than the second threshold voltage and is lower than the third threshold voltage.

US Pat. No. 10,559,947

PROTECTIVE SKIRT FOR TELECOMMUNICATIONS LINES

Corning Optical Communica...

1. A protective apparatus for telecommunication lines, comprising:a mounting frame, wherein the mounting frame comprises a sidewall having a sidewall opening;
a transition platform coupled to the mounting frame, the transition platform comprising an opening; and
a protective skirt, wherein the mounting frame, the transition platform and the protective skirt define an internal space when the protective skirt is removably coupled to the mounting frame, wherein the protective skirt comprises a cutout for allowing unobstructed access to the sidewall opening, wherein the opening of the transition platform comprises a non-enclosed shape having an open end, and wherein the open end is positional against an external wall when the mounting frame is secured to the external wall to facilitate trapping a telecommunications line between the opening and the external wall.

US Pat. No. 10,559,944

SPARK PLUG FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. A spark plug for an internal combustion engine comprising:a cylindrical housing;
a cylindrical insulator held inside the housing;
a center electrode held inside the insulator so that a tip end portion protrudes;
a ground electrode forming a spark discharge gap between the center electrode and the ground electrode; and
a conductive glass filled in the insulator so as to be located at a base end side of the center electrode, wherein
the center electrode has a locking portion locked from the base end side to a step portion formed on an inner peripheral surface of the insulator, and an electrode head closer to the base end side than the locking portion is;
the electrode head has a base end surface on which a concave portion is partially formed; and
the concave contour, which is an outer peripheral contour of the concave portion when viewed in a plug axis direction, forms a closed curve which is spaced apart from a head contour, which is an outer peripheral contour of the base end surface of the electrode head, and surrounds the center axis of the center electrode, and
the concave contour has outward portions each protruding toward the head contour and four inward portions each protruding toward the center axis of the center electrode, and wherein
the distance between the concave contour and the head contour is 0.1 mm or more; and
the four inward portions each has an inwardly curved shape protruding toward the center axis.

US Pat. No. 10,559,940

LASER POWER CONTROL SYSTEM FOR LASER DIODE USING DUAL CLOSE LOOPS

Rafael Microelectronics, ...

1. A laser power control system, comprising:a laser diode configured to convert an output current into a light signal;
a monitor photodiode configured to convert the light signal into a monitor current;
a bias control circuit coupled to the monitor photodiode, comprising:
a first current comparator comprising a negative input terminal coupled to the monitor photodiode and a positive input terminal coupled to a first target current, and configured to compare the monitor current with the first target current to generate a first comparison result;
a clamp diode comprising an anode coupled to an output terminal of the first current comparator and a cathode, and configured to clamp the first comparison result; and
a capacitor comprising one end coupled to the cathode of the clamp diode and another end coupled to a ground voltage, and configured to store the first comparison result; and
a digital controller coupled to the bias control circuit and the laser diode, and configured to adjust a bias current of the output current according to the first comparison result.

US Pat. No. 10,559,937

PULSED LIGHT GENERATION DEVICE, PULSED LIGHT GENERATION METHOD, EXPOSURE APPARATUS HAVING PULSED LIGHT GENERATION DEVICE AND INSPECTION APPARATUS HAVING PULSED LIGHT GENERATION DEVICE

NIKON CORPORATION, Tokyo...

1. A pulsed light generation device, comprising:a first optical fiber through which first pulsed light and second pulsed light, having an intensity that decreases while an intensity of the first pulsed light increases, and increases while the intensity of the first pulsed light decreases, having been multiplexed and entered therein, are propagated; and
a second optical fiber at which the first pulsed light, having exited the first optical fiber and entered therein, is amplified while being propagated therein, wherein:
at the first optical fiber, phase modulation occurs in the first pulsed light due to cross phase modulation caused by the second pulsed light; and
self-phase modulation occurring in the first pulsed light at the second optical fiber is diminished by the phase modulation having occurred at the first optical fiber.

US Pat. No. 10,559,934

MULTIFUNCTIONAL ROTARY DATA MEMORY

SHENZHEN DNS INDUSTRIES C...

1. A multifunctional rotary data memory, comprising a housing, a master control module, a memory, a first connector, and a second connector, wherein the housing comprises an upper housing having a first side wall between a first baseplate and a first cover and a lower housing having a second side wall between a second baseplate and a second cover, the upper housing and the lower housing are movably connected, and the upper housing and the lower housing can relatively and rotatably move around a pivot shaft; the first connector is mounted on the first side wall, the second connector is mounted on the second side wall, and the first connector and the second connector are both communicatively connected to the master control module; the first baseplate and the second baseplate are rotatably connected through the pivot shaft; a first through hole is arranged in a middle of the first baseplate, a second through hole is arranged in a middle of the second baseplate, and the second through hole is communicated with the first through hole for a conductor to pass through; the second baseplate is provided with a plurality of bulges standing and extending outwardly at a periphery of the second through hole, the plurality of bulges are arranged in circular and pass through the first through hole, so as to be served as the pivot shaft; and the first baseplate is provided with a shaft sleeve standing and extending inwardly at a periphery of the first through hole and corresponding to the plurality of bulges, and top portions of at least a part of the plurality of bulges are provided with reverse hooks so as to prevent the bulges from being separated from the first baseplate.

US Pat. No. 10,559,933

MANUAL DISCONNECT WITH CONNECTOR POSITION ASSURANCE ASSEMBLY

Lear Corporation, Southf...

1. A manual disconnect for an electric circuit comprising:a base including primary terminals and an interlock connector;
a plug assembly including fuse terminals and an interlock resistor assembly, the plug assembly adapted to be moved relative to the base between a disconnected position, wherein the fuse terminals are not engaged with respective primary terminals, a primary circuit engaged position, wherein the fuse terminals are engaged with respective primary terminals, and an interlock position, wherein the interlock connector is engaged with the interlock resistor assembly; and
a connector position assurance assembly including a connector position assurance button movable relative to the plug assembly between a pre-lock position and an assurance position, wherein the connector position assurance assembly prevents the plug assembly from rotating relative to the base;
wherein the plug assembly is adapted to be moved in an insertion direction relative to the base to move the plug assembly from the disconnected position to the primary circuit engaged position, and the plug assembly is adapted to be rotated about an axis relative to the base to move the plug assembly from the primary circuit engaged position to the interlock position.

US Pat. No. 10,559,911

PLUG CONNECTOR MODULE PROVIDING GROUND CONNECTION THROUGH A MODULE HOLDING FRAME

1. An electrical plug connector module and a frame assembly for insertion into a modular plug connector, wherein said frame assembly comprises a holding frame for accommodating two or more electrical plug connector modules, and having one or more electrical plug connector modules fixed in the holding frame, the electrical plug connector modules each comprising an insulating housing and at least one electrical contact, wherein the insulating housing comprises fixing devices for fixing the electrical plug connector module in the holding frame, and wherein the at least one electrical contact is received in the insulating housing and comprises a second plugging side and also a second connecting side that can be accessed from a first plugging side and a first connecting side of the insulating housing respectively, wherein the electrical plug connector module further comprises a contact means that is connected to the at least one electrical contact in an electrically conductive manner and is guided to an outer side of the insulating housing, wherein the contact means is embodied on the outer side of the insulating housing as an L-shaped resilient region having an S-shaped formation at a distal end of the L-shaped region, wherein the electrical plug connector module is inserted into the holding frame, wherein the holding frame is arranged in the modular plug connector, and the resilient region of the contact means contacts the holding frame.

US Pat. No. 10,559,895

CONNECTION ADAPTER FOR CONNECTING AN EARTHING LINE TO A METAL PROTECTIVE HOSE

Wieland Electric GmbH, B...

2. A connection adapter for connecting an earthing line to a metal protective hose, comprising:a line contact having at least one ring segment configured to rest on an outer sheath of the earthing line, wherein the line contact is crimped on the earthing line;
a hose contact having a contact tab configured to rest on an inner sheath of the metal protective hose; and
a flange-like disc forming an opening, comprising:
a disc face, the ring sleeve extending from the disc face;
a counter-face remote from the disc face; and
a contact tab that extends from the counter-face.

US Pat. No. 10,559,894

METHOD OF MANUFACTURING CONNECTION STRUCTURE, WIRE HARNESS, AND DEVICE FOR MANUFACTURING CONNECTION STRUCTURE

FURUKAWA ELECTRIC CO., LT...

1. A method of manufacturing a connection structure, comprising:separating a crimp terminal from a terminal connecting belt coupled to a carrier formed in a band shape;
inserting, after the separating, at least an electric wire tip portion of an insulated wire into a crimping portion of the crimp terminal separated from the terminal connecting belt; and
crimping, after the inserting, the crimping portion of the crimp terminal into which the electric wire tip portion has been inserted such that a crimping blade holds and crimps the crimping portion and that a crimp connection is formed on the insulated wire,
wherein the insulated wire comprises a conductor and an insulating covering that covers the conductor such that the insulated wire has the electric wire tip portion on a tip side of the insulated wire, the carrier has a band shape, the crimp terminal is one of a plurality of crimp terminals connected to the carrier through the terminal connecting belt such that the plurality of crimp terminals is connected to the carrier along a latitudinal direction of the carrier at predetermined intervals in a longitudinal direction of the carrier, each of the crimp terminals has a closed-barrel shape, and the separating of the crimp terminal comprises separating the crimp terminal from the terminal connecting belt by a separating blade while the crimping blade pinches the crimping portion of the crimp terminal, and
wherein the method further comprises:
stripping, before the separating, the insulating covering from the tip side of the insulated wire such that the electric wire tip portion is formed;
applying, after the stripping and before the separating, a mark on the insulating covering at a predetermined position based on a length of the electric wire tip portion inserted into the crimping portion; and
testing, after the stripping, the applying, the separating, the inserting, and the crimping, a state of the crimping of the electric wire tip portion to the crimping portion using the mark.

US Pat. No. 10,559,889

SLOT ARRAY ANTENNA, AND RADAR, RADAR SYSTEM, AND WIRELESS COMMUNICATION SYSTEM INCLUDING THE SLOT ARRAY ANTENNA

NIDEC CORPORATION, Kyoto...

1. A slot array antenna comprising:a first electrically conductive member including a first electrically conductive surface and a plurality of slots therein, the plurality of slots being arrayed in a first direction which extends along the first electrically conductive surface and in a second direction which intersects the first direction;
a second electrically conductive member including a second electrically conductive surface which opposes the first electrically conductive surface;
a plurality of ridge-shaped waveguide members arrayed between the first and second electrically conductive members along the second direction, each of the plurality of waveguide members including an electrically conductive waveguide face which extends along the first direction so as to oppose at least two slots among the plurality of slots; and
an artificial magnetic conductor in a subregion which is within a region between the first and second electrically conductive members, but which is outside of a subregion including the plurality of waveguide members; wherein
the second electrically conductive member includes a plurality of through holes;
at least one of the plurality of waveguide members is split by one of the plurality of through holes into a first ridge and a second ridge, each of the first and second ridges including an end face, the end faces opposing each other;
the one of the plurality of through holes includes an inner peripheral surface connected to the end faces of the first and second ridges;
each of a length of the first ridge and a length of the second ridge is greater than a distance between the first and second electrically conductive surfaces;
the artificial magnetic conductor includes a plurality of electrically conductive rods arrayed on the second electrically conductive member;
no electric wall exists in a space between two adjacent waveguide faces of two adjacent waveguide members among the plurality of waveguide members; and
one row of electrically conductive rods is provided between the two adjacent waveguide members.

US Pat. No. 10,559,880

MULTI-LAYERED HYBRID BEAMFORMING

AVAGO TECHNOLOGIES INTERN...

1. A device comprising:at least one processor configured to:
determine a first beam setting based on a first set of criteria associated with a first user device;
form a first beam based on the first beam setting using two radio frequency (RF) beamforming circuits and at least one digital beamforming circuit, the at least one digital beamforming circuit being interspersed between the two radio frequency beamforming circuits; and
transmit, via first antenna elements, the first beam to the first user device.

US Pat. No. 10,559,863

DYNAMIC METAL-ANODE FLOW BATTERY ENERGY-STORAGE SYSTEM

NATIONAL TAIPEI UNIVERSIT...

1. A dynamic metal-anode flow battery energy-storage system, comprising:a discharge module including at least one metal-air battery which includes a plurality of discharge reactants in a first electrolyte, wherein the discharge reactants react with oxygen in air to form a plurality of discharged products and discharge electric energy;
a charging module, being electrically connected to the discharge module and including at least one electrolysis device and at least one removal device, wherein the at least one electrolysis device includes a conductive member and a plurality of electrolysis reactants immersed in a second electrolyte; the electrolysis reactants are electrolyzed to form a plurality of electrolysis products which are adhered to a surface of the conductive member; the electrolysis products and the discharge reactants are of the same material; the at least one removal device includes a scraper adapted to remove the adhered electrolysis products from the surface of the conductive member; and
a delivery device adapted to deliver the electrolysis products into the first electrolyte as the discharge reactants, and deliver the discharged products into the second electrolyte as the electrolysis reactants.

US Pat. No. 10,559,836

METHOD AND ARRANGEMENT FOR DISTRIBUTING REACTANTS INTO A FUEL CELL OR INTO AN ELECTROLYZER CELL

ELCOGEN OY, Vantaa (FI)

1. A solid oxide fuel cell including a fuel flow guiding arrangement, the solid oxide fuel cell having a fuel side, an air side, and an electrolyte element between the fuel side and the air side, wherein the arrangement comprises:a flow field plate for each cell to arrange air flow on a first side of the flow field plate and fuel flow on a second side of flow field plate;
a flow distribution area on the flow field plate;
a flow outlet area on the flow field plate;
a side gas channel of the fuel cell located perpendicularly to a main flow direction of the fuel flow channel area for guiding fuel feed flow to the fuel distribution area, the flow distribution area being located outside of an electrochemically active electrolyte element area;
an air inflow and outflow to and from respectively, an electrolyte element in one of the same flow direction and opposite flow direction with the main fuel flow;
a flow adjusting structure for turning about 90° at least one of a fuel feed flow on the flow distribution area and fuel outlet flow on the flow outlet area, the flow adjusting structure including flow restriction orifices, each having a geometrical shape defining fuel flow volume of parallel fuel flow channels in order to equalize flow distribution on the electrolyte element, the flow adjusting structure being located outside of the electrochemically active electrolyte element area; and
the flow adjusting structure having at least partly an elliptical shape as said at least one geometrical shape, wherein the solid oxide fuel cell is configured to operate at a temperature range of 500°-1000° C.

US Pat. No. 10,559,815

METHOD OF PRODUCING MULTI-LEVEL GRAPHENE-PROTECTED CATHODE ACTIVE MATERIAL PARTICLES FOR BATTERY APPLICATIONS

Global Graphene Group, In...

1. A method of producing a mass of graphene-embraced particulates or secondary particles directly from a graphitic material for use as a lithium-ion battery cathode active material, said method comprising:a) mixing multiple particles of a graphitic material and multiple primary particles of a solid cathode active material and optional ball-milling media to form a mixture in an impacting chamber of an energy impacting apparatus, wherein said graphitic material has never been previously intercalated, oxidized, or exfoliated and said impacting chamber contains therein no previously produced isolated graphene sheets;
b) operating said energy impacting apparatus with a frequency and an intensity for a length of time sufficient for peeling off graphene sheets from said particles of graphitic material and transferring said peeled graphene sheets to surfaces of said primary particles of said solid cathode active material and fully embrace or encapsulate said primary particles to produce graphene-embraced or graphene-encapsulated primary particles of said cathode active material inside said impacting chamber;
c) recovering said graphene-embraced or graphene-encapsulated primary particles from said impacting chamber, wherein at least one of said embraced or encapsulated primary particles contains multiple graphene sheets of a first graphene material embracing or encapsulating at least one of said primary particles; and
d) combining a mass of said recovered graphene-embraced or graphene-encapsulated primary particles, an optional conductive additive, and graphene sheets of a second graphene material into a mass of graphene-embraced particulates, wherein said particulate comprises a single or a plurality of graphene-encapsulated primary particles of an cathode active material, comprising a primary particle of said cathode active material and multiple sheets of first graphene material overlapped together to embrace or encapsulate said primary particle, and wherein said single or a plurality of graphene-encapsulated primary particles, along with an optional conductive additive, are further embraced or encapsulated by multiple sheets of a second graphene material, wherein said first graphene material is the same as or different from said second graphene material, and wherein said first graphene and said second graphene material is each in an amount from 0.01% to 20% by weight and said optional conductive additive is in an amount from 0% to 50% by weight, all based on the total weight of said particulate.

US Pat. No. 10,559,810

POSITIVE ELECTRODE ACTIVE MATERIAL, POSITIVE ELECTRODE, BATTERY, BATTERY PACK, ELECTRONIC DEVICE, ELECTRIC VEHICLE, POWER STORAGE DEVICE, AND POWER SYSTEM

Murata Manufacturing Co.,...

1. A positive electrode active material comprising:a particle including a lithium composite oxide;
a first layer that is provided on a surface of the particle and includes a lithium composite oxide; and
a second layer that is provided on a surface of the first layer,
wherein the lithium composite oxide included in the particle and the lithium composite oxide included in the first layer have the same constituent elements and the same atomic ratio or a difference between atomic ratios of the constituent elements of the core particles and the first covering layer is within 10 atom %,
the second layer includes an oxide or a fluoride, and
the lithium composite oxide included in the first layer has lower crystallinity than the lithium composite oxide included in the particle.

US Pat. No. 10,559,802

SEPARATOR MEMBRANES FOR LITHIUM ION BATTERIES AND RELATED METHODS

Celgard, LLC, Charlotte,...

1. A ceramic coated separator for an energy storage device, such as a secondary lithium ion battery, comprising:a microporous polyolefin membrane having a first surface and a second surface, wherein said microporous membrane is at least one of a single layer, multiple layer, single ply, and/or multiple ply structure; and,
a ceramic coating on at least one surface of said microporous membrane, said ceramic coating comprising a layer of ceramic particles in a polymeric binder, said ceramic particles having an average particle size ranging from 0.01 ?m to 5 ?m in diameter, said polymeric binder includes poly (sodium acrylate-acrylamide-acrylonitrile) copolymer,
wherein said ceramic coated separator has a TMA TD shrinkage of about 0.5% or less at ?130° C. and at least one of the following physical characteristics: a TMA MD dimensional change of ?2% or more at ?110° C.; a MD shrinkage of 15% or less at 135° C. for one hour; a volatile component evolution of ?0.5% volatile components at ?250° C.; and a strain shrinkage of 0% at ?120° C.

US Pat. No. 10,559,777

RADIATION CURABLE COMPOSITION FOR WATER SCAVENGING LAYER, AND METHOD OF MANUFACTURING THE SAME

1. A photocurable resin composition comprising:(A) 1-30% by weight of alkaline earth metal oxide particles selected from the group consisting of dehydrated CaO, dehydrated BaO and dehydrated MgO particles;
(B) 0.1-10% by weight of at least one photoinitiator, or any mixture thereof;
(C) 30-80% by weight of at least one acrylate or methacrylate component with a ClogP higher than 2, or any mixture thereof;
(D) 5-40% by weight of at least one monofunctional acrylate or methacrylate diluent component, or any mixture thereof;
(E) 5-30% by weight of at least one acrylate or methacrylate component with functionality equal or higher than 3, or any mixture thereof;
(F) 0.1-30% by weight of a polybutadiene acrylate or methacrylate, a silicone acrylate or methacrylate, or a two-mole ethoxylated bisphenol A di(meth)acrylate, or any mixture thereof;
based on the total weight of the composition;
wherein the photocurable resin exhibits a water content of less than 1000 ppm by weight;
wherein Mica is excluded from the group of (A) alkaline earth metal oxide particles; and
wherein the photocurable resin composition does not comprise any urethane (meth)acrylate, polyester (meth)acrylate, or polyethylene glycol (PEG) (meth)acrylate.

US Pat. No. 10,559,765

ORGANIC LIGHT-EMITTING DEVICE

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting device comprising:a first electrode;
a second electrode facing the first electrode; and
an emission layer disposed between the first electrode and the second electrode; and
an electron transport region between the second electrode and the emission layer,
wherein the electron transport region comprises an electron injection layer comprising a first component comprising at least one halide of an alkali metal (Group I), a second component comprising at least one organometallic compound, and a third component comprising at least one lanthanide metal,
wherein the electron injection layer comprises a first layer and a second layer,
wherein the first layer is a film comprising the second component dispersed within a matrix comprising the first component, and the second layer is a film comprising the third component dispersed within a matrix comprising the first component; or
the first layer is a film comprising the second component dispersed within a matrix comprising the first component, and the second layer is a film comprising the third component dispersed within a matrix comprising the second component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the first component, and the second layer is a film comprising the second component dispersed within a matrix comprising the first component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the first component, and the second layer is a film comprising the third component dispersed within a matrix comprising the second component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the second component, and the second layer is a film comprising the second component dispersed within a matrix comprising the first component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the second component, and the second layer is a film comprising the third component dispersed within a matrix comprising the first component.

US Pat. No. 10,559,750

NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile memory device comprising:a first conductive portion;
an insulating film surrounding a side surface of the first conductive portion;
an intermediate layer provided on the first conductive portion and the insulating film;
a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state; and
a second conductive portion provided at least on the resistance change portion,
wherein the resistance change portion is located at a position corresponding to a position where crystal grain boundaries of three crystal grains contained in the first film are gathered.

US Pat. No. 10,559,734

LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT INCLUDING THE SAME

LG Innotek Co., Ltd., Se...

1. A light emitting device package comprising:a body;
a plurality of lead frames including a first lead frame and a second lead frame embedded in the body;
a first light emitting device disposed on the first lead frame;
a second light emitting device disposed on the second lead frame;
a first wire having a first end connected to the first lead frame and a second end connected to the first light emitting device; and
a second wire having a first end connected to the second lead frame and a second end connected to the second light emitting device,
wherein the body includes:
a bottom portion;
a first sidewall and a second sidewall disposed on the bottom portion and extending in a first direction;
a third sidewall and a fourth sidewall disposed on the bottom portion and extending from the first sidewall toward the second sidewall, and
wherein the bottom portion is disposed on a bottom of the body between the first sidewall, the second sidewall, the third sidewall and the fourth sidewall,
wherein a length between an outer side of the first sidewall and an outer side of the second sidewall in a second direction orthogonal to the first direction is longer than a length between an outer side of the third sidewall and an outer side of the fourth sidewall in the first direction,
wherein the first lead frame includes:
a first upper surface on which the first light emitting device is disposed and exposed on the bottom portion; and
a second upper surface extending from the first upper surface toward the first sidewall, exposed on the bottom portion and on which the first end of the first wire is disposed,
wherein the second lead frame includes:
a third upper surface on which the second light emitting device is disposed and exposed on the bottom portion; and
a fourth upper surface extending from the third upper surface toward the second sidewall, exposed on the bottom portion and on which the first end of the second wire is disposed,
wherein the first light emitting device is disposed closer to a center line passing from a center of the outer side of the third sidewall to a center of the outer side of the fourth sidewall than the outer side of the first sidewall,
wherein the second light emitting device is disposed closer to the center line than the outer side of the second sidewall,
wherein the center line extends from the center of the outer side of the third sidewall toward the center of the outer side of the fourth sidewall in the first direction,
wherein a length of the first upper surface in the first direction is longer than a length of the second upper surface in the first direction,
wherein a length of the third upper surface in the first direction is longer than a length of the fourth upper surface in the first direction,
wherein a length of the first upper surface in the second direction is longer than a length of the second upper surface in the second direction,
wherein a length of the third upper surface in the second direction is longer than a length of the fourth upper surface in the second direction, and
wherein a region of the body in the first direction corresponding to the center line is exposed to the bottom portion of the body and on which the plurality of lead frames are not exposed.

US Pat. No. 10,559,725

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a light emitting element having a peak emission wavelength in a range of 410 nm to 440 nm; and
a phosphor member, the phosphor member containing a phosphor comprising:
a first phosphor having a peak emission wavelength in a range of 430 nm to 500 nm and containing an alkaline-earth phosphate, which includes Cl and is activated with Eu;
a second phosphor having a peak emission wavelength in a range of 440 nm to 550 nm and containing at least one of an alkaline-earth aluminate, which is activated with Eu, and a silicate, which includes Ca, Mg, and Cl and is activated with Eu;
a third phosphor having a peak emission wavelength in a range of 500 nm to 600 nm and containing a rare-earth aluminate, which is activated with Ce;
a fourth phosphor having a peak emission wavelength in a range of 610 nm to 650 nm and containing a silicon nitride, which includes Al and at least one of Sr and Ca and is activated with Eu; and
a fifth phosphor having a peak emission wavelength in a range of 650 nm to 670 nm and containing a fluorogermanate, which is activated with Mn, wherein a percentage content of the first phosphor to a total content of the phosphor is in a range of 20 mass % to 80 mass %, and wherein when the light emitting device is configured to emit light of correlated color temperature in a range of 5,500 K to 7,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.4 to 1.5;
when the light emitting device is configured to emit light of correlated color temperature in a range of 4,500 K to 5,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.4 to 1.5;
when the light emitting device is configured to emit light of correlated color temperature in a range of 3,500 K to 4,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.3 to 1.3; and
when the light emitting device is configured to emit light of correlated color temperature in a range of 2,500 K to 3,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.2 to 1.4;
wherein the light emitting device is configured to emit light with a sum of special color rendering Indices R9 to R15 of 600 or greater.

US Pat. No. 10,559,722

LIGHT-EMITTING DEVICE

CITIZEN ELECTRONICS CO., ...

1. A light-emitting device comprising:a planar lead frame configured from first and second metal portions which are spaced apart from each other with an insulating resin interposed therebetween;
light-emitting elements mounted on the first metal portion and electrically connected by wires to the first and second metal portions;
a first resin frame disposed on the lead frame so as to enclose the light-emitting elements;
a sealing resin containing a phosphor for converting a wavelength of light emitted from the light-emitting elements, the sealing resin being filled into a region on the lead frame enclosed by the first resin frame to seal the light-emitting elements; and
a second resin frame being harder than the first resin frame and covering an outer surface of the first resin frame at an outer edge of the lead frame.

US Pat. No. 10,559,721

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate;
a light emitting element mounted on the substrate;
a light reflecting resin member surrounding the light emitting element, and configured and arranged to reflect light emitted from the light emitting element;
a sealing member disposed in a region surrounded by the light reflecting, resin member;
an electrically conductive wiring arranged on an upper surface of the substrate such that the substrate includes an exposed region exposed from the electrically conductive wiring with at least a part of the exposed region of the substrate being embedded in the light reflecting resin member, the electrically conductive wiring being electrically connected to the light emitting element; and
a lens member disposed above the light emitting element to reach an outer edge of the substrate, the lens member being in contact with an upper surface of the sealing member and an upper surface and an outer lateral surface of the light reflecting resin member, an entire top surface of the lens member being exposed with the top surface of the lens member defining a part of an outermost surface of the light emitting device.

US Pat. No. 10,559,712

QUANTUM DOTS AND DEVICES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A core-shell quantum dot including at least two different halogens,the core-shell quantum dot comprising:
a core comprising a first semiconductor nanocrystal; and
a shell disposed on the core, the shell comprising a crystalline or amorphous material,
wherein the core-shell quantum dot does not include cadmium,
wherein a solid state photoluminescence quantum efficiency of the core-shell quantum dot, when measured at 90° C. or greater, is greater than or equal to about 95% of a solid state photoluminescence quantum efficiency of the core-shell quantum dot when measured at 25° C., and
wherein the at least two different halogens comprise fluorine and at least one of chlorine, bromine, and iodine.

US Pat. No. 10,559,699

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive layer over an insulating surface;
a first insulating layer over the first conductive layer;
oxide semiconductor stacked lavers comprising a first oxide semiconductor layer and a second oxide semiconductor layer, the oxide semiconductor stacked layers comprise a region overlapping with the first conductive layer with the first insulating layer interposed therebetween;
a second conductive layer and a third conductive layer, each of which comprises a region over and in contact with the second oxide semiconductor layer;
a second insulating layer comprising a region in direct contact with the oxide semiconductor stacked layers and positioned over the oxide semiconductor stacked layers, the second conductive layer and the third conductive layer; and
a fourth conductive layer comprising a region overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed therebetween,
wherein the second semiconductor layer is provided over the first oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises a region in direct contact with the first insulating layer,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises at least indium and gallium,
wherein an indium content in the first oxide semiconductor layer is higher than a gallium content,
wherein an indium content in the second oxide semiconductor layer is lower than a gallium content,
wherein the first oxide semiconductor layer comprises a microcrystal,
wherein the second oxide semiconductor layer comprises a c-axis aligned crystal part,
wherein the first conductive layer comprises molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, and
wherein the fourth conductive layer comprises indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium oxide-zinc oxide, or indium tin oxide to which silicon oxide is added.

US Pat. No. 10,559,688

TRANSISTOR WITH THERMAL PERFORMANCE BOOST

Intel Corporation, Santa...

1. An integrated circuit including a finFET transistor, the integrated circuit comprising:a fin including a first material comprising semiconductor material;
a gate structure above the fin and adjacent sidewalls of the fin, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the fin;
a source region and a drain region, the fin at least partially between the source and drain regions, the source and drain regions including a second material comprising semiconductor material; and
a third material distinct from the first and second materials, the third material adjacent to at least one of the source or drain regions, the at least one of the source or drain regions between the third material and the fin, wherein the third material has a linear coefficient of thermal expansion (CTE) value that is either greater than 5 parts per million per degree Celsius (ppm/° C.) at around 20° C. or less than 0 ppm/° C. at around 20° C.

US Pat. No. 10,559,681

HIGH VOLTAGE LATERAL JUNCTION DIODE DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating an integrated circuit (IC), comprising:forming in a semiconductor surface layer, doped a first conductivity type, a depletion-mode laterally diffused MOSFET (LDMOS device), including forming a source and a drain doped a second conductivity type within said substrate, a channel region between the source and the drain, a gate dielectric over the channel region, a gate over the gate dielectric, and a drift region between said channel region and said drain, wherein said drain also provides a first cathode for a lateral junction diode having a first anode adjacent the source and running in parallel with a path between said source and said drain;
forming a clamp diode including a second cathode and a second anode, wherein said clamp diode is junction-isolated from the LDMOS device by a doped region of the second conductivity type located between said second anode and said source, and
directly connecting said gate to said second anode, and directly connecting said source to said second cathode.

US Pat. No. 10,559,666

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A structure, comprising:a semiconductor substrate;
a semiconductor buffer layer disposed over the semiconductor substrate;
an oxide layer disposed over the buffer layer; and
a fin comprising a semiconductor material disposed over the oxide layer,
wherein the semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer, and
wherein a distance between a top surface of the oxide layer and a bottom surface of the buffer layer is more than a distance between a bottom surface of the fin and the bottom surface of the buffer layer.

US Pat. No. 10,559,662

HYBRID ASPECT RATIO TRAPPING

International Business Ma...

1. A semiconductor structure comprising:a material stack consisting of a silicon germanium alloy portion that is relaxed and defect-free and a semiconductor material pillar that is defect-free, wherein the silicon germanium alloy portion is in direct physical contact with a topmost surface of a semiconductor substrate and the semiconductor material pillar is in direct physically contact with a topmost surface of the silicon germanium alloy portion, and wherein an entirety of the semiconductor substrate extends beyond outermost sidewalls of the material stack; and
a dielectric material structure located laterally adjacent to the material stack and having a bottommost surface in direct contact with physically exposed portions of the topmost surface of the semiconductor substrate, wherein the bottommost surface of the dielectric material stack is coplanar with a bottommost surface of the silicon germanium alloy portion of the material stack that forms an interface with the topmost surface of the semiconductor substrate.

US Pat. No. 10,559,659

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:a surface electrode disposed on a semiconductor substrate and through which a main current flows;
a first metal layer that is disposed on the surface electrode and is not a sintered compact; and
at least one second metal layer that is disposed on the first metal layer and is a sintered compact,
wherein the second metal layer has a size to cover all the surface electrode in plan view, and has higher heat conductivity than the first metal layer,
wherein the first metal layer is wider in the plan view than the second metal layer, and
wherein the first metal layer is disposed between the second metal layer and the surface electrode.

US Pat. No. 10,559,658

SCHOTTKY BARRIER DIODE

ROHM CO., LTD., Kyoto (J...

1. A Schottky barrier diode, comprising:a first semiconductor layer having depressions on a top surface thereof;
a guard ring arranged in an outer periphery portion of the first semiconductor layer so as to surround the depressions; and
a first metal layer covering an entire area of the top surface surrounded by the guard ring and entire surfaces of the depressions, and being in Schottky junction with the top surface as well as bottom faces of the depressions; wherein
the guard ring extends from the top surface to an inner position of the first semiconductor layer at a depth deeper than depths of the depressions.

US Pat. No. 10,559,648

CHIP RESISTOR AND CHIP RESISTOR ASSEMBLY

SAMSUNG ELECTRO-MECHANICS...

1. A chip resistor, comprising:a base substrate having a first surface and a second surface opposing each other, two side surfaces connecting the first surface and the second surface, and two end surfaces connecting the first surface and the second surface;
a resistive layer disposed on the second surface of the base substrate, the resistive layer having a first surface in contact with the base substrate and a second surface opposing the first surface of the resistive layer;
a first terminal and a second terminal spaced apart from each other and each being connected to the resistive layer on the second surface of the resistive layer; and
a third terminal connected to the resistive layer on the second surface of the resistive layer, disposed between the first terminal and the second terminal, and extending to the first surface of the base substrate along the side surfaces,
wherein the third terminal includes a first surface portion disposed on the first surface of the base substrate, and the first surface portion is divided into two portions extended from the two side surfaces.

US Pat. No. 10,559,642

ORGANIC LIGHT-EMITTING DEVICE HAVING A FLUORIDE AND METAL BASED INTERMEDIATE LAYER AND PRODUCTION METHOD

JOLED INC., Tokyo (JP)

2. An organic light-emitting device, comprising:a substrate;
an anode disposed above the substrate;
a wiring disposed above the substrate, the wiring being spaced away from the anode in a direction parallel to a main surface of the substrate;
a light-emitting layer disposed above the anode and containing an organic light-emitting material;
an intermediate layer disposed on the light-emitting layer and above the wiring, the intermediate layer being continuous over the light-emitting layer and the wiring and containing a fluoride of a first metal, the first metal being an alkali metal or an alkaline earth metal;
an organic functional layer disposed on the intermediate layer, the organic functional layer being continuous over the light-emitting layer and the wiring and made of an organic material doped with a second metal, the organic material having at least one of an electron transporting property and an electron injection property, the second metal having a property of cleaving a bond between the first metal and fluorine in the fluoride of the first metal; and
a cathode disposed on the organic functional layer, the cathode being continuous over the light-emitting layer and the wiring, wherein
1?x?2, 20?y?40, and y?20x, where
x denotes a film thickness [nm] of the intermediate layer and y denotes a dope concentration [wt %] of the second metal in the organic functional layer.

US Pat. No. 10,559,641

MULTIPLE SUBTHRESHOLD SWING CIRCUIT AND APPLICATION TO DISPLAYS AND SENSORS

International Business Ma...

1. A three-terminal apparatus, comprising:a field-effect transistor (FET) comprising:
a first layer comprising silicon having a first type of carrier as its majority carrier;
a gate comprising a second layer formed on the first layer, the second layer comprising intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer, the third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier, and a conductive layer formed on the third layer; and
drain and source terminals, each of the drain and source terminals comprising a fourth layer formed on the first layer, the fourth layer comprising crystalline hydrogenated silicon having the first type of carrier as its majority carrier, and a conductive layer formed on the fourth layer; and
a set of one or more serially-connected diodes, each diode having first and second terminals, wherein the first terminal of a first diode in the set of one or more serially-connected diodes is connected to the source terminal of the FET;
wherein the gate of the FET forms a first terminal of the three-terminal apparatus, the drain terminal of the FET forms a second terminal of the three-terminal apparatus, and the second terminal of a last diode in the set of one or more serially-connected diodes forms a third terminal of the three-terminal apparatus, the first, second and third terminals of the three-terminal apparatus being independently controllable relative to one another; and
wherein a subthreshold swing of the three terminal apparatus is higher than a subthreshold swing of the FET by a factor proportional to a sum of ideality factors of the set of one or more serially-connected diodes.

US Pat. No. 10,559,640

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light emitting display device comprising:a display panel having a plurality of gate lines and data lines;
a timing controller controlling an operation timing of each pixel;
a gate driver driving the gate lines;
a data driver having a plurality of data driving integrated circuits driving the data lines; and
an embedded point-to-point interface between the timing controller and each of the data driving integrated circuits,
transmitting video/control data signal from the timing controller to each of the data driving integrated circuits and transmitting a sensing value from the data driving integrated circuits to the timing controller,
wherein the timing controller comprises;
a first transmission module transmitting video/control data signal to each of the data driving integrated circuits via the embedded point-to-point interface,
a first reception module receiving the sensing value from each of the data driving integrated circuits via the embedded point-to-point interface,
a first transmission/reception selector enabling one of the first transmission module and the first reception module, and disabling the other of non-enabled module, and
a transmission/reception timing controller controlling the first transmission/reception selector, and
wherein each of data driving integrated circuits comprises;
a second reception module receiving the video/control data signal from the timing controller through the embedded point-to-point interface;
a clock data recovery unit restoring video data, control data, and a clock signal from the video/control data signal received through the second reception module;
an oscillator generating the clock signal in accordance with the restored control signal;
an encoder encoding the sensing value sensed from the display panel in synchronization with the clock signal generated by the oscillator;
a second transmission module converting the sensing value encoded by the encoder into a transmission packet and transmitting the transmission packet to the timing controller through the embedded point-to-point interface;
a counter counting the clock signal generated from the oscillator and outputting a control signal when a counted value reaches a predetermined value; and
a second transmission/reception selector disabling the second reception module and enabling the second transmission module according to the control signal restored by the control data processing unit, and disabling the second transmission module and enabling the second reception module according to the control signal of the counter.

US Pat. No. 10,559,639

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing an organic light-emitting display device, comprising steps of:providing a substrate;
forming a first patterned metal layer on the substrate, wherein the patterned metal layer comprises a gate of a switching thin film field-effect transistor and a gate of a driving thin film field-effect transistor;
forming a gate insulating layer having a first via hole on the first patterned metal layer;
forming a first indium-gallium-zinc oxide layer on the gate insulating layer, wherein the first indium-gallium-zinc oxide layer comprises a first active layer for reducing a sub-threshold swing of a transfer characteristic curve of the switching thin film field-effect transistor;
forming a second indium-gallium-zinc oxide layer on the first active layer and the gate insulating layer, wherein the second indium-gallium-zinc oxide layer comprises a third active layer and a second active layer for increasing a sub-threshold swing of a transfer characteristic curve of the driving thin film field-effect transistor;
forming a second patterned metal layer on the second indium-gallium-zinc oxide layer, wherein the second patterned metal layer comprises a source and a drain of the switching thin film field-effect transistor and a source and a drain of the driving thin film field-effect transistor, and the source of the switching thin film field-effect transistor is connected with the gate of the driving thin film field-effect transistor through the first via hole;
forming a passivation layer having a second via hole on the second patterned metal layer; and forming a third metal layer on the passivation layer, wherein the third metal layer comprises a pixel electrode connecting with the source of the driving thin film field-effect transistor through the second via hole,
wherein an oxygen content of the second indium-gallium-zinc oxide layer is greater than that of the first indium-gallium-zinc oxide laver.

US Pat. No. 10,559,631

METHOD OF MANUFACTURING A DISPLAY DEVICE UTILIZING PIXEL AND DUMMY PORTIONS

Samsung Display Co., Ltd....

1. A method for manufacturing a display device, the method comprising:preparing a first mother substrate;
preparing a second mother substrate having a plurality of unit areas divided by an imaginary line;
forming a pixel portion at the unit areas;
forming a dummy portion along the imaginary line;
bonding the first mother substrate and the second mother substrate with an interlayer between the first mother substrate and the second mother substrate; and
cutting the first mother substrate and the second mother substrate along the imaginary line,
wherein at least a portion of the pixel portion and at least a portion of the dummy portion are formed by a same process.

US Pat. No. 10,559,619

IMAGING DEVICE AND METHOD OF MANUFACTURING IMAGING DEVICE

Sony Corporation, Tokyo ...

1. An imaging device comprising:a first semiconductor chip configured to include a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line, wherein the first semiconductor chip includes a transfer gate and an overflow gate disposed in a first row, the signal input transistor and the reference input transistor are disposed in a second row, and a photodiode located between the first row and the second row; and
a second semiconductor chip configured to include a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad.

US Pat. No. 10,559,615

METHODS FOR HIGH-DYNAMIC-RANGE COLOR IMAGING

OmniVision Technologies, ...

8. A method for generating high-dynamic-range images, comprising:partly absorbing first light propagating from a scene toward a plurality of first pixels of a photosensitive pixel array to attenuate the first light as compared to second light propagating from the scene toward a plurality of second pixels of the photosensitive pixel array, the plurality of second pixels being interleaved with the plurality of first pixels; and
after said partly absorbing, spectrally filtering the first light to form an attenuated color image of the scene on the photosensitive pixel array at the first pixels and spectrally filtering the second light to form a brighter color image of the scene on the photosensitive pixel array at the second pixels;
said spectrally filtering the first and second light including (a) spectrally filtering, with first color filters having a first thickness, first and second light propagating toward a first subset of the plurality of first pixels and the plurality of second pixels and (b) spectrally filtering, with second color filters having a second thickness, first and second light propagating toward a second subset of the plurality of first pixels and the plurality of second pixels, the second thickness exceeding the first thickness, the first color filters being configured to transmit longer wavelengths than the second color filters;
said partly absorbing including partly absorbing, with the same type of grey material, the first light propagating toward (a) the first pixels of the first subset and (b) the first pixels of the second subset, the grey material over the first pixels of the first subset being thinner than the grey material over the first pixels of the second subset to compensate for transmission of the grey material being an increasing function of wavelength.

US Pat. No. 10,559,614

DUAL CONVERSION GAIN CIRCUITRY WITH BURIED CHANNELS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor pixel formed on a semiconductor substrate, the image sensor pixel comprising:a photodetector that generates charge in response to incident light;
a floating diffusion node that stores the charge;
a dual conversion gain capacitor;
a dual conversion gain switch that transfers the charge from the floating diffusion node to the dual conversion gain capacitor while the dual conversion gain switch is on; and
a buried channel in the semiconductor substrate that transfers the charge from the floating diffusion node to the dual conversion gain capacitor while the dual conversion gain switch is off.

US Pat. No. 10,559,612

SIGNAL PROCESSING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SIGNAL PROCESSING CIRCUIT

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a back gate voltage control circuit;
wherein the transistor comprises a gate, a back gate and a channel formation region,
wherein the channel formation region comprises an oxide semiconductor, wherein the gate of the transistor is electrically connected to a wiring,
wherein the back gate of the transistor is electrically connected to the back gate voltage control circuit, and
wherein the back gate voltage control circuit is configured to apply a potential corresponding to a command to the back gate of the transistor.

US Pat. No. 10,559,611

IMAGE SENSOR

STMicroelectronics (Croll...

1. An image sensor including a plurality of pixels, each pixel comprising:a semiconductor substrate doped with a first dopant type;
a first insulated vertical electrode that delimits a photosensitive area doped with a second dopant type, wherein the first insulated vertical electrode is electrically connected to receive a first bias voltage;
a second insulated vertical electrode and a third insulated vertical electrode that delimit a charge storage area doped with said second dopant type, wherein the second and third insulated vertical electrodes are physically separate from each other but electrically connected to receive a second bias voltage;
wherein said first insulated vertical electrode and said third insulated vertical electrode extend parallel to each other with a first portion of said semiconductor substrate doped with the first dopant type positioned in contact with and extending between said first and third insulated vertical electrodes;
wherein the third insulated vertical electrode extends between the charge storage area and the photosensitive area; and
wherein the second insulated vertical electrode extends perpendicular to the third insulated vertical electrode at a first end of the third insulated vertical electrode to delimit a region for charge passage between the photosensitive area and the charge storage area in response to the second bias voltage.

US Pat. No. 10,559,603

DISPLAY PANEL AND DISPLAY APPARATUS THEREOF

SHANGHAI TIANMA MICRO-ELE...

1. A display panel, comprising:a display region;
a bonding region bonding a flexible circuit board with the display panel,
wherein the bonding region comprises a first surface located at a displaying side of the display panel and an opposing second surface,
the bonding region includes a plurality of first pins and a plurality of second pins,
the plurality of first pins are disposed at the first surface of the bonding region, and
the plurality of second pins are disposed at the second surface of the bonding region; and
a plurality of first transmission lines and a plurality of second transmission lines,
wherein a first transmission line of the plurality of first transmission lines is connected to a first pin of the plurality of first pins,
a distance between the first pin and the display region is a first distance,
a second transmission line of the plurality of second transmission lines is connected to a second pin of the plurality of second pins,
a distance between the second pin and the display region is a second distance,
the first distance is approximately equal to the second distance,
the second transmission line and the second pin are disposed on different film layers, and
the plurality of first transmission lines and the plurality of second transmission line transmit display signals.

US Pat. No. 10,559,597

DISPLAY PANEL AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

20. A display device, comprising:a display panel comprising a display area and a non-display area surrounding the display area, wherein:
the display area is disposed with a plurality of data lines extending along a first direction; the display area has a notch, and a boundary of the display area is recessed into the display area in a second direction to form the notch; the second direction intersects with the first direction; and the non-display area includes a notched non-display area that surrounds the notch by substantially in half; and
the display panel includes:
a substrate layer;
an array layer located over the substrate layer, wherein the data lines are located at the array layer;
a display layer located at a side of the array layer away from the substrate layer, wherein the display layer includes a plurality of light emitting components;
an encapsulation cover located at a side of the display layer away from the array layer;
an encapsulant disposed between the array layer and the encapsulation cover, wherein the encapsulant is located in the non-display area and surrounds the display layer; and
an encapsulated metal located in the non-display area, wherein the encapsulated metal is disposed in the array layer; in a laser-sintering process of the encapsulant, the encapsulated metal is used for reflecting laser light; an orthographic projection of the encapsulated metal in the substrate layer has a non-closed pattern; and the encapsulated metal is undisposed in at least a portion of the notched non-display area.

US Pat. No. 10,559,592

MEMORY DEVICE AND FORMING METHOD THEREOF

Yangtze Memory Technologi...

1. A memory device, comprising:a substrate;
a first layer stack above the substrate, having alternating conductor and insulator layers;
a capping dielectric layer disposed over the first layer stack;
a second layer stack, disposed over the capping dielectric layer, having alternating conductor and insulator layers; and
one or more array common source contacts extending orthogonally with respect to the surface of the substrate through the first layer stack and the second layer stack, wherein at least one of the one or more array common source contacts comprises a first conductive contact and a second conductive contact that is disposed over and electrically connected with the first conductive contact.

US Pat. No. 10,559,591

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A vertical memory device, comprising:first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate;
a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region;
a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction;
a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel,
wherein the channel directly contacts a sidewall of the second impurity region; and
a support pattern between a top surface of the first impurity region and a lower surface of the third impurity region, wherein an upper surface of the support pattern contacts an edge of the lower surface of the third impurity region.

US Pat. No. 10,559,586

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a semiconductor substrate comprising a termination region surrounding a device region thereof, the termination region comprising a first stacked body extending around the device region and including a first layer composed of an insulating material located on a surface of the semiconductor substrate, a second layer composed of a conductive material located over the first layer, and a third layer composed of an insulating material located over the second layer;
an opening extending through the first stacked body and extending around the device region;
a fourth layer, composed of an insulating material, located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening;
a fifth layer, composed of an insulating material, located over the fourth layer; and
a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the semiconductor substrate, wherein
the composition of the third and fifth layers is different from that of the first and fourth layers.

US Pat. No. 10,559,583

MEMORY DEVICE

Samsung Electronics Co., ...

1. A memory device comprising:a substrate having an upper surface and source regions at the upper surface;
a stack on the upper surface and including gate electrode layers, each of some of the gate electrode layers including unit electrodes and connecting electrodes, each of the unit electrodes extending longitudinally in a first direction, and each of the connecting electrodes disposed between a pair of the unit electrodes being closest to each other in a second direction and connecting the pair of the unit electrodes to each other;
first common source lines, each of the first common source lines connecting to a respective one of the source regions and extending longitudinally in the first direction to separate the stack into a plurality of blocks; and
second common source lines, each of the second common source lines connecting to a respective one of the source regions and extending longitudinally in the first direction, wherein
each of the second common source lines includes a first line and a second line separated in the first direction, by a respective one of the connecting electrodes, the first line and the second line in each of the second common source lines are disposed at the same position in the second direction,
the first lines included in a pair of the second common source lines being closest to each other in the second direction, in at least one of the plurality of blocks, have different lengths in the first direction,
in at least one of the plurality of blocks, two of the second lines have the same length in the first direction, and one of the second lines between the two of the second lines have a different length from the two of the second lines in the first direction, and
a distance between the first line and the second line included in one of the pair of the second common source lines is substantially the same with a distance between the first line and the second line included in another one of the pair of the second common source lines.

US Pat. No. 10,559,574

THREE-DIMENSIONAL VERTICAL ONE-TIME-PROGRAMMABLE MEMORY COMPRISING SCHOTTKY DIODES

HangZhou HaiCun Informati...

1. A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;
a plurality of vertical address lines in said memory holes and in contact with said antifuse layer;
a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state;
wherein said horizontal and vertical address lines are separated by said antifuse layer only.

US Pat. No. 10,559,570

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor memory device, comprising:a semiconductor substrate;
bit line structures disposed on the semiconductor substrate, wherein each of the bit line structures is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction, wherein the second direction is substantially orthogonal to the first direction;
storage node contacts disposed on the semiconductor substrate, wherein each of the storage node contacts is disposed between two of the bit line structures disposed adjacent to each other in the second direction;
isolation structures disposed on the semiconductor substrate, wherein each of the isolation structures is disposed between two of the bit line structures disposed adjacent to each other in the second direction, each of the storage node contacts is disposed between two of the isolation structures disposed adjacent to each other in the first direction, and each of the isolation structures comprises two first portions and a second portion disposed between the two first portions in the second direction, wherein each of the first portions is elongated in the first direction and partially disposed between one of the bit line structures disposed adjacent to the isolation structure and one of the storage node contacts disposed adjacent to the isolation structure in the second direction, wherein each of the first portions is disposed between the second portion and one of the bit line structures disposed adjacent to the isolation structure in the second direction; and
a plurality of word line structures having extending direction thereof in the second direction.

US Pat. No. 10,559,563

METHOD FOR MANUFACTURING MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS

Taiwan Semiconductor Manu...

1. A method for manufacturing an integrated circuit (IC), the method comprising:forming a first interlayer dielectric (ILD) layer over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer;
transferring a first doping-type layer and a second doping-type layer to a top surface of the first ILD layer, wherein the first and second doping-type layers are stacked and are semiconductor materials with opposite doping types;
patterning the first and second doping-type layers to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire; and
forming a gate electrode straddling the first and second doping-type wires, wherein the gate electrode and the first and second doping-type wires at least partially define a junctionless semiconductor device (JSD).

US Pat. No. 10,559,553

POWER MODULE

General Electric Company,...

1. A power module, comprising:a plurality of conductive traces disposed on a first portion of a surface and a second portion of the surface, wherein the first portion is opposite the second portion; and
a bus bar structure comprising:
a first bus bar having a first plurality of tabs extending away from the first bus bar, wherein each tab of the first plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first portion of the surface, and wherein the first bus bar comprises a first terminal disposed on a first side of a transversal axis;
a second bus bar having a second plurality of tabs extending away from the second bus bar, wherein each tab of the second plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second portion of the surface, and wherein the second bus bar comprises a second terminal disposed on the first side of the transversal axis; and
a third bus bar having a third plurality of tabs extending away from the third bus bar, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first portion of the surface and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second portion of the surface; wherein the third bus bar comprises a third terminal disposed on a second side of the transversal axis, and wherein the first side is opposite the second side.

US Pat. No. 10,559,552

SEMICONDUCTOR DEVICE COMPRISING PN JUNCTION DIODE AND SCHOTTKY BARRIER DIODE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:an insulating substrate;
a first conductive wiring provided on the insulating substrate;
a second conductive wiring provided on the insulating substrate and separated from the first conductive wiring;
a third conductive wiring provided on the insulating substrate and separated from the first and second conductive wirings, the second and third conductive wirings being arranged on the insulating substrate with the first conductive wiring interposed therebetween;
a MOSFET made of a semiconducting material that chiefly includes SiC, the MOSFET including a PN junction diode having a cathode connected to the first conductive wiring;
a diode having an operating voltage lower than an operating voltage of the PN junction diode, the diode having a cathode connected to the first conductive wiring;
a first bonding wire that connects an anode of the PN junction diode to the second conductive wiring;
a second bonding wire that connects an anode of the diode to the second conductive wiring, the second bonding wire having an inductance that is smaller than an inductance of the first bonding wire; and
a third bonding wire that connects a gate of the MOSFET to the third conductive wiring.

US Pat. No. 10,559,548

ANISOTROPIC CONDUCTIVE BONDING MEMBER, SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE PRODUCTION METHOD

FUJIFILM Corporation, To...

1. An anisotropic conductive bonding member comprising:an insulating base which is made of an inorganic material;
a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof, and are provided in a mutually insulated state; and
a pressure sensitive adhesive layer which is provided on a surface of the insulating base,
wherein each of the conductive paths has a protrusion protruding from the surface of the insulating base,
the protrusion of each of the conductive paths is buried in the pressure sensitive adhesive layer,
the pressure sensitive adhesive layer contains an antioxidant material and a polymer material, and
wherein in the pressure sensitive adhesive layer, the antioxidant material is eccentrically located on a side close to an interface between the protrusion of each of the conductive paths and the pressure sensitive adhesive layer.

US Pat. No. 10,559,546

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising a solder ball, the solder ball comprising:a copper ball;
a layer of solder over an outer surface of the copper ball; and
an intermediate layer separating the copper ball and the layer of solder, wherein the intermediate layer has a first annular thickness on a first portion of the copper ball and has a second annular thickness on a second portion of the copper ball, the second annular thickness being greater than the first annular thickness.

US Pat. No. 10,559,536

MULTI-LAYER CONDUCTORS FOR NOISE REDUCTION IN POWER ELECTRONICS

ABB Schweiz AG, Baden (C...

1. A multi-layered conductor comprising:one or more conductor layers comprising an electrically conductive material; and
one or more shielding layers having a first shield end and an opposing second shield end, at least a portion of the one or more shielding layers between the first shield end and the second shield end being directly attached to at least a portion of an outer surface of the one or more conductor layers, and another portion of the one or more shield layers around the second shield end being detached from an adjacent portion of the outer surface of the one or more conductor layers, the one or more shielding layers comprising a soft magnetic material having a lower conductivity and a higher magnetic permeability than the electrically conductive material of the one or more conductor layers.

US Pat. No. 10,559,533

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a stacked body including a plurality of first films and a plurality of second films that are alternately provided on a substrate in a first direction; and
N2 plugs that are provided in the stacked body, are adjacent to one another in a second direction crossing with the first direction and a third direction crossing with the first and second directions, and have first to (N2)th depths where N is an integer of three or more regarding the N2 plugs and the (N2)th depths,
wherein
a Yth depth is a depth of penetration of Y second film(s) where Y is an integer from 1 to N2,
plugs adjacent to each other in the second direction have an ?th depth and an (?+1)th depth,
plugs adjacent to each other in the third direction have a ?th depth and a (?+N)th depth, and
any of ?, ?+1, ? and ?+N is an integer from 1 to N2.

US Pat. No. 10,559,528

SEMICONDUCTOR DEVICE INCLUDING EXTERNAL TERMINAL GROUPS

Rohm Co., Ltd., Kyoto (J...

1. An electronic apparatus comprising:a semiconductor device, and
a bypass capacitor,
wherein the semiconductor device comprises:
an upper-side transistor,
a lower-side transistor, and
a plurality of external terminals arranged in a matrix at a bottom surface of a package,
wherein the plurality of external terminals include:
a first external terminal group connected to a first node of the upper-side transistor,
a second external terminal group connected to a second node of the upper-side transistor and a first node of the lower-side transistor,
a third external terminal group connected to a second node of the lower-side transistor, and
a fourth external terminal which does not belong to the first external terminal group, the second external terminal group or the third external terminal group, and
wherein the first external terminal group, the second external terminal group and the third external terminal group are laid out such that an arrangement pattern of the second external terminal group engages with at least one of an arrangement pattern of the first external terminal group or an arrangement pattern of the third external terminal group,
wherein the first external terminal group is connected to a power supply line which is outside the semiconductor device, and the third external terminal group is connected to a ground line which is outside the semiconductor device,
wherein the bypass capacitor is connected between the power supply line and the ground line outside the semiconductor device, and
wherein the fourth terminal is disposed neither between the first external terminal group and the bypass capacitor, nor between the third external terminal group and the bypass capacitor.

US Pat. No. 10,559,526

ELECTRO-LUMINESCENCE DISPLAY DEVICE AND DRIVER IC FILM UNIT FOR ELECTRO-LUMINESCENCE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A driver IC film unit including:a flexible film;
a driver IC on a first surface of the flexible film and configured to receive an input signal and convert the input signal into an image signal for a display panel;
at least first to third pad units, on the first surface of the flexible film, configured to electrically connect the driver IC and the flexible film; and
at least first to third wire units, on the first surface of the flexible film, electrically connected to the at least first to third pad units,
wherein at least one wire unit among the at least first to third wire units is configured to be extended to a second surface facing the first surface via a first via hole passing through the flexible film, and is configured to include a cut portion of wire corresponding to an edge of the flexible film.

US Pat. No. 10,559,524

2-STEP DIE ATTACH FOR REDUCED PEDESTAL SIZE OF LAMINATE COMPONENT PACKAGES

TEXAS INSTRUMENTS INCORPO...

1. A method of assembling a semiconductor device, comprising:providing a leadframe (LF) strip having a plurality of LFs each with a plurality of laminate-supporting pedestals;
adding a first die attach (DA) material comprising an ultraviolet (UV)-curing DA material or a B-stage DA material on an outer edge of the plurality of pedestals;
adding a thermally-curing DA material on an area of the plurality of pedestals not occupied by the UV-curing DA material;
mounting a laminate component having bond pads on a top side with the top side up on the plurality of pedestals, and
thermally curing to cure the thermally-curing DA material.

US Pat. No. 10,559,519

SERIES CIRCUIT ARRANGEMENT OF POWER SEMICONDUCTORS

SIEMENS AKTIENGESELLSCHAF...

1. A series circuit arrangement of power semiconductors, the series circuit comprising:a cooling water distribution apparatus including cooling-water boxes arranged on the power semiconductors;
wherein the cooling-water boxes are connected to the power semiconductors in electrically conducting manner; and
two cooling-water distributor lines;
wherein a first cooling-water distributor line includes a cooling-water inlet; and
a second cooling-water distributor line includes a cooling-water outflow;
wherein cooling chambers are connected in parallel between the cooling-water distributor lines with respect to a cooling-water stream; and
respective branchings on the cooling-water distributor lines for the cooling chambers;
wherein the cooling chambers are connected to the branchings via a respective connecting line; and
a control electrode arranged on the cooling-water distributor lines, terminally in each instance;
wherein, for at least some of the cooling chambers, the branchings on the cooling-water distributor lines are arrayed relative to the position of the respective cooling chamber in offset manner in relation to a geometrically shortest possible link to the cooling-water distributor lines, so that a difference of potential between the cooling chambers and the branchings is minimized.

US Pat. No. 10,559,516

METHOD OF FABRICATING RFIC DEVICE

NINGBO SEMICONDUCTOR INTE...

1. A method of fabricating the radio frequency integrated circuit (RFIC) device, the method comprising:forming a semiconductor component based on a first semiconductor layer over a substrate layer, the semiconductor component including at least one transistor; and forming a first dielectric layer covering the semiconductor component, wherein a second dielectric layer is included between the first semiconductor layer and the substrate layer;
bonding a second substrate to the semiconductor component using the first dielectric layer as a bonding layer;
removing the substrate layer from the second dielectric layer with the second substrate serving as a support, thereby exposing the second dielectric layer;
forming a sheet-like heat sink by a material at least including a dielectric material, on the exposed surface of the second dielectric layer for dissipating heat from the semiconductor component; and
removing the second substrate.

US Pat. No. 10,559,514

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface, and containing a semiconductor material that has a bandgap wider than that of silicon;
a first semiconductor layer of a first conductivity type provided in the semiconductor substrate;
a second semiconductor layer of a second conductivity type provided in the semiconductor substrate, the second semiconductor layer being closer to the first main surface than is the first semiconductor layer, the second semiconductor layer being in contact with the first semiconductor layer and exposed at the first main surface;
a first first-conductivity-type semiconductor region of the first conductivity type selectively provided in the second semiconductor layer;
a trench penetrating the first first-conductivity-type semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer;
a gate insulating film provided in the trench, along an inner wall of the trench;
a gate electrode provided on the gate insulating film in the trench;
an interlayer insulating film provided on the first main surface of the semiconductor substrate and covering the gate insulating film and the gate electrode;
a contact hole penetrating the interlayer insulating film in a depth direction and reaching the first main surface of the semiconductor substrate;
a first electrode forming an ohmic contact with the first first-conductivity-type semiconductor region and the second semiconductor layer in the contact hole;
a terminal pin soldered to the first electrode via a plating film; and
a second electrode provided on the second main surface of the semiconductor substrate, wherein
the first electrode includes:
a first titanium nitride film provided separated from the first main surface of the semiconductor substrate exposed in the contact hole, the first titanium nitride film covering a part of the interlayer insulating film,
a silicide film forming the ohmic contact and provided on the first main surface of the semiconductor substrate exposed in the contact hole,
an aluminum-based metal film containing aluminum as a principal component and provided on the first main surface of the semiconductor substrate, from on the interlayer insulating film, the aluminum-based metal film covering the first titanium nitride film and the silicide film.

US Pat. No. 10,559,513

CIRCUIT BOARD AND PACKAGED CHIP

MEDIATEK INC., Hsinchu (...

1. A circuit board, comprising:an upper surface and a lower surface that are opposite to each other;
a plurality of heat sink bonding pads, disposed on the upper surface, and electrically insulated from one another, for electrically connecting to a heat sink;
a plurality of heat sink conductive pads, disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively; and
a circuit layer, comprising a plurality of heat sink traces, wherein the heat sink conductive pads are electrically connected to the heat sink bonding pads through the heat sink traces, respectively, and the heat sink traces are electrically insulated from one another.

US Pat. No. 10,559,505

PROTECTIVE FILM-FORMING FILM, SHEET FOR FORMING PROTECTIVE FILM, COMPLEX SHEET FOR FORMING PROTECTIVE FILM, AND INSPECTION METHOD

Lintec Corporation, Toky...

1. An inspection method comprising: adhering a protective film-forming film to a semiconductor wafer; curing the protective film-forming film to obtain a semiconductor wafer provided with a protective film; and, irradiating infrared rays to the semiconductor wafer provided with the protective film or a semiconductor chip obtained by processing the semiconductor wafer provided with the protective film, to inspect presence of cracks which cannot be detected by visual observation in the semiconductor wafer provided with the protective film or the semiconductor chip provided with the protective film; wherein the light transmittance at a wavelength of 1600 nm of the protective film-forming film is 72% or greater, and the light transmittance at a wavelength of 550 nm of the protective film-forming film is 20% or less.

US Pat. No. 10,559,503

METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

GLOBALFOUNDRIES INC., Gr...

1. A finFET device, comprising:a first gate structure and a second gate structure on a semiconductor substrate;
a first active area contacting a first end of said first gate structure and contacting a first end of said second gate structure;
a second active area contacting a second end of said first gate structure and contacting a second end of said second gate structure; and
a self-aligned trench silicide (TS) structure configured to operatively couple said first active area to said second active area, wherein said TS structure is flush in height with said first gate structure and said second gate structure.

US Pat. No. 10,559,499

SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an image processing portion comprising a correction circuit,
wherein the correction circuit comprises a programmable logic device,
wherein the programmable logic device is configured to be reconfigured so as to be capable of executing first gamma correction by input of first configuration data,
wherein the programmable logic device is configured to be reconfigured so as to be capable of executing second gamma correction by input of second configuration data,
wherein the first gamma correction is performed by a first method and the second gamma correction is performed by a second method,
wherein the first method is table approximation, and
wherein the second method is polygonal line approximation.

US Pat. No. 10,559,498

LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE

INTERNATIONAL BUSINESS MA...

1. A system for completing of annealing metal interconnect overburden layers on semiconductor devices being fabricated on a chip on a semiconductor wafer, comprising:a scanning electron microscope (SEM) equipped with an electron backscatter diffraction (EBSD) capability;
a laser;
a processor; and
a memory, the memory storing instructions to cause the processor to perform:
on a wafer having a metal interconnect overburden layer initially partially annealed, detecting and determining an orientation of early recrystallizing grains at specific locations on a top surface of the metal overburden layer, as implemented and controlled by the processor, using data from the SEM equipped with the EBSD capability;
determining whether the orientations of the early recrystallizing grains at the specific locations is desirable or undesirable, as executed by the processor; and
selectively performing a laser anneal of the metal interconnect overburden layer, as implemented and controlled by the processor, using the laser, in a manner that selectively promotes or inhibits grain orientations from growing at selective locations on the metal interconnect overburden layer.

US Pat. No. 10,559,494

MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION

Tessera, Inc., San Jose,...

1. A microelectronic unit, comprising:a carrier structure having a front surface, a rear surface opposite the front surface, and a recess having edge surfaces extending below the front surface of the carrier structure;
a microelectronic element having contacts at a top surface thereof, the microelectronic element having edge surfaces adjacent the edge surfaces of the recess;
terminals electrically connected with the contacts of the microelectronic element;
a dielectric region extending between the edge surfaces of the recess and the edge surfaces of the microelectronic element; and
a conductive via extending through the dielectric region between one of the edge surfaces of the recess and one of the edge surfaces of the microelectronic element to the rear surface of the carrier structure, the conductive via being electrically connected with a respective one of the terminals and a respective one of the contacts of the microelectronic element.

US Pat. No. 10,559,487

WAFER DIVIDING METHOD AND DIVIDING APPARATUS

DISCO CORPORATION, Tokyo...

1. A wafer dividing method using a dividing apparatus, the dividing apparatus including a table adapted to suction hold a wafer through a heat-shrinkable tape of a work set, the work set having the tape attached to a ring frame to close an opening of the ring frame, the wafer being formed with division starting points along division lines and attached to the tape at the opening; a ring frame holding section adapted to hold the ring frame of the work set; a lifting unit adapted to relatively move the table and the ring frame holding section in a vertical direction for bringing them closer to and away from each other; and a heater adapted to heat the tape in a ring shape between an outer periphery of the wafer and an inner periphery of the ring frame of the work set, the table and the ring frame holding section being relatively moved respectively in an upward direction and a downward direction such as to be spaced away from each other by the lifting unit, in a state in which the work set is held by the ring frame holding section, to expand the tape at the opening and thereby to divide the wafer at the division starting points into chips, the water dividing method comprising:a holding step of holding the work set by the ring frame holding section;
a dividing step of relatively moving the table and the ring frame holding section away from each other by the lifting unit to expand the tape, and dividing the wafer at the division starting points to form a predetermined gap between the adjacent chips, after the holding step;
a tape holding step of suction holding that area of the expanded tape to which the wafer is adhered by the table, after the dividing step;
a ring tape expanding step of relatively moving the table and the ring frame holding section further away from each other, to expand the ring-shaped tape between the outer periphery of the wafer and the inner periphery of the ring frame, after the tape holding step; and
a fixing step of relatively moving the table and the ring frame holding section closer to each other by the lifting unit to slacken the ring-shaped tape and heating the ring-shaped tape by the heater, to heat shrink the ring-shaped tape and to fix the work set while maintaining the predetermined gap between the adjacent chips, after the ring tape expanding step.

US Pat. No. 10,559,483

PLATFORM ARCHITECTURE TO IMPROVE SYSTEM PRODUCTIVITY

LAM RESEARCH CORPORATION,...

1. A loading station for a substrate processing system, the loading station having a vertically-stacked configuration and comprising:a first loading station, the first loading station comprising
a first airlock volume, and
a first valve and a second valve arranged at respective ends of the first loading station, wherein the first valve and the second valve are configured to selectively provide access to the first airlock volume, wherein the first valve and the second valve include a first actuator and a second actuator, respectively, configured to open and close the first valve and the second valve, and wherein the first actuator and the second actuator extend downward from the first loading station; and
a second loading station arranged above and adjacent to the first loading station, the second loading station comprising
a second airlock volume, and
a third valve and a fourth valve arranged at respective ends of the second loading station, wherein the third valve and the fourth valve are configured to selectively provide access to the second airlock volume, wherein the third valve and the fourth valve include a third actuator and a fourth actuator, respectively, configured to open and close the third valve and the fourth valve,
a third loading station arranged above and adjacent to the second loading station, the third loading station comprising
a third airlock volume, and
a fifth valve and a sixth valve arranged at respective ends of the third loading station, wherein the fifth valve and the sixth valve are configured to selectively provide access to the third airlock volume, wherein the fifth valve and the sixth valve include a fifth actuator and a sixth actuator, respectively, configured to open and close the fifth valve and the sixth valve,
wherein a length of the first loading station is less than a length of the second loading station, wherein the length of the first loading station corresponds to a horizontal distance between ends of the first loading station and the length of the second loading station corresponds to a horizontal distance between ends of the second loading station, and wherein the third actuator and the fourth actuator each extend downward from the second loading station to overlap a horizontal plane defined by the first loading station.

US Pat. No. 10,559,478

METHOD FOR MANUFACTURING ELECTRONIC DEVICE AND ELECTRONIC DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A manufacturing method for an electronic device comprising:a step of placing a substrate, which has a metal plate on a back-surface side, on a back-surface-side mold having a mold recessed part;
a step of placing an insertion part for inserting a fastening member on a front surface of the substrate and peripherally inside the mold recessed part;
a step of placing a front-surface-side mold on the back-surface-side mold so as to cover the substrate; and
a step of pouring resin by potting between the front-surface mold and the back-surface-side mold, while the substrate is pressed against the back-surface-side mold,
wherein the metal plate is pressed against the back-surface-side mold by pressing a top part of the insertion part and circumferential part, peripherally outside the insertion part, of the metal plate is in contact with an edge of the mold recessed part, when the substrate is pressed against the back-surface-side mold in the step of pouring resin,
wherein the metal plate has a central metal body part surrounded by a peripheral metal thinned part surrounding the metal body part and which is thinner than the metal body part,
wherein the metal thinned part is located outward of circumference of the mold recessed part and the metal body part is in contact with an edge of the circumference of the mold recessed part, when the metal plate is pressed against the back-surface-side mold in the step of pouring resin.

US Pat. No. 10,559,476

METHOD AND STRUCTURE FOR A 3D WIRE BLOCK

1. A method for forming an electrical interconnect mechanism, the steps comprising:depositing metal to form a plane having a programmed shape through a process that adds material rather than removes it to form a metal plane by a 3D forming;
extending wires of programmed geometries from said formed metal plane and extending said wires to programmed locations in three dimensional space, and
adding a dielectric to fill on top of said metal plane encompassing all of said metal wires and curing said dielectric to form one or more substrates, removing said metal plane from said one or more substrates by a secondary process thereby producing a finished block having separate isolated paths that provides one or more electrical connections to different spots on said one or more substrates.

US Pat. No. 10,559,469

DUAL POCKET APPROACH IN PFETS WITH EMBEDDED SI-GE SOURCE/DRAIN

TEXAS INSTRUMENTS INCORPO...

1. A p-type metal-oxide-semiconductor field effect transistor (PFET), comprising:a p-type silicon substrate;
an n-type well formed in the p-type silicon substrate;
a p-type source formed in the n-type well;
a p-type drain formed in the n-type well;
dual pockets formed in the n-type well laterally between the source and drain, the dual pockets comprising a first pocket with first arsenic n-type dopants and a second pocket with second arsenic n-type dopants;
a first p-type lightly-doped drain (LDD) coupled to the source and on the first and second pockets;
a second p-type LDD coupled to the drain and on the first and second pockets, wherein the first pocket is directly below the first LDD and the second LDD, the second pocket is below the first pocket, the first pocket has a higher arsenic n-type doping concentration than the second pocket, and both the first pocket and the second pocket have a higher n-type doping concentration than the n-type well;
a gate oxide layer formed on the n-type well; and
a gate formed on the gate oxide layer.

US Pat. No. 10,559,462

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Kokusai Electric Corporat...

1. A method of manufacturing a semiconductor device, comprising:forming a film containing at least Si, O and N on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing:
forming a first layer by supplying a precursor gas containing at least a Si—N bond and a Si—Cl bond and a first catalyst gas to the substrate;
exhausting the precursor gas and the first catalyst gas in the process chamber through an exhaust system;
forming a second layer by supplying an oxidizing gas and a second catalyst gas to the substrate to modify the first layer; and
exhausting the oxidizing gas and the second catalyst gas in the process chamber through the exhaust system.

US Pat. No. 10,559,453

TECHNIQUES FOR DETECTING MICRO-ARCING OCCURRING INSIDE A SEMICONDUCTOR PROCESSING CHAMBER

Taiwan Semiconductor Manu...

1. A system for determining micro-arcing in a chamber comprising:a magnetic-field sensor comprising a closed conductive path, wherein the magnetic-field sensor is configured to generate a magnetic-field signal that varies in time commensurate with a time-varying magnetic flux passing through the closed conductive path;
a micro-arc detecting element configured to determine whether a micro-arc has occurred in the chamber based on a magnitude of the magnetic-field signal;
a radio frequency (RF) generator configured to output a RF signal;
a transmission line coupled to the RF generator; and
wherein the transmission line has a central portion that extends laterally along a first plane, and a pair of peripheral portions that extend laterally from the central portion in parallel with a second plane.

US Pat. No. 10,559,451

APPARATUS WITH CONCENTRIC PUMPING FOR MULTIPLE PRESSURE REGIMES

Applied Materials, Inc., ...

10. A processing chamber comprising:a chamber body defining a processing region and configured to generate a plasma therein;
a substrate support assembly disposed in the process region; and
an exhaust module comprising:
a body coupled to the chamber body, the body having a first vacuum pump opening and a second vacuum pump opening formed therethrough;
a pumping ring positioned in the body over both the second vacuum pump opening and the vacuum pump opening, the pumping ring comprising:
a substantially ring shaped body, comprising:
a top surface and a bottom surface, the top surface having one or more through holes formed therein, wherein the one or more through holes are arranged in a pattern concentric with the first vacuum pump opening and the bottom surface having a fluid passage formed therein fluidly isolated from the first vacuum pump opening, the fluid passage interconnecting each of the one or more through holes to the second vacuum pump opening; and
an opening formed in the substantially ring shaped body, the opening substantially aligned with the first vacuum pump opening; and
a symmetric flow valve positioned in the body over the pumping ring, the symmetric flow valve movable between a raised position allowing for passage through the opening of the substantially ring shaped body and into the vacuum pump opening and a lowered position substantially sealing the opening of the substantially ring shaped body without sealing the one or more through holes.

US Pat. No. 10,559,440

SWITCH MECHANISM FOR A VEHICLE INTERIOR COMPONENT

Shanghai Yanfeng Jinqiao ...

1. A switch mechanism for a vehicle interior component comprising:(a) a carrier;
(b) a slide configured to slide within the carrier;
(c) at least one pin configured to move within the slide to center the slide in the carrier; and
(d) a spring configured to move the at least one pin within the slide;
wherein the at least one pin comprises a feature configured to guide movement of the at least one pin relative to the slide;
wherein the feature comprises a protrusion configured to move against the slide to guide movement of the at least one pin relative to the slide;
wherein the slide comprises a rib;
wherein the protrusion is configured to slide against the rib to guide movement of the at least one pin relative to the slide;
wherein the carrier comprises a surface;
wherein the at least one pin is configured to slide against the surface of the carrier;
wherein the rib extends from the slide away from the surface of the carrier.

US Pat. No. 10,559,434

CONTROL CIRCUIT FOR ELECTRIC LEAKAGE CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A control circuit for an electric leakage circuit breaker, comprising:a zero phase current transformer configured to detect a zero phase current on a circuit as a leakage detection signal;
a filter circuit section configured to remove a high frequency noise included in the leakage detection signal;
an input amplifier configured to amplify a voltage formed by a current of the leakage detection signal and an impedance of the filter circuit section, and including a pair of transistors, bases of the transistors connected to both output terminals of the filter circuit section, respectively;
a base current generator commonly connected to the bases of the pair of transistors and configured to supply the same amount of base current to the pair of transistors;
a trip determination circuit section configured to determine whether to output a trip control signal by comparing a voltage value of an amplified leakage detection signal outputted from the input amplifier with a preset reference voltage value, and
a gain adjuster, connected to the base current generator, configured to adjust the gain of a collector current of the pair of transistors over the base current by adjusting the base current supplied to the bases of the pair of transistors.

US Pat. No. 10,559,430

POWER STORAGE MODULE

AutoNetworks Technologies...

1. An electricity storage module comprising:an electricity storage element group composed of a plurality of electricity storage elements having exhaust ports that discharge gas produced therein, each of the exhaust ports having a constant diameter so as to be continuously open; and
a cover attached to the electricity storage element group,
wherein the electricity storage element group has exhaust surfaces on which the exhaust ports are arranged, and the cover is attached so as to cover the exhaust surfaces,
guide portions that surround the exhaust ports in the form of loops are respectively formed integrally on the exhaust surfaces of the plurality of electricity storage elements,
guided portions that come into close contact with the guide portions are formed integrally on an opposing surface of the cover that opposes the exhaust surfaces, and
the cover is provided with a duct that communicates with the exhaust ports and through which gas discharged from the exhaust ports passes.

US Pat. No. 10,559,428

MULTILAYER CERAMIC ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and internal electrodes stacked to be alternately exposed to a first end surface and a second end surface of the ceramic body with respective dielectric layers interposed therebetween; and
external electrodes disposed on external surfaces of the ceramic body,
wherein the external electrodes include seed layers disposed on at least one surface of the ceramic body in a thickness direction, first electrode layers electrically connected to the internal electrodes and the seed layers, and plating layers disposed on the seed layers and the first electrode layers, respectively,
0.8?T2/T1?1.2, where T1 is a thickness of each of the first electrode layers in a central region of the ceramic body in the thickness direction, and T2 is a thickness of each of the first electrode layers at a point at which an outermost internal electrode, among the internal electrodes, is positioned, and
the first electrode layers are connected to the seed layers in contact portions between the at least one surface of the ceramic body in the thickness direction and the at least one surface of the ceramic body in a length direction,
wherein the first electrode layers and the seed layers directly contact each other without a gap.

US Pat. No. 10,559,423

MULTILAYER CERAMIC ELECTRONIC DEVICE

TDK CORPORATION, Tokyo (...

7. A multilayer ceramic electronic device comprising a laminated body having alternately laminated internal electrode layers and dielectric layers, whereineach of the dielectric layers has a thickness of 0.5 ?m or less,
each of the internal electrode layers contains ceramic particles,
a content ratio of the ceramic particles contained in the each of the internal electrode layers is 2 to 15% by representation of cross sectional area, and
the each of the dielectric layers has a thickness standard deviation (?) of 100 nm or less.

US Pat. No. 10,559,409

PROCESS FOR MANUFACTURING A LEADLESS FEEDTHROUGH FOR AN ACTIVE IMPLANTABLE MEDICAL DEVICE

Greatbatch Ltd., Clarenc...

1. A method for manufacturing a feedthrough that is configured for incorporation into an active implantable medical device (AIMD), the method comprising the steps of:a) forming a first sintered ceramic reinforced metal composite (CRMC) paste, comprising the steps of:
i) mixing platinum with a first ceramic material to form a first CRMC material;
ii) subjecting the first CRMC material to a first sintering step to thereby form a first sintered CRMC material;
iii) ball-milling or grinding the first sintered CRMC material to form a first powdered sintered CRMC material; and
iv) mixing the first powdered sintered CRMC material with a solvent to form the first sintered CRMC paste;
b) forming a green-state ceramic body, comprising the steps of:
i) forming a ceramic body in a green state, the green-state ceramic body having a ceramic body body fluid side opposite a ceramic body device side, wherein, when the feedthrough is attached to a housing for the AIMD, the ceramic body fluid side resides outside the AIMD and the ceramic body device side resides inside the AIMD;
ii) forming at least one first via hole comprising a first via hole inner surface extending along a longitudinal axis through the green-state ceramic body to the body fluid and device sides;
iii) filling the at least one first via hole in the green-state ceramic body with the first sintered CRMC paste extending to a first sintered CRMC paste first end residing at or adjacent to the ceramic body fluid side and a first sintered CRMC paste second end residing at or adjacent to the ceramic body device side;
iv) drying the green-state ceramic body including the first sintered CRMC paste to thereby form a second CRMC material filling the at least one first via hole in the ceramic body;
v) forming a second via hole extending through the second CRMC material to the ceramic body fluid and device sides so that an inner surface of the second CRMC material is spaced closer to the longitudinal axis than the first via hole inner surface;
vi) providing a substantially pure metal core in the second via hole; and
vii) subjecting the green-state ceramic body including the second CRMC material and the substantially pure metal core to a second sintering step to thereby form a sintered ceramic body comprising the second CRMC material surrounding the substantially pure metal core; and
c) providing an electrically conductive ferrule comprising a ferrule opening; and
d) hermetically sealing the sintered ceramic body to the ferrule in the ferrule opening.

US Pat. No. 10,559,400

FLEX FLAT CABLE STRUCTURE AND FIXING STRUCTURE OF CABLE CONNECTOR AND FLEX FLAT CABLE

ENERGY FULL ELECTRONICS C...

1. A flex flat cable (FFC) electrical connector fix structure, comprising:an electrical connector, comprising:
a housing;
a spacer, assembled onto the housing, and comprising a plurality of containing recesses;
a printed circuit board (PCB), comprising a plurality of conductive portions and a plurality of connecting portions, and the plurality of conductive portions being electrically connected to the plurality of corresponding connecting portions respectively;
a plurality of terminals, one end of the plurality of terminals passing through the containing recess and being connected to the plurality of connecting portions; and
a shell, assembled onto the housing; and
an FFC structure, comprising:
a plurality of metallic transmission lines, being arranged parallel, and comprising one or more power line and a plurality of signal lines; the power line being configured to transmit power; the plurality of signal lines being configured to transmit a data signal;
a plurality of first insulating jackets, each of the plurality of first insulating jackets enclosing one of the plurality of metallic transmission lines;
a second insulating jacket, surrounding the plurality of first insulating jackets;
a third insulating jacket, enclosing the plurality of first insulating jackets without any gap, and the second insulating jacket enclosing the third insulating jacket; and
a shield layer, configured to isolate the second insulating jacket from the third insulating jacket, comprising:
an insulating film, comprising a first side and a second side, and the first side and the second side being on opposite sides of the insulating film;
a first block layer, adhering to the first side of the insulating film; and
a second block layer, adhering to and contacting the first block layer,
wherein the first block layer and the second block layer are made of different materials,
wherein all of the plurality of metallic transmission wires are respectively connected to all of the plurality of conductive portions on one surface of the PCB,
wherein the printed circuit board is between the FFC structure and the spacer.

US Pat. No. 10,559,391

IRRADIATION TARGET PROCESSING SYSTEM

FRAMATOME GMBH, Erlangen...

1. An irradiation target processing system for insertion and retrieving irradiation targets into and from an instrumentation tube in a nuclear reactor core, the system comprising:a target retrieving system comprising a target exit port configured to be coupled to a target storage container and an exhaust system;
a target insertion system comprising a target filling device, a target retention tubing, a target diverter coupled to the target filling device, the target retention tubing and the target retrieving system, and a target supply junction at the target retention tubing, wherein the target supply junction is configured to be connected to the instrumentation tube; and
a transport gas supply system comprising a first gas supply tubing, a second gas supply tubing, and a transport gas supply junction coupled to the first and second gas supply tubing, wherein the first gas supply tubing is coupled to the exit port of the target retrieving system, and the second gas supply tubing is configured to be coupled to a junction for supplying gas to the instrumentation tube; and
wherein the target retrieving system, the target insertion system, and the transport gas supply system are mounted on a movable support.

US Pat. No. 10,559,383

EMPLOYEE VISIT VERIFICATION SYSTEM

1. A visit verification (VV) system for verifying visits by a Mobile Service Provider (MSP) to a residence of a client comprising:a. a beacon having:
i. a transmitter configured for transmitting a signal;
ii. a visual code;
b. a mobile computing device (MCD) having:
i. an optical device configured for reading the visual code on the beacon;
ii. a receiver capable of receiving the signal from the beacon,
iii. a controller configured for determining the distance from the beacon based upon the received signal;
iv. a communication device configured for communicating information from the MCD;
c. a server comprising:
i. a network adapter configured for receiving information from the MCD,
ii. a memory configured for storing information;
iii. an input/output (I/O) device configured for providing output to, and receiving input from a user;
iv. a controller connected to the network adapter, the memory, the I/O device, configured to:
1. authenticate an MSP;
2. determine when the MSP is outside of an acceptable perimeter:
3. store task status information from the MCD.

US Pat. No. 10,559,382

EMPLOYEE VISIT VERIFICATION SYSTEM

1. A visit verification (VV) system for verifying visits by a Mobile Service Provider (MSP) to a residence of a client comprising:a. a beacon having:
i. an RF transmitter configured for transmitting an RF signal;
ii. a visual code;
b. a mobile computing device (MCD) having:
i. an optical device configured for reading the visual code on the beacon;
ii. a receiver capable of receiving the signal from the beacon,
iii. a controller running executable code configured for determining:
1. if the visual code matches a prestored code indicating that this is the proper beacon;
2. the distance from the beacon to the MCD based upon the received signal;
iv. a direct communication link configured for communicating information from the MCD to another local computing device;
c. a server, being a computing device, configured for receiving information periodically from the MCD relating to at least one of login information, RSSI, distance from beacon, longitude, latitude, tasks completed, task status through a manual, direct connection, storing and providing information being at least one of a task schedule, client to visit, beacon UUIDs, addresses, residence locations to the MCD.

US Pat. No. 10,559,367

REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES

Micron Technology, Inc., ...

1. A method comprising:precharging channel material of strings of memory cells in both a selected sub-block and an unselected sub-block in a block of memory cells to a precharge voltage during a first portion of a programming operation; and
after precharging the channel material of the strings of memory cells in the selected sub-block and the unselected sub-block, applying a programming voltage to an access line of a selected memory cell in the selected sub-block of the block of memory cells during a second portion of the programing operation,
wherein the selected memory cell in the selected sub-block and an unselected memory cell in the unselected sub-block are coupled to the access line, and
wherein during the second portion of the programing operation, the channel material in the unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on the selected access line of the selected memory cell in the selected sub-block.

US Pat. No. 10,559,362

NON-VOLATILE MEMORY DEVICE AND A READ METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A non-volatile memory device, comprising:a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and
a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

US Pat. No. 10,559,353

WEIGHT STORAGE USING MEMORY DEVICE

Micron Technology, Inc., ...

1. A device, comprising:a plurality of digit lines;
a plurality of word lines;
a neural memory unit comprising a plurality of memory cells coupled with the plurality of digit lines and the plurality of word lines, the neural memory unit configured to store an analog value, the neural memory unit comprising: a primary memory cell configured to receive a programming pulse during a write operation of the neural memory unit; and
a plurality of secondary memory cells configured to be thermally coupled with the primary memory cell during the write operation, each secondary memory cell being thermally coupled with the primary memory cell according to a thermal relationship, wherein the analog value stored in the neural memory unit is based at least in part on each thermal relationship between the plurality of secondary memory cells and the primary cell.

US Pat. No. 10,559,349

POLARIZATION GATE STACK SRAM

Intel Corporation, Santa...

1. An apparatus comprising:a first inverter comprising a first pull up transistor and a first pull down transistor;
a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor;
a first access transistor coupled to the first inverter; and
a second access transistor coupled to the second inverter, a gate stack of one transistor of each inverter comprising a polarization layer between and in contact with a gate oxide and a respective channel of each transistor that comprises the polarization layer.

US Pat. No. 10,559,348

SYSTEM, APPARATUS AND METHOD FOR SIMULTANEOUS READ AND PRECHARGE OF A MEMORY

Intel Corporation, Santa...

1. An apparatus comprising:a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells; and
a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells, the sense amplifier circuit including:
a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit, the first and second internal nodes separate from a first bitline coupled to the memory cell; and
an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array.

US Pat. No. 10,559,345

ADDRESS DECODING CIRCUIT PERFORMING A MULTI-BIT SHIFT OPERATION IN A SINGLE CLOCK CYCLE

Amazon Technologies, Inc....

1. An address decoder within an Integrated Circuit (IC) to access an address space, comprising:shifting hardware for receiving a constant first input and a second input associated with a window size of an address region within the address space, the shifting hardware configured to perform a multi-bit shift operation on the constant in one clock cycle to generate a mask signal on mask signal lines, wherein the multi-bit shift operation is configured to shift a number of bit positions in the one clock cycle based on the second input associated with the window size of the address region;
XOR-based logic having a first input coupled to receive a base address of the address region and a second input coupled to receive a transaction address within the address region;
combinatorial logic coupled to the mask signal lines and coupled to an output of the XOR-based logic, wherein an output of the combinatorial logic is configured as an indicator that identifies if the transaction address is within the address region of the address space.

US Pat. No. 10,559,342

DYNAMIC RANDOM ACCESS MEMORY WITH REDUCED POWER CONSUMPTION

Windbond Electronics Corp...

1. A dynamic random access memory, comprising:a temperature sensor, sensing an operating temperature of the dynamic random access memory;
a dynamic memory cell array;
a control circuit, coupled to the dynamic memory cell array, and accessing and managing the dynamic memory cell array;
a plurality of power supply circuits, supplying power to the dynamic memory cell array and the control circuit; and
a power control circuit, controlling power outputs of the power supply circuits,
wherein when the dynamic random access memory enters a self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the dynamic random access memory,
wherein in case that the dynamic random access memory is in the self-refresh mode, when the operating temperature of the dynamic random access memory is higher than a threshold temperature, the power control circuit is operated in the normal power control state, and when the operating temperature of the dynamic random access memory is lower than the threshold temperature, the power control circuit is operated in the low power control state.

US Pat. No. 10,559,335

METHOD OF TRAINING DRIVE STRENGTH, ODT OF MEMORY DEVICE, COMPUTING SYSTEM PERFORMING THE SAME AND SYSTEM-ON-CHIP PERFORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of training for a memory device, the method comprising:performing an initialization operation on the memory device based on the memory device being powered on;
performing a training operation on a plurality of operating frequencies of the memory device to obtain, as a configurable operating parameter for each of the plurality of operating frequencies, at least one of a plurality of operating parameters of the memory device;
storing, as training data, the obtained configurable operating parameter for each of the plurality of operating frequencies; and
using an optimized operating parameter for the memory device based on the training data, a current operation mode of the memory device, and a current operating frequency of the memory device.

US Pat. No. 10,559,312

USER AUTHENTICATION USING AUDIOVISUAL SYNCHRONY DETECTION

International Business Ma...

1. A method for preventing a replay attack, comprising:receiving, at a first time, first video and first audio signals generated in response to a user uttering a passphrase;
receiving, at a second time subsequent to the first time, second video and second audio signals generated respectively by a camera and a microphone in response the user uttering the passphrase;
extracting, from the received audio signals, speech-based features;
extracting, from the received video signals, visual-based features;
computing, by a processor, an audio temporal alignment between the first and the second audio signals, by computing a dynamic time warping on the audio-based features extracted from the first and second audio signals, the audio temporal alignment comprising a first registration that synchronizes the first and the second audio signals;
computing, by the processor, a video temporal alignment between the first and the second video signals, by computing a dynamic time warping on the video-based features extracted from the first and second video signals, the video temporal alignment comprising a second registration that synchronizes the first and the second video signals;
comparing the audio temporal alignment between the first and the second audio signals to the video temporal alignment between the first and the second video signals; and
successfully authenticating the user upon detecting, as a result of the comparing, that the audio and the video temporal alignments are synchronized; and
failing the authentication of the user upon detecting, as a result of the comparison, that the audio and the video temporal alignments are not synchronized.

US Pat. No. 10,559,303

METHODS AND APPARATUS FOR REDUCING LATENCY IN SPEECH RECOGNITION APPLICATIONS

Nuance Communications, In...

1. A computing device including a speech-enabled application installed thereon, the computing device comprising:an input interface, which receives audio comprising speech from a user of the computing device;
an automatic speech recognition (ASR) engine, which:
detects an end of speech in a first audio portion of the received audio, and
generates a first ASR result based, at least in part, on the first audio portion; and
at least one processor programmed to:
determine whether a valid action can be performed by the speech-enabled application using the first ASR result; and
instruct the ASR engine to process a second audio portion of the received audio, recorded after the detected end of speech of the first audio portion, when it is determined that a valid action cannot be performed by the speech-enabled application using the first ASR result,
wherein the ASR engine processes the second audio portion in addition to the first audio portion when instructed by the at least one processor.

US Pat. No. 10,559,298

DISCUSSION MODEL GENERATION SYSTEM AND METHOD

International Business Ma...

1. A computer-implemented method comprising:receiving, at a computing device, an input text;
tagging one or more portions of the input text, wherein tagging the one or more portions of the input text includes tagging the one or more portions of the input text with one or more sentiment metrics based upon, at least in part, performing sentiment analysis on the one or more portions of the input text;
generating a discussion model between a plurality of virtual speakers based upon, at least in part, the tagging of the one or more portions of the input text; and
presenting the discussion model.

US Pat. No. 10,559,296

AUTOMATED SPEECH PRONUNCIATION ATTRIBUTION

Google LLC, Mountain Vie...

1. A computer-implemented method comprising:receiving, by a digital assistant device that stores multiple user profiles that are each associated with a respective one of multiple users, a voice command of a particular one of the multiple users, wherein the voice command includes a particular term that, among the multiple users, is pronounced uniquely by the particular one of the multiple users, and wherein each user profile stored by the digital assistant device specifies pronunciation data for terms that the respective user pronounces uniquely;
matching the voice command to a particular user profile among the multiple stored user profiles that are stored by the digital assistant;
generating, by the digital assistant device, an acknowledgment of the voice command, wherein the acknowledgement includes the particular term and pronunciation data that was stored in the matched, particular user profile and that reflects the unique pronunciation of the particular term by the particular one of the multiple users; and
providing, for output by a speech synthesizer of the digital assistant device, a spoken representation of the acknowledgment, wherein the spoken representation of the acknowledgement of the voice command includes the particular term as uniquely pronounced by the particular one of the multiple users.

US Pat. No. 10,559,291

ARRANGEMENTS AND METHODS FOR GENERATING NATURAL DIRECTIONAL PINNA CUES

Harman Becker Automative ...

1. A headphone arrangement that is configured to induce natural directional pinna cues, the arrangement comprising:at least one ear cup comprising a frame that is configured to be arranged to at least partly encircle an ear of a user, thereby defining an open volume around the ear of the user, wherein the frame is at least partially hollow, thereby providing at least one cavity on its inside that is separated from an outside by at least one wall of the frame;
at least one loudspeaker arranged within a wall of at least one of a frontal part, a rear part, an upper part, and a lower part of the frame of the ear cup, wherein the at least one loudspeaker comprises a membrane and wherein a first side of the membrane faces a cavity inside the frame and a second side of the membrane faces the outside and wherein, when the at least one ear cup is arranged to encircle the ear of the user, at least one of the at least one loudspeaker is arranged at a first angle (?, ?) with respect to a median plane such that at least one of:
its main direction of sound propagation is directed away from the median plane; and
the second side of the membrane is directed away from the median plane; wherein
the median plane crosses a user's head midway between the user's ears, thereby virtually dividing the head into an essentially mirror-symmetrical left half side and right half side,
a horizontal plane virtually divides the frame of the ear cup into an upper and a lower part,
a frontal plane virtually divides the frame of the ear cup into a frontal part and a rear part,
the frontal plane is perpendicular to the horizontal plane,
the frontal plane and the horizontal plane intersect along a first axis (x), and
the first axis (x) is perpendicular to the median plane and runs through a concha of the user when the at least one ear cup is arranged to encircle the ear of the user.

US Pat. No. 10,559,288

STEEL DRUM WITH GREATER RANGE OF NOTES

1. A steel drum for playing soprano music, comprising:a. a single circular steel drum having a concave surface with notes placed in the order of 4ths and 5ths, with an associated steel skirt extending downward from a rim; and
b. a stand associated with the steel drum, said steel drum suspended from the stand by at least two non-rigid attachments;
c. the single circular steel drum comprising at least 14 note areas adjacent to and around the rim on the concave surface wherein the at least 14 note areas consist of at least twelve root notes and two octaves C and C? adjacent said root notes, and a plurality of other note areas distributed over the concave surface below the rim, with at least two octaves available for each root note.

US Pat. No. 10,559,284

VEHICLE INFORMATION DISPLAY CONTROL DEVICE, AND METHOD FOR DISPLAYING AUTOMATIC DRIVING INFORMATION

MITSUBISHI ELECTRIC CORPO...

1. A vehicle information display control device, comprising:a memory to store a program and a processor to execute the program to perform the method of:
defining a first image and a second image for each of the actuators, the first image representing a manual control mode, the second image representing an automatic control mode;
obtaining automatic driving information including information indicating whether each of actuators of a vehicle is in the manual control mode or the automatic control mode; and
causing a display to simultaneously display the first image and the second image of each of the actuators and to display, based on the automatic driving information, (i) the first image of an actuator in the manual control mode closer in position to a driver of the vehicle than the second image of the actuator in the manual control mode and (ii) the second image of an actuator in the automatic control mode closer in position to the driver of the vehicle than the first image of the actuator in the automatic control mode.

US Pat. No. 10,559,275

INFERRING BATTERY STATUS OF AN ELECTRONIC DEVICE IN A WIRELESS POWER DELIVERY ENVIRONMENT

Ossia Inc., Bellevue, WA...

1. A wireless power receiver comprising:one or more radio frequency (RF) transceivers;
a client battery;
control circuitry adapted to:
receive, at the one or more RF transceivers, wireless RF energy from a wireless power transmission system;
process and store the wireless RF energy in the client battery; and
provide the stored power to a primary battery of an electronic device; and
a detection and monitoring apparatus adapted to:
monitor power usage characteristics including current or voltage provided to the primary battery; and
infer a status of the primary battery of the electronic device based, at least in part, on the power usage characteristics without battery status feedback from the electronic device.

US Pat. No. 10,559,274

MULTIPLEXER AND METHOD FOR DRIVING THE SAME

AU OPTRONICS CORPORATION,...

1. A multiplexer, comprising:a plurality of first driving units, each of the first driving units comprising:
a first data voltage input terminal, for receiving a first pixel voltage signal;
a first capacitor, comprising:
a first terminal, for receiving a first switch signal; and
a second terminal;
a first transistor, comprising:
a first terminal, coupled to the second terminal of the first capacitor;
a second terminal, for receiving a first reset signal; and
a control terminal, for receiving a second switch signal;
wherein the first switch signal and the second switch signal have opposite phases; and
a second transistor, comprising:
a first terminal, coupled to the first data voltage input terminal;
a second terminal, coupled to a first data line; and
a control terminal, coupled to the second terminal of the first capacitor; and
a plurality of second driving units, each of the second driving units comprising:
a second data voltage input terminal, for receiving a second pixel voltage signal, wherein the first pixel voltage signal and the second pixel voltage signal have opposite polarities;
a second capacitor, comprising:
a first terminal, coupled to the first terminal of the first capacitor, and is for receiving the first switch signal; and
a second terminal;
a third transistor, comprising:
a first terminal, coupled to the second terminal of the second capacitor;
a second terminal, for receiving a second reset signal; and
a control terminal, coupled to the control terminal of the first transistor, for receiving the second switch signal; and
a fourth transistor, comprising:
a first terminal, coupled to the second data voltage input terminal;
a second terminal, coupled to a second data line; and
a control terminal, coupled to the second terminal of the second capacitor;
wherein the first reset signal is different from the second reset signal.

US Pat. No. 10,559,253

DISPLAY PANEL AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A display panel, comprising:a display region having a first edge;
a non-display region surrounding the display region;
a plurality of display pixels including a first and second plurality of display pixels, in the display region;
a plurality of signal lines for transmitting driving signals to the plurality of display pixels;
a plurality of first compensation lines in the non-display region; and
a potential line in the non-display region for providing a fixed potential;
wherein:
the plurality of signal lines and the first edge of the display region extend along a first direction;
the first edge recesses toward an inside of the display region to form a notch;
the display region includes a first display region and a second display region separated by the notch along the first direction;
the plurality of signal lines includes first signal lines for transmitting the driving signals to the first plurality of display pixels in the first display region and second signal lines for transmitting the driving signals to the second plurality of display pixels in the second display region;
the first signal lines are not electrically connected to the second signal lines;
the plurality of first compensation lines is electrically connected to the first signal lines;
the potential line and the plurality of first compensation lines are disposed in different metal layers respectively; and
each of the plurality of first compensation lines at least partially overlaps with the potential line to form a compensation capacitor.

US Pat. No. 10,559,252

DISPLAY APPARATUS

Sakai Display Products Co...

1. A display apparatus comprising:a display panel comprising a plurality of display elements arranged in a matrix form on a substrate having flexibility;
a supporting member having a surface, the substrate of the display panel being placed on the surface; and
a holding member provided at a part of or the entire of an outer edge of the display panel along the outer edge so as to rim the display panel, the holding member holding the display panel on the surface of the supporting member,
wherein the holding member engages with an outer periphery of the display panel,
the holding member is bonded to the surface of the supporting member,
the substrate closely contacts with the surface of the supporting member at a lower strength than a bonding strength between the holding member and the surface of the supporting member,
the holding member has a frame-like shape surrounding the display panel along the entire of the outer edge, and
the holding member comprises:
a through hole or a groove communicating with an inside of the frame-like shape in the holding member and communicating with an outside of the frame-like shape in the holding member; and
a closing member to prevent ventilation through the through hole or the groove.

US Pat. No. 10,559,249

DEVICE, TELEVISION SYSTEM, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

11. A device comprising:a decoder;
a driver circuit; and
a display portion comprising a first display panel and a second display panel,
wherein the decoder is configured to generate a signal corresponding to an image displayed on the display portion,
wherein the decoder is further configured to detect a change in an image in each of the first display panel and the second display panel, and determine whether or not image rewriting is necessary in each of the first display panel and the second display panel, and
wherein the decoder is further configured to perform the determination on the basis of a value of a motion vector of the image displayed on the first display panel and a prediction error of an inter-frame prediction of the image displayed on the first display panel.

US Pat. No. 10,559,221

PROCESSOR-IMPLEMENTED SYSTEMS AND METHODS FOR ENHANCING COGNITIVE ABILITIES BY PERSONALIZING COGNITIVE TRAINING REGIMENS

Akili Interactive Labs, I...

1. A processor-implemented method for enhancing cognitive abilities of a user by personalizing a cognitive training regimen through difficulty progression, the method comprising:performing, using one or more data processors, a cognitive assessment of a user using a set of assessment tasks;
estimating, using the one or more data processors, a maximal performance of the user related to the set of assessment tasks;
determining, using the one or more data processors, a performance range based at least in part on the maximal performance of the user;
dividing, using the one or more data processors, the performance range into a plurality of progress gates, the plurality of progress gates corresponding to a plurality of task difficulty levels that the user may perform to progress within the training regimen, data related to the performance range being stored in a data structure in a non-transitory machine-readable storage medium;
selecting, using the one or more data processors, a first progress gate within the performance range;
generating, using the one or more data processors, a first set of training tasks associated with the first progress gate;
collecting the user's first training responses to the first set of training tasks;
determining, using the one or more data processors, whether the user succeeds at the first progress gate based at least in part on the user's first training responses; and
in response to the user succeeding at the first progress gate,
selecting, using the one or more data processors, a second progress gate within the performance range;
generating, using the one or more data processors, a second set of training tasks associated with the second progress gate; and
collecting the user's second training responses to the second set of training tasks for determining whether the user succeeds at the second progress gate,
wherein (i) the plurality of task difficulty levels are within a range personalized for the user, and (ii) difficulties of the generated first and second sets of training tasks are within the personalized range of task difficulty levels.

US Pat. No. 10,559,218

METHOD AND DEVICE FOR CONTROLLING A SIMULATOR

1. A method for actuating a simulator for simulating translational and rotational movements of a vehicle, wherein, in relation to a three vehicle axes, a rotational rate about a first vehicle axis and specific forces respectively acting along a second vehicle axis and a third vehicle axis are provided from a movement model that simulates the vehicle and converted into translational and rotational control commands for actuating the simulator, comprising the following steps:calculating, using a control unit, a rotational angle from the rotational rate about the first vehicle axis,
calculating, using the control unit, from the specific forces, an apparent perpendicular angle between a vertical axis as the third vehicle axis and the apparent perpendicular arising on account of the specific forces acting along the second vehicle axis and third vehicle axis,
calculating, using the control unit, an apparent perpendicular angle difference between a rotational angle and the apparent perpendicular angle and ascertaining a high-frequency difference component of the apparent perpendicular angle difference that is intended to be compensated by a translational movement of the simulator, depending on the apparent perpendicular angle difference,
calculating, using the control unit, translational control commands for actuating the simulator for a translational movement of the simulator along the second vehicle axis, depending on the ascertained high-frequency rotational angle component of the apparent perpendicular angle difference,
calculating, using the control unit, a compensation angle that corresponds to an acceleration value to be simulated along the second vehicle axis by inclining the simulator in relation to perpendicular to the Earth, depending on the rotational angle, the high-frequency difference component of the apparent perpendicular angle difference and the apparent perpendicular angle,
calculating, using the control unit, a limited compensation angle from the compensation angle by means of a physiological rotational rate limitation, which restricts an inclination of the simulator below a perception threshold, and
calculating, using the control unit, rotation control commands for actuating the simulator for a rotational movement of the simulator about the first vehicle axis, depending on the limited compensation angle and the rotational angle.

US Pat. No. 10,559,208

SYSTEM AND METHOD FOR CONTROLLING REPORTING FREQUENCY

Caterpillar Paving Produc...

1. A method, comprising:receiving first location information, at a first reporting frequency, with a controller, the first location information being generated by a location sensor and indicating a first location of a paving system component;
determining that a distance between a second location of the paving system component and a first geofence is less than or equal to a distance threshold;
based at least in part on determining that the distance is less than or equal to the distance threshold, controlling the location sensor to provide second location information at the first reporting frequency;
receiving third location information, at the first reporting frequency, with the controller, the third location information being generated by the location sensor and indicating a third location of the paving system component;
determining, based at least in part on the third location information, that the third location of the paving system component is within the first geofence; and
based at least in part on determining that the third location is within the first geofence, controlling the location sensor to provide fourth location information at a second reporting frequency greater than the first reporting frequency.

US Pat. No. 10,559,201

USING CONNECTED VEHICLE DATA TO OPTIMIZE TRAFFIC SIGNAL TIMING PLANS

TRAFFIC TECHNOLOGY SERVIC...

1. A method comprising:provisioning a fleet of vehicles to enable the vehicles each to wirelessly transmit probe data in real time, the probe data including, for a given vehicle, a series of probe messages, each probe message including at least an identifier of the vehicle, a GPS location, and a timestamp;
receiving the transmitted probe data messages over a collection period of time and storing the probe data carried by the received messages;
processing the stored probe data to assemble vehicle usage data over at least one target time span for a selected electronic signal-controlled intersection, wherein the selected intersection has signal controls operating according to a corresponding signal timing plan; and
adjusting the signal timing plan of the intersection, based on the vehicle usage data, to improve selected objectives for the intersection.

US Pat. No. 10,559,198

SYSTEM AND METHOD OF ADAPTIVE CONTROLLING OF TRAFFIC USING ZONE BASED OCCUPANCY

Cubic Corporation, San D...

1. A device comprising:memory having computer-readable instructions stored therein; and
one or more processors configured to execute the computer-readable instructions to:
receive identification of zones and corresponding rules for a signalized roadway intersection, wherein a perimeter of at least one zone is based on user input at a graphical user interface of a traffic control system that is communicatively coupled to the device; and
for each identified zone:
receive traffic data from one or more sensors at the signalized roadway intersection;
detect a number of objects in the zone by performing one or more of image processing or video processing on the received traffic data;
based at least in part on the number of objects detected in the zone, determine if a corresponding condition is met; and
upon determining that the corresponding condition is met for the zone, send a corresponding signal to a traffic signal controller to change a traffic signal for the zone.

US Pat. No. 10,559,195

FACILITY MANAGEMENT SYSTEM

JTEKT CORPORATION, Osaka...

1. A facility management system comprising:a processing facility;
a signal lamp configured to indicate information on the processing facility;
an information acquisition device that is attached to the signal lamp and is configured to acquire light emission information on the signal lamp and wirelessly transmit the light emission information; and
a terminal configured to wirelessly receive the light emission information which is transmitted by the information acquisition device, determine, on the basis of the light emission information, which of a continuous light-on state, a flashing state, and a continuous light-off state the signal lamp is in, and manage a state of the processing facility, wherein:
the information acquisition device includes a sensor configured to acquire the light emission information and a controller configured to control the sensor;
the controller is configured to:
execute a flashing detection operation in which a first cyclic operation is repeatedly performed a plurality of times consecutively, the first cyclic operation being defined as an operation constituted of a predetermined sampling operation to acquire the light emission information through the sensor and a first quiescent operation performed subsequent to the sampling operation and having a cycle corresponding to a flashing cycle of the signal lamp, and
repeat a second cyclic operation a plurality of times consecutively, the second cyclic operation being defined as an operation constituted of the flashing detection operation and a second quiescent operation performed subsequent to the flashing detection operation and having a time that is longer than a time of the first quiescent operation; and
the terminal is configured to:
determine, on the basis of the light emission information which is acquired in each flashing detection operation, whether or not the signal lamp is in the flashing state, and
cyclically determine whether or not the signal lamp is in the flashing state with the controller cyclically executing the second cyclic operation.

US Pat. No. 10,559,179

SYSTEM AND METHOD FOR DETECTING SMOKE USING AN IONIZATION SENSOR

4Morr Enterprises IP, LLC...

1. A smoke detector comprisingan ionization sensor comprising an ionization chamber
a smoke detector memory comprising
a smoke detector application,
a plurality of ionization smoke signatures, wherein each of said ionization smoke signatures relates to how said ionization chamber interacts with one of a plurality of particulates, each of said plurality of particulates indicative or non-indicative of a fire;
a microprocessor that, according to instructions from said smoke detector application;
receives current data from said ionization sensor;
compares said current data with said plurality of ionization smoke signatures to determine if said current data matches any of said plurality of ionization smoke signatures; and
initiates an alarm sequence based at least in part on a determination as to whether said current data matches an ionization smoke signature related to a fire-indicative particulate of said plurality of particulates.

US Pat. No. 10,559,178

PORTABLE POWER HANDHELD AND WEARABLE TAG DETACHERS

Sensormatic Electronics, ...

1. A method for detaching a security tag from an article, comprising:integrating a mobile communication device with a mobile tag detacher by
receiving at least a portion of the mobile communication device in a first insert space of the mobile tag detacher whereby the portion of the mobile communication device is housed inside the mobile tag detacher, and
mechanically and electrically coupling the mobile communication device to the mobile tag detacher;
receiving a tag body of the security tag in a second insert space of the mobile tag detacher;
mechanically coupling the tag body of the security tag to the mobile tag detacher if at least one of the mobile communication device and the mobile tag detacher verified that removal of the security tag from the article is permitted;
performing operations by the mobile tag detacher to facilitate the detachment of the security tag from the article; and
decoupling the tag body from the mobile tag detacher such that the tag body is removable from the second insert space.

US Pat. No. 10,559,176

RECOILER FOR A MERCHANDISE SECURITY SYSTEM

InVue Security Products I...

1. A merchandise security system for displaying and protecting an article of merchandise and an auxiliary device of the article of merchandise from theft, comprising:a sensor that is secured to the article of merchandise and that detects removal of the article of merchandise from the sensor;
a base that removably supports the sensor and the article of merchandise thereon, wherein the base further comprises an auxiliary port housed therein that operably connects to the auxiliary device; and
a cable operably connected to the sensor,
wherein the base transfers power to the auxiliary port for powering the auxiliary device, and
wherein a security signal is transmitted through the auxiliary port that is used to detect removal of the auxiliary device from the base.

US Pat. No. 10,559,175

MAGNETIC APPARATUS FOR PROVIDING TACTILE SENSATION

CK Materials Lab Co., Ltd...

1. A magnetic apparatus for providing a tactile sensation, the apparatus comprising:a tactile sensation provider, and
a magnetic field generator for generating a magnetic field, the magnetic field being applied to the tactile sensation provider,
wherein the tactile sensation provider includes,
an outer cover, at least part of the outer cover being made of an elastic body, and
a magnetorheological fluid sealed in an inner space of the outer cover, the magnetorheological fluid being a suspension of magnetic particles,
wherein the tactile sensation provider provides vibrational sensations to a user when an alternating current magnetic field is generated by the magnetic field generator, and
wherein the tactile sensation provider provides sensations based on change in rigidity to a user when a direct current magnetic field is generated by the magnetic field generator.

US Pat. No. 10,559,167

METHOD OF AND SYSTEM FOR RENDERING FINANCIAL SERVICES

Novomatic AG, Gumpoldski...

1. A financial services system comprising:A financial services server (1), a plurality of user terminals (2), and a first database (11) operatively coupled with the financial services server (1) for handling an e-wallet account (71) of a user; wherein the financial services server (1) and the plurality of user terminals (2) are connected via a network (6);
the first database (11) storing a plurality of records, each record having an account number of the user as a key value;
each user terminal (2) comprising at least one payment device (61, 62, 21) and a biometric device (72), wherein a user-identification-signal (83) is provided to the financial services server (1) based on a user's biometric data upon accessing the biometric device (72); and wherein the financial services server (1), upon, receiving the user-identification-signal (83), is adapted to request both a credit value of the user terminal (2) and the value of the respective user's e-wallet account (71); and wherein if the credit value is zero and the e-wallet account (71) value is greater than or equal to zero, then a disable-signal (84) for locking the biometric device (72) is sent to the biometric device (72) and, if the e-wallet account (71) value is greater than zero then the e-wallet value is transferred from the e-wallet account (71) to the credit of the user terminal (2); and
wherein while the biometric device (72) is locked, the payment device (61, 62, 21) is unlocked.

US Pat. No. 10,559,157

AUTOMATED VENDING MACHINE WITH TRAY TRANSPORT SYSTEM

SIGNIFI SOLUTIONS INC., ...

1. An automated vending machine comprising:a housing defining an interior, the interior having a dispensing zone accessible from an exterior of the automated vending machine;
a shelving system having wall racking, support shelves, and declined rails;
each support shelf of the support shelves and the wall racking configured with hook coupling mechanisms for facilitating manual releasable coupling of the support shelf to the wall racking, the wall racking for receiving and supporting each support shelf of the support shelves at desired heights;
each support shelf of the support shelves supporting a declined rail of the declined rails having a declivity from an upper end of the declined rail to a lower end of the declined rail and a stopper at the lower end;
a plurality of moveable trays disposed within the interior of the housing, each of the plurality of moveable trays riding on a respective declined rail of the declined rails, whereby each respective moveable tray is gravity fed toward the stopper at the lower end of the respective declined rail;
each moveable tray of the plurality of moveable trays configured to support a vendible product displayed thereon;
a dispensing unit having a coupling mechanism configured to releasably couple with a selected moveable tray of the plurality of moveable trays; and
a gantry system configured to move the dispensing unit about the interior of the automated vending machine and the dispensing zone, and configured to position the coupling mechanism of the dispensing unit for releasably coupling and decoupling with the selected moveable tray.

US Pat. No. 10,559,139

ACTIONS ASSOCIATED WITH VEHICLE RECEIVING STATIONS

BlackBerry Limited, Wate...

1. A method comprising:receiving, by a system associated with a vehicle receiving station, information transmitted by a vehicle, the information acquired by a sensor of the vehicle; and
in response to the received information, directing, by the system, the vehicle to a selected queue of a plurality of queues of the vehicle receiving station, wherein the directing of the vehicle comprises sending, by the system, a message over a network to a controller of the vehicle, the message instructing the vehicle to the selected queue.

US Pat. No. 10,559,132

DISPLAY APPARATUS, DISPLAY SYSTEM, AND CONTROL METHOD FOR DISPLAY APPARATUS

OLYMPUS CORPORATION, Tok...

1. A display apparatus that combines images into a single frame of reference, the display apparatus comprising:a first camera that acquires a first image;
a communication interface that is communicatively coupled to a second camera;
a display; and
a processor that is communicatively coupled to the first camera, the communication interface and the display,
wherein the processor:
receives the first image from the first camera,
determines a first imaging range of the first image in a first frame of reference,
receives, using the communication interface, information from the second camera,
calculates a second imaging area of the second camera in a second frame of reference based on the information, the second imaging area included in the first imaging range,
superimposes the second imaging area onto the first frame of reference to identify a surveillance area of the second camera, and
displays, on the display, the surveillance area of the second camera as a superimposed display image on the first image.

US Pat. No. 10,559,126

6DOF MEDIA CONSUMPTION ARCHITECTURE USING 2D VIDEO DECODER

Samsung Electronics Co., ...

10. A method for rendering three-dimensional (3D) media content, comprising:receiving a multimedia stream;
parsing the multimedia stream into 2D video bitstreams including geometry frames and texture frames, 2D to 3D conversion metadata for rendering 3D points from 2D frames, and scene description metadata describing 6 degree of freedom (6DoF) relationships among objects in a 6DoF scene;
decoding the 2D video streams including the geometry frames and texture frames to generate 2D pixel data;
converting the 2D pixel data into 3D voxel data using the 2D to 3D conversion metadata; and
generating the 6DoF scene from 3D voxel data using the scene description metadata.

US Pat. No. 10,559,116

INTERACTIVE CARICATURE GENERATION FROM A DIGITAL IMAGE

Adobe Inc., San Jose, CA...

1. In a digital medium caricature creation environment, a method implemented by a computing device, the method comprising:detecting, by the computing device, landmark values of facial features in a digital image;
generating, by the computing device, a face model based on the facial features;
distorting, by the computing device, the face model based on a plurality of blend shapes applied sequentially to the face model using a ranking based on the detected facial features, the ranking based on how much the landmark values of the facial features deviate with respect to reference values of the facial features
rendering, by the computing device, the distorted face model as a digital image caricature.

US Pat. No. 10,559,112

HYBRID MECHANISM FOR EFFICIENT RENDERING OF GRAPHICS IMAGES IN COMPUTING ENVIRONMENTS

INTEL CORPORATION, Santa...

1. An apparatus comprising:one or more processors to:
detect a video stream including two-dimensional (2D) images, wherein the video stream is processed through a graphics pipeline; and
perform hybrid combination of a luma (Y)-plane with chrominance (UV)-planes to directly generate a YUV texture by, in a single pass path, generating the UV-planes and the Y-plane separately without performing Red Green Blue (RGB) related conversion and without detouring from the single pass path, wherein the YUV texture is created by combining the UV-planes with the Y-plane, wherein the YUV texture is used to generate three-dimensional (3D) images corresponding to the 2D images, wherein the Y-plane is rendered using a pixel backend, and wherein the UV-planes are rendered using a store command including an unordered access view (UAV) store command.

US Pat. No. 10,559,102

MAKEUP SIMULATION ASSISTANCE APPARATUS, MAKEUP SIMULATION ASSISTANCE METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING MAKEUP SIMULATION ASSISTANCE PROGRAM

PANASONIC INTELLECTUAL PR...

1. A makeup simulation assistance apparatus comprising:a simulation image generator that generates a simulation image obtained by superimposing, on a facial image picked up by an image pickup unit that picks up an image of a face of a user as the facial image, a makeup image showing a state of makeup as being applied to a facial component of the face;
a simulation image output unit that outputs the simulation image being generated to a first display;
an interest degree sensor that senses an interest degree of the user for the makeup image, based on a facial image picked up when the simulation image is output;
an interest degree information output unit that outputs, to a second display, interest degree information indicative of the interest degree being sensed;
a determination unit that determines whether or not the generated simulation image generated by the simulation image generator is desired by the user;
an interest degree history information recorder that stores, in an interest degree history information storage when the determination unit determines that the generating is not desired by the user, interest degree history information in which a facial component corresponding to the makeup image and the interest degree being sensed are associated with each other; and
a makeup candidate information output unit that outputs, to the second display, makeup candidate information indicative of a candidate for makeup recommended to apply next, based on the interest degree being sensed.

US Pat. No. 10,559,101

METHOD AND APPARATUS FOR GENERATING X-RAY TOMOGRAPHIC IMAGE DATA

SAMSUNG ELECTRONICS CO., ...

1. A method comprising:radiating X-rays onto an object at a plurality of preset angular locations via an X-ray source, and obtaining a sparsely-sampled sinogram including X-ray projection data obtained via the X-rays that passed through the object;
applying a trained model parameter to the sparsely-sampled sinogram by using a machine learning model, to thereby generate trained image data, wherein the trained model parameter is obtained via the machine learning model that uses a sub-sampled sinogram for learning as an input and uses a full-sampled sinogram for learning as a ground truth;
estimating, from the sparsely-sampled sinogram, X-ray projection data with respect to the object that is not included in the sparsely-sampled sinogram; and
generating a densely-sampled sinogram using the trained image data and the estimated X-ray projection data.

US Pat. No. 10,559,092

METHOD AND DEVICE FOR PROCESSING WHITE BALANCE OF IMAGE AND STORAGE MEDIUM

GUANGDONG OPPO MOBILE TEL...

1. A method for processing white balance of an image, a content of an image comprising a subject and the method comprising:calculating a first gain for the image according to a Face Automatic White Balance (FaceAWB) algorithm configured to regulate a face in the image to a skin color;
calculating a second gain for the image according to a simple gray world algorithm;
determining whether the first gain is similar to the second gain;
responsive to a determination that the first gain is similar to the second gain, performing white balance processing on the image according to the second gain; and
responsive to a determination that the first gain is not similar to the second gain, performing white balance processing on the image according to the first gain.

US Pat. No. 10,559,079

SYSTEM AND METHOD FOR IMAGE RECONSTRUCTION

UIH AMERICA, INC., Houst...

1. An image reconstruction method comprising:obtaining image data, at least a portion of the image data relating to a region of interest (ROI);
determining local information of the image data, wherein the local information including orientation information of the image data and gradient information of the image data;
determining a regularization item based on a product of the orientation information of the image data and the gradient information of the image data, wherein the orientation information of the image data is modified by an Eigenvalue adjustment function that includes a factor of a scale of the Eigenvalues and at least one factor of a location of a peak of a characteristic curve;
modifying the image data based on the regularization item; and
generating an image based on the modified image data.

US Pat. No. 10,559,077

IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM

TERUMO KABUSHIKI KAISHA, ...

1. An image processing apparatus for using OCT to process a plurality of cross-sectional images obtained by moving an imaging core inside a catheter in an axial direction while rotating the imaging core, the apparatus comprising:a processor configured to:
store data relating to the cross-sectional images in association with position information in the axial direction when each of the cross-sectional images is acquired;
extract a first cross-sectional image in which a disappearance section enabling determination that there is a disappeared portion of an external elastic membrane included in a vascular tomographic image starts, and a second cross-sectional image in which the disappearance section ends, in the plurality of cross-sectional images; and
acquire the position information in the axial direction of the first cross-sectional image and the second cross-sectional image, and for calculating an ablation range influenced by ablation at a position associated with the disappearance section, based on a difference in the acquired position information in the axial direction; and
wherein in a case where a distance from an intravascular wall to the external elastic membrane is set to t and a difference in the position information in the axial direction is set to m, the processor is configured to:
set a semicircle having a string having a length m at a position away from the center as far as the distance t, as the ablation range.

US Pat. No. 10,559,071

IMAGE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM

FUJI XEROX CO., LTD., To...

1. An image processing apparatus comprising:at least one hardware processor configured to implement:
a correcting unit that corrects a dynamic range of a second image in accordance with pixel information of a region in a first image; and
a pasting unit that pastes the second image on the first image after the correction of the dynamic range, the second image having pixel information, the pixel information being corrected in such a manner that a boundary with the first image is inconspicuously viewed.

US Pat. No. 10,559,068

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM PROCESSING IMAGE WHICH IS DEVELOPED AS A PANORAMA

FUJIFILM Corporation, To...

1. An image processing device comprising:an image acquisition section that acquires a first image which is acquired from an imaging element by imaging a subject image using an optical system;
a second image generation section that generates a second image which is developed as a panorama by performing polar coordinate transformation on the first image acquired by the image acquisition section, wherein the sagittal direction and the tangential direction of the first image correspond to the horizontal direction and the vertical direction of the second image such that the tangential direction and the sagittal direction of the first image and the vertical direction and the horizontal direction of the second image are aligned; and
a resolution enhancement processing section that performs resolution enhancement processing on the second image asymmetrically in the horizontal direction and the vertical direction of the second image,
wherein the resolution enhancement processing section performs the resolution enhancement processing on only a partial area of the second image in the vertical direction.

US Pat. No. 10,559,065

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. An information processing apparatus, comprising:a processor configured to:
obtain user information of a user, wherein
the user information is different from gaze information of the user,
the user information includes at least one of heartbeat information, sweating information, body temperature information, brain-wave information, or speed information of the user, and
the user information is detected by a sensor;
determine a central field of view of the user based on the user information;
determine whether the user information indicates a first state or a second state of the user, wherein an activity level of the user in the second state is higher than that in the first state;
set a size of a high-image-quality area in the second state smaller than that in the first state, wherein
a quality of an image displayed in the high-image-quality area is higher than a quality of an image displayed in an area other than the high-image-quality area in an entire display area; and
control display of the image in the high-image-quality area based on the central field of view.

US Pat. No. 10,559,063

IMAGE GENERATING APPARATUS AND METHOD FOR GENERATION OF 3D PANORAMA IMAGE

SAMSUNG ELECTRONICS CO., ...

1. A method for generating a 3D panoramic image by an image generating apparatus, the method comprising:receiving a plurality of 2D images and a plurality of depth maps, each depth map corresponding to a respective one of the plurality of 2D images;
setting a left-eye image area and a right-eye image area for each of the plurality of 2D images based on the plurality of depth maps; and
generating a left-eye panoramic image by composing the left-eye image areas set for each of the plurality of 2D images, and generating a right-eye panoramic image by composing the right-eye image areas set for each of the plurality of 2D images,
wherein the setting comprises analyzing depth values of each of the plurality of depth maps and setting, from among 2D image areas in a respective 2D image corresponding to areas having similar depth values, an image area belonging to a first area as a left-eye image area for the respective 2D image and an image area belonging to a second area as a right-eye image area for the respective 2D image.

US Pat. No. 10,559,060

METHOD AND APPARATUS FOR REAL TIME IMAGE DISTORTION COMPENSATION IN IMMERSIVE THEATER SYSTEM

KOREA ADVANCED INSTITUTE ...

1. A method for real time content viewpoint distortion compensation in an immersive theater system comprising:a) creating geometry data of a theater screen, and mapping position information of seating on the geometry data to reconstruct a virtual theater structure;
b) generating a grid mesh for each seat corresponding to each of a plurality of seats in the theater screen without changing edges of the theater screen; and
c) generating a compensation map with minimized distortion of the grid mesh for each seat, and based on this, single-sampling compensating a pixel of an image to be displayed on the theater screen by the compensation map,
wherein the step c) comprises comparing grid coordinates of a reference viewpoint best represented in image projected onto the theater screen with the grid mesh dependent on the viewpoint for each seat, and creating a compensation map with minimized grid mesh disparity depending on the viewpoint for each seat,
wherein the theater screen is one of a “?” shaped three-screen, a cylindrical screen in shape, and a dome screen in shape,
wherein the grid mesh may be created using different coordinate systems depending on the type of theater screen, in the case of “?” shape, the grid mesh is represented by a xy coordinate system, in the case of cylindrical shape, the grid mesh is represented by a cylindrical coordinate system, and in the case of dome shape, the grid mesh is represented by a fisheye coordinate system.

US Pat. No. 10,559,049

DIGITAL PASSPORT COUNTRY ENTRY STAMP

International Business Ma...

1. A method of verifying a user's passport comprising:generating a first identity element comprising an integration of a unique user identifier data associated with the user's passport with an image file of a stamp having indicia indicating a date of entry of the user in a country and provided with the user's passport, said first identity element generated by applying a group homomorphism function to a combination of the stamp image and the unique user identifier data that links the stamp to the user's passport to form a trusted group homomorphism for only the user's passport, said stamp revealing no sensitive information associated with the user;
digitally signing the first identity element with one or more secret keys associated with a public key infrastructure to create one or more digital signatures, said one or more digital signatures belonging to the trust group; and
appending the one or more digital signatures to the image file of said stamp;
uploading the image file of said stamp with the appended one or more digital signatures for storage to a mobile device associated with the user,
wherein the image file of said stamp and the appended digital signatures and the user provided unique user identifier data is used to verify a date of entry of the user in a country with one or more other digital signature elements that used the unique user identifier data as a trust group belonging to the stamp image file.

US Pat. No. 10,559,043

VISUALIZATION TOOL FOR DISPLAYING AND CONFIGURING ROUTING PATHS AND RELATED ATTRIBUTES FOR TASKS PERFORMED IN MANUFACTURING PROCESSES

Flextronics AP, LLC., Br...

1. A system for determining manufacturing processes, the system comprising:a. a database configured to store attributes assigned to each of a plurality of manufacturing task, links between manufacturing tasks that define a routing path, a manufacturing task standard time for each manufacturing task, manufacturing task standard time variable values associated with manufacturing task formulas, support task standard time variable values associated with support task formulas, a manufacturing task standard time for each manufacturing task, and a support task standard time for each support task;
b. an enterprise resource planning system that manages resources corresponding to the manufacturing tasks and support tasks performed in a manufacturing process for each of a plurality of manufactured items and defines specific manufacturing tasks and support tasks associated with each manufactured item; and
c. a standard time system including a visualization tool having a plurality of graphical user interface (GUI) tools, wherein a first set of GUI tools is configured to:
assign attributes to each of the plurality of manufacturing tasks and manufacturing task standard time variable values, as entered by a user via the first set of GUI tools, wherein each manufacturing task is defined by a manufacturing task formula that includes one of the manufacturing task standard time variables, the manufacturing task formula calculates the manufacturing task standard time which is a time it takes to perform the manufacturing task,
arrange the specific manufacturing tasks for each manufacturing process and a corresponding manufactured item as a routing path, as entered by the user via the first set of GUI tools, and to display the routing path as a connected series of block figures that correspond to the specific manufacturing tasks;
further wherein a second set of GUI tools is configured to:
assign one or more support task formulas for each routing path according to user input provided via the second set of GUI tools, wherein each support task is an activity that supports one or more of the plurality of manufacturing tasks, and each support task is defined by one of the support task formulas, wherein one or more of the support task formulas include a support task standard time variable a value of which is linked to the calculated manufacturing task standard time for one of the manufacturing tasks, the support task formula calculates a support task standard time which is a time to perform the support task,
assign values to each of the support task standard time variables, as entered by the user via the second set of GUI tools,
wherein the database and the visualization tool define a linking matrix that includes links between specific support tasks and one or more specific manufacturing tasks and links between support task formulas and manufacturing task formulas, as defined by the user via the plurality of GUI tools, and to automatically propagate, via the standard time system, a change of a variable value in any variable used in the manufacturing task formulas or the support task formulas to recalculate and update within the database all manufacturing task standard times and all support task standard times linked to the changed variable value by the linking matrix for all manufacturing processes corresponding to the plurality of manufacturing items.

US Pat. No. 10,559,041

CONDUCTING VARIOUS ACTIONS INDICATED BY A FINANCIAL CARD

International Business Ma...

1. A computer-implemented method of performing desired actions in response to conducting transactions with a financial card issued to a cardholder, the method comprising:generating, via at least one processor, a configuration control on a user interface, the configuration control being configured to access a memory in which a plurality of independent sets of information associated with respective indicators of the financial card are stored, the configuration control being further configured to modify the plurality of sets of information in accordance with user input on the configuration control independently of conducting a transaction, the plurality of independent sets of information including a first set of information comprising data defining one or more actions to tender payment for the transaction without posting to a social media network, and a plurality of second sets of information;
wherein each second set of information comprising data defining:
one or more actions to tender payment for the transaction,
one or more actions to geo-tag information for posting to the social media network, wherein the geo-tag includes a location of the cardholder retrieved from a mobile device of the cardholder;
one or more actions that are performed separately from tendering payment for the transaction to post information associated with the transaction automatically to the social media network, each of the actions specifying one or more entities to which information regarding the transaction is disseminated; and
one or more settings according to which the corresponding actions are carried out, wherein the one or more settings comprise settings for the social media network;
wherein each of the first and second sets of information tender payment that is verified against a financial account;
receiving, via the at least one processor from a point of sale device reading the financial card at a merchant location for a purchase transaction, one of the indicators of the financial card to indicate user selection of one of the sets of information;
in response to the received indicator indicating the first set of information:
retrieving, from the memory via the at least one processor, the first set of information; and
performing, via the at least one processor, the one or more actions defined in the retrieved first set of information to tender payment for the purchase transaction without posting to the social media network;
in response to the received indicator indicating one of the second sets of information:
retrieving, from the memory via the at least one processor, the indicated second set of information for the purchase transaction;
performing, via the at least one processor, the one or more actions defined in the retrieved second set of information to tender payment for the purchase transaction, wherein the one or more actions defined in the retrieved second set of information to tender payment for the purchase transaction include:
verifying the location from the mobile device with the location of the point of sale device to authorize payment for the purchase transaction;
performing, via the at least one processor, the one or more actions defined in the retrieved second set of information to geo-tag information for posting to the social media network, wherein the geo-tag includes the location of the cardholder retrieved from the mobile device of the cardholder; and
performing, via the at least one processor, the one or more actions defined in the retrieved second set of information to post information associated with the purchase transaction automatically to the social media network, wherein the posted information includes the geo-tagged information and tendering payment for the purchase transaction is performed concurrently with the posting to the social media network.

US Pat. No. 10,559,037

SYSTEM AND METHOD FOR AUTOMATICALLY CREATING INSURANCE POLICY QUOTES BASED ON RECEIVED IMAGES OF VEHICLE INFORMATION STICKERS

STATE FARM MUTUAL AUTOMOB...

1. A GUI and server based method for real-time generation and editing of dynamic insurance policy quotes based on camera image data of new vehicles and user-specific data, the method comprising:implementing a dynamic policy module as software as a service (SaaS) on a back-end server, the dynamic policy module implemented at least partially on the back-end server and at least partially on a smart phone, the dynamic policy module including an application programming interface (API) portion executing on the back-end server, and the dynamic policy module further including a client portion executing on the smart phone, wherein the client portion accesses the back-end server via the API portion through a computer network;
generating, with the client portion of the dynamic policy module, a graphical user interface (GUI) on a display of the smart phone, the smart phone associated with a customer;
receiving, via the GUI of the smart phone, customer data from a customer to be insured, wherein the customer data includes a user name, a user password, and customer responses to demographic or lifestyle questions;
transmitting, via the computer network, the customer responses to the demographic or lifestyle questions, from the client portion to the API portion of the dynamic policy module;
capturing, by a camera of the smart phone, an image comprising a vehicle information sticker of a new vehicle;
transmitting, via the computer network, the image of the vehicle information sticker to the API portion of the dynamic policy module, the image of the vehicle information sticker comprising at least one of a make, a model, a year, a color, a manufacturer's suggested retail price (MSRP), a fuel economy, a quick response (QR) code, a standard equipment list, an optional equipment list, or a safety rating corresponding to the new vehicle;
processing, by the back-end server, the image of the vehicle information sticker, wherein the processing includes:
(i) extracting information from the image;
(ii) transforming, by the API portion of the dynamic policy module, the image of the vehicle information sticker into a computer readable format by implementing one or more of optical character recognition, bar-code scanning, or QR-code scanning;
(iii) identifying a particular vehicle based on the extracted and transformed information, wherein the vehicle information sticker includes one or more of a make, a model, a year, a color, a manufacturer's suggested retail price (MSRP), a fuel economy, a quick response (QR) code, a standard equipment list, an optional equipment list, or a safety rating corresponding to the particular vehicle;
determining, based on the computer readable format of the image of the vehicle information sticker, by the API portion of the dynamic policy module, that the new vehicle corresponds to a particular vehicle, the particular vehicle having a set of technical specifications;
retrieving, via the computer network, vehicle data corresponding to the particular vehicle from a vehicle database operating separately from the back-end server;
creating, by the back-end server, an insurance policy quote based at least in part on the customer responses to the demographic or lifestyle questions and the retrieved vehicle data of the particular vehicle, wherein each insurance policy quote includes a premium and one or more of: (i) a deductible amount, (ii) a liability amount, (iii) an uninsured motorist amount, or (iv) a damage coverage amount;
sending to the client portion of the dynamic policy module on the smart phone, via the computer network, the insurance policy quote for the particular vehicle to be presented via the GUI of the smart phone;
receiving, at the back-end server via the GUI of the smart phone and via the computer network, an indication to edit the insurance policy quote;
presenting, via the GUI of the smart phone, an editing interface, wherein the editing interface receives a customer input to modify one or more of (i) the deductible amount, (ii) a liability amount, (iii) an uninsured motorist amount, or (iv) a damage coverage amount of the insurance policy quote of the particular vehicle;
executing, via the client portion of the dynamic policy module, the GUI on the display of the smart phone, the GUI providing an editing interface for editing the insurance policy quote for the particular vehicle in real-time, wherein editing the insurance-policy quote for the particular vehicle in real-time comprises:
(a) receiving, by the API portion executing on the back-end server, edited insurance policy quote information corresponding to the one or more of (i) the deductible amount, (ii) a liability amount, (iii) an uninsured motorist amount, or (iv) a damage coverage amount of the insurance policy quote of the particular vehicle,
(b) receiving, by the API portion executing on the back-end server, the customer data corresponding to demographic or lifestyle information of the customer,
(c) updating, by the API portion executing on the back-end server, the insurance policy quote for the particular vehicle based on the edited insurance policy quote information and the customer data to generate a new insurance policy quote,
(d) calculating, by the back-end server, a new premium for the new insurance policy quote for the particular vehicle based on the customer input,
(e) transmitting, to the client portion of the dynamic policy module, the new insurance policy quote for the particular vehicle,
(f) presenting, via the GUI of the smart phone, the new insurance policy quote for the particular vehicle,
(g) receiving, from the client portion of the dynamic policy module, an indication to purchase the new insurance policy quote,
(h) receiving, at the back-end server, a purchase transaction corresponding to the new insurance policy quote, and
(i) generating a profile of the customer associating the new insurance policy quote with the new vehicle.

US Pat. No. 10,559,029

SYSTEM AND METHOD FOR MANAGEMENT AND ACTIVATION OF CONDITIONAL BID OFFERS

1. A system for interaction between a plurality of network-connected buyer devices and a plurality of network-connected seller devices, comprising:a network-connected controller computer comprising at least a processor and a storage device further comprising a program stored in the storage device and operating on the processor, the program when executed by the processor, causes the processor to:
receive a plurality of connections, over a network, from a plurality of seller devices;
receive a plurality of connections, over the network, from a plurality of buyer devices;
receive a plurality of subscriptions from the plurality of seller devices wherein the plurality of subscriptions subscribe to at least a plurality of seller product keywords, the plurality of seller product keywords corresponding to a plurality of products;
receive a bid offer request from a first buyer device of the plurality of buyer devices, the bid offer request comprising at least a plurality of buyer product keywords;
parse the bid offer request to identify at least one buyer product keyword;
identify at least one identified seller device from the plurality of seller devices that subscribe to the plurality of seller product keywords wherein the at least one buyer product keywords is in a same category as an at least one seller product keyword of the plurality of seller product keywords;
send the bid offer request to the at least one identified seller device;
receive a plurality of conditional offer responses from at least a portion of the plurality of seller devices, each conditional offer response of the plurality of conditional offer responses comprising at least an offer and conditional variables, the conditional variables comprising a criterion to quantify a purchase condition;
send the plurality of conditional offer responses to the first buyer device;
receive a first activation response from the first buyer device, the first activation response fulfilling a purchase condition of a first conditional offer response from a first seller device whereby fulfilling the purchase condition activates a corresponding first offer of the first conditional offer response;
receive a fulfillment of the purchase condition, from the first buyer device, the fulfillment associated to processing and verifying a pre-payment;
generate a unique token code associated to the first offer;
send the token code to the first buyer device and to the first seller device.

US Pat. No. 10,559,019

SYSTEM FOR CENTRALIZED E-COMMERCE OVERHAUL

1. An e-commerce enhancing system, the system comprising:one or more storage machines holding instructions executable by one or more logic machines to:
at a personal computing device, receive product identification data relating to a potential e-commerce interest of a user;
at a product identifier, identify a product profile of a plurality of archived product profiles that matches the product identification data;
at an e-commerce enhancement data generator, generate e-commerce enhancement data based on the product profile, the e-commerce enhancement data configured to enhance e-commerce experience relating to the potential e-commerce interest; and
present the e-commerce enhancement data to the user via a display subsystem of the personal computing device;
wherein the product identification data includes an attribute, and the instructions are further executable to:
automatically determine if the attribute of the potential e-commerce interest is compatible with one or more attributes of the plurality of archived product profiles.

US Pat. No. 10,559,011

VIRAL MARKETING OBJECT ORIENTED SYSTEM AND METHOD

PAYASONE INTELLECTUAL PRO...

1. A computer server for providing reference placement on sites accessible over a network by a viewer, said computer server comprising:a processor and associated memory said memory including:
reference specification software module enabling the processor to receive and store a topic specified by a user and at least one parameter relating to the display of references relating to the specified topic for a specified type of viewer;
site information software module enabling said processor to obtain information relating to at least one of a web site being visited and information relating to the viewer;
content evaluation software module enabling said processor to evaluate a favorability of content of a web page in relation to the specified topic, wherein favorability relates to approving or supporting the specified topic; and
placement software module enabling said processor to send a computer file having at least one reference to a web page in response to a placement request wherein the reference relates to content correlated to the parameter and specified topic in accordance with favorability indicated by the content evaluation software module,
wherein said placement software module enables the processor to send a reference in the form of a link, and
wherein said site information software module includes software enabling said processor to obtain metadata relating to at least one of the web site being visited and information relating to the viewer.

US Pat. No. 10,559,005

SYSTEMS AND METHODS FOR GENERATING AND MAINTAINING INTERNET USER PROFILE DATA

PATHMATICS, INC., Santa ...

1. A method, comprising:with cookie harvesting computing equipment, obtaining a cookie set associated with a user profile in a user profile database;
with a web crawler of the cookie harvesting computing equipment, loading a publisher website while allowing the publisher website to update the obtained cookie set;
with advertisement discovery equipment, identifying advertisements that have been placed on the publisher website by an advertisement channel that is separate from the advertisement discovery equipment, wherein at least some of the advertisements that have been placed on the publisher website are associated with the user profile;
with the advertisement discovery equipment, identifying placement pathways associated with the identified advertisements that have been placed on the publisher website by the advertisement channel; and
storing the updated cookie set in the user profile database in association with the user profile.

US Pat. No. 10,559,003

SERVER-SIDE CONTENT MANAGEMENT

A9.com, Inc., Palo Alto,...

1. A computer-implemented method, comprising:under control of one or more computer systems configured with executable instructions,
receiving, to a supplemental content provider from a primary content provider, a supplemental content request for supplemental content to be displayed with primary content to be provided to a client device, the request including at least a content identifier for the primary content, an authentication token, and a publisher token;
verifying, using the authentication token, that the request was generated by the primary content provider;
analyzing the publisher token to determine whether a client identifier associated with the client device is present in the publisher token;
generating the client identifier to be associated with the client device if the client identifier is not present in the publisher token;
determining, based at least in part upon the content identifier and the client identifier, one or more instances of supplemental content determined to be relevant for the supplemental content request; and
providing at least a subset of the one or more instances of supplemental content to the primary content provider, a given instance of supplemental content provided via a two-part payload, wherein a first part of the two-part payload is a header including the supplemental content and a second part of the two-part payload is a footer including the client identifier, wherein the primary content provider is enabled to determine at least one of a selection or a layout of the supplemental content with respect to the primary content before causing the primary content and the supplemental content to be sent for presentation via the client device.

US Pat. No. 10,558,991

METHOD AND APPARATUS FOR PAYMENT, RETURN ON INVESTMENT, AND IMPACT REPORTING

Groupon, Inc., Chicago, ...

1. A computer program product comprising a non-transitory computer readable medium storing computer readable instructions, the computer readable instructions configured, when executed by a processor, to cause the processor to:receive multiple static attributes characterizing a promotion, wherein the multiple static attributes include a promotion value for the promotion and a unit cap for the promotion;
receive multiple dynamic attributes for the promotion, wherein the multiple dynamic attributes include: one or more first dynamic attributes indicative of historic per-redemption revenue generated by one or more past promotions associated with one or more past promotion values, one or more second dynamic attributes indicative of historic redemption frequency of the one or more past promotions, one or more third dynamic attributes indicative of historic customer spending in excess of the one or more past promotion values, one or more fourth dynamic attributes indicative of historic customer return rate in response to the one or more past predictions, one or more fifth dynamic attributes indicative of historic customer return frequency in response to the one or more past predictions, and one or more sixth dynamic attributes indicative of historic fulfillment costs for the one or more past predictions;
calculate, using a processor, multiple visual metrics for the promotion based on the multiple static attributes and the multiple dynamic attributes, including:
calculate, based on the one or more first dynamic attributes for the promotion and the unit cap for the promotion, a redemption revenue visual metric for the promotion, wherein the redemption revenue visual metric is indicative of revenue generated from the promotion;
calculate, based on the one or more third dynamic attributes for the promotion and the unit cap for the promotion, an upsell revenue visual metric for the promotion, wherein the upsell visual revenue metric is indicative of revenue predicted to be generated from promotion upsells associated with the promotion;
calculate, based on the one or more first dynamic attributes for the promotion, the one or more second dynamic attributes for the promotion, the one or more fourth dynamic attributes for the promotion, the one or more fifth dynamic attributes for the promotion, and the unit cap for the promotion, a repeat revenue visual metric for the promotion, wherein the repeat business revenue visual metric is indicative of revenue predicted to be generated from one or more repeat business transactions associated with the promotion; and
calculate, based on the one or more fifth dynamic attributes for the promotion, the redemption revenue visual metric for the promotion, the upsell revenue visual metric for the promotion, and the repeat revenue visual metric for the promotion, a cost visual metric for the promotion;
generate a graph-based user interface that includes multiple user interface elements, wherein the multiple user interface elements include: a first user interface element generated based on the redemption revenue visual metric, the upsell revenue visual metric, and the repeat revenue visual metric, and a second user interface element generated based on the cost visual metric;
receive consumer input data associated with the promotion, wherein the consumer data includes one or more updates each related to at least one dynamic attribute of the multiple dynamic attributes; and
responsive to receiving the consumer input data, update the graph-based user interface based on the consumer input data, including:
update at least one dynamic attribute of the multiple dynamic attributes based on the one or more updates;
update at least one visual metric of the multiple visual metrics based on the at least one updated dynamic attribute; and
generate one or more real-time updates to at least one of the first user interface element and the second user interface element based on the at least one updated visual metric.

US Pat. No. 10,558,987

SYSTEM IDENTIFICATION FRAMEWORK

Adobe Inc., San Jose, CA...

1. A computing device comprising:a processing system;
one or more computer-readable media storing instructions that, when executed by the processing system, implement:
a data collector configured to collect marketing data indicative of user interaction with online marketing offers provided by digital marketers in connection with access to resources over a computer network;
a simulator configured to perform operations including:
analyzing the collected marketing data to learn a set of features, classifying the features by feature types, and assigning response functions to the feature types that define how variables classified within each feature type respond to simulated online marketing offers; and
deriving a prediction model based on the assigned response functions that models multiple marketing strategies according to a Q iteration reinforcement algorithm;
an evaluator configured to test the multiple marketing strategies offline using the prediction model, including, for each of the multiple marketing strategies:
ascertaining a respective value for each of the variables at a first time-state;
generating a first simulated online marketing offer at the first time-state according to the respective marketing strategy;
predicting a user reaction to the first simulated online marketing offer at the first time-state;
responsive to predicting the user reaction to the first simulated online marketing offer, updating the respective value for each of the variables at a second time-state based on the response functions by:
updating a value of at least one of the variables to a random value; and
updating a value of at least one other of the variables based on the respective value at the first time-state and the random value;
generating a second simulated online marketing offer at the second time-state according to the respective marketing strategy; and
predicting a user reaction to the second simulated offer at the second time-state;
the evaluator further configured to perform operations including:
comparing the multiple marketing strategies one to another using the Q iteration reinforcement algorithm, fitted by non-parametric regression trees corresponding to a long term offer acceptance value for each of the marketing strategies to the user reactions at the first and second time-states;
selecting an optimal marketing strategy from among the multiple marketing strategies that maximized a Q value of the Q iteration reinforcement algorithm corresponding to the long term offer acceptance value; and
outputting the optimal marketing strategy.

US Pat. No. 10,558,983

USER ACCESS TO A REGISTRY OF BUSINESS ENTITY DEFINITIONS

INTERNATIONAL BUSINESS MA...

1. A method for controlling user access to a registry of business entity definitions to handle user requests to access business entity definitions, the method comprising, with a processor having a network connector to interface with a computer network and associated memory communicatively coupled to the processor, performing all of:maintaining the registry of business entity definitions, wherein each business entity definition comprises a description of a corresponding business entity, the description of each corresponding business entity comprising a description of at least one business service provided by that business entity, each of said business entity definitions and business service descriptions having different and separate permission details associated therewith;
receiving a request in the processor associated with said registry from a user, via the network connector, the request comprising search criteria and requesting to access a corresponding business entity definition comprising a plurality of information elements;
obtaining the identity of the user from data associated with the request with said processor;
determining, with said processor, a list of business entity definitions that satisfy the search criteria and whether the user has permission to access that business entity definition and any business service description of that business entity that matched the search criteria; and
with said processor, returning filtered search results in response to said request, wherein filtering the search results comprises removing from the search results any business entity for which it is determined that the user does not have permission for either the corresponding business entity definition or business service description that matched the search criteria.

US Pat. No. 10,558,982

SYSTEMS AND METHODS FOR UNDERSTANDING AND SOLVING CUSTOMER PROBLEMS BY EXTRACTING AND REASONING ABOUT CUSTOMER NARRATIVES

CAPITAL ONE SERVICES, LLC...

1. A system for autonomously identifying and responding to customer problems, the system comprising:one or more processors; and
memory in communication with the one or more processors and storing instructions that, when executed by the one or more processors, are configured to cause the system to:
receive a customer utterance associated with a customer;
determine whether the customer utterance comprises sufficient customer identification information to identify the customer;
responsive to determining that the customer utterance does not comprise sufficient customer identification information to identify the customer, iteratively prompt the customer for and receive a new customer utterance associated with the customer until the new customer utterance comprises sufficient customer identification information to identify the customer;
responsive to determining that the customer utterance comprises sufficient customer identification information:
define, based on the customer utterance, a first customer narrative comprising a first customer goal;
determine whether the first customer narrative is sufficient to identify a first customer problem;
responsive to determining that the first customer narrative is insufficient to identify the first customer problem:
redefine the first customer narrative as a second customer narrative based on either (i) one or more prior customer interactions with the customer or (ii) a lack of prior customer interactions, each of the one or more prior customer interactions predating the customer utterance;
determine whether the second customer narrative is sufficient to identify the first customer problem; and
responsive to determining that the second customer narrative is insufficient, iteratively (i) provide follow-up system utterances to the customer in order to elicit additional information related to the first customer goal, (ii) receive the additional information, and (iii) redefine the second (or (n?1)th) customer narrative as a third (or nth) customer narrative based on the received additional information until the third (or nth) customer narrative is determined to be sufficient to identify the first customer problem;
responsive to determining that the first customer narrative, the second customer narrative, or the third/nth customer narrative is sufficient to identify the first customer problem, identify at least a first response corresponding with the first customer problem;
customize the first response for the customer based on the first customer narrative, the second customer narrative, or the third customer narrative; and
execute the customized first response.