US Pat. No. 10,511,554

MAINTAINING TRIBAL KNOWLEDGE FOR ACCELERATED COMPLIANCE CONTROL DEPLOYMENT

INTERNATIONAL BUSINESS MA...

1. A system comprising:a memory that stores computer executable components; and
a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:
a knowledge base generation component that generates a knowledge graph corresponding to respective commitments created via tribal exchanges, the knowledge graph comprising a semantic level and an operational level;
a semantic graph population component that populates the semantic level of the knowledge graph based on identified parties to the respective commitments;
an operational graph population component that populates the operational level of the knowledge graph based on tracked status changes associated with the respective commitments; and
an assessment component that retrieves an account configuration from the knowledge graph at the semantic level or the operational level and assesses an impact of enforcing a compliance control associated with the knowledge graph.

US Pat. No. 10,511,550

SYSTEMS AND METHODS FOR INSTANT MESSAGING

TENCENT TECHNOLOGY (SHENZ...

1. A method for instant messaging comprising:establishing, by a user client, a first association relationship with at least one first apparatus client for instant messaging through a predetermined network;
transmitting, by the user client, a first control instruction to the at least one first apparatus client to trigger the at least one first apparatus client to control, according to the first control instruction, an intelligent apparatus connected to the at least one first apparatus client to execute one or more predetermined operations;
receiving, by the user client, apparatus information of the intelligent apparatus;
displaying a list of associated intelligent apparatuses in a graphical user interface of the user client, the list including the intelligent apparatus having the first association relationship with the at least one first apparatus client; and
establishing at least two apparatus groups based on a group-creation user selection on the graphical user interface designating multiple listed intelligent apparatuses to be included in one of the at least two apparatus groups, the at least two apparatus groups including a monitoring apparatus group and a non-monitoring apparatus group, the monitoring apparatus group being associated with a first control mode, and the non-monitoring apparatus group being associated with a second control mode;
wherein transmitting the first control instruction to the at least one first apparatus client comprises:
in response to a first user instruction directed to the monitoring apparatus group and received on the graphical user interface, respectively transmitting, by the user client through the predetermined network, a first-type control instruction to each apparatus client corresponding to each intelligent apparatus in the monitoring apparatus group to trigger all intelligent apparatus in the monitoring apparatus group to perform a same first operation; and
in response to a second user instruction directed to the non-monitoring apparatus group and received on the graphical user interface, respectively transmitting, by the user client through the predetermined network, a second-type control instruction to each apparatus client corresponding to each intelligent apparatus in the non-monitoring apparatus group to trigger all intelligent apparatus in the non-monitoring apparatus group to perform a same second operation,
wherein:
the intelligent apparatus is associated with either the monitoring apparatus group or the non-monitoring apparatus group based on the received apparatus information; and
the first control mode of the monitoring apparatus group differs from the second control mode of the non-monitoring apparatus group; and
wherein:
the first-type control instruction is a switch-on instruction and the same first operation is switching on the corresponding intelligent apparatus in the monitoring apparatus group; or the first-type control instruction is a switch-off instruction and the same first operation is switching off the corresponding intelligent apparatus in the monitoring apparatus group; and
the method further comprises:
receiving a control mode selection on the graphical user interface, the control mode selection comprising both the first user instruction and the second user instruction, wherein one of the first-type control instruction and the second-type control instruction is the switch-on instruction, and the other one of the first-type control instruction and the second-type control instruction is the switch-off instruction; and
transmitting the first-type control instruction to each apparatus client corresponding to each intelligent apparatus in the monitoring apparatus group, at the same time as transmitting the second-type control instruction to each apparatus client corresponding to each intelligent apparatus in the non-monitoring apparatus group.

US Pat. No. 10,511,549

HIGH-SPEED INTERCONNECT SOLUTIONS WITH SUPPORT FOR CONTINUOUS TIME IN-BAND BACK CHANNEL COMMUNICATION AND PROPRIETARY FEATURES

Avago Technologies Intern...

1. A network device for performing serializer-deserializer communication with a remote link partner (LP) over a transmission line, the network device comprising:a receiver comprising a decoder configured to extract link training data, indicating support for a proprietary mode, from an in-band link training communication channel in a signal received from the remote LP over the transmission line, wherein the in-band link training communication channel is embedded among data traffic corresponding to an Open Systems Interconnect (OSI) data link layer and other higher OSI layers in the signal; and
a transmitter configured to receive the link training data from the receiver and adjust one or more parameters of the transmitter based on the proprietary mode indicated as being supported by the link training data,
wherein the proprietary mode includes a proprietary forward error correction scheme for encoding the OSI data link layer and other higher OSI layers in the signal, and wherein the proprietary forward error correction scheme comprises a proprietary generator matrix or polynomial.

US Pat. No. 10,511,548

MULTICAST PACKET HANDLING BASED ON CONTROL INFORMATION IN SOFTWARE-DEFINED NETWORKING (SDN) ENVIRONMENT

NICIRA, INC., Palo Alto,...

1. A method for a first host to perform multicast packet handling in a software-defined networking (SDN) environment that includes the first host, one or more second hosts and a network management entity, wherein the method comprises:in response to the first host detecting, from a first virtualized computing instance supported by the first host, a request to join a multicast group address,
obtaining, from the network management entity by the first host, control information that includes one or more destination addresses associated with the one or more second hosts that have joined the multicast group address on behalf of multiple second virtualized computing instances, wherein obtaining the control information comprises sending, to the network management entity, a request to join the multicast group address on behalf of the first virtualized computing instance, and wherein the request includes the multicast group address, a source virtual tunnel endpoint (VTEP) address associated with the first host and an identifier of a logical overlay network on which the first virtualized computing instance is located; and
in response to the first host detecting, from the first virtualized computing instance, an egress multicast packet that includes an inner header addressed to the multicast group address,
generating one or more encapsulated multicast packets based on the control information, wherein a particular encapsulated multicast packet is generated by encapsulating the egress multicast packet with an outer header addressed to a particular destination address; and
sending the one or more encapsulated multicast packets to the one or more second hosts in a unicast manner or multicast manner, or a combination of both.

US Pat. No. 10,511,533

SYSTEMS AND METHODS FOR ADJUSTING A CONGESTION WINDOW VALUE OF A CONTENT DELIVERY NETWORK

Level 3 Communications, L...

1. A content delivery network (CDN) comprising:a first content server configured to:
set a congestion window (CWND) value for a first communication session between a client device and the first content server;
control the CWND value during a duration of the first communication session based at least on a detected congestion on a connection between the client device and the first content server;
receive a request for CWND statistics from the client device comprising one or more controlled CWND values; and
transmit the CWND statistics to the client device; and
a second content server configured to:
receive a request for content from the client device, the request comprising an identification of the content and the CWND statistics; and
set an initial CWND value for a second communication session between the client device and the second content server based at least on the received CWND statistics from the client device.

US Pat. No. 10,511,510

PERFORMANCE OF COMMUNICATION NETWORK BASED ON END TO END PERFORMANCE OBSERVATION AND EVALUATION

Accenture Global Solution...

1. A computer-implemented method for evaluating performance of one or more communication networks, the method being executed by one or more processors and comprising:receiving a generated performance index for a communication network, wherein the performance index is generated based at least in part on a set of key performance indicators and corresponding thresholds values, the key performance indicators being measurable aspects of the communication network's performance;
receiving an external performance index for the communication network, wherein the external performance index is based on data collected from one or more users of the communication network and represents user experience with the communication network;
in response to determining a discrepancy between the generated performance index and the external performance index, evaluating one or more key performance indicators associated with the communication network, wherein the one or more key performance indicators under evaluation include at least one key performance indicator not included in the set of key performance indicators on which the generated performance index for the communication network is based, the evaluating comprising, for each key performance indicator under evaluation:
(i) receiving data associated with the key performance indicator;
(ii) based at least in part on the received data, determining a key performance indicator value and one or more corresponding threshold values for the key performance indicator; and
(iii) comparing the key performance indicator value to the corresponding one or more threshold values; and
in response to determining that a value of a given key performance indicator fails a threshold comparison against its one or more corresponding threshold values, (i) updating the set of key performance indicators to include the given key performance indicator and its one or more corresponding threshold values, and (ii) automatically modifying one or more settings for the communication network.

US Pat. No. 10,511,506

METHOD AND DEVICE FOR MANAGING VIRTUALIZED NETWORK FUNCTION

ZTE CORPORATION, Shenzhe...

1. A method for managing a virtualized network function, comprising:initializing, by a Network Functions Virtualization Orchestrator (NFVO), a Virtualized Network Function Manager (VNFM) pool according to configuration information of the VNFM pool, wherein the configuration information comprises an initial number of VNFMs managed by the VNFM pool, a maximum number of VNFMs managed by the VNFM pool, and a maximum number of Virtualized Network Functions (VNFs) managed by each VNFM in the VNFM pool, the maximum number of VNFs managed by each VNFM is the same;
monitoring, by the NFVO, a status of each VNFM in the VNFM pool, and, when an invalid VNFM is monitored, ascribing, by the NFVO, one or more VNFs managed by the invalid VNFM to one or more valid VNFMs in the VNFM pool;
monitoring, by the NFVO, the number of VNFMs managed by the VNFM pool;
when the number of VNFMs currently managed by the VNFM pool is greater than the initial number of VNFMs managed by the VNFM pool, searching, by the NFVO, for a VNFM which manages the most VNFs in the VNFM pool; when the number of VNFs managed by the VNFM which manages the most VNFs is less than a half of the maximum number of VNFs managed by the VNFM which manages the most VNFs, selecting, by the NFVO, a VNFM which manages the fewest VNFs in the VNFM pool as a VNFM to be deleted;
performing, by the NFVO, following operations for each VNF managed by the VNFM to be deleted: finding out a VNFM which manages the fewest VNFs in all VNFMs excluding the VNFM to be deleted to serve as a deletion takeover VNFM for the VNF managed by the VNFM to be deleted, and ascribing the VNF to the deletion takeover VNFM; and
after all VNFs managed by the VNFM to be deleted have been ascribed to the one or more valid VNFMs, deleting, by the NFVO, the VNFM to be deleted.

US Pat. No. 10,511,503

SERVER DEVICE AND COMMUNICATION SYSTEM

FUJITSU LIMITED, Kawasak...

1. A server device that provides services to a terminal, the server device comprising:a memory configured to store information indicating one or more measurement devices and information indicating one or more relay devices in association with identification information of the terminal, the one or more measurement devices performing one or more measurements to obtain measurement data that is used in the terminal, the one or more relay devices being able to relay the measurement data to the server device;
a processor configured to generate one or more report packets that are each destined for at least one of the relay devices, each report packet reporting a corresponding list of one or more white-listed measurement devices that are a transmission source of measurement data to be relayed by a respective relay device of the one or more relay devices to the server device; and
a transceiver configured to transmit the one or more report packets, wherein:
when the transceiver receives a request that the use of the services in the terminal be stopped, the processor:
generates a first report packet destined for a first relay device associated with the identification information of the terminal, the first report packet including a first list in which the one or more measurement devices associated with the identification information of the terminal are not included; and
makes a request to a second relay device that measurement data received by the second relay device not be relayed to the server device in response to the second relay device relaying only measurement data transmitted from measurement devices associated with the identification information of the terminal.

US Pat. No. 10,511,490

AUTOMATED CONFIGURATION OF SOFTWARE DEFINED NETWORK CONTROLLER

International Business Ma...

1. A method, comprising:communicating network configuration information and network behaviors of software defined network (SDN) applications directly to at least one software defined networking controller, where each of the SDN applications has only SDN application logic and northbound interface (NBI) drivers and the at least one software defined networking controller has only NBI agents, SDN control logic, and a control to plane interface (CDPI) driver; and
automatically transferring the configuration information from a plurality of network devices each including a software defined network datapath directly to the at least one software defined networking controller, wherein said automatically transferring step includes:
identifying a type of each of the plurality of network devices;
retrieving the configuration information associated with a subset of the plurality of network devices of a certain type and communicated directly to the at least one software defined networking controller;
converting, solely via the software networking controller, the configuration information associated with a subset of the plurality of network devices of a certain type into one or more sets of equivalent rules defined by a communications protocol to be used by the at least one software defined networking controller; and
configuring the at least one software defined networking controller with the converted configuration information to maintain currently configured behaviors of the plurality of network devices,
wherein different SDN controllers concurrently support different configuration interfaces.

US Pat. No. 10,511,479

SERVICE DEPLOYMENT METHOD AND NETWORK FUNCTIONS ACCELERATION PLATFORM

Huawei Technologies Co., ...

1. A service deployment method, wherein the service deployment method is applied to a network functions acceleration platform (NFAP), wherein the NFAP comprises a physical machine and an acceleration card, the physical machine and the acceleration card are connected by a PCIe data channel, and the acceleration card comprises a field-programmable gate array (FPGA), and the method comprises:loading, by the FPGA, an FPGA framework file when the FPGA is powered on, so that the FPGA comprises M partial reconfigurable (PR) areas, a configuration module, and a data flow forwarding module, wherein a hardware resource in the FPGA is allocated to the PR areas, the configuration module is connected to the PCIe data channel and is connected to the PR areas, the data flow forwarding module is connected to the PR areas, the data flow forwarding module comprises an empty forwarding flow table, and M is a positive integer greater than or equal to 1;
when receiving a service configuration instruction, generating, by the physical machine, a virtual machine (VM), and selecting at least one PR area from the M PR areas to establish a correspondence with the VM;
performing, by the configuration module, service resource configuration on the selected at least one PR area according to a PR configuration resource, so that the selected at least one PR area has a service processing capability, wherein the PR configuration resource is generated by the VM according to the service configuration instruction and a configuration template; and
adding, by the configuration module, a forwarding entry corresponding to the PR area in the forwarding flow table, so that the data flow forwarding module forwards a received network packet to the corresponding PR area by searching the forwarding flow table, wherein the forwarding entry is generated by the physical machine according to a to-be-processed network packet and a forwarding template.

US Pat. No. 10,511,474

INFORMATION PROCESSING APPARATUS, COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM, AND METHOD FOR PROCESSING INFORMATION

FUJITSU LIMITED, Kawasak...

9. A method of processing information, in an information processing system comprising a plurality of nodes, a plurality of first switches each of which is connected to a set of respectively unique nodes among the plurality of nodes, and a plurality of second switches each of which is connected thereto the plurality of first switches via a plurality of links, in allocating a job executed in a predetermined number of nodes to one or more nodes among the plurality of nodes, the method comprising:determining whether a single target switch of the plurality of first switches is connected to a plurality of unoccupied nodes equal to or more than the predetermined number of nodes, wherein the plurality of unoccupied nodes are among the plurality of nodes;
upon determining that the single target switch is connected to the plurality of unoccupied nodes equal to or more than the predetermined number of nodes, allocating the job to the plurality of unoccupied nodes connected to the single target first switch; and
upon determining that the single target switch is not connected to the plurality of unoccupied nodes equal to or more than the predetermined number of nodes, allocating the job to unoccupied nodes connected to each of two or more target first switches among the plurality of the first switches,
wherein a number of the unoccupied nodes connected to each of the two or more target first switches does not exceed a number of the valid links among the plurality of links connected to each of the two or more target first switches.

US Pat. No. 10,511,472

METHOD OF SIMULTANEOUSLY PERFORMING PACKET DETECTION, SYMBOL TIMING ACQUISITION, AND CARRIER FREQUENCY OFFSET ESTIMATION USING MULTIPLE CORRELATION DETECTION, AND BLUETOOTH APPARATUS USING SAME

ABOV Semiconductor co., L...

1. A Bluetooth apparatus, the apparatus comprising:a frequency demodulating unit receiving a frequency modulated signal and converting the frequency modulated signal into a similar amplitude modulated signal which is a frequency proportional signal having a value proportional to frequency of a baseband signal; and
multiple correlation detectors generating multiple correlation indices from the similar amplitude modulated signal, on a basis of an access address received from a link layer and a plurality of carrier frequency offset search windows,
wherein a packet detection, a symbol timing acquisition, and a carrier frequency offset estimation for the frequency modulated signal are simultaneously performed in parallel, on a basis of the multiple correlation indices.

US Pat. No. 10,511,469

SYNTHESIZER

SONY CORPORATION, Tokyo ...

1. A synthesizer comprisinga first two-point modulation phase locked loop, TPM PLL, circuit configured to receive a first reference clock signal at a first reference frequency and a feedback signal at a feedback frequency and to generate a first chirp signal in a first mm-wave frequency range by applying a two-point modulation PLL on the first reference clock signal,
a second integer-n TPM PLL circuit configured to receive a second reference clock signal at a second reference frequency lower than the first reference frequency and to generate a second chirp signal in a second mm-wave frequency range by applying a two-point modulation PLL on the second reference clock signal,
a mixer configured to downconvert the first chirp signal by the second chirp signal to obtain the feedback signal at the feedback frequency corresponding to the difference of the frequency of the first chirp signal and the second chirp signal, and
a feedback path configured to feed back the feedback signal to the first TPM PLL circuit.

US Pat. No. 10,511,464

BAUD RATE TRACKING AND COMPENSATION APPARATUS AND METHOD

REALTEK SEMICONDUCTOR COR...

1. An apparatus comprising:a sampling circuit configured to sample a reception signal according to a clock and generate a sampled result, the sampling circuit being configured to generate a transition notification signal when the sampled result indicates a transition of the reception signal;
a clock counting circuit configured to count cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal and to generate a number of the cycles of the clock between the first transition of the reception signal and the second transition of the reception signal;
a bit counting circuit configured to count bit(s) between the first transition and the second transition according to the clock and a bit cycle indicative of cycles of the clock per bit, so as to generate a number of the bit(s) between the first transition of the reception signal and the second transition of the reception signal; and
a divisional circuit configured to update the bit cycle with a calculation value obtained by dividing the number of the cycles of the clock by the number of the bit(s).

US Pat. No. 10,511,459

SELECTION OF MANAGED FORWARDING ELEMENT FOR BRIDGE SPANNING MULTIPLE DATACENTERS

NICIRA, INC., Palo Alto,...

1. For a set of central controllers that manages forwarding elements operating in a plurality of datacenters, a method comprising:receiving a configuration for a bridge between (i) a logical L2 network that spans at least two datacenters and (ii) a physical L2 network, wherein the configuration comprises a tuple that includes a logical network identifier, a physical network identifier, and a datacenter identifier that specifies a particular one of the datacenters for implementation of the bridge;
identifying a plurality of managed forwarding elements that implement the logical L2 network and are operating in the particular datacenter;
selecting one of the identified managed forwarding elements to implement the bridge; and
distributing bridge configuration data to the selected managed forwarding element.

US Pat. No. 10,511,449

AUTHENTICATION METHOD, NOTIFICATION METHOD, SOURCE DEVICE, AND SINK DEVICE

PANASONIC INTELLECTUAL PR...

1. A method for use in a source device, the method comprising:acquiring a random number;
transmitting the acquired random number to a sink device through a High Definition Multimedia Interface-Consumer Electronics Control (HDMI-CEC) bus;
receiving first signature information and capability information from the sink device through the HDMI-CEC bus, the first signature information being information in which the random number is encrypted with a first secret key correlated with the sink device, and the capability information being information about a display capability of the sink device;
acquiring a result of a first determination whether first decrypted information is compatible with the transmitted random number, the first decrypted information being obtained by decrypting the received first signature information with a first public key paired with the first secret key;
acquiring a result of a second determination whether second decrypted information is correct information, the second decrypted information being obtained by decrypting second signature information with a second public key corresponding to a second secret key, the second public key being externally acquired with the source device, and the second secret key being an externally-acquired second secret key,
wherein certification information and the second signature information are received from the sink device in the receiving, the certification information being constructed with the first public key and the capability information, the second signature information including information in which the sink device encrypts the certification information with the second secret key,
when the result of the first determination is that the first decrypted information is compatible with the transmitted random number, and when the result of the second determination is that the second decrypted information is correct information, determining that the received capability information is correct information; and
outputting video corresponding to the capability information determined to be correct information to the sink device,
wherein each of the first secret key and the first public key is an encryption key that the sink device previously retains.

US Pat. No. 10,511,447

SYSTEM AND METHOD FOR GENERATING ONE-TIME DATA SIGNATURES

Guardtime SA, Lausanne (...

1. A method for verifying the authenticity of a digital data set D comprising:selecting a plurality T of secret values;
for each secret value, computing a representative value as the output of a randomizing function;
computing a public key from the representative values;
computing a document function value of the digital data set;
compiling a set of T authentication code values by computing each authentication code value as an at least pseudo-randomizing functional combination of the document function value and a respective one of the secret values;
timestamping the set of T authentication code values at a signing time t said timestamping being synchronized with physical time, and compiling a time vector having elements corresponding to binary bits of a digital representation of the signing time;
digitally signing the set of authentication code values at the signing time t to yield a first signature;
compiling a selected key vector having a plurality of elements, each element being a respective one of the secret values when the corresponding respective element of the time vector has a first binary value; and
forming a signature of the digital data set to include the set of authentication code values, the first signature, and the selected key vector.

US Pat. No. 10,511,442

METHOD AND SYSTEM FOR RESPONDING TO AN UNAUTHORIZED ACTION ON A MOBILE COMMUNICATIONS DEVICE

Lookout, Inc., San Franc...

1. A method comprising:determining, by an autonomous security component of a mobile communications device, that the mobile communications device is in a first state, the first state being an indication that an unauthorized action has been attempted on the mobile communications device, wherein the autonomous security component is preloaded on a system partition of an internal memory of a mobile communications device where an operating system is stored, wherein the autonomous security component is configured to persist after a factory reset of the mobile communications device, and wherein the autonomous security component is separate from the operating system;
in response to the determination that the mobile communications device is in the first state, initiating and causing, by the autonomous security component, a destruction of a cryptographic key of a bootloader from a key store on the mobile communications device;
upon initiating and causing the destruction of the cryptographic key of the bootloader, initiating, by the autonomous security component, a boot sequence at the mobile communications device; and
during the boot sequence at the mobile communications device after the destruction of the cryptographic key, booting the mobile communications device into a kernel that restricts operation of the mobile communications device so that the mobile communications device can only communicate with a single server:
(i) to report at least one of: a mobile communications device location, or mobile communications device contextual information; and
(ii) to receive a re-enablement cryptographic key from the single server.

US Pat. No. 10,511,438

METHOD, SYSTEM AND APPARATUS USING FORWARD-SECURE CRYPTOGRAPHY FOR PASSCODE VERIFICATION

OneSpan North America Inc...

1. A method for generating a dynamic authentication credential comprising the steps of:obtaining a value of a passcode;
obtaining a value of a passcode-blinding data element;
obtaining a value of a dynamic variable;
obtaining a value of a cryptographic credential generation key;
calculating a value of a passcode verifier data element from the obtained passcode value and the obtained passcode-blinding data element value;
calculating the dynamic authentication credential from the calculated passcode verifier data element value, the obtained dynamic variable value and the obtained cryptographic credential generation key value, and
maintaining and storing a value of a state variable in a memory of an authentication token or authentication client performing the method;
wherein obtaining the cryptographic credential generation key value comprises reading the value of the state variable from the memory of the authentication token or authentication client performing the method and determining the cryptographic credential generation key value as a function of the value of the state variable.

US Pat. No. 10,511,435

METHODS AND APPARATUS FOR DIRECT COMMUNICATION KEY ESTABLISHMENT

Telefonaktiebolaget LM Er...

1. A method, performed by a user equipment (UE), for obtaining a direct communication key for direct communication with a device over an interface, the method comprising:sending, to the device, an identifier of the UE and requesting the direct communication key for direct communication with the device;
receiving, from the device, a Message Authentication Code (MAC), a device identifier, key generation information, and an encrypted direct communication key, wherein the MAC is generated using the direct communication key;
deriving a session shared key from at least the key generation information;
deriving a UE delivery key from at least the session shared key and the device identifier;
decrypting the encrypted direct communication key using the derived UE delivery key; and
using the decrypted direct communication key for the direct communication between the UE and the device over the interface.

US Pat. No. 10,511,432

APPARATUS AND METHOD FOR CLOCK RECOVERY BASED ON NON-NON RETURN TO ZERO (NON-NRZ) DATA SIGNALS

PHOTONIC TECHNOLOGIES (SH...

1. A method comprising:receiving different clock signals and a Pulse Amplitude Modulation (PAM) data signal having 2N different amplitude levels, wherein N is an integer that is equal to or greater than 2;
generating a plurality of sampled signals by sampling the PAM data signal according to the different clock signals;
generating a plurality of synchronized signals by sampling each of the plurality of sampled signals according to one of the different clock signals; and
adjusting a frequency of the one of the different clock signals based on the plurality of synchronized signals until the frequency of the one of the different clock signals is within a threshold range associated with a frequency of the PAM data signal or a division of the frequency of the PAM data signal.

US Pat. No. 10,511,428

APPARATUS AND METHOD FOR PERIODIC CHANNEL STATE REPORTING IN A WIRELESS NETWORK

Samsung Electronics Co., ...

1. A method of reporting channel characteristics of at least two component carriers to at least one base station in a wireless communication, the method comprising:performing periodic channel state information (CSI) reporting regarding the at least two component carriers on at least two individually configured physical uplink control channels (PUCCHs),
wherein, in case that a collision between a first CSI report of a first report type on a first of the at least two PUCCHs and a second CSI report of a second report type on a second of the at least two PUCCHs occurs in a subframe,
if priorities allocated to the first report type of the first CSI report and the second report type of the second CSI report are different, the performing periodic CSI reporting comprises transmitting a CSI report having a higher priority among the first CSI report and the second CSI report, wherein a highest priority is assigned to a report type including wideband precoding matrix indicator (PMI), and
if priorities allocated to the first report type of the first CSI report and the second report type of the second CSI report are the same, the performing periodic CSI reporting comprises transmitting a CSI report corresponding to a primary cell among the first CSI report and the second CSI report.

US Pat. No. 10,511,425

CHANNEL-STATE INFORMATION PROCESS PROCESSING METHOD, NETWORK DEVICE, AND USER EQUIPMENT

Huawei Technologies Co., ...

1. An apparatus comprising a storage medium including processor-executable instructions, and a processor coupled to the storage medium, wherein the processor-executable instructions, when executed by the processor, cause the apparatus to:send a first channel-state information (CSI) request to a terminal device to request the terminal sending aperiodic CSI; and
in response to the first CSI request, receive aperiodic CSI corresponding to multiple CSI processes, wherein the aperiodic CSI comprises a first part and a second part, the first part is associated with a part of the multiple CSI processes, and is a previous measurement result when a quantity of the multiple aperiodic CSI processes exceeds a first threshold, and the second part is associated with other part of the multiple CSI processes.

US Pat. No. 10,511,422

METHOD AND TERMINAL FOR TRANSMITTING REFERENCE SIGNAL IN D2D COMMUNICATION

LG ELECTRONICS INC., Seo...

1. A method for transmitting a demodulation reference signal (DMRS) related to a physical sidelink broadcast channel (PSBCH) by a user equipment (UE) in a wireless communication system, the method comprising:obtaining a comb-index based on a mobility of the UE and a priority of a Vehicle to Everything (V2X) signal transmitted by the UE;
mapping a primary sidelink synchronization signal (PSSS) to two consecutive symbols in a first slot of a subframe and a secondary sidelink synchronization signal (SSSS) to two consecutive symbols in a second slot of the subframe;
mapping the DMRS to a first symbol and a second symbol in the first slot and to a third symbol in the second slot,
wherein the DMRS is mapped to a part of subcarriers in the first, the second and the third symbols based on the comb-index; and
transmitting the PSSS, the SSSS, the PSBCH and the DMRS in the subframe including 14 symbols,
wherein each of the 14 symbols has normal cyclic prefix (CP),
wherein the second symbol is located between the first symbol and the third symbol, and
wherein the first symbol is located after one symbol interval from the two consecutive symbols in the first slot, and the third symbol is located before one symbol interval from the two consecutive symbols in the second slot.

US Pat. No. 10,511,418

MEASUREMENT METHOD IN CARRIER AGGREGATION AND ASYNCHRONOUS DUAL CONNECTIVITY

Intel IP Corporation, Sa...

1. An apparatus of a base station, comprising:a controller to:
configure a first measurement gap pattern with a first measurement gap repetition period (MGRP) for a first receive (Rx) chain of a user equipment (UE);
configure one or more gaps in addition to measurement gaps of the first measurement gap pattern for the first Rx chain; and
configure a second measurement gap pattern with a second MGRP for a second Rx chain of the UE, wherein the first MGRP is different from the second MGRP; and
a transmitter, coupled to the controller, to transmit the first measurement gap pattern and the second measurement gap pattern to the UE.

US Pat. No. 10,511,415

UPLINK ACK RESOURCE ALLOCATION IN NEW RADIO

QUALCOMM Incorporated, S...

1. A method of wireless communications at a user equipment (UE), comprising:receiving, from a base station, a radio resource channel (RRC) configuration indicating multiple UE-specific uplink control information (UCI) resource sets, wherein each UE-specific UCI resource set of the multiple UE-specific UCI resource sets is different from each remaining UE-specific UCI resource set of the multiple UE-specific UCI resource sets;
determining, at the UE, a size of a payload for a UCI to be transmitted on a physical uplink control channel (PUCCH); and
determining, at the UE, a selected UE-specific UCI resource set from the multiple UE-specific resource sets for transmitting the UCI on the PUCCH based, at least in part, on the size of the payload of the UCI.

US Pat. No. 10,511,393

GEOCAST-BASED FILE TRANSFER

1. A system comprising:a first apparatus; and
a second apparatus communicatively connected with the first apparatus, the second apparatus comprising:
a processor; and
memory coupled to the processor, the memory comprising executable instructions that when executed by the processor cause the processor to effectuate operations comprising:
geocasting a plurality of geocast messages to a plurality of devices of a mobile ad hoc network, the plurality of devices comprising the first apparatus, wherein the geocast messages are associated with a plurality of chunks of an entire file;
responsive to the plurality of chunks of the entire file being sent, sending a notification to the plurality of devices that instructs the plurality of devices to commence sending requests to the second apparatus for chunks that were not received, wherein the first apparatus does not send a request for chunks that were not received based on analysis of requests of other devices of the plurality of devices;
waiting a predetermined amount of time;
if a request for a chunk of the plurality of chunks of the entire file is received prior to expiration of the predetermined amount of time:
incorporating the requested chunk into a new geocast message; and
geocasting the new geocast message; and
responsive to receiving an indication that any of the plurality of devices received the plurality of the chunks of the entire file, terminating the process of sending the chunks that were not received to remaining devices of the plurality of devices.

US Pat. No. 10,511,392

SYSTEMS, METHODS, AND COMPUTER PROGRAMS FOR WIRELESS LOCAL AREA NETWORK LOCALIZATION

BOARD OF REGENTS, THE UNI...

1. A method comprising:identifying a radio map for an area;
determining a plurality of access points within the area;
determining, via a computing device, a set of location-dependent measurements characterizing signals received from at least one of the plurality of access points;
determining a position vector corresponding to a location of the computing device based at least in part on the set of location-dependent measurements according to the formula

 where ?k is the set of reference points in group k and wk is their corresponding weights, and y=?y is the set of location-dependent measurements for the access points.

US Pat. No. 10,511,384

DEVICES AND METHODS FOR OPTICAL COMMUNICATION IN A ROTARY PLATFORM

Waymo LLC, Mountain View...

1. A system comprising:a first platform that includes a first mounting surface;
a second platform that includes a second mounting surface;
an actuator configured to rotate the first platform about an axis of rotation of the first platform;
a plurality of light sources mounted on the first mounting surface, wherein the plurality of light sources are configured to emit a plurality of light beams that diverge to form a ring-shaped light beam projected onto the second mounting surface;
a light detector mounted on the second mounting surface such that the light detector remains at least partially overlapping the ring-shaped light beam in response to the actuator rotating the first platform;
a device coupled to the first platform; and
a controller configured to:
receive data from the device,
modulate an electrical signal based on the received data to form a modulated electrical signal, and
cause transmission of the modulated electrical signal for receipt by the plurality of light sources, wherein the plurality of light sources modulate the ring-shaped light beam based on the modulated electrical signal.

US Pat. No. 10,511,378

HYBRID ANALOG/DIGITAL BEAM FORMING RAIN FADE MITIGATION

RKF Engineering Solutions...

1. A computer-implemented method comprising:determining fade conditions for one or more gateways in gateway clusters of a set of gateway clusters;
selecting a proper subset of the gateway clusters based on the fade conditions determined for the one or more gateways, wherein selecting the proper subset of the gateway clusters comprises:
deselecting a first gateway cluster of the set of gateway clusters that is currently active in data transmission with a satellite, the first gateway cluster including a plurality of gateways, and
selecting a second gateway cluster of the set of gateway clusters for inclusion in the proper subset, wherein the second gateway cluster is currently inactive for data transmission with the satellite, the second gateway cluster including a plurality of gateways;
determining a beam plan based on the proper subset of the gateway clusters; and
executing the beam plan.

US Pat. No. 10,511,377

HIGH LINEARITY SATELLITE PAYLOAD USING SOLID STATE POWER AMPLIFIERS

1. A solid state amplifier, comprising:an input
port; an
output
port;
a main arm connected between the input port and the output port, including a first main amplifier stage configured to generate a first output signal from an input signal received from the input port;
an auxiliary arm connected in parallel with the main arm between the input port and the output port, including a first auxiliary amplifier stage configured to generate a second output signal by amplifying portions of the input signal received the input port having an amplitude above a threshold level;
an input splitter configured to receive the input signal and provide it to the main arm and the auxiliary arm;
a combining circuit configured to receive the first output signal and the second output signal, generate therefrom a combined output signal and provide the combined output signal to the output port;
a first bias control circuit connected to the first main amplifier stage and configured to bias the first main amplifier stage according to a corresponding first set of control signals;
a second bias control circuit connected to the first auxiliary amplifier stage and configured to bias the first auxiliary amplifier stage according to a corresponding second set of control signals; and
a control circuit configured to generate the corresponding first set of control signals and the corresponding second sets of control signals, the first set of controls signals configured to generate the first output signal to have a specified response over a first output range when the input signal has an amplitude below the threshold level, and the corresponding second set of control signals configured relative to the corresponding first set of control signals to generate the combined output signal to have the specified response over a second output range when the input signal has an amplitude above the threshold level.

US Pat. No. 10,511,370

METHOD FOR BEAM MANAGEMENT FOR WIRELESS COMMUNICATION SYSTEM WITH BEAMFORMING

MEDIATEK INC., Hsin-Chu ...

1. A method comprising:receiving reference signals over a plurality of TX beams from a base station by a user equipment (UE) in a beamforming wireless communication network, wherein each TX beam has a TX beam identifier;
performing measurements over the plurality of TX beams and determining a corresponding beam metric value;
grouping the plurality of TX beams into multiple beam groups, wherein the grouping is determined based on an association between each TX beam and a number of UE receive panels or UE antenna subarrays; and
reporting the beam value metrics of the plurality of TX beams in an order associated with each beam group, wherein each beam group is implicitly indicated by a number of TX beams per beam group, or explicitly indicated by a beam group identifier.

US Pat. No. 10,511,364

METHOD FOR TRANSMITTING SIGNALS IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of transmitting a signal, which is transmitted by a user equipment in a wireless communication system supporting MIMO (Multiple Input Multiple Output), comprising the steps of:generating precoded SRSs (sounding reference signals) based on the N number of antenna elements coupled with the M number of transceivers (wherein M and N correspond to natural numbers, M transmitting information on grouped SRSs among the precoded SRSs to a base station,
wherein the grouped SRSs are associated with SRS ports capable of being simultaneously transmitted by the user equipment via the M number of transceivers.

US Pat. No. 10,511,361

METHOD FOR DETERMINING A PRECODING MATRIX AND PRECODING MODULE

Intel Corporation, Santa...

1. A method for determining a precoding matrix for a multi-input multi-output (MIMO) transmitter based on a weighted minimum mean square error (MMSE) algorithm, the method comprising:identically transforming a first matrix expression into a second matrix expression using a processor circuit, wherein the first matrix expression comprises a matrix inversion operation of a quadratic matrix having a rank equal to a number of antennas of the MIMO transmitter and the second matrix expression comprises a matrix inversion operation of a quadratic matrix having a rank equal to a number of receivers scheduled for the MIMO transmitter, wherein the number of antennas of the MIMO transmitter is greater than the number of receivers scheduled for the MIMO transmitter; and
precoding a data stream for transmission using a precoding matrix according to the second matrix expression, wherein the precoded data stream comprises MIMO transmitter signals.

US Pat. No. 10,511,360

METHOD AND APPARATUS FOR ESTIMATING CHANNEL IN COMMUNICATION SYSTEM SUPPORTING MIMO-BASED BEAMFORMING

Samsung Electronics Co., ...

1. A method of estimating a channel by a transmission side in a communication system supporting Multiple-Input Multiple-Output (MIMO)-based beamforming, the method comprising:acquiring a candidate channel estimation value of each of a plurality of candidate beam combinations including at least one transmission beam and at least one reception beam among transmission beams of the transmission side and reception beams of a reception side, wherein a channel estimation interval corresponding to each of the plurality of candidate beam combinations includes a serving channel estimation interval corresponding to a serving beam combination of the transmission side and the reception side, a channel gain estimation interval of one of the plurality of candidate beam combinations, and a channel estimation interval of the one of the plurality of candidate beam combinations; and
acquiring an optimal channel estimation value of the transmission side and the reception side based on the acquired candidate channel estimation values.

US Pat. No. 10,511,349

CONNECTOR AND DEVICE FOR WIRELESS TRANSMISSION OF DATA AND POWER

KONINKLIJKE PHILIPS N.V.,...

1. A connector for wireless transmission of data and power between separate devices comprising such a connector of a system, in particular of a patient monitoring system, said separate devices comprising such a connector, said connector comprising:a data transmission unit arranged for transmitting data to and/or receiving data from another device of the system having a counterpart connector,
a magnetic coupling unit for transmitting power to and/or receiving power from another device of the system having a counterpart connector by use of inductive coupling,
a detection unit for detecting the strength of magnetic coupling between the magnetic coupling unit and a magnetic coupling unit of a counterpart connector, and
a control unit for using a near-field mode by switching the data transmission unit into a low-power mode and enabling the magnetic coupling unit to transmit power to and/or receive power from another device, if the detected magnetic coupling is above a first threshold and/or its increase is above a second threshold, and for using a far-field mode by switching the data transmission unit into a high-power mode and disabling the magnetic coupling unit, if the detected magnetic coupling is below a third threshold and/or its decrease is above a fourth threshold.

US Pat. No. 10,511,337

INTEGRATIVE SOFTWARE RADIO

PHYSICAL OPTICS CORPORATI...

1. An integrative software radio embodying a single multi-radio device including functionalities that are a superset of a plurality of individual discrete radio devices, the integrative software radio comprising:a radio frequency transmitter that integrates transmission capabilities of a plurality of discrete transmitters such that the radio frequency transmitter is configured to generate a first amalgamated waveform that is a combination of individual waveforms, each individual waveform corresponding to the transmission capabilities of its respective one of the plurality of discrete transmitters, wherein the transmission capabilities each of the plurality of discrete transmitters comprise operating characteristics different from one or more of the other discrete transmitters, wherein a waveform of a discrete transmitter comprises an adjustable electromagnetic wavefront and a proprietary waveform generation component;
a radio frequency receiver that integrates reception capabilities of a plurality of discrete receivers such that the radio frequency receiver is configured to receive a plurality of waveforms generated by two or more discrete transmitters, wherein each transmitter operates according to a different set of operating characteristics;
a mission component communicatively coupled to the plurality of discrete transmitters and configured to alter the wavefront of at least one of the plurality of discrete transmitters to reduce interference among the at least one of the plurality of discrete transmitters without adjusting the proprietary waveform generation component, wherein altering the waveform comprises characterizing a non-linear response of at least one of the plurality of discrete transmitters in predicting frequency and power levels of distortion products based on the non-linear responses; and
a first superconnector comprising:
a first connector portion disposed on and physically attached to the mission component and comprising one or more first electrical connections;
a second connector portion disposed on and physically attached to the first radio device, the first super connector and comprising one or more second electrical connections complementary to the one or more first electrical connections and configured to align with the one or more first electrical connections;
wherein when the first connector portion is mated with the second connector portion the first superconnector detachably physically couples the mission component to the first radio device and the one or more first electrical connections contact with and electrically couple to their corresponding ones of the one or more second electrical connections thereby such that the first super connector electrically couples the mission component to the first radio device;
a second superconnector comprising:
a third connector portion disposed on and physically attached to the mission component and comprising one or more third electrical connections;
a fourth connector portion disposed on and physically attached to the first radio device, the third super connector and comprising one or more fourth electrical connections complementary to the one or more third electrical connections and configured to align with the one or more third electrical connections; and
wherein when the third connector portion is mated with the fourth connector portion the second superconnector detachably physically couples the mission-component to the second radio device and the one or more third electrical connections contact with and electrically couple to their corresponding ones of the one or more fourth electrical connections thereby such that the second superconnector electrically couples the mission component to the first radio device.

US Pat. No. 10,511,320

LOW DISTORTION SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) AND ASSOCIATED METHODS

Taiwan Semiconductor Manu...

1. An analog-to-digital converter (ADC) device comprising:a comparator having an output, a first input, and a second input;
a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage;
a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator,
wherein the DAC includes a capacitor network coupled to the first input having:
a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage;
one or more first capacitors also coupled to the first voltage at least one first capacitor associated with the MSB; and
a plurality of second capacitors coupled to the reference voltage, wherein the redistribution capacitor having a capacitive value that is equal to (1?N) times the total capacitance of a parallel combination of the one or more first capacitors, further wherein the second capacitors are associated with less significant bits; and
an input voltage line carrying an input voltage (VIN) switchably coupled to the first input or switchably coupled to the second input.

US Pat. No. 10,511,294

CROSS-POINT OFFSET ADJUSTMENT CIRCUIT

Finisar Corporation, Sun...

1. A differential signal offset adjustment circuit, comprising:a first circuit operatively coupled to an amplification circuit so as to receive a first one of a differential input signal including a DC offset and configured to generate a first one of a differential output signal with a positive offset based on a combination of a differential offset signal and the DC offset; and
a second circuit operatively coupled to the amplification circuit so as to receive a second one of the differential input signal including the DC offset and configured to generate a second one of the differential output signal with a negative offset based on a combination of the differential offset signal and the DC offset.

US Pat. No. 10,511,293

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a clock driver associated with a first row of the semiconductor device, the clock driver configured to output a clock signal and an inverted clock signal, the clock driver including a plurality of gate lines including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction such that the plurality of gate lines extend to at least a second row of the semiconductor device, the first gate line and the second gate line each configured to receive the clock signal, and the third gate line and the fourth gate line each configured to receive the inverted clock signal;
a master latch circuit associated with the second row of the semiconductor device and overlapping the first gate line and the third gate line extending in the first direction thereto such that the master latch circuit is configured to receive the clock signal from the first gate line and to receive the inverted clock signal from the third gate line; and
a slave latch circuit associated with the second row of the semiconductor device and overlapping the second gate line and the fourth gate line extending in the first direction thereto such that the slave latch circuit is configured to receive the clock signal from the second gate line, and to receive the inverted clock signal from the fourth gate line.

US Pat. No. 10,511,287

ACOUSTIC WAVE FILTER INCLUDING TWO TYPES OF ACOUSTIC WAVE RESONATORS

Skyworks Solutions, Inc.,...

9. A multiplexer with acoustic wave filters, the multiplexer comprising:a first acoustic wave filter coupled to a common node, the first acoustic wave filter including acoustic wave resonators of a first type and a series acoustic wave resonator of a second type coupled between the acoustic wave resonators of the first type and the common node, the acoustic wave resonators of the first type being non-temperature compensated surface acoustic wave resonators and the series acoustic wave resonator of the second type being a temperature compensated surface acoustic wave resonator; and
three other acoustic wave filters coupled to the common node and each having a respective pass band, the series acoustic wave resonator of the second type having a higher quality factor in each of the respective passbands of the three other acoustic wave filters than the acoustic wave resonators of the first type.

US Pat. No. 10,511,234

POWER INTERFACE SYSTEM FOR REDUCING POWER VARIATIONS IN AN OUTPUT POWER OF SWITCHING REGULATORS

Linear Technology LLC, M...

1. A power interface system for reducing power variations, comprising:one or more control circuits configured to control a plurality of switching regulators operating at different frequencies to provide a shared output power at an output terminal to a load, wherein each of the one or more control circuits is configured to:
receive a power variation signal resulting from a power variation in the shared output power of the plurality of switching regulators;
separate a respective frequency component from multiple frequency components of the power variation signal; and
control, based on the respective frequency component, a respective switching regulator of the plurality of switching regulators to source current to, or sink current from the the output terminal until the shared output power reaches a threshold level.

US Pat. No. 10,511,228

DC-DC CONVERTING CONTROLLER

UPI SEMICONDUCTOR CORP., ...

1. A DC-DC converting controller, coupled to an output stage and an external resistor network and providing a pulse-width-modulation signal to control the output stage to provide an output voltage, the DC-DC converting controller comprising:a sensing circuit, coupled to the output stage and providing a sensing current;
a droop current circuit, coupled to the sensing circuit and providing a droop current according to the sensing current;
a first pin, coupled to the droop current circuit and the external resistor network and receiving the droop current and a first reference voltage, wherein the first pin provides the droop current to the external resistor network to make the external resistor network provide a second reference voltage; and
a pulse-width-modulation signal control loop, coupled to the external resistor network and generating the pulse-width-modulation signal according to the second reference voltage and a feedback voltage related to the output voltage,
wherein the droop current is reduced to a default value with a default time.

US Pat. No. 10,511,221

SYSTEM FOR CONVERTING A DC ELECTRIC POWER INTO AN AC ELECTRIC POWER WITH AN ENERGY RECOVERY MODULE

IFP Energies nouvelles, ...

1. A system for converting direct electrical current into three output phases of alternating electrical current comprising three switching arms, a voltage and current variation modulation circuit comprising a capacitor for each alternating electrical current output phase and a coil wherein the system for converting comprises an electrical energy recovery module linked to the three switching arms and to the current variation modulation circuit wherein the electrical energy recovery module comprises at least one inductor and at least one switch and three branches linked at a junction with a first branch comprising a switch and a first capacitor which is located between the switch and ground, a second branch comprising a diode, and a third branch comprising an inductor; and wherein a point of the electrical energy recovery module linked to the junction between the switching arm and the capacitor of the current variation modulation circuit is in the first branch of the electrical energy recovery system module between the switch and the first capacitor.

US Pat. No. 10,511,218

GATE DRIVE CIRCUIT, THAT SUPPLIES POWER TO A GATE OF A SEMICONDUCTOR SWITCHING ELEMENT, AND CARRIES OUT A DRIVING ON AND OFF OF THE GATE

Mitsubishi Electric Corpo...

1. A gate drive circuit, comprising:a drive-on element that includes a positive electrode side driver switch and applies an on-state voltage to a gate of a drive target semiconductor element by turning on the positive electrode side driver switch; and
a drive-off element that includes a negative electrode side driver switch and applies an off-state voltage to the gate of the drive target semiconductor element by turning on the negative electrode side driver switch; wherein
a recovery circuit including a positive electrode side recovery circuit and a negative electrode side recovery circuit that are in parallel with each other and connected between output terminals of the gate drive circuit, the positive electrode side recovery circuit including a positive electrode side recovery switch, a positive electrode side reactor, and a positive electrode side capacitor which are all connected in series with each other within the positive electrode side recovery circuit and the negative electrode side recovery circuit including a negative electrode side recovery switch, a negative electrode side reactor, and a negative electrode side capacitor which are all connected in series with each other within the negative electrode side recovery circuit,
the gate drive circuit further comprises a control circuit that controls the drive-on element, the drive-off element, the positive electrode side recovery switch, and the negative electrode side recovery switch, and a charge accumulated in input capacitance of the drive target semiconductor element can be recovered when the drive target semiconductor element is turned on or turned off.

US Pat. No. 10,511,214

OSCILLATING MOTOR AND ELECTRIC CLIPPERS

Jiankun Hu, Shenzhen (CN...

1. An oscillating motor, comprising:a U-shaped magnetic yoke having a first support leg and a second support leg, and the first support leg and the second support leg are wound with coils;
a control circuit electrically connected to the coils and generating alternating pulses to generate alternating magnetic poles at end faces of the first support leg and the second support leg of the U-shaped magnetic yoke;
a swing arm swingable around a fulcrum; wherein the first support leg and the second support leg respectively extend outward from a base portion of the U-shaped magnetic yoke so as to form a U-shaped structure; the swing arm is substantially arranged in an extending direction of the first support leg and the second support leg; the swing arm is bounded by the fulcrum, an end of the swing arm close to the U-shaped magnetic yoke is an inner arm and the other end of the swing arm remote from the U-shaped magnetic yoke is an outer arm; the inner arm levers the outer arm to swing around the fulcrum in a swinging plane where the swing arm locates under the action of electromagnetic force;
a second magnetic yoke mounted at one end of the inner arm close to the U-shaped magnetic yoke for forming magnetic pathways; wherein the second magnetic yoke and the swing arm form a T-shaped structure; and
a first permanent magnet, a second permanent magnet, a third permanent magnet, and a fourth permanent magnet being fixedly mounted on the second magnetic yoke; wherein the first permanent magnet, the second permanent magnet, the third permanent magnet, and the fourth permanent magnet are orderly spaced and distributed on a same circumference centered on the fulcrum; radial end faces of the first permanent magnet and the fourth permanent magnet have a same polarity; radial end faces of the second permanent magnet and the third permanent magnet have a same polarity; the radial end faces of the first permanent magnet and the second permanent magnet have opposite polarities and are provided corresponding to an end face of the first support leg; the radial end faces of the third permanent magnet and the fourth permanent magnet have opposite polarities and are provided corresponding to an end face of the second support leg; and
end faces of the first permanent magnet and the second permanent magnet correspondingly have an air gap with the end face of the first leg; end faces of the third permanent magnet and the fourth permanent magnet correspondingly have an air gap with the end face of the second leg.

US Pat. No. 10,511,213

METHOD AND APPARATUS FOR DETERMINING MAGNETIC FLUX AND MAGNETIC FORCE IN A SOLENOID ASSEMBLY

GM Global Technology Oper...

1. A solenoid assembly comprising:a solenoid actuator having a core;
a coil configured to be wound at least partially around the core such that a magnetic flux (?) is generated when an electric current flows through the coil, the coil defining a coil turn number (N);
an armature configured to be movable based on the magnetic flux (?), the armature defining a position (x) and an armature velocity (dx/dt);
a controller operatively connected to the coil and having a processor and tangible, non-transitory memory on which is recorded instructions, execution of the instructions by the processor causing the controller to:
obtain a plurality of model matrices, including a first model matrix (A0), a second model matrix (B0) and a third model matrix (C0);
obtain a coil current (i1) and an eddy current (i2) based at least partially on an applied coil voltage (V) and at least two of the plurality of model matrices;
obtain the magnetic flux (?) based at least partially on the third model matrix (C0), the coil current (i1) and the eddy current (i2); and
control operation of the solenoid actuator based at least partially on the magnetic flux (?).

US Pat. No. 10,511,197

WIRELESS CHARGING SYSTEM WITH OBJECT DETECTION

Apple Inc., Cupertino, C...

1. A wireless power transmitting device, comprising:a coil;
wireless power transmitting circuitry coupled to the coil and configured to transmit wireless power signals to a wireless power receiving device with a receiving coil in a wireless power receiving circuit that is configured to resonate at a wireless power receiving circuit resonant frequency;
control circuitry configured to control transmission of the wireless power signals;
an oscillator coupled to the coil that is configured to apply a probe signal to the coil at a probe frequency; and
an analog-to-digital converter configured to measure signals at the probe frequency, wherein the control circuitry is configured to:
in a standby mode, determine whether an external object is present by directing the oscillator to supply the probe signal to the coil in bursts separated by respective periods of time in which no probe signals are supplied to the coil by the oscillator, wherein the probe frequency of the probe signal is the same during each of the bursts, wherein the probe frequency is equal to 101% to 150% of the wireless power receiving circuit resonant frequency, wherein each burst has a first duration greater than 0.5 milliseconds, and wherein each period of time in which no probe signals are supplied to the coil by the oscillator has a second duration greater than 100 milliseconds.

US Pat. No. 10,511,176

POWER CONVERTER

Delta Electronics, Inc., ...

1. A power converter, comprising:a pre-stage circuit, configured to receive an input voltage and convert the input voltage to a bus voltage; and
a plurality of post-stage circuits, connected in parallel to an output terminal of the pre-stage circuit, and configured to receive the bus voltage from the pre-stage circuit and each converts the bus voltage to an output voltage,
wherein the pre-stage circuit comprises a first capacitor disposed on an output side of the pre-stage circuit, and each of the post-stage circuits comprises a second capacitor disposed on an input side of the post-stage circuit,
wherein the power converter comprises an inductor disposed between the first capacitor and the second capacitor, and
wherein the second capacitor is connected in series with the inductor to define a first series branch, the first series branch is connected in parallel across the first capacitor, and a distance between the first capacitor and the second capacitor is set to satisfy both of following conditions:
at a frequency of an output current of the pre-stage circuit, an absolute value of an impedance of the first series branch is less than or equal to
times of an absolute value of an impedance of the fir capacitor and greater than or equal totimes of the absolute value of the impedance of the first capacitor, wherein 0.5?k?1;the impedance of the first series branch is capacitive at the frequency of the output current.

US Pat. No. 10,511,149

LASER DIODES WITH AN ETCHED FACET AND SURFACE TREATMENT

Soraa Laser Diode, Inc., ...

1. A display device comprising:a laser diode device comprising:
a surface region bounded by edge regions including a first edge region; and
a laser stripe overlying a portion of the surface region, the laser stripe characterized by a length in a length direction and a width in a width direction, in the length direction the laser stripe includes a first end and a second end opposite the first end, the length direction being substantially orthogonal to the first edge region, and the width direction being substantially parallel to the first edge region;
wherein the laser stripe forms a ridge that protrudes outward from the surface region and is spaced on all sides from the edge regions by portions of the surface region;
wherein the first end of the laser stripe comprises a first facet, and the second end of the laser stripe comprises a second facet, the first facet having a primary emission surface, the first facet being substantially parallel to and recessed from the first edge region in the length direction;
wherein the laser stripe is operable to emit electromagnetic radiation in a wavelength range selected from a first range of about 400 nm to about 435 nm, a second range of about 435 nm to about 480 nm, a third range of about 480 nm to about 505 nm, and a fourth range of about 505 nm to about 550 nm, and wherein the first edge region comprises a first surface-treated region that includes a laser slag material and is configured to interact with the electromagnetic radiation emitted by the laser stripe; and
a package configured with the laser diode for the display device.

US Pat. No. 10,511,146

GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD

Lightwave Logic Inc., Lo...

1. A guide transition device comprising:a platform of semiconductor material;
a monolithic semiconductor laser and a semiconductor waveguide formed as a part of the platform and designed to generate a light beam, the semiconductor waveguide defining a light input port for receiving the light beam from the monolithic semiconductor laser, the monolithic semiconductor laser and the semiconductor waveguide being positioned on a first plane;
a lower cladding layer, a polymer core, and an upper cladding layer forming a polymer waveguide and included polymer modulator positioned on the platform at least partially on the semiconductor waveguide, the polymer waveguide and polymer modulator being on a second plane different than the first plane with a first end defining a light output port on the second plane, the light output port designed to couple a received light beam to output equipment; and
plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane, the plane shifting apparatus including one or more digital gratings and one or more angular deflection surfaces each designed to deflect the light beam approximately ninety degrees, the plane shifting apparatus being coupled to transfer the light beam to the light output port on the second plane.

US Pat. No. 10,511,124

ELECTRICAL PLUG CONNECTION

Robert Bosch GmbH, Stutt...

1. An electrical plug connection comprising:a plug that includes:
a housing that includes a plurality of electrical plug contacts; and
an operating element that is moveably fastened onto the housing and that includes
a sliding track;
a plug module that includes a plurality of complementary plug contacts, which, in a completely plugged-in position of the plug on the plug module, electrically contact the electrical plug contacts;
a pin attached to the plug module and that is guided in the sliding track, such that, during a movement of the operating element relative to the housing, a force is transmittable from the sliding track to the pin so that the plug and the plug module are movable toward each other in a plug-in direction and movable away from each other opposite to the plug-in direction, wherein the sliding track includes at least one first section and at least one second section oriented such that plugging of the plug into the plug module in the plug-in direction and detaching of the plug from the plug module opposite to the plug-in direction each is carried out by two movements of the operating element respectively in a first movement direction and in a second movement direction that is opposite the first movement direction, wherein the operating element is a lever that is rotatable relative to the housing of the plug.

US Pat. No. 10,511,111

CONDUCTOR CONNECTION STRUCTURE OF LAMINATED WIRING BODY

YAZAKI CORPORATION, Toky...

1. A conductor connection structure of a laminated wiring body comprising:a plurality of plate wiring members which are made of a conductive material and stacked to each other;
an insulating layer which is arranged between the vertically-adjacent plate wiring members to insulate the vertically-adjacent plate wiring members;
a connection portion which is provided in an upper surface of each of the plate wiring members on a way in an extending direction of the plate wiring members; anda leading-out portion configured to permit a mating connector to be electrically connected to the connection portion of a lower plate wiring member among the plurality of plate wiring member while avoiding an upper plate wiring member among the plurality of plate wiring member, the lower plate wiring member is arranged at a layer lower than the upper plate wiring member in the laminated wiring body,wherein each of the plate wiring members terminates at a front end, a rear end, a first lateral edge and a second lateral edge, the first and second lateral edges extend from the front end to the rear end, and
wherein each of the plate wiring members has a width that is measured from the first lateral edge to the second lateral edge, the width is uniform from the front end to the rear end.

US Pat. No. 10,511,102

FEEDER CIRCUIT

Mitsubishi Electric Corpo...

1. A feeder circuit comprising:a first line having a first end and a second end;
a second line having a first end and a second end;
a third line having a first end and a second end;
a first combiner connected to the second end of the first line and the second end of the second line, and configured to combine signals output from both the second end of the first line and the second end of the second line;
a first coupling portion configured to electrically couple a portion of the first line and a portion of the third line to each other; and
a second coupling portion configured to electrically couple a portion of the second line and a portion of the third line to each other in a manner that allows a signal reaching the first combiner from the first end of the third line through the first coupling portion and a signal reaching the first combiner from the first end of the third line through the second coupling portion, to be cancelled out.

US Pat. No. 10,511,100

INKJET PRINTED FLEXIBLE VAN ATTA ARRAY SENSOR

Georgia Tech Research Cor...

1. A radio-frequency responsive device, comprising:(a) a dielectric substrate having a first side and an opposite second side;
(b) a Van Atta array reflector printed on the first side of the dielectric substrate that reflects an incident signal at a predetermined radio frequency at an incident angle; and
(c) a conductive ground layer disposed adjacent the second side of the dielectric substrate,
wherein the Van Atta array comprises a plurality of linear antenna array pairs, each antenna array pair including two antenna arrays that are electrically coupled to each other and that are spaced apart from each other so that the antenna array pairs form a reflected beam in response to an incident signal that is emitted in a direction corresponding to a source of the incident signal, and
wherein each linear antenna array includes a plurality of patch antenna elements, each patch antenna element including a first port that is electrically coupled to a first wire and a second port, disposed orthogonally to the first port, that is electrically coupled to a second wire.

US Pat. No. 10,511,094

ANTENNA ASSEMBLY FOR A COMMUNICATION SYSTEM

TE Connectivity Corporati...

1. A communication system comprising:an antenna assembly having an antenna element and a transmission line terminated to the antenna element, the antenna element having a substrate and a dual dipole antenna circuit including a low-band ground terminal, a low-band feed terminal, a high-band ground terminal and a high-band feed terminal, the transmission line having at least one feed line electrically connected to the dual dipole antenna circuit and at least one ground line electrically connected to the dual dipole antenna circuit; and
a housing holding the antenna assembly, the housing including an upper shell and a lower shell meeting at an interface, the upper shell having an inner end at the interface and the lower shell having an inner end at the interface, the upper shell including an upper strain relief component at the inner end of the upper shell, the lower shell including a lower strain relief component at the inner end of the lower shell aligned with the upper strain relief to receive the transmission line, the upper shell having an upper locating feature, the lower shell having a lower locating feature, the upper locating feature interfacing with the lower locating feature to locate the upper shell relative to the lower shell.

US Pat. No. 10,511,089

ANTENNA DEVICE AND ELECTRONIC APPARATUS

MURATA MANUFACTURING CO.,...

1. An antenna device comprising:a first system coil antenna including a first coil conductor wound around a first winding axis and a first coil opening surrounded by the first coil conductor; and
a second system coil antenna including a second coil conductor wound around a second winding axis extending in a second winding axis direction different from a first winding axis direction in which the first winding axis extends, and a second coil opening surrounded by the second coil conductor; wherein
when viewed from the first winding axis direction, the second coil conductor is positioned within a first region including the first coil conductor and the first coil opening;
the second coil conductor includes a first conductor section and a second conductor section on opposed sides of the second winding axis; and
the first conductor section or the second conductor section does not overlap with any other portion of the second coil conductor when viewed from the first winding axis direction.

US Pat. No. 10,511,088

ANTENNA SYSTEM

Huawei Technologies Co., ...

1. An antenna system, comprising:a radiating element, a strip line that has a hollow cavity, and an inner conductor disposed in the hollow cavity, wherein:
the radiating element comprises: at least two radiation baluns, radiation arms that are in one-to-one correspondence with and are connected to the radiation baluns, and feeding inner cores that are in one-to-one correspondence with the radiation arms;
an upper wall of the strip line is a strip line ground plane, and the radiation baluns are fastened on the strip line ground plane and are electrically connected to the strip line ground plane;
radiation arms that are in a same polarization direction in the radiating element are corresponding to one inner conductor, and the radiation arms that are in the same polarization direction are electrically connected to the inner conductor by using corresponding feeding inner cores;
the radiating element is a dual-polarization radiating element, and the dual-polarization radiating element comprises a radiation arm whose polarization direction is positive 45 degrees and a radiation arm whose polarization direction is negative 45 degrees; and
there are two inner conductors, the radiation arm whose polarization direction is positive 45 degrees is electrically connected to one inner conductor by using a corresponding connected feeding inner core, and the radiation arm whose polarization direction is negative 45 degrees is electrically connected to the other inner conductor by using a corresponding connected feeding inner core.

US Pat. No. 10,511,084

ANTENNA SYSTEM WITH ANTENNA SWAPPING AND ANTENNA TUNING

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a housing having peripheral conductive housing structures that run around at least first, second, third, and fourth edges of the housing, wherein the first edge opposes the third edge and the second edge opposes the fourth edge;
an antenna ground, wherein the antenna ground is formed at least partly from conductive portions of the housing;
a first dielectric-filled gap in the peripheral conductive housing structures along the first edge of the housing;
a second dielectric-filled gap in the peripheral conductive housing structure along the third edge of the housing; and
an antenna that includes the antenna ground, an antenna resonating element arm formed from a segment of the peripheral conductive housing structures extending from the first dielectric-filled gap to the second dielectric-filled gap, and an antenna feed coupled to the segment of the peripheral conductive housing structures and the antenna ground.

US Pat. No. 10,511,076

RF COUPLER INCLUDING VERTICALLY STACKED COUPLING SECTIONS HAVING CONDUCTIVE LAYERS DISPOSED BETWEEN THE COUPLING SECTIONS AND THE COUPLER INCLUDING A SURROUNDING ELECTRIC SHIELD

Raytheon Company, Waltha...

2. An RF coupler, comprising:a plurality of electrically connected, vertically stacked, coupling sections, each one of the coupling sections comprising:
a pair of dielectrically separated strip conductors, the strip conductors being separated by an electromagnetic coupling region disposed between the pair of strip conductors;
a plurality of electrically conductive layers, each one of the electrically conductive layers being disposed between a pair of the vertically stacked coupling sections; and
an electric shield disposed over top and sides of the coupling sections;
a solid dielectric structure disposed between the plurality of electrically connected, vertically stacked, coupling sections and the electric shield; and
wherein the dielectric structure comprises:
a plurality of dielectric layers, at least one of the dielectric layers having a horizontal portion and a vertical portion, the vertical portion being disposed at an end of the horizontal portion;
wherein each one of the plurality of dielectric layers is disposed over at least one electromagnetic coupling region; and
wherein the vertical portion of the at least one of the plurality of dielectric layers being disposed between a corresponding one of the plurality of vertically stacked, coupling sections layers and a corresponding portion of an inside surface of the electric shield.

US Pat. No. 10,511,061

LOW TEMPERATURE LIQUID METAL BATTERIES FOR ENERGY STORAGE APPLICATIONS

UNIVERSITY OF KENTUCKY RE...

1. A liquid metal battery comprising a vessel, the vessel holding a first electrode of liquid tin (Sn) and a second electrode of liquid bismuth (Bi) in a co-axial and co-planar ring-disk electrode geometry arrangement, wherein the first electrode and the second electrode are in contact with a eutectic electrolyte blanketed above.

US Pat. No. 10,511,046

FUEL CELL ASSEMBLING METHOD AND FUEL CELL ASSEMBLING APPARATUS

Toyota Jidosha Kabushiki ...

1. A fuel cell assembling method comprising:fixing a first end portion of a coupling member to a first end plate;
temporarily fixing a tensile load application device to a second end portion of the coupling member by engaging a plurality of hooks at distal ends of arm portions of the tensile load application device in a plurality of holes at the second end portion of the coupling member;
fixing, in a state where a prescribed tensile load is applied to the coupling member and a prescribed compressive load is applied to a cell stack of a fuel cell by a compressive load application device, the second end portion of the coupling member to a second end plate by a fixing device, wherein:
the fixing device is a swaging device, and
the second end portion of the coupling member is swaged inward in a thickness direction of the coupling member by the swaging device; and
removing the tensile load application device and the fixing device from the second end portion of the coupling member, and removing the compressive load application device from the cell stack, wherein:
the prescribed compressive load applied to the cell stack is maintained after removal of the tensile load application device and the fixing device from the second end portion, and removal of the compressive load application device from the cell stack.

US Pat. No. 10,511,032

FUEL CELL WITH PURGE MANIFOLD

AUDI AG, Ingolstadt (DE)...

1. A fuel cell comprising:an electrode assembly including an electrolyte between an anode and a cathode for generating an electric current and byproduct water;
a porous plate adjacent the electrode assembly, the porous plate including reactant gas channels for delivering a reactant gas to the electrode assembly; and
a separator plate adjacent the porous plate such that the porous plate is between the electrode assembly and the separator plate, the separator plate including a reactant gas inlet manifold and a reactant gas outlet manifold in fluid connection with the reactant gas channels, and a purge manifold in fluid connection with the porous plate such that limiting flow of the reactant gas through the reactant gas outlet manifold and opening the purge manifold under a pressure of the reactant gas in the reactant gas channels drives the byproduct water through pores in the porous plate toward the purge manifold for removal from the fuel cell.

US Pat. No. 10,511,026

ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, BATTERY PACK, AND VEHICLE

Kabushiki Kaisha Toshiba,...

1. A negative electrode active material for a nonaqueous electrolyte battery, comprising:a particle of silicon oxide enveloping particles of silicon;
a carbonaceous substance covering the particle of silicon oxide enveloping particles of silicon; and
a phase comprising a silicate compound mixed with a conductive assistant, the phase being interposed between the particle of silicon oxide enveloping particles of silicon and the carbonaceous substance,
wherein
the silicate compound is at least one compound selected from the group consisting of MgSiO3, Mg2SiO4, TiSiO4, Mn2SiO4, FeSiO3, Fe2SiO4, Co2SiO4, Ni2SiO4, Al2SiO5, ZrSiO4, Y2SiO5, and Y2Si2O7.

US Pat. No. 10,511,023

FLUORINATED COAL DERIVED CARBONS AND ELECTRODES FOR USE IN BATTERY SYSTEMS AND SIMILAR

UNIVERSITY OF KENTUCKY RE...

1. An electrode comprising fluorinated coal particles, wherein said particles comprise fluorinated carbon at a ratio of between about CF0.3 and CF1.4.

US Pat. No. 10,511,005

BATTERY PACK AND VEHICLE CONTAINING BATTERY PACK

LG CHEM, LTD., Seoul (KR...

1. A battery pack, comprising:a pack case forming an appearance of the battery pack;
a battery module assembly provided in the pack case and having at least one battery module; and
a service plug configured to electrically connect the battery module assembly or cut off the electric connection of the battery module assembly, the service plug having a plug bus bar directly connected to the battery module assembly, the service plug including:
a plug body mounted to the pack case, the plug bus bar being provided at a lower portion of the plug body; and
a plug cover detachably mounted to the plug body,
wherein the plug body has a bus bar opening provided above the plug bus bar to expose the plug bus bar when the plug cover is separated,
wherein the plug bus bar is coupled to the battery module assembly by means of at least one coupling member, and
wherein the at least one coupling member passes through the bus bar opening when the plug bus bar and the battery module assembly are coupled.

US Pat. No. 10,511,002

BATTERY MODULE

PANASONIC INTELLECTUAL PR...

1. A battery module comprising:a case body for storing a plurality of cells each having an exhaust gas valve;
an exhaust passage for releasing an exhaust gas to an outside of the case body, the exhaust gas having come from the plurality of cells; and
a flow route changing unit disposed in the exhaust passage, the flow route changing unit being used for elongating a flow route of the exhaust gas from an upstream side to a downstream side of the exhaust passage by changing a flow direction of the exhaust gas a plurality of times in a zigzag manner along at least one direction of a width direction and a height direction of the exhaust passage,
wherein the flow route changing unit includes a plurality of plate portions, each of the plurality of plate portions includes a plurality of paths for passing the exhaust gas.

US Pat. No. 10,511,001

COMPACT BATTERY-BASED ENERGY STORAGE SYSTEMS

Sinexcel Inc., Rancho Cu...

1. A battery-based energy storage device comprising:a plurality of rechargeable battery packs;
a battery chamber configured to host the plurality of rechargeable battery packs;
an operation chamber separated from the battery chamber by at least an insulation board;
an energy storage inverter mounted on the operation chamber, wherein the energy storage inverter is configured to convert AC to DC when charging a rechargeable battery pack in the plurality of rechargeable battery packs and to convert DC to AC when providing power to an external device from a rechargeable battery pack in the plurality of rechargeable battery packs;
a battery control box mounted on the operation chamber and configured to control one or more operations of the plurality of rechargeable battery packs;
a first door rotatably mounted on the battery chamber;
a second door rotatably mounted on the battery chamber, wherein the first door and the second door open outward and are on opposite sides of the battery chamber;
a third door rotatably mounted on the operation chamber; and
an air conditioner mounted on the third door, wherein the insulation board includes a protruding portion that covers at least some space above the operation chamber, so as to create an airway path from the plurality of rechargeable battery packs to the air conditioner.

US Pat. No. 10,511,000

BATTERY PACK

SAMSUNG SDI CO., LTD., Y...

1. A battery pack, comprising:a battery with an electrode terminal connected to a lead tab;
a metal holder to accommodate the battery; and
an insulating holder spacing apart the metal holder from the battery, the insulating holder including a coupling part, the coupling part coupling between the insulation holder and the metal holder, and the lead tab being connected to the electrode terminal through an opening in the insulating holder,
wherein the insulating holder has a ring shape that at least partially surrounds a circumference of an end of the battery.

US Pat. No. 10,510,998

ELECTRODE FEEDTHRU HAVING PIN ATTACHED TO WIRE THEREIN AND METHOD OF MANUFACTURING

PACESETTER, INC., Sylmar...

1. A feedthru assembly for an electrolytic device, the feedthru assembly comprising:a ferrule having a bore, the bore having a reduced diameter portion forming a shoulder;
an electrode assembly positioned within the ferrule, the electrode assembly comprising:
an electrode wire including a first portion and a second portion; and
a crimp pin including a crimp terminal portion and a pin terminal portion, the crimp terminal portion being connected to the first portion of the electrode wire to form a connected portion of the electrode assembly, the connected portion being positioned within the bore of the ferrule, the second portion of the electrode wire extending out from the ferrule in a direction away from the crimp pin; and
an elastomer disposed in the bore of the ferrule between the ferrule and the electrode assembly, the elastomer electrically isolating the ferrule from the electrode assembly and encapsulating at least the connected portion of the electrode assembly, the shoulder of the ferrule extending into the elastomer.

US Pat. No. 10,510,991

MASK STRUCTURE FOR PIXEL LAYOUT OF OLED PANEL, OLED PANEL AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A mask structure for pixel layout of an OLED panel, comprising:a deposition mask patterned on a substrate and surrounding each pixel region, the deposition mask comprising a first deposition wall and a second deposition wall arranged oppositely in pairs in a first direction, a third deposition wall and a fourth deposition wall arranged oppositely in pairs in a second direction intersecting the first direction, as well as a fifth deposition wall and a sixth deposition wall arranged oppositely in pairs in the first direction,
wherein the pixel layout comprises a first sub-pixel region adjacent to the second deposition wall, a second sub-pixel region adjacent to the first deposition wall and a third sub-pixel region adjacent to the fourth deposition wall.

US Pat. No. 10,510,988

ANTI-REFLECTION FILM AND FLEXIBLE DISPLAY DEVICE INCLUDING ANTI-REFLECTION FILM

WUHAN TIANMA MICRO-ELECTR...

1. An anti-reflection film, comprising:a linear polarization film stretched in a first stretching direction; and
a phase delay film stretched in a second stretching direction;
wherein when a light beam passes through the linear polarization film, the light beam is converted into a linear polarized light, and when the light beam passes through the phase delay film, the phase delay film changes a phase of the light beam,
wherein a first acute angle ? is formed between the first stretching direction and the second stretching direction, and
wherein the anti-reflection film has a folding axis, and a vertical line of the folding axis is located within the first acute angle ? in a plane of the anti-reflection film.

US Pat. No. 10,510,987

DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A method for manufacturing a display panel, comprising steps of:forming an encapsulation structure layer on a display motherboard to obtain a panel motherboard, the encapsulation structure layer comprising at least one encapsulation film layer, and the at least one encapsulation film layer overlying a surface of the display motherboard;
forming a cutting groove on the encapsulation structure layer along a cutting line of the panel motherboard;
filling the cutting groove with an isolation material, the isolation material having greater flexibility than the encapsulation film layer in contact with the isolation material; and
cutting the panel motherboard from the isolation material along the cutting line to obtain the display panel.

US Pat. No. 10,510,986

ENCAPSULATION STRUCTURE FOR FLEXIBLE DISPLAY AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. An encapsulation structure for a flexible display having an OLED lighting device on a flexible substrate, the encapsulation structure disposed on the OLED lighting device, comprising a stack of layers for preventing moist from permeating into the OLED lighting device; wherein the stack of layers comprising at least one first organic layer and at least two inorganic layers wrapping the at least one first organic layer; and two inorganic layers of the stack of layers have interfacing faces that contact each other and separate the at least one first organic layer into a plurality of independent geometric regions; wherein the stack of layers comprise one or more first layer sets stacked together; each first layer set comprises two inorganic layers and a first organic layer wrapped between the two inorganic layers; and the two inorganic layers of each first layer set have interfacing faces that contact each other and separate the first organic layer into a plurality of independent geometric regions; wherein the first organic layer comprises a plurality of independent blocks; each block has a spindle shape whose cross-sectional area decreases from a middle section towards its two lateral ends.

US Pat. No. 10,510,983

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a sealant, the method comprising:forming an organic-sealant on a first substrate;
providing a source gas to a free volume of the organic-sealant; and
providing a reactive gas into the organic-sealant into which the source gas is introduced,
wherein an inorganic material is formed in the free volume of the organic-sealant, by reacting the source gas and the reactive gas.

US Pat. No. 10,510,982

DISPLAY SUBSTRATE, METHOD FOR FABRICATING THE SAME, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising functional films, wherein at least one of the functional films comprises a protrusion array on a side away from the display substrate, and wherein at least one protrusion portions of the protrusion array are configured to be embedded into a frame sealant between the display substrate and another display substrate, during assembling the display substrate with the another display substrate;wherein the protrusion array comprises protrusion sub-arrays, each of the protrusion sub-arrays comprises a flat portion, and the at least one protrusion portions are arranged on the flat portion;
wherein the functional films comprise a first functional film and a second functional film, the first functional film contacts the display substrate on a side, and contacts a side of the second functional film on the other side, the second functional film comprises the protrusion array on a side away from the display substrate, and the flat portion and the at least one protrusion portions are arranged on the first functional film;
wherein the functional films further comprise a third functional film, the third functional film covers the flat portion, a thickness of the third functional film is smaller than a thickness of the protrusion portions, the third functional film is provided with at least one via holes, and a top of the at least one protrusion portions passes through the via holes.

US Pat. No. 10,510,956

COUPLED QUANTUM DOT MEMRISTOR

Oxford University Innovat...

1. A quantum memristor, comprising:a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2),
a source electrode,
a drain electrode, and
a bath electrode,
wherein said source electrode and said drain electrode are coupled via quantum tunneling to QD1 and said bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

US Pat. No. 10,510,955

PHASE CHANGE MEMORY

STMicroelectronics (Croll...

1. A phase change memory, comprising:a silicon oxide layer;
a silicon nitride layer on top of the silicon oxide layer;
a conductive via having an upper part that extends through the silicon nitride layer and a lower part that extends through the silicon oxide layer;
a layer of phase change material;
a metal resistive element having a first part that extends between a bottom surface of the layer of phase change material and an upper end of the conductive via and having a second part that extends beyond a peripheral edge of the conductive via with a bottom surface of the second part being in direct contact with a surface of the silicon nitride layer.

US Pat. No. 10,510,954

PHASE CHANGE RANDOM ACCESS MEMORY DEVICE

Taiwan Semiconductor Manu...

1. A memory device, comprising:a first conductive column structure extending entirely through a first dielectric layer, wherein the first conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to a first end of the shell portion and disposed below the core structure, wherein the shell portion comprises a conductive layer;
a first phase change material layer formed over the first dielectric layer, wherein a lower boundary of the first phase change material layer contacts at least a first portion of a second end of the shell portion, the second end being opposite the first end;
a second dielectric layer disposed above the first phase change material layer; and
a second conductive column structure extending through the second dielectric layer, wherein the second conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to one end of the shell portion and disposed below the core structure,
wherein an upper boundary of the first phase change material layer contacts the end portion of the second conductive column.

US Pat. No. 10,510,951

LOW TEMPERATURE FILM FOR PCRAM SIDEWALL PROTECTION

Taiwan Semicondutor Manuf...

1. A method for forming a phase change random access memory (PCRAM) device, the method comprising:forming a memory stack over an insulator layer;
performing a first etch process to pattern the memory stack defining a memory cell, wherein the memory cell comprises a top electrode overlying a dielectric layer, wherein the dielectric layer comprises a center region laterally between a first outer region and a second outer region, wherein an etchant used in the first etch process creates a compound in the first and second outer regions, and wherein the compound has a first melting point temperature; and
performing a first deposition process to form a first sidewall spacer over the memory cell, wherein the first sidewall spacer is in direct contact with outer sidewalls of the memory cell, and wherein the first deposition process reaches a first maximum temperature less than the first melting point temperature.

US Pat. No. 10,510,950

MAGNETORESISTIVE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive memory device comprising:a first magnetic layer having a variable magnetization direction;
a second magnetic layer, a magnetization direction of the second magnetic layer being invariable;
a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer; and
a second nonmagnetic layer provided on the first magnetic layer, which is opposite the first nonmagnetic layer, wherein
the first magnetic layer having a stacked layer structure in which an amorphous magnetic material layer is sandwiched between crystalline magnetic material layers,
the magnetoresistive memory device further comprising
nonmagnetic material layers provided between one of the crystalline magnetic material layers and the amorphous magnetic material layer, and between the other crystalline magnetic layer and the amorphous magnetic material layer, respectively.

US Pat. No. 10,510,949

MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic memory device, comprising:a metal-containing layer including a first portion, a second portion, a third portion located between the first portion and the second portion, a fourth portion located between the third portion and the second portion, and a fifth portion located between the third portion and the fourth portion;
a first magnetic layer separated from the third portion in a first direction crossing a second direction, the second direction being from the first portion toward the second portion;
a second magnetic layer provided between the first magnetic layer and a portion of the third portion;
a first intermediate layer including a portion provided between the first magnetic layer and the second magnetic layer, the first intermediate layer being nonmagnetic;
a third magnetic layer separated from the fourth portion in the first direction;
a fourth magnetic layer provided between the third magnetic layer and a portion of the fourth portion;
a second intermediate layer including a portion provided between the third magnetic layer and the fourth magnetic layer, the second intermediate layer being nonmagnetic; and
a controller electrically connected with the first portion, the second portion, and the fifth portion,
a length along a third direction of the third portion being longer than a length along the third direction of the second magnetic layer, the third direction crossing a plane including the first direction and the second direction,
the length along the third direction of the third portion being longer than a length along the third direction of the fifth portion,
the controller being configured to implement:
supplying a first current from the first portion toward the fifth portion, and a second current from the second portion toward the fifth portion; and
supplying a third current from the fifth portion toward the first portion, and a fourth current from the fifth portion toward the second portion.

US Pat. No. 10,510,937

INTERCONNECTION BY LATERAL TRANSFER PRINTING

X-Celeprint Limited, Cor...

1. A transfer print structure, comprising:a destination substrate having a substrate surface and one or more substrate conductors disposed on or in the destination substrate; and
one or more interconnect structures disposed on and protruding from the destination substrate in a direction orthogonal to the substrate surface, each of the one or more interconnect structures comprising one or more notches, each of the one or more notches (i) having an opening on an edge of the interconnect structure and extending at least partially through the interconnect structure in a direction parallel to the substrate surface from the edge of the interconnect structure, (ii) comprising a notch conductor disposed at least partially in the notch and (iii) electrically connected to at least one of the one or more substrate conductors.

US Pat. No. 10,510,919

METHOD FOR ENHANCING THE EFFICIENCY OF A SOLAR MODULE BY SUBJECTING IT TO EXTREMELY-LOW-FREQENCY EMR

1. A method for enhancing the efficiency of a photovoltaic module comprising the steps of:subjecting an active surface of the photovoltaic module to electromagnetic radiation from at least one electric arc generated by ionizing atmospheric gases between a pair of spaced-apart electrodes, said at least one electric arc being insulated from the active surface of the photovoltaic module by a solid insulative material, and said at least one electric arc being maintained at a uniform distance from the active surface, said uniform distance having a range of about 3 mm to 13 mm.

US Pat. No. 10,510,911

CONTROL OF SURFACE PROPERTIES BY DEPOSITION OF PARTICLE MONOLAYERS

NANOCLEAR TECHNOLOGIES IN...

1. A method comprising:functionalizing a surface with a monolayer of a first functional group by contacting a first fluid to the surface;
removing an excess quantity of the first fluid once the monolayer of the first functional group is formed on the surface;
functionalizing a first plurality of particles with a second functional group by contacting a second fluid to the first plurality of particles, the second functional group chosen so as to attach to the first functional group;
removing an excess quantity of the second fluid once the second functional group has functionalized the first plurality of particles;
forming a first monolayer of particles on the surface, by contacting the functionalized first plurality of particles to the functionalized surface and attaching the first functional group to the second functional group;
functionalizing the first monolayer of particles with a monolayer of a third functional group by contacting a third fluid to the first monolayer of particles; and
removing an excess quantity of the third fluid once a monolayer of the third functional group is formed on first monolayer of particles,
wherein the particles of the first plurality of particles have lateral dimensions less than 100 micrometers.

US Pat. No. 10,510,906

MOS CAPACITOR, SEMICONDUCTOR FABRICATION METHOD AND MOS CAPACITOR CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A metal-oxide-semiconductor (MOS) capacitor circuit, comprising:a front-end-of-the-line (FEOL) field effect transistor (FET), comprising:
a source region and a drain region positioned in a semiconductor substrate;
a shallow trench isolation (STI) positioned in a first diffusion region only; and
a gate over the semiconductor substrate, the shallow trench isolation (STI) being laterally abutting the gate; and
a biasing circuit for providing bias to the FET;
wherein the source region and the drain region are positioned in the first diffusion region, the first diffusion region is positioned in a second diffusion region having a polarity opposite to a polarity of the first diffusion region; and
wherein the FET operates in an accumulation mode, and the biasing circuit supplies a first supply voltage to the first and second diffusion regions, and supplies a second supply voltage to the gate, wherein subtracting the first supply voltage from the second supply voltage is a negative value.

US Pat. No. 10,510,901

THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A thin film transistor, comprising a gate electrode, an active layer, a source electrode, and a drain electrode, wherein,the source electrode and the drain electrode each include a first conductive layer and a second conductive layer;
the first conductive layer is provided on the active layer and directly contacts the active layer;
in an etching liquid, an etching rate of a material of the first conductive layer is greater than an etching rate of a material of the active layer;
the second conductive layer is provided on a side, facing away from the active layer, of the first conductive layer and does not directly contact the active layer, wherein a conductivity of the second conductive layer is greater than a conductivity of the first conductive layer; and
the material of the first conductive layer comprises one or more of oxygen-doped zinc nitride, silicon-doped zinc oxide, germanium-doped zinc oxide, titanium-doped zinc oxide, hafnium-doped zinc oxide, yttrium-doped zinc oxide, zirconium-doped zinc oxide, and indium-doped cadmium oxide.

US Pat. No. 10,510,900

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a gate line and a data line that are provided on the substrate and are insulated from each other;
a thin film transistor that is connected with the gate line and the data line; and
a pixel electrode that is connected with the thin film transistor,
wherein at least one of the gate line and the data line comprises:
a metal layer; and
a blocking layer that contacts the metal layer, and
wherein the blocking layer is formed of a metal oxide and comprises:
a first metal from a first group including molybdenum (Mo) and tungsten (W);
a second metal from a second group including vanadium (V), niobium (Nb), zirconium (Zr), and tantalum (Ta); and
oxygen (O), and
wherein a content of the second metal is about 3 to 10 wt % with respect to entire content of the blocking layer;
wherein the metal layer comprises a first layer that includes at least one of aluminum (Al) and copper (Cu); and
wherein the metal layer further comprises a second layer that is provided between the substrate and the first layer, and the second layer, the first layer, and the blocking layer are sequentially stacked on the substrate.

US Pat. No. 10,510,895

DEVICE AND METHOD OF DIELECTRIC LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a semiconductor substrate;
a gate stack over the semiconductor substrate; and
an interlayer dielectric over the semiconductor substrate and surrounding the gate stack, wherein the interlayer dielectric comprises:
a liner layer lining the gate stack; and
a filling layer over the liner layer, wherein the filling layer comprises a metal-contained ternary dielectric material.

US Pat. No. 10,510,887

METHOD FOR FABRICATING A STRAINED STRUCTURE AND STRUCTURE FORMED

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a fin structure disposed on a substrate;
a gate structure disposed over the fin structure, the gate structure including a sidewall spacer;
an isolation structure disposed in the substrate;
a source/drain feature associated with the fin structure, the source/drain feature including:
a first strained layer that is in direct contact with the isolation structure;
a dielectric layer that is in direct contact with the fin structure, wherein the first strained layer is disposed between the isolation structure and the dielectric layer thereby preventing the dielectric layer from interfacing with the isolation structure; and
a second strained layer overlying the first strained layer and in direct contact with the fin structure and the sidewall spacer, wherein the second strained layer does not extend under the sidewall spacer such that no portion of any source/drain feature is disposed under the sidewall spacer.

US Pat. No. 10,510,885

TRANSISTOR WITH ASYMMETRIC SOURCE/DRAIN OVERLAP

International Business Ma...

1. A method of fabricating an asymmetric field-effect transistor device, comprising:obtaining a structure including a semiconductor substrate having a first portion including a recess extending vertically therein, a second portion lacking a recess, and a channel region between the first and second portions, the recess being formed between a pair of dummy gates and including undercut portions extending beneath the dummy gates;
epitaxially growing an embedded source region within the recess in the first portion of the semiconductor substrate;
epitaxially growing a cladded drain region on the second portion of the semiconductor substrate, wherein the embedded source region and the cladded drain region are grown simultaneously;
depositing a gate dielectric layer over the channel region of the semiconductor substrate, and
forming a metal gate on the gate dielectric layer, wherein forming the metal gate includes replacing at least one of the dummy gates with the metal gate.

US Pat. No. 10,510,883

ASYMMETRIC SOURCE AND DRAIN STRUCTURES IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device, comprising:etching a first and a second source/drain structures on a first and a second fin structures in a first and a second active region, respectively, on a substrate by an etching gas mixture including a sulfur containing passivation gas, wherein the etching gas mixture etches the first source/drain structure at a faster etching rate than etching the second source/drain structure, the etching forming the first source/drain structure in the first active region having a first vertical height less than a second vertical height formed in the second source/drain structure in the second active region, wherein the first source/drain structure is n-type and the second source/drain structure is p-type.

US Pat. No. 10,510,882

EMBEDDED JFETS FOR HIGH VOLTAGE APPLICATIONS

Taiwan Semiconductor Manu...

15. A device comprising:a semiconductor substrate; and
a Junction Field-Effect Transistor (JFET) formed at a surface region of the semiconductor substrate, wherein the JFET comprises:
a source region and a drain region of a first conductivity type;
a first conductive feature between the source region and the drain region;
a first plurality of current channels formed of semiconductor regions of a first conductivity type;
a first plurality of well regions of a second conductivity type opposite to the first conductivity type, wherein the first plurality of well regions are electrically connected to the first conductive feature, and are configured to receive voltages of the first conductive feature and to pinch off the first plurality of current channels;
a second current channel having portions lower than the first plurality of well regions;
a second conductive feature, wherein the source region and the first conductive feature are between the second conductive feature and the drain region; and
a second well region of the second conductivity type electrically connected to the second conductive feature, wherein the second well region is configured to receive voltages of the second conductive feature and to pinch off the second current channel.

US Pat. No. 10,510,879

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising:a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer;
a plurality of control electrodes provided respectively in a plurality of trenches, the plurality of trenches having depths into the first semiconductor layer from a top surface of the third semiconductor layer, the plurality of control electrodes having ends positioned in the first semiconductor layer;
an insulating region provided between a first control electrode and a second control electrode of the plurality of control electrodes, the first control electrode and the second control electrode being adjacent to each other in a first direction along an interface between the first semiconductor layer and the second semiconductor layer, the insulating region extending in a second direction from the third semiconductor layer toward the first semiconductor layer, the insulating region having an end positioned in the first semiconductor layer, the end of the insulating region being positioned at a level in the second direction lower than the level in the second direction of the ends of the plurality of control electrodes;
a fourth semiconductor layer of the second conductivity type provided between the insulating region and the first semiconductor layer, between the insulating region and the first control electrode, and between the insulating region and the second control electrode;
a first insulating film provided between the first control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the first insulating film positioned between the first control electrode and the fourth semiconductor layer;
a second insulating film provided between the second control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the second insulating film positioned between the second control electrode and the fourth semiconductor layer; and
a first electrode connected to the third semiconductor layer and the fourth semiconductor layer.

US Pat. No. 10,510,877

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a source/drain region over the substrate;
a composite layer over the substrate, wherein the composite layer comprises:
a first sublayer comprising a first material;
a second sublayer comprising a second material stacked on the first sublayer, wherein a bandgap of the second material is larger than a bandgap of the first material; and
a third sublayer comprising the first material, wherein the second sublayer is between the first sublayer and the third sublayer; and
a plug through the composite layer, and electrically connected to the source/drain region, wherein the plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion, and the second portion of the plug has a substantially curved sidewall profile.

US Pat. No. 10,510,872

FINFETS AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:removing a dummy gate stack in an inter-layer dielectric to form a trench, wherein a semiconductor fin is exposed to the trench;
doping germanium on the semiconductor fin through the trench to form a germanium channel doping layer; and
forming a gate dielectric and a gate electrode in the trench and over the germanium channel doping layer, wherein the gate dielectric comprises a portion overlapping the germanium channel doping layer.

US Pat. No. 10,510,871

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method, comprising:depositing a first layer on a substrate, the first layer including a first semiconductor material; and
growing a second layer on the first layer, the second layer including a second semiconductor material being different from the first semiconductor material and the first and second layers forming a first stack, wherein the first stack includes a first diffusion interface between the first layer and the second layer, wherein the first diffusion interface has a thickness that is greater than zero and less than or equal to 2 nanometers, wherein the depositing the first layer or the growing the second layer comprises using a first deposition process with a first precursor material, and wherein forming another one of the depositing the first layer or the growing the second layer comprises using a second deposition process with the first precursor material and a second precursor material.

US Pat. No. 10,510,868

FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming first spacers on opposing sidewalls of a first fin, wherein the first fin protrudes above a substrate;
recessing the first fin to form a first recess between the first spacers;
performing a cleaning process after recessing the first fin;
after the cleaning process, performing a baking process to change a profile of the first spacers, wherein the baking process is performed using a gas mixture comprising hydrogen, hydrofluoric acid, and germanium hydride, wherein the baking process curves inner sidewalls of the first spacers facing the first fin; and
forming a first semiconductor material over a top surface of the first fin after the baking process.

US Pat. No. 10,510,851

LOW RESISTANCE CONTACT METHOD AND STRUCTURE

Taiwan Semiconductor Manu...

1. A method, comprising:forming an opening in an insulating layer between a first gate and a second gate, the opening exposing a contact area of a source/drain region;
cleaning the opening;
bombarding a bottom of the opening with a first material, thereby causing a chemical reaction between the first material and a top surface of the contact area;
depositing a metal layer in the opening;
depositing a capping layer over the metal layer;
creating a silicide at the top surface of the contact area, the silicide having a first depth, wherein an upper surface of the silicide includes a first concentration of the first material, wherein the first concentration of the first material in the silicide decreases by a first gradient to a second concentration of the first material at a second depth of the silicide, wherein the silicide has the second concentration from the second depth of the silicide to the first depth of the silicide, wherein the second depth is interposed between the top surface of the silicide and the first depth of the silicide;
after creating the silicide, depositing a metal plug in the opening.

US Pat. No. 10,510,844

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Mitsubishi Electric Corpo...

1. A semiconductor device, comprising:a semiconductor substrate;
a first semiconductor layer of a first conductivity type, provided on a first main surface of the semiconductor substrate;
a plurality of first semiconductor regions selectively provided at upper layer parts of the first semiconductor layer, the plurality of first semiconductor regions having a second conductivity type;
a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, the second semiconductor region having a first conductivity type;
a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region;
a third semiconductor layer provided on the second semiconductor layer;
a gate insulating film provided such that the first semiconductor regions and the third semiconductor layer are covered therewith;
a gate electrode provided on the gate insulating film;
an interlayer insulating film provided such that the gate insulating film and the gate electrode are covered therewith;
a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof;
a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole; and
a second main electrode provided on a second main surface of the semiconductor substrate,
the first semiconductor layer being configured of a silicon carbide semiconductor having a first band gap,
the second semiconductor layer being configured of a semiconductor having a second band gap being narrower than the first band gap, and
the third semiconductor layer being configured of a semiconductor having a third band gap being narrower than the second band gap.

US Pat. No. 10,510,840

GAA FET WITH U-SHAPED CHANNEL

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a channel region, extending along a direction, that has a first U-shaped cross-section, the first U-shaped cross-section having a middle portion, a first extension extending up from a first end of the middle portion, and a second extension extending up from a second end of the middle portion;
a gate dielectric layer completely wrapping around the channel region to form a U-shaped structure having a second U-shaped cross-section that contains the first U-shaped cross-section; and
a gate electrode completely wrapping around the second U-shaped cross-section of the gate dielectric layer, wherein the gate electrode is interposed between the first extension and the second extension.

US Pat. No. 10,510,834

HIGH-VOLTAGE SEMICONDUCTOR DEVICE HAVING A DOPED ISOLATION REGION BETWEEN A LEVEL SHIFT REGION AND A HIGH VOLTAGE REGION

Nuvoton Technology Corpor...

13. A semiconductor device, comprising:a substrate structure, comprising a semiconductor substrate having a first conductive type, wherein the substrate structure comprises:
a high side region;
a low side region separated from the high side region; and
a level shift region and an isolation region disposed between the high side region and the low side region, wherein the level shift region and the high side region are separated from each other by the isolation region;
an epitaxial layer disposed on the semiconductor substrate, wherein the epitaxial layer has a second conductive type different from the first conductive type; and
a doped isolation region, having the first conductive type and located in the isolation region, and the doped isolation region extended from a top surface of the substrate structure to a portion of the substrate structure, wherein the doped isolation region has a width decreased linearly from a top surface of the epitaxial layer to a bottom surface of the epitaxial layer, and wherein a first width of the doped isolation region close to the top surface of the substrate structure is greater than a second width of the doped isolation region close to the bottom surface of the substrate structure in a cross-sectional view,
wherein a first side wall and a second side wall of the doped isolation region near the top surface of the substrate structure are non-parallel with each other.

US Pat. No. 10,510,832

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

23. A semiconductor device comprising:a semiconductor substrate having a drift region of first conductivity type;
a dummy trench portion which is provided from an upper surface of the semiconductor substrate to the drift region and arranged extending in a predetermined extending direction;
a diode mesa portion provided in direct contact with the dummy trench portion in the semiconductor substrate perpendicular to the extending direction;
an accumulation region of first conductivity type which is provided in direct contact with the dummy trench portion and above the drift region in the diode mesa portion and has higher doping concentration than doping concentration of the drift region;
a base region of second conductivity type provided in direct contact with the dummy trench portion and above the accumulation region in the diode mesa portion;
an emitter region of first conductivity type provided between the base region and an upper surface of the semiconductor substrate in the diode mesa portion and has higher doping concentration than doping concentration of the drift region;
a contact region of second conductivity type provided between the base region and an upper surface of the semiconductor substrate in the diode mesa portion; and
an intermediate region of second conductivity type provided adjacent to the dummy trench portion and above the drift region in the diode mesa portion.

US Pat. No. 10,510,821

DISPLAY DEVICE

Innovation Counsel LLP, ...

1. A display device comprising:a substrate; and
a plurality of pad terminals on the substrate,
wherein each of the plurality of pad terminals comprises a lower conductive layer and an upper conductive layer disposed on the lower conductive layer,
an elastic layer disposed between the lower conductive layer and the upper conductive layer, the elastic layer being an insulating layer, and
at least a portion of the lower conductive layer being electrically connected to at least a portion of the upper conductive layer in a region in which the elastic layer is not arranged,
wherein a thin film transistor comprising a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, a data line connected to the thin film transistor, an organic light-emitting diode comprising a first electrode, an emissive layer, and a second electrode, a touch sensor comprising a plurality of touch electrodes, and a plurality of insulating layers respectively disposed between electrodes are arranged on the substrate, and
wherein the electrodes are the gate electrode, the source electrode, the drain electrode, the first electrode, the second electrode, and the plurality of touch electrodes, and the lower conductive layer and the upper conductive layer being respectively arranged in a same layer as at least one of the electrodes and the data line, and the elastic layer being arranged in a same layer as at least one of the plurality of insulating layers is arranged on the substrate.

US Pat. No. 10,510,812

DISPLAY-INTEGRATED INFRARED EMITTER AND SENSOR STRUCTURES

Lockheed Martin Corporati...

1. An electronic display comprising:a first plurality of hexagon-shaped pixels, the first plurality of hexagon-shaped pixels each comprising an infrared (IR) emitter subpixel operable to emit IR light; and
a second plurality of hexagon-shaped pixels that are coplanar with the first plurality of hexagon-shaped pixels, the second plurality of hexagon-shaped pixels each comprising an IR detector subpixel operable to detect IR light, wherein:
each IR emitter subpixel and each IR detector subpixel comprises;
an anode layer; and
a cathode layer;
each particular IR emitter subpixel comprises an IR emissive layer located between the anode layer and the cathode layer of the particular IR emitter subpixel;
each particular IR detector subpixel comprises an IR detector layer located between the anode layer and the cathode layer of the particular IR detector subpixel; and
at least one of the anode layer and the cathode layer of each particular IR emitter subpixel and each particular IR detector subpixel is transparent to IR light.

US Pat. No. 10,510,798

METHOD OF FORMING DEEP TRENCH ISOLATION IN RADIATION SENSING SUBSTRATE AND IMAGE SENSOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming deep trench isolation in a radiation sensing substrate, comprising:forming a trench in the radiation sensing substrate, the trench extending from a back surface of the radiation sensing substrate into the radiation sensing substrate; and
forming a corrosion resistive layer in the trench, wherein the corrosion resistive layer comprises titanium carbon nitride.

US Pat. No. 10,510,797

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A back side illumination (BSI) image sensor comprising:a substrate comprising a front side and a back side opposite to the front side;
a plurality of pixel sensors disposed in the substrate, and each of the pixel sensors comprising a photo-sensing device and a plurality of micro structures disposed over the photo-sensing device on the back side of the substrate;
an isolation structure disposed in the substrate;
a plurality of color filters comprising a side wall disposed over the pixel sensors on the back side of the substrate;
a grid disposed over the backside of the substrate comprising a side wall in contact with the side wall of the color filter; and
a plurality of micro-lenses disposed over the color filter,wherein the micro structures and the photo-sensing device of one of the pixel sensors are isolated from the micro structures and the photo-sensing device of an adjacent pixel sensor by the isolation structure.

US Pat. No. 10,510,789

EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION

Taiwan Semiconductor Manu...

1. A method of forming an image sensor, comprising:implanting a dopant into a substrate to form a doped region;
implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate;
etching the substrate to form one or more trenches extending into a back-side of the substrate after implanting the dopant into the substrate to form the doped region, wherein the back-side of the substrate opposes the front-side of the substrate; and
filling the one or more trenches with one or more dielectric materials to form isolation structures.

US Pat. No. 10,510,781

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A method of producing a semiconductor device which includes a substrate, a plurality of first thin film transistors supported on the substrate, an interlevel dielectric layer covering the plurality of first thin film transistors, and a plurality of terminal portions electrically connecting the plurality of first thin film transistors to corresponding external wiring lines, each of the plurality of terminal portions including an upper conductive portion provided on the interlevel dielectric layer, the semiconductor device including an active region in which the plurality of first thin film transistors are provided, and a peripheral region being located around the active region and including the plurality of terminal portions provided therein, the method comprising:step (A) of forming gate electrodes of the plurality of first thin film transistors on the substrate;
step (B) of forming a gate dielectric layer covering the gate electrodes;
step (C) of forming an oxide semiconductor layer of the plurality of thin film transistors on the gate dielectric layer;
step (D) of forming source electrodes and drain electrodes of the plurality of thin film transistors;
step (E) of forming the interlevel dielectric layer to cover the plurality of thin film transistors;
step (F) of forming an aperture in the interlevel dielectric layer, the aperture being located between the active region and the plurality of terminal portions and extending through the interlevel dielectric layer; and
step (G) of, after the step (F), forming the upper conductive portion on the interlevel dielectric layer, wherein,
in the step (C), above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions, a protection layer is formed from a same oxide semiconductor film as the oxide semiconductor layer,
in the step (F), the aperture is formed so as to overlap the protection layer,
the aperture does not extend through the gate dielectric layer, and
in the step (C), the protection layer and the oxide semiconductor layer are formed simultaneously.

US Pat. No. 10,510,777

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode;
a gate insulating layer over the gate electrode;
an oxide semiconductor layer over the gate insulating layer;
a metal oxide layer over the oxide semiconductor layer;
a first insulating layer over the metal oxide layer;
a source electrode over the first insulating layer;
a drain electrode over the first insulating layer; and
a second insulating layer over the source electrode and the drain electrode,
wherein the gate insulating layer contains silicon and oxygen,
wherein the second insulating layer contains silicon and oxygen,
wherein the source electrode is in contact with the oxide semiconductor layer through a first opening of the metal oxide layer and the first insulating layer,
wherein the drain electrode is in contact with the oxide semiconductor layer through a second opening of the metal oxide layer and the first insulating layer, and
wherein the metal oxide layer contains at least one of metal elements selected from constituent elements of the oxide semiconductor layer.

US Pat. No. 10,510,775

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first field effect transistor formed in a first region of a semiconductor substrate; and
a second field effect transistor formed in a second region of the semiconductor substrate, which is different from the first region,
wherein, in the first region, a first insulating film is formed on the semiconductor substrate, and a semiconductor layer is formed on the first insulating film,
wherein the first field effect transistor has:
a first gate electrode formed on the semiconductor layer via a first gate insulating film;
a second insulating film formed on a side surface of the first gate electrode, and formed on the semiconductor layer;
an epitaxial layer formed on the semiconductor layer exposed from the second insulating film, and having an end portion whose thickness is thinner than a thickness of a central portion of the epitaxial layer; and
a third insulating film formed on the side surface of the first gate electrode via the second insulating film such that the third insulating film covers an upper surface of the epitaxial layer in the end portion,
wherein a first extension region, which serves as a part of one of a source region of the first field effect transistor and a drain region of the first field effect transistor, is formed in a first portion of the semiconductor layer, which is covered with the second insulating film and the third insulating film,
wherein a first diffusion layer, which serves as a part of one of the source region of the first field effect transistor and the drain region of the first field effect transistor, is formed at least a portion of the epitaxial layer, which is not covered with the second insulating film and the third insulating film,
wherein an impurity concentration of the first diffusion layer is higher than and impurity concentration of the first extension region,
wherein the semiconductor substrate in the second region is exposed from the first insulating film and the semiconductor layer,
wherein the second field effect transistor has:
a second gate electrode formed on the semiconductor substrate in the second region via a second gate insulating film;
a fourth insulating film formed on a side surface of the second gate electrode, and formed on the semiconductor substrate in the second region; and
a fifth insulating film formed on the side surface of the second gate electrode via the fourth insulating film,
wherein a second extension region, which serves as a part of one of a source region of the second field effect transistor and a drain region of the second field effect transistor, is formed in a first portion of the semiconductor substrate, which is covered with the fourth insulating film and the fifth insulating film,
wherein a second diffusion layer, which serves as a part of the one of the source region of the second field effect transistor and the drain region of the second field effect transistor, is formed in a second portion of the semiconductor substrate in the second region, which is not covered with the fourth insulating film and the fifth insulating film,
wherein an impurity concentration of the second diffusion layer is higher than an impurity concentration of the second extension region,
wherein, in cross-section view, an upper surface of the first diffusion layer is positioned higher than an interface between the semiconductor layer and the first gate insulating film, and
wherein, in cross-section view, an upper surface of the second diffusion layer is positioned lower than or equal to an interface between the semiconductor substrate and the second gate insulating film.

US Pat. No. 10,510,773

APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD

Micron Technology, Inc., ...

1. A memory device, comprising:a first vertical string of memory cells, wherein each memory cell of the first vertical string is formed at an intersection between a respective access line and a first vertical structure of ferroelectric material that is common to the first vertical string.

US Pat. No. 10,510,772

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A method of manufacturing a semiconductor device, the method comprising:alternately stacking first material layers and second material layers;
forming a hole passing through the first material layers and the second material layers;
forming cell blocking insulating layers arranged on side walls of the second material layers and dummy blocking insulating layers arranged on side walls of the first material layers, the dummy blocking insulating layers having side walls protruding further toward the hole than the cell blocking insulating layers; and
forming a data storage layer along the side walls of the cell blocking insulating layers and the dummy blocking insulating layers,
wherein forming the cell blocking insulating layers and the dummy blocking insulating layers comprises:
forming third material layers having side walls protruding further toward the hole than the side walls of the second material layers on the side walls of the first material layers; and
oxidizing the third material layers and portions of the side walls of the second material layers.

US Pat. No. 10,510,767

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A method for manufacturing an integrated circuit (IC), the method comprising:forming a charge trapping layer on a semiconductor substrate;
forming a sacrificial gate layer covering the charge trapping layer;
patterning the sacrificial gate layer to form a sacrificial control gate overlying the charge trapping layer, and to further form a sacrificial select gate neighboring the charge trapping layer and the sacrificial control gate;
forming a common source/drain in the semiconductor substrate, between the sacrificial control and select gates, wherein the common source/drain has a first doping type; and
replacing the sacrificial control gate with a control gate electrode, wherein the replacing of the sacrificial control gate is performed independent of the sacrificial select gate, wherein the control gate electrode comprises a first metal, wherein a work function of the first metal is within about 0.4 electron volts of a work function of doped polysilicon having a second doping type, and wherein the second doping type is opposite the first doping type.

US Pat. No. 10,510,765

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a memory device, comprising:providing a semiconductor substrate;
forming a plurality of logic well regions and a memory well region in the semiconductor substrate;
forming a charge storage structure on the memory well region;
forming a dummy dielectric layer on the charge storage structure and the logic well regions;
forming a dummy gate layer on the dummy dielectric layer;
forming a gate mask layer on the dummy gate layer;
etching the gate mask layer, the dummy gate layer and the dummy dielectric layer to form a plurality of dummy gate structures, wherein each of the dummy gate structures comprises a remaining portion of the dummy dielectric layer, a remaining portion of the dummy gate layer and a remaining portion of the gate mask layer;
forming a plurality of spacers on sidewalls of the dummy gate structures;
forming a plurality of sources and drains in the logic well regions and the memory well region;
removing the gate mask layer;
removing the remaining portion of the dummy gate layer to form a plurality of openings defined by the spacers; and
filling the openings with a plurality of high-k dielectric layers and a plurality of metal gate electrodes.

US Pat. No. 10,510,759

SEMICONDUCTOR MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device comprising:a plurality of lower electrodes located on a substrate and spaced apart from one another;
a first etch stop pattern located on the substrate and surrounding a lower portion of a sidewall of each of the plurality of lower electrodes; and
a second etch stop pattern located on the first etch stop pattern,
wherein a horizontal cross-sectional area of the second etch stop pattern decreases and then increases as the horizontal cross-sectional area of the second etch stop pattern goes away from the substrate in a vertical direction.

US Pat. No. 10,510,758

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor memory device, comprising:forming a gate structure on a semiconductor substrate, wherein the gate structure comprises:
a floating gate electrode;
a control gate electrode disposed on the floating gate electrode;
a first oxide layer disposed between the floating gate electrode and the semiconductor substrate; and
a second oxide layer disposed between the floating gate electrode and the control gate electrode;
forming an oxide spacer layer conformally on the gate structure and the semiconductor substrate;
forming a nitride spacer on the oxide spacer layer and on a sidewall of the gate structure; and
performing an oxidation process after the step of forming the nitride spacer, wherein a thickness of an edge portion of the first oxide layer is increased by the oxidation process, and a thickness of an edge portion of the second oxide layer before the oxidation process is equal to the thickness of the edge portion of the second oxide layer after the oxidation process, wherein the oxide spacer layer directly contacts a topmost surface of the control gate electrode during the oxidation process.

US Pat. No. 10,510,753

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit comprising:first and second semiconductor fins;
first and second epitaxy structures respectively on the first and second semiconductor fins, wherein the first epitaxy structure and the second epitaxy structure are merged together; and
first and second dielectric fin sidewall structures respectively on opposite first and second sidewalls of the first epitaxy structure, wherein the first sidewall of the first epitaxy structure faces the second epitaxy structure, and the first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.

US Pat. No. 10,510,739

METHOD OF PROVIDING LAYOUT DESIGN OF SRAM CELL

TAIWAN SEMICONDUCTOR MANU...

1. A method of providing a layout design of an SRAM cell, comprising:providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first oxide diffusion area is parallel to the second oxide diffusion area, the first polysilicon layout is parallel to the second polysilicon layout, the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area;
forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout;
forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout;
forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and
forming a second pull-down transistor on the second oxide diffusion area and the second polysilicon layout;
wherein forming the first pull-up transistor on the first oxide diffusion area and the first polysilicon layout comprises:
disposing a first contact layout to overlap a first portion of the first oxide diffusion area; and
disposing a second contact layout to overlap a second portion of the first oxide diffusion area; and
forming the first pull-down transistor on the second oxide diffusion area and the first polysilicon layout comprises:
arranging the first contact layout to overlap a first portion of the second oxide diffusion area; and
disposing a third contact layout on a second portion of the second oxide diffusion area.

US Pat. No. 10,510,734

SEMICONDUCTOR PACKAGES HAVING DUMMY CONNECTORS AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:encapsulating a first integrated circuit die in an encapsulant;
forming a redistribution layers (RDL) electrically connected to the first integrated circuit die;
bonding a substrate to the RDL using a plurality of functional connectors, wherein the plurality of functional connectors electrically connects a second integrated circuit die to the first integrated circuit die, and wherein the first integrated circuit die and the second integrated circuit die are disposed on opposing sides of the substrate;
disposing a plurality of dummy connectors between the substrate and the RDL, wherein the plurality of functional connectors extends below the plurality of dummy connectors, and wherein the plurality of functional connectors at least partially encircles the plurality of dummy connectors in a top down view, wherein the plurality of dummy connectors is in physical contact with a same surface of the substrate as the plurality of functional connectors; and
dispensing an underfill between the same surface of the substrate and the RDL, the underfill is further dispensed around the plurality of functional connectors and the plurality of dummy connectors.

US Pat. No. 10,510,728

MAGNETIC COUPLING PACKAGE STRUCTURE FOR MAGNETICALLY COUPLED ISOLATOR WITH DUO LEADFRAMES AND METHOD FOR MANUFACTURING THE SAME

LITE-ON SINGAPORE PTE. LT...

1. A method for manufacturing a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator, comprising:a leadframe providing step including providing a first leadframe and a second leadframe, wherein the first leadframe includes a first chip-mounting portion, at least a first coil portion, a plurality of first pins and a plurality of floated pins, and the second leadframe includes a second chip-mounting portion, at least a second coil portion, a plurality of second pins and a plurality of second floated pins;
a chip connecting step including respectively disposing at least a first chip and at least a second chip on the first chip-mounting portion and the second chip-mounting portion and establishing electrical connections between the first chip and the first pins and between the second chip and the second pins; and
a coil aligning step including disposing the first leadframe at a position above or under the second leadframe and respectively applying a first magnetic field and a second magnetic field to the first leadframe and the second leadframe for aligning the first coil portion and the second coil portion;
wherein the first chip and the first coil portion together form a first closed circuit through a first connecting wire, and the at least one second chip and the at least one second coil portion together form a second closed circuit through a second connecting wire.

US Pat. No. 10,510,722

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first electronic component having a first surface;
a second electronic component over the first electronic component, the second electronic component having a second surface facing the first surface of the first electronic component;
a plurality of interconnection structures between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures,
wherein the first electronic component comprises a plurality of electrical terminals, and each of the interconnection structures is electrically connected to two or more of the plurality of electrical terminals of the first electronic component, and wherein the plurality of interconnection structures comprises a first set of interconnection structures and a second set of interconnection structures, the interconnection structures of the first set are electrically connected, the interconnection structures of the second set are electrically connected, and the interconnection structures of the first set and the second set are arranged alternately in the second direction and electrically disconnected from one another; and
a plurality of capacitors each comprising a first electrode and a second electrodes overlapping to each other, wherein the first electrodes of the capacitors are electrically connected to the second electronic component through the first set of the interconnection structures, and the second electrodes of the capacitors are electrically connected to the second electronic component through the second set of the interconnection structures.

US Pat. No. 10,510,719

METHODS OF PACKAGING SEMICONDUCTOR DEVICES AND PACKAGED SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A packaged semiconductor device comprising:an integrated circuit die, the integrated circuit die having a plurality of contact pads disposed thereon,
a dam structure disposed on a periphery of the integrated circuit die; a molding material disposed along sidewalls of the integrated circuit die and along sidewalls of the dam structure, wherein the molding material extends over an upper surface of the integrated circuit die: and
an interconnect structure disposed over the integrated circuit die and the molding material, the interconnect structure comprising a first dielectric layer, the first dielectric layer being interposed between the dam structure and the plurality of contact pads.

US Pat. No. 10,510,718

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a first die disposed over the substrate;
a second die disposed over the substrate and arranged laterally adjacent to the first die from a cross-sectional perspective, wherein the second die includes a first surface facing the substrate, and a second surface opposite to the first surface;
a molding disposed over the substrate and surrounding the first die and the second die, wherein the molding separates the first die and the second die, and the molding includes a first surface facing the substrate, and a second surface opposite to the first surface;
an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, the dielectric layer is in contact with the second surface of the molding and the second surface of the second die, and the conductive member is surrounded by the dielectric layer; and a via disposed between the dielectric layer and the substrate, the via extended within the second die.

US Pat. No. 10,510,713

SEMICONDCUTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a redistribution structure;
at least one semiconductor device disposed on and electrically connected to the redistribution structure;
a heat dissipation component disposed on the redistribution structure and comprising a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion connects the at least one semiconductor device; and
an encapsulating material disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

US Pat. No. 10,510,711

ANISOTROPIC CONDUCTIVE FILM AND CONNECTED STRUCTURE

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film comprising an insulating adhesive layer and conductive particles arranged in the insulating adhesive layer in a lattice-like manner, whereinwhen among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, a shortest distance to the arbitrary conductive particle is defined as a first center distance, and a next shortest distance is defined as a second center distance,
the first center distance and the second center distance are each 1.5 to 5 times a particle diameter of the conductive particles, and
regarding an acute triangle formed by an arbitrary conductive particle P0, a conductive particle P1 spaced apart from the arbitrary conductive particle P0 by the first center distance, and a conductive particle P2 spaced apart from the arbitrary conductive particle P0 by the first center distance or the second center distance, an acute angle ? formed between a straight line orthogonal to a direction (hereinafter, referred to as a first array direction) of a straight line passing through the conductive particles P0 and P1 and a direction (hereinafter, referred to as a second array direction) of a straight line passing through the conductive particles P1 and P2 is 18 to 35° , and
when a direction passing through the conductive particles P0 and P2 is defined as a third array direction, the first array direction, the second array direction, and the third array direction are tilted with respect to the longitudinal direction of the anisotropic conductive film, and
an angle formed between the first array direction and the longitudinal direction of the anisotropic conductive film is smaller than an angle formed between the second array direction and the longitudinal direction of the anisotropic conductive film.

US Pat. No. 10,510,703

SEMICONDUCTOR DEVICE AND METHOD OF FORMING 3D DUAL SIDE DIE EMBEDDED BUILD-UP SEMICONDUCTOR PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a semiconductor die;
disposing the semiconductor die over a carrier;
disposing a substrate over the carrier;
laminating a prefabricated insulating film onto the substrate; and
mounting the substrate to the carrier with the semiconductor die embedded in the prefabricated insulating film after laminating the insulating film onto the substrate.

US Pat. No. 10,510,696

PAD STRUCTURE AND MANUFACTURING METHOD THEREOF IN SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a memory cell on a substrate;
forming a conductive pad region to electrically couple to the memory cell;
depositing a dielectric layer over the conductive pad region;
forming a first passivation layer over the dielectric layer;
etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region;
forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and
etching the second passivation layer to expose a second area of the conductive pad region.

US Pat. No. 10,510,695

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a die on an adhesive layer;
an encapsulant, laterally encapsulating the die and laterally encapsulating the adhesive layer;
a redistribution layer (RDL) structure electrically connected to the die, wherein the RDL structure and the adhesive layer are disposed at opposite sides of the die, and the RDL structure comprises:
a first dielectric layer on the encapsulant and the die;
a first RDL embedded in the first dielectric layer and comprising a first via and a first trace connected to each other, wherein a top surface of the first RDL is coplanar with a top surface of the first dielectric layer;
a second dielectric layer on the first dielectric layer and the first RDL; and
a second RDL embedded in the second dielectric layer and comprising a second via and a second trace connected to each other, wherein a top surface of the second RDL is coplanar with a top surface of the second dielectric layer,
wherein the second via is stacked directly on the first via.

US Pat. No. 10,510,694

RADIO FREQUENCY COMMUNICATION SYSTEMS

Analog Devices, Inc., No...

1. A packaged radio frequency (RF) module comprising:a package substrate;
a first die electrically and mechanically attached to the package substrate, the first die comprising an RF switch;
a second die electrically and mechanically attached to the package substrate, the second die comprising an RF amplifier;
an encapsulating material protecting electrical connections between the first die and the package substrate; and
a lid attached to the package substrate such that the package substrate and the lid at least partially define an air cavity within which the first and the second die are mounted, an active surface of the second die being exposed to the air cavity.

US Pat. No. 10,510,691

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first substrate including a first surface and a second surface opposite to the first surface;
a via extending through the first substrate;
a die disposed over the first surface of the first substrate;
a redistribution layer (RDL) disposed over the second surface of the first substrate, and including a dielectric layer over the second surface, a first conductive structure disposed within the dielectric layer and electrically connected to the via, and a second conductive structure disposed within the dielectric layer and electrically isolated from the via;
a second substrate including a third surface and a fourth surface opposite to the third surface;
a conductive bump disposed between the third surface of the second substrate and the RDL and bonding the first conductive structure with the second substrate; and
a first underfill material surrounding the first substrate, the RDL and the conductive bump,
wherein a height of the first conductive structure and a height of the second conductive structure are the same, and one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.

US Pat. No. 10,510,689

SOLDER BALL PROTECTION IN PACKAGES

Taiwan Semiconductor Manu...

1. A method comprising:placing a coated conductive ball on a metal feature, with the metal feature comprised in a chip, wherein the coated conductive ball comprises:
a conductive ball; and
a coating material at least encircling a middle portion of the conductive ball;
aligning the conductive ball to the metal feature, wherein during the aligning an electromagnetic field is applied on the conductive ball by conducting a current into a partially-looped metal trace to reposition the conductive ball relative the metal feature, the partially-looped metal trace is underlying and aligned to the metal feature; and
attaching the coated conductive ball to the metal feature.

US Pat. No. 10,510,675

SUBSTRATE STRUCTURE WITH SPATIAL ARRANGEMENT CONFIGURED FOR COUPLING OF SURFACE PLASMONS TO INCIDENT LIGHT

GLOBALFOUNDRIES INC., Gr...

1. A method of detecting overlay alignment when fabricating an integrated circuit (IC) structure, the method comprising:providing a substrate structure, the substrate structure including:
a first dielectric layer positioned above a semiconductor substrate;
a first plurality of trenches within an upper surface of the first dielectric layer; and
a first metal within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light;
illuminating the substrate structure with a light source including wavelength components which couple with surface plasmons in the first metal, and wherein the illuminating yields focused plasmons within the substrate structure; and
detecting the overlay alignment by detecting the incident light reflected from the substrate structure.

US Pat. No. 10,510,673

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. An integrated fan-out package, comprising:an integrated circuit die;
an insulating encapsulation encapsulating the integrated circuit die, the insulating encapsulation comprising contact openings and through holes extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation, and the first surface being opposite to the second surface; and
a redistribution circuit structure comprising a first redistribution conductive layer on the first surface of the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, a second redistribution conductive layer on the first inter-dielectric layer, and a second inter-dielectric layer covering the second redistribution conductive layer,
wherein the first redistribution conductive layer comprises a plurality of first conductive patterns, first seed patterns underlying the first conductive patterns, second conductive patterns, and second seed patterns underlying the second conductive patterns, the first seed patterns and the first conductive patterns are electrically connected to the integrated circuit die through the contact openings, and the second seed patterns and the second conductive patterns located in the through holes, and
wherein the second seed patterns and the second conductive patterns respectively extend from the first surface of the insulating encapsulation toward the second surface of the insulating encapsulation, and the second seed patterns are accessibly exposed at the second surface of the insulating encapsulation.

US Pat. No. 10,510,668

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, comprising:providing a hybrid bonded structure;
providing a cover lid comprising a base portion and at least one dummy portion protruding from the base portion;
bonding the at least one dummy portion of the cover lid to the hybrid bonding structure;
removing the base portion; and
forming a redistribution structure over the hybrid bonding structure and the at least one dummy portion.

US Pat. No. 10,510,666

INTERCONNECT STRUCTURE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. An apparatus comprising:a first dielectric layer formed over a substrate;
a first conductive structure embedded in the first dielectric layer, wherein a top surface of the first conductive structure and a surface of the first dielectric layer form a first inverted trapezoidal shape;
a second conductive structure embedded in the first dielectric layer, wherein a top surface of the second conductive structure and the surface of the first dielectric layer form a second inverted trapezoidal shape;
a second dielectric layer formed over the first dielectric layer; and
a third conductive structure embedded in the second dielectric layer, wherein:
the third conductive structure is in direct contact with the top surface of the first conductive structure; and
the third conductive structure is in direct contact with a sidewall of the first dielectric layer, the sidewall of the first dielectric layer extending from a lateral extent of the top surface of the first conductive structure to an uppermost surface of the first dielectric layer, and wherein a portion of the sidewall of the first dielectric layer extending from the third conductive structure to the uppermost surface of the first dielectric layer is covered by a dielectric material.

US Pat. No. 10,510,658

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate;
a first insulating film on the substrate;
a lower metal layer in the first insulating film;
a second insulating film on the first insulating film, wherein the lower metal layer is in the second insulating film, the second insulating film comprises a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film is upwardly convex;
a barrier dielectric film on the second insulating film, wherein the barrier dielectric film comprises a recess; and
a via metal layer in the recess of the barrier dielectric film and electrically connected with the lower metal layer,
wherein the barrier dielectric film extends on a side of a portion of the via metal layer,
wherein the first insulating film and the second insulating film are sequentially stacked on the substrate in a vertical direction, and
wherein a longest vertical distance between an upper surface of the lower metal layer and the substrate is less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

US Pat. No. 10,510,656

SEMICONDUCTOR DEVICE

PANASONIC INTELLECTUAL PR...

1. A semiconductor device comprising:a substrate;
a semiconductor layer disposed on the substrate;
a first transistor including a first gate electrode, a plurality of first drain electrodes and a plurality of first source electrodes that are disposed vertically above the semiconductor layer;
a second transistor including a second gate electrode, a plurality of second drain electrodes and a plurality of second source electrodes that are disposed vertically above the semiconductor layer;
first drain pads that are disposed vertically above the first drain electrodes, are electrically connected to the first drain electrodes, and extend in a first direction;
a plurality of first source pads that are disposed vertically above the second source electrodes, are electrically connected to the second source electrodes, and extend along the first direction;
a plurality of first common interconnects, each of which is continuously disposed from vertically above one of the first source electrodes to vertically above one of the second drain electrodes, is electrically connected to the one of the first source electrodes and the one of the second drain electrodes, and extends in the first direction; and
a plurality of second common interconnects, each of which is connected to the first common interconnects, and extends in a second direction that intersects with the first direction,
wherein the plurality of first common interconnects and the plurality of second common interconnects are disposed in a same layer, and
wherein each of the plurality of second common interconnects is directly connected to the first common interconnects.

US Pat. No. 10,510,652

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:receiving a first substrate with a surface;
receiving a second substrate;
determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad;
forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern, a projection area of the via contacting the first type pad on the surface is located within and smaller than a projection area of the first type pad on the surface, and the second type pad in the pad array is clear of any via of the via pattern;
laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and
disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate thereby connecting the first substrate and the second substrate through the first type pad and the second type pad in the pad array.

US Pat. No. 10,510,650

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE PACKAGING STRUCTURE HAVING THROUGH INTERPOSER VIAS AND THROUGH SUBSTRATE VIAS

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:attaching a first semiconductor device and a second semiconductor device to a first wafer;
forming first through interposer vias adjacent to the first semiconductor device and the second semiconductor device;
exposing through substrate vias by removing a portion of the first semiconductor device and the second semiconductor device;
applying a dielectric material around the first through interposer vias;
singulating the first wafer to form a first package and a second package;
attaching the first package and the second package to a carrier wafer, wherein second through interposer vias are located on the carrier wafer;
encapsulating the first package, the second package, and the second through interposer vias with an encapsulant;
thinning the encapsulant to expose the through substrate vias; and
forming a redistribution structure over the encapsulant.

US Pat. No. 10,510,648

FAN-OUT PACKAGE STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:embedding a semiconductor structure in a molding compound layer;
depositing a plurality of photo-sensitive material layers over the molding compound layer, the plurality of photo-sensitive material layers comprising a second photo-sensitive material layer over a first photo-sensitive material layer;
developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein the first photo-sensitive material layer is exposed to light prior to depositing the second photo-sensitive material layer, the first photo-sensitive material layer being developed after depositing the second photo-sensitive material layer, wherein a first portion and a second portion of an opening of the plurality of openings are formed in the first and second photo-sensitive material layers respectively; and
filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

US Pat. No. 10,510,644

PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a redistribution structure over a carrier, wherein the redistribution structure comprises dielectric layers and redistribution lines extending into the dielectric layers, wherein a redistribution line in the redistribution structure forms a first recess and a second recess, and the redistribution line comprises a first portion underlying the first recess, and second portions forming sidewalls of the first recess;
bonding a device die to the redistribution lines;
attaching a conductive region onto the redistribution lines, wherein the conductive region extends into the first recess and is in contact with a top surface of the first portion and sidewall surfaces of the second portions of the first recess;
encapsulating the device die and the conductive region in an encapsulating material, wherein the encapsulating material extends into the second recess;
performing a planarization step to reveal the conductive region; and
de-mounting the device die and the redistribution structure from the carrier after the planarization step.

US Pat. No. 10,510,638

ELECTRONIC COMPONENT-EMBEDDED BOARD

SHINKO ELECTRIC INDUSTRIE...

1. An electronic component-embedded board comprising:a first insulating layer;
a metal layer formed on the first insulating layer;
a first electronic component disposed on the metal layer;
a second insulating layer formed on the first insulating layer and the metal layer such that the first electronic component is buried in the second insulating layer;
a second electronic component disposed above the second insulating layer; and
a heat radiating member thermally connected to the metal layer exposed from the second insulating layer and thermally connected to the second electronic component.

US Pat. No. 10,510,628

CONTACT PADS FOR ELECTRICAL MODULE ASSEMBLY WITH MULTIDIMENSIONAL TRANSDUCER ARRAYS

Siemens Medical Solutions...

1. A multidimensional transducer array system, the system comprising:a first printed circuit board having a first surface with ends of traces, the ends of the traces electrically connecting to metallic contact pads separated by kerfs in the first surface;
a multidimensional transducer array having first elements in electrical contact with the metallic contact pads, wherein the kerfs in the first surface are patterned to match kerfs separating the first elements of the multidimensional array; and
an integrated circuit connected with the first printed circuit board such that signals on the contact pads are provided at the integrated circuit by the traces, the integrated circuit connected on a second surface of the first printed circuit board different than the first surface.

US Pat. No. 10,510,625

SYSTEMS AND METHODS FOR CONTROLLING PLASMA INSTABILITY IN SEMICONDUCTOR FABRICATION

Lam Research Corporation,...

1. An apparatus for supporting a wafer during a plasma processing operation, comprising:a pedestal configured to have a bottom surface and a top surface;
a column configured to support the pedestal at a central region of the bottom surface of the pedestal;
an electrical insulating layer disposed over the top surface of the pedestal;
an electrically conductive layer disposed over a top surface of the electrical insulating layer;
at least three support structures distributed on a top surface of the electrically conductive layer, each of the at least three support structures formed of electrically conductive material and secured in electrical contact with the electrically conductive layer, the at least three support structures configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer; and
an electrical connection extending from the electrically conductive layer to a location outside of the pedestal, wherein the electrical connection is electrically connected to a positive terminal of direct current power supply so that the at least three support structures are electrically connected to the positive terminal of the direct current power supply.

US Pat. No. 10,510,614

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

16. A semiconductor arrangement, comprising:a first set of fins;
a second set of fins, spaced apart from the first set of fins;
a first metal connect contacting the first set of fins;
a second metal connect contacting the second set of fins, wherein the second metal connect is separated from the first metal connect by a first dielectric layer;
a second dielectric layer over the first dielectric layer, the first metal connect, and the second metal connect; and
a third metal connect disposed in the second dielectric layer, wherein the third metal connect electrically couples the first metal connect to the second metal connect.

US Pat. No. 10,510,613

CONTACT STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:an active gate structure composed of conductive material located between sidewall material;
a source/drain region on sides of the active gate structure;
an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and
a first contact structure in electrical contact with the conductive material of the active gate structure, the first contact structure being located between the sidewall material and between the upper sidewall material;
contact material in electrical contact with the source/drain region, the contact material being separated from active gate structure by at least the sidewall material;
a second contact structure in electrical and direct physical contact with the contact material of the source/drain region,
wherein:
the sidewall material is a low-k dielectric material and the upper sidewall material has an etch selectivity different than the low-k dielectric material;
the upper sidewall material separates the first contact structure for the active gate structure from the second contact structure of the source/drain region of the active gate structure; and
a lower portion of the second contact structure of the source/drain region is located between the sidewall material and an upper portion of the second contact structure of the source/drain region is located between and in direct physical contact with the upper sidewall material.

US Pat. No. 10,510,563

WAFER CARRIER ASSEMBLY

TAIWAN SEMICONDUCTOR MANU...

1. A wafer carrier assembly, comprising:a wafer carrier comprising a retainer ring confining a wafer accommodation space, a plate over the retainer ring, and a rim surrounding a periphery of the plate, wherein the plate has a bore through the plate; and
a fluid passage inside the wafer carrier and configured to deliver a fluid, wherein the fluid passage includes an inlet, and at least an outlet to dispense the fluid into the wafer accommodation space, and wherein the fluid passage comprises a first tube through the bore of the plate, and a second tube under the plate and in communication with the first tube, the first tube has a first end configured as the inlet of the fluid passage, the second tube has a first end in communication with a second end of the first tube, and a second end configured as the outlet of the fluid passage, and the second tube is rotatable with respect to the rim and the first tube,
wherein the first end of the second tube surrounds the second end of the first tube, and an inner diameter of the first end of the second tube is greater than an outer diameter of the second end of the first tube.

US Pat. No. 10,510,560

METHOD OF ENCAPSULATING A SUBSTRATE

Nanyang Technological Uni...

1. A method of encapsulating a substrate having at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, wherein the first semiconductor material is a group III-V semiconductor material or a material formed from combining different III-V semiconductor materials, and wherein the layer of first semiconductor material is arranged intermediate the CMOS device layer and the layer of second semiconductor material such that adjoining edges of the layer of first semiconductor material, the CMOS device layer and the layer of second semiconductor material define a circumferential edge of the substrate, the method comprising:(i) removing a portion of the circumferential edge, wherein the portion removed comprises a portion of the CMOS device layer and a portion of the layer of first semiconductor material; and
(ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material such that the layer of first semiconductor material is unexposed.

US Pat. No. 10,510,553

DRY ASHING BY SECONDARY EXCITATION

Taiwan Semiconductor Manu...

1. A method, comprising:generating a first plasma from a first gas;
diffusing, in a wafer processing chamber, the first plasma through a first gas distribution plate (GDP), forming a first low energy region;
diffusing the first plasma from the first low energy region through a second GDP, forming a substrate processing region; and
supplying a second gas in the substrate processing region, wherein the first plasma energizes the second gas to form radicals of the second gas, wherein the radicals of the second gas strip a layer from a substrate.

US Pat. No. 10,510,551

ETCH RESISTANT ALUMINA BASED COATINGS

PIBOND OY, Espoo (FI)

1. A method of forming a protective hard mask layer on a substrate in a semiconductor etch process, consisting of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminium oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst; wherein 1 to 4 alumina precursors are polymerized with a silane precursor in a solvent or combination of solvents to produce a solution or a colloidal dispersion of a silane containing alumina polymer; and wherein the alumina precursor is peptisized with an agent selected from the group of carboxylic acids, alpha-hydroxy carboxylic acids, carboxylic acid salts, beta-diketones, esters, or beta-ketoesters selected from C1-12 alkyl groups in which halogen, unsaturated, and aromatic functionalities may be present, in order to produce the solution or colloidal dispersion of alumina polymer capable of being applied onto the substrate, optionally followed by curing and patterning the alumina polymer.

US Pat. No. 10,510,549

METHOD OF FABRICATING A METAL LAYER

UNITED MICROELECTRONICS C...

1. A method of fabricating a metal layer, comprising:providing a conductive layer, a metal compound contacting a top surface of the conductive layer, a dielectric layer covering the conductive layer, and a trench disposed in the dielectric layer, the metal compound being exposed through the trench;
performing a first re-sputtering on the metal compound and the dielectric layer with inert ions and metal ions, wherein the metal compound is removed entirely during the first re-sputtering, wherein during the first re-sputtering, the metal ions bombard the surface of the dielectric layer, and turn into metal atoms to deposit onto the surface of the dielectric layer;
after the first re-sputtering, forming a barrier covering the trench, wherein the barrier is formed in a chamber;
performing a second re-sputtering on the barrier with the inert ions and the metal ions, wherein the barrier at a bottom of the trench is entirely removed during the second re-sputtering and the second re-sputtering is performed in the chamber; and
forming a metal layer in the trench.

US Pat. No. 10,510,548

SEMICONDUCTOR STRUCTURE

Semiconductor Manufacturi...

1. A semiconductor structure, comprising:a base including a first region, a second region, a third region, and a fourth region, used for a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively;
a gate dielectric layer on the first, second, third and fourth regions of the base;
a first material layer on the gate dielectric layer;
a second material layer on the first material layer above the fourth region;
a third material layer on the first material layer above the third region and on the second material layer above the fourth region; and
a fourth material layer on the third material layer above the third and fourth regions and on the first material layer on the second region, wherein:
the first material layer above the first region is used as a first work function layer for the first transistor,
the first and fourth material layers above the second region are used as a second work function layer for the second transistor,
the first, third and fourth material layers above the third region are used as a third work function layer for the third transistor,
the first, second, third and fourth material layers above the fourth region are used as a fourth work function layer for the fourth transistor, and
a thickness of the first work function layer is smaller than a thickness of the second work function layer, the thickness of the second work function layer is smaller than a thickness of the third work function layer, the thickness of the third work function layer is smaller than a thickness of the fourth work function layer.

US Pat. No. 10,510,545

HYDROGENATION AND NITRIDIZATION PROCESSES FOR MODIFYING EFFECTIVE OXIDE THICKNESS OF A FILM

APPLIED MATERIALS, INC., ...

18. A method of forming a structure in a semiconductor device, the method comprising:depositing a high-k dielectric layer on a semiconductor substrate;
depositing a capping layer on the high-k dielectric layer to form a portion of the structure, wherein the portion includes the capping layer and the high-k dielectric layer, and wherein the deposited capping layer has an exposed surface; and
exposing the exposed surface to a plasma-excited hydrogen species and a plasma-excited nitrogen species, wherein the plasma-excited hydrogen species comprises ammonia, and the plasma-excited nitrogen species comprises nitrogen gas (N2).

US Pat. No. 10,510,541

ANGULAR CONTROL OF ION BEAM FOR VERTICAL SURFACE TREATMENT

VARIAN SEMICONDUCTOR EQUI...

1. A method for forming a semiconductor device, the method comprising:providing a set of surface features extending from a substrate, the set of surface features including a sidewall;
treating the sidewall with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the substrate, wherein the ion beam impacts just a portion of the sidewall;
rotating the substrate about the perpendicular to the plane of the upper surface of the substrate; and
treating the sidewall with the ion beam, wherein the ion beam impacts an entire height of the sidewall with the ion beam.

US Pat. No. 10,510,533

NANOWIRE FABRICATION METHOD AND STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a template layer having a predetermined template thickness;
a recess formed in the template layer and having a recess pattern, the recess further having a recess depth smaller than the template thickness and bounded by a bottom surface within the template layer and an upper surface of the semiconductor device;
a semiconductor structure formed in the recess and extending above the recess, the semiconductor structure extending in a substantially vertical direction with respect to the major surface of the substrate, the portion of the semiconductor structure extending above the recess having a generally uniform cross-section corresponding to the recess pattern; and
a pre-layer on the bottom surface of the template layer below the semiconductor structure,
wherein the template layer comprises amorphous materials, and the bottom surface defining the recess comprises an amorphous surface;
wherein the recess depth is substantially uniform and is about 1 nm to about 3 nm; and
wherein a thickness of the pre-layer is about 1 monolayer.

US Pat. No. 10,510,529

FORMATION OF SIOCN THIN FILMS

ASM IP Holding B.V., Alm...

1. A plasma enhanced atomic layer deposition (PEALD) method of forming a thin film comprising silicon, oxygen and carbon on a substrate that comprises a material that would be oxidized by exposure to oxygen plasma, wherein the PEALD method comprises at least one deposition cycle comprising:contacting a surface of the substrate with a vapor phase silicon precursor to thereby adsorb a silicon species on the surface of the substrate; and
contacting the adsorbed silicon species with at least one reactive species generated by plasma formed from a gas that does not comprise oxygen,
wherein the silicon precursor comprises a silicon atom, an alkoxide group bonded to the silicon atom and a ligand comprising an amino group bonded to the silicon atom through a carbon, and
wherein the substrate is not contacted with a reactive species generated by a plasma from oxygen in the at least one deposition cycle.

US Pat. No. 10,510,527

SINGLE WAFER CLEANING TOOL WITH H2SO4 RECYCLING

Taiwan Semiconductor Manu...

1. A single wafer cleaning tool, comprising:a processing chamber configured to house a semiconductor substrate having a photoresist residue having metal impurities;
an oxidative treatment unit in communication with the processing chamber by way of a first inlet and configured to apply an oxidative chemical pre-treatment to the semiconductor substrate to remove a part of the photoresist residue having metal impurities in a manner that results in a contaminant remainder;
a SPM cleaning unit in communication with the processing chamber by way of a second inlet configured to apply a sulfuric-peroxide mixture (SPM) cleaning solution to the semiconductor substrate separate from the oxidative chemical pre-treatment to remove the contaminant remainder from the semiconductor substrate as an SPM effluent; and
a recycling unit coupled to the processing chamber and configured to recover sulfuric acid (H2SO4) from the SPM effluent and to provide the recovered H2SO4 to the SPM cleaning unit via a feedback conduit, wherein the recycling unit comprises:
first and second collection tanks;
a first switching element having inputs directly coupled by first and second conduits to outputs of the first and second collection tanks, respectively;
a heating element having an input that is coupled to an output of the first switching element by a first fluid path;
a second switching element having an input that is coupled to an output of the heating element by a second fluid path;
a feedback path extending between a first output of the second switching element and an input of a third switching element, wherein the third switching element has a first output coupled to the first collection tank and a second output coupled to the second collection tank; and
wherein the feedback path further comprises a filter.

US Pat. No. 10,510,517

CLEANING APPARATUS FOR AN EXHAUST PATH OF A PROCESS REACTION CHAMBER

RETRO-SEMI TECHNOLOGIES, ...

1. A cleaning apparatus installed in an exhaust path of a process reaction chamber, the apparatus comprising:an inflow pipe having an associated gas inlet for receiving exhaust gas from an upstream portion of the exhaust path;
an outflow pipe having an associated gas outlet for expelling exhaust gas from the cleaning apparatus into a downstream portion of the exhaust path;
a connecting pipe fluidly connecting the inflow pipe to the outflow pipe;
a first radio frequency (RF) coil assembly wound around an outer circumferential surface of the inflow pipe and a second RF coil assembly wound around an outer circumferential surface of the outflow pipe;
an RF generator for generating RF power;
a matching network for receiving the RF power from the RF generator and for applying it to one end of each of the first and second RF coil assemblies, a second end of each of the first and second RF coils being connected to ground;
wherein flux lines for each of the first and second coil assemblies, when energized by RF power from the RF generator via the matching network, cause VHF resonance within the respective inflow or outflow pipe, thereby forming plasma within the exhaust gas flowing therethrough, the plasma forming free radicals from the exhaust gas for cleaning a portion of the exhaust path of the process reaction chamber downstream of the cleaning apparatus, and
wherein one or both of the inflow pipe and the outflow pipe is configured so that a diameter (r1) of an inlet side inner wall is formed smaller than a diameter (r2) of a central portion of the inflow or outflow pipe, and an outlet side inner wall has a tapered shape that gradually slopes inward toward the outlet.

US Pat. No. 10,510,513

PLASMA PROCESSING DEVICE AND HIGH-FREQUENCY GENERATOR

TOKYO ELECTRON LIMITED, ...

1. A plasma processing device which processes an object to be processed using plasma, the plasma processing device comprising:a processing container configured to perform a processing on the object by the plasma therein; and
a plasma generator including a high-frequency generator disposed outside the processing container to generate high-frequency waves, and the plasma generator being configured to generate the plasma in the processing container using the high-frequency waves generated by the high-frequency generator,
wherein the high-frequency generator includes a first high-frequency oscillator configured to generate the high-frequency waves and a branch circuit configured to inject a signal into the first high-frequency oscillator, wherein the first high frequency oscillator is a magnetron,
the branch circuit comprises a second high-frequency oscillator which is configured to detect a fundamental frequency of the high-frequency waves generated by the first high-frequency oscillator and to generate, based on the fundamental frequency of the high-frequency waves, the signal having a frequency which is the same as the fundamental frequency generated by the first high-frequency oscillator and having reduced different frequency components, and wherein the branch circuit injects the signal generated by the second high-frequency oscillator into the first high-frequency oscillator through a first band-pass filter,
wherein the fundamental frequency of the high-frequency waves is not changed after the branch circuit injects the signal generated by the second high-frequency oscillator into the first high-frequency oscillator.

US Pat. No. 10,510,499

SMD SWITCH AND TOUCHPAD MODULE AND COMPUTING DEVICE USING SAME

PRIMAX ELECTRONICS LTD., ...

1. A touchpad module, comprising:a circuit board comprising at least one circuit board contact part; and
a surface mount device switch comprising:
a pedestal located under the circuit board, and comprising a first conducting part, a second conducting part and at least one pedestal contact part, wherein the at least one pedestal contact part is electrically connected with the at least one circuit board contact part;
a metal dome; and
at least one conductive buffering sheet arranged between the metal dome and the pedestal, and contacted with the first conducting part and/or the second conducting part,
wherein when the circuit board is pressed down and the surface mount device switch is moved downwardly to push a triggering part, the metal dome is subjected to deformation and contacted with the at least one conductive buffering sheet, so that the first conducting part and the second conducting part are electrically connected with each other.

US Pat. No. 10,510,498

TRAVEL SWITCH WITH HIGH-SAFETY LEVER STRUCTURE

Albert Chi Man Ao, Chino...

1. A travel switch with a high-safety lever structure, comprising:a travel adjustment device;
a transmission device;
a lever-structure electric-connection switch assembly;
an insulation assembly; and
a rivet fixing assembly;
wherein the lever-structure electric-connection switch assembly comprises a dual-energy-storage-reed structure and a stationary contact piece, wherein the dual-energy-storage-reed structure comprises a stationary reed and a moving reed, wherein one end of the moving reed and the stationary reed are arranged in intervals, and another end of the moving reed is fixedly connected with the stationary reed, wherein two sides of the moving reed are respectively provided with an energy storage reed, wherein one end of the energy storage reed is connected with a main body of the moving reed, and another end of the energy storage reed is provided with an open end, wherein two sides of the stationary reed are respectively provided with an energy storage reed positioning hook, and the open end of the energy storage reed is hooked with the energy storage reed positioning hook in a matched mode, wherein the moving reed is provided with a moving contact, and the stationary contact piece is provided with a stationary contact, wherein a moving contact limiting block is arranged on the stationary reed, wherein an upper portion of the moving contact is correspondingly connected with the stationary contact, and a lower portion of the moving contact is arranged to correspond to the moving contact limiting block; and
wherein the two sides of the stationary reed are respectively provided with a first reinforcing rib, wherein a positioning notch is formed in a tail portion of the stationary reed, wherein the two sides of the moving reed are respectively provided with a second reinforcing rib, wherein a positioning convex piece is arranged at an end portion of one end of the moving reed, wherein the positioning convex piece of the moving reed is arranged to correspond to the positioning notch of the stationary reed.

US Pat. No. 10,510,493

CORE-SHELL COMPOSITE, METHOD FOR PRODUCING THE SAME, ELECTRODE MATERIAL, CATALYST, ELECTRODE, SECONDARY BATTERY, AND ELECTRIC DOUBLE-LAYER CAPACITOR

TPR CO., LTD., Tokyo (JP...

1. A core-shell composite comprising a core formed from a carbon porous body having a large number of pores from an interior through to a surface, and a shell layer formed from conductive polymer nanorods that extend outward from cavities of pores on a surface of the core,wherein the conductive polymer nanorods narrow with increasing distance from the pores.

US Pat. No. 10,510,489

MOUNTING STRUCTURE AND MULTILAYER CAPACITOR BUILT-IN SUBSTRATE

MURATA MANUFACTURING CO.,...

1. A mounting structure comprising:a circuit board including one principal surface on which a multilayer capacitor is mounted; wherein
the circuit board includes a first insulating layer, and a second insulating layer having a Young's modulus smaller than a Young's modulus of the first insulating layer;
the second insulating layer is disposed closer to the one principal surface on which the multilayer capacitor is mounted than the first insulating layer;
a land is provided on the one principal surface of the circuit board; and
the multilayer capacitor is mounted on the land on the one principal surface.

US Pat. No. 10,510,484

FORMING AN ELECTRICAL COIL DEVICE BY CUTTING A STRIP CONDUCTOR WINDING INTO AT LEAST TWO PARTIAL COILS

SIEMENS AKTIENGESELLSCHAF...

1. A method for producing an electrical coil, the method comprising:winding a strip conductor into a coil winding having a stack of strip conductor layers,
wherein winding the strip conductor comprises winding a first portion of the strip conductor into the coil winding, but leaving at least one of an internal end piece or an external end piece of the strip conductor as an unwound projection, and
dividing the coil winding into at least two partial coils by performing at least one cut through the stack of strip conductor layers while the layers are wound in the coil winding,
wherein after the at least one cut through the stack of strip conductor layers, the strip conductor remains connected at end regions of the strip conductor, to thereby define the electrical coil including a contiguous loop shape of the strip conductor that includes the at least two partial coils and the connected end regions of the strip conductor.

US Pat. No. 10,510,481

TRANSFORMER SYSTEM WITH DYNAMIC CONTROL

1. A transformer system comprising:a magnetic core;
one or more windings, wherein each of the one or more windings comprise one or more sub-windings configured with a plurality of connection points;
a switching network connected to the plurality of connection points, wherein the switching network is controllably operative at one or more times during each quarter-cycle of an AC input voltage to select different effective numbers of turns in each winding;
whereby the transformer system transforms the AC input voltage to an AC output voltage which is regulated to a desired AC output voltage.

US Pat. No. 10,510,476

SLOW WAVE INDUCTIVE STRUCTURE AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A slow wave inductive structure comprising: a first substrate;a first conductive winding over the first substrate; and
a second substrate over the first substrate, the second substrate having a thickness ranging from about 50 nanometers (nm) to about 150 nm, wherein a distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m, wherein a second conductive winding on an opposite side of the second substrate from the first conductive winding and the second substrate comprises polysilicon or doped silicon.

US Pat. No. 10,510,474

SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS

University of Rochester, ...

1. A base element for switching a magnetization state of a nanomagnet comprising:a heavy-metal strip having a surface;
a ferromagnetic nanomagnet disposed adjacent to said surface, said ferromagnetic nanomagnet comprising a shape having a long axis and a short axis, said ferromagnetic nanomagnet having both a perpendicular-to-the-plane anisotropy Hkz and an in-plane anisotropy Hkx and said ferromagnetic nanomagnet having a first magnetization equilibrium state and a second magnetization equilibrium state, said first magnetization equilibrium state or said second magnetization equilibrium state settable in an absence of an external magnetic field by a flow of electrical charge through said heavy-metal strip; and
wherein a direction of flow of said electrical charge through said heavy-metal strip comprises an angle ? with respect to said short axis of said nanomagnet.

US Pat. No. 10,510,469

COAXIAL CABLE AND WIRING HARNESS USING SAME

YAZAKI CORPORATION, Toky...

1. A coaxial cable comprising:an inner conductor;
an insulator that is provided on an outer circumference of the inner conductor;
a film that abuts an outer circumference of the insulator;
an outer conductor that abuts on an outer circumference of the film; and
a sheath that is provided on an outer circumference of the outer conductor, wherein
at least a part of the film is colored, over an entire circumferential direction of the insulator, in a different color from both colors of the insulator and the outer conductor.

US Pat. No. 10,510,465

METHODS AND SYSTEMS FOR SECURELY ACCESSING AND MANAGING AGGREGATED SUBMARINE CABLE SYSTEM INFORMATION

Global Broadband Solution...

1. An architecture for providing end users with the ability to securely access and manage aggregated submarine cable (SC) system information, comprising:an information management sub-system;
an SC information storage sub-system configured to allow display of a plurality of SC System information as distinct images, where each image represent a type of SC System information, and wherein the information management sub-system and the SC information storage sub-system are further operable to generate an audit signal or message each time a communication occurs or a connection is established between an end-user device and the information management sub-system and the SC information storage sub-system, respectively;
an SC System administrative sub-system; a multi-factor authentication (MFA) sub-system operable to enable completion of multi-factor authentication compliant with National institutes of Standard And Technology (NIST) SP 800-171 and US. Government Defense Federal Acquisition Regulations requirements to access the aggregated, SC system information; and
a remote data monitoring and protection sub-system.

US Pat. No. 10,510,456

MULTI-LEAF COLLIMATOR AND DRIVING SYSTEM

SHANGHAI UNITED IMAGING H...

1. A multi-leaf collimator (MLC) comprising:a driving array comprising a plurality of motors;
a leaf array comprising a plurality of leaves; and
a plurality of elongated flexible transmission units, each connected to one of the leaves of the leaf array to form a collimator unit such that motors of the driving array are operably connected with leaves of the leaf array through the transmission units to form a MLC array that comprises a plurality of collimator units;
wherein in each collimator unit, the motor transmits motion from the motor to the leaf through the transmission unit to adjust the position of each leaf independently, and
wherein the transmission unit comprises a transmission line and an elastic piece operably connected to the transmission line, and the transmission line provides the leaf a first force, and the elastic piece provides the leaf a second force.

US Pat. No. 10,510,450

HEAT PIPE MOLTEN SALT FAST REACTOR WITH STAGNANT LIQUID CORE

Westinghouse Electric Com...

13. A nuclear reactor for operative connection to a power conversion system, the reactor comprising:a containment vessel;
a reactor core housed within the containment vessel;
a neutron reflector spaced froze the containment vessel and positioned between the core and the containment vessel;
a livid fuel comprised of a nuclear fission material dissolved in a molten salt enclosed within the core;
a plurality of heat transfer pipes, each pipe having a first end and a second end, the first end being positioned within the reactor core for absorbing heat from the fuel;
a heat exchanger external to the containment vessel, the heat exchanger receiving the second end of each heat transfer pipe for transferring heat from the core to the heat exchanger; and
at least three reactor shut down systems comprising a first shut down system, a second shut down system, and a third shut down system, the first shut down system comprising:
a rotatable member mechanism comprising:
a plurality of rotatable members positioned evenly within the neutron reflector, each rotatable member having a neutron absorber section and a non-absorber section; and,
a rotating drive mechanism operatively connected to each rotatable member for rotating the rotatable member to move the neutron absorber section to one of a first position facing the core and a second position facing away from the core;
the second shut down s stem comprising:
a melt-plug mechanism comprising:
an opening in the containment vessel;
a chamber fluidly connected to the opening in the containment vessel;
a first melt plug, to plug the opening in the containment vessel;
the first melt plug being made of a material that melts at a predetermined melting temperature deemed to be indicative of unsafe temperature conditions within the reactor core; and the third shut down system comprising:
a central axis extending through the core and a neutron absorber activation system comprising
a hollow tube defining a cavity and being positioned coaxially to the central axis and extending from an area above the core into the core;
a gate separating a first portion of the hollow tube above the core from a second portion of the hollow tube within the core;
a neutron absorber material housed in an unactivated position within the first portion of the hollow tube;
an activation rod operatively connected to the gate;
a release member for releasing the actuation rod from the unactivated position to move to an activated position, wherein in the activated position, the actuation rod opens the gate to release the neutron absorber material into the cavity within the second portion of the hollow tube in proximity to the fuel to absorb neutrons from the fuel sufficient to shut down the reactor.

US Pat. No. 10,510,438

SYSTEM AND METHOD FOR BUILDING INTUITIVE CLINICAL TRIAL APPLICATIONS

Definitive Media Corp., ...

1. A method for remote clinical trial organization, the method comprising;receiving a response to at least a first question from a hierarchy of questions designed to identify one or more elements necessary to complete a clinical trial in an application-based testing environment;
positing at least a second question from the hierarchy of questions, the second question based on the received response to the at least first question, whereby the collective responses to the questions are used to access the identified elements from a database of elements, wherein the database is updated with modules and applications related to application self-construction;
constructing an application for the clinical trial based on the collective responses, the application constructed as an arrangement of the identified elements and including any clinical and consumer medical monitoring devices necessary for the trial;
processing data collected from a trial subject utilizing the application for the clinical trial and any corresponding clinical and consumer medical monitoring devices, the data processed at a cloud-based server environment including at least one server from a server farm and that stores and instantiates a software platform that organizes the clinical trial through authoring of the application and that further operates in conjunction with the clinical trial; and
modifying the application in real-time responsive to the processed data collected from the trial subject, wherein modifying the application includes modifying the arrangement of the identified elements within the application.

US Pat. No. 10,510,418

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a cell string including a plurality of memory cells coupled in series between a common source line and a bit line;
a common source line controller configured to provide a channel current to the cell string through the common source line in a read operation; and
a page buffer configured to sense data stored in a selected memory cell among the plurality of memory cells based on a current of the bit line when the channel current is provided,
wherein the common source line controller precharges the bit line with the channel current supplied to the cell string through the common source line,
wherein, after the bit line is precharged, the page buffer senses the data stored in the selected memory cell based on a voltage of the bit line transmitted to a sensing node.

US Pat. No. 10,510,393

RESISTIVE MEMORY DEVICE INCLUDING REFERENCE CELL AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device comprising:a cell array including the memory cell and a reference cell;
a reference resistance circuit electrically connected to the reference cell;
an offset current source circuit configured to generate an offset current based on a control signal, the offset current being combined with a read current provided to the reference resistance circuit to increase or decrease a magnitude of the read current; and
a control circuit configured to generate the control signal to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.