US Pat. No. 10,461,150

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor device comprising:a substrate;
a first transistor formed on the substrate, and including a first impurity region of a first conductivity type, and a second impurity region of the first conductivity type;
a second transistor formed on the substrate, and including a third impurity region of the first conductivity type electrically connected to the second impurity region, and a fourth impurity region of the first conductivity type;
a power supply terminal electrically connected to the first impurity region;
a ground terminal electrically connected to the fourth impurity region;
a first guard ring of a second conductivity type different from the first conductivity type, formed on the substrate, surrounding the first transistor in a plan view, and electrically connected to the ground terminal; and
a second guard ring of the second conductivity type, formed on the substrate, surrounding the second transistor in a plan view, and electrically connected to the ground terminal,
wherein the first guard ring includes a first part having a longitudinal axis which extends in a first direction in the plan view,
wherein the second guard ring includes a second part having a longitudinal axis which extends in the first direction in the plan view, and
wherein a width of the second part along a second direction, which is perpendicular to the first direction, is narrower than a width of the first part along the second direction in a plan view.

US Pat. No. 10,461,149

ELEVATIONALLY-ELONGATED CONDUCTIVE STRUCTURE OF INTEGRATED CIRCUITRY, METHOD OF FORMING AN ARRAY OF CAPACITORS, METHOD OF FORMING DRAM CIRCUITRY, AND METHOD OF FORMING AN ELEVATIONALLY-ELONGATED CONDUCTIVE STRUCTURE OF INTEGRATED CIRCUITRY

Micron Technology, Inc., ...

1. A method of forming an array of capacitors, comprising:providing a substrate comprising an array of horizontally-elongated and laterally-spaced conductive-line structures, conductive vias being laterally between and spaced longitudinally along immediately-laterally-adjacent of the conductive-line structures;
forming conductive material directly above the conductive-line structures and directly above and directly against the conductive vias, the conductive material having an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section, the conductive material having a second sidewall directly above an immediately-laterally-adjacent of the conductive-line structures in the vertical cross-section;
forming covering material directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias, the covering material comprising a composition different from that of at least some of the conductive material;
etching completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching into said conductive material below uppermost surfaces of the conductive-line structures, the covering material that is against the individual first sidewalls masking the individual first sidewalls from being etched during said etchings; and
forming a plurality of capacitors individually comprising a lower conductive electrode, an upper conductive electrode, and a capacitor insulator there-between; individual of the lower conductive electrodes comprising the conductive material directly above said immediately-laterally-adjacent individual conductive-line structures.

US Pat. No. 10,461,148

MULTILAYER BURIED METAL-INSULTOR-METAL CAPACITOR STRUCTURES

International Business Ma...

1. A method comprising:providing an insulator layer overlying a semiconductor substrate;
forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer;
forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers;
forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer; and
etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first trench greater than the second conductive layers, wherein each of the plurality of the recessed first conductive layers and the second recessed second conductive layers are in continuous contact with the at least one dielectric layer between each of the alternating recessed first conductive layers and the second recessed second conductive layers.

US Pat. No. 10,461,147

SEMICONDUCTOR DEVICE FABRICATING METHOD AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising:a lower electrode disposed on a substrate;
a first insulating film disposed on one portion of an upper surface of the lower electrode;
an upper electrode disposed on one portion of an upper surface of the first insulating film;
a second insulating film that covers the upper electrode, another portion of the upper surface of the first insulating film other than the one portion of the upper surface of the first insulating film and
covers another portion of the upper surface of the lower electrode other than the one portion of the upper surface of the lower electrode;
a first conductive portion formed in a first open portion of the second insulating film, the first open portion runs through the second insulating film and exposes the upper electrode, and the first conductive portion is electrically connected to the upper electrode; and
a second conductive portion formed in a second open portion of the second insulating film, the second open portion runs through the second insulating film and exposes the lower electrode, and the second conductive portion is electrically connected to the lower electrode;
wherein a material of the first insulating film is different from a material of the second insulating film and the second insulating film extends beyond the second open portion on the another portion of the upper surface of the lower electrode.

US Pat. No. 10,461,146

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

UNIMICRON TECHNOLOGY CORP...

1. A package structure, comprising:a substrate;
a metal-insulator-metal capacitor disposed on the substrate, comprising a first electrode, a second electrode, and an insulating layer, wherein the insulating layer is disposed between the first electrode and the second electrode;
a circuit redistribution structure disposed on the metal-insulator-metal capacitor, wherein the circuit redistribution structure comprises:
a first circuit redistribution layer, comprising a first wire and a second wire, wherein the first wire is electrically connected to the first electrode, and the second wire is electrically connected to the second electrode; and
a second circuit redistribution layer disposed on the first circuit redistribution layer, comprising a third wire and a fourth wire, wherein the third wire is electrically connected to the first wire, and the fourth wire is electrically connected to the second wire; and
a chip disposed on the circuit redistribution structure and electrically connected to the third wire and the fourth wire.

US Pat. No. 10,461,145

METHOD FOR FABRICATING MAGNETIC CORE

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a magnetic core, comprising:depositing a magnetic layer on a dielectric layer;
forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer;
etching the magnetic layer through the patterned first photoresist layer, wherein a first section of the magnetic layer exposed by the patterned first photoresist layer remains on the dielectric layer after etching the magnetic layer;
removing the patterned first photoresist layer;
forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer such that the patterned second photoresist layer has a curve portion;
etching the magnetic layer through the patterned second photoresist layer such that the curve portion of the patterned second photoresist layer suspends without support above the magnetic layer; and
removing the patterned second photoresist layer.

US Pat. No. 10,461,144

CIRCUIT FOR PREVENTING STATIC ELECTRICITY AND DISPLAY DEVICE HAVING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a display unit comprising a plurality of pixels in a display region;
a driving circuit in a non-display region, the driving circuit being configured to drive the display unit;
a first clock signal wire configured to transmit a first clock signal to the driving circuit; and
a first circuit in the non-display region,
wherein the first circuit comprises:
a transistor electrically coupled to the first clock signal wire through a conductive wire and comprising a source electrode, a drain electrode, and a gate electrode; and
a capacitor comprising a first electrode coupled to the source electrode and to the drain electrode of the transistor, and a second electrode,
wherein the conductive wire is coupled to the first clock signal wire through a first contact hole and coupled to the gate electrode, and
wherein the second electrode of the capacitor is configured to receive a fixed voltage so that the second electrode is set to a voltage of the fixed voltage.

US Pat. No. 10,461,143

TRANSISTOR SUBSTRATE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE TRANSISTOR SUBSTRATE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a pixel electrode;
a common electrode overlapping the pixel electrode;
a light emitting layer positioned between the pixel electrode and the common electrode;
a base substrate;
a data line disposed on the base substrate;
a conductive layer disposed on the base substrate and being spaced from the data line;
a semiconductor layer overlapping the conductive layer, being spaced from the conductive layer, and comprising a source electrode and a drain electrode, wherein the source electrode is electrically connected to the data line, and wherein the drain electrode is electrically connected to the pixel electrode; and
a gate electrode overlapping the semiconductor layer,
wherein the base substrate is a single layer structure or a multilayer structure having a polymer.

US Pat. No. 10,461,142

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a base layer including a plurality of islands in which a pixel is disposed, and a plurality of bridges disposed around each of the plurality of islands;
an inorganic insulating layer disposed on the base layer and having an opening exposing a portion of the bridge;
an organic material layer covering the opening; and
a plurality of first wires disposed on a bridge of the plurality of bridges and electrically connected to the pixel,
wherein adjacent islands of the plurality of islands are connected to each other through at least the bridge of the plurality of bridges,
and the plurality of first wires are disposed on the organic material layer.

US Pat. No. 10,461,141

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A display device comprising:a substrate;
a buffer layer disposed on the substrate;
a first semiconductor layer of a first thin film transistor disposed on the buffer layer;
a gate insulating layer disposed on a channel region of the first semiconductor layer, on a source region of the first semiconductor layer, and on a drain region of the first semiconductor layer;
a first gate electrode disposed on the gate insulating layer over the channel region of the first semiconductor layer;
a first source electrode in direct contact with the source region of the first semiconductor layer, wherein the first source electrode is disposed on the gate insulating layer over the source region of the first semiconductor layer and contacts the source region of the first semiconductor layer via a first channel hole through the gate insulating layer;
a first drain electrode in direct contact with the drain region of the first semiconductor layer, wherein the first drain electrode is disposed on the gate insulating layer over the drain region of the first semiconductor layer and contacts the drain region of the first semiconductor layer via a second channel hole through the gate insulating layer;
a passivation layer disposed on the first gate electrode, the first source electrode, and the first drain electrode, wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first source electrode and the first gate electrode, and wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first gate electrode and the first drain electrode,
wherein the first gate electrode, the first source electrode, and the first drain electrode are in a same layer and comprise a same material.

US Pat. No. 10,461,140

LIGHT EMITTING DEVICE

Semiconductor Energy Labo...

1. A light emitting device comprising:a current control transistor;
a light emitting element;
a power supply line; and
a capacitor,
wherein one of a source and a drain of the current control transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the current control transistor is electrically connected to the light emitting element,
wherein a part of the power supply line is configured to function as one terminal of the capacitor,
wherein a part of a gate electrode of the current control transistor is configured to function as the other terminal of the capacitor,
wherein the current control transistor is driven in a saturation region, and
wherein the current control transistor has a channel conductance gd from 0 to 1×10?8 S.

US Pat. No. 10,461,139

LIGHT EMITTING DEVICE MANUFACTURING METHOD AND APPARATUS THEREOF

INT TECH CO., LTD., Hsin...

1. A method of manufacturing a light emitting device, comprising:providing a substrate;
forming a plurality of photosensitive bumps over the substrate;
forming a photosensitive layer over the plurality of photosensitive bumps;
forming a buffer layer between the photosensitive layer and the plurality of photosensitive bumps;
patterning the photosensitive layer to form a recess through the photosensitive layer to expose a surface;
disposing an organic emissive layer on the surface,
forming a metal containing layer over the organic emissive layer, and
removing the patterned photosensitive layer.

US Pat. No. 10,461,138

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

BOE Technology Group Co.,...

1. An organic light-emitting display device, comprising:a substrate;
a plurality of pixel definition strips disposed on the substrate, wherein the plurality of pixel definition strips are spaced apart from and arranged in parallel with each other, and two adjacent pixel definition strips among the plurality of pixel definition strips and a portion of the substrate between the two adjacent pixel definition strips constitute a pixel definition groove; and
an organic light-emitting functional layer disposed in the pixel definition groove, wherein the organic light-emitting functional layer comprises a plurality of sub organic light-emitting functional layers which are insulated with each other and arranged along an extension direction of the plurality of pixel definition strips.

US Pat. No. 10,461,137

ORGANIC ELECTROLUMINESCENT DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME

BOE Technology Group Co.,...

1. An organic electroluminescent display panel, comprising a substrate, and a pixel defining layer and a light emitting layer on the substrate, wherein:the pixel defining layer comprises a first pixel defining layer on the substrate, a second pixel defining layer on the first pixel defining layer, and a third pixel defining layer between the first pixel defining layer and the second pixel defining layer;
the first pixel defining layer comprises a plurality of first opening areas, each of which defines a sub-pixel light emitting area, and the light emitting layer is arranged in the plurality of first opening areas;
the second pixel defining layer comprises a plurality of second opening areas, each of which defines a virtual pixel area comprising at least two adjacent sub-pixel light emitting areas in a same color; and
the third pixel defining layer comprises a plurality of third opening areas corresponding to the plurality of first opening areas in a one-to-one manner, and each of the plurality of third opening areas is not larger than a corresponding first opening area;
wherein respective virtual pixel areas defined by the plurality of second opening areas comprise a same number of sub-pixel light emitting areas; and virtual pixel areas containing red sub-pixel light emitting areas, virtual pixel areas containing green sub-pixel light emitting areas, and virtual pixel areas containing blue sub-pixel light emitting areas are disposed alternately in each row of the respective virtual pixel areas; and
wherein sidewalls of respective first opening areas, respective second opening areas, and respective third opening areas are sloped, top areas of the respective first opening areas and the respective third opening areas are smaller than their corresponding bottom areas, and top areas of the respective second opening areas are greater than their corresponding bottom areas.

US Pat. No. 10,461,136

ORGANIC ELECTROLUMINESCENT DISPLAY PANEL WITH SEMICONDUCTOR LAYER, MANUFACTURING METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An organic electroluminescent display panel comprising:a base substrate, a first electrode and a second electrode on the base substrate, and an organic light emitting layer located between the first electrode and the second electrode, wherein the first electrode is closer to the base substrate than the second electrode,
wherein the organic electroluminescent display panel further comprises a semiconductor layer covering the entire base substrate of the display panel, wherein the semiconductor layer is located between the organic light emitting layer and one of the first electrode and the second electrode,
wherein the semiconductor layer comprises a first portion and a second portion, an orthographic projection of the first portion of the semiconductor layer on the first electrode overlaps the first electrode, the second portion of the semiconductor layer covers a side surface of the first electrode, the side surface of the first electrode is crossed with a plane where the base substrate is located, and the first portion of the semiconductor layer and the second portion of the semiconductor layer are integral.

US Pat. No. 10,461,135

FLEXIBLE DISPLAY PANEL AND FABRICATION METHOD THEREOF, AND FLEXIBLE DISPLAY DEVICE

Shanghai Tianma Micro-Ele...

11. A flexible display device including a flexible display panel, wherein the flexible display panel comprises:a stacked structure having a plurality of layers comprising a flexible substrate, a light-emitting device layer, and a polarizing layer stacked in a preset order;
at least one upper-side resistive force-sensitive electrode disposed on a layer above a neutral plane of the stacked structure; and
at least one lower-side resistive force-sensitive electrode disposed on a layer below the neutral plane, wherein:
each upper-side resistive force-sensitive electrode includes a first resistive force-sensitive electrode and a second resistive force-sensitive electrode,
each lower-side resistive force-sensitive electrode includes a third resistive force-sensitive electrode and a fourth resistive force-sensitive electrode,
the first resistive force-sensitive electrode, the second resistive force-sensitive electrode, the third resistive force-sensitive electrode, and the fourth resistive force-sensitive electrode are electrically connected to form a bridge circuit,
the bridge circuit further includes a positive terminal, a negative terminal, a first voltage terminal, and a second voltage terminal,
one end of the first resistive force-sensitive electrode being electrically connected to one end of the third resistive force-sensitive electrode,
one end of the second resistive force-sensitive electrode being electrically connected to one end of the fourth resistive force-sensitive electrode,
another end of the first resistive force-sensitive electrode being electrically connected to another end of the fourth resistive force-sensitive electrode,
another end of the third resistive force-sensitive electrode being electrically connected to another end of the second resistive force-sensitive electrode,
a connection node between the first resistive force-sensitive electrode and the third resistive force-sensitive electrode is connected to one of the positive terminal and the negative terminal,
a connection node between the second resistive force-sensitive electrode and the fourth resistive force-sensitive electrode is connected to the other one of the positive terminal and the negative terminal,
a connection node between the first resistive force-sensitive electrode and the fourth resistive force-sensitive electrode is connected to the first voltage terminal, and
a connection node between the third resistive force-sensitive electrode and the second resistive force-sensitive electrode is connected to the second voltage terminal.

US Pat. No. 10,461,134

LIGHT-EMITTING DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first light-emitting element comprising:
a first electrode that is reflective;
a first light-emitting layer;
a second light-emitting layer over the first light-emitting layer; and
a second electrode;
a second light-emitting element comprising:
a third electrode that is reflective;
the first light-emitting layer;
the second light-emitting layer over the first light-emitting layer; and
the second electrode;
a first color filter overlapping with the first light-emitting element and having a first central wavelength of a first wavelength range in which the first color filter has a transmittance of 50% or higher in a visible wavelength range; and
a second color filter overlapping with the second light-emitting element and having a second central wavelength of a second wavelength range in which the second color filter has a transmittance of 50% or higher in the visible light range,
wherein the first wavelength range is different from the second wavelength range,
wherein the first central wavelength is different from the second central wavelength, and
wherein a first optical path length between the first light-emitting layer and the first electrode is different from a second optical path length between the second light-emitting layer and the third electrode in accordance with the difference between the first central wavelength and the second central wavelength.

US Pat. No. 10,461,133

LIGHT EMITTING DISPLAY DEVICE INCLUDING AN INFRARED RAY LIGHT EMITTING DIODE

Samsung Display Co., Ltd....

1. A light emitting display device comprising:a first electrode on a substrate;
a second electrode overlapping the first electrode;
a red emission layer, a green emission layer, a blue emission layer, and an infrared ray emission layer between the first electrode and the second electrode and emitting light of different wavelengths from each other;
a green resonance auxiliary layer between the green emission layer and the first electrode; and
a blocking layer between the green resonance auxiliary layer and the green emission layer,
wherein the infrared ray emission layer and the green resonance auxiliary layer comprise the same material,
the green emission layer comprises a green light emitting dopant, and
a Lowest Unoccupied Molecular Orbital (LUMO) energy of the blocking layer is larger than a LUMO energy of the green light emitting dopant.

US Pat. No. 10,461,132

DISPLAY APPARATUS AND METHOD FOR MANUFACTURING SAME

SHARP KABUSHIKI KAISHA, ...

1. A display apparatus comprising:a display region;
a first electrode;
a second electrode; and
a layered body formed between the first electrode and the second electrode,
wherein the display region includes
a first subpixel,
a second subpixel, and
a third subpixel,
the first subpixel, the second subpixel, and the third subpixel emit their respective light having mutually different peak wavelengths,
the layered body includes
a first light-emitting layer containing a first fluorescent luminescent material,
a second light-emitting layer containing a second fluorescent luminescent material,
a third light-emitting layer containing a third fluorescent luminescent material or a phosphorescent luminescent material as a luminescent material, and
a separation layer containing no luminescent material,
the second fluorescent luminescent material has a lower energy level in a minimum excited singlet state than an energy level of the first fluorescent luminescent material in the minimum excited singlet state,
the third fluorescent luminescent material or the phosphorescent luminescent material has a lower energy level in a minimum excited singlet state than the energy level of the second fluorescent luminescent material in the minimum excited singlet state,
the second light-emitting layer is formed as a layer that is common to the first subpixel, the second subpixel, and the third subpixel,
the first light-emitting layer is formed only in the first subpixel,
the third light-emitting layer is formed only in the third subpixel,
the separation layer is formed between the first light-emitting layer and the second light-emitting layer in the first subpixel, and
a distance between the first light-emitting layer and the second light-emitting layer in the first subpixel is greater than a Förster radius.

US Pat. No. 10,461,131

QUANTUM DOT LED AND OLED INTEGRATION FOR HIGH EFFICIENCY DISPLAYS

Apple Inc., Cupertino, C...

1. A display comprising:a tandem hybrid pixel including an organic light emitting diode (OLED) subpixel and a quantum dot light emitting diode (QD-LED) subpixel;
a common hole transport layer in the OLED subpixel and the QD-LED subpixel;
a common quantum dot layer over the common hole transport layer in the QD-LED subpixel and in the OLED subpixel;
a semi-common charge generation layer over the common quantum dot layer in the OLED subpixel;
a first cathode over the common quantum dot layer in the QD-LED subpixel;
a semi-common hole transport layer over the semi-common charge generation layer in the OLED subpixel;
an organic emission layer over the semi-common hole transport layer in the OLED subpixel;
a semi-common electron transport layer over the organic emission layer in the OLED subpixel; and
a semi-common second cathode over the semi-common electron transport layer in the OLED subpixel.

US Pat. No. 10,461,130

IMAGE DEVICE INCLUDING PHOTOELECTRIC CONVERSION LAYER

PANASONIC INTELLECTUAL PR...

1. An imaging device comprising unit pixels, each unit pixel including:a photoelectric conversion unit including
a first electrode including a first conducting material,
a second electrode facing the first electrode,
a photoelectric conversion layer between the first and second electrodes, the photoelectric conversion layer including a first photoelectric conversion material, and
an electron-blocking layer between the first electrode and the photoelectric conversion layer, the electron-blocking layer including an electron-blocking material; and
a signal detection circuit electrically connected to the first electrode, wherein
the electron-blocking material has an ionization potential higher than both a work function of the first conducting material and an ionization potential of the first photoelectric conversion material,
the photoelectric conversion unit is adapted to be applied with a voltage between the first electrode and the second electrode, and the photoelectric conversion unit has a characteristic, responsive to the voltage within a range from a first voltage to a second voltage, showing that a density of current passing between the first electrode and the second electrode when light is incident on the photoelectric conversion layer becomes substantially equal to that when no light is incident on the photoelectric conversion layer, and
a difference between the first voltage and the second voltage is 0.5 V or more.

US Pat. No. 10,461,129

DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION CONSISTING OF ORGANIC MATERIALS

ISORG, Grenoble (FR)

1. An electromagnetic radiation detection device comprising: at least one row of photoresistors, each photoresistor comprising an active portion comprising organic semiconductor materials; emitters of the electromagnetic radiation; and a waveguide; wherein the waveguide comprises at least one surface intended to be in contact with at least one object, the photoresistors being distributed along an edge of said surface, the emitters being located along said edge.

US Pat. No. 10,461,128

ARRAYS OF MEMORY CELLS AND METHODS OF FORMING AN ARRAY OF ELEVATIONALLY-OUTER-TIER MEMORY CELLS AND ELEVATIONALLY-INNER-TIER MEMORY CELLS

Micron Technology, Inc., ...

1. A method of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells, comprising:forming an elevationally-inner tier of line constructions comprising spaced-lower-first-conductive lines, programmable material directly above the inner-tier-lower-first-conductive lines, and insulator material over sidewalls of the inner-tier-lower-first-conductive lines and over sidewalls of the inner-tier-programmable material;
forming an elevationally-outer tier of line constructions comprising spaced-lower-first-conductive lines, spaced-programmable-material lines directly above the outer-tier-lower-first-conductive lines, and insulative material over sidewalls of the outer-tier-lower-first-conductive lines and over sidewalls of the outer-tier-programmable-material lines; individual of the outer-tier-lower-first-conductive lines being laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions, the forming of the outer-tier-line constructions comprising:
forming at least lowermost portions of the outer-tier-lower-first-conductive lines in a self-aligned manner by depositing conductive material laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions;
forming the outer-tier-programmable material directly above the conductive material;
patterning at least the outer-tier-programmable material to form lines thereof that are directly above the lowermost portions of the outer-tier-lower-first-conductive lines; and
forming the insulative material over tops and the sidewalls of the outer-tier-programmable material lines and then anisotropically etching the insulative material to remove it from being over the tops; and
forming spaced-upper-second-conductive lines for each of an elevationally-outer tier of memory cells and an elevationally-inner tier of memory cells.

US Pat. No. 10,461,127

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A variable resistance memory device comprising:a first conductive line on a substrate, the first conductive line extending in a first direction;
a second conductive line on the first conductive line, the second conductive line extending in a second direction, the second direction being a direction crossing the first direction; and
a memory cell pillar connected to the first conductive line and the second conductive line at an intersection point therebetween, the memory cell pillar including a heating electrode layer and a variable resistance layer, the variable resistance layer in contact with the heating electrode layer, two opposite sidewalls of the heating electrode layer aligned with two opposite sidewalls of the first conductive line in the first direction, respectively.

US Pat. No. 10,461,126

MEMORY CIRCUIT AND FORMATION METHOD THEREOF

Taiwan Semiconductor Manu...

1. A memory circuit, comprising:a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal;
a first memory device having a first lower electrode separated from a first upper electrode by a first data storage layer, wherein the first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line; and
a second memory device having a second lower electrode separated from a second upper electrode by a second data storage layer, wherein the second upper electrode is coupled to a second bit-line and the second lower electrode is coupled to the third terminal.

US Pat. No. 10,461,125

THREE DIMENSIONAL MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a plurality of first dielectric materials and a plurality of stacks, wherein each respective first dielectric material and each respective stack alternate, and wherein each respective stack comprises a first conductive material and a storage material on only one side of the first conductive material;
a second conductive material passing through the plurality of first dielectric materials and the plurality of stacks such that a major axis of the second conductive material is perpendicular to a major axis of the storage material; and
a second dielectric material in direct physical contact with the second conductive material and passing through the plurality of first dielectric materials and the plurality of stacks between the second conductive material and the plurality of stacks;
wherein each respective stack further comprises a third dielectric material between the first conductive material and the second dielectric material such that the storage material of the respective stack is on only one side of the third dielectric material, the second dielectric material is between the second conductive material and the third dielectric material, and the third dielectric material is in direct physical contact with the first conductive material and the second dielectric material.

US Pat. No. 10,461,124

ULTRASONIC SENSING DEVICE

InvenSense, Inc., San Jo...

1. An electronic device comprising:a CMOS substrate having a first surface and a second surface opposite the first surface;
a plurality of Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices having a transmit/receive surface, wherein the transmit/receive surface is disposed on the second surface of the CMOS substrate, wherein at least one PMUT device comprises:
an edge support structure connected to the CMOS substrate; and
a membrane connected to the edge support structure such that a cavity is defined between the membrane and the CMOS substrate, the membrane configured to allow movement at ultrasonic frequencies, the membrane comprising:
a piezoelectric layer; and
first and second electrodes coupled to opposing sides of the piezoelectric layer; and
an interior support structure disposed within the cavity and connected to the CMOS substrate and the membrane; and
a contact surface piezoelectrically associated with the plurality of PMUT devices and disposed on the first surface;
wherein the CMOS substrate is between the plurality of PMUT devices and the contact surface.

US Pat. No. 10,461,123

LIGHT EMITTING DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A light emitting device, comprising:a substrate;
a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction;
one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element;
a first reflection electrode adjacent the first end portion of the light emitting element;
a second reflection electrode adjacent the second end portion of the light emitting element;
a first contact electrode directly connected to the first reflection electrode and the first end portion of the light emitting element;
an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and
a second contact electrode on the insulating layer, the second contact electrode being connected to the second reflection electrode and the second end portion of the light emitting element through the opening.

US Pat. No. 10,461,122

LIGHT EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light emitting diode display panel, comprising:a substrate;
a plurality of light emitting diodes arranged in an array on the substrate;
a plurality of polarization layers, located on a light exit side of the plurality of light emitting diodes respectively, and the plurality of polarization layers are in a one-to-one correspondence to the plurality of light emitting diodes;
wherein the plurality of polarization layers comprise a plurality of first polarization layers and a plurality of second polarization layers having different polarization directions.

US Pat. No. 10,461,121

MINIATURE LED DISPLAY PANEL AND MINIATURE LED DISPLAY

SHENZHEN CHINA STAR OPTOE...

1. A miniature LED display panel comprising:a first substrate;
a second substrate having a cathode driving circuit disposed on a surface of the second substrate facing the first substrate;
N row signal lines disposed on the first substrate;
an insulating layer disposed on the first substrate and the row signal lines;
M column signal lines disposed on the insulating layer;
M compensation signal lines disposed on the insulating layer; and
a plurality of LED light emitting components arranged in an array of M rows and N columns on the first substrate;
wherein the LED light emitting components in a same row are electrically connected with a same row signal line, the LED light emitting components in a same column are electrically connected with a same compensation signal line and a same column signal line, and one end of each of the LED light emitting components away from the first substrate is connected with the second substrate and electrically connected with the cathode driving circuit; and
wherein each of the LED light emitting components comprises:
a first thin film transistor disposed on the first substrate and having a source electrically connected with a corresponding column signal line and a gate electrically connected with a corresponding row signal line;
a second thin film transistor disposed on the first substrate and having a source connected with a corresponding compensation signal line and a gate electrically connected with a drain of the first thin film transistor;
a first connecting metal layer disposed on the first substrate and electrically connected with a corresponding row signal line;
a second connecting metal layer disposed on the insulating layer, wherein the first connecting metal layer and the second connecting metal layer partially face each other to form a storage capacitor; and
a light emitting unit having one end electrically connected with the cathode driving circuit and the other end electrically connected with the second connecting metal layer and a drain of the second thin film transistor;
wherein the insulating layer is a silicon nitride layer or a silicon dioxide layer;
wherein each of the first substrate and the second substrate is a glass substrate; and
wherein the light emitting unit is an inorganic LED.

US Pat. No. 10,461,120

DISPLAY DEVICE AND METHOD FOR PRODUCING A DISPLAY DEVICE

OSRAM Opto Semiconductors...

1. A pixel headlight comprising:a carrier; and
a semiconductor layer sequence having a major face facing the carrier, the semiconductor layer sequence comprising a first semiconductor layer, a second semiconductor layer, and an active region arranged between the first semiconductor layer and the second semiconductor layer, the active region adapted to generate radiation and form a plurality of pixels;
wherein the semiconductor layer sequence comprises a recess that extends from the major face of the semiconductor layer sequence through the active region into the first semiconductor layer and is provided for electrical contacting of the first semiconductor layer; and
wherein the carrier comprises a plurality of switches that are integrated into the carrier, each switch provided for controlling at least one pixel.

US Pat. No. 10,461,119

SOLID-STATE IMAGING DEVICE, IMAGING SYSTEM, AND METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE

Canon Kabushiki Kaisha, ...

1. A solid-state imaging device, comprising:a pixel including a photoelectric conversion element and a charge holding portion to which a charge generated by the photoelectric conversion element is transferred in a pixel region;
a peripheral circuit that processes a signal from the pixel in a peripheral region;
a light-shielding layer that is disposed in the pixel region and the peripheral region and that is electrically connected to a substrate at a contact portion in the peripheral region;
a first insulating layer that has a side surface between the charge holding portion and the contact portion in a plan view and that is disposed between the substrate and the light-shielding layer in a section perpendicular to a plane of the plan view; and
a first insulating member that is disposed on the side surface of the first insulating layer,
wherein an angle formed between an upper surface of the first insulating layer and a side surface of the first insulating member is larger than an angle formed between the upper surface of the first insulating layer and the side surface of the first insulating layer, and
wherein a portion of the light-shielding layer that overlaps the first insulating member in the plan view has an upper surface having a shape following a shape of the first insulating member.

US Pat. No. 10,461,118

METHOD FOR MAKING CMOS IMAGE SENSOR INCLUDING PHOTODIODES WITH OVERLYING SUPERLATTICES TO REDUCE CROSSTALK

ATOMERA INCORPORATED, Lo...

15. A method for making a CMOS image sensor comprising:forming a plurality of laterally adjacent photodiodes on a semiconductor substrate by
forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well also having the second conductivity type,
forming a second well within the retrograde well having the first conductivity type, and
forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

US Pat. No. 10,461,117

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

XINTEC INC., Taoyuan (TW...

1. A method for manufacturing semiconductor structure, comprising:(a) adhering a first carrier to a first surface of a wafer by a first temporary bonding layer;
(b) etching a second surface of the wafer facing away from the first carrier to form at least one through hole and at least one trench, wherein a conductive pad of the wafer is exposed through the through hole;
(c) forming an isolation layer on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench;
(d) forming a redistribution layer on the isolation layer and the conductive pad;
(e) adhering a second carrier to the second surface of the wafer by a second temporary bonding layer, wherein the through hole and the trench are covered by the second carrier;
(f) removing the first carrier and the first temporary bonding layer;
(g) disposing an optical element that has a dam element on the first surface of the wafer;
(h) removing the second carrier and the second temporary bonding layer after the optical element is disposed on the first surface of the wafer; and
(i) forming an insulating layer that covers the redistribution layer, the through hole, and the trench after the second carrier and the second temporary bonding layer are removed.

US Pat. No. 10,461,116

SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR DEVICE BASED ON MOLDING PROCESS

NINGBO SUNNY OPOTECH CO.,...

1. An image processing assembly, comprising:an encapsulated component;
a photosensitive element, supported by at least one portion of a top surface of the encapsulated component;
a compensation part, disposed in a portion of the top surface of the encapsulated component other than the at least one portion, and in contact with a side portion of the photosensitive element; and
a packaging component, configured to embed at least two of the photosensitive element, the encapsulated component, and the compensation part; wherein the compensation part is distributed around the photosensitive element to form a frame.

US Pat. No. 10,461,115

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. A photodiode array comprising a plurality of photodiodes formed in a semiconductor substrate,wherein each of the photodiodes includes:
a first semiconductor region of a first conductivity type, and provided in the semiconductor substrate;
a second semiconductor region of a second conductivity type, provided with respect to the first semiconductor region on one surface side of the semiconductor substrate so as to surround a predetermined region, and constituting a light detection region together with the first semiconductor region; and
a through-electrode provided within a through-hole passing through the one surface and another surface of the semiconductor substrate so as to pass through the first semiconductor region and the predetermined region, and electrically connected to the second semiconductor region, wherein:
the through-hole includes a portion expanded from the one surface toward the another surface,
the predetermined region is surrounded by one monolithic or a plurality of second semiconductor regions electrically connected to the through-electrode so that the predetermined region is surrounded by an inner edge of the one monolithic second semiconductor region that is electrically connected to the through-electrode, or so that the predetermined region is surrounded by each inner edge of the plurality of second semiconductor regions that are electrically connected commonly to the through-electrode,
each of the one or more inner edges of the one monolithic or plurality of second semiconductor regions is separated from an aperture edge of the through-hole on the one surface side of the semiconductor substrate,
a portion of the first semiconductor region is included in the predetermined region between the inner edge of the second semiconductor region and the aperture edge of the through-hole on the one surface side,
each of the photodiodes includes a contact electrode formed on the one surface and electrically connecting the second semiconductor region and the through-electrode, and
the contact electrode comprises metal, covers an aperture of through-hole on the one surface side, and extends to the predetermined region surrounded by the second semiconductor region.

US Pat. No. 10,461,114

MARKING SYSTEM AND METHOD

LMD Power of Light Corpor...

1. An infrared laser emitting system comprising:a quantum cascade laser emitter configured to generate a beam of infrared radiation;
an optical system downstream of the quantum cascade laser emitter, the optical system being configured to receive the beam of infrared radiation and to emit a cone of divergent infrared laser radiation from the infrared laser emitting system; and
a driver configured to control at least one of the quantum cascade laser emitter or the optical system to vary a divergence of the beam, the cone emitted from the infrared laser emitting system having a varying divergence such that when the cone is detected by a thermal imager remote from the quantum cascade laser emitter, the cone is distinguishable from a background object in a corresponding image generated by the thermal imager.

US Pat. No. 10,461,113

IMAGE SENSORS, AND FABRICATION AND OPERATION METHODS THEREOF

Samiconductor Manufacturi...

1. An image sensor, comprising:a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a photo-sensitive region and a connection region, the photo-sensitive region comprises a transparent region and a shading region, and the shading region is between the transparent region and the connection region;
a buffer layer formed on the first surface of the substrate in the photo-sensitive region;
a metal grid formed on the buffer layer and including a plurality of staggered metal wires in the transparent region and in the shading region, wherein the metal grid is connected to an operation voltage, and a plurality of trenches are formed in the metal grid with each trench surrounded by the plurality of staggered metal wires; and
a plurality of color filters formed in the plurality of trenches of the metal grid.

US Pat. No. 10,461,112

IMAGE SENSOR USING A LARGE-AREA HIGH-ASPECT-RATIO INTEGRAL IMAGE SENSOR WITH PLURAL LIGHT SENSITIVE SUBAREAS

Alentic Microscience Inc....

1. An apparatus comprisinga large-area high-aspect-ratio integral image sensor comprising two or more light-sensitive subareas in at least one row at a sensor surface,
a chamber configured to confine a sample at a supporting surface, the chamber having a chamber surface spaced from the supporting surface by a predetermined distance associated with characteristics of the sample, and
a processor and an application coupled to a memory, the application being configured to perform a count of elements in the sample.

US Pat. No. 10,461,111

SOLID STATE IMAGING APPARATUS AND METHOD OF PRODUCING THE SAME

Sony Corporation, Tokyo ...

1. A solid state imaging apparatus comprising:a solid state image sensor including
an optical pixel region;
a metal body; and
a peripheral circuit region positioned at a periphery of the optical pixel region, the peripheral circuit region including
a multifunctional chip being electrically connected to the optical pixel region via the metal body;
a sealing resin layer formed with a sealing resin and seals the multifunctional chip in the peripheral circuit region; and
a concave structure configured to inhibit a flow of the sealing resin in a liquid state when the sealing resin layer is formed;
wherein the concave structure configured to inhibit the flow of the sealing resin in the liquid state includes a scoop portion having a scooping surface that surrounds the multifunctional chip, and
wherein the concave structure that is configured to inhibit the flow of the sealing resin in the liquid state is formed only by an optical film layer of the solid state image sensor.

US Pat. No. 10,461,110

IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:a substrate;
a first photoelectric conversion region disposed in the substrate;
a second photoelectric conversion region disposed in the substrate;
a trench disposed between the first photoelectric conversion region and the second photoelectric conversion region;
a first silicon oxide film disposed in the trench, the first silicon oxide film contacting the substrate;
a hafnium oxide film disposed in the trench, the hafnium oxide film disposed at an inner side of the first silicon oxide film;
a tantalum oxide film disposed in the trench, the tantalum oxide film disposed at an inner side of the hafnium oxide film;
a second silicon oxide film disposed in the trench, the second silicon oxide film disposed at an inner side of the tantalum oxide film; and
tungsten material disposed in the trench, the tungsten material disposed at an inner side of the second silicon oxide film,
wherein,
the first silicon oxide film is disposed over the first photoelectric conversion region and contacts the substrate,
the hafnium oxide film is disposed over the first photoelectric conversion region and contacts the first silicon oxide film,
the tantalum oxide film is disposed over the first photoelectric conversion region and contacts the hafnium oxide film,
the second silicon oxide film is disposed over the first photoelectric conversion region and contacts the tantalum oxide film, and
a thickness of the second silicon oxide film over the first photoelectric conversion region is larger than a thickness of the second silicon oxide film between the tantalum oxide film and the tungsten material in the trench.

US Pat. No. 10,461,109

MULTIPLE DEEP TRENCH ISOLATION (MDTI) STRUCTURE FOR CMOS IMAGE SENSOR

Taiwan Semiconductor Manu...

1. A CMOS image sensor, comprising:a substrate having a front-side and a back-side opposite to the front-side;
a plurality of pixel regions disposed on the substrate and respectively comprising a photodiode configured to convert radiation that enters the substrate from the back-side into an electrical signal;
a boundary deep trench isolation (BDTI) structure disposed between adjacent pixel regions, extending from the back-side of the substrate to a first depth within the substrate, and surrounding the photodiode;
a multiple deep trench isolation (MDTI) structure disposed within the plurality of pixel regions, extending from the back-side of the substrate to a second depth within the substrate, and overlying the photodiode; and
a dielectric layer filling in a BDTI trench of the BDTI structure and a MDTI trench of the MDTI structure;
wherein the MDTI structure comprises segments that are spaced apart from one other and are symmetrical along a middle line of the pixel region.

US Pat. No. 10,461,108

IMAGING DEVICE

Hitachi, Ltd., Tokyo (JP...

1. An imaging device comprising:a modulator with a first pantoscopic grating pattern, the modulator configured to modulate light intensity by passage through the first pantoscopic grating pattern;
an image sensor configured to convert light passing through the modulator, to image data, and output the image data; and
an image processor configured to conduct image processing of restoring an image with the use of the image data output from the image sensor,
wherein the first pantoscopic grating pattern is configured to comprise multiple basic patterns, and
each of the basic patterns has the shape of a concentric circle, and
wherein the modulator comprises a first polarization plate and a second polarization plate,
the first polarization plate is disposed closer to a surface configured to serve as an input face of the modulator,
the second polarization plate is disposed closer to a rear surface configured to serve as an output face of the modulator, and
the first polarization plate and the second polarization plate have polarizing axes determined on the basis of an arrangement of the basic patterns.

US Pat. No. 10,461,107

IMAGE PICKUP ELEMENT, IMAGE PICKUP DEVICE, MANUFACTURING DEVICE AND METHOD

Sony Corporation, Tokyo ...

1. An image pickup element comprising:a non-planar layer between a microlens and a filter, the filter and the microlens touch the non-planar layer,
wherein a refractive index of the microlens is greater than a refractive index of the non-planar layer, the refractive index of the non-planar layer is greater than a refractive index of the filter.

US Pat. No. 10,461,106

IMAGING ELEMENT AND CAMERA SYSTEM

Sony Corporation, Tokyo ...

1. An imaging element comprising:a plurality of photoelectric conversion sections that are arrayed on a substrate to receive light incident through a dual-pass filter having transmission bands for visible light and a predetermined range of near-infrared light,
wherein the photoelectric conversion sections include a visible light photoelectric conversion section and a near-infrared light photoelectric conversion section, and the visible light photoelectric conversion section includes a red light photoelectric conversion section, a green light photoelectric conversion section, and a blue light photoelectric conversion section,
wherein a near-infrared absorption filter is selectively disposed on a light incident surface of the photoelectric conversion sections in correspondence with the visible light photoelectric conversion section, and
wherein at least a part of the near-infrared absorption filter is embedded into an opening in a light-shielding layer separating neighboring photoelectric conversion sections.

US Pat. No. 10,461,105

PHOTODIODE ARRAY

ams AG, Unterpremstaette...

1. A photodiode array, comprising:A first photodiode comprising a first set of spatially separate and electrically interconnected photodiode segments,
A second photodiode comprising a second set of spatially separate and electrically interconnected photodiode segments,
A first group of photodiode segments comprising photodiode segments from the first and/or second set of photodiode segments, wherein the photodiode segments from the first group of photodiode segments are radially arranged around a common center of symmetry in a common first distance with respect to the common center of symmetry, and
A second group of photodiode segments comprising photodiode segments from the first and/or second set of photodiode segments, wherein photodiode segments from the second group of photodiode segments are radially arranged around the common center of symmetry in a second common distance with respect to the common center of symmetry, wherein the first distance is different from the second distance, and wherein
Each photodiode has an area matched counterpart photodiode forming a matched pair of photodiodes,
The matched counterpart photodiodes comprise a matched set of spatially separate and electrically interconnected photodiode segments, and
Each group of photodiode segments comprises the corresponding matched set of photodiode segments.

US Pat. No. 10,461,103

POWER STORAGE ELEMENT, MANUFACTURING METHOD THEREOF, AND POWER STORAGE DEVICE

Semiconductor Energy Labo...

1. A power storage element comprising:a pair of electrodes;
a solid electrolyte layer in contact with the pair of electrodes; and
a lithium layer spaced apart from the pair of electrodes with the solid electrolyte layer provided therebetween,
wherein the solid electrolyte layer is between the pair of electrodes.

US Pat. No. 10,461,102

DISPLAY DEVICE, TRANSFLECTIVE ARRAY SUBSTRATE, AND MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A manufacturing method of a transflective array substrate, wherein the transflective array substrate comprises a plurality of pixel cells, each of the pixel cells comprises a reflective area, and the manufacturing method comprises:arranging a plurality of scanning lines, a plurality of data lines intersecting with the scanning lines, and a plurality of TFTs, wherein the TFT is surrounded by the scanning lines and the data lines, the TFT is configured within the pixel cell, and the TFT electrically connects to the scanning line and the data line respectively;
arranging a photoresist layer above the TFT corresponding to each of the pixel cells;
arranging at least one pixel electrode above the photoresist layer corresponding to each of the pixel cells, wherein the TFT electrically connects to the pixel electrode;
arranging a reflective layer within the reflective area, wherein the reflective layer is configured above the photoresist layer, so as to prevent ambient light beams from being filtered by the photoresist layer when the ambient light beams enter the reflective area;
wherein step of arranging a plurality of the scanning lines, a plurality of the data lines intersecting with the scanning lines, and a plurality of the TFTs further comprises:
depositing a gate metal layer on a glass substrate;
forming the scanning lines and a gate of the TFT by conducting an exposure process, a development process, a wet-etching process, and a peeling-off process on the gate metal layer, wherein the gate electrically connects to the scanning line;
depositing a source-drain metal layer above the scanning line and the gate;
forming the data lines, and a source and a drain of the TFT by conducting the exposure process, the development process, the wet-etching process, a dry-etching process, and the peeling-off process on the source-drain metal layer, wherein the source electrically connects to the data line, and the drain electrically connects to the pixel electrode;
wherein, before the step of depositing the source-drain metal layer above the scanning line and the gate, the manufacturing method further comprises:
depositing a gate insulation layer above the scanning line and the gate to form a first insulation layer;
depositing an N-doped amorphous silicon layer on the first insulation layer;
forming a semiconductor layer by conducting the exposure process, the development process, the dry-etching process, and the peeling-off process on the N-doped amorphous silicon layer;
before the step of arranging the photoresist layer above the TFT corresponding to each of the pixel cells, the manufacturing method further comprises:
depositing a photoresist insulation layer on the data line, and the source and the drain of the TFT to form a second insulation layer;
before the step of arranging at least one pixel electrode above the photoresist layer corresponding to each of the pixel cells, the manufacturing method further comprises:
depositing a flat layer on the photoresist layer to form a third insulation layer;
forming a through hole by conducting a through-hole etching process on the third insulation layer, wherein the through hole penetrates the third insulation layer, the photoresist layer, and a second insulation layer, the drain is exposed by the through hole;
the step of arranging the pixel electrode above the photoresist layer corresponding to each of the pixel cells further comprises:
depositing a first conductive material layer on the third insulation layer;
forming the pixel electrode by conducting the exposure process, the development process, the wet-etching process, and the peeling-off process on the first conductive material layer, wherein the pixel electrode electrically connects to the drain via the through hole;
before the step of arranging the reflective layer, the manufacturing method further comprises:
depositing an electrode insulation layer on the pixel electrode to form a fourth insulation layer.

US Pat. No. 10,461,101

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor layer over a first insulating film;
the oxide semiconductor layer comprising a first region and a second region;
a transistor over an insulating surface, the transistor including:
a source electrode layer and a drain electrode layer;
a second insulating film over the first region; and
a gate electrode layer over the first region with the second insulating film therebetween;
a transparent conductive film overlapping with the second region;
a dielectric between the second region and the transparent conductive film; and
a capacitor comprising
the second region;
the transparent conductive film; and
the dielectric serving as a dielectric of the capacitor,
wherein the dielectric is in direct contact with a side edge surface of the second insulating film, a first electrode of the capacitor, and a second electrode of the capacitor.

US Pat. No. 10,461,100

DISPLAY DEVICE HAVING A DIFFERENT TYPE OF OXIDE SEMICONDUCTOR TRANSISTOR

Japan Display Inc., Toky...

1. A display device comprising:a display circuit provided with a plurality of pixel circuits in a matrix shape;
a drive circuit provided in a periphery of the display circuit, the drive circuit driving each of the plurality of pixel circuits;
a first transistor having a first oxide semiconductor layer as a channel and a first gate electrode, the first transistor being included in the drive circuit;
a second transistor having a second oxide semiconductor layer as a channel and a second gate electrode, the second transistor being included in the pixel circuit, and a composition of the first oxide semiconductor layer is different from a composition of the second oxide semiconductor layer,
wherein
the first oxide semiconductor layer and the second oxide semiconductor layer include Sn, and
a content ratio of the Sn included in the first oxide semiconductor layer is more than a content ratio of the Sn included in the second oxide semiconductor layer.

US Pat. No. 10,461,099

METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM

Semiconductor Energy Labo...

1. A method for manufacturing a metal oxide film comprising:forming the metal oxide film by a sputtering method using a sputtering target comprising a polycrystalline oxide in an atmosphere where oxygen partial pressure is greater than or equal to 33%,
wherein the sputtering target comprises indium, gallium and zinc,
wherein the metal oxide film comprises a plurality of crystal parts when the metal oxide film is formed,
wherein a size of one of the plurality of crystal parts is less than or equal to 10 nm, and
wherein a crystal peak is not observable in an XRD spectrum with respect to the metal oxide film.

US Pat. No. 10,461,098

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. An electronic device comprising:a band portion configured to be worn on a wrist;
a display portion configured to display a button on a screen; and
a microphone,
wherein the display portion comprises a pixel portion comprising a transistor,
wherein the transistor comprises an oxide semiconductor layer comprising In, Ga, Zn and O,
wherein the electronic device is configured such that data is input by touching the button, and
wherein the electronic device is configured such that data is input by inputting voice into the microphone.

US Pat. No. 10,461,097

ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Shenzhen China Star Optoe...

1. An array substrate, comprising: a substrate; a first insulating layer disposed on the substrate, wherein the first insulating layer defines a channel; a source electrode pattern disposed in the channel of the first insulating layer; an annular gate electrode pattern disposed on the first insulating layer and surrounding the periphery of the source electrode pattern; a second insulating layer covering the annular gate electrode pattern, wherein the second insulating layer defines an opening corresponding to the channel of the first insulating layer, such that a face of the source electrode pattern away from the substrate is at least partially accessible through the channel of the first insulating layer and the opening of the second insulating layer; a semiconductor pattern disposed in the annular area of the annular gate electrode pattern, and is electrically connected to the accessible face of the source electrode pattern, the semiconductor pattern is further electrically insulated from the annular gate electrode pattern by the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to a face of the semiconductor pattern away from the substrate;a data line electrically connected to the source electrode pattern, wherein the first insulating layer comprising a buffer layer and a passivation layer, the data line is formed within the buffer layer and covered by the passivation layer; and wherein the source electrode pattern comprises a first source electrode pattern layer and a second source electrode pattern layer disposed stacked together, the first source electrode pattern layer and the data line are formed by the same material, the second source electrode pattern layer and the annular gate electrode pattern are formed by the same material.

US Pat. No. 10,461,096

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate having a central area and a peripheral area disposed adjacent to the central area, the central area comprising a display area;
at least one semiconductive layer or one conductive layer in the display area;
a first insulating layer disposed in the peripheral area of the substrate, the first insulating layer covering at least one of the at least one semiconductive layer or the one conductive layer;
at least one pattern corresponding to a region of the first insulating layer;
a cover layer on the first insulating layer and covering the at least one pattern in the peripheral area, the cover layer comprising an insulating material; and
an encapsulating layer on the display area, at least one layer of the encapsulating layer is spaced apart from the cover layer.

US Pat. No. 10,461,095

FERROELECTRIC NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. A non-volatile storage element comprising:a control gate;
a blocking layer comprising a ferroelectric material;
a charge storage region; and
a tunneling layer,
wherein the blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer, and
wherein the blocking layer comprises doped hafnium oxide including crystal grains that may be switched between a first polarization state to a second polarization state.

US Pat. No. 10,461,094

3D MEMORY DEVICE

Trinandable S.r.l., Mila...

8. A three-dimensional, 3D, memory device comprising:a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an alignment of strings of memory cells extending along a first direction, said rows following one another along a second direction, wherein each string of memory cells comprises a stack of memory cells, said strings of memory cells of the stack extending along a third direction from a first end to a second end;
a source region at the second end of the strings of memory cells;
wherein rows of strings of memory cells consecutive along said second direction are spaced apart from each other of a pitch and arranged in “zigzag” along said second direction;
wherein between pairs of said rows of strings of memory cells consecutive along said second direction a slit is formed which extend in said third direction from said first end to said source region; and
wherein said slit has size, along said second direction, less than, equal to or greater than said pitch, sufficient for the formation, in said slit, of an electrical contact to the source region.

US Pat. No. 10,461,093

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a plurality of conducting layers and a plurality of insulating layers that are alternately disposed above a semiconductor substrate;
a plurality of pillars that extend through the alternately-disposed layers of the conductive layers and the insulating layers in a first direction which crosses a surface of the semiconductor substrate, the plurality of pillars being arranged in a second direction along the surface of the semiconductor substrate; and
a plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, extends in the second direction, and is disposed apart from the plurality of pillars in a third direction along the surface of the semiconductor substrate, the third direction being different from the second direction,
wherein the plate has convex portions and non-convex portions alternately arranged on a side of the plate in the second direction, the convex portions and the non-convex portions both extend through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, and the convex portions and at least part of the plurality of pillars are arranged in a staggered manner.

US Pat. No. 10,461,092

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a stacked body including:
a first stacked unit and a second stacked unit stacked above the first stacked unit, each of the first and second stacked units including a plurality of electrode layers alternately stacked with a plurality of first insulating layers therebetween, and
an intermediate insulating layer provided above the first stacked unit and below the second stacked unit; and
a columnar member piercing the stacked body in a stacking direction of the stacked body, the columnar member including an intermediate columnar part inside the intermediate insulating layer; wherein
a diameter of the intermediate columnar part in a first direction perpendicular to the stacking direction is broadened downwardly to a predetermined depth in a diameter broadening portion of the columnar member, a sidewall of the diameter broadening portion of the columnar member having a curved shape in a cross section along the stacking direction, the diameter of the intermediate columnar part being broadened downwardly on both sides of the diameter broadening portion in the first direction, and wherein
the predetermined depth does not reach any electrode layers functioning as word lines in the first stacked unit, memory cells being provided at intersections of the word lines and the columnar member.

US Pat. No. 10,461,091

NAND FLASH MEMORY DEVICE HAVING FACING BAR AND METHOD OF FABRICATING THE SAME

DOSILICON CO., LTD., Sha...

1. A NAND flash memory device comprising:a facing bar configured to protrude to have a predetermined width and height from a planar surface of a semiconductor substrate and configured to extend in a first direction which is a horizontal direction with respect to a horizontal surface of the semiconductor substrate, the facing bar being divided into a plurality of device forming sections by a plurality of active regions, wherein the plurality of active regions extend parallel with one another in a second direction of the horizontal direction and are electrically isolated from one another, and the second direction intersects the first direction; and
a first side structure and a second side structure provided on two side surfaces of the facing bar, each of the first side structure and the second side structure including a base electrode guard including a conductive material, the base electrode guard extending in the first direction to be provided on the plurality of active regions, wherein the first side structure and the second side structure are divided into a plurality of first active structures and a plurality of second active structures to correspond to the plurality of device forming sections,
wherein each of the plurality of first active structures and the plurality of second active structures comprises a base transistor in which at least a portion of a base transmission channel is provided on a side surface of the facing bar according to a voltage applied to a control gate, and the control gate is provided as a portion of the base electrode guard,
wherein the base transistor of the first active structures and the base transistor of the second active structures, which correspond to one of the device forming sections, are provided as a portion of one cell string.

US Pat. No. 10,461,090

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a plurality of first conductive films stacked in a first direction above the substrate and extend in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction;
a memory columnar body extending in the first direction and having a side surface covered by the plurality of first conductive films; and
a first structure extending in the second direction and dividing the plurality of first conductive films in the third direction, a length of the first structure in the second direction being greater than a length of the first structure in the third direction, and the length of the first structure in the second direction being equal to or greater than a length of the plurality of first conductive films in the second direction,
each of the memory columnar body and the first structure comprising:
a memory insulating film provided on a side surface of at least one of the plurality of first conductive films; and
a first semiconductor layer provided on a side surface of the memory insulating film.

US Pat. No. 10,461,089

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:a semiconductor substrate including a peripheral region and a memory region separated by an isolation structure, wherein the isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material;
a memory cell on the memory region;
a dummy control gate structure on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall that faces the peripheral region and that comprises multiple different materials;
a sidewall spacer on the isolation structure, along the dummy sidewall of the dummy control gate structure, wherein the sidewall spacer has a boundary sidewall that faces the peripheral region and that is smooth; and
a logic device on the peripheral region.

US Pat. No. 10,461,088

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a gate stack and a conductive layer over a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate, the gate stack is formed over the first region, and the conductive layer is formed over the second region and the isolation structure;
forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer;
forming a mask layer over the negative photoresist layer and the conductive layer, wherein the mask layer has trenches over the second portion of the conductive layer, wherein the mask layer over the conductive layer is thicker than the mask layer over the negative photoresist layer;
removing the second portion through the trenches;
removing the mask layer; and
removing the negative photoresist layer.

US Pat. No. 10,461,087

STRUCTURE AND METHOD FOR FINFET SRAM

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor fabrication, comprising:forming mandrel patterns over a substrate using a first mask that defines the mandrel patterns, wherein the first mask includes at least four first patterns that are spaced from each other in a first direction, wherein each of the first patterns extends lengthwise in a second direction orthogonal to the first direction;
forming spacers on sidewalls of the mandrel patterns;
removing the mandrel patterns;
etching the substrate using the spacers as an etch mask, thereby forming fin lines in the substrate; and
performing a fin cut process using a second mask to remove selective ones of the fin lines, wherein the second mask includes at least four second patterns, each being an elongated shape extending lengthwise in the second direction, wherein the second patterns are spaced from each other in the first direction, and each of the second patterns covers a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction.

US Pat. No. 10,461,086

MEMORY CELL STRUCTURE

Taiwan Semiconductor Manu...

1. A memory device comprising:an SRAM memory cell disposed on a substrate and including:
a first transistor;
a first Vss node component including a first conductive island on a first metallization layer;
a first via physically interfacing a bottom surface of the first metallization layer and coupling the first Vss node component and the first transistor, wherein the first via has a length and a width, the length at least 1.5 times that of the width, wherein the length and width are measured on a plane parallel a top surface of the substrate;
an extended contact physically interfacing a bottom surface of the first via and extending to a source region of the first transistor;
a second Vss node component including a second conductive island on a second metallization layer, wherein a second via extends from the first conductive island to the second conductive island;
a word line on a second metallization layer above the first metallization layer; and
a Vss line coupled to the second Vss node component by a third via extending from the second conductive island to the Vss line.

US Pat. No. 10,461,085

SEMICONDUCTOR DEVICE INCLUDING INSULATING ELEMENT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a substrate;
a first transistor on the substrate, wherein the first transistor comprises a first source/drain electrode in the substrate;
a second transistor on the substrate, wherein the second transistor comprises a second source/drain electrode; and
an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate, wherein the insulating layer corresponds to a continuous poly on oxide definition (CPODE) pattern.

US Pat. No. 10,461,084

COMPACT SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED NUMBER OF CONTACTS, METHODS OF OPERATING AND METHODS OF MAKING

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises:
a floating body region for storing charge indicating a state of said semiconductor memory cell; and
a back-bias region;
wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;
wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;
wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and
a control circuitry configured to apply said voltage to said back-bias region.

US Pat. No. 10,461,083

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A semiconductor memory cell comprising:a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region;
a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions, wherein:
said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region; and
an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region.

US Pat. No. 10,461,082

WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS

Intel Corporation, Santa...

1. Integrated circuit (IC) structures, comprising:a well recess in a first region of a substrate, the well recess containing an amorphous well-isolation material over a bottom of the well recess, and a crystalline well material over the well-isolation material, wherein the well material is coupled to a seeding surface of the substrate at the bottom of the well recess by a crystalline pillar material that extends through the well-isolation material;
an amorphous fin-isolation material over a first surface of the well material, and over a second surface in a second region of the substrate adjacent to the first region wherein the first surface is substantially planar with the second surface; and
a first fin comprising a first crystalline material, wherein the first fin extends from the first surface of the well material and protrudes through the fin-isolation material to a first height over the fin-isolation material; and
a second fin comprising a second crystalline material, wherein the second fin extends from the second surface of the second region of the substrate and protrudes through the fin-isolation material to a second height over the fin-isolation material, the second height being substantially equal to the first height.

US Pat. No. 10,461,081

SUPER-SELF-ALIGNED CONTACTS AND METHOD FOR MAKING THE SAME

Tel Innovations, Inc., L...

1. A semiconductor device, comprising:a first linear gate structure;
a second linear gate structure located next to the first linear gate structure, the second linear gate structure separated from the first linear gate structure by a gate pitch, the second linear gate structure forming a first PMOS transistor and a first NMOS transistor;
a third linear gate structure located next to the second linear gate structure, the third linear gate structure separated from the second linear gate structure by the gate pitch, the third linear gate structure forming a second PMOS transistor and a second NMOS transistor;
a fourth linear gate structure located next to the third linear gate structure, the fourth linear gate structure separated from the third linear gate structure by the gate pitch, the fourth linear gate structure forming a third PMOS transistor and a third NMOS transistor;
a fifth linear gate structures located next to the fourth linear gate structure, the fifth linear gate structure separated from the fourth linear gate structure by the gate pitch;
a first gate contact physically connected to the second linear gate structure at a location between the first PMOS transistor and the first NMOS transistor;
a second gate contact physically connected to the third linear gate structure at a location between the second PMOS transistor and the second NMOS transistor; and
a third gate contact physically connected to the fourth linear gate structure at a location between the third PMOS transistor and the third NMOS transistor.

US Pat. No. 10,461,080

METHOD FOR MANUFACTURING A FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:etching a semiconductor substrate of a wafer to form at least one fin;
forming an insulation structure around the fin;
recessing the fin;
epitaxially growing an epitaxial channel structure over the recessed fin;
removing a portion of the epitaxial channel structure over a top surface of the insulation structure;
performing a non-contact-type cleaning operation to clean a top surface of the wafer after removing said portion of the epitaxial channel structure;
cleaning the top surface of the wafer using hydrogen fluoride after removing said portion of the epitaxial channel structure; and
recessing the insulation structure such that the epitaxial channel structure protrudes from the recessed insulation structure.

US Pat. No. 10,461,079

METHOD AND DEVICE OF PREVENTING MERGING OF RESIST-PROTECTION-OXIDE (RPO) BETWEEN ADJACENT STRUCTURES

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating semiconductor device, comprising:epitaxially growing a first source/drain on a first fin structure and a second source/drain on a second fin structure;
forming a first layer over the first source/drain but not over the second source/drain;
forming a dielectric layer over the first layer and over the second source/drain; and
removing a first segment of the dielectric layer but not a second segment of the dielectric layer, wherein the first segment is disposed over the first layer, and wherein the second segment is disposed over the second source/drain.

US Pat. No. 10,461,078

CREATING DEVICES WITH MULTIPLE THRESHOLD VOLTAGE BY CUT-METAL-GATE PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a workpiece that includes a substrate, a semiconductor fin over the substrate, and first and second high-k metal gate structures engaging the semiconductor fin to define first and second transistors respectively, wherein the first and second high-k metal gate structures have a same number of material layers, are isolated from each other, and are oriented lengthwise along a first direction;
etching the first and second high-k metal gate structures, resulting in a first trench and a second trench in the workpiece, wherein the first trench has a first dimension along the first direction, and is away from the semiconductor fin by a first distance along the first direction, wherein the second trench has a second dimension along the first direction, and is away from the semiconductor fin by a second distance along the first direction; and
filling the first and second trenches with one or more dielectric materials, wherein the first dimension is configured to be different from the second dimension or the first distance is configured to be different from the second distance such that the first and second transistors are provided with different threshold voltages.

US Pat. No. 10,461,077

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, comprising:a first conductive-type SiC base layer having a first surface and a second surface, the second surface of the first conductive-type SiC base layer being on a first conductive-type SiC substrate, the first conductive-type SiC substrate having a first surface facing the second surface of the SiC base layer and a second surface opposite the first surface of the SiC substrate and defining a drain region of the SiC-MOSFET;
a trench etched in the second surface of the SiC substrate, the trench dividing the SiC substrate into a plurality of first conductive-type regions;
a second conductive-type region in a bottom surface of the trench so as to form a collector region in the bottom surface;
a second conductive-type region in the first surface of the SiC base layer so as to form a channel region in a surficial portion of the SiC base layer;
a first conductive-type region in the first surface of the SiC base layer so as to form an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET;
a second conductive-type region in the first surface of the SiC base layer so as to form a channel contact region in a surficial portion of the SiC base layer, the channel contact region penetrating the emitter region and contacting with the channel region, wherein
a first unit including the channel region, the emitter region and the channel contact region faces a second unit including a plurality of collector region and the plurality of the first conductive-type regions in the thickness direction of the SiC base layer, and
a deepest portion of the trench is at a position nearer the first surface of the SiC base layer with respect to an interface between the SiC substrate and the SiC base layer.

US Pat. No. 10,461,076

3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO ACCELERATE ARTIFICIAL NEURAL NETWORK (ANN) COMPUTATION

MICRON TECHNOLOGY, INC., ...

1. A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN), comprising:a non-volatile memory die comprising an array of non-volatile memory partitions, wherein each partition of the array of non-volatile memory partitions is configured to store first parameters of a set of neurons;
a volatile memory die comprising an array of volatile memory partitions, wherein each partition of the array of volatile memory partitions is configured to store second parameters of the set of neurons; and
a processing logic die comprising an array of processing logic partitions, wherein each partition of the array of processing logic partitions is configured to:
receive input data; and
process the input data according to the set of neurons to generate output data.

US Pat. No. 10,461,075

EMBEDDED TUNGSTEN RESISTOR

Texas Instruments Incorpo...

1. An integrated circuit, comprising:a substrate;
a well formed in the substrate;
a silicide layer formed in the well;
a tungsten resistor formed over the silicide layer;
a first polysilicon lead formed over the silicide layer; and
a second polysilicon lead formed over the silicide layer and adjacent to the first polysilicon lead to define a resistor trench above the substrate.

US Pat. No. 10,461,074

FIELD-EFFECT SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION CONTACT

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor body having a main surface, the semiconductor body comprising a drift region of monocrystalline SiC, the drift region being of a first conductivity type; and
a metallization arranged at the main surface,
wherein in a cross-section which is substantially orthogonal to the main surface, the semiconductor body further comprises:
a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, the contact region being of a second conductivity type; and
an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC, the anode region being in ohmic contact with the metallization and forming a heterojunction with the drift region.

US Pat. No. 10,461,073

POWER MODULE WITH MOSFET BODY DIODE ON WHICH ENERGIZATION TEST CAN BE CONDUCTED EFFICIENTLY

Mitsubishi Electric Corpo...

1. A power module comprising:a casing;
a first terminal, a second terminal, and a third terminal, each being fixed to the casing and connectable to an outside;
a first MOS transistor contained in the casing, connected between the first terminal and the second terminal, and having a forward direction from the second terminal to the first terminal;
a second MOS transistor contained in the casing, connected between the second terminal and the third terminal, and having a forward direction from the third terminal to the second terminal;
a first Schottky barrier diode contained in the casing, being in parallel with the first MOS transistor, having an anode connected to the first terminal, and having a cathode connected to the second terminal; and
a second Schottky barrier diode contained in the casing, being in parallel with the second MOS transistor, having an anode connected to the second terminal, and having a cathode connected to the third terminal,
each of the first Schottky barrier diode and the second Schottky barrier diode including a resistive layer formed of polysilicon in direct contact with a surface of a cathode electrode layer on a side of the cathode electrode layer opposite to an n-type drift layer having a p-type guard ring region which is in direct contact with portions of a dielectric film and a Schottky anode electrode,
the resistive layer of the first Schottky barrier diode being configured such that:
a current value at a first crossing point is within a range of ±10% of a rated current of the power module, the first crossing point being a crossing point of:
a current-voltage characteristic graph of the first MOS transistor when forward current is caused to flow in a body diode of the first MOS transistor crossing a current-voltage characteristic graph of the first Schottky barrier diode when forward current is caused to flow in the first Schottky barrier diode,
the resistive layer of the second Schottky barrier diode being configured such that:
a current value at a second crossing point is within a range of ±10% of the rated current of the power module, the second crossing point being a crossing point of:
a current-voltage characteristic graph of the second MOS transistor when forward current is caused to flow in a body diode of the second MOS transistor crossing a current-voltage characteristic graph of the second Schottky barrier diode when forward current is caused to flow in the second Schottky barrier diode.

US Pat. No. 10,461,072

ISOLATION STRUCTURE FOR IC WITH EPI REGIONS SHARING THE SAME TANK

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device comprising:a substrate having a p-type epitaxial (p-epi) layer thereon;
an n+ buried layer disposed within the p-epi layer and defining a buried portion of the p-epi layer below the n+ buried layer;
an outer isolation ring including a first dielectric sidewall and a first deep n-type (DEEPN) diffusion region, wherein the first DEEPN diffusion region is arranged in a ring in the p-epi layer and contacts the p-epi layer and the first dielectric sidewall, and wherein the first DEEPN diffusion region extends downward from the p-epi layer to the n+ buried layer and encloses a portion of the p-epi layer to define an enclosed p-epi region; and
a plurality of inner isolation structures within the enclosed p-epi region, each inner isolation structure including one of a corresponding plurality of second dielectric sidewalls and one of a corresponding plurality of second DEEPN diffusion regions each second DEEPN diffusion region contacting the corresponding second dielectric sidewall, separating the corresponding second dielectric sidewall from an adjacent second dielectric sidewall, and extending downward from the p-epi layer to the n+ buried layer;
wherein the plurality of inner isolation structures are spaced apart such that adjacent ones of the second DEEPN diffusion regions overlap to form a continuous wall of n-type material extending from a first side to a second side of the outer isolation ring thereby dividing the enclosed p-epi region into a first p-epi region and a second p-epi region, wherein the n+ buried layer in the first p-epi region connects to the n+ buried layer in the second p-epi region.

US Pat. No. 10,461,071

ELECTROSTATIC DISCHARGE PROTECTION OF AN INTEGRATED CIRCUIT CLOCK

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:a direct-current power supply;
a voltage-controlled oscillation (VCO) circuit having an oscillation frequency and including an amplification circuit and capacitance circuitry;
an electrostatic protection circuit arranged to connect power to the VCO circuit while reducing variation in the oscillation frequency of the VCO circuit resulting from electrostatic energy; and
a voltage regulator connected between the direct-current power supply and a power supply connection at which the direct-current power is connected to the VCO, the voltage regulator configured to mitigate an imbalance of electric charges from adversely altering a tuning capacitance of the VCO established by the capacitance circuitry, wherein the apparatus is an integrated chip and the VCO circuit includes an electronic oscillator tuned by the capacitance circuitry to oscillate at the oscillation frequency, wherein the electronic oscillator is electrically isolated from the electrostatic protection circuit.

US Pat. No. 10,461,070

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus, comprising:a substrate comprising a display area and a peripheral area surrounding the display area, the display area comprising:
a main area located at a center of the substrate;
a first protruding area extending from the main area and protruding toward the peripheral area in a first direction;
a second protruding area extending from the main area and protruding toward the peripheral area in the first direction, the second protruding area being spaced apart from the first protruding area in a second direction that intersects the first direction; and
a groove portion disposed between the first protruding area and the second protruding area;
a display unit comprising a first light emitter disposed on the first protruding area and a second light emitter disposed on the second protruding area;
a first load matching part disposed on a portion of the peripheral area adjacent to the first light emitter and electrically connected to the first light emitter; and
a second load matching part disposed on a portion of the peripheral area adjacent to the second light emitter and electrically connected to the second light emitter,
wherein the first load matching part and the second load matching part are electrically connected to each other by a conductive film disposed on the peripheral area.

US Pat. No. 10,461,069

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:a bonding structure formed between a first substrate and a second substrate, wherein the bonding structure comprises a first polymer bonded to a second polymer, and a first conductive material bonded to a second conductive material;
a first TSV formed in the first substrate;
an interconnect structure formed over the first TSV, wherein the first TSV is between the interconnect structure and the bonding structure; and
a first conductive layer between the first conductive material and the first TSV, wherein the first conductive layer has a first surface and a second surface, the first surface is in direct contact with the first TSV, and the second surface is in direct contact with the first polymer.

US Pat. No. 10,461,068

HIGHLY INTEGRATED RF POWER AND POWER CONVERSION BASED ON GA2O3 TECHNOLOGY

The United States of Amer...

1. An integrated circuit, comprising:a first substrate with a first thermal conductivity;
an active layer deposited on the first substrate;
at least one native device fabricated on the active layer;
a window formed in the active layer and exposing a portion of the first substrate; and
a non-native device fabricated in a second substrate with a second thermal conductivity lower than the first thermal conductivity,
wherein the non-native device is mounted in the window on the first substrate using a flip chip mount and electrically connected to the at least one native device,
wherein the non-native device added a circuit or electrical functionality to the first substrate, and
wherein the non-native device is thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.

US Pat. No. 10,461,067

THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:integrated circuit (IC) chips, comprising a logic chip and at least one memory stack adjacent the logic chip, attached to an upper surface of a substrate;
a lid thermally connected to an upper surface of the IC chips by a first thermal interface material (TIM1);
a slit formed through the lid by punch and die at a boundary between the logic chip and each memory stack;
a heat sink thermally connected to the lid by a second thermal interface material (TIM2);
at least one co-axial hole formed in the lid and the heat sink; and
a vertical heat pipe extending through each co-axial hole for direct thermal contact with an IC chip and the heat sink.

US Pat. No. 10,461,066

STRUCTURE AND METHOD FOR HYBRID OPTICAL PACKAGE WITH GLASS TOP COVER

Maxim Integrated Products...

1. An optical package, comprising:a package substrate comprising at least one of: at least one die attach pad, at least one vent hole configured to prevent pop-corning of the panel level substrate or at least one pedestal;
an application specific integrated circuit (ASIC) die disposed on the package substrate, the application specific integrated circuit die including a detector;
at least one non-optical sensor die disposed on the package substrate;
a pre-molded polymer panel unit cell disposed on and coupled to the package substrate using a first adhesive film element, the pre-molded polymer panel unit cell including multiple sidewalls that form an outer perimeter and a middle sidewall that defines two cavities, the ASIC die disposed in a first cavity and the at least one non-optical sensor die disposed in a second cavity, the middle sidewall configured to restrict cross talk between the application specific integrated circuit die and the at least one non-optical sensor die, the middle sidewall further comprising a shelf-structure; and
an individual glass cover disposed on the pre-molded polymer panel unit cell, where the glass cover is transparent to an electro-magnetic spectral region detected by the ASIC die and the at least one non-optical sensor die, the individual glass cover adhesively bonded directly to the pre-molded polymer panel unit cell using a second adhesive film element, the individual glass cover adhesively bonded directly to the shelf-structure using a third adhesive film element.

US Pat. No. 10,461,065

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, the method comprising:mounting a plurality of light emitting elements on a collective substrate;
arranging at least one light transmissive member for each light emitting device on an upper surface of each of the plurality of light emitting elements;
arranging a first protruding member that surrounds the plurality of light emitting elements on an upper surface of the collective substrate;
arranging a second protruding member between the plurality of light emitting elements on the upper surface of the collective substrate;
after the arranging the first protruding member and the second protruding member, forming a cover member that covers an upper end of the second protruding member, the light emitting elements, and a lateral surface of the light transmissive member in a region surrounded by the first protruding member; and
singulating the light emitting devices by dividing the cover member, the second protruding member, and the collective substrate at a portion including the second protruding member;
wherein an upper end of the second protruding member is located in the region surrounded by the first protruding member so as to be lower than an upper end of the first protruding member but higher than the upper surface of each of the light emitting elements, and
wherein the second protruding member is harder than the cover member.

US Pat. No. 10,461,064

RED FLIP CHIP LIGHT EMITTING DIODE, PACKAGE, AND METHOD OF MAKING THE SAME

Bridgelux, Inc., Livermo...

1. A method for making a flip chip light emitting diode comprising the steps of:growing a layer of active material onto a substrate having a crystalline lattice matching the crystalline lattice of the layer of active material;
attaching a carrier to a surface of the active material layer that is opposite the substrate, wherein the carrier is formed from a material transparent to a wavelength of light emitted from the active material layer, wherein the carrier is continuous construction extending along the surface of the active material layer;
removing the substrate from the active material layer thereby exposing a surface of the active material layer opposite the carrier; and
forming a pair of electrodes on the light emitting diode along a common surface of the active material layer earlier covered by the substrate and opposite the carrier for connecting with electrical contacts of an adjacent connection member positioned opposite the common surface, wherein a surface of the carrier opposite the active material layer is free of electrodes.

US Pat. No. 10,461,063

LIGHT-EMITTING DEVICE

Toshiba Hokuto Electronic...

1. A light-emitting device having flexibility comprising:a light-emitting part;
an external wiring part; and
a joint part,
the light-emitting part comprising a first portion of a first insulating substrate, at least a first portion of a second insulating substrate, a plurality of light-emitting elements, a first portion of an internal wiring pattern, and a resin layer, the first portion of the first insulating substrate and the first portion of the second insulating substrate are each light transmitting and flexible, the plurality of light-emitting elements are between the first portion of the first insulating substrate and the first portion of the second insulating substrate, the first portion of the internal wiring pattern is formed on at least one inside surface of at least one of the first portion of the first insulating substrate and the first portion of the second insulating substrate, the resin layer is light transmissive and insulating, the resin layer is between the first portion of the first insulating substrate and the first portion of the second insulating substrate,
the external wiring part comprising a first portion of a third insulating substrate and a first portion of an external wiring, the first portion of the third substrate is flexible,
the joint part comprising:
a second portion of the internal wiring pattern that extends beyond the light-emitting part, said second portion of the internal wiring pattern comprising first and second internal wiring ends, each of the internal wiring ends having a respective internal wiring end width, the first internal wiring end is an anode, the second internal wiring end is a cathode;
a second portion of the external wiring that extends beyond the external wiring part;
a second portion of the third insulating substrate that extends beyond the external wiring part; and
an anisotropic conductive adhesive,
at least part of the second portion of the external wiring is divided into a plurality of divided wirings, each divided wiring of the plurality of divided wirings having a width that is less than each of the internal wiring end widths,
the first internal wiring end is adjacent to the second internal wiring end, and the anisotropic conductive adhesive comprises a single region that is in contact with each of the plurality of divided wirings and the first and second internal wiring ends, and the single region of the anisotropic conductive adhesive electrically connects the first internal wiring end to at least a first divided wiring of the plurality of divided wirings, and connects the second internal wiring end to at least a second divided wiring of the plurality of divided wirings.

US Pat. No. 10,461,062

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A semiconductor device comprising:a first board having a first electrically conducting layer and a first electronic element that is provided on the first electrically conducting layer and that is a power device;
a first intermediate layer being provided on the first board, and having a first connector and a first resin board section, in which the first connector is fixed; and
a second intermediate layer being provided on the first intermediate layer, and having a plurality of second connectors and a second resin board section, in which the second connectors are fixed;
wherein the first connector is exposed from the first resin board section on the first board side, and connected with the first electrically conducting layer or the first electronic element,
wherein the first connector is exposed on an opposite side to the first board from the resin board section, and a second electronic element, which is a power device, is provided on the first connector,
wherein one of the second connectors is exposed from the second resin board section on the first board side, and connected with the second electronic element,
wherein another second connector protrudes from the second resin board section to the side on which the first intermediate layer is provided, and the first resin board section is provided with a first insertion section, into which the other second connector, which protrudes from the second resin board section, is inserted, and
wherein each of the second connectors penetrates the second resin board section and is exposed on the opposite side to the first board from the second resin board section.

US Pat. No. 10,461,061

APPARATUSES AND METHODS FOR SEMICONDUCTOR DIE HEAT DISSIPATION

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
a thermal interface layer disposed on a surface of the substrate; and
a heat spreader with a plurality of substrate-facing protrusions in contact with the thermal interface layer,
wherein the heat spreader covers an entire surface of a top die of a stack of semiconductor die, and
wherein a thickness of the thermal interface layer under a face of the substrate-facing protrusions facing the substrate is thinner relative to a thickness of the thermal interface layer under areas of the heat spreader that have no substrate-facing protrusions.

US Pat. No. 10,461,060

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH REDISTRIBUTION LAYERS

Taiwan Semiconductor Manu...

1. A chip package, comprising:a semiconductor die;
a protective layer surrounding the semiconductor die;
an interface between the semiconductor die and the protective layer; and
a conductive layer over the protective layer and the semiconductor die, wherein the conductive layer has a first portion and a second portion, the first portion is closer to an inner portion of the semiconductor die than the second portion, the first portion is in direct contact with the second portion, the second portion extends across the interface, and in a top view of the conductive layer, the second portion has a line width greater than that of the first portion.

US Pat. No. 10,461,059

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:a thermally conductive casing;
a package substrate comprising a plurality of first raised bond pads that each have a first vertical height, wherein the package substrate and the thermally conductive casing together define an enclosure;
an interposer having a front side surface and an opposing back side surface, the back side surface attached to the thermally conductive casing within the enclosure and the front side surface comprising a plurality of second raised bond pads that each have a second vertical height;
a stack of semiconductor dies having a stack height disposed between the front side surface of the interposer and the package substrate within the enclosure; and
a plurality of conductive members interposed between the plurality of first raised bond pads and the plurality of second raised bond pads, wherein each conductive member of the plurality of conductive members include a solder bump having a third vertical height, and wherein a sum of the first, second, and third vertical heights is about equal to or greater than the stack height of the stack of semiconductor dies.

US Pat. No. 10,461,058

METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC DEVICE USING DEVICE CHIP

SHASHIN KAGAKU CO., LTD.,...

1. A method of manufacturing electronic devices comprising:a preparation step for preparing a first substrate having a first adhesive layer and a second substrate having a second adhesive layer, the first adhesive layer including a surface where a plurality of device chips are adhered;
a first take-out step for making at least part of the device chips on the first substrate come into contact with and adhere to at least part of a selective adhesive region on a third adhesive layer of a first drum and for separating the at least part of the device chips from the first substrate by rotating the first drum; and
a first transfer step for making the device chips on the selective adhesive region come into contact with and adhere to the second adhesive layer and for separating the device chips from the selective adhesive region by rotating the first drum.

US Pat. No. 10,461,057

DUAL-INTERFACE IC CARD MODULE

NXP B.V., Eindhoven (NL)...

1. A dual-interface integrated circuit card module, the module comprising:a substrate having first and second opposing surfaces;
a contact pad on the first surface of the substrate;
an integrated circuit on the second surface of the substrate, the integrated circuit having electrical connections to the contact pad through the substrate; and
a pair of antenna pads for providing electrical contact, disposed in recesses in the second surface of the substrate and electrically connected to corresponding antenna connections on the integrated circuit,
wherein the recesses pass through the substrate, the antenna pads being attached to a back surface of the contact pad with a non-conductive material, the non-conductive material in contact with the antenna pads and the contact pad, and the non-conductive material providing an insulating layer between the antenna pads and the contact pad.

US Pat. No. 10,461,056

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

Infineon Technologies AG,...

1. A chip package, comprising:a chip comprising a chip metal surface;
a metal contact structure, the metal contact structure electrically contacting the chip metal surface;
a packaging material; and
a protective layer comprising a portion formed at an interface between a portion of the metal contact structure and the packaging material;
wherein the protective layer comprises at least one material of a group of inorganic materials, the group consisting of
Ni, Co, Cr, Ti, V, Mn, Zn, Sn, Mo, and Zr,
wherein the protective layer further comprises a noble metal, wherein the protective layer comprises regions free from the noble metal, wherein the regions free from the noble metal provide at least a portion of the interface between the portion of the metal contact structure and the packaging material.

US Pat. No. 10,461,055

CU ALLOY CORE BONDING WIRE WITH PD COATING FOR SEMICONDUCTOR DEVICE

NIPPON MICROMETAL CORPORA...

1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; and
a Pd coating layer formed on a surface of the Cu alloy core material, wherein
the bonding wire contains at least one or more first elements selected from Sb, Bi and Se,
a concentration of the first elements in total is 0.1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire, and
Sb?10 ppm by mass; and Bi?1 ppm by mass, and
the bonding wire contains at least one or more second elements selected from Ni, Zn, Rh, In, Ir, Pt, Ga and Ge, and
a concentration of each of the second elements is 0.011% by mass or more and 1.2% by mass or less relative to the entire wire.

US Pat. No. 10,461,054

ANISOTROPIC CONDUCTIVE FILM AND PRODUCTION METHOD OF THE SAME

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film in which conductive particles are dispersed in an insulating resin layer, the anisotropic conductive film comprising:a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness of the anisotropic conductive film; and
a second conductive particle layer in which conductive particles are dispersed at a depth that is different from that of the first conductive particle layer, wherein
in each of the conductive particle layers, a closest distance between the adjacent conductive particles is 2 times or more an average particle diameter of the conductive particles.

US Pat. No. 10,461,053

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;
(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;
(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;
(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and
(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,
wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,
wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,
wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,
wherein the plurality of protection elements include a first protection element and a second protection element,
wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when viewed from a direction perpendicular to the substrate, and
wherein the second protection element electrically coupled to the second bump electrode is disposed at a position different from a position overlapped with the second bump electrode in a planar view when viewed from a direction perpendicular to the substrate.

US Pat. No. 10,461,052

COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS

Monolithic Power Systems,...

1. An integrated circuit (IC) chip comprising:a substrate comprising an integrated circuit;
a metal pad disposed on the substrate and electrically connects to the integrated circuit;
a redistribution layer that electrically connects to the metal pad;
a copper pillar that is disposed on and electrically connects to the redistribution layer;
a solder bump that is disposed on and electrically connects to the copper pillar; and
a tin-copper intermetallic coating that is formed on a surface of the copper pillar and the redistribution layer.

US Pat. No. 10,461,051

VIA STRUCTURE FOR PACKAGING AND A METHOD OF FORMING

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a substrate;
a plurality of conductive pads on the substrate;
a passivation layer on the conductive pads and the substrate;
a plurality of conductive pillars extending through the passivation layer and connected to the conductive pads; and
a molding compound extending between the conductive pillars and encapsulating sidewalls of the substrate, the molding compound comprising a single continuous material, wherein uppermost surfaces of the conductive pillars are level with uppermost surfaces of the molding compound.

US Pat. No. 10,461,050

BONDING PAD STRUCTURE OF A SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor chip;
a metal electrode formed on a surface of the semiconductor chip; and
metal wiring connected to the metal electrode via a bonding part,
wherein an outer peripheral of the metal wiring is covered with a metal layer consisting of a metal or an alloy different from a constituent metal of the metal electrode,
the bonding part has an alloy region harder than the metal wiring, and
the metal layer is formed on an upper surface and a lower surface of at least the metal wiring, and a part of the lower surface contacts the bonding part.

US Pat. No. 10,461,049

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
an aluminum electrode provided on the semiconductor substrate;
a metallic film for a solder joint provided on the aluminum electrode; and
an organic protective film provided on the aluminum electrode and apart from the metallic film,
wherein an interval between the organic protective film and the metallic film is equal to or greater than half of a thickness of the organic protective film.

US Pat. No. 10,461,048

INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING

LEONARDO MW LTD., Basild...

7. A method according to claim 6, in which:the manufacturing step (a) comprises:
manufacturing the amplifier with a first smaller gate size, and
the manufacturing step (b) comprises:
manufacturing a carrier chip having the second stage amplifier with a second gate size larger than that in the first portion.

US Pat. No. 10,461,047

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a substrate having an insulating layer disposed thereon, the substrate having a perimeter;
a metallization structure disposed on the insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack, wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon;
a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing;
a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring; and
a metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

US Pat. No. 10,461,046

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first region;
a second region surrounding an outer periphery of the first region; and
an annular seal ring formed in the second region,
wherein the second region includes:
an SOI substrate comprised of a semiconductor substrate of a first conductivity type, a buried insulating film over the semiconductor substrate, and a semiconductor layer over the buried insulating film; and
an interlayer insulating film formed over the semiconductor layer,
wherein the seal ring includes:
an annular electrode portion comprised of a conductive film buried in the interlayer insulating film;
the semiconductor layer; and
the buried insulating film, and
wherein the electrode portion is electrically connected with the semiconductor layer,
wherein an element isolation portion is formed in the semiconductor substrate between the first region and the second region, and the element isolation portion is thicker than the buried insulating film, and
wherein the semiconductor substrate under the buried insulating film has more than one PN junction portion.

US Pat. No. 10,461,045

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:an insulating substrate having a metal layer which is formed on an upper surface of said insulating substrate;
a semiconductor element and a main electrode each bonded to an upper surface of said metal layer;
a metal ware connecting said metal layer and said semiconductor element;
a metal member bonded to a lower surface side of said insulating substrate;
a case member surrounding said insulating substrate and affixed to said metal member; and
a sealing resin filled in a region surrounded by said metal member and said case member, said sealing resin having a resin strength equal to or higher than 0.12 MPa at room temperature, a microcrystallization temperature equal to or lower than ?55° C. and a needle penetration of 30 to 50 after storage at 175° C. for 1000 hours, said sealing resin sealing said insulating substrate, said metal layer, said semiconductor element, said metal wire, and said main electrode.

US Pat. No. 10,461,044

WAFER LEVEL FAN-OUT PACKAGE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a wafer level fan-out package, comprising:placing a chip and a base substrate against each other with an active surface of the chip facing the base substrate;
encapsulating the chip by forming an encapsulant on the base substrate;
removing the base substrate to expose the active surface of the chip and a surface of the encapsulant laterally adjacent to the chip;
forming a wiring structure on the active surface of the chip and on the surface of the encapsulant adjacent to the chip; and
subsequently mounting a passive electronic component on and electrically connecting the passive electronic component to the wiring structure,
wherein a recess is formed in the surface of the encapsulant laterally adjacent to the chip such that the recess is defined to one side of the chip in a direction parallel to said surface of the encapsulant, and
the passive electronic component is set within the recess such that the passive electronic component is disposed to said one side of the chip in the direction parallel to said surface of the encapsulant.

US Pat. No. 10,461,043

METHOD OF MANUFACTURING AN ELECTROMAGNETIC SHIELD

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package having a plurality of integrated circuit (IC) modules, wherein:
an inter-module area is horizontally in between two adjacent IC modules of the plurality of IC modules; and
each of the plurality of IC modules comprises a module substrate and at least one electronic component that is attached to a top surface of the module substrate and encapsulated by a mold compound, wherein the module substrate comprises a ground plane formed within the module substrate, and a plurality of first input/output (I/O) contacts formed at a bottom surface of the module substrate;
placing the precursor package onto a chemical resistant tape, such that the plurality of first I/O contacts of each module substrate are sealed and against the chemical resistant tape;
performing a sweller process on the precursor package, which resides over the chemical resistant tape;
performing a desmear process on the precursor package, which resides over the chemical resistant tape;
removing the chemical resistant tape to expose the plurality of first I/O contacts;
singulating the precursor package at each inter-module area to form a plurality of individual IC modules, each of which comprises the module substrate;
placing the individual IC modules onto a top surface of a carrier tape, such that the plurality of first I/O contacts of each individual IC module are sealed and against the carrier tape; and
applying a shielding structure completely over a top surface and side surfaces of each of the plurality of individual IC modules to form a plurality of shielded IC modules, wherein the shielding structure is electrically coupled to the ground plane within the corresponding module substrate.

US Pat. No. 10,461,042

SEMICONDUCTOR MODULE

SHINDENGEN ELECTRIC MANUF...

1. A semiconductor module comprising:a first substrate having a first insulating substrate and a first conductor layer which is formed on one-surface side of the first insulating substrate;
a power device part having a first electrode on one surface thereof and a second electrode and a gate electrode on the other surface thereof, and having the first electrode electrically connected to the first conductor layer;
a second substrate having a second insulating substrate, a second conductor layer formed on one-surface side of the second insulating substrate and a third conductor layer formed on the other surface of the second insulating substrate, wherein a hole is formed in the second insulating substrate at a position corresponding to a position of the gate electrode, the second conductor layer has a bonding portion bonded to the second electrode and a surrounding wall portion having an L shape formed at a position which surrounds the bonding portion as viewed in a plan view in a state where an upper end surface of the surrounding wall portion projects from a bonding surface between the second electrode and the bonding portion, and the second substrate is brought into contact with the first substrate by way of the surrounding wall portion;
an inner resin portion made of a resin and disposed in a space defined by the surrounding wall portion and sandwiched between the first insulating substrate and the second insulating substrate;
a control IC disposed on the third conductor layer; and
an outer resin portion made of a resin and disposed on the one surface side of the first substrate so as to cover the second substrate and the control IC, wherein
the first substrate, the power device part, the second substrate and the control IC are stacked in this order, wherein
a connecting member is disposed inside the hole formed in the second insulating substrate, and
the gate electrode is electrically connected to a control signal output terminal of the control IC through the connecting member.

US Pat. No. 10,461,041

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. An electronic package, comprising:a first carrier having a first side and a second side opposite to the first side;
at least one semiconductor chip disposed on the first side of the first carrier;
an encapsulant formed on the second side of the first carrier;
a first conductor disposed on the encapsulant and configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation; and
a second conductor disposed on the second side of the first carrier and corresponding in function to the first conductor.

US Pat. No. 10,461,040

MATCHED CERAMIC CAPACITOR STRUCTURES

APPLE INC., Cupertino, C...

1. A capacitor device comprising:a first capacitor comprising a first and a second electrical termination and first and second stacks of electrodes; and
a second capacitor comprising a third and a fourth electrical termination and third and fourth stacks of electrodes, wherein the first stack is disposed atop the third stack, the third stack is disposed atop the second stack, and the second stack is disposed atop the fourth stack;
wherein the first stack comprises:
a first set of electrodes, each respective electrode of the first set comprising a respective tab that couples each respective electrode to the first electrical termination; and
a second set of electrodes, each respective electrode of the second set comprising a respective tab that couples each respective electrode to the second electrical termination, wherein each electrode of the second set is disposed between two electrodes of the first set of electrodes;
the second stack comprises:
a third set of electrodes, each respective electrode of the third set comprising a respective tab that couples each respective electrode to the first electrical termination; and
a fourth set of electrodes, each respective electrode of the fourth set comprising a respective tab that couples each respective electrode to the second electrical termination, wherein each electrode of the fourth set is disposed between two electrodes of the third set of electrodes;
the third stack comprises:
a fifth set of electrodes, each respective electrode of the fifth set comprising a respective tab that couples each respective electrode to the third electrical termination; and
a sixth set of electrodes, each respective electrode of the sixth set comprising a respective tab that couples each respective electrode to the fourth electrical termination, wherein each electrode of the sixth set is disposed between two electrodes of the fifth set of electrodes; and
the fourth stack comprises:
a seventh set of electrodes, each respective electrode of the seventh set comprising a respective tab that couples each respective electrode to the third electrical termination; and
an eighth set of electrodes, each respective electrode of the eighth set comprising a respective tab that couples each respective electrode to the fourth electrical termination, wherein each electrode of eighth set is disposed between two electrodes of the seventh set of electrodes; and
wherein a body of the capacitor device comprises a right prism shape that comprises:
a square base comprising a bottom of the body of the capacitor device;
a first side comprising the first electrical termination;
a second side distinct from the first side, comprising the second electrical termination;
a third side distinct from the first and the second side, comprising the third electrical termination; and
a fourth side distinct from the first, the second, and the third side, comprising the fourth electrical termination.

US Pat. No. 10,461,039

MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS

NIKON CORPORATION, Tokyo...

1. A method for producing a device comprising:forming a pre-pattern on a mark formation area of a substrate;
applying a polymer layer containing a block copolymer to the pre-pattern;
allowing the polymer layer, applied to the pre-pattern, to form a self-assembled area;
selectively removing a portion of the self-assembled area;
forming an alignment mark by using the self-assembled area from which the portion of the self-assembled area has been removed;
illuminating the alignment mark formed on the substrate with an illumination light;
detecting the alignment mark by receiving a light from the alignment mark with a detector; and
changing a polarization state of the illumination light.

US Pat. No. 10,461,038

METHODS OF ALIGNMENT MARKING SEMICONDUCTOR WAFERS, AND SEMICONDUCTOR PACKAGES HAVING PORTIONS OF ALIGNMENT MARKINGS

Micron Technology, Inc., ...

1. A method for alignment marking a semiconductor wafer, comprising:defining die locations associated with the semiconductor wafer, and defining alignment mark locations between the die locations;
forming first alignment marks within the alignment mark locations at a first level of processing associated with the semiconductor wafer; the first alignment marks comprising first segments extending primarily along a first direction, and comprising second segments extending primarily along a second direction substantially orthogonal to the first direction;
forming second alignment marks within the alignment mark locations at a second level of processing associated with the semiconductor wafer; the second level of processing being subsequent to the first level of processing; the second alignment marks comprising third segments extending primarily along the first direction, and comprising fourth segments extending primarily along the second direction; and
forming a texture within the alignment mark locations, the texture having a pattern other than lines extending along either the first or second direction.

US Pat. No. 10,461,037

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH OVERLAY GRATING

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:forming a first overlay grating over a substrate, wherein the first overlay grating has a first strip portion and a second strip portion, the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other, there is a first distance between a first sidewall of the first strip portion and a second sidewall of the second strip portion, the first sidewall faces away from the second strip portion, and the second sidewall faces the first strip portion;
forming a first layer over the first overlay grating, wherein the first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion; and
forming a second overlay grating over the first layer, wherein the second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, and the first distance is substantially equal to the second distance,
wherein the first layer further has a second trench elongated in the second elongated axis, the second trench extends across the first strip portion and the second strip portion, there is a third distance between a first inner wall of the first trench and a second inner wall of the second trench, the first inner wall faces away from the second trench, the second inner wall faces the first trench, and the third distance is less than the second distance.

US Pat. No. 10,461,036

MULTI-STACKED PACKAGE-ON-PACKAGE STRUCTURES

Taiwan Semiconductor Manu...

1. A device comprising:a first substrate;
a first integrated circuit die over the first substrate;
a second integrated circuit die over the first substrate, the second integrated circuit die having a different function than the first integrated circuit die;
a passive device over the second integrated circuit die, the passive device comprising a second substrate and through silicon vias (TSVs) extending through the second substrate; and
a first redistribution structure over the passive device, the first integrated circuit die, and the second integrated circuit die, the TSVs of the passive device electrically connecting the second integrated circuit die to the first redistribution structure.

US Pat. No. 10,461,035

SEMICONDUCTOR PACKAGE STRUCTURE

Industrial Technology Res...

1. A semiconductor package structure, comprising:a redistribution structure comprising a redistribution layer and a first dielectric layer disposed on the redistribution layer;
a chip disposed the on the redistribution structure;
an upper dielectric layer disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials;
a plurality of conductive members disposed between the redistribution layer and the chip, with each conductive member having a first end adjacent to the chip and a second end adjacent to the redistribution structure;
wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer; and
an encapsulation layer filled between the redistribution structure, the chip and the plurality of conductive members,
wherein Young's modulus of the upper dielectric layer is A, Young's modulus of the encapsulation layer is B, and Young's modulus of the first dielectric layer is D, wherein the semiconductor package structure satisfies the following inequalities:
A/B<1; and D/B<1.

US Pat. No. 10,461,034

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

18. A manufacturing method of a package structure, comprising:providing a carrier;
forming a conductive plate having a first surface and a second surface opposite to the first surface and disposing the first surface of the conductive plate on the carrier;
disposing at least one die provided with a connecting film directly on the second surface of the conductive plate and physically contacting the at least one die and the second surface of the conductive plate by sandwiching the connecting film therebetween;
forming through interlayer vias on the second surface of the conductive plate;
encapsulating the at least one die, the connecting film and the through interlayer vias, and covering the second surface of the conductive plate with a molding compound;
debonding the carrier and exposing a third surface of the molding compound levelled and coplanar with the first surface of the conductive plate;
forming an encapsulant over the third surface of the molding compound; and
forming antenna elements on the encapsulant, the encapsulant being located between the antenna elements and the conductive plate, and the conductive plate being located between the encapsulant and the connecting film.

US Pat. No. 10,461,033

SEMICONDUCTOR MEMORY PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory package comprising:a package base substrate comprising a substrate base, and a plurality of chip connection pads and a plurality of external connection pads respectively arranged on upper and lower surfaces of the substrate base; and
at least two semiconductor memory chips mounted on the package base substrate and each having a plurality of chip pads electrically connected to the plurality of chip connection pads,
wherein a first electrical path extends from one of the plurality of external connection pads to a first chip pad of one of the at least two semiconductor memory chips and a second electrical path extends from the one of the plurality of external connection pads to a second chip pad of another of the at least two semiconductor memory chips,
the first electrical path and the second electrical path comprises a common line extending from a branch point of the first electrical path and the second electrical path, to the one of the plurality of external connection pads,
a first branch line of the first electrical path extends from the branch point to the first chip pad and a second branch line of the second electrical path extends from the branch point to the second chip pad, and
the package base substrate comprises an open stub extending from the common line, the open stub having one end connected to the common line and another other end which is open without being connected to another electrical path and having a stub extension length greater than half of a branch extension length of a longer of the first branch line and the second branch line and less than twice the branch extension length.

US Pat. No. 10,461,032

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

Intel Corporation, Santa...

1. An apparatus, comprising:a first die and a die-bonding film disposed on and entirely covering a back surface of the first die, but not extending beyond the back surface of the first die, wherein a surface of the die-bonding film is an exposed surface;
a second die including one or more through-silicon vias disposed therein (TSV die), the first die electrically coupled to the TSV die through the one or more through-silicon vias, wherein the first die is electrically coupled to the TSV die through the one or more through-silicon vias by one or more corresponding conductive bumps disposed on the first die and by one or more bond pads disposed on the TSV die;
a layer of epoxy flux material disposed between the first die and the TSV die, the layer of epoxy flux material surrounding the one or more corresponding conductive bumps disposed on the first die;
a coreless substrate, wherein the die-bonding film and both the first die and the TSV die are embedded in the coreless substrate, wherein no surface of the first die and the die-bonding film protrudes from a surface of the coreless substrate, and wherein the coreless substrate comprises a continuous encapsulation layer laterally surrounding both the first die and the TSV die, wherein one or more conductive vias extend through the entirety of the coreless substrate, wherein the exposed surface of the die-bonding film is co-planar with corresponding pads of the one or more conductive vias;
a plurality of conductive contacts disposed on a surface of the coreless substrate, wherein the plurality of conductive contacts is above the second die and the second die is above the first die and the die-bonding film; and
a packaged die attached to the corresponding pads of the one or more conductive vias.

US Pat. No. 10,461,031

METHOD FOR PATTERNING A POWER METALLIZATION LAYER, ELECTRONIC DEVICE AND METHOD FOR PROCESSING AN ELECTRONIC DEVICE

INFINEON TECHNOLOGIES AG,...

1. A method for processing an electronic device, the method comprising:forming a patterned hard mask layer over a copper power metallization layer, the patterned hard mask layer exposing a major outer surface of the copper power metallization layer; and
patterning the copper power metallization layer by wet etching of the exposed major surface of the copper power metallization layer, wherein forming the patterned hard mask layer comprises forming a patterned alumina layer with a thickness less than 15 nm, wherein the copper power metallization layer has a thickness greater than 5 ?m.

US Pat. No. 10,461,030

PAD STRUCTURES AND WIRING STRUCTURES IN A VERTICAL TYPE SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A pad structure of a vertical type semiconductor device, comprising:a plurality of conductive patterns stacked in a vertical direction from a top surface of a substrate, the plurality of conductive patterns including a first group including a plurality of first conductive patterns and a plurality of second conductive patterns for confirming process disposed between the plurality of first conductive patterns included in the first group; and
a plurality of insulation patterns between the plurality of conductive patterns in the vertical direction,
wherein edge portions of the plurality of conductive patterns stacked including a first stepped shape portion having first steps in a first direction, the first direction being an extension direction of the plurality of first and second conductive patterns, and a second stepped shape portion having second steps in a second direction substantially perpendicular to the first direction, and
wherein one of the plurality of first conductive patterns has a first exposed region on a first top surface thereof that is adjacent to a first edge thereof in the first direction,
one of the plurality of second conductive patterns, which is immediately below the one of the plurality of first conductive patterns, has a second exposed region on a second top surface thereof that is adjacent to a second edge thereof in the first direction,
a first length of the first exposed region in the first direction is different from a second length of the second exposed region in the first direction, and
the one of the plurality of first conductive patterns has a first edge shape without a dent at the first edge thereof, and the one of the plurality of second conductive patterns has a second edge shape with a dent at one side of the second edge thereof such that a protrusion corresponding to the second exposed region is provided.

US Pat. No. 10,461,029

HYBRID MATERIAL ELECTRICALLY PROGRAMMABLE FUSE AND METHODS OF FORMING

GLOBALFOUNDRIES INC., Gr...

1. An electrically programmable fuse (e-fuse) comprising:a substrate;
an insulator layer over the substrate;
a pair of contact regions overlying the insulator layer; and
a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP), wherein the first portion has an upper surface and a lower surface and the second portion has an upper surface and a lower surface, wherein the upper surface of the first portion is coplanar with the upper surface of the second portion and the lower surface of the first portion is coplanar with the lower surface of the second portion;
wherein a first one of the pair of contact regions includes a silicon layer on the common level with the first portion of the silicide channel and the second portion of the silicide channel, and a second one of the pair of contact regions includes a SiGe layer on the common level with the second portion of the silicide channel and the first portion of the silicide channel;
wherein the first portion is formed entirely of the silicide Si and the second portion is formed entirely of the silicide SiGe or the silicide SiP; and
wherein an upper surface of the silicon layer of the first one of the pair of contact regions is coplanar with an upper surface of the SiGe layer of the second one of the pair of contact regions.

US Pat. No. 10,461,028

SEMICONDUCTOR DEVICE INCLUDING A VERTICAL ONE-TIME PROGRAMMABLE FUSE THAT INCLUDES A CONDUCTIVE LAYER AND A RESISTIVE MATERIAL AND A METHOD OF MAKING THE SAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a substrate;
forming a first insulating layer over the substrate;
forming a first opening through the first insulating layer;
forming a first conductive layer along a sidewall of the first opening; and
depositing a resistive material within the first opening over the first conductive layer, wherein:
the resistive material has a resistivity 10 times or greater than the first conductive layer, and
the first conductive layer and resistive material form a vertical one-time-programmable (OTP) fuse with electrically conductive properties associated with the fuse along the sidewall of the first opening.

US Pat. No. 10,461,027

SEMICONDUCTOR DEVICE INCLUDING VIA PLUG AND METHOD OF FORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a lower insulating layer on a substrate;
a conductive pattern in the lower insulating layer;
a middle insulating layer on the lower insulating layer and the conductive pattern;
a via control region in the middle insulating layer, the via control region having a lower etch rate than the middle insulating layer;
an upper insulating layer on the middle insulating layer and the via control region; and
a via plug passing through the via control region and connected to the conductive pattern.

US Pat. No. 10,461,026

TECHNIQUES TO IMPROVE RELIABILITY IN CU INTERCONNECTS USING CU INTERMETALLICS

International Business Ma...

1. A method of forming a copper (Cu) interconnect in a dielectric over a Cu line, the method comprising the steps of:forming at least one via in the dielectric over the Cu line;
depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic;
annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via;
plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier; and
forming a Cu intermetallic liner on sidewalls of the via, wherein the Cu intermetallic liner is formed on the sidewalls of the via after the Cu intermetallic barrier is formed at the bottom of the via,
wherein the method further comprises the steps of:
depositing a Cu seed layer into and lining the via;
performing another anneal which comprises annealing the metal layer and the Cu seed layer to form the Cu intermetallic liner on the sidewalls of the via; and
plating the Cu into the via over the Cu intermetallic liner.

US Pat. No. 10,461,025

LOW COST METALLIZATION DURING FABRICATION OF AN INTEGRATED CIRCUIT (IC)

Skyworks Solutions, Inc.,...

1. An integrated circuit comprising:a wafer having a front surface and a back surface;
a via hole etched on the wafer;
a metal layer deposited along walls of the via hole, the metal layer electrically connects the front surface and the back surface; and
a seed metal layer deposited on the back surface of the wafer, the seed metal layer deposited prior to a photoresist layer and thickened after removal of the photoresist layer.

US Pat. No. 10,461,024

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a laminated substrate including an insulating substrate and a circuit board provided on a main surface of the insulating substrate, the circuit board including a first circuit pattern;
a hollow case provided on an outer edge of the laminated substrate, the laminated substrate being surrounded by the hollow case in a plan view of the semiconductor device;
a first lead frame having a first end soldered directly to the first circuit pattern, and another end provided outside the case, the first lead frame extending through the case such that the first end is located inward of an inside surface of the case and the second end is located outward of an outside surface of the case; and
a semiconductor element soldered directly to the first lead frame inside the case.

US Pat. No. 10,461,023

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a chip;
a redistribution circuit structure, disposed over and electrically connected to the chip and comprising a topmost conductive pattern;
a under-ball metallurgy (UBM) pattern disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern comprises a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern;
a passive component mounted to the redistribution circuit structure through the UBM pattern; and
a solder region between the UBM pattern and the passive component.

US Pat. No. 10,461,022

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first die including a first surface and a second surface opposite to the first surface;
a molding surrounding the first die;
a via extended through the molding;
an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer;
a second die disposed over the molding and including a third surface facing the first die, a fourth surface opposite to the third surface and a sidewall between the third surface and the fourth surface;
a connector disposed between the second die and the via and being in contact with the third surface of the second die and the via; and
an underfill surrounding the connector and being in contact with a portion of the second surface of the first die,wherein the second die is electrically connected to the via, and the underfill covers a portion of the sidewall of the second die and exposes entirely the fourth surface of the second die.

US Pat. No. 10,461,021

ELECTRONIC ASSEMBLY WITH ENHANCED THERMAL DISSIPATION

1. An electronic assembly comprising:a first heat sink having a first base or substantially planar mating surface;
a semiconductor device comprises a first side and a second side opposite the first side; the first side having a first conductive pad; the second side having a primary metallic surface;
a first substrate bonded to the first conductive pad via first metallic bonding layer, wherein the first substrate comprises a lead frame with a substantially planar portion having a lower surface for interfacing with the first conductive pad on the semiconductor device and having an upper surface;
a dielectric thermal interface material disposed between the lead frame and the first heat sink, such that the first base or the substantially planar mating surface adjoins the dielectric thermal interface material; and
a second substrate bonded to the primary metallic surface via a second metallic bonding layer, wherein the second metallic bonding layer is composed of solder and copper pellets or a copper material embedded in the solder as filler, wherein the semiconductor device has a primary coefficient of thermal expansion (CTE) and wherein the first substrate has a secondary coefficient of thermal expansion (CTE), and wherein the copper material in the first metallic bonding layer or the second metallic bonding layer, respectively, reduces a mismatch between the primary CTE and the secondary CTE.

US Pat. No. 10,461,020

POSITIONAL RELATIONSHIP AMONG COMPONENTS OF SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. An electronic device, comprising:a mother board;
a plurality of metal pins inserted into the mother board;
a first semiconductor device mounted on the mother board; and
a second semiconductor device mounted on the mother board,
wherein the plurality of metal pins has:
a first metal pin located closest to the first semiconductor device, and
a second metal pin located closest to the second semiconductor device,
wherein a first distance between the first metal pin and the first semiconductor device is smaller than a second distance between the second metal pin and the second semiconductor device,
wherein the first semiconductor device is comprised of:
a die pad including a first surface and a second surface opposite to the first surface,
a semiconductor chip including a main surface, a plurality of bonding electrodes formed on the main surface and a back surface opposite to the main surface, and mounted on the first surface of the die pad via a die bond material such that the back surface faces the first surface of the die pad, the semiconductor chip being essentially comprised a first material having a first linear expansion coefficient,
a plurality of leads electrically connected with the plurality of bonding electrodes via a plurality of wires, respectively, and
a sealing body including an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and also opposite to the first side surface, and sealing the semiconductor chip and the plurality of wires, the sealing body being essentially comprised of a second material having a second linear expansion coefficient, which is higher than the first linear expansion coefficient,
wherein each of the plurality of leads has:
an inner part sealed with the sealing body, and
an outer part exposed from the sealing body,
wherein the outer part has:
a first part connected to the inner part and extending in a horizontal direction, which is along the upper surface of the sealing body,
a second part connected to the first part via a first bending portion that bends the outer part in a thickness direction, which is from the upper surface toward the lower surface, of the sealing body, and
a third part connected to the second part via a second bending portion that bends the outer part in the horizontal direction,
wherein the plurality of leads has:
a first lead electrically connected with a first bonding electrode of the plurality of bonding electrodes via a first wire of the plurality of wires and protruding from the first side surface of the sealing body, and
a second lead electrically connected with a second bonding electrode of the plurality of bonding electrodes via a second wire of the plurality of wires and protruding from the second side surface of the sealing body,
wherein, in cross-section view, the semiconductor chip is located between the inner part of the first lead and the inner part of the second lead,
wherein, in cross-section view, a first thickness of the semiconductor chip is greater than a second thickness from the second surface of the die pad to the lower surface of the sealing body, which is greater than a third thickness of each of the die pad and the die bond material,
wherein, in cross-section view, a stand-off amount of each of the plurality of leads, which is a distance, in the thickness direction of the sealing body, from the lower surface of the sealing body to the third part of the outer part, is greater than 0.40 mm and less than a fourth thickness from the upper surface of the sealing body to the lower surface of the sealing body, and body, and
wherein, in cross-section view, the stand-off amount of each of the plurality of leads is greater than a fifth thickness from an upper surface of the inner part of each of the plurality of leads, which is located on the same side as the main surface of the semiconductor chip, to the upper surface of the sealing body, or a sixth thickness from a lower surface of the inner part of each of the plurality of leads, which is located on the same side as the second surface of the die pad, to the lower surface of the sealing body.

US Pat. No. 10,461,019

PACKAGE WITH BACKSIDE PROTECTIVE LAYER DURING MOLDING TO PREVENT MOLD FLASHING FAILURE

STMICROELECTRONICS, INC.,...

1. A semiconductor package, comprising:a leadframe, the leadframe including:
a die pad having a thick portion and a thin portion, the thin portion being in a peripheral region of the die pad and extending away from a central region; and
a plurality of leads spaced from and adjacent to the die pad, each lead of the plurality of leads having a thick portion and a thin portion, the thin portion of the lead being in a peripheral region of the lead and extending towards the thin portion of the die pad;
a die coupled to the die pad;
a plurality of wires, each wire having a first end coupled to a respective lead of the plurality of leads and a second end coupled to the die;
a molding compound that encases the die, the plurality of wires, the die pad, and each lead of the plurality of leads, the molding compound being positioned in the space between the die pad and each lead of the plurality of leads, the molding compound having a first width in a location between the thin portion of the die pad and the thin portion of the lead and a second, greater width in a location between the thick portion of the die pad and the thick portion of the lead;
an extension portion of molding compound that is integral with the molding compound, the extension portion including an end extending a first length beyond a first exposed surface of each lead of the plurality of leads and a second exposed surface of the die pad, the extension portion having the second width that is greater than the first width and extending a second, greater length from the thin portions of the plurality of leads and the thin portion of the die pad to the end of the extension portion;
a plurality of first recesses in the molding compound exposing the first exposed surface of each lead of the plurality of leads, each first recess having a first depth equal to the first length; and
a second recess exposing the second exposed surface of the die pad, the second recess having a second depth equal to the first length.

US Pat. No. 10,461,018

INTEGRATED MULTI-CHAMBER HEAT EXCHANGER

Lockheed Martin Corporati...

1. A method of cooling a component with a heat exchanger configured to provide multi-mode cooling, the method comprising:arranging the heat exchanger adjacent to the component, wherein the heat exchanger comprises a first inlet, a first outlet, a second inlet, a second outlet, and a plurality of channels, wherein the plurality of channels includes a first set of channels configured to provide cooling in a first cooling mode using a first coolant medium and a second set of channels configured to provide cooling in a second cooling mode using a second coolant medium having different thermal properties than the first coolant medium;
circulating the first coolant medium through the first set of channels such that the first coolant medium flows between the first inlet and the first outlet; and
circulating the second coolant medium through the second set of channels such that the second coolant medium flows between the second inlet and the second outlet.

US Pat. No. 10,461,017

PACKAGE WITH PARTIALLY ENCAPSULATED COOLING CHANNEL FOR COOLING AN ENCAPSULATED CHIP

Infineon Technologies AG,...

1. A power module, comprising:a semiconductor chip;
at least one cooling plate with at least one cooling channel integrally formed therein, thermally coupled to a first main surface of the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel; and
an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel;
a second cooling channel thermally coupled to a second main surface of the semiconductor chip opposing the first main surface;
an electrically conductive wiring structure which is configured for electrically connecting the semiconductor chip with regard to an environment and which is attached to a surface of the cooling plate;
wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

US Pat. No. 10,461,016

CERAMIC MODULE FOR POWER SEMICONDUCTOR INTEGRATED PACKAGING AND PREPARATION METHOD THEREOF

DONGGUAN CHINA ADVANCED C...

1. A ceramic module for power semiconductor integrated packaging, comprising a ceramic substrate and an integrated metal dam layer; a lower surface of the ceramic substrate being provided with a conductive circuit layer, an insulating layer and a heat dissipation layer, the insulating layer completely covering the conductive circuit layer, the heat dissipation layer being located on an area outside the conductive circuit layer and spaced apart from the conductive circuit layer, the heat dissipation layer having a thickness not less than a total thickness of the conductive circuit layer and the insulation layer; an upper surface of the ceramic substrate being provided with a positive electrode pad, a negative electrode pad and a plurality of die bonding regions, the die bonding regions each having a connecting layer and a die bonding layer, the connecting layer and the die bonding layer being spaced apart from each other; the ceramic substrate being provided with vertical via holes, the vertical via holes being electrically connected between the die bonding regions and the conductive circuit layer and between the conductive circuit layer and the positive electrode pad and the negative electrode pad respectively; the integrated metal dam layer being disposed on the upper surface of the ceramic substrate, the integrated metal dam layer surrounding a periphery of a single one or the plurality of die bonding regions and being spaced apart from the die bonding regions, the integrated metal dam layer having a thickness greater than that of the die bonding regions;wherein the integrated metal dam layer is formed with a plurality of cavities each of which extends from a top surface of the integrated metal dam to the upper surface of the ceramic substrate, each of the plurality of cavities defining one of the die bonding regions, the connecting layer and the die bonding layer of the one of the die bonding region being disposed on a part of the upper surface of the ceramic substrate that is located inside the cavity such that each of the connecting layer and the die bonding layer is connected to one of the vertical via holes; and
wherein each one of the die bonding regions is separated from adjacent ones of the die bonding regions by the integrated metal dam and the connecting layer and the die bonding layer of said each one of the die bonding regions are each connected to one of the connecting layer and the die bonding layer of an adjacent one of the die bonding regions by means of the vertical via holes connected thereto and a part of the conductive circuit layer connected between the via holes that are connected to said each one of the die bonding regions and said adjacent one of the die bonding regions so that said each one and said adjacent one of the die bonding regions that are provided on the upper surface of the ceramic substrate are electrically connected to each other by means of the part of the conductive circuit layer provided on the lower surface of the ceramic substrate and the plurality of die bonding regions are connected to each other and are also connected to the positive and negative electrode pads by means of the conductive circuit layer provided on an opposite side of the ceramic substrate.

US Pat. No. 10,461,015

CARBON NANOTUBE-BASED THERMAL INTERFACE MATERIALS AND METHODS OF MAKING AND USING THEREOF

CARBICE CORPORATION, Atl...

1. A method for making contact to a device under test with a thermally conductive and/or electrically conductive, mechanically compliant substrate having an adhesive surface, the method comprising the steps of:attaching the thermally conductive and/or electrically conductive, mechanically compliant substrate directly to a thermal or electrical unit head to cover an area of the thermal or electrical unit head completely or matching a size of the device under test;
engaging the thermal or electrical unit head to the attached thermally conductive and/or electrically conductive, mechanically compliant substrate to the device under test at a pressure of at least 10 psi and at a temperature of less than 150° C.;
holding the thermal or electrical unit head engaged to the attached thermally conductive and/or electrically conductive, mechanically compliant substrate to the device under test under the pressure of at least 10 psi for at least 1 to 300 seconds;
disengaging and re-engaging the thermal or electrical head to the attached thermally conductive and/or electrically conductive, mechanically compliant substrate with the device under test for at least 1,500 cycles of powering up of the device under test; and
measuring or calculating thermal resistance and/or relative thermal resistance of the device under test following cycling.

US Pat. No. 10,461,014

HEAT SPREADING DEVICE AND METHOD

Taiwan Semiconductor Manu...

19. A method comprising:attaching a die stack to an interposer, the die stack comprising active devices, the interposer comprising interconnect structures, the interconnect structures of the interposer being electrically coupled to the active devices of the die stack after the attaching the die stack to the interposer;
encapsulating the die stack with an encapsulant;
forming a dummy through substrate via (TSV) in the die stack;
plating dummy metallization on the dummy TSV, the die stack, and the encapsulant;
forming a conductive feature on the dummy metallization, wherein the dummy TSV, the dummy metallization, and the conductive feature are electrically isolated from the active devices of the die stack and the interconnect structures of the interposer;
dispensing a thermal interface material around the conductive feature and on the dummy metallization; and
attaching a heat spreader to the die stack with the thermal interface material, the thermal interface material, the dummy metallization, and the conductive feature thermally coupling the heat spreader to the dummy TSV.

US Pat. No. 10,461,013

HEAT SINK AND ELECTRONIC COMPONENT DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A heat sink comprising:a flat plate portion;
a first protruding portion which is formed on an outer peripheral portion of the flat plate portion so as to surround a central portion of the flat plate portion and which protrudes in a thickness direction of the flat plate portion, and the first protruding portion is formed into a frame shape in a plan view;
an extending portion which extends outward from the flat plate portion; and
a second protruding portion which is formed on the extending portion such that the first protruding portion is positioned between the second protruding portion and the central portion of the flat plate portion and which protrudes in the thickness direction of the flat plate portion, the second protruding portion is formed on the extending portion such that the second protruding portion discontinuously surrounds the first protruding portion such that the second protruding portion is not opposed to the first protruding portion at four corners of the first protruding portion,
wherein the flat portion, the extending portion, the first protruding portion, and the second protruding portion are integrally formed as a unitary piece.

US Pat. No. 10,461,012

SEMICONDUCTOR MODULE WITH REINFORCING BOARD

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor module comprising:a semiconductor element;
an insulating circuit board having an insulating substrate, a circuit member electrically connected to the semiconductor element and disposed on one principal surface of the insulating substrate, and a first metal member disposed on another principal surface of the insulating substrate arranged at a side opposite to the one principal surface;
a second metal member, a portion of which is at least disposed outside the insulating substrate, continuously and entirely surrounding the insulating substrate with a space therebetween, the second metal member including a bottom portion and side portions extending from the bottom portion in a direction away from the cooler;
a molding resin portion sealing the semiconductor element, the insulating circuit board, and the second metal member such that a bottom portion of the first metal member and the bottom portion of the second metal member are not covered by the molding resin, and the molding resin is interposed between the first metal member and the second metal member and is surrounded by the side portions of the second metal member;
a cooler, wherein the bottom portion of the second metal member faces the cooler;
a first bonding member bonding the cooler and the first metal member; and
a second bonding member bonding the cooler and the second metal member and spaced from the first bonding member without the molding resin between the first bonding member and the second bonding member,
wherein the second metal member is a frame forming an L shaped erected portion that reinforces an outer shape of the molding resin portion.

US Pat. No. 10,461,011

MICROELECTRONICS PACKAGE WITH AN INTEGRATED HEAT SPREADER HAVING INDENTATIONS

Intel Corporation, Santa...

13. A method of manufacturing a microelectronics package, the method comprising:attaching a first die, a second die, and a third die to a substrate;
forming a first indentation in a first surface of an integrated heat spreader;
forming a second indentation in the integrated heat spreader; and
attaching the integrated heat spreader to the first die, the second die, and the third die such that:
the first indentation is located in between the first die and the second die, and
the second indentation is located in between the third die and the first die and the second die.

US Pat. No. 10,461,010

POWER MODULE, POWER SEMICONDUCTOR DEVICE AND POWER MODULE MANUFACTURING METHOD

MITSUBISHI ELECTRIC CORPO...

1. A power module which comprises a power element, a metal base for dissipating heat from the power element, a lead frame electrically connected to electrodes of the power element, and a resin enclosure that encapsulates the power element so that one surface of the metal base and a part of the lead frame are exposed from the enclosure,said resin enclosure comprising:
a body portion in which the power element and a part of the lead frame are placed, and at a bottom surface of which said one surface of the metal base is exposed; and
a rib portion which is placed on the bottom surface of the body portion so as to surround an outer periphery of the metal base, and is formed to protrude from the bottom surface of the body portion in a direction perpendicular to the bottom surface, the rib portion extending lower than said one surface of the metal base;
wherein the rib portion has a depression at its end overhanging from the bottom surface.

US Pat. No. 10,461,009

3DIC PACKAGING WITH HOT SPOT THERMAL MANAGEMENT FEATURES

Taiwan Semiconductor Manu...

1. A package comprising:a die stack comprising:
a plurality of first dies; and
a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and
a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises:
a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and
a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line.

US Pat. No. 10,461,008

ELECTRONIC COMPONENT PACKAGE HAVING STRESS ALLEVIATION STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer;
a semiconductor chip disposed on the wiring part;
a frame disposed on the wiring part, having upper and lower surfaces opposing each other, and including a component disposition region defined by an inner wall of the frame surrounding the semiconductor chip; and
an encapsulant filling at least a portion of the component disposition region,
wherein a portion of the inner wall of the frame has first and second protrusions, made of an insulating material and disposed on opposite sides of the semiconductor chip, protruding toward the semiconductor chip,
each of the first and second protrusions has an upper surface, a lower surface opposing the upper surface, and an end surface connecting the upper and lower surfaces of a respective one of the first and second protrusions and opposing the inner wall of the frame, the semiconductor chip disposed between the end surfaces of the first and second protrusions,
the upper surface of the frame and the upper surface of each of the first and second protrusions have a first step, and the lower surface of the frame and the lower surface of each of the first and second protrusions have a second step,
the encapsulant extends continuously from the upper surface of the frame to the second step and passes the first step, a space between the first protrusion and the semiconductor chip, and a space between the second protrusion and the semiconductor chip, and
no electrically conductive pattern is disposed directly on the upper surface or the lower surface of each of the first and second protrusions to be electrically connected to the semiconductor chip.

US Pat. No. 10,461,007

SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

Intel Corporation, Santa...

1. A microelectronics package, comprising:a substrate having a top substrate surface and a substrate outer periphery, the top substrate surface having an electronic component mounted thereon and the top substrate surface having a conductive trace along at least a portion of the substrate outer periphery;
a molding compound provided over the top substrate surface, having a bottom molding surface, a top molding surface, and a molding sidewall substantially overlying the substrate outer periphery;
a metallic sheet provided over the top molding surface; and
epoxy provided on the molding sidewall, wherein the epoxy includes conductive particles, and wherein the epoxy is electrically coupled to the metallic sheet, wherein the electronic component is a first electronic component, and wherein the microelectronics package further comprises:
a second electronic component; and
a conductive structure electrically connected to the conductive trace and the
metallic sheet, and disposed between the first electronic component and the second electronic component in a trench formed in the molding extending from the bottom molding surface to the top molding surface.

US Pat. No. 10,461,006

ENCAPSULATED SEMICONDUCTOR PACKAGE

Amkor Technology, Inc., ...

1. An integrated circuit package comprising:a substrate comprising a first substrate side, a second substrate side opposite the first substrate side, and a plurality of lateral substrate sides that extend between the first substrate side and the second substrate side;
an integrated circuit die comprising a first die surface, a second die surface opposite the first die surface, and a plurality of lateral die surfaces that extend between the first die surface and the second die surface, where the second die surface is coupled to the first substrate side; and
an encapsulant that covers at least the plurality of lateral die surfaces and the plurality of lateral substrate sides,
wherein the substrate comprises a plurality of conductive layers comprising:
a first conductive layer comprising a plurality of conductive interconnects at the first substrate side, wherein:
each of the conductive interconnects is coupled to a respective pad of the integrated circuit die;
each of the conductive interconnects comprises a metal positioned outside a footprint of the integrated circuit die; and
each of the conductive interconnects comprises a laterally outermost surface that is positioned laterally inward from an outermost periphery of the substrate; and
a second conductive layer comprising a plurality of lands at the second substrate side.

US Pat. No. 10,461,005

SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a dielectric layer having a first surface and a second surface opposite to the first surface; and
a conductive post disposed in the dielectric layer, the conductive post comprising a first portion and a second portion disposed above the first portion, the second portion of the conductive post being recessed from the second surface of the dielectric layer,
wherein the second surface of the dielectric layer has an arithmetic average surface roughness (Ra) value, and wherein the Ra value is greater than approximately 450 nanometers (nm).

US Pat. No. 10,461,004

INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF PRODUCING THEREOF

QDOS FLEXCIRCUITS SDN BHD...

1. An integrated circuit substrate, comprising:at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited through plating or printing of an electronically conductive material on a partially or completely removable carrier; and
a dielectric layer encapsulating the internal conductive trace layers through a lamination process or printing process;
wherein the dielectric layer has a first opening to expose at least one top surface of a topmost internal conductive trace layer when the carrier is partially or completely removed;
wherein the dielectric layer has a second opening to expose at least one bottom surface of a bottommost internal conductive trace layer when the carrier is partially or completely removed;
a first finishing layer formed on the exposed top surface of the topmost internal conductive trace layer when the carrier is partially or completely removed;
a second finishing layer formed on the exposed bottom surface of the bottommost internal conductive trace layer when the carrier is partially or completely removed;
wherein the internal conductive trace layers are configured in a manner where the internal conductive trace of an upper internal conductive trace layer is disposed on top of at least an internal conductive trace of a lower internal conductive trace layer;
at least an external conductive trace layer formed by one or more external conductive traces on any one or combination of a top surface of the dielectric layer, a top surface of the exposed topmost internal conductive trace layer, a bottom surface of the dielectric layer when the carrier is partially or completely removed, and a bottom surface of the exposed bottommost internal conductive trace layer when the carrier is partially or completely removed;
a third finishing layer formed on a top surface of a topmost external conductive trace layer when the carrier is partially or completely removed; and
a fourth finishing layer formed on a bottom surface of a bottommost external conductive trace layer when the carrier is partially or completely removed.

US Pat. No. 10,461,003

ELECTRONIC PACKAGE THAT INCLUDES MULTIPLE SUPPORTS

Intel Corporation, Santa...

1. An electronic package comprising:a substrate;
a die attached to the substrate, the die including an upper surface;
an underfill positioned between the die and the substrate;
a first support adjacent to the die and attached to the substrate; and
a second support mounted on the first support, the second support including an upper surface, wherein the second support is closer to the die than the first support, wherein the second support is thicker than the first support, wherein the upper surface of the die is aligned with the upper surface of the second support.

US Pat. No. 10,461,002

FABRICATION METHOD OF ELECTRONIC MODULE

Siliconware Precision Ind...

1. A method for fabricating an electronic module, comprising the steps of:providing a substrate having a plurality of electronic elements and a plurality of separation portions each formed between adjacent two of the electronic elements, wherein each of the electronic elements has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface;
disposing the substrate on a carrier, wherein the active surface of each of the electronic elements is disposed on the carrier;
after disposing the substrate on the carrier, removing each of the separation portions to form at least an opening in each of the separation portions, causing each of the electronic elements to have a side surface connecting the active and inactive surfaces thereof;
forming a strengthening layer in the openings of the separation portions and on the side surfaces of the electronic elements; and
singulating the electronic elements along the opening.

US Pat. No. 10,461,001

METHOD FOR MANUFACTURING HERMETIC SEALING LID MEMBER, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT HOUSING PACKAGE

HITACHI METALS, LTD., To...

1. A method for manufacturing a hermetic sealing lid member used for an electronic component housing package in which an electronic component is housed, comprising:forming a Ni plated metal plate by forming a Ni plated layer on a surface of a metal plate made of an alloy having a corrosion resistance comprising Fe and 1 mass % or more of Cr; and
forming the hermetic sealing lid member by punching the Ni plated metal plate.

US Pat. No. 10,461,000

SEMICONDUCTOR WAFER AND METHOD OF PROBE TESTING

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer;
providing a wafer holder including a tape portion with an opening through the tape portion;
mounting the semiconductor wafer over the opening in the tape portion of the wafer holder; and
providing an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test.

US Pat. No. 10,460,999

METROLOGY DEVICE AND METROLOGY METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A metrology device, comprising:a light source configured to provide an X-ray;
at least one lens configured to focus the X-ray to a wafer that has a periodic structure, the focused X-ray passing through the wafer and being diffracted by the wafer;
an image sensor configured to detect the diffracted X-ray;
a Fourier's transformer configured to conduct a Fourier's transform of the diffracted X-ray detected by the image sensor; and
a processor configured to identify at least one peak from the Fourier's transform and to analyze the at least one peak to obtain a distance between layers of a transistor structure of the wafer.

US Pat. No. 10,460,998

METHOD FOR INSPECTING SUBSTRATE, SUBSTRATE INSPECTION APPARATUS, EXPOSURE SYSTEM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Nikon Corporation, Tokyo...

1. A method for inspecting a substrate comprising:irradiating infrared light of a plurality of different wavelengths onto a first surface or a second surface opposite to the first surface, of the substrate in which a pattern having a periodicity and extending from the first surface to an inside of the substrate is formed in the first surface, each of the plurality of different wavelengths of the infrared light having a permeability to permeate the substrate to a respective predetermined depth;
detecting, with respect to each of the wavelengths, a diffracted light diffracted by the pattern of the substrate, or a polarization component of light transmitted through the substrate; and
inspecting the substrate up as far as the predetermined depths based on detection results of the wavelengths regarding the diffracted light diffracted by the pattern of the substrate, or the polarization component of the light transmitted through the substrate,
wherein at least one of an incidence angle of the infrared light with respect to the substrate and an exit angle of the diffracted light or the transmitted light with respect to the substrate is changed in accordance with the plurality of different wavelengths.

US Pat. No. 10,460,997

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of manufacturing a semiconductor device, comprising:providing a semiconductor substrate, wherein the semiconductor substrate comprises at least one fin structure;
forming a patterned mask layer on the fin structure, wherein the patterned mask layer comprises an opening corresponding to a part of the fin structure in a vertical direction;
performing an etching process with the patterned mask layer as a mask for forming a trench in the fin structure;
performing a pullback process to the patterned mask layer for enlarging the opening of the patterned mask layer; and
forming an isolation structure in the trench and the enlarged opening of the patterned mask layer.

US Pat. No. 10,460,996

FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a fin field effect transistor (FinFET), comprising:providing a plurality of discrete fins on a semiconductor substrate;
forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins;
forming an interlayer dielectric layer, covering the dummy gate and the fins;
forming an opening in the interlayer dielectric layer by removing the dummy gate;
forming a gate dielectric layer in the opening and on the interlayer dielectric layer;
forming a barrier layer on the gate dielectric layer;
removing a portion of the gate dielectric layer on the interlayer dielectric layer and a portion of the barrier layer on the interlayer dielectric layer;
performing an annealing treatment after removing the portion of the gate dielectric layer on the interlayer dielectric layer and the portion of the barrier layer on the interlayer dielectric layer;
removing a remaining portion of the barrier layer in the opening after performing the annealing treatment; and
forming a metal gate in the opening.

US Pat. No. 10,460,995

METHOD OF MANUFACTURE OF A FINFET DEVICE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:depositing a first dummy gate stack and a second dummy gate stack, wherein the first dummy gate stack has a first channel length and the second dummy gate stack has a second channel length different from the first channel length;
depositing an interlayer dielectric around the first dummy gate stack and the second dummy gate stack;
planarizing the first dummy gate stack, the second dummy gate stack and the interlayer dielectric;
after planarizing the first dummy gate stack, implanting ions into the interlayer dielectric to form an implanted region;
after implanting ions into the interlayer dielectric, removing the first dummy gate stack and the second dummy gate stack to form a first opening and a second opening, wherein the removing the first dummy gate stack and the second dummy gate stack reduces a height of the interlayer dielectric; and
filling the first opening and the second opening with a conductive material.

US Pat. No. 10,460,994

RESIDUE-FREE METAL GATE CUTTING FOR FIN-LIKE FIELD EFFECT TRANSISTOR

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:receiving an integrated circuit (IC) device structure that includes:
a substrate;
one or more fins disposed over the substrate;
a plurality of gate structures disposed over the one or more fins, wherein the plurality of gate structures traverses the one or more fins and includes first and second gate structures;
a dielectric layer disposed between and adjacent to the plurality of gate structures; and
a patterning layer disposed over the plurality of gate structures and the dielectric layer;
creating an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer between and adjacent to the first and second gate structures; and
removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer, wherein the removing of the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer includes performing an etching process, wherein the etching process includes a plurality of etching cycles for removing, in thickness increments, the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

US Pat. No. 10,460,993

FIN CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction;
a first isolation structure separating a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction, the first isolation structure having a width along the first direction, the first end of the first portion of the fin having a surface roughness;
a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the first direction; and
a second isolation structure over a second end of a first portion of the fin, the second end opposite the first end, the second isolation structure having the width along the first direction, and the second end of the first portion of the fin having a surface roughness less than the surface roughness of the first end of the first portion of the fin, wherein a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the first direction.

US Pat. No. 10,460,992

HIGH FREQUENCY ATTENUATOR

THIN FILM TECHNOLOGY CORP...

1. A passive, high frequency attenuator comprising:a substrate comprising a substrate material having a first side and a second side, the second side being opposite the first;
a first portion coupled to the first side of the substrate, the first portion comprising:
an input contact section;
an output contact section; and
a ground section;
a second portion coupled to the second side of the substrate, the second portion comprising:
a first ground section positioned along a first edge of the second side of the substrate;
a second ground section positioned along a second edge of the second side of the substrate, the second edge being opposite the first edge; and
an attenuation section positioned between the first and second ground sections, the attenuation section comprising:
an input section;
an output section; and
a plurality of resistive sections positioned between the input section, the output section, and the first ground section; and
a plurality of through-holes extending through the substrate and providing electrical communication between the first side of the substrate and the second side of the substrate; and wherein
the input contact section of the first portion is in electrical communication with the input section of the attenuation section of the second portion;
the output contact section of the first portion is in electrical communication with the output section of the attenuation section of the second portion; and
the ground section of the first portion is in electrical communication with the first ground section of the second portion and the second ground section of the second portion.

US Pat. No. 10,460,991

RESIN PACKAGE SUBSTRATE PROCESSING METHOD

DISCO CORPORATION, Tokyo...

1. A resin package substrate processing method for processing a resin package substrate including a mold resin in which a filler having a plurality of filler particles is mixed, said resin package substrate processing method comprising:a fixing step of fixing said resin package substrate through an expandable adhesive tape to an annular frame having an inside opening in the condition where said resin package substrate is positioned in said inside opening of said annular frame;
a dividing step of applying a laser beam having an absorption wavelength to said mold resin of said resin package substrate, to said mold resin after performing said fixing step, thereby forming a plurality of division grooves and dividing said resin package substrate into a plurality of chips;
an interchip distance increasing step of expanding said adhesive tape after performing said dividing step, thereby increasing the distance between any adjacent ones of said chips to a distance greater than or equal to a maximum diameter of said filler particles caught between said adjacent chips; and
a cleaning step of supplying a cleaning liquid to said resin package substrate after performing said interchip distance increasing step, thereby removing said filler particles caught between said adjacent chips,
whereby when each chip is picked up from said adhesive tape, falling of said filler particles from each chip is prevented.

US Pat. No. 10,460,990

SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE

INTERNATIONAL BUSINESS MA...

12. A semiconductor device comprising:a first conductive line including a first conductive material;
a second conductive line including a second conductive material;
a via including opposing tapered sidewalls each having a lower end contacting the first conductive material and an upper end contact the second conductive material, a distance between the lower end of the tapered sidewalls being less than a distance between the upper end of tapered sidewalls, the via connecting the first conductive line and the second conductive line, wherein the via includes a via material disposed between the tapered sidewalls such that the via material includes a via material top surface extending between the upper end of the tapered sidewalls and a via material bottom surface, wherein the via material bottom surface has a first contact area extending between the lower end of the tapered sidewalls that is in direct physical contact with the first conductive line, wherein the via material top surface is convex and has a second contact area that is greater than the first contact area;
a first liner material coating inner surfaces of the via side walls; and
a second liner material coating the via material top surface,
wherein the via material top surface directly contacts a bottom surface of the second liner material.

US Pat. No. 10,460,989

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a semiconductor substrate on which the semiconductor element is mounted, the substrate having a main surface;
a conductive layer formed on the substrate; and
a sealing resin covering the semiconductor element,
wherein the substrate is formed with a recess receding from the main surface, the recess including a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to a thickness direction of the substrate,
the conductive layer includes first conduction paths on the first sloped surface, second conduction paths on the second sloped surface and bottom conduction paths on the bottom surface,
the second sloped surface includes a plurality of regions that are line-symmetrical to the first conduction paths with respect to an imaginary line parallel to a second direction perpendicular to both the thickness direction of the substrate and the first direction, and the plurality of regions are without the second conduction paths,
each of the bottom conduction paths includes a portion extending parallel to the second direction,
said portion extending parallel to the second direction is in physical contact with an intersection between the bottom surface and the first or second sloped surface, and
the semiconductor element is a Hall-effect element.

US Pat. No. 10,460,988

REMOVAL METHOD AND PROCESSING METHOD

Tokyo Electron Limited, ...

1. A removal method for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber, the removal method comprising process steps of: exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas; stopping introduction of the BCl3 gas and performing a purge process; exposing the plurality of types of metal oxide films and a plurality of types of metal films underneath the plurality of types of metal oxide films to a plasma generated by introducing an inert gas; and stopping introduction of the inert gas and performing the purge process; wherein the process steps are repeated a plurality of times; and wherein the process step of exposing the plurality of types of metal oxide films and the plurality of types of metal films underneath the plurality of types of metal oxide films to the plasma includes performing a first process step of exposing the plurality of types of metal oxide films to one plasma generated from a single gas of the inert gas, and a second process step of exposing the plurality of types of metal films to two different plasmas each generated from a single gas selected from a plurality of types of gases including the inert gas.

US Pat. No. 10,460,987

SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor package device, comprising:a semiconductor die; and
a first redistribution layer disposed over and electrically coupled to the semiconductor die, the first redistribution layer comprising:
a first conductive plate;
a second conductive plate disposed over the first conductive plate;
an insulating film between the first conductive plate and the second conductive plate and electrically isolating the first conductive plate from the second conductive plate; and
a first dielectric material being different from the insulating film and laterally surrounding the first conductive plate, the second conductive plate and the insulating film, the first conductive plate and the second conductive plate being configured as an antenna plane and a ground plane, respectively.

US Pat. No. 10,460,986

CAP STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:a gate structure composed of conductive gate material;
sidewall spacers on the gate structure, extending above the conductive gate material;
a first capping material directly on the conductive gate material and comprising a recessed portion between the sidewall spacers on the gate structure; and
a second capping material within the recessed portion of the first capping material and extending over and in direct contact with a top surface of the sidewall spacers on the gate structure.

US Pat. No. 10,460,985

ENHANCEMENT OF ISO-VIA RELIABILITY

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure comprising:a semiconductor base comprising a plurality of semiconductor devices;
a back end of the line wiring layer comprising:
a wiring line;
a cap layer on the wiring line;
a reliability enhancement material within the cap layer and on the wiring line;
an interlayer dielectric (ILD) layer on the cap layer and the reliability enhancement material;
a via extending through the ILD and the reliability enhancement material to communicate with the wiring line; and
a metal filling the via and in contact with the wiring line;
wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the reliability enhancement material has different physical properties than the cap layer.

US Pat. No. 10,460,984

METHOD FOR FABRICATING ELECTRODE AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for fabricating an electrode, comprising:forming an insulating layer over a first conductive layer, wherein the first conductive layer contains a metal element;
forming a mask layer over the insulating layer;
forming an opening in the insulating layer, wherein the opening is formed by etching the insulating layer using plasma and the mask layer as a mask;
performing plasma treatment on at least the opening, wherein the plasma treatment is performed in an atmosphere containing oxygen;
removing an oxide comprising the metal element formed in the opening; and
forming a second conductive layer in the opening,
wherein the oxide is removed by washing treatment using a liquid in the removing step,
wherein the washing treatment comprises three or more cycles of first to fourth steps,
wherein the first step is to supply water so that a washing bath overflows while bubbling the water in the washing bath with the use of a nitrogen gas,
wherein the second step is to drain the water from the washing bath while supplying water from a shower to the washing bath,
wherein the third step is to supply water in the washing bath, and
wherein the fourth step is to supply water so that the washing bath overflows while bubbling the water in the washing bath with the use of a nitrogen gas.

US Pat. No. 10,460,983

METHOD FOR MANUFACTURING A BONDED SOI WAFER

SHIN-ETSU HANDOTAI CO.,LT...

1. A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, comprising, in sequential order, the steps of:depositing a polycrystalline silicon layer on the bonding surface side of the base wafer,
polishing a surface of the polycrystalline silicon layer,
forming the insulator film on the bonding surface of the bond wafer,
forming an ion-implanted layer in the bond wafer,
bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and
thinning the bonded bond wafer by delaminating along the ion-implanted layer in the bond wafer to form an SOI layer; wherein,
as the base wafer, a silicon single crystal wafer having a resistivity of 100 ?·cm or more is used,
the step for depositing the polycrystalline silicon layer further comprises a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited,
the polycrystalline silicon layer is deposited by a method consisting of two growth stages, a first growth performed at a first temperature of 900° C. or more and 1010° C. or less, and a second growth performed at a second temperature of 1100° C. or more to deposit the polycrystalline silicon layer thicker than in the first growth,
deposition of the polycrystalline silicon layer is performed using trichlorosilane as a source gas at atmospheric pressure in the first growth and the second growth,
the oxide film is formed by wet cleaning,
the oxide film has a thickness of 0.3 nm or more and 10 nm or less, and
the polycrystalline silicon layer has a thickness of 2 ?m or more when the base wafer and the bond wafer are bonded.

US Pat. No. 10,460,982

FORMATION OF SEMICONDUCTOR DEVICES WITH DUAL TRENCH ISOLATIONS

International Business Ma...

1. A method for fabricating a semiconductor device with dual trench isolations, comprising:forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors;
forming a first shallow trench located between transistors within the first array and a second shallow trench located between transistors within the second array; and
forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

US Pat. No. 10,460,981

ARRAY OF GATED DEVICES AND METHODS OF FORMING AN ARRAY OF GATED DEVICES

Micron Technology, Inc., ...

1. An array of gated devices, comprising:rows and columns comprising a plurality of gated devices individually comprising an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region, individual of the inner regions comprising one of a plurality of pillars, the one pillar being spaced from others of the pillars of other inner regions in a horizontal cross section;
a plurality of access lines that individually are laterally proximate the mid regions along individual of the rows;
a plurality of data/sense lines that individually are elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns;
metal circumferentially surrounding, directly against, and electrically coupled to sidewalls of the inner regions of the pillars; the metal being electrically isolated from the data/sense lines; and
the inner regions being electrically coupled to one another elevationally inward of the metal, thereby being electrically coupled to one another by other than, and/or not solely by, the metal that is directly against the sidewalls of the inner regions of the pillars.

US Pat. No. 10,460,980

SEMICONDUCTOR DEVICE COMPRISING A DEEP TRENCH ISOLATION STRUCTURE AND A TRAP RICH ISOLATION STRUCTURE IN A SUBSTRATE AND A METHOD OF MAKING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a metal-oxide semiconductor (MOS) transistor on a substrate;
a deep trench isolation structure in the substrate and around the MOS transistor, wherein the deep trench isolation structure comprises a liner in the substrate and an insulating layer on the liner, wherein the liner comprises silicon oxide and the insulating layer comprises undoped polysilicon or silicon nitride; and
a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure, wherein the deep trench isolation structure and the trap rich isolation structure comprise different materials and a number of layers in the trap rich isolation structure is less than a number of layers in the deep trench isolation structure, wherein the trap rich isolation structure comprises undoped polysilicon and the undoped polysilicon of the trap rich isolation structure is in direct contact with the substrate.

US Pat. No. 10,460,979

SEMICONDUCTOR STRUCTURE CAPABLE OF IMPROVING ROW HAMMER EFFECT IN DYNAMIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor structure, comprising:providing a semiconductor substrate having a first conductivity type;
forming at least one active area on the semiconductor substrate, wherein a major axis of the active area extends along a first direction;
performing a first oblique ion implantation process to form a first doped region having a second conductivity type above a first depth on an end surface of the active area;
performing a second oblique ion implantation process to form a second doped region having a third conductivity type above a second depth on the end surface of the active area, wherein the third conductivity type and the second conductivity types are opposite to each other, so that a localized doped region having the second conductivity type is formed between the first depth and the second depth; and
forming a trench isolation structure around the active area and adjacent to the end surface of the active area.

US Pat. No. 10,460,978

BOLTLESS SUBSTRATE SUPPORT ASSEMBLY

LAM RESEARCH CORPORATION,...

1. A substrate support, comprising:a conductive baseplate arranged to support a ceramic layer, the conductive baseplate including a first cavity extending along an axis perpendicular to a horizontal plane defined by the conductive baseplate; and
a coupling assembly arranged within the first cavity, the coupling assembly comprising
a gear arranged within the first cavity and configured to rotate about the axis, and
a pin arranged within the first cavity, the pin extending along the axis through the gear and into a second cavity below the conductive baseplate, wherein rotation of the gear causes the pin to move upward or downward relative to the conductive baseplate, and wherein the pin is retained within the second cavity when the gear is rotated to cause the pin to move downward into the second cavity, and wherein the pin does not extend to an upper surface of the conductive baseplate.

US Pat. No. 10,460,977

LIFT PIN HOLDER WITH SPRING RETENTION FOR SUBSTRATE PROCESSING SYSTEMS

LAM RESEARCH CORPORATION,...

1. A lift pin holder assembly, comprising:a lift pin holder including a central bore extending in a first direction, wherein the central bore defines a first groove arranged transverse to the first direction on a radially inner surface of the central bore,
wherein the lift pin holder is made of ceramic;
a lift pin received in the central bore, extending in the first direction and including a second groove arranged transverse to the first direction on a radially outer surface thereof; and
a spring at least partially arranged in the first groove of the lift pin holder and the second groove of the lift pin to retain the lift pin in the central bore of the lift pin holder.

US Pat. No. 10,460,976

SUBSTRATE TRANSFER DEVICE AND SUBSTRATE TRANSFER METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate transfer device, comprising:at least one first supporting portion and at least one second supporting portion configured to support a substrate from below the substrate;
an elevating mechanism configured to elevate the at least one second supporting portion up and down between a first position higher than a height of the at least one first supporting portion, which is maintained fixed, and a second position lower than the height of the at least one first supporting portion;
a control unit configured to control the elevating mechanism; and
a detecting unit configured to detect an external surface of the at least one second supporting portion,
wherein the control unit determines whether the at least one second supporting portion is in a required elevation state based on a detection result of the detecting unit,
the detecting unit includes a light projecting unit configured to irradiate light, and a light receiving unit configured to receive the light irradiated from the light projecting unit, and
the control unit controls the detecting unit to overlap an optical axis of the light with the at least one second supporting portion.

US Pat. No. 10,460,975

VACUUM CHUCK, BEVELING/POLISHING DEVICE, AND SILICON WAFER BEVELING/POLISHING METHOD

SUMCO CORPORATION, Tokyo...

1. A vacuum chuck comprising:a vacuum chuck stage comprising a circular vacuum surface;
a vacuum protection pad provided to the vacuum surface;
an annular or arc-shaped concave portion dividing the vacuum surface into a central region located closer to a center of the vacuum surface and an outer circumferential region located on an outer circumferential side; and
radially-extending concave portions formed in the central region, wherein
the vacuum protection pad has through holes in communication with the radially-extending concave portions, and
the vacuum protection pad is bonded to the vacuum surface at the central region excluding the radially-extending concave portions and is unbonded to the vacuum surface in the outer circumferential region.