US Pat. No. 10,431,431

GAS SUPPLY DELIVERY ARRANGEMENT INCLUDING A GAS SPLITTER FOR TUNABLE GAS FLOW CONTROL

LAM RESEARCH CORPORATION,...

1. A gas supply delivery arrangement for supplying process gas to a chamber of a plasma processing system wherein a semiconductor substrate is processed with gases introduced through at least first, second, and third gas injection zones, comprising:a plurality of process gas supply inlets and a plurality of tuning gas inlets; a mixing manifold comprising a plurality of gas supply sticks each of which is adapted to provide fluid communication with a respective process gas supply;
a plurality of tuning gas sticks each of which is adapted to provide fluid communication with a respective tuning gas supply;
a first gas outlet adapted to deliver gas to the first gas injection zone, a second gas outlet adapted to deliver gas to the second gas injection zone, and a third gas outlet adapted to deliver gas to the third gas injection zone;
a gas splitter in fluid communication with the mixing manifold, the gas splitter including a first valve arrangement which splits mixed gas exiting the mixing manifold into:
a first mixed gas which can be supplied to the first gas outlet; and
a second mixed gas which can at different times be supplied to:
only the second gas outlet;
only the third gas outlet; and
the second and third gas outlets; and
a second valve arrangement which, at different times, selectively delivers tuning gas from the tuning gas sticks to:
only the first gas outlet;
only the second gas outlet;
only the third gas outlet;
only the first and second gas outlets;
only the first and third gas outlets;
only the second and third gas outlets; and
the first, second, and third gas outlets.

US Pat. No. 10,431,430

PLASMA TREATMENT OF AN ELASTOMERIC MATERIAL FOR ADHESION

NIKE, Inc., Beaverton, O...

1. A plasma treatment system, the plasma treatment system comprising:a first plasma torch;
a first multi-axis conveyance mechanism coupled with the first plasma torch, the first multi-axis conveyance mechanism able to position the first plasma torch within a 20-40 millimeter offset height range from a surface of an elastomeric component;
a component identification mechanism; and
computer readable media having instructions embodied thereon that when executed by a processor:
generate a tool path for the first multi-axis conveyance mechanism based on an input from the component identification mechanism; and
control the first plasma torch and the first multi-axis conveyance mechanism to apply plasma to the surface while maintaining the 20-40 millimeter offset height range to form an altered region extending from the surface into the elastomeric component.

US Pat. No. 10,431,428

SYSTEM FOR PROVIDING VARIABLE CAPACITANCE

RENO TECHNOLOGIES, INC.

21. A semiconductor processing tool comprising:a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising:
an RF input configured to be operably coupled to an RF source;
an RF output operably coupled to the plasma chamber, the plasma chamber having a variable impedance;
electronically variable capacitors (EVCs) each comprising discrete capacitors operably coupled in parallel, the discrete capacitors comprising:
fine capacitors each having a capacitance value substantially similar to a fine capacitance value; and
coarse capacitors each having a capacitance value substantially similar to a coarse capacitance value, the coarse capacitance value being greater than the fine capacitance value;
wherein each EVC has a variable total capacitance that is increased when the discrete capacitors are switched in and decreased when the discrete capacitors are switched out; and
a control circuit operably coupled to the EVCs, the control circuit configured to determine the variable impedance of the plasma chamber;
the control circuit further configured to:
determine, based on the determined variable impedance, a total number of coarse capacitors of the coarse capacitors to have switched in;
determine, based on the determined variable impedance, a total number of fine capacitors of the fine capacitors to have switched in; and
cause an impedance match by causing the total number of coarse capacitors and the total number of fine capacitors to be switched in;
wherein the increase of the variable total capacitance of each EVC is achieved by switching in more of the coarse capacitors or more of the fine capacitors than are already switched in without switching out a coarse capacitor that is already switched in.

US Pat. No. 10,431,426

GAS PLENUM ARRANGEMENT FOR IMPROVING ETCH NON-UNIFORMITY IN TRANSFORMER-COUPLED PLASMA SYSTEMS

LAM RESEARCH CORPORATION,...

1. A gas plenum arrangement for a substrate processing system, the gas plenum arrangement comprising:a gas plenum body having an inner opening and an outer edge, wherein
the gas plenum body is arranged to define a gas plenum between a coil and a processing chamber, and
the coil is arranged around and outside of the outer edge of the gas plenum body; and
a plurality of discrete flux attenuating portions, wherein
the plurality of discrete flux attenuating portions is arranged outside of the outer edge of the gas plenum body and extends radially outward from the outer edge of the gas plenum body, and
the plurality of discrete flux attenuating portions (i) overlaps, in a vertical direction, some angular portions of the coil outside of the outer edge of the gas plenum body and (ii) does not overlap, in the vertical direction, other angular portions of the coil outside of the outer edge of the gas plenum body.

US Pat. No. 10,431,425

POLY-PHASED INDUCTIVELY COUPLED PLASMA SOURCE

Tokyo Electron Limited, ...

1. A system for plasma processing comprising:a metal source configured to supply a metal for ionized physical vapor deposition on a substrate in a process chamber;
a high-density plasma source configured to generate a dense plasma, the high-density plasma source comprising a plurality of individual inductively coupled antennas arranged in a pattern around an axis in the process chamber;
a substrate bias source configured to provide a potential necessary to thermalize and further ionize the plasma;
the high density plasma source including a control system and matching network coupled with the plurality of antennas and configured to deliver power to each individual antenna at an individual phase orientation determined according to a phase arrangement;
the high density plasma source further configured, according to the phase arrangement, for dynamically varying the delivery of power and phase orientation over time to each individual antenna in the process chamber according to a phase pattern to dynamically vary the radiation pattern delivered to the plasma, and for delivering power, in the phase pattern, to a first group of antennas at a synchronized phase at a first time period, and then for sequentially delivering power to other different groups of the antennas at a synchronized phase progressively in the process chamber at further sequential time periods following the first time period for consistent plasma processing.

US Pat. No. 10,431,424

PARASITIC CAPACITANCE COMPENSATION CIRCUIT

RENO TECHNOLOGIES INC.

7. A semiconductor processing tool comprising:a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising:
an RF input configured to be operably coupled to an RF source;
an RF output operably coupled to the plasma chamber; and
an electronically variable capacitor (EVC), the EVC comprising discrete capacitors, each discrete capacitor having a corresponding switch for switching in and out the discrete capacitor, each corresponding switch comprising a parasitic capacitance compensation circuit comprising:
a first inductor operably coupled between a first terminal and a second terminal of the corresponding switch, the first inductor causing a first inductance between the first and second terminals, the first and second terminals configured to be operably coupled, respectively, to first and second terminals of the switch; and
a second inductor operably coupled between the first and second terminals and parallel to the first inductor, the second inductor causing a second inductance between the first and second terminals of the switch when the second inductor is switched in, the second inductor being switched in when a peak voltage on the first and second terminals falls below a first voltage;
wherein the first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage; and
wherein the first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

US Pat. No. 10,431,423

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

Taiwan Semiconductor Manu...

1. A method of semiconductor device fabrication, comprising:identifying a first template having a first layout pattern with a first pattern density (PD) and a second template having a second layout pattern with a second PD less than the first PD;
splitting the first template into a plurality of subset templates, wherein a first subset template has a first subset PD that is outside of a PD target, and wherein the second PD is outside of the PD target;
performing a PD uniformity (PDU) optimization to both the first subset template and the second template to make the first subset PD and the second PD satisfy the PD target; and
performing multiple individual electron beam (e-beam) lithography exposure processes with an e-beam lithography tool to a semiconductor substrate, using respective ones of the subset templates.

US Pat. No. 10,431,422

METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY

D2S, Inc., San Jose, CA ...

1. A system for fracturing or mask data preparation, the system comprising:a device configured to determine pattern exposure information that forms a reticle pattern on a resist-coated reticle with a charged particle beam writer;
wherein the reticle is to be used to form a wafer pattern on a substrate using optical lithography; and
wherein the device configured to determine calculates a sensitivity of the wafer pattern to changes in dimension of the reticle pattern.

US Pat. No. 10,431,421

APPARATUS AND TECHNIQUES FOR BEAM MAPPING IN ION BEAM SYSTEM

VARIAN SEMICONDUCTOR EQUI...

1. An apparatus for monitoring of an ion beam, comprising:a processor; and
a memory unit coupled to the processor, including a display routine, the display routine operative on the processor to manage monitoring of the ion beam, the display routine comprising:
a measurement processor to:
receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan, the fast scan comprising a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction;
receive position information from the detector, the position information comprising a plurality of detector locations, collected at a plurality of instances, wherein the plurality of spot beam profiles correspond to the plurality of detector locations;
determine a spot beam center position at the plurality of detector locations;
determine a difference between the spot beam center position and an ideal center position at a plurality of detector locations; and
send a signal to display the difference as a function of detector location.

US Pat. No. 10,431,419

SPARSE SAMPLING METHODS AND PROBE SYSTEMS FOR ANALYTICAL INSTRUMENTS

Battelle Memorial Institu...

1. A method for sparse sampling with an analytical probe, the method comprising:a) acquiring in a serial mode a plurality of contiguous measured values lying at positions along a scan path extending in a line toward a first direction and having random perturbations in a second direction, wherein the random perturbations are limited within a predetermined distance from the line; and
b) inpainting among the measured values and reconstructing a representation of actual information.

US Pat. No. 10,431,418

FOCUSING MAGNET AND CHARGED PARTICLE IRRADIATION APPARATUS

B DOT MEDICAL INC., Saku...

1. A focusing magnet comprising a coil pair arranged on both sides of a path of a charged particle beam, wherein:when a current is input, the coil pair is configured to generate an effective magnetic field region in which a magnetic field is oriented in a direction (z-axis) perpendicular to a traveling direction (x-axis) of a charged particle beam, where an axis perpendicular to the x-axis and z-axis is assumed to be a y-axis;
in an xy-plane,
a charged particle beam which has been deflected at a deflection angle ? with respect to the x-axis at a deflection point Q and incident on the effective magnetic field region is deflected by the effective magnetic field region, and irradiates an isocenter at an irradiation angle ? with respect to the x-axis,
an arbitrary point P2 on a boundary on an exit side of the charged particle beam of the effective magnetic field region is at an equal distance r1 from the isocenter,
a point P1 on a boundary on an incident side of the charged particle beam of the effective magnetic field region and the point P2 are on a radius r2 and an arc of a central angle (?+?), and
when a distance between the deflection point Q and the isocenter is L, a distance R between the deflection point Q and the point P1 satisfies the following relational equation (4):
R=?L2+r12?2L(r1 cos ?+r2 sin ?)  (4).

US Pat. No. 10,431,417

CHARGED PARTICLE BEAM DEVICE AND SAMPLE HOLDER

Hitachi High-Technologies...

1. A charged particle beam device comprising a charged particle source, a sample holder placed with a sample thereon, a charged particle beam optical system in which the sample is irradiated with a charged particle emitted from the charged particle source as a charged particle beam, a detector detecting a signal emitted from the sample, and a controller controlling each constituent element, whereinthe sample holder includes
a sample placement portion including a first top surface on which a counterbore part is formed and a rotational axis for rotating the first top surface horizontally, the counterbore part being aligned by being mounted with a sample supporting member having a pattern for alignment including a central marker and a pattern and an address marker for analyzing magnification and a rotation angle,
a sample base portion including an opening through which the sample placement portion is capable of moving vertically and a second top surface around the opening, and
a sample cover portion which has conductivity, includes a window through which the pattern for alignment of the sample supporting member is exposed, and is pressed down toward a direction of the second top surface of the sample base portion, so that a top surface of the sample supporting member placed on the sample placement portion and the second top surface are flush with each other.

US Pat. No. 10,431,416

OBSERVATION SUPPORT UNIT FOR CHARGED PARTICLE MICROSCOPE AND SAMPLE OBSERVATION METHOD USING SAME

HITACHI HIGH-TECHNOLOGIES...

1. An observation support device for observation by irradiating a sample disposed in a non-vacuum space separated by a diaphragm from an inner space of a charged particle optical lens barrel that generates a charged particle beam, with the charged particle beam, comprising:a cover comprising a main body portion which defines a hole portion that forms an observation region where the sample is observed,
wherein the observation support device is disposed directly between the sample and the diaphragm and is mounted on the sample.

US Pat. No. 10,431,414

COMPOSITE TARGET AND X-RAY TUBE WITH THE COMPOSITE TARGET

NanoRay Biotech Co., Ltd....

1. A composite target, being interacted with an electron to generate an X-ray, and an energy of the electron is capable of being changed by controlling a tube voltage at least, and the composite target comprising:a target body;
an interposing layer, connected with the target body; and
a protective layer, disposed at an upstream side of the composite target, and the protective layer facing the electron, a critical energy of electron sputtering of the protective layer is more than a critical energy of electron sputtering of the target body,
wherein the interposing layer moves a highest peak of an energy spectrum of the X-ray toward a high energy direction,
a low energy photon of the X-ray is filtered by the interposing layer, and the low energy photon of the X-ray is capable of being increased by increasing a thickness of the interposing layer,
as the tube voltage is enhanced, an amount of a high energy photon of the X-ray generated is increased.

US Pat. No. 10,431,413

X-RAY SOURCE AND SYSTEM COMPRISING AN X-RAY SOURCE

LIGHTLAB SWEDEN AB, Upps...

1. An x-ray source configured to provide an omnidirectional transmission of x-ray radiation, the x-ray source comprising:an anode;
a field emission cathode;
an evacuated chamber transparent to x-ray radiation, the anode and the field emission cathode being arranged inside of the evacuated envelope,
wherein the evacuated envelope is an extended tube shaped evacuated chamber having an essentially circular symmetry, the field emission cathode is arranged adjacently to an inside surface of the extended tube shaped evacuated chamber, and the anode is centrally arranged inside of the extended tube shaped evacuated chamber,
the field emission cathode surrounds the anode,
the field emission cathode comprises a plurality of ZnO nanostructures selected to be at least 1 micrometer,
the field emission cathode is substantially transparent to X-ray radiation and formed as a transmission cathode, and
the x-ray source is connected to a controllable high voltage source, electrons during operation of the x-ray source are accelerated from the field emission cathode in a direction towards the anode, and x-ray radiation is omnidirectionally irradiated from the anode towards and through the field emission cathode and out from the x-ray source.

US Pat. No. 10,431,412

COMPACT ION BEAM SOURCES FORMED AS MODULAR IONIZER

Massachusetts Institute o...

1. A compact ion beam source comprising:an electron beam unit, comprising:
a modular housing unit that is selectively impermeable to gasses including oxidizing gaseous molecules, the modular housing unit comprising:
a base portion; and
a membrane window made of a single monolayer two-dimensional material and selectively transmissive to electrons;
an electron beam source disposed in the modular housing unit, the electron beam source comprising:
at least one field emitter element disposed over the base portion, comprising:
a first end that is proximate to the base portion; and
a field emitter tip disposed proximate to a second end that is opposite to the first end; and
at least one gate electrode disposed proximate to the second end of the at least one field emitter element, to apply a potential difference proximate to the field emitter tip of the at least one field emitter elements, thereby extracting electrons from the at least one field emitter tip to form an electron beam; and
at least one anode component disposed in the modular housing unit and configured to accelerate the electron beam in a path directed at the membrane window of the modular housing unit.

US Pat. No. 10,431,411

FUSE WITH A THERMOMECHANICAL COMPENSATION ELEMENT

PACIFIC ENGINEERING CORPO...

1. A melting fuse, especially for a motor vehicle that has a high-voltage circuit, said fuse comprising:an electrically insulating housing;
a fusible conductor inside the housing;
two contacts connected with each other by the fusible conductor,
wherein, between two longitudinal areas that are adjacent to each other, the fusible conductor has a rotation point around which the longitudinal areas are rotatable during thermo-mechanical expansion,
wherein the fusible conductor is bent uniformly and free of kinks so as to allow expansions of the fusible conductor caused by thermo-mechanical stresses to be converted into rotational movement,
wherein the fusible conductor is surrounded in the insulating housing by an arc suppressing means, and
wherein the fusible conductor is movable inside the arc suppressing means that surrounds it.

US Pat. No. 10,431,409

ELECTRICAL SWITCHING APPARATUS AND ACCESSORY WIRE RETENTION ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. An accessory wire retention assembly for an electrical switching apparatus, said electrical switching apparatus comprising a housing, separable contacts and an accessory enclosed by the housing, an operating mechanism for opening and closing said separable contacts, and a number of wires adapted to be electrically connected to said accessory, the housing including an interior, an exterior, and an aperture, said wires extending from the interior through said aperture to the exterior, said accessory wire retention assembly comprising:an insert structured to cooperate with the housing and to establish a predetermined position of said wires with respect to said accessory and said aperture; and
a fastening mechanism structured to fasten said wires to said insert to maintain said wires in said predetermined position,
wherein said insert is an elongated molded member comprising a number of molded features structured to cooperate with the housing, said wires, and said fastening mechanism, and
wherein said housing further includes a base and a cover coupled to said base; wherein said aperture extends through said base; and wherein said number of molded features includes a guide portion structured to cooperate with said base to accurately position said insert and said wires proximate said accessary and said aperture.

US Pat. No. 10,431,408

TEMPERATURE SENSITIVE SYSTEM

Tsinghua University, Bei...

5. A temperature sensitive system comprising: a power supply, a detector, a first electrode, a second electrode and an actuator; the power supply, the detector, the first electrode, the second electrode and the actuator are connected to form a loop circuit; wherein the loop circuit is in an on state or an off state, the state of the loop circuit is switched by a deformation of the actuator in response to a temperature change of the actuator; the detector is connected to the actuator in parallel or in series and shows a current change of the loop circuit; wherein the actuator is a free-standing composite structure comprising vanadium dioxide and a plurality of carbon nanotubes.

US Pat. No. 10,431,407

MEDIUM VOLTAGE CONTACTOR

ABB Schweiz AG, Baden (C...

1. A contactor comprising:an electric pole including:
a fixed contact and a movable contact, the movable contact being reversibly movable, along a displacement axis lying on a displacement plane, between a first position (A), at which said movable contact is decoupled from the fixed contact, and a second position (B), at which said movable contact is coupled with the fixed contact, and
a first plunger coupled with the movable contact, the first plunger extending along a main longitudinal axis parallel or coinciding with the displacement axis;
a movable armature coupled with the first plunger and reversibly movable, along a displacement direction parallel to the displacement axis of said movable contact, between a third position (C) and a fourth position (D);
an electromagnetic actuator comprising a magnetic yoke having a fixed yoke member and a movable yoke member, said fixed yoke member comprising a pair of through holes, said fixed yoke member and said movable yoke member being arranged respectively at a proximal position and a distal position with respect to said movable contact, said movable yoke member being reversibly movable, along a displacement direction parallel to the displacement axis of said movable contact, between a fifth position (E), at which the movable yoke member is decoupled from said fixed yoke member, and a sixth position (F), at which the movable yoke member is coupled with said fixed yoke member, said electromagnetic actuator further comprising a coil wound around said fixed yoke member and adapted to be fed by a coil current (IC) to make said fixed yoke member to magnetically interact with said movable yoke member and generate a force to move said movable yoke member from said fifth position (E) to said sixth position (F) or maintain said movable yoke member in said sixth position (F);
a pair of opening springs coupled with said fixed yoke member and said movable yoke member, said opening springs being adapted to provide a force to move said movable yoke member from said sixth position (F) to said fifth position (E), the pair of opening springs being symmetrically positioned with respect to a main symmetry plane, which is parallel to the displacement axis of said movable contact and perpendicular to the displacement plane of said movable contact; and
a pair of second plungers coupled with said movable yoke member and said movable armature, the pair of second plungers being symmetrically positioned with respect to the main symmetry plane of said contactor, each of said second plungers being inserted in a corresponding through hole and passing through said fixed yoke member.

US Pat. No. 10,431,406

PYROTECHNIC CIRCUIT BREAKER

AUTOLIV DEVELOPMENT AB, ...

1. A pyrotechnic circuit breaker comprising:a housing including a first housing part, a second housing part and at least one cutting chamber;
at least one electrical conductor to be sectioned traversing at least a part of the housing at a level of the at least one cutting chamber, the at least one electrical conductor including a molded-on insert moulded thereon;
at least one punch arranged in the housing facing the at least one cutting chamber and moveable between a first position and a second position, the at least one punch designed to section the at least one electrical conductor during movement of the at least one punch from the first to the second position; and
at least one pyrotechnical actuator for making the at least one punch pass from the first position to the second position when activated;
a seal for sealing the at least one cutting chamber, the seal disposed between the molded-on insert and one of the first housing part and the second housing part,
wherein the seal is compressed directly between the molded-on insert and the one of the first and second housing parts to confine gases in the at least one cutting chamber;
wherein the at least one electrical conductor is elongated in a direction of elongation and wherein the molded on insert surrounds the at least one electrical conductor at a first distinct zone and a second distinct zone, the first and second distinct zones spaced from one another in the direction of elongation.

US Pat. No. 10,431,405

SWITCHING DEVICE COMPRISING A VACUUM TUBE

SIEMENS AKTIENGESELLSCHAF...

1. A switching device comprising:a vacuum tube;
an adjustable drive configured to open and close contacts of the switching device; and
a sensor configured to detect a position of the switching device relative to a mounting location at which the switching device is mounted wherein the detected position is used to adjust the adjustable drive, to at least one of open and close the contacts, wherein the sensor for measuring the position of the switching device is configured to detect a change in an angular position of the switching device.

US Pat. No. 10,431,404

LINKAGE ASSEMBLY AND KEY SWITCH DEVICE HAVING THE SAME

SUNREX TECHNOLOGY CORP., ...

1. A linkage assembly for guiding movement of a key cap in an upright direction relative to a support board between a normal position, where the keycap is distal from the support board, and a pressed position, where the key cap is proximate to the support board, said linkage assembly comprising:a left modular linking member including
a pair of left arms which are spaced apart from each other in a front-to-rear direction, each of said left arms extending in a left-to-right direction and including
a left power segment configured for pivotally coupling with the key cap so as to move therewith in said upright direction,
a left weight segment disposed rightwardly of said left power segment, and having a first left sub-segment, and a second left sub-segment opposite to said first left sub-segment in said front-to-rear direction, and
a left fulcrum area which is disposed between said left weight segment and said left power segment, and which is configured for pivotally coupling to the support board about a first moving axis in said front-to-rear direction, such that in response to downward movement of the key cap from the normal position to the pressed position, said left weight segment is moved angularly and upwardly about the first moving axis, and such that in response to upward movement of the key cap from the pressed position to the normal position, said left weight segment is moved angularly and downwardly about the first moving axis, and
a left crosspiece extending in said front-to-rear direction to interconnect said left power segments of said left arms; and
a right modular linking member including
a pair of right arms which are spaced apart from each other in said front-to-rear direction, each of said right arms extending in said left-to-right direction and including
a right power segment configured for pivotally coupling to the key cap so as to move therewith in said upright direction,
a right weight segment disposed leftwardly of said right power segment, and having a first right sub-segment, and a second right sub-segment opposite to said first right sub-segment in said front-to-rear direction, and
a right fulcrum area which is disposed between said right weight segment and said right power segment, and which is configured for pivotally coupling to the support board about a second moving axis parallel to the first moving axis, such that in response to the downward movement of the key cap, said right weight segment is moved angularly and upwardly about the second moving axis, and such that in response to the upward movement of the key cap, said right weight segment is moved angularly and downwardly about the second moving axis, and
a right crosspiece extending in said front-to-rear direction to interconnect said right power segments of said right arms; and
a pair of synchronizing units which are configured to couple said left weight segments of said left arms respectively to said right weight segments of said right arms so as to synchronize movement of each of said left arms and a corresponding one of said right arms, each of said synchronizing units including
a left upper cavity which is formed in and extends from an upper surface of said first left sub-segment to terminate at a left upward abutment region,
a left lower cavity which is formed in and extends from a lower surface of said second left sub-segment to terminate at a left downward abutment region,
a right upper cavity which is formed in and extends from an upper surface of said first right sub-segment to terminate at a right upward abutment region confronting said left downward abutment region,
a right lower cavity which is formed in and extends from a lower surface of said second right sub-segment to terminate at a right downward abutment region confronting said left upward abutment region such that in response to the downward movement of the key cap, said left upward abutment region is brought into frictional engagement with said right downward abutment region to thereby retain the key cap in the pressed position, and such that in response to the upward movement of the key cap, said left downward abutment region is brought into frictional engagement with said right upward abutment region to thereby retain the key cap in the normal position.

US Pat. No. 10,431,403

REACTIVE FORCE GENERATION DEVICE

YAMAHA CORPORATION, Hama...

1. A reactive force generation device comprising:a to-be-depressed member including a base section, and a dome section formed of an elastic material and protruding from the base section, a sectional shape of the dome section orthogonal to an axis line of the dome section being substantially line-symmetric about a symmetry axis, the dome section having a three-dimensional shape that is substantially symmetric with respect to a virtual plane containing the symmetry axis and the axis line; and
an opposed member having an opposed surface opposed to a distal end of the dome section, the opposed member in a non-operated state being located remote from the to-be-depressed member,
at least one of the opposed member and the to-be-depressed member being constructed to make a swinging movement in response to a depressing operation applied thereto, wherein the opposed member relatively approaches the base section in response to the depressing operation, the dome section deforms by contact between the opposed surface and the distal end during the relative approaching, and the relative approaching is stopped in a depression-completed state corresponding to a maximum movable range of the opposed member relative to the base section,
the virtual plane being defined so as not to vary throughout an entire depression stroke from an initial state, where no depressing operation is applied yet, to the depression-completed state,
the to-be-depressed member and the opposed member being constructed in such a manner that, as for a variation amount of an angle of the axis line relative to a normal line of the opposed surface during the depression stroke, an acute-side angle defined between the axis line and the normal line of the opposed surface in the initial state falls in an angle range from a first variation amount of the angle of the axis line relative to the normal line during a transition from the initial state to a state where the distal end of the dome section starts contacting the opposed surface to a second variation amount of the angle of the axis line relative to the normal line during a transition from the initial state to the depression-completed state,
the first variation amount of the angle of the axis line relative to the normal line being greater than zero degree.

US Pat. No. 10,431,402

BUTTON SWITCH WITH ADJUSTABLE TACTILE FEEDBACK

DARFON ELECTRONICS CORP.,...

1. A button switch connected to a cap, the button switch comprising:a base having a pillar extending along a Z-axis, the Z-axis, an X-axis and a Y-axis being perpendicular to each other;
a cover disposed on the base;
a flexible acoustic member having a fixing rod and a flexible rod, the fixing rod being fixed to the base;
a sleeve rotatably jacketing the pillar to be movable upward and downward between a high position and a low position along the Z-axis, an upper end of the sleeve passing through the cover to be connected to the cap, the sleeve having an outer annular surface, the outer annular surface having a first convex portion, a first concave portion, a second convex portion, a second concave portion, and a protruding edge located between the second convex portion and the second concave portion;
an upward-force-applying member abutting against the sleeve and the base respectively for driving the sleeve to move away from the base; and
a resilient arm adjacent to the pillar, the resilient arm selectively abutting against the first convex portion at a first position or a second position with rotation of the sleeve on the pillar around the Z-axis when the sleeve is located at the high position, the resilient arm moving to a position corresponding to the first concave portion when the sleeve is located at the low position;
wherein when the sleeve rotates to make the resilient arm abut against the first convex portion at the first position, the protruding edge is misaligned with the flexible rod, and the sleeve receives an external force to move downward along the Z-axis, the flexible rod does not need to cross the protruding edge and the resilient arm moves from the first position to the position corresponding to the first concave portion with downward movement of the sleeve;
when the sleeve rotates to make the resilient arm abut against the first convex portion at the second position, the protruding edge is located above the flexible rod, and the sleeve receives the external force to move downward along the Z-axis, the flexible rod needs to cross the protruding edge and the resilient arm moves from the second position to a position corresponding to the second concave portion with downward movement of the sleeve;
when the sleeve moves downward along the Z-axis and deformation of the flexible rod caused by pressing of the protruding edge is not enough to make the flexible rod cross the protruding edge, the flexible rod deforms downward with the protruding edge;
when deformation of the flexible rod is enough to make the flexible rod cross the protruding edge, the flexible rod is released and then moves upward to collide with the cover for making a sound;
when the external force is released, the upward-force-applying member drives the sleeve to move upward relative to the pillar along the Z-axis for making the resilient arm abut against the first convex portion at the first position or the second position.

US Pat. No. 10,431,401

LOCK OUT/TAG OUT DEVICE HAVING A TIE-RECEIVING PASSAGEWAY

Brady Worldwide, Inc., M...

1. A device for temporarily restricting use of a control via at least one of lock out and tag out, the device comprising:a first portion having a passageway extending therethrough along a distance of passageway extension, the passageway being adapted for reception of a tie;
a second portion having a tang comprising an arm extending to a distal end having a projection, the arm being elastically flexible relative to a remainder of the second portion to accommodate a temporary deflection of the projection of the tang, the second portion being movable relative to the first portion to move the tang transversely across the passageway relative to the direction of passageway extension thereby toggling the device between an opened position in which the projection of the tang is on one side of the passageway and a closed position in which the projection of the tang is on the other side of the passageway; and
wherein a tie is receivable in the passageway and a reception of the tie in the passageway prevents the device from being moved from the closed position back into the opened position due to inability of the tang of the second portion to be moved past the tie in the passageway of the first portion.

US Pat. No. 10,431,400

PROGRAM SWITCH AND MODULAR PROGRAM SWITCH ARRANGEMENT FOR MOUNTING ON A PRINTED CIRCUIT BOARD AND METHOD FOR PRODUCING SUCH A PROGRAM SWITCH ARRANGEMENT

1. A program switch for forming a modular program switch arrangement and for mounting on a printed circuit board, the program switch comprising:a housing;
an insulator component with contact elements arranged thereon; and
a switching element movable between an on switching position and an off switching position and the switching element contacting the contact elements in the on switching position, wherein the housing has a first side wall and a second side wall and at least two connection elements are arranged on each side of the first side wall and the second side wall and spaced apart from each other for connection to adjacent program switches, wherein the at least two connection elements on each side wall are identical, wherein an inner side of the housing is embodied such that the insulator component is positioned in a defined manner in the housing such that the switching element is assigned unambiguously to the on switching position and the off switching position.

US Pat. No. 10,431,396

CHARGING RAM ASSEMBLY, AND PIN ASSEMBLY AND SECURING METHOD THEREFOR

EATON INTELLIGENT POWER L...

1. A pin assembly for a charging ram assembly of an electrical switching apparatus, said charging ram assembly comprising a biasing element, a ram member structured to bias said biasing element, and a plate member, said pin assembly comprising:a pin member structured to extend through said biasing element and said plate member, said pin member having a first end portion and a second end portion disposed opposite and distal from said first end portion;
a plurality of collar members comprising a first collar member and a second collar member each being coupled to said first end portion, each of said first collar member and said second collar member comprising a first disc-shaped portion, a second disc-shaped portion disposed opposite the first portion, and a third disc-shaped portion extending between the first portion and the second portion; and
a securing apparatus comprising a retaining member coupled to said first collar member and said second collar member in order to prevent said pin member from moving with respect to said first collar member and said second collar member,
wherein the first portion, the second portion, and the third portion each have a width; and
wherein the width of the third portion is less than the width of the first portion and the width of the second portion.

US Pat. No. 10,431,395

MULTI-FUNCTION CONTROLLER AND MOBILE DEVICE HAVING SAME

HON HAI PRECISION INDUSTR...

1. A multi-function controller comprising:a mounting member having a receiving hole defined therein;
a control member partially received in the receiving hole of the mounting member, and being capable of being pressed and rotated with respect to the mounting member;
a first switch located at an end of the mounting member;
a second switch disposed at a peripheral wall of the mounting member,
a third switch located spaced from the second switch and at the peripheral wall of the mounting member; and
a processing unit, the processing unit being electrically connected to the first switch, the second switch, and the third switch;
wherein the processing unit is configured for selectively receiving a first control signal from the first switch when the control member is pressed, receiving a second control signal from the second switch when the control member is rotated clockwise, or receiving a third control signal from the third switch when the control member is rotated counterclockwise, wherein the control member comprises a control tube received in the receiving hole of the mounting member and a control ring, the control tube comprises a conventional audio jack, an open end and a closed end, the control ring extends from the open end of the control tube.

US Pat. No. 10,431,393

DEFECT MITIGATION OF THIN-FILM HYBRID PEROVSKITE AND DIRECT WRITING ON A CURVED SURFACE

United States of America ...

1. A method for aerosol jet printing a layered perovskite structure, comprising:a) applying a PEDOT:PSS layer to a substrate;
b) applying a layer of lead iodide (PbI2) to the PEDOT:PSS layer; and
c) applying an aerosol mist of methylammonium iodide (CH3NH3I) atop the PbI2 layer with an aerosol-jet nozzle to form a CH3NH3PbI3 perovskite film layer.

US Pat. No. 10,431,392

ELECTRICAL STORAGE DEVICE, MANUFACTURING METHOD OF THE SAME, AND SEPARATOR

PANASONIC INTELLECTUAL PR...

1. An electrical storage device comprising:an electrical storage element including:
an anode body;
a cathode body facing the anode body; and
a separator including a separator substrate and a conductive polymer adhering to the separator substrate, and interposed between the anode body and the cathode body; and
an electrolytic solution with which the electrical storage element is impregnated, wherein:
the separator includes a first surface layer having a first surface facing the anode body, and a second surface layer having a second surface facing the cathode body,
the first surface layer includes a first region that is not provided with the conductive polymer,
the second surface layer includes a second region provided with the conductive polymer,
the first surface layer includes a third region provided with the conductive polymer, and
an area, of the third region in the first surface layer, facing the anode body is smaller than an area, of the second region in the second surface layer, facing the cathode body.

US Pat. No. 10,431,391

CAPACITOR PACKAGE STRUCTURE AND ANTI-OXIDATION ELECTRODE FOIL THEREOF

APAQ TECHNOLOGY CO., LTD....

1. An anti-oxidation electrode foil, comprising:a base material structure having a top surface and a bottom surface;
a first conductive material structure disposed on the top surface of the base material structure; and
a first carbonaceous material structure disposed on the first conductive material structure;
wherein one portion of the first conductive material structure is a first outermost layer for contacting the first carbonaceous material structure, the first outermost layer of the first conductive material structure is a first oxygen-containing metal compound layer formed by an oxidation process, and the first oxygen-containing metal compound layer is disposed between the other portion of the first conductive material structure and the first carbonaceous material structure so as to prevent oxygen from contacting the other portion of the first conductive material structure;
wherein, the first conductive material structure composed of a Ti layer, a TiNx layer formed on the Ti layer, and a TiNxCy layer (0?x?1) formed on the TiNx layer; the first conductive material structure is heated so as to transform the TiNxCy layer into a TiNxCyOz layer.

US Pat. No. 10,431,389

SOLID ELECTROLYTIC CAPACITOR FOR HIGH VOLTAGE ENVIRONMENTS

AVX Corporation, Fountai...

1. A method of forming a high voltage solid electrolytic capacitor element, the method comprising:subjecting a sintered anode pellet to a formation profile to form an anode, wherein the formation profile includes subjecting the pellet to an increasing current so that a target forming voltage is achieved in about 30 minutes or less; and
applying a solid electrolyte to the anode.

US Pat. No. 10,431,388

VOLTAGE TUNABLE MULTILAYER CAPACITOR

AVX Corporation, Fountai...

1. A tunable multilayer capacitor comprising:first active electrodes that are in electrical contact with a first active termination and alternating second active electrodes that are in electrical contact with a second active termination;
first DC bias electrodes that are in electrical contact with a first DC bias termination and alternating second DC bias electrodes that are in electrical contact with a second DC bias termination; and
a plurality of dielectric layers disposed between the alternating first and second active electrodes and between the alternating first and second bias electrodes, wherein at least a portion of the dielectric layers contain a tunable dielectric material that exhibits a variable dielectric constant upon the application of an applied voltage;
wherein the dielectric material has a voltage tunability coefficient of from about 10% to about 90%, wherein the voltage tunability coefficient is determined according to the following general equation:
T=100×(?0??V)/?0
wherein,
T is the voltage tunability coefficient;
?0 is the static dielectric constant of the material without an applied voltage;
and
?V is the variable dielectric constant of the material after application of an applied voltage (DC).

US Pat. No. 10,431,386

MULTILAYER ELECTRONIC COMPONENT INCLUDING A COMPOSITE BODY AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a main body including an active region in which a plurality of internal electrodes are stacked with respective dielectric layers interposed therebetween, and upper and lower cover regions disposed above and below the active region, respectively;
external electrodes disposed on external surfaces of the main body and electrically connected to the plurality of internal electrodes; and
a composite body disposed below the lower cover region of the main body and lower portions of the external electrodes,
wherein the composite body comprises a dielectric material having a same composition as that of a dielectric material contained in the lower cover region of the main body,
wherein the composite body further comprises a resin, and
wherein a content of the resin is at least 6 wt % based on 100 wt % of the dielectric material.

US Pat. No. 10,431,385

MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a pair of external electrodes;
a first internal electrode that contains a base metal and is coupled to one of the pair of external electrodes;
a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and the base metal, wherein a main component of the dielectric layer is the ceramic material; and
a second internal electrode that is stacked on the dielectric layer, contains the base metal, and is coupled to another one of the pair of external electrodes, wherein
a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, each of the five regions including the base metal, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, wherein abundance of Ba and Ti in each of the five regions is more than 90% as measured by measuring abundance of Ba atoms and Ti atoms by a transmission electron microscope,
an average grain size in the dielectric layer is 200 nm or less, and
the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain.

US Pat. No. 10,431,383

MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a pair of external electrodes;
a first internal electrode that contains a base metal and is coupled to one of the pair of external electrodes;
a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and the base metal, wherein a main component of the dielectric layer is the ceramic material; and
a second internal electrode that is stacked on the dielectric layer, contains the base metal, and is coupled to another one of the pair of external electrodes, wherein
a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, each of the five regions including the base material, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, wherein abundance of Ba and Ti in each of the five regions is more than 90% as measured by measuring abundance of Ba atoms and Ti atoms by a transmission electron microscope,
a thickness of the first internal electrode and a thickness of the second internal electrode are 0.2 ?m or greater, and
the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain.

US Pat. No. 10,431,382

PRINTED CIRCUIT BOARD ASSEMBLY HAVING A DAMPING LAYER

Apple Inc., Cupertino, C...

1. A printed circuit board assembly, comprising:a printed circuit board (PCB) having a first flexural modulus and a top surface;
a plurality of electronic components mounted on the top surface of the PCB;
a damping layer mounted on the top surface of the PCB, wherein the damping layer includes a continuous layer of viscoelastic material covering the plurality of electronic components, wherein the damping layer is attached to the top surface of the PCB at a plurality of locations around the plurality of electronic components, and wherein the damping layer includes a second flexural modulus lower than the first flexural modulus; and
an overmold layer mounted on the top surface of the PCB, wherein the overmold layer is a continuous layer of waterproof material covering the plurality of electronic components and the continuous layer of viscoelastic material, and wherein the overmold layer is in direct contact with the damping layer and is attached to the top surface of the PCB at a plurality of locations around the damping layer.

US Pat. No. 10,431,381

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body having a length and a width substantially equal to each other, and including dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces and the third and fourth surfaces and opposing each other;
a first external electrode disposed on the third surface of the capacitor body, a portion of the first external electrode extending to cover a portion of the fifth surface of the capacitor body; and
a second external electrode disposed on the fourth surface of the capacitor body, a portion of the second external electrode extending to cover a portion of the sixth surface of the capacitor body,
wherein each of the plurality of first internal electrodes has a first lead portion exposed to a first corner of the capacitor body in which the third and fifth surfaces of the capacitor body meet each other and covered with the first external electrode, such that adjacent edges of each of the plurality of first internal electrodes are spaced apart from the third and fifth surfaces of the capacitor body, respectively, by a substantially same distance, and
each of the plurality of second internal electrodes has a second lead portion exposed to a second corner of the capacitor body at which the fourth and sixth surfaces of the capacitor body meet each other and covered with the second external electrode, such that adjacent edges of each of the plurality of second internal electrodes are spaced apart from the fourth and sixth surfaces of the capacitor body, respectively, by a substantially same distance.

US Pat. No. 10,431,379

METHOD OF MANUFACTURING A MULTILAYER CERAMIC CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A method of manufacturing a multilayer ceramic capacitor, comprising:preparing a first ceramic green sheet on which a plurality of stripe-type first inner electrode patterns are formed to be spaced apart from one another by a predetermined distance and a second ceramic green sheet on which a plurality of stripe-type second inner electrode patterns are formed to be spaced apart from one another by a predetermined distance;
forming a ceramic green sheet laminate by alternately stacking the first ceramic green sheet and the second ceramic green sheet in such a manner that a central portion of each of the stripe-type first inner electrode patterns and a predetermined distance between the stripe-type second inner electrode patterns overlap with each other;
forming first and second groove portions on at least one of a top surface and a bottom surface of the ceramic green sheet laminate, wherein the first groove portions are formed at locations aligned, in a stacking direction of the ceramic green sheet laminate, with the predetermined distance formed between the stripe-type first inner electrode patterns formed on the first ceramic green sheet, and the second groove portions are formed at locations aligned, in the stacking direction of the ceramic green sheet laminate, with the predetermined distance formed between the stripe-type second inner electrode patterns formed on the second ceramic green sheet; and
cutting the ceramic green sheet laminate.

US Pat. No. 10,431,378

METHOD FOR MANUFACTURING ELECTRONIC COMPONENT WITH COIL

SUMIDA CORPORATION, (JP)...

1. A method for manufacturing an electronic component comprising:placing a T-shaped core and an air-core coil in a mold;
placing a mixture of a metal magnetic material and a thermosetting resin into the mold so as to embed the T-shaped core and the air-core coil in the mixture;
after placing the mixture, applying pressure in a range of 0.1 to 20.0 kg/cm2 to the placed mixture so that a shape of the placed mixture conforms to the T-shaped core, the air-core coil, and the mold; and
after applying the pressure, heating the mixture at a predetermined temperature for a predetermined time so that the placed mixture is hardened.

US Pat. No. 10,431,377

HIGH EFFICIENCY MAGNETIC COMPONENT

1. A magnetic air core apparatus, comprising:a first toroid formed of a plate like structure continuously wrapped in a helical shape having a substantially circular cross-section, and including an air core, the plate like structure having an outer peripheral surface and an inner peripheral surface, a width of each turn of the plate-like structure varies in width, and a gap between successive turns is straight, has a constant width, and is angled in a radial direction of the first toroid;
a second toroid substantially enveloping the first toroid in a concentric manner, the first and second toroids having a first air gap provided therebetween;
a start terminal connected to the first toroid; and
a return terminal connected to the second toroid, the start and return terminals enabling connection to other electrical devices,
wherein the second toroid includes at least one poloidal slot to enable access to the first toroid, and
the poloidal slot has a notch adjacent thereto to allow access to the start and return terminals.

US Pat. No. 10,431,376

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a primary coil wound around a primary spool;
a secondary coil wound around a secondary spool provided on an outer circumference side of the primary coil;
a center core disposed on an inner circumference side of the primary coil and the secondary coil;
an outer circumferential core disposed on the outer circumference side of the primary coil and the secondary coil;
an igniter provided on a front side of the center core in a coil axis direction which is a direction of an axis about which the primary coil and the secondary coil are wound;
a case which houses the primary coil, the secondary coil, the center core, the outer circumferential core, and the igniter;
a connector unit mounted on a front end of the case and including at least a signal terminal member for transmitting a switching signal to the igniter and a grounding terminal member for grounding the igniter; and
a relay member that electrically connects the outer circumferential core and the grounding terminal member, wherein
the connector unit includes an engagement wall that is engaged with the case and faces the igniter from front of the igniter in the coil axis direction,
the signal terminal member penetrates the engagement wall and includes an inner signal terminal projecting into the case,
the grounding terminal member penetrates the engagement wall and includes an inner grounding terminal projecting into the case,
the relay member includes a base portion provided along a rear surface of the engagement wall, a standing portion standing rearward of the base portion, and a curved portion that extends from a rear end of the standing portion in a vertical direction orthogonal to the coil axis direction and is curved to protrude rearward,
the base portion is in contact with the inner grounding terminal at one end in the vertical direction,
the standing portion is provided further outward than the igniter in a horizontal direction orthogonal to both the coil axis direction and the vertical direction, and
the curved portion is elastically deformed and is in pressure-contact with a front surface of the outer circumferential core.

US Pat. No. 10,431,374

MANUFACTURING METHOD OF A FILTER STRUCTURE

Guangdong MISUN Technolog...

1. A manufacturing method of a filter structure, the filter structure comprising:a box, having a cavity;
a plurality of coil components, installed in the cavity; and
a plurality of wiring components, each having a positive wiring pin and a negative wiring pin fixed to the box;
conductive wires coupled to both ends of each coil component being welded and fixed to the positive wiring pin and the negative wiring pin respectively, wherein the manufacturing method comprises the steps of:
(A) embedding a plurality of wiring components into both sides of the box respectively;
(B) installing a coil component into a chamber of a welding fixture, and latching the conductive wires at both ends of the coil component into a latch slot of the welding fixture tightly;
(C) installing a welding fixture to a top of the box, pressing the conductive wire by a protruding portion, so that the conductive wire is contacted with the positive wiring pin or the negative wiring pin;
(D) using a spot welding machine to sequentially weld the conductive wire and the positive wiring pin or the negative wiring pin; and
(E) packaging the filter structure.

US Pat. No. 10,431,373

COUPLED INDUCTOR

1. Coupled inductor havinga core and two windings,
wherein a first winding has a first and second terminal end and wherein a second winding had a third and fourth terminal end,
wherein the first to fourth terminal ends are arranged on a lower side of the core,
wherein each winding has an intermediate section extending through a through hole in the core,
wherein the two windings are designed at least in the intermediate section as flat stripes each having first and second side faces with a large width and third and fourth side faces having a small width compared to the width of the first and second side faces,
wherein the first side laces of both windings are arranged in the intermediate section perpendicular to the lower side of the core and wherein the two first side faces of the windings in the intermediate section face each other and/or abut each other in the intermediate section,
wherein the core has a front side surface and a backside surface, wherein the intermediate sections of the windings continuously extends from the front side surface to the back side surface of the core, and wherein the windings have sections arranged parallel to the front side surface and the back side surface of the core,
wherein the terminal ends are connected to the sections of the windings.

US Pat. No. 10,431,372

HIGH CURRENT, LOW EQUIVALENT SERIES RESISTANCE PRINTED CIRCUIT BOARD COIL FOR POWER TRANSFER APPLICATION

Futurewei Technologies, I...

1. A device, comprising:a housing; and
a wireless charging coil, the coil including a layered structure of electric conductors on a printed circuit board (PCB), wherein the layered structure comprises:
a first layer including a first electrically conductive trace comprising a first turn and a second turn adjacent to the first turn;
a second layer including a second electrically conductive trace comprising a third turn and a fourth turn adjacent to the third turn; and
a plurality of vias coupling the first layer and the second layer, wherein the plurality of the vias include a first via, a second via and a third via distributed separately along a length of the first turn, each of the first via, the second via and the third via electrically connecting the first turn and the third turn, wherein the plurality of the vias further include a fourth via, a fifth via and sixth via distributed separately along a length of the second turn, each of the fourth via, fifth via and sixth via connecting the second turn and the fourth turn, wherein thickness of the device is less than 1 centimeter.

US Pat. No. 10,431,370

ELECTRONICS SYSTEM AND METHOD OF FORMING SAME

SCHNEIDER ELECTRIC SOLAR ...

1. A heat-generating electrical component and base assembly configured to be secured to a component wall, the assembly comprising:a base including an upper portion having a recess and a lower portion having a floating electrical connector including a threaded element disposed within a retaining body including one or more flattened inner walls which prevent rotation of the threaded element within the retaining body and a ring lug that retains the threaded element within an internal volume of the retaining body;
a heat-generating electrical component secured in the recess of the base and including an electrical lead in electrical communication with the floating electrical connector; and
a gasket circumscribing a perimeter of the lower portion.

US Pat. No. 10,431,369

REACTOR

TAMURA CORPORATION, Toky...

1. A reactor comprising:a reactor body having a core; and
a case that is substantially rectangular and houses the reactor body; wherein
the reactor body has:
a resin member that covers a circumference of the core; and
no more and no less than three fixing portions for fixing the reactor body to the case, the three fixing portions being a first fixing portion, a second fixing portion and a third fixing portion,
the case has:
sidewalls that are flexible; and
mount portions that are provided on the sidewalls and are for mounting the fixing portions, and
the core is an annular core including:
two or more leg portions; and
a pair of yoke portions arranged at both end portions of the leg portions, each yoke portion having a bent portion,
the resin member includes a first joint portion that covers one of the pair of yoke portions,
the third fixing portion is provided at a central part of the first joint portion,
the reactor body is fixed to the case by the fixing portions being mounted on the mount portions, and
a clearance is formed between corners of the case and a portion of the first joint portion covering the bent portion of the one of the pair of yoke portions.

US Pat. No. 10,431,368

COIL ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a magnetic body,
wherein the magnetic body includes a substrate, and a coil part including patterned insulating films disposed on a surface of the substrate, a first coil shaped plating layer disposed between the patterned insulating films, and a second coil shaped plating layer disposed directly on the first plating layer, and
wherein a total thickness of the first and second coil shaped plating layers on the surface of the substrate exceeds a height of the patterned insulating films on the surface of the substrate,
wherein a width of a portion of the second coil shaped plating layer arranged outside an area between the patterned insulating films is less than or equal to a width of the area between the patterned insulating films.

US Pat. No. 10,431,367

METHOD FOR GAPPING AN EMBEDDED MAGNETIC DEVICE

Radial Electronics, Inc.,...

1. A method comprising:forming a feature on a substrate, the feature being a depression defining an inside surface;
disposing a first conductive pattern on the substrate and the inside surface of the feature;
disposing a permeability material on the inside surface of the feature and the first conductive pattern, the permeability material being a separate solid object placed within the feature;
disposing a substrate material on the substrate and the feature;
disposing a second conductive pattern on the substrate material, the second conductive pattern substantially matching the first conductive pattern to wrap the permeability material between the first conductive pattern and the second conductive pattern producing a winding type structure electrically coupling the first conductive pattern and the second conductive pattern in electrical connection to define at least one electrical circuit to facilitate a magnetic field in the permeability material; and
gapping the permeability material, after the permeability material has been disposed on the inside surface of the feature on the substrate, to remove at least a portion of the permeability material to produce a gap in the at least a portion of the permeability material.

US Pat. No. 10,431,366

NOISE FILTER

YAZAKI CORPORATION, Mina...

1. A noise filter used for a plurality of conducting members, the noise filter comprising,a ring-shaped core made from a magnetic material, the ring-shaped core being attached to the plurality of conducting members to reduce noise of currents flowing through each of the plurality of the conducting members,
the ring-shaped core including:
a base core having a plurality of support pillar portions extending outward in radial directions; and
a plurality of divisional cores each being placed between two of the plurality of the support pillar portions adjacent to each other in the circumferential direction, and each having two end surfaces connected to end portions of the two of the plurality of the support pillar portions,
the plurality of the divisional cores being configured to allow the plurality of the conducting members to be wound on the plurality of the divisional cores,
a magnetic path being formed between the end surface of each of the plurality of the divisional cores and the end portion of each of the plurality of the support pillar portions contacting the end surface,
the ring-shaped core being configured to form a common-mode magnetic path passing through all of the plurality of the divisional cores and all of the end portions of the plurality of the support pillar portions and normal-mode magnetic paths each passing through one of the plurality of the divisional cores and the two of the plurality of the support pillar portions connected to the one of the plurality of the divisional cores, the normal-mode magnetic paths being the same in number as the conducting members.

US Pat. No. 10,431,365

ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a main body made from a metal magnetic powder and an insulating resin;
a coating film covering the surface of the main body;
a conductor disposed inside the main body;
inorganic particles adhering to the surface of the coating film, the inorganic particles having an average particle diameter of 1 nm or more and 200 nm or less; and
outer electrodes which are electrically connected to the conductor and which cover portions of the surface of the coating film while inorganic particles adhere to the portions,
wherein the coating film contains a resin and metal cations.

US Pat. No. 10,431,364

ELECTRO-MECHANICAL DEVICE AND MANUFACTURING METHODS FOR VARIOUS APPLICATIONS

1. A single monolithic electromechanical device wherein;each single component of the device's electrical structure is staked alternately with magnetic material core segments and,
the entire device is also completely encapsulated by this magnetic material core material on the device's entire surface,
this encapsulation is done in a manner to totally suppress induced currents produced by the proximity effect.

US Pat. No. 10,431,363

PLUNGER FOR MAGNETIC LATCHING SOLENOID ACTUATOR

JOHNSON ELECTRIC INTERNAT...

1. A plunger for a magnetic latching solenoid actuator, the plunger comprising:an elongate plunger body; and
a plunger head at one end of the plunger body;
a first portion of the plunger body;
a second portion of the plunger body having a same transverse cross-section as a transverse cross-section of the first portion;
a magnet-interface body portion of the body portion between the first portion of the plunger body and the second portion of the plunger body which defines first and second planar surfaces on opposite lateral sides of the plunger body with a different transverse cross-section than the transverse cross-sections of the first and second portions of the plunger body.

US Pat. No. 10,431,362

VALVE ACTUATOR WITH ANTI-CORROSION COATING

Ademco Inc., Golden Vall...

1. A method for making a valve actuator for use in actuating a gas valve, the method comprising:winding an insulated copper wire around an interconnecting segment of a non-conductive support bobbin, with a ground terminal and an interconnect terminal being secured to the non-conductive support bobbin so as not to interfere with the winding of the insulated copper wire around the non-conductive support bobbin, wherein the non-conductive support bobbin includes a first flange, a second flange, and the interconnecting segment extending between and generally orthogonal to the first flange and the second flange, and wherein an arm of a magnetic flux concentration member extends through the interconnecting segment;
electrically connecting a first end portion of the insulated copper wire to the ground terminal;
electrically connecting a second end portion of the insulated copper wire to the interconnect terminal;
bending each of the ground terminal and the interconnect terminal inward over the wound insulated copper wire; and
applying an anti-corrosion coating to at least the wound insulated copper wire, wherein the valve actuator comprises an armature that has a valve seal that is configured to align with a valve seat of the gas valve, the armature is configured to be actuated by magnetic attraction to the magnetic flux concentration member when a current is applied through the wound insulated copper wire via the interconnect terminal and the ground terminal.

US Pat. No. 10,431,361

APPARATUSES AND METHODS FOR CANCELLATION OF INHOMOGENOUS MAGNETIC FIELDS INDUCED BY NON-BIOLOGICAL MATERIALS WITHIN A PATIENT'S MOUTH DURING MAGNETIC RESONANCE IMAGING

THE BOARD OF REGENTS OF T...

1. An apparatus comprising:an arch-shaped body configured to be worn outside of a user's mouth such that the arch-shaped body is configured to overlie a user's lips and follow a contour of at least some of the user's teeth;
where the arch-shaped body comprises one or more sidewalls coupled to a plurality of members comprising magnetically permeable material such that the magnetically permeable material overlies a user's teeth when the apparatus is worn by a user.

US Pat. No. 10,431,360

BALANCED MAGNETIC ARRAY

Apple Inc., Cupertino, C...

1. A consumer electronic device, comprising:a housing that carries a first array of magnetic elements that include a pinning magnet and first magnetic attachment elements, each of the first magnetic attachment elements is limited to forming a magnetic circuit with a corresponding second magnetic attachment element carried by an accessory device, and
wherein the pinning magnet has a length that alters a magnetic property of the magnetic circuits such that the magnetic circuits taken together have a net zero torque or a near net zero torque value, and a net non-zero attraction force.

US Pat. No. 10,431,359

METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET

JFE Steel Corporation, T...

1. A method for producing a grain-oriented electrical steel sheet comprising a series of steps of:heating a steel slab having a chemical composition comprising C: 0.04-0.12 mass %, Si: 1.5-5.0 mass %, Mn: 0.01-1.0 mass %, sol. Al: 0.010-0.040 mass %, N: 0.004-0.02 mass %, one or two of S and Se: 0.005-0.05 mass % in total and the remainder being Fe and inevitable impurities to not lower than 1250° C.,
hot rolling to obtain a hot rolled sheet having a thickness of not less than 1.8 mm,
subjecting the hot rolled sheet to a single cold rolling or two or more cold rollings including an intermediate annealing therebetween to obtain a cold rolled sheet having a final thickness of 0.15-0.20 mm, and
subjecting the cold rolled sheet to primary recrystallization annealing and further to final annealing,
wherein a content ratio of sol. Al to N in the steel slab (sol. Al/N) and a final thickness d (mm) satisfy the following formulas (1) and (2):
4d+1.52?sol. Al/N?4d+2.32  (1)
sol. Al/N?2.84  (2)
and the steel sheet in the heating process of the final annealing is held at a temperature of 775-875° C. for 40-200 hours and then heated in a temperature region of 875-1050° C. at a heating rate of 20-60° C./hr, and
wherein a region of 200-700° C. in the heating process of the primary recrystallization annealing is heated at a heating rate of not less than 50° C./s, while any temperature between 250-600° C. is held for 1-5 seconds.

US Pat. No. 10,431,358

RESISTOR PRODUCTION METHOD, RESISTOR, AND ELECTRONIC DEVICE

STANLEY ELECTRIC CO., LTD...

1. A method of manufacturing a resistor including (i) a substrate, and (ii) a resistive film provided on the substrate, wherein one portion or a whole of the resistive film is configured of a layer of sintered conductive nanosized particles with a particle diameter of less than 1 ?m, the method comprising:a first step of applying a solution wherein at least the conductive nanosized particles with a particle diameter of less than 1 ?m and an insulating material are dispersed, or a solution wherein at least the conductive nanosized particles covered with an insulating material layer are dispersed, in a desired form on a surface of the substrate, thereby forming a film;
a second step of irradiating one portion of the film with light in a predetermined pattern, and sintering the conductive nanosized particles with the light, thereby forming the resistive film, which is a conductive particle layer of the predetermined pattern;
a third step of measuring a resistance value of the resistive film; and
a fourth step of sintering the conductive nanosized particles by irradiating the film with light, thereby forming an additional resistive film, when the measured resistance value is greater than a range of a desired resistance value, and irradiating the resistive film with light, thereby trimming the resistive film, when the measured resistance value is smaller than the range of the desired resistance value.

US Pat. No. 10,431,357

VERTICALLY-CONSTRUCTED, TEMPERATURE-SENSING RESISTORS AND METHODS OF MAKING THE SAME

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material;
a first contact coupled to the first doped region;
a second contact opposite the first contact coupled to the second doped region; and
an isolation trench to circumscribe the third doped region.

US Pat. No. 10,431,356

MOLDED PART-EQUIPPED ELECTRICAL CABLE AND MOLDED PART-EQUIPPED ELECTRICAL CABLE MANUFACTURING METHOD

AutoNetworks Technologies...

1. A molded part-equipped electrical cable, comprising:a terminal-equipped electrical cable including an insulated electrical cable having a core and an insulation coating covering the periphery of the core and a terminal connected to an end part of the insulated electrical cable;
an adhesive provided on a surface of the insulation coating of the terminal-equipped electrical cable; and
a molded member covering from a part provided with the adhesive on the insulation coating of the terminal-equipped electrical cable to a connected part of the insulated electrical cable and the terminal,
wherein:
the molded member includes a first molded part and a second molded part separately molded;
the first molded part includes a part entirely covering the adhesive while being in contact with the adhesive;
the second molded part is present on the terminal side of the first molded part covering the adhesive in a longitudinal direction of the terminal-equipped electrical cable; and
the first molded part includes no part covering the terminal and the second molded part includes no part covering the insulation coating.

US Pat. No. 10,431,355

FEED-THROUGH ASSEMBLY FOR CONVEYANCE OF A FEED ELEMENT

United States of America ...

1. A feed-through assembly comprising,a) a lower compression member including an axially extending aperture extending between an inner, lower compression member surface and an outer, lower compression member surface;
b) an upper compression member including an axially extending aperture extending between an inner, upper compression member surface and an outer, upper compression member surface;
c) a packing stack including a plurality of packing buttons each including axially extending apertures, said packing stack has a lower packing button adjacent to said inner, lower compression member surface and an upper packing button adjacent to said inner, upper compression member surface, and wherein each of said packing buttons is made from expanded polytetrafluoroethylene (ePTFE) foam material; and
d) at least one feed element including a distal end and a proximal end, said at least one feed element extends through said apertures of each of said lower compression member, said packing stack including a plurality of packing buttons, and said upper compression member surface, said distal end of said at least one feed element is exposed to a first boundary environment and said proximal end is exposed to a second boundary environment.

US Pat. No. 10,431,354

METHODS FOR DIRECT PRODUCTION OF GRAPHENE ON DIELECTRIC SUBSTRATES, AND ASSOCIATED ARTICLES/DEVICES

Guardian Glass, LLC, Aub...

1. A method of making a coated article comprising a graphene-inclusive film on a substrate, the method comprising:disposing a metal-inclusive catalyst layer on the substrate;
exposing the substrate with the metal-inclusive catalyst layer thereon to a precursor gas and a strain-inducing gas at a temperature of no more than 900 degrees C., the strain-inducing gas inducing strain in the metal-inclusive catalyst layer; and
forming and/or allowing formation of graphene, from the precursor gas, both over and contacting the metal-inclusive catalyst layer, and between the substrate and the catalyst metal-inclusive catalyst layer, as facilitated by the strain induced in the metal-inclusive catalyst layer, in making the coated article.

US Pat. No. 10,431,353

METAL SHEATHED CABLE WITH JACKETED, CABLED CONDUCTOR SUBASSEMBLY

AFC Cable Systems, Inc., ...

1. A metal clad cable assembly, comprising:a core comprising a plurality of power conductors and a subassembly, each of the plurality of power conductors and the subassembly including an electrical conductor, a layer of insulation provided over the electrical conductor, and a jacket layer disposed directly atop the layer of insulation, wherein the layer of insulation and the jacket layer are different materials;
an assembly jacket layer disposed over the subassembly, wherein the jacket layer of each of the plurality of power conductors is provided directly adjacent an exterior of the assembly jacket layer such that no element is present between the assembly jacket layer and the jacket layer of each of the plurality of power conductors, and wherein the jacket layer of the subassembly is provided directly adjacent an interior of the assembly jacket layer such that no element is present between the assembly jacket layer and the jacket layer of the subassembly; and
a metal sheath disposed over the core.

US Pat. No. 10,431,352

CABLE AND METHOD FOR PRODUCING A CABLE

1. A cable comprising: at least one litz wire having twisted litz wire strands for conducting electrical current and an insulation sheath surrounding the at least one litz wire for electrical insulation of the at least one litz wire, where the cable has an interruption segment without insulation sheath disposed between two cable segments with insulation sheath, characterized in that the at least one litz wire is birdcaged in the interruption segment in order to interrupt the transport of moisture through the cable, in particular through the at least one litz wire due to capillary pressure and/or temperature-related pressure differences along the cable, and the interruption segment is not sealed so that a pressure equalization to the external environment takes place.

US Pat. No. 10,431,351

FLAT CABLE AND PRODUCTION METHOD THEREFOR

AUTONETWORKS TECHNOLOGIES...

1. A flat cable, comprising:a plurality of conductors respectively extending in an axial direction; and
an insulating sheath configured to, in a state where the conductors are lined up in a width direction orthogonal to the axial direction of the conductors, restrict the conductors from outside and collectively cover the conductors,
wherein the insulating sheath has an expander enabling bending in the width direction by permitting relative displacement between the conductors, and the expander, by expanding so as to partially separate from the conductors in at least a thickness direction orthogonal to both the width direction and the axial direction, forms an internal space permitting relative displacement such that adjacent conductors overlap in the thickness direction.

US Pat. No. 10,431,350

NON-CIRCULAR ELECTRICAL CABLE HAVING A REDUCED PULLING FORCE

Southwire Company, LLC, ...

1. A process for producing non-circular electrical cable, wherein the non-circular electrical cable comprises one or more conductors arranged in a non-circular arrangement and an exterior sheath comprising a first sheath layer and a second sheath layer, said process comprising steps for:advancing the one or more conductors through an extruder head;
extruding a first sheath layer comprising a plastic material around the one or more conductors, wherein the first sheath layer is initially extruded in a substantially circular shape having an inner surface and an exterior surface and at least a portion of the inner surface thereof is spaced from the one or more conductors;
extruding a second sheath layer comprising a nylon material around an exterior surface of the first sheath layer, wherein the second sheath layer has a different polymer composition than the first sheath layer;
applying a negative pressure to the interior surface of the first sheath layer, thereby pulling the first sheath layer and second sheath layer onto the one or more conductors and into a non-circular shape having a cross section substantially similar to the combined cross section of the one or more conductors; and
cooling the first and second sheath layers.

US Pat. No. 10,431,348

PRESSURE SENSOR INCLUDING ELECTRICAL CONDUCTORS COMPRISING ELECTROCONDUCTIVE RESIN COMPOSITION THAT DOES NOT NEED CROSS-LINKING

HITACHI METALS, LTD., To...

1. A pressure sensor, comprising:an insulator having a hollow portion; and
a plurality of electrical conductors that have been disposed apart from each other along the inner surface facing the hollow portion of the insulator,
wherein the insulator comprises an insulating resin composition made of a material which does not need cross-linking,
wherein the plurality of electrical conductors comprise an electroconductive resin composition made of a material which does not need cross-linking,
wherein the insulating resin composition and the electroconductive resin composition comprise a process oil, and a mass percentage concentration of the process oil in the electroconductive resin composition is higher than a mass percentage concentration of the process oil in the insulating resin composition.

US Pat. No. 10,431,346

RADIATION SHIELDING LIQUID FILTER, AND X-RAY IMAGING DEVICE PROVIDED WITH SAME

1. An X-ray imaging device with a radiation shielding liquid filter, the radiation shielding liquid filter having a function of shielding radiation emitted from an X-ray imaging device toward an operator to protect the operator from exposure to the radiation, the liquid filter comprising:a casing filled with a liquid material, the liquid material having a composition of: 10 to 30 parts by weight of silver (Ag) in powder form; 25 to 40 parts by weight of a polymeric dispersant; 45 to 50 parts by weight of water; and 1 to 5 parts by weight of at least one element selected from copper (Cu), aluminum (Al), and mercury (Hg),
the X-ray imaging device comprising: a radiation shielding unit, the radiation shielding unit including:
an attachment member having a hole formed through a central portion of the attachment member in a vertical direction, and a step formed along a circumference of the hole, the attachment member being provided on a distal end of a tube that is an X-ray generation part of the X-ray imaging device; and
a filter holding member having a hole formed through a central portion of the filter holding member in the vertical direction, and screw-coupled to the attachment member, the filter holding member holding the liquid filter seated in the attachment member, wherein
the liquid filter is seated on the step of the attachment member.

US Pat. No. 10,431,345

SMALL FORM FACTOR BETAVOLTAIC BATTERY FOR USE IN APPLICATIONS REQUIRING A VOLUMETRICALLY-SMALL POWER SOURCE

CITY LABS, INC., Homeste...

1. A betavoltaic power source comprising:a source of beta particles;
a plurality of regions each for collecting the beta particles and for generating electron hole pairs responsive thereto, a first set of the plurality of regions disposed proximate a first surface of the source and a second set of the plurality of regions disposed proximate a second surface, the first and second surface in opposing relation; and
a secondary power source charged by a current developed by the electron hole pairs.

US Pat. No. 10,431,344

ASSEMBLY WITH A TUBE LOCKING DEVICE, AND ASSOCIATED MAINTENANCE METHOD

AREVA NP, Courbevoie (FR...

1. An assembly comprising:a plurality of tubes having respective segments parallel to one another;
a locking device for locking the tubes in position relative to one another, the device including:
at least one first arm;
a locking axle having a plurality of bearing surfaces; and
a link connecting the locking axle to the first arm, the locking axle being movable relative to the first arm between a locking position, in which the segments of the tubes are each pinched between one of said bearing surfaces and the first arm, and a released position, in which the segments of the tubes are free relative to the first arm,
the bearing surfaces being depressions hollowed along the locking axle.

US Pat. No. 10,431,343

SYSTEM AND METHOD FOR INTERPRETING PATIENT RISK SCORE USING THE RISK SCORES AND MEDICAL EVENTS FROM EXISTING AND MATCHING PATIENTS

KONINKLIJKE PHILIPS N.V.,...

1. A computer-implemented method for determining a likelihood of occurrence of a medical event for a subject, the method comprising:acquiring a subject risk profile for the subject based upon measurement, by a physiological characteristic sensor, of physiological characteristics of the subject, wherein the subject risk profile comprises a time series of risk scores for the subject;
obtaining a plurality of other subject risk profiles for other subjects from a database, wherein the other subject risk profiles comprise a time series of risk scores for the other subjects;
comparing the acquired subject risk profile to the obtained plurality of other subject risk profiles;
selecting at least one risk profile from the obtained plurality of other subject risk profiles that most closely matches the acquired subject risk profile;
determining the likelihood of occurrence of the medical event for the subject based on the selected at least one risk profile; and
outputting a signal indicative of the determined likelihood of occurrence of the medical event for the subject.

US Pat. No. 10,431,342

TRACKING THE PROBABILITY FOR IMMINENT HYPOGLYCEMIA IN DIABETES FROM SELF-MONITORING BLOOD GLUCOSE (SMBG) DATA

University of Virginia Pa...

1. A method for maintaining the health of a diabetic patient by preventing the occurrence of a hypoglycemic event in said patient, comprising:obtaining self monitoring blood glucose (SMBG) readings from the patient;
measuring glycemic variability of said patient and low blood glucose (BG) of said patient based on said obtained SMBG readings;
creating in a processor a bivariate distribution that maps probability for an upcoming hypoglycemic event in said patient jointly to values of said measured glycemic variability and said measured low blood glucose (BG);
optimizing in said processor the bivariate distribution to achieve prediction of a predetermined percentage of hypoglycemic events below a predetermined BG value occurring in said patient within a predetermined future time period;
tracking in said processor the optimized distribution over time using routine SMBG readings from the patient;
outputting via said processor a message to said patient when said optimized distribution indicates a certain probability for the occurrence of a hypoglycemic event in said patient within said predetermined future time period, based on SMBG data obtained from said patient; and
causing said patient to take a physical action in response to receiving said message to prevent a hypoglycemic event from occurring in said patient.

US Pat. No. 10,431,341

DETECTION DEVICE, METHOD, AND PROGRAM FOR ASSISTING NETWORK ENTROPY-BASED DETECTION OF PRECURSOR TO STATE TRANSITION OF BIOLOGICAL OBJECT

Japan Science and Technol...

1. A detection device for detecting a pre-disease state comprising detecting a biomarker candidate that serves as an early-warning signal indicating the pre-disease state by detecting an index of a symptom of a biological object to be measured, based on measured data of a plurality of factors obtained by measurement on the biological object, said device comprising:selection means for selecting the factors based on time-dependent changes of measurement data of each of the factors;
microscopic calculation means for calculating microscopic entropy as understood in statistical mechanics between the factors selected by the selection means and neighboring factors thereof;
index detection means for detecting the index based on the microscopic entropy calculated by the microscopic calculation means;
precursor detection means for detecting a precursor to a state transition based on the index detected by the index detection means,
wherein the selection means selects the factors of which the measured data shows the time-dependent changes beyond a predetermined criterion,
wherein the microscopic calculation means calculates the microscopic entropy as understood in statistical mechanics between each of the factors selected by the selection means and every neighboring factor thereof,
wherein the precursor detection means detects the precursor to the state transition when the microscopic entropy calculated by the microscopic calculation means shows a decrease beyond a predetermined detection criterion,
choosing means for choosing, as a candidate for a biomarker, a factor for which the microscopic entropy calculated by the microscopic calculation means shows a decrease beyond a predetermined choosing criterion, the biomarker being the index of the symptom of the biological object,
wherein the precursor detection means detects the precursor to the state transition when the microscopic entropy for the factor chosen by the choosing means shows the decrease beyond the predetermined detection criterion; and
an acquisition unit configured to acquire the measurement data on the plurality of factors of the biological object to be measured.

US Pat. No. 10,431,340

SYSTEMS FOR PREDICTING HYPOGLYCEMIA AND METHODS OF USE THEREOF

Eco-Fusion, Ramat Gan (I...

1. A system, comprising:at least one user-wearable device, wherein the at least one user-wearable device is in contact with a skin of a user when the user wears the at least one user-wearable device, and wherein the at least one user-wearable device comprises at least one sensor configured to acquire physiological measurements for at least one hypoglycemia-related physiological characteristic of the user that is correlated with at least one of a blood insulin excess or a hypoglycemic blood glucose level;
wherein the at least one hypoglycemia-related physiological characteristic is chosen from beat-to-beat heart rate, heart rate variability, oxygen saturation, galvanic skin response, and any combination thereof;
a non-transient computer readable medium having hypoglycemia-predictive software;
at least one processor configured to execute the hypoglycemia-predictive software;
wherein, upon execution of the hypoglycemia-predictive software, the at least one processor is at least configured to:
receive, in real-time, user-specific data from a user, wherein the user-specific data comprises: food intake of the user, glucose readings of the user, medication intake by the user, user behavior data and at least one insulin dose taken by the user;
receive, in real-time, from the at least one user-wearable device, user-specific hypoglycemia-related physiological data, comprising at least one particular physiological measurement of the at least one hypoglycemia-related physiological characteristic of the user;
determine, in real-time, a hypoglycemic event of the user, based on the at least one particular physiological measurement of the at least one hypoglycemia-related physiological characteristic of the user and at least one chosen from:
1) a predicted user-specific value of the at least one hypoglycemia-related physiological characteristic, determined based on the user-specific data, and
2) an expected population-based value of the at least one hypoglycemia-related physiological characteristic, determined based on a population of individuals identified based on the user-specific data;
generate, in real-time, in response to the determination of the hypoglycemic event of the user, at least one alert, instructing the user to consume glucose-rich intake; and
output, in real-time, the at least one alert to at least one of: the user, at least one family member, at least one medical practitioner, or any combination thereof.

US Pat. No. 10,431,339

METHOD AND SYSTEM FOR DETERMINING RELEVANT PATIENT INFORMATION

EPIC Systems Corporation,...

1. A non-transitory computer-readable medium having stored thereon instructions executable by a processing system to cause the processing system to perform functions comprising:receiving data indicative of a patient identity of a patient and a current condition;
in response to receiving the data indicative of the patient identity and the current condition, transmitting a request for historical patient information, and wherein the historical patient information is received in response to the transmitted request;
dividing the historical patient information into a plurality of classifications, wherein at least one of the plurality of classifications is representative of a past diagnosis of the patient;
using a weighted graph unique to the patient to determine a weight between the past diagnosis and the current condition;
using the weight and an input value to determine a relevance score of the past diagnosis to the current condition;
determining a level of prominence with which to display the historical information based on the relevance score, wherein determining the level of prominence comprises comparing the relevance score to a plurality of thresholds, and wherein each threshold of the plurality of thresholds defines a different level of prominence for displaying the historical patient information; and
displaying the historical patient information on a graphical user interface in accordance with the determined level of prominence such that historical patient information satisfying a first threshold of the plurality of thresholds is displayed in a first manner and historical patient information satisfying a second threshold of the plurality of thresholds is displayed in a second manner.

US Pat. No. 10,431,338

SYSTEM AND METHOD FOR WEIGHTING MANAGEABLE PATIENT ATTRIBUTES DURING CRITERIA EVALUATIONS FOR TREATMENT

International Business Ma...

1. A computer-implemented method for evaluating attribute values to determine eligibility for a first treatment, the computer-implemented method comprising:responsive to receiving input regarding a first patient, determining a topic based on parsing the received input using natural language processing, the topic comprising a request to identify treatment protocols for which the first patient can be eligible, wherein the topic is determined by a question classifier component of an application and stored in a feature store;
determining, based on a corpus and by a pipeline execution component of the application, a set of required attributes associated with a treatment protocol associated with the first treatment, wherein the pipeline execution component reduces processing of sources in the corpus that do not pertain to the stored topic;
responsive to receiving a case, wherein the case includes a patient history containing patient attribute values for the first patient, identifying, by an attribute verification component of the application, a first patient attribute value that does not satisfy a first attribute specified by the treatment protocol as a required attribute;
determining that the first patient is not currently eligible to receive the first treatment, based on determining that the first patient attribute value does not satisfy the first attribute specified by the treatment protocol;
upon determining that the first patient is not currently eligible to receive the first treatment, determining, by operation of one or more computer processors and based on evaluating the patient history using one or more machine learning models, a likelihood that the patient will meet the first attribute in the future due to a change in the first patient attribute value, thereby determining potential eligibility of the first patient for the treatment protocol with a greater measure of accuracy than absent determining the likelihood, wherein the likelihood is determined based on an upward or downward trend of the first patient attribute value and based further on an extent by which the first patient attribute value differs from the required attribute; and
causing approval, based on the determined likelihood, of the first patient for receiving the treatment protocol, whereafter the treatment protocol is applied to the first patient, wherein absent determining the likelihood, the first patient would have been denied from receiving the treatment protocol.

US Pat. No. 10,431,337

SYSTEM AND METHOD FOR WEIGHTING MANAGEABLE PATIENT ATTRIBUTES DURING CRITERIA EVALUATIONS FOR TREATMENT

International Business Ma...

1. A system for evaluating attribute values to determine eligibility for a first treatment, the system comprising:one or more computer processors; and
a memory containing a program which, when executed by the one or more computer processors performs an operation comprising:
responsive to receiving input regarding a first patient, determining a topic based on parsing the received input using natural language processing, the topic comprising a request to identify treatment protocols for which the first patient can be eligible, wherein the topic is determined by a question classifier component of an application and stored in a feature store;
determining, based on a corpus and by a pipeline execution component of the application, a set of required attributes associated with a treatment protocol associated with the first treatment, wherein the pipeline execution component reduces processing of sources in the corpus that do not pertain to the stored topic;
responsive to receiving a case, wherein the case includes a patient history containing patient attribute values for the first patient, identifying, by an attribute verification component of the application, a first patient attribute value that does not satisfy a first attribute specified by the treatment protocol as a required attribute;
determining that the first patient is not currently eligible to receive the first treatment, based on determining that the first patient attribute value does not satisfy the first attribute specified by the treatment protocol;
upon determining that the first patient is not currently eligible to receive the first treatment, determining, based on evaluating the patient history using one or more machine learning models, a likelihood that the patient will meet the first attribute in the future due to a change in the first patient attribute value, thereby determining potential eligibility of the first patient for the treatment protocol with a greater measure of accuracy than absent determining the likelihood, wherein the likelihood is determined based on an upward or downward trend of the first patient attribute value and based further on an extent by which the first patient attribute value differs from the required attribute; and
causing approval, based on the determined likelihood, of the first patient for receiving the treatment protocol, whereafter the treatment protocol is applied to the first patient, wherein absent determining the likelihood, the first patient would have been denied from receiving the treatment protocol.

US Pat. No. 10,431,336

COMPUTERIZED SYSTEMS AND METHODS FOR FACILITATING CLINICAL DECISION MAKING

CERNER INNOVATION, INC., ...

1. A computerized method for determining treatment for a patient having congestive heart failure and at least one other medical condition, the method comprising:receiving, by one or more computer processing components, patient-results information for a patient from a patient information database, wherein the patient information database is remote from at least one of the one or more computer processing components;
extract, by the one or more computer processing components, discrete patient data from the patients-results information;
receiving, by the one or more computer processing components, one or more rules from a parameters database, wherein the parameters database is remote from the one or more computer processing components, and wherein the one or more rules comprise a rule relevant to the discrete patient data;
based on said discrete patient data and the one or more rules, determining, by a first processing component of the one or more computer processing components, whether said patient-results information suggests a trigger event;
upon a determination that said trigger event has occurred, determining by a second processing component of the one or more computer processing components, at least one goal based on said trigger event, wherein the at least one goal is communicated to the one or more computer processing components by the parameters database;
based on said goal, selecting, by the one or more computer processing components, a first plan, from a library of plans, corresponding to said determined goal, wherein the library of plans is communicated to the one or more computer processing components by the parameters database;
in response to selecting the first plan, receiving additional patient-results information specified by said plan, wherein the additional patient-results information is communicated to the one or more computer processing components by the patient information database; and
executing said first plan, wherein said execution comprises:
(1) from among a library of solvers, determining a first solver to determine patient conditions and recommended treatments, said first solver comprising a finite state machine;
(2) receiving first-solver parameters for said first solver, wherein said first solver is running on the one or more computer processing components;
(3) preparing patient-results information for said first solver;
(4) instantiating said first solver based on said prepared patient-results information and said first-solver parameters;
(5) applying said first solver to determine said patient conditions and recommended treatments, each patient condition comprising an evaluated state for the patient condition;
(6) determining that a second solver is needed to assist said first solver to determine patient conditions and recommended treatments, wherein the second solver is running on the one or more computer processing components;
(7) invoking the second solver to assist said first solver to determine patient conditions and recommended treatments, said second solver comprising a mixed-integer linear solver, said second solver being invoked by the first solver;
(8) communicating the evaluated states for the determined said patient conditions from the first solver to the second solver;
(9) preparing patient-results information for said second solver;
(10) instantiating said second solver based on said prepared patient-results information and said evaluated states;
(11) based on said determined patient conditions and recommended treatments, communicating actions and dispositions specific to said patient from the one or more computer processing components to a second computer processing component, wherein the second computer processing component is remote from the one or more computer processing components; and
(12) displaying the communicated actions and dispositions specific to said patient on a user interface of the second computer processing component.

US Pat. No. 10,431,335

MOBILE APPLICATIONS FOR MEDICAL DEVICES

Fenwal, Inc., Lake Zuric...

16. A computer-implemented method for medical device management using a handheld mobile device, said method comprising:providing, via a handheld mobile device graphical user interface, a representation of one or more medical devices, the medical devices comprising at least one of a blood processing device, an infusion pump, and a drug delivery device, with a visual indication of a status for each medical device, the representation visually conveying information regarding each of the one or more medical devices and selectable by a user to provide additional information regarding each of the one or more medical devices;
updating the status for each medical device via wireless communication with the handheld mobile device;
receiving an indication of an alarm code at the handheld mobile device, the alarm code representing an alarm or error condition of one or more of the medical devices;
providing information at the handheld mobile device to assist a user in handling the alarm or error condition of the one or more of medical devices; and
displaying an inventory of available products for the one or more medical devices at a healthcare facility and facilitating inventory control via the mobile device.

US Pat. No. 10,431,334

PERFORMING AN APHERESIS PROCEDURE ON A HUMAN SUBJECT WITH IDENTITY CONFIRMATION

Fenwal, Inc., Lake Zuric...

1. A system for performing an apheresis procedure on a human subject, comprising:an apheresis treatment device configured to draw blood from a human subject, separate the blood by blood component, and return at least one of the components to the human subject; and
a remote data storage device located remotely from the apheresis treatment device and configured to communicate with the apheresis treatment device over a network, the remote data storage device programmed with a plurality of subject data entries, each subject data entry associated with a human subject, each subject data entry comprising subject-specific information, the remote data storage device configured to download subject-specific information comprising a name and a birth date from the subject data entry and further configured to program the apheresis treatment device with a plurality of parameters for the apheresis medical procedure;
the apheresis treatment device comprising:
a wireless circuit configured to communicate with the remote data storage device;
a touch screen configured to receive an input; and
a controller configured to confirm an identity of the human subject based on the input and, based at least in part on the result of the confirmation, provide access to an apheresis procedure operated according to the programmed parameters on the apheresis treatment device.

US Pat. No. 10,431,333

SYSTEMS AND METHOD FOR DEVELOPING RADIATION DOSAGE CONTROL PLANS USING A PARETOFRONT (PARETO SURFACE)

Fraunhofer Gesellschaft z...

1. A system for selecting a desired portion of a subject to receive a radiation dose the system comprising: a radiation apparatus, a computer, the computer comprising multiple cores and wherein a Pareto Surface is developed for intensity modulated radiation therapy (IMRT) or volumetric arc therapy (VMAT) planning and controlling delivery of radiation to the desired portion of the subject by adjusting, based on an IMRT or VMAT treatment plan including the developed Pareto Surface, positions of movable elements of the radiation apparatus;the system further comprising a non-transitory computer readable medium having computer readable program code thereon, the computer readable program code comprising a series of computer readable program steps to develop the Pareto Surface for said intensity modulated radiation therapy (IMRT) or volumetric arc therapy (VMAT);
and comprising
a) Covering the yet un-determined Pareto surface by a set of m-dimensional boxes, the Pareto surface having a plurality of points wherein at least three points from the plurality of points are selected and by solving a Pascoletti-Serafini problem along a diagonal of a corresponding box;
b) Applying a measure to find the largest available box;
c) Comparing the measure to a threshold value and update the set of boxes;
d) Repeating steps b) and c) along a first direction (q1) until the measure of the corresponding box is below the threshold value and using a first core of the computer, comprising said multiple cores for repeating the steps;
e) Selecting the second point on the Pareto surface and repeating steps corresponding to steps b) and c) along a second direction (q2) using the second core of the computer comprising the multiple cores;
f) Selecting the third point on the Pareto surface and repeating steps corresponding to steps b) to d) along a third direction (q3) using the third core of the computer comprising the multiple cores until the measure of the corresponding box is below the threshold value.

US Pat. No. 10,431,332

MEDICAL ASSISTANCE DEVICE, OPERATION METHOD AND OPERATION PROGRAM FOR MEDICAL ASSISTANCE DEVICE, AND MEDICAL ASSISTANCE SYSTEM

FUJIFILM Corporation, To...

1. A medical assistance device, comprising:a storage device, configured to store historical medical data of a patient, a plurality of diagnostic assistance programs, and recommended data ranges preset for each of the diagnostic assistance programs;
a processor, configured to:
control a diagnostic assistance program, selected from among the plurality of diagnostic assistance programs, that is executed to perform calculation using medical data of the patient as input data and output a result of the calculation as diagnostic assistance information for assisting diagnosis of the patient, wherein the medical data of the patient is extracted from the historical medical data of the patient;
receive an input of a designated data range, which is designated as a range to be used for the input data, of the medical data, wherein the input of the designated data range is input by a medical staff other than the patient;
acquire a recommended data range, from the stored recommended data ranges, that is preset for the selected diagnostic assistance program and is recommended as a range to be used for the input data, of the medical data of the patient; and
in response to determining a difference between the designated data range and the recommended data range display difference information indicating the difference on a graphical user interface configured to display the diagnostic assistance information.

US Pat. No. 10,431,331

COMPUTER-EXECUTABLE APPLICATION THAT IS CONFIGURED TO PROCESS CROSS-CLINICAL GENOMICS DATA

ALLSCRIPTS SOFTWARE, LLC,...

1. A computing system comprising:at least one processor; and
memory that has an application loaded therein, wherein the application, when executed by the at least one processor, is configured to perform acts comprising:
responsive to receipt of an identifier of a patient:
retrieving clinical data about the patient based upon the identifier of the patient, the clinical data being accessible by the application and identifies health problem of the patient;
applying a rule for a genetic disorder to the health problem identified in the clinical data;
determining using the rule that the patient is a candidate for genetic testing for the genetic disorder;
causing graphical data to be presented on a display of a computing device, the graphical data indicating to a clinician that the patient is a candidate for genetic testing for the genetic disorder;
based upon determining that the patient is a candidate for genetic testing for the genetic disorder, transmitting an order for a genetic test for the genetic disorder to a genetics lab computing device that is in network communication with the computing system;
receiving results for the genetic test from the genetics lab computing device; and
causing a visualization based upon the results to be presented on the display of the computing device, wherein the visualization is based on a relationship between:
a body system affected by the genetic disorder;
the genetic disorder; and
a genetic mutation associated with the genetic disorder, and further wherein the visualization comprises:
a first group of icons assigned to body systems of the patient, the body system that is affected by the genetic disorder is included in the body systems;
a second group of icons assigned to genetic disorders of the body systems, the genetic disorder is included in the genetic disorders; and
a third group of icons assigned to genetic mutations that cause the genetic disorders, the genetic mutation that is associated with the genetic disorder that is tested for in the genetic test is included in the genetic mutations,wherein the relationship is indicated in the visualization by a visually perceptible connection between a first icon corresponding to the body system from the first group, a second icon corresponding to the genetic disorder from the second group, and a third icon corresponding to the genetic mutation from the third group, the relationship being between the body system, the genetic disorder, and the genetic mutation.

US Pat. No. 10,431,330

METHOD AND SYSTEM TO PROVIDE PATIENT INFORMATION AND FACILITATE CARE OF A PATIENT

1. A method comprising:retrieving, by a server computer system, patient medical records pertaining to a patient;
processing, by the server computer system, the patient medical records to extract patient medical data pertaining to the patient, wherein said processing includes, by the server computer system,
accessing medical record datasets of a plurality of different types, associated with the patient,
identifying one or more first data fields in the medical record datasets as being relevant to a particular medical condition of the patient,
identifying one or more second data fields in the medical record datasets as having been classified as being classified as sensitive or protected information,
flagging the identified first data fields and the identified second data fields for subsequent processing, and
merging at least portions of the medical record datasets of the plurality of different types, including the flagged first data fields and second data fields, into a single database record for the patient;
creating, by the server computer system, a patient webpage specific to the patient from the single database record for the patient, the patient webpage including the patient medical data, wherein said creating the patient webpage includes creating the patient webpage to include the one or more first data fields in the patient webpage and to omit the one or more second data fields from the patient webpage, based on said flagging;
providing a wallet-size patient identification card associated with a patient, the patient identification card including a processor, an embedded fingerprint scanner, a memory to store a fingerprint of the patient, and a display device, the patient identification card further having an indicator disposed thereon, the indicator being a network resource locator corresponding to the patient webpage or a machine-readable code representing the network resource locator corresponding to the patient webpage;
receiving, by the server computer system, from a second computer, a request corresponding to the network resource locator, the request having been sent by the second computer in response to the second computer having received as input the network resource locator or an image of a machine readable code corresponding to the network resource locator, the request having been sent by the second computer in connection with the patient being treated by or seeking treatment or advice from a first health care provider other than a primary care physician of the patient;
the processor of the patient identification card being configured to cause the embedded fingerprint scanner of the wallet-size patient identification card to acquire a fingerprint of a person and to compare the acquired fingerprint to a stored fingerprint of the patient stored in the memory and, when the acquired fingerprint matches the stored fingerprint, to cause a personal identifier to be displayed on the display device of the patient identification card;
receiving the personal identifier at the server computer system from the second computer system, after the personal identifier is provided as input to the second computer by a user in response to display of the personal identifier by the display device of the patient identification card;
determining, by the server computer system, whether the personal identifier is correct;
in response to determining that the personal identifier is correct, transmitting, by the server computer system, the patient webpage to the second computer; and
in response to the network resource locator being accessed in connection with the patient being treated by or seeking treatment or advice from the first health care provider other than the primary care physician of the patient, automatically generating a notification message to the primary care physician of the patient, indicative that the patient webpage has been accessed, wherein the patient webpage is not owned or controlled by the first health care provider or the primary care physician of the patient.

US Pat. No. 10,431,329

REAL-TIME SYMPTOM ANALYSIS SYSTEM AND METHOD

1. A method of presenting real-time health information, the method comprising steps of:(a) administering by a user interface associated with a mobile device, a virtual questionnaire to obtain information regarding the user's symptoms,
(b) determining the location of the user using a location determination circuit associated with the mobile device;
(c) obtaining environmental data from an internet-accessible database corresponding with the user's local environmental conditions at the time the questionnaire is administered;
(d) automatically by a processor associated with the mobile device determining the health status of the user based on the user's response to the virtual questionnaire;
(e) storing the health status of the user and corresponding environmental data in a data store associated with the mobile device;
(f) developing a data structure from which the health status of the user is correlated with the user's local environmental conditions to identify causes of symptoms for the user;
(g) repeating steps (a) through (e) a plurality of different times, and recorrelating health status with the user's local environmental conditions to refine and enhance the data structure;
(h) determining at predetermined times the location of the user using the location determination circuit of the mobile device;
(i) obtaining current or predicted environmental data from the internet-accessible database at the location determined in step (h) contemporaneously with step (h);
(j) predicting future symptoms based upon the data structure and current or predicted local environmental conditions determined in step (i);
(k) determining whether to deliver a warning of environmental risks that are predicted to induce symptoms in the user; and
(l) presenting by a display associated with the mobile device a visualization indicative of the future symptoms if it is determined that a warning is to be delivered wherein presenting the visualization includes:
generating a map image;
overlaying a plurality of animated particles over the map image; and
displaying the map image and the plurality of animated particles on the display.

US Pat. No. 10,431,328

METHOD AND SYSTEM FOR ANATOMICAL TREE STRUCTURE ANALYSIS

BEIJING CURACLOUD TECHNOL...

1. A computer-implemented method for an anatomical tree structure analysis, comprising the following steps:receiving a task of the anatomical tree structure analysis;
setting, by a processor, a set of positions in an anatomical tree structure, wherein the anatomical tree structure represents a vessel or an airway;
determining, by the processor, a model input at each position among the set of positions on the basis of the task;
selecting, by the processor, an encoder for each position on the basis of the task, wherein the encoder is configured to receive the model input at each position and extract features for the corresponding position;
constructing, by the processor, a tree structured recurrent neural network (RNN) with nodes corresponding to the set of positions, by selecting an RNN unit for each node on the basis of the task and setting an information propagation among the nodes on the basis of spatial constraints of the set of positions in the anatomical tree structure, wherein each encoder is connected with the corresponding node of the tree structured RNN; and
providing the tree structured RNN for performing the task of the anatomical tree structure analysis.

US Pat. No. 10,431,327

COMPUTER GRAPHICAL USER INTERFACE WITH GENOMIC WORKFLOW

Palantir Technologies Inc...

1. A method comprising:presenting, in a graphical user interface, graphical components representing a source from which one or more nucleic acid sequences are to be obtained and one or more sets of instructions for processing data, including at least one set of instructions for processing the one or more nucleic acid sequences, wherein the source and the one or more sets of instructions are represented as nodes within a workspace;
wherein the source and the one or more sets of instructions are arranged as a workflow comprising a series of nodes, the series of nodes indicating, for each particular set of instructions of the one or more sets of instructions, that output from one of the source or another particular set of instructions is to be input into the particular set of instructions;
generating an output for the workflow, wherein the output comprises a set of one or more items of genomic data that are based upon the one or more nucleic acid sequences that are processed by each set of instructions of the one or more sets of instructions in an order indicated by the series of nodes;
generating a first data node from the output, the first data node comprising the set of one or more items of genomic data, the first data node linked to a last set of instructions in the series;
receiving, via the graphical user interface, a first input that selects a subset of one or more items of genomic data from the set of one or more items of genomic data in the first data node;
receiving, via the graphical user interface, a second input that moves the subset of one or more items of genomic data to a location on the graphical user interface not associated with the first data node;
generating a second data node comprising the subset of one or more items of genomic data, wherein the output for the workflow is reconfigured to generate multiple data nodes; and
wherein the method is performed by one or more computing devices.

US Pat. No. 10,431,324

DATA STORAGE DEVICE FOR PERFORMING DECODING OPERATION AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A data storage device comprising:a nonvolatile memory device configured to store a codeword; and
a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword,
wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.

US Pat. No. 10,431,323

CALIBRATING I/O IMPEDANCES USING ESTIMATION OF MEMORY DIE TEMPERATURE

Toshiba Memory Corporatio...

1. A memory system comprising:a memory having an input/output (“I/O”) terminal;
a memory controller configured to receive a plurality of memory commands, the memory controller communicatively coupled to the memory and further configured to:
estimate a first energy consumed by the memory based on a tally of the plurality of memory commands during a first time interval;
determine a first operating characteristic of the memory based on the first energy consumed in the first time interval by comparison to a second energy consumed in a second time interval, the second time interval having a different starting or ending time than the first time interval; and
perform an adjustment based on the first operating characteristic.

US Pat. No. 10,431,322

MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system, comprising:a memory device including;
a bit line;
a word line;
a first string coupled to the bit line via a first transistor and including a first cell transistor; and
a second string coupled to the bit line via a second transistor and including a second cell transistor, the second cell transistor and the first cell transistor being coupled to the word line; and
a controller configured to:
instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor; and
instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.

US Pat. No. 10,431,321

EMBEDDED TRANSCONDUCTANCE TEST CIRCUIT AND METHOD FOR FLASH MEMORY CELLS

Integrated Silicon Soluti...

1. A transconductance test method implemented in a flash memory device, the flash memory device comprising a two-dimensional array of memory cells, the method comprising:after an erase operation applied to one or more memory cells of the flash memory device, selecting a first test step as a present test step;
applying a first bias level of the present test step to a control terminal of a selected memory cell;
measuring a cell current of the selected memory cell in response to the first bias level of the present test step being applied to the control terminal;
determining if the cell current is greater than a first reference level;
in response to the cell current being greater than the first reference level, setting an indicator for the selected memory cell;
applying a second bias level of the present test step to the control terminal of the selected memory cell, the second bias level being the first bias level plus a predetermined margin;
measuring the cell current of the selected memory cell in response to the second bias level of the present test step being applied to the control terminal;
determining if the cell current is greater than a second reference level, the second reference level being greater than the first reference level; and
in response to the indicator for the selected memory cell being set and in response to the cell current being less than the second reference level, storing a memory cell address associated with the selected memory cell in a memory, the stored memory cell address indicating the selected memory cell has been detected to have a low transconductance value.

US Pat. No. 10,431,320

SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of testing a semiconductor memory device comprising a memory cell block including a plurality of memory cells, a first group of word lines coupled to first memory cells among the plurality, and a second group of word lines coupled to second memory cells among the plurality that alternate with the first group, the method comprising:writing data to the first and second memory cells during a first period;
applying a first boosted voltage to the second group of word lines and a second boosted voltage to the first group of word lines during a second period after the first period, wherein the first boosted voltage has a voltage level different from that of the second boosted voltage; and
reading the data from the first memory cells coupled to the first group of the word lines during a third period after the second period to determine whether each of the first memory cells is defective.

US Pat. No. 10,431,319

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells; and
a controller, wherein the controller is coupled to the array of memory cells and includes control circuitry configured to:
store a number of sets of trim settings; and
select a particular set of trims settings of the number of sets of trim settings including particular trim setting parameters based on desired operational characteristics for the array of memory cells, wherein the particular trim setting parameters include programming signal magnitude, sensing signal magnitude, erase signal magnitude, programming signal length, erase signal length, and sensing signal length.

US Pat. No. 10,431,318

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a ninth transistor,
wherein:
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have a same conductivity type;
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to the second wiring;
the other of the source and the drain of the second transistor is electrically connected to a third wiring;
one of a source and a drain of the third transistor is electrically connected to a fourth wiring;
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;
one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor;
the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring;
a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;
the first conductive layer is configured to be the gate of the first transistor;
the third conductive layer is configured to be a gate of the third transistor, and
the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor.

US Pat. No. 10,431,317

MEMORY SYSTEM

NXP B.V., Eindhoven (NL)...

1. A memory system comprising:a memory cell comprising:
a poly-fuse-resistor,
a bipolar junction transistor having a collector-emitter channel and a base-terminal, wherein the collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal; and the base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor, and
a NOR logic gate having p-channel transistors configured to provide the transistor-control-signal.

US Pat. No. 10,431,316

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A memory system comprising:a nonvolatile memory device including a plurality of memory cells; and
a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed,
wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.

US Pat. No. 10,431,315

OPERATION METHOD OF A NONVOLATILE MEMORY DEVICE FOR CONTROLLING A RESUME OPERATION

SAMSUNG ELECTRONICS CO., ...

1. An operation method of a nonvolatile memory device for erasing a selected memory block from among a plurality of memory blocks, the method comprising:performing an erase operation;
suspending the erase operation after performing a first portion of the erase operation;
resuming the erase operation to perform a second portion of the erase operation, wherein the erase operation is resumed when a resume time, which is a time elapsed since the erase operation was suspended, is less than a reference time, wherein the reference time is a length of time for securing reliability of the erase operation with respect to a threshold voltage distribution of the suspended erase operation; and
erasing a memory block different than the selected memory block when the resume time is equal to or greater than the reference time.

US Pat. No. 10,431,314

NON-VOLATILE MEMORY DEVICE FOR IMPROVING DATA RELIABILITY AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A non-volatile memory device, comprising:a memory cell array comprising a plurality of memory cells connected to a plurality of word lines, some of the plurality of word lines corresponding to a deterioration area; and
a voltage generator configured to generate a program voltage provided to the plurality of memory cells through the plurality of word lines,
wherein control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the plurality of word lines,
wherein the deterioration area comprises word lines of a first group, where data of at least one first bit is written in each of the plurality of memory cells, and word lines of a second group where data of at least two second bits is written in each of the plurality of memory cells, wherein the at least two second bits are more than the at least one first bits, and
wherein the control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.

US Pat. No. 10,431,312

NONVOLATILE MEMORY APPARATUS AND REFRESH METHOD THEREOF

Winbond Electronics Corp....

1. A non-volatile memory apparatus, comprising:a non-volatile memory; and
a control circuit, coupled to the non-volatile memory and refreshing a non-selected block when an erasing operation is performed, wherein the non-selected block comprises a plurality of memory sectors, each of the memory sectors comprises a plurality of memory cells, and the control circuit determines whether threshold voltages of the memory cells in the memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, wherein the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage,
wherein the control circuit further determines whether a first memory sector to which a current address corresponds comprises the memory cell having the threshold voltage larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage, and if the first memory sector to which the current address corresponds does not comprise the memory cell having the threshold voltage larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage, a refresh operation of the remaining memory sectors in the non-selected block is skipped to complete the refresh operation of the non-selected block.

US Pat. No. 10,431,311

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a plurality of conductors being stacked with insulators being interposed therebetween;
a pillar through the plurality of conductors, the pillar including a first pillar portion, a second pillar portion above the first pillar portion, and a joint portion between the first pillar portion and the second pillar portion, the pillar functioning as a transistor in parts where the pillar crosses the respective conductors; and
a controller configured to perform a write operation, wherein
among the plurality of conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line,
among the plurality of conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line,
the controller
performs a program loop which includes a program operation in the write operation, the program operation including a pre-charge operation,
applies a first voltage higher than a ground voltage to the first word line, the first dummy word line, the second dummy word line, and the second word line, in the pre-charge operation in the write operation for which the first word line is selected,
applies a second voltage lower than the first voltage to the first word line, and applies the first voltage to the second dummy word line and the second word line, in the pre-charge operation in the write operation for which the second word line is selected.

US Pat. No. 10,431,310

BOOSTED CHANNEL PROGRAMMING OF MEMORY

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:boosting a channel voltage of a first memory cell selected for programming to a first voltage level for a particular programming pulse, and boosting a channel voltage of a second memory cell selected for programming to a second voltage level for the particular programming pulse;
boosting the channel voltage of the first memory cell selected for programming to a third voltage level, greater than the first voltage level, for a subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a fourth voltage level, greater than the second voltage level, for the subsequent programming pulse; and
boosting the channel voltage of the first memory cell selected for programming to a fifth voltage level, greater than the third voltage level, for a next subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a sixth voltage level, greater than the fourth voltage level, for the next subsequent programming pulse;
wherein the sixth voltage level is greater than the fifth voltage level;
wherein a difference between the third voltage level and the first voltage level is the same as a difference between the fifth voltage level and the third voltage level;
wherein a difference between the fourth voltage level and the second voltage level is the same as a difference between the sixth voltage level and the fourth voltage level;
wherein the second memory cell is selected for programming to a data state corresponding to a range of threshold voltages less than a range of threshold voltages corresponding to a data state to which the first memory cell is selected for programming; and
wherein the difference between the third voltage level and the first voltage level is different than the difference between the fourth voltage level and the second voltage level.

US Pat. No. 10,431,309

SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a bit line;
a source line;
a memory cell unit including
a first selection transistor connected to the bit line,
a second selection transistor connected to the source line, and
a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including
a first memory cell,
a second memory cell located closer to the first selection transistor than the first memory cell,
a third memory cell located closer to the first selection transistor than the second memory cell, and
a fourth memory cell located closer to the first selection transistor than the third memory cell;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a third word line connected to the third memory cell;
a fourth word line connected to the fourth memory cell;
a driver circuit configured to apply a voltage to
the first word line,
the second word line,
the third word line, and
the fourth word line;
a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the driver circuit;
a second transistor connected between the second word line and the driver circuit;
a third transistor connected between the third word line and the driver circuit; and
a fourth transistor connected between the fourth word line and the driver circuit,
wherein when data is written into the first memory cell,
a first voltage is applied to
the first word line,
a second voltage is applied to
the second word line,
a third voltage is applied to
the third word line, and
a fourth voltage is applied to
the fourth word line,
wherein the first voltage is larger than the second voltage, the third voltage and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage,
wherein the second word line, the third word line, and the fourth word line are not located above the first diffused layer and the second diffused layer, and
wherein each of the first word line, the second word line, the third word line, and the fourth word line is arranged in a first direction,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor has a gate length in a second direction perpendicular to the first direction,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in the first direction, and
wherein a distance between the first transistor and the memory cell unit is smaller than a distance between the second transistor and the memory cell unit.

US Pat. No. 10,431,308

MEMORY CELL SIZE REDUCTION FOR SCALABLE LOGIC GATE NON-VOLATILE MEMORY ARRAYS

Flashsilicon Incorporatio...

1. An array of nonvolatile memory (NVM) cells comprising:a plurality of source lines and bit lines; and
a plurality of NVM cells organized in rows and columns on a substrate, each NVM cell having a source region, a drain region, a floating gate, a control gate region and a channel region, the NVM cells in a row being arranged in cell pairs, such that each cell pair comprises a sharing source region connected to a common source line and two drain regions connected to two different bit lines, wherein two drain regions of any two column-adjacent NVM cells in each row are connected to two different bit lines;
wherein the floating gate is disposed over and insulated from both the channel region and the control gate region and the floating gate extends in a column direction from the channel region to the control gate region, and wherein a gate width of the floating gate are aligned with the boundaries of the channel region and the control gate region without protruding from the channel region and the control gate region;
means for processing the array with CMOS logic technologies;
wherein the means for processing the array with CMOS logic technologies limits a gate length of the floating gate to a minimal feature size of a process technology node; and
wherein the control gate region, the source region and the drain region have the same conductivity type; and
wherein a control gate length of the array is perpendicular to the bit lines.

US Pat. No. 10,431,307

ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIONS WITH CONTENT ADDRESSABLE MEMORY (CAM) CIRCUITS

INTERNATIONAL BUSINESS MA...

1. A circuit comprising:a first portion of a content addressable memory (CAM) configured to perform a first inequality operation implemented between 1 to n CAM entries, wherein the 1 to n CAM entries of the first portion are read from left to right to perform the first inequality operation;
a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries, wherein the 1 to n CAM entries of the second portion are read from right to left to perform the second inequality operation;
a first matchline configured to indicate a match or mismatch for each of the 1 to n CAM entries implemented in the first portion; and
a second matchline configured to indicate a match or mismatch for each of the 1 to n CAM entries implemented in the second portion,
wherein the first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines,
wherein two valid bits are provided for each of the 1 to n CAM entries as extra bits, in addition to data bits defining each of the 1 to n CAM entries, to indicate that the data bits defining each of the 1 to n CAM entries comprise a valid pattern,
wherein the first and second portions of the CAM are each comprised of binary CAM (BCAM) cells,
wherein, for each 1 to n CAM entry, the valid bit is latched in a latch circuit, wherein the latch circuit is coupled to a precharge driver for the first and second matchlines such that the first and second matchlines will only be precharged when the valid bit for a corresponding one of the 1 to n CAM entries is latched in the latch circuit, and
wherein, for each 1 to n CAM entry, one valid bit is provided for the first matchline and another valid bit is provided for the second matchline.

US Pat. No. 10,431,306

RECONFIGURABLE SEMICONDUCTOR INTEGRATED CIRCUIT

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor integrated circuit comprising:first wiring lines;
at least two second wiring lines intersecting with the first wiring lines;
third wiring lines intersecting with the first wiring lines;
first memory elements disposed in a cross region between the first wiring lines and the second wiring lines, at least one of the first memory elements including a first terminal connected to corresponding one of the first wiring lines and a second terminal connected to corresponding one of the second wiring lines;
second memory elements disposed in a cross region between the first wiring lines and the third wiring lines, at least one of the second memory elements including a third terminal connected to corresponding one of the first wiring lines and a fourth terminal connected to corresponding one of the third wiring lines;
a first write control circuit connected to the first wiring lines;
a first circuit connected to one of the second wiring lines, the first circuit supplying a first potential;
a second circuit connected to the other one of the second wiring lines, the second circuit supplying a second potential lower than the first potential;
SRAM cells disposed to correspond to the third wiring lines, and at least one of the SRAM cells being connected to corresponding one of the third wiring lines; and
a selection circuit including input terminals corresponding to the first wiring lines and an output terminal, each of the input terminals being electrically connected to corresponding one of the first wiring lines, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

US Pat. No. 10,431,305

HIGH-PERFORMANCE ON-MODULE CACHING ARCHITECTURES FOR NON-VOLATILE DUAL IN-LINE MEMORY MODULE (NVDIMM)

Advanced Micro Devices, I...

1. A hybrid memory module, comprising:a first non-volatile memory;
a first integrated control buffer coupled directly to the first non-volatile memory, wherein the first integrated control buffer operates as both a data buffer and a multiplexer; and
a first volatile memory and a first volatile memory tag unit coupled directly to the first integrated control buffer, wherein the first integrated control buffer is integrated with first cache integration logic to perform cache operations and the first integrated control buffer performs data multiplexing between at least two of the first non-volatile memory, the first volatile memory, and the first volatile memory tag unit, wherein the cache operations include at least one of instructing the first non-volatile memory and the first volatile memory to load a cache line when a miss operation occurs, write back to the cache line when an eviction occurs, or read the cache line when a hit operation occurs.

US Pat. No. 10,431,304

METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

ARM Ltd., Cambridge (GB)...

1. A method comprising:applying a first programing signal across first and second terminals of a correlated electron switch (CES) element to place the CES element in a conductive or low impedance state;
applying a second programming signal across the first and second terminals to place the CES element in an insulative or high impedance state, the second programming signal comprising a second voltage across the first and second terminals; and
applying a third voltage across the first and second terminals as a supply voltage during a read operation, and wherein a magnitude of the third voltage is equal or greater to a magnitude of the second voltage.

US Pat. No. 10,431,303

RESISTANCE CHANGE TYPE MEMORY INCLUDING WRITE CONTROL CIRCUIT TO CONTROL WRITE TO VARIABLE RESISTANCE ELEMENT

NATIONAL INSTITUTE OF ADV...

1. A resistance change type memory comprising:a variable resistance element connected between a first bit line and a second bit line;
a write control circuit including
a first transistor including a first terminal connected to the first bit line;
a second transistor including a second terminal connected to the first bit line;
a first element including a first output terminal outputting a first signal which controls ON and OFF of the first transistor;
a first interconnect connected to the first output terminal; and
a second element including a first input terminal connected to the first interconnect, and a second output terminal outputting a second signal which controls ON and OFF of the second transistor, the second signal being based on the first signal from the first interconnect,
the write control circuit controlling write to the variable resistance element;
a second interconnect supplied with a first voltage and connected to the first bit line via the first transistor; and
a third interconnect supplied with a second voltage which is higher than the first voltage, and connected to the first bit line via the second transistor,
wherein the write control circuit:
supplies the first voltage to the first bit line via the first transistor which is in an ON state;
sets the second transistor in an ON state after supplying the first voltage; and
supplies the second voltage to the first bit line with a first pulse width via the second transistor which is in the ON state.

US Pat. No. 10,431,302

METHODS, ARTICLES, AND DEVICES FOR PULSE ADJUSTMENT TO PROGRAM A MEMORY CELL

Micron Technology, Inc., ...

1. A method, comprising:determining that a resistance value for a memory cell is lower than a previous resistance value for the memory cell;
adjusting a parameter of an electrical pulse based at least in part on determining that the resistance value is lower than the previous resistance value; and
applying the electrical pulse to the memory cell based at least in part on the adjusted parameter.

US Pat. No. 10,431,301

AUTO-REFERENCED MEMORY CELL READ TECHNIQUES

Micron Technology, Inc., ...

1. A method, comprising:initializing a counter in a controller coupled with a memory array;
activating at least a portion of a first group of memory cells of the memory array by applying a read voltage to the memory array;
determining that a set of memory cells has been activated based at least in part on applying the read voltage;
updating the counter to a first value based at least in part on determining that the set of memory cells has been activated;
comparing the first value of the updated counter to a threshold stored at the controller; and
reading one or more memory cells of the memory array based at least in part on the comparison.

US Pat. No. 10,431,300

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A nonvolatile memory device comprising:a memory cell array including a plurality of memory cells and dummy cells formed on a body;
a row decoder connected to the memory cells through word lines;
a dummy bit line bias circuit connected to the dummy cells through a dummy bit line;
a dummy word line bias circuit connected to the dummy cells through a plurality of dummy word lines;
a write driver and sense amplifier connected to the memory cells through bit lines;
a source line driver connected to the memory cells through a plurality of source lines; and
a leakage detector connected to the dummy cells through a dummy source line.

US Pat. No. 10,431,299

SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A semiconductor storage device comprising:a plurality of memory cells, each of the plurality of memory cells being capable of storing data of n bits (n is an integer equal to or larger than 3);
a word line which is connected to the plurality of memory cells; and
a control circuitry including a first latch circuitry, a second latch circuitry, a third latch circuitry, and a fourth latch circuitry, wherein the control circuitry is configured to;
in response to a first read request, perform a first read operation of reading first data out of the plurality of memory cells with a first voltage applied to the word line, and storing the first data in the second latch circuitry, and
in response to a second read request,
perform a second read operation of reading second data out of the plurality of memory cells with a second voltage within first voltage range and a third voltage within a second voltage range applied the word line, and storing the second data in the third latch circuitry, the first voltage range smaller than the first voltage, the second voltage range larger than the first voltage,
perform first logical operation of logically processing the first data stored in the second latch circuitry and the second data stored in the third latch circuitry,
store third data generated by the first logical operation in the first latch circuitry, and
output the third data stored in the first latch circuitry.

US Pat. No. 10,431,298

NONVOLATILE MEMORY AND WRITING METHOD

Toshiba Memory Corporatio...

1. A method for controlling a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store data by correlating three bits with eight threshold regions, the eight threshold regions corresponding to first to eighth threshold regions defined in ascending order of threshold voltage, each of the plurality of memory cells connected to a word line, the three bits respectively corresponding to first to third pages, a threshold voltage of an unwritten state of the memory cells being set at the first threshold region, the method comprising:when writing a first value to the first page of an unwritten memory cell, performing programming such that the threshold voltage of the unwritten memory cell is within the fifth threshold region;
when performing writing of the second page of the memory cell after the writing of the first page of the memory cell,
if a value corresponding to the first page of the memory cell is a second value and a value to be written to the second page is the first value, performing programming such that the threshold voltage of the memory cell is within the second threshold region, and
if a value corresponding to the first page of the memory cell is the first value and a value to be written to the second page is the first value, performing programming such that the threshold voltage of the memory cell is within the seventh threshold region;
when performing writing of the third page of the memory cell after the writing of the second page of the memory cell,
if a value corresponding to the first page of the memory cell is the second value, a value corresponding to the second page of the memory cell is the second value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the fourth threshold region,
if a value corresponding to the first page of the memory cell is the second value, a value corresponding to the second page of the memory cell is the first value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the third threshold region;
if a value corresponding to the first page of the memory cell is the first value, a value corresponding to the second page of the memory cell is the second value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the sixth threshold region,
if a value corresponding to the first page of the memory cell is the first value, a value corresponding to the second page of the memory cell is the first value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the eighth threshold region, and
when reading out data from the first page, reading out the data using a fourth read voltage, the fourth read voltage being a boundary voltage between the fourth threshold region and the fifth threshold region, and determining data of the first page on a basis of the read out data;
when reading out data from the second page, reading out the data using a first, a third and a sixth read voltage, the first read voltage being a boundary voltage between the first threshold region and the second threshold region, the third read voltage being a boundary voltage between the third threshold region and the fourth threshold region, the sixth read voltage being a boundary voltage between the sixth threshold region and the seventh threshold region, and determining data of the second page on a basis of the read our data; and
when reading out data from the third page, reading out the data using a second, a fifth and a seventh read voltage, the second read voltage being a boundary voltage between the second threshold region and the third threshold region, the fifth read voltage being a boundary voltage between the fifth threshold region and the sixth threshold region, the seventh read voltage being a boundary voltage between the seventh threshold region and the eighth threshold region, and determining data of the third page on a basis of the read out data.

US Pat. No. 10,431,296

SERIALIZED SRAM ACCESS TO REDUCE CONGESTION

Taiwan Semiconductor Manu...

1. A system, comprising:a plurality of memory arrays each comprising a plurality of columns having a plurality of bit-cells therein, wherein each of the plurality of memory arrays is configured to receive a serialized input signal and generate a serialized output signal;
a plurality of clock generators, wherein each of the plurality of clock generators is configured to generate an array-specific clock signal for a respective one of the plurality of memory arrays, and wherein the respective one of the plurality of memory arrays is configured to sequentially latch a respective bit of the serialized input signal or sequentially output a respective bit of the serialized output signal when the array-specific clock signal is active.

US Pat. No. 10,431,295

STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) comprising:a memory cell, wherein the memory cell comprises at least two p-type pass gates;
a bit line connected to the memory cell;
a bit line bar connected to the memory cell;
a word line connected to the memory cell;
an n-type transistor connected between a ground voltage and a first node;
a first inverter having an input terminal configured to receive a data signal and an output terminal connected to the word line, the first inverter being connected between a supply voltage and the first node; and
a voltage control unit configured to control the N-type transistor and to control the memory cell by providing an operating voltage on the first node which affects operation of the first inverter and thereby causes a voltage on the word line to undergo at least a double transition including a first transition to the ground voltage and then a second transition to an intermediate voltage which is greater than the ground voltage but substantially lower than the supply voltage; and
wherein:
the voltage control unit includes a p-type capacitor-connected transistor connected to the first node and thereby to the word line; and
the voltage control unit is further configured to selectively adjust voltages correspondingly of the bit line and the bit line bar.

US Pat. No. 10,431,294

WRITE LEVEL ARBITER CIRCUITRY

Micron Technology, Inc., ...

1. A semiconductor device comprising:memory comprising a group of storage elements;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory;
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory; and
arbiter circuitry configured to detect which phase of the plurality of phases captures a write start signal for the write command, wherein the arbiter circuitry comprises a latch that is configured to:
receive a first indication of a pulse in a first phase of the plurality of phases; and
receive a second indication of a pulse in a second phase of the plurality of phases.

US Pat. No. 10,431,293

SYSTEMS AND METHODS FOR CONTROLLING DATA STROBE SIGNALS DURING READ OPERATIONS

Micron Technology, Inc., ...

1. An apparatus comprising:a first data strobe (DQS) output buffer (OB) and a second DQS OB each coupled to a DQS terminal, the first DQS OB and the second DQS OB configured to provide a DQS signal to the DQS terminal responsive to a read clock signal; and
control logic configured to receive the read clock signal to control the first DQS OB and the second DQS OB,
wherein the apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

US Pat. No. 10,431,292

METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A COMMON BUS BY MULTIPLE COMPONENTS

Micron Technology, Inc., ...

1. An apparatus comprising:a first memory die;
a first bus;
a common bus; and
an interface control logic stacked with the first memory die and coupled to the first memory die through the first bus and the common bus, the interface control logic including:
a plurality of delay circuits configured to output a plurality of strobe signals having different amounts of delay from one another; and
a multiplexer configured to select a first one of the plurality of strobe signals, responsive to a first command, based on a type of the first command and a first latency of the first memory die, transferred through the common bus and output the first one of the plurality of strobe signals to the first bus;
wherein the first memory die is configured to capture the first command responsive to the first one of the plurality of strobe signals.

US Pat. No. 10,431,291

SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL VOLTAGE BOOSTING

Micron Technology, Inc., ...

1. A memory device, comprising:a memory array having at least one memory cell;
a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof;
a first bus configured to provide a first electric power to the sense amplifier circuit; and
a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell, wherein the first bus is electrically coupled to a first power supply, wherein the second bus is electrically coupled to a second power supply, and wherein the second power supply is configured to deliver a voltage higher than the first power supply.

US Pat. No. 10,431,290

PROTOCOL FOR MEMORY POWER-MODE CONTROL

Rambus Inc., Sunnyvale, ...

1. A dynamic random access memory (DRAM) device comprising:a memory core having a plurality of memory cells;
a command/address (CA) interface to receive command and address information;
a data interface to output data in response to a command received via the CA interface;
an interface to receive a power mode signal; and
a plurality of mode registers to store parameter values including a first parameter value that sets a power down mode for the CA interface and the data interface, such that a combination of the first parameter value and a level of the power mode signal determine which of the data interface and the CA interface are powered down in response to a transition in the level of the power mode signal, the parameter values further associated with a plurality of operating clock frequencies of a clock signal.

US Pat. No. 10,431,289

MEMORY DEVICES WITH SELECTIVE PAGE-BASED REFRESH

Micron Technology, Inc., ...

1. A memory device comprising:a main memory including a memory region having a plurality of memory pages; and
a controller operably coupled to the main memory, wherein the controller is configured to:
track a first subset of the plurality of memory pages having a first refresh schedule and a second subset of the plurality of memory pages having a second refresh schedule that is different than the first refresh schedule, wherein at least one of the first and second refresh schedules is a function of an elapsed time since the last refresh operation,
refresh the first subset of memory pages according to the first refresh schedule, and
refresh the second subset of memory pages according to the second refresh schedule.

US Pat. No. 10,431,288

SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED ADDRESS PATH

Micron Technology, Inc., ...

1. A method comprising:receiving an instruction to refresh a row address stored in a counter of a memory device;
blocking incrementing the row address when the memory device transitioned from a first mode of operation to a second mode of operation and an immediately previous refresh operation was unpaired;
incrementing the row address stored in the counter when the memory device did not transition from the first mode of operation to the second mode of operation, or the memory device transitioned from the first mode of operation to the second mode of operation and the immediately previous refresh operation was paired; and
refreshing the row address stored in the counter.

US Pat. No. 10,431,286

REFRESH IN NON-VOLATILE MEMORY

Micron Technology, Inc., ...

9. An apparatus, comprising:an array of memory cells; and
a processor configured to:
determine a threshold miss rate based on a number of memory cells that fail to refresh;
determine a refresh rate of the array of memory cells based on the threshold miss rate; and
refresh a memory cell of the array of memory cells in response to the array of memory cells being accessed a threshold number of accesses, wherein the threshold is based on the refresh rate.

US Pat. No. 10,431,284

DYNAMIC REFERENCE VOLTAGE DETERMINATION

Micron Technology, Inc., ...

14. An electronic memory apparatus, comprising:a first memory cell comprising a first digit line;
a second memory cell comprising a second digit line; and
a controller coupled with the first memory cell and the second memory cell, wherein the controller is operable to:
activate a first switching component coupled with the first and second digit lines; and
determine a reference voltage based at least in part on a voltage of a conductive path, wherein the conductive path is established between the first and second digit lines when the first switching component is activated.

US Pat. No. 10,431,283

APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY

Micron Technology, Inc., ...

1. A method, comprising:increasing a voltage of a first cell plate of a capacitor to change a voltage of a second cell plate of the capacitor, a second digit line, and a second sense node;
decreasing the voltage of the second cell plate and the second digit line to change the voltage of the first cell plate, a first digit line, and a first sense node, wherein decreasing the voltage of the second cell plate and the second digit line includes decreasing the voltage of the second cell plate from an increased voltage to an initial voltage of the second cell plate;
driving the first sense node to a first voltage and driving the second sense node to a second voltage responsive to the voltage of the first sense node being greater than the voltage of the second sense node; and
driving the first sense node to the second voltage and driving the second sense node to the first voltage responsive to the voltage of the first sense node being less than the voltage of the second sense node.

US Pat. No. 10,431,282

ARRAY DATA BIT INVERSION

Micron Technology, Inc., ...

1. A method, comprising:sensing, by a sense component through a first set of transistors, a first logic value stored at a memory cell; and
applying an output of the sense component to the memory cell through a second set of transistors different than the first set of transistors, the output of the sense component corresponding to the first logic value, wherein a second logic value different than the first logic value is stored at the memory cell based at least in part on the applying.

US Pat. No. 10,431,281

ACCESS SCHEMES FOR SECTION-BASED DATA PROTECTION IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method, comprising:initializing a timer associated with sections of a memory device, each of the sections comprising memory cells associated with one of a plurality of word lines of the section that is configured to selectively couple the memory cells with one of a plurality of digit lines of the section;
selecting one of the sections for a voltage adjustment operation based at least in part on a determined value of the timer; and
performing the voltage adjustment operation on the selected section by activating each of the plurality of word lines of the selected section.

US Pat. No. 10,431,280

FERROELECTRIC OPENING SWITCH

1. A ferroelectric opening switch, comprising:a ferroelectric material comprising at least one crystal having a permanent electric dipole determined by the crystallographic symmetry of the ferroelectric material and a having plurality of nucleation sites; and
a voltage source for applying an electric field to the ferroelectric material;
wherein polarization reversal of the electric dipoles is nucleated at the nucleation sites when the electric field is applied, thereby changing current flow in the switch.

US Pat. No. 10,431,277

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a memory cell; and
a first circuit configured to:
perform a first read for the memory cell and generate a first voltage,
write first data to the memory cell that has undergone the first read,
perform a second read for the memory cell to which the first data is written and generate a second voltage, and
determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage,
wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage to a floating state,
wherein the generation unit is sandwiched by two transistors, and the second voltage varies as a result of the second read and control signals provided to the two transistors.

US Pat. No. 10,431,276

SEMICONDUCTOR DEVICES INCLUDING REVERSIBLE AND ONE-TIME PROGRAMMABLE MAGNETIC TUNNEL JUNCTIONS

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a plurality of word lines;
a plurality of bit lines crossing the plurality of word lines, the plurality of bit lines including first bit lines and second bit lines, the second bit lines spaced apart from the first bit lines in a direction of extension of the plurality of word lines;
a plurality of first memory cells connected between the plurality of word lines and the first bit lines, each of the plurality of first memory cells including a first memory element and a first selection element, the first memory element and the first selection element connected to each other; and
a plurality of second memory cells connected between the plurality of word lines and the second bit lines, each of the plurality of second memory cells including a second memory element and a second selection element, the second memory element and the second selection element connected to each other,
wherein the first memory element includes a first magnetic tunnel junction, and the second memory element includes a second magnetic tunnel junction, each of the first and second magnetic tunnel junctions including a pinned layer, a free layer, and a tunnel barrier layer between the pinned layer and the free layer,
wherein the tunnel barrier layers of a first portion of the second magnetic tunnel junctions have an irreversible resistance state,
wherein the first magnetic tunnel junction has a rewritable structure, and is configured to have one of (i) a first resistance corresponding to first data, and (ii) a second resistance corresponding to second data;
wherein at least one second magnetic tunnel junction among the first portion of the second magnetic tunnel junctions has a third resistance corresponding to the first data, the at least one second magnetic tunnel junction having been programmed through a first one-time programming operation,
wherein at least one other second magnetic tunnel junction from among the first portion of the second magnetic tunnel junctions has a fourth resistance corresponding to the second data, the at least one other second magnetic tunnel junction having been programmed through a second one-time programming operation,
wherein the first to fourth resistances are different from each other,
wherein one or more of the plurality of first memory cells are configured as one or more first reference cells for a reading operation on the plurality of first memory cells, and one or more of the plurality of second memory cells are configured as one or more second reference cells for a reading operation on the plurality of second memory cells, and
wherein the one or more of the plurality of first memory cells includes one or more pairs of first memory cells, and a pair of first memory cells among the one or more pairs of first memory cells are connected in parallel to one of the first bit lines.

US Pat. No. 10,431,275

METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS HAVING HYBRID OXIDE AND NOBLE METAL CAPPING LAYERS

Samsung Electronics Co., ...

1. A magnetic apparatus residing on a substrate and usable in a magnetic device, the magnetic apparatus comprising:a magnetic junction; and
a hybrid capping layer adjacent to the magnetic junction, the hybrid capping layer including an insulating layer, a discontinuous oxide layer, and a noble metal layer, the discontinuous oxide layer being between the insulating layer and the noble metal layer, the insulating layer being between the magnetic junction and the noble metal layer.

US Pat. No. 10,431,274

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a plurality of banks, each having a dedicated line and sharing a global line;
a plurality of sub-global lines shared by neighboring banks among the plurality of banks;
a plurality of data input/output circuits coupled to the plurality of banks, respectively, through the dedicated line and coupling the dedicated lines of corresponding banks to the sub-global lines in response to bank strobe signals, respectively; and
a plurality of data intervention blocks corresponding to the plurality of sub-global lines, respectively, and coupling the global line to corresponding sub-global lines in response to a delayed write strobe signal or read strobe signals.

US Pat. No. 10,431,273

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a row decoder provided on a semiconductor substrate; and
a memory cell array provided above the row decoder and including a first block,
wherein the first block includes:
a first region spreading along a first plane formed by a first direction that is an in-plane direction of the semiconductor substrate and a second direction that is the in-plane direction and is different from the first direction and having a first width along the second direction;
a second region spreading along the first plane, having a second width larger than the first width along the second direction, and being adjacent to the first region in the first direction; and
a third region spreading along the first plane, having a third width smaller than the first width along the second direction, and located between the first region and the second region to connect the first region and the second region,
wherein the first region, the second region, and the third region include a plurality of first word lines stacked along a third direction that is a vertical direction of the semiconductor substrate, and the first region further includes a first selection gate line provided above a first word line of an uppermost layer, and
the memory cell array further includes:
a first insulating layer buried in a first trench between the first region and the second region and being in contact with the third region in the second direction;
a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and
a first interconnect configured to connect the first selection gate line and the first contact plug.

US Pat. No. 10,431,272

VOLTAGE CONTROL CIRCUIT INCLUDING ASSIST CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a volatile memory cell array connected to a plurality of word lines and comprising a memory cell that comprises at least one transistor;
a word line driver connected to the plurality of word lines, wherein a first node is connected to the word line driver and receives a voltage derived from a main power supply voltage; and
an assist circuit comprising an N-channel metal oxide semiconductor (NMOS) transistor having a diode connection structure, the NMOS transistor having a drain to source path connected between the first node and a point of reference potential, the assist circuit adjusting a word line voltage of a word line among the plurality of word lines by performing voltage pull-down for the first node.

US Pat. No. 10,431,271

APPARATUSES AND METHODS FOR PROVIDING AN INDICATOR OF OPERATIONAL READINESS OF VARIOUS CIRCUITS OF A SEMICONDUCTOR DEVICE FOLLOWING POWER UP

Micron Technology, Inc., ...

17. An apparatus, comprising:a supply voltage detection circuit configured to receive a supply voltage and further configured to provide a power up signal responsive to the supply voltage; and
a power supply ready circuit coupled to the first circuit, the second circuit configured to provide a ready detect signal that is active to a control circuit that enables a third circuit when the first signal is active.

US Pat. No. 10,431,270

APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus comprising:first and second memory access lines;
a memory cell coupled to the first and second memory access lines and configured to have a threshold voltage; and
memory access circuits coupled to the first and second memory access lines and configured to apply a pre-bias voltage across the memory cell by the first and second memory access lines,
wherein the pre-bias voltage is initially held constant and then increased and held constant until a ratio of the increased pre-bias voltage to the threshold voltage is above a threshold value.

US Pat. No. 10,431,269

METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MEMORY CIRCUITRY BY CONTROLLING PRECHARGE DURATION

Altera Corporation, San ...

1. A method of operating an integrated circuit, comprising:during a decode time period, using a decoder circuit to address a memory cell;
using a precharge circuit to precharge a bit line that is coupled to the memory cell;
keeping the precharge circuit turned off during the decode time period; and
after the bit line is precharged, asserting a word line signal to access the memory cell.

US Pat. No. 10,431,268

SEMICONDUCTOR DEVICE AND MEMORY CONTROLLER RECEIVING DIFFERENTIAL SIGNAL

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a differential signal phase detector configured to receive a differential signal comprising a first signal and a second signal, detect a phase between the first and second signals, and generate a mode control signal according to the phase detected; and
a receiver configured to receive the differential signal and, based on the mode control signal, perform a processing operation using the differential signal in a differential mode, or, perform a processing operation using the first signal and a reference voltage in a single mode.

US Pat. No. 10,431,267

ELECTRONIC DEVICE AND METHOD FOR DRIVING THE SAME

SK HYNIX INC., Icheon (K...

1. An electronic device comprising a semiconductor memory,wherein the semiconductor memory includes:
a memory circuit comprising a plurality of memory cells;
a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and
a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal, and
wherein the control circuit controls the read circuit to reread the data from the read target memory cell only when a value of the first read data signal corresponds to a high resistance state of the read target memory cell.

US Pat. No. 10,431,266

SEMICONDUCTOR STORAGE DEVICE

Toshiba Memory Corporatio...

1. A semiconductor storage device, comprising:a first terminal configured to output a signal to an external device;
a plurality of first output buffers and a plurality of second output buffers connected to the first terminal;
a register configured to retain a first signal corresponding to the plurality of second output buffers and a second signal corresponding to the plurality of first output buffers;
a plurality of first pre-drivers, each first pre-driver connected to one of the plurality of first output buffers, each first pre-driver including a plurality of first transistors connected in parallel between a first inverter and a ground voltage supply terminal, wherein the plurality of first transistors are configured to operate in accordance with values of the first signal;
a plurality of second pre-drivers, each second pre-driver connected to one of the plurality of second output buffers, each second pre-driver including a plurality of second transistors connected in parallel between a second inverter and a power voltage supply terminal, wherein the plurality of second transistors are configured to operate in accordance with values of the second signal;
a first output control circuit connected to the plurality of first pre-drivers through a plurality of first signal lines, the first output control circuit configured to select at least one of the plurality of first signal lines in accordance with values of a third signal corresponding to a conversion of the second signal;
a second output control circuit connected to the plurality of second pre-drivers through a plurality of second signal lines, the second output control circuit configured to select at least one of the plurality of second signal lines in accordance with values of a fourth signal corresponding to a conversion of the first signal; and
a third output control circuit configured to transmit an output signal to the first and second output control circuits.

US Pat. No. 10,431,265

ADDRESS FAULT DETECTION IN A FLASH MEMORY SYSTEM

SILICON STORAGE TECHNOLOG...

1. A flash memory system, comprising:a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row in the address fault detection array; and
a comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple word lines by the row decoder;
wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.

US Pat. No. 10,431,264

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. A system, comprising:a host configured to generate instructions; and
a memory device comprising an array of memory cells coupled to sensing circuitry comprising a sense amplifier and a compute component, wherein the memory device is configured to:
receive an instruction from the host; and
execute the instruction to perform at least one of a NAND operation and an AND operation using data values stored in the array as inputs by controlling the sensing circuitry without transferring data externally from the array and the sensing circuitry.

US Pat. No. 10,431,262

METHOD FOR CONTROLLING OPERATIONS OF MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF, AND ASSOCIATED ELECTRONIC DEVICE

Silicon Motion Inc., Hsi...

1. A method for controlling operations of a memory device, the memory device comprising a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the method comprising:before a voltage-drop event regarding a driving voltage occurs, respectively mapping a rising reference voltage and a falling reference voltage to a first reference voltage and a second reference voltage generated by a reference voltage generating circuit in the memory device, to respectively select the first reference voltage and the second reference voltage as the rising reference voltage and the falling reference voltage, wherein the memory device retrieves the driving voltage from a host device, the reference voltage generating circuit generates at least one portion of a plurality of candidate reference voltages, the at least one portion of the plurality of candidate reference voltages comprises the first reference voltage and the second reference voltage, and the first reference voltage is greater than the second reference voltage;
using a voltage detector in the memory device to monitor the driving voltage according to the second reference voltage selected as the falling reference voltage, to determine whether the voltage-drop event occurs;
when the voltage-drop event occurs, pausing at least one access operations to the NV memory, and respectively mapping the rising reference voltage and the falling reference voltage to another first reference voltage and another second reference voltage generated by the reference voltage generating circuit, to respectively select the another first reference voltage and the another second reference voltage as the rising reference voltage and the falling reference voltage, wherein the at least one portion of the plurality of candidate reference voltages comprises the another first reference voltage and the another second reference voltage, and the another first reference voltage is greater than the another second reference voltage;
using the voltage detector to monitor the driving voltage according to the another first reference voltage selected as the rising reference voltage, to determine whether the voltage-drop event ends; and
when the voltage-drop event ends, respectively mapping the rising reference voltage and the falling reference voltage to the first reference voltage and the second reference voltage, to respectively select the first reference voltage and the second reference voltage as the rising reference voltage and the falling reference voltage.

US Pat. No. 10,431,261

FLEXIBLE-MOUNT ELECTRICAL CONNECTION

Western Digital Technolog...

1. A flexible-mount electrical connection comprising:a mating connector configured to physically couple with a hard drive connector; and
a plurality of electrical pins that suspend the mating connector over a void in a printed circuit board (PCB), each electrical pin having:
a connector portion positioned within the mating connector configured to electrically couple with hard drive connector pins positioned within the hard drive connector; and
an extended portion extending externally away from the mating connector, the extended portion having:
an attachment portion configured to electrically couple the electrical pin to the PCB; and
a curved shape formed therein configured to reduce transmission of vibrations in the connector portion along each axis of a three-dimensional space to the attachment portion.

US Pat. No. 10,431,260

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD

Ricoh Company, Ltd., Tok...

1. An information processing apparatus comprising circuitry configured to:acquire time data relating to a state of an object in each process of an operation performed on the object, the operation including at least one process;
calculate an achievement value indicating a state of each process, based on the time data acquired;
compare the achievement value of each process with a reference value; and
generate a chart that visually represents a result of comparison for each process, the visual representation of the result of comparison being different according to the result of comparison.

US Pat. No. 10,431,258

APPARATUS AND METHODS FOR EMBEDDING METADATA INTO VIDEO STREAM

GoPro, Inc., San Mateo, ...

1. A system for generating a multimedia streaming file, the system comprising:information storage; and
one or more processors configured by computer instructions to:
obtain a series of images captured by an imaging sensor;
obtain information captured by one or more sensors other than the imaging sensor, the obtained information being relevant to one or more images within the series of images, the one or more sensors other than the imaging sensor including a first sensor;
generate an encoded video track that includes images from the series of images;
generate a sensor track that includes a first sensor record based on the obtained information;
generate a combined multimedia stream comprised of the encoded video track and the sensor track; and
store the combined multimedia stream in the information storage;
wherein:
the first sensor record comprises:
a header portion comprising a tag field comprising a sensor tag selected from potential sensor tags, the sensor tag identifying type of the obtained information;
a type size field comprising at least one of a value type field identifying a value type of a given value of the obtained information that is within the first sensor record; an item size field indicating size of the given value of the obtained information that is within the first sensor record; and/or a repeat field indicating a number of values of the obtained information that is within the first sensor record; and
a data portion comprising the values of the obtained information; and
wherein individual ones of the values of the obtained information correspond temporally to specific ones of the one or more images within the series of images.

US Pat. No. 10,431,257

DATA CENTER DUAL STAGE DRIVE WITH DATA STRIPING

KABUSHIKI KAISHA TOSHIBA,...

1. A disk drive comprising:a first magnetic head and a second magnetic head;
a voice-coil motor configured for coarse positioning of the first magnetic head and the second magnetic head;
a first microactuator coupled to the voice-coil motor and the first magnetic head;
a second microactuator coupled to the voice-coil motor and the second magnetic head; and
a controller configured to:
receive from a host device a write command that includes a set of data that has a first data block and a second data block;
select a first storage block disposed on a first disk surface for storing the first data block and a second storage block disposed on a second disk surface for storing the second data block;
position the first magnetic head over the first storage block with the voice-coil motor, the first microactuator, and a first servo controller and writing the first data block to the first storage block; and
position the second magnetic head over the second storage block with the voice-coil motor, the second microactuator, and a second servo controller and writing the second data block to the second storage block.

US Pat. No. 10,431,256

METHOD OF PERFORMING READ/WRITE PROCESS ON RECORDING MEDIUM, PARAMETER ADJUSTMENT METHOD, STORAGE DEVICE, COMPUTER SYSTEM, AND STORAGE MEDIUM EMPLOYING THE METHODS

Seagate Technology LLC, ...

11. A storage device comprising:a recording medium comprising a plurality of tracks, each of the plurality of tracks comprising a plurality of data sectors;
a media interface which writes information to, or reads information from, the recording medium by accessing the recording medium;
a processor which controls the media interface to write data to, or read data from, the plurality of data sectors of a target track of the recording medium; and
a memory containing code objects configured to cause the processor to
write test data to the plurality of data sectors of the target track,
read the test data from the plurality of data sectors of the target track,
count a total number of error-corrected error correcting code (“ECC”) symbols in the read of each of the plurality of data sectors,
determine whether the total number of error-corrected ECC symbols of a data sector exceeds a first threshold value,
upon determining that the total number of error-corrected ECC symbols exceeds the first threshold value, determining the data sector to be a defective sector,
analyze a distribution of defective data sectors on the target track to determine whether an area of the track containing the defective data sectors is greater than a second threshold,
upon determining that the area of the target track is greater than the second threshold, determine whether corresponding defective areas occur in one or more consecutive adjacent tracks of the target track, and
upon determining that corresponding defective areas occur in one or more consecutive adjacent tracks of the target track, determine the area of the target track and the corresponding areas of the one or more consecutive adjacent tracks including the defective data sectors to be a massive defective area.

US Pat. No. 10,431,255

MAGNETIC-TAPE STORAGE APPARATUS

UNITEX CORPORATION, Toky...

1. A magnetic-tape storage apparatus comprisinga housing;
a cartridge storage part provided in the housing to store a plurality of cartridges respectively having a wound magnetic tape and a memory chip which can be read contactlessly;
a magnetic tape drive provided in the housing to perform reading, writing and rewinding of each magnetic tape of the cartridges;
a cartridge transfer device provided in the housing to selectively transfer each of the cartridges stored in the cartridge storage part to the magnetic tape drive and to return the transferred cartridge to an original position;
a cartridge data reading device disposed on the cartridge transfer device to selectively and contactlessly read data retained in each memory chip of the cartridges stored in the cartridge storage part; and
a controller provided to the housing to control the magnetic tape drive and the cartridge transfer device so that a cartridge requiring rewriting is found based on the data read by the cartridge data reading device, and that a magnetic tape of the found cartridge is rewound;wherein each memory chip of the cartridges retains a rewinding history of the corresponding cartridge;wherein the cartridge storage part stores the cartridges aligned in the left-right direction on a base plate;wherein the cartridge transfer device comprisesa slide frame directed in the front-rear direction and provided in the housing so as to move in the left-right direction above or below the cartridges stored in the cartridge storage part,
a left-right moving device moving the slide frame in the left-right direction,
a slider mounted on the slide frame so as to move in the front-rear direction,
a front-rear moving device moving the slider in the front-rear direction along the slide frame,
an engaging member disposed on the slider and selectively engaging with/disengaging from a concavity formed on the top face of each of the cartridges stored in the cartridge storage part,
an engaging/disengaging driving device moving the engaging member between an engaged position at which the engaging member engages with the concavity of each of the cartridge and an disengaged position at which the engaging member disengages from the concavity, and
a moving receiving member integrally formed with the slide frame so as to be positioned behind the base plate, and receiving a cartridge moved to behind the base plate by engaging the engaging member with the concavity;and wherein the cartridge data reading device on the slide frame is disposed at a position facing to a memory chip of the cartridges stored in the cartridge storage part.

US Pat. No. 10,431,254

SYSTEM FOR PROVIDING AN ACCLIMATION ENCLOSURE FOR A DATA STORAGE LIBRARY

International Business Ma...

1. An enclosure configured to surround at least one library access opening that permits access to an interior of a data storage library, the enclosure comprising:a plurality of side wall panels configured to surround the data storage library and the at least one library access opening, wherein at least one of the plurality of side wall panels is configured to permit access to the at least one library access opening of the data storage library;
at least one top panel coupled to the plurality of side wall panels and disposed over a top surface of the data storage library so as to enclose the data storage library to form a chamber around the data storage library;
a plurality of top side panels coupled to the plurality of side wall panels and the at least one top panel, wherein each of the top side panels is configured to extend only to at least one environmental conditioning unit enclosure coupled to the top surface of the data storage library such that waste heat generated by at least one environmental conditioning unit within the at least one environmental conditioning unit enclosure is not captured within the enclosure;
at least one enclosure access opening in the at least one of the plurality of side wall panels to permit access to an interior of the chamber; and
at least one vent formed in at least one of the plurality of side wall panels, wherein the at least one vent is separate from the at least one enclosure access opening, and further wherein the at least one vent is configured to selectively allow ambient external air from outside the enclosure to intrude into the chamber,
wherein the enclosure is configured to selectively permit environmental conditions within the chamber to acclimate between environmental conditions outside the enclosure and environmental conditions within the data storage library.

US Pat. No. 10,431,253

WAVEGUIDE INPUT COUPLER WITH ASYMMETRIC TAPER

Seagate Technology, LLC, ...

1. An apparatus comprising:an input waveguide disposed on a substrate-parallel plane and configured to receive light from an input surface of the apparatus;
a mode converter joining the input waveguide at a junction away from the input surface, the mode converter converting the light from a fundamental mode to a higher-order mode; and
an input coupler proximate to and overlapping the mode converter parallel to the substrate-parallel plane and offset therefrom in a downtrack direction, the input coupler extending from the input surface to an output end of the mode converter and comprising first and second edges forming an asymmetric taper that transitions from a wider crosstrack dimension near the input surface to a narrower crosstrack dimension away from the input surface, the mode converter located between the first and second edges.

US Pat. No. 10,431,252

SUBSTRATE FOR MAGNETIC DISK AND MAGNETIC DISK

HOYA CORPORATION, Tokyo ...

1. An annular substrate to be polished for manufacturing a magnetic-disk substrate having a circular hole at a center, and comprising a pair of main surfaces and a side wall surface orthogonal to the main surfaces,a roundness of the circular hole being 1.5 ?m or less,
in the side wall surface of the circular hole, three outlines in a circumferential direction of the side wall surface, which include an outline at a center position of a thickness of the substrate and outlines at two positions that are spaced apart from the center position in opposite directions along a substrate thickness direction by a predetermined distance, being obtained,
a difference between a maximum value and a minimum value of radii of three inscribed circles that are respectively derived from the three outlines being 3.5 ?m or less, and
when positions spaced apart from the center position in the opposite directions along the substrate thickness direction by 200 ?m exist on the side wall surface, the predetermined distance being 200 ?m, and when positions spaced apart from the center position in the opposite directions of the substrate thickness direction by 200 ?m do not exist on the side wall surface, the predetermined distance being 100 ?m,
a substrate thickness of the annular substrate being 0.8 mm or less.

US Pat. No. 10,431,251

MAGNETIC TAPE DEVICE AND MAGNETIC REPRODUCING METHOD

FUJIFILM Corporation, To...

1. A magnetic tape device comprising:a magnetic tape; and
a reproducing head,
wherein the reproducing head is a magnetic head including a tunnel magnetoresistance effect type element as a reproducing element,
the magnetic tape includes a non-magnetic support, and a magnetic layer including ferromagnetic powder, a binding agent, and fatty acid ester on the non-magnetic support,
a center line average surface roughness Ra measured regarding a surface of the magnetic layer is equal to or smaller than 2.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer before performing a vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a difference Safter?Sbefore between a spacing Safter measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape and a spacing Sbefore measured by optical interferometry regarding the surface of the magnetic layer before performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 8.0 nm, and
?SFD in a longitudinal direction of the magnetic tape calculated by Expression 1 is equal to or smaller than 0.50,
?SFD=SFD25° C.?SFD?190° C.  Expression 1
in Expression 1, the SFD25° C. is a switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of 25° C., and the SFD?190° C. is a switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of ?190° C.

US Pat. No. 10,431,250

MAGNETIC TAPE HAVING CHARACTERIZED MAGNETIC LAYER

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support,
wherein the center line average surface roughness Ra measured regarding the surface of the magnetic layer is equal to or smaller than 1.8 nm,
the logarithmic decrement acquired by a pendulum viscoelasticity test performed regarding the surface of the magnetic layer is 0.010 to 0.050,
?SFD in a longitudinal direction of the magnetic tape calculated by Expression 1 is equal to or greater than 0.35,
?SFD=SFD25° C.?SFD?190° C.  Expression 1
in Expression 1, the SFD25° C. is the switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of 25° C., and the SFD?190° C. is the switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of ?190° C., and
the logarithmic decrement on the magnetic layer side is determined by the following method:
securing a measurement sample of the magnetic tape with the measurement surface, which is the surface on the magnetic layer side, facing upward on a substrate in a pendulum viscoelasticity tester;
disposing a columnar cylinder edge which is 4 mm in diameter and equipped with a pendulum 13 g in weight on the measurement surface of the measurement sample such that the long axis direction of the columnar cylinder edge runs parallel to the longitudinal direction of the measurement sample;
raising the surface temperature of the substrate on which the measurement sample has been positioned at a rate of less than or equal to 5° C./min up to 80° C.;
inducing initial oscillation of the pendulum;
monitoring the displacement of the pendulum while it is oscillating to obtain a displacement-time curve for a measurement interval of greater than or equal to 10 minutes; and
obtaining the logarithmic decrement ? from the following equation:

wherein the interval from one minimum displacement to the next minimum displacement is adopted as one wave period; the number of waves contained in the displacement-time curve during one measurement interval is denoted by n, the difference between the minimum displacement and the maximum displacement of the nth wave is denoted by An, and the logarithmic decrement is calculated using the difference between the next minimum displacement and maximum displacement of the nth wave (An+1 in the above equation).

US Pat. No. 10,431,247

MAGNETIC HEAD CONTROL CAPABLE OF AVOIDANCE MEDIA BUMPS DURING SEEKING PROCESS

Kabushiki Kaisha Toshiba,...

1. A magnetic disk drive comprising:a selector selecting a plurality of evaluation commands in order in a command reordering operation;
a determiner determining whether media bumps which influence a dynamic flying height (DFH) control exist in a seek section between completion of a previous command and start of a selected evaluation command or not; and
a calculator calculating a delay time necessary for avoidance of the media bumps if it is determined by the determiner that the media bumps which influence the dynamic flying height (DFH) control exist; wherein
the reordering operation compares a latency time which is obtained by summing a seek time which is determined in accordance with a seek distance, a rotational latency time which is determined after a seek completion and the delay time of each of a plurality of evaluation commands, and selects the evaluation command of the shortest latency time as the command to be next processed.

US Pat. No. 10,431,245

PIEZOELECTRIC ELEMENT HAVING POLYMER COATING, PIEZOELECTRIC ACTUATOR USING SAID PIEZOELECTRIC ELEMENT, AND HEAD SUSPENSION USING SAID PIEZOELECTRIC ACTUATOR

NHK Spring Co., Ltd., Ka...

1. A piezoelectric element, comprising:an element body configured to deform, so as to elongate and contract along a deformation direction, in response to a voltage applied thereto;
electrodes formed on opposite sides of the element body;
peripheral end faces defining a peripheral shape of the element body; and
polymer coatings formed by vapor deposition polymerization to have first portions and second portions, the first portions coating at least respective opposite end faces of the peripheral end faces of the element body in an orthogonal direction relative to the deformation direction, and the second portions continuously extending from the first portions and located on respective side portions of one of the electrodes in said orthogonal direction to coat the side portions of said one of the electrodes so that said one of the electrodes has an exposed portion exposing outside at a middle portion defined in said orthogonal direction between the side portions that are covered with the second portions of polymer coatings.

US Pat. No. 10,431,244

DEVICES INCLUDING A NEAR FIELD TRANSDUCER (NFT) INCLUDING PEG AND DISC FROM DIFFERENT MATERIALS

Seagate Technology LLC, ...

1. A device having an air bearing surface (ABS), the device comprising:a near field transducer (NFT) comprising:
a disc configured to convert photons incident thereon into plasmons; and
a peg configured to couple plasmons coupled from the disc into an adjacent magnetic storage medium,
wherein the peg extends beyond the disc, and the peg comprises rhodium (Rh), aluminum (Al), iridium (Ir), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), alloys thereof, or combinations thereof and
wherein the disc comprises a disc material comprising gold or a gold alloy and the peg comprises a peg material, wherein the disc material is different from the peg material.

US Pat. No. 10,431,243

SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, SIGNAL PROCESSING PROGRAM

NEC CORPORATION, Tokyo (...

4. A signal processing method implemented using a signal processing apparatus, the method comprising:transforming, by the signal processing apparatus, input signal samples into frames of amplitude components representing different frequencies in a frequency domain;
smoothing, by the signal processing apparatus, the amplitude components along time to obtain time-smoothed amplitude components,
smoothing, by the signal processing apparatus, the time-smoothed amplitude components along frequency to obtain frequency-smoothed amplitude components;
calculating, by the signal processing apparatus, differences of the frequency-smoothed amplitude components along the frequency;
accumulating, by the signal processing apparatus, the differences to obtain an accumulated value; and
analyzing, by the signal processing apparatus, the input signal samples to detect a male voice in accordance with the accumulated value.

US Pat. No. 10,431,242

SYSTEMS AND METHODS FOR IDENTIFYING SPEECH BASED ON SPECTRAL FEATURES

GoPro, Inc., San Mateo, ...

1. A system that identifies speech, the system comprising:one or more physical processors configured by machine-readable instructions to:
access audio information defining audio content, the audio content having a duration;
segment the audio content into audio segments, individual audio segments corresponding to a portion of the duration, the audio segments including a first audio segment corresponding to a first portion of the duration;
determine energy features of the audio segments, the energy features characterizing energy of the audio segments, the energy features including a first energy feature of the first audio segment;
determine entropy features of the audio segments, the entropy features characterizing spectral flatness of the audio segments, the entropy features including a first entropy feature of the first audio segment;
determine frequency features of the audio segments, the frequency features characterizing highest frequencies of the audio segments, the frequency features including a first frequency feature of the first audio segment;
identify one or more of the audio segments as containing speech based on the energy features, the entropy features, and the frequency features by generating a binary curve indicating the one or more of the audio segments as containing speech, wherein the first audio segment is identified as containing speech based on the first energy feature, the first entropy feature, and the first frequency feature, wherein the binary curve is smoothed based on a number of silent audio segments; and
effectuate storage of the identification of the one or more of the audio segments as containing speech in a storage medium.

US Pat. No. 10,431,241

SPEECH ENHANCEMENT METHOD AND APPARATUS FOR SAME

SAMSUNG ELECTRONICS CO., ...

1. An electronic device comprising:a plurality of microphones disposed on an upper part of the electronic device;
a processor configured to:
operate in a first mode, in which an estimation of a direction of a user and a beamforming operation based on the estimated direction are deactivated, to:
receive at least one signal from any one or any combination of the plurality of microphones; and
determine whether the received at least one signal is associated with a speech of the user to activate the deactivated estimation of the direction and the deactivated beamforming operation;
based on the at least one signal being determined to be associated with the speech of the user, operate in a second mode, in which the estimation of the direction and the beamforming operation are activated, to:
estimate the direction of the user, based on a difference between at least two of a plurality of signals that is received from at least two of the plurality of microphones; and
based at least on the estimated direction, beamform the received plurality of signals such that at least one of the plurality of signals from the estimated direction is emphasized and at least another one of the plurality of signals is suppressed; and
output the plurality of beamformed signals to perform speech recognition based on the plurality of beamformed signals.

US Pat. No. 10,431,240

SPEECH ENHANCEMENT METHOD AND SYSTEM

Samsung Electronics Co., ...

1. A speech enhancement method comprising:receiving at least one speech signal;
generating a first speech signal by performing a primary speech enhancement on the at least one speech signal;
selecting a noise removing gain corresponding to the first speech signal from pre-learned noise removing gain information; and
generating a second speech signal by performing a secondary speech enhancement on the first speech signal based on the selected noise removing gain,
wherein the selecting of the noise removing gain comprises:
obtaining an a priori signal-to-noise ratio (SNR) and an a posteriori SNR regarding the first speech signal; and
selecting the noise removing gain corresponding to the a priori SNR and the a posteriori SNR, from among a plurality of noise removing gains included in the pre-learned noise removing gain information.

US Pat. No. 10,431,239

HEARING SYSTEM

1. A binaural hearing aid system comprising a first hearing aid device configured to be worn at, behind and/or in an ear of a user, and a second hearing aid device configured to be worn at, behind and/or in an ear of a user, wherein the first hearing aid device comprises:a direction sensitive input sound transducer unit configured to convert acoustical sound signals into electrical noisy sound signals,
a wireless sound receiver unit configured to receive wireless sound signals from a remote device, the wireless sound signals representing noiseless electrical sound signals,
and
a memory storing sets of head related impulse responses for different positions relative to the direction sensitive input transducer unit,
wherein a processing unit is configured to estimate the direction to an active source, and the processing unit configured to map the electrical noisy sound signals and the wireless sound signals into binaural electrical output signals by convolving the noiseless electrical sound signals with the set of the head related impulse responses stored in the memory in correspondence with the estimated sound source location.

US Pat. No. 10,431,238

MEMORY AND COMPUTATION EFFICIENT CROSS-CORRELATION AND DELAY ESTIMATION

Apple Inc., Cupertino, C...

1. A memory-efficient and computation-efficient cross-correlator for audio signals, comprising:a first array in memory;
a second array in memory;
a cross-correlation array in memory;
a processor configured to receive a first audio signal, partition a first segment of the first audio signal into a first plurality of shorter segments, combine the first plurality of shorter segments into a first combined segment that is less than a size of the first segment, and write the first combined segment into the first array;
the processor configured to receive a second audio signal, partition a second segment of the second audio signal into a second plurality of shorter segments, and combine the second plurality of shorter segments into a second combined segment that is less than a size of the second segment, and write the second combined segment into the second array; and
the processor configured to cross-correlate the first combined segment, from the first array, and the second combined segment, from the second array, into a cross-correlation result and write the cross-correlation result into the cross-correlation array.

US Pat. No. 10,431,237

DEVICE AND METHOD FOR ADJUSTING SPEECH INTELLIGIBILITY AT AN AUDIO DEVICE

MOTOROLA SOLUTIONS, INC.,...

1. A device comprising:a microphone;
a transmitter; and
a controller having access to a memory storing a plurality of preconfigured voice tags associated with respective noise levels, each of the plurality of preconfigured voice tags comprising a respective voice recording of a given user,
the controller configured to:
determine a noise level at the microphone;
select a voice tag, of the plurality of preconfigured voice tags, based on the noise-level;
determine an intelligibility rating of a mix of the voice tag and noise received at the microphone; and
when the intelligibility rating is below a threshold intelligibility rating, enhance speech from the given user received at the microphone based on the intelligibility rating prior to transmitting, at the transmitter, a signal representing intelligibility enhanced speech.

US Pat. No. 10,431,236

DYNAMIC PITCH ADJUSTMENT OF INBOUND AUDIO TO IMPROVE SPEECH RECOGNITION

Sphero, Inc., Boulder, C...

1. A system for dynamically adjusting the pitch of inbound audio, comprising:at least one processor; and
memory encoding computer executable instructions that, when executed by the at least one processor, perform a method comprising:
receiving an input audio segment;
detecting one or more clusters of speech input within the input audio segment;
detecting an average pitch for at least one of the one or more clusters of speech input;
determining, based on at least the average pitch and an expected content for the input audio segment, whether the pitch of the input audio segment should be adjusted;
based on determining that the pitch should be adjusted, adjusting the pitch of at least one of the one or more speech clusters to generate an adjusted audio segment; and
transmitting the adjusted audio segment to a speech recognition component.

US Pat. No. 10,431,235

METHODS AND SYSTEMS FOR SPEECH ADAPTATION DATA

Elwha LLC, Bellevue, WA ...

1. A method for controlling a computer processor to perform operations comprising:detecting speech data of a particular party at a personal device of the particular party, the speech data being related to a speech-facilitated interaction of the particular party with a target device;
acquiring at the personal device adaptation data that is at least partly based on at least one previous speech interaction of the particular party;
converting the speech data at the personal device into converted data based at least partly on feedback from the target device at least indicating that the target device is able to process the converted data more quickly than the speech data; and
transmitting the adaptation data and the converted data from the personal device to the target device to facilitate speech recognition.

US Pat. No. 10,431,234

DEVICE AND METHOD FOR TRANSMITTING AND RECEIVING VOICE DATA IN WIRELESS COMMUNICATION SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. An operating method of a transmission terminal for transmitting an audio signal, the method comprising:generating bandwidth information indicating a first bandwidth range, and bit rate information indicating a first bit rate range;
transmitting the bandwidth information indicating a first bandwidth range and the bit rate information indicating a first bit rate range to a reception terminal;
receiving combination determination information from the reception terminal;
compressing the audio signal according to the received combination determination information; and
transmitting the compressed audio signal to the reception terminal,
wherein the combination determination information is determined based on bandwidth information indicating a second bandwidth range, and bit rate information indicating a second bit rate range, by the reception terminal, and
wherein the second bandwidth range is comprised in the first bandwidth range, and the second bit rate range is comprised in the first bit rate range.

US Pat. No. 10,431,233

METHODS, ENCODER AND DECODER FOR LINEAR PREDICTIVE ENCODING AND DECODING OF SOUND SIGNALS UPON TRANSITION BETWEEN FRAMES HAVING DIFFERENT SAMPLING RATES

VoiceAge EVS LLC, Newpor...

1. A method for encoding a sound signal, comprising:sampling the sound signal during successive sound signal processing frames;
producing, in response to the sampled sound signal, parameters for encoding the sound signal during the successive frames, wherein the sound signal encoding parameters include linear predictive (LP) filter parameters, wherein producing the LP filter parameters comprises, upon switching from a first one of the frames using an internal sampling rate S1 to a second one of the frames using an internal sampling rate S2, converting LP filter parameters from the first frame from the internal sampling rate S1 to the internal sampling rate S2, and wherein converting the LP filter parameters from the first frame comprises:
computing, at the internal sampling rate S1, a power spectrum of a LP synthesis filter using the LP filter parameters;
modifying the power spectrum of the LP synthesis filter to convert it from the internal sampling rate S1 to the internal sampling rate S2 based on a ratio between the internal sampling rates S1 and S2;
inverse transforming the modified power spectrum of the LP synthesis filter to determine autocorrelations of the LP synthesis filter at the internal sampling rate S2; and
using the autocorrelations to compute the LP filter parameters at the internal sampling rate S2; and
encoding the sound signal encoding parameters into a bitstream.

US Pat. No. 10,431,232

APPARATUS AND METHOD FOR SYNTHESIZING AN AUDIO SIGNAL, DECODER, ENCODER, SYSTEM AND COMPUTER PROGRAM

Fraunhofer-Gesellschaft z...

1. An apparatus for synthesizing an audio signal, comprising:a processing unit configured to apply a spectral tilt to the code of a codebook used for synthesizing a current frame of the audio signal,
wherein the spectral tilt is based on the spectral tilt of the current frame of the audio signal,
wherein the apparatus is configured to determine the spectral tilt of the current frame of the audio signal on the basis of spectral envelope information for the current frame of the audio signal,
wherein the processing unit is configured to apply the spectral tilt by filtering the code from the codebook based on a transfer function modeling the spectral tilt, and
wherein the processing unit comprises a hardware implementation.

US Pat. No. 10,431,231

HIGH-BAND RESIDUAL PREDICTION WITH TIME-DOMAIN INTER-CHANNEL BANDWIDTH EXTENSION

Qualcomm Incorporated, S...

1. A device comprising:a low-band mid signal decoder configured to decode a low-band portion of an encoded mid signal to generate a decoded low-band mid signal;
a low-band residual prediction unit configured to process the decoded low-band mid signal to generate a low-band residual prediction signal;
an up-mix processor configured to generate a low-band left channel and a low-band right channel based partially on the decoded low-band mid signal and the low-band residual prediction signal;
a high-band mid signal decoder configured to decode a high-band portion of the encoded mid signal to generate a time-domain decoded high-band mid signal;
a high-band residual prediction unit configured to process the time-domain decoded high-band mid signal to generate a time-domain high-band residual prediction signal; and
an inter-channel bandwidth extension decoder configured to generate a high-band left channel and a high-band right channel based on the time-domain decoded high-band mid signal and the time-domain high-band residual prediction signal.

US Pat. No. 10,431,230

DOWNSCALED DECODING

Fraunhofer-Gesellschaft z...

1. An audio decoder configured to decode an audio signal at a first sampling rate from a data stream into which the audio signal is transform coded at a second sampling rate, the first sampling rate being 1/Fth of the second sampling rate, the audio decoder comprising:a receiver configured to receive, per frame of length N of the audio signal, N spectral coefficients;
a grabber configured to grab-out for each frame, a low-frequency fraction of length N/F out of the N spectral coefficients;
a spectral-to-time modulator configured to subject, for each frame, the low-frequency fraction to an inverse transform comprising modulation functions of length (E+2)·N/F temporally extending over the respective frame and E+1 previous frames so as to acquire a temporal portion of length (E+2)·N/F;
a windower configured to window, for each frame, the temporal portion using a synthesis window of length (E+2)·N/F comprising a zero-portion of length ¼·N/F at a leading end thereof and comprising a peak within a temporal interval of the synthesis window, the temporal interval succeeding the zero-portion and comprising length 7/4·N/F so that the windower acquires a windowed temporal portion of length (E+2)·N/F; and
a time domain aliasing canceler configured to subject the windowed temporal portion of the frames to an overlap-add process so that a trailing-end fraction of length (E+1)/(E+2) of the windowed temporal portion of a current frame overlaps a leading end of length (E+1)/(E+2) of the windowed temporal portion of a preceding frame,
wherein the inverse transform is an inverse MDCT or inverse MDST, and
wherein the synthesis window is a downsampled version of a reference synthesis window of length (E+2)·N, downsampled by a factor of F by a segmental interpolation in segments of length ¼·N.

US Pat. No. 10,431,229

DEVICES AND METHODS FOR ENCODING AND DECODING AUDIO SIGNALS

Sony Corporation, Tokyo ...

1. A signal processing device comprising:an extracting unit that extracts a low frequency component of an audio signal, envelope information representing an envelope of a high frequency component of the audio signal, and sine wave information which includes information representing a distance from a start position of a frame of the high frequency component to an appearance start position of a sine wave component included in the high frequency component, and is for specifying a frequency and an appearance position of the sine wave component;
a pseudo high frequency generating unit that generates a pseudo high frequency signal configuring the high frequency component on the basis of a low frequency signal as the low frequency component and the envelope information;
a sine wave generating unit that generates a sine wave signal which is at a frequency represented by the sine wave information and in which the appearance start position specified from the sine wave information is set as a start position within a frame; and
a combining unit that combines the low frequency signal, the pseudo high frequency signal, and the sine wave signal to generate an audio signal.

US Pat. No. 10,431,228

PROVING FILE OWNERSHIP

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:receiving a first digital fingerprint;
using first and second information unpredictable to another system to modify a digital representation of an instance of content to result in a modified digital representation of the instance of content, wherein the modified digital representation is generated by permutating segments of the digital representation of the instance of content based on the first information, wherein a size of the segments of the digital representation of the instance of content is determined based on the second information;
calculating, based at least in part on the modified digital representation of the instance of content, a second digital fingerprint using a fingerprinting algorithm configured to produce matching digital fingerprints from different digital encodings of the same content;
verifying that the first digital fingerprint matches the second digital fingerprint; and
performing one or more operations corresponding to the first digital fingerprint matching the second digital fingerprint, wherein the one or more operations include providing access to the content.

US Pat. No. 10,431,227

MULTI-CHANNEL AUDIO DECODER, MULTI-CHANNEL AUDIO ENCODER, METHODS, COMPUTER PROGRAM AND ENCODED AUDIO REPRESENTATION USING A DECORRELATION OF RENDERED AUDIO SIGNALS

Fraunhofer-Gesellschaft z...

1. A multi-channel audio encoder for providing an encoded representation on the basis of at least two input audio signals,wherein the multi-channel audio encoder comprises a downmix signal provider configured to provide an encoded representation of one or more downmix signals on the basis of the at least two input audio signals, and
wherein the multi-channel audio encoder comprises a parameter provider configured to provide one or more parameters describing a relationship between the at least two input audio signals, and
wherein the multi-channel audio encoder comprises a decorrelation method parameter provider configured to provide a decorrelation method parameter describing which decorrelation mode out of a plurality of decorrelation modes should be used at the side of an audio decoder;
wherein the decorrelation method parameter provider is configured to selectively provide the decorrelation method parameter, to signal one out of the following modes for the operation of an audio decoder:
a first mode in which no mixing between different rendered audio signals is allowed when combining the rendered audio signals, or a scaled version thereof, with the one or more decorrelated audio signals, and in which it is allowed that a given decorrelated signal of the one or more decorrelated audio signals is combined, with same or different scaling, with a plurality of the rendered audio signals, or a scaled version thereof, in order to adjust cross-correlation characteristics or cross-covariance characteristics of the output audio signals, and
a second mode in which no mixing between the different rendered audio signals is allowed when combining the rendered audio signals, or a scaled version thereof, with the one or more decorrelated audio signals, and in which it is not allowed that the given decorrelated signal is combined with rendered audio signals other than a rendered audio signal from which the given decorrelated signal is derived.