US Pat. No. 10,432,027

MOVABLE PORTION TRANSMISSION SYSTEM USING WIRELESS POWER TRANSMISSION

MITSUBISHI ELECTRIC ENGIN...

1. A movable portion transmission system using wireless power transmission which is performed via a rotary member, said movable portion transmission system comprising:a primary transmission power supply to supply electric power;
a transmission antenna to perform wireless transmission of the electric power from the primary transmission power supply; and
a reception antenna to receive the electric power from the transmission antenna;
wherein the transmission antenna includes a transmission side coil in a spiral shape having successive conductor turns arranged along a same axial plane of the rotary member and each of the successive conductor turns has different diameters, a center of the spiral shape of the transmission side coil being an axial center of the rotary member, and the reception antenna includes a reception side coil in a spiral shape having successive conductor turns arranged along the same axial plane and each of the successive conductor turns has different diameters, a center of the spiral shape of the reception side coil being the axial center of the rotary member, wherein
a plurality of sets each having the transmission antenna and the reception antenna are disposed, and are arranged at intervals along a direction of the axial center of the rotary member.

US Pat. No. 10,432,026

PRIMARY-SIDE POWER CONTROL FOR INDUCTIVE POWER TRANSFER

Auckland UniServices Limi...

1. A method of controlling an output voltage of a pickup in an inductive power transfer (IPT) system comprising the pickup, a power supply, and a primary conductive path, the method comprising steps of:deriving an estimate of the output voltage of the pickup from a real component of a voltage across the primary conductive path; and
adjusting a current in the primary conductive path so that the estimated pickup output voltage matches a required pickup output voltage, by controlling a voltage supplied to the primary conductive path by the power supply.

US Pat. No. 10,432,021

EMERGENCY INVERTER AND EMERGENCY LIGHTING SYSTEM

SIGNIFY HOLDING B.V., Ei...

1. An emergency inverter configured to provide an output power to a plurality of device drivers, comprising:a power detection module configured to detect an output current and an output voltage, and, based on the output current and output voltage, determine the total output power of the emergency inverter in an emergency state; and
a dimming signal generating module coupled to the power detection module and configured to generate a dimming signal based on the total output power of the emergency inverter in the emergency state;
wherein the dimming signal generating module is configured to generate the dimming signal in response to the total output power being detected by the power detection module as greater than a rated power of the emergency inverter and to send the dimming signal to the plurality of device drivers to instruct an adjustment of a power level of the plurality of device drivers, wherein the emergency inverter is configured to set the total output power in response to the power level of the plurality of device drivers, and wherein the emergency inverter is configured enable mains power to be provided as the output power when in a non-emergency state and to impose the rated power when the emergency inverter is in the emergency state.

US Pat. No. 10,432,018

POWER SUPPLY BUS CIRCUIT

HUAWEI TECHNOLOGIES CO., ...

1. A power supply bus circuit comprising a high-voltage power supply circuit, wherein the high-voltage power supply circuit comprises:at least two alternating current/direct current (AC/DC) converters, wherein each of the AC/DC converters comprises a power grid feedback circuit;
at least two high-voltage direct current (HVDC) power supply buses, wherein each of the HVDC power supply buses is electrically coupled to a separate AC/DC converter of the at least two AC/DC converters;
at least one high-voltage backup power supply electrically coupled to at least one of the HVDC power supply buses; and
at least one direct current/direct current (DC/DC) converter,
wherein each of the AC/DC converters comprises a corresponding mains end,
wherein a first AC/DC converter of the AC/DC converters is electrically coupled to one HVDC power supply bus of the HVDC power supply buses,
wherein the first AC/DC converter is configured to:
connect to mains using a first mains end of the AC/DC converter;
adjust the alternating current at the mains into a direct current; and
output the direct current to a first HVDC power supply bus,
wherein the first HVDC power supply bus is electrically coupled to the first AC/DC converter,
wherein the power grid feedback circuit is configured to:
receive the direct current from the first HVDC power supply bus when the high-voltage backup power supply discharges;
invert the direct current into an alternating current; and
output the alternating current through the first mains end of the first AC/DC converter,
wherein a first DC/DC converter is electrically coupled between two of the HVDC power supply buses, and
wherein the first DC/DC converter is configured to perform voltage conversion on the direct current between the two HVDC power supply buses that are coupled to the first DC/DC converter so as to implement mutual backup of power supplies between the two HVDC power supply buses.

US Pat. No. 10,432,011

CHARGE-DISCHARGE CONTROL APPARATUS AND CHARGE-DISCHARGE CONTROL APPARATUS METHOD

TOSHIBA TEC KABUSHIKI KAI...

1. A charge-discharge control apparatus, comprising:a power-feeding device including:
an inverter circuit,
a primary coil, a voltage output from the inverter circuit being applied to the primary coil,
a current detector circuit that detects a current output from the inverter circuit and flowing in the primary coil, and
an over-discharge suppression controller circuit;
a power-receiving device including:
a secondary coil that receives power supplied from the primary coil without contacting the primary coil, and
a rectifier circuit that supplies the received power to a load to operate the load and a battery to charge the battery; and
a rectifier-voltage decrease detector circuit that detects that a voltage output from the rectifier circuit decreases to below a predetermined voltage value, wherein
the over-discharge suppression controller circuit is configured to:
determine if the current detected by the current detector circuit exceeds a predetermined current value,
when the current detected by the current detector circuit is determined to exceed the predetermined current value, determine if the rectifier-voltage decrease detector circuit detects that the voltage output from the rectifier circuit has decreased below the predetermined voltage value, and
control the inverter circuit to suppress over-discharge when the rectifier-voltage decrease detector detects that the voltage output from the rectifier circuit decreases below the predetermined voltage.

US Pat. No. 10,432,004

AUXILIARY POWER SYSTEM MOUNTED IN A VEHICLE

OX PARTNERS, LLC, Wilson...

13. A method, comprising:detecting, by an auxiliary power system mounted within a vehicle, a trigger event;
coupling, by the auxiliary power system, an auxiliary battery of the auxiliary power system to a vehicle electrical system of the vehicle, the auxiliary battery providing power to the vehicle electrical system for starting an engine of the vehicle, the vehicle including a starter battery in electrical connection with the vehicle electrical system;
providing, from the auxiliary battery, power to the vehicle electrical s stem to start the engine upon detection of the trigger event; and
drawing, independent from providing power to the vehicle electrical system, power from the vehicle electrical system to charge the auxiliary battery.

US Pat. No. 10,431,998

SUB FOR A PIPE ASSEMBLY AND SYSTEM AND METHOD FOR USE OF SAME

1. A sub for a pipe assembly, the sub comprising:a mandrel having a body section including an internal flow passage that extends generally axially through the mandrel from an upper connection end to a lower connection end;
a recessed region within the mandrel;
a battery charger including an enclosed chamber, the battery charger being disposed in the recessed region;
a pair of capacitors located within the battery charger, each of the pair of capacitors including opposing spaced plates having contact segments thereon, the opposing spaced plates including electret;
an output power increasing, electrically resistive fluid held within the enclosed chamber, the output power increasing, electrically resistive fluid partially filling the enclosed chamber such that a fluid motion varies a fluid-contact segment contact within the enclosed chamber;
in response to a movement of the sub, an induced relative motion between the output power increasing, electrically resistive fluid and contact segments varies the fluid-contact segment contact within the enclosed chamber, thereby inversely alternating the capacitance between the pair of capacitors and triboelectrically generating an electrical charge;
an electronic circuit coupled to the opposing spaced plates of the pair of capacitors, the electronic circuit configured to transfer the electrical charge to a battery associated with the mandrel; and
a moveable element disposed within the enclosed chamber, the moveable element being an output power increasing, electrically resistive object partially filling the enclosed chamber such that motion of the moveable element varies a moveable element-contact segment contact within the enclosed chamber, thereby inversely alternating the capacitance between the pair of capacitors and triboelectrically generating the electrical charge.

US Pat. No. 10,431,994

SELF-CONTAINED EVCS DISPLAY

Schneider Electric USA, I...

1. An accessory for an electric vehicle charging station, comprising:a housing separate from and external to the electric vehicle charging station, the housing being composed of a first clamp member and a second clamp member configured to clamp around a power cord of the electric vehicle charging station;
a display unit mounted on the housing and configured to display detailed charging information related to an electric vehicle charging process in near real time;
a processor within the housing and connected to the display unit, the processor configured to provide the detailed charging information to the display unit; and
a current sense circuit within the housing and connected to the processor, the current sense circuit including a split core transformer configured to provide the processor with a signal indicative of an amount of electric current being supplied by the electric vehicle charging station through the power cord in near real time during the electric vehicle charging process, the split core transformer having a first transformer core portion mounted within the first clamp member, a second transformer core portion mounted within the second clamp member, and a hinge assembly holding the first transformer core portion and the second transformer core portion together;
wherein the processor is further configured to determine at least a portion of the detailed charging information provided to the display unit using the signal provided by the current sense circuit; and
wherein the housing of the accessory is a clamp configured to be clamped around the power cord of the electric vehicle charging station.

US Pat. No. 10,431,987

METHODS AND SYSTEMS FOR MAINTAINING PHOTOVOLTAIC POWER PLANT REACTIVE POWER CAPABILITY

SUNPOWER CORPORATION, Sa...

1. A control system comprising:a monitor input for receiving a monitor signal indicative of an input voltage of an inverter system, wherein the inverter system is configured to provide a specified amount of reactive power to a point of interconnection with an electric grid;
a control output for outputting a control signal to a voltage-clipping device of a solar panel system supplying a solar output voltage to the inverter system; and
a control circuit configured to perform operations comprising:
determining, using the monitor signal, that the input voltage of the inverter system exceeds a threshold voltage; and
in response to determining that the input voltage of the inverter system exceeds the threshold voltage, causing, using the control signal, the voltage-clipping device to reduce the solar output voltage by shorting out one or more photovoltaic solar cells of the solar panel system, wherein the threshold voltage is selected so that reducing the solar output voltage reduces the input voltage of the inverter system below an inverter threshold at which, if exceeded, the inverter system cannot supply the specified amount of reactive power; wherein the control circuit is configured to cause the voltage-clipping device to reduce the solar output voltage by modulating an output voltage of the inverter system or an output current of the inverter system or both.

US Pat. No. 10,431,982

SURGE SUPPRESSION SYSTEM FOR MEDIUM AND HIGH VOLTAGE

Asator Global Technologie...

1. A surge suppression system of a power distribution system of a power grid which provides power to low-voltage power consumers, comprising:at least one surge suppressor unit which is configured to connect, via respective direct electrical connections and in immediate physical proximity to a three phase system transformer, in a shunt connection to at least one of (i) a first set of power distribution lines on a primary side of said phase system transformer of said power distribution system and (ii) a second set of power distribution lines on a secondary side of said system transformer, each surge suppressor unit configured to correct disruptions due to at least one of a voltage swell and a voltage sag through said first set of power distribution lines or said second set of power distribution lines;
wherein said primary and secondary sides transform a three phase power from a first voltage on said primary side to a second voltage on said secondary side different from said first voltage;
wherein each surge suppressor unit comprises a plurality of transformer banks to correct said disruptions, each of said plurality of transformer banks including (i) a respective primary coil which connects to and receives a respective phase of three phase power received from said power distribution system and (ii) a respective secondary coil which connects in series together with a secondary coil of each other of said plurality of transformer banks and has a resistor connected in series therewith to harmlessly reflect energy from said disruptions due to at least one of a voltage swell and a voltage sag.

US Pat. No. 10,431,974

SURGE PROTECTION CIRCUIT

GE Aviation Systems, LLC,...

1. A clamp circuit for protecting a load against a surge, the clamp circuit comprising:a power dissipation circuit including at least one transistor and a resistor;
a voltage sensitive device comprising a diode being reversed biased and configured to limit a voltage across the load by turning the at least one transistor on when the surge occurs;
a biasing circuit comprising a voltage divider formed by a pair of resistors connected between the at least one transistor of the power dissipation circuit and an anode of the voltage sensitive device, wherein when a surge occurs, the diode avalanches and avalanche current flows to the biasing circuit from the voltage sensitive device and the biasing circuit is configured to activate the power dissipation circuit, and the power dissipation circuit is configured to turn on the at least one transistor to dissipate power generated by the surge across one of the resistor and the at least one transistor, wherein the at least one transistor acts in conjunction with the diode and the biasing circuit, and when the at least one transistor is turned on, a voltage divider is formed between a source impedance and the resistor of the power dissipation circuit disposed in series with a channel of the at least one transistor and the resistor holds a portion of transient pulse seen by the load to a low voltage and the low voltage is added to a threshold voltage of the at least one transistor.

US Pat. No. 10,431,967

APPARATUS FOR CABLE MANAGEMENT

Eaton Intelligent Power L...

1. An apparatus comprising:a plurality of distinct phase conductors, each of the distinct phase conductors including one or more insulated electrical cables;
an electrically nonconductive support brace having two opposite sides, and having apertures extending through the support brace between the two opposite sides of the support brace;
a plurality of retainer straps, each of the plurality of retainer straps reaching around a corresponding one of the plurality of distinct phase conductors at one of the two opposite sides of the support brace, and reaching further to the other of the two opposite sides of the support brace through a pair of the apertures extending through the support brace; and
a plurality of strap locks engaging the plurality of retainer straps to secure the plurality of retainer straps in place around the plurality of distinct phase conductors.

US Pat. No. 10,431,956

NANOCAVITY MONOLAYER LASER MONOLITHICALLY INTEGRATED WITH LED PUMP

International Business Ma...

1. A laser structure including a nanocavity laser and light emitting diode (LED) monolithically formed within the laser structure, comprising:a substrate including at least one of silicon (Si) and germanium (Ge);
a buffer layer including a III-V material and having a first surface finned directly on the substrate, the buffer layer including an interface material to reduce dislocation defects due to lattice mismatch between the at least one of Si and Ge of the substrate and the III-V material of the buffer layer;
a light emitting diode (LED) formed directly on a second surface of the buffer layer;
a photonic crystal layer formed on the LED; and
a nanocavity laser including a monolayer of a transition metal dichalcogenide formed on the photonic crystal layer for receiving light through the photonic crystal layer from the LED to optically pump the nanocavity laser, the transition metal dichalcogenide having a chemical formula of MX2, where M is selected from the group consisting of: W and Mo and X is selected from the group consisting of: S, Se and Te, wherein the buffer layer reduces the dislocation defects to allow for the formation of the LED within the laser structure.

US Pat. No. 10,431,953

LASER APPARATUS INCLUDING PLURALITY OF LASER MODULES

FANUC CORPORATION, Yaman...

1. A laser apparatus comprising:a plurality of laser modules;
a laser power source section configured to drive each of the plurality of laser modules;
a combiner configured to combine laser beams emitted by the plurality of laser modules and to output a combined laser beam;
an optical output command section configured to generate a first optical output command with respect to the combined laser beam;
a laser module selection/command section configured to select a laser module to be driven from the plurality of laser modules, based on the first optical output command and to generate a second optical output command for the laser module that has been selected; and
a control section configured to control the laser module and the laser power source section, based on the second optical output command,
wherein, with respect to switching the number of laser-oscillating laser modules in accordance with a change in the first optical output command, the laser module selection/command section is configured to set a second threshold value for the first optical output command, when increasing the number of laser-oscillating laser modules to N, to a value higher or lower, by a predetermined value that is greater than a fluctuation range of an actual optical output, than a first threshold value for the first optical output command serving as a reference, when reducing the number of laser-oscillating laser modules from N.

US Pat. No. 10,431,950

SMART CONDUCTOR/CONNECTOR SELECTING DIE

Hubbell Incorporated, Sh...

1. A crimping die comprising:an outer body having a tool engaging surface;
an inner body coupled to said outer body having a crimping area;
a first selecting aperture in said outer body configured to indicate one of an appropriately sized connector and an appropriately sized conductor relative to the crimping area.

US Pat. No. 10,431,934

CONNECTOR

Japan Aviation Electronic...

1. A connector mountable on a circuit board and mateable with a mating connector along a mating direction, wherein:the connector comprises a housing and a plurality of contacts which include two or more signal contacts for signal transmission and two or more predetermined contacts maintained at predetermined voltage levels;
the housing holds the contacts;
each of the contacts has a horizontal portion extending along the mating direction, an intersecting portion extending along an intersecting direction intersecting with the mating direction, a fixed portion extending from the intersecting portion and fixed to the circuit board when the connector is used, and a coupling portion coupling the horizontal portion and the intersecting portion to each other;
the contacts include one or more first contact groups;
each of the first contact groups consists of two of the predetermined contacts and one differential pair of two of the signal contacts;
for each of the first contact groups, the contacts are arranged in a pitch direction perpendicular to the mating direction, and the differential pair is located between the predetermined contacts in the pitch direction;
for each of the first contact groups, a size of the coupling portion of each of the predetermined contacts in the pitch direction is larger than another size of the coupling portion of each of the signal contacts in the pitch direction, and a size of the intersecting portion of each of the predetermined contacts in the pitch direction is larger than another size of the intersecting portion of each of the signal contacts in the pitch direction; and
the horizontal portion of each of the predetermined contacts of each of the first contact groups includes a contact portion which is to be brought into contact with a corresponding one of mating contacts of the mating connector, and for each of the predetermined contacts of each of the first contact groups, a size of the intersecting portion in the pitch direction is larger than another size of the contact portion in the pitch direction.

US Pat. No. 10,431,931

ELECTRICAL UNIT AND ASSEMBLY

Lear Corporation, Southf...

1. An electrical unit, comprising:a housing member;
a slider configured to slide along an outer surface of the housing member and selectively retain an electrical connector relative to the housing member; and
a bracket fixed to the housing member, the bracket restricting movement of the slider in at least one direction;
wherein the bracket includes a protrusion; the housing member includes a bracket recess; the bracket includes a securing tab and is fixed to the housing member via the securing tab; and the protrusion is disposed at least partially in the bracket recess.

US Pat. No. 10,431,928

ANGLED CONTACT PIN FOR BEING PRESSED INTO A CONTACT PIN RECEPTACLE, A CONNECTOR WITH AT LEAST ONE CONTACT PIN AND A METHOD FOR PRODUCING A CONNECTOR

TE Connectivity Germany G...

1. A contact pin, comprising:a contact section extending substantially parallel to a contacting direction in which the contact pin is pressed into a contact pin receptacle;
a mounting section angled with respect to the contact section; and a transition region connecting the contact section and the mounting section, the transition region having a recess forming a substantially planar engagement surface, a depth of the recess extends from a rear side of the contact pin in the contacting direction to over a middle of a cross-section of the mounting section, the depth of the recess is less than a depth of the mounting section in the contacting direction, a height of the recess extends in a direction parallel to the mounting section into the transition region from an upper side edge of the contact pin opposite the mounting section.

US Pat. No. 10,431,914

NETWORK CONNECTOR ASSEMBLY

CISCO TECHNOLOGY, INC., ...

1. A network connector assembly comprising:an upper board member having one or more upper alignment pins and an off-center upper coupling pin engaged with a printed circuit board, the upper board member having a first set of contact pins disposed on an upper board top surface;
a lower board member having one or more lower alignment pins and an off-center lower coupling pin, each of the one or more lower alignment pins extending into an alignment pin aperture shared with one of the one or more upper alignment pins and formed in the printed circuit board, the off-center lower coupling pin extending upwardly from a bottom surface, through the printed circuit board, and into a coupling pin aperture formed in the upper board member, the lower board member having a second set of contact pins; and
a housing disposed over the upper board member and the lower board member, the housing forming one or more network couplers, each of the one or more network couplers configured to receive one of the first set of contact pins or the second set of contact pins.

US Pat. No. 10,431,908

ELECTRICAL COUPLERS AND METHODS OF USING THEM

1. A device for coupling two or more insulated electrical wires, the device comprising a body sized and arranged to receive an uninsulated section of a first insulated electrical wire and an uninsulated section of a second insulated electrical wire, the device comprising an external fastener, separate from the body and configured to removably couple to the body, the external fastener sized and arranged to permit wrapping of the uninsulated section of the first insulated electrical wire and the uninsulated section of the second insulated electrical wire around a section of the external fastener within the body, the device further comprising a retention device configured to removably couple to the external fastener to bias the uninsulated section of the first insulated electrical wire to the uninsulated section of the second insulated electrical wire into contact to electrically couple the first insulated electrical wire and the second insulated electrical wire and retain the uninsulated section of the first insulated electrical wire and the uninsulated section of the second insulated electrical wire within the body.

US Pat. No. 10,431,902

WAVEGUIDE SLOTTED ARRAY ANTENNA

Ningbo University, Zheji...

1. A waveguide slotted array antenna, comprising:a feed layer; and
a radiation layer,
wherein the feed layer is located below the radiation layer,
wherein the radiation layer comprises a first radiation unit, a second radiation unit, a third radiation unit and a fourth radiation unit which are stacked from bottom to top,
wherein the first radiation unit comprises a first flat metal plate and a first radiation array arranged on the first flat metal plate,
wherein the first radiation array comprises n2 radiation cavities which are arranged at intervals, wherein n=2k , and k is a positive integer which is equal to or greater than two,
wherein the n2 radiation cavities are rectangular concave cavities formed in the upper surface of the first flat metal plate, and the n2 radiation cavities are distributed on the first flat metal plate in n rows and n columns,
wherein first matching plates are separately arranged in the middle of the front side wall and the middle of the rear side wall of each radiation cavity, and second matching plates are separately arranged in the middle of the left side wall and the middle of the right side wall of each radiation cavity; with the front side wall direction of each radiation cavity as the length direction and the left side wall direction of each radiation cavity as the width direction, the height of each first matching plate and the height of each second matching plate are equal to that of each radiation cavity; the upper end faces of the first matching plates and the upper end faces of the second matching plates are located on the same plane with the upper end face of the first flat metal plate,
wherein the length of each first matching plate is smaller than one fifth of the length of each radiation cavity, and the width of each first matching plate is smaller than one fifth of the width of each radiation cavity; the length of each second matching plate is smaller than one fifth of the length of each radiation cavity, and the width of each second matching plate is smaller than one third of the width of each radiation cavity,
wherein an input port extending to the lower surface of the first flat metal plate is arranged at the bottom end of each radiation cavity, and the input ports are rectangular ports; the front side wall of each input port is parallel to the front side wall of the corresponding radiation cavity, the left side wall of each input port is parallel to the left side wall of the corresponding radiation cavity, the center of each input port overlaps with the center of the corresponding radiation cavity, the length of each input port is smaller than the distance between the two corresponding second matching plates, and the width of each input port is smaller than the distance between the two corresponding first matching plates,
wherein the second radiation unit comprises a second flat metal plate and a second radiation array arranged on the second flat metal plate,
wherein the second radiation array comprises n2 first radiation sets which are arranged at intervals, and the n2 first radiation sets are distributed on the second flat metal plate in n rows and n columns and communicated with the n2 radiation cavities in a one-to-one correspondence mode,
wherein each first radiation set comprises four first radiation holes which are distributed in two rows and two columns at intervals,
wherein the first radiation holes are rectangular holes extending from the upper surface to the lower surface of the second flat metal plate, the four first radiation holes in the first radiation set are located over the n2 radiation cavities correspondingly communicated with the four first radiation holes; the front side walls of the two first radiation holes located in the first row are flush with the front side walls of the corresponding n2 radiation cavities, and the rear side walls of the two first radiation holes located in the second row are flush with the rear side walls of the corresponding n2 radiation cavities; the left side walls of the two first radiation holes located in the first column are flush with the left side walls of the corresponding n2 radiation cavities, and the right side walls of the two first radiation holes located in the second column are flush with the right side walls of the corresponding n2 radiation cavities,
wherein the third radiation unit comprises a third flat metal plate and a third radiation array arranged on the third flat metal plate,
wherein the third radiation array comprises n2 second radiation sets which are arranged at intervals, and the n2 second radiation sets are distributed on the third flat metal plate in n rows and n columns and communicated with the n2 first radiation sets in a one-to-one correspondence mode,
wherein each second radiation set comprises four second radiation holes which are distributed in two rows and two columns at intervals,
wherein the second radiation holes are rectangular holes extending from the upper surface to the lower surface of the third flat metal plate, the four second radiation holes in the second radiation set completely overlap with the four first radiation holes in the first radiation set communicated with the second radiation set in a one-to-one correspondence mode after clockwise rotating by 22.5 degrees around the center,
the fourth radiation unit comprises a fourth flat metal plate and a fourth radiation array arranged on the fourth flat metal plate,
wherein the fourth radiation array comprises n2 third radiation sets which are arranged at intervals, and the n2 third radiation sets are distributed on the fourth flat metal plate in n rows and n columns and communicated with the n2 second radiation sets in a one-to-one correspondence mode,
wherein each third radiation set comprises four third radiation holes which are distributed in two rows and two columns at intervals,
wherein the third radiation holes are rectangular holes extending from the upper surface to the lower surface of the fourth flat metal plate, the four third radiation holes in the third radiation set are communicated with the four second radiation holes in the corresponding second radiation set in a one-to-one correspondence mode, and the center of each third radiation hole overlaps with the center of the second radiation hole communicated with the third radiation hole; each third radiation hole can anticlockwise deflect by 22.5 degrees around the center relative to the corresponding second radiation hole,
wherein the length of each third radiation hole is greater than that of each second radiation hole and smaller than 1.5 times of the length of each second radiation hole, and the width of each third radiation hole is greater than two times of the width of each second radiation hole and smaller than three times of the width of each second radiation hole;
wherein a rectangular metal strip is arranged in each third radiation hole, wherein the left end face of the rectangular metal strip is connected with the left side wall of the third radiation hole, and the right end face of the rectangular metal strip is connected with the right side wall of the third radiation hole; the distance from the front end face of the rectangular metal strip to the front side wall of the third radiation hole is equal to the distance from the rear end face of the rectangular metal strip to the rear side wall of the third radiation hole; the upper end face of the rectangular metal strip is located on the same plane with the upper end face of the fourth flat metal plate,
wherein the height of the rectangular metal strip is smaller than that of the third radiation hole, the width of the rectangular metal strip is smaller than one third of the width of third radiation hole, and the length of the rectangular metal strip is equal to that of the third radiation hole,
wherein the first flat metal plate, the second flat metal plate, the third flat metal plate and the fourth flat metal plate are rectangular plates with equal lengths and widths, and the edges of the four flat metal plates are aligned.

US Pat. No. 10,431,900

ARRAY ANTENNA WITH OPTIMIZED ELEMENTS POSITIONS AND DIMENSIONS

Agence Spatiale Europeenn...

1. A method of manufacturing an array antenna comprising:a design phase, comprising synthesizing an array layout of said array antenna and choosing or designing radiating elements to be arranged according to said array layout; and
a phase of physically making said array antenna, comprising arranging said radiating elements according to said array layout;
wherein said radiating elements are maximum efficiency elements, having uniform amplitude excitation;
the method being characterized in that said design phase comprises the steps of:
a. defining a continuous reference aperture;
b. subdividing said continuous reference aperture into a plurality of elementary cells with assigned power levels;
c. determining, within each said elementary cell, a position for at least one maximum efficiency radiating element;
d. determining a size and an aperture field amplitude of each said maximum efficiency radiating element, such that a variation of a cumulative field distribution of the resulting array antenna aperture over each said elementary cell is substantially equal to a variation of a cumulative field distribution of said reference aperture over the same elementary cell, subject to size constraints.

US Pat. No. 10,431,898

MULTIMODE ANTENNA SYSTEM AND METHODS FOR USE THEREWITH

1. A communication device, comprising:a dielectric antenna having a feed point and an aperture;
a feedline coupled to the feed point of the dielectric antenna; and
a multi-input multi-output (MIMO) transceiver, coupled to the feedline, the MIMO transceiver configured to transmit first electromagnetic waves along the feedline to the feed point of the dielectric antenna, wherein the first electromagnetic waves propagate along the feedline via a plurality of guided wave modes at non-optical frequencies without requiring an electrical return path, wherein the first electromagnetic waves convey first data in accordance with one or more MIMO techniques and wherein the first electromagnetic waves generate first free-space wireless signals at the aperture of the dielectric antenna in accordance with the one or more MIMO techniques.

US Pat. No. 10,431,897

MICROWAVE GAIN MEDIUM WITH NEGATIVE REFRACTIVE INDEX

ARIZONA BOARD OF REGENTS ...

1. A microwave gain medium (100) having a negative refractive index adapted to be placed in a rectangular waveguide to form a volumetric structure, the medium (100) comprising:(a) a unit cell (102) comprising a substrate (104);
(b) a linear sub-wavelength wire (106) printed on the substrate (104) of the unit cell (102);
(c) a circular-shaped split ring resonator (110) printed on the substrate (104) of the unit cell (102), the circular-shaped split ring resonator (110) overlays the linear sub-wavelength wire (106);
(d) a first negative resistance device (112) being embedded at a horizontal symmetry axis of the linear sub-wavelength wire (106), which causes the sub-wavelength wire (106) to exhibit a negative permittivity;
(e) a second negative resistance device (212) being embedded at an opposite end of a split point on the split ring resonator (110), which causes the split ring resonator (110) to exhibit a negative permeability;
wherein a microwave incident on the medium (100) induces the sub-wavelength wire (106), the split ring resonator (110), and the first and second negative resistance devices (212) in the unit cell (102) to electromagnetically interface, which effects a gain in the medium (100), thus providing a spatial amplification of the incident microwave, while the medium (100) maintains a negative refractive index, thereby eliminating an energy loss.

US Pat. No. 10,431,896

MULTIBAND ANTENNA WITH PHASE-CENTER CO-ALLOCATED FEED

CUBIC CORPORATION, San D...

1. A multiband antenna for operation at two or more selected wavelengths, the multiband antenna comprising:a first cavity having first sidewalls disposed within the antenna, the first sidewalls extending upward from the interior of the antenna to an upper surface of the antenna such that the first sidewalls provide a first aperture having an annular shape in the upper surface;
a second cavity having second sidewalls disposed within the antenna, the second sidewalls extending upward from the interior of the antenna to the upper surface of the antenna such that the second sidewalls provide a second aperture having an annular shape in the upper surface, the second aperture disposed internally to the first aperture within the upper surface;
a first pair of excitation probes disposed within the first cavity; and
a second pair of excitation probes disposed within the second cavity;
wherein each of the first and second cavities has a cross-sectional shape in a plane perpendicular to the upper surface which is “L”-shaped.

US Pat. No. 10,431,893

OMNIDIRECTIONAL MULTIBAND ANTENNA

King Saud University, Ri...

1. An omnidirectional multiband antenna, comprising:an electrically conductive conical surface having a vertex end and a base end;
at least one electrically conductive annular member mounted on the base end of the electrically conductive conical surface, the at least one electrically conductive annular member having a plurality of stacked segments and a corrugated exterior surface;
a ground plane plate having opposed first and second surfaces, the vertex end of the electrically conductive conical surface being positioned adjacent to, and spaced apart from, the first surface of the ground plane plate;
a plurality of cylindrical rods, each of the rods having opposed first and second ends, the first end of each of the rods being secured to the at least one electrically conductive annular member, the second end of each of the rods being mounted on the first surface of the ground plane plate; and
a coaxial cable having a center conductor and an outer conductor, the center conductor being in electrical communication with the vertex end of the electrically conductive conical surface, and the outer conductor being in electrical communication with the ground plane plate.

US Pat. No. 10,431,888

COMMUNICATION METHOD AND DEVICE USING BEAMFORMING IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for transmitting a signal using beamforming by a base station in a wireless communication system, the method comprising:determining to enable a beam superposition based on a first trigger condition that a standard deviation of receive signal strength measurements for at least one unitary beam reported by a mobile station exceeds a beam superposition allocation threshold, the at least one unitary beam being at least one among a plurality of unitary beams corresponding to an array antenna of the base station;
determining a number of unitary beams to be superposed and selecting the determined number of unitary beams from among the plurality of unitary beams based on at least one predetermined condition related to the beam superposition and channel quality information received from the mobile station, the channel quality information including information about a channel quality measured by the mobile station for a combination of the selected unitary beams;
configuring the array antenna of the base station to form a superposed beam by superposing the selected unitary beams;
performing a communication with the mobile station through the superposed beam;
determining to disable the beam superposition based on a second trigger condition that a standard deviation of receive signal strength measurements for the superposed beam reported by the mobile station exceeds a beam superposition release threshold; and
performing the communication with the mobile station through one or more unitary beams among the plurality of unitary beams,
wherein the combination of the selected unitary beams is determined based on beam information transmitted from the base station to the mobile station, and the beam information includes information about a maximum number of unitary beams available to form the superposed beam.

US Pat. No. 10,431,878

WEARABLE DEVICE DESIGN FOR 4G ANTENNAS

Verizon Patent and Licens...

1. A wearable device, comprising:an outer wall defining a circumference of an inner core portion of the wearable device, wherein a first portion of the outer wall includes a first material and a second portion of the outer wall includes a second material that is different from the first material;
a bottom cover, coupled to a bottom portion of the outer wall, defining a bottom most portion of the inner core portion of the wearable device;
a bezel, coupled to a top portion of the outer wall, defining a top portion of the inner core portion of the wearable device, wherein a first portion of the bezel includes the first material, wherein the first portion of the bezel and the first portion of the outer wall form a contiguous gap feature that includes the first material;
a connector portion coupled to an outer edge of the outer wall, wherein the outer wall includes an opening proximate to the connector portion, such that the connector portion and the outer wall include a contiguous space;
a printed circuit board (PCB), coupled to the bottom cover by one or more metal nodes such that a first vertical space is formed between the PCB and the bottom cover,
wherein the PCB comprises circuitry to enable the wearable device to communicate with a wireless telecommunication network,
wherein the PCB extends through the opening and is situated partially within the connector portion; and
an antenna, through which the PCB communicates with the wireless telecommunications network, wherein the antenna is positioned along a circumference of an inner portion of the outer wall and above the PCB to create a second vertical space between the antenna and the PCB,
wherein the antenna includes a first antenna portion and a second antenna portion that are arranged separately along the circumference of the outer wall such that a gap exists between the first antenna portion and the second antenna portion, and
wherein the first antenna portion and the second antenna portion are positioned within the inner core portion, below the bezel and not in contact with the bezel, and above the bottom cover.

US Pat. No. 10,431,874

ANTENNA DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. An electronic device comprising:a housing including:
a front face having a substantially rectangular shape and facing in a first direction,
a rear face having a substantially rectangular shape and facing in a second direction that is opposite to the first direction, and
first to fourth side face members that together enclose a space between the front face and the rear face, at least a portion of the first to fourth side face members being formed of a conductive material;
a touch screen display arranged within the housing and exposed through the front face of the housing; and
at least one wireless communication circuit arranged within the housing,
wherein the rear face includes:
a substantially flat conductive plate that constitutes a substantial portion of the rear face,
at least one slit that may be formed along a rim of the substantially flat conductive plate and be disposed between the first to fourth side face and the substantially flat conductive plate, and
an elongated non-conductive strip that encloses the conductive plate when viewed from above the rear face, and extends along the first to fourth side face members and disposed in the at least one slit.

US Pat. No. 10,431,861

COOLING STRUCTURE FOR AN ENERGY STORAGE DEVICE

FLEXTRONICS INTERNATIONAL...

1. An energy storage device, particularly for use in motor vehicles, comprisingat least one base body as well as at least one housing section fixed thereto for accommodating at least one energy storage unit, wherein the base body comprises at least one integrated cooling duct for a gaseous medium;
wherein the at least one cooling duct is connected to at least one air intake opening provided in the base body and extending substantially perpendicular to the cooling duct;
wherein the base body comprises two oppositely disposed side surfaces, wherein a housing section for accommodating the at least one energy storage unit is affixed to each of the side surfaces;
wherein the at least one cooling duct is separated by dividing bars and between each dividing bar and a lower side of the base body a distance A is provided which defines the height of the respective air intake opening into the respective cooling duct; and
wherein the distance A between the lower end of the dividing bars and the lower side of the base body is successively, stepwise reduced from the peripheral surface to the center of the base body.

US Pat. No. 10,431,860

COLD PLATE ASSEMBLY FOR ELECTRIFIED VEHICLE BATTERIES

FORD GLOBAL TECHNOLOGIES,...

1. An assembly, comprising:a top plate piece;
a bottom plate piece;
tubing sandwiched between said top plate piece and said bottom plate piece, said tubing included a flange adapted to limit an insertion distance of said tubing between said top plate piece and said bottom plate piece;
each of said top plate piece and said bottom plate piece includes flared portions that overlap said tubing; and
said flared portions include tapered inner walls that limit said insertion distance.

US Pat. No. 10,431,856

METHOD FOR PRODUCING A BATTERY CONTACT-MAKING SYSTEM, AND BATTERY CONTACT-MAKING SYSTEM

ElringKlinger AG, Dettin...

1. A method for producing a cell contact-making system for an electrochemical device, including the following:separating out from a first starting material at least one signal conductor track group, which includes at least two signal conductor tracks of a signal conductor system of the cell contact-making system, by which signal sources or measuring points of the electrochemical device are electrically conductively connected to a signal conductor terminal connector serving as an interface for a monitoring unit of the electrochemical device, and at least one connection element by means of which at least two of the signal conductor tracks are directly connected to one another;
separating out from a second starting material, which is different from the first starting material, at least one cell connector or cell terminal connector;
connecting the signal conductor tracks of the signal conductor track group separated out from the first starting material to a respective cell connector or cell terminal connector separated out from the second starting material or to a sensor element of the cell contact-making system by a substance-to-substance bond or with positive engagement, after the separating out of the signal conductor track group from the first starting material; and
removing the at least one connection element.

US Pat. No. 10,431,852

FLAT SECONDARY BATTERY

Envision AESC Japan Ltd.,...

1. A flat lithium ion secondary battery comprising:a laminate-type power generation element in which two or more positive electrode plates and negative electrode plates are laminated via each of separators, wherein:
the positive electrode plate includes an NMC composite oxide and polyvinylidene fluoride,
the negative electrode plate includes a mixture of graphite and polyvinylidene fluoride or a mixture of graphite and styrene-butadiene copolymer latex,
the electrolyte solution includes ester-based solvent of propylene carbonate, ethylene carbonate, dimethyl carbonate, diethyl carbonate or ethyl methyl carbonate as an organic liquid solvent; and
a pair of rectangular exterior members defined by long sides and short sides when viewed from a lamination direction of the two or more positive electrode plates and negative electrode plates, the rectangular exterior members sealing the laminate-type power generation element and an electrolyte solution, wherein
at least one exterior member of the pair of the rectangular exterior members comprises:
an abutting part including an abutting surface that abuts against an uppermost layer electrode of the positive electrode plates and negative electrode plates;
a sealing part at which the rectangular exterior members overlap each other at an outer circumferential position of the rectangular exterior members; and
an extending part that extends from the abutting part to the sealing part, a space defined by the rectangular exterior members is defined by:
1.0?LA/LB?1.90,
bA, a length from the sealing parts to an electrode directly across from the sealing parts in millimeters, is within the range from 4 mm or more to 10 mm or less,
LA/d?LB/d, wherein d is a thickness of the laminate-type power generation element from the uppermost layer electrode to the electrode directly across from the sealing parts, and
a value of LA/d to b is between a first straight line and a second straight line, the first straight line defined between (bA=5, LA/d=1.675) and (bA=10, LA/d=2.75) and the second straight line defined between (bA=5, LA/d=2.0) and (bA=10, LA/d=2.85), such that:
LA/d is within the range from 1.675 or more to 2.0 or less when bA is 5 mm,
LA/d is within the range from 2.75 or more to 2.85 or less when bA is 10 mm, wherein:
LA is an average of lengths of the extending parts located at both ends in a direction parallel to the long sides in a first cross section of the flat secondary battery when cutting through the flat secondary battery by a plane parallel to the long sides and along the lamination direction, and
LB is an average of lengths of the extending parts located at both ends in a direction parallel to the short sides in a second cross section of the flat secondary battery when cutting through the flat secondary battery by a plane parallel to the short sides and along the lamination direction,
a value of a ratio of a battery surface area to a rated capacity of the flat lithium ion secondary battery is 5 cm2/Ah or more, the rated capacity is 3 Ah or more, and the battery surface area is a projected area of the flat lithium ion secondary battery including a battery exterior body,
a capacity retention ratio is 80% or more and the capacity retention ratio is a capacity retention ratio to initial capacity retention ratio of the flat lithium ion secondary battery when used 1000 cycles, and
an aspect ratio of the electrode plates is 1 to 3, and the aspect ratio is defined as a ratio of a length of the long sides to a length of the short sides of a lamination surface of the two or more positive electrode plates and negative electrode plates.

US Pat. No. 10,431,850

GARNET MATERIALS FOR LI SECONDARY BATTERIES AND METHODS OF MAKING AND USING GARNET MATERIALS

QuantumScape Corporation,...

1. An electrode comprising:a metal foil or metal powder;
two thin and sintered lithium-stuffed garnet films, wherein the film thickness of each thin and sintered lithium-stuffed garnet film is, independently in each instance, less than 50 ?m and greater than 10 nm, wherein each film comprises, independently in each instance, a lithium-stuffed garnet characterized by the formula LiALaBM?CM?DZrEOF, LiALaBM?CM?DTaEOF, or LiALaBM?CM?DNbEOF, wherein 4 wherein the metal foil or metal powder is between, and in direct contact with, the two thin and sintered lithium-stuffed garnet films.

US Pat. No. 10,431,849

HIGH ENERGY DENSITY ALKALI METAL BATTERIES INCORPORATING SOLID ELECTROLYTES

GM Global Technology Oper...

1. An electrochemical cell comprising an alkali metal anode layer of one of lithium or sodium, a solid electrolyte layer, and a cathode layer, the solid electrolyte layer comprising:a glass, ceramic, or glass-ceramic, solid electrolyte layer with opposing surfaces, one of the surfaces being roughened to increase its effective surface area for increased direct physical contact with the alkali metal anode layer, the roughened surface being maintained in electrical and mechanical face-to-face contact with the alkali metal anode layer and the opposing surface being maintained in electrical and mechanical face-to-face contact with the cathode layer in the operation of the electrochemical cell by an applied pressure, the applied pressure being sufficient to cause the alkali metal anode layer material to flow into contact with the roughened surface of the solid electrolyte layer and to enable an increase in critical current density of at least 25% over a like dimensioned cell with a solid electrolyte with an un-roughened surface.

US Pat. No. 10,431,843

FRAME BODY, CELL FRAME, CELL STACK, AND REDOX FLOW BATTERY

Sumitomo Electric Industr...

1. A frame body for a cell frame of a redox flow battery,the frame body comprising an outer peripheral portion that is to face and contact, when a plurality of the cell frames are stacked, a frame body of another cell frame that is adjacent to the cell frame,
the outer peripheral portion including a thin region whose thickness gradually decreases in a direction from a center of the frame body toward an outer periphery of the frame body,
the frame body having a through window disposed in a central portion of the frame body, and
the frame body being formed of a resin,
wherein the thickness of the thin region gradually decreases by gradual tapering from a first flat surface of the frame body toward the outer periphery of the frame body, and by tapering from a second flat surface of the frame body toward the outer periphery of the frame body, the tapering from the first flat surface opposing the tapering from the second flat surface.

US Pat. No. 10,431,838

GAS DIFFUSION LAYER FOR FUEL CELL APPLICATIONS

Hyundai Motor Company, S...

9. A method of manufacturing a compressible gas diffusion layer (GDL) for fuel cell applications, the fuel cell comprising a polymer electrolyte membrane, catalyst layers comprising a first catalyst layer and a second catalyst layer, compressible gas diffusion layers comprising a first compressible gas diffusion layer (GDL) and a second compressible gas diffusion layer (GDL) and bipolar plates comprising a first bipolar plate and a second bipolar plate,wherein the polymer electrolyte membrane is coated on one side with the first catalyst layer and coated on the other side coated with the second catalyst layer,
the first compressible gas diffusion layer (GDL) is attached to an outer surface of the first catalyst layer, and the first bipolar plate is attached to an outer surface of the first compressible gas diffusion layer and is composed of a major flow field having a longer accumulated length of flow field channels and a minor flow field having a shorter accumulated length of the flow field channels than the major flow field, and the first compressible gas diffusion layer has a width direction perpendicular to a major flow field direction of the first bipolar plate and a length direction which is in parallel with the major flow field direction of the first bipolar plate,
the second compressible gas diffusion layer (GDL) is attached to an outer surface of the second catalyst layer, and the second bipolar plate attached to an outer surface of the second compressible gas diffusion layer and is composed of a major flow field having a longer accumulated length of flow field channels and a minor flow field having a shorter accumulated length of the flow field channels that the major flow field, and the second compressible gas diffusion layer has a width direction perpendicular to a major flow field direction of the second bipolar plate and a length direction which is in parallel with the major flow field direction of the second bipolar plate, the method comprising:
a first step of providing a rolled compressible GDL material having a dual layer structure including a microporous layer and a macroporous substrate which is formed of carbon fiber felt, or carbon fiber paper, wherein a machine direction of the rolled compressible GDL material is an inherent high stiffness direction and a cross-machine direction thereof is a low stiffness direction,
a second step of determining a certain angle (q) formed by the machine direction of the inherent high stiffness of the compressible GDL material and the major flow field direction of each of the first bipolar plate and the second bipolar plate such that the machine direction of the inherent high stiffness of the compressible GDL material is not in parallel with each of the major flow field direction of the first bipolar plate and the second bipolar plate to reduce the compressible GDLs' intrusion into the flow field channels of the first bipolar plate and the second bipolar plate being in contact with the first compressible GDL and the second compressible GDL, respectively, and
a third step of cutting the rolled compressible GDL material according to the certain angle determined in the second step, to make the compressible GDL in which each of the inherent high stiffness direction of the first compressible GDL and the second compressible GDL is arranged in one direction and each of the inherent high stiffness direction of the first compressible GDL and the second compressible GDL is not parallel with the length direction of the first compressible GDL and the second compressible GDL, respectively, wherein each of the first compressible GDL and the second compressible GDL is cut from the rolled GDL material at an angle of 90°, formed by the machine direction of the inherent high stiffness of the GDL material and the major flow field direction of the first bipolar plate and the second bipolar pate, respectively.

US Pat. No. 10,431,828

MICROBATTERY WITH THROUGH-SILICON VIA ELECTRODES

INTERNATIONAL BUSINESS MA...

1. A method of forming a battery, comprising:forming an anode substrate;
forming a cathode substrate;
forming anode through vias in the anode substrate;
forming cathode through vias in the cathode substrate;
forming an anode conductive liner on the anode substrate, in contact with the anode through vias;
forming an anode on the anode conductive liner;
forming a cathode conductive liner on the cathode substrate, in contact with the cathode through vias;
forming a cathode on the cathode conductive liner;
assembling the anode substrate and the cathode substrate to form a battery structure; and
forming a conductive overcoat over the anode substrate and the cathode substrate to seal a cavity formed by the anode substrate and the cathode substrate.

US Pat. No. 10,431,827

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO ELECTRIC CO., LTD.,...

1. A non-aqueous electrolyte secondary battery comprising:a positive electrode plate in which a positive electrode mix layer is disposed on a positive electrode core body;
a negative electrode plate in which a negative electrode mix layer is disposed on a negative electrode core body;
a positive electrode terminal electrically connected to the positive electrode plate;
a negative electrode terminal electrically connected to the negative electrode plate;
a flat rolled electrode assembly in which the positive electrode plate and the negative electrode plate in the state of being insulated from each other with a separator therebetween are rolled into a flat shape;
a non-aqueous electrolytic solution; and
an outer body,
wherein a rolled positive electrode core body exposed portion is disposed at one end portion of the flat rolled electrode assembly,
a rolled negative electrode core body exposed portion is disposed at the other end portion of the flat rolled electrode assembly,
the rolled positive electrode core body exposed portion is bundled and connected to a positive electrode collector,
the rolled negative electrode core body exposed portion is bundled and connected to a negative electrode collector,
a pressure-sensitive forced short-circuit mechanism that short-circuits the positive electrode plate and the negative electrode plate in response to an increase in pressure inside the outer body,
lithium carbonate is contained in the positive electrode mix layer, and
a porous protective layer is disposed along the border with the positive electrode mix layer at the position opposite to the separator on at least one surface of the positive electrode core body exposed portion,
wherein the protective layer has electrical conductivity and is a protective layer having the electrical conductivity lower than that of the positive electrode core body, and
the protective layer contains lithium carbonate.

US Pat. No. 10,431,821

CATHODE ACTIVE MATERIAL, CATHODE, BATTERY, BATTERY PACK, ELECTRONIC APPARATUS, ELECTRIC VEHICLE, ELECTRIC STORAGE APPARATUS, AND ELECTRIC POWER SYSTEM

Murata Manufacturing Co.,...

1. A battery comprising:a cathode;
an anode; and
an electrolyte,
wherein the cathode includes a cathode active material,
the cathode active material includes a first cathode material comprising a lithium metal oxide having a layered rocksalt structure, the lithium metal oxide including lithium and a metal other than lithium, the metal comprising nickel and at least one selected from the group consisting of iron, zinc, and zirconium,
a site occupancy of metal ions other than lithium at a 3a site obtained by Rietveld analysis of a powder X-ray diffraction pattern of the first cathode material in the cathode in a discharged state is about 5% or less,
a site occupancy of metal ions other than the metal occupying a part of a 3b site at the 3b site is 1% or over, the cathode active material is covered with a coating film including a resolvent of an electrolyte salt and a resolvent of the electrolyte solvent, and
an exposed amount of the cathode active material exposed from the coating film is within a range from about 0.05% to about 8% both inclusive.

US Pat. No. 10,431,806

THIN FILM LITHIUM CONDUCTING POWDER MATERIAL DEPOSITION FROM FLUX

QuantumScape Corporation,...

1. A method for making an electrolyte, the method comprising:providing a lithium conducting garnet electrolyte powder at a first quantity, the lithium conducting garnet electrolyte powder being characterized by a first density and a median particle size of about 100 nm to 10 ?m;
providing a first flux material at a second quantity, the first flux material comprising inorganic salts of lithium, the first flux material being characterized by a melting temperature of about 500-1000° C.;
providing a second flux material at a third quantity, the second flux material being characterized by a melting temperature of about 500-1000° C.;
mixing the first flux material and the second flux material with the lithium conducting garnet electrolyte powder to form a fluxed electrolyte powder;
shaping the fluxed electrolyte powder in to a predetermined shape;
flux sintering the shaped electrolyte powder at a temperature of greater than 100° C. and less than 800° C. to form a dense lithium conducting electrolyte, the dense lithium conducting electrolyte being characterized by a second density, the second density is at least 20% higher than the first density; and
removing the first and second flux materials from the dense lithium conducting electrolyte.

US Pat. No. 10,431,802

BATTERY MODULE INCLUDING A HEAT PIPE POSITIONED IN PROXIMITY TO A TERMINAL COMPONENT AT A POSITIVE OR NEGATIVE TERMINAL OF THE BATTERY MODULE

InEVit LLC, Santa Clara,...

1. A battery module, comprising:a plurality of battery cell groups that are connected in series with each other, each of the plurality of battery cell groups including a plurality of battery cells that are connected to each other in parallel;
a contact plate that is connected to one of the plurality of battery cell groups at a terminal of the battery module, the terminal corresponding to either a positive terminal of the battery module or a negative terminal of the battery module, wherein a positive or negative high-voltage (HV) connector protrudes out of the battery module, and wherein the HV connector is integrated as part of the contact plate or is directly coupled to the contact plate;
a cooling plate integrated into the battery module and configured to be cooled by an external liquid cooling system; and
a heat pipe coupled to the contact plate in proximity to the HV connector of the contact plate and configured to transfer heat away from the HV connector and towards the cooling plate.

US Pat. No. 10,431,801

BUS BAR MODULE AND METHOD FOR PRODUCING BUS BAR MODULE

YAZAKI CORPORATION, Toky...

1. A bus bar module comprising:a plurality of linear conductors disposed in parallel at predetermined intervals;
a belt-form flat conductor disposed adjacent to the linear conductors and extending in an axial direction of the linear conductors; and
an insulating resin portion that integrally covers outer peripheral portions of the plurality of linear conductors and one side edge portion of the flat conductor, the one side edge portion being adjacent to the linear conductors,
wherein a tensile strength of the flat conductor and the insulating resin portion is not less than 50 N/mm2,
wherein the flat conductor has a plurality of through holes formed in the one side edge portion at predetermined intervals along the axial direction of the linear conductors,
wherein the one side edge portion is covered with the insulating resin portion over an area comprising the through holes, and
wherein a dripping amount of the insulating resin portion through the through holes is set within a range of not less than 0.2 mm and not more than 4 mm.

US Pat. No. 10,431,799

LAYERED DOUBLE HYDROXIDE, LAYERED DOUBLE HYDROXIDE DENSE FILM, AND COMPOSITE MATERIAL

NGK INSULATORS, LTD., Na...

1. A layered double hydroxide represented by the following formula:[Mg2+(1-y)M1?+y]1-x[Al3+(1-z)M2?+z]x(OH)2An?x/n.mH2O
wherein 0.1?x?0.4, 0?y?0.95, and 0?z?0.95, with the proviso that both y and z are not 0 at the same time; ?=1 or 2; ?=2 or 3; An? is an n-valent anion, with the proviso that n is an integer of 1 or greater; m?0; M1?+ is a cation of at least one substituent element selected from the group consisting of monovalent elements, transition metal elements, and other elements with an ionic radius greater than that of Mg2+; and M2?+ is a cation of at least one substituent element selected from the group consisting of divalent elements, transition metal elements, and other elements with an ionic radius greater than that of Al3+.

US Pat. No. 10,431,794

METHOD FOR PRODUCING ASSEMBLY, AND ASSEMBLY

SUMITOMO CHEMICAL COMPANY...

1. A method for producing an assembly including (i) a core member having a pillar shape, (ii) a plurality of rolls each of which includes a core and a film wound around the core and has an axis hole, and (iii) at least one first buffer member made of a flexible material and having an axis hole, the method comprising the steps of:inserting the core member through the respective axis holes of the rolls and the axis hole of the at least one first buffer member for an alternate arrangement of the rolls and the at least one first buffer member;
fitting opposite ends of the core member with respective protectors configured to protect the rolls and the at least one first buffer member, the protectors being inserted into the respective opposite ends of the core member in such a manner as to each press a member adjacent to the protector; and
inserting the core member through respective axis holes of second buffer members, the second buffer members being each made of a flexible material, such that the protectors are each separated from an adjacent one of the rolls by one of the second buffer members.

US Pat. No. 10,431,781

BATTERY LOADING MAGAZINE

General Electric Company,...

11. A method for loading battery assemblies within a storage rack, the method comprising:stacking a plurality of battery magazines onto a base member to form a battery magazine stack, the base member including at least one support wall defining an upper surface, the upper surface of the support wall defining at least one base engagement feature, each battery magazine at least partially surrounding a battery assembly, each battery magazine including a first sidewall, a second sidewall, and a transverse wall extending between the first and second sidewalls, wherein the first sidewall, the second sidewall, and the transverse wall define a cavity to receive the battery assembly, and wherein each battery magazine is configured to engage a portion of the battery assembly to prevent lateral movement of the battery assembly relative to the battery magazine when the battery assembly is positioned within the cavity, each of the first and second sidewalls extending between an upper surface and a lower surface opposite the upper surface, the lower surface of at least one of the first and second sidewalls of each battery magazine defining at least one magazine engagement feature configured to engage the at least one base engagement feature, wherein one of the at least one base engagement feature and the at least one magazine engagement feature comprises at least one engagement channel and the other of the at least one base engagement feature and the at least one magazine engagement feature comprises at least one rib configured to be received within the at least one engagement channel;
lifting the base member and the battery magazine stack relative to the storage rack, the storage rack defining a plurality of storage slots, each storage slot configured to receive one of the battery assemblies;
vertically aligning a top battery magazine of the battery magazine stack with a corresponding storage slot of the plurality of storage slots; and
laterally moving the battery assembly contained within the top battery magazine relative to an adjacent battery magazine of the battery stack to install the battery assembly into the corresponding storage slot.

US Pat. No. 10,431,735

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory,wherein the semiconductor memory comprises:
a variable resistance element exhibiting two different states for storing data; and
an upper layer disposed over the variable resistance element,
wherein the upper layer has a stepped profile and includes an upper portion and a lower portion having a wider width than the upper portion,
wherein sidewalls of the upper portion and sidewalls of the lower portion are configured to be discontinuous from each other, and
wherein a height of the upper portion is higher than a height of the lower portion.

US Pat. No. 10,431,734

ENGINEERED BARRIER LAYER INTERFACE FOR HIGH SPEED SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY

QUALCOMM Incorporated, S...

1. A perpendicular magnetic tunnel junction, comprising:a free layer;
a reference layer; and
a barrier layer between the free layer and the reference layer, the barrier layer having a first interface that faces the free layer and a second interface that faces the reference layer, in which a surface of the first interface is fabricated to not physically correlate with a surface of the second interface.

US Pat. No. 10,431,733

PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICES WITH HIGH THERMAL STABILITY

THE ARIZONA BOARD OF REGE...

1. A perpendicular magnetic tunnel junction device (pMTJ) comprising:a first heavy metal layer;
a first thin dusting layer on the first heavy metal layer;
a first CoFeB layer on the first thin dusting layer;
a MgO barrier layer on the first CoFeB layer;
a second CoFeB layer on the MgO barrier layer;
a second thin dusting layer on the second CoFeB layer; and
a second heavy metal layer on the thin dusting layer.

US Pat. No. 10,431,728

SUPERCONDUCTING BUMP BONDS

Google LLC, Mountain Vie...

1. A method comprising:providing a first chip comprising a first circuit element;
forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;
forming a first titanium nitride barrier layer on the first aluminum interconnect pad;
providing a second chip comprising a second circuit element;
forming an indium bump bond; and
joining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element, wherein joining the first chip to the second chip is performed at room temperature.

US Pat. No. 10,431,723

MICRO LED MIXING CUP

Apple Inc., Cupertino, C...

1. A light emitting structure comprising:a light emitting diode (LED) bonded to a substrate;
a diffuser layer adjacent the LED, the diffuser layer comprising scattering particles dispersed in a matrix;
a well structure, wherein the LED is bonded to the substrate within a well opening of the well structure that completely laterally surrounds the LED, the diffuser layer laterally surrounds the LED within the well opening, and the well structure that completely laterally surrounds the LED is thicker than a portion of the diffuser layer and the LED within the well opening;
a transparent electrode layer on a top side of the LED, and spanning over the diffuser layer within the well opening and over a top surface of the well structure outside of the well opening;
an angular filter directly over the diffuser layer and the LED; and
an overcoat layer directly over the angular filter, the LED, and the transparent electrode layer spanning over the top surface of the well structure outside of the well opening.

US Pat. No. 10,431,721

LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME

CITIZEN ELECTRONICS CO., ...

1. A light-emitting device comprising:a substrate;
a plurality of light-emitting elements that are mounted on the substrate in a lattice manner;
a first resin layer that integrally seals the plurality of light-emitting elements and includes a first phosphor that is excited by light from the plurality of light-emitting elements at a concentration that is high as it goes to a lower end near the substrate from an upper end distant from the substrate; and
a second resin layer that is disposed on an upper side of the first resin layer via an interface, the second resin layer including a second phosphor that is the same as the first phosphor, at a uniform concentration, wherein
the first phosphor is precipitated on upper surfaces of the light-emitting elements and the upper surface of the substrate between the light-emitting elements, and the second phosphor is uniformly dispersed in the second resin layer at a concentration lower than the concentration of the first phosphor at the lower end of the first resin layer, and thereby generates a smaller amount of heat than the first phosphor.

US Pat. No. 10,431,713

NITRIDE UNDERLAYER AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTOELECTRON...

1. A nitride underlayer comprising, from bottom up:a substrate;
a sputtered AlN buffer layer; and
an AlXIn1-X-YGaYN layer (0?X?1, 0?Y?1) grown via MOCVD,
wherein the sputtered AlN buffer layer has a flat surface and band-shaped holes therein formed with laser scanning and configured to provide a stress release path to release stress during growth of the AlXIn1-X-YGaYN layer, and
wherein side walls of the holes and the AlN buffer layer are connected.

US Pat. No. 10,431,702

TRANSPARENT ELECTRODE, MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE EMPLOYING THE TRANSPARENT ELECTRODE

KABUSHIKI KAISHA TOSHIBA,...

1. A transparent electrode having a laminate structure comprising:a first metal oxide layer having an amorphous structure and electroconductivity,
a metal layer which comprises a metallic material comprising silver or copper,
a second metal oxide layer having an amorphous structure and electroconductivity, and
a third metal oxide layer having an amorphous structure and continuity,
stacked in this order.

US Pat. No. 10,431,689

THIN FILM TRANSISTOR AND DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A thin film transistor, comprising: a gate, a source, a drain, an active layer and a heat transmitting layer;wherein the heat transmitting layer is arranged on at least one side of the active layer;
wherein the thin film transistor further comprises:
a substrate and a gate insulating layer;
the gate is arranged on the substrate;
the gate insulating layer is arranged on the gate, and the active layer is arranged on the gate insulating layer;
the source and the drain are arranged on the active layer, or the source and the drain are arranged on the gate insulating layer and partially covered by the active layer.

US Pat. No. 10,431,663

METHOD OF FORMING INTEGRATED CIRCUIT WITH GATE-ALL-AROUND FIELD EFFECT TRANSISTOR AND THE RESULTING STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:providing a substrate;
forming a semiconductor fin on the substrate, wherein the semiconductor fin has a first width; and
forming a first transistor using the semiconductor fin, the forming of the first transistor comprising:
forming a sacrificial gate on a first portion of the semiconductor fin such that second portions of the semiconductor fin extend laterally beyond the sacrificial gate;
forming a sidewall spacer comprising a gate section on the sacrificial gate and fin sections on the second portions of the semiconductor fin;
removing the second portions of the semiconductor fin to create source/drain openings and to expose vertical surfaces of the first portion of the semiconductor fin;
widening the source/drain openings such that the widened source/drain openings have a second width that is greater than the first width of the semiconductor fin, wherein the first width of the semiconductor fin and the second width of the widened source/drain openings are measured in a same direction; and
after the widening of the source/drain openings, forming source/drain regions in the widened source/drain openings.

US Pat. No. 10,431,661

TRANSISTOR WITH INNER-GATE SPACER

INTEL CORPORATION, Santa...

1. An integrated circuit including at least one transistor, the integrated circuit comprising:a body including semiconductor material;
a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material and dopant;
a first spacer and a second spacer, the first and second spacers including one or more dielectrics;
a gate structure at least above the body, the gate structure between the first and second spacers, the gate structure including one or more metals, the gate structure having an upper portion, a middle portion, and a lower portion, the middle portion of the gate structure between the lower and upper portions of the gate structure, the lower portion of the gate structure closer to the body than the middle portion of the gate structure, wherein the lower portion of the gate structure has a larger width between the first and second spacers than the middle portion of the gate structure; and
a gate dielectric between the body and the gate structure.

US Pat. No. 10,431,648

MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES

Invensas Corporation, Sa...

1. A fabrication method comprising:(a) obtaining a first integrated circuit structure comprising a first substrate comprising a bottom surface having a cavity, and comprising a first circuitry comprising one or more first capacitors each of which is at least partially located in a respective first through silicon via (TSV) extending through the first substrate, each first capacitor comprising:
a first electroconductive layer formed within or upon an interior surface of the respective first TSV;
a dielectric layer formed over the first electroconductive layer and at least partially located in the respective first TSV;
a second electroconductive layer formed over the dielectric layer and at least partially located in the respective first TSV;
(b) obtaining a second integrated circuit structure comprising a second substrate comprising a second circuitry comprising one or more second capacitors each of which is at least partially located in a respective second TSV extending through the second substrate, each second capacitor comprising:
a first electroconductive layer formed within or upon an interior surface of the respective second TSV;
a dielectric layer formed over the first electroconductive layer and at least partially located in the respective second TSV;
a second electroconductive layer formed over the dielectric layer and at least partially located in the respective second TSV;
the second integrated circuit structure further comprising a semiconductor die attached to the top surface of the second substrate and electroconductively coupled to the second circuitry;
(c) after obtaining the first and second integrated circuit structures, positioning the first and second integrated circuit structures to align each first TSV with a corresponding second TSV, and bonding the first integrated structure to the second integrated structure, the bonding comprising bonding the first substrate to the second substrate with a direct dielectric-to-dielectric bond,
wherein in said bonding of the first and second integrated structures, for each aligned pair of a first TSV and a second TSV, the first electroconductive layer of the respective first capacitor becomes electroconductively coupled to the second electroconductive layer of the respective second capacitor with a metal-to-metal bond;
wherein at a conclusion of said bonding of the first and second integrated circuit structures, the semiconductor die is disposed in the cavity but is spaced from the first substrate to define a headspace between the cavity surface and the semiconductor die surface;
wherein the method further comprises injecting a filler into the headspace through one or more channels in the first substrate that communicate between the cavity and the top surface of the first substrate.

US Pat. No. 10,431,647

APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT

Micron Technology, Inc., ...

1. A semiconductor device comprising:a plate electrode elongating continuously in a horizontal direction to define first, second and third portions;
a first pad electrode overlapping the first portion of the plate electrode in a vertical direction to provide a first capacitance element therebetween;
a second pad electrode overlapping the second portion of the plate electrode in a vertical direction to provide a second capacitance element therebetween;
a third pad electrode overlapping the third portion of the plate electrode in a vertical direction to provide a third capacitance element therebetween;
a first contact coupled to the first pad electrode;
a transistor comprising a gate electrode;
a second contact coupled to the second pad electrode and the gate electrode; and
a third contact coupled to the third pad electrode.

US Pat. No. 10,431,644

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a display unit on a substrate, the display unit comprising a thin film transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode that are electrically coupled;
a pad unit at one outer side of the display unit on the substrate; a wiring unit comprising a plurality of wiring layers on the substrate to couple the display unit to the pad unit, each of the plurality of wiring layers comprising a plurality of wirings;
a thin film encapsulating layer covering the display unit, the thin film encapsulating layer comprising a stacked structure of a first inorganic layer, a first organic layer and a second inorganic layer, the first organic layer being between the first and second inorganic layers; and
a protrusion unit on the wiring unit, the protrusion unit overlapping a boundary of the thin film encapsulating layer,
wherein the protrusion unit is spaced apart from the gate electrode, the source electrode and the drain electrode of the thin film transistor,
the protrusion unit overlays with at least one of a boundary of the first inorganic layer and a boundary of the second inorganic layer of the thin film encapsulating layer, and
a portion of the thin film encapsulating layer is between the protrusion unit and the display unit,
wherein the protrusion unit comprises a plurality of support protrusions and a support base supporting the plurality of support protrusions, the display unit further comprises: a pixel electrode coupled to the drain electrode; an opposite electrode facing the pixel electrode;
a light-emitting layer between the pixel electrode and the opposite electrode; a planarization layer between the drain electrode and the pixel electrode; and a pixel defining layer partitioning a region of the light-emitting layer between the pixel electrode and the opposite electrode,
wherein the support base comprises a same material and is on a same layer as the planarization layer, and
the support protrusion comprises a same material and is on a same layer as the pixel defining layer.

US Pat. No. 10,431,642

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

LG DISPLAY CO., LTD., Se...

1. A method for fabricating a display device, the method comprising:providing a base film on an auxiliary substrate, wherein the base film includes a display area, and a first pad area;
providing a plurality of thin film transistors on the display area of the base film;
providing first pads on the first pad area of the base film;
providing a plurality of organic light emitting diodes connected with the plurality of thin film transistors;
providing an encapsulation layer for covering the plurality of organic light emitting diodes;
attaching a plurality of source flexible films onto the first pads, respectively;
separating the base film from the auxiliary substrate; and
cutting a part of the base film between each of the plurality of source flexible films.

US Pat. No. 10,431,640

DISPLAY DEVICE

Samsung Display Co., Ltd....

17. A display device comprising:a substrate comprising a display area including a plurality of pixels, and a peripheral area outside the display area and including a bending area;
a first conductive layer over the substrate;
a first insulating layer over the first conductive layer;
a second insulating layer over the first insulating layer, overlapping the bending area in a plan view, and having a first edge positioned around the bending area;
a second conductive layer over the second insulating layer such that the second insulating layer is between the second conductive layer and the first insulating layer in a sectional view; and
a third insulating layer over the second conductive layer,
wherein the first conductive layer includes a first signal wire in the peripheral area, extending to cross the first edge of the second insulating layer in the plan view, and not overlapping the bending area,
wherein the first signal wire includes a first portion that does not overlap by the second insulating layer in the plan view, and
wherein the third insulating layer includes a protector that overlaps at least a portion of the first portion, and has an edge that is parallel with an edge of the first portion in the plan view.

US Pat. No. 10,431,636

ELECTRONIC DEVICES HAVING DISPLAYS WITH OPENINGS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a housing;
a display mounted in the housing, wherein the display has an active area, an inactive area, an array of pixels in the active area, and a region in the active area; and
a light sensor located behind the display, wherein the light sensor detects light through the region in the active area.

US Pat. No. 10,431,634

ORGANIC ELECTROLUMINESCENCE DEVICE WITH RECESSES FILLED WITH A PHOSPHOR FILLING LAYER IN THE BASE MATERIAL

SHARP KABUSHIKI KAISHA, ...

1. An organic electroluminescence device comprising:a base material including a recessed portion on a surface side;
a reflective layer;
a filling layer having optical transparency;
a first electrode having optical transparency;
an organic layer including at least a light emitting layer; and
a second electrode having optical transparency and light reflectivity,
the reflective layer being disposed at least along a surface of the recessed portion, the filling layer being disposed in the recessed portion through the reflective layer, the first electrode being disposed at least on an upper-layer side of the filling layer, the organic layer being disposed on an upper-layer side of the first electrode, and the second electrode being disposed on an upper-layer side of the organic layer, wherein
the filling layer includes at least one type of phosphor, and
a lower face of the first electrode at a position inside the recessed portion is positioned lower than a plane including the surface side of the base material.

US Pat. No. 10,431,633

METHOD FOR PRODUCING A MULTI-COLORED LIGHT EMITTING COMPONENT

1. A method for producing a component comprising a substrate configured to emit an electromagnetic radiation in a first wavelength range and an electromagnetic radiation in a second wavelength range within one surface area, the method comprising:providing the substrate having a surface on which a plurality of electrodes are formed within the one surface area;
depositing a first layer stack on the entire one surface area, the first layer stack comprising at least one layer configured to cause emission of the electromagnetic radiation in the first wavelength range, and a first cover layer;
removing the first layer stack from a partial surface area comprising at least one of the electrodes;
depositing a second layer stack on the entire one surface area after the first layer stack was removed from the partial surface area, the second layer stack comprising at least one layer configured to cause emission of the electromagnetic radiation in the second wavelength range and a second cover layer; and
producing an electrically conductive connection between the first and second cover layers, the first and second cover layers configured to act as a counterelectrode, wherein the at least one layer of the second layer stack deposited on the first layer stack is short circuited so as not to emit the electromagnetic radiation in the second wavelength range.

US Pat. No. 10,431,632

LIGHT-EMITTING DEVICE, ELECTRONIC APPLIANCE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first light-emitting element including a first electrode, a first transparent conductive layer in contact with the first electrode, an EL layer in contact with the first transparent conductive layer, and a second electrode in contact with the EL layer;
a second light-emitting element including a third electrode, a second transparent conductive layer in contact with the third electrode, the EL layer in contact with the second transparent conductive layer, and the second electrode in contact with the EL layer; and
a third light-emitting element including a fourth electrode, the EL layer in contact with the fourth electrode, and the second electrode in contact with the EL layer,
wherein the EL layer includes a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer,
wherein the light with the wavelength ?1 is emitted from the first light-emitting element,
wherein the light with the wavelength ?2 is emitted from the second light-emitting element,
wherein the light with the wavelength ?3 is emitted from the third light-emitting element,
wherein a wavelength relation of ?3>?1>?2 is satisfied,
wherein an optical path length from the first electrode to the second light-emitting layer is 3?1/4, and an optical path length from the first electrode to the second electrode is ?1 in the first light-emitting element,
wherein an optical path length from the third electrode to the third light-emitting layer is 3?2/4, and an optical path length from the third electrode to the second electrode is ?2 in the second light-emitting element, and
wherein an optical path length from the fourth electrode to the first light-emitting layer is ?3/4, and an optical path length from the fourth electrode to the second electrode is ?3/2 in the third light-emitting element.

US Pat. No. 10,431,630

METHOD FOR PRODUCING TRANSISTORS, IN PARTICULAR SELECTION TRANSISTORS FOR NON-VOLATILE MEMORY, AND CORRESPONDING DEVICE

STMicroelectronics (Rouss...

11. A method for producing a plurality of MOS transistors commonly controlled by two vertical gates, comprising:etching a semiconductor substrate to form trenches which surround a rectangular semiconductor zone doped with a first type of conductivity providing a common channel region for the plurality of MOS transistors and having a buried region doped with a second type of conductivity providing a common source region for the plurality of MOS transistors, said rectangular semiconductor zone having opposed first sides and opposed second sides, wherein the opposed first sides are longer than the opposed second sides;
forming an isolated region comprising a gate material in first ones of said trenches on at least the opposed first sides of the rectangular semiconductor zone to form the two vertical gates for the plurality of MOS transistors;
making an electrically conductive connection in second ones of said trenches trench between the two vertical gates along the opposed second sides of the rectangular semiconductor zone; and
forming, at a top surface of the surrounded rectangular semiconductor zone providing the common channel region, a plurality of drain regions for the plurality of MOS transistors, wherein the drain regions are insulated from each other and doped with the second type of conductivity.

US Pat. No. 10,431,623

METHOD APPLIED TO BJT PIXEL OF IMAGE SENSOR APPARATUS AND IMAGE SENSOR APPARATUS

PixArt Imaging Inc., Hsi...

1. A method applied to a BJT pixel of a pixel array of an image sensor apparatus, comprising:obtaining at least one of a surface quality signal of a first image sensed by the BJT pixel and a shutter turn-on time corresponding to the first image; and
adaptively adjusting a pre-flash time of the BJT pixel for sensing of a second image according to the at least one of the surface quality signal of the first image and the shutter turn-on time corresponding to the first image;
wherein the second image follows the first image.

US Pat. No. 10,431,622

SOLID-STATE IMAGING APPARATUS, AND ELECTRONIC APPARATUS

SONY SEMICONDUCTOR SOLUTI...

1. A solid-state imaging apparatus, comprising:a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, wherein
the first pixel includes:
a first photoelectric conversion unit that generates electric charges according to an amount of incident light;
a first unnecessary electric charge drain unit that receives unnecessary electric charges being electric charges generated by the first photoelectric conversion unit; and
a first unnecessary electric charge discharge gate unit that discharges the unnecessary electric charges generated by the first photoelectric conversion unit to the first unnecessary electric charge drain unit in accordance with a height of a first electrical barrier formed between the first photoelectric conversion unit and the first unnecessary electric charge drain unit, and
the second pixel includes:
a second photoelectric conversion unit that generates electric charges according to an amount of incident light;
a second unnecessary electric charge drain unit that receives unnecessary electric charges being electric charges generated by the second photoelectric conversion unit; and
a second unnecessary electric charge discharge gate unit that discharges the unnecessary electric charges generated by the second photoelectric conversion unit to the second unnecessary electric charge drain unit in accordance with a height of a second electrical barrier formed between the second photoelectric conversion unit and the second unnecessary electric charge drain unit,
wherein the height of the first electrical barrier and the height of the second electrical barrier are different from each other.

US Pat. No. 10,431,614

EDGE SEALS FOR SEMICONDUCTOR PACKAGES

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor package comprising:a digital signal processor comprising a first side and a second side;
an image sensor array comprising a first side and a second side, the first side of the image sensor array coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and a first edge seal coupled directly with the HBI bond pads;
an etch stop layer comprised in the second side of the digital signal processor; and
one or more first openings extending from the second side of the image sensor array into the second side of the digital signal processor and to the etch stop layer in the second side of the digital signal processor, the one or more first openings coated with a sealing material, the one or more first openings forming a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor;
wherein the first edge seal is comprised of a first metal stack comprised within the digital signal processor directly coupled to a second metal stack comprised within the image sensor array.

US Pat. No. 10,431,611

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a thin film transistor, comprising:forming an active layer on a base substrate;
forming a metal layer on a surface of the active layer;
processing the metal layer using a patterning process for one time and an oxidation treatment process to form a source electrode, a drain electrode and a passivation layer, the source electrode and the drain electrode are in contact with the active layer, and the passivation layer is formed on a side of the source electrode and the drain electrode away from the active layer, which includes:
forming a photoresist layer on a surface of the metal layer;
processing the photoresist layer using the patterning process for one time to form a photoresist completely-removed region, photoresist partly-reserved regions and a photoresist completely-reserved region; wherein the photoresist partly-reserved regions are connected to the photoresist completely-reserved region;
performing a complete oxidation treatment on a region of the metal layer corresponding to the photoresist completely-removed region to form a first passivation portion;
removing a photoresist in the photoresist partly-reserved regions;
performing a partial oxidation treatment on a region of the metal layer corresponding to the photoresist partly-reserved regions to form the source electrode, the drain electrode and a second passivation portion; wherein the source electrode and drain electrode are in contact with the active layer, and the second passivation portion is formed on a side of the source electrode and the drain electrode away from the active layer; the first passivation portion and the second passivation portion form the passivation layer;
removing a photoresist in the photoresist completely-reserved region to form a conductive portion connected to the source electrode and the drain electrode.

US Pat. No. 10,431,602

ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display area; and
a surrounding area having a first signal line, and a second signal line disposed over, insulated from, and staggered at a staggering region with, the first signal line, the surrounding area encircling the display area;
wherein:
the surrounding area comprises a first zone and a second zone, wherein the first zone and the second zone are configured to have a height difference to form a substantially uneven upper surface of the array substrate to thereby allow a sealant to be securely attached onto the array substrate; and
an upper surface of the first zone is substantially flat across the first zone from over a side of the second signal line to an opposing side of the second signal line.

US Pat. No. 10,431,600

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A METAL OXIDE FILM

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor film at a first temperature;
processing the oxide semiconductor film into an island shape;
depositing a material to be a source electrode and a drain electrode over the oxide semiconductor film by a sputtering method;
processing the material to form the source electrode and the drain electrode;
forming a protective insulating film over the oxide semiconductor film, the source electrode and the drain electrode;
heating the protective insulating film at a second temperature which is higher than the first temperature;
forming a metal oxide film over the protective insulating film by a sputtering method; and
heating the protective insulating film at a third temperature which is higher than the first temperature,
wherein at least one of the second temperature and the third temperature is the highest in the method.

US Pat. No. 10,431,599

SUBSTRATE FOR DISPLAY DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. A display device, comprising:a substrate;
a pixel on the substrate, the pixel including:
a first TFT on the substrate, the first TFT including:
a first active layer formed of oxide semiconductor; and
a second thin film transistor (TFT) on the substrate, the second TFT including:
a gate electrode on the substrate,
at least a first part of a gate insulating film on the gate electrode,
a second active layer formed of polycrystalline silicon on the first part of the gate insulating film, wherein a bottom surface of the second active layer faces the gate electrode, and
a source electrode and a drain electrode contacting a top surface of the second active layer;
a light-emitting device electrically connected to the second TFT; and
a connection electrode contacting both of the drain electrode of the second TFT and an anode electrode of the light-emitting device between the drain electrode of the second TFT and the anode electrode.

US Pat. No. 10,431,595

MEMORY DEVICES HAVING VERTICALLY EXTENDING CHANNEL STRUCTURES THEREIN

Samsung Electronics Co., ...

1. A memory device comprising:a substrate having a first source film thereon;
an upper stacked structure on the first source film;
an electrically conductive channel structure extending through the upper stacked structure and the first source film, said channel structure comprising a channel pattern, which extends vertically through the upper stacked structure and the first source film, and an information storage pattern on a sidewall of the channel pattern;
a second source film extending between the first source film and a surface of said substrate, said second source film contacting the channel pattern and comprising an upward extending protrusion, which extends underneath the information storage pattern; and
a channel protective film extending between at least a portion of the protrusion and at least a portion of the information storage pattern.

US Pat. No. 10,431,594

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a lower stack;
a first upper stack disposed on the lower stack;
a second upper stack disposed on the lower stack, and spaced apart from the first upper stack by a select line separation trench;
first plugs configured to pass through the first upper stack and the lower stack, each of the first plugs including a sidewall protruding further into the select line separation trench than a sidewall of the first upper stack facing the select line separation trench to define a sidewall of the select line separation trench;
second plugs configured to pass through the second upper stack and the lower stack, each of the second plugs including a sidewall protruding further into the select line separation trench than a sidewall of the second upper stack facing the select line separation trench to define a sidewall of the select line separation trench; and
a select line separation layer formed along a contour of the protruded sidewalls of the first and second plugs in the select line separation trench.

US Pat. No. 10,431,593

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor memory device, comprising:a substrate; and
a first channel group, a second channel group, a third channel group, and a fourth channel group each arranged in a first direction on the substrate,
the first channel group to the fourth channel group being spaced apart from each other along a second direction on the substrate that crosses the first direction,
each of the first channel group, the second channel group, the third channel group, and the fourth channel group including a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate,
the first channel group and the second channel group being adjacent to each other in the second direction and spaced apart by a first distance in the second direction,
the second channel group and the third channel group being adjacent to each other in the second direction and spaced apart by a second distance less than the first distance in the second direction, and
the third channel group and the fourth channel group being adjacent to each other in the second direction and spaced apart by a third distance less than the second distance in the second direction.

US Pat. No. 10,431,592

3D MEMORY DEVICE

Trinandable S.r.l., Mila...

1. A 3D memory device comprising:a substrate;
at least one first group of four first “U”-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and
at least one second group of four second “U”-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string portion, each of the second “U”-shaped memory cells strings including memory cells stacks along the second source line selector side string portion and along the second bit line selector side string portion;
wherein the first and second source line selector side string portions are between the first and second bit line selector side string portions;
wherein a first pair of the first “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the first “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of first “U”-shaped memory cells strings and one surrounded by the other, a first pair of the second “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the second “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of second “U”-shaped memory cells strings and one surrounded by the other;
wherein first bit line selectors surround the first bit line selector side string portions and second bit line selectors surround the second bit line selector side string portions, and wherein the first bit line selectors comprise one first bit line selector for each of the first bit line selector side string portions and the second bit line selectors comprise one second bit line selector for each of the second bit line selector side string portions;
wherein the 3D memory device comprises a first, a second, a third and a fourth bit lines operatively associated to the first and second groups of four first and second “U”-shaped memory cells strings, wherein:
the first bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of one of the first pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of one of the first pair of the second “U”-shaped memory cells strings;
the second bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of the other one of the first pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of the other one of the first pair of the second “U”-shaped memory cells strings;
the third bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of one of the second pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of one of the second pair of the second “U”-shaped memory cells strings, and
the fourth bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of the other one of the second pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of the other one of the second pair of the second “U”-shaped memory cells strings.

US Pat. No. 10,431,591

NAND MEMORY ARRAYS

Micron Technology, Inc., ...

1. A NAND memory array, comprising:a vertical stack of alternating insulative levels and wordline levels, the wordline levels having terminal ends corresponding to control gate regions;
charge-trapping material along the control gate regions of the wordline levels, and being spaced form the control gate regions by charge-blocking material; the charge-trapping material along the wordline levels being charge-trapping material segments; the charge-trapping material segments being vertically spaced from one another by intervening regions; charge migration being impeded along said intervening regions relative to charge migration within the charge-trapping material segments; and
channel material extending vertically along the stack and being spaced from the charge-trapping material segments by charge-tunneling material.

US Pat. No. 10,431,588

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, the method comprising:providing a first semiconductor structure;
partially removing the first semiconductor structure to form a second semiconductor structure, wherein the second semiconductor structure has a first trench;
performing a first in-situ doping process on the second semiconductor structure to form a third semiconductor structure, wherein the third semiconductor structure includes a first electrode, and wherein the first electrode is positioned in the first trench;
after the first electrode has been formed, partially removing the third semiconductor structure to form a fourth semiconductor structure, wherein the fourth semiconductor structure has a second trench;
performing a second in-situ doping process on the fourth semiconductor structure to form a fifth semiconductor structure, wherein the fifth semiconductor structure includes a second electrode, and wherein the second electrode is positioned in the second trench; and
after the second electrode has been formed, forming a first gate member on the fifth semiconductor structure to form a sixth semiconductor structure, wherein each of the first gate member, the first electrode, and the second electrode directly contacts a first semiconductor portion, wherein the first semiconductor portion is positioned between the first electrode and the second electrode, and wherein an area of the first electrode is unequal to an area of the second electrode in a layout view of the semiconductor device.

US Pat. No. 10,431,587

SEMICONDUCTOR DEVICE FOR AVOIDING SHORT CIRCUIT BETWEEN ADJACENT STORAGE NODES AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate comprising a plurality of active regions, wherein each of the active regions comprises two source/drain regions, and each of the source/drain regions is disposed at a respective end of the active area;
a plurality of word lines disposed in the substrate, wherein each of the word lines is disposed elongated in a first direction;
a plurality of bit lines disposed on the substrate, wherein each of the bit lines is disposed elongated in a second direction and straddling the word lines, and each of the source/drain regions is disposed in a region surrounded by two of the word lines adjacent to each other and two of the bit lines adjacent to each other;
a plurality of storage node contacts disposed on the source/drain regions respectively, wherein a width of a top surface of each of the storage node contacts in the second direction is smaller than a width of a bottom surface of each of the storage node contacts in the second direction; and
a cap layer disposed on the word lines, wherein each of the storage node contacts is disposed on a plane of a top surface of the cap layer, and each of the storage node contacts has a trapezoid shape in the second direction.

US Pat. No. 10,431,586

SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
a first fin on the substrate;
a first source/drain on the first fin; and
a first contact plug on the first source/drain,
wherein a center of the first contact plug is offset from a center of the first fin,
wherein a bottom surface of the first contact plug is inclined with respect to a top surface of the substrate,
wherein the bottom surface of the first contact plug includes a first edge and a second edge opposite to the first edge, and
wherein the first edge is at a different level than the second edge.

US Pat. No. 10,431,585

SEMICONDUCTOR DEVICES WITH MULTI-GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,
wherein the first transistor comprises: a first nanowire having a first channel region; a first gate electrode surrounding the first nanowire; a first gate dielectric layer between the first nanowire and the first gate electrode; a first source/drain region connected to an edge of the first nanowire; and an inner-insulating spacer between the first gate dielectric layer and the first source/drain region,
the second transistor comprises: a second nanowire having a second channel region; a second gate electrode surrounding the second nanowire; a second gate dielectric layer between the second nanowire and the second gate electrode; and a second source/drain region connected to an edge of the second nanowire,
the second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region, and
the first source/drain region is not in contact with the first gate dielectric layer.

US Pat. No. 10,431,581

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) INTEGRATION WITH COMPOUND SEMICONDUCTOR DEVICES

QUALCOMM Incorporated, S...

1. A semiconductor device comprising:a substrate;
a well region disposed adjacent to the substrate;
a first fin disposed above the well region;
a second fin disposed above the substrate;
a gate region disposed adjacent to each of the first fin and the second fin;
at least one third fin disposed above the substrate;
a support layer disposed above the at least one third fin; and
a compound semiconductor device disposed above the support layer.

US Pat. No. 10,431,580

MONOLITHIC SINGLE CHIP INTEGRATED RADIO FREQUENCY FRONT END MODULE CONFIGURED WITH SINGLE CRYSTAL ACOUSTIC FILTER DEVICES

Akoustis, Inc., Huntersv...

1. A monolithic single chip single crystal device, the device comprising:a substrate having a substrate surface region and an underlying cavity region;
a first single crystal epitaxial layer formed overlying the substrate surface region;
a passive device configured within the first single crystal epitaxial layer and within the underlying cavity region;
one or more second single crystal epitaxial layers formed overlying the first single crystal epitaxial layer;
an active device configured overlying the one or more second single crystal epitaxial layers; and
wherein the first single crystal epitaxial layer and the one or more second single crystal epitaxial layers are formed as a monolithic epitaxial stack integrating multiple circuit functions.

US Pat. No. 10,431,579

DISPLAY PANEL INCLUDING ELECTROSTATIC PROTECTION CIRCUIT, DRIVING METHOD OF THE SAME, AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A display panel, comprising:a plurality of pixel circuits arranged in a display area of the display panel, wherein the plurality of pixel circuits is arranged in rows and columns, the display area of the display panel comprises a first display area and a second display area arranged along a row direction, and an outer edge of the second display area extends stepwise along a column direction;
a plurality of data lines each extending along the column direction, wherein the plurality of data lines corresponds to a plurality of columns of the plurality of pixel circuits in one-to-one correspondence;
a plurality of signal line groups, wherein the plurality of signal line groups corresponds to a plurality of rows of the plurality of pixel circuits in one-to-one correspondence, and each of the plurality of signal line groups comprises a scan line and a light-emitting control signal line each extending along the row direction; and
a plurality of first electrostatic protection circuits, wherein the plurality of first electrostatic protection circuits corresponds and is connected to the data lines in the second display area in one-to-one correspondence, each of the plurality of first electrostatic protection circuits is electrically connected to a scan line and a light-emitting control signal line of a same signal line group, and each of the plurality of first electrostatic protection circuits is used to discharge static electricity on a data line connected to the first electrostatic protection circuit to the scan line or the light-emitting control signal line connected to the first electrostatic protection circuit.

US Pat. No. 10,431,578

ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes,
wherein an emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor; and
an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node,
wherein a gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor.

US Pat. No. 10,431,576

MEMORY CELL ARRAY AND METHOD OF MANUFACTURING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a memory cell array, the method comprising:generating a first set of tiles extending in a first direction, wherein the generating the first set of tiles comprises:
generating a first layout design of a first set of memory cells, each tile of the first set of tiles corresponds to the first layout design of the first set of memory cells, and each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction;
generating a second set of tiles, wherein the generating the second set of tiles comprises:
generating a second layout design of a second set of memory cells, each tile of the second set of tiles corresponds to the second layout design of the second set of memory cells, and each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction,
wherein each tile of the first set of tiles extends in a third direction different from the first direction and the second direction, the first set of tiles and the second set of tiles alternate with each other in the second direction, and each tile of the second set of tiles extends in the third direction, and at least one of the above generating operations is performed by a hardware processor, and the first layout design is stored in a non-transitory computer-readable medium; and
manufacturing the memory cell array based on at least the first layout design.

US Pat. No. 10,431,575

MULTI-DIE ARRAY DEVICE

NXP B.V., Eindhoven (NL)...

1. A method for fabricating a multi-die package, the method comprising:placing a plurality of flip chip dies and a plurality of splitter dies on a sacrificial carrier, each flip chip die and each splitter die positioned in an active side down orientation on the sacrificial carrier;
performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier, wherein the sacrificial carrier comprises test probe circuitry;
testing the plurality of flip chip dies and the plurality of splitter dies in a probe test using the test probe circuitry;
replacing any faulty flip chip dies and any faulty splitter dies as indicated by the testing;
overmolding the plurality of flip chip dies and the plurality of splitter dies on the sacrificial carrier to form a panel of embedded dies;
planarizing the panel of embedded dies to expose a back surface of each flip chip die and each splitter die in a back surface of the panel of embedded dies;
forming a metallization layer across the back surface of the panel of embedded dies that contacts the back surface of each flip chip die and each splitter die; and
removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and each splitter die is exposed in the front surface of the panel of embedded dies.

US Pat. No. 10,431,574

METHODS AND SYSTEMS FOR PACKAGING SEMICONDUCTOR DEVICES TO IMPROVE YIELD

Marvell World Trade Ltd.,...

1. A method for packaging semiconductor devices in a chamber, the method comprising:arranging a carrier substrate including a first semiconductor device and a second semiconductor device within the chamber;
flowing a molding compound into the chamber to cover surfaces of the first semiconductor device, the second semiconductor device, and the carrier substrate; and
flowing a forming gas into the chamber while curing the molding compound, wherein the forming gas includes a reactive gas configured to react with the first semiconductor device and the second semiconductor device during curing,
wherein the forming gas reforms broken bonds of the first semiconductor device and the second semiconductor device resulting from the curing.

US Pat. No. 10,431,571

OPTO-ELECTRONIC MODULES, IN PARTICULAR FLASH MODULES, AND METHOD FOR MANUFACTURING THE SAME

ams Sensors Singapore Pte...

1. An opto-electronic module comprising:a substrate member;
at least two emission members mounted on said substrate member;
at least one detecting member mounted on said substrate member;
an optics member comprising a first lens and a second lens; and
a spacer member arranged between said substrate member and said optics member, the spacer member abutting a first side of the substrate member and a first side of the optics member, and establishing a well-defined distance between the substrate member and the optics member, wherein the first side of the substrate member faces the first side of the optics member;
wherein the first lens is assigned to a first of said at least two emission members and the second lens is assigned to a second of said at least two emission members, said first lens and said first emission member being arranged such that light emitted from said first emission member traverses predominantly said first lens, and said second lens and said second emission member being arranged such that light emitted from said second emission member traverses predominantly said second lens, wherein a light intensity distribution of light emitted by said first emission member through said first lens leaving the opto-electronic module is different from a light intensity distribution of light emitted by said second emission member through said second lens leaving the opto-electronic module.

US Pat. No. 10,431,570

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYODA GOSEI CO., LTD., ...

1. A light emitting device, comprising:a substrate;
a plurality of light emitting elements disposed on the substrate;
a transparent resin embedded only in a space between the plurality of light emitting elements; and
a phosphor containing resin layer formed on the plurality of light emitting elements and the transparent resin,
wherein the transparent resin includes no phosphor,
wherein the phosphor containing resin layer comprises a plurality of regions comprising different kinds of phosphors,
wherein each one of the plurality of regions is disposed on each one of the plurality of light emitting elements,
wherein the plurality of light emitting elements are disposed on the substrate in a stacking direction of the phosphor containing resin layer on the plurality of light emitting elements, and
wherein, in the stacking direction, a bottom surface of the phosphor containing resin layer and a border of the plurality of regions of the phosphor containing resin layer are disposed on a top surface of the transparent resin.

US Pat. No. 10,431,567

WHITE CERAMIC LED PACKAGE

CREE, INC., Durham, NC (...

1. An emitter package, comprising:a casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of light emitting devices (LEDs) on said first set of bond pads, with said light emitting devices and portions of said bond pads exposed through said cavity;
a plurality of electrodes at least on the bottom surface of said casing; and
through-holes integral to each of said bond pads, wherein said through-holes are embedded within said casing and extend into each of said bond pads and said electrodes to provide electrical paths between said bond pads and said electrodes;
wherein at least one of said chip carrier parts or connection parts is at least partially defined by an indentation.

US Pat. No. 10,431,566

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus comprising a first die and a second die, each of the first and second dies including a face-side and a back-side, the face-side of the first die being defined by first and second edges substantially parallel to each other, and the face-side of the second die being defined by third and fourth edges substantially parallel to each other;wherein the first die comprises, on the face-side thereof:
at least one first interconnection region between the first and second edges;
a first coupling region between the at least one first interconnection region and the first edge;
a second coupling region between the at least one first interconnection region and the second edge;
a first redistribution wiring electrically coupling the at least one first interconnection region to the first coupling region;
a second redistribution wiring electrically coupling the at least one first interconnection region to the second coupling region;
a first supply circuit including a third coupling region and configured to provide a first voltage to the third coupling region, the third coupling region being between the at least one first interconnection region and the first edge; and
a second supply circuit including a fourth coupling region and configured to provide a second voltage to the fourth coupling region, the fourth coupling region being between the at least one first interconnection region and the second edge;
wherein the second die comprises, on the face-side thereof:
at least one second interconnection region between the third and fourth edges;
a fifth coupling region between the at least one second interconnection region and the third edge;
a sixth coupling region between the at least one second interconnection region and the fourth edge;
a third redistribution wiring electrically coupling the at least one second interconnection region to the fifth coupling region;
a fourth redistribution wiring electrically coupling the at least one second interconnection region to the sixth coupling region;
a third supply circuit including a seventh coupling region and configured to provide the second voltage to the seventh coupling region, the seventh coupling region being between the at least one second interconnection region and the third edge; and
a fourth supply circuit including an eighth coupling region and configured to provide the first voltage to the eighth coupling region, the eighth coupling region being between the at least one second interconnection region and the fourth edge; and
wherein the first die is bonded to the second die in a face-to-face relationship such that the first, second, third and fourth coupling regions are vertically aligned with the seventh, eighth, fifth and sixth coupling regions, respectively.

US Pat. No. 10,431,556

SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS MOUNTED OVER BOTH SURFACES OF SUBSTRATE

Micron Technology, Inc., ...

1. A method of forming a semiconductor device, the method comprising:mounting a first semiconductor chip to a first side of a substrate, the first semiconductor chip including a first short side and a plurality of first electrodes positioned along the first short side;
mounting a second semiconductor chip to a second side of the substrate, the second semiconductor chip having a second short side and a plurality of second electrodes positioned along the second short side, wherein—
the second semiconductor chip is mounted to the substrate such that (a) the first electrodes of the first semiconductor chip are laterally external to the second semiconductor chip, and (b) the second electrodes of the second semiconductor chip are laterally external to the first semiconductor chip,
the second side is opposite the first side, and
an outermost surface of the second semiconductor chip is separated from a surface of the substrate by a first distance;
forming a plurality of conductive posts at the second side of the substrate, wherein an outermost surface of the conductive posts is separated from the surface of the substrate by a second distance greater than the first distance;
sealing at least a portion of the first semiconductor chip with a first sealant; and
sealing at least a portion of the second semiconductor chip and conductive posts with a second sealant.

US Pat. No. 10,431,555

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

DISCO CORPORATION, Tokyo...

12. A method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin, comprising the steps of:preparing a wiring board having a plurality of mounts for mounting semiconductor chips thereon, the mounts being disposed in respective areas demarcated on an upper surface of a wiring board by a plurality of projected dicing lines which cross each other, upstanding encircling walls disposed between said mounts and said projected dicing lines in surrounding relation to said mounts individually, and side-surface shield layers for blocking electromagnetic waves, disposed individually in said upstanding encircling walls in surrounding relation to said mounts and extending in thicknesswise directions of said upstanding encircling walls;
mounting the semiconductor chips individually on said mounts on said wiring hoard;
supplying synthetic resin to spaces surrounded by said upstanding encircling walls over the semiconductor chips mounted on said mounts on said wiring board to seal said semiconductor chips, thereby producing a sealed board;
after said sealed board has been produced, dividing said sealed board along said projected dicing lines into individual semiconductor packages;
after said sealed board has been produced, forming an upper-surface shield layer for blocking electromagnetic waves on upper surfaces of the sealing synthetic resin of said semiconductor packages; and
after said sealed board has been produced, removing the sealing synthetic resin supplied to upper surfaces of said upstanding encircling walls along the side-surface shield layers, thereby exposing tip ends of the side-surface shield layers disposed individually in said upstanding encircling walls.

US Pat. No. 10,431,554

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier;
an electronic component disposed over a top surface of the carrier;
a package body disposed over the top surface of the carrier and covering the electronic component; and
a shield layer, comprising a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer,
wherein the first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer,
wherein a permeability of the first electrically conductive layer is lower than each of a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.

US Pat. No. 10,431,551

VISUAL IDENTIFICATION OF SEMICONDUCTOR DIES

TEXAS INSTRUMENTS INCORPO...

1. An electronic device, comprising:a die; and
a package surrounding the die, wherein the electronic device includes a unique visual identification mark, wherein a first character of a set of characters in the unique visual identification mark includes at least one line that connects two adjacent sides of a bond pad of the die, wherein the unique visual identification mark encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

US Pat. No. 10,431,550

FAN-OUT ELECTRONIC COMPONENT PACKAGE

Samsung EIectro-Mechanics...

1. A fan-out electronic component package, comprising:a core member comprising a through-hole, wiring layers and vias configured to electrically connect the wiring layers to each other;
a first electronic component disposed in the through-hole, and comprising filters configured to filter different frequency bands;
a first encapsulant disposed to cover portions of the core member and the first electronic component, and fill portions of the through-hole;
a connection member disposed on the core member and the first electronic component, and comprising a redistribution layer electrically connected to the wiring layers and the first electronic component;
a second electronic component disposed on the connection member and electrically connected to the redistribution layer; and
a second encapsulant disposed to cover the second electronic component,
wherein the first electronic component comprises a first active surface comprising a first connection pad disposed thereon and a second active surface opposite the first active surface and comprising a second connection pad disposed thereon.

US Pat. No. 10,431,549

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A semiconductor package, comprising:a stacked-die structure comprising:
a first semiconductor die comprising a first active surface;
a circuit layer disposed on and not extending laterally beyond the first active surface of the first semiconductor die;
a second semiconductor die electrically connected to the first semiconductor die through the circuit layer and comprising a second active surface facing towards the first active surface of the first semiconductor die;
a plurality of conductive features disposed on the circuit layer and the first semiconductor die and electrically connected to the first semiconductor die and the second semiconductor die, wherein
a portion of the plurality of conductive features laterally surrounds the second semiconductor die, and
the plurality of conductive features comprise a first coupling structure disposed between the first semiconductor die and the second semiconductor die and a second coupling structure surrounding the first coupling structure; and
a first encapsulant encapsulating the second semiconductor die and the plurality of conductive features;
a second encapsulant laterally encapsulating the stacked-die structure, wherein a second back surface of the second semiconductor die opposite to the second active surface and a top surface of the second coupling structure are coplanar with a top surface of the first encapsulant and a top surface of the second encapsulant; and
a redistribution layer disposed on the second encapsulant and the staked-die structure, wherein
the redistribution layer is electrically connected to the staked-die structure, and
the second coupling structure is electrically connected to the first semiconductor die and the redistribution layer.

US Pat. No. 10,431,544

SELF-FORMING BARRIER FOR COBALT INTERCONNECTS

INTERNATIONAL BUSINESS MA...

11. An interconnect for a semiconductor device, comprising;a silicon dioxide insulator layer that includes a trench;
a low-k dielectric film formed on a surface of the insulator layer in the trench;
a diffusion barrier layer formed on a surface of the low-k dielectric film in the trench, wherein the diffusion barrier layer does not extend laterally outside the trench;
an adhesion layer formed on the low-k dielectric film in the trench; and
an elemental cobalt conductor formed on the adhesion layer, wherein the diffusion barrier layer prevents material from the elemental cobalt conductor from diffusing into the insulator layer.

US Pat. No. 10,431,539

SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING DISCHARGE CONTROL CIRCUIT

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor integrated circuit, comprising:an output circuit connected between a power supply and a first node at which a load component can be connected, the output circuit electrically connecting the power supply to the first node when a first control signal supplied to the output circuit is a first logic level and electrically disconnecting the power supply from the first node when the first control signal is a second logic level;
a discharge circuit connected between the first node and a reference potential source, the discharge circuit electrically disconnecting the first node from the reference potential source when a second control signal supplied to the discharge circuit is the first logic level and electrically connecting the first node to the reference potential source when the second control signal is the second logic level; and
a discharge control circuit configured to set the second control signal to the second logic level when the first control signal changes to the second logic level from the first logic level and to set the second control signal to the first logic level after a predetermined time has elapsed from a time when the first control signal changes to the second logic level, wherein
the discharge control circuit includes:
a delay circuit receiving the first control signal as an input and generating a delay signal by delaying a signal corresponding to the first control signal; and
a first logic circuit configured to perform a logical operation on at least the first control signal and the delay signal and to output a logical operation result as the second control signal.

US Pat. No. 10,431,536

INTERPOSER SUBSTRATE AND SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate;
a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate; and
an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip,
wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess in a region overlapped with the lower semiconductor chip, and
wherein the dummy wiring layer is electrically floating.

US Pat. No. 10,431,535

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. A method for fabricating an electronic package, comprising:providing a packaging substrate having a circuit structure and an antenna structure, wherein the circuit structure has a first side and a second side opposite to the first side, the circuit structure comprises at least one dielectric layer and a circuit layer formed on the dielectric layer, and the antenna structure is in contact with the first side of the circuit structure, without an antenna on the second side of the circuit structure; and
disposing at least one electronic component on the second side of the circuit structure and electrically connecting the electronic component to the second side of the circuit structure, wherein the electronic component is a semiconductor chip, wherein the circuit structure further comprises a core layer.

US Pat. No. 10,431,532

SEMICONDUCTOR DEVICE WITH NOTCHED MAIN LEAD

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a main lead on which the semiconductor element is disposed;
a first auxiliary lead and a second auxiliary lead, the first auxiliary lead and the second auxiliary lead each being electrically connected to the semiconductor element;
a first wire electrically connecting the semiconductor element to the first auxiliary lead;
a second wire electrically connecting the semiconductor element to the second auxiliary lead; and
a resin package covering the semiconductor element, the main lead, the first auxiliary lead, and the second auxiliary lead,
wherein the main lead includes a main full thickness part and a main eave part that is smaller in size in a thickness direction of the semiconductor element than the main full thickness part,
the semiconductor element overlaps with each of the main full thickness part and the main eave part in plan view,
the main eave part includes an end face that faces the first auxiliary lead and the second auxiliary lead and that is formed with a notch recessed toward a center of the main lead in plan view,
the first auxiliary lead includes a first auxiliary full thickness part and a first auxiliary eave part that is smaller in size in the thickness direction of the semiconductor element than the first auxiliary full thickness part,
the second auxiliary lead includes a second auxiliary full thickness part and a second auxiliary eave part that is smaller in size in the thickness direction of the semiconductor element than the second auxiliary full thickness part,
the first wire is bonded at a position overlapping with the first auxiliary full thickness part in plan view, and the second wire is bonded at a position overlapping with the second auxiliary full thickness part in plan view,
the first wire has an end bonded to the semiconductor element, the end of the first wire being bonded to the semiconductor element at a position that overlaps with the main full thickness part in plan view,
the main eave part is formed with a pair of main lateral connecting parts that project in mutually opposite directions from a main body of the main eave part, the main lateral connecting parts including respective front faces and respective back faces opposite to the respective front faces, the front faces being flush with the end face of the main eave part, and
the second wire has an end bonded to the semiconductor element, the end of the second wire being bonded to the semiconductor element at a position that overlaps with the main eave part in plan view and is located between the main full thickness part and an imaginary straight line connecting the back faces of the main lateral connecting parts in plan view.

US Pat. No. 10,431,531

SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method comprising:electrically connecting one or more leadfingers of a leadframe to a semiconductor die;
encapsulating the semiconductor die, a removable tie, and a support paddle with an encapsulant, wherein the removable tie connects the support paddle to the leadframe, and wherein the support paddle is attached to the semiconductor die; and
removing a frame portion of the leadframe and at least portion of the removable tie from the encapsulated semiconductor die and support paddle.

US Pat. No. 10,431,529

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a first island;
a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element and a sixth semiconductor element mounted on the first island and spaced apart from each other in plan view, the second semiconductor element overlapping with the first semiconductor element as viewed in a first direction, the third semiconductor element overlapping with the first semiconductor element as viewed in a second direction perpendicular to the first direction, the fourth semiconductor element overlapping with the third semiconductor element as viewed in the first direction, the fifth semiconductor element overlapping with the third semiconductor element as viewed in the second direction, the sixth semiconductor element overlapping with the fifth semiconductor element as viewed in the first direction;
a second island spaced apart from the first island;
a first control IC mounted on the second island for driving the first semiconductor element, the third semiconductor element and the fifth semiconductor element;
a first terminal, a second terminal and a third terminal spaced from each other and spaced from the first island and the second island in plan view;
a first wire connecting the first semiconductor element to the second semiconductor element;
a second wire connecting the first wire to the first terminal;
a third wire connecting the third semiconductor element to the fourth semiconductor element;
a fourth wire connecting the third wire to the second terminal;
a fifth wire connecting the fifth semiconductor element to the sixth semiconductor element; and
a sixth wire connecting the fifth wire to the third terminal,
wherein in the second direction, a center of the first control IC is offset from a center of the first semiconductor element, a center of the second semiconductor element and a center of the third semiconductor element.

US Pat. No. 10,431,525

BOND-OVER-ACTIVE CIRCUITY GALLIUM NITRIDE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a first layer with a plurality of cells, each cell comprising a drain finger, a source finger and a gate ring; and
a second layer comprising a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad;
wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer;
wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact; and
wherein one of the drain pad or the source pad is positioned over one of the drain finger or the source finger.

US Pat. No. 10,431,521

INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF

CUBIC CORPORATION, San D...

1. A method of forming an integrated electronic component, comprising:providing an electronic device;
disposing a plurality of layers over a substrate, wherein the layers comprise one or more of dielectric, conductive and sacrificial materials; and
forming from the layers a microstructure comprising: a waveguide section comprising a plurality of waveguides, the waveguides each having a non-solid core volume within an outer conductor surrounding the core volume; and a transition structure coupling the waveguides to the electronic device,
wherein the waveguides each comprise a center conductor disposed in and surrounded by the outer conductor with the non-solid volume disposed between the center conductor and the outer conductor, and wherein the transition structure comprises a post mechanically coupling the substrate to the center conductor.

US Pat. No. 10,431,518

RFIC DEVICE AND METHOD OF FABRICATING SAME

NINGBO SEMICONDUCTOR INTE...

1. A radio frequency integrated circuit (RFIC) device, comprising:a first semiconductor layer having a first surface and a second surface;
a first dielectric layer on the first surface of the first semiconductor layer;
a semiconductor component within the first semiconductor layer and the first dielectric layer, the semiconductor component including at least one transistor;
a second dielectric layer on the second surface of the first semiconductor layer; and
a sheet-like heat sink, formed of a material at least including a dielectric material on a surface of the second dielectric layer opposite to the first semiconductor layer and configured to dissipate heat from the semiconductor component, wherein the sheet-like heat sink includes a first heat sink sheet arranged in a vertical projection area of the at least one transistor.

US Pat. No. 10,431,517

ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES

Advanced Micro Devices, I...

1. A semiconductor chip device, comprising:a first semiconductor chip having a side and a floor plan with a high heat producing area and a low heat producing area;
at least one second semiconductor chip stacked on the side and on the low heat producing area; and
means for thermally contacting the side and transferring heat from the high heat producing area.

US Pat. No. 10,431,515

METHODS AND APPARATUS FOR SELF-ALIGNMENT OF INTEGRATED CIRCUIT DIES

Marvell World Trade Ltd.,...

1. A method comprising:depositing, on a surface of a substrate, a hydrophobic material to form a pattern that exposes areas of the substrate surface for placement of integrated circuit (IC) dies;
applying, to the exposed areas of the substrate surface, a water-based solution such that droplets of the water-based solution form on the exposed areas of the substrate surface;
placing IC dies on the droplets of the water-based solution that are formed on the exposed areas of the substrate surface; and
causing the droplets of the water-based solution to evaporate such that the IC dies settle on the exposed areas of the substrate surface.

US Pat. No. 10,431,514

SEMICONDUCTOR PACKAGES HAVING DUAL ENCAPSULATION MATERIAL

STMicroelectronics (Malta...

1. A semiconductor package comprising:a substrate having a center portion and a perimeter portion, the perimeter portion having a surface and first and second thicknesses exposed at the surface, wherein the first and second thicknesses are different from each other, at least one of the first and second thicknesses being less than a third thickness of the center portion;
a first die of semiconductor material mounted to the substrate at the center portion;
a transparent encapsulation material on the center portion of the substrate and around the first die; and
an opaque encapsulation material on the perimeter portion of the substrate,
wherein the surface of the perimeter portion is coplanar with an outer surface of the opaque encapsulation material.

US Pat. No. 10,431,513

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Micron Technology, Inc., ...

12. A stacked microelectronic device, comprising:a first microelectronic device, including:
a first lower substrate with a footprint,
a first microelectronic die carried on the first lower substrate and electrically coupled to the first lower substrate by a first plurality of wirebonds, and
a first upper substrate disposed over the first microelectronic die and electrically coupled to the first lower substrate by a second plurality of wirebonds,
wherein the first microelectronic die includes a first perimeter array of bond-pads on an upper side thereof, and wherein the first upper substrate is positioned inboard of the first perimeter array; and
a second microelectronic device disposed over the first microelectronic device, the second microelectronic device including:
a second lower substrate with the footprint,
a second microelectronic die carried on the second lower substrate and electrically coupled to the second lower substrate by a third plurality of wirebonds, and
a second upper substrate disposed over the second microelectronic die and electrically coupled to the second lower substrate by a fourth plurality of wirebonds,
wherein the second microelectronic die includes a second perimeter array of bond-pads on an upper side thereof, and wherein the second upper substrate is positioned inboard of the second perimeter array;
wherein the second lower substrate is electrically coupled to the first upper substrate by a plurality of solder connections.

US Pat. No. 10,431,512

SEMICONDUCTOR PACKAGE WITH BARRIER FOR RADIO FREQUENCY ABSORBER

Analog Devices, Inc., No...

1. A semiconductor package comprising:a substrate;
a frame;
an integrated device die mounted to the substrate, the integrated device die comprising a transmitter die; and
a lid comprising a ventilation hole, the lid mounted to at least one of the frame and substrate over the integrated device die, wherein the lid, frame, and substrate at least partly define a cavity in which the integrated device die is disposed, the lid comprising a compartment formed therein, the compartment separated from the cavity by a partition,
wherein the ventilation hole provides fluid communication between the compartment and the outside environs.

US Pat. No. 10,431,511

POWER AMPLIFIER WITH RF STRUCTURE

QUALCOMM Incorporated, S...

1. A shield structure, comprising:a first substrate;
a second substrate located above the first substrate;
a power amplifier on the first substrate and configured to output a drive current;
a first inductor embedded in the first substrate and coupled to the power amplifier;
a second inductor embedded in the second substrate and coupled to the first inductor, the first inductor and the second inductor configured to match an impedance of the power amplifier; and
a ground wall surrounding the first inductor and the second inductor, the ground wall configured to isolate a magnetic field produced by the first inductor and the second inductor.

US Pat. No. 10,431,509

NON-MAGNETIC PACKAGE AND METHOD OF MANUFACTURE

General Electric Company,...

1. A micro-electro-mechanical (MEMS) package comprising:a non-magnetic package body comprising:
a floor; and
a wall extending from the floor and surrounding a cavity;
a non-magnetic seal ring formed on an upper edge of the wall;
a MEMS device mounted to the floor via an indium preform; and
a non-magnetic metallic lid hermetically sealed to the package body by the seal ring, the non-magnetic metallic lid comprising a molybdenum substrate coated with layers of copper and palladium.

US Pat. No. 10,431,508

METHODS AND SYSTEMS TO IMPROVE PRINTED ELECTRICAL COMPONENTS AND FOR INTEGRATION IN CIRCUITS

VQ RESEARCH, INC., Palo ...

1. An integrated circuit, comprising:a circuit die;
a lid covering a top surface of the circuit die;
a ceramic matrix packaging, and
wherein the ceramic matrix packaging comprises at least one of an embedded resistor, capacitor, inductor, and multi-property device disposed within the ceramic matrix packaging,
wherein formation of the integrated circuit is specified by successive additions of a plurality of voxels of material through a deposit of droplets, and
wherein the at least one of an embedded resistor, capacitor, inductor, and multi-property device is oriented at an angle to minimize a parasitic effect.

US Pat. No. 10,431,507

CONTACT-VIA CHAIN AS CORROSION DETECTOR

Robert Bosch GmbH, Stutt...

1. A detector for determining a faulty semiconductor component, comprising:a semiconductor component;
a contact-via chain situated laterally at a distance from the semiconductor component and which surrounds the semiconductor component in regions;
a guard ring situated laterally at another distance from the semiconductor component; and
an evaluation unit situated on the semiconductor component, wherein the evaluation unit is configured to apply a permanent electrical voltage to the contact-via chain to detect a resistance value of the contact-via chain and to produce an output signal when the resistance value of the contact-via chain exceeds a threshold value;
wherein the contact-via chain is connected, through the evaluation unit, to a positive electrical voltage by a substrate with n-doped wells and a p-doped substrate or to a negative electrical voltage by the substrate with the use of p-doped wells in an n-doped substrate, and
wherein the contact-via chain is surrounded by dielectric material or is embedded in the dielectric material.

US Pat. No. 10,431,505

METHOD OF INSPECTING SURFACE HAVING A MINUTE PATTERN BASED ON DETECTING LIGHT REFLECTED FROM METAL LAYER ON THE SURFACE

Samsung Electronics Co., ...

1. A method, comprising:forming a metal layer on a surface of an inspection target device, the inspection target device including a pattern, such that the metal layer is formed on the pattern and an outer surface of the metal layer is distal to the surface of the inspection target device;
emitting light incident on the outer surface of the metal layer, and adjusting the emitted light to be incident to the outer surface of the metal layer and normal to the outer surface of the metal layer;
detecting a spectrum of the light reflected from the outer surface of the metal layer; and
generating, based on the detected spectrum, information associated with a structural characteristic of the pattern formed on the surface of the inspection target device,
wherein the pattern includes a plurality of patterns, the patterns being spaced apart according to a particular period,
wherein the generating includes measuring a width of at least one pattern of the plurality of patterns and a distance between adjacent patterns, based on a material of the metal layer.

US Pat. No. 10,431,503

SACRIFICIAL CAP FOR FORMING SEMICONDUCTOR CONTACT

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first semiconductor fin and a second semiconductor fin;
a gate stack arranged over a channel region of the first semiconductor fin and the second semiconductor fin;
a source/drain region comprising a crystalline material having top faceted surfaces and bottom faceted surfaces, the bottom faceted surfaces contacting the first semiconductor fin and the second semiconductor fin, wherein the source/drain region comprises an undulating or non-planar surface;
an air gap formed conformally and in direct contact with the top faceted surfaces and the bottom faceted surfaces of the source/drain region; and
a conductive contact material in contact with the top faceted surfaces of the crystalline material.

US Pat. No. 10,431,500

MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a trench in a material;
forming a conductor in a lower portion of the trench;
performing a first atomic layer deposition (ALD) of a first liner material to line a middle portion and an upper portion of the trench, the middle portion is between the lower portion and the upper portion;
flowing a fill material comprising an insulator to fill the middle portion and the upper portion of the trench;
removing the fill material from the upper portion of the trench to leave the fill material in the middle portion of the trench; and
performing a second ALD of a second material to fill the upper portion of the trench with the second material.

US Pat. No. 10,431,495

SEMICONDUCTOR DEVICE WITH LOCAL CONNECTION

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a first trench silicide (TS) coupled to a first source or drain (S/D), a second TS coupled to a second S/D, and a gate metal separated from the first and second TS;
forming a trench above and on sides of the gate metal;
forming a local connection metal in the trench such that the gate metal is coupled to the first TS and the second TS; and
forming a local connection cap on top of the local connection metal.

US Pat. No. 10,431,494

BEOL SELF-ALIGNED INTERCONNECT STRUCTURE

International Business Ma...

1. An interconnect structure comprising:a lower interconnect level comprising a first interconnect dielectric material layer having a first electrically conductive line feature embedded therein;
an upper interconnect level located above the lower interconnect level and comprising a second interconnect dielectric material layer having a first electrically conductive via feature, a second electrically conductive line feature, and a second electrically conductive via feature stacked one atop the other, and embedded in the second interconnect dielectric material layer, wherein the first and second electrically conductive via features are self-aligned perpendicularly to, and along the direction of, the second electrically conductive line feature;
a third interconnect dielectric material layer having a lower portion embedded in the second interconnect dielectric material layer and laterally adjacent the second electrically conductive via feature, and an upper portion that is located above the second interconnect dielectric material layer and the second electrically conductive via feature; and
a first metal liner located on an entirety of a topmost surface of the second electrically conductive line feature and entirely separating the second electrically conductive line feature from the second electrically conductive via feature and from the third interconnect dielectric material layer.

US Pat. No. 10,431,489

SUBSTRATE SUPPORT APPARATUS HAVING REDUCED SUBSTRATE PARTICLE GENERATION

APPLIED MATERIALS, INC., ...

1. An apparatus for supporting a substrate, comprising:a support surface; and
a plurality of substrate contact elements protruding from the support surface, wherein the plurality of substrate contact elements are formed of a non-silicon based material having a hardness less than or equal to a hardness of silicon, having non-adhesiveness with silicon-based materials, having a coefficient of static friction that prevents sliding when contacting silicon-based materials, having a surface roughness less than or equal to 10 Ra, and that is electrically conductive such that particles generated from a substrate when contacting the plurality of substrate contact elements is reduced.

US Pat. No. 10,431,487

MICRO-TRANSFER-PRINTABLE FLIP-CHIP STRUCTURES AND METHODS

X-Celeprint Limited, Cor...

1. A semiconductor structure suitable for transfer printing, comprising:a handle substrate;
a cured bonding layer disposed in contact with the handle substrate;
a capping layer disposed in contact with the bonding layer;
a patterned release layer disposed in contact with the capping layer; and
a completed semiconductor device disposed on or over the patterned release layer and attached to an anchor disposed on the handle substrate with at least one tether,
wherein the at least one tether is in a common plane with an exposed entry path to the patterned release layer.

US Pat. No. 10,431,486

WAFER ALIGNING DEVICE AND METHOD FOR ALIGNING A WAFER INTO A SPECIFIED ROTATIONAL ANGULAR POSITION

1. A wafer aligning device for placing a wafer in a predetermined rotational angular position (?S), the wafer aligning device comprising:a wafer table having a table receiving area configured to receive the wafer at the predetermined rotational angular position (?S); and
an aligning mechanism having an aligning receiving area configured to align the wafer into the predetermined rotational angular position (?S),
wherein the aligning receiving area is configured in an aligning position (PA) when receiving the wafer such that the aligning receiving area is positioned above the wafer table,
wherein the aligning mechanism is configured to place the wafer received in the aligning receiving area on the table receiving area of the wafer table by traversing toward the table receiving area via a vertical downward movement, and
wherein the aligning mechanism is configured to simultaneously align the wafer to the predetermined rotational angular position while traversing toward the table receiving area via the vertical downward movement.

US Pat. No. 10,431,484

METHOD AND STATION FOR MEASURING THE CONTAMINATION OF A TRANSPORT BOX FOR THE ATMOSPHERIC CONVEYANCE AND STORAGE OF SUBSTRATES

PFEIFFER VACUUM, Annecy ...

1. A method for measuring contamination of a transport box for atmospheric conveyance and storage of substrates, the method comprising:measuring a concentration of at least one gaseous species inside the transport box by a measurement device comprising at least one gas analyzer and a measurement line connecting the at least one gas analyzer to an interface, the interface placing the measurement line in communication with an internal atmosphere of the transport box; and
supplying a gas flow containing water vapor to the measurement device.

US Pat. No. 10,431,481

LOAD LOCK APPARATUS AND SUBSTRATE PROCESSING SYSTEM

TOKYO ELECTRON LIMITED, ...

1. A load lock apparatus having a load lock chamber connected to a vacuum transfer chamber configured to transfer a substrate under a vacuum pressure state via a communication hole which is opened and closed by a gate valve, and configured to be capable of switching an inner pressure into an atmospheric pressure state and the vacuum pressure state, the load lock apparatus comprising:a load lock chamber main body having a carrying-in/out hole through which a substrate container, which is configured to accommodate a plurality of substrates and has an attachable/detachable cover installed on a side surface of the substrate container, can be carried in/out, and an opening/closing door configured to open and close the carrying-in/out hole, wherein the communication hole is formed in a side surface of the load lock chamber;
a cover attaching/detaching mechanism installed at a height position which is a lower side of the communication hole in the load lock chamber, and configured to be horizontally advanced and retracted between an attachment/detachment position at which the cover is attached/detached to/from the substrate container and a retraction position at which the cover is retracted from the attachment/detachment position; and
an elevating mechanism installed in the load lock chamber and including a mounting table on which the substrate container is loaded, the elevating mechanism being configured to lift and lower the mounting table such that the cover-installed side surface of the substrate container loaded on the mounting table can be moved between a height position opposite to the communication hole and a height position opposite to the cover attaching/detaching mechanism.

US Pat. No. 10,431,479

HEAT TREATMENT APPARATUS AND TEMPERATURE CONTROL METHOD

Tokyo Electron Limited, ...

1. A heat treatment apparatus comprising:a processing container configured to accommodate a substrate therein;
a furnace body having a heater configured to heat the substrate accommodated in the processing container and provided around the processing container;
a blower configured to supply a coolant to a space between the processing container and the furnace body; and
a controller having a continuous operation mode in which the blower is continuously energized and an intermittent operation mode in which energization and de-energization of the blower are repeated, and configured to control driving of the blower based on an instruction voltage,
wherein the controller drives the blower in the intermittent operation mode when the instruction voltage is higher than 0 V and lower than a predetermined threshold voltage.

US Pat. No. 10,431,478

TIME-VARYING FREQUENCY POWERED HEAT SOURCE

1. An apparatus comprising:an article of manufacture, comprising an active heat source including:
a predefined substrate; and
two or more electrodes, formed at manufacture to be located directly or indirectly on the substrate, the electrodes configured to receive a non-zero frequency time-varying electrical energy that is coupled by the one or more electrodes to the substrate to generate a frequency-controlled heat source in the substrate, the heat source location selected along a length of the two or more electrodes by adjusting the frequency of the time-varying electrical energy; and
wherein the two or more electrodes include first and second electrodes separated from each other by different minimum spacing at different locations on at least one of the first and second electrodes so that adjusting the frequency of the time-varying electrical energy is capable of selectably adjusting at least one corresponding frequency-dependent current path between the first and second electrodes to provide the frequency-controlled heat at at least one desired location in the substrate.

US Pat. No. 10,431,476

METHOD OF MAKING A PLURALITY OF PACKAGED SEMICONDUCTOR DEVICES

NXP B.V., Eindhoven (NL)...

1. A method of making a plurality of packaged semiconductor devices, the method comprising:providing a carrier blank having a die receiving surface and an underside;
mounting a plurality of semiconductor dies on the die receiving surface of the carrier blank,
wherein the dies extend to a first height above the die receiving surface;
depositing an encapsulant on the die receiving surface,
wherein an upper surface of the encapsulant is located above said first height,
whereby the encapsulant covers the plurality of semiconductor dies; and
singulating the carrier blank and encapsulant to form the plurality of packaged semiconductor devices by:
sawing into the underside of the carrier to saw through the carrier blank and
saw partially through the encapsulant to a saw depth intermediate the first height and the upper surface of the encapsulant,
wherein said sawing separates the carrier blank into a plurality of carriers,
each carrier having
an underside corresponding to the underside of the carrier blank and
a die receiving surface corresponding to the die receiving surface of the carrier blank,
wherein the die receiving surface of each carrier has at least one of said semiconductor dies mounted thereon; and
removing encapsulant from upper surface of the encapsulant at least until said saw depth is reached;
further comprising contacting an electrical probe to the underside of at least some of the carriers to test the packaged semiconductor devices; and
performing solder reflow;
wherein said solder reflow is performed after said testing the packaged semiconductor devices;
further comprising contacting an electrical probe to the underside of at least some of the carriers to re-test the packaged semiconductor devices after said solder reflow is performed.

US Pat. No. 10,431,474

METHOD FOR FORMING A CAVITY AND A COMPONENT HAVING A CAVITY

Robert Bosch GmbH, Stutt...

1. A method for forming a cavity in a silicon substrate, comprising:providing the silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate;
situating an etching mask on the surface of the silicon substrate, the etching mask having a mask opening having a first transverse edge and a second transverse edge parallel to the first transverse edge, the first transverse edge being situated in the first plane of the silicon substrate, the etching mask having a first retarding structure that protrudes into the mask opening, the etching mask having a first etching projection region, and all further edges of the mask opening outside the first etching projection region being situated parallel to {111} planes of the silicon substrate; and
anisotropically etching the silicon substrate during a defined etching duration, an etching rate in the <111> directions of the silicon substrate being lower than in other spatial directions, the first retarding structure being undercut going out from the first etching projection region in a first undercut direction, the first undercut direction being oriented parallel to the first transverse edge and the second transverse edge of the mask opening, the etching duration being defined such that through the anisotropic etching, a cavity forms in the silicon substrate hat has an opening on the surface of the silicon substrate, the opening of the cavity being limited at two sides by the first transverse edge and the second transverse edge of the mask opening, and at a further side by a first longitudinal edge, perpendicular to the first and to the second transverse edge, that is produced by the undercutting of the first retarding structure, and the etching duration moreover being defined such that after elapsing of the etching duration, the first plane of the silicon substrate is exposed and forms a floor surface of the cavity.

US Pat. No. 10,431,473

FINFET WITH SOURCE/DRAIN STRUCTURE AND METHOD OF FABRICATION THEREOF

Taiwan Semiconductor Manu...

1. A method of semiconductor device fabrication, comprising:providing a plurality of adjacent first fins extending from a substrate, wherein the plurality of adjacent first fins include at least two inner first-fin sidewalls facing each other and two outer first-fin sidewalls facing away from the plurality of adjacent first fins;
depositing a first spacer layer over the plurality of adjacent first fins, wherein the first spacer layer includes a first region disposed along the at least two inner first-fin sidewalls and a second region disposed over the top of the plurality of adjacent first fins and along the two outer first-fin sidewalls;
performing a tilted implantation process to the first spacer layer so that the second region and a top portion of the first region of the first spacer layer have a first dopant concentration corresponding to a first etch rate and a bottom portion of the first region has a second dopant concentration corresponding to a second etch rate greater than the first etch rate;
performing an etching process to remove a top portion of the second region to form two outer first-fin spacers along the two outer first-fin sidewalls, remove a top portion of the plurality of adjacent first fins, and remove at least partially the first region; and
forming a first epitaxial layer over a remaining portion of the plurality of adjacent first fins, wherein the forming of at least a portion of the first epitaxial layer is laterally constrained by the two outer first-fin spacers.

US Pat. No. 10,431,470

METHOD OF QUASI-ATOMIC LAYER ETCHING OF SILICON NITRIDE

TOKYO ELECTRON LIMITED, ...

1. A method of etching, comprising:providing a substrate having a first material containing silicon nitride and a second material that is different from the first material with the second material provided along first and second side walls of the first material such that the first material is between the second material on the first and second side walls and the first material fills a region between the second material on the first and second side walls;
forming a first chemical mixture by plasma-excitation of a first process gas containing H and optionally a noble gas;
exposing the first material on the substrate to the first chemical mixture to hydrogenate a surface and subsurface regions of the first material, the subsurface regions including a first portion and a second portion below the first portion, and after the exposing first material to the first chemical mixture the first portion has a hydrogen concentration greater than that at the surface and the second portion has a hydrogen concentration lower than that at the surface;
thereafter, forming a second chemical mixture by plasma-excitation of a second process gas containing S and F, and optionally a noble element;
exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material; and
repeating the exposing the first material to the first chemical mixture and the exposing the first material to the second plasma-excited process gas to remove the first material between the second material until a layer positioned under the first material is exposed, and after the layer positioned under the first material is exposed, the second material remains on the substrate.

US Pat. No. 10,431,468

LOCATION-SPECIFIC TUNING OF STRESS TO CONTROL BOW TO CONTROL OVERLAY IN SEMICONDUCTOR PROCESSING

Tokyo Electron Limited, ...

1. A method for correcting wafer overlay, the method comprising:receiving a substrate having a working surface and having a backside surface opposite to the working surface, the substrate having an initial overlay error resulting from one or more micro fabrication processing steps that have been executed to create at least part of a semiconductor device on the working surface of the substrate;
receiving an initial bow measurement of the substrate that maps z-height deviations on the substrate relative to one or more reference z-height values;
generating an overlay correction pattern that defines adjustments to internal stresses at specific locations on the substrate based on the initial bow measurement of the substrate, wherein a first given location on the substrate has a different internal stress adjustment defined as compared to a second given location on the substrate in the overlay correction pattern; and
physically modifying internal stresses on the substrate at specific locations on the substrate according to the overlay correction pattern resulting in a modified bow of the substrate, the substrate with the modified bow having a second overlay error, the second overlay error having reduced overlay error as compared to the initial overlay error.

US Pat. No. 10,431,467

MODULE INCLUDING METALLIZED CERAMIC TUBES FOR RF AND GAS DELIVERY

Lam Research Corporation,...

1. A module useful for processing semiconductor substrates in a vacuum chamber including a processing zone in which a semiconductor substrate may be processed, the module comprising:a ceramic body;
a stem made of ceramic material having a flange bonded to the ceramic body; and
at least one metallized ceramic tube configured to supply gas to the ceramic body and supply power to an electrode embedded in the ceramic body.

US Pat. No. 10,431,464

LINER PLANARIZATION-FREE PROCESS FLOW FOR FABRICATING METALLIC INTERCONNECT STRUCTURES

International Business Ma...

1. A method for fabricating a device, comprising:forming a dielectric layer on a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
depositing a first layer of metallic material over the dielectric layer to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening;
depositing a second layer of metallic material to fill the opening with metallic material;
removing an overburden portion of the second layer of metallic material by planarizing the second layer of metallic material down to an overburden portion of the liner layer on the upper surface of the dielectric layer;
applying a surface treatment to the overburden portion of the liner layer on the upper surface of the dielectric layer to convert the overburden portion of the liner layer into a layer of metal nitride material, wherein the portion of the liner layer deposited on exposed surfaces within the opening is not converted into the layer of metal nitride material; and
wherein applying a surface treatment comprises performing a plasma nitridation surface treatment to infuse nitrogen atoms into the overburden portion of the liner layer; and selectively etching away the layer of metal nitride material.

US Pat. No. 10,431,463

SUBSTRATE HOLDING DEVICE, LITHOGRAPHY APPARATUS, AND ARTICLE PRODUCTION METHOD

Canon Kabushiki Kaisha, ...

1. A substrate holding device configured to hold a substrate, the substrate holding device comprising:a holding member including a center part having a hole through which gas is exhausted from a space between the substrate and the holding member and an outer peripheral part surrounding the center part;
a moving unit configured to relatively move the substrate and the holding member in a direction perpendicular to a substrate holding surface of the center part; and
a seal member provided on the outer peripheral part, configured to seal the space and configured to be deformed in response to a distance between the substrate and the holding member relatively moved by the moving unit,
wherein at least one of the outer peripheral part and the seal member has a through hole, and
wherein a first end of the through hole faces the space and a second end of the through hole faces an atmosphere.

US Pat. No. 10,431,459

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device, the method comprising:forming an etching target layer on a substrate;
forming an upper mask layer on the etching target layer;
forming a plurality of preliminary mask patterns on the upper mask layer, two neighboring preliminary mask patterns of the plurality of preliminary mask patterns defining a preliminary opening; and
performing an ion beam etching process on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns,
wherein the first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

US Pat. No. 10,431,457

METHOD FOR FORMING PATTERNED STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for forming a patterned structure, comprising:providing a layout pattern, wherein the layout pattern comprises:
a plurality of first lines, wherein each of the first lines is elongated in a first direction; and
a plurality of second lines, wherein each of the second lines is elongate in a second direction, wherein the first direction is orthogonal to the second direction;
decomposing the layout pattern for forming:
a first mask comprising:
a plurality of first line patterns corresponding to the first lines; and
a first block pattern corresponding to the second lines; and
a second mask comprising:
a plurality of second line patterns corresponding to the second lines; and
a second block pattern corresponding to the first lines; and
performing a first photolithography process with the first mask and a second photolithography process with the second mask for forming a patterned structure comprising:
a plurality of first line structures, wherein each of the first line structures is elongated in the first direction, and the first line structures are defined by and structurally confined to a region where the first line patterns and the second block pattern overlap with one another; and
a plurality of second line structures, wherein each of the second line structures is elongated in the second direction, and the second line structures are defined by and structurally confined to a region where the second line patterns and the first block pattern overlap with one another.

US Pat. No. 10,431,456

IMPRINT APPARATUS AND METHOD

SAMSUNG DISPLAY CO., LTD....

1. An imprint method comprising:applying a material layer for forming a patterned layer having a pattern, to a substrate;
feeding a stamp film including a stamp pattern corresponding to the pattern of the patterned layer, along a pressure roller and an idle roller, to dispose the stamp pattern of the stamp film facing the material layer on the substrate;
forming the patterned layer having the pattern, comprising:
the pressure roller pressing the stamp film including the stamp pattern toward the material layer on the substrate to contact the stamp pattern of the stamp film with the material layer and form the pattern in the material layer,
curing the material layer in contact with the stamp pattern of the stamp film, and
moving the pressure roller and the idle roller to peel the stamp film including the stamp pattern off the material layer which is cured, by a peeling force, to form the patterned layer having the pattern from the material layer which is cured; and
detecting a defect in the pattern of the formed patterned layer, during the peeling of the stamp film off the material layer which is cured, by sensing the peeling force in real time by a pressure sensor connected to the pressure roller.

US Pat. No. 10,431,454

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

Nuvoton Technology Corpor...

1. A semiconductor substrate, comprising:a base;
a buffer layer, disposed on the base, wherein doped regions are disposed in a portion of a surface of the buffer layer and the doped regions are separated from each other;
a mask layer, disposed on the buffer layer and located on the doped regions; and
a first GaN layer, disposed on the buffer layer and covering the mask layer.

US Pat. No. 10,431,452

PROTECTIVE FILM FORMING METHOD

Tokyo Electron Limited, ...

1. A protective film forming method, comprising steps of:causing an entire surface of a silicon-containing underfilm to be terminated with fluorine by supplying an activated fluorine-containing gas to the silicon-containing underfilm formed on a substrate having a surface including a plurality of recesses and a flat surface provided between the adjacent recesses, the substrate being provided in a process chamber;
nitriding a surface of the silicon-containing underfilm formed on the flat surface of the substrate by supplying a nitriding gas converted to plasma to the silicon-containing underfilm terminated with fluorine such that a silicon adsorption site is formed on the surface of the silicon-containing underfilm formed on the flat surface of the substrate;
adsorbing a silicon-containing gas on the silicon adsorption site by supplying the silicon-containing gas to the silicon-containing underfilm;
changing a rotational speed of the turntable between the steps of causing the entire surface of the silicon-containing underfilm to be terminated with fluorine and nitriding the surface of the silicon-containing underfilm,
wherein the substrate is arranged on a turntable along a circumferential direction thereof,
wherein a fluorine-containing gas supply region configured to supply the activated fluorine-containing gas to the substrate, a silicon-containing gas supply region configured to supply the silicon-containing gas to the substrate, and a nitriding gas supply region configured to supply the nitriding gas to the substrate are arranged above the turntable, along the circumferential direction, and apart from each other,
wherein the step of causing the entire surface of the silicon-containing underfilm to be terminated with fluorine is performed by stopping the supply of the silicon-containing gas in the silicon-containing gas supply region and the supply of the nitriding gas in the nitriding gas supply region and supplying the activated fluorine-containing gas to the substrate in the fluorine-containing gas supply region while rotating the turntable at least one time,
wherein the step of nitriding the surface of the silicon-containing underfilm is performed by stopping the supply of the activated fluorine-containing gas in the fluorine-containing gas supply region and supplying the nitriding gas converted to the plasma in the nitriding gas supply region while rotating the turntable a plurality of times, and
wherein the step of adsorbing the silicon-containing gas on the silicon adsorption site is performed by stopping the supply of the activated fluorine-containing gas in the fluorine-containing gas supply region and supplying the silicon-containing gas to the substrate in the silicon-containing gas supply region while rotating the turntable a plurality of times.

US Pat. No. 10,431,450

FILM FORMING METHOD

TOKYO ELECTRON LIMITED, ...

1. A film forming method for a target object including a main surface and grooves formed in the main surface, the method comprising:accommodating the target object in a processing chamber of a plasma processing apparatus;
after the accommodating, supplying a first gas into the processing chamber; and
after the supplying the first gas, supplying a second gas and a high frequency power for plasma generation in the processing chamber by using a gas that includes the second gas in the processing chamber,
wherein:
the first gas comprises an oxidizing agent that does not include a hydrogen atom;
the second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom;
a film containing silicon and oxygen is selectively formed on the main surface of the target object except the grooves; and
a temperature of the target object during the supplying the second gas is lower than 450° C.

US Pat. No. 10,431,449

MICROELECTRONIC SYSTEMS CONTAINING EMBEDDED HEAT DISSIPATION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, Inc., Austin, T...

1. A microelectronic system, comprising:a substrate having a tunnel therein;
a microelectronic component attached to the substrate at a location enclosing an end of the tunnel;
a solder material attaching the microelectronic component to the substrate, the solder material having a first thermal conductivity; and
an embedded heat dissipation structure at least partially contained within the tunnel, the embedded heat dissipation structure comprising:
a thermally-conductive component bond layer in contact with the microelectronic component and having a second thermal conductivity substantially equivalent to or exceeding the first thermal conductivity;
a thermal conduit member at least partially contained within the tunnel and bonded to the microelectronic component through the thermally-conductive component bond layer; and
a conduit bond layer extending around a periphery of the thermal conduit member and bonding the thermal conduit member to inner sidewalls of the substrate defining the tunnel.

US Pat. No. 10,431,448

WET ETCHING METHOD, SUBSTRATE LIQUID PROCESSING APPARATUS, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A wet etching method for wet-etching a substrate including a first surface and a second surface opposite to the first surface and formed with a first layer as a lower layer and a second layer as an upper layer that are laminated on at least a peripheral edge portion of the first surface of the substrate, the method comprising:a process of rotating the substrate;
a process of supplying a chemical liquid capable of etching both the first layer and the second layer, to the first surface of the rotating substrate; and
a first process of supplying an etching inhibiting liquid to the second surface of the substrate while supplying the chemical liquid to the substrate;
wherein in the first process, the etching inhibiting liquid is supplied while rotating the substrate such that the etching inhibiting liquid wraps around the first surface through an edge of the substrate and reaches a first region extending from the edge of the substrate on the peripheral edge portion of the first surface to a first radial position located radially inward from the edge on the first surface.

US Pat. No. 10,431,447

POLYSILICON CHIP RECLAMATION ASSEMBLY AND METHOD OF RECLAIMING POLYSILICON CHIPS FROM A POLYSILICON CLEANING APPARATUS

HEMLOCK SEMICONDUCTOR COR...

1. A polysilicon chip reclamation assembly comprising:a polysilicon cleaning apparatus configured to clean a plurality of bodies of polysilicon;
a plurality of polysilicon chips generated from the bodies of polysilicon during cleaning thereof, wherein each of the plurality of polysilicon chips has a longest dimensional length ranging from 0.1 mm to 25.0 mm;
a polysilicon apparatus drain line configured to route the plurality of polysilicon chips from the polysilicon cleaning apparatus to a main chip drain line, wherein the main chip drain line is oriented at a downward slope away from the polysilicon apparatus drain line;
a fluid source fluidly coupled to the main chip drain line and configured to inject a fluid into the main chip drain line to drive the plurality of polysilicon chips through the main chip drain line;
a chip collection tank, wherein the main chip drain line comprises an outlet proximate the chip collection tank, the outlet configured to direct the plurality of polysilicon chips into the chip collection tank; and
a chip routing line extending between an outlet of the chip collection tank and a conveyor.

US Pat. No. 10,431,441

REDUCING CALIBRATION OF COMPONENTS IN AN IMAGING PLATE SCANNER

PALODEX GROUP OY, Tuusul...

1. A photomultiplier tube for use in an imaging plate scanner, the photomultiplier tube comprising:a housing having a window;
a focusing electrode located in the housing;
an electron multiplier dynode located in the housing;
an anode;
a cathode and
a memory storing parameters.

US Pat. No. 10,431,438

TITANIUM TARGET FOR SPUTTERING AND MANUFACTURING METHOD THEREOF

1. A high-purity titanium target for sputtering having a purity of 5N5 (99.9995%) or higher, wherein the high-purity titanium target has no macro pattern in which a difference in average crystal grain size is 20% or more and a difference in crystal orientation ratio is 10% or more on the target surface.

US Pat. No. 10,431,437

DETECTING AN ARC OCCURING DURING SUPPLYING POWER TO A PLASMA PROCESS

TRUMPF Huettinger Sp. z o...

1. A method of detecting an arc occurring during supplying power to a plasma process in a plasma chamber, comprising:determining a first signal sequence present between a DC source and an output signal generator, wherein the output signal generator comprises an input connected to the DC source and an output connected to the plasma chamber;
determining a second signal sequence present at the output of the output signal generator;
determining a reference signal sequence based on one of the first and second signal sequences;
comparing the reference signal sequence with the other of the first and second signal sequences; and
detecting an arc by determining if the reference signal sequence and the other of the first and second signal sequences cross.

US Pat. No. 10,431,436

METHOD AND SYSTEM OF MONITORING AND CONTROLLING DEFORMATION OF A WAFER SUBSTRATE

SPTS TECHNOLOGIES LIMITED...

1. A method of monitoring and controlling deformation of an electrically insulating wafer substrate during plasma etching of the wafer substrate, the method comprising:disposing an electrically insulating wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the electrically insulating wafer substrate is exposed;
passing a process gas into the process chamber;
applying a radio frequency bias voltage to the platen assembly;
etching the exposed entire upper surface of the electrically insulating wafer substrate by generating a plasma within the process chamber;
determining, during said etching, a warping of the electrically insulating wafer substrate relative to the platen assembly by monitoring a voltage difference between the platen assembly and the process chamber;
attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.

US Pat. No. 10,431,429

SYSTEMS AND METHODS FOR RADIAL AND AZIMUTHAL CONTROL OF PLASMA UNIFORMITY

Applied Materials, Inc., ...

1. A system that generates a plasma for processing a workpiece, comprising:a process chamber that is operable to be evacuated;
a housing that defines a waveguide cavity;
a first conductive plate disposed within the housing, wherein the first conductive plate faces the process chamber and is disposed on a distal side of the waveguide cavity from the process chamber;
one or more adjustment devices that couple with the first conductive plate and the housing, wherein the one or more adjustment devices are operable to adjust at least a position of the first conductive plate within a range of positions;
a second conductive plate, coupled with the housing and interposed between the waveguide cavity and the process chamber, the second conductive plate forming a plurality of apertures therein for allowing electromagnetic radiation within the waveguide cavity to propagate, through the apertures, into the process chamber;
a dielectric plate that seals off the process chamber from the waveguide cavity such that the waveguide cavity is not evacuated when the process chamber is evacuated; and
one or more electronics sets that transmit the electromagnetic radiation into the waveguide cavity, such that the plasma forms when at least one process gas is within the process chamber, and the electromagnetic radiation propagates into the process chamber from the waveguide cavity.

US Pat. No. 10,431,427

MONOPOLE ANTENNA ARRAY SOURCE WITH PHASE SHIFTED ZONES FOR SEMICONDUCTOR PROCESS EQUIPMENT

Applied Materials, Inc., ...

1. A plasma reactor comprising:a chamber body having an interior space that provides a plasma chamber;
a gas distribution port to deliver a processing gas to the plasma chamber;
a workpiece support to hold a workpiece;
an antenna array comprising a plurality of monopole antennas extending partially into the plasma chamber, wherein the plurality of monopole antennas are divided into a plurality of groups of monopole antennas; and
an AC power source to supply a first AC power to the plurality of monopole antennas, wherein the AC power source is configured to generate AC power on a plurality of power supply lines at a plurality of different phases, and different groups of monopole antennas are coupled to different power supply lines.

US Pat. No. 10,431,415

X-RAY TUBE ION BARRIER

General Electric Company,...

1. An X-ray tube comprising:a cathode configured to emit a beam of electrons;
an anode spaced from the cathode to define an acceleration area to accelerate the beam of electrons through an opening in the anode;
a target spaced from the anode and adapted to emit x-rays when struck by the beam of electrons;
an ion barrier electrode disposed between the cathode and the target and defining an aperture through which the beams of electrons can pass, wherein the ion barrier electrode is connectable to a voltage source so as to apply a voltage bias to the ion barrier electrode and generate a positively charged potential barrier across the ion barrier electrode or about a region including the ion barrier electrode or about a region including the ion barrier electrode and space extending beyond the perimetric boundaries of the ion barrier electrode, to deflect positively charged ions contacting the potential barrier.

US Pat. No. 10,431,410

ELECTRICAL SWITCHING APPARATUS AND HARNESS ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. A harness assembly for an electrical switching apparatus, said electrical switching apparatus comprising a frame having a slot, and a printed circuit board coupled to said frame, said harness assembly comprising:a plurality of individual wires each structured to extend through the slot and be electrically connected to said printed circuit board; and
a restriction mechanism comprising a sleeve member surrounding each of said plurality of individual wires in order to prevent longitudinal movement of each of said plurality of individual wires with respect to each other, said sleeve member being structured to be disposed within the slot,
wherein each of said plurality of individual wires has a helical-shaped portion disposed internal with respect to said sleeve member, thereby allowing each of said plurality of individual wires to engage said sleeve member.

US Pat. No. 10,431,399

CRADLE ASSIST DEVICES AND RELATED KITS AND METHODS

Eaton Intelligent Power L...

1. A retrofit kit for a breaker cradle having a base with right and left handles that communicate with lock members, wherein the lock members are retractable and extendable relative to sidewalls of the base, comprising:a cradle assist assembly that releasably engages or attaches to the breaker cradle, wherein the cradle assist assembly has at least one actuator attached to right and left transverse members, wherein the right and left transverse members are above and external to a front of the base and are configured to engage respective right and left handles of the breaker cradle to thereby allow retraction of the right and left handles and the lock members using a single operator,
wherein, when engaged or attached to the breaker cradle, the at least one actuator is entirely external to the front of the base and the breaker cradle.

US Pat. No. 10,431,398

SWIVEL CATCH APPARATUS, ENCLOSED SWITCH ASSEMBLIES, AND OPERATIONAL METHODS THEREOF

SIEMENS INDUSTRY, INC., ...

1. A switch box mechanism, comprising:a swivel catch having an elongated body, a pivot configured to allow the swivel catch to rotate, and a catch end, the catch end including a catch configured to engage with a lid, and a slide feature formed in the elongated body;
a rod including a first end configured to couple to a switch engagement member that is configured to engage with a rotor of a line base assembly, and a slide portion of the rod slidably engaged with the slide feature; and
a spring configured to bias the swivel catch,
wherein the catch end of the elongated body of the swivel catch including a lock-out hole therethrough and a second lock-out hole formed through an operating handle such that the swivel catch is mounted in such a way that the lock-out hole aligns with the second lock-out hole in an off position which allows a lock to be placed through the swivel catch and the operating handle while a gap between the swivel catch and the operating handle allows the lock to pass only through the swivel catch and not the operating handle thus providing a cover lock-out function in that an enclosure is locked with the lock without locking the operating handle.

US Pat. No. 10,431,391

CAPACITOR PACKAGE STRUCTURE AND ANTI-OXIDATION ELECTRODE FOIL THEREOF

APAQ TECHNOLOGY CO., LTD....

1. An anti-oxidation electrode foil, comprising:a base material structure having a top surface and a bottom surface;
a first conductive material structure disposed on the top surface of the base material structure; and
a first carbonaceous material structure disposed on the first conductive material structure;
wherein one portion of the first conductive material structure is a first outermost layer for contacting the first carbonaceous material structure, the first outermost layer of the first conductive material structure is a first oxygen-containing metal compound layer formed by an oxidation process, and the first oxygen-containing metal compound layer is disposed between the other portion of the first conductive material structure and the first carbonaceous material structure so as to prevent oxygen from contacting the other portion of the first conductive material structure;
wherein, the first conductive material structure composed of a Ti layer, a TiNx layer formed on the Ti layer, and a TiNxCy layer (0?x?1) formed on the TiNx layer; the first conductive material structure is heated so as to transform the TiNxCy layer into a TiNxCyOz layer.

US Pat. No. 10,431,389

SOLID ELECTROLYTIC CAPACITOR FOR HIGH VOLTAGE ENVIRONMENTS

AVX Corporation, Fountai...

1. A method of forming a high voltage solid electrolytic capacitor element, the method comprising:subjecting a sintered anode pellet to a formation profile to form an anode, wherein the formation profile includes subjecting the pellet to an increasing current so that a target forming voltage is achieved in about 30 minutes or less; and
applying a solid electrolyte to the anode.

US Pat. No. 10,431,387

ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

TAIYO YUDEN CO., LTD., T...

1. An electronic component, comprising:an insulator made of a material containing resin, the insulator including a first insulating layer that has a first bonding surface perpendicular to one axial direction and a second insulating layer bonded to the first bonding surface;
an internal conductor including a plurality of first via conductive members provided in the first insulating layer and a plurality of second via conductive members provided in the second insulating layer, each of the first via conductive members including a first contact that is situated at a position offset in the one axial direction with respect to the first bonding surface and connected to the corresponding second via conductive member; and
an external electrode provided on the insulator and electrically coupled to the internal conductor,
wherein the first contact intervenes between the first via conductive member and the second via conductive member; and
wherein each of the first via conductive members is in direct contact with the first insulating layer, and each of the second conductive members is in direct contact with the second insulating layer.

US Pat. No. 10,431,386

MULTILAYER ELECTRONIC COMPONENT INCLUDING A COMPOSITE BODY AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a main body including an active region in which a plurality of internal electrodes are stacked with respective dielectric layers interposed therebetween, and upper and lower cover regions disposed above and below the active region, respectively;
external electrodes disposed on external surfaces of the main body and electrically connected to the plurality of internal electrodes; and
a composite body disposed below the lower cover region of the main body and lower portions of the external electrodes,
wherein the composite body comprises a dielectric material having a same composition as that of a dielectric material contained in the lower cover region of the main body,
wherein the composite body further comprises a resin, and
wherein a content of the resin is at least 6 wt % based on 100 wt % of the dielectric material.

US Pat. No. 10,431,382

PRINTED CIRCUIT BOARD ASSEMBLY HAVING A DAMPING LAYER

Apple Inc., Cupertino, C...

1. A printed circuit board assembly, comprising:a printed circuit board (PCB) having a first flexural modulus and a top surface;
a plurality of electronic components mounted on the top surface of the PCB;
a damping layer mounted on the top surface of the PCB, wherein the damping layer includes a continuous layer of viscoelastic material covering the plurality of electronic components, wherein the damping layer is attached to the top surface of the PCB at a plurality of locations around the plurality of electronic components, and wherein the damping layer includes a second flexural modulus lower than the first flexural modulus; and
an overmold layer mounted on the top surface of the PCB, wherein the overmold layer is a continuous layer of waterproof material covering the plurality of electronic components and the continuous layer of viscoelastic material, and wherein the overmold layer is in direct contact with the damping layer and is attached to the top surface of the PCB at a plurality of locations around the damping layer.

US Pat. No. 10,431,376

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a primary coil wound around a primary spool;
a secondary coil wound around a secondary spool provided on an outer circumference side of the primary coil;
a center core disposed on an inner circumference side of the primary coil and the secondary coil;
an outer circumferential core disposed on the outer circumference side of the primary coil and the secondary coil;
an igniter provided on a front side of the center core in a coil axis direction which is a direction of an axis about which the primary coil and the secondary coil are wound;
a case which houses the primary coil, the secondary coil, the center core, the outer circumferential core, and the igniter;
a connector unit mounted on a front end of the case and including at least a signal terminal member for transmitting a switching signal to the igniter and a grounding terminal member for grounding the igniter; and
a relay member that electrically connects the outer circumferential core and the grounding terminal member, wherein
the connector unit includes an engagement wall that is engaged with the case and faces the igniter from front of the igniter in the coil axis direction,
the signal terminal member penetrates the engagement wall and includes an inner signal terminal projecting into the case,
the grounding terminal member penetrates the engagement wall and includes an inner grounding terminal projecting into the case,
the relay member includes a base portion provided along a rear surface of the engagement wall, a standing portion standing rearward of the base portion, and a curved portion that extends from a rear end of the standing portion in a vertical direction orthogonal to the coil axis direction and is curved to protrude rearward,
the base portion is in contact with the inner grounding terminal at one end in the vertical direction,
the standing portion is provided further outward than the igniter in a horizontal direction orthogonal to both the coil axis direction and the vertical direction, and
the curved portion is elastically deformed and is in pressure-contact with a front surface of the outer circumferential core.

US Pat. No. 10,431,370

ELECTRONICS SYSTEM AND METHOD OF FORMING SAME

SCHNEIDER ELECTRIC SOLAR ...

1. A heat-generating electrical component and base assembly configured to be secured to a component wall, the assembly comprising:a base including an upper portion having a recess and a lower portion having a floating electrical connector including a threaded element disposed within a retaining body including one or more flattened inner walls which prevent rotation of the threaded element within the retaining body and a ring lug that retains the threaded element within an internal volume of the retaining body;
a heat-generating electrical component secured in the recess of the base and including an electrical lead in electrical communication with the floating electrical connector; and
a gasket circumscribing a perimeter of the lower portion.

US Pat. No. 10,431,368

COIL ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a magnetic body,
wherein the magnetic body includes a substrate, and a coil part including patterned insulating films disposed on a surface of the substrate, a first coil shaped plating layer disposed between the patterned insulating films, and a second coil shaped plating layer disposed directly on the first plating layer, and
wherein a total thickness of the first and second coil shaped plating layers on the surface of the substrate exceeds a height of the patterned insulating films on the surface of the substrate,
wherein a width of a portion of the second coil shaped plating layer arranged outside an area between the patterned insulating films is less than or equal to a width of the area between the patterned insulating films.

US Pat. No. 10,431,366

NOISE FILTER

YAZAKI CORPORATION, Mina...

1. A noise filter used for a plurality of conducting members, the noise filter comprising,a ring-shaped core made from a magnetic material, the ring-shaped core being attached to the plurality of conducting members to reduce noise of currents flowing through each of the plurality of the conducting members,
the ring-shaped core including:
a base core having a plurality of support pillar portions extending outward in radial directions; and
a plurality of divisional cores each being placed between two of the plurality of the support pillar portions adjacent to each other in the circumferential direction, and each having two end surfaces connected to end portions of the two of the plurality of the support pillar portions,
the plurality of the divisional cores being configured to allow the plurality of the conducting members to be wound on the plurality of the divisional cores,
a magnetic path being formed between the end surface of each of the plurality of the divisional cores and the end portion of each of the plurality of the support pillar portions contacting the end surface,
the ring-shaped core being configured to form a common-mode magnetic path passing through all of the plurality of the divisional cores and all of the end portions of the plurality of the support pillar portions and normal-mode magnetic paths each passing through one of the plurality of the divisional cores and the two of the plurality of the support pillar portions connected to the one of the plurality of the divisional cores, the normal-mode magnetic paths being the same in number as the conducting members.

US Pat. No. 10,431,365

ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a main body made from a metal magnetic powder and an insulating resin;
a coating film covering the surface of the main body;
a conductor disposed inside the main body;
inorganic particles adhering to the surface of the coating film, the inorganic particles having an average particle diameter of 1 nm or more and 200 nm or less; and
outer electrodes which are electrically connected to the conductor and which cover portions of the surface of the coating film while inorganic particles adhere to the portions,
wherein the coating film contains a resin and metal cations.

US Pat. No. 10,431,362

VALVE ACTUATOR WITH ANTI-CORROSION COATING

Ademco Inc., Golden Vall...

1. A method for making a valve actuator for use in actuating a gas valve, the method comprising:winding an insulated copper wire around an interconnecting segment of a non-conductive support bobbin, with a ground terminal and an interconnect terminal being secured to the non-conductive support bobbin so as not to interfere with the winding of the insulated copper wire around the non-conductive support bobbin, wherein the non-conductive support bobbin includes a first flange, a second flange, and the interconnecting segment extending between and generally orthogonal to the first flange and the second flange, and wherein an arm of a magnetic flux concentration member extends through the interconnecting segment;
electrically connecting a first end portion of the insulated copper wire to the ground terminal;
electrically connecting a second end portion of the insulated copper wire to the interconnect terminal;
bending each of the ground terminal and the interconnect terminal inward over the wound insulated copper wire; and
applying an anti-corrosion coating to at least the wound insulated copper wire, wherein the valve actuator comprises an armature that has a valve seal that is configured to align with a valve seat of the gas valve, the armature is configured to be actuated by magnetic attraction to the magnetic flux concentration member when a current is applied through the wound insulated copper wire via the interconnect terminal and the ground terminal.

US Pat. No. 10,431,359

METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET

JFE Steel Corporation, T...

1. A method for producing a grain-oriented electrical steel sheet comprising a series of steps of:heating a steel slab having a chemical composition comprising C: 0.04-0.12 mass %, Si: 1.5-5.0 mass %, Mn: 0.01-1.0 mass %, sol. Al: 0.010-0.040 mass %, N: 0.004-0.02 mass %, one or two of S and Se: 0.005-0.05 mass % in total and the remainder being Fe and inevitable impurities to not lower than 1250° C.,
hot rolling to obtain a hot rolled sheet having a thickness of not less than 1.8 mm,
subjecting the hot rolled sheet to a single cold rolling or two or more cold rollings including an intermediate annealing therebetween to obtain a cold rolled sheet having a final thickness of 0.15-0.20 mm, and
subjecting the cold rolled sheet to primary recrystallization annealing and further to final annealing,
wherein a content ratio of sol. Al to N in the steel slab (sol. Al/N) and a final thickness d (mm) satisfy the following formulas (1) and (2):
4d+1.52?sol. Al/N?4d+2.32  (1)
sol. Al/N?2.84  (2)
and the steel sheet in the heating process of the final annealing is held at a temperature of 775-875° C. for 40-200 hours and then heated in a temperature region of 875-1050° C. at a heating rate of 20-60° C./hr, and
wherein a region of 200-700° C. in the heating process of the primary recrystallization annealing is heated at a heating rate of not less than 50° C./s, while any temperature between 250-600° C. is held for 1-5 seconds.

US Pat. No. 10,431,358

RESISTOR PRODUCTION METHOD, RESISTOR, AND ELECTRONIC DEVICE

STANLEY ELECTRIC CO., LTD...

1. A method of manufacturing a resistor including (i) a substrate, and (ii) a resistive film provided on the substrate, wherein one portion or a whole of the resistive film is configured of a layer of sintered conductive nanosized particles with a particle diameter of less than 1 ?m, the method comprising:a first step of applying a solution wherein at least the conductive nanosized particles with a particle diameter of less than 1 ?m and an insulating material are dispersed, or a solution wherein at least the conductive nanosized particles covered with an insulating material layer are dispersed, in a desired form on a surface of the substrate, thereby forming a film;
a second step of irradiating one portion of the film with light in a predetermined pattern, and sintering the conductive nanosized particles with the light, thereby forming the resistive film, which is a conductive particle layer of the predetermined pattern;
a third step of measuring a resistance value of the resistive film; and
a fourth step of sintering the conductive nanosized particles by irradiating the film with light, thereby forming an additional resistive film, when the measured resistance value is greater than a range of a desired resistance value, and irradiating the resistive film with light, thereby trimming the resistive film, when the measured resistance value is smaller than the range of the desired resistance value.

US Pat. No. 10,431,354

METHODS FOR DIRECT PRODUCTION OF GRAPHENE ON DIELECTRIC SUBSTRATES, AND ASSOCIATED ARTICLES/DEVICES

Guardian Glass, LLC, Aub...

1. A method of making a coated article comprising a graphene-inclusive film on a substrate, the method comprising:disposing a metal-inclusive catalyst layer on the substrate;
exposing the substrate with the metal-inclusive catalyst layer thereon to a precursor gas and a strain-inducing gas at a temperature of no more than 900 degrees C., the strain-inducing gas inducing strain in the metal-inclusive catalyst layer; and
forming and/or allowing formation of graphene, from the precursor gas, both over and contacting the metal-inclusive catalyst layer, and between the substrate and the catalyst metal-inclusive catalyst layer, as facilitated by the strain induced in the metal-inclusive catalyst layer, in making the coated article.

US Pat. No. 10,431,352

CABLE AND METHOD FOR PRODUCING A CABLE

1. A cable comprising: at least one litz wire having twisted litz wire strands for conducting electrical current and an insulation sheath surrounding the at least one litz wire for electrical insulation of the at least one litz wire, where the cable has an interruption segment without insulation sheath disposed between two cable segments with insulation sheath, characterized in that the at least one litz wire is birdcaged in the interruption segment in order to interrupt the transport of moisture through the cable, in particular through the at least one litz wire due to capillary pressure and/or temperature-related pressure differences along the cable, and the interruption segment is not sealed so that a pressure equalization to the external environment takes place.

US Pat. No. 10,431,351

FLAT CABLE AND PRODUCTION METHOD THEREFOR

AUTONETWORKS TECHNOLOGIES...

1. A flat cable, comprising:a plurality of conductors respectively extending in an axial direction; and
an insulating sheath configured to, in a state where the conductors are lined up in a width direction orthogonal to the axial direction of the conductors, restrict the conductors from outside and collectively cover the conductors,
wherein the insulating sheath has an expander enabling bending in the width direction by permitting relative displacement between the conductors, and the expander, by expanding so as to partially separate from the conductors in at least a thickness direction orthogonal to both the width direction and the axial direction, forms an internal space permitting relative displacement such that adjacent conductors overlap in the thickness direction.

US Pat. No. 10,431,346

RADIATION SHIELDING LIQUID FILTER, AND X-RAY IMAGING DEVICE PROVIDED WITH SAME

1. An X-ray imaging device with a radiation shielding liquid filter, the radiation shielding liquid filter having a function of shielding radiation emitted from an X-ray imaging device toward an operator to protect the operator from exposure to the radiation, the liquid filter comprising:a casing filled with a liquid material, the liquid material having a composition of: 10 to 30 parts by weight of silver (Ag) in powder form; 25 to 40 parts by weight of a polymeric dispersant; 45 to 50 parts by weight of water; and 1 to 5 parts by weight of at least one element selected from copper (Cu), aluminum (Al), and mercury (Hg),
the X-ray imaging device comprising: a radiation shielding unit, the radiation shielding unit including:
an attachment member having a hole formed through a central portion of the attachment member in a vertical direction, and a step formed along a circumference of the hole, the attachment member being provided on a distal end of a tube that is an X-ray generation part of the X-ray imaging device; and
a filter holding member having a hole formed through a central portion of the filter holding member in the vertical direction, and screw-coupled to the attachment member, the filter holding member holding the liquid filter seated in the attachment member, wherein
the liquid filter is seated on the step of the attachment member.