US Pat. No. 10,396,241

DIFFUSION REVEALED BLOCKING JUNCTION

Apple Inc., Cupertino, C...

1. A light emitting diode comprising:laterally opposite sidewalls;
a first cladding layer spanning between the laterally opposite sidewalls, and doped with a first dopant type;
an active layer over the first cladding layer and spanning between the laterally opposite sidewalls;
a second cladding layer over the active layer and spanning between the laterally opposite sidewalls, and doped with a second dopant type opposite the first dopant type; and
a co-doped region embedded within the first cladding layer and spanning between the laterally opposite sidewalls, and including dopants of the first dopant type and the second dopant type;
a current injection region within the laterally opposite sidewalls; and
a current confinement region laterally surrounding the current injection region, and spanning along the laterally opposite sidewalls, wherein the current confinement region comprises a dopant concentration of the first dopant type extending through the first cladding layer; and
wherein the current confinement region dopant concentration extends through and overlaps the co-doped region to form a net second dopant type blocking junction within the first cladding layer, and the current confinement region dopant concentration surrounds a net first dopant type region of the co-doped region that is within first cladding layer and overlaps the current injection region.

US Pat. No. 10,396,239

OPTOELECTRONIC LIGHT-EMITTING DEVICE

1. Optoelectronic light-emitting device, including:at least one light-emitting diode having an emitting surface adapted to emit excitation radiation; and
a photoluminescent material that coats the emitting surface, the photoluminescent material containing photoluminescent particles adapted to convert said excitation radiation through the emitting surface at least in part into photoluminescence radiation; wherein
at least one photodiode includes a photodiode included adjacent to the at least one light-emitting diode, having a receiving surface coated by the photoluminescent material, and adapted to detect at least part of the excitation radiation or the photoluminescence radiation coming from the photoluminescent material through the receiving surface,
each of the at least one light-emitting diode and the photodiode has a mesa structure, the emitting surface and the receiving surface being substantially coplanar,
each of the at least one light-emitting diode and the photodiode includes a first semiconductor portion doped with a first conductivity type and a second semiconductor portion doped with a second conductivity type opposite the first conductivity type, the first and second semiconductor portions being respectively substantially coplanar and made from a same material,
each of the first doped semiconductor portion of the at least one light-emitting diode and the first doped semiconductor portion of the photodiode has a lateral flank including a stepped surface formed by a second part of the first doped semiconductor portion facing a first part of the first doped semiconductor portion,
a lateral electrical connection element fills a gap formed by lateral flanks of the mesa structures of the at least one light-emitting diode and the adjacent photodiode so as to be in electrical contact with the stepped surface of the first doped semiconductor portion of the at least one light-emitting diode, the lateral connection element being further electrically insulated from the second doped semiconductor portion and active zone of the at least one light-emitting diode by dielectric portions covering the lateral flanks of the second doped semiconductor portion and active zone of the at least one light-emitting diode and electrically insulated from the adjacent photodiode by a dielectric portion covering the lateral flank of the adjacent photodiode facing the at least one light-emitting diode, and
a control chip disposed at a side of the at least one light-emitting diode and of the photodiode opposite the emitting surface and the receiving surface, the control chip being connected to the lateral electrical connection element and including separate elements connected to the at least one light-emitting diode and to the adjacent photodiode.

US Pat. No. 10,396,238

PRINTABLE INORGANIC SEMICONDUCTOR STRUCTURES

X-Celeprint Limited, Cor...

1. A method of making an inorganic semiconductor structure suitable for micro-transfer printing, comprising:providing a source substrate;
forming a semiconductor layer on the source substrate, wherein the semiconductor layer has a first side and a second side opposite the first side and adjacent to the substrate;
removing a portion of the semiconductor layer to form a cantilever extension;
forming a first electrical contact on the semiconductor layer;
forming a second electrical contact on the cantilever extension;
removing a portion of the semiconductor layer surrounding each pair of first and second electrical contacts to form a trench surrounding a semiconductor element made from the semiconductor layer, the semiconductor element having a substrate side in contact with the source substrate and a handle side opposite the substrate side;
providing a sacrificial layer covering the first and second electrical contacts and covering at least a portion of the handle side of the semiconductor element and filling a portion of the trench;
providing an interlayer over the sacrificial layer, the interlayer having different chemical selectivity than the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at the base of the trench to form an anchor;
adhering the interlayer to a handle substrate;
removing the source substrate to expose the substrate side of the semiconductor element;
forming a tether bridging the exposed substrate side of the semiconductor element to the anchor; and
removing the sacrificial layer, thereby forming a printable semiconductor structure partially released from the handle substrate and physically secured to the anchor by the tether.

US Pat. No. 10,396,237

LIGHT-EMITTING DIODE SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a light-emitting diode (LED) substrate, comprising:disposing a supporting substrate supporting a plurality of LED units to be opposed to a receiving substrate so that a side of the supporting substrate facing the receiving substrate supports the plurality of LED units, wherein the receiving substrate is provided thereon with a pixel definition layer, the pixel definition layer defines a plurality of sub-pixel regions, each of the sub-pixel regions is configured to receive at least one of the LED units, a solder point and an auxiliary metal member are both provided in the sub-pixel region, the auxiliary metal member is provided at a periphery of the solder point, an interval is provided between the solder point and the auxiliary metal member in a plan view of the receiving substrate, and a melting point of the auxiliary metal member is higher than a melting point of the solder point; and
irradiating a side of the supporting substrate away from the receiving substrate with laser, stripping the LED units from the supporting substrate, and transferring the LED units onto the receiving substrate so that the at least one of the LED units in the sub-pixel region is in contact with both the solder point and the auxiliary metal member.

US Pat. No. 10,396,236

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first electrode;
a first insulating layer over the first electrode, wherein the first insulating layer comprises nitrogen;
a second insulating layer over the first insulating layer, wherein the second insulating layer comprises oxygen;
a first oxide semiconductor layer over the second insulating layer and overlapping with the first electrode, wherein the first oxide semiconductor layer comprises indium, gallium, and zinc;
a second electrode and a third electrode each over the first oxide semiconductor layer, wherein the second electrode and the third electrode each comprise copper;
a third insulating layer over the first oxide semiconductor layer, the second electrode, and the third electrode, wherein the third insulating layer comprises oxygen and is in contact with the first oxide semiconductor layer; and
a fourth insulating layer over the third insulating layer, wherein the fourth insulating layer comprises nitrogen.

US Pat. No. 10,396,235

INDENTATION APPROACHES FOR FOIL-BASED METALLIZATION OF SOLAR CELLS

SunPower Corporation, Sa...

1. A method of fabricating a solar cell, the method comprising:forming a plurality of alternating N-type and P-type semiconductor regions in or above a substrate;
locating a metal foil above the alternating N-type and P-type semiconductor regions;
forming a plurality of continuous indentations through only a portion of the metal foil, the plurality of indentations formed between and in a direction parallel with the alternating N-type and P-type semiconductor regions;
during the forming the plurality of continuous indentations, forming a continuous compression bond to bond the metal foil to the alternating N-type and P-type semiconductor regions, wherein forming the plurality of continuous indentations and the continuous compression bond is performed using raised features and a cylindrical base of a roller; and
subsequent to forming the plurality of indentations, isolating regions of remaining metal foil corresponding to the alternating N-type and P-type semiconductor regions.

US Pat. No. 10,396,234

PACKAGE STRUCTURE OF LONG-DISTANCE SENSOR AND PACKAGING METHOD OF THE SAME

Lingsen Precision Industr...

1. A package structure of a long-distance sensor, the package structure comprising:a substrate having a bearing surface;
a light-emitting chip disposed on the bearing surface;
a sensing chip disposed on the bearing surface and separated from the light-emitting chip;
two packaging gel bodies covering the light-emitting chip and the sensing chip respectively and separated from each other; and
a cap disposed on the bearing surface and the packaging gel bodies, fastened to the bearing surface and the packaging gel bodies by adhesive, and provided with a light-emitting hole located above the light-emitting chip and a light-receiving hole located above the sensing chip;
wherein a top surface of each of the packaging gel bodies has a lens portion and a shoulder portion; the cap comprises a transverse section provided with the light-emitting hole and the light-receiving hole; the transverse section of the cap is directly fastened to the shoulder portions of the top surfaces of the packaging gel bodies by the adhesive.

US Pat. No. 10,396,232

CDTE-BASED DOUBLE HETEROSTRUCTURES AND RELATED LIGHT-CONVERSION DEVICES

ARIZONA BOARD OF REGENTS ...

1. A device configured to convert light to electricity, the device comprising:an InSb substrate, and
a double-heterojunction (DH) structure carried on said InSb substrate, said DH structure including a CdTe-containing absorber layer sandwiched between first and second MgxCd1-xTe-containing barrier layers,
wherein the first and second barrier layers are configured to confine minority carriers to said absorber layer, and
wherein said DH structure is characterized by an open-circuit voltage that exceeds 1 V,
and further comprising a layer of a-Si:H on the DH structure, said a-Si:H layer configured as a p-type doped electrical contact layer, and
wherein a barrier layer from the first and second barrier layers contains a spatial doping material profile that is not uniform across the thickness of said barrier layer.

US Pat. No. 10,396,231

PHOTOVOLTAIC MATERIAL AND USE OF IT IN A PHOTOVOLTAIC DEVICE

1. A photovoltaic material comprising:a cubic nanocrystalline material with the following phases: ternary system XYS2 and a quaternary system XYS2-zVz where 2>z>0, wherein X is selected from Ag or Cu; Y is selected from Bi or Sb, and V is selected from a halogen; in the cubic lattice the cations, X and Y alternate in space and the anionic sites are occupied by sulfur atoms, or V and wherein the cationic sites are passivated from the halide atoms.

US Pat. No. 10,396,230

BACKSIDE CONTACT SOLAR CELLS WITH SEPARATED POLYSILICON DOPED REGIONS

SUNPOWER CORPORATION, Sa...

1. A solar cell comprising:a substrate having a front side and a backside;
a first dielectric layer disposed on the backside of the substrate;
a P-type doped polysilicon region; and
an N-type doped polysilicon region that is adjacent to the P-type doped polysilicon region,
wherein the P-type and N-type doped polysilicon regions are disposed on the first dielectric layer, and the P-type doped polysilicon region is physically separated from the N-type doped polysilicon region.

US Pat. No. 10,396,229

SOLAR CELL WITH INTERDIGITATED BACK CONTACTS FORMED FROM HIGH AND LOW WORK-FUNCTION-TUNED SILICIDES OF THE SAME METAL

International Business Ma...

1. A method of forming a borderless interdigitated back contact solar cell comprising:providing a lightly-doped absorber having a front surface and a back surface;
providing at least one of a first dopant type region and a first work function region disposed on said back surface;
forming trenches in said back surface;
forming sidewall spacers on trench sidewalls and only extending from the trench floors to said back surface;
providing at least one of a second dopant type region and a second work function region disposed on the trench floors between said sidewall spacers, the second regions being horizontally self-aligned to the first region by respective sidewalls spacers;
forming a dopant-segregated interface of said first dopant type on said back surface between said trenches and a dopant-segregated interface of said second dopant type on the trench floors, each said dopant-segregated interface tuning work function at the interface,
wherein the at least one of the first dopant type region and the first work function region and the at least one of the second dopant type region and the second work function region are at opposite ends of one of said sidewall spacers, and separated vertically from each other and self-aligned with respect to each other by said respective sidewalls spacers.

US Pat. No. 10,396,227

METHOD FOR FABRICATING A SOLAR MODULE OF REAR CONTACT SOLAR CELLS USING LINEAR RIBBON-TYPE CONNECTOR STRIPS AND RESPECTIVE SOLAR MODULE

REC SOLAR PTE. LTD., Sin...

1. A method for fabricating a solar module, the method comprising:providing a plurality of rear contact solar cells having emitter contacts and base contacts on a rear surface of a semiconductor substrate and soldering pad arrangements applied on emitter contacts and on base contacts,
wherein each soldering pad arrangement comprises one or more soldering pads arranged linearly and
wherein the soldering pad arrangements are arranged on the rear surface of the semiconductor substrate asymmetrically with respect to a longitudinal axis of the semiconductor substrate;
separating each of the rear contact solar cells into first and second cell portions along a line perpendicular to the longitudinal axis of the semiconductor substrate;
arranging the plurality of first and second cell portions of the rear contact solar cells alternately along a line such that the second cell portions are arranged in a 180° orientation with respect to the first cell portions and such that soldering pad arrangements of emitter contacts and of base contacts of first cell portions are aligned with soldering pad arrangements of base contacts and of emitter contacts of second cell portions, respectively;
electrically connecting the plurality of first and second cell portions of the rear contact solar cells in series by
arranging a linear ribbon-type connector strip on top of a linear soldering pad arrangement of an emitter contact of each first cell portion and on top of an aligned linear soldering pad arrangement of a base contact of a second cell portion neighboring the respective first cell portion on one side, and by
arranging a linear ribbon-type connector strip on top of a linear soldering pad arrangement of a base contact of the respective first cell portion and on top of an aligned linear soldering pad arrangement of an emitter contact of a second cell portion neighboring the respective first cell portion on an opposite side, and by
electrically connecting the connector strips to the underlying soldering pad arrangements.

US Pat. No. 10,396,225

PHOTOVOLTAIC MODULE WITH IMPROVED MOISTURE PROTECTION LAYER

BEIJING APOLLO DING RONG ...

1. A sealed photovoltaic module comprising:at least one photovoltaic cell positioned between a first sealing layer and a second sealing layer and having a light incident surface that faces toward a light source during operation, wherein one of the first and second sealing layers overlies the at least one photovoltaic cell and another of the first and second sealing layers underlies the at least one photovoltaic cell; and
a moisture resistant layer located between the first and second sealing layers and extending around a portion of a perimeter around the at least one photovoltaic cell, wherein:
the moisture resistant layer comprises:
a particle-containing region including an outer surface of the moisture resistant layer and in which moisture barrier particles are disposed, the outer surface facing away from the at least on photovoltaic cell; and
a substantially particle-free region disposed between the particle-containing region and the at least one photovoltaic cell;
the lateral width of the particle-containing region is less than the lateral width of the particle-free region;
moisture resistant layer comprises the same material in both the substantially particle-free region and in the particle-containing region; and
the moisture barrier particles have a respective maximum dimension that is less than a thickness of the moisture resistant layer between the first and the second sealing layers.

US Pat. No. 10,396,224

SOLAR CELL INTEGRATED FILM MATERIAL

Chukoh Chemical Industrie...

1. A solar cell integrated film material comprising:a film material comprising a heat-resistant fabric and a fluorocarbon resin layer formed on both sides of the heat-resistant fabric;
a solar cell comprising a weather resistant layer;
a glass fiber sheet provided between the film material and the solar cell;
a first bonding layer provided between the film material and the glass fiber sheet; and
a second bonding layer provided between the glass fiber sheet and the solar cell,
wherein the weather resistant layer is an outermost layer of the solar cell,
a surface of the other outermost layer of the solar cell directly adheres to the second bonding layer and the second bonding layer directly adheres to the glass fiber sheet, and
the first bonding layer consists of a first adhesive resin or a mixture of a first adhesive resin and silicon dioxide particles, and the second bonding layer consists of a second adhesive resin, wherein the first and second adhesive resins are the same.

US Pat. No. 10,396,223

METHOD FOR MAKING CMOS IMAGE SENSOR WITH BURIED SUPERLATTICE LAYER TO REDUCE CROSSTALK

ATOMERA INCORPORATED, Lo...

1. A method for making a CMOS image sensor comprising:forming a superlattice on a semiconductor substrate having a first conductivity type, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a plurality of laterally adjacent photodiodes on the superlattice by
forming a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate,
forming a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well having the first conductivity type, and
forming a second well overlying the retrograde well having the first conductivity type.

US Pat. No. 10,396,222

INFRARED LIGHT-RECEIVING DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. An infrared light-receiving device comprising:a substrate having a principal surface;
an optical absorption layer disposed on the principal surface of the substrate, the optical absorption layer including a type-II superlattice structure; and
an optical filter disposed on the optical absorption layer, the optical filter including an incident surface, the optical filter including a first semiconductor region disposed on the optical absorption layer, a second semiconductor region disposed on the first semiconductor region, and a third semiconductor region disposed on the second semiconductor region, each of the first, second, and third semiconductor regions including an n-type InGaAs layer, wherein
the first semiconductor region has an n-type impurity concentration of 2.0×1019 cm?3 or more,
the third semiconductor region has an n-type impurity concentration of 3.0×1018 cm?3 or less and 8.0×1017 cm?3 or more, and
the second semiconductor region has an n-type impurity concentration between the n-type impurity concentration of the first semiconductor region and the n-type impurity concentration of the third semiconductor region.

US Pat. No. 10,396,221

SOLUTION PROCESS FOR SILVER-CONTAINING CHALCOGENIDE LAYER DEPOSITION

INTERNATIONAL BUSINESS MA...

1. A solar cell, comprising:an Ag2ZnSn(S,Se)4 compound layer on a substrate.

US Pat. No. 10,396,220

DEVICE LAYER THIN-FILM TRANSFER TO THERMALLY CONDUCTIVE SUBSTRATE

International Business Ma...

1. A semiconductor structure, comprising:a thin-film device layer;
an optoelectronic device disposed in the thin-film device layer, the optoelectronic device excitable by light at an application wavelength; and
a surrogate substrate permanently attached to the thin film device layer, wherein the surrogate substrate has a volume of substrate removed therefrom to form a via, the via aligned with a location of the optoelectronic device, a cross-sectional area of the via being about equal to an active area of the optoelectronic device, and a depth of the via being substantially less than a thickness of the surrogate substrate,
wherein the light passes through the via and at least some of the surrogate substrate prior to reaching the optoelectronic device.

US Pat. No. 10,396,219

TRANSPARENT CONDUCTIVE OXIDE IN SILICON HETEROJUNCTION SOLAR CELLS

Arizona Board of Regents ...

1. A method for fabricating a solar cell, comprising:(a) preparing a silicon (Si) base layer;
(b) depositing an emitter layer on a first surface of the Si base layer, wherein the emitter layer comprises an amorphous silicon;
(c) depositing a first antireflective coating layer on the emitter layer, wherein the first antireflective coating layer comprises a transparent conducting oxide, wherein the transparent conducting oxide comprises indium tin oxide, GalnO, GaInSnO, ZnInO, and/or ZnInSnO;
(d) depositing a second antireflective coating layer on the first antireflective coating layer, wherein the second antireflective coating layer comprises a hydrogenated silicon oxide; and
(e) annealing the solar cell such that the first antireflective coating layer is hydrogenated by the second antireflective coating layer thereby increasing conductivity of the first antireflective coating layer.

US Pat. No. 10,396,218

SELF-ASSEMBLY PATTERING FOR FABRICATING THIN-FILM DEVICES

FLISOM AG, Duebendorf (C...

1. A method for fabricating patterns on a surface of a layer of a solar cell, an optoelectronic, or a photovoltaic device formed on a substrate, comprising:adding at least one alkali metal to at least one layer that is disposed on the substrate; and
processing the at least one layer to form a plurality of embossings at the surface of the at least one layer by a method comprising:
forming a plurality of alkali crystals on the surface of the at least one layer, wherein the plurality of alkali crystals comprise at least one alkali metal; and
forming the alkali crystals so that the formed alkali crystals are disposed within a portion of the at least one layer, and thereby forming at least a first line of regularly spaced embossings that are adjacent to at least a second line of regularly spaced embossings within at least one region of the at least one layer.

US Pat. No. 10,396,217

DECOUPLING FINFET CAPACITORS

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device including a fin capacitor, comprising:forming a first silicon fin and a second silicon fin, wherein the first and second silicon fins are two adjacent silicon fins extending from and above a surface of a substrate, wherein each of the two adjacent silicon fins has a first sidewall and an opposing second sidewall, the first and second sidewalls extending from the surface of the substrate;
forming a first insulating material over the substrate, and extending from an interface with the first sidewall of the first silicon fin to an interface with the first sidewall of the second silicon fin;
forming an electrical conductor over the first insulating material and between the two adjacent silicon fins wherein a top surface of the two adjacent silicon fins and a top surface of the electrical conductor are coplanar; and
depositing a second insulating material over the first insulating material and extending between the first sidewall of a first silicon fin of the two adjacent silicon fins and the electrical conductor and also extending between the first sidewall of a second silicon fin of the two adjacent silicon fins and the electrical conductor, thereby providing for a capacitance to be formed between each of the two adjacent silicon fins and the electrical conductor.

US Pat. No. 10,396,216

DEVICE INCLUDING A SIDEWALL SCHOTTKY INTERFACE

Semiconductor Components ...

1. A device, comprising:a first trench disposed in a semiconductor region;
a second trench disposed in the semiconductor region;
a recess disposed in the semiconductor region between the first trench and the second trench, the recess having a sidewall and a bottom surface; and
a Schottky interface formed by a first portion of the semiconductor region disposed along a sidewall of the recess, the first portion of the semiconductor region disposed along the sidewall having a dopant concentration less than a doping concentration of a second portion of the semiconductor region disposed between the first portion and the first trench in a direction perpendicular to the sidewall, the semiconductor region having a third portion disposed along the bottom surface of the recess and defining a PN junction with the first portion of the semiconductor region.

US Pat. No. 10,396,215

TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL

United Silicon Carbide, I...

1. A trench JFET, comprising:a) a substrate comprising a backside drain region and a topside drift region, the backside drain region and the topside drift region being of a first doping type, wherein the first doping type is n-type;
b) mesas, the mesas extending from the topside drift region, wherein the mesas are separated by trenches cut into the topside drift region; and
c) in each mesa, a source region, a gate region, a vertical channel region, and a first mesa core region and a second mesa core region;
d) wherein the source region is of the first doping type and is located at the tops of the mesa;
e) wherein the gate region is of a second doping type and is located on the surfaces of the trenches, wherein the second doping type is p-type, and wherein the gate region abuts the source region;
f) wherein the first and second mesa core regions are of the first doping type, wherein the first mesa core region is located beneath source region and above the second mesa core, with the first mesa core region abutting the source region and the second mesa core region, and wherein the doping concentration at the center of the first mesa core region is at least ten times lower than that of the topside drift region;
g) wherein the vertical channel region is of the first doping type, where in the vertical channel region extends vertically substantially the height of the mesas and abuts the source region, and wherein the vertical channel region extends laterally to abut a portion of the gate region on the vertical wall of the trench and to abut a portion of the first mesa core region and a portion of the second mesa core region; and
h) wherein the peak doping concentration of the vertical channel region is at least ten times higher than the doping level of the center of the first mesa core region.

US Pat. No. 10,396,214

METHOD OF FABRICATING ELECTROSTATICALLY ENHANCED FINS AND STACKED NANOWIRE FIELD EFFECT TRANSISTORS

International Business Ma...

1. A semiconductor structure comprising:a vertical stack of semiconductor nanowires located atop a surface of a base layer, wherein the base layer has a concave upper surface located adjacent the vertical stack of semiconductor nanowires; and
a semiconductor material protruding portion located on a sidewall surface of each of the semiconductor nanowires.

US Pat. No. 10,396,213

ACTIVE DEVICE ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

Chunghwa Picture Tubes, L...

1. An active device array substrate, comprising:a substrate;
a first active device, disposed on the substrate and comprising a first gate electrode, a first semiconductor block, a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode contact the first semiconductor block and are separate from each other;
a second active device, disposed on the substrate and comprising a second gate electrode, a second semiconductor block, a second source electrode and a second drain electrode, wherein the second source electrode and the second drain electrode contact the second semiconductor block and are separate from each other, and a film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode;
a gate insulation layer, disposed on the substrate, wherein the first gate electrode and the second gate electrode are located between the gate insulation layer and the substrate, and the gate insulation layer is located between the first gate electrode and the first semiconductor block and is also located between the second gate electrode and the second semiconductor block; and
an insulation barrier layer, disposed on the gate insulation layer, and covering the first semiconductor block, and the insulation barrier layer having a first through hole reaching a surface of the first semiconductor block, wherein the insulation barrier layer is disposed between the first source electrode and the first drain electrode and the insulation barrier layer reveals the second semiconductor block, the second source electrode and the second drain electrode, and wherein one of the first source electrode and the first drain electrode contacts the first semiconductor block through the first through hole and the other one is located between the gate insulation layer and the insulation barrier layer.

US Pat. No. 10,396,212

THIN FILM TRANSISTOR ARRAY PANEL

Samsung Display Co., Ltd....

1. A thin film transistor array panel, comprising:a substrate;
a metal pattern disposed on the substrate;
a buffer layer disposed on the metal pattern; and
a semiconductor layer disposed on the buffer layer and comprising a source region, a channel region, and a drain region,
a first electrode disposed on the semiconductor layer,
wherein the metal pattern overlaps at least one of the source region and the drain region, and
wherein the metal pattern does not overlap the channel region and the first electrode.

US Pat. No. 10,396,211

FUNCTIONAL METAL OXIDE BASED MICROELECTRONIC DEVICES

Intel Corporation, Santa...

1. A microelectronic apparatus, comprising:a microelectronic substrate;
a buffer transition layer on the microelectronic substrate;
a functional metal oxide channel on the buffer transition layer; and
an electrode on the functional metal oxide channel;
wherein the microelectronic substrate includes a microelectronic transistor source region formed therein, and wherein the buffer transition layer contacts the microelectronic transistor source region.

US Pat. No. 10,396,210

SEMICONDUCTOR DEVICE WITH STACKED METAL OXIDE AND OXIDE SEMICONDUCTOR LAYERS AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductor over a substrate;
a first insulator over the first conductor;
a first metal oxide over the first insulator to overlap with at least part of the first conductor;
an oxide semiconductor in contact with at least part of a top surface of the first metal oxide;
a second metal oxide in contact with at least part of a top surface of the oxide semiconductor;
a second conductor in contact with at least part of the second metal oxide; and
a third conductor in contact with at least part of the second metal oxide and separated from the second conductor,
wherein an entire portion of the oxide semiconductor overlaps with the first conductor in a channel length direction,
wherein the first metal oxide comprises In, Zn, and M,
wherein a content of In is lower than a content of M in the first metal oxide,
wherein the content of In is K times lower than a content of Zn in the first metal oxide,
wherein the oxide semiconductor comprises In and M,
wherein a content of In is higher than a content of M in the oxide semiconductor,
wherein the second metal oxide comprises In, Zn, and M,
wherein M represents any one of Ti, Ga, Y, Zr, La, Ce, Nd, Sn, and Hf, and
wherein K is greater than or equal to 4 and less than or equal to 7.

US Pat. No. 10,396,209

THIN FILM TRANSISTOR COMPRISING LIGHT SHIELDING LAYERS, ARRAY SUBSTRATE AND MANUFACTURING PROCESSES OF THEM

BOE Technology Group Co.,...

1. A thin film transistor, comprising:a gate electrode, an insulating layer, an active layer, and a source/drain electrode layer,
wherein the thin film transistor further comprises a light shielding layer which is configured to block light from entering the active layer via the insulating layer, the light shielding layer and the gate electrode are arranged in a same layer and electrically unconnected with each other, and the light shielding layer is provided on at least two sides of the active layer, wherein the light shielding layer comprises at least one of a direct irradiation light shielding layer and a reflection light shielding layer;
the direct irradiation light shielding layer is configured to prevent the light from entering the active layer via the insulating layer; and the reflection light shielding layer is configured to prevent light from being irradiated to the source/drain electrode layer via the insulating layer and then being reflected to the active layer by a surface of the source/drain electrode layer.

US Pat. No. 10,396,208

VERTICAL TRANSISTORS WITH IMPROVED TOP SOURCE/DRAIN JUNCTIONS

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a top source/drain junction of a vertical transistor, the method comprising:forming a structure comprising a bottom source/drain, a fin channel comprising a semiconductor material and extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate comprising a dielectric layer, a gate metal, a top spacer arranged on a top surface of the gate, and a bottom spacer arranged on a bottom surface of the gate;
etching to form a recess in a top surface of the semiconductor material of the fin channel, the recess having sidewalls that contact a top surface of the top spacer and form oblique angles with respect to sidewalls of the fin channel and sidewalls of the top spacer, and the semiconductor material of the fin channel covering sidewalls of the top spacer;
forming a top source/drain on the fin channel and within the recess;
doping the top source/drain with a dopant; and
annealing to diffuse the dopants from the top source/drain into the fin channel.

US Pat. No. 10,396,207

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

SAKAI DISPLAY PRODUCTS CO...

1. A method of manufacturing a thin-film transistor substrate comprising:annealing a semiconductor film being formed on a gate insulation film covering a gate electrode with a laser beam by using a mask, the gate electrode being formed within a thin-film transistor substrate region on a substrate;
forming a first alignment mark outside the thin-film transistor substrate region on the substrate, by irradiating the substrate through the mask with the laser beam;
patterning the semiconductor film by photolithography and etching;
forming a conductive film on the semiconductor film;
positioning a photomask on the basis of the first alignment mark; and
forming a source electrode and a drain electrode by patterning the conductive film through the photomask;
wherein the first alignment mark is formed while annealing the semiconductor film, and
one or more first openings to be used for annealing the semiconductor film and one or more second openings to be used for forming the first alignment mark are provided in the mask.

US Pat. No. 10,396,206

GATE CUT METHOD

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor structure, comprising:forming a sacrificial gate over a plurality of semiconductor fins;
forming an interlayer dielectric laterally adjacent to the sacrificial gate;
forming a hard mask over the sacrificial gate and over the interlayer dielectric;
etching an opening in the hard mark to expose a top surface of the sacrificial gate and form a recessed region within the interlayer dielectric;
forming an oxide layer on at least the top surface of the sacrificial gate, a top surface of the interlayer dielectric within the recessed region, and a sidewall surface of the hard mask within the opening;
removing a portion of the oxide layer to expose the top surface of the sacrificial gate, wherein a remaining portion of the oxide layer is positioned over the top surface of the interlayer dielectric; and
etching the sacrificial gate to form a gate cut opening that extends through the sacrificial gate, wherein the gate cut opening is located between an adjacent pair of the fins in the plurality of semiconductor fins.

US Pat. No. 10,396,205

INTEGRATED CIRCUIT DEVICE

Samsung Electronics Co., ...

1. An integrated circuit device, comprising:a fin-type active region protruding from a substrate and extending longitudinally in a first horizontal direction;
a base burying insulating film including a vertical extension and a horizontal extension on the substrate, the vertical extension covering a lower side wall of the fin-type active region and having a first top surface at a first level, and the horizontal extension being integrally connected to the vertical extension and covering a top surface of the substrate;
an isolation pattern covering a side wall of the vertical extension on the horizontal extension and having a second top surface at a second level, the second level being higher than the first level; and
a gate line having an upper gate and a lower gate, the upper gate extending in a second horizontal direction crossing the first horizontal direction to cover an upper portion of a channel section of the fin-type active region and the second top surface of the isolation pattern, and the lower gate protruding from the upper gate toward the substrate and filling a space on the first top surface between a lower portion of the channel section and an upper side wall of the isolation pattern.

US Pat. No. 10,396,203

PRE-SCULPTING OF SI FIN ELEMENTS PRIOR TO CLADDING FOR TRANSISTOR CHANNEL APPLICATIONS

Intel Corporation, Santa...

1. A transistor, comprising:a fin continuous with and extending from a substrate, the fin comprising a single crystal material, and the fin having a narrow upper fin portion on a wide lower fin portion, wherein the wide lower fin portion has a width of between 5 nm and 15 nm greater than a width of the narrow upper fin portion;
a trench oxide material above the substrate, the trench oxide material laterally adjacent the wide lower fin portion, wherein the narrow upper fin portion is exposed above the trench oxide material;
a gate dielectric directly on a top and sides of the narrow upper fin portion; and
a gate electrode on the gate dielectric along the top and sides of the narrow upper fin portion.

US Pat. No. 10,396,202

METHOD AND STRUCTURE FOR INCORPORATING STRAIN IN NANOSHEET DEVICES

International Business Ma...

1. A semiconductor structure, comprising:a dielectric nanosheet base portion located on a semiconductor substrate;
a plurality of stacked and suspended semiconductor nanosheets located entirely above the dielectric nanosheet base portion, each semiconductor nanosheet of the plurality of stacked and suspended semiconductor nanosheets having a pair of end sidewalls comprising a V-shaped undercut surface;
a functional gate structure entirely surrounding, and present above and beneath, a portion of each semiconductor nanosheet of the plurality of stacked and suspended semiconductor nanosheets, wherein a bottommost surface of the functional gate structure is located beneath a bottommost semiconductor nanosheet of the plurality of stacked and suspended semiconductor nanosheets and directly contacts a topmost surface of the dielectric nanosheet base portion;
a first source/drain (S/D) semiconductor material structure located on a first side of the functional gate structure, wherein the first S/D semiconductor material structure is in direct contact with the V-shaped undercut surface of a first end sidewall of the pair of end sidewalls of each semiconductor nanosheet of the plurality of stacked and suspended semiconductor nanosheets; and
a second S/D semiconductor material structure located on a second side of the functional gate structure opposite the first side, wherein the second S/D semiconductor material structure is in direct contact with the V-shaped undercut surface of a second end sidewall of the pair of end sidewalls of each semiconductor nanosheet of the plurality of stacked and suspended semiconductor nanosheets.

US Pat. No. 10,396,201

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES

Intel Corporation, Santa...

1. A method of forming a structure comprising:forming openings in source/drain regions of a device disposed on a substrate, the openings beneath dielectric spacers adjacent to a gate electrode, wherein the gate electrode is on a gate dielectric, and wherein the openings further extend beneath the gate dielectric;
forming a dislocation nucleation material in the source/drain openings, wherein the dislocation nucleation material is selectively grown using epitaxial growth, wherein the dislocation nucleation material comprises a lattice constant that is mismatched with a substrate lattice constant, and wherein a plurality of dislocations form in the dislocation nucleation material, and wherein the dislocation nucleation material is in contact with a bottom surface of the dielectric spacers and with a bottom surface of the gate dielectric; and
forming a source/drain material on the dislocation nucleation material, wherein a plurality of source/drain dislocations are formed in the source/drain material.

US Pat. No. 10,396,200

METHOD AND STRUCTURE OF IMPROVING CONTACT RESISTANCE FOR PASSIVE AND LONG CHANNEL DEVICES

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:removing a first dummy gate of a plurality dummy gates to form a contact trench, the contact trench being arranged between an active gate and a second dummy gate of the plurality of dummy gates, the contact trench extending from a source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned between the second dummy gate and the contact trench and another portion of the source/drain positioned between the active gate and the contact trench, and the source/drain contacting a bottom sidewall of the contact trench; and
depositing a conductive material in contact trench to form a source/drain contact between the active gate and the second dummy gate.

US Pat. No. 10,396,199

ELECTROSTATIC DISCHARGE DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A device, comprising:a substrate having a top surface;
an n-type region extending from the top surface;
a p-type region within the n-type region and extending from the top surface;
a first n+ region within the p-type region and separated from the n-type region by the p-type region;
a second n+ region within the p-type region and separated from the n-type region and the first n+ region by the p-type region; and
an impedance above the top surface, and coupled between the n-type region and the second n+ region.

US Pat. No. 10,396,198

VERTICAL TRANSISTOR PASS GATE DEVICE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first source/drain region having a first epitaxial material with a diamond shaped geometry is present at a first end of a fin structure, the fin structure being present on a substrate;
a second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure; and
a gate structure present on a fin channel region portion of the fin structure between the first source/drain region and the second source/drain region, wherein the first source/drain region, the fin channel region, and second source/drain region are arranged perpendicular to the plane of an upper surface of the substrate.

US Pat. No. 10,396,197

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A semiconductor device comprising:a planar semiconductor layer on a substrate;
a pillar-shaped semiconductor layer on the planar semiconductor layer;
a gate insulating film surrounding the pillar-shaped semiconductor layer;
a first metal surrounding the gate insulating film,
the first metal in contact with an upper portion of the planar semiconductor layer;
an element isolation insulating film surrounding the planar semiconductor layer,
wherein the first metal extends over the element isolation insulating film;
a gate above the first metal and surrounding the gate insulating film, where the gate is electrically insulated from the first metal; and
a second metal above the gate so as to surround the gate insulating film, where the second metal is electrically insulated from the gate, and has an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.

US Pat. No. 10,396,195

SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A semiconductor device, comprising:an n? type layer disposed at a first surface of a substrate;
a trench, an n type region, and a p+ type region disposed on the n? type layer;
a p type region disposed on the n type region;
an n+ type region disposed on the p type region;
a gate insulating layer disposed in the trench;
a gate electrode disposed on the gate insulating layer;
an insulating layer disposed on the gate electrode;
a source electrode disposed on the insulating layer, the n+ type region, and the p+ type region; and
a drain electrode disposed at a second surface of the substrate,
wherein the n type region includes a first portion in contact with the side surface of the trench and extending parallel to an upper surface of the substrate and a second portion in contact with the first portion, separated from the side surface of the trench, and extending in a direction vertical to the upper surface of the substrate.

US Pat. No. 10,396,194

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
a first semiconductor layer provided on a front surface of the semiconductor substrate, an impurity concentration of a first sub-layer of the first semiconductor layer being lower than an impurity concentration of the semiconductor substrate;
a first semiconductor region of a second conductivity type selectively provided in the first semiconductor layer, an impurity concentration of the first semiconductor region being higher than the impurity concentration of the first sub-layer of the first semiconductor layer;
a second semiconductor region of the second conductivity type selectively provided in a first side of the first semiconductor layer opposite a second side of the first semiconductor layer, the second side facing the semiconductor substrate, the first sub-layer located on the second side of the first semiconductor layer, an impurity concentration of the second semiconductor region being lower than the impurity concentration of the first semiconductor region;
a third semiconductor region of the first conductivity type selectively provided in the first semiconductor layer, an impurity concentration of the third semiconductor region being higher than the impurity concentration of the first sub-layer of the first semiconductor layer;
a trench penetrating the third semiconductor region and the second semiconductor region, and reaching the first semiconductor region;
a gate insulating film covering sides of the trench;
a gate electrode provided in the trench, via the gate insulating film;
a first electrode in contact with the first semiconductor region and the third semiconductor region; and
a Schottky electrode in contact with a second sub-layer of the first semiconductor layer having an impurity concentration higher than the first sub-layer of the first semiconductor layer, wherein
a first sidewall of the trench on a side where the Schottky electrode is located is in contact with the second sub-layer of the first semiconductor layer,
a second sidewall of the trench on a side where the first electrode is located is in contact with the second semiconductor region and the third semiconductor region,
at least a part of a region of the Schottky electrode faces the first semiconductor region in a depth direction, and
the trench faces the first semiconductor region in the depth direction.

US Pat. No. 10,396,193

III-NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR

EPISTAR CORPORATION, Hsi...

1. A III-nitride high electron mobility transistor (HEMT), comprising:a substrate;
a semiconductor epitaxial stack, formed on the substrate, comprising:
a buffer structure;
a channel layer, formed on the buffer structure; and
a barrier layer, formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer; and
a first electrode, a second electrode and a third electrode, respectively formed on the barrier layer, wherein the second electrode is located between the first electrode and the third electrode,
wherein the semiconductor epitaxial stack comprises a sheet resistance greater than 500 ?/sq,
wherein there is a first minimum space between the first electrode and the second electrode, a second minimum space between the second electrode and the third electrode, and the first minimum space and the sum of the first minimum space and the second minimum space comprises a ratio greater than or equal to 0.77 and less than 1,
wherein the second electrode comprises a length greater than or equal to 9 ?m.

US Pat. No. 10,396,192

HEMT TRANSISTORS WITH IMPROVED ELECTRON MOBILITY

STMICROELECTRONICS S.R.L....

1. A transistor, comprising:a semiconductor body;
a first dielectric layer on the semiconductor body;
an opening extending through the first dielectric layer, the opening having sidewalls and a bottom surface;
an interface layer on the sidewalls of the opening;
a second dielectric layer formed on the interface layer;
a gate electrode positioned at least partially in the opening and on the second dielectric layer;
a source contact having a first portion and a second portion, the first portion of the source contact extending through the first dielectric layer and into the semiconductor body in a first direction, the second portion of the source contact extending on the second dielectric layer in a second direction that is transverse to the first direction; and
a drain contact having a first portion and a second portion, the first portion of the drain contact extending through the first dielectric layer and into the semiconductor body in the first direction, the second portion of the drain contact extending on the second dielectric layer in the second direction.

US Pat. No. 10,396,191

SEMICONDUCTOR DEVICE

Epistar Corporation, Hsi...

1. A semiconductor device, comprising:a channel layer formed on a substrate;
a top barrier layer formed on the channel layer, wherein a first heterojunction is formed between the channel layer and the top barrier layer so that a first two-dimensional electron gas is generated in the channel layer;
a buffer structure formed between the substrate and the channel layer;
a back barrier layer formed between the buffer structure and the channel layer, wherein a second heterojunction is formed between the buffer structure and the back barrier layer so that a second two-dimensional electron gas is generated in the buffer structure; and
a source electrode, a drain electrode, and a gate electrode formed on the top barrier layer, respectively;
wherein a sheet carrier density of the second two-dimensional electron gas is less than 8E+10 cm?2.

US Pat. No. 10,396,190

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a first nitride semiconductor layer;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a mesa part formed over the third nitride semiconductor layer and including a fourth nitride semiconductor layer;
a source electrode formed over the third nitride semiconductor layer and on a first side of the mesa part;
a drain electrode formed over the third nitride semiconductor layer and on a second side of the mesa part;
a gate electrode formed above the mesa part; and
a side part formed on at least one side of the mesa part and including the fourth nitride semiconductor layer,
wherein the gate electrode is formed above a first a portion of the side part,
wherein a second portion of the side part extends to the outside of the gate electrode, and
wherein generation of two-dimensional electron gas between the second nitride semiconductor layer and the third nitride semiconductor layer is suppressed below the mesa part while being unsuppressed below the side part.

US Pat. No. 10,396,189

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and
a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein
the second top surface electrode has:
a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and
a second connecting portion that connects the first region and the second region above the first connecting portion.

US Pat. No. 10,396,188

HETEROJUNCTION BIPOLAR TRANSISTORS AND METHOD OF FABRICATING THE SAME

QUALCOMM Incorporated, S...

1. A semiconductor device, comprising:a first heterojunction bipolar transistor (HBT) on a die, wherein the first HBT comprises a first emitter, a first collector, and a first base between the first emitter and the first collector and wherein a width of the first emitter is less than 100 nanometers (nm); and
a second HBT on the die, wherein the second HBT comprises a second emitter, a second collector, and a second base between the second emitter and the second collector and wherein a width of the second emitter is equal to or greater than 0.1 micron (?m).

US Pat. No. 10,396,187

SEMICONDUCTOR DEVICE

Japan Display Inc., Toky...

1. A semiconductor device comprising:a first oxide insulating layer;
a barrier layer above the first oxide insulating layer, the barrier layer including an opening;
a second oxide insulating layer above the first oxide insulating layer at a position overlapping the opening;
an oxide semiconductor layer facing the first oxide insulating layer interposed by the second oxide insulating layer at a position overlapping the opening;
a gate electrode facing the oxide semiconductor layer at side opposite to the first oxide insulating layer with respect to the oxide semiconductor layer; and
a gate insulating layer between the oxide semiconductor layer and the gate electrode;
wherein
a contained amount of oxygen in the first oxide insulating layer is larger than a contained amount of oxygen in the second oxide insulating layer.

US Pat. No. 10,396,186

THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a thin film transistor, comprising:forming an active layer on a substrate;
forming an insulating layer on the active layer and an exposed surface of the substrate;
forming a first conductive layer on the insulating layer;
patterning the first conductive layer and the insulating layer to form a first stack on the active layer, wherein the first stack comprises a first portion of the first conductive layer and a first portion of the insulating layer, the first stack acts as a gate stack of the thin film transistor, and the active layer comprises a channel region below the gate stack and a source region and a drain region at two sides of the channel region; and
performing plasma treatment on the first conductive layer, the source region, and the drain region, to improve the conductivity of the first conductive layer, the source region, and the drain region.

US Pat. No. 10,396,185

INTEGRATION OF STRAINED SILICON GERMANIUM PFET DEVICE AND SILICON NFET DEVICE FOR FINFET STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method of forming a finFET transistor device, the method comprising:forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate;
masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer;
performing an implant process on the exposed second region of the cSiGe layer, wherein the implant process amorphizes a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer;
performing an annealing process so as to recrystallize the rSiGe layer;
recessing the recrystallized rSiGe layer;
epitaxially growing a tensile strained silicon layer on the rSiGe layer; and
patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

US Pat. No. 10,396,184

INTEGRATED CIRCUIT DEVICE FINS

Taiwan Semiconductor Manu...

1. A method comprising:receiving a substrate that includes:
a plurality of fins extending above a remainder of the substrate;
a first region that includes a first fence region that contains a first subset of the plurality of fins; and
a second region that includes a second fence region that contains a second subset of the plurality of fins;
wherein the first region has a first performance characteristic; and
wherein the second region has a second performance characteristic that is different from the first performance characteristic;
based on the first performance characteristic, recessing the first subset of the plurality of fins to a first height; and
based on the second performance characteristic, recessing the second subset of the plurality of fins to a second height that is less than the first height, and
wherein the first region of the substrate further includes a first guard ring region that is free of fins, and wherein each fin of the first subset extends above a top surface of the substrate in the first guard ring region.

US Pat. No. 10,396,183

PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET

INTERNATIONAL BUSINESS MA...

1. A method comprising:creating, in a fin-Field Effect Transistor (finFET), a recess at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate;
filling the recess at least partially with a first conductive material;
insulating the first conductive material from the gate;
replacing the fin with a replacement structure;
connecting electrically, using a second conductive material, the replacement structure to the first conductive material, wherein the first conductive material and the second conductive material are identical;
insulating the second conductive material from a first surface of the finFET;
fabricating a first electrical contact structure on the first surface; and
fabricating a second electrical contact structure on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

US Pat. No. 10,396,182

SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING

International Business Ma...

1. A method of forming a silicon germanium-on-insulator (SGOI) material, said method comprising:forming a structure comprising, from bottom to top, a germanium-on-insulator substrate and an amorphous silicon layer, wherein the germanium-on-insulator substrate comprises a germanium layer located directly on a surface of an insulator layer, and wherein the amorphous silicon layer is located directly on a topmost surface of the germanium layer;
forming an opening extending through said amorphous silicon layer and said germanium layer of said germanium-on-insulator substrate;
forming a dielectric structure within said opening, wherein said dielectric structure has a topmost surface coplanar with a topmost surface of said amorphous silicon layer, and a sidewall surface that contacts a sidewall surface of the amorphous silicon layer, and a sidewall surface of the germanium layer; and
converting said structure into a silicon germanium-on-insulator material by annealing said structure containing said dielectric structure within an entirely inert ambient annealing environment, wherein during said annealing silicon atoms from said amorphous silicon layer diffuse into the germanium layer and intermix with germanium atoms in said germanium layer of said germanium-on-insulator substrate to form a silicon germanium layer directly on said surface of said insulator layer.

US Pat. No. 10,396,181

FORMING STACKED NANOWIRE SEMICONDUCTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A method for forming a nanowire semiconductor device, the method comprising:forming a nanowire stack comprising a first nanowire and a second nanowire arranged on the first nanowire;
forming a sacrificial gate over the nanowire stack;
forming a sacrificial spacer adjacent to the sacrificial gate;
removing one or more portions of the first nanowire to form a first cavity;
removing the sacrificial spacer;
depositing a layer of spacer material adjacent to the sacrificial gate and in the first cavity;
removing a portion of the layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;
removing one or more portions of the second nanowire to form a second cavity; and
epitaxially growing a source/drain region in the second cavity from the one or more portions of the second nanowire.

US Pat. No. 10,396,180

METHOD FOR FORMING APPARATUS COMPRISING TWO DIMENSIONAL MATERIAL

EMBERION OY, Espoo (FI)

1. A method for forming a field effect transistor, said method comprising:providing a release layer with a smooth surface on a carrier substrate;
depositing source, gate and drain electrodes on the release layer;
depositing a mouldable polymer overlaying the source, gate and drain electrodes on the release layer, so that the source, gate and drain electrodes and the mouldable polymer form a planar surface against the smooth surface of the release layer;
removing the carrier substrate and the release layer;
providing a dielectric on the planar surface overlying the gate electrode and at least part of the source and drain electrodes;
depositing a layer of two dimensional material on the dielectric;
providing a first contact between the source electrode and the two dimensional material so that the contact provides a direct current path between the source electrode and the two dimensional material; and
providing a second contact between the drain electrode and the two dimensional material so that the contact provides a direct current path between the drain electrode and the two dimensional material.

US Pat. No. 10,396,179

FORMING VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS WITH UNIFORM BOTTOM SPACER THICKNESS

INTERNATIONAL BUSINESS MA...

1. A vertical transport field effect transistor with uniform bottom spacer thickness, comprising:a vertical fin on a substrate;
a protective liner segment on the substrate adjacent to the vertical fin;
a conversion segment on the protective liner segment, wherein the conversion segment includes silicon oxide (SiO); and
a gate dielectric layer on the conversion segment, wherein the gate dielectric layer follows the shape and varying thickness of the conversion segment.

US Pat. No. 10,396,178

METHOD OF FORMING IMPROVED VERTICAL FET PROCESS WITH CONTROLLED GATE LENGTH AND SELF-ALIGNED JUNCTIONS

INTERNATIONAL BUSINESS MA...

1. A method of forming a vertical field-effect transistor (FET), the method comprising:depositing a highly doped bottom source-drain layer over a substrate of a first type;
depositing a first heterostructure layer over the highly doped bottom source-drain layer;
depositing a channel layer over the first heterostructure layer;
depositing a second heterostructure layer over the channel layer;
forming a first fin having a hard mask thereon, wherein the hard mask is disposed on the second heterostructure layer;
recessing the first and the second heterostructure layers such that they are narrower than the first fin and the hard mask;
filling gaps formed in the recessed first and second heterostructure layers with a dielectric inner spacer;
laterally trimming the channel layer to a narrower width;
depositing a dielectric bottom outer spacer over the highly doped bottom source-drain layer;
depositing a high-k dielectric layer on the dielectric bottom outer spacer, the first fin, and the hard mask; and
depositing a metal gate layer on top of the high-k dielectric layer.

US Pat. No. 10,396,177

PREVENTION OF EXTENSION NARROWING IN NANOSHEET FIELD EFFECT TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, comprising:forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material;
recessing the first layers relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers;
forming first spacers in recesses formed by recessing the first layers;
forming second spacers in recesses formed by recessing the first layers;
etching the first spacers to expose sidewalls of the second spacer;
forming source/drain extensions in contact with exposed ends of the second layers; and
etching away the first layers of sacrificial material after forming the source/drain extensions to expose the second layers of channel material.

US Pat. No. 10,396,176

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

Intel Corporation, Santa...

1. A method for fabricating a transistor comprising:forming a blocking material on a semiconductor fin;
disposing a dummy gate on at least a first portion of the blocking material, wherein the dummy gate and the blocking material comprise different surface chemistries;
selectively forming a conformal layer on an entirety of the dummy gate, wherein the conformal layer has an etch selectivity with respect to the blocking material and wherein the conformal layer is not formed on at least a second portion of the blocking material;
removing exposed portions of the blocking material by an etch wherein the conformal layer protects the dummy gate during the etch;
forming an interlayer dielectric material adjacent to a sidewall of the conformal layer and exposing the dummy gate;
removing the dummy gate and a portion of the blocking material to expose a third portion of the semiconductor fin;
disposing a gate dielectric on the third portion of the semiconductor fin and a gate electrode on the gate dielectric; and
forming, prior to selectively forming the conformal layer, a blocking self-assembled monolayer on at least a portion of the blocking material, wherein said removing the dummy gate and the portion of the blocking material further comprises removing a portion of the blocking self-assembled monolayer.

US Pat. No. 10,396,175

NANOGAPS ON ATOMICALLY THIN MATERIALS AS NON-VOLATILE READ/WRITABLE MEMORY DEVICES

UNIVERSITY OF KENTUCKY RE...

1. A non-volatile memory element, comprising an atomically-thin layer on top of a gate layer which is on top of a substrate, and a metallic layer with a bowtie geometry dispersed on top of the atomically-thin layer, wherein an electromigrated break junction in the metallic layer at the bowtie geometry provides well defined metallic interfaces and a clean nanogap channel of a width of about 0.1 nm to 10 nm entirely across the metallic layer that exposes the top of the atomically thin layer, such that the electromigrated break junction divides the metallic layer into a source electrode and a drain electrode that are separated by the clean nanogap, wherein the exposed atomically-thin layer functions as an ultra-short ballistic channel between the source and drain electrodes through the atomically thin layer over the gate layer and the substrate, and further wherein the substrate comprises an insulating material that supports charge trapping or a floating gate electrode.

US Pat. No. 10,396,174

STI-DIODE STRUCTURE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a fin-type diode, comprising:providing a substrate structure, the substrate structure comprising:
a substrate;
a first set of fins on the substrate;
a second set of fins on the substrate;
an isolation region disposed between the first set of fins and the second set of fins and having an upper surface lower than an upper surface of the first set of fins and an upper surface of the second set of fins;
a well region partially in the substrate and overlapping the first set of fins and the second set of fins, or the well region entirely in the substrate and overlapping the first set of fins and the second set of fins;
forming a dielectric layer on a surface of first set of fins and on a surface of the second set of fins above the upper surface of the isolation region;
forming a dummy gate structure covering a portion of the dielectric layer on a distal end of the second set of fins and the upper surface or a portion of the upper surface of the isolation region;
performing a first dopant implantation on the first set of fins to form a first doped region;
performing a second dopant implantation on the second set of fins and a portion of the well region below the second set of fins using the dummy gate structure as a mask to form a second doped region;
wherein the first doped region and the second doped region have different conductivity types;
wherein the first doped region and the well region have a same conductivity type.

US Pat. No. 10,396,173

TRANSIENT DEVICES DESIGNED TO UNDERGO PROGRAMMABLE TRANSFORMATIONS

The Board of Trustees of ...

1. A passive transient electronic device comprising:a substrate; and
one or more inorganic components supported by said substrate; wherein said one or more inorganic components independently comprise a selectively transformable material, wherein said one or more inorganic components have a preselected transience profile in response to an external or internal stimulus;
wherein at least partial transformation of said one or more inorganic components provides a programmable transformation of the passive transient electronic device in response to said external or internal stimulus and at a pre-selected time or at a pre-selected rate, wherein said programmable transformation provides a change in function of the passive transient electronic device from a first condition to a second condition;
wherein change in function transforms said one or more inorganic components from:
(i) a NOR gate to a NAND gate;
(ii) an inverter to an isolated transistor;
(iii) a resistor to a diode;
(iv)a NAND gate to an inverter;
(v) a NOR gate to an isolated transistor; or
(vi) a NAND gate to an isolated transistor.

US Pat. No. 10,396,172

TRANSISTOR WITH AIR SPACER AND SELF-ALIGNED CONTACT

INTERNATIONAL BUSINESS MA...

1. A semiconductor transistor, comprising:a source region and a drain region formed within a substrate;
a gate formed above the substrate;
a source contact formed above the source region and a drain contact formed above the drain region;
air spacers formed within a dielectric between the gate and each of the source contact and the drain contact;
metal caps formed on the source contact and the drain contact; and
a gate cap between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact, wherein the gate cap contacts the dielectric on a first side of the gate cap and the gate cap contacts the portion of the bottom surface of the higher-level contacts on a second side of the gate cap that is opposite the first side of the gate cap.

US Pat. No. 10,396,171

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A method for forming a semiconductor structure, comprising:providing a substrate;
forming an interlayer dielectric (ILD) on the substrate;
forming a first dummy gate in the ILD, wherein the first dummy gate comprises a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively;
forming two contact holes in the ILD at two sides of the first dummy gate respectively;
removing the dummy gate electrode, so as to form a gate recess in the ILD;
filling a first material layer in the gate recess and a second material layer in the two contact holes respectively; and
performing an anneal process on the two spacers, to bend the two spacers into two inward curving spacers.

US Pat. No. 10,396,170

SEMICONDUCTOR DEVICES AND METHODS FOR FORMING SEMICONDUCTOR DEVICES

Infineon Technologies AG,...

1. A semiconductor device comprising:a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate;
a plurality of graphene layer portions, wherein each of the plurality of graphene layer portions is located adjacent to a respective portion of the transistor doping region at a surface of the semiconductor substrate; and
a transistor wiring structure located adjacent to the plurality of graphene layer portions,
wherein the transistor wiring structure is in contact with the transistor doping region between neighboring graphene layer portions of the plurality of graphene layer portions.

US Pat. No. 10,396,169

NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first nanosheet stack on a substrate, the first nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a second nanosheet stack on the substrate, the second nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a dielectric layer formed over a channel region of the first nanosheet stack;
a first gate formed over the dielectric layer in the channel region of the first nanosheet stack;
a second gate formed over a channel region of the second nanosheet stack;
a first gate contact on the first gate; and
a second gate contact on the second gate;
wherein a distance between adjacent nanosheets in the first nanosheet stack is greater than a distance between adjacent nanosheets in the second nanosheet stack;
wherein spacers are formed between the adjacent nanosheets in the first nanosheet stack and between adjacent nanosheets in the second nanosheet stack;
wherein a length of the spacers between the adjacent nanosheets in the first nanosheet stack is greater than a length of at least one of the spacers between the adjacent nanosheets in the second nanosheet stack;
wherein the first gate comprises a high-k dielectric film formed on a surface of the dielectric layer in the channel region of the first nanosheet stack; and
wherein the length of a bottom most spacer of the spacers below the adjacent nanosheets in the first nanosheet stack is greater than the length of the at least one of the spacers between the adjacent nanosheets in the second nanosheet stack.

US Pat. No. 10,396,168

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first pipe gate;
a second pipe gate disposed on the first pipe gate;
an inter-gate insulating layer disposed between the first pipe gate and the second pipe gate;
first memory cells and second memory cells, disposed on the second pipe gate;
a first channel layer extending toward the first memory cells from the inside of the first pipe gate, the first channel layer connecting the first memory cells in series;
a second channel layer extending toward the second memory cells from the inside of the second pipe gate, the second channel layer connecting the second memory cells in series;
a first contact structure connected to the first pipe gate; and
a second contact structure connected to the second pipe gate.

US Pat. No. 10,396,167

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a first resistive element formed in an insulating film on a semiconductor substrate, the first resistive element including a first portion and a second portion, the first portion being at a different depth and made of a different material than the second portion; and
a second resistive element that differs from the first resistive element, and is formed in the insulating film, the second resistive element located at a different depth in the insulating film as the first portion of the first resistive element, and facing, at least in part, the first portion of the first resistive element with the insulating film therebetween, wherein
the first portion is located in a first region of the first resistive element, and the second portion is connected to the first portion and located in a second region of the first resistive element, and
the second resistive element has terminals to which external voltages are applied, and are connected with the first resistive element between the terminals.

US Pat. No. 10,396,166

SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION

MediaTek Inc., Hsin-Chu ...

1. A semiconductor device, comprising:a semiconductor substrate having a first conductivity type;
a first well doped region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type;
a source doped region formed on the first well doped region, having the second conductivity type;
a drain doped region formed on the first well doped region and separated from the source doped region, having the second conductivity type;
a first gate structure formed over the first well doped region and adjacent to the source doped region;
a second gate structure formed beside the first gate structure and close to the drain doped region; and
a third gate structure formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

US Pat. No. 10,396,165

THIN LOW DEFECT RELAXED SILICON GERMANIUM LAYERS ON BULK SILICON SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a strain relaxed silicon germanium layer having a thickness from 50 nm to 1000 nm and a defect density of less than 100 defect atoms/cm2 located directly on a surface of a silicon substrate, wherein lattices of the strain relaxed silicon germanium layer and the silicon substrate are misaligned.

US Pat. No. 10,396,164

SEMICONDUCTOR CRYSTAL SUBSTRATE WITH FE DOPING

FUJITSU LIMITED, Kawasak...

1. A semiconductor crystal substrate, comprising:a first buffer layer formed of a nitride semiconductor over a substrate;
a second buffer layer formed of a nitride semiconductor on the first buffer layer;
a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer; and
a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer,
wherein an iron (Fe) concentration of the first buffer layer is higher than a carbon (C) concentration of the first buffer layer,
a C concentration of the second buffer layer is higher than an Fe concentration of the second buffer layer throughout the second buffer layer in a thickness direction of the second buffer layer, and
the Fe concentrations of the first and second buffer layers peak at an interface between the first and second buffer layers.

US Pat. No. 10,396,163

SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide epitaxial substrate, comprising:a silicon carbide single crystal substrate having a first main surface; and
a silicon carbide layer on the first main surface,
the silicon carbide layer including a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate,
the second main surface having a maximum diameter of more than or equal to 100 mm,
the second main surface including an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region,
the central region having a haze of more than or equal to 20 ppm and less than or equal to 75 ppm.

US Pat. No. 10,396,162

SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device, comprising:a first semiconductor layer of a first conductivity type, formed on a front surface of a silicon carbide semiconductor substrate of the first conductivity type;
a first semiconductor region of a second conductivity type, selectively formed in a surface layer of the first semiconductor layer;
a second semiconductor region of the second conductivity type, selectively formed in the surface layer of the first semiconductor layer so as to be connected with the first semiconductor region, bottoms of the first semiconductor region and the second semiconductor region being located at a same depth relative to a surface of the first semiconductor layer and within the first semiconductor layer;
a first electrode forming a Schottky contact with the first semiconductor layer and the first semiconductor region; and
a second electrode forming an ohmic contact with the second semiconductor region,
wherein
a density of the second electrode per unit area of the silicon carbide semiconductor substrate in a plan view is higher at a center portion of the silicon carbide semiconductor substrate and decreases in a direction toward an outer peripheral side of the silicon carbide semiconductor substrate.

US Pat. No. 10,396,161

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising: a silicon carbide (SiC) substrate of a first conductivity type, having a front surface and a back surface; a SiC layer of the first conductivity type, formed on the front surface of the SiC substrate and having an impurity concentration lower than that of the SiC substrate; a first region of a second conductivity type, selectively formed in the SiC layer at a surface thereof; a source region of the first conductivity type formed in the first region; a contact region of the second conductivity type formed in the first region, the contact region having an impurity concentration higher than that of the first region; a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region; a first gate electrode disposed on the gate insulating film above the portion of the first region; an interlayer insulating film covering the first gate electrode; a source electrode electrically connected to the source region and the contact region; a drain electrode formed on the back surface of the SiC substrate; a first barrier film formed on and covering the interlayer insulating film, interposing the source electrode and the interlayer insulating film, the first barrier film separating the source electrode from the interlayer insulating film, so as to prevent penetration of metal atoms of the source electrode into the interlayer insulating film; and a first metal electrode formed directly on the source electrode and the first barrier film, wherein the first barrier film is formed by a single-layer structure of titanium nitride (TiN), or a layered structure of titanium (Ti) and TiN, and the first metal electrode is formed by a layered structure of Ti and aluminum (Al).

US Pat. No. 10,396,160

SEMICONDUCTOR STRUCTURE HAVING A SINGLE OR MULTIPLE LAYER POROUS GRAPHENE FILM AND THE FABRICATION METHOD THEREOF

CHANG GUNG UNIVERSITY, T...

1. A semiconductor structure having a single-layer porous graphene film with a thickness of about 0.34 nm, formed by a low pressure chemical vapor deposition (LPCVD) and a metalorganic chemical vapor deposition (MOCVD), comprising:a sapphire substrate;
wherein said single-layer porous graphene film having the thickness of about 0.34 nm is provided on said sapphire substrate, said single-layer porous graphene film being formed on a metal foil by the low pressure chemical vapor deposition (LPCVD) at 900° C. to 1100° C. via passing through methane (CH4) and hydrogen (H2),
wherein said metal foil is selected from a group consisting of a Cu foil or Ni foil; and
wherein a gallium nitride layer is formed on said single-layer porous graphene film, said gallium nitride being deposited on said single-layer porous graphene film and said sapphire substrate by using the metalorganic chemical vapor deposition (MOCVD) at 900° C. to 1100° C.

US Pat. No. 10,396,159

FINFET CASCODE LATERALLY-DIFFUSED SEMICONDUCTOR DEVICE

AVAGO TECHNOLOGIES INTERN...

1. A semiconductor device, comprising:a substrate having a first well region comprising a first dopant and a second well region comprising a second dopant;
one or more semiconductor fin structures formed on the substrate, the one or more semiconductor fin structures having a channel region along a channel axis through the first well region;
a drain region formed on the one or more semiconductor fin structures;
a source region formed on the one or more semiconductor fin structures, the first well region and the drain region being formed to operate at a first operating voltage, the second well region and the source region being formed to operate at a second operating voltage that is smaller than the first operating voltage;
a gate structure disposed on at least a portion of the one or more semiconductor fin structures;
a dummy gate disposed on at least a portion of the one or more semiconductor fin structures, the dummy gate being disposed between the gate structure and the drain region; and
a plurality of epitaxial growth structures formed on the one or more semiconductor fin structures, wherein the dummy gate is disposed between and adjacent to two epitaxial growth structures of the plurality of epitaxial growth structures, and wherein the plurality of epitaxial growth structures comprises a doping material having a doping concentration that is greater than that of at least one of the first dopant or the second dopant.

US Pat. No. 10,396,158

TERMINATION STRUCTURE FOR NANOTUBE SEMICONDUCTOR DEVICES

Alpha and Omega Semicondu...

1. A termination structure for a semiconductor device including an active area and a termination area surrounding the active area, the termination structure being formed in the termination area and comprising:a first semiconductor layer of a first conductivity type comprising a plurality of trenches formed in a top surface of the first semiconductor layer, the trenches forming mesas in the first semiconductor layer;
a first epitaxial layer of the first conductivity type formed on the sidewalls of the mesas;
a second epitaxial layer of a second conductivity type, opposite the first conductivity type, formed on the first epitaxial layer, the trenches between the second epitaxial layer formed on adjacent mesas being filled with a first dielectric layer;
a first termination cell formed in the termination area at an interface to the active area, the first termination cell being formed in a mesa of the first semiconductor layer and having a first width; and
an end termination cell being formed away from the interface to the active area in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

US Pat. No. 10,396,157

SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A semiconductor device comprising:a semiconductor layer having a first device region and a second device region;
a shallow trench isolation structure, in the semiconductor layer, located at a periphery of the first device region and the second device region;
a first insulating layer and a second insulating layer, on the semiconductor layer, respectively located in the first device region and the second device region;
a first gate structure located on the first insulating layer;
a source region and a drain region, in the semiconductor layer, located at two sides of the first gate structure;
a gate doped region in a surface region of the semiconductor layer in the second device region to serve as a second gate structure;
a channel layer located on the second insulating layer; and
a source layer and a drain layer, directly on the shallow trench isolation structure, located at two sides of the channel layer.

US Pat. No. 10,396,156

METHOD FOR FINFET LDD DOPING

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a structure that includes a substrate, a fin over the substrate, and a gate structure engaging the fin;
performing a first implantation process to implant a dopant into the fin adjacent to the gate structure;
forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin;
performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers;
after the first etching process, performing a second implantation process to implant the dopant into the fin and the fin sidewall spacers;
after the second implantation process, performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers; and
epitaxially growing a semiconductor material in the trench.

US Pat. No. 10,396,154

LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE

International Business Ma...

1. A device comprising:a dielectric pedestal including a nucleation dielectric layer;
a base region comprised of a germanium containing material in contact with the pedestal, wherein the germanium containing material is silicon free germanium; and
an emitter region and collector region present on opposing sides of the base region contacting a sidewall of the pedestal and an upper surface of the nucleation dielectric layer.

US Pat. No. 10,396,153

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer;
a third nitride semiconductor layer formed on the second nitride semiconductor layer;
a mesa-shaped fourth nitride semiconductor layer formed on the third nitride semiconductor layer;
a source electrode formed on the third nitride semiconductor layer and formed on one side of the fourth nitride semiconductor layer;
a drain electrode formed on the third nitride semiconductor layer and formed on the other side of the fourth nitride semiconductor layer;
a gate electrode formed over the fourth nitride semiconductor layer; and
an element isolation region provided in a stack body of the first to fourth nitride semiconductor layers and defining an active region,
wherein the gate electrode extends from over the active region to over the element isolation region, and
wherein in plan view, length of a border line between the active region and the element isolation region in a region overlapped with the mesa-shaped fourth nitride semiconductor layer is longer than gate length of the gate electrode.

US Pat. No. 10,396,152

FABRICATION OF PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE USING INTERFACE INTERACTION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a plurality of vertically stacked suspended nanowires extending having a gate structure being present on a channel region portion of the suspended nanowires;
a dielectric spacer having a uniform composition in direct contact with the gate structure, the dielectric spacer having a uniform length extending from a upper surface of the gate structure to the base of the gate structure, wherein a first length of the dielectric spacer positioned between adjacently stacked suspended nanowires is substantially equal to a second length of the dielectric spacer adjacent to the upper surface of the gate structure; and
source and drain regions present on source and drain region portions of the plurality of suspended nanowires, wherein the suspended nanowires are uniform in geometry along an entire length of the suspended nanowires from a channel region of the suspended nanowire to the source and drain region portions of the suspended nanowire.

US Pat. No. 10,396,151

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of forming a fin field effect transistor device, comprising:forming a vertical fin layer on a bottom source/drain layer;
forming one or more fin templates on the vertical fin layer;
forming a vertical fin below each of the one or more fin templates;
reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin; and
depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.

US Pat. No. 10,396,149

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a wide-bandgap semiconductor substrate of a first conductivity type containing a semiconductor material having a bandgap wider than that of silicon;
a first wide-bandgap semiconductor layer of the first conductivity type provided on a front surface of the wide-bandgap semiconductor substrate, the first wide-bandgap semiconductor layer containing a semiconductor material having a bandgap wider than that of silicon, an impurity concentration of the first wide-bandgap semiconductor layer being lower than that of the wide-bandgap semiconductor substrate;
a base region of a second conductivity type selectively provided in a first side of the first wide-bandgap semiconductor layer opposite to a second side of the first wide-bandgap semiconductor layer facing toward the wide-bandgap semiconductor substrate;
a second wide-bandgap semiconductor layer of the second conductivity type provided on a surface on the first side of the first wide-bandgap semiconductor layer opposite to the second side of the first wide-bandgap semiconductor layer facing toward the wide-bandgap semiconductor substrate;
a source region of the first conductivity type selectively provided in the second wide-bandgap semiconductor layer;
a plurality of trenches that are parallel to each other, each penetrating the source region and the second wide-bandgap semiconductor layer to reach the first wide-bandgap semiconductor layer;
a gate electrode provided in each of the trenches, with a gate insulating film disposed therebetween;
a source electrode contacting the second wide-bandgap semiconductor layer and the source region; and
a drain electrode on a rear surface of the wide-bandgap semiconductor substrate, wherein
the base region includes a plurality of first portions that extend in a direction perpendicular to the trench plurality of trenches, the first portions being spaced apart from each other by a same predetermined distance in a direction parallel to the trenches,
the base region is formed at a bottom end of the trenches and includes a second portion formed at a bottom end of each of the trenches, the second portion extending in a direction parallel to the trenches, the second portion connecting the plurality of first portions of the base region to each other, and
the base region is free of any portion that extends in a direction parallel to the trenches and that intersects any of the first portions of the base region between two abutting trenches except the second portion.

US Pat. No. 10,396,148

SEMICONDUCTOR DEVICE

MURATA MANUFACTURING CO.,...

1. A semiconductor device comprising:a semiconductor layer arranged on a semiconductor substrate, the semiconductor layer comprising a first active region and an element isolation region, wherein, when the semiconductor device is viewed in a plan view, the element isolation region surrounds the first active region;
a first field effect transistor formed in the first active region;
a plurality of guard ring electrodes separated from each other and configured to affect an electric potential of the first active region through the element isolation region;
an interlayer insulating film formed over the semiconductor layer, the first field effect transistor, and the guard ring electrodes; and
at least one guard ring connection wiring formed on the interlayer insulating film and configured to electrically interconnect the plurality of guard ring electrodes.

US Pat. No. 10,396,147

GRATED MIM CAPACITOR TO IMPROVE CAPACITANCE

International Business Ma...

1. A method of forming a semiconductor structure comprising:providing a metallization structure comprising a first dielectric material layer and a first lower interconnect structure embedded in a portion of the first dielectric material layer and a second lower interconnect structure embedded in another portion of the first dielectric material layer;
forming a second dielectric material layer on the metallization structure;
forming a plurality of trenches in an upper portion of the second dielectric material layer, wherein the plurality of trenches extend across the first lower interconnect structure and the second lower interconnect structure, and each trench defines a gap that is present between a neighboring pair of dielectric mesa portions of the second dielectric material layer;
forming a first metal layer along sidewall surfaces and a bottom surface of each trench of the plurality of trenches and a topmost surface of each of the dielectric mesa portions of the second dielectric material layer;
patterning the first metal layer to remove the first metal layer completely from an area where the second lower interconnect structure is located, wherein the patterning the first metal layer provides a first metal portion overlying the first lower interconnect structure, and wherein the first metal portion is continuously present on the sidewall surfaces and the bottom surface of each trench that is located above and between the first lower interconnect structure and the second lower interconnect structure, and the first metal portion has a first end wall that is vertically aligned with a sidewall of a first dielectric mesa portion of the second dielectric material that overlies the first lower interconnect structure and a second end wall that is vertically aligned with a sidewall of a second dielectric mesa portion of the second dielectric material that is laterally adjacent to, but not, directly over the second lower interconnect structure;
forming a first capacitor dielectric layer on the first metal portion and exposed surfaces of the plurality of trenches;
forming a second metal layer over the first capacitor dielectric layer;
patterning the second metal layer to remove the second metal layer completely from an area where the first lower interconnect structure is located, wherein the patterning the second metal layer provides a second metal portion overlying the second lower interconnect structure;
forming a third dielectric material layer to completely fill the plurality of trenches; and
forming a first upper interconnect structure extending through the third dielectric material layer, the first capacitor dielectric layer, the first metal portion and the second dielectric material layer to contact the first lower interconnect structure, and a second upper interconnect structure extending through the third dielectric material layer, the second metal portion, the first capacitor dielectric layer and the second dielectric material layer to contact the second lower interconnect structure, wherein the forming of the first upper interconnect structure comprises removing an entirety of the first and second mesa portions of the second dielectric material.

US Pat. No. 10,396,146

LEAKAGE CURRENT REDUCTION IN STACKED METAL-INSULATOR-METAL CAPACITORS

INTERNATIONAL BUSINESS MA...

1. A method of forming a capacitor, comprising:forming a dielectric layer on a first metal layer;
oxygenating the dielectric layer such that interstitial oxygen is implanted in the dielectric layer;
forming a second metal layer on the dielectric layer; and
heating the dielectric layer to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

US Pat. No. 10,396,145

MEMORY CELLS COMPRISING FERROELECTRIC MATERIAL AND INCLUDING CURRENT LEAKAGE PATHS HAVING DIFFERENT TOTAL RESISTANCES

Micron Technology, Inc., ...

1. A memory cell, comprising:a capacitor comprising:
a first capacitor electrode having laterally-spaced walls that individually have a top surface;
a second capacitor electrode laterally between the walls of the first capacitor electrode, the second capacitor electrode comprising a portion above the first capacitor electrode; and
ferroelectric material laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode, the capacitor comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material; and
a parallel current leakage path between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode, the parallel current leakage path being circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path.

US Pat. No. 10,396,144

MAGNETIC INDUCTOR STACK INCLUDING MAGNETIC MATERIALS HAVING MULTIPLE PERMEABILITIES

INTERNATIONAL BUSINESS MA...

1. An inductor structure, comprising:a laminated first stack including:
layers having insulating material; and
layers having a first magnetic material, the layers having insulating material alternating with the layers having the first magnetic material; and
a laminated second stack including:
layers having second insulating material; and
layers having a second magnetic materials, the second magnetic materials having at least two different permeabilities,
wherein the layers having the second insulating material alternate with the layers having the second magnetic material, the second magnetic material having a permeability larger than that of the first magnetic material, and
wherein the first and second magnetic materials are selected from the group consisting of a Co containing magnetic material, FeTaN, and FeNi.

US Pat. No. 10,396,143

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device comprising: a substrate with an active area and a pad area; a first anode electrode in the active area of the substrate; a second anode electrode on the first anode electrode, the second anode electrode being electrically connected to the first anode electrode; an organic emitting layer on the second anode electrode; a cathode electrode on the organic emitting layer; a first auxiliary electrode in a same layer as the first anode electrode; a second auxiliary electrode in a same layer as the second anode electrode, the second auxiliary electrode being electrically connected to the first auxiliary electrode and the cathode electrode, a first signal line and a second signal line in the active area; a first pad in the pad area and connected to the first signal line, wherein the first pad includes a link region electrically connected to the first signal line and a first bonding region connected to the link region, the first bonding region including one or more first contact holes for electrical connection with the link region; and a second pad in the pad area and connected to the second signal line, wherein the second pad includes a second bonding region corresponding to the first bonding region of the first pad and a contact region corresponding to the link region of the first pad, the contact region being electrically connected to the second bonding region and including one or more second contact holes for electrical connection with the second signal line.

US Pat. No. 10,396,142

ARRAY SUBSTRATE AND AMOLED DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate, comprising:a substrate;
a driver chip, located on the substrate;
a plurality of data lines, arranged in turn on the substrate and extended longitudinally to be connected electrically to the driver chip;
a plurality of high level lines, arranged in turn on the substrate, and extending longitudinally on the substrate;
a metal block, located on the substrate and electrically connected to the high level lines, so that the high level lines are at the same high level; wherein the data lines are electrically connected to the driver chip through the area which the metal block is located in, and an insulating layer exists between the metal block and the data lines, a hollow area located in the metal block overlapping the data lines to reduce parasitic capacitance formed by the metal block and the data lines, wherein the hollowed area is a plurality of derating slits, the number of the derating slits is multiple, and at least one of the data lines corresponds to at least one of the derating slits one to one,
wherein de-electrostatic slits are provided in the metal block, the de-electrostatic slits are not overlapping the data lines and are surrounded by the metal block.

US Pat. No. 10,396,141

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device, comprising:a flexible substrate including an image display area and a non-display area surrounding the image display area;
a first insulating film disposed on the flexible substrate;
a switching element disposed on the first insulating film;
a second insulating film disposed on a semiconductor layer of the switching element;
a third insulating film disposed on a gate electrode of the switching element;
a signal wiring disposed on the third insulating film and electrically connected with the switching element;
a first organic film disposed on the signal wiring;
a connection wiring disposed on the first organic film and electrically connected with the signal wiring through a first contact hole in the first organic film;
a second organic film disposed on the connection wiring and the first organic film; and
a pad electrode disposed on the second organic film and electrically connected with the connection wiring through a second contact hole in the second organic film,
wherein the connection wiring is located between the first organic film and the second organic film and is in contact with the first organic film and the second organic film,
the non-display area includes a first area adjacent to the image-display area, a second area adjacent to the first area, and a third area adjacent to the second area,
the flexible substrate is bent at the second area in which the connection wiring is located between the first organic film and the second organic film,
the first contact hole is located in the first area,
the second contact hole is located in the third area,
the connection wiring is formed continuously as one unitary wiring from the first contact hole to the pad electrode, and
the first insulating film, the second insulating film, and the third insulating film are not disposed in the second area,
the first organic film is in contact with a surface of the flexible substrate in the second area,
the first organic film has a first thickness in the first area and the third area, and a second thickness in the second area, and
the second thickness is larger than the first thickness.

US Pat. No. 10,396,140

THIN FILM TRANSISTOR INCLUDING A VERTICAL CHANNEL AND DISPLAY APPARATUS USING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor comprising:a substrate;
a gate electrode disposed over the substrate, and comprising a center part and a peripheral part configured to at least partially surround the center part, wherein the gate electrode includes an opening disposed directly between the center part and the peripheral part, and the opening at least partially surrounds the center part of the gate electrode;
a gate insulating layer disposed below the gate electrode;
a first electrode insulated from the gate electrode by the gate insulating layer, and having at least a portion thereof overlapping the center part in a direction perpendicular to an upper surface of the substrate;
a spacer disposed below the first electrode;
a second electrode insulated from the first electrode by the spacer, and having at least a portion thereof overlapping the peripheral part; and
a semiconductor layer connected to the first and second electrodes, and insulated from the gate electrode by the gate insulating layer.

US Pat. No. 10,396,139

ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY

Samsung Display Co., Ltd....

1. An organic light-emitting diode (OLED) display, comprising:a substrate;
an active pattern formed over the substrate and including: a first region, a second region, a third region, a fourth region, a fifth region, and a sixth region, wherein the second region and the sixth region are: i) electrically connected to each other and ii) formed directly adjacent each other in a first continuous region of the active pattern, and wherein the fourth region and the fifth region are: i) electrically connected to each other and ii) formed directly adjacent each other in a second continuous region of the active pattern;
a gate insulation layer formed over the active pattern;
a first gate electrode formed over the gate insulation layer, wherein the first gate electrode defines a first transistor together with the first region and the second region;
a second gate electrode formed on the same layer as the first gate electrode, wherein the second gate electrode defines: i) a second transistor together with the third region and the fourth region which are arranged in a first direction ii) a third transistor together with the fifth region and the sixth region which are arranged in a second direction, wherein the fifth region and the sixth region are on opposite sides of a gate region of the third transistor, and wherein the second direction is substantially perpendicular to the first direction;
a first insulating interlayer formed over the first gate electrode, the second gate electrode, and the gate insulation layer;
a first conductive pattern formed over the first insulating interlayer, wherein the first conductive pattern overlaps at least a portion of the fourth and fifth regions in a thickness direction of the substrate, wherein the first conductive pattern defines a parasitic capacitor together with the portion of the fourth and fifth regions; and
an OLED configured to receive a driving current from the first transistor,
wherein the second and third transistors are configured to provide an initialization voltage to the first transistor.

US Pat. No. 10,396,138

ORGANIC LIGHT EMITTING DEVICE

LG Display Co., Ltd., Se...

1. An organic light emitting device comprising:an overcoat layer disposed on a substrate and including a plurality of convex parts or a plurality of concave parts, at least one of the convex parts of the overcoat layer having a Full Width at High Maximum (“FWHM”) smaller than a radius of said at least one of the convex parts of the overcoat layer;
a first electrode disposed on the overcoat layer in a direction away from the substrate;
an organic light emitting layer disposed on the first electrode in the direction away farther from the substrate than the first electrode is from the substrate; and
a second electrode disposed on the organic light emitting layer in the direction farther away from the substrate than the organic light emitting layer is from the substrate.

US Pat. No. 10,396,137

TESTING TRANSFER-PRINT MICRO-DEVICES ON WAFER

X-Celeprint Limited, Cor...

1. A method of making and testing transfer-printable micro-devices on a source wafer, comprising:providing the source wafer comprising a plurality of sacrificial portions spatially separated by anchors, the source wafer comprising one or more test contact pads;
providing at least one micro-device disposed entirely over each of the plurality of sacrificial portions, each of the at least one micro-device physically connected to at least one of the anchors;
providing one or more electrical test connections from each of the at least one micro-device to a corresponding test contact pad;
testing the at least one micro-device disposed over each of the plurality of sacrificial portions through the one or more test connections to determine one or more functional micro-devices and one or more faulty micro-devices; and
removing at least a portion of the one or more test connections.

US Pat. No. 10,396,135

OLED SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting display (OLED) substrate, comprising a plurality of pixel regions, at least one of the plurality of pixel regions provided with a pixel driving circuit, and comprising a display region and a connection region; wherein,the OLED substrate comprises:
a base;
a reflective electrode layer disposed on the base, wherein the reflective electrode layer comprises a plurality of reflective electrodes, each of which is correspondingly disposed in one display region;
a pixel defining layer disposed on the reflective electrode layer, wherein the pixel defining layer is provided with a first opening corresponding to the display region and a second opening corresponding to the connection region;
a light-emitting material layer disposed in the first opening;
a display electrode continuously disposed on the light-emitting material layer and in the second opening, wherein the display electrodes in the respective pixel regions are electrically insulated from each other,
wherein the display electrode in each of the at least one pixel region is electrically coupled to the pixel driving circuit in the pixel region through the second opening, and
a barrier layer surrounding one pixel region provided with a pixel driving circuit is disposed on the pixel defining layer, wherein the barrier layer has a thickness of about 20 to 500 nm, and an angle between a top surface of the barrier layer away from the pixel defining layer and a side surface of the barrier layer is greater than or equal to about 60° such that the display electrode is broken at the side surface of the barrier layer to separate a display electrode in the one pixel region from a display electrode in an adjacent pixel region.

US Pat. No. 10,396,134

FLEXIBLE COLOR FILTER INTEGRATED WITH TOUCH SENSOR, ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

DONGWOO FINE-CHEM CO., LD...

1. A manufacturing method of a flexible color filter integrated with a touch sensor, the manufacturing method comprising:forming a separation layer on a carrier substrate;
forming a color filter array on one surface of the separation layer;
forming an overcoating layer on the color filter array;
forming a touch sensor array on the overcoating layer;
forming a refractive index adjusting layer between the color filter array and the touch sensor array;
forming a first protective film on the touch sensor array;
separating the carrier substrate from the separation layer;
forming a second protective film on the other surface of the separation layer;
separating the first protective film, which is formed on the touch sensor array, from the touch sensor array; and
forming a base film on the touch sensor array.

US Pat. No. 10,396,133

TWO-WAY ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A two way organic light emitting diode display device including red, green and blue sub-pixels defined at an array substrate, comprising:a plurality of driving thin film transistors each driving corresponding each of the red, green and blue sub-pixels;
an organic light emitting diode disposed at each sub-pixel and including an anode layer electrically connected to each thin film transistor at the red, green and blue sub-pixels, an organic light emitting layer disposed on the anode layer and emitting white light, and a cathode layer disposed on the organic light emitting layer;
an encapsulating substrate encapsulating the plurality of driving thin film transistors and the organic light emitting diode; and
red, green and blue color filters corresponding to each of the red, green and blue sub-pixels and disposed on the encapsulating substrate,
wherein the anode layer includes a first electrode, a first color control layer corresponding to the red sub-pixel and disposed on the first electrode, a second color control layer corresponding to the green sub-pixel and disposed on the first electrode, a third color control layer corresponding to the blue sub-pixel and disposed on the first electrode, a second electrode disposed on the first, second and third color control layers,
wherein the white light passes through the anode layer and is converted to red, green and blue light in a first direction and passes through the red, green and blue color filters and is converted to red, green and blue light in a second direction, opposite to the first direction.

US Pat. No. 10,396,132

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a display element;
a wavelength conversion element disposed on the display element and comprising a plurality of first wavelength conversion layers and a plurality of second wavelength conversion layers arranged in a first predetermined pattern;
a transparent frame disposed on the wavelength conversion element and having a plurality of air gaps defined on a surface facing the wavelength conversion element, wherein the air gaps are recessed in a thickness direction; and
a color filter element disposed on the transparent frame and comprising a plurality of first wavelength filter layers, a plurality of second wavelength filter layers, and a plurality of third wavelength filter layers arranged in a second predetermined pattern,
wherein the first and second wavelength filter layers are arranged to overlap the first and second wavelength conversion layers, respectively, and
wherein the air gaps are arranged to overlap the first and second wavelength conversion layers.

US Pat. No. 10,396,131

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a substrate;
a pixel electrode over the substrate;
a pixel-defining layer comprising an opening that exposes at least a portion of the pixel electrode;
an intermediate layer, which is over the portion of the pixel electrode exposed by the opening and comprises an organic emission layer;
a counter electrode over the intermediate layer; and
an encapsulating structure, which is over the counter electrode and comprises at least one inorganic layer and at least one organic layer, wherein the at least one inorganic layer is in the opening and extends outside the opening, and wherein the at least one organic layer comprises quantum dots and is formed in the opening such that a thickness of the encapsulating structure in the opening is greater than a thickness of the encapsulating structure outside the opening.

US Pat. No. 10,396,130

DISPLAY SUBSTRATE INCLUDING SUB-ELECTRODES HAVING TRAPEZIUM SHAPE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a display substrate, wherein the display substrate comprises a first electrode formed on a base substrate, the display substrate comprises a plurality of sub-pixels, the first electrode comprises a plurality of sub-electrodes corresponding to the plurality of sub-pixels respectively, wherein the display substrate further comprises: a pixel definition layer arranged on the base substrate on which the plurality of sub-electrodes has been formed, wherein the pixel definition layer is made of an opaque material, and comprises light-transmissible openings corresponding to the sub-electrodes respectively, and an overlapping area between an orthogonal projection of each of the openings on the base substrate and an orthogonal projection of a sub-electrode corresponding to the opening on the base substrate is within a predetermined range, wherein a distance between two crossing points of a first line and each sub-electrode changes when the first line extending in a first direction moves in a second direction within an area of each of the sub-electrodes, the first direction is perpendicular to the second direction, the overlapping area is an effective light-emitting area of each sub-pixel corresponding to a respective sub-electrode, the openings of the pixel definition layer are of an identical shape, each of the openings is a rectangle, each of two opposite sides of the rectangle is parallel to the first direction, the sub-electrodes are trapeziums, and each of two parallel sides of each of the trapeziums is parallel to the first direction, wherein the method comprises:determining a predetermined requirement of the effective light-emitting area of each sub-pixel; and
forming the pixel definition layer on the base substrate on which the plurality of sub-electrodes has been formed, wherein a location of the pixel definition layer on the display substrate is controlled in the second direction, to control the overlapping area between the orthogonal projection of each of the openings on the base substrate and the orthogonal projection of the sub-electrode corresponding to the opening on the base substrate to be within a predetermined range, and the effective light-emitting area of the sub-pixel is enabled to satisfy the predetermined requirement by the overlapping area being the effective light-emitting area of the sub-pixel corresponding to the sub-electrode.

US Pat. No. 10,396,129

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light-emitting display device comprising:a substrate;
a pixel disposed on the substrate and including a plurality of subpixels;
an overcoat layer disposed on the substrate, the overcoat layer including microlenses having a plurality of concave portions concavely formed from an upper surface of the overcoat layer;
an organic electroluminescent device disposed on the overcoat layer;
a bank pattern disposed on the overcoat layer and configured to define a light-emitting area of the plurality of subpixels; and
light filter layers respectively disposed in each of the plurality of subpixels,
wherein some of the plurality of subpixels include both microlenses and the respective light filter layer, and the remaining subpixels of the plurality of subpixels include only the light filter layer,
wherein the organic electroluminescent device disposed in the some of the plurality of subpixels is directly contacted with a surface of the microlenses, and
wherein the organic electroluminescent device disposed in the remaining subpixels is directly contacted with the overcoat layer.

US Pat. No. 10,396,128

ANTI-REFLECTIVE OPTICAL FILM AND BENDABLE DISPLAY APPARATUS INCLUDING THE OPTICAL FILM

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a display panel configured to display an image, the display panel including a folding axis extending in a first direction; and
an optical film disposed over the display panel, the optical film comprising a circular polarizer comprising at least two phase retarders and one polarizer, wherein each of the at least two phase retarders has a slow axis and a fast axis,
wherein the optical film is delineated into four quadrants by the folding axis and a virtual axis extending in a second direction perpendicular to the first direction, and
wherein slow axes of each of the at least two phase retarders are located in a same quadrant of the four quadrants of the optical film.

US Pat. No. 10,396,127

CONSTRUCTIONS COMPRISING STACKED MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a semiconductor construction, comprising:forming a first memory array deck comprising phase change memory containing first memory cells comprising a first chalcogenide, the first memory cells being laterally spaced from one another by a first dielectric material;
forming a second memory array deck over the first memory array deck, the second memory array deck containing second memory cells comprising a second chalcogenide that differs from the first chalcogenide in one or both of composition and thickness, the second memory cells being separated from one another by a second dielectric material, the first and second dielectric materials differing from another in one or more structural parameters selected from differing materials and differing material thicknesses; and
providing a first series of access/sense lines and a second series of access/sense lines, the first series of access/sense lines being disposed vertically between the first memory array deck and the second memory array deck, the lines of the first series of access/sense lines being formed of a single material; the second series of access/sense lines being disposed vertically above the second memory array deck, the lines of the second series of access/sense lines comprising multiple materials.

US Pat. No. 10,396,126

RESISTIVE MEMORY DEVICE WITH ELECTRICAL GATE CONTROL

International Business Ma...

1. A semiconductor device comprising:a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode;
a bottom dielectric layer disposed on the first side of the bottom electrode around the gate structure;
a top dielectric layer disposed on the first side of the top electrode around the gate structure; and
a gate electrode disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode to produce a conductive filament in the resistive switching medium with linear switching relative to the current flow.

US Pat. No. 10,396,125

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Micron Technology, Inc., ...

1. A method, comprising:forming a first memory cell pillar and a second memory cell pillar on a substrate, wherein the first memory cell pillar and the second memory cell pillar are separated by a first gap; and
partially filling the first gap with a gap-seal dielectric to form a seal region wherein the seal region is formed above a buried void that is in contact with at least a portion of opposing side walls of each of the first memory cell pillar and the second memory cell pillar, wherein the seal region comprises abutting portions formed in the first gap; and forming an isolation region above a bottom surface of the seal region between the abutting portions in the first gap.

US Pat. No. 10,396,124

MEMORY CELLS AND DEVICES

XEROX CORPORATION, Norwa...

1. A memory cell comprising a protective layer in the form of a crosslinked mixture of a polyether-modified acrylate oligomer; a polyester acrylic resin; a component selected from the group consisting of a silicone acrylate oligomer and a fluorinated acrylate oligomer; and a photoinitiator, wherein the polyether-modified acrylate oligomer, the polyester acrylic resin, the component, and the photoinitiator are present at a ratio in a range of from about 30/62/4/4 to about 48/49/1/2.

US Pat. No. 10,396,123

TEMPLATING LAYERS FOR PERPENDICULARLY MAGNETIZED HEUSLER FILMS

International Business Ma...

1. A device, comprising:a multi-layered structure that is non-magnetic at room temperature, the structure comprising alternating layers of Co and E, wherein E comprises at least one other element that includes Al, wherein the composition of the structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55; and
a first magnetic layer that includes a Heusler compound, the magnetic layer being in contact with the structure.

US Pat. No. 10,396,122

HALL SENSOR WITH BURIED HALL PLATE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:a substrate having a surface;
a first doped region extending from the surface to a first depth, the first doped region having a first conductivity type;
a second doped region within the first doped region, and extending from the surface to a second depth less than the first depth, the second doped region having a second conductivity type opposite of the first conductivity type;
a first transistor within the second doped region;
a second transistor outside of the first doped region and the second doped region; and
a Hall sensor having a Hall plate in the first doped region below the second depth and free of overlapping the second transistor.

US Pat. No. 10,396,121

FINFETS FOR LIGHT EMITTING DIODE DISPLAYS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming replacement fin structures with a doped core region, on doped substrate material;
forming isolation regions between the replacement fin structures;
forming quantum wells over the replacement fin structures;
forming contacts between each of the replacement fin structures and contacting the substrate material through the isolation regions;
forming a first color emitting region by depositing a first material on at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and
forming a second color emitting region by depositing a second material on another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to have the second material deposited thereon.

US Pat. No. 10,396,120

METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL WAFER AND METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE

SUMCO CORPORATION, Tokyo...

1. A method of producing a semiconductor epitaxial wafer, the method comprising:a first irradiating provided by irradiating a surface of a semiconductor wafer with cluster ions containing hydrogen as a constituent element, to form a modifying layer formed from, as a solid solution, a constituent element of the cluster ions including hydrogen in a surface portion of the semiconductor wafer;
a second irradiating, after the first irradiating, provided by irradiating the semiconductor wafer with electromagnetic waves of a frequency of 300 MHz or more and 3 THz or less, to heat the semiconductor wafer; and
after the second irradiating, forming an epitaxial layer on the modifying layer of the semiconductor wafer.

US Pat. No. 10,396,119

UNIT PIXEL OF IMAGE SENSOR, IMAGE SENSOR INCLUDING THE SAME AND METHOD OF MANUFACTURING IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a unit pixel of an image sensor, the method comprising:forming a photoelectric conversion region in a substrate;
forming, in the substrate, a first floating diffusion region spaced apart from the photoelectric conversion region of the substrate, and a second floating diffusion region spaced apart from the first floating diffusion region;
forming a first recess spaced apart from the first floating diffusion region and the second floating diffusion region by removing a portion of the substrate from a first surface of the substrate;
filling the first recess to form a dual conversion gain (DCG) gate that extends perpendicularly or substantially perpendicularly from the first surface of the substrate; and
forming a conductive layer to fill an inside of the first recess.

US Pat. No. 10,396,118

SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device, comprising:first and second semiconductor substrates;
a photoelectric conversion element outputting a pixel signal based on an incident light, wherein the photoelectric conversion element is disposed in the first semiconductor substrate,
an analog circuit that generates an analog signal based on the pixel signal, wherein a first part of the analog circuit is disposed on the first semiconductor substrate, the first part comprising a transfer transistor, a reset transistor, a select transistor, and an amplification transistor, and wherein a second part of the analog circuit is disposed on the second semiconductor substrate, the second part comprising a current supply transistor for current supply;
a digital circuit on the second semiconductor substrate, wherein the digital circuit converts the analog signal into a digital signal;
a connection connecting the first part of the analog circuit to the second part of the analog circuit; and
a light-shielding metal disposed between the current supply transistor and the photoelectric conversion element.

US Pat. No. 10,396,117

OPTICAL RECEIVER SYSTEMS AND DEVICES WITH DETECTOR ARRAY INCLUDING A PLURALITY OF SUBSTRATES DISPOSED IN AN EDGE TO EDGE ARRAY

Waymo LLC, Mountain View...

1. A system comprising:a plurality of substrates disposed in an edge-to-edge array along a primary axis, wherein each respective substrate of the plurality of substrates comprises:
a plurality of detector elements, wherein each detector element of the plurality of detector elements generates a respective detector signal in response to light received by the detector element, wherein the plurality of detector elements is arranged with a detector pitch between adjacent detector elements of the plurality of detector elements, and wherein the detector pitch is a distance between respective centers of adjacent detector elements;
a signal receiver circuit configured to receive the detector signals generated by the plurality of detector elements, wherein the respective substrates of the plurality of substrates are disposed such that the detector pitch is maintained between adjacent detector elements on their respective substrates; and
an encapsulation overlaying at least the plurality of detector elements, wherein the encapsulation comprises an alignment structure configured to provide lateral alignment between respective substrates of the plurality of substrates.

US Pat. No. 10,396,116

SOLID-STATE IMAGE-CAPTURING ELEMENT AND ELECTRONIC DEVICE

SONY SEMICONDUCTOR SOLUTI...

1. A solid-state image-capturing element, comprising:a floating diffusion;
a floating diffusion wiring connected to the floating diffusion; and
a wiring other than the floating diffusion wiring,
wherein at least a part of a first region between the floating diffusion wiring and the wiring other than the floating diffusion wiring is a hollow region, and
wherein the floating diffusion wiring and the hollow region are not in contact with each other.

US Pat. No. 10,396,115

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE SENSOR AND CAMERA SYSTEM

Sony Corporation, Tokyo ...

1. A light detecting device, comprising:a first substrate having a first surface and a second surface opposite the first surface;
a pixel array unit comprising a plurality of photoelectric conversion elements, wherein the pixel array unit is included in the first substrate;
a second substrate vertically integrated with the first substrate such that the second surface of the first substrate faces the second substrate;
circuitry included in the second substrate, the circuitry configured to at least (a) generate first signals to control operation of the plurality of photoelectric conversion elements, or (b) process second signals corresponding to outputs of the plurality of photoelectric conversion elements;
a first via disposed at least partially within the first substrate and located outside the pixel array unit, the first via extending from the first surface of the first substrate and positioned to establish at least a portion of a first signal path between the first substrate and the second substrate for at least one of the first signals or at least one of the second signals; and
a second via disposed at least partially within the first substrate and located outside the pixel array unit, the second via extending from the first surface of the first substrate and positioned to establish at least a portion of a second signal path between the first substrate and the second substrate for at least one of the first signals or at least one of the second signals, wherein:
the pixel array unit has a first edge side and a second edge side,
the first via is located on the first edge side,
the second via is located on the second edge side, and
the first edge side is perpendicular to the second edge side.

US Pat. No. 10,396,114

METHOD OF FABRICATING LOW CTE INTERPOSER WITHOUT TSV STRUCTURE

Invensas Corporation, Sa...

1. A microelectronic assembly comprising:a dielectric region including a plurality of pads at a first surface, a plurality of contacts at a second surface opposite the first surface, and a back-end-of-line structure;
a plurality of electrically conductive elements coupled to the pads at the first surface of the dielectric region;
a first encapsulant extending above the first surface of the dielectric region, the first encapsulant filling spaces between the plurality of electrically conductive elements and having a surface overlying and facing away from the first surface of the dielectric region, wherein ends of the plurality of electrically conductive elements are at the surface of the first encapsulant; and
a plurality of microelectronic elements each having one or more contacts, wherein each of the contacts of the plurality of microelectronic elements are connected to one or more of the plurality of contacts at the second surface of the dielectric region through an electrically conductive material; and
a second encapsulant extending above the second surface of the dielectric region, the second encapsulant filling spaces between the plurality of microelectronic elements and the dielectric region.

US Pat. No. 10,396,113

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS INCLUDING A PHOTOELECTRIC CONVERSION UNIT DISPOSED BETWEEN ANOTHER PHOTOELECTRIC CONVERSION UNIT AND A PHOTOELECTRIC CONVERSION FILM

Sony Semiconductor Soluti...

1. An imaging device comprising:a substrate having a first side and a second side as a light-incident side, the substrate including:
a first photoelectric conversion unit, and
a second photoelectric conversion unit;
a wiring layer disposed adjacent to the first side of the substrate;
a photoelectric conversion film disposed over the second side of the substrate; and
portions of a conductive material disposed between the photoelectric conversion film and the substrate,
wherein
the conductive material is electrically connected to the substrate,
at least a portion of the second photoelectric conversion unit is disposed between the first photoelectric conversion unit and the photoelectric conversion film, and
the substrate is disposed between the photoelectric conversion film and the wiring layer.

US Pat. No. 10,396,112

IMAGING APPARATUS AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging system, comprising:an optical system; and
an imaging apparatus configured to receive incident light from the optical system and generate an image signal based on the incident light,
a processor configured to perform signal processing on the image signal,
the imaging apparatus including:
an interposer;
a mold disposed on the interposer, wherein the mold includes at least one protrusion in a cross sectional view;
an image sensor disposed on the interposer; and
a translucent member having a first side that receives the incident light and a second side that opposes the first side, wherein the second side is coupled to the mold such that the image sensor is spaced apart from the translucent member,
wherein the image sensor is disposed between the translucent member and the interposer, and
wherein at least a portion of the second side of the translucent member is in direct contact with at least a portion of the at least one protrusion.

US Pat. No. 10,396,110

REDUCTION OF TFT INSTABILITY IN DIGITAL X-RAY DETECTORS

Carestream Health, Inc., ...

1. A digital radiographic detector comprising:a two-dimensional array of imaging pixels, each imaging pixel comprising a photo-sensitive element and a switching element;
read-out circuits electrically coupled to the two-dimensional array of imaging pixels to generate a radiographic image by reading out image data from the two-dimensional array of imaging pixels; and
a housing enclosing the two-dimensional array of imaging pixels and the read-out circuits,
wherein each switching element in the two-dimensional array of imaging pixels comprises an active layer formed from indium-gallium-zinc oxide having a thickness less than about 7 nm.

US Pat. No. 10,396,109

LOCAL STORAGE DEVICE IN HIGH FLUX SEMICONDUCTOR RADIATION DETECTORS AND METHODS OF OPERATING THEREOF

Redlen Technologies, Inc....

1. A detector element circuit in a CT imaging system, comprising:a plurality of radiation sensors for detecting photons attenuated by an object;
a first electronic component configured to determine an energy of photons detected by the plurality of radiation sensors and generate digitized photon count data, wherein the digitized photon count data comprises a digitized count of detected photons in one or more energy bins;
a field programmable gate array (FPGA) configured to receive the digitized photon count data from the first electronic component and generate an output representing the digitized photon count data, wherein the FPGA comprises a FPGA clock configured to control a rate at which the FPGA receives the digitized photon count data from channels of the first electronic component and at which the FPGA outputs the output representing the digitized photon count data; and
a local memory storage configured to receive the output representing the digitized photon count data from the FPGA and comprising a local storage clock configured to control a rate at which the local memory storage generates buffered output data derived from the digitized photon count data,wherein:the FPGA clock and the local storage clock are set such that the FPGA is clocked at a first clock rate and the local storage element outputs the buffered output data at a second clock rate; and
the second clock rate and the first clock rate are selected to reduce bottlenecks or data transfer issues imposed by bandwidth limitations between the local memory storage and a computer of the CT imaging system that is configured to receive the buffered output data from the local memory storage.

US Pat. No. 10,396,108

SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT MANUFACTURING METHOD, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A solid-state imaging element comprising:a photodiode that performs photoelectric conversion on a basis of an amount of incident light;
a photoelectric conversion film that performs photoelectric conversion on the basis of the amount of incident light;
a diffusion layer that has a second polarity and stores an electric charge derived from the photoelectric conversion by the photoelectric conversion film, the second polarity being different from a first polarity of the photodiode; and
an impurity layer that includes impurities having the first polarity,
wherein the photodiode and the diffusion layer are disposed on a same substrate in parallel with each other, and
wherein the impurity layer is disposed below the diffusion layer.

US Pat. No. 10,396,107

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. An avalanche photodiode array comprising a plurality of avalanche photodiodes operating under Geiger mode, each avalanche photodiode of the avalanche photodiode array comprising:a first semiconductor layer having a first conductive type;
a second semiconductor layer disposed over at least a portion of the first semiconductor layer;
a third semiconductor layer disposed over at least a portion of the second semiconductor layer, wherein the third semiconductor has a second conductive type different from the first conductive type, wherein a pn junction is formed between one of
i) the second semiconductor layer and the first semiconductor layer or
ii) the second semiconductor layer and the third semiconductor layer, and
wherein the third semiconductor layer has an impurity concentration higher than an impurity concentration of the second semiconductor layer;
an insulator disposed over at least a portion of a light incident surface of the avalanche photodiode; and
a resistor disposed over a least a portion of the insulator and that extends along a space between adjacent avalanche photodiodes of the plurality of photodiodes, wherein the resistor is connected to the avalanche photodiode, and wherein the resistor includes a linear portion.

US Pat. No. 10,396,106

METHOD FOR PRODUCING A SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP

OSRAM OPTO SEMICONDUCTORS...

1. A method for producing a semiconductor chip, wherein, during a growth process for growing a first semiconductor layer, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer, such that a lateral variation of a material composition of the first semiconductor layer is produced, the lateral variation of the material composition comprising a gradient of a proportion of one or more constituents of the first semiconductor layer.

US Pat. No. 10,396,105

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display substrate comprising:a base substrate comprising a plurality of sub-pixels;
a first switching element disposed on the base substrate and electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction;
a color filter layer disposed on the first switching element and comprising a red color filter, a green color filter, a blue color filter and a white color filter alternately disposed on the plurality of sub-pixels, respectively;
a column spacer disposed on the color filter layer and comprising the same material as that of the white color filter;
an insulation layer disposed on the base substrate on which the color filter layer and the column spacer are disposed; and
a pixel electrode disposed on the insulation layer.

US Pat. No. 10,396,104

DISPLAY SUBSTRATE COMPRISING VERTICAL STORAGE CAPACITOR WITH INCREASED STORAGE CAPACITANCE, METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising a substrate, a plurality of device layers which are formed on the substrate, and an insulating layer which is formed between the device layers,wherein the display substrate further comprises a first electrode, a second electrode, and a vertical storage capacitor which is arranged in the insulating layer;
the vertical storage capacitor comprises a first plate and a second plate which are spaced apart, the first plate is connected with the first electrode, and the second plate is connected with the second electrode; and
the first plate and the second plate are perpendicular with or tilted with respect to the substrate,
wherein the display substrate comprises a plurality of pixel units, each of the pixel units comprises a display region and a peripheral region, and the vertical storage capacitor is arranged in the peripheral region.

US Pat. No. 10,396,103

THIN-FILM NEGATIVE DIFFERENTIAL RESISTANCE AND NEURONAL CIRCUIT

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming source and drain structures of a heterojunction field effect transistor (HJFET) on a first portion of a semiconductor material located on a surface of an insulating substrate, each of the source and drain structures including a hydrogenated silicon layer, a conducting layer, and a sacrificial layer;
forming a base structure of a heterojunction bipolar transistor (HBT) on a second portion of the semiconductor material located on the surface of the insulating substrate, the base structure including a hydrogenated silicon layer, a conducting layer, and a sacrificial layer;
depositing hydrogenated silicon resulting in formation of crystalline hydrogenated silicon adjacent the semiconductor material and formation of first amorphous hydrogenated silicon over the sacrificial layer of the source and drain structures of the HJFET and over the base structure of the HBT;
depositing second amorphous hydrogenated silicon over the sacrificial layer of the source and drain structures of the HJFET and over the base structure of the HBT;
depositing and patterning another conducting layer over the second amorphous hydrogenated silicon; and
etching the exposed second amorphous hydrogenated silicon and the first amorphous hydrogenated silicon to form a gate structure for the HJFET, and emitter and collector structures for the HBT,
wherein the HJFET and the HBT are integrated to create negative differential resistance by forming a lambda diode.

US Pat. No. 10,396,102

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a first scanning line and a second scanning line which extend over a display area and a non-display area;
first semiconductors crossing the first scanning line in the non-display area, the first semiconductors being a in number;
second semiconductors crossing the second scanning line in the non-display area, the second semiconductors being b in number;
third semiconductors crossing the first scanning line in the display area, the third semiconductors being c in number;
fourth semiconductors crossing the second scanning line in the display area, the fourth semiconductors being d in number; and
an insulating film disposed between the first and second semiconductors and the first and second scanning lines, wherein
the first scanning line has a first wiring length in the non-display area,
the second scanning line has a second wiring length different from the first scanning length in the non-display area,
the first scanning line has a third wiring length in the display area,
the second scanning line has a fourth wiring length different from the third wiring length in the display area,
a and b are integers greater than or equal to 2, and a is different from b,
c and d are integers greater than or equal to 2, and c is different from d, and
the first and second semiconductors are both entirely covered with the insulating film.

US Pat. No. 10,396,101

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A method for manufacturing a thin film transistor array panel, the method comprising:forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode;
forming a semiconductor member on the gate insulating layer;
depositing a doping barrier layer on the semiconductor member;
patterning the doping barrier layer to form a barrier pattern overlapping the gate electrode and exposing at least a part of the semiconductor member;
forming an interlayer insulating layer on the barrier pattern and the exposed semiconductor member;
patterning the interlayer insulating layer to form a first hole exposing the barrier pattern;
depositing a conductive layer on the interlayer insulating layer;
patterning the conductive layer to form a data conductor;
removing the barrier pattern; and
forming a passivation layer on the data conductor.

US Pat. No. 10,396,100

ARRAY SUBSTRATE, DISPLAY PANEL AND PIXEL PATCHING METHOD

Shenzhen China Star Optoe...

1. An array substrate, comprising a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors (TFTs), a plurality of pixel electrodes, and a plurality of conductive members, wherein the plurality of data lines and the plurality of gate lines are to cross each other to enclose a plurality of pixel regions, the plurality of conductive members are insulated from each other, and each of the conductive members of the plurality of conductive members corresponds to two adjacent pixel regions of the plurality of pixel regions;in each of the pixel regions of the plurality of pixel regions, a control terminal of a respective TFT is electrically connected with a corresponding gate line of the plurality of gate lines, an input terminal of the respective TFT is electrically connected with a corresponding data line of the plurality of data lines, and an output terminal of the respective TFT is electrically connected with a corresponding pixel electrode of the plurality of pixel electrodes; the output terminal comprises a body, and a first contact and a second contact which are connected with the body, the first contact and one conductive member of the plurality of conductive members extending into a corresponding pixel region of the plurality of pixel regions are disposed to overlap each other and are insulated from each other, the second contact and another conductive member of the plurality of conductive members extending into the corresponding pixel region of the plurality of pixel regions are disposed to overlap each other and are insulated from each other.

US Pat. No. 10,396,099

COPLANAR TYPE OXIDE THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. An oxide thin film transistor (TFT) comprising:a first substrate;
a light shielding layer provided on the first substrate;
a buffer provided on the light shielding layer;
a semiconductor layer provided on the buffer, the semiconductor layer including an oxide semiconductor material and comprising an active area, a first conductor adjacent to a first end of the active area, and a second conductor adjacent to a second end of the active area;
a gate insulation layer covering the semiconductor layer and the buffer;
a gate electrode provided on the gate insulation layer and overlapping a portion of the semiconductor layer; and
a passivation layer covering the gate electrode and the gate insulation layer,
wherein a resistance of the active area is different from a resistance of the first conductor and a resistance of the second conductor,
wherein a width of the active area is substantially the same as a width of the light shielding layer, and wherein the light shielding layer does not receive a gate pulse for turning on the oxide TFT, and
wherein the gate electrode is electrically connected to a gate line of a display device, and wherein the light shielding layer is electrically isolated from the gate line.

US Pat. No. 10,396,098

THIN FILM TRANSISTOR SUBSTRATE, AND DISPLAY PANEL AND DISPLAY DEVICE INCLUDING SAME

LG INNOTEK CO., LTD., Se...

1. A thin film transistor substrate comprising:a substrate;
a switching thin film transistor disposed on the substrate, the switching thin film transistor comprising a first channel layer including a nitride-based semiconductor layer, a first source electrode electrically connected to a first region of the first channel layer, a first drain electrode electrically connected to a second region of the first channel layer, a first gate electrode disposed on the first channel layer, and a first depletion forming layer disposed between the first channel layer and the first gate electrode; and
a driving thin film transistor disposed on the substrate, the driving thin film transistor comprising a second channel layer including a nitride-based semiconductor layer, a second source electrode electrically connected to a first region of the second channel layer, a second drain electrode electrically connected to a second region of the second channel layer, a second gate electrode disposed on the second channel layer, and a second depletion forming layer disposed between the second channel layer and the second gate electrode.

US Pat. No. 10,396,097

METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising steps of:forming a gate electrode layer over an insulating surface;
forming a gate insulating layer over the gate electrode layer;
forming an oxide semiconductor layer over the gate insulating layer;
forming a silicon oxide insulating layer over the oxide semiconductor layer;
forming a first opening and a second opening in the silicon oxide insulating layer so that the silicon oxide insulating layer covers and in contact with a periphery of the oxide semiconductor layer and a first region of the oxide semiconductor layer;
forming a source electrode layer in contact with the oxide semiconductor layer through the first opening; and
forming a drain electrode layer in contact with the oxide semiconductor layer through the second opening,
wherein the first region of the oxide semiconductor layer comprises a channel formation region,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the gate electrode layer is a portion of a gate wiring layer,
wherein the source electrode layer is a portion of a source wiring layer, and
wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate wiring layer, the gate insulating layer, the silicon oxide insulating layer, and the source wiring layer are stacked in this order.

US Pat. No. 10,396,096

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel, comprisinga substrate;
a gate line and a data line on the substrate;
a transistor on the substrate; and
a pixel electrode connected to the transistor,wherein the transistor includes:a gate electrode connected to the gate line,
a semiconductor layer on the gate electrode,
a source electrode on the semiconductor layer and connected to the data line, and
a drain electrode on the semiconductor layer and connected to the pixel electrode,
wherein the semiconductor layer includes:
a first portion overlapping the source electrode,
a second portion overlapping the drain electrode, and
a third portion between the first portion and the second portion,wherein:a thickness of the first portion is a minimum thickness of a portion where the source electrode and the semiconductor layer are overlapped,
a thickness of the second portion is a minimum thickness of a portion where the drain electrode and the semiconductor layer are overlapped,
a thickness of the third portion is a minimum thickness of a portion where the semiconductor is exposed between the source electrode and the drain electrode,
the thickness of the first portion, the thickness of the second portion, and the thickness of the third portion are significantly different from one another,
the thickness of the first portion is equal to a thickness of the semiconductor layer overlapping the data line, and
the thickness of the third portion is less than the thickness of each of the first portion and the second portion.

US Pat. No. 10,396,095

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:hole source patterns;
electron source patterns located between adjacent hole source patterns;
a stack structure over the hole source patterns and the electron source patterns; and
channel layers penetrating the stack structure,
wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

US Pat. No. 10,396,093

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Samsung Electronics Co., ...

1. A three-dimensional (3D) semiconductor memory device comprising:a substrate;
an electrode structure extending in a first direction on the substrate, the electrode structure including a plurality of cell electrodes vertically stacked on the substrate;
a lower string selection electrode and an upper string selection electrode sequentially stacked on the electrode structure;
a first vertical structure penetrating the lower string selection electrodes, the upper string selection electrodes, and the electrode structure;
a second vertical structure spaced apart from the upper string selection electrode such that the second vertical structure does not extend through the upper string selection electrode, the second vertical structure penetrating the lower string selection electrode and the electrode structure; and
a first bit line extending in a second direction different than the first direction, the first bit line intersecting the electrode structure, the first bit line connected in common to the first vertical structure and the second vertical structure.

US Pat. No. 10,396,092

VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A vertical memory device comprising:a substrate;
a gate stack structure on the substrate, the gate stack structure including conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction such that cell regions and inter-cell regions are alternately arranged in the vertical direction;
a channel structure on the substrate, the channel structure penetrating through the gate stack structure in the vertical direction; and
a charge trap structure between the gate stack structure and the channel structure, the charge trap structure and the conductive structures defining memory cells at the cell regions, the charge trap structure configured to selectively store charges, the charge trap structure including an anti-coupling structure in the inter-cell regions for reducing a coupling between the memory cells that neighbor each other in the vertical direction, wherein
the charge trap structure includes a block pattern, a tunnel insulation pattern, and a charge trap pattern,
the block pattern contacts the gate stack structure and extends in the vertical direction,
the tunnel insulation pattern has a cylinder shape,
the tunnel insulation pattern encloses that channel structure and contacts the channel structure,
the charge trap pattern includes a plurality of traps for storing the charges,
the charge trap pattern is between the block pattern and the tunnel insulation pattern,
the charge trap pattern includes a first pattern covering the block pattern and a second pattern covering the tunnel insulation pattern, and
the anti-coupling structure is enclosed by the first pattern and the second pattern in the inter-cell regions.

US Pat. No. 10,396,091

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a plurality of control gate electrodes stacked in a first direction above a substrate;
a first semiconductor layer that extends in the first direction and faces the plurality of control gate electrodes;
a gate insulating layer provided between the control gate electrode and the first semiconductor layer;
a first contact connected to an upper end of the first semiconductor layer;
a second semiconductor layer connected to a lower end of the first semiconductor layer and extending in a second direction intersecting the first direction;
a second contact connected to the second semiconductor layer at its lower end and extending in the first direction, an upper end of the second contact being further from the substrate than an upper surface of the second semiconductor layer; and
a first conductive layer provided above the second contact, an upper surface of the first conductive layer being nearer to the substrate than an upper end of the first contact and a lower surface of the first conductive layer being further from the substrate than a lower end of the first contact, wherein
in the second direction, an end of the first conductive layer closest to the first contact is positioned on a closer side to the first contact than an end of the second contact closest to the first contact, and
the first conductive layer and the second contact are not connected to each other.

US Pat. No. 10,396,090

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a cell stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked over the first region of the substrate;
a channel layer penetrating the cell stack structure;
a peripheral contact plug extending in parallel to the channel layer over the second region of the substrate; and
first dummy conductive rings disposed at the same levels as the conductive patterns, the first dummy conductive rings being spaced apart from the peripheral contact plug and surrounding the peripheral contact plug.

US Pat. No. 10,396,089

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a main surface;
first and second nonvolatile memory cells formed on the main surface of the semiconductor substrate;
the first nonvolatile memory cell including a first memory MISFET for storing data, having a first memory gate electrode, and a first select MISFET for selecting the first memory MISFET, having a first select gate electrode; and
the second nonvolatile memory cell including a second memory MISFET for storing data, having a second memory gate electrode, and a second select MISFET for selecting the second memory MISFET, having a second select gate electrode;
wherein the first and second select gate electrodes extend in a first direction so as to be disposed next to each other in a second direction substantially perpendicular to the first direction in a plan view,
wherein each of the first and second select gate electrodes has a first portion and a second portion;
wherein the second portion is wider than the first portion in the second direction;
wherein the first memory gate electrode extends in the first direction so as to be disposed along a sidewall of the first select gate electrode,
wherein the second memory gate electrode extends in the first direction so as to be disposed along a sidewall of the second select gate electrode,
wherein the first and second memory gate electrodes are disposed between the first select gate electrode and the second select gate electrode,
wherein the first memory gate electrode has a first contact portion extending in the second direction to provide an electrical contact to a first interconnect, and the first contact portion is disposed adjacent the second potion of the first select gate electrode,
wherein the second memory gate electrode has a second contact portion extending in the second direction to provide an electrical contact to a second interconnect, and the second contact portion is disposed adjacent the second potion of the second select gate electrode,
wherein the first contact portion is spaced apart from the second contact portion in the first direction in the plan view, and
wherein a first portion of the first contact portion and a second portion of the second contact portion are overlapped each other in the second direction in the plan view.

US Pat. No. 10,396,088

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

19. A three-dimensional semiconductor memory device, comprising:a stack structure including insulating layers and electrodes that are alternately stacked on a substrate;
a horizontal semiconductor pattern between the substrate and the stack structure;
vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and
a first common source plug and a second common source plug at opposite sides of the stack structure, respectively,
the horizontal semiconductor pattern including a first sidewall adjacent to the first common source plug and a second sidewall adjacent to the second common source plug, and
a first distance between the first sidewall and the first common source plug being different from a second distance between the second sidewall and the second common source plug.

US Pat. No. 10,396,087

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of electrode layers stacked with an insulating body interposed along a stacking direction;
at least two first insulating layers extending in a first direction crossing the stacking direction and being provided in the stacked body from an upper end of the stacked body to a lower end of the stacked body;
at least one second insulating layer extending in the first direction and being provided in the stacked body from the upper end of the stacked body to partway through the stacked body between one of the first insulating layers and another one of the first insulating layers; and
a plurality of semiconductor layers extending in the stacking direction and being provided in the stacked body between the second insulating layer and the one of the first insulating layers and between the second insulating layer and the other one of the first insulating layers,
the semiconductor layers having a first width in the first direction at a first position of the stacking direction, a second width in the first direction at a second position of the stacking direction, and a third width in the first direction at a third position of the stacking direction,
the second position being a position between the first position and the third position,
the second width being wider than the first width and the third width, and
the second insulating layer being provided in a region including a location of a maximum width of the semiconductor layers.

US Pat. No. 10,396,086

VERTICAL NON-VOLATILE MEMORY DEVICE HAVING CHANNEL-ACCOMODATING OPENING FORMED OF ETCH STOP REGION IN LOWER STACK LAYERS

Samsung Electronics Co., ...

1. A non-volatile memory device comprising:a substrate;
a lower insulating layer disposed on the substrate;
a multilayer structure of layers comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening extending vertically from the lower insulating layer, the opening including a first open portion and a second open portion,
wherein the first open portion extends through at least one of the layers of the multilayer structure from the lower insulating layer, and the second open portion is located on the first open portion and extends vertically upwardly from the first open portion in the multilayer structure, and
the opening has a first width at the first open portion and a second width at the second open portion, the second width being less than the first width;
a gate dielectric extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively; and
a channel structure disposed on the gate dielectric within the opening as extending along the inner surface and the lower surface defining the side and the bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the substrate,
wherein the first open portion has a first height,
the second open portion has a second height,
the first height with respect to the first width is less than or equal to 1, and
the second height with respect to the second width is equal to or greater than 1.

US Pat. No. 10,396,085

CIRCULAR PRINTED MEMORY DEVICE WITH ROTATIONAL DETECTION

Xerox Corporation, Norwa...

1. A circular printed memory device, comprising:a base substrate;
a plurality of bottom electrodes arranged in a circular pattern on the base substrate;
a ferroelectric layer on top of the plurality of bottom electrodes; and
a single top electrode on the ferroelectric layer, wherein the ferroelectric layer contacts each one of the plurality of bottom electrodes and the single top electrode.

US Pat. No. 10,396,084

SEMICONDUCTOR DEVICES INCLUDING SELF-ALIGNED ACTIVE REGIONS FOR PLANAR TRANSISTOR ARCHITECTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a first plurality of first mask features from a sacrificial material layer formed above a semiconductor layer of a semiconductor device, said first plurality of first mask features having one or more first lateral spacings of a first value along a width direction, said one or more first lateral spacings being defined by a lithography process;
forming a second plurality of second mask features associated with said first plurality of first mask features by forming a mask material directly adjacent to said first plurality of first mask features, said second plurality of second mask features having one or more second lateral spacings of a second value, said second value being less than said first value;
modifying at least one of said one or more second lateral spacings of said second plurality of second mask features by forming a spacer material directly adjacent to and between associated second mask features; and
forming a plurality of active regions from said semiconductor layer by using said second plurality of second mask features including said modified at least one second lateral spacing, each of said plurality of active regions representing a semiconductor base layer for forming a planar field effect transistor.

US Pat. No. 10,396,083

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a substrate including an active region that extends in a first direction;
a bit line structure running across the active region in a second direction different from the first direction;
a first spacer on a first sidewall of the bit line structure, the first spacer including:
a first sub-spacer on the first sidewall of the bit line structure;
a second sub-spacer spaced apart from the first sub-spacer;
a first air gap between the first sub-spacer and the second sub-spacer; and
a third sub-spacer covering a portion of the first air gap; and
a storage node structure including a storage node contact contacting the active region and a landing pad on the storage node contact, and both the storage node contact and the landing pad covering the first spacer,
wherein the third sub-spacer is disposed on the second sub-spacer at a first vertical point vertically distant from the substrate by a first height, and is disposed on a sidewall of the first sub-spacer at a second vertical point vertically distant from the substrate by a second height, and the second height is higher than the first height; and
wherein a lower surface of the third sub-spacer is on an upper surface of the second sub-spacer in a direction perpendicular to the substrate.

US Pat. No. 10,396,082

MEMORY CELLS HAVING A CONTROLLED-CONDUCTIVITY REGION

Micron Technology, Inc., ...

1. A memory cell, comprising:a transistor having a channel region between a first source/drain region and a second source/drain region; the transistor having a transistor gate extending along the channel region;
a controlled-conductivity region adjacent the first source/drain region, the controlled-conductivity region being along a surface of the transistor gate and separated from the surface of the transistor gate by a dielectric material, the controlled-conductivity region being gated by said transistor gate; the controlled-conductivity region having a low-conductivity mode and a high-conductivity mode; the high-conductivity mode having a conductivity at least 106 greater than a conductivity of the low-conductivity mode; the channel region comprising a first material having a first bandgap, and the controlled-conductivity region comprising a second material having a second bandgap which is greater than the first bandgap; an insulative material over an upper surface of the transistor gate, and a conductive region over the controlled-conductivity region and along the insulative material;
a charge-storage device electrically coupled to the first source/drain region through the controlled-conductivity region; and
a bitline electrically coupled to the second source/drain region.

US Pat. No. 10,396,081

SEMICONDUCTOR DEVICE, ANTENNA SWITCH CIRCUIT, AND WIRELESS COMMUNICATION APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a compound semiconductor upper barrier layer between an insulating film and a compound semiconductor channel layer; and
a compound semiconductor first cap layer between a first electrode and a first low resistance region of the upper barrier layer,
wherein the first electrode extends through the insulating film to the first cap layer, and
wherein the first cap layer is in direct physical contact with the first low resistance region, the first cap layer is of a first electrically conductive type and the first low resistance region is of a second electrically conductive type.

US Pat. No. 10,396,080

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising a semiconductor substrate including a principal surface, whereinthe semiconductor substrate comprises:
a first shallow well of a first conductive type, a second shallow well of a second conductive type, a third shallow well of the first conductive type, and a fourth shallow well of the second conductive type formed in a part of the semiconductor substrate on a side of a principal surface in such a way that they are in regions different from one another when the semiconductor substrate is seen from the principal surface;
a deep well of the second conductive type formed in a region including the first shallow well and the second shallow well, which is a region other than the region in which the third shallow well and the fourth shallow well are formed, the deep well of the second conductive type being formed in a part deeper than the first shallow well and the second shallow well in a depth direction from the principal surface; and
a base material of the first conductive type formed in a region including the third shallow well, the fourth shallow well, and the deep well, the base material of the first conductive type being formed in a part deeper than the third shallow well, the fourth shallow well, and the deep well in the depth direction from the principal surface, the semiconductor device further comprises:
a first transistor pair comprising a field effect transistor of the second conductive type in which a diffusion layer of the second conductive type is formed in a part of the first shallow well on the side of the principal surface and the field effect transistor of the first conductive type in which the diffusion layer of the first conductive type is formed in a part of the second shallow well on the side of the principal surface;
a second transistor pair comprising the field effect transistor of the second conductive type in which the diffusion layer of the second conductive type is formed in a part of the third shallow well on the side of the principal surface and the field effect transistor of the first conductive type in which the diffusion layer of the first conductive type is formed in a part of the fourth shallow well on the side of the principal surface; and
a wire between transistor pairs configured to connect the first transistor pair and the second transistor pair, and
the second shallow well is formed in such a way as to surround a peripheral edge of the region of the first shallow well.

US Pat. No. 10,396,079

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion, the first fin of an NMOS device;
a second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion, the second fin of a PMOS device;
a first dielectric layer comprising silicon and oxygen, the first dielectric layer directly on sidewalls of the lower fin portion of the first fin;
a second dielectric layer comprising silicon and oxygen, the second dielectric layer directly on sidewalls of the lower fin portion of the second fin;
an insulating layer comprising nitrogen, the insulating layer over the first dielectric layer and over the second dielectric layer, and the insulating layer continuous over the first dielectric layer and the second dielectric layer;
a dielectric fill material directly on the insulating layer, wherein the dielectric fill material comprises silicon and oxygen;
a first gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over the dielectric fill material; and
a second gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, the second gate electrode over the dielectric fill material.

US Pat. No. 10,396,078

INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit structure comprising:a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin;
a first source/drain epitaxial region substantially surrounding at least a portion of the first fin;
a spacer substantially surrounding the first source/drain epitaxial region, the spacer including a void in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and
a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

US Pat. No. 10,396,077

PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS

International Business Ma...

1. A method for forming a plurality of semiconductor devices, comprising:forming a first channel region on a first region of a semiconductor layer, the semiconductor layer including a first semiconductor material;
forming a second channel region on a second region of the semiconductor layer by etching a trench in the second region, the trench defined on sides and a bottom by the first semiconductor material, and filling the trench with a second semiconductor material different from the first semiconductor material; and
forming a gate on a nitrogen-containing layer in one or more of the first and second regions.

US Pat. No. 10,396,076

STRUCTURE AND METHOD FOR MULTIPLE THRESHOLD VOLTAGE DEFINITION IN ADVANCED CMOS DEVICE TECHNOLOGY

International Business Ma...

1. A method of forming a semiconductor structure having multiple defined threshold voltages, the method comprising:forming a plurality of field-effect transistor (FET) devices in the semiconductor structure, each of the FET devices comprising a channel and a gate stack formed of one of at least two different work function metals, the gate stack being formed proximate the channel;
forming each gate stack in each of at least a subset of the plurality of FET devices by using a single metal patterning level and two different work function metals in a given region of a same conductivity type in the semiconductor structure; and
varying a valence band offset and a conduction band offset of the channel in each of the at least a subset of the FET devices in the given region of the same conductivity type in the semiconductor structure by controlling a percentage of one or more compositions of a material forming the channel;
wherein a threshold voltage of each of the plurality of FET devices is configured as a function of a type of work function metal forming the gate stack of the corresponding FET device and the percentage of one or more compositions of the material forming the channel.

US Pat. No. 10,396,075

VERY NARROW ASPECT RATIO TRAPPING TRENCH STRUCTURE WITH SMOOTH TRENCH SIDEWALLS

International Business Ma...

1. A semiconductor structure comprising:a plurality of epitaxial semiconductor fins located permanently on, and in direct physical contact with, a semiconductor material portion of a substrate, wherein each epitaxial semiconductor fin is inverted T-shaped having a horizontal bottom portion and a vertically extending upper portion, wherein the horizontal bottom portion is wider than the vertically extending upper portion;
a bottom spacer laterally surrounding, and directly contacting, a sidewall surface of the horizontal bottom portion of each epitaxial semiconductor fin, wherein the bottommost spacer has a bottommost surface directly contacting a topmost surface of the semiconductor material portion of the substrate; and
a semiconductor oxide insulator structure located between each pair of neighboring epitaxial semiconductor fins and neighboring bottom spacers and having a topmost surface located below a topmost surface of each epitaxial semiconductor fin, wherein the semiconductor oxide insulator structure has a horizontal bottom surface that comprises a first portion directly contacting an entirety of a topmost surface of the bottom spacer and a second portion, adjacent to the first portion, directly contacting a portion of the topmost surface of the horizontal bottom portion of each epitaxial semiconductor fin, and wherein the bottom spacer has a width that is less than a width of the semiconductor oxide insulator structure.

US Pat. No. 10,396,074

POWER SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL REGIONS

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and to a second load terminal structure and configured to conduct a load current during a conducting state of the power semiconductor device and to block a load current during a blocking state of the power semiconductor device;
a first cell and a second cell, each cell being configured for controlling the load current and each cell being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; and
a second mesa included in the second cell, the second mesa including: a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region,
wherein each of the first mesa and the second mesa has a total extension of less than 100 nm in a direction perpendicular of the load current within the respective mesa,
wherein the first and second cells are configured to fully deplete the first and second channel regions of mobile charge carriers of the second conductivity type in the conducting state,
wherein the first cell is configured to induce a current path for mobile charge carriers of the first conductivity type in the first channel region in the conducting state and no current path for mobile charge carriers of the first conductivity type in the blocking state,
wherein the power semiconductor device is configured to concurrently induce an accumulation channel for charge carriers of the second conductivity type in the second channel region and a current path for charge carriers of the first conductivity type in the first channel region in a switching state of the power semiconductor device.

US Pat. No. 10,396,073

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first gate structure in a substrate;
a second gate structure in the substrate and adjacent to the first gate structure;
a shallow trench isolation (STI) under the first gate structure, wherein the STI comprises a bottom portion and a top portion directly under the first gate structure, two sidewalls of the top portion are aligned with two sidewalls of the first gate structure, and a topmost surface of the top portion is even with or higher than a bottom surface of the second gate structure and lower than a top surface of the substrate; and
a mask on each of the first gate structure and the second gate structure, wherein a top surface of the mask is even with the top surface of the substrate.

US Pat. No. 10,396,072

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

9. A semiconductor device having a first region and a second region surrounding the first region, comprising:a first electrode;
a first semiconductor layer of a first conductivity type on the first electrode;
a second semiconductor layer of the first conductivity type on the first semiconductor layer;
a second electrode on the second semiconductor layer;
at least one first PIN diode comprising a portion of the first and second semiconductor layers located in the first region; and
at least one second PIN diode comprising a portion of the first and second semiconductor layers located in the second region, wherein
the at least one second PIN diode surrounds the first region,
the at least one PIN diode further comprises:
a third semiconductor layer of a second conductivity type on the second semiconductor layer;
a fourth semiconductor layer of the second conductivity type on the third semiconductor layer; and
a fifth semiconductor layer of the first conductivity type extending inwardly of the second semiconductor layer from the third semiconductor layer, and
the fifth semiconductor layer surrounds at least a portion of the second semiconductor layer contacting the third semiconductor layer, wherein the first conductivity type is different from the second conductivity type.

US Pat. No. 10,396,071

SEMICONDUCTOR DEVICE HAVING A SENSE DIODE PORTION

FUJI ELECTRIC CO., LTD., ...

8. The semiconductor device according to claim 1, further comprising:an edge termination structure portion that is provided surrounding the main transistor portion and the main diode portion on the upper surface of the semiconductor substrate, wherein
the sense diode portion is arranged on an outer side of the edge termination structure portion on the upper surface of the semiconductor substrate.

US Pat. No. 10,396,070

FIN-SHAPED FIELD EFFECT TRANSISTOR AND CAPACITOR STRUCTURES

AVAGO TECHNOLOGIES INTERN...

1. A semiconductor device, comprising:a first semiconductor substrate;
a second semiconductor substrate located within a first region of the first semiconductor substrate, the second semiconductor substrate having a doping concentration different from that of the first semiconductor substrate;
a first fin structure formed on the second semiconductor substrate;
a first insulation layer disposed on the first fin structure and in contact with the second semiconductor substrate, the first insulation layer comprising one or more dielectric layers;
an isolation layer disposed adjacent to sidewalls of the first insulation layer, the isolation layer being in contact with the second semiconductor substrate and the first semiconductor substrate; and
a first conductor structure disposed on the first insulation layer and within the sidewalls of the first insulation layer, the one or more dielectric layers of the first insulation layer being in direct contact with the first conductor structure and a top surface of the second semiconductor substrate.

US Pat. No. 10,396,068

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

ALi Corporation, Hsinchu...

1. An electrostatic discharge protection device, comprising:an electrostatic discharge protection unit, coupled between a signal input terminal and a system voltage terminal, wherein when a voltage level of a signal received by the signal input terminal reaches an electrostatic discharge protection level, the electrostatic discharge protection unit transmits the signal from the signal input terminal to the system voltage terminal; and
a control circuit, coupled to a control terminal of the electrostatic discharge protection unit, and controlling a conduction state between the signal input terminal and the system voltage terminal through the electrostatic discharge protection unit, wherein the control circuit comprises:
a first voltage providing circuit comprising a first transistor and a first impedance providing circuit, wherein a first terminal, a second terminal and a control terminal of the first transistor are respectively coupled to the first impedance providing circuit, the signal input terminal and the control terminal of the electrostatic discharge protection unit, wherein a first terminal of the first impedance providing circuit is coupled to the system voltage terminal and a second terminal of the first impedance providing circuit is coupled to the first terminal of the first transistor and the control terminal of the electrostatic discharge protection unit; and
a second voltage providing circuit comprising a second transistor and a second impedance providing circuit, wherein a first terminal, a second terminal and a control terminal of the second transistor are respectively coupled to the system voltage terminal, a first terminal of the second impedance providing circuit and the control terminal of the electrostatic discharge protection unit, wherein the first terminal of the second impedance providing circuit is further coupled to the control terminal of the electrostatic discharge protection unit and a second terminal of the second impedance providing circuit is coupled to the signal input terminal,
wherein the control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the electrostatic discharge protection unit, and to make the electrostatic discharge protection unit not transmit the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the electrostatic discharge protection level.

US Pat. No. 10,396,067

SEMICONDUCTOR DEVICE HAVING A LOAD CURRENT COMPONENT AND A SENSOR COMPONENT

Infineon Technologies AG,...

1. A semiconductor device comprising a semiconductor body having a first surface and a second surface opposite to the first surface, the semiconductor body comprising:a load current component comprising a load current transistor area; and
a sensor component comprising a sensor transistor area,
wherein the load current transistor area and the sensor transistor area share a same transistor unit construction,
wherein the load current transistor area comprises first and second transistor area parts and the sensor transistor area comprises a third transistor area part,
wherein the first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part,
wherein the second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.

US Pat. No. 10,396,066

ELECTRO-STATIC DISCHARGE TRANSISTOR ARRAY APPARATUS

SEMICONDUCTOR MFG. INTL. ...

1. An electro-static discharge (ESD) transistor array apparatus, comprising:a semiconductor substrate, the semiconductor substrate comprising:
a semiconductor layer,
a doped region on the semiconductor layer, and
a substrate contact region,
wherein the doped region and the substrate contact region are isolated, and the substrate contact region comprises at least a first contact region part separately disposed on two sides of the doped region;
multiple gates arranged in parallel on the doped region, where a direction of extension of the multiple gates is in parallel with a direction of extension of the first contact region part; and
a dissipation layer contact member disposed on each gate of the multiple gates along the direction of extension of the gate, wherein a density of the dissipation layer contact member decreases with a decrease in a distance from the gate on which the dissipation layer contact member is located to the first contact region part on a corresponding side.

US Pat. No. 10,396,065

SEMICONDUCTOR DEVICE HAVING A TEMPERATURE-DETECTING DIODE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:an insulated gate semiconductor element that makes a current flow in a thickness direction of a semiconductor substrate;
a temperature detecting diode that detects a temperature of the insulated gate semiconductor element and is provided in an active region of the insulated gate semiconductor element;
an anode metal wiring line that is provided on a first main surface side of the semiconductor substrate and is connected to an anode of the temperature detecting diode;
a cathode metal wiring line that is provided on the first main surface side of the semiconductor substrate and is connected to a cathode of the temperature detecting diode, the anode metal wiring line and the cathode metal wiring line each being not connected to the insulated gate semiconductor element;
a first semiconductor region of a second conductivity type, formed on the semiconductor substrate;
a first insulating film that is formed on the first semiconductor region between the anode and cathode metal wiring lines and the semiconductor substrate;
a first semiconductor layer that is formed directly between the first insulating film and the anode metal wiring line and spaced apart from the temperature detecting diode, and is connected to the anode metal wiring line;
a second semiconductor layer that is formed directly between the first insulating film and the cathode metal wiring line and spaced apart from the temperature detecting diode, and is connected to the cathode metal wiring line;
a first capacitor that has the first insulating film, as a first capacitive component region, between the first semiconductor layer and the semiconductor substrate;
a second capacitor that has the first insulating film, as a second capacitive component region, between the second semiconductor layer and the semiconductor substrate; and an interlayer insulating film disposed directly on the first semiconductor region in a gap in the first insulating film.

US Pat. No. 10,396,064

LAYOUT PATTERN FOR SRAM AND MANUFACTURING METHODS THEREOF

UNITED MICROELECTRONICS C...

1. A static random access memory (SRAM), comprising:a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern comprising:
a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second pull-up transistor (PL2) and a second pull-down transistor (PD2);
a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the second access transistor has a second gate length, and the first gate length is different from the second gate length; and
a first read port transistor (RPD) and a second read port transistor (RPG) connected to each other, wherein the first read port transistor is connected to the latch circuit, and a gate of the first read port transistor is electrically connected to a gate of the first pull-down transistor, wherein the gate of the first pull-down transistor (PD1) directly contacts the gate of the first read port transistor (RPD), and wherein the gate of the first pull-down transistor (PD1) and the gate of the first read port transistor (RPD) are arranged along a same symmetry axis.

US Pat. No. 10,396,063

CIRCUIT WITH COMBINED CELLS AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming an integrated circuit, comprising:providing a first design layout having a first cell layout and a second cell layout using electronic design automation software;
the step of providing the first cell layout comprising forming:
a first higher power line and a first lower power line;
a first output pin;
at least one first up transistor formed to electrically couple the first output pin to the first higher power line; and
at least one first down transistor formed to electrically couple the first output pin to the first lower power line;
the step of providing the second cell layout comprising forming:
a second higher power line and a second lower power line;
a second output pin;
at least one second up transistor formed to electrically couple the second output pin to the second higher power line;
at least one second down transistor formed to electrically couple the second output pin to the second lower power line;
the at least one second up transistor and the at least one second down transistor comprising a first gate line;
generating a third cell layout according to the first cell layout and the second cell layout using the electronic design automation software, comprising:
non-selectively electrically coupling the first gate line to the first output pin to form a first node; and
generating a second design layout by replacing the first cell layout and the second cell layout in the first design layout with the third cell layout using the electronic design automation software; and
generating a netlist for fabricating the integrated circuit according to the second design layout using the electronic design automation software to minimize at least one of routing resources, wire lengths, via counts and layout area required for fabricating the integrated circuit;
wherein the step of generating of the third cell layout further comprises:
combining a first source or drain region of one of the at least one first up transistor and the at least one first down transistor with a second source or drain region of one of the at least one second up transistor and the at least one second down transistor of a same conductivity type as the first source or drain region,
during the combining, the first higher power line and the second higher power line being combined into a higher power line and the first lower power line and second lower power line being combined into a lower power line; and
forming a second node by forming: a first conductive line overlapped with one of the first source or drain region and the second source or drain region and non-selectively electrically coupled to the one of the first source or drain region and the second source or drain region and to one of the higher power line and lower power line corresponding to the one of the first source or drain region and the second source or drain region, and a second conductive line in substantially the same direction as the first conductive line and non-selectively electrically coupled to the one of the higher power line and the lower power line; and
forming a plurality of gate finger lines non-selectively electrically coupled to each other, one of the plurality of gate finger lines being adjacent to the one of the first source or drain region and the second source or drain region so as to enable forming of the second node; and
wherein the first source or drain region and the second source or drain region are combined through joining, the first source or drain region and the second source or drain region are joined to opposite sides of a second gate line, and the second conductive line overlaps with the other of the first source or drain region and the second source or drain region.

US Pat. No. 10,396,062

MICRO LIGHT EMITTING DIODE DISPLAY PANEL

PlayNitride Inc., Tainan...

1. A micro light emitting diode display panel, comprising:a substrate including a plurality of pixel regions arranged in a display area;
a plurality of control elements, disposed on the substrate and in the display area; and
a plurality of light emitting units, disposed on the substrate and in the display area, wherein each of the light emitting units is electrically connected to one of the control elements, and each of the light emitting units comprises a plurality of micro light emitting diodes, wherein the plurality of micro light emitting diodes at least have a red micro light emitting diode, a green micro light emitting diode and a blue micro light emitting diode, and a shortest distance between the green micro light emitting diode and the one of the control elements is less than a shortest distance between the blue micro light emitting diode and the one of the control elements,
wherein the pixel regions comprise a plurality of first pixel regions and a plurality of second pixel regions, the first pixel regions are sequentially arranged in a first direction, the second pixel regions are sequentially arranged in the first direction, and the first pixel regions and the second pixel regions are alternately arranged in a second direction perpendicular to the first direction, wherein an arrangement between one of the control elements and one of the light emitting units in each of the first pixel regions is different from an arrangement between one of the control elements and one of the light emitting units in each of the second pixel regions.

US Pat. No. 10,396,061

TRANSPARENT ELECTRONICS FOR INVISIBLE SMART DUST APPLICATIONS

International Business Ma...

1. A transparent semiconductor nanochip comprising:a transparent substrate;
a transparent semiconductor material layer located on a surface of the transparent substrate and comprising one or more transparent semiconductor devices disposed thereon; and
a transparent back-end-of-the-line (BEOL) structure disposed entirely above the transparent semiconductor material layer and the one or more transparent semiconductor devices, wherein the transparent BEOL structure comprises at least one interconnect level containing at least one electrically conductive and transparent metallic structure embedded in a transparent interconnect dielectric material layer, and wherein the transparent semiconductor nanochip is invisible to visible light and cannot be seen by a human eye.

US Pat. No. 10,396,060

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:an interconnect layer;
an electrical element, a direction from the interconnect layer toward the electrical element being a first direction;
an optical element, a direction from the interconnect layer toward the optical element being aligned with the first direction, a second direction from the electrical element toward the optical element crossing the first direction; and
a resin portion including a first partial region, the first partial region being between the electrical element and the optical element,
at least a portion of the optical element not overlapping the resin portion in the first direction,
the first partial region having a first resin portion surface and a second resin portion surface, the second resin portion surface being opposite to the first resin portion surface and opposing the interconnect layer,
the optical element having a first optical element surface and a second optical element surface, the second optical element surface being opposite to the first optical element surface and opposing the interconnect layer, the optical element including at least one of a light emitter or a light receiver, the at least one of the light emitter or the light receiver being provided at the second optical element surface,
a distance along the first direction between the interconnect layer and the first resin portion surface being longer than a distance along the first direction between the interconnect layer and the first optical element surface,
wherein the optical element includes:
an antireflective layer; and
a transparent layer provided between the antireflective layer and the interconnect layer, and
a refractive index of the antireflective layer is greater than 1 and lower than a refractive index of the transparent layer.

US Pat. No. 10,396,059

MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A stacked system of microelectronic devices, comprising:a first microelectronic device having a first die, a first bottom side, and first metal leads coupled to the first bottom side;
a second microelectronic device having a second die, a top side, a lateral side, a second bottom side, a second bottom side bond-site, and second metal leads coupled to the second bottom side, the second leads including a lateral portion that laterally projects away from the lateral side, a tiered portion that laterally projects towards the lateral side, and an angled portion between the lateral portion and the tiered portion that positions the tiered portion above the lateral portion;
metal solder bumps between individual first leads and individual tiered portions of the second leads;
a support substrate adjacent to and spaced apart from the second bottom side, the support substrate having a substrate bond-site; and
a substrate connector attached to the substrate bond-site and to the second bottom side.

US Pat. No. 10,396,057

HALF-BRIDGE POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME

NISSAN ARC, LTD., Kanaga...

1. A switching control half-bridge power semiconductor module comprising:an insulating wiring substrate comprising:
a single insulating plate, and
a positive electrode wiring conductor, a bridge wiring conductor, and multiple negative electrode wiring conductors disposed on or above the insulating plate while being electrically isolated from one another;
at least one high side power semiconductor device having a rear surface electrode bonded onto the positive electrode wiring conductor;
at least one low side power semiconductor device having a rear surface electrode bonded onto the bridge wiring conductor;
a stand-up multiple-legged bridge terminal connected to the bridge wiring conductor;
a stand-up multiple-legged high side terminal disposed between the high side power semiconductor device and the stand-up multiple-legged bridge terminal, and connected to the positive electrode wiring conductor;
a stand-up multiple-legged low side terminal disposed between the stand-up multiple-legged bridge terminal and the low side power semiconductor device, and connected to the negative electrode wiring conductors;
a high side connector connecting a front surface main electrode of the high side power semiconductor device to the stand-up multiple-legged bridge terminal; and
a low side connector connecting a front surface main electrode of the low side power semiconductor device to the stand-up multiple-legged low side terminal.

US Pat. No. 10,396,055

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES

Intel Corporation, Santa...

1. A method comprising:forming a stack comprising multiple integrated circuit (IC) dies including a first IC die and a second IC die;
coupling to the first IC die a first end of a first wire;
anchoring a second end of the first wire to the stack, wherein the first wire comprises the second end and a first portion including the first end;
while the first end is coupled to the first IC die and the second end is anchored to the stack, disposing a package material around the multiple IC dies and the first portion;
after disposing the package material around the multiple IC die, separating the second end from the first portion, including exposing another end of the first portion at a first surface of the package material; and
coupling the first IC die to the second IC die, including forming a redistribution layer on the first surface, wherein the redistribution layer is coupled to the second IC die and to the other end of the first portion.

US Pat. No. 10,396,054

BONDING ALIGNMENT TOOL

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus, comprising:a bonding system configured to bond at least two wafers, the bonding system having a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers;
sensors configured to detect data related to a flag-out condition of the flags of the plurality of flags, wherein the data comprises one or more time durations for removing the flags of the plurality of flags; and
at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers, wherein
a first wafer of the at least two wafers comprises at least two alignment markings, and the bonding system is configured to align the first wafer of the at least wafers with a second wafer of the at least two wafers based on the at least two alignment markings, and wherein the at least one processor is configured to:
calculate a velocity by which each alignment marker of the at least two alignment markers is removed,
generate an indicator of misalignment of the at least two wafers based on the calculated velocity, and
determine the at least two wafers are misaligned based on a difference between the velocities by which the each alignment marker of the at least two alignment markers is removed.

US Pat. No. 10,396,053

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

General Electric Company,...

1. A reconfigured semiconductor logic device comprising:a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon; and
a redistribution layer comprising:
an insulating layer disposed on the active surface of the semiconductor logic device; and
a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer, wherein the plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer, and wherein the plurality of discrete terminal pads are larger than the plurality of I/O pads;
wherein the plurality of discrete terminal pads comprise:
a plurality of signal terminal pads electrically coupled to signal I/O pads of the plurality of I/O pads;
a plurality of power terminal pads electrically coupled to power I/O pads of the plurality of I/O pads; and
a plurality of ground terminal pads electrically coupled to ground I/O pads of the plurality of I/O pads.