US Pat. No. 10,366,899

METHOD OF DETECTING A CONDITION

SPTS Technologies Limited...

1. A control method of a plasma dicing process, comprising the steps of:providing a non-metallic substrate having a plurality of designated dicing lanes;
plasma etching through the substrate along the dicing lanes;
during the plasma etching, monitoring emission of infrared radiation by at least a portion of the dicing lanes of the substrate to detect an increase in infrared radiation due to emission of infrared radiation by the dicing lanes; and
determining, prior to singulation of the substrate along the dicing lanes, that a condition associated with a final phase of the plasma dicing process exists when the increase in the infrared radiation has been detected.

US Pat. No. 10,366,898

TECHNIQUES AND SYSTEMS FOR CONTINUOUS-FLOW PLASMA ENHANCED ATOMIC LAYER DEPOSITION (PEALD)

Nano-Master, Inc., Austi...

1. An atomic layer deposition (ALD) system comprising:(a) a cylindrical chamber comprising an upper portion and a lower portion such that said upper portion and said lower portion can be closed to obtain a sealed state of said chamber;
(b) said upper portion comprising a planar inductively coupled plasma (ICP) source laterally affixed at its distal end from said lower portion;
(c) said lower portion containing a platen onto which a substrate is placed, said platen and said substrate heated by a platen heater to a desired temperature;
(d) said substrate isolated from said ICP source in said chamber by a grounded metal plate laterally affixed above said substrate and a ceramic plate laterally affixed below said grounded metal plate but above said substrate, said grounded metal plate and said ceramic plate having a first plurality of holes and a second plurality of holes respectively such that each of said first plurality of holes is aligned with a corresponding hole of said second plurality of holes, and each of said second plurality of holes has a diameter less than two Debye lengths of a plasma, said ICP source configured to generate from a gas A said plasma above said grounded plate and said grounded metal plate configured to terminate said plasma;
(e) said ICP source configured to receive a continuous supply of said gas A;
(f) said lower portion configured to contain a gas B passed as a pulse from below said ceramic plate; and
(g) each of said gas A and said gas B comprising one or more individual chemical species;wherein a uniform atomically sized film is produced on said substrate by a self-limiting reaction of excited neutrals of said gas A, said gas B and said substrate.

US Pat. No. 10,366,897

DEVICES WITH MULTIPLE THRESHOLD VOLTAGES FORMED ON A SINGLE WAFER USING STRAIN IN THE HIGH-K LAYER

International Business Ma...

1. A method for adjusting a threshold voltage, comprising:controlling an amount of strain in a silicon nitride liner deposited over a transistor to diffuse work function (WF) modulating species from the silicon nitride liner into a gate dielectric in a channel region of the transistor, the amount of strain in the liner being controlled by adjusting deposited liner thickness.

US Pat. No. 10,366,896

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a gate electrode on a substrate, wherein the gate electrode comprises a metal gate;
a gate dielectric layer between the gate electrode and the substrate, wherein the gate dielectric layer comprises a top portion and a bottom portion and a width of the top portion is less than a width of the bottom portion, and the gate dielectric layer does not extend directly over the source/drain regions respectively;
a high-k dielectric layer between and directly contacts the gate dielectric layer and the gate electrode, wherein a width of the high-k dielectric layer is equal to the width of the top portion and less than the width of the bottom portion;
a first spacer on the bottom portion and directly contacting the high-k dielectric layer, the top portion, and the bottom portion; and
a second spacer adjacent to the first spacer, wherein a bottom surface of the second spacer is even with a bottom surface of the bottom portion, a large portion of the first spacer and the second spacer are substantially parallel and vertically arranged, and the first spacer and the second spacer end at tops thereof at substantially same point.

US Pat. No. 10,366,895

METHODS FOR FORMING A SEMICONDUCTOR DEVICE USING TILTED REACTIVE ION BEAM

Infineon Technologies AG,...

1. A method for forming a semiconductor device, the method comprising:forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate;
forming of a first insulating layer inside the trench;
irradiating the first insulating layer with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the first insulating layer is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the first insulating layer is masked by an edge of the trench; and
forming a second insulating layer inside the trench after the irradiation of the first insulating layer to form a combined insulating layer with vertically varying thickness.

US Pat. No. 10,366,894

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM

KOKUSAI ELECTRIC CORPORAT...

1. A method for manufacturing a semiconductor device, comprising:forming a metal carbide film including a first metal element and a second metal element on a substrate, by time-divisionally performing:
forming a first film containing the first metal element and carbon and not containing the second metal element by time-divisionally performing supplying a first precursor gas containing the first metal element and not containing carbon to the substrate to form a first metal-containing layer and supplying a reaction gas containing carbon and not containing a metal element to the first metal-containing layer; and
forming a second film containing the second metal element and carbon and not containing the first metal element on the first film by time-divisionally performing supplying a second precursor gas containing the second metal element differing from the first metal element and not containing carbon to the first film to form a second metal-containing layer on the first film and supplying the reaction gas to the second metal-containing layer,
wherein the first precursor gas and the second precursor gas are halides.

US Pat. No. 10,366,893

PROCESS FOR MAKING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a silicon carbide semiconductor device, comprising:forming a gate insulating film on a silicon carbide substrate;
forming a polysilicon film on an entire surface of the gate insulating film;
ion implanting one or more dopants selected from a group consisting of N, P, As, Sb, B, Al, and Ar into the polysilicon film that is on the entire surface of the gate insulating film;
before conducting any thermal process on the polysilicon film that has been ion implanted, removing a thickness of 50 nm to 300 nm uniformly from a surface layer of the polysilicon film that has been ion implanted;
selectively forming a mask on the polysilicon film from which the thickness of 50 nm to 300 nm has been removed uniformly;
forming a polysilicon electrode by removing an exposed portion of the polysilicon film that is exposed by the mask via isotropic dry etching;
removing the mask; and
forming an interlayer insulating film on the polysilicon electrode.

US Pat. No. 10,366,892

HYBRID III-V TECHNOLOGY TO SUPPORT MULTIPLE SUPPLY VOLTAGES AND OFF STATE CURRENTS ON SAME CHIP

International Business Ma...

1. A method of forming dual III-V semiconductor channel materials on a wafer, the method comprising the steps of:providing a wafer having a first III-V semiconductor layer on an oxide;
forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer;
using shallow trench isolation to define at least one first active area and at least one second active area in the wafer;
converting the first III-V semiconductor layer in the at least one second active area to an insulator using ion implantation; and
removing the second III-V semiconductor layer from the at least one first active area selective to the first III-V semiconductor layer,
wherein the first III-V semiconductor layer in the at least one first active area and the second III-V semiconductor layer in the at least one second active area serve as the dual III-V semiconductor channel materials on the wafer.

US Pat. No. 10,366,891

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A vertical semiconductor apparatus comprising:a gallium nitride substrate;
a gallium nitride semiconductor layer provided on the gallium nitride substrate;
a p-type impurity region that is provided in the gallium nitride semiconductor layer and has an element to function as an acceptor for gallium nitride;
an n-type impurity region that is provided in the p-type impurity region and has an element to function as a donor for gallium nitride; and
an electrode provided in contact with a rear surface of the gallium nitride substrate, wherein
the element to function as the donor in the n-type impurity region includes:
a first impurity element that enters sites of gallium atoms in the gallium nitride semiconductor layer; and
a second impurity element that is an element different from the first impurity element and enters sites of nitrogen atoms in the gallium nitride semiconductor layer, and
in the n-type impurity region, a concentration of the first impurity element is higher than a concentration of the second impurity element.

US Pat. No. 10,366,890

METHOD FOR PATTERNING A SUBSTRATE USING A LAYER WITH MULTIPLE MATERIALS

Tokyo Electron Limited, ...

1. A method of patterning a substrate, the method comprising:forming mandrels on a target layer of a substrate, the mandrels being comprised of a first material, the target layer being comprised of a third material;
forming sidewall spacers on sidewalls of the mandrels by depositing a conformal film on the substrate and removing portions of the conformal film above top surfaces of the mandrels while leaving the conformal film below top surfaces of the mandrels such that the sidewall spacers are formed on vertical sidewalls of the mandrels and such that the conformal film covers the target layer between adjacent sidewall spacers, the conformal film being comprised of a second material;
forming a first etch mask on the substrate, the first etch mask defining openings that uncover regions of both the first material and the second material
executing a first etch process that selectively etches uncovered portions of the second material until the conformal film covering the target layer between adjacent sidewall spacers is removed while the sidewall spacers remain on the substrate; and
forming a second etch mask on the substrate, the second etch mask defining openings that uncover regions of both the first material and the second material; and
executing a second etch process that selectively etches uncovered portions of the first material until uncovered mandrels are removed.

US Pat. No. 10,366,889

METHOD OF FORMING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor device, comprising:providing a material layer on a substrate;
performing a spacer patterning process to form a plurality of first mask patterns parallel with each other on the material layer, the first mask patterns extending along a first direction;
performing a pattern splitting process to remove a portion of the first mask patterns to form a plurality of second openings, the second openings parallel with each other and extending along a second direction, across the first mask patterns; and
patterning the material layer by using remaining portion of the first mask patterns as a mask, to form a plurality of patterns in an array arrangement.

US Pat. No. 10,366,888

PATTERN FORMING METHOD

Tokyo Electron Limited, ...

1. A pattern forming method comprising steps of:forming a first organic film by coating an etching target film with a composition including a polymer including a cross-linkable component;
infiltrating an inorganic substance into the first organic film;
cross-linking the polymer;
forming a second organic film on the first organic film after the steps of infiltrating and cross-linking;
forming a second organic film pattern by patterning the second organic film;
forming a first organic film pattern having a pitch reduced to one-half of a pitch of the second organic film pattern by patterning the first organic film by a self-aligned patterning method that uses the second organic film pattern as a core pattern; and
forming an etching target film pattern having a pitch reduced to one-half of a pitch of the first organic film pattern by patterning the etching target film by a self-aligned patterning method that uses the first organic film pattern as a core pattern.

US Pat. No. 10,366,887

METHOD OF USING CHEMICALLY PATTERNED GUIDE LAYERS IN CHEMOEPITAXY DIRECTING OF BLOCK CO-POLYMERS

Brewer Science, Inc., Ro...

1. A method of forming a microelectronic structure, said method comprising: providing a stack comprising:a substrate having a surface; and
one or more optional intermediate layers on said substrate surface;
forming a patternable layer having first and second surfaces, said first surface being on said intermediate layers, if present, or on said substrate surface, if no intermediate layers are present, and said second surface being remote from said first surface, said patternable layer having an initial surface property at said second surface;
exposing said patternable layer to radiation so as to selectively alter said initial surface property to yield an altered surface property at the areas of exposure, forming a patterned layer;
without altering said patterned layer, applying a self-assembling composition to the second surface of said patterned layer, said composition comprising a block copolymer comprising a first block and a second block; and
causing said composition to self-assemble into a self-assembled layer in response to the initial surface property, the altered surface property, or both, wherein said self-assembled layer comprises a first self-assembled region and a second self-assembled region different from said first self-assembled region, wherein:
said initial surface property is a lack of affinity towards one of said first and second blocks over the other of said first and second blocks; and
during said exposing, an affinity to one of said first and second blocks over the other of said first and second blocks develops, said affinity being the altered surface property.

US Pat. No. 10,366,886

PATTERN FORMING METHOD, SELF-ORGANIZATION MATERIAL, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS

Toshiba Memory Corporatio...

9. A method of manufacturing a semiconductor apparatus comprising:placing a self-organization material on an under layer, the self-organization material including a block copolymer which includes a first polymer, a second polymer, and a third polymer, the third polymer is bonded to the first polymer and has a molecular structure including oxygen attached to a cyclic structure;
phase separating the block copolymer on the under layer to form a phase-separation pattern;
removing the first polymer or second polymer from the phase-separation pattern; and
after removing the first polymer or second polymer from the phase-separation pattern, processing the under layer by using the phase-separation pattern as a mask.

US Pat. No. 10,366,885

LASER IRRADIATION METHOD AND LASER IRRADIATION DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method of manufacturing a semiconductor device comprising:forming a semiconductor film comprising amorphous silicon over a substrate;
irradiating desired regions of the semiconductor film with a plurality of laser beams to crystallize the desired regions of the semiconductor film; and
patterning the crystallized semiconductor film to form a plurality of semiconductor layers, each being comprised in a respective one of a plurality of thin film transistors,
wherein the plurality of laser beams are slantingly incident on an irradiation surface of the semiconductor film.

US Pat. No. 10,366,884

METHODS FOR FORMING A GERMANIUM ISLAND USING SELECTIVE EPITAXIAL GROWTH AND A SACRIFICIAL FILLING LAYER

STRATIO, Seoul (KR)

1. A method for obtaining a semiconductor island, the method comprising:epitaxially growing one or more semiconductor structures over a substrate with one or more mask layers defining one or more regions that are not covered by the one or more mask layers over the substrate, wherein the one or more semiconductor structures are epitaxially grown over the one or more regions that are not covered by the one or more mask layers, a respective epitaxially grown semiconductor structure of the one or more epitaxially grown semiconductor structures including a first portion located adjacent to the one or more mask layers and a second portion located away from the one or more mask layers, the first portion of the respective epitaxially grown semiconductor structure having a height that is less than a height of a portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure, the second portion of the respective epitaxially grown semiconductor structure having a height that is equal to, or greater than, the height of the portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure;
forming one or more dielectric or polysilicon filling layers directly on at least the first portion of the respective epitaxially grown semiconductor structure; and,
subsequent to forming the one or more filling layers on at least the first portion of the respective epitaxially grown semiconductor structure, removing at least a portion of the respective epitaxially grown semiconductor structure that is located above the height of the portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure.

US Pat. No. 10,366,883

HYBRID MULTILAYER DEVICE

Hewlett Packard Enterpris...

1. A multilayer device, comprising:a substrate;
a first layer disposed on the substrate;
a trench extending longitudinally through at least one of the substrate and the first layer, the trench having a first sidewall spaced apart from a second sidewall, each sidewall extending from a given surface of the substrate to another surface of the first layer that is spaced apart from the given surface by the first and second sidewalls; and
an active region disposed on the first layer, both the active region and the first layer overlying the trench, and the first layer bonded to the substrate at locations laterally outward of the first and second sidewalls of the trench.

US Pat. No. 10,366,882

SYSTEM FOR PRODUCING POLYCRYSTALLINE SILICON, APPARATUS FOR PRODUCING POLYCRYSTALLINE SILICON, AND PROCESS FOR PRODUCING POLYCRYSTALLINE SILICON

Shin-Etsu Chemical Co., L...

1. A process for producing polycrystalline silicon, comprising generating steam during growth of polycrystalline silicon while keeping a temperature of an inner wall surface of a reactor at not more than 370° C., wherein the inner wall surface of the reactor which contacts a process gas comprises a steel type comprising an alloy for which a value of a relational expression in mass content percentage among chromium, nickel, and silicon, [Cr]+[Ni]?1.5 [Si], is not less than 40%,wherein water is removed and returned to said reactor via a coolant circulation path, which comprises a first pressure control section, a second pressure control section, and a coolant tank,
wherein said steam is generated by feeding hot water, having a temperature higher than a standard boiling point, to said reactor, then vaporizing a portion of said hot water,
where the pressure of said hot water is reduced so that a portion of said hot water itself is flashed into said steam,
wherein the pressure of water discharged from said reactor is controlled by said first pressure control section and the pressure in said coolant tank is controlled by said second pressure control section, and
said hot water is flashed to generate steam and to cool the hot water simultaneously by reducing the pressure of the hot water in the first pressure control section,
wherein said first pressure control section comprises a first pressure indicator controller and a first pressure control valve configured for reducing the pressure of said hot water, and said second pressure control section comprises a second pressure indicator controller and a second pressure control valve configured for controlling pressure within said coolant tank.

US Pat. No. 10,366,881

POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS

International Business Ma...

1. A semiconductor device, comprising:a porous fin formed on a monocrystalline substrate;
a hydrogenated surface formed on the porous fin; and
an epitaxial monocrystalline layer formed on the hydrogenated surface, the epitaxial monocrystalline layer including a material other than a material of the monocrystalline substrate and forming a relaxed heteroepitaxial interface with the monocrystalline substrate wherein a thickness of the porous fin and a thickness of the epitaxial monocrystalline layer include a thickness ratio configured to relax strain in the epitaxial monocrystalline layer.

US Pat. No. 10,366,880

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a semiconductor device on a semiconductor wafer;
forming an electrode layer on a first main surface of the semiconductor wafer, the electrode layer being electrically connected to the semiconductor device;
forming a first protective film on the first main surface of the semiconductor wafer, the first protective film containing a first resin and having an opening that partially exposes the electrode layer;
forming an electrode film on a surface of the electrode layer exposed in the opening;
selectively applying a second resin on surfaces of the first protective film and the electrode film by an inkjet method so as to form, along a boundary between the first protective film and the electrode film, two second protective films that extend parallel to the boundary, one of the second protective films being formed on a first side of the boundary and the other second protective film being formed on an opposite side of the boundary, and
applying a third resin between the two second protective films by the inkjet method so as to form a third protective film in contact with the two second protective films, a viscosity of the third resin being lower than a viscosity of the second resin.

US Pat. No. 10,366,879

DRY AND WET ETCH RESISTANCE FOR ATOMIC LAYER DEPOSITED TIO2 FOR SIT SPACER APPLICATION

International Business Ma...

1. A method for creating an etch resistant Titanium Oxide film for sidewall image transfer (SIT) spacer application, the method comprising:generating a mandrel formation;
depositing a Titanium Oxide spacer on the mandrel formation, wherein depositing the Titanium Oxide spacer further comprises at least one of exposing the Titanium Oxide spacer to at least 100 C and plasma conditions of RF power of least 500 W for at least 1 second; and
generating a Titanium Oxide film, wherein the Titanium Oxide film comprises: Titanium Oxide density of at least 5 g/cm3, a hardness of at least 10 GPa, and a Titanium percentage of at least 30%.

US Pat. No. 10,366,877

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A substrate processing method comprising:supplying a first cleaning liquid containing water to a first surface of a substrate while the substrate is being rotated, thereby cleaning the first surface of the substrate;
supplying a second cleaning liquid containing water to a second surface of the substrate that is opposite to the first surface of the substrate while the substrate is being rotated and the first cleaning liquid is being supplied to the first surface of the substrate, thereby cleaning the second surface of the substrate;
supplying a rinsing liquid to the first surface of the substrate and the second surface of the substrate while the substrate is being rotated, thereby rinsing the first cleaning liquid and rinsing the second cleaning liquid;
stopping the supplying of the rinsing liquid to the second surface of the substrate at a predetermined time, continuing the rinsing of the first surface of the substrate after stopping the rinsing of the second surface of the substrate and thereafter supplying an organic solvent to the first surface of the substrate to substitute the rinsing liquid on the first surface such that the first surface of the substrate is not exposed to outside air while the substrate is continuously rotated, thereby removing the rinsing liquid remaining on the first surface of the substrate by the organic solvent and removing the rinsing liquid remaining on the second surface of the substrate by a centrifugal force;
supplying a water-repellent agent to the first surface of the substrate while the substrate is being rotated; and
after the supplying the water-repellent agent to the first surface of the substrate, increasing a rotation speed of the substrate thereby drying the substrate.

US Pat. No. 10,366,876

PHOSPHOR-CONTAINING FILM AND BACKLIGHT UNIT

FUJIFILM Corporation, To...

1. A phosphor-containing film, comprising:a first substrate film; and
a phosphor-containing layer at which a plurality of regions containing phosphors are discretely disposed in a resin layer having an impermeability to oxygen, the phosphor having a property that deteriorates upon exposure to oxygen by reacting with the oxygen, and the phosphor-containing layer being disposed on the first substrate film,
wherein the plurality of regions containing phosphors comprise a plurality of first fluorescent regions containing phosphors and a plurality of second fluorescent regions dispersed at different positions in a film thickness direction from positions of the plurality of first fluorescent regions, both the first fluorescent regions and the second fluorescent regions being disposed in the same resin layer having an impermeability to oxygen.

US Pat. No. 10,366,874

GAS DISCHARGE LAMP AND SPOTLIGHT SYSTEM COMPRISING GAS DISCHARGE LAMP

1. A gas discharge lamp comprising a cylindrical outer bulb providing an enclosure in which a burner including two electrodes each having an electrode connection is arranged, wherein the cylindrical outer bulb hermetically seals the enclosure against the outside and the cylindrical outer bulb is made from doped quartz glass containing samarium.

US Pat. No. 10,366,873

CRYOGENIC 2D LINEAR ION TRAP AND USES THEREOF

University of Florida Res...

1. A rectilinear ion trap comprising:spaced x and y pairs of flat RF electrodes disposed in the zx and zy plane to define a trap volume, wherein each of the x flat RF electrodes comprise a slit;
a pair of DC plates, wherein the DC plates are coupled to the x and y pairs of flat RF electrodes, wherein the DC plates are disposed in the xy plane, and wherein each DC plate comprises holes configured to receive a fastener;
a base plate, wherein the base pate is coupled to the DC plates, wherein the base plate is positioned on top of the spaced x and y pairs of flat RF electrodes, and wherein the base plate is disposed of in the zy plane, wherein the base plate is parallel to the Y pair of flat RF electrodes, and wherein the base plate comprises holes to receive a fastener,
sapphire spacers, wherein the sapphire spacers have two holes configured to receive a fastener, wherein the sapphire spacers are placed between the base plate and the DC plate, wherein the sapphire spacers are placed between the DC plates and the ends of the x and y flat RF electrodes; and
fasteners, wherein the fasteners are passed through the holes in the DC plates, base plates, x and y flat RF electrodes and sapphire spacers.

US Pat. No. 10,366,872

FREQUENCY AND AMPLITUDE SCANNED QUADRUPOLE MASS FILTER AND METHODS

The Trustees of Indiana U...

1. A method of operating a quadrupole mass filter, the method comprisingionizing a sample to produce ions, each produced ion having a mass-to-charge ratio,
passing the produced ions into a quadrupole, and
applying at least one AC voltage to the quadrupole and controlling the at least one AC voltage to separate the ions by (i) incrementally varying a frequency of the at least one AC voltage within a first range of frequencies and (ii) for each of at least some of the incremental frequencies in the first range of frequencies, incrementally varying an amplitude of the at least one AC voltage within a range of amplitudes,
wherein each incremental frequency and incremental amplitude pair of the at least one AC voltage creates a different band pass filter in the quadrupole through which produced ions having a different corresponding mass-to-charge ratio pass to a detector.

US Pat. No. 10,366,871

ANALYZER

ATONARP INC., Minato-ku,...

1. An analyzer comprising:an ionizer that is configured to ionize molecules to be analyzed;
a filter that is configured to selectively pass ions generated by the ionizer via a magnetic field;
a detector that is configured to detect ions that have passed the filter; and
a processing device that is configured (a) to measure a tuning gas having components with respective concentrations and provided at one or more predetermined intervals during an operation and (b) to adjust, based on the measuring, (i) an ion current of the ionizer, (ii) the magnetic field associated with the filter, (iii) and a sensitivity of the detector to detect the components and the respective concentrations of the components of the provided tuning gas.

US Pat. No. 10,366,870

CYLINDRICAL SPUTTERING TARGET AND PROCESS FOR PRODUCING THE SAME

TOSOH CORPORATION, Shuna...

1. A process for producing a cylindrical ceramic sputtering target comprising a bonding material filled in a cavity defined by a cylindrical ceramic target material and a cylindrical base material wherein the cylindrical base material is disposed inside the cylindrical ceramic target material, wherein as observed by an X-ray radiograph of the bonding material, the total area of portions where no bonding material exists is 10 cm2 or less per 50 cm2 of X-ray radiograph area, and the maximum area of the portions where no bonding material exists is 9 cm2 or less and wherein the volume ratio of the bonding material at 25° C. that is filled in the cavity is at least 96.8% with respect to the volume of the cavity at the melting point of the bonding material, said process comprising filling a molten bonding material in a cavity, starting cooling the molten bonding material from its one end toward its other end in a cylindrical axial direction in sequence, further filling the molten bonding material in the cavity during cooling and further comprising vibrating the molten bonding material filled in the cavity when or after filling the bonding material in the cavity.

US Pat. No. 10,366,869

ACTIVE FEEDBACK CONTROL OF SUBSYSTEMS OF A PROCESS MODULE

Lam Research Corporation,...

15. A communications system for synchronizing control signals between a plurality of subsystems coupled to a process module used for processing a substrate, comprising:a distributed controller coupled to each of the plurality of subsystems and configured to initiate a plurality of process steps, each of the process steps having a step period, each step period having a plurality of fractions, the distributed controller including a master clock having a clock speed that includes a plurality of clock cycles, each clock cycle having a duration that is pre-correlated to a feedback loop within which synchronized control signals are delivered to and received from the plurality of subsystems by the distributed controller, wherein the distributed controller is configured to assign a predefined number of clock cycles for performing a corresponding number of feedback loops for transitioning between process steps,
wherein the predefined number of clock cycles are restricted to a fraction of the step period.

US Pat. No. 10,366,868

APPARATUS AND METHOD FOR APPLYING SURFACE COATINGS

Europlasma NV, Oudenaard...

1. A plasma chamber for coating a sheet of fabric, such as a textile material, with a polymer layer, the plasma chamber havinga plurality of electrode layers each having a generally planar or plate like form arranged successively and substantially parallel to each other, within the plasma chamber,
wherein both electrode layers of at least one pair of adjacent electrode layers of the plurality of electrode layers are either radiofrequency electrode layers or ground electrode layers,
wherein one electrode layer of said pair of immediately adjacent electrode layers is disposed in use on one side of the sheet of fabric and another electrode layer of said pair of immediately adjacent electrode layers is disposed on an obverse side of the sheet of fabric,
wherein the remaining electrode layers are arranged on either side of a passage for receiving the sheet of fabric, and
wherein the plasma chamber further includes a plurality of rollers for guiding the sheet of fabric, in use, between said electrode layers thereby having coatings on both sides of the sheet of fabric.

US Pat. No. 10,366,867

TEMPERATURE MEASUREMENT FOR SUBSTRATE CARRIER USING A HEATER ELEMENT ARRAY

Applied Materials, Inc., ...

1. A method to determine a temperature profile of a substrate attached to an carrier during processing, the method comprising:measuring a first combined current load of each of a plurality of heating elements in the carrier, wherein the measuring a first combined current load comprises measuring when the plurality of heating elements are in an ON state except for a first heating element of the plurality of heating elements;
changing a power status of a first heating element of the plurality of heating elements, wherein changing a power status comprises changing the first heating element to an ON state;
measuring a second combined current load of each of the plurality of heating elements after changing the power status of the first heating element;
determining the difference between the first and second combined current loads;
determining a temperature of the first heating element using the difference; and
reverting the power status of the first heating element to that before the change and repeating changing power, measuring a current load, determining a difference, and determining a temperature for each of the other heating elements of the plurality to determine a temperature at each of the heating elements of the plurality of heating elements.

US Pat. No. 10,366,866

PLASMA DEVICE DRIVEN BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT

AGC FLAT GLASS NORTH AMER...

1. A plasma source comprising:at least three electrodes, including a first electrode, a second electrode, and a third electrode, the at least three electrodes being arranged linearly such that a first distance between the first electrode and the second electrode is smaller than a second distance between the first electrode and the third electrode; and
a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave, wherein the first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase;
wherein each electrode is electrically connected to the source of power such that the first electrode is electrically connected to the first output wave, the second electrode is electrically connected to the second output wave, and the third electrode is electrically connected to the third output wave;
wherein electrical current flows between the at least three electrodes that are out of electrical phase;
wherein each electrode alternately serves as anode and cathode when powered by the multiple output waves, and
wherein the plasma source is capable of generating a plasma between the electrodes, including a first plasma directly between the first electrode and the second electrode, a second plasma directly between the second electrode and the third electrode, and a third plasma directly between the first electrode and the third electrode.

US Pat. No. 10,366,865

GAS DISTRIBUTION SYSTEM FOR CERAMIC SHOWERHEAD OF PLASMA ETCH REACTOR

Lam Research Corporation,...

1. A gas delivery ring configured to supply process gas to an outer periphery of a showerhead of a plasma processing apparatus wherein a semiconductor substrate supported on a substrate support is subjected to plasma processing, the gas delivery ring comprising:a gas ring having a single gas inlet, a plurality of channels, and a plurality of gas outlets in fluid communication with the gas inlet via the channels;
the channels including a first channel connected to the gas inlet at a midpoint thereof with downstream ends of the first channel equidistant from the gas inlet and from each other, two second channels connected at midpoints thereof to the downstream ends of the first channel with downstream ends of the second channels equidistant from the downstream ends of the first channel and from each other, and four third channels connected at midpoints thereof to downstream ends of the second channels with downstream ends of the third channels connected to the gas outlets; and
a bottom ring and cover ring, the channels extending into an upper surface of the bottom ring and enclosed by the cover ring,
wherein an upper surface of the gas delivery ring includes mounting surfaces having mounting holes therein configured to receive fasteners of gas connection blocks which attach the gas delivery ring to the outer periphery of the showerhead, and wherein the channels are disposed within the same plane.

US Pat. No. 10,366,864

METHOD AND SYSTEM FOR IN-SITU FORMATION OF INTERMEDIATE REACTIVE SPECIES

ASM IP Holding B.V., Alm...

1. A method for providing intermediate reactive species to a reaction chamber of a reactor, the method comprising the steps of:providing a first gas to a remote plasma unit;
controlling a pressure of the remote plasma unit;
forming a plasma in the remote plasma unit;
forming intermediate reactive species from the first gas using the remote plasma unit, while maintaining steady-state conditions for the remote plasma unit; and
while maintaining the steady-state conditions in the remote plasma unit, pulsing the intermediate reactive species from the remote plasma unit to the reaction chamber by switching flow of the intermediate reactive species between the reaction chamber and a vacuum source.

US Pat. No. 10,366,863

DETECTOR SUPPLEMENT DEVICE FOR SPECTROSCOPY SETUP

1. A detector supplement device for integration in a spectroscopy setup, wherein the spectroscopy setup comprises a vacuum chamber, a light source, a sample irradiating a reflected photon beam and a charged particle beam in the same direction of propagation into a radiation detector, whereinthe detector supplement device comprises a Rogowski coil placeable inside the vacuum chamber between the sample and radiation detector, wherein the charged particle beam is guided through the hollow core of the Rogowski coil allowing synchronized measurements of electrical currents due to the charged particle beam correlated to the reflected photon beam, while irradiation of the reflected photon beam and the charged particle beam takes place in the same direction of propagation.

US Pat. No. 10,366,862

METHOD AND SYSTEM FOR NOISE MITIGATION IN A MULTI-BEAM SCANNING ELECTRON MICROSCOPY SYSTEM

KLA-Tencor Corporaton, M...

1. A multi-beam scanning electron microscopy apparatus comprising:a multi-beam scanning electron microscopy sub-system comprising:
a multi-beam electron beam source configured to generate a plurality of electron beams;
a sample stage configured to secure a sample;
an electron-optical assembly including a set of electron-optical elements configured to direct at least a portion of the plurality of electron beams onto a portion of the sample; and
a detector assembly configured to detect a plurality of electron signal beams emanating from the surface of the sample to form a plurality of images, each image associated with an electron beam of the plurality of electron beams, wherein a first image contains a first instance of a pattern element obtained from a first location of the sample and at least an additional image contains an additional instance of the pattern element at an additional location of the sample; and
a controller including one or more processors configured to execute a set of program instructions stored in memory for causing the one or more processors to:
receive the plurality of images from the detector assembly;
compare two or more of the images to identify one or more common positional noise components present in the two or more images; and
remove the identified one or more common positional noise components from one or more images of the plurality of images by shifting the one or more images by an amount equal in distance and opposite in direction to the one or more common positional noise components.

US Pat. No. 10,366,861

HIGH VOLTAGE FEEDTHROUGH ASSEMBLY, TIME-RESOLVED TRANSMISSION ELECTRON MICROSCOPE AND METHOD OF ELECTRODE MANIPULATION IN A VACUUM ENVIRONMENT

Max-Planck-Gesellschaft z...

1. High voltage feedthrough assembly, which is configured for providing an electric potential in a vacuum environment within an electron diffraction or imaging apparatus, comprising:a flange connector being adapted for a connection with a column of the electron diffraction or imaging apparatus vacuum vessel, wherein the flange connector has an inner side facing into the vacuum vessel and an outer side facing to an environment of the vacuum vessel,
a vacuum-tight electrical insulator tube having a longitudinal extension with a first end facing to the flange connector and a second end being adapted for projecting into the vacuum vessel,
a flexible tube connector being adapted for a vacuum-tight coupling of the insulator tube with the flange connector, an interior of said flexible tube connector exposed to the environment of the vacuum vessel,
a manipulator device connected with the insulator tube, wherein the manipulator device is adapted for adjusting a geometrical arrangement of the insulator tube relative to the flange connector, and
an electrode device coupled to the second end of the insulator tube, wherein the electrode device has a front electrode outside the insulator tube and facing to the vacuum vessel and a cable mount inside the insulator tube for receiving a high-voltage cable, wherein
the front electrode can be positioned within the vacuum vessel relative to a counter-electrode anode, fixed within the vacuum vessel, by adjusting the geometrical arrangement of the insulator tube relative to the flange connector using the manipulator device, wherein the manipulator device is capable of varying and subsequently maintaining a distance between the front electrode and the counter-electrode anode, wherein
the front electrode includes a photo-cathode or a field emitter tip, being included in the electrode device and exposed to the vacuum vessel.

US Pat. No. 10,366,860

HIGH ASPECT RATIO X-RAY TARGETS AND USES OF SAME

FEI Company, Hillsboro, ...

1. An x-ray target, comprising:a substrate made from a soft x-ray producing material; and
a plurality of high aspect ratio structures made from a hard x-ray producing material and arranged into one or more grids or arrays,
wherein the high aspect ratio structures in one of the one or more grids or arrays are arranged as different elements of a Hadamard matrix structure.

US Pat. No. 10,366,859

ELECTROMAGNETIC INTERFERENCE CONTAINMENT FOR ACCELERATOR SYSTEMS

Varian Medical Systems, I...

1. An apparatus for attachment to a component of a microwave device, comprising:a cage;
a shield within the cage, wherein the shield is in a form of a container, and at least a majority of the shield is spaced away from an interior wall of the cage; and
a connector at the cage, wherein the connector is configured to connect to a cable connection, and wherein the connector is electrically connected to two terminals within the shield;
wherein a voltage between the two terminals has a first voltage value, and a voltage between the shield and the cage has a second voltage value that is higher than the first voltage.

US Pat. No. 10,366,858

ION BEAM DEVICE

Hitachi High-Technologies...

1. An ion beam apparatus comprising: a vacuum chamber; a gas field ion source that is installed in the vacuum chamber and has an emitter tip; an extraction electrode that is disposed to face the emitter tip; gas supply means for supplying a gas to the emitter tip; a focusing lens that focuses an ion beam emitted from the emitter tip; a deflector that deflects the ion beam that has passed through the focusing lens; and a secondary particle detector that irradiates a sample with the ion beam to detect secondary particles emitted from the sample,wherein the gas supply means includes a mixed gas chamber containing two or more types of gases including at least a hydrogen gas and a pipe that connects the vacuum chamber to the mixed gas chamber, and concentration of the hydrogen gas in the mixed gas chamber is equal to or lower than about 4% volume ratio of the hydrogen gas to a total volume of gas in the mixed gas chamber.

US Pat. No. 10,366,857

MAGNETRON FOR MICROWAVE OVEN

LG ELECTRONICS INC., Seo...

1. A magnetron for a microwave oven, comprising:a yoke forming a body of the magnetron;
an anode cylinder installed inside of the yoke;
a plurality of vanes that radially extends toward an axial center of the anode cylinder;
a filament positioned at the axial center of the anode cylinder;
a lower end shield positioned at a lower end of the filament, wherein an outer diameter of the lower end shield is about 80% to about 89% of a diameter of an inscribed circle formed by the plurality of vanes;
a center lead positioned at a center of the filament, wherein a lower end of the center lead extends downward through a center portion of the lower end shield; and
a side lead having an upper end which is connected to the lower end shield and spaced apart from the center lead.

US Pat. No. 10,366,856

NANOSCALE FIELD-EMISSION DEVICE AND METHOD OF FABRICATION

CALIFORNIA INSTITUTE OF T...

1. An apparatus including a first field-emission device, the first field-emission device comprising:a substrate;
a first electrode disposed on the substrate, the first electrode having a tip whose radius of curvature is at least 20 nm, wherein the first electrode comprises a first material having a first work function; and
a second electrode disposed on the substrate, the second electrode having a tip whose radius of curvature is at least 20 nm, wherein the second electrode comprises a second material having a second work function that is different than the first work function; and wherein the first electrode and second electrode define a first gap having a first environment that is characterized by an ionization potential;
wherein the first gap has a first separation that enables field emission of electrons from one of the first electrode and second electrode with an electron energy that is less than the ionization potential.

US Pat. No. 10,366,855

FUSE ELEMENT ASSEMBLIES

Micron Technology, Inc., ...

1. A fuse element assembly comprising:a cathode having a first end and an opposing second end; the cathode having a slit into the first end that spaces a first projecting portion from a second projecting portion, the first and second projecting portions being substantially parallel to each other and merging at a merge region; and
a fuse link extending from the merge region and beyond the second end of the cathode; and further comprising
a third projecting portion of the cathode and a fourth projecting portion of the cathode, the third and fourth projecting portions extending from the merge region toward the second end of the cathode on opposing sides of the fuse link.

US Pat. No. 10,366,854

CONTACTOR WITH COIL POLARITY REVERSING CONTROL CIRCUIT

TE CONNECTIVITY CORPORATI...

1. A contactor, comprising:a plurality of switches;
a first input circuit for receiving a power-up input signal;
a second input circuit for receiving a trip input signal;
a movable actuator mechanically coupled to switches in the plurality of switches, the actuator moveable between a tripped position and an operational position upon receipt of a power-up input signal on the first input circuit, and moveable between the operational position and the tripped position upon receipt of a trip input signal on the second input circuit;
a coil having first and second ends, the moveable actuator extending through the coil as a core, the coil capable of moving the actuator when either a power-up input signal is received by the first input circuit or a trip input signal is received by the second input circuit;
first and second switches coupled to respective first and second ends of the coil for reversing the polarity of the coil each occurrence of the actuator being actuated,
the first and second switches being switchable to include the coil in the second input circuit when the actuator is in the operational position, wherein when the trip input signal is received on the second input circuit the coil is energized to operate the actuator to transition to the tripped position, and
the first and second switches being switchable to include the coil in the first input circuit when the actuator is in the tripped position, wherein when the power-up input signal is received on the first input circuit the coil is energized to operate the actuator to transition to the operational position;
wherein as the actuator is being actuated the first and second switches change state in preparation to energize the coil to be magnetically polarized in an opposite polarization direction during a next subsequent actuation.

US Pat. No. 10,366,852

POWER RELAY FOR A VEHICLE

1. A power relay for a vehicle, comprising:a housing having a connector base and a housing can mounted on said connector base, said housing can being an injection molded component made of plastic;
two terminal studs for contacting a load circuit and inserted into said connector base;
a coil subassembly disposed in said housing and containing a solenoid coil, an armature, a force-transmission member and a contact bridge, said armature is coupled by said force-transmission member to said contact bridge and can be moved in said housing, under an action of a magnetic field generated by said solenoid coil, such that said contact bridge can be moved reversibly between a closed position, in which said contact bridge bridges said terminal studs in an electrically conducting manner, and an open position, in which said contact bridge is not in contact with said terminal studs; and
said coil subassembly further having a magnet yoke, which has a torsionally stable structure, which is accommodated nonrotatably in said housing can over an entire axial height of said housing can.

US Pat. No. 10,366,851

SWITCH DEVICE AND DETECTING APPARATUS EQUIPPED WITH IT

ALPS ALPINE CO., LTD., T...

1. A switch device comprising:a housing;
at least two internal terminals provided in the housing;
a movable contact; and
a manipulation body that operates the movable contact; wherein
an opening into which an external terminal is insertable is disposed in the housing,
each internal terminal has a contact touching part that is electrically connected to the movable contact and has a terminal connecting part connectable to the external terminal inserted into the housing, and
the housing has at least one of a guide concave part and a guide protrusion that guides the housing toward an external base material to which the external terminal is fixed, and that extend in a direction in which the external terminal is inserted, wherein:
the housing has a bottom part facing an attachment surface of the external base material to which the external terminal is fixed and also has two side parts erected from the attachment surface with the bottom part intervening between the two side parts;
the opening is in the bottom part; and
each of the two side parts has at least one of the guide concave part and the guide protrusion.

US Pat. No. 10,366,850

ELECTRONIC DEVICE INCLUDING KEY BUTTON

Samsung Electronics Co., ...

1. An electronic device comprising:a housing including a through hole;
a key button including a first extension movably inserted into the through hole;
a sealing member disposed between the through hole and the first extension; and
a separation prevention member coupled to the housing to prevent the key button from being separated from the housing, wherein the separation prevention member comprises a fixed portion fixed to an inner face of the housing and a second extension extended from the fixed portion and coupled to one or more recesses formed on a portion of the first extension of the key button, wherein, in order for the one or more recesses to receive the second extension, a width of the one or more recesses in a moving direction of the key button is larger than a thickness of the second extension.

US Pat. No. 10,366,849

METHOD TO CREATE A REDUCED STIFFNESS MICROSTRUCTURE

DUALITY REALITY ENERGY, L...

1. A method to create a reduced stiffness microstructure, comprising:forming a first buckled membrane along a first buckling direction; and
forming a second buckled membrane along a second buckling direction, the second buckling direction is opposite to the first buckling direction, the first buckled membrane is in contact with the second buckled membrane over a contact area, within an operating zone a stiffness of the reduced stiffness microstructure during contact is less than an absolute value of a stiffness of at least one of the first buckled membrane, before contact, and the second buckled membrane, before contact, when the contact area translates along either one of the first buckling directions and the second buckling direction.

US Pat. No. 10,366,848

METHOD FOR PRODUCING ELECTRIC SWITCHGEAR AND ELECTRIC SWITCHGEAR WITH ENHANCED SEAL-TIGHTNESS

SCHNEIDER ELECTRIC INDUST...

1. A method for producing low- or medium-voltage electrical switchgear comprising an electrical component, at least one electrical connector connected electrically to the electrical component and an enclosure delimiting a volume in which the electrical component is received, in which the electrical connector comprises a body which passes through the enclosure,the method comprising a step of fitting a seal in a peripheral groove formed in a wall of the body and
a step of injecting a plastic material around the body of the electrical connector and around the seal,
wherein the injection step consists of injecting the plastic material at a pressure causing an elastic crushing of the seal in the peripheral groove, and
a dimension of at least part of the peripheral groove, measured along a main axis of the electrical connector, is less than a greatest axial dimension of the seal.

US Pat. No. 10,366,847

DEVICE FOR GUIDING A SPRING IN A CONTROL MECHANISM AND ELECTRICAL PROTECTION APPARATUS COMPRISING SAME

SCHNEIDER ELECTRIC INDUST...

1. A device for guiding a spring belonging to a control mechanism having first and second axes of which at least one axis of the first and second axes is linked mechanically to an operating shaft, said device comprising:a compression spring having first and second ends;
a first slideable element including:
a guiding portion for guiding movement of the compression spring during compression and including first and second holes passing lengthwise through the guiding portion, and
a first base including (a) a notch configured to link the first base in an articulated manner to the first axis, and (b) a first bearing surface configured to abut the first end of the compression spring, wherein the first and second holes passing through the guiding portion continue through the first base;
a second slideable element including:
a second base including (a) a notch configured to link the second base in an articulated manner to the second axis, and (b) a second bearing surface configured to abut the second end of the compression spring, and
first and second parallel rods, each rod of the first and second parallel rods having (a) a fixed end being fixed onto said second base, and (b) a free end being mounted to slide through a respective one of the first and second holes and extend out of the first base.

US Pat. No. 10,366,846

REMOTE CONTROL DEVICE FOR AN ELECTRICAL DEVICE IN AN ELECTRICAL ENCLOSURE

SCHNEIDER ELECTRIC INDUST...

1. A remote control device for an electrical device in an electrical enclosure, said electrical enclosure including a bottom wall and side walls extending at right angles to the bottom wall and delimiting a housing, an electrical device being fixed, on the bottom wall, inside the housing, said remote control device comprising:a rotary control member that is fixed onto a wall of the enclosure outside the housing at a right angle to a face of the electrical device, the rotary control member remaining at a same orientation relative to the face of the electrical device when the electrical enclosure is open and when the electrical enclosure is closed, said rotary control member being selectively movable between first and second configurations,
a transmission system that mechanically links the rotary control member to a control lever of the electrical device, said control lever movable between the first and second positions, the transmission system moving the control lever between the first and second positions based on movement of the rotary control member between the first and second configurations,
wherein:
the rotary control member is mountable on one of the side walls of the housing and is rotationally mobile,
the transmission system comprises:
a first pinion, secured in rotation with the rotary control member about a first fixed axis, at right angles to the side walls,
a second pinion, meshed with the first pinion and rotationally mobile about a second fixed axis at right angles to the first fixed axis, said second pinion being coupled mechanically with the control lever to move said control lever between the first and second positions when the second pinion is moved in rotation.

US Pat. No. 10,366,845

MONITORED ADAPTABLE EMERGENCY OFF-SWITCH

1. An emergency off-switch for triggering an emergency switch-off function for safety-related shutdown of an electrical device, comprising:an actuator and at least two electrical contact points which can be connected to one another via a contact bridge, wherein a position of the contact bridge is influenced by the actuator such that the electrical contact points can selectively be opened or closed,
an active operating state, in which the emergency switch-off function can be triggered by moving the contact bridge, and a passive operating state, in which the emergency off-switch is non-functional,
a visualization unit having at least a first and a second display state, wherein the emergency off-switch is visually highlighted in the first display state, and the emergency off-switch is neutrally displayed in the second display state, the visualization unit being designed to adopt the first display state in the active operating state and to adopt the second display state in the passive operating state, and
a monitoring unit which monitors whether the visualization unit is in the first or in the second display state,
wherein, in the first display state, the visualization unit has a defined nominal current and the monitoring unit triggers the emergency switch-off function, when an actual current into the visualization unit is less than the defined nominal current.

US Pat. No. 10,366,843

CARBON FIBER AND PARYLENE STRUCTURAL CAPACITOR

1. A method of manufacturing a structural capacitor comprising:(a) forming a first layer made of a nonconductive structural material into a desired shape of a structural component of an object;
(b) placing a conductive layer including carbon fiber on the first layer;
(c) placing parylene directly on the conductive layer to form a dielectric layer; and
(d) repeating steps (b) and (c) until a desired property is achieved.

US Pat. No. 10,366,842

DYE-SENSITIZED SOLAR CELL AND METHOD FOR MANUFACTURING THEREOF

SHARP KABUSHIKI KAISHA, ...

1. A dye-sensitized solar cell comprising;a substrate,
two or more light transmitting conductive layers provided on the substrate,
a first light transmitting conductive layer which is one of the two or more light transmitting conductive layers,
a second light transmitting conductive layer which is one of the two or more light transmitting conductive layers and provided adjacent to the first light transmitting conductive layer and on the substrate,
a first insulating layer provided on the substrate between the first light transmitting conductive layer and the second light transmitting conductive layer,
a first porous semiconductor layer including first semiconductor particles and a first dye, and provided on the first light transmitting layer,
a second porous semiconductor layer including second semiconductor particles, and provided on the first porous semiconductor layer, and
a first counter electrode including a counter conductive layer and provided on the second porous semiconductor layer and the insulating layer, and the counter conductive layer connected to the second light transmitting conductive layer.

US Pat. No. 10,366,840

CAPACITOR WITH MULTIPLE ELEMENTS FOR MULTIPLE REPLACEMENT APPLICATIONS

American Radionic Company...

1. An apparatus comprising:a case having an elliptical cross-section capable of receiving a plurality of capacitive devices, one or more of the capacitive devices providing at least one capacitor having a first capacitor terminal and a second capacitor terminal, wherein a first of the plurality of capacitive devices is affixed to the case by a first bracket and a second of the plurality of capacitive devices is affixed to the case by a second bracket, wherein the first bracket includes a curved middle portion that has a shape substantially similar to a shape of an outer surface of the first of the plurality of capacitive devices, and the second bracket includes a curved middle portion that has a shape substantially similar to a shape of an outer surface of the second of the plurality of capacitive devices;
a cover assembly comprising:
a deformable cover mountable to the case,
a common cover terminal having a contact extending from the deformable cover,
at least three capacitor cover terminals, each of the at least three capacitor cover terminals having at least one contact extending from the deformable cover, wherein the deformable cover is configured to displace at least one of the at least three capacitor cover terminals upon an operative failure of at least one of the plurality of capacitive devices, and
at least four insulation structures, wherein at least one of the at least four insulation structures is associated with one of the at least three capacitor cover terminals;
a first conductor capable of electrically connecting the first capacitor terminal of a capacitor provided by one of the plurality of capacitive devices to one of the at least three capacitor cover terminals; and
a second conductor capable of electrically connecting the second capacitor terminal of the capacitor provided by the one of the plurality of capacitive devices to the common cover terminal.

US Pat. No. 10,366,839

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a multilayer ceramic capacitor including a capacitor body and external electrodes disposed on opposite ends of the capacitor body in a first direction, respectively; and
an interposer including an interposer body including a woven glass fiber material and external terminals disposed on opposite ends of the interposer body in the first direction, respectively,
wherein an angle between a weaving direction of the woven glass fiber material and the first direction is 0° to 10° or 80° to 90°.

US Pat. No. 10,366,838

LAMINATED CERAMIC ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING SAME

MURATA MANUFACTURING CO.,...

1. A method for producing a laminated ceramic electronic component, the method comprising:preparing a laminate having a plurality of dielectric layers and a plurality of internal electrode layers respectively laminated, and having a first main surface and a second main surface opposed to each other in a lamination direction, a first side surface and a second side surface opposed to each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal to the lamination direction and the width direction;
preparing an electroconductive paste containing Cu particles coated with an oxide of Al or Zr; and
applying the electroconductive paste onto the first end surface and the second end surface of the laminate.

US Pat. No. 10,366,836

ELECTRONIC COMPONENT STRUCTURES WITH REDUCED MICROPHONIC NOISE

KEMET Electronics Corpora...

1. An electronic structure comprising:a first conductive metal layer and a second conductive metal layer;
a first compliant non-metallic layer on said first conductive metal layer wherein said first compliant non-metallic layer comprises a gap wherein said gap is a via through said first compliant non-metallic layer and said gap is smaller than said first conductive metal layer;
an electronic component comprising a first external termination of a first polarity and a second external termination of a second polarity wherein said gap is smaller than said first external termination;
a transient liquid phase sintering adhesive in electrical contact with said first external termination and said first conductive metal layer wherein said transient liquid phase sintering adhesive extends through said gap;
wherein said electronic component is a multilayered ceramic capacitor comprising at least one floating electrode wherein said floating electrode is selected from the group consisting of an external floating electrode coplanar with at least one first electrode of said first electrodes and an internal floating electrode coplanar with at least one first electrode of said first electrodes; and
wherein said multilayered ceramic capacitor further comprises a shock absorbing conductor wherein said shock absorbing conductor has a shape selected from S shaped, and Z shaped.

US Pat. No. 10,366,835

PLATED TERMINATIONS

AVX Corporation, Fountai...

1. A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the plurality of the interior plates being exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the plurality of interior plates are also exposed upon at least a portion of the second surface of the capacitor, the method comprising:electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where the edges of the plurality of interior plates are exposed upon the first surface, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface; and
concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where the edges of the plates are exposed upon the second surface, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,
wherein each of the first layer of electrically-conductive first metal on the first surface and the first layer of electrically-conductive first metal on the second surface is not deposited on any of the additional surfaces which meet the first surface, and
wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

US Pat. No. 10,366,834

CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A ceramic electronic component, comprising:a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other;
a first external electrode including a first electrode layer disposed on the third surface of the body and electrically connected to the first internal electrode, a first inorganic insulating layer disposed on the first electrode layer, and a first plating layer disposed on the first inorganic insulating layer;
a second external electrode including a second electrode layer disposed on the fourth surface of the body and electrically connected to the second internal electrode, a second inorganic insulating layer disposed on the second electrode layer, and a second plating layer disposed on the second inorganic insulating layer; and
a third inorganic insulating layer disposed on the first, second, fifth, and sixth surfaces of the body and connected to the first and second inorganic insulating layers,
wherein the first, second, and third inorganic insulating layers comprise at least one selected from the group of SiO2, Al2O3 and ZrO2, and the first, second, and third inorganic insulating layers have a thickness within a range from 20 nm to 150 nm, and
wherein the first and second inorganic insulating layers have an, opening formed therein, and the first and second plating layers are in direct contact with the first and second electrode layers through the opening, respectively.

US Pat. No. 10,366,833

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers including a ceramic co-material are alternately stacked,
wherein a concentration of Mg in a ceramic grain that is included in the ceramic dielectric layer and contacts to the internal electrode layer is smaller than that in the co-material.

US Pat. No. 10,366,832

CAPACITOR AND ELECTRONIC DEVICE HAVING A PLURALITY OF SURFACE ELECTRODES ELECTRICALLY CONNECTED TO EACH OTHER BY AN INTERMEDIATE ELECTRODE

MURATA MANUFACTURING CO.,...

1. A capacitor comprising:a substrate having a first main surface;
a first inner electrode and a second inner electrode disposed above a side of the first main surface, the second inner electrode being arranged so as to face the first inner electrode;
a dielectric layer between the first inner electrode and the second inner electrode;
a first intermediate electrode connected to the first inner electrode at a plurality of first locations;
a plurality of first surface electrodes which are each electrically connected to the first intermediate electrode; and
a second surface electrode electrically connected to the second inner electrode at a plurality of second locations,
wherein a first layer of the capacitor containing the first inner electrode and a second layer of the capacitor containing the first intermediate electrode have different electrode patterns.

US Pat. No. 10,366,831

MULTILAYER CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer capacitor having:a laminate comprising a stack of multiple dielectric layers made of dielectric material and having a first principal face and a second principal face on an opposite side of the first principal face; and
multiple internal electrode layers whose primary component is Ni and which are arranged in parallel with the first principal face and second principal face inside the laminate in such a way that they alternate from opposing sides with the dielectric layers placed in between; wherein,
of the internal electrode layers, at least the internal electrode layer closest to the first principal face and internal electrode layer closest to the second principal face contain in its entirety at least one metal element selected from the group consisting of Pt, Ru, Rh, Re, Ir, Os, and Pd;
of the multiple internal electrode layers, the internal electrode layer closest to the first principal face has a distance of 30 ?m or less from the first principal face; and
of the multiple internal electrode layers, the internal electrode layer closest to the second principal face has a distance of 30 ?m or less from the second principal face,
wherein internal electrode layers away from the first and second principal faces, among the multiple internal electrode layers, contain none of any metal element selected from the group consisting of Pt, Ru, Rh, Re, Ir, Os, and Pd.

US Pat. No. 10,366,830

SURFACE MOUNT ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A surface mount electronic component comprising:an element including a dielectric layer including a first main surface and a second main surface;
a first external electrode disposed on the first main surface;
a second external electrode disposed on the second main surface;
a first metal terminal connected to the first external electrode;
a second metal terminal connected to the second external electrode; and
an exterior material covering at least a portion of the element, the first and second external electrodes, and the first and second metal terminals; wherein
upper and lower surfaces of the exterior material are flat or substantially flat;
the first metal terminal includes:
a first bonding portion connected to the first external electrode;
a first extending portion connected to the first bonding portion and extending in a direction parallel or substantially parallel to the first main surface with a space from the first main surface;
a second extending portion connected to the first extending portion and extending towards the element;
a third extending portion connected to the second extending portion and extending in the direction parallel or substantially parallel to the first main surface;
a fourth extending portion connected to the third extending portion and extending in a mounting direction; and
a first mounting portion connected to the fourth extending portion and mounted on a mounting substrate;
the second metal terminal includes:
a second bonding portion connected to the second external electrode;
a fifth extending portion connected to the second bonding portion and extending in a direction parallel or substantially parallel to the second main surface with a space from the second main surface;
a sixth extending portion connected to the fifth extending portion and extending towards the element;
a seventh extending portion connected to the sixth extending portion and extending in the direction parallel or substantially parallel to the second main surface;
an eighth extending portion connected to the seventh extending portion and extending in the mounting direction; and
a second mounting portion connected to the eighth extending portion and mounted on the mounting substrate;
in the first bonding portion, a distal end of the first bonding portion is disposed in a direction away from the first main surface from an intermediate portion of the first bonding portion towards the distal end, and the first bonding portion is in surface contact with the first external electrode at the intermediate portion located on an opposite side of the distal end;
a first cut-out portion is provided in a portion in which the second extending portion of the first metal terminal and the third extending portion of the first metal terminal intersect with each other;
the second bonding portion includes a bifurcated distal end and is in surface contact with the second external electrode at the bifurcated portion;
a second cut-out portion is provided in the fifth extending portion of the second metal terminal;
a third cut-out portion is provided in a portion in which the sixth extending portion of the second metal terminal and the seventh extending portion of the second metal terminal intersect with each other; and
the first, second and third cut-out portions are covered with the exterior material.

US Pat. No. 10,366,829

COIL ASSEMBLY FOR NON-CONTACT CHARGING

OMRON AUTOMOTIVE ELECTRON...

1. A coil assembly for non-contact charging which has a power supplying surface facing a power receiving device and is provided in a power transmission device which wirelessly transmits power to the power receiving device, the coil assembly comprising:a circuit board;
a first coil positioned directly onto the circuit board;
a second coil positioned as close as, or farther than, the first coil from the power supplying surface; and
a single magnetic body that:
is positioned farther than the second coil from the power supplying surface, overlaps with the second coil, and
does not overlap with the first coil when seen from the power supplying surface.

US Pat. No. 10,366,828

APPARATUS FOR WIRELESS POWER TRANSFER, APPARATUS FOR WIRELESS POWER RECEPTION AND COIL STRUCTURE

KOREA ELECTROTECHNOLOGY R...

1. A wireless power transmitting device, comprising:a bowl-shaped transmitting device body; and
a transmitting coil unit for wirelessly transmitting power to a receiving device,
wherein the transmitting coil unit comprises:
a multi-loop coil unit wound flatways in a bottom of the transmitting device body; and
a helical coil unit extending from the maximum radius of the multi-loop coil unit, wound around a side wall of the transmitting device body, and wound to increase a radius of a coil loop in a direction to an upper part,
wherein the whole or a part of the receiving device is located in an interior area defined by the transmitting device body, and receives wireless power from the wireless power transmitting device, and
wherein the wireless power transmitting device generates a magnetic field that is formed in a wider area than the sum of magnetic fields independently generated by the helical coil unit and the multi-loop coil unit.

US Pat. No. 10,366,827

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a coil main body portion having a primary coil and a secondary coil magnetically coupled to each other;
a cylindrical connecting portion for connecting the coil main body portion and a spark plug; and
a conducting member disposed inside the connecting portion and electrically connecting the coil main body portion and the spark plug; wherein
a convex surface forming portion, which is a portion constituting an inner peripheral convex surface, an inner peripheral surface of which projects toward an inner peripheral side, is disposed in the connecting portion;
the convex surface forming portion has an outer peripheral concave surface, an outer peripheral surface of which is recessed toward the inner peripheral side;
the connecting portion has a boundary portion which is a boundary between the convex surface forming portion and other portions in an axial direction;
in the convex surface forming portion, at least a part of a region where the outer peripheral concave surface is formed has a portion having an area, in a cross-section orthogonal to the axial direction, equal to or smaller than an area of a cross-section orthogonal to the axial direction in the boundary portion, and a thickness of the convex surface forming portion is equal to or thicker than a thickness of the boundary portion; and
a thickness of the convex surface forming portion is equal to or thicker than a thickness of the boundary portion.

US Pat. No. 10,366,825

BARRIER ARRANGEMENT BETWEEN TRANSFORMER COIL AND CORE

ABB Schweiz AG, Baden (C...

1. An insulation barrier for a transformer, comprising:an inner portion including a first cylindrical body and a radially outwardly extending flange extending from a first end of the first cylindrical body; and
an outer portion including a second cylindrical body and a radially inwardly extending flange extending from a second end of the second cylindrical body in overlapping relation with the radially outwardly extending flange of the inner portion, wherein the first and second cylindrical body portions are spaced from one another to form a space sized to receive a high voltage coil between the first and second cylindrical bodies.

US Pat. No. 10,366,824

DIRECT MOUNTING BRACKET

TRENCH LIMITED, Ontario ...

1. An air core reactor for use in an electric power transmission and distribution system or in an electric power system of an electrical plant, the air core reactor comprising:an electrically insulated support structure;
a coil of windings supported by the electrically insulated support structure; and
an insulator mounting bracket configured as an interface between the coil and the electrically insulated support structure, wherein the insulator mounting bracket includes:
a body that comprises a closed shape in a form of an annulus having a plurality of holes and the body comprises first and second grooves to receive a spider,
a mounting flange attached to the body, and
a plurality of attachments that are composite bands being threaded through the plurality of holes.

US Pat. No. 10,366,821

COMMON MODE NOISE FILTER

Panasonic Intellectual Pr...

1. A common mode noise filter comprising:a first insulating layer;
a second insulating layer formed under the first insulating layer;
a first coil including a first coil conductor and a second coil conductor, the first coil conductor being electrically connected to the second coil conductor;
a second coil including a third coil conductor and a fourth coil conductor, the third coil conductor being electrically connected to the fourth coil conductor; and
a third coil including a fifth coil conductor and a sixth coil conductor, the fifth coil conductor being electrically connected to the sixth coil conductor,
wherein the first coil, the second coil, and the third coil are electrically independent of one another,
the first coil conductor, the third coil conductor, and the fifth coil conductor are formed side by side on the first insulating layer in a spiral fashion such that the first coil conductor, the third coil conductor, and the fifth coil conductor are sequentially positioned from an outer side of the first insulating layer,
the first coil conductor, the third coil conductor, and the fifth coil conductor have regions disposed in parallel to one another,
the second coil conductor, the fourth coil conductor, and the sixth coil conductor are formed side by side on the second insulating layer such that the fourth coil conductor, the sixth coil conductor, and the second coil conductor are sequentially positioned from an outer side of the second insulating layer,
the second coil conductor, the fourth coil conductor, and the sixth coil conductor have regions disposed in parallel to one another,
the first coil conductor and the fourth coil conductor have regions overlapping each other as seen from a top view,
the third coil conductor and the sixth coil conductor have regions overlapping each other as seen from a top view, and
the fifth coil conductor and the second coil conductor have regions overlapping each other as seen from a top view.

US Pat. No. 10,366,820

THIN FILM INDUCTOR

TDK CORPORATION, Tokyo (...

1. A thin film inductor comprising:a coil part formed of at least one coil conductor layer and having terminal electrodes provided at both ends thereof;
a first insulating layer configured to cover the coil part; and
a second insulating layer configured to cover the first insulating layer and having a higher Young's modulus than the first insulating layer, the second insulating layer enclosing an entire outer surface of the first insulating layer, other than in a region of the first insulating layer covered by the terminal electrodes.

US Pat. No. 10,366,819

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising:a preformed coil that is formed of a winding part which winds a coated conductive wire continuously and spirally in an axial direction and includes an inner circumferential surface, an outer circumferential surface, and a principle face of one end portion and a principle face of the other end portion in the axial direction, and of a pair of leader parts which extends outwardly from the winding part;
a first core member that includes a shaft part disposed inside the inner circumferential surface, a side wall portion disposed in at least a portion of the outer circumferential surface, and a connection portion which is disposed such that a first gap is formed between the principle face of the one end portion and the connection portion, and through which the shaft part is connected to the side wall portion, and that contains metal magnetic grains; and
a second core member which is disposed such that a second gap is formed between the principle face of the other end portion and the second core member which contains metal magnetic grains and is provided with an adhesive, wherein:
the pair of leader parts are disposed in a portion where the side wall portion of the first core member is not formed on the outer circumferential surface of the winding part, and the pair of leader parts are not covered by the side wall portion,
the coil component further comprises a pair of terminal electrodes formed at respective ends of the leader parts in a manner extending in a same direction and facing the principle face of the other end portion of the winding part, wherein a peripheral portion of the second core member including a portion of the second gap provided with the adhesive is in direct contact with and fitted between the principle face of the other end portion of the winding part and the pair of terminal electrodes,
the second core member is of an E-type wherein the second core member includes a second shaft part facing and axially aligned with the shaft part of the first core member, a second side wall portion facing and axially aligned with the side wall portion of the first core member, and a second connection portion connecting the second shaft part and the second side wall portion, and
the first gap formed between the principle face of the one end portion of the winding part and the connection portion of the first core member is constituted by a void.

US Pat. No. 10,366,818

CHOKE HAVING A CORE WITH A PILLAR HAVING A NON-CIRCULAR AND NON-RECTANGULAR CROSS SECTION

CYNTEC CO., LTD, Hsinchu...

1. An inductor comprising: a core structure having a first board, a second board, and a pillar located between the first and second boards, a winding space being located among the first board, the second board and the pillar, wherein the pillar has a non-circular and non-rectangular cross section along a direction substantially perpendicular to an axial direction of the pillar, wherein the periphery of the cross section of the pillar comprises a first substantially straight line, a first arc, a second substantially straight line, and a second arc on four sides of the periphery, respectively, wherein the substantially straight lines are interleaved with the arcs on the periphery of the cross section of the pillar, and wherein each arc is convex with respect to said substantially straight lines, wherein a coil is disposed in the winding space and wound on the first substantially straight line, the first arc, the second substantially straight line, and the second arc, wherein the cross section of the pillar has a first axis and a second axis intersecting with each other at a center of the cross section of the pillar and being substantially perpendicular with each other, wherein the length of the first axis is greater than that of the second axis, and an inequality is satisfied:
wherein X represents the length of the first axis, and Y represents the length of the second axis;
wherein the periphery of the cross section of the pillar encloses the center of the first board, wherein each of a first edge and a third edge of the first board is substantially in parallel with the first axis, and each of a second edge and a fourth edge of the first board is substantially in parallel with the second axis, wherein an inequality is satisfied:

wherein M? represents the distance between the second edge of the first board and the center of the cross section of the pillar along the direction of the first axis, N? represents the distance between the first edge of the first board and the center of the cross section of the pillar along the direction of the second axis, wherein the distance between the second edge of the first board and the center of the cross section of the pillar along the direction of the first axis is equal to the distance between the fourth edge of the first board and the center of the cross section of the pillar along the direction of the first axis; and the distance between the first edge of the first board and the center of the cross section of the pillar along the direction of the second axis is equal to the distance between the third edge of the first board and the center of the cross section of the pillar along the direction of the second axis.

US Pat. No. 10,366,817

APPARATUS AND METHOD FOR PASSIVE COOLING OF ELECTRONIC DEVICES

General Electric Company,...

1. An electronic device assembly comprising:a heat dissipation member; and
a dielectric two-phase heat transfer device comprising:
an evaporator region coupled in thermal communication with a hot region of a heat producing component; and
a condenser region coupled in thermal communication with said heat dissipation member, said dielectric two-phase heat transfer device fabricated from a dielectric material,
wherein the heat producing component comprises a secondary winding portion of a transformer assembly, the secondary winding portion further comprising:
an upper conductive secondary turn; and
a lower conductive secondary turn,
wherein the dielectric two-phase heat transfer device extends about 180 degrees around the upper conductive secondary turn and the lower conductive secondary turn opposite a plurality of leads.

US Pat. No. 10,366,816

SOLENOID DRIVE DEVICE

HONDA MOTOR CO., LTD., T...

1. A solenoid drive device comprising:a first solenoid drive circuit including a first solenoid, a first switching element configured to perform duty control of an application voltage of the first solenoid, and a first current detection element configured to detect a first drive current supplied to the first solenoid;
a second solenoid drive circuit including a second solenoid, a second switching element configured to perform duty control of an application voltage of the second solenoid, and a second current detection element configured to detect a second drive current supplied to the second solenoid; and
a control element configured to change the first drive current and the second drive current by performing on/off duty control of the first switching element and the second switching element,
wherein the solenoid drive device includes a selection circuit configured to select either one of a first current detection signal outputted from the first current detection element and a second current detection signal outputted from the second current detection element,
wherein the control element comprises:
a duty control element configured to supply a selection command signal selecting either one of the first current detection signal and the second current detection signal to the selection circuit, acquire values of the first drive current and the second drive current based on a selection detection signal outputted from the selection circuit, and perform the on/off duty control depending on the acquired values of the first drive current and the second drive current; and
a failure determination element configured to perform failure determination with the selection circuit, the first solenoid drive circuit, and the second solenoid drive circuit as determination targets based on change characteristics of the selection detection signal,
wherein the duty control element performs the on/off duty control of the first switching element in the same control cycle as on/off duty control of the second switching element, and sets on/off switching direction of the first switching element at a start time of one control cycle and on/off switching direction of the second switching element reversely from each other, the on/off switching direction including a switching direction from on to off and a switching direction from off to on, and
wherein the failure determination element performs the failure determination based on change characteristics of the selection detection signal in a specified period when on/off states of the first switching element and the second switching element are different from each other.

US Pat. No. 10,366,815

PERMANENT MAGNET DRIVE ON-LOAD TAP-CHANGING SWITCH

1. A permanent magnet drive on-load tap-changing switch, comprising:a changing switch circuit, the changing switch circuit comprising an odd-numbered tap-changing circuit and an even-numbered tap-changing circuit that are structurally identical;
the odd-numbered tap-changing circuit and the even-numbered tap-changing circuit comprising working contactors and dual-contact synchronous transition contactors consisting of primary contactors and secondary contactors;
the working contactors being connected to the primary contactors through trigger transmitters and transition resistors;
a primary contactor of a tap-changing circuit being connected to a secondary contactor of another tap-changing circuit through a high-voltage thyristor;
a trigger transmitter being configured to provide a trigger current to the high-voltage thyristor connected with the secondary contactor of a same tap-changing circuit, wherein:
the working contactors and the dual-contact synchronous transition contactors directly face moving contactors;
the moving contactors are connected in parallel to each other;
moving contactor permanent magnets are bijectively connected to the moving contactors;
the moving contactor permanent magnets directly face, on an other extremity thereof, a moving contactor driving mechanism, the moving contactor driving mechanism comprising a moving permanent magnet which moves to change a force acting on the moving contactor permanent magnets to allow the moving contactors to get contact with or depart from the working contactors and the dual-contact synchronous transition contactors.

US Pat. No. 10,366,814

PERMANENT MAGNET

TDK CORPORATION, Tokyo (...

1. A permanent magnet with a composition ratio of RXT(100-X-Y)CY comprising a main phase with Nd5Fe17 crystal structure, wherein:R is one or more rare earth elements including Sm, and the rare earth elements are Sm, Y, La, Pr, Ce, Nd, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu; and
T is one or more transition metal elements including Fe or a combination of Fe and Co; and
23.2?X(at %)?37.1, 6.0?Y(at %)?14.7, 1.51?(100-X-Y)/X?2.92.

US Pat. No. 10,366,813

HIGH-PRECISION ADDITIVE FORMATION OF ELECTRICAL RESISTORS

1. A method of forming an electrical resistor having a target electrical resistance by additive manufacturing comprising the steps of:forming an electrically resistive layer on a substrate;
measuring an electrical resistance-related parameter of the electrically resistive layer and determining from the electrical resistance-related parameter a target length of the electrically resistive layer corresponding to the target electrical resistance; and
forming a first electrically conductive terminal and a second electrically conductive terminal contacting the electrically resistive layer, said first and second electrically conductive terminals being separated by a distance corresponding to the target length, such that an electrical resistance of a portion of the electrically resistive layer extending between the first electrically conductive terminal and the second electrically conductive terminal corresponds to the target electrical resistance.

US Pat. No. 10,366,812

CONNECTION STRUCTURE OF SUPERCONDUCTING WIRES

Furukawa Electric Co., Lt...

1. A connection structure of superconducting wires comprising:a plurality of superconducting wires are overlapped and connected with each other, each of the plurality of superconducting wires including a substrate and a superconducting layer that are laminated, a non-superconductor being provided at a part of a surface of the superconducting layer of at least one of the superconducting wires and protruding from the surface,
wherein a part of the non-superconductor is embedded in the surface of the superconducting layer,
the superconducting layer has a multilayer structure including an uppermost superconducting layer and at least one superconducting layer other than the uppermost superconducting layer, the uppermost superconducting layer having a thickness greater than a thickness of the at least one superconducting layer other than the uppermost superconducting layer, and
the part of the non-superconductor is embedded in the uppermost superconducting layer and a remaining part of the non-superconductor is protruded from the surface of the superconducting layer.

US Pat. No. 10,366,811

PARALLEL PAIR CABLE

SUMITOMO ELECTRIC INDUSTR...

1. A parallel pair cable, comprising:a pair of insulated wires arranged to be in contact with each other, parallel to each other, and not twisted;
a first resin tape wrapped around the pair of insulated wires;
a shield tape comprising a metal layer longitudinally folded on the outside of the first resin tape;
a drain wire outside the shield tape, wherein the drain wire is arranged to be in electrical contact with the metal layer of the shield tape;
a jacket layer provided around the shield tape and the drain wire; and
a conductive tape helically wrapped on the outside of the shield tape,
wherein the drain wire is arranged on the outside of the conductive tape so that the drain wire is electrically connected to the conductive tape and the shield tape; and
wherein the jacket layer is provided around the conductive tape and the drain wire.

US Pat. No. 10,366,810

EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE

3M Innovative Properties ...

1. An electrical cable comprising:a plurality of substantially parallel conductors extending along a length, and arranged along a width, of the cable, each conductor substantially surrounded by a shield;
first and second layers disposed on opposite sides of the conductors, each layer folded along the length of the cable toward the other layer, the folds defining first portions of the first and second layers facing each other and comprising a longitudinal edge of the cable, and second portions of the first and second layers facing away from each other; and
a bonding material bonding the first portions of the first and second layers to each other along the length of the cable.

US Pat. No. 10,366,809

INSULATED WIRE, COIL, AND ELECTRIC OR ELECTRONIC EQUIPMENT

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire comprising a thermosetting resin layer on the outer periphery of a conductor, and a thermoplastic resin layer on the outer periphery of the thermosetting resin layer,wherein a total thickness of the thermosetting resin layer and the thermoplastic resin layer is 100 ?m or more and 250 ?m or less, and a degree of orientation of a thermoplastic resin in the thermoplastic resin layer, that is calculated by the following Formula 1, is 20% or more and 90% or less;
Formula 1 Degree of orientation H (%)=[(360??Wn)/360]×100
Wn: A half width of orientation peak in the azimuth angle intensity distribution curve by X-ray diffraction
n: the number of orientation peak at a ? angle of 0° or more and 360° or less.

US Pat. No. 10,366,808

HIGH-VOLTAGE APPARATUS AND METHOD FOR PRODUCING SAME

Siemens Aktiengesellschaf...

1. A high-voltage device, comprising:an internal conductor;
an insulating body surrounding said internal conductor along a longitudinal direction, said insulating body including:
insulating layers configured from a synthetic material that is impregnated with a resin; and
electrically conductive control inserts for providing field control, said electrically conductive control inserts being disposed in a concentric manner around said internal conductor and being spaced apart from one another by means of said insulating layers, at least one of said control inserts is a conductive base layer; and
a contact-making device, at least one of said control inserts is a contact insert that is connected in an electric manner to said internal conductor by means of said contact-making device, said contact-making device having a contact element configured from an electrically conductive material that is connected in an electrical manner to said contact insert, said contact element being fixed by means of an adhesive to said conductive base layer being in electrical contact with said internal conductor.

US Pat. No. 10,366,807

RESIN COMPOSITION FOR AUTOMOTIVE CABLE MATERIAL AND CABLE USING THE SAME

Hyundai Motor Company, S...

1. A resin composition comprising:a mixture of a base resin and a magnesium hydroxide flame retardant;
an antioxidant; and
a lubricant,
wherein the resin composition comprises an amount of about 2 to 5 parts by weight of the antioxidant and an amount of about 0.5 to 2 parts by weight of the lubricant with respect to 100 parts by weight of the mixture,
wherein the mixture comprises an amount of about 40 to 60% by weight of the base resin and an amount of about 60 to 40% by weight of the magnesium hydroxide flame retardant, based on the total weight of the mixture,
wherein a surface of the magnesium hydroxide flame retardant is treated with silane or aliphatic or polymeric fatty acid,
wherein the base resin comprises 100 parts by weight of a high crystalline polypropylene resin, an amount of about 5 to 10 parts by weight of a modified polypropylene and an amount of about 15 to 20 parts by weight of an elastomer,
wherein the high crystalline polypropylene resin comprises an amount of about 60 to 90% by weight of a high crystalline homo polypropylene resin and an amount of about 10 to 40% by weight of a high crystalline block polypropylene resin, based on the total weight of the high crystalline polypropylene resin, and
wherein the base resin further comprises maleic acid in an amount of about 0.1 to 3 parts by weight with respect to 100 parts by weight of the base resin; and an initiator.

US Pat. No. 10,366,806

VEHICLE ELECTRIC WIRE AND WIRE HARNESS USING THE SAME

YAZAKI CORPORATION, Mina...

1. A vehicle electric wire comprising:an electrical insulation coating layer which contains: a vinyl chloride resin; a plasticizer which includes one type or two or more types selected from a trimellitic acid plasticizer and a pyromellitic acid plasticizer; a compound containing a lanthanoid which is at least one of lanthanum oxide and lanthanum hydroxide; a stabilizer; and a filler; and
an electrical conductor which is coated with the electrical insulation coating layer,
wherein, in the electrical insulation coating layer, with respect to 100 parts by mass of the vinyl chloride resin, a content of the plasticizer is 25 to 49 parts by mass, a content of the stabilizer is 1 to 15 parts by mass, and a content of the compound containing the lanthanoid is 1 to 15 parts by mass, and
when dynamic viscoelasticity measurement using a dynamic viscoelasticity measurement device is performed on the electrical insulation coating layer at 0.5 Hz in frequency and under a temperature rise condition of 2° C./minute in temperature rise speed in a single cantilever measurement mode, a storage modulus at 140° C. is 0.1 MPa or more.

US Pat. No. 10,366,805

INSULATED WINDING WIRE ARTICLES HAVING CONFORMAL COATINGS

Essex Group, Inc., Fort ...

1. An article formed from an insulated winding wire, the article comprising:an insulated winding wire having a cross-sectional area greater than or equal to 0.823mm2 and formed into a predefined shape comprising at least one bend, the insulated winding wire comprising a conductor and insulation formed around the conductor, the insulation comprising at least one of polyimide or polyamideimide; and
a coating comprising parylene formed around the insulated winding wire, the parylene comprising at least one of parylene HT, parylene AF-4, or parylene F.

US Pat. No. 10,366,803

METAL OXIDE THIN FILM, METHOD FOR DEPOSITING METAL OXIDE THIN FILM AND DEVICE COMPRISING METAL OXIDE THIN FILM

Plansee SE, Reutte (AT)

1. A metal oxide thin film, comprising a film formed of ?-MoO3 having a monoclinic ?-MoO3 crystal structure and including at least one doping element selected from the group consisting of Re, Mn, and Ru.

US Pat. No. 10,366,802

COMPOSITIONS INCLUDING NANO-PARTICLES AND A NANO-STRUCTURED SUPPORT MATRIX AND METHODS OF PREPARATION AS REVERSIBLE HIGH CAPACITY ANODES IN ENERGY STORAGE SYSTEMS

1. A lithium-ion battery anode electrode, comprising:a current collector having a planar surface;
a plurality of a first nanomaterial selected from the group consisting of carbon nanotube, carbon nanowire, carbon nanorod and mixtures thereof, having a first end and a second end, the first end deposited on the planar surface of the current collector, each of said plurality of the first nanomaterial being vertically aligned with one another, perpendicular to the planar surface of the current collector, and exhibiting defined spacing between one another;
a plurality of a second nanomaterial deposited on a surface of each of the plurality of the first nanomaterial, the second nanomaterial composed of an element selected from the group consisting of metallic, metalloid, non-metallic and mixtures thereof, the second nanomaterial as-deposited in a form selected from the group consisting of nano-particle, nano-cluster, droplet and mixtures thereof, each of the plurality of the second nanomaterial exhibiting defined spacing between one another,
wherein the surface of the plurality of a first nanomaterial underlying the plurality of a second nanomaterial has excess amorphous carbon; and
an interfacial layer comprising the amorphous carbon, formed in-situ on the plurality of a first nanomaterial underlying said plurality of a second nanomaterial.

US Pat. No. 10,366,801

ELECTRIC CURRENT TRANSMISSION CABLE AND METHOD OF FABRICATING SUCH A CABLE

1. An electric current transmission cable comprising:a non-anodized bare conductor based on aluminum or an aluminum alloy, having a hydrophilic external specific surface configured to be in contact with the atmospheric environment, and an inside volume intended to conduct an electric current,
wherein the external specific surface of the bare conductor has a first roughness parameter, defined as the arithmetic mean deviation, measurable by profilometry, of peaks and valleys in comparison to a predetermined average profile over a reference length or surface, equal to or greater than 1.9 ?m, and
the inside volume of the bare conductor has oxygen doping of its aluminum-based or aluminum alloy-based components at a ratio equal to or greater than 20%, to a depth of at least 300 nm with respect to the external specific surface.

US Pat. No. 10,366,800

METHODS OF PROVIDING ELECTRICALLY-CONDUCTIVE SILVER

EASTMAN KODAK COMPANY, R...

18. A method for providing two or more electrically-conductive silver metal patterns, the method comprising:providing a continuous substrate having a first supporting side and a second opposing supporting side,
providing two or more photosensitive thin film patterns on two or more respective portions on the first supporting side of the continuous substrate from a solution of a photosensitive reducible silver ion-containing composition, comprising:
a) one or more non-hydroxylic-solvent soluble silver complexes, each comprising a reducible silver ion complexed with one or more ?-oxy carboxylates via one or more oxygen atoms and the same reducible silver ion is complexed with an oxime compound via a nitrogen atom,
each of the one or more non-hydroxylic-solvent soluble silver complexes being represented by the following formula (I):
(Ag+)a(L)b(P)c  (I)
wherein L represents the ?-oxy carboxylate; P represents the oxime compound; a is 1 or 2; b is 1 or 2; and c is 1, 2, 3, or 4, provided that when a is 1, b is 1, and when a is 2, b is 2,
solubilized in a b) solvent medium of one or more non-hydroxylic organic solvents; and
c) a photosensitizer that can either reduce the reducible silver ion or oxidize the ?-oxy carboxylate having a reduction potential;
photochemically converting reducible silver ions in each of the two or more photosensitive thin film patterns on the first supporting side of the continuous substrate to provide correspondingly two or more electrically-conductive silver metal-containing patterns on the first supporting side of the continuous substrate;
contacting each of the two or more electrically-conductive silver metal-containing patterns with water or an aqueous or non-aqueous salt solution;
optionally, contacting each of the two or more electrically-conductive silver metal-containing patterns with an aqueous or non-aqueous non-salt solution; and
optionally, drying each of the two or more electrically-conductive silver metal-containing patterns.

US Pat. No. 10,366,798

GARMENT WITH ELECTROMAGNETIC RADIATION SHIELDED POCKET

1. A garment that shields a wearer from electromagnetic radiation, the garment comprising:at least one first fabric forming a wearable garment, the at least one first fabric comprising a non-metallized fabric;
at least one pocketed area formed from a second fabric, the at least one pocketed area having at least a front side and a back side and defining an interior with the at least one pocketed area being coupled to the at least one first fabric;
a closure mechanism for selectively sealing an opening of the at least one pocketed area;
wherein the second fabric is configured to attenuate emission of electromagnetic radiation from the at least one pocketed area;
wherein the at least one pocketed area is lined with the second fabric; and
wherein the second fabric comprises about 70% to about 90% of a polyamide and about 10% to about 35% of an elastomer, with the second fabric being plated in silver, the silver having a purity of about 90% to about 99%.

US Pat. No. 10,366,797

SYSTEM AND METHOD FOR PREVENTING AND MONITORING LEAKAGE OF WATER FROM TANK LINER

Korea Atomic Energy Resea...

1. A system for preventing and monitoring a leakage of water from a tank liner at a storage tank, the system comprising:a concrete reservoir;
the tank liner made up of a wall liner that is formed by coupling a plurality of first panels and is attached to an inner wall of the concrete reservoir, and a floor liner that is formed by coupling a plurality of second panels, is attached to a floor of the concrete reservoir, and is coupled to the wall liner by welding;
a leaking water collecting plate formed by welding a plurality of third panels and inserted between the floor liner and the floor of the concrete reservoir; and
an edge leaking water collecting channel buried in an edge of the storage tank and configured to collect leaking water discharged between the floor liner and the leaking water collecting plate.

US Pat. No. 10,366,796

PASSIVE DEPRESSURIZATION SYSTEM FOR PRESSURIZED CONTAINERS

ASVAD INT, S.L., Tarrago...

1. A nuclear reactor comprising a depressurization system for a pressurized container, comprising a main valve which comprises:a pneumatic actuator, and
an opening spring,
wherein:
the main valve is configured to be fluidly connected at one side to a pressurized container in which contains a gas and at the other side to the atmosphere, and
the opening spring is adjusted to set a predetermined mechanical pressure such that when a pressure inside the pressurized container is bigger than the predetermined mechanical pressure, the main valve remains closed, and that when the pressure inside the pressurized container is lower than the predetermined mechanical pressure, the main valve opens to establish a fluid communication so as to allow the pressurized gas from the pressurized container be discharged into the atmosphere.

US Pat. No. 10,366,795

LONG-LIFE HIGH-EFFICIENCY NEUTRON GENERATOR

Starfire Industries LLC, ...

1. An extended lifetime system for generating neutrons comprising:an external enclosure;
an insulating dielectric contained within the external enclosure;
a high voltage power supply;
a target at a target location capable of being loaded with hydrogen isotopes selected from the group consisting of: deuterium and tritium;
an ion source assembly configured to supply a beam of ions, the ion source assembly comprising:
a vessel comprising a wall made from an insulator material and having a plasma source cavity containing a plasma source from which a plasma is generated;
an anode electrode, connected to the high voltage power supply, the anode electrode being configured to bias the plasma;
an external applicator that is:
electrically connected to an excitation signal source, and
configured to deposit electromagnetic energy into the plasma source cavity through electromagnetic fields passing through the wall made from an insulator material,
wherein the external applicator is selected from the group consisting of an RF antenna and a microwave launcher,
wherein an insulating gap comprising the insulating dielectric separates the external applicator and the plasma source cavity; and
a target electrode electrically coupled to the target
wherein the high voltage power supply is configured to deliver a voltage between the anode electrode and the target electrode between 10 kV and 500 kV.

US Pat. No. 10,366,794

RISK PROFILING USING PORTAL BASED SCANNERS

GlobalTrak, LLC, Sterlin...

1. A hierarchical scanning system for monitoring shipping containers within a transportation system having one or more shipping cranes, the system comprising:a portal-based scanner, wherein the portal-based scanner is deployed on a structure which handles shipping containers during short term events; wherein the portal-based scanner comprises a sensor to detect the presence of a shipping container; further wherein the portal-based scanner is configured to scan and detect container anomalies; wherein the portal-based scanner is attached to a shipping crane;
a data fusion center, wherein the data fusion center is configured to receive data detected by the portal-based scanner; further wherein the data fusion center is further configured to collect and consolidate information from a plurality of additional portal-based scanners;
a first receiver, wherein the first receiver is configured to receive data from the portal-based scanner;
a processing element for identifying anomalies;
a decision module for generating an alert message containing data regarding identified anomalies; and
a first transmitter, wherein the first transmitter is configured to transmit an alert signal comprising the alert message;
wherein the data fusion center is configured to receive initial manifest data regarding the shipping container;
further wherein the initial manifest data comprises data regarding the container inventory and the container itinerary;
wherein the portal-based scanner is configured to gather data about the container in a short-term interaction and to transmit the data to the data fusion center;
wherein the data fusion center is configured to create a risk profile for the container based on data collected during the short-term interaction;
wherein the processing element is configured to compare the risk profile to at least one risk profile from a previous short-term interaction to identify anomalies.

US Pat. No. 10,366,792

SYSTEM AND METHOD FOR DETECTING RETINA DISEASE

Bio-Tree Systems, Inc., ...

1. A method of diagnosing disease in a retina, comprising:collecting a plurality of images of the retina;
processing the plurality of images to create a 3D computer model, where blood vessels are modelled as a series of stacked disks;
dividing the 3D model into a plurality of equally sized volumes;
determining a vascular density in each equally sized volume based on a number of disks in each equally sized volume; and
analyzing the vascular density in at least a portion of the equally sized volumes to determine the presence of a disease, wherein the portion of equally sized volumes comprises all equally sized volumes that are disposed in one plane.

US Pat. No. 10,366,791

METHOD AND SYSTEM FOR GLOBAL EPIDEMIC DISEASE OUTBREAK PREDICTION

EMC IP Holding Company LL...

1. A method comprising:receiving a request from a given user to predict disease outbreak information for a given location and a given time;
obtaining, from a plurality of data sources, a first set of disease outbreak patterns for the given location and the given time;
assigning weights to one or more reported diseases in the first set of disease outbreak patterns for the given location, the weights being based at least in part on an authenticity of one or more of the plurality of data sources from which data regarding the one or more reported diseases is obtained;
obtaining a second set of disease outbreak patterns for the given location at one or more historic time periods;
assigning weights to one or more reported diseases in the second set of disease outbreak patterns based at least in part on determining whether data in the second set of disease outbreak patterns correlates with data in the first set of disease outbreak patterns;
obtaining a set of personalized trends for the given user;
assigning weights to the set of personalized trends based at least in part on determining whether user profile attributes in the set of personalized trends correlate with the first set of disease outbreak patterns and the second set of disease outbreak patterns; and
generating at least one personalized alert for the given user based on the assigned weights for the first set of disease outbreak patterns, the second set of disease outbreak patterns, and the set of personalized trends; and
delivering the at least one personalized alert to a computing device associated with the given user over at least one network;
wherein the method is performed by at least one processing device comprising a processor coupled to a memory.

US Pat. No. 10,366,790

PATIENT SAFETY PROCESSOR

Lawrence A. Lynn, Columb...

1. A patient monitoring system for monitoring, in real time, a plurality of patients in a hospital system to detect the development of sepsis cascades and for identifying the patients developing the sepsis cascade, the system comprising:a plurality of local patient safety monitors, each of the plurality of local patient safety monitors configured to receive physiological measurements from at least one of a pulse oximeter or a blood pressure monitor for the plurality of patients,
a central patient safety monitor remote from the plurality of local patient safety monitors, the central patient safety monitor having a processor and memory storing instructions that, when executed by the processor, cause the system to:
receive the physiological measurements from the plurality of local patient safety monitors, and store the physiological measures in an electronic medical record;
receive the electronic medical records relating to the plurality of patients;
convert the electronic medical record into trend data, wherein the trend data is sequential, and wherein the trend data comprises information indicative of trends in physiologic parameters and laboratory data over time;
detect relational trends based on the trend data, the relational trends comprising positive or negative trends;
continuously search for and detect a sepsis cascade pattern associated with the relational trends occurring in at least one of the plurality of patients;
identify the at least one patient generating a sepsis cascade pattern detected in the continuous search;
automatically trigger, in response to the identification of the sepsis cascade pattern, generation of a real-time image of the sepsis cascade pattern at the central patient safety monitor;
compare the sepsis cascade pattern to a pattern definition to determine one or more characteristics of the sepsis cascade pattern; and
output the real-time image of the sepsis cascade pattern, an indication of the one or more characteristics of the sepsis cascade pattern, and the identity of the at least one patient to at least a display device of the central patient safety monitor by
generating a graphical display having viewing regions corresponding to physiologic systems of the patient, wherein the viewing regions include at least an inflammatory region, wherein the viewing regions are configured so that the sepsis cascade pattern is displayed such that the sepsis cascade pattern is viewable spreading over time within at least the inflammation region, and generating indications of the one or more characteristics of the cascade pattern on the graphical display, and
configuring the viewing regions so that sepsis cascade pattern is displayed as spreading within and/or across the viewing regions as the severity of the cascade patterns progress over time, such that the sepsis cascade is viewable progressively spreading over time from the origin of the sepsis cascade to the termination of the sepsis cascade, and the viewing regions are configured so that the sepsis cascade spreads along at least one axis and at least partially across the graphical display over time.

US Pat. No. 10,366,788

ADMINISTRATION SET DETECTION AND AUTHENTICATION USING CAM PROFILES

Curlin Medical Inc., Eas...

1. An administration set of a predetermined type for use with an infusion pump to administer a specified infusion protocol to a patient, wherein the predetermined type is chosen from a plurality of different administration set types, and wherein the infusion pump includes a follower, the administration set comprising:tubing for conveying an infusion liquid; and
a free-flow prevention device operable to selectively stop and permit flow of the infusion liquid through the tubing;
wherein the free-flow prevention device includes a carrier and a plunger movable relative to the carrier between an open position permitting flow of the infusion liquid through the tubing and a closed position stopping flow of the infusion liquid through the tubing, the plunger being biased toward the closed position and having a cam surface defining an uneven profile along a direction of movement of the plunger;
wherein the cam surface is exposed through a slot in the carrier and is slidably engageable by the follower, and the cam surface profile is configured to displace the follower in an elevation direction orthogonal to the direction of movement of the plunger as the plunger is moved from the closed position to the open position;
wherein the cam surface profile indicates the administration set is authorized for use with the infusion pump.

US Pat. No. 10,366,787

PHYSIOLOGICAL ALARM THRESHOLD DETERMINATION

MASIMO CORPORATION, Irvi...

1. A method of reducing nuisance alarms for a physiological parameter by determining an alarm threshold optimized for a specific care unit, the care unit including a plurality of patients being monitored for the physiological parameter, the method comprising:in the care unit, electronically measuring patient specific physiological parameters for the plurality of patients using a plurality of patient monitors;
electronically providing the patient specific physiological parameters to a threshold recommendation system;
receiving at least one recommended parameter specific alarm threshold value, said value responsive to a number of alarms triggered by said patient specific physiological parameters at said at least one recommended parameter specific alarm threshold value;
said at least one recommended parameter specific alarm threshold value calculated to reduce said number of alarms at said care center for said parameter by determining how many alarms are generated for each of a range of threshold values and choosing a threshold value from the range of threshold values that reduces a number of alarms; and
programming at least one of said plurality of patient monitors with a threshold value incorporating information gained by said suggested threshold value.

US Pat. No. 10,366,786

METHODS, SYSTEMS, AND PRODUCTS FOR FORMAT CONVERSION

1. A method, comprising:receiving, by a server, an electronic healthcare record associated with a recipient address;
comparing, by the server, the recipient address to addresses registered with a reformatting service that reformats the electronic healthcare record;
determining, by the server, that the recipient address is associated with the reformatting service;
executing, by the server, the reformatting service in response to the determining that the recipient address is associated with the reformatting service, the reformatting service generating a reformatted electronic healthcare record; and
sending, from the server, the reformatted electronic healthcare record to the recipient address.

US Pat. No. 10,366,783

IMAGING EXAMINATION PROTOCOL UPDATE RECOMMENDER

KONINKLIJKE PHILIPS N.V.,...

1. A system, comprising:a data repository configured to store a plurality of images;
a viewing station comprising:
a display monitor configured to visually present a displayed image, wherein the displayed image is selected from the plurality of images and corresponds to a scan, wherein the scan is within an electronically stored examination protocol;
at least one sensor configured evaluate a plurality of radiologist interactions reading the displayed image and to generate an output based on the evaluated radiologist interaction with the displayed image, wherein the at least one sensor is selected from the group consisting of:
a visual sensor configured to track movement of the radiologist viewing the displayed image;
an audio sensor configured to record audio uttered by the radiologist; and
an input device sensor configured to sense inputs corresponding to the displayed image; and
a computing device comprising:
a processor; and
a memory encoded with computer readable instructions which when executed by the processor cause the processor to:
determine at least one statistic based on the generated output; and
in response to determining the at least one statistic satisfies a predetermined threshold, remove the scan that corresponds to the displayed image from the examination protocol.

US Pat. No. 10,366,781

MAPPING AND DISPLAY FOR EVIDENCE BASED PERFORMANCE ASSESSMENT

IQVIA Inc., Parsippany, ...

1. A computer-implemented method for organizing clinical trial data executed by one or more processors, the method comprising:obtaining, by the one or more processors of a server system and from a selectable record in an aggregate database of the server system, identities of a plurality of investigators and data representing a set of attributes associated with each of the plurality of investigators from a first data set and a second data set, wherein:
the first data set containing proprietary data associated with at least one of the investigators and received from a first set of databases,
the second data set containing third-party data associated with at least one of the investigators and received from a second set of databases that is different from the first set of databases, and
the selectable record enables the one or more processors to perform one or more adjustments to data of the identities of the plurality of investigators included within the aggregate database in a first time period that is shorter than a second time period for performing the one or more adjustments on data of the identities of the plurality of investigators included within the first set of databases and the second set of databases but not stored within the aggregate database;
receiving, by the one or more processors and from a computing device, a user input indicating a subset of attributes from the set of attributes associated with each of the plurality of investigators;
generating, by the one or more processors, a multi-dimensional chart that organizes the identities of the plurality of investigators based on the subset of attributes and a user designation of selected dimensions to reflect two or more of attributes from the subset of attributes, the multi-dimensional chart comprising:
a first dimension representing a first attribute from the subset of attributes;
a second dimension representing a second attribute from the subset of attributes; and
a plurality of icons,
each icon representing an identity of one of the plurality of investigators,
wherein each icon is positioned on the multidimensional chart along the first dimension according to a value of the first attribute associated with the represented identity and along the second dimension according to a value of the second attribute of the represented identity, and
wherein a graphical property of each icon represents a value of a third attribute of the represented identity;
linking, by the one or more processors, each icon included in the plurality of icons to the selectable record in the aggregate database so that user interactions with icons included in the plurality of icons by the computing device cause one or more attributes associated with the icons included in the plurality of icons to be altered within the aggregate database;
providing, by the one or more processors and for display on the computing device, a graphical user interface (GUI) including the multi-dimensional chart and a clinical trial roster;
receiving, by the one or more processors and from the computing device, a user selection of one or more icons from among the plurality of icons for inclusion in a clinical trial;
in response to receiving the user selection:
adding, by the one or more processors, identities of investigators represented by the one or more selected icons to the clinical trial roster;
updating, by the one or more processors, the selectable record to reflect that the identities of investigators represented by the one or more selected icons have been added to the clinical trial roster; and
updating, by the one or more processors and based on linking each icon included in the plurality of icons to the selectable record in the aggregate database, one or more attributes in the selectable record that are associated with the one or more selected icons.

US Pat. No. 10,366,780

PREDICTIVE PATIENT TO MEDICAL TREATMENT MATCHING SYSTEM AND METHOD

ELLIGO HEALTH RESEARCH, I...

1. A method for matching patients with a specific medical treatment comprising:receiving specified information about a specific medical treatment from a company looking for potential candidates for said specific medical treatment at a server, wherein said specified information about said specific medical treatment is determined by a software application residing on said server and provided by said company over a network by said company's system;
accessing said specified information about said specific medical treatment on said server by the administrator of said server, wherein said administrator approves said specified information about said specific medical treatment and thereinafter creates a medical treatment specific query record based on said specified information about said specific medical treatment that includes inclusion and exclusion criteria, a medical treatment specific patient screening survey record based on said specified information about said specific medical treatment, a medical treatment specific physician consultation questionnaire record based on said specified information about said specific medical treatment, a medical treatment specific patient information record based on said specified information about said specific medical treatment, and a medical treatment specific physician information record based on said specified information about said specific medical treatment;
browsing said medical treatment specific physician information records using a browser connected to the system of a referring physician's office to connect to said server through said network, wherein said system of a referring physician's office includes a patient database;
selecting at least one said specific medical treatment;
launching an applet from said server, wherein said applet runs in said browser, connects to said patient database, and accesses said medical treatment specific query record relating to said selected medical treatment;
using the medical treatment specific query record, querying said patient database, wherein said applet runs said medical treatment specific query and compares patient records in said patient database with said inclusion and exclusion criteria of said medical treatment specific query, returning said patient records from said patient database that match said inclusion and exclusion criteria of said medical treatment specific query through said network to said server and storing said patient records on said server;
comparing said patient record with said medical treatment specific patient screening survey record and said medical treatment specific physician consultation questionnaire record and completing fields in said medical treatment specific patient screening survey record and said medical treatment specific physician consultation questionnaire record that match information from said patient record;
contacting a patient associated with said patient records stored on said server by accessing said patient records through said network on said system of referring physician's office, wherein said referring physician's office contacts said patient to inquire whether said patient is interested in learning more about said medical treatment, wherein if said patient declines, said patient record is updated by said referring physician's office through said network using said system of referring physician's office, wherein if said patient accepts, said patient is transferred to an interactive voice response system connected to said server;
completing the medical treatment specific patient screening survey, wherein said interactive voice response system accesses said medical treatment specific patient screening survey record and asks said patient unmatched questions from said medical treatment specific patient screening survey, wherein said patient answers said unmatched questions and said answers are sent through said interactive voice response system to said server, wherein said medical treatment specific patient screening survey record and said medical treatment specific physician consultation questionnaire record are updated and stored on said server;
scoring answers in said medical treatment specific patient screening survey record using said software application and scheduling said patient that has a predetermined minimum score for a consultation with said referring physician's office;
completing the medical treatment specific physician consultation questionnaire record, wherein said patient visits said referring physician's office and personnel from said referring physician's office accesses said medical treatment specific physician consultation questionnaire record using a browser connected to said system of said referring physician's office to connect to said server through said network, wherein said personnel completes answers to said medical treatment physician consultation questionnaire and sends those answers to said server using a browser connected to the system of a referring physician's office to connect to said server through said network, wherein said medical treatment specific physician consultation questionnaire record is updated and stored on said server; and
sending said patient record to said company looking for potential candidates for said specific medical treatment using said software application.

US Pat. No. 10,366,779

SCHEME OF NEW MATERIALS

International Business Ma...

1. A method for predicting and designing chemical structures, comprising:receiving, at a user interface, intended structural feature values in vector form;
receiving, at the user interface, intended chemical property values in vector form;
compressing, by a hardware processor, the vector form of the intended structural feature values into a scalar form of the intended structural feature values;
constructing, by the hardware processor, a prediction model, wherein the prediction model predicts other structural feature values in scalar form from the scalar form of the intended structural feature values and the vector form of the intended chemical property values;
automatically configuring, by the hardware processor, at least one chemical structure candidate from the other structural feature values in vector form;
evaluating the at least one chemical structure candidate to determine structural feature values and chemical property values of the at least one chemical structure candidate; and
designing at least one chemical structure for constructing at least one chemical material, including performing, by the hardware processor, machine learning based on the determined structural feature values and the determined chemical property values of the at least one chemical structure candidate.

US Pat. No. 10,366,778

METHOD AND DEVICE FOR PROCESSING CONTENT BASED ON BIO-SIGNALS

SAMSUNG ELECTRONICS CO., ...

1. A method of processing content based on at least one bio-signal, the method comprising:outputting a content including at least one from among audio content and image content;
acquiring information related to the at least one bio-signal of a user with respect to the content;
determining a parameter for processing of the content, based on the acquired information related to the at least one bio-signal;
processing the content, based on the determined parameter;
outputting the processed content;
determining a concentration level of the user based on the at least one bio-signal;
obtaining information related to the content while the determined concentration level of the user is less than a reference point; and
providing to the user the obtained information related to the content if the concentration level of the user is greater than or equal to the reference point, or according to a user's input.

US Pat. No. 10,366,775

MEMORY DEVICE USING LEVELS OF DYNAMIC REDUNDANCY REGISTERS FOR WRITING A DATA WORD THAT FAILED A WRITE OPERATION

SPIN MEMORY, INC., Fremo...

1. A memory device comprising:a memory array of memory cells, wherein the memory array is configured to store a data word at one of a plurality of memory addresses;
a first level dynamic redundancy buffer comprising data storage elements; and
a pipeline coupled to the memory array and the first level dynamic redundancy buffer, wherein the pipeline is configured to:
write a data word into the memory array at a selected one of the plurality of memory addresses;
verify the data word written into the memory array to determine whether the data word was successfully written by the write;
responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy buffer; and
attempt to re-write the data word stored in the first level dynamic redundancy buffer into the memory array at the selected one of the plurality of memory addresses.

US Pat. No. 10,366,774

DEVICE WITH DYNAMIC REDUNDANCY REGISTERS

Spin Memory, Inc., Fremo...

1. A method of writing data into a memory device, the method comprising:writing a data word into a memory bank at a selected one of a plurality of memory addresses, wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) memory cells, wherein each memory cell is arranged to store a data word at one of a plurality of memory addresses;
verifying the data word written into the memory bank to determine whether the data word was successfully written thereto; and
responsive to a determination that the data word was not successfully written, performing:
writing the data word and the selected one of the plurality of memory addresses into a first level dynamic redundancy register; and
re-writing the data word stored in the first level dynamic redundancy register into the memory bank at the selected one of the plurality of memory addresses.

US Pat. No. 10,366,773

E-FUSE CIRCUIT

SK hynix Inc., Icheon-si...

1. An electrical fuse (E-fuse) circuit comprising:a boot-up controller configured to generate at least one fuse address and a sensing enable signal based on a boot-up signal;
an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and output fuse data having defect fusing information of the plurality of fuse sets when a word line corresponding to the fuse address is activated;
a fail controller configured to detect failed data from the fuse data, and activate a failed signal when the failed data is detected wherein the failed data is defect of an E-fuse included in the plurality of fuse sets; and
a failed address storage circuit configured to store a failed address corresponding to a fuse-set in which a defect is detected from among the fuse addresses when the failed signal is activated,
wherein the defect fusing information indicates that a failed part has occurred in the E-fuse of the fuse set resulting in the occurrence of the failed data,
wherein the fail controller includes:
a fail processor configured to activate a masking control signal when the failed data is detected from the fuse data; and
a failed signal generator configured to generate the failed signal based on the masking control signal during activation of a test signal.

US Pat. No. 10,366,772

SYSTEMS AND METHODS FOR TESTING A SEMICONDUCTOR MEMORY DEVICE HAVING A REFERENCE MEMORY ARRAY

Micron Technology, Inc., ...

1. An apparatus comprising:a first memory cell array comprising a first bit-line and a plurality of normal word lines coupled to the first bit-line;
a second memory cell array comprising a second bit-line and a plurality of dummy word lines coupled to the second hit-line, the number of dummy word lines being smaller than that of the normal word lines;
a sense amplifier coupled to the first bit-line and a first end of the second bit-line;
a first word decoder configured to activate one of the plurality of normal word lines during a memory access operation to a memory cell coupled to the one of the plurality of normal word lines;
a second word decoder configured to activate two or more of the plurality of dummy word lines during the memory access operation and further configured to operate selected ones of the plurality of dummy word lines responsive to a first test signal; and
a transistor coupled to a second end of the second bit-line and operated by a second test signal.

US Pat. No. 10,366,771

CONTROLLER, MEMORY SYSTEM, AND BLOCK MANAGEMENT METHOD FOR NAND FLASH MEMORY USING THE SAME

Toshiba Memory Corporatio...

1. A memory system comprising:a nonvolatile memory including a plurality of physical blocks; and
a controller circuit electrically connected to the nonvolatile memory, and configured to manage a plurality of logical blocks each of which includes a respective set of physical blocks among the plurality of physical blocks, and execute an erase operation in units of logical blocks, wherein
the controller circuit is configured to:
monitor at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among the plurality of logical blocks;
disassemble the first logical block among the plurality of logical blocks, the disassembling including de-allocating the physical blocks included in the first logical block to join a pool of de-allocated physical blocks, the pool of de-allocated physical blocks being a subset of the plurality of physical blocks, when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range specified by a first threshold value, and the second physical block having an erasing time length or a programming time length falling outside the first range;
select, from the pool of de-allocated physical blocks, physical blocks having erasing time lengths or programming time lengths belonging to a same time length range;
assemble a new logical block with the selected physical blocks; and
execute, on the basis of an erasing time length or a programming time length corresponding to each of the plurality of logical blocks, wear leveling to level erasing time lengths or programming time lengths of the plurality of logical blocks.

US Pat. No. 10,366,770

BIT ERROR RATE ESTIMATION FOR NAND FLASH MEMORY

Toshiba Memory Corporatio...

1. A method comprising:performing a program operation on a multi-level cell flash memory having a plurality of threshold voltages;
for each threshold voltage:
programming a state immediately greater than the threshold voltage,
defining at least one verify threshold value,
determining a first number of cells having voltage less than the at least one verify threshold value, and
determining an estimated under-programmed bit error rate (BER) based on the first number of cells and a first BER threshold value; and
determining an overall under-programmed BER based on the estimated under-programmed BER for each threshold voltage of the plurality of threshold voltages.

US Pat. No. 10,366,769

NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD FOR FAST AND SLOW CELLS THEREOF

Samsung Electronics Co., ...

1. A programming method of a nonvolatile memory device, the method comprising the steps of:a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, based on threshold voltages from among the plurality of first memory cells, a first fast memory cell and a first slow memory cell;
a second programming loop including applying a first program pulse to the first fast memory cell and the first slow memory cell, and applying a second program pulse to the first slow memory cell and a plurality of second memory cells, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop; and
a third programming loop, and
wherein the plurality of second memory cells have a target threshold voltage greater than the first target threshold voltage.

US Pat. No. 10,366,768

MEMORY DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An operating method of a memory device, comprising:increasing a voltage applied to channels of non-selected strings during a program operation according to an increase of at least one of a target voltage, a verify voltage, and a program time of the program operation; and
programming selected memory cells based on the increased voltage.

US Pat. No. 10,366,767

MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS

Micron Technology, Inc., ...

1. A memory device, comprising:an array of memory cells; and
circuitry for control and/or access of the array of memory cells, the circuitry configured to perform a method comprising:
bringing a selected access line of a program operation to a first voltage;
applying a particular voltage to an unselected access line of the program operation;
while applying the particular voltage to the unselected access line and after bringing the selected access line to the first voltage, sensing a current of the selected access line while applying a reference current to the selected access line;
indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current; and
proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.

US Pat. No. 10,366,766

POWER SHAPING AND PEAK POWER REDUCTION BY DATA TRANSFER THROTTLING

WESTERN DIGITAL TECHNOLOG...

1. An arrangement, comprising:a device configured to transmit and receive data from a host, the device comprising:
a device controller configured to interact with at least a memory array; and
a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold; and
an internal counter configured to increment for an amount of the bandwidth to be consumed, wherein any consumed bandwidth is decremented by the internal counter when a read/write command is issued.

US Pat. No. 10,366,765

ADJUSTMENT CIRCUIT FOR PARTITIONED MEMORY BLOCK

Taiwan Semiconductor Manu...

1. An adjustment circuit comprising:a controller circuit configured to output a control signal that indicates a memory type;
a timer circuit configured to output a timing signal for a read memory operation based on the control signal;
a temperature adaptive reference (TAR) generator configured to adjust a verify reference current for a verify memory operation based on temperature, wherein the verify reference current is set based on the control signal; and
an amplifier circuit configured to:
receive the timing signal, the verify current, and a current provided by a memory cell, wherein the amplifier circuit outputs a signal based on the timing signal, the verify current, and the memory cell current.

US Pat. No. 10,366,763

BLOCK READ COUNT VOLTAGE ADJUSTMENT

Micron Technology, Inc., ...

1. A NAND memory device comprising:a NAND memory array including a first pool of memory;
a controller executing instructions and performing operations comprising:
receiving a command from a host to read a value of at least one cell from the first pool of memory;
determining a read voltage to apply to the at least one cell by adding a first offset value to a base read voltage, the first offset value calculated as a stepwise function of a count of a number of previous reads during a period of time to a group of cells, the group of cells including the at least one cell; and
applying the read voltage to the at least one cell.

US Pat. No. 10,366,762

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a cell string including a plurality of memory cells coupled in series between a common source line and a bit line;
a common source line controller configured to provide a channel current to the cell string through the common source line in a read operation; and
a page buffer configured to sense data stored in a selected memory cell among the plurality of memory cells based on a current of the bit line when the channel current is provided,
wherein the common source line controller precharges the bit line with the channel current supplied to the cell string through the common source line,
wherein, after the bit line is precharged, the page buffer senses the data stored in the selected memory cell based on a voltage of the bit line transmitted to a sensing node.

US Pat. No. 10,366,760

NAND FLASH MEMORY WITH WORLDLINE VOLTAGE COMPENSATION USING COMPENSATED TEMPERATURE COEFFICIENTS

GigaDevice Semiconductor ...

1. A NAND flash memory with wordline voltage compensate, comprising:a plurality of wordlines, wherein each of the plurality of wordlines corresponds to a wordline voltage with a compensated temperature coefficient, wherein the plurality of wordlines are divided into a plurality of groups, each group corresponds to the compensated temperature coefficient, wherein the each wordline corresponds to a wordline address, and the groups of wordlines are divided by at least a border according to wordline addresses;
wherein the NAND flash memory further comprises a power-on read block storing a border enable parameter for enabling or disabling the compensated temperature coefficient.

US Pat. No. 10,366,759

MEMORY DEVICES HAVING SELECTIVELY ELECTRICALLY CONNECTED DATA LINES

Micron Technology, Inc., ...

11. A memory device, comprising:a first string of memory cells selectively connected to a first data line;
a second string of memory cells selectively connected to a second data line;
a first transistor connected in series with the first data line; and
a second transistor connected in series with the second data line and the first transistor;
wherein the first string is connected between a third transistor that selectively connects the first string to a first source and a fourth transistor that selectively connects the first string to the first data line, and wherein the second string is connected between a fifth transistor that selectively connects the second string to a second source and a sixth transistor that selectively connects the second string to the second data line.

US Pat. No. 10,366,758

STORAGE DEVICE AND STORAGE METHOD

RENESAS ELECTRONICS CORPO...

1. A storage device, comprising:a write circuit;
a data memory circuit configured to include a pair of first flash memory cells to be read by a complementary read mode, where complementary 1-bit data is stored in the pair of first flash memory cells by the write circuit; and
a status memory circuit configured to include a plurality of second flash memory cells to be read by a reference read mode, where a status flag is stored in the flash memory cell by the write circuit,
wherein the write circuit is configured to write the complementary 1-bit data to each of the pair of first flash memory cells, and to write the status flag of a same value to each respective second flash memory cell, the status flag indicating a data write status of the first flash memory cells, and
wherein the storage device further comprises a determination circuit configured to determine a value of the status flag by comparing a sum current of currents flowing through the plurality of second flash memory cells with a reference current.

US Pat. No. 10,366,757

COMPACT NON-VOLATILE MEMORY DEVICE

STMicroelectronics (Rouss...

1. A method of erasing a memory cell, the method comprising:applying a first voltage to a control gate of the memory cell, wherein the control gate is disposed over and insulated from a floating gate of the memory cell, wherein the floating gate comprises an embedded portion disposed over and insulated from a selection gate of the memory cell, wherein the embedded portion of the floating gate is located between a first substrate region of a semiconductor substrate and a second substrate region of the semiconductor substrate, wherein the floating gate further comprises a projecting portion extending out of the semiconductor substrate and disposed over the embedded portion of the floating gate and below the control gate, wherein the selection gate is embedded in the semiconductor substrate and below the embedded portion of the floating gate, wherein the selection gate is located between the first substrate region of the semiconductor substrate and the second substrate region of the semiconductor substrate, wherein the semiconductor substrate further comprises a source region disposed below the selection gate, the first substrate region of the semiconductor substrate, and the second substrate region of the semiconductor substrate;
applying a second voltage to the first substrate region of the semiconductor substrate; and
applying a third voltage to the second substrate region of the semiconductor substrate, wherein the third voltage is different from the second voltage, wherein a potential difference between the second voltage and the first voltage is greater than an erasure threshold of the memory cell so as to perform an erasing operation on the memory cell.

US Pat. No. 10,366,756

CONTROL CIRCUIT USED FOR TERNARY CONTENT-ADDRESSABLE MEMORY WITH TWO LOGIC UNITS

UNITED MICROELECTRONICS C...

1. A control circuit for a ternary content-addressable memory comprising:a first logic unit comprising:
a first terminal coupled to a data access terminal of a first storage unit and configured to access a first storage voltage;
a second terminal coupled to a data access terminal of a second storage unit and configured to access a second storage voltage;
a third terminal coupled to a first search line;
a fourth terminal coupled to a second search line;
a fifth terminal coupled to a reference voltage terminal; and
a sixth terminal coupled to a match line; and
a second logic unit comprising:
a first terminal coupled to the data access terminal of the first storage unit;
a second terminal coupled to the data access terminal of the second storage unit;
a third terminal coupled to the first search line;
a fourth terminal coupled to the second search line;
a fifth terminal coupled to a first power supply line; and
a sixth terminal coupled to a second power supply line;
wherein when a first search voltage of the first search line and a second search voltage of the second search line match the first storage voltage and the second storage voltage, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

US Pat. No. 10,366,755

SEMICONDUCTOR DEVICE INCLUDING TCAM CELL ARRAYS CAPABLE OF SKIPPING TCAM-CELL SEARCH IN RESPONSE TO CONTROL SIGNAL

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a plurality of sub-arrays, each of the sub-arrays including:
a plurality of TCAM (Ternary Content Addressable Memory) cells arranged in rows and columns;
a plurality of search line pairs respectively connected to ones of the TCAM cells arranged in the columns;
a plurality of match lines respectively connected to ones of the TCAM cells arranged in the rows;
a search line driver unit driving the search line pairs in response to a search line enable signal;
a plurality of match amplifier units, each connected to a corresponding one of the match lines and configured to output a search result according to a potential of the corresponding one of the match lines;
a register; and
a control logic unit generating the search line enable signal based on a search command and register data in the register,
wherein the register data indicates whether or not data stored in all the TCAM cells have a don't care value.

US Pat. No. 10,366,754

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED POWER CONSUMPTION

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit including a content addressable memory device, comprising:a memory cell array including:
a first memory cell containing a first part of entry data and a second memory cell containing a second part of the entry data;
a first match line and a second match line coupled to the first memory cell and the second memory cell, respectively; and
a first search line carrying a first part of search data and a second search line carrying a second part of the search data, the first search line and the second search line being coupled to the first memory cell and the second memory cell, respectively;
an equalizer circuit disposed between the first match line and the second match line;
a first precharge circuit being coupled to the first match line, and precharging the first match line to a first potential; and
a second precharge circuit being coupled to the second match line, and precharging the second match line to a second potential different from the first potential,
wherein the first memory cell includes a first comparator circuit comparing the first part of the search data supplied through the first search line and the first part of the entry data,
wherein the second memory cell includes a second comparator circuit comparing the second part of the search data supplied through the second search line and the second part of the entry data,
wherein the equalizer circuit couples, in accordance with a control signal, the first match line and the second match line after the first match line and the second match line are precharged, and
wherein the first search line and the second search line are each supplied with a search signal based on a valid data at the same time as the first match line and the second match line are coupled by the equalizer circuit.

US Pat. No. 10,366,753

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Arm Limited, Cambridge (...

1. A method, comprising:selectively connecting or disconnecting one or more portions of an integrated circuit to one or more other portions of the integrated circuit at least in part by selectively applying a programming voltage to one or more correlated electron switch devices to cause a transition in the one or more correlated electron switch devices from a first impedance state to a second impedance state, wherein the one or more correlated electron switch devices are respectively positioned between one or more electrodes of a first metallization layer and one or more electrodes of a second metallization layer.

US Pat. No. 10,366,752

PROGRAMMING FOR ELECTRONIC MEMORIES

1. Memory circuitry comprising:a memory cell having a first terminal and a second terminal, the circuitry further comprising a feedback path between said first terminal and said second terminal,
wherein said feedback path is configured to compensate for a slowdown in a resistance transition caused by non-linearity within said memory cell, and thereby brings about a linear state transition within said memory cell between respective memory states, and
wherein said feedback path comprises an operational amplifier and is configured to connect said memory cell in a negative feedback configuration.

US Pat. No. 10,366,751

RESISTANCE MEMORY CELL

Hefei Reliance Memory Lim...

1. A resistance memory cell, comprising:an inert electrode;
an active electrode; and
an electrolyte layer between the active electrode and the inert electrode, and adjacent the active electrode; and
a two-terminal access device adjacent one of the inert electrode and the active electrode, but not between the electrolyte layer and the active electrode;
wherein:
application of a set pulse having a set polarity to the resistance memory cell sets the resistance memory cell to a low-resistance state that is retained after application of the set pulse, and application of a reset pulse having a reset polarity to the resistance memory cell resets the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, the set polarity being opposite to the reset polarity;
application of a read pulse of the reset polarity determines the resistance state of the resistance memory cell;
the two-terminal access device is configured to enable a bi-directional flow of current through the resistance memory cell in response to application of a voltage greater than a threshold voltage;
application of the read pulse of the reset polarity produces a read current having a larger read current ratio between the low-resistance state and the high-resistance state than application of a read pulse of the set polarity; and
the read pulse of the reset polarity is smaller in magnitude than the reset pulse.

US Pat. No. 10,366,750

NONVOLATILE MEMORY DEVICE

Winbond Electronics Corp....

1. A semiconductor memory device, comprising:a memory array, configured to storing data by a reversible and nonvolatile variable resistance element;
an erasure unit, wherein when erasing a selected block of the memory array in response to an external erasure command, the erasure unit configured to set a first flag data indicating whether the selected block is in an erasure state without changing the data in the selected block;
a reading unit, wherein when reading a selected word of the memory array in response to an external reading command, the reading unit configured to output data of the selected word or data indicating the erasing based on the first flag data,
wherein the erasure unit configured to set the first flag data, when the first flag data indicates the erasure state, the data indicating the erasing is output by the reading unit without relation of data stored in the selected word; and
a programming unit, configured to receive an external programming command and programming input data to the selected word of the memory array, the programming unit setting the first flag data to be in a non-erasure state,
wherein the programming unit configured to compare the data stored in the selected word with the input data, programs the input data or reverse conversion data of the input data to the selected word according to a comparing result, and sets a second flag data for determining data for programming,
wherein the programming unit configured to reverse inconsistent data in the selected word according to the comparing result,
a ratio of inconsistency is the relationship between the input data and the data stored in the selected word;
if the ratio of inconsistency between the input data and the data stored in the selected word is 50% or more than 50%, the input data is programmed to the selected word, but only the data of the selected word corresponding to “1” indicating Inconsistency in an EXOR calculation is reversed;
if the ratio of inconsistency is less than 50%, the reverse conversion data is programmed to the selected word, but only the data of the selected word corresponding to “0” indicating consistency in the EXOR calculation is reversed, and the second flag data indicates the input data or the reverse conversion data is already programmed.

US Pat. No. 10,366,749

MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a memory device including a memory cell with a variable resistance value, and a first controller; and
a second controller configured to instruct the memory device to write data having a first value or a second value that is different from the first value,
wherein:
the first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell,
the first voltage is different from the second voltage,
the first read data has the first value or the second value, and
the second read data has the first value or the second value.

US Pat. No. 10,366,748

RESISTANCE VARIABLE MEMORY SENSING USING PROGRAMMING SIGNALS

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of resistance variable memory cells; and
circuitry, coupled to the array of resistance variable memory cells, including a comparator to detect a change in resistance of a memory cell, wherein the memory cell is selected by applying a select signal to a word line coupled to the memory cell, by comparing a signal on a bit line coupled to the memory cell when a programming signal is applied to the memory cell to a signal associated with a reference signal applied to the circuitry while the programming signal is applied to the memory cell, wherein a voltage of the reference signal increases as a current of the programming signal increases and wherein the circuitry indicates that a data state of the memory cell is a data state that is different from the data state associated with the programming signal when the signal associated with the memory cell input into the comparator is from a capacitor.

US Pat. No. 10,366,747

COMPARING INPUT DATA TO STORED DATA

Micron Technology, Inc., ...

1. A method, comprising:comparing first input data to first stored data stored in a first memory cell by applying a first voltage differential across the first memory cell during a first time period;
comparing second input data to second stored data stored in a second memory cell by applying a second voltage differential across the second memory cell during a second time period, wherein the first and second voltage differentials have opposite polarities; and
determining whether the first input data matches the first stored data based on whether the first memory cell snaps back in response to applying the first voltage differential across the first memory cell.

US Pat. No. 10,366,746

SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE

INTERNATIONAL BUSINESS MA...

1. A memory cell, comprising:cross coupled inverters;
a bitline left (BL) which accesses a first inverter of the cross coupled inverters;
a bitline right (BR) which accesses a second inverter of the cross coupled inverters;
a wordline left (WL) which enables a first access transistor;
a wordline right (WR) which enables a second access transistor; and
a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,
wherein:
the GNDL and the GNDR are separate vertical SRAM GND buses, and
in a standby mode of the memory cell, Vdd is at an elevated GND (GNDH).

US Pat. No. 10,366,745

SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING DEVICE

HITACHI, LTD., Tokyo (JP...

1. A semiconductor device which performs a non-linear operation, comprising:a memory;
a reading unit that reads data from the memory;
a majority circuit coupled to a plurality of spin value signal lines that inputs a result of a predetermined operation on the data read by the reading unit;
a write circuit that receives an output of the majority circuit; and
a control unit that controls the memory, the reading unit, the majority circuit, and the write circuit,
wherein the control unit has a step of calculation using a parameter T determined by the control unit regardless of a value in the memory, and
wherein in the step,
the value of the predetermined signal in the semiconductor device is stochastically inverted based on a result of the calculation, and
“1” is randomly output with a probability f(x,T) given by function

which includes a hyperbolic tangent function with an argument as a value x determined by the value in the memory, and
wherein a value of a predetermined signal is stochastically inverted at a preceding stage of the majority circuit.

US Pat. No. 10,366,744

DIGITAL FILTERS WITH MEMORY

Micron Technology, Inc., ...

1. An electronic device, comprising:a quantizing circuit configured to be coupled to an internal data storage location via an electrical conductor, the quantizing circuit comprising:
an analog-to-digital converter having an input and an output; and
a digital filter coupled to the output of the analog-to-digital converter, wherein the digital filter comprises memory distinct from filtering circuitry of the digital filter, and wherein the digital filter is configured to store a preset value in the memory, wherein the preset value is utilized to initialize the digital filter to mitigate a downward bias or rounding error introduced by the filtering circuitry to an output of the filtering circuitry.

US Pat. No. 10,366,743

MEMORY WITH A REDUCED ARRAY DATA BUS FOOTPRINT

Micron Technology, Inc., ...

1. A memory device, comprising:a memory array including two or more memory bank groups;
I/O gating circuitry;
a local data bus electrically coupling the I/O gating circuitry to the two or more memory bank groups; and
one or more data latches electrically coupled to the local data bus,
wherein—
the local data bus includes a plurality of array data lines shared between the two or more memory bank groups,
the plurality of shared array data lines is configured to transfer data between the I/O gating circuitry and each of the two or more memory bank groups,
data transferred over the plurality of shared array data lines between the I/O gating circuitry and a first memory bank group in the two or more memory bank groups has a first propagation delay,
data transferred over the plurality of shared array data line between the I/O gating circuitry and a second memory bank group in the two or more memory bank groups has a second data propagation delay different than the first propagation delay,
the memory device is configured to match column select generations for the first and the second memory bank groups with the first and the second propagation delays, and
the data latches are configured to transfer first data corresponding to a first access operation off of the local data bus to free up the local data bus to transfer second data corresponding to a second access operation.

US Pat. No. 10,366,742

MEMORY DEVICE PARALLELIZER

Micron Technology, Inc., ...

1. A memory device, comprising:a plurality of memory banks configured to store data;
an input buffer configured to receive input data and output serial data;
a serial shift register configured to shift in the serial data and to output the serial data in a parallel format as parallel data;
a parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer, wherein the parallel register is configured to pass the parallel data and the buffered data to a data write bus to be stored in the plurality of memory banks; and
serial-to-parallel conversion circuitry that controls loading of the parallel register from the serial shift register and the input buffer, wherein the serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

US Pat. No. 10,366,741

BIT PROCESSING

ARM Limited, Cambridge (...

1. Circuitry comprising:a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array;
each bit processing circuitry for a given bit position within the ordered bit array comprising:
bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and
bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals;
in which:
the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.

US Pat. No. 10,366,740

APPARATUSES HAVING MEMORY STRINGS COMPARED TO ONE ANOTHER THROUGH A SENSE AMPLIFIER

Micron Technology, Inc., ...

1. An apparatus comprising:a first bitline extending horizontally;
a second bitline being offset vertically from the first bitline and extending horizontally in parallel to the first bitline;
a common plate extending horizontally between the first and second bitlines;
a plurality of first memory cell structures disposed horizontally between the first bitline and the common plate, each of the plurality of first memory cell structures including a first access device and a first capacitor coupled in series between the first bitline and the common plate;
a plurality of second memory cell structures disposed horizontally between the second bitline and the common plate, each of the plurality of second memory cell structures including a second access device and a second capacitor coupled in series between the second bitline and the common plate;
a first sense amplifier coupled to the first bitline;
a second sense amplifier coupled to the second bitline;
a third bitline extending horizontally;
a plurality of third memory cell structures each coupled to the third bitline;
a fourth bitline extending horizontally; and
a plurality of fourth memory cell structures each coupled to the fourth bitline;
wherein the first sense amplifier is further coupled to the third bitline to compare the first and third bitlines with each other; and
wherein the second sense amplifier is further coupled to the fourth bitline to compare the third and fourth bitlines with each other.

US Pat. No. 10,366,739

STATE DEPENDENT SENSE CIRCUITS AND SENSE OPERATIONS FOR STORAGE DEVICES

SanDisk Technologies LLC,...

1. A circuit comprising:a sense circuit coupled to a bit line, the sense circuit comprising:
a charge-storing circuit configured to generate a sense voltage; and
an input circuit configured to:
supply a first pulse to the charge-storing circuit in response to the bit line comprising a selected bit line; and
supply a second pulse to the charge-storing circuit with a lower magnitude than the first pulse in response to the bit line comprising an unselected bit line.

US Pat. No. 10,366,738

INTEGRATED MEMORY ASSEMBLIES COMPRISING MULTIPLE MEMORY ARRAY DECKS

Micron Technology, Inc., ...

1. An integrated memory assembly, comprising:a first memory array deck over a second memory array deck;
a first series of conductive lines extending across the first memory array deck, and a second series of conductive lines extending across the second memory array deck;
a first conductive line of the first series and a first conductive line of the second series being coupled with a first component through a first conductive path;
a second conductive line of the first series and a second conductive line of the second series being coupled with a second component through a second conductive path;
the first and second conductive lines of the first series extending through first isolation circuitry to the first and second conductive paths, respectively; the first isolation circuitry including a first transistor which gatedly connects the first conductive line of the first series to the first conductive path, and including a second transistor which gatedly connects the second conductive line of the first series to the second conductive path; the gates of the first and second transistors being coupled with a first isolation driver; and
the first and second conductive lines of the second series extending through second isolation circuitry to the first and second conductive paths, respectively; the second isolation circuitry including a third transistor which gatedly connects the first conductive line of the second series to the first conductive path, and including a fourth transistor which gatedly connects the second conductive line of the second series to the second conductive path; the gates of the third and fourth transistors being coupled with a second isolation driver.

US Pat. No. 10,366,737

MANAGEMENT OF STROBE/CLOCK PHASE TOLERANCES DURING EXTENDED WRITE PREAMBLES

Micron Technology, Inc., ...

1. A memory device comprising:a command decoder configured to receive a command signal, wherein the command decoder is configured to provide a write command signal when the received command signal indicates a write operation;
an input/output (I/O) interface configured to receive the write command signal, a data strobe signal that comprises a first preamble of a plurality of preambles, and a data signal, wherein the I/O interface comprises preamble decoding circuitry configured to:
receive a preamble signal associated with the first preamble;
capture a preamble feature of the data strobe signal based on the preamble signal, wherein the preamble feature comprises a rising edge, a falling edge, a high logic value, a low logic value, or a first combination thereof; and
cause the I/O interface to capture a first bit of the data signal based on a data strobe feature that follows the preamble feature, wherein the data strobe feature comprises the rising edge, the falling edge, the high logic value, the low logic value, or a second combination thereof.

US Pat. No. 10,366,735

BOOSTING A DIGIT LINE VOLTAGE FOR A WRITE OPERATION

Micron Technology, Inc., ...

20. An electronic memory apparatus, comprising:a memory cell;
a boost component; and
a controller coupled with the memory cell and the boost component, wherein the controller is operable to:
applying, during a write operation, a first voltage to a digit line coupled with the memory cell;
coupling the boost component to the digit line during the write operation based at least in part on applying the first voltage; and
boosting the digit line to a second voltage during the write operation based at least in part on coupling the boost component to the digit line.

US Pat. No. 10,366,734

PROGRAMMABLE WRITE WORD LINE BOOST FOR LOW VOLTAGE MEMORY OPERATION

Advanced Micro Devices, I...

1. A computing system comprising:a memory configured to operate with each of a plurality of operational voltages, each of said operational voltages corresponding to a different power-performance state (P-state);
a processing unit configured to generate access requests for the memory; and
a system management unit configured to:
set a cross-over region comprising a range of operating voltages for the memory;
determine a target P-state different than a current P-state based on feedback information received from one or more of the processing unit and the memory; and
enable boosting of word line voltage levels in the memory as a transitioning operational voltage of the memory transitions from the current operational voltage to the target operational voltage responsive to determining:
the current operational voltage is greater than the target operational voltage; and
the transitioning operational voltage of the memory is less than a lower limit of the range.

US Pat. No. 10,366,733

WORD LINE CACHE MODE

Micron Technology, Inc., ...

1. A semiconductor device comprising:a plurality of memory cells;
a plurality of word lines that controls operations of the plurality of memory cells;
a plurality of word line drivers that each controls a respective word line of the plurality of word lines, wherein each word line driver of the plurality of word line drivers comprises:
a pull-up transistor to transition a corresponding word line to a logic high voltage; and
a pull-down transistor to transition the corresponding word line to a logic low voltage, wherein the pull-down transistor comprises an n-channel transistor that is activated during an inactive period for the corresponding word line; and
local controls that each controls a respective word line driver of the plurality of word line drivers, wherein the local controls are configured to:
assert a voltage on the corresponding word line of the plurality of word lines;
start an internal timer responsive, at least in part, to assertion of the voltage, wherein the internal timer is configured to provide additional settling of the corresponding word line before activation to reduce channel hot carrier issues for the n-channel transistor;
determine whether the internal timer has elapsed; and
after the internal timer has elapsed, de-assert the voltage from the corresponding word line as a row address strobe timer (tRAS) lockout.

US Pat. No. 10,366,732

SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a buffer control circuit for receiving a power-down mode signal and a detection pulse to generate a buffer control signal;
a first buffer circuit for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal, in a power-down mode; and
a detection pulse generation circuit for receiving the first internal chip select signal to generate the detection pulse.

US Pat. No. 10,366,731

MEMORY DEVICES HAVING SPECIAL MODE ACCESS USING A SERIAL MESSAGE

Micron Technology, Inc., ...

1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:a command field of the serial message configured to enable the serial interface controller to access the register;
a register address field of the serial message immediately following the command field indicating an address of the register; and
a data field of the serial message immediately following the register address field, wherein the data field of the serial message is configured to cause the memory device to operate according to a one time programmable (OTP) access mode.

US Pat. No. 10,366,730

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:a semiconductor device configured to generate first group of data and second group of data in response to a command and an address, and
wherein, the semiconductor device configured to sequentially latch the first group of data loaded on a first group of I/O lines and the second group of data loaded on a second group of I/O lines to generate output data in response to a burst length information signal or to simultaneously latch the first and second groups of data loaded on the first and second groups of I/O lines to generate the output data in response to the burst length information signal.

US Pat. No. 10,366,729

SENSE CIRCUIT WITH TWO-STEP CLOCK SIGNAL FOR CONSECUTIVE SENSING

SanDisk Technologies LLC,...

1. An apparatus, comprising:a sense node;
a first transistor between the sense node and a bit line;
a capacitor connected to the sense node;
a second transistor connected to the sense node; and
a control circuit, the control circuit to perform a sense operation for a memory cell connected to the bit line, is configured to:
increase a voltage of the capacitor which steps up a voltage of the sense node to a peak level by way of capacitive coupling,
provide the first transistor in a conductive state to connect the sense node with the bit line in a discharge period,
provide a first decrease of the voltage of the capacitor which provides a first decrease of the voltage of the sense node,
perform a first strobe of an output of the second transistor after the first decrease of the voltage of the capacitor,
provide a second decrease of the voltage of the capacitor which provides a second decrease of the voltage of the sense node, and
perform a second strobe of the output of the second transistor after the second decrease of the voltage of the sense node.

US Pat. No. 10,366,728

METHODS AND APPARATUSES FOR PROVIDING A PROGRAM VOLTAGE RESPONSIVE TO A VOLTAGE DETERMINATION

Micron Technology, Inc., ...

1. A method, comprising:providing a common inhibit voltage to a plurality of access lines;
determining whether an access line of the plurality of access lines has reached a voltage equal to or greater than a threshold voltage, wherein the threshold voltage is different from the common inhibit voltage;
responsive to a determination that the access line of the plurality of access lines has reached the voltage equal to or greater than the threshold voltage, providing a program voltage to a target access line of the plurality of access lines, wherein the program voltage is higher than the common inhibit voltage, and the threshold voltage is not a voltage held for a length of time on the access line of the plurality of access lines before the providing of the program voltage; and
holding the program voltage on the target access line.

US Pat. No. 10,366,727

SEMICONDUCTOR CHIP MODULE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor chip module comprising:a chip unit including first and second semiconductor chips which are formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned and a second surface which faces away from the first surface, wherein the bonding pads are arranged along a second direction;
a plurality of oblique redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads of the first and second semiconductor chips, and extending toward the scribe line region; and
a plurality of redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the oblique redistribution lines which face away from the one set of ends, the redistribution pads comprising:
one or more shared redistribution pads electrically coupled in common to one or more of the oblique redistribution lines electrically coupled to the bonding pads of the first semiconductor chip and one or more of the oblique redistribution lines electrically coupled to the bonding pads of the second semiconductor chip; and
a plurality of individual redistribution pads individually electrically coupled to the oblique redistribution lines which are not electrically coupled with the shared redistribution pads,
wherein the first direction is perpendicular to the second direction,
wherein the first and second semiconductor chips are electrically connected with each other through the shared redistribution pads and the oblique redistribution lines electrically coupled to the shared redistribution pads, and
wherein the oblique redistribution lines are inclined with respect to the first direction.

US Pat. No. 10,366,726

INTERLACED MAGNETIC RECORDING IN WITH MULTIPLE INDEPENDENT-ACTUATORS HAVING RESPECTIVE INDEPENDENT HEADS

Seagate Technology LLC, ...

1. A method, comprising:writing a first set of bottom tracks via a first head that is moved via a first actuator over a surface of a disk; and
writing a second set of top tracks interlaced between and partially overlapping the bottom tracks via a second head that is moved via a second actuator over the surface of the disk independently of the first actuator and first head, the first and second actuators rotating about separate axes such that the first and second heads are rotationally offset from each other on the disk surface, the rotational offset allowing the first and second head to write both the bottom tracks and the top tracks simultaneously.

US Pat. No. 10,366,725

SERVER SIDE CROSSFADING FOR PROGRESSIVE DOWNLOAD MEDIA

Sirius XM Radio Inc., Ne...

1. A method for implementing a server side crossfade or other transitional effect, the method comprising:receiving, from each of a plurality of client devices, user data indicative of behavior or at least one preference of a user of that client device;
identifying at least one media clip to be transmitted to a first one of the plurality of client devices for playback, the at least one media clip including multiple chunks;
determining at least one chunk of the at least one media clip to process for the effect;
processing the at least one chunk based on the user data received from the first client device such that the effect is personalized for the user of that device; and
transmitting the processed at least one chunk and the remaining chunks of the at least one media clip to the first client device for playback.

US Pat. No. 10,366,724

STORAGE CONTROL DEVICE, STORAGE SYSTEM AND METHOD OF CONTROLLING A STORAGE DEVICE

FUJITSU LIMITED, Kawasak...

1. A storage control device comprising:a memory; and
a processor coupled to the memory and configured to:
dividing a plurality of storage regions of a storage device into a plurality of groups such that each group includes one or more sectors, each sector being an access unit of the storage device and including one or more storage regions of the plurality of storage regions,
upon detection of an error in reading data from a first storage region of the storage device, determine the first storage region to be an error region at which the error has occurred, and set a first sector including the error region as a defective sector by setting a defective flag in the first sector without storing address information of the first sector into the memory,
store, into the memory, error-flag information associated with each of the plurality of groups and indicating whether the error region is included in each of the plurality of groups,
upon reception of a request to reference information on an error that has occurred in the storage device, identify a first group including the error region, from among the plurality of groups based on the error-flag information that is stored in the memory in association with each of the plurality of groups,
read, from the storage device, the one or more sectors included in the identified first group, and
identify the defective sector and the error region included in the defective sector by detecting the defective flag set in the defective sector of the read one or more sectors.

US Pat. No. 10,366,723

SYSTEM AND METHOD FOR DISTRIBUTING SHUTTLE CARS IN A DATA STORAGE LIBRARY SHUTTLE COMPLEX

International Business Ma...

1. A system for transporting components between data storage libraries, the system comprising:a plurality of data storage libraries;
a plurality of shuttle connections coupled to the plurality of data storage libraries;
a plurality of shuttle cars, wherein at least one of the plurality of shuttle cars is movably housed within each of the plurality of shuttle connections, each of the shuttle cars being configured for movement between each of the plurality of data storage libraries via a corresponding shuttle connection; and
at least one system controller, wherein the at least one system controller is configured to receive host commands and control movement of the shuttle cars between the plurality of data storage libraries, and further wherein the at least one system controller is configured to control movement of each of the shuttle cars such that at least one shuttle car is associated with each of the plurality of data storage libraries during operation of the system,
wherein the system controller is configured to move a first shuttle car from a position associated with a first data storage library to a position associated with a second data storage library after the second data storage library has been vacated by a second shuttle car.

US Pat. No. 10,366,722

LASER MODE HOP DETECTION IN A HEAT-ASSISTED MAGNETIC RECORDING DEVICE USING A SLIDER SENSOR AND LASER MODULATION

Seagate Technology LLC, ...

1. A method, comprising:while writing to a magnetic recording medium using a slider configured for heat-assisted magnetic recording:
supplying a modulated current to a laser diode of or near the slider to produce modulated light, the modulated current having a mean amplitude that varies or is constant;
supplying power to a writer heater of the slider, the power having a magnitude that varies or is constant;
producing, by a sensor of the slider, a sensor signal representative of output optical power of the laser diode while writing to the medium;
measuring a change in the sensor signal; and
detecting a laser mode hop using the measured sensor signal change.

US Pat. No. 10,366,721

HEAD POSITIONING OF TIMING-BASED SERVO SYSTEM FOR MAGNETIC TAPE RECORDING DEVICE

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support,
wherein the magnetic layer includes a timing-based servo pattern,
the ferromagnetic powder is ferromagnetic hexagonal ferrite powder having an activation volume equal to or smaller than 1,600 nm3,
an intensity ratio Int(110)/Int(114) of a peak intensity Int(110) of a diffraction peak of a (110) plane with respect to a peak intensity Int(114) of a diffraction peak of a (114) plane of a hexagonal ferrite crystal structure obtained by an X-ray diffraction analysis of the magnetic layer by using an In-Plane method is 0.5 to 4.0,
a vertical direction squareness ratio of the magnetic tape is 0.65 to 1.00, and
an edge shape of the timing-based servo pattern specified by magnetic force microscope observation is a shape in which a difference (L99.9?L0.1) of a value L99.9 of a cumulative distribution function of 99.9% of a position shift width from an ideal shape in a longitudinal direction of the magnetic tape and a value L0.1 of the cumulative distribution function of 0.1% is equal to or smaller than 180 nm.

US Pat. No. 10,366,720

OXIDATION RESISTANT SENSOR FOR HEAT-ASSISTED MAGNETIC RECORDING

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider comprising an air bearing surface (ABS) and configured for heat-assisted magnetic recording, the slider comprising:
a writer and a reader at the ABS;
a near-field transducer (NFT) proximate the writer;
an optical waveguide optically coupled to a laser source and the NFT;
a sensor configured to contact and sense thermal asperities of a magnetic recording medium, the sensor formed from one of Ru, Rh, Pd, Os, Ir, and Pt;
a protective coating covering at least a portion of the ABS including the writer, reader, NFT, and sensor; and
the sensor is configured to operate at a temperature that degrades the protective coating and exposes the sensor leaving the sensor unprotected.

US Pat. No. 10,366,719

BOOSTED PREHEAT TRAJECTORY TO OBTAIN DESIRED CLEARANCE BEFORE WRITING TO DISK

Seagate Technology LLC, ...

1. A method, comprising:engaging a resistive clearance heater embedded near an air bearing surface of a read/write head with a boosted current that exceeds a steady-state current, the steady-state current applied to the resistive clearance heater causing the write head to maintain a desired clearance over a disk during reading and writing, the boosted current applied before and after a start of the reading and the writing;
decreasing the boosted current according to a profile that has two or more steps that approximate a monotonically decreasing curve; and
applying the steady-state current to the resistive clearance heater after the start of the reading and the writing.

US Pat. No. 10,366,718

HARD DISK SERVO CONTROL ADAPTIVE NOTCH FILTER USING A RECURSIVE LEAST SQUARES PROCESSOR

Seagate Technology LLC, ...

1. A method comprising:monitoring a signal that provides an indicator of disturbance affecting a hard disk drive, the signal being monitored during an operational track following mode of the hard disk drive;
in response to determining that the indicator of the disturbance satisfies a threshold:
applying a lattice recursive least squares computation to the signal to determine at least one notch frequency; and
using the at least one notch frequency to form a notch filter used by a servo controller loop that positions a read/write head over a disk of the hard disk drive; and
apply the notch filter to the servo control loop for subsequent positioning of the read/write head.

US Pat. No. 10,366,717

MAGNETIC DISK DEVICE AND METHOD OF WRITING RRO CORRECTION DATA

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk which includes a plurality of servo sectors radially extending in a radial direction and being discretely disposed with a gap in a circumferential direction;
a head which writes data to the disk and reads data from the disk; and
a controller which writes a plurality of pieces of correction data with respect to a repeatable run-out of the disk to a plurality of first sectors disposed between the servo sectors in a first region, and writes the pieces of correction data to a plurality of second sectors disposed between the servo sectors in a second region different from the first region.

US Pat. No. 10,366,716

CHARACTERIZATION OF NONLINEARITY IN SERVO PATTERNS

International Business Ma...

1. A method, comprising:applying a static head skew to a magnetic tape head for misaligning first and second readers in a direction perpendicular to a tape travel direction thereacross;
positioning the first reader at a first y-position relative to a servo pattern in a servo band;
measuring y-positions of the second reader relative to the servo pattern in the servo band while the first reader is at the first y-position;
averaging the measured y-positions;
repeating the following process several times:
moving the first reader to a next y-position,
measuring y-positions of the second reader while the first reader is at the next y-position,
averaging the y-positions measured by the second reader while the first reader is at the next y-position;
calculating a unique nonlinearity value of the servo pattern in the servo band for each of the average y-position values using the respective average y-position value; and
storing and/or outputting the calculated nonlinearity values.

US Pat. No. 10,366,714

MAGNETIC WRITE HEAD FOR PROVIDING SPIN-TORQUE-ASSISTED WRITE FIELD ENHANCEMENT

Western Digital Technolog...

1. A magnetic write head for providing spin-torque-assisted write field enhancement,the magnetic write head comprising, within a write gap:
a main pole;
a trailing shield;
a spacer disposed between the main pole and the trailing shield, wherein the spacer is non-magnetic;
a non-magnetic layer disposed between the main pole and the trailing shield; and
a DC-field-generation (DFG) layer adjacent to the spacer and disposed between the spacer and the non-magnetic layer, wherein the DFG layer is magnetic,
wherein the DFG layer is the only magnetic layer within the write gap that is not adjacent to the main pole or the trailing shield.

US Pat. No. 10,366,713

DESIGNS FOR MULTIPLE PERPENDICULAR MAGNETIC RECORDING (PMR) WRITERS AND RELATED HEAD GIMBAL ASSEMBLY (HGA) PROCESS

Headway Technologies, Inc...

1. A head gimbal assembly (HGA), comprising:(a) a slider on which a PMR writer structure is formed;
(b) the PMR writer structure, comprising:
(1) a first writer with a first main pole that is formed between a first bucking coil and a first driving coil; and
(2) a second writer with a second main pole that is formed between a second bucking coil (DC) and a second driving coil (DC);
(c) a plurality of nW+ pads on the slider, and comprised of a W1+ pad that is connected to the first DC, and a W2+ pad connected to the second DC, and a plurality of nW? pads formed on the slider, and comprising a W1? pad that is connected to the first BC, and a W2? pad connected to the second BC; and
(d) a first trace line (TL1) from a preamp where the TL1 is formed on a flexure in the HGA and has a plurality of nTL1? arms wherein one TL1 arm is connected to one of the plurality of W? pads, and a second trace line (TL2) from the preamp where the TL2 is formed on the flexure and has a plurality of nTL2? arms wherein one TL2 arm is connected to one of the plurality of W+ pads thereby enabling only the first writer to be functional when the one TL1 arm is connected to the W1? pad and the one TL2 arm is connected to the W1+ pad, or only the second writer to be functional when the one TL1 arm is connected to the W2? pad and the one TL2 arm is connected to the W2+ pad.

US Pat. No. 10,366,712

MAGNETIC HEAD FOR PERPENDICULAR MAGNETIC RECORDING INCLUDING TWO SIDE SHIELDS CONFIGURED TO ENABLE A REDUCTION IN WIDTH OF AN END FACE OF THE MAIN POLE LOCATED IN A MEDIUM FACING SURFACE AND AN INCREASE IN CROSS-SECTIONAL AREA OF THE MAIN POLE IN THE VICI

HEADWAY TECHNOLOGIES, INC...

1. A magnetic head for perpendicular magnetic recording, comprising:a medium facing surface configured to face a recording medium;
a coil configured to produce a magnetic field corresponding to data to be written on the recording medium;
a main pole configured to pass a magnetic flux corresponding to the magnetic field produced by the coil, and to produce a write magnetic field for writing the data on the recording medium by means of a perpendicular magnetic recording system;
a write shield formed of a magnetic material;
a gap section formed of a nonmagnetic material and provided between the main pole and the write shield; and
a substrate having a top surface, wherein
the coil, the main pole, the write shield and the gap section are disposed above the top surface of the substrate,
the write shield includes a first side shield and a second side shield located on opposite sides of the main pole in a track width direction,
the first side shield has a first end face located in the medium facing surface, and has a first sidewall and a second sidewall facing the main pole,
the second side shield has a second end face located in the medium facing surface, and has a third sidewall and a fourth sidewall facing the main pole,
the first sidewall is connected to the first end face,
the second sidewall is located farther from the medium facing surface than is the first sidewall,
the third sidewall is connected to the second end face,
the fourth sidewall is located farther from the medium facing surface than is the third sidewall,
the first sidewall has a first edge farthest from the top surface of the substrate,
the second sidewall has a second edge farthest from the top surface of the substrate,
the third sidewall has a third edge farthest from the top surface of the substrate,
the fourth sidewall has a fourth edge farthest from the top surface of the substrate,
each of the first and third edges has a front end located in the medium facing surface and a rear end opposite to the front end,
each of the second and fourth edges has a front end closest to the medium facing surface,
a distance between the rear end of the first edge and the rear end of the third edge in the track width direction is greater than a distance between the front end of the first edge and the front end of the third edge in the track width direction,
a distance between the second edge and the fourth edge in the track width direction increases with increasing distance from the medium facing surface,
the first edge and the second edge are contiguous to each other to form a first contour line, the rear end of the first edge and the front end of the second edge coinciding with each other,
the third edge and the fourth edge are contiguous to each other to form a second contour line, the rear end of the third edge and the front end of the fourth edge coinciding with each other,
the front end of the second edge is an inflection point or a corner at which there occurs a change in an angle of inclination of the first contour line relative to a first direction at a first point on the first contour line when the first point is shifted from the first edge to the second edge, the first direction being perpendicular to the medium facing surface, the change being a decrease,
the front end of the fourth edge is an inflection point or a corner at which there occurs a change in an angle of inclination of the second contour line relative to the first direction at a second point on the second contour line when the second point is shifted from the third edge to the fourth edge, the change being a decrease,
the main pole has an end face located in the medium facing surface, and has a first side surface and a second side surface,
part of the first side surface is opposed to the first sidewall,
part of the second side surface is opposed to the third sidewall,
the gap section includes a first portion interposed between the first side surface and the first and second sidewalls, and a second portion interposed between the second side surface and the third and fourth sidewalls,
a distance from the medium facing surface to the front end of the second edge, and a distance from the medium facing surface to the front end of the fourth edge are each within a range of 20 to 90 nm, and
a distance between the front end and the rear end of the first edge in the track width direction, and a distance between the front end and the rear end of the third edge in the track width direction are each within a range of 40 to 290 nm.

US Pat. No. 10,366,711

APPLYING A PRE-ERASE OR PRE-CONDITION FIELD TO A HARD DISK BEFORE WRITING DATA TO THE HARD DISK

Seagate Technology LLC, ...

1. A method, comprising:detecting an event during field operation of a hard drive that causes at least part of a track of the hard drive to be selected for pre-erase or preconditioning;
in response to the event, pre-writing a pattern using a pre-erase or pre-conditioning magnetic field applied within at least part of the selected track via a first write transducer prior to the selected track being written; and
subsequent to the pre-writing, writing target user data over the pattern pre-written to the part of the selected track.

US Pat. No. 10,366,709

SOUND DISCRIMINATING DEVICE, SOUND DISCRIMINATING METHOD, AND COMPUTER PROGRAM

CANON KABUSHIKI KAISHA, ...

1. A sound discriminating device comprising:a sound input unit configured to input a sound to the sound discriminating device;
a feature amount extracting unit configured to extract, as a feature amount of the input sound, a differential value between an amplitude of a fundamental frequency of the input sound and an amplitude of a second harmonic of the fundamental frequency; and
a determining unit configured to determine whether or not the input sound is a given sound by using the extracted feature amount,
wherein the given sound includes a scream or a verbal aggression such as a female scream, a female voice verbally abusing someone, a male scream, and a male voice verbally abusing someone,
wherein the differential value tends to be a large positive value in a case of the input sound being a female scream, and a large negative value in a case of the input sound being a male scream, a male voice verbally abusing someone, and a female voice verbally abusing someone.

US Pat. No. 10,366,708

SYSTEMS AND METHODS OF DETECTING SPEECH ACTIVITY OF HEADPHONE USER

BOSE CORPORATION, Framin...

1. A headphone system, comprising:a left earpiece;
a right earpiece;
a left microphone coupled to the left earpiece to receive a left acoustic signal and to provide a left signal derived from the left acoustic signal;
a right microphone coupled to the right earpiece to receive a right acoustic signal and to provide a right signal derived from the right acoustic signal; and
a detection circuit coupled to the left microphone and the right microphone, the detection circuit configured to process both a principal signal and a reference signal through a smoothing algorithm, the principal signal derived from a sum of the left signal and the right signal and the reference signal derived from a difference between the left signal and the right signal, the smoothing algorithm configured to calculate a principal power signal from a decaying weighted average of power of the principal signal over time, to calculate a reference power signal from a decaying weighted average of power of the reference signal over time, and to selectively indicate that the user is speaking based at least in part upon a comparison between the principle power signal and the reference power signal.

US Pat. No. 10,366,707

PERFORMING COGNITIVE OPERATIONS BASED ON AN AGGREGATE USER MODEL OF PERSONALITY TRAITS OF USERS

International Business Ma...

1. A method, in a natural language processing (NLP) system comprising a processor and a memory, the method comprising:receiving, by the NLP system, a plurality of communications associated with a communication system, over a predetermined time period, from a plurality of end user devices;
identifying, by the NLP system, for each communication in the plurality of communications, a user submitting the communication to thereby generate a set of users comprising a plurality of users associated with the plurality of communications;
retrieving, by the NLP system, a user model for each user in the set of users, wherein the user model specifies at least one personality trait of a corresponding user;
generating, by the NLP system, an aggregate user model that aggregates the at least one personality trait of each user in the set of users together to generate an aggregate representation of the personality traits of the plurality of users in the set of users; and
performing, by the NLP system, a cognitive operation based on the aggregate use model.

US Pat. No. 10,366,706

SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD AND LABELING APPARATUS

Kabushiki Kaisha Toshiba,...

1. A signal processing apparatus comprising:a memory; and
a hardware processor electrically coupled to the memory and configured to:
separate a plurality of signals using a separation filter to obtain a plurality of separate signals, and output the plurality of separate signals, the plurality of signals including signals which come from different directions,
estimate incoming directions of the plurality of separate signals, respectively, and associate the plurality of separate signals with the incoming directions, and
associate either one of a first attribute or a second attribute with the separate signals from the plurality of separate signals which are associated with the incoming directions based at least in part on results of the estimation of the incoming directions in a first period, respectively, the first period being set by at least one of button operations.

US Pat. No. 10,366,705

METHOD AND SYSTEM OF SIGNAL DECOMPOSITION USING EXTENDED TIME-FREQUENCY TRANSFORMATIONS

ACCUSONUS, INC., Lexingt...

1. A method of digital signal decomposition to identify components of a source signal comprising a first sound signal from a musical instrument and a second sound signal, comprising:obtaining a first representation of the source signal, during a first time period, comprising a mixture of the first and second sound signals;
calculating a time-frequency transformation of the first representation;
obtaining, during a second time period, a second representation of the source signal, which comprises the first sound signal captured in isolation of the second sound signal and/or the second sound signal captured in isolation of the first sound signal;
calculating a time-frequency transformation of the second representation;
forming an extended time-frequency transformation by combining the first time frequency transformation and the second time-frequency transformation;
applying a decomposition technique to the extended time-frequency transformation to extract one or more decomposed components of the source signal; and
audibly outputting one or more time domain signals related to the one or more decomposed components of the source signal.

US Pat. No. 10,366,704

ACTIVE ACOUSTIC ECHO CANCELLATION FOR ULTRA-HIGH DYNAMIC RANGE

Intel Corporation, Santa...

1. An apparatus comprising:a speaker to generate audio output;
an audio input device to receive audio input and to provide an audio input signal responsive to the audio input at a first sampling rate; and
one or more processors coupled to the speaker and the audio input device, the one or more processors to:
generate an audio output signal having at least a portion thereof corresponding to a first audio frequency range, the portion of the audio output signal, when provided as first audio output from the speaker, to negate a response of the audio input device, at a response negation rate, to second audio output from the speaker in a second audio frequency range, wherein each audio frequency of the first audio frequency range exceeds a maximum audio frequency of the second audio frequency range; and
decimate the audio input signal based on the response negation rate to a second sampling rate less than the first sampling rate to generate a resultant audio input signal.

US Pat. No. 10,366,703

METHOD AND APPARATUS FOR PROCESSING AUDIO SIGNAL INCLUDING SHOCK NOISE

SAMSUNG ELECTRONICS CO., ...

1. A method of processing an audio signal in a terminal device, the method comprising:acquiring an audio signal of a frequency domain for a current frame;
dividing a frequency band into a plurality of sections;
acquiring energies of a first section and a second section from among the plurality of sections;
determining whether the audio signal of the current frame includes noise based on an energy difference between the first section and the second section; and
applying a suppression gain to the audio signal of the current frame and outputting the audio signal of the current frame applied the suppression gain, based on a result of determining,
wherein the first section and the second section are non-overlapped in the frequency band, and
wherein at least one of the first section and the second section is determined as a shock noise section based on the energy difference.

US Pat. No. 10,366,702

DIRECTION DETECTION DEVICE FOR ACQUIRING AND PROCESSING AUDIBLE INPUT

LOGITECH EUROPE, S.A., L...

1. A method of determining a direction from which an audible signal is received, comprising:defining an audible signal detection region by dividing a first angular distance created between a first microphone and a second microphone that are disposed on an electronic device into at least two regions, wherein one of the at least two regions comprise a second angular distance that is formed between a first direction and a second direction that each extend from a vertex point;
determining, by use of an electronic device, a first relative time delay created by the delivery of a first portion of an audible signal to the first microphone and the second microphone from an external audible source, wherein the first relative time delay is calculated by determining a difference between a time when the second microphone received the first portion of the audible signal and a time when the first microphone received the first portion of the audible signal;
comparing, by use of the electronic device, the first relative time delay with a plurality of stored time delays, wherein the plurality of stored time delays comprise:
a first stored time delay that is associated with the external audible source being positioned a distance from the first and second microphones along the first direction; and
a second stored time delay that is associated with the external audible source being positioned a distance from the first and second microphones along the second direction; and
determining, by use of the electronic device, that the external audible source is positioned in a third direction by determining that the first portion of the audible signal was received from a direction that is closer to the third direction that is positioned between the first and second directions versus a fourth direction that is positioned outside of the second angular distance formed between the first and second directions based on the comparison of the first relative time delay with the first and second stored time delays.