US Pat. No. 10,340,390

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

SHARP KABUSHIKI KAISHA, ...

1. A semiconductor device comprising:a substrate, a thin-film transistor supported on the substrate, and a first insulating layer,
the thin-film transistor including a semiconductor layer, a gate electrode, a gate insulating layer arranged between the gate electrode and the semiconductor layer, a source electrode, and a drain electrode, the source electrode and the drain electrode being in contact with the semiconductor layer, wherein
one of an upper surface and a lower surface of the semiconductor layer is in contact with the gate insulating layer, the other is in contact with the first insulating layer,
the semiconductor layer has a laminated structure including a first oxide semiconductor layer and a second oxide semiconductor layer, the first oxide semiconductor layer is arranged on a gate insulating layer side of the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer,
the first insulating layer contains silicon oxide,
the second oxide semiconductor layer contains In and Ga and does not contain Sn,
the first oxide semiconductor layer contains In, Sn, and Zn,
a percentage of Zn in the first oxide semiconductor layer in a depth direction does not have a maximum value in a vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer,
a percentage of Sn having a metallic bonding state at an interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 90% or less with respect to a total amount of Sn, and
a region where the percentage of Sn having the metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 50% or more with respect to the total amount of Sn has a thickness of less than 10 nm.

US Pat. No. 10,340,389

MULTI-GATE THIN FILM TRANSISTORS, MANUFACTURING METHODS THEREOF, ARRAY SUBSTRATES, AND DISPLAY DEVICES

BOE Technology Group Co.,...

1. A thin film transistor comprising a base substrate, an active layer, a source, a gate, and a drain, the active layer, the source, the gate, and the drain disposed on the base substrate, the active layer including an end connected to the source and another end connected to the drain,the gate including a top gate and a bottom gate, the top gate including a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate top portion and the bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate side portion extending from the top gate top portion towards the base substrate and not physically contacting the bottom gate,
the active layer sandwiched between the top gate top portion and the bottom gate, and the active layer including a sidewall at least partially surrounded by the top gate side portion.

US Pat. No. 10,340,388

INTERMEDIATE SEMICONDUCTOR DEVICE HAVING AN ALIPHATIC POLYCARBONATE LAYER

Japan Advanced Institute ...

1. An intermediate semiconductor device comprising:a semiconductor layer; and
an aliphatic polycarbonate layer that covers a portion of the semiconductor layer, the aliphatic polycarbonate layer comprising a dopant.

US Pat. No. 10,340,387

LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND ARRAY SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of a low temperature poly-silicon thin film transistor, comprising:providing a substrate and sequentially forming a buffer layer, a low temperature poly-silicon layer, a source contact region, a drain contact region, a gate insulator layer, a gate layer, and a dielectric layer on the substrate, wherein the source contact region and the drain contact region are disposed in a same layer as the low temperature poly-silicon layer and are respectively disposed at two opposite ends of the low temperature poly-silicon layer;
respectively forming a first contact hole and a second contact hole through the dielectric layer and the gate insulator layer by dry etching to expose the source contact region and the drain contact region respectively; wherein an etching gas used in the dry etching comprises a fluorine-containing gas and a hydrogen gas; and
forming a source electrode on the dielectric layer to contact the source contact region through the first contact hole and a drain electrode on the dielectric layer to contact the drain contact region through the second contact hole;
wherein during the dry etching, a pressure is in a range of 30-50 mtorr, a gas source power is in a range of 400-800 W, and a bias voltage is in a range of 100-200 V.

US Pat. No. 10,340,386

ELECTRONIC DEVICE INCLUDING LIGHT DETECTION DEVICE AND OPERATION METHOD THEREOF

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a display exposed through a surface of the housing;
a light emitting unit configured to be disposed on at least a part of a rear surface of the display, and including at least one light source for outputting light of at least one wavelength band;
a light receiving unit configured to include at least one area for receiving light of the at least one wavelength band;
a light blocking element that blocks light output from the at least one light source, from entering a switch for turning on/off at least one pixel of the display;
a processor electrically connected with the display, the light emitting unit, and the light receiving unit; and
a memory electrically connected with the processor,
wherein the memory includes instructions configured to cause, when executed, the processor to output light through the at least one light source in a state where one or more pixels included in a specific area of the display, which includes an area covering the at least one light source, are turned off or displayed in a specific color.

US Pat. No. 10,340,385

METHOD TO IMPROVE FINFET DEVICE PERFORMANCE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate structure comprising a PMOS region and an NMOS region, the PMOS region including a first semiconductor region, a first gate structure on the first semiconductor region, and a first epitaxial grown raised source region and a first epitaxial grown raised drain region on opposite sides of the first gate structure, the NMOS region including a second semiconductor region and a second gate structure on the second semiconductor region;
introducing a p-type dopant into the first epitaxial grown raised source region and the first epitaxial grown raised drain region;
performing a first annealing process on the substrate structure after the p-type dopant has been introduced into the first epitaxial grown raised source region and the first epitaxial grown raised drain region;
forming a second source region and a second drain region on opposite sides of the second gate structure;
introducing an n-type dopant into the second source region and the second drain region; and
performing a second annealing process on the substrate structure after the n-type dopant has been introduced into the second source region and the second drain region.

US Pat. No. 10,340,384

METHOD OF MANUFACTURING FIN FIELD-EFFECT TRANSISTOR DEVICE

Taiwan Semiconductor Manu...

1. A method comprising:forming a first fin protruding above a substrate, the first fin having a PMOS region;
forming a first gate structure over the first fin in the PMOS region;
forming a first spacer layer over the first fin and the first gate structure;
forming a second spacer layer over the first spacer layer;
performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region;
performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and
epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

US Pat. No. 10,340,383

SEMICONDUCTOR DEVICE HAVING STRESSOR LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a fin extending along a first direction over a semiconductor substrate;
a gate structure extending in a second direction overlying the fin,
wherein the gate structure comprises:
a gate dielectric layer overlying the fin;
a gate electrode overlying the gate dielectric layer; and
insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction;
a source/drain region in the fin in a region adjacent the gate structure,
wherein the source/drain region consists essentially of Ge or SiGe and a first dopant; and
a stressor layer between the source/drain region and the semiconductor substrate,
wherein the stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a second dopant, and
a portion of the fin under the gate structure is a channel region.

US Pat. No. 10,340,382

EMBEDDED SOURCE OR DRAIN REGION OF TRANSISTOR WITH DOWNWARD TAPERED REGION UNDER FACET REGION

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a semiconductor structure comprising a body structure;
forming a gate structure over the body structure;
forming a first pair of dielectric structures abutting the body structure;
removing a portion of the body structure and a portion of the first pair of dielectric structures to form downward tapered sidewalls of the first pair of dielectric structures to define a source or drain recess;
growing stressor material with a lattice constant different from that of the body structure in the source or drain recess to form a source or drain region, wherein the source or drain region comprises:
a first region formed above a first level at a top of the first pair of dielectric structures; and
a second region formed under the first level and abutting the downward tapered side walls of the first pair of dielectric structures.

US Pat. No. 10,340,381

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor structure, comprising:providing a substrate;
forming a dielectric layer on the substrate;
forming a gate conductive layer and two spacers disposed in the dielectric layer, wherein the two spacers are respectively disposed on both sides of the gate conductive layer;
forming a high-k layer and a work function metal layer between the gate conductive layer and the substrate;
removing parts of the gate conductive layer, parts of the high-k layer and parts of the work function metal layer;
removing parts of the two spacers, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and wherein a top surface of the high-k layer and a top surface of the work function metal layer are higher than the top surface of the two spacers and lower than the top surface of the gate conductive layer; and
forming a cap layer overlying the gate conductive layer and the two spacers, wherein parts of the cap layer is located right above the two spacers.

US Pat. No. 10,340,380

THREE-DIMENSIONAL TRANSISTOR WITH IMPROVED CHANNEL MOBILITY

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor structure, comprising:a plurality of spaced apart fins, each of said plurality of spaced apart fins comprising a semiconductor material;
a dielectric material layer positioned between each of said plurality of spaced apart fins;
a common gate structure positioned above said dielectric material layer and extending across each of said plurality of spaced apart fins;
a continuous merged semiconductor material region positioned on each of said plurality of spaced apart fins and above said dielectric material layer, wherein said continuous merged semiconductor material region is laterally spaced apart from said common gate structure and extends between and physically contacts each of said plurality of spaced apart fins, said continuous merged semiconductor material region having a first sidewall surface that faces toward said common gate structure and a second sidewall surface that is opposite of said first sidewall surface and faces away from said common gate structure, wherein said first sidewall surface of said continuous merged semiconductor material region, a first portion of opposing sidewall surfaces of an adjacent pair of said plurality of spaced apart fins, and a first portion of an upper surface of said dielectric material layer at least partially define a first space between said continuous merged semiconductor material region and said common gate structure, and wherein said second sidewall surface of said continuous merged semiconductor material region, a second portion of said opposing sidewall surfaces of said adjacent pair of said plurality of spaced apart fins, and a second portion of said upper surface of said dielectric material layer at least partially define a second space on an opposite side of said continuous merged semiconductor material region from said first space; and
a stress-inducing material positioned in said first space.

US Pat. No. 10,340,379

SEMICONDUCTOR DEVICE WITH PLURALITY OF ACTIVE BARRIER SECTIONS

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first output element;
a second output element that is provided to be spaced apart from the first output element when seen in a plan view;
a circuit unit that is provided between the first output element and the second output element when seen in a plan view;
a first element isolation section that is configured in a closed pattern enclosing the circuit unit when seen in a plan view;
a second element isolation section that is configured in a closed pattern enclosing the first element isolation section while spaced apart from the first element isolation section when seen in a plan view;
an isolation section that is connected to the first element isolation section and the second element isolation section and separates a region sandwiched between the first element isolation section and the second element isolation section into a first region and a second region;
a first barrier section that is enclosed by the first region when seen in a plan view; and
a second barrier section that is enclosed by the second region when seen in a plan view.

US Pat. No. 10,340,378

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a second conductivity type;
a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of the first conductivity type;
a gate electrode provided on the first semiconductor region, the gate electrode including
a first portion, the first portion opposing, in a second direction with a gate insulating portion interposed, the second semiconductor region, a portion of the first semiconductor region, and at least a portion of the third semiconductor region, the second direction being perpendicular to a first direction, the first direction being from the first semiconductor region toward the second semiconductor region,
a second portion separated from the first portion in a third direction, the third direction being perpendicular to the first direction and the second direction, and
a third portion positioned between the first portion and the second portion,
a fourth semiconductor region including a first region and being of the second conductivity type, the first region opposing the second portion in the second direction with the gate insulating portion interposed;
an interconnect portion provided on the third portion and electrically connected to the third portion; and
a second electrode provided on the second semiconductor region, the third semiconductor region, and the first region, the second electrode being electrically connected to the second semiconductor region, the third semiconductor region, and the fourth semiconductor region and electrically isolated from the interconnect portion.

US Pat. No. 10,340,377

EDGE TERMINATION FOR SUPER-JUNCTION MOSFETS

Vishay-Siliconix, San Jo...

1. A metal oxide semiconductor field effect transistor (MOSFET) comprising:a core region comprising a plurality of parallel core plates coupled to a source terminal of said super-junction MOSFET; and
a termination region surrounding said core super-junction region comprising
a plurality of termination segments configured to force breakdown into said core super-junction region and away from said termination region,
wherein all said termination segments in said termination region are electrically floating,
wherein each of said termination segments has a length dimension less than a length dimension of said core plates.

US Pat. No. 10,340,376

HETEROJUNCTION FIELD-EFFECT TRANSISTOR HAVING GERMANIUM-DOPED SOURCE AND DRAIN REGIONS

OMMIC, Limeil Brevannes ...

1. A heterojunction field-effect transistor comprising:a semiconductor structure made up of superposed layers, comprising in a stacking order on a substrate layer:
a buffer layer composed of a material having a hexagonal crystal structure of Ga(1-x-y)Al(x)In(y)N, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1,
a channel layer on the buffer layer, the channel layer being composed of a material having a hexagonal crystal structure of Ga(1-z-w)Al(z)In(w)N, where z and w are comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from x or y, respectively, and
a barrier layer on the channel layer, the barrier layer being composed of a material having a hexagonal crystal structure of Ga(1-z?-w?)Al(z?)In(w?)N, where z? and w? are comprised between 0 inclusive and 1 inclusive, the sum z?+w? being lower than or equal to 1, at least one of z? and w? being different from z or w, respectively,
a layer of epitaxial material, deposited by epitaxy on a growth zone corresponding to the location of an opening formed in a dielectric masking layer, the growth material having a hexagonal crystal structure and being composed of Ga(1-x?-y?)Al(x?)In(y?)N and previously-doped with germanium, where x? and y? are comprised between 0 inclusive and 1 inclusive, the sum x?+y? being lower than or equal to 1, at a temperature sufficient for constituent atoms of the semiconductor material having the hexagonal crystal structure of Ga(1-x?-y?)Al(x?)In(y?)N doped with germanium to migrate toward the growth zone, by mass transport, and
a contact electrode on the layer of growth material and a gate electrode in a location outside of the growth zone,
wherein the material doped with germanium has a sufficiently defined crystal structure for lateral edges of the growth layer to have an inclination between 5° and 60° relative to the vertical.

US Pat. No. 10,340,375

EPITAXIAL SUBSTRATE FOR FIELD EFFECT TRANSISTOR

SUMITOMO CHEMICAL COMPANY...

1. An epitaxial substrate for a field effect transistor, said epitaxial substrate comprising:a ground layer;
a first buffer layer that (i) is disposed directly and physically above the ground layer, (ii) has a thickness from 50 angstroms to 2000 angstroms, and (iii) contains only AlN doped with Mn as a compensation impurity element at a first concentration from 1E10 cm?3 to 1E20 cm?3;
a second buffer layer that (i) is disposed directly and physically above the first buffer layer, (ii) has a thickness of 5,000 angstroms or more, and (iii) contains only AlGaN doped with Mn at a second concentration from 1E15 cm?3 to 5E20 cm?3;
an epitaxial crystal layer that (i) is disposed directly and physically above the second buffer layer and (ii) is an undoped epitaxial crystal layer containing only GaN; and
an operating layer that is disposed above the epitaxial crystal layer and comprises undoped AlGaN.

US Pat. No. 10,340,374

HIGH MOBILITY FIELD EFFECT TRANSISTORS WITH A RETROGRADED SEMICONDUCTOR SOURCE/DRAIN

Intel Corporation, Santa...

1. A monolithic high mobility field effect transistor, comprising:a gate electrode over a channel region comprising a first III-V semiconductor material of a first alloy composition; and
a pair of semiconductor source/drain regions impurity doped to a same conductivity type and interfacing the channel region, the source/drain regions comprising a compositionally graded III-V semiconductor alloy varying between:
the first alloy composition proximal to an interface of the channel region and a second alloy composition a first distance from the interface, wherein material with the second alloy composition has a charge carrier-blocking band offset from material with the first alloy composition; and
the second alloy composition and a third alloy composition at a second distance from the interface, material with the third alloy composition having a non-blocking band offset from material with the second alloy composition.

US Pat. No. 10,340,373

REVERSE CONDUCTING IGBT

University of Electronic ...

1. A reverse conducting insulated gate bipolar transistor (RC-IGBT), comprising:a P-type region;
an N-type emitter region;
a P-type body contact region;
a dielectric trench;
a collector region; and
an electrical field cutting-off region,
wherein
the P-type region is formed on a surface of a N-type high resistance semiconductor material,
the N-type emitter region and the P-type body contact region are alternately formed on a surface of the P-type region side by side along a lateral direction of the RC-IGBT,
the dielectric trench is formed in a central region of the N-typed emitter region and passes through the P-type region,
a bottom of the dielectric trench contacts the N-type high resistance semiconductor material,
in the dielectric trench are provided an insulating dielectric layer located at an inner wall of the dielectric trench and a conductive material surrounded by the insulating dielectric layer,
a gate electrode is led out from the conductive material in the dielectric trench to form a trench-gate structure,
a common terminal led out from the N-type emitter region and the P-type body contact region serves as an emitter electrode,
on a backside of the high resistance N-type semiconductor material, a collector region consists of a N-type area and a P-type area that are continuously alternately disposed along the lateral direction of the RC-IGBT,
a common terminal led out from the N-type area and the P-type area serves as a collector electrode,
an electrical field cutting-off region is provided on the top of the collector region,
there is an interval of the N-type high resistance material between the electrical field cutting-off region and the collector region in a longitudinal direction of the RC-IGBT,
the electrical field cutting-off region is formed by N-type heavily doped regions and P-type lightly doped regions that are continuously alternately disposed along the lateral direction of the RC-IGBT, and
the lateral direction and the longitudinal direction of the RC-IGBT are in the same plane and are perpendicular to each other.

US Pat. No. 10,340,372

TRANSISTOR DEVICE HAVING A PILLAR STRUCTURE

Semiconductor Components ...

1. An apparatus, comprising:a first trench disposed in a semiconductor region and including a gate electrode;
a second trench disposed in the semiconductor region;
a mesa region disposed between the first trench and the second trench;
a source region of a first conductivity type disposed in a top portion of the mesa region;
an epitaxial layer of the first conductivity type;
a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type, the second conductivity type being different than the first conductivity type; and
a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to, and in contact with the pillar, and a second portion of the source region is disposed above, and in contact with the pillar.

US Pat. No. 10,340,371

MODULATION DEVICE COMPRISING A NANODIODE

CENTRE NATIONAL DE LA REC...

1. A modulation device made on a substrate including at least one nanodiode which appears as T fitted into a U, a channel of this nanodiode being a leg of the T which penetrates into the U,characterized in that it includes at least one electrically conductive line which passes over at least one portion of this channel thereby forming a switch.

US Pat. No. 10,340,370

ASYMMETRIC GATED FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) DIODES

QUALCOMM Incorporated, S...

1. An asymmetric gated fin Field Effect Transistor (FET) (finFET) diode, comprising:a substrate comprising:
a first-type well region; and
a fin disposed in a direction, the fin comprising:
a first source/drain region having a first length in the direction, wherein, within the first length, the first source/drain region comprises a first-type doped material disposed in the fin and extending in the direction from a first side to a second side of the first-type doped material;
a second source/drain region having a second length in the direction that is larger than the first length, wherein, within the second length, the second source/drain region comprises a second-type doped material disposed in the fin and extending in the direction from a first side to a second side of the second-type doped material; and
a gate region disposed between the first source/drain region and the second source/drain region having a third length in the direction that is equal to the second length plus a difference of the second length and the first length.

US Pat. No. 10,340,369

TUNNELING FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES Inc., Gr...

1. A tunneling field effect transistor device comprising a drain region, a source region and a gate region, the device comprising:a semiconductor substrate;
a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region; and
a gate structure positioned above said first, second and third semiconductor materials in said gate region, wherein said gate structure includes a gate insulation layer and said third semiconductor material has an uppermost surface having a height greater than a height of an uppermost surface of said gate insulation layer.

US Pat. No. 10,340,368

FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a plurality of fins from a first material;
depositing a semiconductor layer formed from a second material over the plurality of fins;
depositing dielectric material covering the plurality of fins and the semiconductor layer, the dielectric material defining dielectric regions; and
diffusing the second material from the semiconductor layer into an entirety of each fin of the plurality of fins.

US Pat. No. 10,340,367

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a spacer layer over a dummy gate, formed over a first portion of a fin structure, and a second portion of the fin structure;
forming a dielectric layer over the spacer layer;
removing the dielectric layer and the spacer layer formed over the dummy gate to expose the first portion of the fin structure;
forming a gate stack over the exposed first portion of the fin structure;
forming trenches by removing the dielectric layer formed over a remaining portion of the spacer layer and a portion of a height of the fin structure underneath the dielectric layer; and
forming source and drain contacts by filling the trenches with a metal.

US Pat. No. 10,340,366

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;
forming a dummy gate structure over a part of the fin structure, the dummy gate structure extending in a second direction crossing the first direction;
removing the dummy gate structure and forming a gate structure in a region in which the dummy gate structure is removed;
forming an interlayer dielectric layer over the fin structure and the gate structure;
forming a contact hole in the interlayer dielectric layer so that a part of the fin structure is exposed;
forming a source/drain structure on the exposed fin structure;
directly depositing a cap layer, by using a first gas and a second gas, on the source/drain structure, the cap layer covering a bottom surface and sidewalls of the contact hole;
forming a dielectric layer over the cap layer; and
forming a contact metal layer over the dielectric layer.

US Pat. No. 10,340,365

METHOD OF MANUFACTURING A THIN FILM TRANSISTOR

SHENZHEN CHINA STAR OPTOE...

1. A method of manufacturing a thin film transistor, comprising:providing a substrate;
depositing a buffer layer on the substrate and patterning the buffer layer, so as to form an active area of a thin film transistor;
sequentially depositing an insulation layer and a first metal layer on the substrate;
coating a photoresist on a gate region and a lightly doped region of the first metal layer, wherein the gate region and the lightly doped region are covered by a projection of the active area on the first metal layer;
metal etching the first metal layer excluding the gate region and the lightly doped region for exposing the insulation layer;
ashing the photoresist for exposing the lightly doped region of the first metal layer;
metal etching the first metal layer at the lightly doped region for forming a metal half tone mask;
implanting ions to the active area for forming a source region, a source lightly doped region, a channel region, a drain lightly doped region, and a drain region of the thin film transistor;
removing the photoresist;
depositing a media layer over the substrate, and forming a source through-hole and a drain through-hole on the media layer;
depositing a second metal layer over the substrate, and patterning the second metal layer, so as to form a source and a drain of the thin film transistor through the source through-hole and the drain through-hole;
depositing an organic planarization layer over the substrate, and forming a pixel electrode through-hole on the organic planarization layer; and
depositing a pixel electrode layer over the substrate, and patterning the pixel electrode layer, so as to form a corresponding pixel electrode through the pixel electrode through-hole;
wherein the step of depositing the buffer layer on the substrate and patterning the buffer layer, comprises:
depositing an amorphous silicon buffer layer on the substrate;
annealing the amorphous silicon buffer layer to form a polycrystalline silicon buffer layer; and
patterning the polycrystalline silicon buffer layer.

US Pat. No. 10,340,364

H-SHAPED VFET WITH INCREASED CURRENT DRIVABILITY

International Business Ma...

1. A method of forming a fin structure for a vertical field effect transistor (VFET), the method comprising the steps of:depositing a hardmask onto a substrate;
depositing a mandrel material onto the hardmask;
patterning the mandrel material along a first direction to form first mandrels;
forming first spacers alongside the first mandrels;
filling gaps between the first mandrels with additional mandrel material to form second mandrels in between the first mandrels;
patterning the first mandrels, the first spacers and the second mandrels along a second direction, wherein the second direction is perpendicular to the first direction;
forming second spacers, perpendicular to the first spacers, alongside the first mandrels and the second mandrels;
selectively removing the first mandrels and the second mandrels leaving behind a ladder-shaped pattern formed by the first spacers and the second spacers;
transferring the ladder-shaped pattern to the hardmask; and
transferring the ladder-shaped pattern from the hardmask to the substrate to form a first fin adjacent to a second fin, and at least one cross fin interconnecting the first fin and the second fin; and
cutting the ladder-shaped pattern in the substrate into individual fin structures, wherein cuts made during the cutting are located to form each individual fin structure comprising: a first cross fin interconnecting the first fin and the second fin at one end of the individual fin structure, and a second cross fin interconnecting the first fin and the second fin at another end of the individual fin structure in an O-shaped fin structure.

US Pat. No. 10,340,363

FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED BOTTOM INSULATING SPACERS

International Business Ma...

18. A semiconductor device, comprising:a vertical field effect transistor (FET) device on a semiconductor substrate, wherein the vertical FET device comprises:
a semiconductor fin formed on a recessed surface of a semiconductor substrate;
a lower source/drain region formed on the recessed surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region comprises a first type of epitaxial semiconductor material;
a self-aligned bottom insulating spacer formed on the lower source/drain region, the self-aligned bottom insulating spacer comprising an oxide layer formed from oxidation of a second type of epitaxial semiconductor material epitaxially grown on the lower source/drain region, which is different from the first type of epitaxial semiconductor material;
a gate structure formed in contact with sidewalls of the semiconductor fin;
an upper insulating spacer formed on the gate structure; and
an upper source/drain region formed on an upper portion of the semiconductor fin;
wherein the self-aligned bottom insulating spacer electrically insulates the lower source/drain region from the gate structure;
wherein the upper insulating spacer electrically insulates the upper source/drain region from the gate structure; and
wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium that is greater than the first concentration of germanium.

US Pat. No. 10,340,362

SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A structure comprising:a semiconductor body having a top surface;
an epitaxial layer of semiconductor material on the semiconductor body;
a first gate structure on the semiconductor body, the first gate structure having a sidewall;
a first spacer adjacent to the sidewall of the first gate structure, the first spacer having a first section and a second section vertically between the first section and the top surface of the semiconductor body, the first section of the first spacer having a first thickness, and the second section of the first spacer having a second thickness different from the first thickness; and
a conformal layer on the first spacer and the epitaxial layer of semiconductor material,
wherein the second section of the first spacer is located between the epitaxial layer of semiconductor material and the sidewall of the first gate structure, the first spacer is composed of SiBCN having a first dielectric constant, and the conformal layer is composed of SiBCN having a second dielectric constant that is less than the first dielectric constant of the SiBCN of the first spacer.

US Pat. No. 10,340,361

FORMING OF A MOS TRANSISTOR BASED ON A TWO-DIMENSIONAL SEMICONDUCTOR MATERIAL

1. A MOS transistor manufacturing method, comprising the successive steps of:a) forming a first layer made of a conductive or semiconductor material on a surface of a support substrate;
b) forming a sacrificial gate on the upper surface of the first layer, and a second layer made of an insulating material laterally surrounding the sacrificial gate;
c) forming, on either side of the sacrificial gate, source and drain electric connection elements made of a conductive material, crossing the second layer and contacting the first layer;
d) removing the sacrificial gate and the portion of the first layer located vertically in line with the sacrificial gate;
e) depositing a third layer made of a two-dimensional semiconductor material on the sides and on the bottom of an opening formed at step d) by the removal of the sacrificial gate and of the first layer);
f) depositing a fourth layer made of an insulating material on the third layer; and
g) forming a conductive gate in the opening, on the fourth layer.

US Pat. No. 10,340,360

NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A nitride semiconductor device comprising:an electron transit layer including GaxIn1-xN (0 an electron supply layer formed on the electron transit layer and including AlaGabIncN (0?a?1, 0?b?1, 0?c?1 and a+b+c=1);
a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and
a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween,
wherein the gate insulating film includes an oxide of the electron supply layer.

US Pat. No. 10,340,359

GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER

GLOBALFOUNDRIES Inc., Gr...

1. A high-k dielectric metal gate (HKMG) transistor, comprising:a substrate;
an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above said substrate, wherein said gate electrode layer has an upper portion and a lower portion;
a first liner contacting a sidewall portion of said upper portion;
a spacer contacting said first liner and a sidewall portion of said lower portion; and
raised source and drain regions adjacent said spacer, wherein a height of an uppermost surface of said spacer is greater than a height of an uppermost surface of said raised source and drain regions, and a width of said upper portion between said raised source and drain regions is smaller than a width of said lower portion between said raised source and drain regions.

US Pat. No. 10,340,358

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate;
a first active pattern disposed on the substrate and spaced apart from the substrate;
a gate insulating film which surrounds the first active pattern;
a first work function adjustment film which surrounds the gate insulating film and comprises carbon; and
a first barrier film which surrounds the first work function adjustment film,
wherein a carbon concentration of the first work function adjustment film increases as it goes away from the first barrier film.

US Pat. No. 10,340,357

DISHING PREVENTION DUMMY STRUCTURES FOR SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:an inner ring-shaped isolation structure disposed in a semiconductor substrate, wherein the inner ring-shaped isolation structure demarcates a device region;
an inner ring-shaped well disposed in the semiconductor substrate and surrounding the inner ring-shaped isolation structure;
an outer ring-shaped isolation structure disposed in the semiconductor substrate and surrounding the inner ring-shaped well;
an outer ring-shaped well disposed in the semiconductor substrate and surrounding the outer ring-shaped isolation structure; and
a plurality of dummy gates arranged over both the inner ring-shaped well and the outer ring-shaped isolation structure, wherein the plurality of dummy gates are disposed in an interlayer dielectric (ILD) layer.

US Pat. No. 10,340,356

LAMINATED ARTICLE

IDEMITSU KOSAN CO., LTD.,...

1. A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, whereina reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.

US Pat. No. 10,340,355

METHOD OF FORMING A DUAL METAL INTERCONNECT STRUCTURE

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming source/drain regions on opposite sides of at least one gate structure located over a channel region of a semiconductor fin;
forming a single interlevel dielectric (ILD) layer overlying the source/drain regions and the at least one gate structure;
forming source/drain contact trenches through the ILD layer, each of the source/drain contact trenches exposing at least a portion of one of the source/drain regions; and
forming a source/drain contact structure within each of the source/drain contact trenches, wherein each of the source/drain contact structures comprises a first contact conductor portion located at a bottom portion of each of the source/drain contact trenches and contacting one of the source/drain regions, and a second contact conductor portion overlying the first contact conductor portion, wherein the first contact conductor comprises a first metal and the second contact conductor portion comprises a second metal having a lower electromigration resistance and a lower electrical resistance than the first metal, and wherein each of the source/drain contact structures further comprises an elemental metal liner located on sidewalls of each of the source/drain contact trenches, a metal nitride liner located on the elemental metal liner and a bottom surface of each of the source/drain contact trenches, wherein the metal nitride liner contacts sidewalls and a bottommost surface of the first contact conductor portion, a contact liner located over the metal nitride liner and directly contacting a top surface of the first contact conductor portion, and an adhesion layer portion located on the contact liner and contacting sidewalls and a bottommost surface of the second contact conductor portion, wherein the elemental metal liner has a bottommost surface that is coplanar with a bottommost surface of the metal nitride liner.

US Pat. No. 10,340,354

MANUFACTURING METHOD OF THIN-FILM TRANSISTOR (TFT) ARRAY SUBSTRATE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing a thin-film transistor (TFT) array substrate, comprising:forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a transparent conductive layer on a base substrate,
wherein the forming of the source/drain electrode layer and the transparent conductive layer includes:
forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer;
forming source electrodes, drain electrodes and pixel electrodes by performing a single patterning process on the stack layer of the transparent conductive film and the first metallic film; and
forming a protective layer film on the first metallic film, and forming the pixel electrodes, the source electrodes, the drain electrodes, and the protective layer by performing a single patterning process on the transparent conductive film, the first metallic film, and the protective layer film;
wherein the protective layer film includes at least one of ITO IZO, IGZO, GZO, or carbon nanotube conductive films.

US Pat. No. 10,340,353

EPITAXIAL METALLIC TRANSITION METAL NITRIDE LAYERS FOR COMPOUND SEMICONDUCTOR DEVICES

The United States of Amer...

9. A semiconductor device, comprising:a substrate;
an epitaxial metal layer selected from the group consisting of TaNx, NbNx, WNx, MoNx, TMN ternary compounds, and combinations thereof; and
at least one epitaxial semiconductor layer comprising a semiconductor material selected from the group consisting of SiC or AlN;
wherein the in-plane lattice constants of the substrate, the epitaxial metal layer, and the epitaxial semiconductor layer are within 2% of one another; and
wherein the epitaxial metal layer is in direct contact with the substrate and the at least one epitaxial semiconductor layer is in direct contact with the epitaxial metal layer to form an epitaxial metal/semiconductor heterostructure, or the at least one epitaxial semiconductor layer is in direct contact with the substrate and the epitaxial metal layer is in direct contact with the at least one epitaxial semiconductor layer to form an epitaxial metal/semiconductor heterostructure.

US Pat. No. 10,340,352

FIELD-EFFECT TRANSISTORS WITH A T-SHAPED GATE ELECTRODE

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a field-effect transistor, the method comprising:forming a first dielectric layer on a semiconductor layer;
forming a second dielectric layer on the first dielectric layer;
forming a first opening extending vertically through the first dielectric layer and the second dielectric layer;
after the first opening is formed, laterally recessing the second dielectric layer relative to the first dielectric layer with a selective etching process so as to widen a first portion of the first opening extending vertically through the second dielectric layer relative to a second portion of the first opening extending vertically through the first dielectric layer;
after the second dielectric layer is laterally recessed, forming a gate dielectric layer on an area of a top surface of the semiconductor layer exposed through the first portion of the first opening in the first dielectric layer; and
after forming the gate dielectric layer, forming a gate electrode that includes a wide section in the first portion of the first opening and a narrow section in the second portion of the first opening,
wherein the narrow section of the gate electrode is in contact with the gate dielectric layer, and the gate dielectric layer is arranged between the narrow section of the gate electrode and the top surface of the semiconductor layer.

US Pat. No. 10,340,351

SEMICONDUCTOR DEVICE

ROHM CO., LTD, Kyoto (JP...

1. A semiconductor device comprising:a first conductivity type SiC substrate;
a first conductivity type epitaxial layer formed on a side of one surface of the SiC substrate;
a second conductivity type body region formed at a surface portion of the epitaxial layer;
a gate trench formed in the epitaxial layer so as to penetrate the body region from a surface of the epitaxial layer;
a gate insulating film formed on an inner surface of the gate trench; and
a gate electrode formed on the gate insulating film, wherein
the gate electrode is made of a same material as the body region.

US Pat. No. 10,340,350

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:an isolation layer on a substrate, the isolation layer having a first gate trench;
a gate dielectric layer in the first gate trench;
a tantalum nitride layer on the gate dielectric layer;
a tantalum oxynitride layer on the tantalum nitride layer;
an n type work function metal layer formed on the tantalum oxynitride layer in the first gate trench; and
a filling metal formed on the n type work function metal layer in the first gate trench;
wherein the tantalum oxynitride layer has a gradient oxygen concentration decreased from a top surface of the tantalum oxynitride layer toward the tantalum nitride layer.

US Pat. No. 10,340,349

METHOD OF FORMING SEMICONDUCTOR STRUCTURE

United Microelectronics C...

1. A method of forming a semiconductor structure, comprising:providing a substrate having a first area and a second area, wherein a first surface of the first area is lower than a second surface of the second area;
sequentially forming a first insulating layer, a first gate, a first dielectric layer and a first dummy gate on the first surface of the first area;
forming a second dielectric layer and a second dummy gate on the second surface of the second area;
forming an inter-layer dielectric layer around the first gate, the first dummy gate and the second dummy gate;
removing the first dummy gate and the second dummy gate, so as to form a first trench and a second trench in the inter-layer dielectric layer; and
filling a second gate and a third gate respectively in the first trench and the second trench,
wherein the method further comprises forming a fourth gate on the first surface at one side of the first gate, and the fourth gate and the first gate are formed simultaneously, and
wherein the method of forming the first gate, the first dummy gate, the second dummy gate and the fourth gate comprises:
sequentially forming a first insulating material layer and a first conductive layer on the substrate in the first area;
forming a first dielectric material layer on the first conductive layer in the first area and forming a second dielectric material layer on the substrate in the second area;
forming a second conductive layer on the first dielectric material layer and on the second dielectric material layer;
performing a first patterning step, so as to form a first stacked structure and a second stacked structure on the substrate in the first area, wherein the first stacked structure comprises the first insulating layer, the first gate, the first dielectric layer and the first dummy gate; and
performing a second patterning step, so as to form the second dielectric layer and the second dummy gate on the substrate in the second area, wherein during the second patterning step, a portion of the second stacked structure is simultaneously removed and the fourth gate remains.

US Pat. No. 10,340,348

METHOD OF MANUFACTURING FINFETS WITH SELF-ALIGN CONTACTS

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a first fin structure and a second fin structure over a substrate, the first and second fin structures extending in a first direction and being arranged in a second direction crossing the first direction, the first fin structure being arranged in parallel with the second fin structure;
forming an isolation insulating layer over the substrate such that upper portions of the first and second fin structures are exposed from the isolation insulating layer;
forming a first gate structure and a second gate structure over parts of the first and second fin structures, the first and second gate structures extending in the second direction and being arranged in the first direction in parallel with each other;
forming an interlayer dielectric layer made of a silicon oxide based material on the first and second gate structures and over the first and second fin structures;
forming a first mask pattern having a first opening over the interlayer dielectric layer, the first opening being located above the first and second gate structures; and
cutting the first and second gate structures through the first opening of the first mask pattern, wherein:
the method further comprises:
etching the isolation insulating layer and the interlayer dielectric layer through the first opening so as to form a first recess;
forming an insulating layer in the first recess;
forming a second mask pattern having a second opening so as to expose a part of the insulating layer in the first recess and a part of the interlayer dielectric layer;
etching the exposed part of the interlayer dielectric layer through the second opening so as to form a second recess; and
forming a conductive material in the second recess, and
the second mask pattern has a third opening so as to expose a part of the insulating layer outside the first recess,
in the etching the exposed part of the interlayer dielectric layer through the second opening, the part of the insulating layer outside the first recess is etched so as to form a third recess, and
in the forming the conductive material in the second recess, the conductive material is also formed in the third recess.

US Pat. No. 10,340,347

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE

PANASONIC INTELLECTUAL PR...

1. A semiconductor device in a face-down, chip-size package, including: a semiconductor substrate that is rectangular and includes an impurity of a first conductivity type; a low-concentration impurity layer that is in contact with a top surface of the semiconductor substrate and includes an impurity of the first conductivity type in a lower concentration than a concentration of the impurity of the first conductivity type included in the semiconductor substrate; and a metal layer that is in contact with an entire bottom surface of the semiconductor substrate and includes only a metal material, the semiconductor device having a curvature at room temperature that curves in a lengthwise direction of the semiconductor substrate, the semiconductor device comprising:a first vertical metal oxide semiconductor (MOS) transistor in a first region of the low-concentration impurity layer; and
a second vertical MOS transistor in a second region of the low-concentration impurity layer adjacent to the first region,
wherein the first vertical MOS transistor includes, on a surface of the low-concentration impurity layer, a first gate electrode and a plurality of first source electrodes,
the second vertical MOS transistor includes, on the surface of the low-concentration impurity layer, a second gate electrode and a plurality of second source electrodes,
the semiconductor substrate acts as a common drain region for a first drain region of the first vertical MOS transistor and a second drain region of the second vertical MOS transistor,
a bidirectional channel from the plurality of first source electrodes to the plurality of second source electrodes via the first drain region, the metal layer, and the second drain region is a principal current channel,
in a plan view of the semiconductor substrate, the first gate electrode is arranged with no other electrode disposed between the first gate electrode and a first short side of the semiconductor substrate,
the plurality of first source electrodes include a plurality of first source electrodes that are approximately rectangular in a plan view of the semiconductor substrate,
in a plan view of the semiconductor substrate, the plurality of first source electrodes that are approximately rectangular are arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate,
in a plan view of the semiconductor substrate, the second gate electrode is arranged with no other electrode disposed between the second gate electrode and a second short side of the semiconductor substrate,
the plurality of second source electrodes include a plurality of second source electrodes that are approximately rectangular in a plan view of the semiconductor substrate,
in a plan view of the semiconductor substrate, the plurality of second source electrodes that are approximately rectangular are arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate,
in a plan view of the semiconductor substrate, a boundary line between the first region and the second region is an approximate line segment, and
in a plan view of the semiconductor substrate, the first gate electrode and the second gate electrode are symmetrical to one another with respect to the boundary line, and the plurality of first source electrodes and the plurality of second source electrodes are symmetrical to one another with respect to the boundary line.

US Pat. No. 10,340,346

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a drain layer of a first conductivity type extending in a first direction and a second direction crossing the first direction;
a drift layer of the first conductivity type formed on a surface that is one surface perpendicular to a third direction crossing the first direction and the second direction of the drain layer;
a base region of a second conductivity type formed on a surface of the drift layer;
a source region of the first conductivity type formed on a surface of the base region;
a plurality of trenches formed in an array in the first direction and the second direction, the plurality of trenches each reaching the drift layer through the base region along the third direction from a surface of the source region;
a base contact region of the second conductivity type formed along the second direction in a region in which the plurality of trenches do not contiguously exist along the second direction between the plurality of trenches along the first direction, the base contact region being formed in the source region to electrically connect the source region to the base region being separate from the plurality of trenches;
a plurality of gate regions each formed along an inner wall of corresponding one of the plurality of trenches, via an insulating film, inside the corresponding one of the plurality of trenches;
a plurality of field plate electrodes each formed in an adjacent from corresponding one of the gate regions, via the insulating film, inside the corresponding one of the plurality of trenches along the third direction, and formed longer than the corresponding one of the gate regions in the third direction;
a plurality of first source contacts each formed on the base contact region and the source region along the second direction between the plurality of trenches along the first direction, the first source contacts electrically connect the base contact region to the source region;
a plurality of second source contacts on each of the field plate electrode connected the corresponding one of the field plate electrodes;
a plurality of gate contacts on the corresponding one of the gate regions, electrically connected the corresponding gate region;
a first metal layer being connected to the base contact region and the source region via a first source contact, and being connected to corresponding one of the field plate electrodes via a second source contact;
a second metal layer being insulated via the insulating film from the first metal layer, and being connected to corresponding one of the gate regions via a gate contact; and
a third metal layer formed to be layered in the third direction of the first metal layer and the second metal layer, to be connected to the first metal layer and to be insulated from the second metal layer via the insulating film.

US Pat. No. 10,340,345

NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR

SUMITOMO CHEMICAL COMPANY...

1. A nitride semiconductor epitaxial wafer, comprising:a substrate;
a GaN layer configured to be an electron transit layer provided over the substrate;
an AlGaN layer configured to be an electron feed layer provided over the GaN layer;
wherein the GaN layer comprises a wurtzite crystal structure, and a measured ratio c/a of the lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in the a-axis orientation of the GaN layer is not more than 1.6266 despite the application of lattice mismatch stresses at interfaces between the GaN layer and the substrate and the AlGaN layer, and
wherein the measured ratio c/a allows the occurrence of only negative charges on the surface of the GaN layer on which a two-dimensional electron gas is induced spatially due to the lattice mismatch stresses to suppress current collapse.

US Pat. No. 10,340,344

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Sumitomo Electric Industr...

1. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of:preparing an intermediate substrate including one main surface and the other main surface opposite to the one main surface;
arranging a sodium blocking member as being in contact with the one main surface of the intermediate substrate;
annealing the intermediate substrate while the sodium blocking member is in contact with the one main surface; and
removing the sodium blocking member from the one main surface after the step of annealing the intermediate substrate,
the intermediate substrate including a silicon carbide substrate having a first main surface facing the one main surface and a second main surface opposite to the first main surface, which forms the other main surface of the intermediate substrate, a gate insulating film partially in contact with the first main surface of the silicon carbide substrate, and a source electrode in contact with the first main surface exposed through the gate insulating film, and
the sodium blocking member being composed of a material having a diffusion constant of sodium not greater than a diffusion constant of sodium into the silicon carbide substrate.

US Pat. No. 10,340,343

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate electrode over the semiconductor substrate;
a channel region between the semiconductor substrate and the gate electrode;
a pair of source/drain regions adjacent to two opposing sides of the channel region in a channel length direction; and
a threshold voltage adjusting region adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type, and a depth of the threshold voltage adjusting region is greater than a depth of the pair of source/drain regions.

US Pat. No. 10,340,342

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a collection region;
a base region adjacent to the collection region;
an emission region adjacent to the base region, wherein the base region comprises:
a first base region; and
a second base region, wherein the collection region is located on a first side of the first base region, the second base region is located on a second side of the first base region opposite the first side of the first base region, the second base region is located between the emission region and the first base region, is adjacent to the emission region, and has a width smaller than the width of the first base region; and
a doped semiconductor layer on the emission region, wherein the width of the doped semiconductor layer is larger than the width of the emission region, a conductive type of the doped semiconductor layer is the same as a conductive type of the emission region.

US Pat. No. 10,340,341

SELF-LIMITING AND CONFINING EPITAXIAL NUCLEATION

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a semiconductor device, the method comprising:forming a fin in a substrate, the fin comprising a first semiconductor material;
depositing a spacer material on the fin;
recessing the spacer material so that a surface of the fin is exposed;
removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the first semiconductor material of the fin on the lateral sidewalls; and
depositing a second semiconductor material within the recess.

US Pat. No. 10,340,340

MULTIPLE-THRESHOLD NANOSHEET TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, comprising:forming a stack of alternating layers of channel material and sacrificial material;
etching away the sacrificial material to free the layers of channel material;
forming a gate stack around the layers of channel material;
forming source and drain regions by epitaxially growing the source and drain regions from sidewalls of each layer of channel material; and
deactivating at least one layer of channel material by etching back the source and drain regions, such that the etched source and drain regions do not contact the at least one deactivated layer of channel material.

US Pat. No. 10,340,339

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Nuvoton Technology Corpor...

9. A semiconductor device, comprising:a substrate, comprising a first region, a second region, and a third region, wherein the second region is located between the first region and the third region;
an isolation structure, located on the substrate in the second region, the isolation structure comprising a top surface, a bottom surface, and a sidewall, the sidewall of the isolation structure being substantially perpendicular to a top surface of the substrate and connecting the top surface and the bottom surface at a second side of the isolation structure, and the top surface of the isolation structure being a step-like top surface, wherein at least a part of the bottom surface of the isolation structure and the top surface of the substrate are substantially coplanar, and the isolation structure continuously extends from one end of the second region to another end of the second region;
a gate structure, disposed at a first side of the isolation structure and extending from a part of the substrate in the first region to cover the step-like top surface of the isolation structure;
a first doped region of a first conductive type, located in the substrate in the first region, and adjacent to one side of the gate structure; and
a second doped region of the first conductive type, located in the substrate in the third region, and exposed by the second side of the isolation structure,
wherein a level of the step-like top surface of the isolation structure gradually decreases from the second side of the isolation structure toward the first side of the isolation structure.

US Pat. No. 10,340,338

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first surface;
an insulating isolation structure disposed at a side of the first surface and composed of an insulator having a first depth; and
a gate electrode,
the semiconductor substrate having a source region disposed in contact with the first surface, a drain region disposed in contact with the first surface, a reverse conductivity region disposed in contact with the first surface and having a second depth, a body region disposed in contact with the first surface so as to surround the source region, and a drift region disposed in contact with the first surface so as to surround the drain region and the reverse conductivity region and sandwich the body region between the source region and the drift region,
the source region, the drift region, and the drain region being of a first conductivity type,
the body region and the reverse conductivity region being of a second conductivity type which is opposite to the first conductivity type,
the reverse conductivity region being disposed between the source region and the drain region,
the insulating isolation structure being disposed between the drain region and the reverse conductivity region,
the gate electrode facing and being insulated from a portion of the body region which is sandwiched by the source region and the drift region,
the first depth being larger than the second depth.

US Pat. No. 10,340,337

DIODE STRUCTURE OF A POWER SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A power semiconductor device comprising a semiconductor body coupled to each of a first load terminal and a second load terminal, wherein the semiconductor body comprises:a drift region with dopants of a first conductivity type;
at least a diode structure configured to conduct a load current between the terminals and comprising an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal;
a field stop region with dopants of the first conductivity type at a higher dopant concentration than the drift region, the field stop region being arranged between the cathode port and the drift region;
wherein the cathode port comprises:
first port sections with dopants of the first conductivity type and second port sections with dopants of a second conductivity type complementary to the first conductivity type, a transition between each of the second port sections and the field stop region forming a respective pn-junction that extends along a first lateral direction, wherein a diffusion voltage of a respective one of the pn-junctions in an extension direction perpendicular to the first lateral direction is greater than a lateral voltage drop laterally overlapping with the lateral extension of the respective pn-junction.

US Pat. No. 10,340,336

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGIONS

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure;
an active cell field implemented in the semiconductor body and configured to conduct a load current;
a plurality of first cells and a plurality of second cells provided in the active cell field, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
wherein:
each first cell comprises a first mesa, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
each second cell comprises a second mesa, the second mesa including: a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
wherein the first channel region has the first conductivity type and wherein the second channel region has the second conductivity type;
each first cell is configured to induce a current path for charge carriers of the first conductivity type within the first channel region; and
each second cell is configured to induce an accumulation channel for charge carriers of the second conductivity type within the second channel region.

US Pat. No. 10,340,335

METHOD OF FORMING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method of forming a semiconductor device, the method comprising:forming a trench in a semiconductor body at a first surface of the semiconductor body;
introducing first dopants into a first region at a bottom side of the trench by ion implantation;
subsequent to introducing the first dopants, forming a first filling material in the trench, wherein the first filling material is formed over the first region including the first dopants;
introducing second dopants into a second region at a top side of the first filling material, wherein introducing the second dopants into the second region includes introducing the second dopants into the first filling material at an entire top surface of the first filling material located at the top side of the first filling material, and introducing the second dopants is performed subsequent to forming the first filling material in the trench; and
thermal processing of the semiconductor body configured to intermix, within the first filling material, the first and the second dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface;
wherein the semiconductor body is a silicon carbide semiconductor body and the first and the second dopants comprise boron or gallium; and
wherein a ratio of a diffusion coefficient of the first and the second dopants in the first filling material and a diffusion coefficient of the first and the second dopants in the semiconductor body is greater than two with respect to a temperature of 1100° C.

US Pat. No. 10,340,334

SEMICONDUCTOR DEVICE INCLUDING AN LDMOS TRANSISTOR AND A RESURF STRUCTURE

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface;
an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate; and
a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate,
wherein the LDMOS transistor comprises a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type,
wherein the source region comprises a first well and a second well of the same second conductivity type,
wherein the first well is more highly doped than the second well,
wherein the first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

US Pat. No. 10,340,333

III-NITRIDE POWER SEMICONDUCTOR DEVICE

Infineon Tecimologies Ame...

1. A power semiconductor device, comprising:a III-nitride heterojunction body that includes a first III-nitride body and a second III-nitride body having a different band gap than that of said first III-nitride body;
a first power electrode comprising a conductive material coupled to said second III-nitride body;
a second power electrode comprising said conductive material coupled to said second III-nitride body;
a gate arrangement including a gate electrode disposed between said first and said second power electrodes;
a conductive channel that includes a two-dimensional electron gas (2DEG) that in a conductive state includes a reduced charge region produced by an implanted region in said second III-nitride body under said gate electrode, wherein said reduced charge region is less conductive than regions of said 2DEG adjacent each side of said reduced charge region;
said implanted region having implanted charge in said second III-nitride body, said implanted charge configured to repel electrons in said 2DEG under and beyond edges of said gate electrode;
said reduced charge region extending beyond at least one of said edges of said gate electrode and comprising negative charge which repels negative carriers in a region below said gate arrangement, said conductive channel being devoid of said negative charge in said regions of said 2DEG adjacent each side of said reduced charge region.

US Pat. No. 10,340,332

FOLDED TERMINATION WITH INTERNAL FIELD PLATE

UNIVERSITY OF ELECTRONIC ...

1. A junction termination with an internal field plate comprising: a heavily doped substrate of a first conductive type semiconductor, a lightly doped drift region of the first conductive type semiconductor on an upper surface of the heavily doped substrate of the first conductive type semiconductor, and a metal drain electrode on a lower surface of the heavily doped substrate of the first conductive type semiconductor; wherein the lightly doped drift region of the first conductive type semiconductor is provided with a trench, and the trench is located in a middle of the lightly doped drift region of the first conductive type semiconductor and extends vertically downward into the lightly doped drift region of the first conductive type semiconductor along an upper surface of the lightly doped drift region of the first conductive type semiconductor, the trench is filled with insulating dielectric; the upper surface of the lightly doped drift region of the first conductive type semiconductor is provided with a field oxide layer; a side of the trench near an active region of a device is provided with a first semiconductor implantation region, and the first semiconductor implantation region is respectively connected to a main junction of a second conductive type semiconductor of the active region and the trench, and an upper surface of the first semiconductor implantation region is in contact with the field oxide layer, a lower surface of the first semiconductor implantation region is in contact with a second semiconductor implantation region, a side of the second semiconductor implantation region is in contact with the trench; the first semiconductor implantation region and the second semiconductor implantation region are both the second conductive type semiconductor, and a concentration of the first semiconductor implantation region is greater than a concentration of the second semiconductor implantation region; an end of the upper surface of the lightly doped drift region of the first conductive type semiconductor, distant from the active region of the device, is provided with a heavily doped region of the first conductive type semiconductor, an upper surface of the heavily doped region of the first conductive type semiconductor is in contact with the field oxide layer; an upper surface of the field oxide layer is provided with a polysilicon layer; a polysilicon field plate is in the trench, and an upper surface of the polysilicon field plate is in contact with the polysilicon layer.

US Pat. No. 10,340,331

METHODS OF FORMING AN ARRAY OF CAPACITORS, METHODS OF FORMING AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR, ARRAYS OF CAPACITORS, AND ARRAYS OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR

Micron Technology, Inc., ...

1. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:forming elevationally-extending transistors over columns of data/sense lines, individual of the transistors comprising a lower source/drain region directly electrically coupled to one of the data/sense lines, the transistors comprising rows of access lines above the data/sense lines, individual of the access lines extending laterally across and operatively laterally adjacent a lateral side of transistor channels and interconnecting the transistors in that row;
forming elevationally-extending and longitudinally-elongated capacitor electrode lines, individual of the capacitor electrode lines being common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed longitudinally along a line of the transistors;
forming a capacitor insulator over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines and over the tops of the individual capacitor electrode lines;
forming an elevationally-extending conductive line over the capacitor insulator longitudinally along each of a pair of laterally-opposing sides of the individual capacitor electrode lines, individual of the conductive lines on one of the laterally-opposing sides of the individual capacitor electrode lines being directly electrically coupled to upper source/drain regions of individual transistors longitudinally along that line of transistors, laterally-extending conductive material atop the capacitor insulator that is over the tops of the respective individual capacitor electrode lines directly electrically coupling together the conductive lines that are along each of a pair of laterally-opposing sides of the respective individual capacitor electrode lines; and
cutting laterally through the conductive lines on each of the laterally-opposing sides of the individual capacitor electrode lines and through the laterally-extending conductive material to form spaced individual other of the two capacitor electrodes of the individual capacitors, the cutting forming individual of the other capacitor electrodes to comprise an elevationally-extending first member directly electrically coupled to and extending elevationally upward from the upper source/drain regions of the individual transistors longitudinally along that line of transistors on the one laterally-opposing side of the individual capacitor electrode lines, the cutting forming individual of the other capacitor electrodes to comprise an elevationally-extending second member laterally spaced from the first member on the other laterally-opposing side of the individual capacitor electrode lines, and the cutting forming the laterally-extending conductive material as part of the spaced individual other of the two capacitor electrodes of the individual capacitors.

US Pat. No. 10,340,330

PRECISION BEOL RESISTORS

International Business Ma...

1. A semiconductor structure comprising:a lower interconnect level including first metal-containing structures embedded within a first interconnect dielectric material layer;
an upper interconnect level located above the lower interconnect level and comprising second metal-containing structures embedded within a second interconnect dielectric material layer;
a resistor present in the upper interconnect level, wherein the resistor has a bottommost surface that is coplanar with a topmost surface of the first interconnect dielectric material layer and a topmost surface that is located entirely beneath a topmost surface of the second interconnect dielectric material layer; and
a continuous dielectric cap located directly on an entirety of the topmost surface of the resistor, directly on a topmost surface of the second interconnect dielectric material layer, and directly on a topmost surface of the second metal-containing structures.

US Pat. No. 10,340,329

DISPLAY PANEL INCLUDING POWER SUPPLY COMPENSATION FILM HAVING REDUCED SHEET RESISTANCE ARRANGED ON OPPOSITE SURFACE OF SUBSTRATE FROM POWER SUPPLY LINE LAYER

Shanghai Tianma Micro-Ele...

1. A display panel, comprising:a substrate, a power supply line layer and a power supply compensation film, wherein the power supply compensation film is arranged on a back surface of the substrate, the power supply line layer is arranged on a front surface of the substrate, and the back surface of the substrate is a surface opposite to a light emitting surface of the display panel;
the display panel comprises:
a display area and a non-display area surrounding the display area, and the non-display area comprises a first frame area and a second frame area positioned on two opposite sides of the display area;
the power supply line layer comprises:
a first power supply line arranged in the first frame area and the second frame area, and a plurality of second power supply lines arranged in the display area, and the first power supply line is electrically connected with the plurality of second power supply lines; and
the power supply compensation film is electrically connected with the first power supply line, and a sheet resistance of the power supply compensation film is smaller than a sheet resistance of the power supply line layer.

US Pat. No. 10,340,328

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a first layer having a first surface and a second surface, the second surface being an opposite side surface of the first surface of the first layer, the first layer arranged with a plurality of pixels on the first surface of the first layer, the plurality of pixels having a display element including a transistor and a first wiring connected to the transistor;
a second layer having a third surface, the third surface facing the second surface;
a first contact hole reaching the first surface from the second surface;
a first electrode arranged in the first contact hole;
a second contact hole arranged in the second layer;
a second electrode arranged in the second contact hole;
a third contact hole arranged in the second layer; and
a third electrode arranged in the third contact hole, wherein
the transistor is located without overlapping the first wiring in a plan view,
at least a part of the first wiring is located directly on the first contact hole,
the first wiring and the first electrode are connected,
the first electrode reaches the first surface from the second surface,
the first electrode and the second electrode are electrically connected, and
the second electrode and the third electrode are electrically connected.

US Pat. No. 10,340,327

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a base material containing resin and including a display region and a bent region, the display region including a plurality of pixels;
a resin layer disposed on one side of the base material, wherein
an exposed section where a surface of the resin layer on a side opposite to a side on which the base material is disposed is exposed is formed in at least the bent region, and
the resin layer includes, in the exposed section, a first resin layer and a second resin layer whose hydrophilicity is lower than that of the first resin layer, in this order from the base material side; and
a component provided on the side of the base material on which the resin layer is disposed, wherein the component is covered by the second resin layer.

US Pat. No. 10,340,326

FLEXIBLE DISPLAY APPARATUS HAVING A BENDING AREA CUTOUT

Shanghai Tianma Micro-Ele...

1. A flexible display apparatus, comprising:a flexible substrate including a bending area;
an insulating layer formed on the flexible substrate and including at least one cutout at the bending area; and
a plurality of wires configured following a surface shape of the insulating layer at the bending area,
wherein the at least one cutout includes sloped sidewalls protruding away from the flexible substrate.

US Pat. No. 10,340,325

FLEXIBLE DISPLAY HAVING A HIGH STRAIN RATE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate; and
a plurality f first display layers formed on an upper surface of the substrate,
wherein the substrate includes a plurality of upper grooves, each of which defines a first opening formed only in the upper surface and a plurality of lower grooves, each of which defines a second opening formed only in a lower surface of the substrate,
wherein the upper grooves and the lower grooves are alternately arranged,
wherein the upper grooves are positioned between the plurality first display layers,
wherein the thickness of the substrate is greater than the depth of each of the upper grooves, and
wherein the first display layer includes an organic emission layer.

US Pat. No. 10,340,324

ORGANIC LIGHT-EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting diode (OLED) display, comprising:a substrate;
a scan line formed over the substrate and configured to provide a scan signal;
a data line crossing the scan line and configured to provide a data voltage;
a driving voltage line crossing the scan line and configured to provide a driving voltage;
a switching transistor electrically connected to the scan line and the data line;
a driving transistor electrically connected to the switching transistor and including a driving gate electrode and a driving channel overlapping each other in a depth dimension of the OLED display;
a first storage capacitor overlapping the driving channel in the depth dimension and including a first lower storage electrode and a portion of the driving voltage line;
a second storage capacitor separated from the first storage capacitor, overlapping the portion of the driving voltage line in the depth dimension, and including a second lower storage electrode and a second upper storage electrode overlapping the second lower storage electrode in the depth dimension, wherein the second upper storage electrode is formed on the same layer as the first lower storage electrode; and
an OLED electrically connected to the driving transistor.

US Pat. No. 10,340,323

DOUBLE-SIDED OLED DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A double-sided organic light-emitting diode (OLEM) display device, comprising a plurality of pixels arranged in an array, a thin-film transistor (TFT) backplate, a pixel definition layer arranged on the TFT backplate, and a polarizer attached to an undersurface of the TFT backplate, and the pixel definition layer comprises a first pixel definition hole and a second pixel definition hole, the top-emission (OLED being received in the first pixel definition hole and arranged on the TFT backplate, the bottom-emission OLED being received in the second pixel definition hole and arranged on the TFT backplate; and a portion of the TFT backplate that corresponds to the second OLED emissive layer is transparent and light transmitting, each of the pixels comprising a plurality of sub-pixels that are arranged in sequence, each of the sub-pixels comprising an OLED:wherein the pixels located in one row of the array or the pixels located in one, column of the array collectively form a displaying section, and for two adjacent ones of the displaying sections, the OLEDs of the pixels of one of the displaying sections are top-emission OLEDs, and the OLEDs of the pixels of the other one of the displaying sections are bottom-emission OLEDs;
wherein the top-emission OLED comprises a first anode, a first OLED emissive layer arranged on the first anode, and a transparent cathode set on and covering the first OLED emissive layer; and
the bottom-emission OLED comprises a second anode, a second OLED emissive layer arranged on the second anode, and a non-transparent cathode set on and covering the second OLED emissive layer.

US Pat. No. 10,340,322

DISPLAY DEVICE AND ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A display device, comprising:a substrate;
a first buffer layer formed on the substrate;
an insulating layer formed on the first buffer layer;
a first metal layer formed on a surface of the insulating layer, wherein the first metal layer is a first electrode of a storage capacitor of the display device;
at least one inorganic film layer formed on a surface of the first metal layer;
a conducting layer formed on a surface of the inorganic film layer;
a second metal layer formed on a surface of the conducting layer, wherein the second metal layer is a second electrode of the storage capacitor; and
an organic light emitting diode (OLED) layer;
wherein the storage capacitor comprises an opening formed in a pixel defining layer and a flattening layer corresponding to the first metal layer, the conducting layer and the second metal layer are formed in the opening and on the inorganic film layer, the first metal layer is a part of a source and drain electrode metal layer of a switching area of a thin film transistor, the inorganic film layer is a passivation layer, the conducting layer is an electron transporting layer of the OLED layer, and the second metal layer is a cathode layer of the OLED layer.

US Pat. No. 10,340,321

ELECTRO-OPTICAL DEVICE, ELECTRONIC APPARATUS, AND METHOD OF DRIVING ELECTRO-OPTICAL DEVICE

SEIKO EPSON CORPORATION, ...

1. An electro-optical device comprising:a first conductive layer;
a second conductive layer;
a third conductive layer;
a first capacitor that includes a fourth conductive layer which is coupled to the second conductive layer, a fifth conductive layer which is coupled to the third conductive layer, and a dielectric film between the fourth conductive layer and the fifth conductive layer;
a sixth conductive layer;
a second capacitor that is formed between the second conductive layer and the sixth conductive layer; and
a pixel circuit that is provided in correspondence with the third conductive layer and the first conductive layer,
wherein the pixel circuit includes a plurality of transistors including a drive transistor, and a light emitting element,
wherein the second conductive layer and the sixth conductive layer are formed in a same layer,
wherein the fourth conductive layer of the first capacitor is formed in a different layer from the second conductive layer, and
wherein the fifth conductive layer of the first capacitor is formed in a different layer from the fourth conductive layer,
wherein the first capacitor and the second capacitor are located in a display region.

US Pat. No. 10,340,320

SUBSTRATE FOR DISPLAY DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. A display device comprising:a substrate;
a pixel on the substrate, the pixel including:
a first thin-film transistor (TFT) on the substrate, the first TFT including:
a first gate electrode,
at least a first part of a first interlayer insulation film on the first gate electrode,
a second interlayer insulation film on the first interlayer insulation film,
a first gate insulation film on the first part of the second interlayer insulation film, and
a first active layer formed of oxide semiconductor on the first gate insulation film;
a second TFT on the substrate, the second TFT including:
a second active layer formed of polycrystalline silicon,
at least a first part of a second gate insulation film on the second active layer, and
a second gate electrode on the first part of the second gate insulation film,
wherein the first interlayer insulation film, the second interlayer insulation film, and the second gate insulation film are between the first active layer and the second active layer;
a storage capacitor on the substrate, the storage capacitor including:
a first storage electrode,
at least a second part of the second interlayer insulation film on the first storage electrode, and
a second storage electrode on the second part of the second interlayer insulation film, wherein the second storage electrode is physically separated from the first gate insulation film; and
a light-emitting device electrically connected to the storage capacitor.

US Pat. No. 10,340,319

ORGANIC LIGHT-EMITTING DEVICE HAVING A COLOR FILTER

Semiconductor Energy Labo...

1. An active matrix organic light-emitting device, comprising:a substrate;
a black matrix formed above a part of the substrate;
at least one transistor formed above the substrate;
a barrier film formed above and entirely covering a gate electrode and a semiconductor layer of the at least one transistor;
a planarization film formed above the barrier film;
a color filter formed on an upper part of the planarization film opposite to a position where the at least one transistor is formed; and
an organic light-emitting element formed above the color filter.

US Pat. No. 10,340,318

DISPLAY DEVICE HAVING BANK WITH GROOVE PORTION AND PIXEL DEFINITION PORTION

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a flexible substrate;
a thin film transistor disposed on the flexible substrate;
a first electrode connected to the thin film transistor;
a bank layer including a pixel definition portion exposing the first electrode and a groove portion spaced apart from the pixel definition portion;
an organic layer disposed on the first electrode and the bank layer; and
a second electrode disposed on the organic layer.

US Pat. No. 10,340,317

ORGANIC LIGHT EMITTING DISPLAY HAVING TOUCH SENSOR AND METHOD OF FABRICATING THE SAME

LG Display Co., Ltd., Se...

1. An organic light emitting display comprising:light emitting elements disposed on an active area of a substrate;
an encapsulation unit disposed on the light emitting elements;
a touch sensor disposed on the encapsulation unit, the touch sensor including a touch sensing line and a touch driving line, wherein the touch driving line comprises first touch electrodes, and the touch sensing line comprises second touch electrodes;
routing lines connected to the touch sensor;
a touch pad disposed on a pad area of the substrate and connected to the touch sensor, the touch pad comprising:
a pad electrode on a same layer as a source electrode and a drain electrode of a thin film transistor on the substrate, the pad electrode connected to one of the routing lines and made of a same material as at least one of the routing lines or the source electrode and the drain electrode of the thin film transistor; and
a pad cover electrode on the pad electrode, the pad cover electrode made of a same material as at least one of the first touch electrodes or the second touch electrodes;
at least one dam disposed between the active area and the pad area, wherein the routing lines are above and overlap the at least one dam; and
a compensation film disposed between the light emitting elements and the routing lines and overlapping at least a part of the at least one dam,
wherein the compensation film has different thicknesses between a region above the at least one dam and a region between the at least one dam and the light emitting elements.

US Pat. No. 10,340,316

DISPLAY DEVICE UTILIZING PIXEL AND DUMMY PORTIONS

Samsung Display Co., Ltd....

1. A display device comprising:a first substrate;
a second substrate comprising a pixel portion configured to display an image, and a dummy portion spaced from the pixel portion, a side of the dummy portion being exposed to the outside; and
an interlayer between the first substrate and both of the pixel and dummy portions of the second substrate,
wherein the pixel portion and the dummy portion each comprise multiple layers, and at least one layer of the pixel portion and at least one layer of the dummy portion comprise a same material, the multiple layers of the dummy portion comprising a dummy sealing layer, a dummy insulating layer, and a dummy electrode layer between the dummy sealing layer and the dummy insulating layer,
wherein the second substrate further has a region on an upper surface of the second substrate defined by a spacing between the pixel portion and the dummy portion,
wherein the upper surface of the second substrate is exposed in the region of the second substrate,
wherein the interlayer is between the first substrate and the upper surface of the second substrate exposed in the region, and
wherein the upper surface of the second substrate exposed in the region is in direct contact with the interlayer.

US Pat. No. 10,340,315

ORGANIC LIGHT EMITTING DISPLAY WITH COLOR FILTER LAYERS

Samsung Display Co., Ltd....

1. An organic light emitting display device, comprising:first to fourth electrodes spaced apart from each other on a base surface;
a fifth electrode spaced apart from the first to fourth electrodes in a normal direction of the base surface;
a first light emitter between the first to fourth electrodes and the fifth electrode and overlapping the first to fourth electrodes;
a second light emitter between at least one of the first and second electrodes and the fifth electrode, overlapping at least one of the first and second electrodes and not overlapping the third electrode and the fourth electrode;
a third light emitter between at least one of the third and fourth electrodes and the fifth electrode, overlapping at least one of the third and fourth electrodes, and not overlapping the first electrode, the second electrode, and the second light emitter;
a charge generating layer between the first and second light emitters and between the first and third light emitters; and
a color filter layer including a first color filter to transmit light from the first light emitter in a first wavelength range having a peak value in a range of about 400 nm to about 500 nm, a second color filter to transmit from the second light emitter in a second wavelength range having a peak value in a range of about 500 nm to about 600 nm, and a third color filter to transmit light from the third light emitter in a third wavelength range having a peak value in a range of about 600 nm to about 700 nm.

US Pat. No. 10,340,314

ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL, ELECTRONIC DEVICE AND MANUFACTURING METHOD

Shanghai Tianma AM-OLED C...

1. An organic light-emitting diode (OLED) display panel, comprising:a substrate; and
a plurality of pixel regions formed on the substrate to emit light of different colors, wherein:
a pixel region includes a first electrode, a light-emitting function layer, and a second electrode, configured facing away from the substrate;
the second electrode is a light-emitting side electrode of the OLED display panel;
a light coupling organic layer is formed on a side of the second electrode facing away from the substrate and a refractive index of the light coupling organic layer is greater than a refractive index of the second electrode;
differences in transmittances at different wavelengths of the second electrode satisfy the following equations:
|T(450 nm)?T(530 nm)|?15%,
|T(610 nm)?T(530 nm)|?15%, and
|T(400 nm)?T(700 nm)|?50%,
where T(Xnm) is a transmittance at a wavelength of Xnm of the second electrode;
a micro-cavity structure is formed between the first electrode and the second electrode in each pixel region and the micro-cavity structures corresponding to the pixel regions of different emission colors have different effective cavity lengths, wherein the effective cavity length of the micro-cavity structure refers to an optical path length in the micro-cavity structure;
the second electrode is made of Ag or a metal alloy containing Ag; and
the metal alloy containing Ag has an Ag content greater than or equal to about 90% by weight percentage.

US Pat. No. 10,340,313

NON-COMMON CAPPING LAYER ON AN ORGANIC DEVICE

Universal Display Corpora...

1. An apparatus comprising:a plurality of OLEDs provided on a first substrate, wherein each OLED comprises:
a first electrode;
a second electrode disposed over the first electrode; and
an organic electroluminescent (EL) material disposed between the first and the second electrodes, wherein the plurality of OLEDs comprising a first portion and a second portion;
a first capping layer disposed over the plurality of OLEDs, wherein a first portion of the first capping layer is disposed over at least the first portion of the plurality of OLEDs and a second portion of the first capping layer is disposed over the second portion of the plurality of OLEDs, wherein the first capping layer and the second electrode are in contact with each other throughout the first and second portions of the first capping layer, such that the first capping layer is optically coupled to at least the first portion and the second portion of the plurality of OLEDs,
wherein substantially all of the light emitting from the first portion and the second portion of the plurality of OLEDs in a direction perpendicular to the second electrode propagates through the first capping layer,
wherein the first capping layer is the only capping layer over the first portion of the plurality of OLEDs and has a first optical thickness that is between 90-130 nm;
a second capping layer disposed over the second portion of the plurality of OLEDs and in contact with the first capping layer throughout the second portion of the first capping layer, such that the second capping layer is optically coupled to the first capping layer and the second portion of the plurality of OLEDs but not the first portion of the plurality of OLEDs,
wherein substantially all of the light emitting from the second portion of the plurality of OLEDs in a direction perpendicular to the second electrode and propagating through the first capping layer also propagates through the second capping layer,
wherein the first capping layer and the second capping layer are the only capping layers over the second portion of the plurality of OLEDs and in combination have a second optical thickness between 125-200 nm that is different from the first optical thickness; and
wherein the second portion of the plurality of OLEDs emits light of different wavelength from the first portion when a driving voltage is applied across the first and second electrodes and the first capping layer having the first optical thickness enhances the amount of light outcoupled from the first portion and the first and second capping layer having the second optical thickness enhance the amount of light outcoupled from the second portion;
wherein the plurality of OLEDs further comprises a third portion of the plurality of OLEDs that is different from the first and second portions of the plurality of OLEDs, wherein the second electrode and a third portion of the first capping layer extend over the third portion of the plurality of OLEDs, wherein the second electrode is in contact with the first capping layer throughout the third portion of the first capping layer such that the first capping layer is also optically coupled to the third portion of the plurality of OLEDs, the apparatus further comprising:
a third capping layer disposed over the third portion of the plurality of OLEDs and in contact with the first capping layer throughout the third portion of the first capping layer such that the third capping layer is optically coupled to the first capping layer and the third portion of the plurality of OLEDs, wherein substantially all of the light emitting from the third portion of the plurality of OLEDs in a direction perpendicular to the second electrode and propagating through the first capping layer also propagates through the third capping layer; wherein the first capping layer and the third capping layer are the only capping layers over the third portion of the plurality of OLEDs and in combination have a third optical thickness between 125-200 nm that is different from the first optical thickness and the second optical thickness; and
wherein the third portion of the plurality of OLEDs emits light of different wavelength from the first portion and the second portion when a driving voltage is applied across the first and second electrodes and the first and the third capping layers having the third optical thickness enhances the amount of light outcoupled from the third portion.

US Pat. No. 10,340,312

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

Hefei Reliance Memory Lim...

1. A re-writeable non-volatile memory device, comprising:a re-writeable non-volatile two-terminal memory element (ME) comprising:
a first terminal,
a second terminal,
a first layer, and
a second layer of reactive metal in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a state of the re-writable non-volatile two-terminal ME.

US Pat. No. 10,340,311

MAGNETORESISTIVE EFFECT ELEMENT WITH MAGNETIC LAYERS AND MAGNETIC MEMORY

Toshiba Memory Corporatio...

1. A magnetoresistive effect element comprising:a first magnetic layer;
a nonmagnetic layer provided on the first magnetic layer;
a second magnetic layer provided on the nonmagnetic layer;
a first insulating layer provided at least on a side surface of the second magnetic layer;
a second insulating layer covering at least a part of the first insulating layer;
a conductive layer provided between the first insulating layer and the second insulating layer; and
an electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer,
wherein a height of a lower surface of the second portion of the electrode is equal to or less than a height of an upper surface of the conductive layer,
a height of an upper surface of the first insulating layer is greater than a height of an upper surface of the second magnetic layer, and
the second insulating layer is provided between the first insulating layer and the first portion of the electrode to be in contact with the upper surface of the second magnetic layer.

US Pat. No. 10,340,309

LIGHT EMITTING DEVICE

Seoul Viosys Co., Ltd., ...

1. A method of forming a light emitting device, the method comprising:forming a first light emitting cell comprising:
disposing a first lower semiconductor layer on a base substrate;
disposing a first active layer on the first lower semiconductor layer;
disposing a first upper semiconductor layer on the first active layer;
forming a first inclined surface comprising a first surface of the first upper semiconductor layer and a first surface of the first active layer; and
removing a portion of the first upper semiconductor layer and a portion of the first active layer to expose the first lower semiconductor layer;
forming a second light emitting cell comprising:
disposing a second lower semiconductor layer on the base substrate;
disposing a second active layer on the second lower semiconductor layer;
disposing a second upper semiconductor layer on the second active layer;
forming a second inclined surface comprising a first surface of the second upper semiconductor layer and a first surface of the second active layer; and
removing a portion of the second upper semiconductor layer and a portion of the second active layer to expose the second lower semiconductor layer;
disposing a first conductive material on the second upper semiconductor layer;
disposing a first insulation layer on the first lower semiconductor layer, the second lower semiconductor layer, the second active layer, and the second upper semiconductor layer;
disposing a second conductive material on the first insulation layer configured to electrically couple the first light emitting cell and the second light emitting cell; and
disposing a second insulation layer on the second conductive material,
wherein the first inclined surface is continuous and has a slope of approximately 20° to approximately 80° from a horizontal plane of the base substrate,
wherein the second inclined surface is continuous and has a slope of approximately 20° to approximately 80° from the horizontal plane of the base substrate, and
wherein the first insulation layer and the second insulation layer comprise a light transmitting material.

US Pat. No. 10,340,308

DEVICE WITH MULTIPLE VERTICALLY SEPARATED TERMINALS AND METHODS FOR MAKING THE SAME

X Development LLC, Mount...

1. A light emitting device, comprising:a plurality of light emitting elements arranged at different locations in a common plane, each light emitting element comprising:
at least one layer of a semiconductor material;
a first electrical terminal for providing charge carriers to a first portion of the light emitting element, the first electrical terminal being located at a first location along an axis perpendicular to the common plane;
a second electrical terminal for providing charge carriers to a second portion of the light emitting element, the second electrical terminal being located at a second location along the axis perpendicular to the common plane different from the first location; and
a third electrical terminal for providing charge carriers to a third portion of the light emitting element, the third electrical terminal being located at a third location along the axis perpendicular to the common plane different from the first and second locations;
a first electrode layer comprising one or more electrodes each being in electrical contact with the first electrical terminal of one or more of the plurality of light emitting elements;
a second electrode layer comprising one or more electrodes each being in electrical contact with the second electrical terminal of one or more of the plurality of light emitting elements;
a third electrode layer comprising one or more electrodes each being in electrical contact with the third electrical terminal of one or more of the plurality of light emitting elements;
a first electrically insulating layer disposed between the plurality of light emitting elements and also disposed between the first and second electrode layers along the axis perpendicular to the common plane; and
a second electrically insulating layer disposed between the plurality of light emitting elements and also disposed between the second and third electrode layers along the axis perpendicular to the common plane.

US Pat. No. 10,340,307

LIGHT EMITTING DIODE HAVING CURRENT CONFINEMENT STRUCTURE

MIKRO MESA TECHNOLOGY CO....

1. A light-emitting diode (LED), comprising:a first type semiconductor layer comprising a first low resistance portion, at least one second low resistance portion, and a high resistance portion, wherein the high resistance portion is between the first low resistance portion and the second low resistance portion, and a resistivity of the first type semiconductor layer increases from the first low resistance portion toward the high resistance portion and decreases from the high resistance portion toward the second low resistance portion, wherein the first low resistance portion has a top surface, a bottom surface, and an outer periphery between the top surface and the bottom surface, and the outer periphery of the first low resistance portion is enclosed by the high resistance portion;
a first electrode electrically connected to the first low resistance portion and substantially no current flowing between the first electrode and the second low resistance portion, wherein the high resistance portion is configured to confine charge carriers substantially within the first low resistance portion;
a second type semiconductor layer, wherein at least a portion of the first type semiconductor layer is between the first electrode and the second type semiconductor layer; and
a second electrode electrically connected to the second type semiconductor layer.

US Pat. No. 10,340,306

SEMICONDUCTOR PACKAGE WITH CHAMFERED CORNERS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method for forming an image sensor device, comprising:forming a first plurality of openings in an optically transmissive cover;
coupling the optically transmissive cover to a wafer comprising a plurality of die;
etching a second plurality of openings through the wafer, the second plurality of openings aligning with the first plurality of openings in the optically transmissive cover; and
singulating the optically transmissive cover and the wafer into a plurality of image sensor devices, wherein each image sensor device includes one of a rounded corner or a chamfered corner edge.

US Pat. No. 10,340,305

IMAGE SENSOR AND IMAGE SENSOR PIXEL HAVING JFET SOURCE FOLLOWER

DARTMOUTH COLLEGE, Hanov...

1. An image sensor comprising a plurality of pixels, at least one pixel comprising:a floating diffusion region formed in a semiconductor substrate;
a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion;
a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate comprising the floating diffusion region; and
wherein the channel region comprises a first doped region of a first conductivity type configured to conduct current between the source and drain along a lateral direction substantially parallel to a surface of the substrate, the floating diffusion region comprises a second doped region of a second conductivity type opposite to the first conductivity type, and wherein the second doped region of the floating diffusion is disposed adjacent to and beneath the first doped region along the lateral direction between the source and drain.

US Pat. No. 10,340,304

CMOS IMAGE SENSOR

SEMICONDUCTOR MANUFACTURI...

1. A CMOS image sensor, comprising:a substrate having a first region and a second region connecting with the first region at a first end of the first region;
a transfer transistor formed on the surface of the substrate in the second region;
a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region;
a third implanting region formed in the surface of the substrate in the first region, being formed from a first implanting region;
a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and
a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region, wherein the third implanting region and the fourth implanting region have side surfaces coinciding with an edge of the transfer transistor.

US Pat. No. 10,340,303

METHOD AND APPARATUS FOR BACKSIDE ILLUMINATION SENSOR

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising;a device substrate including a dielectric layer and a metal wire in the dielectric layer;
a first opening over the metal wire, the first opening having a bottom at a depth the same as an upper surface of the metal wire; and
a first insulation layer including a first color filter material on sidewalls of the first opening.

US Pat. No. 10,340,302

COMPACT SENSOR MODULE

Analog Devices, Inc., No...

1. A sensor module for an imaging system, the sensor module comprising:a sensor substrate;
an imaging sensor die mounted on the sensor substrate, the imaging sensor die comprising a plurality of pixels on a front side of the imaging sensor die; and
a support structure disposed behind the imaging sensor die, the support structure comprising a back side that faces away from the front side of the imaging sensor die,
the support structure comprising an alignment feature on the back side of the support structure, the support structure having a planar portion that is generally parallel to the imaging sensor die, the support structure providing mechanical support to the sensor module, the alignment feature positioned at a fixed displacement from a reference pixel of the plurality of pixels, the alignment feature exposed on an outermost surface of the sensor module and aligned behind a back side of the imaging sensor die, wherein the alignment feature comprises an alignment hole extending into the support structure of the sensor module,
wherein the alignment feature is configured to mechanically connect to a corresponding alignment pin of the imaging system.

US Pat. No. 10,340,301

SUPPORT STRUCTURE FOR INTEGRATED CIRCUITRY

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a first trench structure within a substrate and surrounding a first area of the substrate within which an integrated circuit is formed, wherein:
the first trench structure defines a first segmented ring comprising a first trench segment and a second trench segment spaced apart from the first trench segment by a first portion of the substrate; and
a second trench structure within the substrate and surrounding the first area of the substrate, wherein:
the second trench structure defines a second segmented ring comprising a third trench segment, a fourth trench segment, a fifth trench segment, and a sixth trench segment extending between a top surface of the substrate and a bottom surface of the substrate, the second segmented ring being adjacent to four external sides of the semiconductor device,
the first trench structure and the second trench structure are disposed in a second area of the substrate,
the third trench segment is spaced apart from the fourth trench segment by a second portion of the substrate, the second portion of the substrate overlaps the second trench segment in a direction extending parallel to the top surface of the substrate;
the second area of the substrate is disposed between the first area of the substrate and a third area of the substrate surrounding the second area,
the fifth trench segment has a first bent right-angle shape and is located at a first corner of the second trench structure, the sixth trench segment has a second bent right-angle shape and is located at a second corner of the second trench structure adjacent to the first corner, the first bent right-angle shape extending in a first direction a first distance, the second bent right-angle shape extending in the first direction a second distance different from the first distance; and
the third trench segment overlaps with the first trench segment and the second trench segment in a direction extending from the third area of the substrate to the first area of the substrate, wherein each portion of the first segmented ring and the second segmented ring is laterally separated from each integrated circuit within the substrate in a top down view.

US Pat. No. 10,340,300

IMAGE SENSOR WITH TRENCHED FILLER GRID

Taiwan Semiconductor Manu...

1. An image sensor, comprising:a first photodiode;
a dielectric grid comprising a first dielectric structure, wherein:
the first dielectric structure comprises a bottommost surface in direct physical contact with a substrate and an uppermost surface; and
the first dielectric structure has a substantially homogeneous material composition which extends between the bottommost surface and the uppermost surface;
a reflective layer having a first portion overlying and in direct physical contact with the uppermost surface;
a first color filter material structure over the first photodiode and having a sidewall in direct physical contact with a sidewall of the reflective layer; and
a lens structure in direct physical contact with the first color filter material structure and the first portion of the reflective layer.

US Pat. No. 10,340,299

OPTICAL SENSOR PACKAGE MODULE AND MANUFACTURING METHOD THEREOF

PIXART IMAGING INC., Hsi...

1. An optical sensor package module comprising:a substrate;
a sensor chip disposed on the substrate and including an array of pixels located at a top side thereof for receiving light; and
a shielding assembly disposed on the substrate and surrounding the sensor chip for limiting influx of light onto the sensor chip, wherein the shielding assembly includes a shielding element disposed on the sensor chip by an adhesive structure, and the shielding element has a first aperture to expose at least a first subset of the pixels that is configured to receive corresponding light;
wherein the adhesive structure is an adhesive layer disposed between the sensor chip and the shielding element and having a through hole to expose the first subset of the pixels, the through hole corresponding to the first aperture.

US Pat. No. 10,340,298

SEMICONDUCTOR DEVICE HAVING NEGATIVE FIXED CHARGE, POSITIVE FIXED CHARGE AND ELECTRONIC APPARATUS CAPABLE OF REDUCING A LEAKING CURRENT OF A PN JUNCTION REGION

Sony Semiconductor Soluti...

1. A semiconductor device comprising:at least one negative fixed charge film that has a negative fixed charge, wherein the at least one negative fixed charge film extends from a P-type region to a depletion layer on a surface of a PN junction formed in a semiconductor substrate, wherein the negative fixed charge film has a boundary located in the depletion layer in the PN junction; and
a positive fixed charge film that has a positive fixed charge, wherein the positive fixed charge film extends from an N-type region to the depletion layer on the surface of the PN junction, wherein the positive fixed charge film has a boundary located in the depletion layer in the PN junction.

US Pat. No. 10,340,297

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a display panel comprising a plurality of data lines extending in a first direction, a plurality of gate lines extending in a second direction intersecting the first direction, and a plurality of thin film transistors connected to the plurality of data lines and the plurality of gate lines, each of the thin film transistors having a channel width;
a data driving circuit configured to supply a data signal to the plurality of data lines; and
a gate driving circuit configured to supply a gate signal to the plurality of gate lines,
wherein the channel width of each of the thin film transistors connected to the same data line increases as the distance between a corresponding thin film transistor and the data driving circuit increases;
each of the plurality of thin film transistors has a gate electrode, a source electrode, a drain electrode and a parasite capacitance generated between the gate electrode and the drain electrode; and
wherein the parasite capacitance between the gate electrode and the drain electrode of each of the thin film transistors connected to the same data line decreases as the distance between a corresponding thin film transistor and the data driving circuit increases.

US Pat. No. 10,340,296

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a plurality of thin film transistors arranged in an array, each of the thin film transistors includes a base substrate, the base substrate comprising:
a gate electrode,
a gate insulating layer,
an oxide active layer,
a light absorption layer for preventing the oxide active layer from irradiated by light,
a source-drain electrode,
a pixel electrode connected to the source-drain electrode, and
a passivation layer for protecting the thin film transistor,
wherein the gate electrode, the gate insulating layer, the oxide active layer, the source-drain electrode, the pixel electrode, the passivation layer and the light absorption layer are sequentially provided on the base substrate, the passivation layer is directly formed on the pixel electrode, the light absorption layer is directly formed on the passivation layer, an orthographic projection of the light absorption layer on the oxide active layer at least partly covers an active region of the oxide active layer, and the light absorption layer is made of black zirconia.

US Pat. No. 10,340,295

FLEXIBLE DISPLAY DEVICE AND BORDER UNIT THEREOF

E Ink Holdings Inc., Hsi...

1. A flexible display device, comprising:a substrate having a display area and a border area that surrounds the display area; and
a border unit located in the border area, and the border unit comprising:
a first metal layer located on the substrate;
an insulation layer covering the first metal layer and the substrate;
a second metal layer located on the insulation layer;
a protection layer covering the second metal layer and the insulation layer;
a semiconductor layer located between the insulation layer and the protection layer;
a planarization layer covering the protection layer; and
a third metal layer located on the planarization layer and having a first part, a second part, and a third part, wherein the third part is located between the first part and the second part, and is physically connected to the first part and the second part, such that a notch is defined by the first part, the second part, and the third part.

US Pat. No. 10,340,294

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND THIN FILM TRANSISTOR

INDUSTRY-UNIVERSITY COOPE...

1. A method for manufacturing a thin film transistor, the method comprising:forming a patterned metal oxide semiconductor layer and a patterned wiring layer on a substrate; and
etching the wiring layer to form a channel part using an etchant,
wherein the wiring layer includes a compensation layer,
wherein the compensation layer is formed from a material including a metal of a metal oxide component among components of a material forming the metal oxide semiconductor layer,
wherein the compensation layer adjusts for a loss of a surface composition of the metal oxide semiconductor layer and suppresses generation of residue during the etching of the wiring layer,
wherein the loss of the surface composition and the generation of the residue are caused by the etchant, and
wherein the wiring layer further includes:
a metal layer formed opposite to the metal oxide semiconductor layer with the compensation layer interposed therebetween,
an additional compensation layer formed opposite to the compensation layer with the metal layer interposed therebetween, and
a transparent conductive layer formed opposite to the metal layer with the additional compensation layer interposed therebetween.

US Pat. No. 10,340,293

TRANSISTOR DISPLAY PANEL INCLUDING A TRANSISTOR AND AN OVERLAPPING REGION OF A GATE LINE AND DATA LINE

SAMSUNG DISPLAY CO., LTD....

1. A transistor display panel comprising:a substrate;
a gate line disposed on the substrate;
a data line disposed on the substrate; and
a transistor disposed on the substrate,
wherein the transistor includes:
a first electrode;
a second electrode overlapping the first electrode;
a semiconductor layer disposed between the first electrode and the second electrode; and
a gate electrode, wherein the semiconductor layer is disposed in an overlapping region where the gate line and the data line overlap each other.

US Pat. No. 10,340,292

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

International Business Ma...

1. A semiconductor structure comprising:a substrate;
a strained silicon germanium layer disposed on the substrate, wherein the strained silicon germanium layer is free of edge strain relaxation;
a plurality of gate stacks, wherein each gate stack of the plurality of gates stacks is disposed on and in contact with a different portion of the strained silicon germanium layer;
a first plurality of oxide regions within and formed from the strained silicon germanium layer; and
a second plurality of oxide regions within and formed from the strained silicon germanium layer, wherein each different portion of the strained silicon germanium layer is situated between and contacts one oxide region in the first plurality of oxide regions and one oxide region in the second plurality of oxide regions.

US Pat. No. 10,340,291

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate including a main surface and a back surface;
a first semiconductor region of a first conductivity type formed in the semiconductor substrate;
a first active region and a second active region whose peripheries are defined by an element isolation region, in the first semiconductor region;
a first semiconductor layer formed on the main surface of the semiconductor substrate via a first insulating film, in the first active region;
a first gate electrode formed on a surface of the first semiconductor layer via a first gate insulating film;
a first sidewall spacer formed on a side wall of the first gate electrode;
first epitaxial layers formed on the first semiconductor layer at both sides of the first gate electrode;
a second semiconductor region and a third semiconductor region of a second conductivity type formed in the first semiconductor layer and the first epitaxial layers at both sides of the first gate electrode, the second conductivity type being a conductivity type opposite to the first conductivity type;
a fourth semiconductor region of the first conductivity type formed below the first insulating film, in the first active region;
a first silicide layer formed on a surface of the first semiconductor region, in the second active region;
an interlayer insulating film covering the first gate electrode; and
a first power supply wiring formed over the interlayer insulating film,
wherein, in a plan view, the second active region extends in a first direction,
wherein, in a plan view, the first power supply wiring extends in the first direction so as to overlap with the second active region,
wherein the first power supply wiring is connected to the second semiconductor region,
wherein the first gate electrode extends in a second direction perpendicular to the first direction, and lies on the element isolation region between the first active region and the second active region, and
wherein the first silicide layer is connected to the first power supply wiring.

US Pat. No. 10,340,290

STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device, comprising:a first semiconductor layer formed on an upper surface of a first buried insulating layer;
a first circuit element formed in and above said first semiconductor layer, said first circuit element comprising drain and source regions that are formed at least partially in said first semiconductor layer;
a conductive layer formed above said first circuit element, wherein said conductive layer is electrically isolated from said drain and source regions that are formed at least partially in said first semiconductor layer;
a second buried insulating layer formed on an upper surface of said conductive layer; and
a second semiconductor layer formed on an upper surface of said second buried insulating layer.

US Pat. No. 10,340,289

CASCODE RADIO FREQUENCY (RF) POWER AMPLIFIER ON SINGLE DIFFUSION

QUALCOMM Incorporated, S...

1. An amplifier, comprising:a cascode structure comprising a first transistor having first characteristics coupled to a second transistor having second characteristics different than the first characteristics, the first transistor located with the second transistor on a single diffusion, the single diffusion having no intervening insulating layer separating the first transistor from the second transistor, the single diffusion comprising at least a P-type well region, a floating P body region having a P+ island, and a no well region having a native state of a silicon-on-insulator (SOI) layer on which the amplifier is located.

US Pat. No. 10,340,288

METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED DOUBLE PATTERNING

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a first set of metal features extending in a first lateral direction in a first metal layer of a memory cell;
forming a second set of metal features extending in a second lateral direction perpendicular to the first lateral direction in a second metal layer of said memory cell;
forming a third set of metal features extending in the second lateral direction in a second metal layer of a functional cell for providing routing compatibility between said memory cell and said functional cell; and
placing said memory cell adjacent to said functional cell for forming an integrated circuit device.

US Pat. No. 10,340,287

APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus comprising:a first deck including alternating levels of first conductor materials and levels of first dielectric materials;
first memory cells located in the first deck, each of the first memory cells located in a respective level of the levels of first conductor materials;
a second deck including alternating levels of second conductor materials and levels of second dielectric materials;
second memory cells located in the second deck, each of the second memory cells located in a respective level of the levels of second conductor materials;
a level of third conductor material located between the first and second decks;
a level of fourth conductor material located between the first and second decks; and
a level of a dielectric material located between the level of third conductor material and the level of fourth conductor material.

US Pat. No. 10,340,286

METHODS OF FORMING NAND MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a NAND memory array, comprising:forming a vertical stack of alternating first and second levels; the first levels comprising first material, and the second levels comprising second material;
recessing the first levels relative to the second levels; the second levels having projecting terminal ends extending beyond the recessed first levels; cavities extending into the first levels between the projecting terminal ends;
forming charge-storage material around the terminal ends of the second levels; the charge-storage material extending into the cavities to line the cavities;
forming charge-tunneling material extending vertically along the charge-storage material; the charge-tunneling material filling the lined cavities;
forming channel material extending vertically along the charge-tunneling material;
removing the first material to leave first voids;
etching into the charge-storage material with etchant provided in the first voids;
forming insulative third material within the first voids after etching into the charge-storage material;
removing the second material to form second voids; and
forming conductive levels within the second voids; the conductive levels being wordline levels of the NAND memory array and having terminal ends corresponding to control gate regions; the control gate regions being adjacent the charge-storage material.

US Pat. No. 10,340,285

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device comprising:a plurality of memory cells stacked in a first direction and electrically connected in series;
at least one of the memory cells including:
a first electrode;
a first semiconductor layer extending in the first direction through the first electrode;
a memory film provided between the first electrode and the first semiconductor layer; and
a first insulating core layer provided inside the first semiconductor layer; and
a select transistor provided above the memory cells in the first direction and electrically connected to the memory cells in series, the select transistor including:
a second electrode;
a second semiconductor layer extending in the first direction through the second electrode, the second semiconductor layer being coupled to the first semiconductor layer of the at least one of the memory cells;
a gate insulating film provided between the second electrode and the second semiconductor layer; and
a second insulating core layer provided inside the second semiconductor layer;
a thickness of the second semiconductor layer in a second direction orthogonal to the first direction being thinner than a thickness of the first semiconductor layer in the second direction.

US Pat. No. 10,340,284

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Samsung Electronics Co., ...

8. A semiconductor device comprising:a stack structure including a plurality of conductive layer patterns and a plurality of interlayer insulating layer patterns that are alternately and vertically stacked on one another;
an air gap disposed vertically in the stack structure;
a passivation layer covering an upper surface of the air gap;
a channel layer surrounding a side surface of the air gap;
a dielectric layer surrounding a side surface of the channel layer and in contact with the stack structure; and
a pad disposed on the passivation layer and in contact with an uppermost interlayer insulating layer pattern of the plurality of interlayer insulating layer patterns.

US Pat. No. 10,340,283

PROCESS FOR FABRICATING 3D MEMORY

MACRONIX International Co...

1. A process for fabricating a 3D memory, comprising:forming a plurality of linear stacks, each of which comprises a plurality of gate lines and a plurality of insulating layers that are stacked alternately;
forming a charge trapping layer covering tops and sidewalls of the linear stacks;
forming an amorphous semiconductor layer on the charge trapping layer;
forming a cap layer on the amorphous semiconductor layer; and
annealing the amorphous semiconductor layer to form a crystalline channel layer while the charge trapping layer covers the tops and the sidewalls of the linear stacks, wherein agglomeration of a material of the amorphous semiconductor layer is suppressed by the cap layer.

US Pat. No. 10,340,282

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

United Microelectronics C...

1. A semiconductor memory device, comprising:a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction;
a plurality of shallow trench isolation (STI) structures, disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions;
a selection gate line, extending along a second direction and crossing over the cell regions and the STI structures; and
a control gate line, adjacent to the selection gate line in parallel extending along the second direction, also crossing over the cell regions and the STI structures, wherein the selection gate line and the control gate line together form a two-transistor (2T) memory cell.

US Pat. No. 10,340,281

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) semiconductor device, comprising:a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater;
a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers above the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein two of the respective contact regions are positioned higher than one of the respective contact regions disposed between said two of the respective contact regions, and an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer, wherein the uppermost active layer of each of the sub-stacks in the respective contact regions is continuously extended from one of the active layers in the array area respectively; and
multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer of the uppermost active layer in each of the sub-stacks.

US Pat. No. 10,340,280

METHOD AND SYSTEM FOR OBJECT RECONSTRUCTION

APPLE INC., Cupertino, C...

1. A system for object reconstruction, comprising:an illuminating unit, configured to generate a pattern of spots;
a diffractive optical element (DOE) in an optical path of illuminating light propagating from the illuminating unit toward an object, thereby projecting the pattern of spots onto an object;
an imaging unit configured to detect a light response of an illuminated region and generating image data indicative of the object within the projected pattern; and
a processor, configured to reconstruct a three-dimensional (3D) map of the object by processing the image data.

US Pat. No. 10,340,279

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Sony Semiconductor Soluti...

1. A method of manufacturing a semiconductor device comprising:selecting a first through electrode from a plurality of through electrodes, the through electrodes penetrating a plurality of conductive layers and a plurality of insulating layers that are alternately stacked, wherein
antifuses are each provided between corresponding ones of the through electrodes and corresponding ones of the conductive layers;
applying a first voltage and a second voltage, the first voltage being applied to one or more of the through electrodes excluding the first electrode, and the second voltage being applied to the first through electrode; and
causing the first through electrode to be electrically floated after the second voltage is applied to the first through electrode.

US Pat. No. 10,340,278

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor memory device, comprising:a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
a patterned conductive structure disposed on the semiconductor substrate, wherein the patterned conductive structure is disposed on the memory cell region and the peripheral region, and the patterned conductive structure comprises:
a first silicon conductive layer;
a second silicon conductive layer disposed on the first silicon conductive layer;
an interface layer disposed between the first silicon conductive layer and the second silicon conductive layer, wherein the interface layer comprises oxygen;
a barrier layer disposed on the second silicon conductive layer; and
a metal conductive layer disposed on the barrier layer, wherein the patterned conductive structure disposed on the memory cell region comprises a bit line structure; and
a bit line contact structure disposed on the memory cell region, wherein the bit line contact structure is disposed between the barrier layer and the semiconductor substrate.

US Pat. No. 10,340,277

SEMICONDUCTOR DEVICES INCLUDING SUPPORT PATTERNS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate including a cell region and a dummy region; and
a support pattern in contact with at least a part of each of the plurality of pillar structures, the support pattern connecting the plurality of pillar structures with one another,
wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including a plurality of first support holes and at least one second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other, and
wherein the plurality of the first support holes are on a central portion of the cell region, and the at least one second support hole is only at an edge portion of the cell region among the central and edge portions of the cell region.

US Pat. No. 10,340,276

METHOD OF MAINTAINING THE STATE OF SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising:
said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a transistor comprising a source region, a floating body region, a drain region, and a gate;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein application of back bias to said first and second collectors results in at least two stable floating base region charge levels;
wherein said transistor is usable to access said memory cell;
a first control circuit configured to apply said back bias to said first and second collectors; and
a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

US Pat. No. 10,340,275

STACKABLE THIN FILM MEMORY

Intel Corporation, Santa...

1. A memory, comprising:a thin film transistor over a first metal layer over a substrate, the thin film transistor comprising:
a thin film transistor layer having an upper surface and a lower surface;
a gate dielectric layer on the lower surface of the thin film transistor layer;
a gate electrode on the gate dielectric layer;
a source region on the upper surface of the thin film transistor layer; and
a drain region on the upper surface of the transistor layer; and
a memory element coupled to the thin film transistor.

US Pat. No. 10,340,274

LDMOS FINFET DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a semiconductor substrate;
first and second fins on the semiconductor substrate and separated by a trench, the first fin comprising a first portion including a first conductivity type and a second portion including a second conductivity type different from the first conductivity type, the first and second portions adjacent to each other, the second portion connected to the second fin through the semiconductor substrate;
a gate structure on the first and second portions, the gate structure comprising:
a gate insulator layer on the first and second portions;
a gate on a portion of the gate insulator layer on the first portion; and
a dummy gate on the second portion and comprising an insulating layer or an undoped semiconductor layer, the dummy gate being adjacent to the gate.

US Pat. No. 10,340,273

DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES

Intel Corporation, Santa...

1. A structure comprising:a first fin comprising silicon and including a first region over a second region;
a gate stack adjacent to a sidewall surface of the first region, wherein the gate stack includes a gate dielectric and a gate electrode;
a first source and a first drain coupled to the first region;
a first dielectric layer adjacent to a sidewall surface of the second region, wherein the first dielectric layer comprises an impurity that is also present within the second region and associated with a conductivity type;
a second fin comprising silicon and including a third region over a fourth region;
a second gate stack is adjacent to a sidewall surface of the third region;
a second source and a second drain coupled to the third region;
a second dielectric layer adjacent to a sidewall surface of the fourth region; and
an isolation material between the first gate stack and a substrate surface that intersects the sidewall surface of the second region, wherein the isolation material is further between the first dielectric layer and the second dielectric layer, and wherein the isolation material comprises a plurality of dielectric layers including a layer comprising silicon and nitrogen that is adjacent to the first dielectric layer and is adjacent to the second dielectric layer.

US Pat. No. 10,340,272

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor device, comprising:providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region adjacent to the first region;
forming a barrier layer on the semiconductor substrate, wherein the barrier layer is formed in the first region and the second region;
performing a first etching process for thinning the barrier layer in the first region, wherein after the first etching process, the barrier layer comprises:
a first part at least partially disposed in the first region and having a first thickness; and
a second part disposed in the second region and having a second thickness, wherein the first thickness is less than the second thickness;
forming a first work function layer on the barrier layer in the first region and the second region after the first etching process; and
performing a second etching process to remove the first work function layer in the first region.

US Pat. No. 10,340,271

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:providing a semiconductor substrate having a first region, a second region, and an isolation region between the first region and the second region;
forming a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region;
forming an isolation structure, covering portions of side surfaces of the first fins and the second fins and with a top surface below the top surfaces of the first fins and the second fins, over the semiconductor substrate; and
forming an isolation layer over the isolation structure in the isolation region and with a top surface coplanar or above the top surfaces of the first fins and the second fins, wherein forming the isolation layer comprises:
forming a sacrificial layer over the isolation structure, the first fins and the second fins and exposing a portion of the isolation structure in the isolation region;
forming an initial isolation layer on exposed portion of the isolation structure and on the sacrificial layer;
removing a portion of the initial isolation layer on the sacrificial layer; and
removing the sacrificial layer.

US Pat. No. 10,340,270

INTEGRATED CIRCUIT HAVING FINFETS WITH DIFFERENT FIN PROFILES

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming a first top fin, a second top fin, and a third top fin extending from a substrate;
forming a first mask over the first top fin;
forming a second mask over the second top fin and the third top fin;
removing a portion of the substrate to form a first base fin and a second base fin, the first top fin extending from the first base fin, the second top fin and the third top fin extending from the second base fin; and
after removing the portion of the substrate to form the first base fin and the second base fin, reducing a width of the first base fin.

US Pat. No. 10,340,269

CONTACT RESISTANCE REDUCTION TECHNIQUE

Taiwan Semiconductor Manu...

1. A device comprising:a fin extending from a substrate;
a gate structure on a top surface and sidewalls of the fin;
a strained material stack on the fin adjacent the gate structure, the strained material stack comprising:
a first boron-doped (B-doped) silicon-germanium (SiGeB) layer on the fin;
a second SiGeB layer on the first SiGeB layer, the second SiGeB layer having a higher concentration of Ge than the first SiGeB layer;
a B-doped germanium-tin (GeSnB) layer on the second SiGeB layer; and
a third SiGeB layer on the GeSnB layer;
a metal-silicide layer on the third SiGeB layer; and
a metal contact on the metal-silicide layer.

US Pat. No. 10,340,268

FINFET STRUCTURE AND FABRICATING METHOD OF GATE STRUCTURE

UNITED MICROELECTRONICS C...

1. A FinFET structure, comprisinga fin structure;
a first gate structure disposed on the fin structure, wherein the first gate structure comprises:
a first gate electrode;
a first silicon oxide layer contacting the fin structure and disposed directly under the first gate electrode, wherein the first silicon oxide layer is an integral monolithic structure;
a silicon nitride layer contacting the silicon oxide layer;
a first gate dielectric layer disposed between the first gate electrode and the silicon nitride layer; and
a dielectric layer disposed at two sides of the first gate electrode;
a second gate structure disposed on the fin structure, wherein the second gate structure comprises:
a second gate electrode;
a second silicon oxide layer; and
a second gate dielectric layer between the second gate electrode and the second silicon oxide layer, wherein the second gate dielectric layer does not cover the silicon nitride layer and the first silicon oxide layer;
first source/drain doped regions disposed in the fin structure at two sides of the first gate electrode; and
second source/drain doped regions disposed in the fin structure at two sides of the second gate electrode, wherein the first silicon oxide layer extends to contact the first source/drain doped regions and the second source/drain doped regions, and a portion of the first silicon oxide layer contacts the first source/drain doped regions, the dielectric layer contacts the portion of the first silicon oxide layer.

US Pat. No. 10,340,267

SEMICONDUCTOR DEVICES INCLUDING CONTROL LOGIC LEVELS, AND RELATED MEMORY DEVICES, CONTROL LOGIC ASSEMBLIES, ELECTRONIC SYSTEMS, AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a stack structure comprising decks each comprising:
a memory element level comprising memory elements; and
a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting transistors laterally displaced from one another.

US Pat. No. 10,340,266

ESD PROTECTION CIRCUIT AND METHOD OF MAKING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate including a device region with an electrostatic discharge (ESD) protection circuit;
a gate over the device region;
a source region in the device region having a n-type (N+) implant and a p-type (P+) implant laterally separated on a first side of the gate;
a drain region in the device region on a second side of the gate, opposite the first;
another N+ implant, wherein an edge of each N+ implant is aligned with an opposite edge of the source region and the P+ implant is laterally separated therebetween; and
a low-voltage p-well (LVPW) formed in the device region prior to a formation of each of the N+ and P+ implants and wherein the N+ and P+ implants and a portion of the another N+ implant are in the LVPW.

US Pat. No. 10,340,265

COMPACT PROTECTION DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGE

STMicroelectronics SA, M...

1. An integrated circuit, comprising:a power supply terminal configured to receive a power supply voltage,
a reference terminal configured to receive a reference voltage,
a first signal terminal configured to receive or transmit a signal,
a first protection device coupled between said first signal terminal and the power supply terminal, the first protection device including a first MOS transistor having a first electrode coupled to said first signal terminal and a second electrode coupled to the power supply terminal,
a second protection device coupled between said first signal terminal and the reference terminal, the second protection device comprising a second MOS transistor having a first electrode coupled to said first signal terminal and a second electrode coupled to the reference terminal,
wherein gates of the first and second MOS transistors are directly connected to the reference terminal, and substrates of the first and second MOS transistors are directly connected to a first terminal of a common resistor and the reference terminal is directly connected to a second terminal of the common resistor.

US Pat. No. 10,340,264

SEMICONDUCTOR DEVICE COMPRISING A CLAMPING STRUCTURE

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor body comprising a clamping structure including a first pn junction diode and a second pn junction diode serially connected back to back between a first contact and a second contact; and
a power transistor including first and second load terminals and a control terminal,
wherein the clamping structure is electrically connected between the control terminal and the second load terminal,
wherein the second load terminal is a drain contact of an insulated gate field effect transistor, a collector contact of an insulated gate bipolar transistor, or a collector contact of a bipolar junction transistor,
wherein the control terminal is a corresponding contact of a gate of the insulated gate field effect transistor, a gate of the insulated gate bipolar transistor, or a base of the bipolar junction transistor,
wherein a breakdown voltage of the first pn junction diode is greater than 100 V,
wherein a breakdown voltage of the second pn junction diode is greater than 10 V.

US Pat. No. 10,340,263

INTEGRATED CIRCUIT FOR REDUCING OHMIC DROP IN POWER RAILS

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit comprising:a plurality of power rail pairs, wherein each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage; and
a circuit chain including a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit, wherein the plurality of unit circuits are connected distributively to the plurality of power rail pairs,
wherein the plurality of high power rails and the plurality of low power rails extend in a row direction and are arranged alternatively one by one in a column direction to form boundaries of a plurality of circuit rows that are arranged in the column direction.

US Pat. No. 10,340,262

OPTOELECTRONIC SEMICONDUCTOR DEVICE HAVING ELECTRODE JUNCTION WITH LOW REFLECTIVITY

ULTRA DISPLAY TECHNOLOGY ...

1. An optoelectronic semiconductor device, comprising:a matrix substrate including a matrix circuit and a substrate, wherein the matrix circuit is disposed on the substrate; and
a plurality of microsized optoelectronic semiconductor elements disposed separately and disposed on the matrix circuit;
wherein each of the microsized optoelectronic semiconductor elements includes a first electrode and a second electrode, the matrix circuit includes a plurality of third electrodes and a plurality of fourth electrodes, the first electrodes are coupled with and electrically connected with the third electrodes respectively, or the second electrodes are coupled with and electrically connected with the fourth electrodes respectively, and reflectivities of at least some of junctions between the first electrode and the third electrode or reflectivities of at least some of junctions between the second electrode and the fourth electrode are less than 20%.

US Pat. No. 10,340,261

SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Micron Technology, Inc., ...

1. An apparatus comprising:a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays; and
a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits,
wherein the first and second semiconductor chips are stacked with each other so that each of the plurality of first bonding electrodes is electrically connected to an associated one of the plurality of second bonding electrodes,
wherein each of the memory cell arrays includes a plurality of first signal lines extending in a first direction, a plurality of second signal lines extending in a second direction different from the first direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of first and plurality of second signal lines,
wherein the plurality of memory cell arrays include first and second memory cell arrays adjacent in the second direction to each other,
wherein the plurality of first bonding electrodes include:
a first group located at one end of the first memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the first memory cell array;
a second group located at another end of the first memory cell array in the first direction and electrically connected to remaining ones of the plurality of first signal lines in the first memory cell array; and
a third group located at one end of the second memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the second memory cell array, a position of the third group in the first direction being located between positions of the first and second groups in the first direction.

US Pat. No. 10,340,260

MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR

Intel Corporation, Santa...

1. An electronic assembly including:a first IC including contact pads and a voltage regulator circuit; and
an inductor module including:
a module substrate including a magnetic dielectric material;
a first surface at the top of the inductor module and a second surface at the bottom of the inductor module;
a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil oriented to extend in the direction from the first surface to the second surface and including a first end and a second end and a core, wherein the coil core includes the magnetic dielectric material; and
a plurality of conductive contact pads electrically coupled to the first and second coil ends, wherein contact pads electrically coupled to the first coil ends are arranged on the first surface, and the contact pads electrically coupled to the second coil ends are arranged on the second surface;
wherein the first IC is arranged on a surface of the inductor module and wherein at least a portion of the contact pads of the inductor module are electrically coupled to the contact pads of the voltage regulator circuit.

US Pat. No. 10,340,259

METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE

MediaTek Inc., Hsin-Chu ...

1. A method for fabricating a semiconductor package, comprising:providing a carrier;
adhering semiconductor dice to a top surface of the carrier by an adhesive that is in direct physical contact with the top surface of the carrier, wherein each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface, and wherein a plurality of input/output (I/O) pads are distributed on the active surface of each of the semiconductor dice;
printing interconnect features, the printing comprising:
printing a first conductive pad on the carrier;
printing a second conductive pad on the active surface of at least one of the semiconductor dice; and
printing a conductive wire connecting the first and second conductive pads, wherein the interconnect features comprise the first conductive pad, the second conductive pad and the conductive wire;
encapsulating the top surface of the carrier, the semiconductor dice and the interconnect features with an encapsulant; and
removing the carrier.

US Pat. No. 10,340,258

INTERCONNECT STRUCTURES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. An interconnect structure, comprising:a polymer material; and
a conductive line comprising:
a post passivation interconnect (PPI) pad disposed above an uppermost surface of the polymer material; and
a PPI line disposed below the uppermost surface of the polymer material, wherein:
the PPI line is coupled to the PPI pad through a transition structure;
the transition structure is interposed between and different than the PPI line and the PPI pad;
the transition structure extends over the polymer material;
the transition structure has an uppermost surface disposed above an uppermost surface of the PPI line;
in a top-down view, the transition structure has a shape that tapers from a first width of the uppermost surface of the transition structure to a second width of the lowermost surface of the transition structure; and
the first width is greater than the second width.

US Pat. No. 10,340,257

DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF

LG ELECTRONICS INC., Seo...

1. A display device, comprising:a plurality of semiconductor light emitting device packages;
a wiring substrate coupled to the plurality of semiconductor light emitting device packages; and
a plurality of wiring electrodes disposed on the wiring substrate,
wherein each of the plurality of semiconductor light emitting device packages comprises:
a plurality of semiconductor light emitting devices;
a support substrate coupled to the plurality of semiconductor light emitting devices; and
a conversion layer disposed to cover the plurality of semiconductor light emitting devices and configured to convert a color of light emitted from at least some of the plurality of semiconductor light emitting devices to a different color such that a red sub-pixel, a green sub-pixel, and a blue sub-pixel are formed, and
wherein:
at least a first semiconductor light emitting device that corresponds to the red sub-pixel or a second semiconductor light emitting device that corresponds to the green sub-pixel, among the plurality of semiconductor light emitting devices, has a light emitting area that has a different size compared to a size of a light emitting area of a third semiconductor light emitting device that corresponds to the blue sub-pixel among the plurality of semiconductor light emitting devices;
the support substrate is formed of a silicon material, and a plurality of through silicon vias are formed on the support substrate;
at least one through silicon via of the plurality of through silicon vias is electrically connected to first conductive electrodes of the plurality of semiconductor light emitting devices; and
other through silicon vias of the plurality of through silicon vias, except for the at least one through silicon via, are electrically connected to second conductive electrodes of the plurality of semiconductor light emitting devices.

US Pat. No. 10,340,256

DISPLAY DEVICES

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate having a surface comprising a display area and a non-display area adjacent to the display area;
a plurality of light-emitting diodes disposed on the display area of the substrate, wherein the light-emitting diode comprises a contact electrode;
an anisotropic conductive layer disposed between the substrate and the plurality of light-emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the anisotropic conductive layer is in a shape of a curve;
a covering layer contacting at least a portion of one of the plurality of light-emitting diodes, wherein the covering layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the covering layer is in a shape of a curve; and
a connection structure disposed on the non-display area and/or the display area of the substrate, wherein the connection structure comprises an electrode having a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the electrode is in a shape of a curve.

US Pat. No. 10,340,255

SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor apparatus comprising:a package substrate; and
a semiconductor chip,
wherein the package substrate comprises a substrate pad coupled with a package ball,
wherein the semiconductor chip comprises:
a main pad coupled with the substrate pad;
a first buffer coupled with the main pad; and
an auxiliary pad coupled with the first buffer.

US Pat. No. 10,340,254

METHOD OF PRODUCING AN INTERPOSER-CHIP-ARRANGEMENT FOR DENSE PACKAGING OF CHIPS

ams AG, Unterpremstaette...

1. A method of producing an interposer-chip-arrangement, comprising:providing an interposer with an integrated circuit, wherein the interposer comprises a semiconductor material;
arranging a dielectric layer with metal layers embedded in the dielectric layer above a main surface of the interposer;
connecting the integrated circuit with at least one of the metal layers;
forming an interconnection through the interposer, the interconnection contacting one of the metal layers;
arranging a further dielectric layer above a further main surface of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection;
arranging a chip provided with at least one contact pad at the main surface; and
electrically conductively connecting the contact pad with the interconnection,
wherein a cavity is formed in the interposer and the dielectric layer, and
wherein the chip is mounted in the cavity by an adhesive or by bonding.

US Pat. No. 10,340,253

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a first die and a second die side by side;
a first encapsulant, encapsulating sidewalls of the first die and sidewalls of the second die;
a bridge, electrically connecting the first die and the second die through two conductive bumps;
an underfill layer, filling the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant;
a second encapsulant over the first die and the second die, encapsulating sidewalls of the underfill layer and sidewalls of the bridge;
a dielectric layer, sandwiched between the first die and the second encapsulant, and between the second die and the second encapsulant; and
a redistribution layer (RDL) structure over the bridge, electrically connected to the first die and the second die though a plurality of through integrated fan-out vias (TIVs),
wherein bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

US Pat. No. 10,340,252

HIGH VOLTAGE DEVICE WITH MULTI-ELECTRODE CONTROL

Texas Instruments Incorpo...

1. A high-voltage device, comprising:a low-voltage transistor (LVT) having a first drain node, a first control gate, and a first source node;
a high electron mobility transistor (HEMT) having a second drain node, a second source node, a second control gate, and a field electrode free of being electrically coupled to the second control gate and the second source node within the HEMT;
a first conductor external to the HEMT and the LVT, and coupling the field electrode of the HEMT to the first source node of the LVT; and
a second conductor external to the HEMT and the LVT, and coupling the second control gate of the HEMT to the first source node of the LVT.

US Pat. No. 10,340,251

METHOD FOR MAKING AN ELECTRONIC COMPONENT PACKAGE

NXP USA, Inc., Austin, T...

17. A method of making an electronic component package, the method comprising:applying a sacrificial material to a first glass carrier;
applying a second glass carrier to a top side of the sacrificial material;
curing the sacrificial material with UV radiation through the second glass carrier while the second glass carrier is applied to the top side;
after the curing, removing the second glass carrier from the sacrificial material, wherein the top side has a top surface defined by the second glass carrier, and wherein after the removing of the second glass carrier, an unfeatured area of the top surface has a roughness (Ra) of 1 nm or less;
after the removing, forming a redistribution structure over the top side of the sacrificial material, the redistribution structure including at least one redistribution layer;
attaching a plurality of electronic components to the redistribution structure;
after the attaching, encapsulating the plurality of electronic components to form an encapsulated panel that includes the redistribution structure;
removing the first glass carrier and the sacrificial material from the encapsulated panel after the encapsulating;
singulating the encapsulated panel into a plurality of electronic component packages, each electronic component package of the plurality of electronic component packages including at least one electronic component of the plurality of electronic components.

US Pat. No. 10,340,250

STACK TYPE SENSOR PACKAGE STRUCTURE

KINGPAK TECHNOLOGY INC., ...

1. A stack type sensor package structure, comprising:a substrate having an upper surface and a lower surface opposite to the upper surface, wherein the substrate includes a plurality of solder pads arranged on the upper surface;
at least one semiconductor chip mounted on the substrate;
a frame fixed on the upper surface of the substrate and surrounded by the solder pads, wherein the at least one semiconductor chip is in a space defined by the frame and the substrate and does not contact the frame, and the frame has a bearing plane above the at least one semiconductor chip;
a sensor chip having a top surface and a bottom surface opposite to the top surface, the sensor chip including a plurality of connecting pads arranged on the top surface thereof, wherein a size of the sensor chip is larger than that of the at least one semiconductor chip, and the bottom surface of the sensor chip is fixed on the bearing plane;
a plurality of wires each having a first end and a second end opposite to the first end, wherein the first ends of the wires are respectively connected to the solder pads, and the second ends of the wires are respectively connected to the connecting pads;
a transparent layer having a first surface and a second surface opposite to the first surface, wherein the second surface has a central region and a ring-shaped supported region encircling the central region;
a support having a ring-shaped structure and disposed on at least one of the top surface of the sensor chip and the bearing surface of the frame, wherein a top end of the support abuts against the supported region of the transparent layer; and
a package compound disposed on the upper surface of the substrate and covering a lateral side of the frame, at least part of a lateral side of the transparent layer, and a lateral side of the support, wherein at least part of each of the wires is embedded in the package compound,
wherein the substrate is recessed from the upper surface thereof to form an accommodating slot, and the at least one semiconductor chip is arranged in the accommodating slot,
wherein multiple semiconductor chips are included in the stack type sensor package structure, and the semiconductor chips are electrically connected to the substrate by wire bonding,
wherein the upper surface of the substrate has a wire bonding region arranged between the frame and the accommodating slot, and at least one of the semiconductor chips is electrically connected to the wire bonding region of the substrate by wire bonding.

US Pat. No. 10,340,249

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a first opening in a first photosensitive adhesive layer, the first photosensitive adhesive layer being adjacent a first side of a first integrated circuit device;
plating a first reflowable layer in the first opening;
forming a second opening in a second photosensitive adhesive layer, the second photosensitive adhesive layer being adjacent a first side of a second integrated circuit device;
plating a second reflowable layer in the second opening;
pressing the first and second photosensitive adhesive layers together, thereby physically connecting the first and second integrated circuit devices; and
reflowing the first and second reflowable layers, thereby forming a conductive connector electrically connecting the first and second integrated circuit devices.

US Pat. No. 10,340,248

BONDING SYSTEMS

TOKYO ELECTRON LIMITED, ...

1. A bonding system comprising:a substrate transfer device configured to transfer a first substrate and a second substrate in an atmospheric pressure atmosphere;
a surface modifying apparatus configured to modify surfaces of the first substrate and the second substrate in a depressurized atmosphere;
a load lock chamber configured to perform delivery of the first substrate and the second substrate between the load lock chamber and the substrate transfer device and between the load lock chamber and the surface modifying apparatus, and configured to switch an internal atmosphere of the load lock chamber between the atmospheric pressure atmosphere and the depressurized atmosphere;
a surface hydrophilizing apparatus configured to hydrophilize the modified surfaces of the first substrate and the second substrate; and
a bonding apparatus configured to bond the hydrophilized surfaces of the first substrate and the second substrate by an intermolecular force,
wherein the substrate transfer device transfers the first substrate and the second substrate to and from the load lock chamber, to and from the surface hydrophilizing apparatus, and to and from the bonding apparatus, and
wherein the load lock chamber sets the internal atmosphere to be the atmospheric pressure atmosphere when the first substrate and the second substrate are delivered between the load lock chamber and the substrate transfer device, and sets the internal atmosphere to be the depressurized atmosphere when the first substrate and the second substrate are delivered between the load lock chamber and the surface modifying apparatus.

US Pat. No. 10,340,247

METHOD FOR FORMING HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a first conductive material in a first polymer material in a first wafer;
forming a second conductive material in a second polymer material in a second wafer;
hybrid bonding the first wafer and the second wafer to form a hybrid bonding structure, wherein the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure; and
forming at least one through-substrate via (TSV) through the second wafer, wherein the TSV extends from a bottom surface of the second wafer to a metallization structure of the first wafer, wherein the metallization structure is in direct contact with the polymer-to-polymer bonding structure.

US Pat. No. 10,340,246

WIRE BALL BONDING IN SEMICONDUCTOR DEVICES

TEXAS INSTRUMENTS INCORPO...

1. A method of interconnecting components of a semiconductor device using wire bonding, the method comprising:providing a coated-aluminum wire, the coated-aluminum wire having a coating that comprises palladium;
forming a free air ball from a first end of the coated-aluminum wire, wherein during the formation of the free air ball, the coating is removed from at least a portion of the free air ball;
bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the free air ball and the aluminum surface layer of the bond pad form a substantially homogenous, aluminum-to-aluminum ball bond; and
bonding a second, opposing end of the coated-aluminum wire to a lead on a lead frame, the lead having a palladium surface layer, wherein the second end of the coated-aluminum wire and the lead form a substantially homogenous, palladium-to-palladium bond.

US Pat. No. 10,340,245

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

Samsung Electro-Mechanics...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip and filling at least a portion of space between walls of the through-hole and side surfaces of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip;
first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant; and
a component package including a wiring substrate and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, the wiring substrate being disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals,
wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads of the semiconductor chip, and
the component package is disposed on a first surface side of the second interconnection member and the active surface of the semiconductor chip is disposed on a second surface side of the second interconnection member, the second surface being opposite the first surface,
wherein an electrical pathway at least traverses the connection pad, a first redistribution pattern of the redistribution layer of the second interconnection member, a first terminal of the first connection terminals, a wiring layer of the wiring substrate, a second terminal of the first connection terminals, a second redistribution pattern of the redistribution layer of the second interconnection member, the redistribution layer of the first interconnection member, and the second connection terminal in that sequence,
wherein the second terminal of the first connection terminals is spaced apart from the first terminal of the first connection terminals, and the second redistribution pattern of the second interconnection member is spaced apart from the first redistribution pattern of the second interconnection member.

US Pat. No. 10,340,244

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device comprising:a low-density substrate;
a high-density patch positioned inside a cavity in the low-density substrate, the high-density patch comprising a base plate and a high-density redistribution structure, wherein the high-density redistribution structure comprises one or more high-density circuit traces on the base plate;
a first semiconductor die including high-density bumps and low-density bumps; and
a second semiconductor die including high-density bumps and low-density bumps,
wherein the high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the one or more high-density circuit traces of the high-density patch, and the low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

US Pat. No. 10,340,243

CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING CIRCUIT SUBSTRATE

FUJI XEROX CO., LTD., To...

1. A circuit substrate comprising:a base material; and
a capacitor layer including:
a first metal layer on the base material;
a dielectric layer on the first metal layer; and
a second metal layer on the dielectric layer,
wherein the first metal layer includes a first electrode region on the base material, which is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit through the capacitor layer is to be connected, and
wherein the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is to be connected.

US Pat. No. 10,340,242

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate including a first surface and a second surface opposite to the first surface;
a package over the substrate;
a plurality of first conductors over the substrate;
a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;
a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;
a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; and
a passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.

US Pat. No. 10,340,241

CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method, comprising:placing a powder on a semiconductor substrate;
sintering the powder to form a plurality of pillars directly in contact with the semiconductor substrate;
repeating the placing and sintering steps until the plurality of pillars reach a predetermined height;
forming a solder cap on the plurality of pillars;
removing non-sintered powder by a cleaning process;
joining the semiconductor substrate to a board using the solder cap and a thermal reflow process;
joining a chip to the semiconductor substrate by a reflow process; andunderfilling empty spaces between the chip, the semiconductor substrate and the board, wherein:the semiconductor substrate is a wafer placed in a chuck and coated with a plurality of layers of the powder, followed by the laser sintering after each coating to form the pillars directly in contact with the wafer;
joining the chip to the wafer between the pillars;
dicing the wafer to form a plurality chips with the pillars;
bonding a chip without the pillars to a substrate of another chip of a plurality of chips between the pillars;
the chip without the pillars including plating of micro-bumps; and
wherein the board is an organic laminate and the organic laminate is bonded to the another chip by the pillars by a reflow of the solder cap at a reflow temperature of about 250° C. to about 260° C.

US Pat. No. 10,340,240

MECHANISMS FOR FORMING POST-PASSIVATION INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:an integrated circuit;
an insulating layer overlying the integrated circuit;
a post-passivation interconnect layer over the insulating layer;
a connector electrically connected to the post-passivation interconnect layer, the connector including:
a bump comprising a first material, and
a diffusion barrier region enclosing the bump and comprising the first material doped with a dopant, a material composition of the diffusion barrier region being different than a material composition of the bump; and
a molding compound layer over the post-passivation interconnect layer and around a bottom portion of the connector, wherein a topmost surface of the molding compound layer is disposed at a level between a topmost point of the bump and a bottommost point of the bump, wherein the level of the topmost surface of the molding compound layer is further disposed between a first point of the diffusion barrier region and a second point of the diffusion barrier region, the first point of the diffusion barrier region is above and contacting the topmost point of the bump, the second point of the diffusion barrier region is below and contacting the bottommost point of the bump.

US Pat. No. 10,340,239

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

Cufer Asset Ltd. L.L.C, ...

1. A method comprising:depositing, in physical contact with at least a portion of multiple chips, a temperature-conductive liquidus or gel material on a rigid body;
hardening the temperature-conductive liquidus or gel material to constrain at least a portion of each of the multiple chips such that the hardened material and the multiple chips behave as part of the rigid body;
bringing a bonding surface of each of the multiple chips into contact with a bonding surface of an element, by uniformly applying a force on the rigid body to place the multiple chips under pressure without causing damage to the multiple chips or the bonding surface of the element; and
removing all of the hardened material from contact with the multiple chips.

US Pat. No. 10,340,238

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a first wiring structure including
a first insulation layer formed from a thermosetting insulative resin and including a reinforcement material,
a recess formed in a lower surface of the first insulation layer,
a first wiring layer with which the recess is filled, and
a via wiring including an upper end surface exposed from an upper surface of the first insulation layer, wherein the via wiring extends in a thickness-wise direction through the first insulation layer and is connected to the first wiring layer;
a protective insulation layer formed on the lower surface of the first insulation layer; and
a second wiring structure laminated on the upper surface of the first insulation layer, wherein the second wiring structure includes
at least one second insulation layer formed from an insulative resin of which main component is a photosensitive resin, and
two or more second wiring layers;
wherein the upper surface of the first insulation layer and the upper end surface of the via wiring are polished surfaces,
the first wiring layer includes a lower surface formed to be flush with the lower surface of the first insulation layer or recessed from the lower surface of the first insulation layer toward the second wiring structure,
the second wiring structure has a wiring density that is higher than a wiring density of the first wiring structure, and
the reinforcement material is located toward the second wiring structure from a thickness-wise center of the first insulation layer and is located at a thickness-wise center of a thickness from the lower surface of the first insulation layer to an upper surface of an uppermost one of the two or more second wiring layers.

US Pat. No. 10,340,237

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:(a) loading a substrate into a process chamber, the substrate comprising a conductive film and an insulating film formed around the conductive film to expose the conductive film; and
(b) forming a protective film selectively on an upper surface of the insulating film without forming the protective film on the conductive film by supplying into the process chamber a process gas comprising a component reactive with a desorbed gas generated from the insulating film.

US Pat. No. 10,340,236

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor substrate;
a top metal layer over the semiconductor substrate;
a first passivation layer over and in physical contact with the top metal layer;
a first redistribution layer over and in physical contact with the first passivation layer;
a first polymer layer over and in physical contact with the first redistribution layer;
an encapsulant in physical contact with the semiconductor substrate, the first passivation layer, and the first polymer layer, wherein the encapsulant contacts a first sidewall and a second sidewall of the first polymer layer, and wherein at least a portion of the first polymer layer extends above a top surface of the encapsulant; and
a first conductive via extending through the first polymer layer and in electrical connection with the first redistribution layer, the first conductive via being laterally separated from the encapsulant, wherein a top surface of the first conductive via extends above a top surface of the encapsulant.

US Pat. No. 10,340,235

SEMICONDUCTOR PACKAGE WITH THREE-DIMENSIONAL ANTENNA

MEDIATEK INC., Hsin-Chu ...

1. A semiconductor package, comprising:a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region;
a semiconductor die disposed on the package substrate in the first region;
a conductive shielding element disposed on the package substrate and covering the semiconductor die; and
a three-dimensional (3D) antenna, comprising:
a planar structure portion disposed on the package substrate in the second region; and
a bridge structure portion above the planar structure portion and connected thereto,
wherein the first bar pattern has an end in the first region to serve as a feeding point of the 3D antenna, and
wherein the conductive shielding element has an opening formed in a sidewall thereof, such that the first bar pattern passes through the conductive shielding element via the opening.

US Pat. No. 10,340,234

SUBSTRATE HAVING EMBEDDED ELECTRONIC COMPONENT

Samsung Electro-Mechanics...

1. A substrate having an electronic component, comprising:a frame having a through hole with the electronic component disposed in the through hole;
a first wiring portion formed on a surface of the frame and the electronic component, comprising a wiring layer and a first insulating layer;
a first layer formed on the first wiring portion; and
a second wiring portion formed on the first layer, comprising an antenna layer,
wherein the first layer is formed of a first material different from a second material of the second wiring portion, and
wherein the first layer comprises a via connecting a pattern layer of the first wiring portion and the antenna layer of the second wiring portion.

US Pat. No. 10,340,233

MILLIMETER WAVE CONNECTORS TO INTEGRATED CIRCUIT INTERPOSER BOARDS

Lockheed Martin Corporati...

1. An apparatus comprising:a connector to receive a millimeter wave signal, the connector including a signal pin;
a pin landing pad conductively coupled to the signal pin, the pin landing pad including a transition portion;
a transmission line coupling the pin landing pad to an input/output (I/O) pad of an integrated circuit; and
an interposer comprising a multilayer printed circuit board (PCB) comprising metallization layers and dielectric layers and including the pin landing pad, the transmission line, and the I/O pad of the integrated circuit, wherein a metallization under the pin landing pad is removed and a dielectric material of the dielectric layers comprises prepreg.

US Pat. No. 10,340,232

WIRING SUBSTRATE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a coil wiring;
a magnetic layer that is in contact with a lower surface of the coil wiring, wherein the magnetic layer includes an opening extending through in a thickness-wise direction;
a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening; and
a signal wiring structure that transmits a signal of a semiconductor element in the wiring substrate when the semiconductor element is mounted on the wiring substrate, wherein the signal wiring structure is formed so that the signal of the semiconductor element travels through the opening of the magnetic layer, wherein
the signal wiring structure includes
a first wiring portion located on an upper surface of the first insulation layer, and
a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion, wherein
the first insulation layer includes an opening extending through in the thickness-wise direction and located inward from the opening of the magnetic layer,
the first via wiring is filled in the opening of the first insulation layer,
the first insulation layer is filled in a gap between the first via wiring and the wall surface of the opening of the magnetic layer, and
the magnetic layer is not in contact with the signal wiring structure.

US Pat. No. 10,340,231

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor package structure, comprising:a semiconductor die comprising an active surface, a back surface and a sidewall surface between the active surface and the back surface, wherein the active surface of the semiconductor die has a contact pad therein;
a molding layer covering the back surface and the sidewall surface of the semiconductor die; and
an inductor in the molding layer, wherein the sidewall surface of the semiconductor die faces toward the inductor, wherein a lower surface of the molding layer is coplanar with a lower surface of the inductor, and wherein an upper surface of the contact pad is coplanar with an upper surface of the inductor.

US Pat. No. 10,340,230

SEMICONDUCTOR CHIP

United Microelectronics C...

1. A semiconductor chip, comprising:at least one interlayer dielectric layer, disposed on a substrate;
a transmission pattern, disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip, wherein the transmission pattern is electrically connected to an external signal source;
a stress absorption structure, disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern, wherein the stress absorption structure is covered by the transmission pattern.

US Pat. No. 10,340,229

SEMICONDUCTOR DEVICE WITH SUPERIOR CRACK RESISTIVITY IN THE METALLIZATION SYSTEM

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device, comprising:a metallization system including a last metallization layer, said last metallization layer comprising a first metal region and a second metal region laterally separated from and adjacent to said first metal region;
a passivation layer formed above said last metallization layer;
a first contact pad formed in said passivation layer so as to be in contact with said first metal region, wherein said first contact pad overlaps a portion of said second metal region in a height direction perpendicular to an upper surface of said first contact pad, and
a second contact pad formed in said passivation layer adjacent to said first contact pad so as to be in contact with said second metal region and overlap a portion of said first metal region in a height direction perpendicular to an upper surface of said second contact pad.

US Pat. No. 10,340,228

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE

Siliconware Precision Ind...

1. A method for fabricating a semiconductor package, comprising the steps of:providing a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface;
disposing at least a semiconductor element on the first top surface of the circuit structure, wherein the semiconductor element is electrically connected to the circuit structure;
forming an encapsulant on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface;
thinning the encapsulant from the second top surface thereof; and
forming a strengthening layer on the second top surface of the encapsulant and forming an adhesive layer between the encapsulant and the strengthening layer, wherein the strengthening layer and the adhesive layer are free from being removed, and the strengthening layer is made of a semiconductor material.

US Pat. No. 10,340,227

METHOD FOR PROCESSING A DIE

Infineon Technologies AG,...

1. A die, comprising:a die body; and
at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is configured to be planar at a die attach process temperature range or to have a positive radius of curvature at the die attach process temperature range, wherein the back side metallization structure is electrically conductive and comprises impurities configured to exert a compressive stress onto the die body that is greater than a compressive stress of the front side metallization structure at the die attach process temperature range.

US Pat. No. 10,340,226

INTERCONNECT CRACK ARRESTOR STRUCTURE AND METHODS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first contact pad on a first semiconductor substrate;
a first crack stopper on the first contact pad, the first crack stopper comprising a first wire that is wire bonded to the first contact pad on the first semiconductor substrate, the first wire having a first portion directly bonded to the first contact pad, the first portion having non-parallel sidewalls comprising a ball or wedge shape at an interface with the first contact pad, the first wire having a second portion continuous with the first portion, the second portion having parallel sidewalls extending from the first portion, the second portion being narrower than the first portion;
a protective layer surrounding sides of the first wire; and
solder surrounding the first crack stopper.

US Pat. No. 10,340,225

METHODS AND MODULES RELATED TO SHIELDED LEAD FRAME PACKAGES

Skyworks Solutions, Inc.,...

1. A method for providing electro-magnetic interference shielding for a radio-frequency module, the method comprising:applying a metal-based covering over a portion of a lead-frame package, the lead-frame package having a plurality of pins with at least one pin exposed from overmold compound and in contact with the metal-based covering, the lead-frame package including an inner row and an outer row of pins on each side, and all the pins of all the outer rows of pins assigned to ground;
mounting the lead-frame package on a substrate; and
connecting the metal-based covering to a ground plane of the substrate.

US Pat. No. 10,340,224

MICROWAVE AND MILLIMETER WAVE PACKAGE

Mitsubishi Electric Corpo...

1. A microwave and millimeter wave package comprising:a conductor base plate having a semiconductor element fixed to an upper surface thereof;
a side wall provided on the conductor base plate to surround the semiconductor element, the side wall having a conductor portion electrically connected to the conductor base plate;
a dielectric cap disposed on the side wall to form an internal space together with the conductor base plate and the side wall;
a front-side metal film provided on an entire front-side of the dielectric cap;
a first back-side metal film provided on an inner surface of the dielectric cap such that a center of the first back-side metal film approximately coincides with a center of a surface of the dielectric cap which faces the conductor base plate; and
a plurality of vias provided to pass through the dielectric cap and achieve electrical connection between the front-side metal film and the first back-side metal film and electrical connection between the front-side metal film and the conductor portion of the side wall, wherein
the first back-side metal film has, in a plan view, any one of a rectangular shape, a circular shape, an oval shape, and a polygonal shape,
the first back-side metal film comprises an opening portion in the first back-side metal film, the opening portion having a shape approximately similar to the shape of the first back-side metal film and having a small area, centers of the opening portion and the first back-side metal film approximately coinciding with each other, and
a width of the first back-side metal film of the opening portion is in a range of 1/16 to 3/16 of the wavelength for the lowest-order cavity resonant frequency.

US Pat. No. 10,340,223

METHOD OF FORMING AN INTERCONNECT STRUCTURE HAVING AN AIR GAP AND STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:embedding a conductive material into a dielectric layer to form a first conductive feature and a second conductive feature, the first conductive feature having a first width;
sealing the first conductive feature with a first etch stop layer;
removing a first portion of the first etch stop layer to form an exposed portion of the first conductive feature, the exposed portion having a second width less than the first width, wherein the removing the first portion also removes a portion of the dielectric layer to form a first opening;
re-sealing the first conductive feature with a second etch stop layer after the removing the first portion of the first etch stop layer, the second etch stop layer extending into the first opening; and
depositing a dielectric material to seal a void within the first opening.

US Pat. No. 10,340,222

STAIR CONTACT STRUCTURE, MANUFACTURING METHOD OF STAIR CONTACT STRUCTURE, AND MEMORY STRUCTURE

MACRONIX INTERNATIONAL CO...

1. A stair contact structure adjacent to a memory array, comprising:a plurality of layers of stacking structures, wherein each stacking structure comprises a conductive layer and an insulating layer, and the conductive layers and the insulating layers are interlaced; and
a first etch stop layer penetrating through the stacking structures vertically and extending along a first horizontal direction, wherein the conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages, wherein a length along the first horizontal direction of one of the conductive layers of said each stacking structure is smaller than a length along the first horizontal direction of one of the insulating layers positioned on and directly contacting said one of the conductive layers of said each stacking structure;
wherein the stair contact structure and the memory array are disposed along a second horizontal direction vertical to the first horizontal direction.

US Pat. No. 10,340,221

STACKED FINFET ANTI-FUSE

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:providing a stacked fin structure on a surface of a first insulator layer, the stacked fin structure comprising a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion;
doping the first semiconductor fin portion and the second semiconductor fin portion;
removing the insulator fin portion;
growing a first highly doped epitaxial structure about the first semiconductor fin portion and a second highly doped epitaxial structure about the second semiconductor fin portion, wherein the first highly doped epitaxial structure has lower-most apex overlying and aligned with an upper-most apex of the second highly doped epitaxial structure, the lower-most apex separated from the upper-most portion by a gap; and
forming a second insulating layer about the first highly-doped epitaxial layer and the second highly-doped epitaxial layer, wherein the second insulator layer fills the gap.

US Pat. No. 10,340,220

COMPOUND LATERAL RESISTOR STRUCTURES FOR INTEGRATED CIRCUITRY

Intel Corporation, Santa...

17. A system on a chip (SOC), comprising:processor logic circuitry;
memory circuitry coupled to the processor logic circuitry;
RF circuitry coupled to the processor logic circuitry and including radio transmission circuitry and radio receiver circuitry; and
power management circuitry including an input to receive a DC power supply and an output coupled to at least one of the processor logic circuitry, memory circuitry, and RF circuitry, wherein at least one of the processor logic circuitry, memory circuitry, RF circuitry, or power management circuitry include both:
a resistor trace over a substrate, a length of the resistor trace comprising a first resistive material in contact a sidewall of a second resistive material;
a first dielectric material over the first resistive material, but not the second resistive material; and
a pair of resistor contacts coupled to opposite ends of the resistive trace and separated by the length; and
a transistor further comprising:
a gate stack over a semiconductor body, the gate stack including a gate electrode over a gate dielectric;
a semiconductor source and drain on opposite sides of the gate stack; and
source and drain contacts on the semiconductor source and drain, and separated from the gate stack by a spacer dielectric material that is also on a sidewall of the first dielectric.

US Pat. No. 10,340,219

SEMICONDUCTOR DEVICE HAVING A METAL VIA

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate having a device isolation region defining an active region;
an active fin positioned in the active region and extended in a first direction;
a gate structure overlapping the active fin along a direction orthogonal to an upper surface of the substrate and extended in a second direction intersecting the first direction;
a source/drain region disposed on the active fin;
a contact plug connected to the source/drain region, and overlapping the active region along the direction orthogonal to the upper surface of the substrate;
a metal via positioned at a first level above the substrate, higher than an upper surface of the contact plug, and spaced apart from the active region along the direction orthogonal to the upper surface of the substrate, wherein the metal via does not overlap the contact plug along the direction orthogonal to the upper surface of the substrate;
a metal line positioned at a second level above the substrate, higher than the first level, and connected to the metal via; and
a via connection layer extended from an upper portion of the contact plug and connected to the metal via.

US Pat. No. 10,340,218

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE COMPRISING PLURALITY OF THROUGH HOLES USING METAL HARD MASK

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure comprising:forming a first portion of a dielectric layer to conceal a conductive structure;
removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure, wherein a top of the first portion of the dielectric layer is at or above the top surface of the conductive structure after removing some of the first portion of the dielectric layer;
forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;
forming a metal hard mask over the dielectric layer;
patterning the metal hard mask to form a patterned metal hard mask;
patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer; and
patterning the second portion of the dielectric layer with the patterned metal hard mask to define a second through hole extending through the second portion of the dielectric layer.

US Pat. No. 10,340,217

SEMICONDUCTOR DEVICE INCLUDING A CYLINDRICAL ELECTRODE INSERTED INTO A LOOPED PORTION OF AN ELECTRODE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor chip;
an electrode electrically connected to the semiconductor chip, the electrode including a looped portion;
a cylindrical electrode including a main portion having a screw thread formed therein and a narrow portion continuous with the main portion, the narrow portion having a smaller width than the main portion, the cylindrical electrode being electrically connected to the electrode by the narrow portion being inserted into the looped portion; and
a case for the semiconductor chip and the electrode, the case contacting the main portion and a top surface of the looped portion, while causing the screw thread and a connecting portion between the looped portion and the cylindrical electrode to be exposed.

US Pat. No. 10,340,215

CHIP ON FILM AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A chip on film comprising:a base material;
a plurality of mutually independent output pads extending in a first direction and disposed on a side of the base material;
a chip; and
a plurality of leads, in one-to-one correspondence with the output pads and extending in a second direction, wherein the leads are configured to connect corresponding output pads to the chip, the second direction is parallel to a plane where the output pads are located,
the output pads constitute at least one set of interdigitated electrode structures arranged in a direction perpendicular to the first direction,
the chip and the output pads are located on two sides of the base material, respectively, the leads comprise:
first leads disposed on the base material on a same side as the output pads, and
second leads disposed on the base material on a same side as the chip,
wherein, first ends of the first leads are connected with a part of output pads that constitute the interdigitated electrode structures, and second ends of the first leads are connected with the chip through first vias penetrating the base material,
first ends of the second leads are connected with another part of the output pads that constitute the interdigitated electrode structures through second vias penetrating the base material, and second ends of the second leads is connected with the chip.

US Pat. No. 10,340,214

CARRIER BASE MATERIAL-ADDED WIRING SUBSTRATE

SHINKO ELECTRIC INDUSTRIE...

1. A carrier base material-added wiring substrate comprising:a wiring substrate including
an insulation layer,
a wiring layer arranged on a lower surface of the insulation layer, and
a solder resist layer that covers the lower surface of the insulation layer and includes
an opening that exposes a portion of the wiring layer as an external connection terminal;
an adhesive layer including an opening that is in communication with the opening of the solder resist layer; and
a carrier base material that is adhered by the adhesive layer to the solder resist layer to form the carrier base material-added wiring substrate, wherein the carrier base material includes an opening that is in communication with the opening of the solder resist layer and the opening of the adhesive layer and exposes the external connection terminal,
wherein the opening of the carrier base material is tapered so that the diameter of the opening of the carrier base material decreases from a lower surface of the carrier base material toward an upper surface of the carrier base material, and the opening of the adhesive layer is tapered so that the diameter of the opening of the adhesive layer decreases from a lower surface of the adhesive layer toward an upper surface of the adhesive layer,
wherein each of the opening of the carrier base material and the opening of the adhesive layer has a diameter that is smaller than that of the opening of the solder resist layer, and
wherein the adhesive layer is a separation layer that is separable from the solder resist layer to remove the carrier base material and the adhesive layer from the carrier base material-added wiring substrate.