US Pat. No. 10,249,397

MODULAR REACTOR STEAM GENERATOR CONFIGURED TO COVER A REACTOR OUTER WALL CIRCUMFERENCE

1. An apparatus comprising:a nuclear reactor comprising an upper head, a reactor vessel shell coupled to the upper head, the reactor vessel shell comprising a cylindrical shape, a lower head provided on a lower portion of the reactor vessel shell, and a core located within an interior of the nuclear reactor;
a steam generator surrounding a circumference of the reactor vessel shell, the steam generator comprising a first penetration hole in fluid communication with the interior of the nuclear reactor such that a fluid flows between the interior of the nuclear reactor and an interior of the steam generator; and
a steam drum surrounding a circumference of the steam generator and comprising a second penetration hole in fluid communication with an interior of the steam generator such that a fluid flows between an interior of the steam drum and the interior of the steam generator, wherein the steam generator further comprises:
a steam generator inner shell connected to or formed in one piece with the reactor vessel shell and surrounding 360 degrees the circumference of the reactor vessel shell, wherein the steam generator inner shell shares a portion with the reactor vessel shell and extends in a longitudinal direction of the reactor vessel shell; and
a steam generator outer shell spaced apart from the steam generator inner shell and surrounding 360 degrees the circumference of the reactor vessel shell, wherein the steam generator outer shell extends in the longitudinal direction of the reactor vessel shell,wherein the steam drum further comprises:a steam drum inner shell connected to or formed in one piece with the steam generator outer shell and surrounding 360 degrees the circumference of the steam generator, wherein the steam drum inner shell shares a portion with the steam generator outer shell and extends in the longitudinal direction of the reactor vessel shell; and
a steam drum outer shell spaced apart from the steam drum inner shell and surrounding 360 degrees the circumference of the steam generator, the steam drum outer shell extending in the longitudinal direction of the reactor vessel shell,
wherein the first penetration hole is provided in a region in which the reactor vessel shell and the steam generator inner shell are connected to or formed in one piece with each other and is used as a flow path allowing a fluid to flow between the interior of the nuclear reactor and the interior of the steam generator,
wherein the second penetration hole is provided in a region in which the steam generator outer shell and the steam drum inner shell are connected to or formed in one piece with each other and is used as a flow path allowing a fluid to flow between the interior of the steam generator and the interior of the steam drum.

US Pat. No. 10,249,395

CLEANING DEVICE FOR BOTTOM SURFACES

Ingenieria y Marketing, S...

1. A floor cleaner, comprising:an outer casing which forms a suction bell,
an upper suction mouth on said casing,
a pulling arrangement set on opposite sides of the casing, the pulling arrangement fitted with independent drive motors and corresponding transmission mechanisms on each side, and
cleaning rollers, the cleaning rollers including:
an assembly of interior cleaning rollers placed close to a center of the casing, and having a width substantially equal to a distance between lateral side elements of said casing, and
an assembly of outer cleaning rollers placed in a zone close to front and rear edges of the casing of the cleaner, and having a total width greater than a width of said casing.

US Pat. No. 10,249,394

PASSIVE NITROGEN INJECTING DEVICE FOR NUCLEAR REACTOR COOLANT PUMP

1. A passive nitrogen injection device for a nuclear reactor coolant pump, comprising:a nitrogen supply unit configured to supply nitrogen;
a pressure control valve configured to control supply of the nitrogen of the nitrogen supply unit according to a pressure;
an electronic control valve configured to selectively supply the nitrogen supplied through the pressure control valve;
an accumulator filled with the nitrogen supplied through the pressure control valve at a preset pressure and configured to supply the filled nitrogen when a loss-of-coolant accident occurs;
an isolation valve configured to control supply of the nitrogen of the accumulator to inside of a seal housing of a nuclear reactor coolant pump; and
a pressure gauge configured to detect a pressure of the accumulator, wherein the pressure gauge automatically fills the accumulator with nitrogen supplied by the nitrogen supply unit in a nitrogen injection system by opening the pressure control valve and the electronic control valve such that the pressure of the accumulator filled with nitrogen is maintained at a set pressure when a pressure of the accumulator detected by the pressure gauge is equal to or lower than the set pressure,
wherein when a loss-of-coolant accident (LOCA) occurs and external power is not supplied, the nitrogen filled in the accumulator is supplied to the inside of the seal housing by the pressure of the accumulator itself, the isolation valve being opened and the electronic control valve being closed when an LOCA occurs and external power is not supplied.

US Pat. No. 10,249,393

MODULAR REACTOR STEAM GENERATOR CONFIGURED TO COVER A REACTOR OUTER WALL CIRCUMFERENCE

1. An apparatus comprising:a nuclear reactor comprising an upper head, a reactor vessel shell coupled to the upper head, the reactor vessel shell comprises a cylindrical shape, a lower head provided on a lower portion of the reactor vessel shell, and a core located within an interior of the nuclear reactor; and
a steam generator surrounding a circumference of the reactor vessel shell, the steam generator comprising a first penetration hole and a second penetration hole, the first penetration hole in fluid communication with the interior of the nuclear reactor such that a fluid flows between the interior of the nuclear reactor and an interior of the steam generator, the second penetration hole being separate from the first penetration hole and in fluid communication with the inside of the nuclear reactor, such that a fluid flows between the interior of the nuclear reactor and an interior of the steam generator, wherein the steam generator further comprises:
a steam generator inner shell connected to or formed in one piece with the reactor vessel shell and surrounding 360 degrees the circumference of the reactor vessel shell, wherein the steam generator inner shell shares a portion with the reactor vessel shell and extends in a longitudinal direction of the reactor vessel shell; and
a steam generator outer shell spaced apart from the steam generator inner shell and surrounding 360 degrees the circumference of the reactor vessel shell, wherein the steam generator outer shell extends in the longitudinal direction of the reactor vessel shell,
wherein the first penetration hole and the second penetration hole are provided in a region in which the reactor vessel shell and the steam generator inner shell are connected to or formed in one piece with each other.

US Pat. No. 10,249,392

METHOD OF FORMING A SUPPORT STRUCTURE FOR A CONTROL ROD ASSEMBLY OF A NUCLEAR REACTOR

BWXT mPower, Inc., Charl...

10. A method comprising:forming a plurality of columnar elements defining a central passage having a constant cross-section;
constructing a control rod guide frame including the plurality of columnar elements by stacking the columnar elements end-to-end;
providing a control rod assembly comprising a plurality of control rods parallel aligned with the central passage of the control rod guide frame;
wherein the plurality of control rods is movable into and out of the central passage of the control rod guide frame, and wherein any portion of the at least one control rod disposed in the central passage is guided by the central passage over the entire length of the portion of the at least one control rod that is disposed in the central passage, and
wherein the control rod assembly comprises the plurality of control rods connected with a spider or other coupling element, and the spider or other coupling element is disposed in the central passage of the control rod guide frame and moves along the central passage as the plurality of control rods move into or out of the central passage.

US Pat. No. 10,249,391

REPRESENTATION OF SYMPTOM ALLEVIATION

COGNIFISENSE, INC., Sunn...

1. A system for modeling a symptom of a user comprising:a virtual reality (VR) headset;
a speaker; and
a computer system communicatively coupled with the VR headset and the speaker, the computer system comprising:
one or more processors; and
one or more computer-readable storage media having stored thereon computer-executable instructions that, when executed by the one or more processors, configure the computer system to create a multidimensional sensory environment comprising a VR environment and visual and aural sensory signals to model a symptom of a user by causing the computer system to perform at least the following:
generate a first digital model within the VR environment comprising a representation of one or more of a room, a landscape, an avatar, or a virtual control panel;
cause the VR headset to display the first digital model;
receive a description of a symptom comprising (i) a size, (ii) a sound, and (iii) a color associated with the symptom;
receive key characteristics of the symptom, the key characteristics comprising (a) a frequency, (b) an intensity, or (c) a saturation for one or more of (i) the size, (ii) the sound, or (iii) the color associated with the symptom;
generate a second digital model comprising a set of visual sensory signals and a set of aural sensory signals, the second digital model being a dynamic representation of the symptom based on the description and the key characteristics of the symptom;
cause the VR headset to display the set of visual sensory signals of the second digital model at a user-defined location within the VR environment; and
deliver the set of aural sensory signals associated with the second digital model to the speaker, the set of aural sensory signals customized to match at least the sound associated with the symptom, as provided by the description and key characteristics of the symptom.

US Pat. No. 10,249,390

METHOD FOR DETERMINING A PROACTIVITY SCORE FOR HEALTH

1. A method for determining a health proactivity score of a human, comprising steps of:receiving, into a computing device at a first instance, a first set of at least two characteristics associated with the human, wherein the at least two characteristics are selected from the group consisting of a height, a weight, a percentage of body fat, a waist circumference, a waist and hip ratio, and a neck size, and
wherein the at least two characteristics associated with the human are measured at a clinical center based on an appointment;
calculating, by the computing device, a first value of a health-related metric based upon the first set of the at least two characteristics received at the first time instance;
receiving, into the computing device at a second time instance, a second set of the at least two characteristics associated with the human;
calculating, by the computing device, a second value of the health-related metric based upon the second set of the at least two characteristics received at the second time instance;
storing, in a database, the first set of the at least two characteristics, the second set of the at least two characteristics, the first value of the health-related metric, and the second value of the health-related metric;
determining, by the computing device, a change between the second value of the health-related metric and the first value of the health-related metric;
determining, by the computing device, a category for the second value of the health-related metric from a plurality of pre-defined categories, wherein each pre-defined category is associated with a pre-defined range of a plurality of values of the health-related metric;
dynamically determining, by the computing device, an overall proactivity score of the human based upon (1) the determined category and, (2) the change between the second value of the health-related metric and the first value of the health-related metric, wherein the overall proactivity score increases in response to improvement of health of the human;
storing, in the database, the overall proactivity score of the human;
automatically decaying, by the computing device, the overall proactivity score over time based on both a lapse of pre-defined time period in response to no further reception of the at least two characteristics at a third time instance, wherein the third time instance is subsequent to both the first time instance and the second time instance and a current value of the health-related metric; wherein the decaying is executed from the predefined time period away from a date associated with the calculating of the second health-related metric; and
displaying, by the computing device, on a display of the computing device, the overall proactivity score.

US Pat. No. 10,249,389

INDIVIDUAL AND COHORT PHARMACOLOGICAL PHENOTYPE PREDICTION PLATFORM

THE REGENTS OF THE UNIVER...

1. A computer-implemented method for identifying pharmacological phenotypes using statistical modeling and machine learning techniques, the method executed by one or more processors programmed to perform the method, the method comprising:obtaining, at one or more processors, a set of training data including for each of a plurality of first patients:
panomic data indicative of biological characteristics of the first patient,
sociomic data indicative of risk factors associated with adverse cultural, childhood, acute or chronic traumatic events, or chronic stress resulting from adverse conditions,
environmental data indicative of experiences of the first patient collected over time, and
phenomic data indicative of at least one of: a response to one or more drugs, whether the first patient experiences substance abuse, or one or more chronic diseases of the first patient;
generating, by the one or more processors, a statistical model for determining pharmacological phenotypes based on the set of training data;
receiving, at the one or more processors, a set of panomic data, and sociomic and environmental data for a second patient collected over a period of time;
applying, by the one or more processors, the panomic data, and the sociomic and environmental data for the second patient to the statistical model to determine one or more pharmacological phenotypes for the second patient; and
providing, by the one or more processors, the one or more pharmacological phenotypes for the second patient for display to a health care provider, wherein the health care provider recommends a course of treatment to the second patient according to the pharmacological phenotypes.

US Pat. No. 10,249,388

METHODS AND SYSTEMS FOR REPLENISHING SUPPLIES IN A PRODUCT ARRAY

CooperVision Internationa...

1. A method comprising:displaying a digital image of an array of storage spaces on a client device having a screen to display the digital image of the array of storage spaces, wherein each storage space of the digital image of the array of storage spaces represents a contact lens prescription for a contact lens;
placing at least a three by three array of the digital image of the array of storage spaces displayed on the client device in a same general space as a three by three array of physical storage spaces so that the digital image of the array of storage spaces and the array of physical storage spaces may be viewed by a user, wherein each physical storage space is sized and shaped to store at least one contact lens package having a contact lens prescription and wherein the contact lens prescription of each storage space of the digital image of the array of storage spaces corresponds to the contact lens prescription of a contact lens for each corresponding storage space in the three by three array of physical storage spaces;
receiving, in the client device, a selection of a chosen storage space within the three by three array of the digital image of the array of storage spaces that corresponds to an empty storage space within the three by three array of the physical array of storage spaces, said selecting of the empty storage space defining a first order selection;
receiving, in the client device, an input of a number that corresponds to a quantity of contact lens packages to order for the first order selection; and
confirming an order in a shopping cart using the client device.

US Pat. No. 10,249,387

METHOD FOR MANAGING AN ELECTRONIC MEDICAL RECORD AND AN EMR MANAGEMENT SYSTEM

1. A method for managing an electronic medical record (EMR), the method to be implemented by an EMR management system for writing an EMR entry into a data storage device possessed by a patient, the EMR management system including a server, an attendance management device that is coupled to the server and that is disposed in proximity of a location where a health care service is to be performed for recording attendance of a health professional, and a computer that is coupled to the server and that is disposed at the location and that is separate from the attendance management device, the EMR management system storing in advance a schedule that contains information associated with the health professional and the location, the method comprising the steps of:generating, by the attendance management device, information associated with the health professional who provides the health care service that results in the EMR entry, and the location which is related to the health care service when the attendance management device is operated for attendance registration by the health professional;
determining, by the server, whether or not to permit writing of the EMR entry into the data storage device by comparing the information generated by the attendance management device and the information contained in the schedule;
the server giving the computer permission to write the EMR entry into the data storage device when it is determined that the information generated by the attendance management device conforms to the information contained in the schedule;
determining, by the computer when the data storage device is used to be connected to the computer, whether or not the patient agrees with writing of the EMR entry into the data storage device according to input of the patient;
writing, by the computer, the EMR entry into the data storage device when writing of the EMR entry is permitted by the server of the EMR management system and is agreed upon by the patient; and
withdrawing, by the server, the permission to write the EMR entry into the data storage device when departure registration, which is made by the health professional by punching out using the attendance management device, has completed for achieving secure circulation of medical records.

US Pat. No. 10,249,386

ELECTRONIC HEALTH RECORDS

Prosocial Applications, I...

1. A method of populating an exclusively patient controlled record in a patient controlled electronic health record (PCHR) record repository, the method comprising:processing a request from a patient for a health information artifact;
determining a supplier of the health information artifact;
generating one or more information request templates required by the supplier of the health information artifact;
generating an information request document using one or more of the information request templates;
encrypting the information request document;
sending the encrypted information request document to the supplier of the health information artifact;
receiving the health information artifact;
adding the health information artifact to the exclusively patient controlled record stored in the PCHR record repository; and
controlling access of a user, human or machine, to the exclusively patient controlled record in the PCHR record repository based on (a) patient authorization of the user for future record access and (b) consent from a registered device in response to the request of a patient-authorized user for current record access, wherein the registered device is a mobile device;
receiving a request from the user for access to the exclusively patient controlled record in the PCHR record repository;
determining if the user has previously been authorized by the patient for record access and patient-authorized user permissions associated with the record;
sending the access request of the patient-authorized user to the registered device; and
receiving a consent reply from the registered device.

US Pat. No. 10,249,385

SYSTEM AND METHOD FOR RECORD LINKAGE

Cerner Innovation, Inc., ...

1. One or more computer-readable storage devices having computer-usable instructions embodied thereon that, when executed, enable a given processor to perform a method of determining that a plurality of health records are related to the same human patient, the method comprising:receiving a target record from a first health-records system, the target record comprising at least one target record blocking variable and a date-time variable associated with the target record;
receiving one or more candidate records from a second health-records system, each candidate record comprising at least one candidate record blocking variable and information of a plurality of episodes associated with a candidate patient, said information including a date-time value associated with each episode of the plurality of episodes, wherein the at least one candidate record blocking variable is the same as the at least one target record blocking variable and comprises a birth day, birth month, birth year, or an indication of a condition, treatment, diagnosis, or other context; and
for each candidate record:
(1) based on said date-time variable associated with each episode, determining a timeseries of time intervals representing the time between each episode and a time duration from the date-time variable associated with a last candidate record episode to the target record date-time variable;
(2) for each timeseries, determining a normalized power-spectrum likelihood weight (“power spectra weight”), based on the timeseries;
(3) determining a record linkage weight based on a measure of lexical similarity between the candidate record and target record;
(4) based on the determined record linkage weight and power spectra weight, determining a composite candidate record score using a root-mean-square transformation, a cosine transformation, or correlation coefficient;
(5) performing a comparison of the candidate record score to a threshold;
(6) based on the comparison, determining that the candidate record score satisfies the threshold, designating the candidate record as related to the target record, adding an indication of the target record to the candidate record thereby creating an updated candidate record, and storing the updated candidate record in the first or second health-records system.

US Pat. No. 10,249,384

BAMBAM: PARALLEL COMPARATIVE ANALYSIS OF HIGH-THROUGHPUT SEQUENCING DATA

THE REGENTS OF THE UNIVER...

1. A computer implemented method of displaying genomic variants between a tumor tissue and a matched normal tissue comprising:receiving a reference genome or portion thereof, a first genetic sequence string object including first sub-strings from the tumor tissue and aligned to the reference genome or portion thereof, and a second genetic sequence string object including second sub-strings from the matched normal tissue and aligned to the reference genome or portion thereof;
generating at least one differential sequence object, each generated through incremental synchronized reading of the first sub-strings from the first genetic sequence string object and the second sub-strings from the second genetic sequence string object using a known position of at least one of a plurality of sub-strings corresponding to the known position to produce local alignment between the first sub-strings and the second sub-strings, the known position determined based on the reference genome or portion thereof, the incremental synchronized reading keeping sequence data read from the first genetic sequence string object and the second genetic sequence string object at common genomic locations across the reference genome or portion thereof during the generating;
instantiating, via a browser computer, the at least one differential sequence object stored in a computer memory, the at least one differential sequence object representing a difference between a localized alignment of multiple sequence reads of a tumor genome sequence of the tumor tissue and a matched normal genome sequence of the matched normal tissues;
identifying, via the browser computer, at least one genomic variant between the tumor tissue and the matched normal tissue based on the at least one differential sequence object at a genomic position corresponding to the localized alignment;
generating, via the browser computer, a browser image including a representation of the at least one genomic variant with respect to a reference genome sequence;
displaying, via the browser computer, on a display, the browser image; and
allowing, via the browser computer, displaying of genomic regions associated with the at least one genomic variant relative to the reference genome sequence.

US Pat. No. 10,249,383

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

9. A method for operating a data storage device including a nonvolatile memory device, the method comprising:adjusting a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state among program states having threshold voltages in a case where a program operation for memory cells of a page of the nonvolatile memory device fails;
reading out data by applying the adjusted read voltage to the memory cells of the page; and
performing an error handling operation to the data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits, which are different data bits between an original data output from an ECC unit before the program operation and the data read out by applying the adjusted read voltage.

US Pat. No. 10,249,382

DETERMINATION OF FAST TO PROGRAM WORD LINES IN NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. An apparatus, comprising:a word line;
a plurality of memory cells connected to the word line;
a programming circuit connected to the plurality of memory cells, the programming circuit configured to apply a series of voltage pulses to the word line during a programming operation;
a sensing circuit connected to the plurality of memory cells, the sensing circuit configured to perform a first verify operation for a first data state after a voltage pulse of the series of voltage pulses; and
a test circuit configured to determine a number of memory cells that satisfy the first verify operation and that are programmed above a reference voltage level and configured to signal an alert in response to the number of memory cells targeted for the first data state that are programmed above the reference voltage level exceeding a threshold number.

US Pat. No. 10,249,381

SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells;
an ECC (Error Checking and Correcting) circuit including an encoder and a decoder, the encoder being configured to generate error correcting codes when writing write data in the plurality of memory cells, and the decoder being configured to perform, when reading read data from the plurality of memory cells, correcting processing of the read data based on the error correcting codes;
a page buffer configured to store the write data, corrected data corrected by the correcting processing of the read data, and the error correcting codes used for the correcting processing; and
a multiplexer including a first input terminal coupled to the encoder, a second input terminal coupled to the page buffer, and an output terminal coupled to the memory cell array, the first input terminal being selected when writing the write data in the plurality of memory cells, and the second input terminal being selected when writing the corrected data in the plurality of memory cells;
wherein a write operation includes a first operation of reading the read data from the plurality of memory cells, a second operation of writing the corrected data and the error correcting codes used for the correcting processing in the plurality of memory cells, and a third operation of writing, in the plurality of memory cells, the write data and error correcting codes generated based on the write data, and the first operation and the second operation are successively executed.

US Pat. No. 10,249,380

EMBEDDED MEMORY TESTING WITH STORAGE BORROWING

QUALCOMM Incorporated, S...

1. An integrated circuit comprising:a functional logic block including multiple storage units, the functional logic block configured to store functional data in the multiple storage units during a regular operational mode, each storage unit of the multiple storage units comprising:
multiplexer circuitry including a first input configured to receive the functional data, a second input configured to receive scan input data, and a third input configured to receive memory test result data;
a memory block; and
test logic configured to perform a test on the memory block to generate the memory test result data, the test logic configured to retain the memory test result data in the multiple storage units of the functional logic block using the third input of the multiplexer circuitry during a testing mode.

US Pat. No. 10,249,379

ONE-TIME PROGRAMMABLE DEVICES HAVING PROGRAM SELECTOR FOR ELECTRICAL FUSES WITH EXTENDED AREA

Attopsemi Technology Co.,...

1. A One-Time Programmable (OTP) memory, comprising:a plurality of OTP cells, at least one of the OTP cells including at least:
an OTP element including at least an electrical fuse coupled to a first supply voltage line; and
a program selector coupled to the OTP element and to a second supply voltage line,
wherein at least a portion of the electrical fuse has at least one extended area, the portion of the electrical fuse pertaining to the extended area has substantially no current flowing therethrough even during program or read operations for the OTP element including the electrical fuse, and
wherein the OTP element is configured to be programmable by applying voltages to the first and second supply voltage lines and by turning on the program selector to thereby change the OTP element into a different logic state,
wherein the program selector including at least a first active region and a second active region isolated from the first active region, the first active region having a first type of dopant and a second active region having a second type of dopant, the first active region providing a first terminal of the program selector, the second active region providing a second terminal of the program selector, both the first and second active regions residing in a common CMOS well or on an isolated substrate, at least one of the first and second active regions being fabricated from sources or drains of CMOS devices.

US Pat. No. 10,249,378

FLASH MEMORY DEVICE AND METHOD FOR RECOVERING OVER-ERASED MEMORY CELLS

Winbond Electronics Corp....

1. A method for recovering over-erased memory cells of a flash memory device using a Fowler-Nordheim (FN) post-programming operation, comprising:selecting a memory block which comprises at least one over-erased memory cell in the flash memory device, wherein the selected memory block comprises a common bulk line and a common source line;
applying a negative voltage to the common bulk line and the common source line of the selected memory block; and
applying a positive voltage to word lines that are coupled to the at least one over-erased memory cell in the selected memory block, wherein the negative voltage is smaller than zero volts and the positive voltage is greater than zero volts.

US Pat. No. 10,249,377

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a memory cell;
a bit line coupled to the memory cell;
a sense amplifier coupled to the bit line;
a word line coupled to a gate of the memory cell; and
a row decoder coupled to the word line,
wherein a write operation repeats a program loop including a program operation, a first verify operation performed after the program operation, and a second verify operation performed after the first verify operation,
the row decoder applies a first read voltage to the word line in the first and second verify operations,
when the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation,
when the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation, and
the sense amplifier senses the voltage of the bit line for a third sense period longer than the first sense period in the second verify operation.

US Pat. No. 10,249,376

FLASH MEMORY STORAGE DEVICE AND OPERATING METHOD THEREOF

Winbond Electronics Corp....

1. A flash memory storage device, comprising:a memory cell array, comprising a plurality of memory blocks and a redundant memory block, wherein the memory blocks are configured to store data; and
a memory control circuit, coupled to the memory cell array and configured to perform an erase operation to a current memory block of the memory blocks and record an erase retry count of the current memory block;
wherein the memory control circuit determines whether the erase retry count exceeds a first threshold value, and the memory control circuit replaces the current memory block by the redundant memory block erased in advance during a time interval of the erase operation if the erase retry count exceeds the first threshold value.

US Pat. No. 10,249,375

FLASH MEMORY ARRAY WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE

Silicon Storage Technolog...

1. A memory device, comprising:a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region,
a control gate disposed over and insulated from the floating gate,
a select gate disposed over and insulated from a second portion of the channel region adjacent the drain region, and
an erase gate disposed over and insulated from the source region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates for the row of memory cells; and
each of the columns of memory cells includes an erase gate line that electrically connects together all the erase gates for the column of memory cells and is not electrically connected to erase gates in others of the columns of the memory cells.

US Pat. No. 10,249,374

VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE

LAPIS Semiconductor Co., ...

1. A voltage supply circuit, comprising:a step-down circuit configured to receive a power supply voltage, and step down the power supply voltage to generate a step-down voltage having a constant value lower than a value of the power supply voltage;
a booster circuit configured to boost the step-down voltage to generate an output voltage so as to suppress an amplitude of ripples in the output voltage, the output voltage having a value greater than the value of the power supply voltage, the booster circuit configured to output the output voltage to a column decoder to supply a corresponding write voltage to a memory cell array; and
a control circuit configured to control turning-on and turning-off of the booster circuit based on each of the output voltage, a selection signal from a memory control unit, and a predetermined clock signal.

US Pat. No. 10,249,373

CIRCUIT AND METHOD FOR READING A MEMORY CELL OF A NON-VOLATILE MEMORY DEVICE

STMICROELECTRONICS S.R.L....

1. A method for reading a memory cell of a non-volatile memory device provided with a memory array with memory cells arranged in wordlines and bitlines, the bitlines including a first bitline associated with the memory cell to be read and a second bitline distinct from the first bitline, wherein a first circuit branch is associated with the first bitline and a second circuit branch is associated with the second bitline, the memory cell being activatable via a wordline coupled to a control terminal of the memory cell, each of the first and second circuit branches having a local node and a global node, each local node coupled to a first dividing capacitor, each global node coupled to a second dividing capacitor, the method comprising:pre-charging the global nodes and the local nodes to a pre-charging voltage, wherein the memory cell is deactivated during the pre-charging;
equalizing the global nodes by coupling the global nodes of the first circuit branch and the second circuit branch so that the global nodes reach a common initial voltage, wherein the memory cell is deactivated during the equalizing; and
reading data stored in the memory cell by:
activating the memory cell via the wordline so that a respective voltage value at the local node of the first circuit branch discharges as a function of the data stored in the memory cell;
coupling, while the memory cell is activated via the wordline, the local node of the first circuit branch to the global node of the first circuit branch to generate a charge division between the first dividing capacitor of the first circuit branch and the second dividing capacitor of the first circuit branch so that the voltage of the global node of the first circuit branch goes to a value that is different from the common initial voltage as a function of the data stored in the memory cell; and
generating, while the memory cell is activated via the wordline, an output signal based upon a comparison between a first comparison voltage that is a function of the voltage of the global node of the first circuit branch, and a second comparison voltage that is a function of the voltage of the global node of the second circuit branch.

US Pat. No. 10,249,372

REDUCING HOT ELECTRON INJECTION TYPE OF READ DISTURB IN 3D MEMORY DEVICE DURING SIGNAL SWITCHING TRANSIENTS

SanDisk Technologies LLC,...

1. An apparatus, comprising:a plurality of memory strings arranged in a selected sub-block and an unselected sub-block, each memory string comprising select gate transistors and memory cells between the select gate transistors;
a plurality of word lines connected to the memory cells;
an unselected word line control circuit configured to apply a voltage at a read pass level to unselected word lines among the plurality of word lines;
a selected word line control circuit configured to apply a voltage at one or more control gate read levels to a selected word line among the plurality of word lines; and
a select gate control circuit associated with the unselected sub-block, configured to provide one or more transitions of at least some of the select gate transistors in the unselected sub-block from a non-conductive state to a conductive state and back to the non-conductive state while the voltage at the one or more control gate read levels is applied on the selected word line and while the voltage at the read pass level is applied to the unselected word lines.

US Pat. No. 10,249,371

CONTROL CIRCUIT, SEMICONDUCTOR STORAGE DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE

FUJITSU LIMITED, Kawasak...

1. A control circuit that controls a memory including a storage region and a redundant region, the control circuit comprising:a detector that detects a defective block in the memory; and
a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme and stores the remaining portion of the data stored in the first block in the first storage scheme to be stored in a second block of the redundant region,
the controller writes all the data stored in the first block in the first storage scheme in the second block of the redundant region and a third block of the redundant region, switches the data storage scheme of the first block from the first storage scheme to the second storage scheme, and writes back data written in the third block of the redundant region to the first block in the second storage scheme after the switching of the data storage scheme.

US Pat. No. 10,249,370

THREE-DIMENSIONAL VERTICAL NOR FLASH THING-FILM TRANSISTOR STRINGS

Sunrise Memory Corporatio...

1. A memory structure, comprising:a storage transistor having a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage representative of data stored therein;
a word line connected to the gate terminal to provide a control voltage during a read operation;
a bit line connecting the first drain or source terminal to data detection circuitry; and
a source line connected to the second drain or source terminal to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

US Pat. No. 10,249,369

SEMICONDUCTOR MEMORY DEVICE WITH FAST AND SLOW CHARGE AND DISCHARGE CIRCUITS

LAPIS Semiconductor Co., ...

1. A semiconductor memory including a memory cell, a pair of bit lines connected to said memory cell to transmit a data signal, and a sense amplifier connected to said pair of bit lines and to amplify the potentials of said pair of bit lines, said semiconductor memory comprising:a first discharge circuit configured to discharge electric charge stored in said pair of bit lines;
a second discharge circuit configured to discharge the electric charge stored in said pair of bit lines; and
a control part configured to selectively execute a low-speed discharge mode for operating only said second discharge circuit of said first and second discharge circuits, a high-speed discharge mode for operating both of said first and second discharge circuits, and a stop mode for stopping both of said first and second discharge circuits.

US Pat. No. 10,249,368

SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY COMPRISING RESISTIVE CHANGE MATERIAL AND METHOD OF OPERATING

Zeno Semiconductor, Inc.,...

1. A semiconductor memory array comprising:a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a floating body region;
a non-volatile memory comprising a bipolar resistive change element;
wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell;
wherein said array is configured to perform a restore operation on said at least two of said memory cells in parallel.

US Pat. No. 10,249,367

SEMICONDUCTOR APPARATUS COMPRISING A PLURALITY OF CURRENT SINK UNITS

SK hynix Inc., Icheon-si...

1. A processor, comprising:a processor configured to interpret a command input from the outside and control an operation of information according to an interpretation result of the command;
an auxiliary storage device configured to store a program for interpretation of the command, and the information;
a main storage device configured to transfer the program and information from the auxiliary storage device and store the program and the information so that the processor performs the operation using the program and information when the program is executed; and
an interface device configured to perform communication between the outside and one or more among the processor, the auxiliary storage device, and the main storage device,
wherein at least one of the auxiliary storage device and the main storage device includes a semiconductor memory apparatus comprising:
a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements in response to a column select signal;
a plurality of current sink units configured to flow current from one of the plurality of resistive memory elements to a ground terminal in response to a plurality of word line select signals; and
a sink current control unit configured to control the plurality of current sink units to flow different amounts of current from the plurality of current sink units to the ground terminal.

US Pat. No. 10,249,366

INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF

Sony Semiconductor Soluti...

1. A memory device comprising:a memory array configured to include a plurality of memory cells;
a controller configured to connect to the memory array via a plurality of word lines;
an interface configured to connect to the memory array via a plurality of bit lines and detect whether a memory cell is in a low resistive state or a high resistive state during a memory read operation; and
a limiter configured to connect to the plurality of bit lines and to limit or clamp a voltage to a predetermined threshold level when the interface detects that the memory cell is in the high resistive state,
wherein the interface includes a set/reset driver connected to the limiter,
wherein the set/reset driver is disabled during the memory read operation, and
wherein the limiter does not limit or clamp the voltage when the interface detects that the memory cell is in the low resistive state.

US Pat. No. 10,249,365

TWO-PART PROGRAMMING METHODS

Micron Technology, Inc., ...

1. A memory device, comprising:control logic;
wherein the control logic is configured to set a first start program voltage and a first stop program voltage for a write operation on a plurality of memory cells;
wherein the control logic is configured to cause the memory device to load actual first data for each memory cell of the plurality of memory cells to be programmed to a respective level greater than or equal to a first particular level;
wherein the control logic is configured to cause the memory device to load inhibit data for each memory cell of the plurality of memory cells to be programmed to a respective level less than a second particular level;
wherein the control logic is configured to cause the memory device to program each memory cell of the plurality of memory cells to be programmed to a respective level greater than or equal to the first particular level with the actual first data using program pulses in a first range from the first start program voltage to the first stop program voltage;
wherein the control logic is configured to set a second start program voltage and a second stop program voltage for the write operation on the plurality of memory cells;
wherein the control logic is configured to cause the memory device to load inhibit data for each memory cell of the plurality of memory cells programmed to a respective level greater than or equal to the first particular level;
wherein the control logic is configured to cause the memory device to load actual second data for each memory cell of the plurality of memory cells to be programmed to a respective level less than the second particular level;
wherein the control logic is configured to cause the memory device to program each memory cell of the plurality of memory cells to be programmed to a respective level less than the second particular level with the actual second data using program pulses in a second range from the second start program voltage to the second stop program voltage; and
wherein the first particular level is one level higher than the second particular level.

US Pat. No. 10,249,364

WORD LINE OVERDRIVE IN MEMORY AND METHOD THEREFOR

Everspin Technologies, In...

1. A method for writing to a magnetic memory cell that includes a selection transistor coupled in series with a magnetic tunnel junction, the method comprising:applying a de-select voltage to a gate of the selection transistor while a voltage at a second end of the selection transistor is a low standby voltage, wherein:
a first end of the magnetic memory cell corresponds to a first end of the selection transistor;
the second end of the magnetic memory cell corresponds to a second end of the magnetic tunnel junction; and
a second end of the selection transistor is coupled to a first end of the magnetic tunnel junction;
applying a first word line voltage to the gate of the selection transistor, wherein a difference between the first word line voltage and the low standby voltage is below a predetermined stress voltage level for the selection transistor;
while applying the first word line voltage, enabling an initial voltage across the memory cell such that the voltage at the second end of the selection transistor is raised from the low standby voltage to a raised source voltage that includes a voltage across the magnetic tunnel junction;
after the voltage at the second end of the selection transistor is raised to the raised source voltage, applying a second word line voltage to the gate of the selection transistor, wherein the second word line voltage is greater than the first word line voltage;
while applying the second word line voltage, applying a voltage across the magnetic memory cell that forces a free portion of the magnetic memory cell to a first state as a part of a first writing operation.

US Pat. No. 10,249,363

CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT SRAM

STMicroelectronics Intern...

1. A memory controller for a memory array having word lines and bit lines, the memory controller comprising:a row decoder;
a row pre-decoder configured to output an address for use by the row decoder:
a read-write clock generator configured to generate a hold clock signal;
an address clock generator configured to receive a read address and a write address, and which is operable in a single port mode and in a dual port mode; and
wherein the address clock generator, when operating in the dual port mode, is configured to:
in a read mode, latch the read address and output the read address to the row pre-decoder as the address as a function of the hold clock signal, and
in a write mode, latch the write address and output the write address to the row pre-decoder as the address as a function of the hold clock signal.

US Pat. No. 10,249,362

COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS

GSI Technology, Inc., Su...

1. A memory computation cell, comprising:a storage cell;
at least one read bit line;
an isolation circuit that buffers the storage cell from signals on the at least one read bit line, the isolation circuit having a read word line and a complementary read word line; and
wherein the memory cell is capable of performing an exclusive logic function when the memory cell is connected to the at least one read bit line with another memory cell and by turning on read word line or complementary read word line of one memory cell to have the exclusive logic result between the read word line and the storage cell data of the memory cell on the read bit line; and
wherein the read bit line is configured to provide read access to storage cell data.

US Pat. No. 10,249,361

SRAM WRITE DRIVER WITH IMPROVED DRIVE STRENGTH

NVIDIA CORPORATION, Sant...

1. A subsystem, comprising:a first bit line driver that drives a single bit line of a memory cell, writes a data bit to the memory cell, and includes:
a first field effect transistor (FET) that includes:
a first FET gate terminal that receives a first write select line as an input,
a first FET first data terminal that transmits a first data line that transports the data bit, and
a first FET second data terminal directly coupled to the first data line;
a second FET that includes:
a second FET pate terminal that receives the first write select line as an input, and
a second FET data terminal that is directly coupled to the first FET first data terminal; and
a first circuit element that includes:
a first input terminal directly coupled to the first FET first data terminal and the second FET data terminal, and
a first circuit data terminal that is directly coupled to the single bit line of the memory cell.

US Pat. No. 10,249,360

METHOD AND CIRCUIT FOR GENERATING A REFERENCE VOLTAGE IN NEUROMORPHIC SYSTEM

NATIONAL TSING HUA UNIVER...

1. A method for generating a reference voltage adapted for an artificial neural network system connected to a storage device with a memory cell array comprising a plurality of neurons arranged in a matrix and connected to a plurality of word-lines, respectively, the method comprising the steps of:arranging a first column of dummy neurons with weight 0 and a second column of dummy neurons with weight 1 with a number corresponding to a number of a row of the memory cell array;
connecting the plurality word-lines to the dummy neurons in the first and second columns, respectively;
disposing a bit-line connecting to a clamping circuit and the first column of dummy neurons;
disposing a complementary bit-line connecting to an adaptive header and the second column of dummy neurons;
connecting the clamping circuit and the adaptive header to a voltage source; and
connecting the bit-line to the complementary bit-line at an output end of the reference voltage;
wherein when the artificial neural network system is operated to sense the neurons of the memory cell array, one or more of the plurality of word-lines are activated, and the corresponding dummy neurons of the first column and the second column are activated to generate the reference voltage at the output end for sensing the neurons of the memory cell array.

US Pat. No. 10,249,359

ADDRESS GENERATION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

SK hynix Inc., Gyeonggi-...

1. An address generation circuit comprising:a first latch unit configured to latch a first address obtained by inverting a part of an input address;
a second latch unit configured to latch the first address latched in the first latch unit at a first time, and configured to latch an added/subtracted address at a second time different form the first time after a first refresh operation during a target row refresh operation, wherein the address latched in the second latch unit at each of the first and second times is a target address for the target row refresh operation;
a third latch unit configured to latch the first address latched in the first latch unit during operations other than the target row refresh operation; and
an addition/subtraction unit configured to generate the added/subtracted address by adding/subtracting a predetermined value to/from the address latched in the second latch unit.

US Pat. No. 10,249,358

APPARATUSES AND METHODS FOR CONFIGURABLE COMMAND AND DATA INPUT CIRCUITS FOR SEMICONDUCTOR MEMORIES

Micron Technology, Inc., ...

1. An apparatus, comprising:a command decoder configured to receive command signals and provide internal control signals to cause an operation to be performed, wherein the operation to be performed includes at least a read operation and a write operation; and
a clock blocking circuit, the clock block circuit configured to receive a first progress signal indicative of a read operation in progress, a second progress signal indicative of a write operation in progress, and a clock signal, the clock blocking circuit configured to provide an active read clock signal, an active write clock signal, and an active common clock signal responsive to an active clock signal when the first and second progress signals indicate neither a write nor read operation is in progress, and further configured to provide the active read and active common clock signals and an inactive write clock signal when the first progress signal indicates a read operation in progress and to provide the active write and active common clock signals and an inactive read clock signal when the second progress signal indicates a write operation is in progress.

US Pat. No. 10,249,357

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having a memory region and a peripheral region defined thereon, wherein the peripheral region comprises at least one transistor, the memory region comprises a plurality of memory cells, and each memory cell comprises at least one gate structure and a capacitor structure;
a mask layer disposed on the capacitor structure in the memory region; and
a dielectric layer disposed on the substrate within the peripheral region, wherein a top surface of the dielectric layer is aligned with a top surface of the mask layer.

US Pat. No. 10,249,356

MEMCAPACITIVE CROSS-BAR ARRAY FOR DETERMINING A DOT PRODUCT

HEWLETT PACKARD ENTERPRIS...

1. A memcapacitive cross-bar array for determining a dot product, comprising:a number of row lines;
a number of column lines intersecting the row lines to form a number of junctions;
a number of capacitive memory devices coupled between the row lines and the column lines at the junctions, the capacitive memory devices to:
receive a number of programming signals, the programming signals defining a number of values within a matrix, and
receive a number of vector signals as voltages inputted into the row lines, the vector signals defining a number of vector values to be applied to the capacitive memory devices; and
a charge collection line to collect charges as an output from the respective column lines of the capacitive memory devices, the collected charges equaling a dot product of the matrix values and vector values, wherein the collected charges are returned from the voltages inputted into the row lines.

US Pat. No. 10,249,355

APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS TO A COMMAND PATH CIRCUIT

Micron Technology, Inc., ...

1. An apparatus comprising:a command path circuit configured to receive a first command signal, the first command signal and a chip select signal provided to the apparatus, the command path circuit further configured to provide an output command responsive, at least in part, to a clock signal, and wherein the first command signal is provided during a command cycle, wherein the command cycle is a first number of clock cycles of the clock signal; and
a command path clock circuit coupled to the command path circuit and configured to, starting at a first clock cycle of the command cycle, provide the clock signal for a second number of clock cycles of the clock signal to the command path circuit responsive, at least in part, to the chip select signal and stopping provision of the clock signal after the second number of clock cycles, and wherein the second number of clock cycles of the clock signal is less than the first number of clock cycles of the clock signal.

US Pat. No. 10,249,354

APPARATUSES AND METHODS FOR DUTY CYCLE DISTORTION CORRECTION OF CLOCKS

Micron Technology, Inc., ...

1. An apparatus, comprising:a receiver circuit configured to provide complementary clocks responsive to an input clock, the receiver circuit further configured to provide the complementary clocks having first high and low voltage amplitudes in a first mode and to provide the complementary clocks having second high and low voltage amplitudes in a second mode; and
a divider circuit configured to provide multiphase clocks responsive to the complementary clocks, wherein the multiphase clocks responsive to the complementary clocks in the second mode having less duty cycle distortion than the multiphase clocks responsive to the complementary clocks in the first mode.

US Pat. No. 10,249,353

MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS

Rambus Inc., Sunnyvale, ...

1. An Apparatus comprising:an interface circuit comprising:
a pad for coupling the apparatus to a data bus;
a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one first clock output to output a first phase adjusted clock signal; and
a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least one second clock output to output a second phase adjusted clock signal,
wherein the interface circuit uses the first phase adjusted clock signal to read data via the pad during a first read operation and uses the second phase adjusted clock signal to read data via the pad during a second read operation after the first read operation.

US Pat. No. 10,249,352

MEMORY DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory device comprising:a memory cell;
a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell;
a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse;
a hold circuit configured to hold a peak value of the second signal; and
a sense amplifier circuit configured to read data from the memory cell based on the peak value,
wherein the filter circuit comprises a high pass filter circuit, and
the first frequency domain is higher than a cutoff frequency of the filter circuit in the first signal.

US Pat. No. 10,249,351

MEMORY DEVICE WITH FLEXIBLE INTERNAL DATA WRITE CONTROL CIRCUITRY

Intel Corporation, Santa...

1. A memory controller, comprising:command logic to generate a write pattern command to trigger an associated dynamic random access memory (DRAM) device to write data to a memory array of the DRAM device without having to send the data to the DRAM device; and
I/O (input/output) circuitry including an interface to a command bus and to a data bus to the DRAM device, wherein the I/O circuitry is to drive the write pattern command to trigger the DRAM device to internally generate a write pattern to write, instead of data bits from the data bus, including to trigger the DRAM device to access the write pattern from a mode register, wherein the I/O circuitry is to send a mode register write command to the DRAM device to program the write pattern.

US Pat. No. 10,249,350

APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells;
a controller configured to operate sensing circuitry to:
perform a first XOR operation on a data value stored in a first memory cell and a data value stored in a second memory cell of a number of memory cells coupled to a sense line of the array that results in a first resultant value; and
perform a second XOR operation on the first resultant value and a data value stored in a third memory cell of the number of memory cells resulting in a second resultant value, wherein the second resultant value protects the data stored in the first memory cell, the data stored in the second memory cell, and the data stored in the third memory cell.

US Pat. No. 10,249,349

CONTROL SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a memory device including a first cell transistor; and
a controller configured to:
store information on a first temperature associated with a temperature of the memory device upon a write of data into the first cell transistor,
obtain a second temperature of the memory device,
determine an adjustment based on a combination of the first temperature and the second temperature, and
instruct the memory device to use a first parameter to read data from the first cell transistor, the first parameter being based on the determined adjustment.

US Pat. No. 10,249,348

APPARATUSES AND METHODS FOR GENERATING A VOLTAGE IN A MEMORY

Micron Technology, Inc., ...

1. An apparatus, comprising:a pull-up circuit configured to be coupled to a power supply and coupled to an output node at which an output voltage is provided;
a capacitance coupled to the output node and to a gate node of the pull-up circuit;
a pull-down circuit configured to be coupled to a reference voltage and coupled to the output node;
an input circuit coupled to the output node and to a gate node of the pull-down circuit, the input circuit configured to receive an input voltage;
a first transistor coupled to the gate node of the pull-up circuit and to the gate node of the pull-down circuit, the first transistor configured to receive a first bias signal; and
a second transistor coupled to the gate node of the pull-up circuit and to the gate node of the pull-down circuit, the second transistor configured to receive a second bias signal.

US Pat. No. 10,249,347

SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first memory cell; and
a second memory cell,
wherein each of the first memory cell and the second memory cell comprises:
a transistor comprising a gate, a first terminal, and a second terminal;
a volatile memory circuit electrically connected to the first terminal and a bit line; and
a capacitor comprising a first electrode electrically connected to the second terminal and a second electrode electrically connected to a potential control line,
wherein the volatile memory circuits of the first and second memory cells are directly connected to a same word line,
wherein the volatile memory circuit of the first memory cell is configured to store a datum in a first period,
wherein a node between the transistor and the capacitor of the first memory cell is configured to store the datum in a second period,
wherein the potential control line is set at a low power supply potential when the transistor of the first memory cell is in an on state in the first period, and
wherein the potential control line is set at a high power supply potential when the transistor of the first memory cell is in an off state in the second period.

US Pat. No. 10,249,346

POWER SUPPLY AND POWER SUPPLYING METHOD THEREOF FOR DATA PROGRAMMING OPERATION

Winbond Electronics Corp....

1. A power supply for data programming operation, adapted for a memory apparatus, comprising:a plurality of charge pump circuits, commonly generating an output voltage for programming a write data to the memory apparatus, wherein each of the charge pump circuits comprises:
a plurality of charge pump units coupled in series; and
a switch, coupled between a last stage charge pump unit and output ends of the charge pump circuits, and controlled by a corresponding bit of the write data to be turned-on or cut-off, wherein the output voltage is output to the output ends of the charge pump circuits when the switch is turned on, and the output voltage is not output to the output ends of the charge pump circuits when the switch is cut off,
wherein number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.

US Pat. No. 10,249,345

MEMORIES HAVING SELECT DEVICES BETWEEN ACCESS LINES AND IN MEMORY CELLS

Micron Technology, Inc., ...

1. A memory, comprising:a first bi-directional diode connected between a first access line and a second access line;
a second bi-directional diode connected between a third access line and a fourth access line; and
a plurality of memory cells;
wherein each memory cell of the plurality of memory cells comprises a respective third bi-directional diode, of a plurality of third bi-directional diodes, and a respective programmable element, of a plurality of programmable elements, connected in series;
wherein each memory cell of a first subset of the plurality of memory cells is connected between the second access line and a respective fifth access line of a plurality of fifth access lines;
wherein each memory cell of a second subset of the plurality of memory cells, mutually exclusive of the first subset of the plurality of memory cells, is connected between the fourth access line and a respective fifth access line of the plurality of fifth access lines; and
wherein the first bi-directional diode, the second bi-directional diode, and each third bi-directional diode of the plurality of third bi-directional diodes are configured to be biased in a same direction in response to a particular bias applied to the first access line and to the third access line and a different bias applied to each fifth access line of the plurality of fifth access lines.

US Pat. No. 10,249,344

TAPE DRIVE CORROSION PROTECTION

International Business Ma...

1. A method for corrosion protection of a tape drive based on a tape drive corrosion protection system, the system comprising the tape drive, a temperature sensor, a heating entity and a controller for activating the heating entity, said method comprising:determining, via a humidity sensor, humidity information;
establishing, via the temperature sensor, temperature information indicative of a temperature in an area of, or within, the tape drive;
receiving the temperature information at the controller; and
activating the heating entity in a manner dependent on the temperature information established via the temperature sensor in order to prevent corrosion within the tape drive, said activating the heating entity being in response to a determination that the humidity information determined via the humidity sensor indicates that the relative humidity is above a specified relative humidity threshold value and the established temperature information indicates a temperature drop above a specified temperature drop value within a specified period of time.

US Pat. No. 10,249,343

HARD DISK DRIVE HOLDER

Lite-On Electronics (Guan...

1. A hard disk drive holder, comprising:a bottom plate, wherein a plurality of gaps and a first bending line define a bendable portion and an unbendable portion on the bottom plate;
a first side plate, having a plurality of first positioning portions; and
a second side plate, having a plurality of second positioning portions, wherein the first side plate and the second side plate are respectively and integrally connected to opposite sides of the bottom plate, and the first positioning portions and part of the second positioning portions are correspondingly disposed to be adapted to install a first hard disk drive,
wherein the bendable portion has a plurality of third positioning portions, the third positioning portions and part of the second positioning portions are correspondingly disposed to be adapted to install at least one second hard disk drive, and a size of the at least one second hard disk drive is less than a size of the first hard disk drive.

US Pat. No. 10,249,342

BASE UNIT, DISK DRIVE APPARATUS, AND METHOD OF MANUFACTURING BASE UNIT

NIDEC CORPORATION, Kyoto...

1. A base unit comprising:a connector electrically connected to a motor having a central axis extending in a vertical direction, the connector including a board portion and an electrode terminal;
a motor support portion arranged to support the motor; and
a connector support portion arranged to support the board portion of the connector; wherein
the connector support portion includes:
a bottom plate portion arranged to extend perpendicularly to the central axis, and arranged to support a lower surface of the board portion;
a window portion arranged to pass through the bottom plate portion in an axial direction, and arranged to cover or overlap with the electrode terminal of the connector when viewed in the axial direction;
a first recessed portion defined in an upper surface of the bottom plate portion around the window portion, and arranged to overlap with the lower surface of the board portion when viewed in the axial direction; and
a second recessed portion defined in the upper surface of the bottom plate portion, and arranged to be spaced apart from the first recessed portion;
the first recessed portion has a thermosetting adhesive arranged therein to fix the bottom plate portion and the board portion to each other; and
the second recessed portion has a temporarily fixing adhesive arranged therein to temporarily fix the bottom plate portion and the board portion to each other.

US Pat. No. 10,249,341

METHOD, APPARATUS AND SYSTEM FOR SYNCHRONIZING AUDIOVISUAL CONTENT WITH INERTIAL MEASUREMENTS

INTERDIGITAL CE PATENT HO...

1. A method for synchronizing audiovisual content with inertial measurements associated with timestamps on a mobile device recording the audiovisual content, said audiovisual content comprising a synchronized audio track, comprising:in response to a vibration of the mobile device, recording an audio signal within the audio track and an inertial signal within the inertial measurements, both being generated by said vibration;
processing the recorded audio signal to determine a first timestamp for a peak in the audio signal;
processing the recorded inertial signal to determine a second timestamp for a peak in the inertial signal;
determining a time distance between the first timestamp and the second timestamp; and
adjusting timestamps of the inertial signal by said time distance causing the synchronization of audiovisual content with inertial measurements.

US Pat. No. 10,249,340

VIDEO GENERATION DEVICE, VIDEO GENERATION PROGRAM, AND VIDEO GENERATION METHOD

1. A video generation device comprising:a memory storing a video generation program; and
a central control unit for performing a control to extract multiple occurrences of valid line-of-sight information included in a reproduction sequence upon executing the video generation program, to select a plurality of frames relating to the multiple occurrences of line-of-sight information, so that a constant number of frames will exist between a pair of the occurrences of line-of-sight information, to extract multiple occurrences of stroke information relating to the selected frames in a number adjusted so as to keep constant the number of frames between the pair of occurrences of line-of-sight information, to renew an omnidirectional image based on the line-of-sight information and drawing attribute where the stroke information includes the drawing attribute, to generate new line-of-sight information in an interpolated manner based on the extracted line-of-sight information, adjacent line-of-sight information, and the position of the extracted frame, upon completion of extraction of the entire stroke information relating to the selected frame, to make drawing the omnidirectional image on a screen image based on the interpolated line-of-sight information, and to write the screen image as an image of the selected frame.

US Pat. No. 10,249,339

READ-AFTER-WRITE METHODOLOGY USING MULTIPLE ACTUATORS MOVEABLE OVER THE SAME MAGNETIC RECORDING DISK SURFACE

Seagate Technology LLC, ...

1. An apparatus, comprising:one or more magnetic recording disks coupled to a spindle motor, each of the disks having opposing recording surfaces;
two or more actuators that independently move over at least a first recording surface of the one or more disks;
a first actuator of the two or more actuators comprising a first write head and a first read head;
a second actuator of the two or more actuators comprising at least a second read head; and
a controller coupled to the two or more actuators and configured to:
write data to a track on the first recording surface using the first write head;
within one revolution of the first recording surface after the data is written to the track, perform a read operation on the data written to the track using the second read head; and
verify that the data was successfully written to the track by the first write head in response to the read operation performed by the second read head.

US Pat. No. 10,249,338

SHINGLED MAGNETIC RECORDING STORAGE SYSTEM DURING VIBRATION

SEAGATE TECHNOLOGY, LLC, ...

1. A method comprising:receiving a write command to write data on a first track in a band of a storage medium;
skipping the first track responsive to determining a number of vibration events is above a vibration predetermined threshold;
seeking to a second track adjacent to the first track; and
increasing an on-cylinder limit (OCLIM) on the second track adjacent to the first track from a default OCLIM to an increased OCLIM.

US Pat. No. 10,249,337

MAGAZINE MANAGEMENT DEVICE, DISC DEVICE, AND MAGAZINE MANAGEMENT SYSTEM

PANASONIC INTELLECTUAL PR...

1. A magazine management device that stores a plurality of magazines where a plurality of optical discs is housed, the magazine management device comprising:a case that supports the plurality of magazines;
a plurality of partitions that divides the case so as to form a plurality of regions in which the plurality of magazines can be stored one by one;
a radio identifier provided to a magazine from the plurality of magazines;
at least one antenna operably connected to the case that transmits a first radio wave to the radio identifier and receives a second radio wave carrying a response transmitted from the radio identifier; and
an arithmetic processor operably connected to the at least one antenna and that receives information obtained from the response carried by the radio wave received by the at least one antenna,
wherein
the at least one antenna includes a first antenna and a second antenna disposed on each region from the plurality of regions such that each region includes at least two antennas, and
the first antenna attempts to transmit the first radio wave to the radio identifier and, when the first antenna does not receive the second radio wave, the second antenna transmits the first radio wave to the radio identifier.

US Pat. No. 10,249,336

ARCHITECTURE FOR METAL-INSULATOR-METAL NEAR-FIELD TRANSDUCER FOR HEAT-ASSISTED MAGNETIC RECORDING

Western Digital Technolog...

1. A heat-assisted magnetic recording (HAMR) device, comprising:a waveguide; and
a near-field transducer (NFT) coupled to the waveguide in a direct-fire configuration, the NFT comprising an insulator core encased in a metal portion, the metal portion comprising a plasmonic metal,
wherein:
the insulator core comprises a rectangular portion and a tapered portion, and
the rectangular portion is between the waveguide and the tapered portion.

US Pat. No. 10,249,335

COMPOSITE HAMR MEDIA STRUCTURE FOR HIGH AREAL DENSITY

Seagate Technology LLC, ...

1. An apparatus comprising a data storage medium having an exchange coupled composite (ECC) structure comprising a coupling layer (ECL) contacting and disposed between a storage layer and a write layer, the storage layer having a lower Curie temperature and a higher anisotropy than the respective ECL and write layers, the ECL coupling the write layer to the storage layer with a coupling strength from 0.1 Jex/Jo to 0.6 Jex/Jo.

US Pat. No. 10,249,334

SLIDER AIR-BEARING SURFACE DESIGNS WITH SIDE PARTICLE-TRAPPING STRUCTURES

Western Digital Technolog...

1. A slider, comprising:a leading edge;
a trailing edge;
a leading-edge structure located between the leading edge and the trailing edge;
a vertical structure located between the leading-edge structure and the trailing edge, the vertical structure having a leading-edge-facing surface and a side-edge-facing surface, the vertical structure having a base at a first level of an air-bearing surface (ABS) of the slider; and
a particle-trapping structure adjacent to the base of the vertical structure, the particle-trapping structure having a first portion adjacent to the leading-edge-facing surface and a second portion adjacent to the side-edge-facing surface, wherein the particle-trapping structure comprises at least one cavity extending below the first level when the ABS is oriented upward.

US Pat. No. 10,249,333

SINGLE RH LAYER OPTICAL FIELD ENHANCER WITH PRE-FOCUSING STRUCTURES

Headway Technologies, Inc...

1. A TAMR (Thermally Assisted Magnetic Recording) write head comprising:a magnetic writer structure having a tapered main write pole section emerging at a distal ABS (Air-Bearing Surface) and configured to write on a magnetic recording medium when said magnetic recording medium has been properly activated thermally by plasmon near-field energy; and
a structure comprising small, weakly plasmonic elements, wherein said elements are not subject to thermal deformations and recessions from said ABS yet are an efficient source of said plasmon near-field energy when excited by pre-focused optical energy provided by a system comprising:
a waveguide, having a horizontally (x-y plane) tapered dielectric waveguide core, formed adjacent to and aligned along (y-direction) said main write pole and configured for directing pre-focused optical energy at a configuration of weakly plasmonic patterned layers comprising an upper layer and a lower layer; wherein
a stratified, highly plasmonic film is formed between said waveguide and said tapered main pole and is separated from said main pole by a weakly plasmonic layer that extends distally to contact said upper layer of said configuration of weakly plasmonic patterned layers and wherein said stratified, highly plasmonic film is separated from said waveguide core by a dielectric layer, wherein a distal edge of said stratified, highly plasmonic film terminates at a distance from said ABS and is thereby recessed from said ABS; wherein
said configuration of weakly plasmonic patterned layers formed between said distal edge of said stratified film and said ABS includes said upper layer and, beneath said upper layer is a lower layer contacting said upper layer and wherein said distal edge of said stratified highly plasmonic film contacts a proximal edge of said upper layer of said patterned configuration; wherein
a downward sloping distal face of said waveguide conformally abuts a complementary sloped edge of a waveguide blocker formed of weakly plasmonic material; and wherein
said downward sloping distal face of said waveguide is separated from said complementary sloped edge of said waveguide blocker by a uniform layer of dielectric material; and
a pair of optical side shields formed of weakly plasmonic material is laterally and symmetrically disposed to either side of said waveguide, and wherein;
said lower layer of said configuration of weakly plasmonic patterned layers is an optical field enhancer (OFE) with a distally emerging peg, said OFE having a patterned shape that coincides with a shape of said pre-focused electromagnetic field.

US Pat. No. 10,249,332

MICROWAVE-ASSISTED MAGNETIC RECORDING APPARATUS AND METHOD

Seagate Technology LLC, ...

1. An apparatus, comprising:a magnetic recording medium having a recording surface comprising a first recording layer having a first ferromagnetic resonant frequency and a second recording layer having a second ferromagnetic resonant frequency, the first recording layer configured for storing user data and the second recording layer configured for storing servo data; and
a recording head arrangement configured for microwave-assisted magnetic recording (MAMR) and writing user data to the first recording layer, the recording head arrangement comprising:
a write pole configured to generate a write magnetic field;
a write-assist arrangement proximate the write pole, the write-assist arrangement configured to generate a radiofrequency assist magnetic field at a frequency that corresponds to the first ferromagnetic resonant frequency; and
a reader configured to read combined signals from the first and second recording layers.

US Pat. No. 10,249,331

METHOD OF MANUFACTURING A WIRING STRUCTURE OF A HEAD SUSPENSION

NHK SPRING CO., LTD., Ka...

1. A method of manufacturing a wiring structure of a head suspension including a flexure that supports a head used to write and read data to and from a recording medium and is attached to a load beam applying load onto the head, the wiring structure comprising write wiring and read wiring formed on the flexure and connected to the head, each having wires of opposite polarities and a stacked interleaved part provided at least for the write wiring, the stacked interleaved part including segments electrically connected to the respective wires of the write wiring at both ends in each segment, the segments stacked on and facing the wires of the write wiring through an intermediate insulating layer so that the facing wire and segment have opposite polarities to interleave at least the write wiring at the stacked interleaved part, the method comprising:a wiring step of forming the wires of the opposite polarities of the write wiring on a base insulating layer and forming a respective wire side-arm branching from each of the wires formed on the base insulating layer;
an insulating layer forming step of forming the intermediate insulating layer on the wires and the wire side-arms and forming the conductors on the wires and the wire side-arms, respectively so that the conductors pass through the intermediate insulating layer and are exposed at a surface of the electrical insulating layer; and
a stacked interleaved part forming step of forming segments of opposite polarities of the stacked interleaved part on the electrical insulating layer so that each segment spans between the conductors on the wire side-arm and the wire having a same polarity and electrically connected to said conductors.

US Pat. No. 10,249,330

METHODS AND SYSTEMS FOR DETECTING ESD EVENTS IN CABLED DEVICES

International Business Ma...

1. An audit device, comprising:a substrate;
at least one test element coupled to the substrate;
a connector configured to couple the at least one test element to leads of a cable; and
a probe for detecting voltage across and/or current through the at least one test element,
wherein one test element is coupled to a group of leads of the connector, the group of leads comprising a plurality of positive polarity leads and a plurality of negative polarity leads,
wherein all positive polarity leads of the group of leads are electrically coupled together on the substrate, and
wherein all negative polarity leads of the group of leads are electrically coupled together on the substrate,
such that the test element is coupled across the positive and the negative polarity leads of the group of leads of the connector,
wherein the test element is coupled across pairs of leads of the cable when the cable is coupled to the connector,
wherein the at least one test element is a resistor or a resistance-inductance-capacitance (RLC) circuit having an equivalent circuit value to a device under test, and
wherein the at least one test element is tunable such that the at least one test element is capable of matching the equivalent circuit value in a predetermined frequency range.

US Pat. No. 10,249,329

CURRENT-PERPENDICULAR-TO-THE-PLANE (CPP) MAGNETORESISTIVE (MR) SENSOR WITH WEDGE SHAPED FREE LAYER

Western Digital Technolog...

1. A magnetoresistive (MR) sensor structure for detecting magnetized regions of a magnetic recording medium, the structure comprising:a substrate; and
a magnetoresistive sensor on the substrate and comprising a stack of layers including a ferromagnetic free layer consisting of a single layer of ferromagnetic material or multiple layers of ferromagnetic material, the free layer having a front edge for facing the recording medium and a back edge recessed from the front edge, wherein the front edge is substantially parallel to the back edge and wherein the free layer has a thickness at the back edge greater than its thickness at the front edge.

US Pat. No. 10,249,328

WRITE COIL COOLING ARRANGEMENT AT AIR BEARING SURFACE

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider configured to interact with a magnetic recording medium and comprising an air bearing surface (ABS);
a writer provided on the slider and comprising a write coil having a plurality of coil turns, a planar configuration, and a media-facing surface situated at the ABS, each of the turns having a thinned section that extends along the ABS and a thickened section spaced away from the ABS; and
a plurality of cooling arms projecting laterally from peripheral surfaces of the write coil, each of the plurality of cooling arms extending along the ABS;
wherein the media-facing surface of the write coil, including at least the thinned section of an outermost turn of the coil turns, and the cooling arms are exposed in a plane of the ABS to facilitate cooling of the write coil at the ABS.

US Pat. No. 10,249,327

DISK DEVICE, CONTROLLER CIRCUIT, AND CONTROL METHOD

KABUSHIKI KAISHA TOSHIBA,...

1. A disk device comprising:a recording medium on which data is recorded;
a decoding circuit configured to decode data read from the recording medium; and
a control circuit configured to cause first data associated with a target sector referenced in a read request to be read from a target track of the recording medium, second data associated with a non-target sector that is not referenced in the read request to be read from the recording medium after the first data is read from the recording medium, and decoding of the first data to be completed by the decoding circuit after the second data is read from the recording medium, wherein
the decoding circuit is configured to execute a first decoding process on the first data based on data from the target sector and not on data from any other sector of the target track and a second decoding process on the first data based on data from each sector of the target track, and
the control circuit is configured to perform the second decoding process on the first data when the first decoding process fails to decode the first data.

US Pat. No. 10,249,326

HEAT-ASSISTED MAGNETIC RECORDING HEAD INCLUDING A WAVEGUIDE WITH DIELECTRIC CAVITY TO REDUCE OPTICAL FEEDBACK

Seagate Technology LLC, ...

1. A recording head comprising:a near-field transducer proximate a media-facing surface of the recording head; and
a waveguide core that overlaps and delivers light from a light source to the near-field transducer along a light propagation direction, the waveguide core comprising a dielectric cavity proximate the near-field transducer, the near-field transducer being located outside of the waveguide core within a cladding material that is located on a side of the waveguide core, the cladding material having a lower refractive index than that of the waveguide core, the dielectric cavity comprising a length along the light propagation direction such that light will propagate through the dielectric cavity, the dielectric cavity filled with the cladding material and reducing optical feedback to the light source.

US Pat. No. 10,249,325

PITCH DETECTION ALGORITHM BASED ON PWVT OF TEAGER ENERGY OPERATOR

OmniSpeech LLC, College ...

1. A method of a pitch detection comprising:sampling a signal to generate a first discrete time signal;
applying a Teager Energy Operator (TEO) to the first discrete time signal to generate a second discrete time signal;
generating a first complex valued signal from the first discrete time signal;
generating a second complex valued signal from the second discrete time signal;
computing a Pseudo Weigner Ville Transformation (PWVT) on the first complex valued signal to generate a first spectral representation of the signal;
computing a PWVT on the second complex valued signal to generate a second spectral representation of the signal;
generating a combined spectral representation from the first spectral representation and the second spectral representation;
computing, to generate a pitch candidate, a harmonic summation on at least one of the combined spectral representation and the first spectral representation; and
deciding the pitch candidate as a pitch value if the pitch candidate is larger than a threshold.

US Pat. No. 10,249,324

SOUND PROCESSING BASED ON A CONFIDENCE MEASURE

Cochlear Limited, Macqua...

1. A method, comprising:receiving a plurality of input signals each representing a spectral component of one or more sounds;
determining a speech importance of each of a plurality of the spectral components;
determining confidence measures for each of a plurality of noise-component estimates generated for each of the plurality of spectral components;
based on the speech importance of each of the plurality of the spectral components and based on the confidence measures generated for each of a plurality of noise-component estimates, selecting one or more of the input signals as selected input signals; and
processing the selected input signals to generate stimulation for delivery to a recipient of a hearing prosthesis.

US Pat. No. 10,249,323

VOICE ACTIVITY DETECTION FOR COMMUNICATION HEADSET

BOSE CORPORATION, Framin...

1. A method of determining that a headset user is speaking, the method comprising:receiving a first signal from a first microphone;
receiving a second signal from a second microphone;
adding the first signal and the second signal, by a processor, to generate a principal signal;
subtracting, by the processor, one of the first signal and the second signal from the other of the first signal and the second signal to generate a reference signal;
limiting a rate of change, by the processor, of at least one of the principal signal or the reference signal by a time constant;
comparing the principal signal to the reference signal, by the processor, to determine whether the principal signal exceeds the reference signal by a threshold amount;
selectively indicating that the user is speaking, responsive to determining that the principal signal exceeds the reference signal by the threshold amount; and
activating a voice operated control in response to selectively indicating that the user is speaking.

US Pat. No. 10,249,322

AUDIO PROCESSING DEVICES AND AUDIO PROCESSING METHODS

INTEL IP CORPORATION, Sa...

1. An audio processing device comprising:an energy distribution determiner configured to determine an energy distribution of a sound and further configured to determine signal subband centroid values of the sound;
an acoustical environment determiner configured to compare the signal subband centroid values of the sound to a pre-determined static threshold and determine that the sound includes a sound caused by the acoustical environment when the subband signal centroid values are below the pre-determined static threshold; and
a noise reduction circuit configured to reduce the sound caused by the acoustical environment in response to the comparison of the signal subband centroid values being below the pre-determined static threshold.

US Pat. No. 10,249,321

SOUND RATE MODIFICATION

Adobe Inc., San Jose, CA...

1. A method implemented by at least one computing device, the method comprising:receiving, as a user input, by the at least one computing device, an indication of an amount of time in which sound data is to be output, the sound data including a waveform representation and a plurality of portions, the indicated amount of time being different from an unmodified amount of time for playback of the sound data;
identifying, by the at least one computing device, at least one active portion and at least one inactive portion of the plurality of portions of the sound data based on spectral characteristics of the sound data, the at least one active portion containing multiple different units of speech, the at least one inactive portion corresponding to pauses in speech;
modifying, by the at least one computing device, the sound data to be output in the indicated amount of time using a set of sound rate rules generated to capture sound rate characteristics of units of speech in a natural language model by:
calculating different relative rates at which the multiple different units of speech are to be output, respectively, based on the set of sound rate rules and the indicated amount of time,
applying a first calculated rate to a first unit of speech in the active portion to cause the first unit of speech to be output at the first calculated rate, and
applying a second different calculated rate to a second unit of speech in the active portion to cause the second unit of speech to be output at the second different calculated rate; and
outputting, by the at least one computing device, the sound data as modified by the first calculated rate and the second different calculated rate in the indicated amount of time.

US Pat. No. 10,249,320

NORMALIZING THE SPEAKING VOLUME OF PARTICIPANTS IN MEETINGS

International Business Ma...

1. A computer-implemented method, comprising:collecting speaking volume samples from multiple participants of a group event, wherein said speaking volume samples are derived from one or more microphones being used during the group event, and wherein said collecting comprises collecting said speaking volume samples from the multiple participants of the group event periodically during the group event;
comparing said speaking volume samples to a predetermined volume level, wherein said predetermined volume level is based on one or more volume models;
determining which of the one or more microphones is being used by which of the multiple participants during the group event;
automatically amplifying a broadcast volume of each audio output device being used in the group event during periods of audio input attributed to each microphone determined as being used by the participants attributed to a speaking volume sample that is below the predetermined volume level by more than a given threshold; and
automatically reducing a broadcast volume of each audio output device being used in the group event during periods of audio input attributed to each microphone determined as being used by the participants attributed to a speaking volume sample that exceeds the predetermined volume level by more than the given threshold.

US Pat. No. 10,249,319

METHODS AND APPARATUS TO REDUCE NOISE FROM HARMONIC NOISE SOURCES

The Nielsen Company (US),...

1. An apparatus to reduce harmonic noise, the apparatus comprising:a contour tracer to:
determine a first point representing a comparatively large amplitude for a frequency value in an audio sample;
generate a first contour trace of other points having amplitude, frequency and phase values within specified thresholds from the first point, the points of the first contour trace occurring in succession within a specified number of frames from each other or from the first point; and
generate a second contour trace of points having amplitude, frequency, and phase values within thresholds of a second point representing a comparatively large amplitude for a frequency value in the audio sample, the points of the second contour trace occurring in succession within a specified number of frames from each other or from the second point;
a parameter calculator to calculate a first parameter for the first contour trace and a second parameter for the second contour trace;
a classifier to determine if the first and second contour traces represent outliers based on the first and second parameters; and
a subtractor to, in response to determining the first or second contour to be an outlier contour trace, remove the outlier contour trace from the audio sample.

US Pat. No. 10,249,318

SPEECH SIGNAL PROCESSING CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A speech-signal-processing-circuit configured to receive a time-frequency-domain-reference-speech-signal and a time-frequency-domain-degraded-speech-signal,wherein each of the time-frequency-domain-reference-speech-signal and the time-frequency-domain-degraded-speech-signal comprises a plurality of frames of data,
wherein:
the time-frequency-domain-reference-speech-signal is in the time-frequency domain and comprises:
an upper-band-reference-component with frequencies that are greater than a frequency-threshold-value; and
a lower-band-reference-component with frequencies that are less than the frequency-threshold-value;
the time-frequency-domain-degraded-speech-signal is in the time-frequency domain and comprises:
an upper-band-degraded-component with frequencies that are greater than the frequency-threshold-value; and
a lower-band-degraded-component with frequencies that are less than the frequency-threshold-value;the speech-signal-processing-circuit comprises:a disturbance calculator configured to determine one or more spectral balance ratio (SBR) features based on the time-frequency-domain-reference-speech-signal and the time-frequency-domain-degraded-speech-signal by:
for each of a plurality of frames:
determining a reference-ratio based on the ratio of the upper-band-reference-component to the lower-band-reference-component;
determining a degraded-ratio based on the ratio of the upper-band-degraded-component to the lower-band-degraded-component; and
determining a spectral-balance-ratio based on the ratio of the reference-ratio to the degraded-ratio; and
determining the one or more SBR-features based on the spectral-balance-ratio for the plurality of frames; and
a score-evaluation-block configured to determine an output-score for the degraded-speech-signal based on the SBR-features;wherein the signal-processing-circuit includes an output configured to pass the output-score for the degraded-speech-signal to a set of quality control and/or monitoring circuitry.

US Pat. No. 10,249,317

ESTIMATING NOISE OF AN AUDIO SIGNAL IN A LOG2-DOMAIN

Fraunhofer-Gesellschaft z...

1. A method for estimating noise in an audio signal, the method comprising:determining an energy value for the audio signal;
converting the energy value into the log 2-domain, and
estimating a noise level for the audio signal based on the converted energy value directly in the log 2-domain,
wherein the energy value is converted into the log 2-domain as follows:

?x? floor (x),
En_log energy value of band n in the log 2-domain,
En_lin energy value of band n in the linear domain,
N quantization resolution.

US Pat. No. 10,249,316

ROBUST NOISE ESTIMATION FOR SPEECH ENHANCEMENT IN VARIABLE NOISE CONDITIONS

Continental Automotive Sy...

1. An apparatus comprising:a linear predictive coding voice activity detector configured to:
low pass filter an input signal;
apply a pre-emphasis to high frequency content of the input signal so that a high frequency spectrum structure of the low-pass-filtered input signal is emphasized;
calculate a sequence of auto-correlations of the pre-emphasized low-pass-filtered input signal;
apply a first higher order linear predictive coding (“LPC”) analysis and calculate a longer set of LPC coefficients;
apply a second higher order LPC analysis and calculate a shorter set of LPC coefficients;
cast the longer set of LPC coefficients and the shorter set of LPC coefficients to the spectral domain;
energy normalize the spectral domain representations of the longer set of LPC coefficients and the shorter set of LPC coefficients;
determine a log spectrum distance between the energy normalized spectral domain representations of the longer set of LPC coefficients and the shorter set of LPC coefficients;
determine whether a frame of the input signal is noise based on whether the determined log spectrum distance between the energy normalized spectral domain representations of the longer set of LPC coefficients and the shorter set of LPC coefficients is less than a noise threshold; and
when the frame of the input signal is determined not to be noise, determining whether the frame of the input signal is speech based on whether the determined log spectrum distance between the energy normalized spectral domain representations of the longer set of LPC coefficients and the shorter set of LPC coefficients is greater than a speech threshold; and
a noise suppressor that accepts as inputs both the input signal to the linear predictive coding voice activity detector and a determination from the linear predictive coding voice activity detector as to whether the frame includes noise or speech, and wherein the noise suppressor generates, based on both of those inputs, a noise-suppressed signal that quickly responds to transient noise signals.

US Pat. No. 10,249,315

METHOD AND APPARATUS FOR DETECTING CORRECTNESS OF PITCH PERIOD

HUAWEI TECHNOLOGIES CO., ...

1. A method for detecting correctness of a pitch period for encoding, comprising:receiving, at a receiver of a detecting apparatus, an input signal comprising a speech signal or an audio signal;
determining, by a processor of the detecting apparatus, according to an initial pitch period of the input signal in a time domain, a pitch frequency bin of the input signal, wherein the initial pitch period is obtained by performing open-loop detection on the input signal;
determining, by the processor, based on an amplitude spectrum of the input signal in a frequency domain, a pitch period correctness decision parameter of the input signal associated with the pitch frequency bin;
determining, by the processor, correctness of the initial pitch period according to the pitch period correctness decision parameter;
performing, by the processor, short-pitch detection to obtain a short pitch period; and
determining, by the processor, according to the correctness of the initial pitch period in combination with one or more other conditions, whether to replace the initial pitch period with the short pitch period,
wherein the pitch period correctness decision parameter comprises a spectral difference parameter, an average spectral amplitude parameter, and a difference-to-amplitude ratio parameter,
wherein the spectral difference parameter is a weighted and smoothed value of a sum of spectral differences of predetermined quantity of frequency bins on two sides of the pitch frequency bin,
wherein the average spectral amplitude parameter is a weighted and smoothed value of an average of spectral amplitudes of the predetermined quantity of frequency bins on the two sides of the pitch frequency bin, and
wherein the difference-to-amplitude ratio parameter is a ratio of the sum of the spectral differences of the predetermined quantity of frequency bins on the two sides of the pitch frequency bin to the average of the spectral amplitudes of the predetermined quantity of frequency bins on the two sides of the pitch frequency bin.

US Pat. No. 10,249,314

VOICE CONVERSION SYSTEM AND METHOD WITH VARIANCE AND SPECTRUM COMPENSATION

OBEN, INC., Pasadena, CA...

1. A voice conversion system comprising:a microphone for recording source speech data;
a neural network for generating estimated target speech data based on the source speech data;
a global variance correction module configured to scale and shift the estimated target speech based on (i) a mean and standard deviation of the source speech data, and further based on (ii) a mean and standard deviation of the estimated target speech data;
a modulation spectrum correction module configured to apply a plurality of filters to the estimated target speech data after being scaled and shifted by the global variance correction module; wherein each filter of the plurality of filters is based on two trajectories comprising (i) a first trajectory consisting of a single feature extracted from a plurality of frames of target training speech data recorded from a target speaker, and (ii) a second trajectory consisting of a single feature extracted from a plurality frames of target training speech data generated by said neural network;
a waveform generator configured to generate a target voice signal based on the estimated target speech data from the modulation spectrum correction module; and
a speaker configured to play the target voice signal.

US Pat. No. 10,249,313

ADAPTIVE BANDWIDTH EXTENSION AND APPARATUS FOR THE SAME

HUAWEI TECHNOLOGIES CO., ...

1. A method of decoding an encoded audio bitstream at a decoder, comprising:decoding the audio bitstream to produce a decoded low band audio signal and generate a low band excitation spectrum corresponding to a low frequency band;
determining a sub-band area from the low frequency band using at least one parameter which indicates energy distribution information of a spectral envelope of the decoded low band audio signal; wherein a starting point of the sub-band area is corresponding to the highest spectral formant energy within a searching range, and wherein the searching range is a frequency region within the low frequency band;
generating a high band excitation spectrum for a high frequency band by copying a sub-band excitation spectrum from the determined sub-band area to the high frequency band;
generating an extended high band audio signal using the generated high band excitation spectrum; and
synthesizing an audio output signal having an extended frequency bandwidth according to the extended high band audio signal and the decoded low band audio signal.

US Pat. No. 10,249,312

QUANTIZATION OF SPATIAL VECTORS

Qualcomm Incorporated, S...

1. A device configured for processing coded audio, the device comprising:a memory configured to store a first set of one or more audio signals corresponding to a time interval; and
one or more processors electronically coupled to the memory, the one or more processors configured to:
obtain, from a coded audio bitstream, an object-based or channel-based representation of each audio signal in the first set of audio signals, wherein in the channel-based representation, each audio signal in the first set of audio signals corresponds to a respective loudspeaker of a source loudspeaker setup;
obtain, from the coded audio bitstream, data representing quantized versions of a set of one or more spatial vectors, wherein:
each respective spatial vector in the set of spatial vectors corresponds to a different respective audio signal in the first set of audio signals,
each of the spatial vectors is in a Higher-Order Ambisonics (HOA) domain and is computed based on a set of source loudspeaker locations, and
for each of the source loudspeaker locations, the spatial vector of the set of spatial vectors that corresponds to an Nth source loudspeaker locations is equivalent to a transpose of a matrix resulting from a multiplication of a first matrix, a second matrix, and a third matrix, the first matrix consisting of a single respective row of elements equivalent in number of the number of loudspeaker positions in the set of source loudspeaker positions, the Nth element of the respective row of elements being equivalent to one and elements other than the Nth element of the respective row being equivalent to 0, the second matrix being an inverse of a matrix resulting from a multiplication of a rendering matrix and the transpose of the rendering matrix, the third matrix being equivalent to the rendering matrix, and wherein the rendering matrix is based on the set of source loudspeaker locations;
inverse quantize the quantized versions of the spatial vectors;
convert the first set of audio signals and the set of spatial vectors to a set of one or more HOA coefficients describing a sound field during the time interval; and
apply a rendering format to the set of HOA coefficients to generate a second set of one or more audio signals, wherein each respective audio signal of the second set of audio signals corresponds to a respective loudspeaker in a set of local loudspeakers.

US Pat. No. 10,249,311

CONCEPT FOR AUDIO ENCODING AND DECODING FOR AUDIO CHANNELS AND AUDIO OBJECTS

Fraunhofer-Gesellschaft z...

1. An audio encoder for encoding audio input data to acquire audio output data comprising:an input interface that receives a plurality of audio channels, a plurality of audio objects and metadata related to one or more of the plurality of audio objects;
a mixer that mixes the plurality of audio objects and the plurality of audio channels received by the input interface to acquire a plurality of pre-mixed audio channels, each pre-mixed audio channel comprising audio data of an audio channel and audio data of at least one audio object;
a core encoder that core encodes core encoder input data; and
a metadata compressor that compresses the metadata related to the one or more of the plurality of audio objects,
wherein the audio encoder is configured to operate in either a first mode or a second mode of a group of at least two modes comprising the first mode, in which the core encoder core encodes the plurality of audio channels received by the input interface and the plurality of audio objects received by the input interface as the core encoder input data, and the second mode, in which the core encoder receives, as the core encoder input data, the plurality of pre-mixed audio channels generated by the mixer and core encodes the plurality of pre-mixed audio channels generated by the mixer; and
an output interface for providing an output signal as the audio output data,
the output signal comprising, when the audio encoder is in the first mode, encoded audio channels and encoded audio objects as an output of the core encoder (300) and the compressed metadata, and
the output signal comprising, when the audio encoder is in the second mode, the output of the core encoder without any metadata related to the at least one audio object included in a pre-mixed audio channel of the plurality of pre-mixed audio channels.

US Pat. No. 10,249,310

AUDIO DECODER AND METHOD FOR PROVIDING A DECODED AUDIO INFORMATION USING AN ERROR CONCEALMENT MODIFYING A TIME DOMAIN EXCITATION SIGNAL

Fraunhofer-Gesellschaft z...

1. An audio decoder for providing a decoded audio information on the basis of an encoded audio information comprising a series of audio frames, the audio decoder comprising:an error concealment configured unit to provide error concealment audio information for concealing a loss of an audio frame,
wherein the error concealment unit is configured to modify a time domain excitation signal acquired for one or more audio frames preceding a lost audio frame to acquire the error concealment audio information;
wherein the error concealment unit is configured to acquire information about an intensity of a deterministic signal component in one or more of the audio frames preceding the lost audio frame, and
wherein the error concealment unit is configured to compare the information about an intensity of the deterministic signal component in one or more of the audio frames preceding the lost audio frame with a threshold value to decide whether to input a deterministic time domain excitation signal with the addition of a noise like time domain excitation signal into an LPC synthesis; or whether to input only a noise time domain excitation signal into the LPC synthesis.

US Pat. No. 10,249,309

AUDIO DECODER AND METHOD FOR PROVIDING A DECODED AUDIO INFORMATION USING AN ERROR CONCEALMENT MODIFYING A TIME DOMAIN EXCITATION SIGNAL

Fraunhofer-Gesellschaft z...

1. An audio decoder for providing a decoded audio information on the basis of an encoded audio information, the audio decoder comprising:a decoder core; and
an error concealment unit configured to provide an error concealment audio information for concealing a loss of an audio frame,
wherein the error concealment unit is configured to modify a time domain excitation signal acquired for one or more audio frames preceding a lost audio frame, in order to acquire the error concealment audio information;
wherein the error concealment unit is configured to adjust the speed used to gradually reduce a gain applied to scale the time domain excitation signal acquired for one or more audio frames preceding a lost audio frame, or the one or more copies thereof, in dependence on a length of a pitch period of the time domain excitation signal, such that a deterministic component of time domain excitation signal input into an LPC synthesis is faded out faster for signals comprising a shorter length of the pitch period when compared to signals comprising a larger length of the pitch period;
wherein the audio decoder provides the decoded audio information in dependence on the error concealment audio information.

US Pat. No. 10,249,308

WEIGHT FUNCTION DETERMINATION DEVICE AND METHOD FOR QUANTIZING LINEAR PREDICTION CODING COEFFICIENT

SAMSUNG ELECTRONICS CO., ...

1. A method of encoding a linear predictive coding (LPC) coefficient in an encoding device, the method comprising:obtaining, performed by at least one processor, a line spectral frequency (LSF) coefficient from the linear predictive coding (LPC) coefficient of a subframe in an audio signal;
obtaining a first weighting parameter of the subframe based on a spectral magnitude of the LSF coefficient;
obtaining a second weighting parameter of the subframe based on position information of adjacent LSF coefficients;
determining a weighting parameter of the subframe from a plurality of weighting parameters including the first weighting parameter of the subframe and the second weighting parameter of the subframe; and
encoding the LSF coefficient based on the weighting parameter of the subframe,
wherein the first weighting parameter is obtained based on a maximum value of a magnitude of a spectral bin corresponding to a frequency of the LSF coefficient and a magnitude of at least one spectral bin neighboring the spectral bin.

US Pat. No. 10,249,307

AUDIO DECODING USING INTERMEDIATE SAMPLING RATE

Qualcomm Incorporated, S...

1. An apparatus comprising:a receiver configured to receive a first frame of a mid channel audio bitstream from an encoder; and
a decoder configured to:
determine a first bandwidth of the first frame based on first coding information associated with the first frame, the first coding information indicating a first coding mode used by the encoder to encode the first frame, the first bandwidth based on the first coding mode;
determine an intermediate sampling rate based on a Nyquist sampling rate of the first bandwidth;
decode an encoded mid channel of the first frame to generate a decoded mid channel;
perform a frequency-domain upmix operation on the decoded mid channel to generate a left frequency-domain low-band signal and a right frequency-domain low-band signal;
perform a frequency-to-time domain conversion operation on the left frequency-domain low-band signal to generate a left time-domain low-band signal having the intermediate sampling rate;
perform a frequency-to-time domain conversion operation on the right frequency-domain low-band signal to generate a right time-domain low-band signal having the intermediate sampling rate;
generate, based at least on the encoded mid channel, a left time-domain high-band signal having the intermediate sampling rate and a right time-domain high-band signal having the intermediate sampling rate;
generate a left signal based at least on combining the left time-domain low-band signal and the left time-domain high-band signal;
generate a right signal based at least on combining the right time-domain low-band signal and the right time-domain high-band signal; and
generate a left resampled signal having an output sampling rate of the decoder and a right resampled signal having the output sampling rate, the left resampled signal based at least in part on the left signal, and the right resampled signal based at least in part on the right signal,
wherein the intermediate sampling rate is equal to the Nyquist sampling rate if the Nyquist sampling rate is less than the output sampling rate, and wherein the intermediate sampling rate is equal to the output sampling rate if the output sampling rate is less than or equal to the Nyquist sampling rate.

US Pat. No. 10,249,306

SPEAKER IDENTIFICATION DEVICE, SPEAKER IDENTIFICATION METHOD, AND RECORDING MEDIUM

NEC CORPORATION, Tokyo (...

1. A speaker identification device comprising:a primary speaker identification unit which computes, for each registered speaker stored in advance, a score that indicates similarity between input speech and speech of the registered speakers;
a similar speaker selection unit which selects a plurality of the registered speakers as similar speakers according to height of the scores;
a learning unit which creates a plurality of classifiers, each classifier corresponding to a different speaker of similar speakers,
wherein for each classifier, the classifier corresponds speech of the different speaker to which the classifier corresponds as a positive instance and speech of other speakers of the similar speakers as negative instances; and
a secondary speaker identification unit which computes, for each classifier, a score of the classifier with respect to the input speech and outputs an identification result.

US Pat. No. 10,249,305

PERMUTATION INVARIANT TRAINING FOR TALKER-INDEPENDENT MULTI-TALKER SPEECH SEPARATION

Microsoft Technology Lice...

1. A method of separating two or more audio source signals from a first mixed signal having audio source signals and noise source signals, the method comprising:generating output layers from a second mixed signal, the output layers being estimates of audio source signals in the second mixed signal;
generating a plurality of labels, wherein a total number of the plurality of labels is equal to a total number of the output layers;
iteratively assigning the plurality of labels to the output layers for possible combinations of labels and output layers to create a set of possible assignments, each possible assignment in the set of possible assignments corresponding to a combination of labels and output layers;
obtaining a plurality of spatially filtered signals, wherein a total number of spatially filtered signals is equal to the total number of the plurality of labels;
determining assignment error scores for each of the set of possible assignments, the assignment error scores determined based at least in part on a difference between labels of the plurality of labels for respective output layers for a respective possible assignment and the plurality of spatially filtered signals;
determining an assignment order of labels to be assigned to the output layers, individual labels being associated with individual audio source signals and the assignment order being based, at least in part, on a minimum total deviation score between individual output layers and the individual audio source signals, wherein the minimum total deviation score is a lowest assignment error score of the assignment error scores;
generating a set of masks by iteratively optimizing model parameters of the model to minimize the minimum total deviation score of the determined assignment order; and
generating the two or more audio source signals from the first mixed signal by using the set of masks, the source of the two or more audio source signals being different from a source of the audio source signals in the second mixed signal.

US Pat. No. 10,249,304

METHOD AND SYSTEM FOR USING CONVERSATIONAL BIOMETRICS AND SPEAKER IDENTIFICATION/VERIFICATION TO FILTER VOICE STREAMS

INTERNATIONAL BUSINESS MA...

1. A method implemented in a computing system, the method comprising:extracting a plurality of audio streams from a communication corresponding to a plurality of participants;
matching portions of the communication in the plurality of audio streams to voice prints which correspond to identified participants within the communication; and
adapting a speaker model of the voice prints after successfully matching the portions of the communication in the plurality of audio streams to the voice prints, wherein adapting the speaker model includes capturing long-term voice changes of the identified participants in the voice prints used for the matching.

US Pat. No. 10,249,303

METHODS AND SYSTEMS FOR DETECTING AND PROCESSING SPEECH SIGNALS

Google LLC, Mountain Vie...

1. A computer-implemented method comprising:receiving, by a computing device that (i) is operating in a low power mode, (ii) is configured to exit the low power mode upon determining that a particular hotword has likely been spoken, and (iii) is in proximity of other computing devices that are each also configured to exit the low power mode upon determining that the particular hotword has been spoken, audio data corresponding to a user uttering the particular hotword;
based on an estimated position of the user in relation to the computing device, determining, by the computing device, to remain operating in the low power mode despite determining that the particular hotword has likely been spoken.

US Pat. No. 10,249,302

METHOD AND DEVICE FOR RECOGNIZING TIME INFORMATION FROM VOICE INFORMATION

TENCENT TECHNOLOGY (SHENZ...

1. A method for recognizing time information from speech data, comprising the following steps:at a device having one or more processors and memory:
obtaining text information corresponding to speech data;
identifying at least a first time feature contained in the speech data based on the text information;
searching within a respective configuration file corresponding to the first time feature to obtain a corresponding time identifier for the first time feature;
assigning the corresponding time identifier to a field that is in intermediate time data and that corresponds to the respective configuration file in which the first time feature is located, the intermediate time data comprising multiple fields, and each field corresponding to a respective configuration file of a plurality of configuration files, each of the plurality of configuration files corresponding to a respective category related to time;
obtaining a current time in accordance with a determination that a day-of-week field in the intermediate time data has an assigned value, and that a this-week/next-week field does not have an assigned value;
determining whether a time identifier of the day-of-week field in the intermediate time data is later than a day-of-week value of the current time;
in accordance with a determination that the time identifier of the day-of-week field in the intermediate time data is later than the day-of-week value of the current time, setting the value of the this-week/next-week field in the intermediate time data as this week;
in accordance with a determination that the time identifier of the day-of-week field in the intermediate time data is earlier than the day-of-week value of the current time, setting the value of the this-week/next-week field in the intermediate time data as next week;
obtaining, according to content of one or more fields in the intermediate time data, system time data corresponding to the time information contained in the speech data; and
generating a calendar reminder at the device according to the system time data corresponding to the time information contained in the speech data.

US Pat. No. 10,249,301

METHOD AND SYSTEM FOR SPEECH RECOGNITION PROCESSING

Alibaba Group Holding Lim...

1. A speech recognition system, comprising:an instant messaging server (IMS) configured to:
assign a unique identifier to speech information received from a sending end to serve as a speech ID;
send the speech information to a receiving end; and
deliver the speech information to a speech recognition module, a speech recognition server, or a speech recognition server cluster;
the speech recognition module, the speech recognition server, or the speech recognition server cluster configured to:
perform speech recognition based on the speech information;
convert the speech information to obtain text information corresponding to the speech information; and
in the event that the IMS, the speech recognition server, or the speech recognition server cluster receives a speech recognition request issued from a user of the receiving end for the speech information, extract the speech ID corresponding to the speech information from the speech recognition request based on the speech ID to look up the text information corresponding to the speech ID, wherein the speech recognition module, the speech recognition server, the speech recognition server cluster, or any combination thereof is connected to the IMS; and
a sending module configured to send the obtained text information back as a speech recognition result to the receiving end.

US Pat. No. 10,249,300

INTELLIGENT LIST READING

Apple Inc., Cupertino, C...

1. An electronic device for operating a digital assistant, comprising:one or more processors; and
memory having instructions stored thereon, the instructions, when executed by the one or more processors, cause the one or more processors to:
receive a spoken user request associated with a plurality of data items;
determine whether a degree of specificity of the spoken user request is less than a threshold level;
in response to determining that a degree of specificity of the spoken user request is less than a threshold level:
determine one or more attributes related to the spoken user request, the one or more attributes not defined in the spoken user request;
obtain a list of data items based on the spoken user request and the one or more attributes;
generate a spoken response comprising a subset of the list of data items; and
provide the spoken response.

US Pat. No. 10,249,299

TAILORING BEAMFORMING TECHNIQUES TO ENVIRONMENTS

Amazon Technologies, Inc....

1. An apparatus comprising:one or more processors;
a microphone array; and
one or more computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform acts comprising:
generating, based at least in part on sound captured by the microphone array, a plurality of audio signals, wherein each of the plurality of audio signals corresponds to a respective microphone of the microphone array;
processing, by a beamforming component configured with one or more beamforming coefficients, at least a first audio signal of the plurality of audio signals to generate a first processed audio signal, wherein the first processed audio signal corresponds to a first portion of the sound received from a first direction;
processing, by the beamforming component configured with the one or more beamforming coefficients, at least a second audio signal of the plurality of audio signals to generate a second processed audio signal, wherein the second processed audio signal corresponds to a second portion of the sound received from a second direction;
selecting a direction of interest based at least in part on:
an amount of energy associated with a portion of the first processed audio signal;
an amount of energy associated with a portion of the second processed audio signal; and
directional data indicating at least one of a number of times speech has been identified from the first direction in previously processed audio signals or a number of times speech has been identified from the second direction in the previously processed audio signals; and
selecting, based at least in part on the direction of interest, the first processed audio signal.

US Pat. No. 10,249,298

METHOD AND APPARATUS FOR PROVIDING GLOBAL VOICE-BASED ENTRY OF GEOGRAPHIC INFORMATION IN A DEVICE

HERE GLOBAL B.V., Eindho...

1. A method for automatic speech recognition in a device, comprising:partitioning a global speech decoding graph into one or more spatial partitions according to a geographic topology of one or more geographic entities, one or more geographic terms, or a combination thereof, wherein each of the spatial partitions contains a decoding graph comprising a sub-set of the one or more geographic entities, the one or more geographic terms, or a combination thereof associated with a geographic area;
determining one or more of key entities occurring in each of the one or more spatial partitions, wherein at least one of the one or more of key entities includes at least one of the one or more geographic entities and the one or more geographic terms;
constructing a combined set of key entities comprising the one or more key entities from said each spatial partition;
creating a retrieval index to map the one or more key entities in the combined set of key entities to a corresponding partition from among the one or more spatial partitions,
wherein a voice input signal associated with a request for one or more navigation or mapping related services is processed, using automatic speech recognition and a first partition associated with a first geographic area from among the one or more spatial partitions, the combined set of key entities, and the retrieved index are stored in a memory of the device, and
wherein a second partition that is associated with a second geographic area and not in the memory of the device is retrieved based on the combined set of key entities and the retrieval index to automatically re-process the voice input signal when an out-of-vocabulary result is obtained with respect to the first partition and to provide the one or more navigation or mapping related services via a user interface based, at least in part, on the re-processing.

US Pat. No. 10,249,297

PROPAGATING CONVERSATIONAL ALTERNATIVES USING DELAYED HYPOTHESIS BINDING

Microsoft Technology Lice...

1. A computer-implemented method comprising:processing, by a speech recognition system, a received input to generate a set of alternatives, wherein the set of alternatives corresponds to hypothetical interpretations of the received input, and wherein the received input is an utterance;
filtering the set of alternatives, wherein the filtering comprises ranking the set of alternatives using machine learning techniques and propagating a plurality of the ranked alternatives for additional processing, wherein the machine learning techniques include comparing confidence metrics for two or more alternatives in the set of alternatives;
processing the propagated alternatives to generate an expanded set of alternatives as potential hypotheses based on the received input, wherein generating the expanded set of alternatives comprises determining one or more domains associated with the input, and generating one or more alternatives associated with the one or more domains;
filtering the expanded set of alternatives, wherein the filtering comprises ranking alternatives of the expanded set and propagating a plurality of the ranked alternatives of the expanded set for additional processing;
evaluating the propagated alternatives of the expanded set based on application of knowledge data fetched from external resources;
generating a response to the received input, wherein the generating comprises ranking the evaluated alternatives and selecting a ranked and evaluated alternative for generating the response; and
providing the response to a user.

US Pat. No. 10,249,296

APPLICATION DISCOVERY AND SELECTION IN LANGUAGE-BASED SYSTEMS

Amazon Technologies, Inc....

1. A system comprising:one or more processors; and
non-transitory computer-readable media storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
determining a first serviceable intent associated with an application, wherein the first serviceable intent corresponds to a function to be performed by the application;
receiving first audio data associated with a user;
generating, via automatic speech recognition, first text data corresponding to the first audio data;
determining, via natural language understanding performed on the first text data, a first intent associated with the first audio data;
determining, based at least in part on the first intent, first response data related to the first audio data, the first response data including text that is to be output to the user;
causing the first response data to be output via a user device of the user, the first response data requesting second audio data from the user;
receiving, via the user device, the second audio data, the second audio data received in response to the first response data;
generating, via automatic speech recognition, second text data corresponding to the second audio data;
determining, via natural language understanding performed on the second text data, a second intent associated with the first audio data and the second audio data;
analyzing the second intent to determine whether the second intent corresponds to the first serviceable intent;
determining that the second intent corresponds to the first serviceable intent;
causing the application to perform the function associated with the serviceable intent;
receiving third audio data;
generating, via automatic speech recognition, third text data corresponding to the third audio data;
determining, via natural language understanding performed on the third text data, a third intent associated with the third audio data;
determining that the third intent corresponds to a second serviceable intent associated with an additional application; and
in response to determining that the third intent corresponds to the second serviceable intent, causing the application to cease performing the function.

US Pat. No. 10,249,295

METHOD OF PROACTIVE OBJECT TRANSFERRING MANAGEMENT

International Business Ma...

1. A method for initiating a file transfer between storage devices associated with users, comprising:receiving, at a cognitive network computing service, a recording of an oral communication among a plurality of users, wherein the oral communication was recorded by an application executing on a device associated with at least one of the plurality of users;
determining a context of the oral communication, wherein determining the context of the oral communication comprises:
processing the communication using one or more voice recognition models to identify a first user and a second user in the plurality of users; and
determining a topic of the oral communication;
detecting, based on the context of the oral communication, a request between the first user and the second user to share a file maintained by the first user;
validating the request, wherein validating the request comprises:
identifying the file that was requested to be shared;
determining that the identified file exists in one or more storage systems associated with the first user;
determining, based on a location-based service, that that the second user and the first user are within a predefined proximity; and
determining, based on accessing one or more social media services, that an identified relationship between the first user and the second user satisfies predefined criteria; and
upon successfully validating the request, performing the file transfer of the file from a storage device associated with the first user to a storage device associated with the second user.

US Pat. No. 10,249,294

SPEECH RECOGNITION SYSTEM AND METHOD

ELECTRONICS AND TELECOMMU...

1. A speech recognition method which allows phones to be automatically generated, comprising:unsupervisedly learning a feature vector of speech data;
generating a phone set by clustering acoustic features selected based on an unsupervised learning result;
allocating a sequence of phones to the speech data on the basis of the generated phone set;
generating an acoustic model on the basis of the sequence of phones and the speech data to which the sequence of phones is allocated; and
generating a speech recognition result by a speech recognition decoder using the acoustic model and a language network.

US Pat. No. 10,249,293

LISTENING DEVICES FOR OBTAINING METRICS FROM AMBIENT NOISE

Capital One Services, LLC...

9. A device comprising:one or more memories; and
one or more processors, communicatively coupled to the one or more memories, configured to:
receive first audio data based on a first capturing of sounds associated with a first structure;
receive second audio data based on a second capturing of sounds associated with a second structure;
obtain a first model associated with the first structure,
the first model having been trained to:
receive the first audio data as input,
determine a first score that identifies a likelihood that a first sound is present in the first audio data, and
identify the first sound based on the first score;
obtain a second model associated with the second structure,
the second model having been trained to:
receive the second audio data as input,
determine a second score that identifies a likelihood that a second sound is present in the second audio data, and
identify the second sound based on the second score;
determine at least one first parameter associated with the first sound;
determine at least one second parameter associated with the second sound;
generate a first metric based on the at least one first parameter associated with the first sound;
generate a second metric based on the at least one second parameter associated with the second sound;
obtain cost data from a third-party device;
determine a first cost of consumption based on a first correlation of the first metric and the cost data;
determine a second cost of consumption based on a second correlation of the second metric and the cost data;
perform a first action based on determining the first cost of consumption; and
perform a second action based on determining the second cost of consumption.

US Pat. No. 10,249,292

USING LONG SHORT-TERM MEMORY RECURRENT NEURAL NETWORK FOR SPEAKER DIARIZATION SEGMENTATION

International Business Ma...

1. A computing system comprising:a processor;
a storage device to store audio data including speech of a first speaker type, speech of a second speaker type, and silence, the storage device storing computer-executable code that the processor is to execute to:
segment the audio data using a long short-term memory (LSTM) recurrent neural network (RNN) to identify a plurality of change points of the audio data that divide the audio data into a plurality of segments, each change point being a transition from one of the first speaker type, the second speaker type, and the silence to a different one of the first speaker type, the second speaker type, and the silence; and
perform speech recognition on the segments,
wherein segmentation of the audio data using the LSTM RNN to identify the change points technically improves speech recognition technology, by improving accuracy of the speech recognition on the segments when the audio data includes one or more of speech articulated by multiple speakers, silence, and music.

US Pat. No. 10,249,291

ANIMATION SYNTHESIS SYSTEM AND LIP ANIMATION SYNTHESIS METHOD

ASUSTeK COMPUTER INC., T...

1. An animation display system comprising:a display;
a storage configured to store a language model database, a phonetic-symbol lip-motion matching database, and a lip motion synthesis database; and
a processor electronically connected to the storage and the display, respectively, the processor includes:
a speech conversion module configured to analyze a language of an input text, and convert the input text into a combination of phonetic symbols and a timestamp based on the language of the input text according to the language model database;
a phonetic-symbol lip-motion matching module configured to output a combination of lip movements that corresponds to the combination of the phonetic symbols according to the phonetic-symbol lip-motion matching database; and
a lip motion synthesis module configured to generate a lip animation corresponding to the combination of the lip movements and the timestamp according to the lip motion synthesis database;
wherein the language of the input text is a country language which is related to a system of communication used by a particular country, and the speech conversion module recognizes the country language of the input text before converting the input text into the combination of phonetic symbols and the timestamp based on the language of the input text, and
wherein the storage is further configured to store a phonetic symbol conversion database, the processor further includes a phonetic symbol conversion module, the phonetic symbol conversion module is configured to convert the combination of the phonetic symbols into a standard combination of the phonetic symbols according to the phonetic symbol conversion database, and the combination of the lip movements is output according to the standard combination of the phonetic symbols,
wherein a type of the combination of phonetic symbols output by the speech conversion module may correspond to a same or different phonetic symbol system with respect to a type of the combination of phonetic symbols used in the phonetic-symbol lip-motion matching module; and
wherein the phonetic symbol conversion module is configured to convert the combination of the phonetic symbols into a standard combination of the phonetic symbols belonging to the same phonetic symbol system according to the phonetic symbol conversion database and in response to the type of the combination of phonetic symbols output by the speech conversion module being different from the type of the phonetic symbols used in the phonetic-symbol lip-motion matching module.

US Pat. No. 10,249,290

SYSTEM AND METHOD FOR PROSODICALLY MODIFIED UNIT SELECTION DATABASES

1. A method comprising:decomposing, via a residual-excited linear prediction algorithm, speech units from a speech unit database into residual coefficients and linear predictive coder coefficients;
determining a cost of modifying the residual coefficients to yield a determination;
modifying, via a pitch synchronous overlap and add algorithm, the residual coefficients, to yield modified residual coefficients based on the determination; and
combining, via the residual-excited linear prediction algorithm, the modified residual coefficients with the linear predictive coder coefficients, to yield new speech units, such that a new prosodic curve corresponding to the new speech units conforms to a desired prosodic curve, wherein speech is generated based on the new speech units.

US Pat. No. 10,249,289

TEXT-TO-SPEECH SYNTHESIS USING AN AUTOENCODER

Google LLC, Mountain Vie...

1. A method performed by one or more computers of a text-to-speech system, the method comprising:obtaining, by the one or more computers, data indicating a text for text-to-speech synthesis;
providing, by the one or more computers, data indicating a linguistic unit of the text as input to an encoder, the encoder being configured to output speech unit representations indicative of acoustic characteristics based on linguistic information, wherein the encoder is configured to provide speech unit representations learned through machine learning training, wherein the encoder comprises a neural network that was trained as part of an autoencoder network that includes the encoder, a second encoder, and a decoder, wherein:
the encoder is arranged to produce speech unit representations in response to receiving data indicating linguistic units;
the second encoder is arranged to produce speech unit representations in response to receiving data indicating acoustic features of speech units; and
the decoder is arranged to generate output indicating acoustic features of speech units in response to receiving speech unit representations for the speech units from either of the encoder and the second encoder;
receiving, by the one or more computers, a speech unit representation that the encoder outputs in response to receiving the data indicating the linguistic unit as input to the encoder;
selecting, by the one or more computers, a speech unit to represent the linguistic unit, the speech unit being selected from among a collection of speech units based on the speech unit representation output by the encoder; and
providing, by the one or more computers and as output of the text-to-speech system, audio data for a synthesized utterance of the text that includes the selected speech unit.

US Pat. No. 10,249,288

SOCIAL NETWORKING WITH ASSISTIVE TECHNOLOGY DEVICE

International Business Ma...

1. A method implemented by an information handling system that includes a processor and a memory accessible by the processor, the method comprising:analyzing, by the processor, a document that is being composed by a visually impaired user, wherein the analysis derives a sensitivity of the document;
retrieving, from the memory, a vocal characteristic corresponding to the derived sensitivity based on one or more predefined settings;
retrieving, from the memory, an additional vocal characteristic corresponding to a size of an audience intended to receive the document; and
audibly reading text from the document to the visually impaired user with a text to speech process utilizing both the retrieved vocal characteristic and the additional vocal characteristic.

US Pat. No. 10,249,287

NOISE-CANCELLING HEADPHONE

KABUSHIKI KAISHA AUDIO-TE...

1. A headphone comprising:a first microphone that receives a front air chamber sound including an external sound, the first microphone being provided on a front air chamber side;
a driver unit that emits a noise-canceling sound into the front air chamber, the noise-canceling sound canceling at least a part of the external sound included in the front air chamber sound received by the first microphone;
a second microphone that receives an inverted noise-canceling sound whose phase is opposite to the phase of the noise-canceling sound emitted from the driver unit and received by the first microphone, the second microphone being provided in a region on a side of the driver unit opposite the front air chamber; and
a sound generating part that generates the noise-canceling sound by adding a signal based on the inverted noise-canceling sound received by the second microphone to a signal based on the front air chamber sound received by the first microphone,
wherein a distance between the second microphone and a center position of the driver unit is less than a distance between the first microphone and the center position of the driver unit.

US Pat. No. 10,249,286

ADAPTIVE BEAMFORMING USING KEPSTRUM-BASED FILTERS

KAAM LLC, Saratoga, CA (...

1. A system, comprising:a plurality of circuits in a signal processing apparatus, the plurality of circuits is configured to:
generate a filtered signal from a plurality of input signals, wherein the plurality of input signals is received from each of a plurality of signal capturing terminals, wherein each of the plurality of input signals comprises a first type of signal and a second type of signal;
determine, for each signal frame, a first resultant estimate of the first type of signal in the plurality of input signals, received from each of the plurality of signal capturing terminals, based on a first impulse response of each first content adaptive filter of a plurality of first content adaptive filters;
determine, for each signal frame, a second resultant estimate of the first type of signal in a composite signal based on a second impulse response of a second content adaptive filter;
restore phase information of an estimated interference signal, obtained from the second content adaptive filter configured with the determined second resultant estimate, to obtain a phase restored interference signal; and
extract the first type of signal from the filtered signal based on filtration of the phase restored interference signal from the filtered signal.

US Pat. No. 10,249,285

ACOUSTIC CONVERSION DEVICE FOR ACTIVE NOISE CONTROL

PIONEER CORPORATION, Tok...

1. An acoustic conversion device for an active noise control comprising:a speaker unit for emitting sound; and
an enclosure for accommodating the speaker unit and forming a closed space to which at least a part of the sound is emitted,
wherein a volume of the closed space is smaller than an equivalent compliance air volume of the speaker unit,
wherein the speaker unit includes a vibration plate, and
wherein an effective vibration diameter of the vibration plate is 10 cm or more and 14 cm or less, and
the volume of the closed space is 5 liters or more and 7 liters or less.

US Pat. No. 10,249,284

BANDLIMITING ANTI-NOISE IN PERSONAL AUDIO DEVICES HAVING ADAPTIVE NOISE CANCELLATION (ANC)

CIRRUS LOGIC, INC., Aust...

1. A personal audio device, comprising:a personal audio device housing;
a transducer mounted on the housing that reproduces an audio signal including both source audio for playback to a listener and an anti-noise signal to counter the effects of ambient audio sounds in an acoustic output of the transducer;
a reference microphone mounted on the housing that generates a reference microphone signal indicative of the ambient audio sounds;
an error microphone mounted on the housing in proximity to the transducer that generates an error microphone signal indicative of the acoustic output of the transducer and the ambient audio sounds at the transducer; and
a processing circuit that implements a first adaptive filter having a response that generates the anti-noise signal from the reference microphone signal to reduce the presence of the ambient audio sounds heard by the listener, wherein the processing circuit shapes the response of the first adaptive filter in conformity with the error microphone signal and the reference microphone signal by adapting the response of the first adaptive filter to minimize the ambient audio sounds at the error microphone according to coefficients generated by a coefficient control that receives an error signal derived from the error microphone signal, wherein the error signal is filtered by a filter implemented by the processing circuit to weight one or more particular frequency regions within the response of the first adaptive filter before being provided to the coefficient control, wherein the coefficient control computes the coefficients by correlating the error signal with the reference microphone signal, wherein the filter filters the error signal to weight a frequency content of the error signal to compensate for a frequency response of an external acoustic path between the reference microphone and the error microphone by causing the coefficients to be adjusted to increase or decrease the degree to which the anti-noise signal cancels the ambient audio sounds in the one or more particular frequency regions relative to the degree to which the anti-noise signal cancels the ambient audio sounds in other frequency regions by respectively increasing or decreasing a gain applied to the error signal in the one or more particular frequency regions relative to gain applied to the other frequency regions within the response of the first adaptive filter, wherein the processing circuit further implements a secondary path filter having a response that generates a shaped source audio signal and a combiner that subtracts the shaped source audio signal from the error microphone signal to generate the error signal, wherein the combiner cancel components of the source audio signal present in the error microphone signal in order to prevent the first adaptive filter from cancelling components of the source audio signal when generating the anti-noise signal.

US Pat. No. 10,249,283

TONE AND HOWL SUPPRESSION IN AN ANC SYSTEM

Cirrus Logic, Inc., Aust...

9. An apparatus, comprising:an audio controller configured to perform steps comprising:
detecting a first tone in an input signal at a first tone frequency;
extracting the detected first tone from the input signal;
adaptively filtering the extracted first tone to generate a second tone that has a magnitude that is approximately equal to a magnitude of the extracted first tone and a phase that is approximately opposite the phase of the extracted first tone; and
adding the second tone to an intermediate signal that is based, at least in part, on the input signal to generate the output signal.

US Pat. No. 10,249,282

ACTIVE NOISE REDUCTION DEVICE

SOUNDCHIP SA, Aran-Ville...

1. A method of manufacturing an Active Noise Reduction (ANR) device, comprising:providing at a stage during manufacture a pre-completion ANR device in a non-final configuration, the pre-completion ANR device comprising:
a plurality of inputs;
a plurality of signal processing resources comprising:
a plurality of analogue signal processing resources; and
a plurality of digital signal processing resources;
an output for driving an earphone driver; and
a programmable switch arrangement capable of assigning any of the plurality of inputs to any of the plurality of signal processing resources;
selecting from the plurality of signal processing resources a subset of signal processing resources to contribute to the output, whereby the remaining signal processing resources of the plurality are unselected; and
in a configuration step during manufacture, programming the programmable switch arrangement to assign each of at least a subset of the plurality of inputs to a different one of the selected subset of signal processing resources to enable the selected subset of signal processing resources to contribute to the output, whereby the unselected signal processing resources of the plurality of signal processing resources are configured not to contribute to the output in any mode of operation of the ANR device.

US Pat. No. 10,249,281

FELT, SOUNDPROOFING MATERIAL AND METHOD FOR PRODUCING SOUNDPROOFING MATERIAL

Nihon Tokushu Toryo Co., ...

1. A felt comprising:10 mass % to 90 mass % of an unstretched thermoplastic resin fiber; and
10 mass % to 90 mass % of a stretched thermoplastic resin fiber, and
having a thickness of 1 mm to 10 mm, and an areal weight of 50 g/m2 to 1600 g/m2.

US Pat. No. 10,249,280

HIGH PRESSURE GAS SILENCER

1. A high and low pressure natural gas silencer comprising:a threaded union to connect to a natural gas pipeline port;
said natural gas pipeline port further comprising a vent valve functioning to allow a venting of a pressurized natural gas to atmosphere;
a cylindrical body connected to the threaded union by a nut assembly;
said nut assembly having a loose mode to allow the cylindrical body to be rotated 360° on the threaded union while remaining attached to the nut assembly, and having a locked mode to affix the cylindrical body at a desired angle;
a plurality of vent holes on only one side of the cylindrical body;
a replacement noise suppression module inside the cylindrical body; and
said cylindrical body having a solid top.

US Pat. No. 10,249,279

D/A CONVERTER, ELECTRONIC MUSICAL INSTRUMENT, INFORMATION PROCESSING DEVICE AND D/A CONVERSION METHOD

CASIO COMPUTER CO., LTD.,...

1. A digital-to-analog converter that converts digital audio data of a music sound represented by an input digital signal into an analog signal, the digital-to-analog converter being configured to perform:a signal output process to output a control signal at a second period, the second period being equal to an integral multiple of a first period in a first clock signal;
a count process to count a second clock signal whose clock frequency is higher than that of the first clock signal, and to store a count value;
a determination process to determine whether ?? computation is under execution with respect to the digital audio data, in accordance with the count value stored by the count process;
a ?? computation process to start the ?? computation based upon the second clock signal with respect to the digital audio data if it is determined in the determination process that the ?? computation is not under execution when the control signal is outputted by the signal output process;
a control process to inhibit the ?? computation based upon the second clock signal from being started with respect to the digital audio data until it is determined in the determination process that the ?? computation is not under execution after it is determined in the determination process that the ?? computation is under execution; and
an output process to convert a computation result of the ?? computation process into an analog signal and to output the analog signal.

US Pat. No. 10,249,278

SYSTEMS AND METHODS FOR CREATING DIGITAL NOTE INFORMATION FOR A METAL-STRINGED MUSICAL INSTRUMENT

Zivix LLC, Minneapolis, ...

1. A method for producing a digital output from a stringed instrument, the method comprising:determining a note being fingered on a string of the stringed instrument based at least in part on detecting deflection of the string;
detecting a pluck of the string on the stringed instrument;
in response to detecting the pluck, using data received from an optical pick up to determine a volume associated with the note; and
outputting a digital output corresponding to the note and the volume.

US Pat. No. 10,249,277

KEYBOARD INSTRUMENT EQUIPPED WITH SPEAKERS

CASIO COMPUTER CO., LTD.,...

1. A keyboard instrument comprising:a musical instrument case;
a speaker which emits sounds in response to instructions from a keyboard section; and
a keyboard lid which is switchable between a first arrangement state in which the keyboard lid covers at least a portion of the keyboard section and a second arrangement state in which the keyboard lid is opened to expose at least a portion of the keyboard section and housed in the musical instrument case,
wherein the musical instrument case is provided with a sound emission hole penetrating a top plate of the musical instrument case in a vertical direction and an opening section located in front of the top plate, and
wherein the keyboard lid, in the second arrangement state, is arranged so as to partition a space in the musical instrument case into a first acoustic space for leading the sounds emitted from the speaker to the sound emission hole and a second acoustic space for leading the sounds emitted from the speaker to the opening section.

US Pat. No. 10,249,276

ROTATING SPEAKER ARRAY

1. An audio effects apparatus comprising:a rotatable sound directing device that is operable to direct acoustical sound waves along a rotatable sound directional axis;
a rotary device coupled to the rotatable sound directing device, the rotary device operable to continuously rotate the rotatable sound directional axis of the rotatable sound directing device about a rotational axis in response to a rotational drive signal;
a rotational position measurement device for generating a rotational position signal that is indicative of a rotational position of the rotary device;
an audio input for receiving an audio input signal;
a motion control and audio signal processing device for receiving the rotational position signal and the audio input signal, and for generating the rotational drive signal and a light timing signal based at least in part on the rotational position signal; and
one or more light emitting devices for emitting pulsed light that is timed based on the light timing signal.

US Pat. No. 10,249,275

HANDPAN HANGER

1. A hanger for removably coupling a handpan musical instrument to a substantially vertical wall with a substantially planar surface, wherein the musical instrument is a handpan, the hanger comprising at least one elongate member, wherein the at least one elongate member comprises: a substrate-mounting-region, wherein the substrate-mounting-region is attachable to the substantially vertical wall so that the hanger is mounted to the substantially vertical wall, wherein mounted is more than the substrate-mounting-region merely resting against the substantially vertical wall; a handpan-engagement-region, wherein the handpan-engagement-region removably engages at least some portion of a bass cavity of the handpan; a hypotenuse-region, wherein the hypotenuse-region is disposed between the substrate-mounting-region and the handpan-engagement-region; wherein the hypotenuse-region is substantially linear; a first-bend, wherein the first-bend is disposed between the substrate-mounting-region and the hypotenuse-region, wherein the first-bend links the substrate-mounting-region to the hypotenuse-region; wherein the first-bend bends away from the substantially vertical wall when the substrate-mounting-region is mounted to the substantially vertical wall; a second-bend, wherein the second-bend is disposed between the hypotenuse-region and the handpan-engagement-region, wherein the second-bend links the hypotenuse-region to the handpan-engagement-region; wherein there are no other bends between the first-bend and the second-bend; wherein the at least one elongate member begins with the substrate-mounting-region and ends with the handpan-engagement-region; wherein the at least one elongate member is substantially rigid; wherein when the hanger is mounted to the substantially vertical wall, the handpan-engagement-region removably supports the handpan so the handpan is mounted in proximity to the substantially vertical wall; wherein when the hanger is mounted to the substantially vertical wall, a critical angle is formed between the substantially vertical wall and the hypotenuse-region; wherein this critical angle is in a range of about 50 degrees to about 70 degrees.

US Pat. No. 10,249,274

KEYBOARD MUSICAL INSTRUMENT, ADJUSTING METHOD THEREOF, AND COMPUTER-READABLE RECORDING MEDIUM THEREFOR

YAMAHA CORPORATION, Hama...

1. A keyboard musical instrument comprising:a string-striking mechanism configured to strike a string responsive to a change in position of an associated one of keys of a keyboard;
a driver including a driving body for each key that is configured to drive the string-striking mechanism for the respective key;
a sound receiver configured to generate an audio signal corresponding to sound occurring in the keyboard musical instrument;
at least one controller each including a processor or circuitry configured to implement instructions stored in a memory and execute a plurality of tasks, including:
a detecting task that detects striking of a string by the string-striking mechanism through analysis of the audio signal from the sound receiver when the string-striking mechanism operates, in accordance with an intensity of the audio signal within a search range that has a predetermined relationship along a time axis with regard to a time at which operation of the string-striking mechanism commences;
a current supplying task that supplies electric driving current to the driving body in accordance with the control data to drive the string-striking mechanism for the respective key;
a current changing task that sequentially changes a value of electric driving current to provide electric driving currents having different values;
an identifying task that identifies, for each key, minimum electric driving current applied to the respective driving body that drives the string-striking mechanism to strike a string, and a delay time from when driving of the string-striking mechanism commences to when the string-striking mechanism strikes the string, based on results of string strike detections when the string-striking mechanism is made to operate with the electric driving currents having different values; and
an adjusting task that adjusts the control data in accordance with the identified minimum electric driving current and the identified delay time.

US Pat. No. 10,249,273

MAGNETIC DRUM SUSPENSION APPARATUS

Randall May International...

1. A percussion instrument mount, comprising:a base that supports a percussion instrument in a playing position;
a swing arm coupled to the percussion instrument, the swing arm also coupled to the base via a joint such that the swing arm rotates about the joint from an equilibrium position in response to a playing impact on the percussion instrument; and
a playing impact energy absorber that provides a restoring force to the swing arm so as to return the swing arm to the equilibrium position, wherein the playing impact energy absorber progressively dampens the swing via magnetic field resistance.

US Pat. No. 10,249,272

PERCUSSION INSTRUMENT WITH ADJUSTABLE AUXILIARY DEVICE

Drum Workshop, Inc., Oxn...

1. A percussion instrument comprising:a tapa having a backside;
a rear surface;
an adjustment device attached to said rear surface;
an adjustment rod operably linked to said adjustment device, said adjustment rod between said rear surface and said tapa;
an auxiliary bar running approximately horizontally across the width of said backside of said tapa; and
an auxiliary device attached to said auxiliary bar;
wherein movement of said adjustment device from a first position to a second position causes translational movement of said adjustment rod, the translational movement of said adjustment rod causing rotational movement of said auxiliary bar such that said more or less of said auxiliary device is in contact with said tapa backside.

US Pat. No. 10,249,271

MUTE FOR A RECORDER

1. A mute for a recorder consisting of a convex sheet, adapted to be inserted into a recorder window, and attached to two identical bands of semi-rigid material that are removably affixed to a recorder mouth, said identical bands arranged symmetrically with respect to the longitudinal axis of the sheet, each of the bands having an approximate shape of an arc with a circumference and length that is less than half the length of the outer circumference of a mouth of the recorder.

US Pat. No. 10,249,270

METHOD AND SYSTEM FOR COMPROMISE TUNING OF MUSICAL INSTRUMENTS

International Business Ma...

1. A method performed by a programmed computing device for tuning a musical instrument, the computing device including one more processors implemented using circuitry, a memory, either a linear actuator or an indicator for prompting a user to stop making tuning adjustments to the musical instrument, and at least one of a sensor and a wireless receiver for receiving sensor data, the method comprising:determining initial frequencies of a plurality of notes played on the musical instrument by the user when the musical instrument is out of tune, wherein the plurality of notes include a first note and one or more other notes in a series that share a resonant path, and wherein tuning adjustments that change a frequency of any note in the plurality of notes affect frequencies of other notes in the plurality of notes;
determining a change in a frequency of the first note, as played on the musical instrument by the user, resulting from a first tuning adjustment made by the linear actuator or the user to the musical instrument;
determining, without the user playing the other notes on the musical instrument, a change in the frequency of each note of the other notes based, at least in part, on the change in the frequency of the first note, the initial frequency of the note, and a relationship between note frequencies;
determining a changed frequency of each note of the other notes based, at least in part, on the determined change in the frequency of the note and the initial frequency of the note;
determining, via the one or more processors, a compromise tuning adjustment of the musical instrument that minimizes a sum of differences between a changed frequency of each note of the first and the other notes and a predefined frequency of the note or a frequency to which the note was previously tuned;
monitoring the frequency of the first note as the linear actuator or the user makes additional tuning adjustments to the musical instrument to determine whether the frequency of the first note has changed by an amount indicating the compromise tuning adjustment that minimizes the sum of the differences is achieved; and
responsive to determining during the monitoring that the compromise tuning adjust is achieved, either indicating to the user via the indicator to stop making the additional tuning adjustments to the musical instrument or automatically controlling the linear actuator to stop making the additional tuning adjustments to the musical instrument.

US Pat. No. 10,249,269

SYSTEM ON CHIP DEVICES AND OPERATING METHODS THEREOF

Samsung Electronics Co., ...

1. An operating method of a system on chip device performed under control of a processor, the operating method comprising:setting a first characteristic by analyzing a request for allocation of a buffer memory of the system on chip device;
allocating a first region of the buffer memory in response to the request for allocation of the buffer memory; and
compressing or not compressing data provided to the first region, based on the first characteristic,
wherein the first characteristic is set based on a determination that a compression algorithm performed in a first Intellectual Property (IP) block that is configured to provide the data to the first region is the same as a decompression algorithm performed in a second IP block that is configured to use the data provided to the first region.

US Pat. No. 10,249,268

ORIENTATION OF VIDEO BASED ON THE ORIENTATION OF A DISPLAY

Google LLC, Mountain Vie...

1. A system comprising:a non-transitory computer readable medium; and
program instructions stored on the non-transitory computer readable medium and executable by at least one processor to cause a sharer mobile device to:
receive first video data, the first video data corresponding to a first orientation of an image-capture device that is arranged on the sharer mobile device;
send the first video data to a viewer mobile device;
receive, from the viewer mobile device, orientation data indicating a requested orientation of the image-capture device, wherein the requested orientation is based on movement data generated at the viewer mobile device in accordance with a movement of the viewer mobile device;
cause a graphical image indicative of the requested orientation to be displayed on a graphical display of the sharer mobile device;
receive second video data, the second video data corresponding to a second orientation of the image-capture device arranged on the sharer mobile device;
determine that the second orientation is within a threshold from the requested orientation; and
responsive to the determination, send the second video data to the viewer mobile device.

US Pat. No. 10,249,267

METHOD FOR GRAPHICALLY REPRESENTING A SYNTHETIC THREE-DIMENSIONAL VIEW OF THE EXTERIOR LANDSCAPE IN AN ON-BOARD VISUALISATION SYSTEM FOR AIRCRAFT

THALES, Courbevoie (FR)

1. A method for graphically representing a synthetic three-dimensional view of the exterior landscape in an on-board visualisation system for aircraft, said graphical representation being displayed on a visualisation screen comprising the piloting or navigation information of said aircraft superposed onto said three-dimensional synthetic representation of the exterior landscape, said synthetic representation being computed up to a first determined distance, wherein said three-dimensional synthetic representation is tilted at a tilt angle about an axis positioned at the level of the terrain in a substantially horizontal plane, and substantially perpendicularly to an axis between the flight direction and the heading of the aircraft, said axis moving with the aircraft, said tilt angle being computed so that the angle between the horizon line or ZPRL and the limit of the synthetic representation computed up to a first determined distance is limited to three degrees.

US Pat. No. 10,249,266

PRESERVING DESKTOP STATE ACROSS LOGIN SESSIONS

VMware, Inc., Palo Alto,...

1. A method for preserving desktop state across login sessions, the method comprising:during an active login session of a desktop by a user, intercepting a request to open a file and recording a path of the file that was opened in response to the request;
detecting that the login session is being terminated;
in response to detecting that the login session is being terminated, capturing a screenshot of at least one window that is open on the desktop at the time of terminating the login session and determining a location of the window;
recording the screenshot and the location of the window;
detecting that the user has established a new active login session; and
restoring a state of the desktop based on the recorded path of the file, the screenshot and the location of the window, wherein restoring the state of the desktop includes:
to restore a first application, invoking restart management application programming interfaces (APIs) of a desktop operating system; and
to restore a second application that does not support the restart management APIs, displaying the captured screenshot of the window corresponding to the second application.

US Pat. No. 10,249,265

MULTI-DEVICE CONTENT PRESENTATION

Cisco Technology, Inc., ...

1. A method for presenting multimedia content on multiple devices, the method implemented on a controlling computing device and comprising:receiving a selection of a multimedia content item, said multimedia content item comprising at least two media segments each of a different type;
defining a first media segment of said at least two media segments as a primary media segment;
defining at least a second media segment of said at least two media segments as at least one secondary media segment;
allocating said at least one secondary media segment for presentation on at least one secondary presentation device;
presenting said primary media segment on said computing device;
detecting a current progress in said presenting;
based on said current progress, forwarding to said at least one secondary presentation device an indication of an instruction for synchronizing presentation of said at least one secondary media segment with said presenting.

US Pat. No. 10,249,264

CONTROLLER FOR COMPENSATING MURA DEFECTS, DISPLAY APPARATUS HAVING THE SAME, AND METHOD FOR COMPENSATING MURA DEFECTS

BOE TECHNOLOGY GROUP CO.,...

1. A method for compensating mura defects in a display image comprising:selecting a plurality of sampling pixels by selecting at least one polygon region to include all pixels determined to have mura defects, pixels within the at least one polygon region are defined as the plurality of sampling pixels;
obtaining a plurality of display data and a plurality of address data corresponding to a plurality of display pixels; and
determining if a pixel is a sampling pixel based on a data table comprising a plurality of compensation data associated with a plurality of compensation points for compensating a plurality of sampling pixels, a respective one of the plurality of compensation points corresponding to a group of at least one sampling pixel, the plurality of sampling pixels comprising a plurality of display pixels having mura defects and constituting a portion of the plurality of display pixels;
wherein a respective one of the at least one polygon region is selected to encompass one or more isolated areas of pixels determined to have mura defects if a distance between isolated areas is less than a threshold distance.

US Pat. No. 10,249,263

RENDERING AND DISPLAYING HIGH DYNAMIC RANGE CONTENT

Apple Inc., Cupertino, C...

1. A system, comprising:a display panel with a display space defined by bit depth of the display panel, the display space comprising N codes for representing pixel values; and
one or more processors configured to implement:
a rendering pipeline configured to render received digital image content according to a maximum rendering value M to generate high dynamic range (HDR) content in a dynamic range of (0.0-M); and
a display pipeline configured to:
obtain the rendered HDR content;
map the rendered HDR content into the display space of the display panel according to a brightness level B that defines a lower portion (codes 0 to n) and an upper portion (codes n to (N?1)) of the display space;
wherein, to map the rendered HDR content into the display space of the display panel, the display pipeline is configured to:
map a first portion of the rendered HDR content in a standard range (0.0-1.0) into codes in the lower portion of the display space; and
map a second portion of the rendered HDR content in an extended range (1.0-M) into codes in the upper portion of the display space; and
output the mapped HDR content to the display panel for display.

US Pat. No. 10,249,262

DISPLAYS WITH ADJUSTABLE CIRCULAR POLARIZERS

Apple Inc., Cupertino, C...

1. A display, comprising:a display layer that emits light that forms images; and
a circular polarizer on the display layer that suppresses reflections from structures in the display layer, wherein the circular polarizer comprises a polarizer layer with an adjustable polarization efficiency, wherein the polarizer layer comprises a layer of photosensitive material, and wherein the polarization efficiency is adjusted in response to light applied to the photosensitive material.

US Pat. No. 10,249,261

DISPLAY CONTROLLER AND APPLICATION PROCESSOR INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display controller comprising:a lookup table configured to store a plurality of reference data; and
an interpolation circuit configured to calculate a first corrected datum and a second corrected datum by performing correction on an image datum based on the plurality of reference data,
wherein the interpolation circuit determines whether the image datum is less than a reference value, calculates the first corrected datum using a first interpolation method, calculates the second corrected datum using a second interpolation method different from the first interpolation method, outputs the first corrected datum when the image datum is less than the reference value, and outputs the second corrected datum when the image datum is greater than or equal to the reference value,
when the first corrected datum is calculated using the first interpolation method, the interpolation circuit calculates the first corrected datum based on a first reference datum, which corresponds to a product of the image datum and the reference value, among the plurality of reference data, and
wherein the interpolation circuit comprises:
a first interpolator configured to calculate the first corrected datum using the first interpolation method;
a second interpolator configured to calculate the second corrected datum using the second interpolation method;
a comparator configured to compare the image datum with the reference value and generate a comparison signal; and
a multiplexer configured to select and output one of the first and second corrected datum based on the comparison signal.

US Pat. No. 10,249,260

IMAGE COLOR ENHANCEMENT METHOD INCLUDING CONVERSIONS OF COLOR PARAMETERS OF PIXELS

SHENZHEN CHINA STAR OPTOE...

1. An image enhancement method for a preset image displayed on a display, the preset image comprising pixels, and the image enhancement method comprising:a hue value converting step, wherein the hue value converting step comprises converting a red grayscale value, a green grayscale value, and a blue grayscale value for each pixel of the preset image represented in an RGB color model into a hue value, a color saturation value, and an intensity value for each pixel of the preset image represented in an HSI color space;
an enhancing step, wherein the enhancing step comprises performing an enhancement process on the color saturation value for each pixel of the preset image;
a rectifying step, wherein the enhancing step comprises rectifying the color saturation value for each pixel of the preset image according to the intensity value of each pixel of the preset image and a preset intensity threshold to avoid a color shift phenomenon of the preset image;
a grayscale value converting step, wherein the grayscale value converting step comprises converting the hue value, the color saturation value, and the intensity value for each pixel of the preset image, which has been rectified as a rectified preset image, into a red grayscale value, a green grayscale value, and a blue grayscale value for each pixel of the rectified preset image to facilitate the image display; and
a displaying step, wherein the displaying step comprises displaying the preset image on the display after the hue value converting step, the enhancing step, rectifying step, and the grayscale value converting step of the preset image;
wherein the red grayscale value, the green grayscale value, and the blue grayscale value for each pixel of the preset image represented in the RGB color model are converted into the hue value, the color saturation value, and the intensity value for each pixel of a preset image represented in an HSI color space according to the following formulas:

where R is a red grayscale value of a given pixel; B is a blue grayscale value of a given pixel; G is a green grayscale value of a given pixel; H is a hue value of a given pixel; S is a saturation value of a given pixel; and I is an intensity value of a given pixel;
wherein the following formula is used to perform the enhancement process on the color saturation value for each pixel of the preset image:
S_enh=S?(min(R,G,B)/max(R,G,B))
where S_enh is a color saturation value of a given pixel which has been subjected to the enhancement process; min (R, G, B) is a minimum value among the red grayscale value of a given pixel, the green grayscale value of a given pixel, and the blue grayscale value of a given pixel; max (R, G, B) is a maximum value among the red grayscale value of a given pixel, the green grayscale value of a given pixel, and the blue grayscale value of a given pixel.

US Pat. No. 10,249,259

METHOD FOR DRIVING A PIXEL ARRAY

BOE TECHNOLOGY GROUP CO.,...

1. A method for driving a pixel array in a display panel, the pixel array comprising a plurality of pixel units, each pixel unit comprising a plurality of sub-pixels of different colors, each sub-pixel having an aspect ratio from 1:2 to 1:1, the method comprising steps of:dividing an image to be displayed on the display panel into a plurality of theoretical pixel units based on a desired resolution, thereby obtaining a pixel pattern of the image to be displayed, each theoretical pixel unit comprising a plurality of color components and having an aspect ratio of 1:1, thereby the theoretical pixel unit being an area unit of the image to be displayed corresponding to the desired resolution, the area of each theoretical pixel unit being smaller than the area of each pixel unit in the pixel array; and
calculating a luminance value of each sub-pixel of each pixel-unit based on the color components of respective divided theoretical pixel units, comprising sub-steps of:
dividing a diamond sampling area for each sub-pixel in the pixel array, a center of the diamond sampling area being a center of the sub-pixel, and four vertexes of the diamond sampling area being midpoints of connecting lines between centers of adjacent sub-pixels in the same row or the same column and with the same color as the sub-pixel and the center of the sub-pixel respectively;
calculating a ratio of an overlapping area of each theoretical pixel unit with the diamond sampling area for the sub-pixel and the area of the diamond sampling area, as an area ratio of the theoretical pixel unit with respect to the diamond sampling area for the sub-pixel; and
using an area ratio of each theoretical pixel unit with respect to the diamond sampling area for the sub-pixel to multiply a color component of the theoretical pixel unit with the same color as the sub-pixel, and taking a summation of respective products to set the luminance value of the sub-pixel.

US Pat. No. 10,249,258

DISPLAY INTERFACE DEVICE AND DATA TRANSMISSION METHOD THEREOF

LG Display Co., Ltd., Se...

1. A display interface device comprising:a transmission part and a reception part, wherein the transmission part serializes clock edge information and display information and distributes a plurality of data packets each including serial clock edge information and display information as a transmission unit to a plurality of channels, and the reception part receives the plurality of data packets from the transmission part,
wherein the transmission part transmits clock edge information included in a data packet of each channel at a different timing from clock edge information included in data packets of other channels, and
the reception part detects a clock edge of each channel from the data packet transmitted through each channel and generates an internal clock signal of each channel, synchronized with the detected clock edge, corrects a delay of each channel depending on a result of a logical operation performed on a delayed clock edge of a channel and a clock edge of another channel to generate a delay-compensated internal clock signal of each channel, and restores the display information from the data packet of each channel using the internal clock signal of each channel.

US Pat. No. 10,249,257

DISPLAY DEVICE AND DRIVE METHOD OF THE DISPLAY DEVICE

Panasonic Liquid Crystal ...

1. A display device, comprising:a plurality of data lines extending in a first direction;
a plurality of gate lines extending in a second direction, the plurality of gate lines divided into groups that are adjacent in the first direction;
a plurality of selector transistors, each of which including a first conductive electrode and a second conductive electrode, wherein the first conductive electrode for each of the plurality of selector transistors is connected to an end of a gate line of the plurality of gate lines;
a plurality of selection signal supplying wirings, each of which is provided for a corresponding group and connected to a control electrode of a corresponding selector transistor of the plurality of the selector transistors for the corresponding group;
a plurality of gate voltage supplying wirings that are connected to the second conductive electrode of one of the selector transistors for each of the groups; and
a gate driver that sequentially supplies a first gate voltage to the plurality of gate voltage supplying wirings while supplying a control voltage to the plurality of selection signal supplying wirings in order to turn on or off the plurality of selector transistors,
wherein the gate driver supplies a second gate voltage to at least one of the plurality of gate voltage supplying wirings for each of the groups before supplying the first gate voltage that is used to turn on a pixel transistor disposed at an intersection portion of a data line among the plurality of data lines and a gate line among the plurality of gate lines,
wherein the second gate voltage is lower than the first gate voltage,
wherein the first gate voltage is Vgh1 and the second gate voltage is Vgh2, and the second gate voltage Vgh2 is set to satisfy (Vgh1)/3?Vgh2

US Pat. No. 10,249,256

DISPLAY PANEL HAVING A PLURALITY OF DISPLAY AREAS, A DISPLAY APPARATUS HAVING THE SAME AND A METHOD OF DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display panel comprising:a plurality of first pixel rows comprising a plurality of first pixels, wherein the plurality of first pixels is connected to a plurality of first data lines;
a plurality of second pixel rows comprising a plurality of second pixels, wherein the plurality of second pixels is connected to a plurality of second data lines disconnected from the plurality of first data lines;
a plurality of third pixel rows comprising a portion of the plurality of first pixels and a portion of the plurality of second pixels, wherein the plurality of third pixel rows is arranged between the plurality of fist pixel rows and the plurality of second pixel rows;
a plurality of gate lines crossing at least one of the first and second data lines; and
a plurality of cut portions disconnecting the plurality of first data lines and the plurality of second data lines,
wherein the plurality of cut portions is disposed in the plurality of third pixel rows.

US Pat. No. 10,249,255

METHOD FOR DRIVING DISPLAY PANEL HAVING A PLURALITY OF VOLTAGE LEVELS FOR GATE SCANNING SIGNALS

BOE TECHNOLOGY GROUP CO.,...

1. A method of driving gate lines of a display panel, comprising:generating a gate scanning signal; and
providing the gate scanning signal to a gate line of the display panel;
wherein the gate scanning signal comprises two or more high voltage levels in consecutive two or more time periods of a single scanning stage for turning on each of a plurality of thin film transistors coupled to the gate line;
the gate scanning signal comprises n numbers of high voltage levels stepwise changing from a first voltage level to a n-th voltage level respectively in n consecutive time periods of a single scanning stage for turning on each of a plurality of thin film transistors coupled to the gate line, n>3, and a n-th time period being a longest time period among the n consecutive time periods;
a non-zero difference between the n-th voltage level and a (n?1)-th voltage level among the n numbers of high voltage levels is set to be equal to a non-zero difference between a (n?1)-th voltage level and a (n?2)-th voltage level among the n numbers of high voltage levels;
the n-th voltage level, the (n?1)-th voltage level, and the (n?2)-th voltage level are different from each other, the n-th voltage level being greater than the (n?1)-th voltage level, and the (n?1)-th voltage level being greater than the (n?2)-th voltage level;
each of the n-th voltage level, the (n?1)-th voltage level, and the (n?2)-th voltage level is different from the first voltage level.

US Pat. No. 10,249,254

DEVICES AND METHODS FOR DISCHARGING OR HARVESTING VCOM CHARGE IN ELECTRONIC DISPLAYS

Apple Inc., Cupertino, C...

1. A method, comprising:while an electronic display is deactivated from displaying images, supplying an activation signal, via a voltage source, to an active switching device of the electronic display, wherein the active switching device is configured to discharge an aberrant charge on a common electrode of the electronic display; and
discharging the aberrant charge by way of the active switching device, wherein discharging the aberrant charge comprises preventing a possible occurrence of image artifacts from becoming apparent on the electronic display.

US Pat. No. 10,249,253

DISPLAY PANEL CONTROLLER TO CONTROL FRAME SYNCHRONIZATION OF A DISPLAY PANEL BASED ON A MINIMUM REFRESH RATE AND DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display panel controller comprising:a display driver integrated circuit configured to drive a display panel;
an application processor configured to provide the display driver integrated circuit with image data and a plurality of control signals generated by a timing controller;
an image analyzer determining a minimum refresh rate supported by the display panel by analyzing the image data and display characteristics of the display panel; and
a synchronization controller configured to control a frame synchronization of the display panel based on the determined minimum refresh rate of the display panel,
wherein the determining comprises:
decreasing a first refresh rate of the display panel to a second refresh rate when the display characteristics indicate the display panel is an Indium-Gallium-Zinc-Oxide display panel and the image data is still image data for implementing a still image; and
setting the minimum refresh rate to the second refresh rate.

US Pat. No. 10,249,252

COLOR CAST COMPENSATION METHOD

Shenzhen China Star Optoe...

1. A color cast compensation method, utilized for a triple-gate liquid crystal display (LCD) panel, the triple-gate LCD panel comprising a plurality of rows of gate lines and a plurality of columns of data lines, said method comprising the steps of:obtaining a first row and column position of a first pixel electrode currently to be charged and a first gray value of a portion of an image corresponding to the first pixel electrode;
determining, based on the first row and column position, a second row and column position of a second pixel electrode on a previous row sharing a same data line with the first pixel electrode, and obtaining a second gray value of the second pixel electrode that is stored in a row data buffer thereof; and
obtaining a target charging voltage of the first pixel electrode based on the first gray value and the second gray value, and charging the first pixel electrode according to the target charging voltage or charging the first pixel electrode according to a charging voltage corresponding to the first gray value, the target charging voltage making image brightness corresponding to the first pixel electrode achieve the brightness corresponding to the first gray value;
wherein obtaining the target charging voltage of the first pixel electrode based on the first gray value and the second gray value comprises:
inquiring a look up table by using the first gray value and the second gray value to obtain a compensation gray value of the first pixel electrode; and
obtaining, based on the compensation gray value, the charging voltage corresponding to the first pixel electrode and serving the same as the target charging voltage;
wherein after charging the first pixel electrode according to the target charging voltage, said method further comprises:
storing the first gray value in the row data buffer corresponding to the first pixel electrode and serving the same as gray value data of a previous row for a third pixel electrode on a next row, where the third pixel electrode and the first pixel electrode share a same data line;
wherein before obtaining the target charging voltage of the first pixel electrode based on the first gray value and the second gray value, and charging the first pixel electrode according to the target charging voltage or charging the first pixel electrode according to the charging voltage corresponding to the first gray value, said method further comprises:
obtaining N gray values of pixel electrodes in sequence on a row where the first pixel electrode is located on, in which N is an even number greater than or equal to 8, and sequentially taking every two adjacent entities of the N gray values as a group and subtracting the gray value of an even column and the gray value of an odd column in each group from each other to obtain N/2 first gray value differences S1 to SN/2;
sequentially taking every two adjacent entities of the N/2 first gray value differences as a group and subtracting the gray value of the even column and the gray value of the odd column in each group from each other to obtain N/4 second gray value differences E1 to EN/4; and
determining to charge the first pixel electrode according to the target charging voltage or to charge the first pixel electrode according to the charging voltage corresponding to the first gray value, based on the relationship between the N/4 second gray value differences E1 to EN/4 and a predetermined first gray value difference threshold and the relationship between the N/2 first gray value differences S1 to SN/2 and a predetermined second gray value difference threshold, where the second gray value difference threshold is greater than the first gray value difference threshold.

US Pat. No. 10,249,251

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device that is a reflective display device comprising:a display unit including a plurality of pixels performing color reproduction by combining outputs of sub-pixels of three or more colors including at least a first color, a second color, and a third color;
an illumination unit including a first light source that emits light in the first color to the display unit, a second light source that emits light in the second color to the display unit, and a third light source that emits light in the third color to the display unit;
a sensor that measures intensity of light in each color of the first color, the second color, and the third color included in external light that is light other than the light from the illumination unit out of the light emitted to the display unit; and
a signal processing unit that controls the intensity of the light to be emitted from each of the first light source, the second light source, and the third light source and controls gradation values of the respective sub-pixels based on the intensity of the external light measured by the measuring unit, wherein
the signal processing unit individually performs, on the sub-pixel of the first color, the sub-pixel of the second color, and the sub-pixel of the third color, processing of calculating a necessary luminance value for obtaining luminance that is N times a luminance value indicated by an input signal in a sub-pixel that performs output with a highest gradation value among the sub-pixels included in a predetermined image display region in the display unit, N being larger than 0,
the signal processing unit determines the intensity of the light to be emitted from each of the first light source, the second light source, and the third light source based on a comparison result between the necessary luminance value and the intensity of the light in each of the first color, the second color, and the third color included in the external light, and
the signal processing unit calculates an output gradation value of each of the sub-pixel of the first color, the sub-pixel of the second color, and the sub-pixel of the third color based on the following expressions (1), (2), and (3):
O1=I1×N/(OL1+IL1)  (1),
O2=I2×N/(OL2+IL2)  (2), and
O3=I3×N/(OL3+IL3)  (3),
where OL1 is the intensity of the light in the first color included in the external light, OL2 is the intensity of the light in the second color included in the external light, OL3 is the intensity of the light in the third color included in the external light, IL1 is the intensity of the light to be emitted from the first light source, IL2 is the intensity of the light to be emitted from the second light source, IL3 is the intensity of the light to be emitted from the third light source, I1 is the gradation value of the first color indicated by the input signal, I2 is the gradation value of the second color indicated by the input signal, I3 is the gradation value of the third color indicated by the input signal, O1 is the output gradation value for the sub-pixel of the first color, O2 is the output gradation value for the sub-pixel of the second color, and O3 is the output gradation value for the sub-pixel of the third color.

US Pat. No. 10,249,250

BACKLIGHT CONTROL METHOD, BACKLIGHT MODULE AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A backlight control method, comprising:dividing a backlight into N blocks, where N is an integer greater than 1;
determining whether each of the N blocks satisfies a high current driving start-up condition or not according to a pixel signal in each input frame of image signal, and determining blocks which satisfy the high current driving start-up condition as candidate blocks;
setting blocks among the candidate blocks which are determined to be driven by high current as selected blocks in a case that power consumption of each frame of picture does not exceed total backlight power consumption without dynamic backlight control; and
calculating backlight driving pulse width modulation duty ratios of the selected blocks according to a correspondence between brightness and pulse width modulation duty ratios, and transmitting the calculated backlight driving pulse width modulation duty ratios to a backlight driving circuit, to respectively drive the respective selected blocks in the backlight;
wherein setting blocks as selected blocks comprises:
calculating a pulse width modulation ratio Ptotal of the backlight without dynamic backlight control;
summing up pulse width modulation duty ratios of all the non-candidate blocks based on the pulse width modulation ratio Ptotal; and
setting the selected blocks based on the pulse width modulation ratio Ptotal, a sum of the pulse width modulation duty ratios of all the non-candidate blocks, and a pulse width modulation duty ratio corresponding to brightness of each candidate block.

US Pat. No. 10,249,249

SEMICONDUCTOR DEVICE, DISPLAY PANEL, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an error amplifier;
a voltage controlled oscillator;
a counter;
a first circuit; and
a terminal,
wherein the terminal is electrically connected to a non-inverting input terminal of the error amplifier,
wherein an inverting input terminal of the error amplifier is supplied with first voltage,
wherein an output terminal of the error amplifier is electrically connected to an input terminal of the voltage controlled oscillator,
wherein an output terminal of the voltage controlled oscillator is electrically connected to the counter,
wherein the first circuit is electrically connected to the output terminal of the voltage controlled oscillator and the terminal,
wherein the counter is configured to count the number of pulses of the signal and to output the number of the pulses,
wherein the first circuit comprises a second circuit, a first switch, a second switch, and a capacitor,
wherein the first switch is configured to control electrical continuity between the terminal and a first terminal of the capacitor,
wherein the second switch is configured to control electrical continuity between the first terminal of the capacitor and a second terminal of the capacitor, and
wherein the second circuit is configured to control on and off states of the first switch and the second switch.

US Pat. No. 10,249,248

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device, comprising:a display panel including a plurality of pixels each of which is connected to one of a plurality of data lines and one of a plurality of sensing lines;
a reference current source configured to provide a reference current; and
a source drive integrated circuit (IC), including a plurality of sensing units for sampling a signal input from a pixel through a sensing line and an analog-to-digital converter (ADC) connected to the plurality of sensing units, configured to provide a data voltage to the pixel through a data line, and obtain sensing data related to a driving of the pixel,
wherein the source drive IC further comprises a switch array connecting the plurality of sensing lines and the plurality of sensing units,
wherein the switch array in each sensing unit comprises a first switch for connecting a corresponding sensing unit to a first sensing line corresponding to the corresponding sensing unit, and a second switch for connecting the corresponding sensing unit to a second sensing line adjacent and previous to the first sensing line or the reference current source, and
wherein each sensing unit is connected to the first sensing line through the first switch to receive a first test current, and then connected to the second sensing line through the second switch to receive a second test current or connected to the reference current source through the second switch to receive the reference current, or
each sensing unit is connected to the second sensing line through the second switch to receive the second test current or connected to the reference current source through the second switch to receive the reference current, and then connected to the first sensing line through the first switch to receive the first test current.

US Pat. No. 10,249,247

TRANSPARENT DUAL-SIDED DISPLAY DEVICE AND DRIVING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A transparent dual-sided display device, comprising a display panel, a source driver electrically connected to the display panel, a timing controller electrically connected to both the source driver and the display panel, and a voltage controller electrically connected to both the timing controller and the source driver;wherein the display panel comprises a transparent substrate, a plurality of sub-pixel groups arranged in an array on the transparent substrate, and a plurality of multiplexer modules respectively corresponding to a plurality columns of the sub-pixel groups; the source driver comprises a plurality of output terminals respectively corresponding to the plurality of rows of sub-pixel groups; each of the sub-pixel groups comprises a front-side organic light emitting display (OLED) sub-pixel and a back-side OLED sub-pixel that are respectively arranged on two opposite sides of the transparent substrate and an electrowetting sub-pixel arranged on one of the sides of the transparent substrate; each of the multiplexer modules comprises a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor, the first thin-film transistor having a gate electrode input with a first control signal, a drain electrode electrically connected to all the front-side OLED sub-pixels of the sub-pixel groups of one of the columns corresponding thereto, and a source electrode electrically connected to one of the output terminals of the source driver corresponding thereto, the second thin-film transistor having a gate electrode input with a second control signal, a drain electrode electrically connected to all the back-side OLED sub-pixels of the sub-pixel groups of the one of the columns corresponding thereto, and a source electrode electrically connected to the one of the output terminals of the source driver corresponding thereto, the third thin-film transistor having a gate electrode input with a third control signal, a drain electrode electrically connected to all the electrowetting sub-pixel of the sub-pixel groups of the one of the columns corresponding thereto, and a source electrode electrically connected to the one of the output terminals of the source driver corresponding thereto;
wherein the voltage controller comprises a fourth thin-film transistor and a fifth thin-film transistor, the fourth thin-film transistor having a gate electrode input with a fourth control signal, a source electrode input with a second voltage, and a drain electrode electrically connected to a drain electrode of the fifth thin-film transistor and outputting a reference voltage to the source driver, the fifth thin-film transistor having a gate electrode input with a fifth control signal and a source electrode input with a first voltage; the first voltage is greater than the second voltage; each of the electrowetting sub-pixels is transparent upon application of the first voltage and blocks light upon application of the second voltage; and
wherein the timing controller is operable to receive an input data signal and generating and supplying a front-side output data signal and a back-side output data signal to the source driver, outputting the first, second, and third control signals to control the first, second, and third thin-film transistors to conduct on or cut off, outputting the fourth and fifth control signals to control a voltage value of the reference voltage output from the voltage controller, and outputting a source driving control signal to the source driver to control the source driver to output the front-side output data signal, the back-side output data signal, or the reference voltage.

US Pat. No. 10,249,246

GOA CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit, comprising a plurality of cascade GOA units, for a positive integer n, the n-th GOA unit comprising:a first thin film transistor (TFT), a gate of the first TFT connected to a constant high voltage, a first source/drain of the first transistor is directly connected to an signal output node of (n?2)th GOA unit, a second source/drain of the first transistor is directly connected to a first source/drain of a ninth TFT;
a ninth TFT, a gate of the ninth TFT connected to the signal output node of the (n?2)th GOA unit, and a second source/drain of the ninth transistor is directly connected to a third node;
a third TFT, a gate of the third TFT connected to the constant high voltage, a first source/drain of the third transistor is directly connected to an signal output node of (n+2)th GOA unit, a second source/drain of the third transistor is directly connected to a first source/drain of a tenth TFT;
a tenth TFT, a gate of the tenth TFT connected to the signal output node of the (n+2)th GOA unit, and a second source/drain of the tenth transistor is directly connected to the third node;
a seventh TFT, a gate of the seventh TFT connected to the third node, a source and a drain of the seventh transistor are directly connected respectively to a second node and a constant low voltage;
a sixth TFT, a gate of the sixth TFT connected to the second node, a source and a drain of the sixth transistor are directly connected respectively to the third node and the constant low voltage;
a fifth TFT, a gate of the fifth TFT connected to the constant high voltage, a source and a drain of the fifth transistor are directly connected respectively to the third node and the first node;
an eighth TFT, a gate of the eighth TFT inputted a second clock signal, a source and a drain of the eighth transistor are directly connected respectively to the second node and the constant high voltage;
a second TFT, a gate of the second TFT connected to the first node, a source and a drain of the second transistor are directly connected respectively to the signal output node of n-th GOA unit and an first clock signal;
a first capacitor, having the two ends connected respectively to the first node and the signal output node of n-th GOA unit;
a fourth TFT, a gate of the fourth TFT connected to the second node, a source and a drain of the fourth transistor are directly connected respectively to the signal output node of n-th GOA unit and the constant low voltage;
a second capacitor, having the two ends connected respectively to the second node and the constant low voltage.

US Pat. No. 10,249,245

COMPENSATION SYSTEM AND COMPENSATION METHOD FOR AMOLED

SHENZHEN CHINA STAR OPTOE...

1. A compensation system for active-matrix organic light-emitting diode (AMOLED) display, comprising a grayscale data conversion unit, a compensation unit electrically connected with the grayscale data conversion unit, a compensation data storage unit electrically connected with the compensation unit, a voltage data conversion unit electrically connected with the compensation unit; wherein the voltage data conversion unit is electrically connected with a source driver of the AMOLED display; the compensation data storage unit stores compensation voltage data and compensation ratio coefficient; wherein:the grayscale data converting unit being configured to input initial grayscale data and convert the initial grayscale data into initial driving voltage data corresponding to the initial grayscale data and transmit the initial driving voltage data to the compensation unit;
the compensation unit being configured to compensate the initial driving voltage data transmitted by the grayscale data conversion unit by using the compensation ratio coefficient and the compensation voltage data in the compensation data storage unit and output the compensation driving voltage data to the voltage data conversion unit;
the voltage data conversion unit being configured to convert the compensation driving voltage data transmitted by the compensation unit into compensation grayscale data and output the compensation grayscale data to the source driver of the AMOLED display.

US Pat. No. 10,249,244

CALIBRATION DEVICE AND METHOD AND ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. An organic light emitting display comprising: a display panel having a plurality of pixels; and a plurality of source driver ICs (integrated circuits) comprising sensing blocks connected to the pixels and sensing electrical characteristics of the pixels and a calibration block applying test currents to the sensing blocks; wherein the calibration block comprises a plurality of discrete current sources generating the test currents; and a switch array connecting the source driver ICs with discrete current sources of the calibration block, wherein two or more neighboring source driver ICs share one discrete current source, and each source driver IC is selectively connected to the plurality of discrete current sources.

US Pat. No. 10,249,243

GOA CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit, comprising a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises:a first thin film transistor, of which a source and a drain of the first transistor are directly coupled to a first node and inputted with a forward scan control signal, and as the nth level is not one of the first two levels, a gate is coupled to a signal output point of an n?2th level GOA circuit unit, otherwise, the gate is inputted with a first activation signal;
a third thin film transistor, of which a source and a drain of the third transistor are directly coupled to the first node and inputted with a backward scan control signal, and as the nth level is not one of the last two levels, a gate is coupled to a signal output point of an n+2th level GOA circuit unit, otherwise, the gate is inputted with a second activation signal;
a seventh thin film transistor, of which a gate is coupled to the first node, and a source and a drain of the seventh transistor are directly coupled to a fourth node and a constant low voltage level;
a sixth thin film transistor, of which a gate is coupled to the fourth node, and a source and a drain of the sixth transistor are directly coupled to the first node and the constant low voltage level;
a fifth thin film transistor, of which a gate is coupled to a first constant high voltage level, and a source and a drain of the fifth transistor are directly coupled to the first node and a second node;
an eighth thin film transistor, of which a gate is inputted with a first clock signal, and a source and a drain of the eighth transistor are directly coupled to the fourth node and the first constant high voltage level;
a ninth thin film transistor, of which a gate is inputted with a first control signal, and a source and a drain of the ninth transistor are directly coupled to a third node and inputted with a second clock signal;
a tenth thin film transistor, of which a gate is inputted with a second control signal, and a source and a drain of the tenth transistor are directly coupled to the third node and a second constant high voltage level;
a second thin film transistor, of which a gate is coupled to the second node, and a source and a drain of the second transistor are directly coupled to a signal output point of the nth level GOA circuit unit and the third node;
a first capacitor, of which two ends are respectively coupled to the second node and the signal output point of the nth level GOA circuit unit;
a fourth thin film transistor, of which a gate is coupled to a fourth node, and a source and a drain of the fourth transistor are directly coupled to the signal output point of the nth level GOA circuit unit and the constant low voltage level;
a second capacitor, of which two ends are respectively coupled to the fourth node and the constant low voltage level;
at work, as the first control signal is a high voltage level, the second control signal is a low voltage level; as the first control signal is the low voltage level, the second control signal is the high voltage level.

US Pat. No. 10,249,242

ORGANIC LIGHT EMITTING PIXEL DRIVING CIRCUIT, DRIVING METHOD AND ORGANIC LIGHT EMITTING DISPLAY PANEL

SHANGHAI TIANMA AM-OLED C...

1. An organic light emitting pixel driving circuit, comprising:a first capacitor, a second capacitor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a data line, a first scanning line, a second scanning line, a light emitting control line, a reference voltage line, an initialization voltage line, a light emitting element and a driving transistor;
wherein a second terminal of the second capacitor is connected to a gate of the driving transistor for storing a voltage transmitted to the gate of the driving transistor;
wherein a second terminal of the first capacitor is directly connected to the second electrode of the driving transistor;
wherein the fourth switching transistor is connected to the reference voltage line for transmitting a signal from the reference voltage line to the first capacitor based on a signal from the second scanning line, a gate of the fourth switching transistor is connected to the second scanning line, and a second electrode of the fourth switching transistor is connected to a first terminal of the first capacitor;
wherein the fifth switching transistor is connected to the second electrode of the driving transistor and an anode of the light emitting element to control the light emitting element to emit light based on a signal from the light emitting control line;
wherein the gates of the first switching transistor, the second switching transistor and the third switching transistor are connected to the first scanning line;
wherein a first electrode of the first switching transistor is connected to the gate of the driving transistor, a second electrode of the first switching transistor is connected to the second electrode of the driving transistor, a first electrode of the second switching transistor is connected to the initialization voltage line, a second electrode of the second switching transistor is connected to the anode of the light emitting element, a first electrode of the third switching transistor is connected to the data line, and a second electrode of the third switching transistor is connected to the first capacitor;
wherein the first switching transistor, the second switching transistor and the third switching transistor are used to reset a potential of the anode of the light emitting element, a potential of the gate of the driving transistor and a potential of the second electrode of the driving transistor based on a signal from the first scanning line, and to transmit a signal from the data line to the first capacitor;
wherein a cathode of the light emitting element is connected to a first power source voltage line; and
wherein a first electrode of the driving transistor is connected to a second power source voltage line.

US Pat. No. 10,249,241

METHOD AND DEVICE OF DRIVING DISPLAY AND DISPLAY DEVICE USING THE SAME

EverDisplay Optronics (Sh...

1. A method of driving a display, comprising:conducting first image data combined with image data relevant to the first image data in time/space by a micro disturbance operation processing, to obtain second image data; and
outputting the second image data,
wherein the image data relevant to the first image data in time/space is image data of two frames preceding the first image data, and
wherein the conducting first image data combined with image data relevant to the first image data in time/space by a micro disturbance operation processing comprises:
according to image data of an xth sub-pixel in a yth scanning line of an (n?1)th frame image and image data of an xth sub-pixel in a yth scanning line of an (n?2)th frame image, calculating a first time axis correction parameter;
according to image data of an xth sub-pixel in a yth scanning line of an nth frame image and image data of an xth sub-pixel in a yth scanning line of an (n?1)th frame image, calculating a second time axis correction parameter; and
according to the first image data combined with the first time axis correction parameter and the second time axis correction parameter, calculating and obtaining the second image data,
wherein the image data of the xth sub-pixel in the yth scanning line of the nth frame image is the first image data.

US Pat. No. 10,249,240

PIXEL DRIVE CIRCUIT

Wuhan China Star Optoelec...

1. A pixel drive circuit, wherein the pixel drive circuit comprises a plurality of cascading pixel drive units, and each pixel drive units comprising:a first resetting circuit connected to a first pixel for receiving an input voltage and resetting the first pixel;
a second resetting circuit connected to a second pixel for receiving an input voltage and resetting the second pixel;
a first controlling circuit connected to the first and the second resetting circuits for receiving a reference voltage and supplying the reference voltage to the first and second resetting circuits; and
a second controlling circuit connected to the first and the second resetting circuits for receiving data voltages and supplying the data voltages to the first and the second resetting circuits to drive the first and the second pixels simultaneously;
the first controlling circuit comprising a reference controllable switch, a controlling port of the reference controllable switch receiving light emission signals, a first port of the reference controllable switch receiving the reference voltage and a second port of the reference controllable switch connected to the second controlling circuit, the first and the second resetting circuits;
the first resetting circuit comprising a first, a second and a third controllable switches and a first capacitor, a first port of the first controllable switch receiving input voltages, a controlling port of the first controllable switch connected to a first port of the first capacitor, a second port of the first capacitor connected to a second port of the reference controllable switch, the second resetting circuit and the second controlling circuit, a second port of the first controllable switch connected to a first port of the second controllable switch and a first port of the third controllable switch, a controlling port of the second controllable switch receiving first scanning signals, a second port of the second controllable switch connected to the first port of the first capacitor and the controlling port of the first controllable switch, a controlling port of the third controllable switch receiving light emission signals, a second port of the third controllable switch connected to the anode of the first pixel, a cathode of the first pixel connected to a ground;
the second resetting circuit comprising a fourth, a fifth and a sixth controllable switches and a second capacitor, a first port of the fourth controllable switch receiving input voltages, a controlling port of the fourth controllable switch connected to a first port of the second capacitor, a second port of the second capacitor connected to the second port of the first capacitor, the second port of the reference controllable switch and the second controlling circuit, a second port of the fourth controllable switch connected to a first port of the fifth controllable switch and a first port of the sixth controllable switch, a controlling port of the fifth controllable switch receiving second scanning signals, a second port of the fifth controllable switch connected to the first port of the second capacitor and the controlling port of the fourth controllable switch, a controlling port of the sixth controllable switch receiving light emission signals, a second port of the sixth controllable switch connected to the anode of the second pixel, a cathode of the second pixel connected to a ground;
the first resetting circuit or the second resetting circuit further comprising a seventh controllable switch, a controlling port of the seventh controllable switch receiving resetting signals, a first port of the seventh controllable switch receiving input voltages, a second port of the seventh controllable switch connected to the first port of the first controllable switch and the first port of the fourth controllable switch;
the first resetting circuit further comprising an eighth controllable switch, a controlling port the eighth controllable switch receiving resetting signals, a first port of the eighth controllable switch receiving initial signals, a second port of the eighth controllable switch connected to the controlling port of the first controllable switch and the first port of the first capacitor;
the second resetting circuit further comprising a ninth controllable switch, a controlling port the ninth controllable switch receiving resetting signals, a first port of the ninth controllable switch receiving initial signals, a second port of the ninth controllable switch connected to the controlling port of the fourth controllable switch and the first port of the second capacitor.

US Pat. No. 10,249,239

DRIVING CIRCUIT OF PIXEL UNIT AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A driving circuit of pixel unit, configured to drive sub-pixel units on a display panel and comprising a power supply port connected to the sub-pixel units through power supply signal lines, the power supply port being configured to transfer a power supply voltage, which is output by a power supply and distinguished from a data voltage, to each of the sub-pixel units through the power supply signal lines, whereinthe display panel comprises a plurality of pixel regions, each of the plurality of pixel regions comprising a plurality of subpixel units,
each of the power supply signal lines has a first terminal and a second terminal with no circuit element connected therebetween, the first terminal being connected to the power supply port, and the second terminal being connected to one of the subpixel units,
the driving circuit of pixel unit further comprises a plurality of compensation units, each of the plurality of compensation units corresponding to one of the plurality of pixel regions and being configured to, acquire, when the sub-pixel units in the one of the plurality of pixel regions display different gray levels according to different data voltages, an average value of currents on at least part of the power supply signal lines according to current values, acquired through the second terminals of the power supply signal lines, on the at least part of the power supply signal lines in the one of the plurality of pixel regions, and then convert the average value of the currents into a compensating voltage, transfer the compensating voltage to the power supply signal lines in the one of the plurality of pixel regions and apply the compensating voltage to the first terminals of the power supply signal lines connected to the subpixel units of the one of the plurality of pixel regions, to compensate the voltage drop on each of the power supply signal lines in the one of the plurality of pixel regions.

US Pat. No. 10,249,238

PIXEL DRIVING CIRCUIT, ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME, AND DRIVING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A pixel driving circuit configured to operate in a display cycle including sequentially an initialization period, a compensation period, and a light-emitting period, the pixel driving circuit comprising:a driving transistor having a gate, a source, and a drain;
a first storage capacitor having a first terminal connected to the gate of the driving transistor and a second terminal connected to a first power signal input port;
an emission control sub-circuit disposed between the source of the driving transistor and the first power signal input port, the emission control sub-circuit comprising a first emission-control transistor, the first emission-control transistor having a first terminal connected to the first power signal input port, and a second terminal connected to the source of the driving transistor;
a data write-in sub-circuit disposed between a data input port and the drain of the driving transistor which is also connected to the emission control sub-circuit, the data write-in sub-circuit being connected to the driving transistor through the drain of the driving transistor;
a compensation sub-circuit disposed between the source of the driving transistor and the first terminal of the first storage capacitor, the compensation sub-circuit being connected to the driving transistor through the source of the driving transistor; and
a light emitting device having a first terminal connected to the emission control sub-circuit and a second terminal connected to a second power signal input port;
wherein the data write-in sub-circuit is configured to control a data voltage signal to be passed into the drain of the driving transistor during the compensation period; the compensation sub-circuit is configured to control a connection between the source and the gate of the driving transistor during the compensation period to set the driving transistor to a conduction state for inducing a source-to-drain current until a gate voltage of the driving transistor reaches a value substantially equal to the data voltage signal plus a threshold voltage of the driving transistor.

US Pat. No. 10,249,237

SYSTEMS AND METHODS FOR DISPLAY SYSTEMS WITH DYNAMIC POWER CONTROL

Ignis Innovation Inc., W...

1. A system for driving a display, the system comprising:a plurality of groups of pixel circuits arranged in an array, each of said pixel circuits comprising a light emitting device and a driving transistor for conveying a driving current through the light emitting device;
a plurality of supply lines each coupled to at least one of said groups of pixel circuits;
a plurality of voltage sources each coupled to at least one of said plurality of supply lines; and
a controller configured to determine when said display is to be in a standby mode and, when said display is in said standby mode, to reduce the voltage supplied to a selected one of said groups of pixel circuits for dimming the selected group of pixel circuits providing a region of subdued brightness, and to turn off the voltage supplied to other groups of pixel circuits.

US Pat. No. 10,249,236

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS INCLUDING AN AUXILIARY GATE ELECTRODE

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting display apparatus comprising:a substrate;
an active layer disposed on the substrate, wherein the active layer comprises a source region, a drain region, and a channel region disposed between the source region and the drain region;
a gate electrode overlapping the channel region, wherein a gate voltage is applied to the gate electrode;
an auxiliary gate electrode disposed between the gate electrode and the channel region, and to which a first voltage is applied; and
a first thin-film transistor comprising the active layer, the auxiliary gate electrode, and the gate electrode, wherein the first thin-film transistor is turned on or off according to the gate voltage, and the gate voltage is different from the first voltage.

US Pat. No. 10,249,235

TIMING CONTROLLER, ELECTRONIC APPARATUS USING THE SAME, IMAGE DATA PROCESSING METHOD

ROHM CO. LTD., Kyoto (JP...

1. A timing controller, configured to receive pixel data constituting image data and an external pixel clock accompanying with the pixel data from a graphic controller and output to a data driver, and comprising:a line memory, capable of retaining at least the pixel data of one line;
an input interface circuit, for receiving the pixel data and storing the pixel data in the line memory;
a frequency synthesizer, for receiving the external pixel clock received by the input interface circuit and generating an internal pixel clock having a frequency being a coefficient K (K is a real number) multiplied by a frequency of the external pixel clock;
an image processing circuit, for processing the pixel data stored in the line memory synchronously with the internal pixel clock;
wherein the image processing circuit receives the internal pixel clock from the frequency synthesizer; and
an output interface circuit, for transmitting the pixel data processed by the image processing circuit to a source driver synchronously with the internal pixel clock.

US Pat. No. 10,249,234

DATA DRIVING APPARATUS AND DISPLAY DEVICE USING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A data driver comprising:a plurality of first output channels connected to a plurality of data lines;
a plurality of second output channels; and
a data driving integrated circuit IC that receives image data of one frame unit according to an image data signal and a data control signal, receives an output channel on/off data based on a channel selection data, and generates a plurality of data signals and a plurality of dummy signals according to the image data of one frame unit, and that switches a plurality of first switches transmitting the plurality of data signals to the plurality of first output channels and a plurality of second switches transmitting the plurality of dummy signals to the plurality of second output channels,
wherein the image data signal includes the channel selection data related to the plurality of first output channels and the plurality of second output channels,
wherein the channel selection data comprises information for arranging the plurality of first output channels and the plurality of second output channels,
wherein the channel selection data is arranged in the data sequence prior to the image data of one frame unit including a plurality of line image data, and
wherein normal image data and dummy image data are arranged in each line image data, according to the channel selection data,
wherein the data driving IC comprises:
a first latch that latches the image data of one frame unit to at least one channel unit and that outputs a latched image data;
a second latch that latches the output channel on/off data and that outputs a latched output channel on/off data to the plurality of second switches; and
a digital-analog converter that converts the latched image data into the plurality of data signals and the plurality of dummy signals and that outputs the plurality of data signals and the plurality of dummy signals, and including the plurality of first switches.

US Pat. No. 10,249,233

GATE DRIVING CIRCUIT AND DISPLAY DEVICE

HannStar Display Corporat...

1. A gate driving circuit for driving a display panel, the gate driving circuit comprising:1st to 4th stage first dummy shift registers configured to respectively generate and output 1st to 4thstage first dummy scan signals, wherein the 1st to 4th stage first dummy shift registers are disposed at one side of the display panel; and
1st to Nth stage first shift registers configured to respectively generate and output 1st to Nth stage first scan signals to a plurality of scan lines of the display panel, wherein N is an integer;
wherein the 1st to 4th stage first dummy scan signals are generated before theist stage first scan signal is generated, wherein time durations required for the 1st to 4th stage first dummy scan signals to rise from a low level to a high level are defined as 1st to 4th time durations, respectively, wherein each of the 1st and 2nd time durations is greater than each of the 3rd and 4th time durations.

US Pat. No. 10,249,232

DISPLAY PANEL DRIVER SETTING METHOD, DISPLAY PANEL DRIVER, AND DISPLAY APPARATUS INCLUDING THE SAME

LAPIS Semiconductor Co., ...

1. A display panel driver setting method for setting a plurality of display panel drivers in accordance with specifications based on setting data stored in a memory, the plurality of display panel drivers being configured to drive a display panel that displays an image corresponding to a video signal, the method comprising:causing one of the display panel drivers to supply, to the memory and to the remainder of the display panel drivers, a memory access signal indicative of only one of either a readout instruction to read the setting data from the memory or a write instruction to write the setting data to the memory;
causing said one display panel driver to fetch the setting data, which is read from the memory and provided on a first line, to perform setting based on the setting data; and
causing said remainder of the display panel drivers to fetch the setting data from the first line to perform the setting based on the setting data, when the memory access signal supplied from said one display panel driver is indicative of the readout instruction.

US Pat. No. 10,249,231

DISPLAY DEVICE AND OPTICAL COMPENSATION METHOD OF A DISPLAY DEVICE

Samsung Display Co., Ltd....

1. An optical compensation method for a display device comprising a plurality of pixels, the method comprising:providing test data having a first grayscale value to the display device;
measuring a luminance of the pixels which emit light based on the test data;
calculating a unique compensation grayscale value for each of the pixels based on a second target luminance and the measured luminance of each of the pixels, the second target luminance being lower than a first target luminance which is set based on the first grayscale value;
re-measuring the luminance of the pixels which emit light based on a first compensated grayscale value which is generated by compensating the first grayscale value by the compensation grayscale value; and
calculating a luminance difference between the re-measured luminance and the first target luminance.

US Pat. No. 10,249,230

METHOD OF IMAGE PROCESSING, IMAGE PROCESSOR PERFORMING THE METHOD, AND DISPLAY DEVICE INCLUDING THE IMAGE PROCESSOR

SAMSUNG DISPLAY CO., LTD....

1. An image processor comprising:an average luminance calculator which calculates an average luminance of a current frame based on a first average luminance of input image data corresponding to a partial screen and a second average luminance of previous image data corresponding to an entire screen, the previous image data stored in a frame memory;
a conversion curve generator which generates a luminance conversion curve based on the average luminance;
a luminance converter which generates conversion image data by converting luminance data of the input image data based on the luminance conversion curve; and
an image merger which generates output image data by merging the conversion image data and the previous image data,
wherein the average luminance calculator receives position data of the input image data, calculates a resolution ratio of the partial screen to the entire screen, which is a ratio of a height of the partial screen to a height of the entire screen, a ratio of a width of the partial screen to a width of the entire screen, or a ratio of a size of the partial screen to a size of the entire screen, based on the position data, and sets a weighted average of the first average luminance and the second average luminance according to the resolution ratio as the average luminance.

US Pat. No. 10,249,229

POWER SWITCHING CIRCUIT AND METHOD FOR CONTROLLING SAME

Silicon Works Co., Ltd., ...

1. A power switching circuit, comprising:a frequency control circuit configured to:
receive a first reference signal starting operation of driving a load, from a timing controller, wherein the first reference signal is related to the timing information of the operation of the driving load; and
generate a second reference signal based on the first reference signal;
a pulse modulation circuit configured to generate a pulse control signal by performing pulse width modulation (PWM) or pulse frequency modulation (PFM) on the second reference signal; and
a switching convertor configured to generate a voltage of output power by switching a switching element connected to the output power, in response to the pulse control signal;
wherein the pulse control signal is synchronized with the first reference signal starting the operation of driving the load.

US Pat. No. 10,249,228

APPARATUS AND METHOD FOR ADJUSTING COLOR OF DISPLAY APPARATUS

DB HiTek Co., Ltd., Seou...

1. A display apparatus with a color adjustment function, comprising:a converter receiving image pixel values corresponding to three primary colors and converting the image pixel values into tri-stimulus values;
a first maximum value unit receiving the image pixel values and outputting a maximum value of the image pixel values as a first maximum value;
a second maximum value unit receiving the tri-stimulus values from the converter and outputting a maximum value of the tri-stimulus values as a second maximum value;
a gain adjuster receiving the first and second maximum values from the first and second maximum value units and outputting a gain adjustment corresponding to the first maximum value and the second maximum value; and
a gain applier receiving the tri-stimulus values from the converter and the gain adjustment from the gain adjuster and outputting a color adjustment value corresponding to the tri-stimulus values and the gain adjustment.

US Pat. No. 10,249,227

SCANNING DRIVING CIRCUITS HAVING CHARGE SHARING AND DISPLAY PANELS

Shenzhen China Star Optoe...

1. A scanning driving circuit having charge sharing, comprising:a driving unit configured to receive a previous scanning signal Gn?1, a current clock signal Ckn, and a next scanning signal Gn+1, and to generate a current scanning signal Gn according to the previous scanning signal, the current clock signal and the next scanning signal, wherein n is an integer;
a pull-down maintain unit connecting to the driving unit and configured to conduct a pull down process with respect to a pull down controlling signal point of the driving unit;
a share unit connecting to the driving unit and the pull-down maintain unit, wherein the share unit is configured to receives first clock signal, a second clock signal, a first voltage signal, and a second voltage signal, and to control an electric potential of a rising edge and a falling edge of the current scanning signal via the first clock signal, the second clock signal, the first voltage signal, and the second voltage signal, so as to reduce a scanning-driving-circuit compensation voltage.

US Pat. No. 10,249,226

DISPLAY DEVICE AND METHOD OF TUNING A DRIVER

SAMSUNG DISPLAY CO., LTD....

1. A method of driving a display device, comprising:outputting sequentially a plurality of eye tuning signals;
receiving a plurality of checking information obtained from a data driving circuit,
wherein the checking information indicates whether the data driving circuit is operating in an ON state in response to each of the plurality of eye tuning signals; and
selecting one optimal eye tuning signal from among the plurality of eye tuning signals operating the data driving circuit based on the checking information, wherein a plurality of image signals is output based on a condition information of the optimal eye tuning signal,
wherein selecting the one optimal eye tuning signal comprises (i) selecting one eye tuning signal having an intermediate value among three or more odd-number eye tuning signals that are consecutive, or (ii) selecting one eye tuning signal of first and second eye tuning signals closest to an intermediate value among two or more even-number eye tuning signals that are consecutive.

US Pat. No. 10,249,225

OVERCURRENT DETECTION CIRCUIT

Rohm Co., Ltd., Kyoto (J...

1. An overcurrent detection circuit arranged to detect overcurrent of a load driving device that drives a capacitance load by switching a voltage applied to the capacitance load between high level and low level, the overcurrent detection circuit comprising:a clock signal generation unit arranged to generate a clock signal;
a comparing unit arranged to compare a physical quantity corresponding to current supplied from the load driving device to the capacitance load with a predetermined value; and
a determination unit arranged to determine whether or not the load driving device is in an overcurrent state based on the clock signal and a result of the comparison by the comparing unit, during a period in which the load driving device applies a high level voltage to the capacitance load, wherein
the determination unit determines whether or not the load driving device is in an overcurrent state based on the number of clocks in the clock signal during a first interval in one continuous period in which the load driving device applies a high level voltage to the capacitance load, and
the physical quantity corresponding to current supplied from the load driving device to the capacitance load is a predetermined value or more in the first interval.

US Pat. No. 10,249,224

IMAGE SUPPLY DEVICE, METHOD OF CONTROLLING IMAGE SUPPLY DEVICE, AND PROGRAM

SEIKO EPSON CORPORATION, ...

1. An image supply device comprising:a processor programmed to function as:
an image acquisition section adapted to obtain an image data and transmit the obtained image data to an image transfer section, the image acquisition section transmitting the obtained image data at a first acquisition frame rate for transmitting data per unit time of outputting the obtained image data; and
the image transfer section adapted to transmit the image data received from the image acquisition section to an external device, wherein
the image transfer section outputs information related to a processing capacity of the image transfer section to the image acquisition section,
the image acquisition section changes the first acquisition frame rate to a second acquisition frame rate based on the information related to the processing capacity of the image transfer section.

US Pat. No. 10,249,223

LIGHT FLUX CONTROLLING MEMBER, LIGHT EMITTING DEVICE AND ILLUMINATION APPARATUS

ENPLAS CORPORATION, Sait...

1. A light flux controlling member configured to control a distribution of light emitted from a light emitting element, the light flux controlling member disposed such that a central axis of the light flux controlling member coincides with an optical axis of the light emitting element, the light flux controlling member comprising:an incidence surface configured such that light emitted from the light emitting element is incident on the incidence surface, the incidence surface being an inner surface of a recess disposed on a side of the light flux controlling member closer to the light emitting element to intersect with the central axis;
a reflection surface configured to reflect part of the light incident on the incidence surface, the reflection surface being disposed to surround the central axis; and
an emission surface configured to emit the light incident on the incidence surface, the emission surface being disposed on an opposite side of the light flux controlling member from the incidence surface to intersect with the central axis,
wherein the incidence surface comprises:
a top surface in the recess, and
a side surface connecting an outer edge of the top surface with an opening edge of the recess;
wherein the top surface is divided by a first plane including the central axis into a first top surface and a second top surface, the second top surface including a first divided top surface and a second divided top surface, the first divided top surface being disposed between the first top surface and the second divided top surface;
wherein the emission surface is divided by the first plane into a first emission surface and a second emission surface, each of the first emission surface and the second emission surface including a plurality of linear segments;
wherein the first top surface and the first emission surface are disposed on a same side with respect to the first plane;
wherein a first angle between the first top surface and central axis is an acute angle and is smaller than a second angle formed between the second divided top surface and the central axis; a third angle between the first emission surface and central axis is an acute angle and is smaller than a fourth angle formed between the second emission surface and the central axis; and wherein
the plurality of liner segments of the first emission surface and the second emission surface are different in their linear length.

US Pat. No. 10,249,222

LABELS AND METHODS OF PRODUCING THE SAME

1. An apparatus comprising:a first substrate, wherein the first substrate has a first side opposite a second side;
a second substrate including a liner;
a first adhesive disposed on the first side of the first substrate;
a transfer tape having a second adhesive wherein the second adhesive comprises adhesive portions on opposite sides of a film of the transfer tape, wherein the transfer tape couples the first substrate and the second substrate and is disposed such that the first adhesive is intermediate the first substrate and the second adhesive; and
a tag coupled to the first substrate and including a remaining portion and a removable portion, the remaining portion is disposed adjacent to the first adhesive and the removable portion is disposed adjacent to the second adhesive;
wherein the second adhesive is adjacent to the remaining portion of the tag and the first adhesive.