US Pat. No. 10,170,460

VOLTAGE BALANCED STACKED CLAMP

International Business Ma...

1. An apparatus for balancing voltages, comprising:a voltage supply pin operatively connected to a voltage divider, wherein the voltage supply pin supplies a total voltage to the voltage divider;
a stacked circuit operatively connected to the voltage divider, wherein the stacked circuit comprises a first layer and a second layer, wherein the first layer is not coupled to the second layer, and the voltage divider distributes the total voltage as to the stacked circuit;
a voltage grounder operatively connected to the voltage divider and wherein the first layer and the second layer comprise:
a group of inverters within the first layer operatively connected to a first n-type channel field effect transistor (NFET), wherein the group of inverters within the first layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the first n-type channel field effect transistor (NFET); and
a group of inverters within the second layer operatively connected to a second n-type channel field effect transistor (NFET), wherein the group of inverters within the second layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the second n-type channel field effect transistor (NFET); and
a third node, wherein the third node is point (principal nodes or junctions) coupled to a first p-type field effect transistor (PFET) at a gate terminal of the first PFET, the second inverter, and the third inverter of the first layer.

US Pat. No. 10,170,459

METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING A FLOATING ESD NODE

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:providing a substrate including a first-type well area in an electrostatic discharge (ESD) region;
forming a base junction of the first-type along the perimeter of the ESD region;
forming a shallow trench isolation (STI) region adjacent the base junction;
forming alternate emitter and collector junctions of a second-type adjacent the STI region, parallel to and spaced from each other by parallel additional STI regions;
forming at least one gate perpendicular to and over a collector junction;
epitaxially forming a floating ESD node of the first-type in the collector junction adjacent one side of the at least one gate; and
determining a gate-length based on a target ESD event trigger-voltage, wherein a shorter gate-length reduces the trigger-voltage such that the ESD region is activated at a lower voltage.

US Pat. No. 10,170,458

MANUFACTURING METHOD OF PACKAGE-ON-PACKAGE STRUCTURE

Powertech Technology Inc....

1. A manufacturing method of a package-on-package (POP) structure, comprising:forming a first package structure, wherein the first package structure comprises a circuit carrier and a die disposed on the circuit carrier, forming the first package structure comprising:
providing a conductive interposer on the circuit carrier, wherein the conductive interposer comprises a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die, the conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier, wherein the plate of the conductive interposer comprises a central region and a peripheral region connected to the central region, the conductive protrusion is formed in the central region and the conductive pillars are formed in the peripheral region;
encapsulating the conductive interposer by an encapsulant; and
removing a portion of the encapsulant and the plate of the conductive interposer; and
forming a second package structure on the first package structure, wherein the second package structure is electrically connected to the first package structure through the conductive interposer.

US Pat. No. 10,170,457

COWOS STRUCTURES AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:attaching a first die and a second die to an interposer;
attaching a first substrate to a first surface of the first die and a first surface of the second die, the first substrate comprising silicon, the first surface of the first die being opposite to a second surface of the first die that is attached to the interposer, and the first surface of the second die being opposite to a second surface of the second die that is attached to the interposer;
forming a plurality of electrical connectors over the interposer, each electrical connector of the plurality of electrical connectors being electrically connected to a respective through via of a plurality of through vias comprised in the interposer, wherein the first substrate physically supports the interposer during the forming of the plurality of electrical connectors;
bonding the interposer to a second substrate using the plurality of electrical connectors; and
attaching a heat dissipation lid to the second substrate, the interposer being disposed in an inner cavity of the heat dissipation lid.

US Pat. No. 10,170,456

SEMICONDUCTOR PACKAGES INCLUDING HEAT TRANSFERRING BLOCKS AND METHODS OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semiconductor chips,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via is electrically isolated from the interconnection layer and the first and second semiconductor chips.

US Pat. No. 10,170,454

METHOD AND APPARATUS FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICE DIE FROM A MAPPED WAFER

1. A system for performing a direct transfer of a plurality of semiconductor die from a first substrate to a second substrate, the system comprising:a first conveyance mechanism to convey the first substrate;
a second conveyance mechanism to convey the second substrate;
a transfer mechanism disposed adjacent to the first conveyance mechanism to effectuate the direct transfer;
a controller including one or more processors communicatively coupled with the first conveyance mechanism, the second conveyance mechanism, and the transfer mechanism, the controller having executable instructions, which when executed, cause the one or more processors to perform operations including:
determining positions of the plurality of semiconductor die based at least in part on map data, the map data describing the positions of the plurality of semiconductor die of a semiconductor wafer,
conveying at least one of the first substrate or the second substrate such that the first substrate, the second substrate, and the transfer mechanism are in a direct transfer position, and
activating the transfer mechanism to perform the direct transfer of the plurality of semiconductor die.

US Pat. No. 10,170,453

ARRANGEMENT AND METHOD FOR GENERATING MIXED LIGHT

OSRAM OPTO SEMICONDUCTORS...

1. An arrangement for generating mixed light, comprising:a first device;
a second device; and
a third device,
the first device having a first semiconductor chip for generating a first primary radiation in the blue spectral range and having a first conversion element for generating a first secondary radiation from the first primary radiation, wherein a first total radiation exiting the first device has a first chromaticity coordinate, which lies within a color quadrilateral having the corner points (0.300, 0.425), (0.308, 0.439), (0.388, 0.407) and (0.370, 0.390) or (0.322, 0.482), (0.330, 0.500), (0.384, 0.450) and (0.375, 0.432) or (0.335, 0.345), (0.335, 0.365), (0.355, 0.365) and (0.355, 0.345),
the second device having a second semiconductor chip for generating a second primary radiation in the blue spectral range and having a second conversion element for generating a second secondary radiation from the second primary radiation, wherein a second total radiation exiting the second device has a second chromaticity coordinate, which lies within a color quadrilateral having the corner points (0.325, 0.225), (0.350, 0.225), (0.350, 0.275) and (0.325, 0.275) or (0.350, 0.325), (0.365, 0.325), (0.350, 0.340) and (0.365, 0.340) or (0.445, 0.309), (0.457, 0.318), (0.425, 0.325) and (0.439, 0.337), and
the third device having a third semiconductor chip for generating a third primary radiation in the blue spectral range and having a third conversion element for generating a third secondary radiation from the third primary radiation, wherein a third total radiation exiting the third device has a third chromaticity coordinate, which lies within a color quadrilateral having the corner points (0.475, 0.400), (0.425, 0.400), (0.425, 0.440) and (0.475, 0.440) or (0.515, 0.420), (0.495, 0.420), (0.515, 0.450) and (0.495, 0.450) or (0.425, 0.465), (0.425, 0.475), (0.440, 0.475) and (0.440, 0.465).

US Pat. No. 10,170,452

PIXEL UNIT STRUCTURE AND MANUFACTURING METHOD THEREOF

1. A pixel unit structure, comprising:a display medium module comprising a first electrode, a second electrode and a display medium, wherein the first electrode and the second electrode are separated from each other, and the display medium is disposed between the first electrode and the second electrode; and
an active switching element electrically connected to the first electrode for allowing the first electrode and the second electrode to change the state of the display medium, wherein the active switching element comprises a wafer portion and a transistor portion with the transistor portion formed on the wafer portion, and the wafer portion is part of a silicon wafer, gallium arsenide wafer, sapphire wafer, indium phosphide wafer or gallium nitride wafer.

US Pat. No. 10,170,451

SEMICONDUCTOR DEVICE METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;
exposing the first set of through vias and the reference via with a planarization process on a first side of the semiconductor die;
connecting the first set of through vias on a second side of the semiconductor die opposite the first side to a second semiconductor die; and
after the connecting the first set of through vias, exposing a first surface of the reference via with a singulation process.

US Pat. No. 10,170,450

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

IMEC vzw, Leuven (BE)

1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate, wherein each IC device comprises a dielectric bonding layer at its outer surface, and wherein each IC device further comprises one or more metal contact structures, the method comprising:producing at least one cavity in the outer surface of the first IC device, the cavity traversing at least the dielectric bonding layer of the first IC device;
aligning the first substrate with respect to the second substrate, and forming a substrate assembly by direct bonding between the dielectric bonding layers, so that in the substrate assembly the cavity formed in the first IC device overlaps a metal contact structure of the second IC device;
after bonding, optionally thinning the first substrate;
producing a Through Substrate Via (TSV) opening in the first substrate, the TSV opening overlapping the cavity;
forming an aggregate opening comprising the TSV opening and the cavity, thereby exposing at least part of the metal contact structure of the second IC device;
after the formation of an isolation liner on at least part of the sidewalls of the aggregate opening, producing a metal interconnection plug in the aggregate opening, that contacts the metal contact structure of the second IC device, and forms at least part of an interconnection path between the metal contact structure of the second IC device and a metal contact structure of the first IC device, wherein the first IC device comprises a stack of dielectric layers with the dielectric bonding layer being present on top of the stack of dielectric layers, wherein the cavity further traverses one or more of the stack of dielectric layers, wherein the first IC device comprises a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, and wherein the stack of dielectric layers comprises a stack of intermetal dielectric layers in the BEOL portion, or in the BEOL portion as well as in the FEOL portion of the first IC device.

US Pat. No. 10,170,449

DEFORMABLE CLOSED-LOOP MULTI-LAYERED MICROELECTRONIC DEVICE

International Business Ma...

1. A deformable closed-loop multi-layered microelectronic device comprising:a top layer comprising at least a first section and a second section, wherein the first section and the second section of the top layer are pivotable with respect to each other to deform the top layer;
a bottom layer comprising at least a first section and a second section, wherein the first section of the bottom layer is vertically aligned with the first section of the top layer and the second section of the bottom layer is vertically aligned with the second section of the top layer, wherein the first section and the second section of the bottom layer are pivotable with respect to each other to deform the bottom layer; and
a middle layer disposed between the top layer and the bottom layer, the middle layer comprising at least a first section and a second section, wherein the first section and the second section of the middle layer are pivotable with respect to each other to deform the middle layer,
wherein the middle layer comprises a first pivot provided to a first terminal end of the first section of the middle layer for allowing the first section to rotate about the first pivot, wherein the first terminal end of the first section of the middle layer is vertically sandwiched between a first terminal end of the first section of the top layer and a first terminal end of the first section of the bottom layer; and
wherein the first pivot is connected to the first terminal end of the first section of the bottom layer through a first adhesive and connected to the first terminal end of the first section of the top layer through a second adhesive, such that the first section of the bottom layer and the first section of the top layer are pivotable in a substantially synchronized manner to deform the bottom layer and the top layer in a substantially synchronized manner.

US Pat. No. 10,170,448

APPARATUS AND METHOD OF POWER TRANSMISSION SENSING FOR STACKED DEVICES

Micron Technology, Inc., ...

1. An apparatus comprising:a substrate;
a plurality of dies, each die of the plurality of dies comprising:
a circuit;
a first conductive via through each die, configured to provide a power supply voltage;
an on-die bus coupled to the first conductive via and configured to provide the power supply voltage from the first conductive via to the circuit;
a second conductive via through each die; and
a switch disposed between the on-die bus and the second conductive via, configured to selectively couple the on-die bus to the second conductive via,
a first conductive path across the substrate and the plurality of dies, configured to provide the power supply voltage to the first conductive via, the first conductive path comprising:
a first bump between the substrate and the plurality of dies, coupled to a corresponding first conductive via of a die of the plurality of dies adjacent to the substrate and the first bump configured to provide the power supply voltage to the corresponding first conductive via;
a plurality of the first pillars configured to couple the first conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of first conductive vias; and
a second conductive path across the substrate and the plurality of dies, the second conductive path comprising:
a second bump between the substrate and the plurality of dies, coupled to a corresponding second conductive via of the die of the plurality of dies adjacent to the substrate;
a plurality of second pillars configured to couple the second conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of the second conductive vias.

US Pat. No. 10,170,447

ADVANCED CHIP TO WAFER STACKING

International Business Ma...

1. A method of forming a 3D chip stack comprising:forming a first bonding layer on a top surface of a first wafer, the first wafer comprising first chips having an upper surface coplanar with the top surface of the first wafer;
forming a second bonding layer on a top surface of a second wafer, the second wafer comprising second chips having an upper surface coplanar with the top surface of the second wafer;
separating the second chips from the second wafer;
placing the separated second chips in loading bays of a vacuum chuck, wherein a location of each of the loading bays is in a corresponding position to each of the first chips on the first wafer, the separated second chips are held in the loading bays using vacuum suction to a surface of the separated second chips opposite the second bonding layer, and each loading bay of the vacuum chuck comprises a plurality of moveable columns together providing a curved contact surface to hold the separated second chips;
bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process creating a third bonding layer, wherein the third bonding layer includes the first bonding layer and the second bonding layer; and
depositing a dielectric over the bonded first chips and second chips.

US Pat. No. 10,170,446

STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT

INTERNATIONAL BUSINESS MA...

1. A method forming an interconnect structure, the method comprising:depositing a first solder bump on a chip;
depositing a second solder bump on a laminate, the second solder bump comprising a nickel copper colloid;
joining the chip to the laminate;
depositing an underfill material around the first solder bump and the second solder bump; and
performing a reflow process at a temperature that is lower than a temperature used to join the chip to the laminate to convert the first solder bump and the second solder bump to an all intermetallic interconnect.

US Pat. No. 10,170,444

PACKAGES FOR SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A package for a semiconductor device, comprising:an integrated circuit die mounting region;
a molding material disposed around the integrated circuit die mounting region;
an interconnect structure disposed over the molding material and the integrated circuit die mounting region, the interconnect structure comprising a plurality of contact pads;
a connector coupled to each of the plurality of contact pads, wherein two or more connectors each comprises a first portion having a ball shape including a rounded top and sides and a second portion having a raised edge vertically further from a respective contact pad than the first portion, the second portion having vertical sidewalls and a planar top surface protruding from the rounded top of the first portion, wherein a material composition of the second portion has a same material composition as the first portion, wherein the first portion is in contact with a respective contact pad of the plurality of contact pads, wherein the second portion comprises an alignment feature, and wherein the first portion and second portion comprises a eutectic material; and
a raised insulating material layer disposed over at least one of the connectors having an alignment feature, the raised insulating material layer having a same shape as the alignment feature, the raised insulating material layer comprising an oxide of the material composition of the second portion.

US Pat. No. 10,170,443

DEBONDING CHIPS FROM WAFER

International Business Ma...

1. A debonding device comprising:a first member provided with a recess for receiving a carrier body, the carrier body including a first plate, a second plate, and a plurality of semiconductor chips, the semiconductor chips being sandwiched between the first plate and the second plate, the first plate being opposed to a bottom of the recess; and
a second member having a location figured to change with respect to the first member, wherein
the second member holds the second plate using a vacuum suction in a position; and
the first member is provided with an inlet to introduce gas into a gap between the first plate and the second plate.

US Pat. No. 10,170,442

MOUNT STRUCTURE INCLUDING TWO MEMBERS THAT ARE BONDED TO EACH OTHER WITH A BONDING MATERIAL LAYER HAVING A FIRST INTERFACE LAYER AND A SECOND INTERFACE LAYER

PANASONIC INTELLECTUAL PR...

1. A mount structure comprising two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members,the bonding material layer containing a first intermetallic compound and a stress relaxation material,
the first intermetallic compound having a spherical, a columnar, or an oval spherical shape, and same crystalline structure as the first interface layer and the second interface layer, and partly closing space between the first interface layer and the second interface layer,
the stress relaxation material containing tin as a main component, and filling around the first intermetallic compound,
wherein the first interface layer, the second interface layer, and the first intermetallic compound are (Cu,Ni)6Sn5.

US Pat. No. 10,170,441

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
an alignment mark adjacent to a surface of the substrate;
a plurality of pillars protruding from the substrate; and
a seal wall protruding from the surface of the substrate and surrounding the alignment mark, wherein the seal wall is between the plurality of pillars and the alignment mark, and the plurality of pillars are configured into at least two different groups wherein a group has an average height different from an average height of an another group.

US Pat. No. 10,170,440

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THEREOF

EPISTAR CORPORATION, Hsi...

1. A semiconductor device, comprising,a semiconductor die comprising a stacking structure, a first bonding pad with a flat top side in a cross-sectional view, positioned away from the stacking structure, and a second bonding pad, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 microns;
a carrier comprising a connecting surface;
a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and
a conductive connecting layer comprising
a first conductive part formed between the first bonding pad and the third bonding pad, and comprising a first conductive material having a first shape with a width;
a second conductive part formed between the second bonding pad and the fourth bonding pad, and comprising the first conductive material; and
a blocking part covering the first conductive part and comprising a second conductive material having a second shape with a diameter less than the width in the cross-sectional view,
wherein the first shape has a height greater than the diameter, and
wherein the first conductive part fully covers the top flat side in the cross-sectional view.

US Pat. No. 10,170,439

CHAMFERING FOR STRESS REDUCTION ON PASSIVATION LAYER

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:an inner layer comprising electronic devices;
an insulator layer on the inner layer, wherein the inner layer has a first surface where the insulator layer contacts the inner layer;
a patterned conductor on the first surface of the inner layer, wherein the patterned conductor comprises a pattern of connected linear sections parallel to the first surface of the inner layer, wherein the linear sections meet at conductor corners, wherein at least one of the conductor corners of the patterned conductor includes a chamfer side that terminates at the linear sections, wherein the chamfer side forms unequal angles with the linear sections, along the first surface, and wherein the chamfer side forms an angle of other than 45° with the linear sections; and
a through conductor extending into the inner layer, and being positioned to electrically connect the patterned conductor to the electronic devices.

US Pat. No. 10,170,438

STATIC DISCHARGE SYSTEM

POWER INTEGRATIONS. INC.,...

1. A circuit, comprising:a semiconductor device, wherein the semiconductor device further comprises a drain terminal, a source terminal, and a gate terminal; and
a static discharge system electrically coupled between the gate terminal and the drain terminal, wherein the static discharge system removes charge that accumulates on a conductor when the semiconductor device is in an on-state, wherein the static discharge systems allows charge to accumulate on the conductor when the semiconductor device is in an off-state, wherein the conductor is capacitively coupled to the gate terminal of the semiconductor device;
wherein the semiconductor device and the static discharge system are formed on separate substrates.

US Pat. No. 10,170,437

VIA DISGUISE TO PROTECT THE SECURITY PRODUCT FROM DELAYERING AND GRAPHIC DESIGN SYSTEM (GDS) HACKING AND METHOD FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:forming a first dielectric layer;
forming a first metal layer in a portion of the first dielectric layer;
forming a first Nblok layer over the first dielectric layer and the first metal layer;
forming a second dielectric layer over the first Nblok layer;
forming a second Nblok layer over a portion of the second dielectric layer;
forming a third dielectric layer over the second dielectric layer and the second Nblok layer;
forming a via and a plurality of vias through the third and second dielectric layers down to the second and first Nblok layers, respectively;
removing portions of the second and first Nblok layers through the via and the plurality of vias down to the second dielectric layer and the first metal layer, respectively; and
filling the via and the plurality of vias with a second metal layer.

US Pat. No. 10,170,436

FLASH MEMORY DEVICE HAVING FLAME RESISTANT

Innodisk Corporation, Ne...

1. A flash memory device having flame resistant, comprising:a first shell;
a first circuit board comprising a controller and a plurality of flash memory elements connected to the controller, wherein the first circuit board is disposed within the first shell, and covered by a ceramic fiber material or a fire protection material with plasticity; and
a first transmission interface disposed outside the first shell, wherein a circuit connection line is connected between the first transmission interface and the first circuit board.

US Pat. No. 10,170,435

GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME

MEDIATEK SINGAPORE PTE. L...

1. A method for forming a seal ring structure, comprising:providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type;
forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions and extending along a second direction perpendicular to the first direction;
performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of bridge portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction;
removing the patterned photoresist layers;
forming an isolation region between and adjacent to the patterned first doping regions; and
forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder.

US Pat. No. 10,170,434

WARPAGE CONTROL IN PACKAGE-ON-PACKAGE STRUCTURES

Taiwan Semiconductor Manu...

1. A package comprising:a bottom package comprising:
a package component; and
a device die over and bonded to the package component;
an adhesive layer over a top surface of the device die, wherein the adhesive layer comprises a slanted sidewall, a planar top surface, and a curved corner joining the slanted sidewall to the planar top surface;
a rigid plate over and contacting the planar top surface of the adhesive layer;
a molding compound, wherein at least a lower portion of the device die is in the molding compound; and
a top package bonded to the bottom package through solder regions penetrating through the molding compound.

US Pat. No. 10,170,433

INSULATED CIRCUIT BOARD, POWER MODULE AND POWER UNIT

Mitsubishi Electric Corpo...

1. An insulated circuit board comprising:an insulated substrate;
a first electrode formed on one main surface of the insulated substrate and having a polygonal shape in plan view; and
a second electrode formed on the other main surface opposite to the one main surface of the insulated substrate and having a polygonal shape in plan view,
a thin portion being formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, so that the thin portion occupies only a portion of an entire length of the outer edges, the thin portion having a thickness smaller than a thickness of a region of the at least one of the first and second electrodes other than the thin portion,
the thin portion in the at least one of the first and second electrodes having a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.

US Pat. No. 10,170,431

ELECTRONIC CIRCUIT PACKAGE

TDK CORPORATION, Tokyo (...

1. An electronic circuit package comprising:a substrate having a main surface, the main surface having a first region and a second region located on a same plane as the first region;
a first electronic component mounted on the first region;
a second electronic component mounted on the second region;
a mold resin that covers the main surface of the substrate so as to embed the first and second electronic components therein;
a magnetic film formed on the mold resin; and
a metal film formed on the mold resin, wherein the metal film covers the first electronic component with an intervention of the magnetic film while the metal film covers the second electronic component without an intervention of the magnetic film.

US Pat. No. 10,170,430

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method of fabricating an integrated fan-out package, the method comprising:attaching an integrated circuit component onto a carrier through a die attach film,
forming an insulating encapsulation on the carrier to laterally encapsulate the integrated circuit component and the die attach film, wherein an uplifted segment of the die attach film is lifted during forming the insulating encapsulation, and the uplifted segment raises toward sidewalls of the integrated circuit component; and
forming a redistribution circuit structure on the integrated circuit component and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit component.

US Pat. No. 10,170,429

METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a package structure, comprising:forming a first bump over a substrate;
placing an integrated circuit die comprising a second bump over the substrate, wherein the second bump is placed on the first bump;
reflowing the first bump and the second bump to form a solder joint and bond the integrated circuit die and the substrate together through the solder joint, wherein a first intermetallic compound is formed between the solder joint and the first bump, and a second intermetallic compound is formed between the solder joint and the second bump;
annealing the solder joint, the first bump and the second bump to react the solder joint with the first bump and the second bump until the first intermetallic compound and the second intermetallic compound become connected to each other; and
migrating a remaining portion of the solder joint to the first bump or the second bump during a high-temperature storage test or a temperature cycling test.

US Pat. No. 10,170,428

CAVITY GENERATION FOR EMBEDDED INTERCONNECT BRIDGES UTILIZING TEMPORARY STRUCTURES

Intel Corporation, Santa...

1. A method comprising:fabricating a package substrate;
placing at least one temporary structure in a first location on the package substrate;
subsequent to placing the at least one temporary structure in the first location on the package substrate, applying a first dielectric material to the package substrate, to surround at least a portion of the at least one temporary structure;
subsequent to applying the first dielectric material to the package substrate, removing the at least one temporary structure from the package substrate to generate a cavity in the package substrate, wherein a portion of the first dielectric material remains over the cavity subsequent to removing the temporary structure;
removing the portion of the first dielectric material from over the cavity;
subsequent to removing the portion of the first dielectric material from over the cavity, bonding an interconnect bridge in the cavity, the interconnect bridge including a plurality of interconnections;
applying a second dielectric material to the package substrate; and
installing a plurality of contacts to a surface of the package substrate, the plurality of contacts being coupled with the interconnect bridge.

US Pat. No. 10,170,427

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

7. A semiconductor device comprising:a gate stack over a semiconductor fin;
a source/drain region adjacent to the gate stack; and
a first contact to the source/drain region, wherein the first contact has a curved surface, the curved surface extending above a top surface of the gate stack.

US Pat. No. 10,170,426

MANUFACTURING METHOD OF WIRING STRUCTURE AND WIRING STRUCTURE

FUJITSU LIMITED, Kawasak...

1. A wiring structure, comprising:a first insulating film including a connection hole;
a second insulating film which is on the first insulating film and includes a wiring trench;
a first conductive material which fills an inside of the connection hole; and
a second conductive material which fills an inside of the wiring trench, wherein
the first conductive material is made of a first graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the connection hole,
the second conductive material is made of a second graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the wiring trench, and
the first graphene layer and the second graphene layer are directly connected to each other.

US Pat. No. 10,170,425

MICROSTRUCTURE OF METAL INTERCONNECT LAYER

INTERNATIONAL BUSINESS MA...

1. A method of forming a metal interconnect layer, the method comprising:forming an opening in a dielectric layer;
forming an embedded metal layer fully filled in the opening, wherein the embedded metal layer is in direct contact with a bottom surface of the dielectric layer;
forming an overburden layer over a top surface of the embedded metal layer and the dielectric layer;
disposing a metal passivation layer in direct contact with a surface of the overburden layer, the metal passivation layer comprising a metal selected only from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy including only Co, Ru, Ti, or W thereof, nitrides of only Co, Ru, Ti, Ni, or W, and any combination thereof;
performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade; and
performing a chemical-mechanical planarization (CMP) to remove the metal passivation layer and the overburden layer.

US Pat. No. 10,170,424

COBALT FIRST LAYER ADVANCED METALLIZATION FOR INTERCONNECTS

International Business Ma...

1. A method for fabricating an advanced metal conductor structure comprising:providing a pattern in a dielectric layer, wherein the pattern includes a set of features in the dielectric for a set of metal conductor structures and an adhesion promoting layer in the set of features;
depositing a ruthenium metal layer disposed on the adhesion promoting layer;
using a physical vapor deposition process to deposit a cobalt layer disposed on the ruthenium layer;
performing a thermal anneal which reflows the cobalt layer to fill a first portion of the set of features leaving a second, remaining portion of the set of features unfilled; and
depositing a second metal layer to fill the second, remaining portion of the set of features, wherein the second metal is a metal other than cobalt, wherein a thickness of the reflowed cobalt layer from the ruthenium layer to a bottom of the second metal layer and a thickness of the second metal layer after planarization are substantially equal.

US Pat. No. 10,170,423

METAL CAP INTEGRATION BY LOCAL ALLOYING

International Business Ma...

1. An interconnect structure, comprising:a dielectric layer having a top surface;
a plurality of open-ended trenches extending within the dielectric layer;
interconnects comprising copper within the open-ended trenches, a plurality of interconnects of the interconnect structure having top surfaces that are substantially coplanar with the top surface of the dielectric layer;
a plurality of metal alloy caps for preventing electromigration, each of the metal alloy caps being integral with one of the interconnects and comprising an alloy of copper and at least one of titanium, ruthenium and cobalt, wherein the metal alloy caps exhibit a stoichiometry of at least one part titanium, ruthenium or cobalt per one part of copper.

US Pat. No. 10,170,422

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Taiwan Semiconductor Manu...

18. A method of forming an integrated chip, comprising:forming a plurality of gate structures extending in a second direction over an active area within a substrate;
forming a first middle-end-of-the-line (MEOL) structure and a second MEOL structure extending in the second direction over the active area and interleaved between the plurality of gate structures along a first direction perpendicular to the second direction, wherein the second MEOL structure extends a non-zero distance past the first MEOL structure along the second direction;
forming a first power rail extending in the first direction, wherein the first power rail is coupled to the second MEOL structure by a first conductive path comprising a conductive contact directly below the first power rail;
forming a first metal wire extending in the first direction over the first MEOL structure;
forming a metal strap coupled to the first metal wire; and
forming a second power rail extending in the first direction over the first power rail, wherein the second power rail is coupled to the first MEOL structure along a second conductive path comprising the first metal wire and the metal strap.

US Pat. No. 10,170,421

LOGIC SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A logic semiconductor device, comprising:a plurality of active patterns extending in a first direction and being spaced apart from each other in a second direction, the first and second directions being perpendicular to each other;
an isolation layer defining the active patterns;
a plurality of gate patterns extending in the second direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the first direction and at least one of the gate patterns being on the plurality of active patterns;
active contacts connected to upper portions of the active patterns adjacent to the gate patterns;
a plurality of sub-wirings integrally connected to the active contacts, the sub-wirings extending in the first direction; and
wirings extending in the second direction over the sub-wirings.

US Pat. No. 10,170,420

PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a semiconductor substrate;
a first interconnect layer over the semiconductor substrate, the first interconnect layer comprising: a first dielectric material having a conductive body embedded therein, the conductive body comprising a first sidewall, a second sidewall, and a bottom surface, and a spacer element having a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body; and
a second interconnect layer overlying the first interconnect layer comprising a second dielectric material having at least one via therein, the at least one via filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer;
wherein a height of the spacer element is greater than a height of the conductive body.

US Pat. No. 10,170,419

BICONVEX LOW RESISTANCE METAL WIRE

International Business Ma...

1. A semiconductor structure comprising:a dielectric material layer having at least one opening located in said dielectric material layer, said at least one opening physically exposing a pair of curved sidewalls of said dielectric material layer and having a biconvex shape comprising a lower portion having a first width, a middle portion having a second width, and an upper portion having a third width, wherein the second width is greater than the first and third widths;
a diffusion barrier liner located in said at least one opening and contacting at least said pair of curved sidewalls of said dielectric material layer;
a reflow enhancement liner located on said diffusion barrier liner; and
a metallic region located on said reflow enhancement liner, said metallic region having a pair of curved outermost sidewalls, said biconvex shape and comprising a lower metallic region portion having a first metallic region width, a middle metallic region portion having a second metallic region width, and an upper metallic region portion having a third metallic region width, wherein the second metallic region width is greater than the first and third metallic region widths.

US Pat. No. 10,170,418

BACKSIDE DEVICE CONTACT

International Business Ma...

1. A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the method comprising:forming a trench in the device layer;
forming a sacrificial plug in the trench;
removing the handle wafer to reveal the buried insulator layer;
partially removing the buried insulator layer to expose the sacrificial plug at a bottom of the trench;
removing the sacrificial plug;
performing backside processing of the buried insulator layer;
filling the trench with a conductor to form a contact plug;
coupling a final substrate to the buried insulator layer such that the contact plug contacts metallization of the final substrate.

US Pat. No. 10,170,417

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a dielectric layer on the substrate and comprising a recess feature therein;
a metal layer in the recess feature, wherein the metal layer has an oxygen content less than about 0.1 atomic percent; and
a tungsten layer in the recess feature and in contact with the metal layer.

US Pat. No. 10,170,416

SELECTIVE BLOCKING BOUNDARY PLACEMENT FOR CIRCUIT LOCATIONS REQUIRING ELECTROMIGRATION SHORT-LENGTH

International Business Ma...

1. A semiconductor structure comprising:a first insulating layer deposited over a semiconductor substrate;
trenches formed by etching the first insulating layer, the trenches configured to receive copper (Cu) wiring, wherein the Cu wiring is selectively recessed in one or more of the trenches resulting in recessed Cu wiring regions and non-recessed Cu wiring regions, the recessed Cu wiring regions corresponding to circuit locations calling for electromigration (EM) short-length;
self-aligned conducting caps formed over the one or more trenches where the Cu wiring has been selectively recessed; and
a first via directly contacting a top surface of the Cu wiring in the non-recessed Cu wiring regions.

US Pat. No. 10,170,415

SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, AND LOAD DRIVING DEVICE

Hitachi Automotive System...

1. A semiconductor device comprising:a transistor layer having arranged thereon in a two-dimensional manner a plurality of transistors each including an input unit, an output unit, and a control unit;
a plurality of interconnection layers configured to electrically connect the input units of the plurality of transistors to an input terminal and electrically connect the output units of the plurality of transistors to an output terminal; and
a plurality of interlayer connection conductors respectively connecting the plurality of interconnection layers to the transistor layer,
wherein the plurality of interconnection layers include a first interconnection layer having arranged therein along a predetermined arranging direction at least one input side interconnection layer connected to the input terminal and at least one output side interconnection layer connected to the output terminal, and
wherein resistance values of the plurality of interlayer connection conductors differ from each other depending on a position in the arranging direction.

US Pat. No. 10,170,414

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

10. A semiconductor device, comprising:a first group of dummy gate structures disposed over a substrate;
a first interlayer dielectric layer in which the first group of dummy gate structures are embedded;
a second interlayer dielectric layer disposed over the first interlayer dielectric layer;
a third interlayer dielectric layer disposed over the second interlayer dielectric layer; and
a resistor wire formed by a conductive material and embedded in the third interlayer dielectric layer, wherein:
the resistor wire is separated from the first group of dummy gate structures by the second and third interlayer dielectric layers,
the first group of dummy gate structure includes two or more first dummy gate structures and
at least one first dummy gate structure of the first group of dummy gate structures fully overlaps the resistor wire.

US Pat. No. 10,170,413

SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a semiconductor substrate;
a fin field effect transistor (FinFet) comprising:
a fin over the semiconductor substrate;
a gate structure over the fin; and
a source/drain structure adjoining the fin and adjacent to the gate structure;
a shallow trench isolation structure surrounding the fin;
a buried metal line under a top surface of the shallow trench isolation structure; and
a metal segment over the source/drain structure, wherein a portion of the metal segment extends into the shallow trench isolation structure to be electrically coupled to the buried metal line.

US Pat. No. 10,170,412

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. An apparatus, comprising:conductive elements of a conductive layer on a bottom side of a package;
wire bond wires coupled to and extending from first upper surface portions of the conductive elements;
a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;
a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; and
a dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.

US Pat. No. 10,170,411

AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT

International Business Ma...

1. A method for via alignment, comprising:depositing a pinch off layer to close off openings to first airgaps between interconnect structures;
forming a protection layer in divots formed in the pinch off layer; and
etching the pinch off layer using the protection layer as an etch stop to form and align a via and expose the interconnect structures through the via.

US Pat. No. 10,170,410

SEMICONDUCTOR PACKAGE WITH CORE SUBSTRATE HAVING A THROUGH HOLE

Samsung Electro-Mechanics...

1. A semiconductor package, comprising:a frame comprising a through hole;
an electronic component disposed in the through hole;
a metal layer disposed on either one or both of an inner surface of the through hole and an upper surface of the electronic component;
a redistribution portion disposed below the frame and the electronic component; and
a conductive layer electrically connected to the metal layer,
wherein the redistribution portion comprises an insulating layer formed of an insulating material, and a wiring layer provided in the insulating layer, and
wherein the insulating layer extends to a space formed by a portion of the metal layer formed on an inner surface of the frame and an outer surface of the electronic component.

US Pat. No. 10,170,409

PACKAGE ON PACKAGE ARCHITECTURE AND METHOD FOR MAKING

INTEL CORPORATION, Santa...

1. A method of fabricating a package assembly, the method comprising:forming a package-on-package (POP) land by partially embedding a prefabricated via bar in a region on a first side of a mold compound and extended to a location between the first side of the mold compound and a second side of the mold compound disposed opposite to the first side, wherein the prefabricated via bar extends across a plurality of package assemblies including a first package assembly and a second package assembly separated from the first package assembly, and wherein a die is at least partially embedded in the mold compound and has an active side proximal to the first side of the mold compound;
removing material of the mold compound to expose a portion of the POP land in a region on the second side of the mold compound after the forming of the POP land; and
depositing at least one of a conductive material, a passivation layer, or a noble metal on the exposed portion of the POP land.

US Pat. No. 10,170,408

MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

Taiwan Semiconductor Manu...

1. A memory circuit, comprising:at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first conductive layer arranged at a first level, the first conductive layer comprising a first landing pad and a second landing pad, the first landing pad forming a landing site formed in the first conductive layer and on which a via lands, the via connecting the first conductive layer to a second conductive layer;
the second conductive layer coupled to the first conductive layer and arranged at a second level different from and over the first level, the second conductive layer being routed to define the first voltage line and the second voltage line, the first voltage line and the second voltage line extending in a first direction, wherein the first voltage line and the second voltage line are located within the second conductive layer; and
a third conductive layer coupled to the second conductive layer and arranged at a third level different from the first level and the second level, the third level over the second level, the third conductive layer being routed to define the word line, the word line extending in a second direction perpendicular to the first direction, wherein the bit line is located within the first conductive layer adjacent to the first landing pad, wherein the bit line in the first conductive layer extends past a periphery of the at least one memory cell in the first direction, wherein the bit line bar is located within the first conductive layer adjacent to the second landing pad, and wherein the bit line bar in the first conductive layer extends past the periphery of the at least one memory cell in the first direction.

US Pat. No. 10,170,407

ELECTRONIC DEVICE AND METHODS OF PROVIDING AND USING ELECTRONIC DEVICE

ARIZONA BOARD OF REGENTS ...

1. A method of providing an electronic device, the method comprising:providing a first device substrate comprising a first side and a second side opposite the first side, the first device substrate comprising a first flexible substrate, a first device portion, and a first perimeter portion at least partially framing the first device portion;
providing one or more first active sections over the second side of the first device substrate at the first device portion, each first active section of the one or more first active sections comprising at least one first semiconductor device, each first semiconductor device of the at least one first semiconductor device comprising at least one first pixel, and each first pixel of the at least one first pixel comprising a first smallest cross dimension; and
after providing the one or more first active sections over the second side of the first device substrate at the first device portion, folding the first perimeter portion of the first device substrate toward the first device portion at the first side of the first device substrate so that a first edge portion remains to at least partially frame the first device portion, the first edge portion comprising a first edge portion width dimension smaller than the first smallest cross dimension;
providing a second device substrate comprising a first side and a second side opposite the first side, the second device substrate comprising a second flexible substrate, a second device portion, and a second perimeter portion at least partially framing the second device portion;
providing one or more second active sections over the second side of the second device substrate at the second device portion, each second active section of the one or more second active sections comprising at least one second semiconductor device, each second semiconductor device of the at least one second semiconductor device comprising at least one second pixel, and each second pixel of the at least one second pixel comprising a second smallest cross dimension;
after providing the one or more second active sections over the second side of the second device substrate at the second device portion, folding the second perimeter portion of the second device substrate toward the second device portion at the first side of the second device substrate so that a second edge portion remains to at least partially frame the second device portion, the second edge portion comprising a second edge portion width dimension smaller than the second smallest cross dimension; and
after folding the first perimeter portion of the first device substrate toward the first device portion at the first side of the first device substrate and after folding the second perimeter portion of the second device substrate toward the second device portion at the first side of the second device substrate, arranging the first device substrate adjacent to the second device substrate in an array grid.

US Pat. No. 10,170,406

TRACE/VIA HYBRID STRUCTURE AND METHOD OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method of forming an interconnect comprising:providing a sacrificial trace structure using an additive forming method;
forming a seed metal layer on the sacrificial trace structure;
removing the sacrificial trace structure, wherein the seed metal layer remains;
forming an interconnect metal layer on the continuous seed layer;
forming a dielectric material on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of said interconnect metal layer are exposed to provide said interconnect extending through said dielectric material;
forming a solder bump on said ends of the interconnect metal layer; and
bonding said solder bump to a substrate including at least one microprocessor.

US Pat. No. 10,170,405

WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:an insulating layer; and
a wiring layer buried in the insulating layer at a first surface of the insulating layer,
the wiring layer including a first portion and a second portion, the first portion being narrower and thinner than the second portion, the first portion including a first surface exposed at the first surface of the insulating layer, the second portion including a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer, the opening being open at a second surface of the insulating layer opposite to the first surface thereof,
wherein the wiring layer includes a first surface exposed at the first surface of the insulating layer, a second surface opposite to the first surface of the wiring layer, and a side surface, and
wherein a surface roughness of the second surface of the wiring layer and the side surface of the wiring layer is greater than a surface roughness of the first surface of the wiring layer.

US Pat. No. 10,170,404

MONOLITHIC 3D INTEGRATION INTER-TIER VIAS INSERTION SCHEME AND ASSOCIATED LAYOUT STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure; and
forming a dummy gate over the second substrate, wherein the dummy gate is formed to be electrically coupled to the via.

US Pat. No. 10,170,403

AMELIORATED COMPOUND CARRIER BOARD STRUCTURE OF FLIP-CHIP CHIP-SCALE PACKAGE

Kinsus Interconnect Techn...

1. An ameliorated compound carrier board structure of Flip-Chip Chip-scale Package comprising:a carrier board having a plurality of first electrical contact pads on a top surface of the carrier board, and a plurality of second electrical contact pads on the top surface of the carrier board and arranged surrounding the first electrical contact pads;
a substrate having a flip region with a through opening arranged over the first electrical contact pads, and a plurality of electric conductors penetrating the substrate with the upper and lower ends of each being exposed on top and bottom surfaces of the substrate and being electrically connected to a bottom surface of a first electrode pad and a top surface of a second electrode pad; the bottom surface of the second electrode pads corresponding to the top surface of the second electrical contact pads; and
an anisotropic conductive film including an insulating layer having a plurality of conductive particles distributed therein at mutually spaced positions, the anisotropic conductive film having portions compressed between the second electrode pads of the carrier board and the second electrical contact pads of the substrate to form a plurality of high-density compressed areas, the conductive particles within each of the high-density compressed areas thereby bursting and contacting with the top surface of the second electrical contact pads for conducting the second electrode pads and the second electrical contact pads, and the conductive particles outside the high-density compressed areas remaining unburst in position within the insulating layer to remain insulation of uncompressed portions of the insulating layer other than the high-density compressed areas between the bottom surface of the substrate and the top surface of the carrier board, and
at least one die, disposed in the through opening, and having an active surface and a non-active surface arranged correspondingly with the active surface having a plurality of bumps, the bottom surface of each bump compressing a portion of the anisotropic conductive film against one of the first electrical contact pads to form a conductive connection therewith, a sealant material being filled in a gap between an inner wall of the through opening of the flip region and an outer peripheral of the die for the die to be fixed in the flip region, with the non-active surface remaining exposed;
wherein the thickness of the anisotropic conductive film is between 30 ?m and 40 ?m, and the conductive particles are nickel- and gold-plated particles with a diameter of 5 ?m; the anisotropic conductive film is compressed onto the carrier board under the process parameters of 70° C.˜90° C. 1 MPa, and 1 second, then the substrate is compressed thereon under the process parameters of 150° C.˜220° C., 2˜4 MPa, and 1˜10 seconds; each second electrode pad has a distance within 50 ?m with other ones so that the conductive particles between the bottom surface of the second electrode pads and the top surface of the second electrical contact pads would have a contact area of at least 50000 ?m with the conductive particles.

US Pat. No. 10,170,402

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface;
a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate; and
a plurality of wires electrically connected with the plurality of terminals, respectively,
wherein, in plan view, the first semiconductor chip is mounted over the upper surface of the wiring substrate such that the plurality of terminals of the wiring substrate is exposed from the first semiconductor chip,
wherein, in plan view, the plurality of terminals is arranged along a first side of the first main surface of the first semiconductor chip,
wherein the plurality of terminals has a plurality of first terminals, and a second terminal,
wherein, in plan view, the second terminal has a first part located on a virtual line comprised of an arrangement of the plurality of first terminals, and a second part not located on the virtual line,
wherein each of the plurality of wires has a ball part, and a stitch part,
wherein, in plan view, a width of the ball part is larger than a width of the stitch part,
wherein the plurality of wires has a plurality of first wires, and a second wire,
wherein, the plurality of first wires are connected to the plurality of first terminals, respectively, via the stitch part,
wherein the second wire is connected to the second part of the second terminal via the ball part, and
wherein a distance from the first side of the first main surface of the first semiconductor chip to the second part of the second terminal is greater than a distance from the first side of the first main surface of the first semiconductor chip to each of the first terminals in a direction perpendicular to the first side of the first main surface of the first semiconductor chip.

US Pat. No. 10,170,401

INTEGRATED POWER MODULE

Mosway Technologies Limit...

1. An integrated power module comprising:a composite printed circuit board having opposed first and second sides and including a first area and a second area, wherein the composite printed circuit board includes at least one aperture extending through the composite printed circuit board, from the first side to the second side, in the second area;
at least one driver mounted on the first side of the composite printed circuit board in the first area;
at least one power switching device mounted on the first side of the composite printed circuit board in the second area, wherein
the at least one driver is connected for driving a gate of the at least one power switching device; and
a respective aperture, of the at least one aperture in the composite printed circuit board, is located directly opposite each of the at least one power switching device;
directly bonded copper disposed on the first side of the composite printed circuit board, in the second area, and providing electrical connections to the at least one power switching device;
a lead frame to which the composite printed circuit board is mounted; and
a package encapsulating the composite printed circuit board, the at least one power switching device, and the at least one driver.

US Pat. No. 10,170,400

MULTI-FINGER TRANSISTOR AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A multi-finger transistor comprising:a plurality of gate fingers arranged in an active region on a semiconductor substrate;
a plurality of source fingers and a plurality of drain fingers which are alternately arranged in said active region in such a way as to sandwich said gate fingers therebetween, respectively;
a gate pad disposed outside said active region, said gate fingers being connected to said gate pad via a gate bus;
a source pad disposed in a region which is located outside said active region and on a side where said gate pad is disposed with respect to said active region, said source fingers being connected to said source pad;
a drain pad disposed in a region which is located outside said active region and which is located at an opposite side of said gate pad across said active region, said drain fingers being connected to said drain pad;
and a source via grounding said source pad, wherein
said multi-finger transistor further comprises a circuit suppressing a variation in voltage current distribution, said circuit connecting said gate fingers to each other, or connecting said source fingers to each other with a resistive member having a resistance higher than said source fingers, in a region which is located outside said active region and on a side where said drain pad is disposed, and
said multi-finger transistor is configured so as to be linearly symmetric with respect to a direction of propagation of a signal from said gate pad at a position of said gate pad.

US Pat. No. 10,170,399

CAPPED THROUGH-SILICON-VIAS FOR 3D INTEGRATED CIRCUITS

Board of Regents, The Uni...

1. A three dimensional (3D) integrated circuit comprising a plurality of electrically connected chips, at least one chip comprisinga wafer;
a back-end-of-line (BEOL) layer deposited on the wafer;
a chip through-silicon-via (TSV) in the wafer, the chip TSV containing a conductive material;
a chip cap layer disposed over the chip TSV and between the chip TSV and the BEOL layer, wherein the chip cap layer is configured to reduce via extrusion of conductive material located in the chip TSV during operation of the chip; and
an interposer on which the plurality of electrically connected chips are located, wherein the interposer comprises a plurality of interposer TSVs and a interposer cap layer configured to reduce via extrusion of conductive material located in the interposer TSV during fabrication or operation of the circuit, or both.

US Pat. No. 10,170,398

THREE-DIMENSIONAL INTEGRATED CIRCUIT

INDUSTRY-ACADEMIC COOPERA...

1. A three-dimensional integrated circuit divided into a plurality of groups, the three-dimensional integrated circuit comprising:a plurality of through-silicon vias (TSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups; and
two or more redundant through-silicon vias (RTSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups,
wherein an RTSV of two or more RTSVs in one group of the plurality of groups is configured to receive a signal of a first failed TSV of a plurality of TSVs in the one group and process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group when a number of failed TSVs among the plurality of TSVs in the one group does not exceed a repairable number, and wherein each of the failed TSVs does not normally perform a function as an electrode, and the repairable number is a number of RTSVs capable of replacing functions of the failed TSVs in the one group, and
wherein the RTSV of the two or more RTSVs in the one group is configured to receive the signal of the first failed TSV of the plurality of TSVs in the one group, process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group, receive a signal of a second failed TSV of the plurality of TSVs in the one group and output the signal of the second failed TSV to an RTSV of two or more RTSVs in another group of the plurality of groups such that a function of the second failed TSV is performed by the RTSV in the another group when the number of failed TSVs among the plurality of TSVs in the one group exceeds the repairable number, the another group being adjacent to the one group.

US Pat. No. 10,170,397

SEMICONDUCTOR DEVICES, VIA STRUCTURES AND METHODS FOR FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A via structure of a semiconductor device, comprising:a through hole penetrating from a first surface to an opposite second surface of a substrate;
a filling insulating layer disposed in the through hole;
a first conductive layer disposed in the through hole and surrounding the filling insulating layer, wherein a portion of the first conductive layer is located directly below the filling insulating layer and at a bottom of the through hole;
a first insulating layer disposed on sidewalls of the through hole and surrounding the first conductive layer; and
a second conductive layer sandwiched between the filling insulating layer and the first conductive layer, wherein a portion of the second conductive layer is located below the filling insulating layer and electrically connected to the first conductive layer.

US Pat. No. 10,170,396

THROUGH VIA STRUCTURE EXTENDING TO METALLIZATION LAYER

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming an intermetal dielectric layer over a substrate;
forming a metal via and a metal line in the intermetal dielectric layer using a dual-damascene process, the metal line formed in a metal one layer (M1);
after forming the intermetal dielectric layer, removing portions of the intermetal dielectric layer to form an opening through the intermetal dielectric layer;
after removing portions of the intermetal dielectric layer, filling the opening with a conductive material to form a through via (TV), the through via extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the metal line; and
after forming the through via, forming one or more dielectric layers over the through via.

US Pat. No. 10,170,395

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor module housing a first semiconductor element and a third semiconductor element;
a second semiconductor module housing a second semiconductor element and a fourth semiconductor element, the second semiconductor element having a switching voltage threshold that is lower than a switching voltage threshold of the first semiconductor element of the first semiconductor module, and the fourth semiconductor element having a switching voltage threshold that is higher than a switching voltage threshold of the third semiconductor element of the first semiconductor module; and
a first busbar that connects an external terminal of the first semiconductor element of the first semiconductor module to an external terminal of the second semiconductor element of the second semiconductor module in parallel to a first common terminal; and
a second busbar that connects an external terminal of the third semiconductor element of the first semiconductor module to an external terminal of the fourth semiconductor element of the second semiconductor module in parallel to a second common terminal, wherein
an inductance of a current path from the first common terminal to the first semiconductor element in the first semiconductor module is lower than an inductance of a current path from the first common terminal to the second semiconductor element in the second semiconductor module, and
an inductance of a current path from the second common terminal to the third semiconductor element of the first semiconductor module is higher than an inductance of a current path from the second common terminal to the fourth semiconductor element of the second semiconductor module.

US Pat. No. 10,170,394

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

10. A semiconductor device comprising:a laminated substrate having a circuit board;
a semiconductor chip having electrodes on a front surface, and a rear surface fixed to the circuit board;
a terminal having a wiring portion with a plate shape, and a leading end portion with a hollow shape extending from the wiring portion, the wiring portion and the leading end portion being integrally formed of one conductive member, the leading end portion having a front open end forming an end of the terminal and a rear open end where a part of the leading end portion continues to the wiring portion; and
a joining material which electrically and mechanically connects the electrode and the front open end of the leading end portion,
wherein the front open end of the leading end portion is located to face the electrode, and is closed by the joining material entered into the front open end, and
a space is arranged between the front open end of the terminal and the electrode so that the joining material enters the front open end of the leading end portion and the space to connect the leading end portion to the electrode.

US Pat. No. 10,170,392

WAFER LEVEL INTEGRATION FOR EMBEDDED COOLING

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a silicon wafer, comprising:
channel structures formed on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas; and
integrated circuits formed on a second surface of the silicon first wafer that opposes the first surface; and
a manifold wafer bonded to the first surface of the silicon wafer, wherein portions of the manifold wafer enclose the radial channels and wherein inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas.

US Pat. No. 10,170,391

BACKSIDE INITIATED UNIFORM HEAT SINK LOADING

LENOVO ENTERPRISE SOLUTIO...

1. A backside initiated uniform heat sink loading system comprising:a system board assembly comprising at least a processing unit;
a heat sink assembly mounted upon the processing unit from a topside of the system board assembly, the heat sink assembly comprising a base, a plurality of fins formed on the base, a plurality of tension members that extend through the system board assembly and through the base into the plurality of fins, and compressive springs mounted about each of the plurality of tension members on a topside of the base;
a loading plate mounted to the plurality of tension members from a backside of the system board assembly, opposite the topside of the system board assembly; and
a fastener that engages with the loading plate from a backside of the loading plate,
wherein the compressive springs are located within the plurality of fins to be surrounded by the plurality of fins,
wherein the fastener is structured to force the loading plate away from the system board assembly when it is engaged with the loading plate from the backside of the system board assembly,
wherein the loading plate is a plate including stiffening features configured to prevent warpage or deflection of the loading plate, and
wherein the loading plate includes a threaded clearance hole structured to engage with threads of the fastener to force the loading plate away from the system board assembly when the threads of the fastener are engaged with the threaded clearance hole of the loading plate from the backside of the loading plate.

US Pat. No. 10,170,390

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein
a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and
a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

US Pat. No. 10,170,389

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method of forming a semiconductor die assembly, the method comprising:electrically coupling a plurality of first semiconductor dies together in a single stack;
electrically coupling the single stack of first semiconductor dies to a second semiconductor die such that the stack of first semiconductor dies is centered with respect to the second semiconductor die along at least one axis, the second semiconductor die having a peripheral portion that extends laterally outward beyond at least one side of the stack of first semiconductor dies, and wherein the stack of first semiconductor dies forms a first thermal path that transfers heat away from the second semiconductor die;
depositing an underfill material between the first semiconductor dies, wherein the underfill material extends from between the first semiconductor dies onto the peripheral portion of the second semiconductor die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the second semiconductor die adjacent to at most a first side and a second side of the single stack of first semiconductor dies and spaced laterally apart from the at most first and second sides of the single stack of first semiconductor dies, wherein the thermal transfer feature is a blank silicon member, and wherein the thermal transfer feature forms a second thermal path away from the second semiconductor die that is separate from the first thermal path; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation generally corresponding to that of a topmost one of the first semiconductor dies in the stack of first semiconductor dies, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation generally corresponding to that of the topmost one of the first semiconductor dies.

US Pat. No. 10,170,388

SURFACE PASSIVATION HAVING REDUCED INTERFACE DEFECT DENSITY

INTERNATIONAL BUSINESS MA...

1. A method of passivating a surface of a semiconductor, the method comprising:forming a semiconductor layer on a substrate;
contacting a surface of the semiconductor layer with a sulfur source comprising thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer;
forming a dielectric layer on the sulfur passivation layer; and
annealing the dielectric layer at a temperature of about 390 degrees Celsius for about 30 minutes;
wherein a minimum interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.

US Pat. No. 10,170,387

TEMPORARY BONDING SCHEME

Taiwan Semiconductor Manu...

15. A structure comprising:an integrated circuit device;
a molding compound encapsulating the integrated circuit device, the molding compound having a major surface; and
a thermoplastic material within the molding compound having a concentration of from 1 ppm to 100 ppm at the major surface.

US Pat. No. 10,170,386

ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component package comprising:a frame having a cavity;
an electronic component disposed in the cavity of the frame;
a first metal layer disposed on an inner wall of the cavity of the frame;
a second metal layer disposed on a lower surface of the frame;
a third metal layer disposed on an upper surface of the frame;
an encapsulant encapsulating at least a portion of the electronic component; and
a redistribution layer disposed below the frame and the electronic component,
wherein a lower surface of the encapsulant is substantially coplanar with lower surfaces of the electronic component, the first metal layer and second metal layer.

US Pat. No. 10,170,385

SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED VIAS WITHIN INTERCONNECT STRUCTURE FOR FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor die;
an encapsulant deposited over and around the semiconductor die;
a first insulating layer formed over the semiconductor die and encapsulant including a first opening formed through the first insulating layer;
a first conductive layer formed over a top surface of the first insulating layer and extending through the first opening to the encapsulant;
a second insulating layer formed over the semiconductor die and encapsulant including a second opening formed through the second insulating layer, wherein a size of the second opening at the first conductive layer is approximately equal to a size of the first opening, and the second opening is aligned with the first opening;
a second conductive layer formed over a top surface of the second insulating layer and extending through the second opening to the first conductive layer;
a third opening formed through the encapsulant, first conductive layer, and second conductive layer, wherein a size of the third opening at the first conductive layer is smaller than the size of the first opening and the size of the second opening; and
a solder material deposited in the third opening to form a conductive via, wherein the solder material in the third opening is exposed from a top surface of the encapsulant opposite the first conductive layer.

US Pat. No. 10,170,384

METHODS AND APPARATUS PROVIDING A GRADED PACKAGE FOR A SEMICONDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A method comprising:generating a graded package for encapsulating a die by spatially varying package material of the graded package based on a package grading design, wherein the generating of the graded package includes:
moving a printhead to a first location of the graded package;
printing at least one of a first material or a first combination of materials at the first location;
moving the printhead to a second location of the graded package; and
printing at least one of a second material or a second combination of materials at the second location, the second material being different from the first material and the second combination being different than the first combination.

US Pat. No. 10,170,383

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an insulating board;
a circuit pattern disposed on the insulating board;
a semiconductor chip connected to the circuit pattern;
a case disposed on and entirely to one side of the insulating board to surround the circuit pattern and the semiconductor chip; and
a cured resin disposed in the case to seal the circuit pattern and the semiconductor chip, wherein
the case includes a surface portion directly opposing and adjacent to a surface portion of the insulating board, and
no bonding material other than the resin is disposed between the opposing and adjacent surface portions.

US Pat. No. 10,170,382

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and
a resin layer disposed between the encapsulant and the second interconnection member and contacting at least portions of side surfaces of the protrusion bump,
wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad,
the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer and contacting the second interconnection member, and
the resin layer contacts at least portions of side surfaces of the third redistribution layer.

US Pat. No. 10,170,381

SEMICONDUCTOR WAFER AND METHOD OF BACKSIDE PROBE TESTING THROUGH OPENING IN FILM FRAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer including a non-active surface;
forming a conductive layer over the non-active surface;
providing a wafer holder;
forming a first opening through the wafer holder;
mounting the semiconductor wafer to the wafer holder with the conductive layer on the non-active surface oriented toward the wafer holder; and
probe testing the semiconductor wafer by contacting the conductive layer through the first opening in the wafer holder.

US Pat. No. 10,170,380

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display region and a peripheral circuit region located outside the display region,
wherein a first gate line, a first data line and a pixel region adjacent to the first gate line and the first data line are arranged in the display region; the pixel region includes a first pixel electrode and a first thin film transistor, and the first thin film transistor includes a first gate electrode connected to the first gate line, a first source electrode connected to the first data line and a first drain electrode connected to the first pixel electrode;
wherein the array substrate further comprises a test unit arranged in the peripheral circuit region, the test unit comprising:
a second gate line and a second data line intersecting with each other, wherein when the array substrate is in a working state, a first signal inputted to the second gate line is identical with a second signal inputted to the first gate line, and a third signal inputted to the second data line is identical with a fourth signal inputted to the first data line;
a second testing pixel electrode arranged close to the intersection of the second gate line and the second data line;
a second testing thin film transistor arranged at the intersection of the second gate line and the second data line, wherein the second testing thin film transistor includes a second gate electrode connected to the second gate line, a second source electrode connected to the second data line and a second drain electrode connected to the second testing pixel electrode, wherein a first test port exposed outside of the display region is provided for the second gate electrode, a second test port exposed outside of the display region is provided for the second source electrode, and a third test port exposed outside of the display region is provided for the second drain electrode,
wherein, the display region is further provided with a first common electrode line and a first common electrode connected to the first common electrode line;
the test unit further includes: a second common electrode line and a second testing common electrode connected to the second common electrode line, wherein the second testing common electrode and the first common electrode are arranged on a same layer and are identical in material and shape; and the second testing common electrode is connected to a third test lead through a first transparent conductive connecting line which is located on the same layer with the second testing common electrode, wherein one end of the first transparent conductive connecting line is connected to the second testing common electrode and the other end of the first transparent conductive connecting line is connected to the third test lead, and the first transparent conductive connecting line and the second testing common electrode are identical in material,
wherein, the first transparent conductive connecting line is intersected with the second common electrode line in a plan view of the array substrate.

US Pat. No. 10,170,379

WAFER PROCESSING SYSTEM

DISCO CORPORATION, Tokyo...

1. A wafer processing system for processing wafers one at a time, the wafer processing system comprising:a plurality of trays each configured to accommodate a wafer;
a conveyor configured to transfer the wafers accommodated in the trays;
first and second tray holding apparatuses arranged to be spaced from each other along the conveyor, the first and second tray holding apparatuses unloading the trays from the conveyor and loading the unloaded trays onto the conveyor;
first and second apparatuses provided for the first and second tray holding apparatuses, respectively, the first and second apparatuses including processing means configured to process the wafers transferred by the conveyor, and loading/unloading means configured to unload a wafer from or load a wafer onto one of the trays that is held by the first or second tray holding apparatus; and
a pair of rail members, with one of said rail members formed on each side of the conveyor, wherein each of said rail members includes first and second accommodation grooves therein, and further wherein said pair of first accommodation grooves are configured and arranged to accommodate downward movement of said first tray holding apparatus and said pair of second accommodation grooves are configured and arranged to accommodate downward movement of said second tray holding apparatus.

US Pat. No. 10,170,378

GATE ALL-AROUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a stacked structure of a plurality of first semiconductor layers, a plurality of second semiconductor layers, and a plurality of third semiconductor layers alternately stacked in a first direction over a substrate, wherein the first, second and third semiconductor layers are made froth different materials;
patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction;
removing a portion of the second and third semiconductor layers between adjacent first semiconductor layers of the first fin structure to form a first nanowire structure;
removing a portion of the first and third semiconductor layers between adjacent second semiconductor layers of the second fin structure to form a second nanowire structure;
forming first gate structures wrapping around first nanowires of the first nanowire structure at a first region of the first nanowires; and
forming second gate structures wrapping around second nanowires of the second nanowire structure at a first region of the second nanowires,
wherein the first and second gate structures include gate electrodes, and
wherein when viewed in a cross section taken along a third direction substantially perpendicular to the first direction and the second direction a height of the first nanowires along the first direction is not equal to a distance of a spacing along the first direction between immediately adjacent second nanowires.

US Pat. No. 10,170,377

MEMORY CELL WITH RECESSED SOURCE/DRAIN CONTACTS TO REDUCE CAPACITANCE

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a device above an active region defined in a semiconducting substrate, said device comprising a plurality of gate structures, a spacer formed adjacent each of said plurality of gate structures, and conductive source/drain contact structures positioned adjacent each of said plurality of gate structures and separated from an associated gate structure by said spacer;
recessing a first portion of said conductive source/drain contact structures of a subset of said plurality of gate structures at a first axial position along a selected gate structure of said plurality of gate structures to define a cavity, wherein a selected source/drain contact structure is not recessed;
forming a first dielectric layer in said cavity; and
forming a conductive line contacting said selected source/drain contact structure in said first axial position.

US Pat. No. 10,170,376

DEVICE AND FORMING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A device, comprising:a first vertical nanowire disposed on a substrate, wherein the first vertical nanowire comprises a silicon germanium channel part, wherein the first vertical nanowire comprises a bottom silicon source/drain part directly contacting the substrate, a top silicon source/drain part on the bottom silicon source/drain part, and the silicon germanium channel part between the top silicon source/drain part and the bottom silicon source/drain part, wherein the material of the silicon germanium channel part is different from the materials of the bottom silicon source/drain part and the top silicon source/drain part;
a second vertical nanowire disposed on the substrate next to the first vertical nanowire, wherein the second vertical nanowire comprises a silicon channel part; and
a gate encircling the silicon germanium channel part and the silicon channel part.

US Pat. No. 10,170,375

FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:forming a first layer over a substrate, the first layer spanning across both a first region and a second region;
forming a second layer over the first layer;
etching the first and second layers to form a plurality of openings in the first region and the second region, wherein the plurality of openings extend vertically through the first layer and the second layer;
forming a dielectric layer in the openings in the first region but not in openings of the second region; and
forming an insulating layer between the first and second layers in the second region.

US Pat. No. 10,170,374

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:at least one n-channel;
at least one p-channel;
at least one first high-k dielectric sheath surrounding the n-channel;
at least one second high-k dielectric sheath surrounding the p-channel, the first high-k dielectric sheath and the second high-k dielectric sheath comprising different high-k dielectric materials;
a first metal gate electrode surrounding and in contact with the first high-k dielectric sheath; and
a second metal gate electrode surrounding and in contact with the second high-k dielectric sheath, wherein the first and second metal gate electrodes are made of the same material.

US Pat. No. 10,170,373

METHODS FOR MAKING ROBUST REPLACEMENT METAL GATES AND MULTI-THRESHOLD DEVICES IN A SOFT MASK INTEGRATION SCHEME

GLOBALFOUNDRIES INC., Gr...

1. A method of fabricating FETs of the same type having different threshold voltages by incorporating a thinned stack in a replacement metal gate process, the method comprising:(a) forming a first opening in a dielectric layer overlying a first FET region of a substrate and forming a second opening in a dielectric layer overlying a second FET region of the substrate;
(b) forming a high-k layer lining both the first and second openings;
(c) forming a thinning stack in the second opening of the second FET region, the thinning stack including a first bottom layer, a second middle layer, and third top layer, wherein the second middle layer has a composition different from the first bottom layer and the third top layer and the second middle layer is positioned between and in contact with the first bottom layer and the third top layer, and wherein the first bottom layer includes titanium nitride (TiN);
(d) removing a portion of the thinning stack to leave a thinned remaining portion of the thinning stack in the second opening of the second FET region, including removing the third top layer such that the thinned remaining portion of the thinning stack in the second opening of the second FET region includes at least the first bottom layer;
(e) forming a threshold voltage metal which is in contact with the high-k layer in the first opening and in contact with the thinned remaining portion of the thinning stack in the second opening;
(f) forming a first work function metal stack in the first and second openings of the first FET and second FET regions; and
(g) filling the first and second openings with a fill material,
wherein the first and second FET regions have the same high-k layer, the same threshold voltage metal, the same work function metal stack and the same fill material but have different threshold voltages.

US Pat. No. 10,170,372

FINFET CMOS WITH SI NFET AND SIGE PFET

International Business Ma...

1. A complementary metal oxide semiconductor (CMOS) device, comprising:pedestals with vertical sidewalls formed from a buried dielectric layer;
a SiGe fin and a Si fin, each formed on the pedestals, the SiGe fin and the Si fin including a same or substantially the same width dimension, wherein the pedestals extend wider than the SiGe fin and the Si fin for the entire length of the fins; and
epitaxial source and drain regions including a first epitaxial region grown from the SiGe fin and a second epitaxially region grown from the Si fin.

US Pat. No. 10,170,371

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

International Business Ma...

1. A fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:a plurality of vertical fins within a perimeter of a fin pattern region on a substrate;
a step formed in the substrate surrounding the plurality of vertical fins;
a doped region within the perimeter of the fin pattern region below the plurality of vertical fins, wherein the depth of the doped region is less than the height of the step;
a dielectric layer on the step and at least a portion of the plurality of vertical fins; and
a gate dielectric layer on at least a portion of the sidewalls of the plurality of vertical fins and on the dielectric layer, wherein the gate dielectric layer extends over at least a portion of the step.

US Pat. No. 10,170,370

CONTACT RESISTANCE CONTROL IN EPITAXIAL STRUCTURES OF FINFET

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:fin regions on a substrate;
shallow trench isolation (STI) regions between the fin regions;
a replacement gate structure over the fin regions and the STI regions;
a merged epitaxial region; and
a capping layer, on the merged epitaxial region, with a top surface having a vertical dimension between a highest point and a lowest point less than about 5 nm.

US Pat. No. 10,170,369

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor device, comprising:providing a substrate having thereon a trench isolation region and a plurality of fin structures extending along a first direction, wherein the plurality of fin structures protrude from a top surface of the trench isolation region;
blanket depositing a polysilicon layer over the substrate;
forming a poly cut opening and a dummy opening in the polysilicon layer;
blanket coating an organic dielectric layer (ODL) over the substrate, wherein the ODL fills into the poly cut opening and the dummy opening;
blanket depositing a hard mask layer on the ODL;
forming a plurality of photoresist line patterns comprising a first photoresist line pattern and a second photoresist line pattern extending along a second direction on the hard mask layer, wherein the first photoresist line pattern overlaps with the poly cut opening, and the second photoresist line pattern is disposed in proximity to the dummy opening, and does not overlap with the dummy opening; and
transferring the plurality of photoresist line patterns to the polysilicon layer, thereby forming a plurality of poly lines extending along the second direction.

US Pat. No. 10,170,368

FABRICATING FIN-BASED SPLIT-GATE HIGH-DRAIN-VOLTAGE TRANSISTOR BY WORK FUNCTION TUNING

International Business Ma...

1. A method for creating an asymmetrical split-gate structure, the method comprising:forming a first device over a semiconductor substrate, the first device having first source drain regions formed adjacent a first set of spacers;
forming a second device over the semiconductor substrate, the second device having second source/drain regions formed adjacent a second set of spacers;
forming a first gate stack between the first set of spacers of the first device and a second gate stack between the second set of spacers of the second device;
depositing a hard mask over the first and second gate stacks;
etching a first section of the first gate stack to create a first gap region and a second section of the second gate stack to create a second gap region;
forming a third gate stack within the first gap region of the first gate stack, the third gate stack having a different number of layers than the first gate stack, and a fourth gate stack within the second gap region of the second gate stack such that dual gate stacks are defined for each of the first and second devices; and
annealing the dual gate stacks of the first and second devices to form first and second replacement metal gate stacks, respectively.

US Pat. No. 10,170,367

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:patterning a plurality of mandrels over a mask layer;
forming an etch coating layer on top surfaces of the mask layer and the mandrels;
depositing a dielectric layer over the mask layer and the mandrels with a deposition process, a first deposition rate of the deposition process along sidewalls of the mandrels being greater than a second deposition rate of the deposition process along the etch coating layer, a first thickness of the dielectric layer along the sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer;
removing horizontal portions of the dielectric layer; and
patterning the mask layer using remaining vertical portions of the dielectric layer as a first etching mask.

US Pat. No. 10,170,366

SEMICONDUCTOR DEVICE HAVING DUMMY GATES AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a plurality of active fins protruding from a substrate and extending in a first direction;
a first device isolation layer disposed at a first side of the active fins;
a second device isolation layer disposed at a second side of the active fins, wherein the second side is opposite to the first side;
a normal gate extending across the active fins in a second direction crossing the first direction;
a first dummy gate extending across the active fins and the first device isolation layer in the second direction;
a second dummy gate extending across the second device isolation layer in the second direction,
wherein the second dummy gate is disposed within a boundary of the second device isolation layer and the second dummy gate is spaced apart from the second side of the active fins, and
wherein a top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and top surfaces of the active fins; and
a third dummy gate extending across the first device isolation layer in the second direction,
wherein the third dummy gate is disposed within a boundary of the first device isolation layer and the third dummy gate is spaced apart from the first side of the active fins.

US Pat. No. 10,170,365

WRAP AROUND SILICIDE FOR FINFETS

Taiwan Semiconductor Manu...

1. A method comprising:forming a gate stack on a first portion of a semiconductor fin, wherein the semiconductor fin overlaps a semiconductor strip;
forming template dielectric regions on opposite sides of a second portion of the semiconductor fin;
forming a recess between the template dielectric regions, wherein the forming the recess comprises etching a top portion of the second portion of the semiconductor fin;
laterally expanding the recess to make the recess wider; and
epitaxially growing a source/drain region in the recess, wherein the source/drain region has substantially vertical sidewalls, and is wider than respective underlying portion of the semiconductor strip.

US Pat. No. 10,170,364

STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE

International Business Ma...

1. A method for forming strained fins, comprising:forming a staircase fin structure in a substrate with narrow top portions for fins;
epitaxially growing raised source and drain regions over the fins; and
performing a pre-amorphization implant to generate defects in the substrate to induce strain and to couple the strain into the top portions of the fins.

US Pat. No. 10,170,363

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. An interconnection structure of a semiconductor integrated circuit device comprising:a first conductive pattern having a first width and a first length;
a second conductive pattern arranged over the first conductive pattern, the second conductive pattern having a second width and a second length being different from the first length;
a dielectric layer interposed between the first conductive pattern and the second conductive pattern; and
a contact part configured to simultaneously make contact with the first conductive pattern and the second conductive pattern,
wherein the second conductive pattern is configured to expose an edge portion of the first conductive pattern, and the contact part is configured to make contact with the an edge portion of the second conductive pattern and the exposed edge portion of the first conductive pattern.

US Pat. No. 10,170,362

SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE CONTACT STRUCTURE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a substrate, comprising a first active region and a plurality of second active regions;
a shallow trench isolation, disposed in the substrate and between the first active region and the second active regions;
a bit line contact opening, disposed in the first active region and the shallow trench isolation;
a bit line contact structure, disposed in the bit line contact opening and contacts the first active region; and
a spacer disposed in the bit line contact opening, wherein the spacer has a sidewall directly contacting one of the second active regions;
a mask layer disposed on the second active regions and exposing the bit line contact opening;
wherein the spacer extends beneath the mask layer to contact the first active region.

US Pat. No. 10,170,361

THIN FILM INTERCONNECTS WITH LARGE GRAINS

International Business Ma...

1. An integrated circuit, comprising:a surface of the integrated circuit, the surface comprising a semiconductor;
a via-line-via interconnect formed from a metal and comprising:
a first via formed in the surface;
a line formed integrally with the first via and orientated perpendicularly relative to the first via, wherein the line and the first via share at least one common grain, and wherein the line is further formed on the surface and orientated parallel to the surface, wherein a thickness of the line is defined in a dimension perpendicular to the surface, and a line width of the line is defined in a dimension parallel to the surface and is within the range of two nanometers to eighty nanometers, wherein an average grain size of the metal of the line is greater than or equal to at least half of a line width of the line, wherein the line has a tapered cross section, and wherein the thickness of the line remains constant; and
a second via formed integrally with the line and orientated perpendicular relative to the line, wherein the line and the second via share at least one common grain, and wherein the line is positioned between the first via and the second via and between the surface and the second via,
such that the via-line-via interconnect exhibits grain continuity and material continuity between the first via and the line and between the line and the second via, where the grain continuity is evident in the line sharing a respective common grain with each of the first via and the second via; and
an insulator deposited on the surface and surrounding the interconnect, wherein the insulator is formed from a material that is different from a material from which the surface is formed.

US Pat. No. 10,170,360

REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing an opening in a dielectric-containing substrate;
forming a reflow enhancement layer in the opening and atop the dielectric-containing substrate;
forming a layer of a contact metal or metal alloy on the reflow enhancement layer;
performing a reflow anneal to completely fill a remaining volume of the opening with the contact metal or metal alloy of the layer of contact metal or metal alloy; and
removing the layer of contact metal or metal alloy, and the reflow enhancement layer located outside of the opening, wherein a portion of the layer of contact metal or metal alloy, and a portion of the reflow enhancement layer remain within the opening, and wherein the portion of the layer of contact metal or metal alloy that remains in the opening has a sidewall that is in direct physical contact with an inner sidewall of the portion of the reflow enhancement layer that remains in the opening.

US Pat. No. 10,170,359

DIFFUSION BARRIER LAYER FORMATION

International Business Ma...

1. A method of forming a titanium nitride diffusion barrier, the method comprising:exposing a deposition surface to a first pulse of a titanium-containing precursor gas to initiate a nucleation of the titanium nitride diffusion barrier in the deposition surface, wherein the deposition surface comprises sidewalls and a bottom of a contact opening;
exposing the deposition surface to a first pulse of a nitrogen-rich plasma to form a first titanium nitride layer with a first nitrogen concentration in the deposition surface, the first titanium nitride layer comprises a lower portion of the titanium nitride diffusion barrier;
exposing the first titanium nitride layer to a second pulse of the titanium-containing precursor gas to continue the nucleation of the titanium nitride diffusion barrier; and
exposing the first titanium nitride layer to a second pulse of the nitrogen-rich plasma to form a second titanium nitride layer with a second nitrogen concentration directly above and in contact with the first titanium nitride layer, the second titanium nitride layer comprises an upper portion of the titanium nitride diffusion barrier, wherein the second nitrogen concentration of the second titanium nitride layer is substantially increased by the second pulse of the nitrogen-rich plasma, the increased nitrogen concentration of the second titanium nitride layer lowers a reactivity of the upper portion of the titanium nitride diffusion barrier to prevent fluorine diffusion, and wherein the second pulse of the nitrogen-rich plasma has a substantially longer duration than the first pulse of the nitrogen rich plasma,
wherein the titanium nitride diffusion barrier comprises the first and the second titanium nitride layers; and
wherein the first pulse of the nitrogen-rich plasma has a duration of approximately 5 seconds and the second pulse of the nitrogen-rich plasma has a duration of approximately 60 seconds.

US Pat. No. 10,170,358

REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS

INTERNATIONAL BUSINESS MA...

1. An interconnect structure comprising:an interlevel dielectric layer on an electrically conductive feature;
an opening in the interlevel dielectric layer, the opening including a first width at a first depth into the interlevel dielectric layer, and a second width at a second depth that is greater than the first depth, wherein the second width is less than the first width of the opening and includes a portion of the opening that extends through the entirety of the interlevel dielectric layer into contact with the electrically conductive feature;
a conformal metal nitride layer present on vertical and horizontal surfaces of the opening, wherein the metal nitride layer is present directly on the interlevel dielectric layer;
a shield liner present over vertical sidewalls of the opening directly on the conformal metal nitride layer, wherein the conformal metal nitride layer is present between the interlevel dielectric layer and the shield liner; and
a contact extending through the opening into direct contact with the shield liner, the conformal metal nitride layer, and the electrically conductive feature, wherein a gouge is present at the interface of the contact and the electrically conductive feature.

US Pat. No. 10,170,357

SOI WAFER MANUFACTURING PROCESS AND SOI WAFER

SUMCO CORPORATION, Tokyo...

1. An SOI wafer manufacturing process, comprising:a first step of implanting light element ions to a surface of at least one of a first substrate made of silicon single crystal and a second substrate made of silicon single crystal to form, in the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution;
a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate;
a third step of bonding the first substrate and the second substrate in a manner such that the modified layer and the oxide film are located between the first substrate and the second substrate; and
a fourth step, performed after the third step, of thinning the first substrate to obtain an active layer, wherein,
in the second step, the oxide film is deposited by accelerating and emitting ionized Si and oxygen to the at least one of the first substrate and the second substrate while heating the at least one of the first substrate and the second substrate, and
in the third step, the first substrate and the second substrate are bonded together at a normal temperature by emitting an ion beam or a neutral atomic beam to surfaces to be bonded of the first substrate and the second substrate under vacuum to activate the surfaces and subsequently by contacting the surfaces to be bonded with each other under vacuum.

US Pat. No. 10,170,356

SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF

ZING SEMICONDUCTOR CORPOR...

1. A manufacturing method of silicon on insulator substrate, comprising the steps of: providing a first semiconductor substrate;forming a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer;
irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer;
providing a second substrate;
growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer;
bonding the first wafer with the second wafer face to face;
annealing the first wafer and second wafer at a deuterium atmosphere such that the doping layer is transferred to a plurality of deuterium-doped bubbles;
separating a part of the first wafer from the second wafer to remain;
forming a deuterium doped layer on the second wafer, wherein the pluralities of deuterium-doped bubbles are in the deuterium doped layer; and
heating the second wafer to a temperature between 600 centigrade degrees and 1200 centigrade degrees once again after separating the part of the first wafer from the second wafer.

US Pat. No. 10,170,355

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first dielectric layer disposed over a substrate;
a plurality of metal wirings surrounded by the first dielectric layer;
a second dielectric layer disposed over a portion of the first dielectric layer, wherein a portion of the second dielectric layer is disposed in a first recess between two adjacent metal wirings of the plurality of metal wirings; and
a third dielectric layer disposed over the first dielectric layer, the second dielectric layer, and the plurality of metal wirings, wherein a portion of the third dielectric layer is disposed in the first recess between the two metal wirings,
wherein the portion of the third dielectric layer comprises an upper portion and a lower portion, the upper portion being above the second dielectric layer and the lower portion being below the second dielectric layer.

US Pat. No. 10,170,354

SUBTRACTIVE METHODS FOR CREATING DIELECTRIC ISOLATION STRUCTURES WITHIN OPEN FEATURES

Tokyo Electron Limited, ...

1. A method for partially filling an open feature on a substrate, comprising:receiving a substrate having a layer with at least one open feature formed therein, the open feature penetrating into the layer from an upper surface and including sidewalls extending to a bottom of the open feature;
over-filling the open feature with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature;
removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature; and
converting the chemical composition of the organic coating plug to create an inorganic plug,
wherein the organic coating includes a polymeric material or co-polymeric material containing a carbonyl functionality, and
wherein removing the portion of the organic coating includes performing a wet etch process comprising:
exposing the organic coating to ultraviolet (UV) radiation to increase the solubility of the as-formed organic coating in a developing solution; and
controllably etching the organic coating to the pre-determined depth by exposing the organic coating to the developing solution.

US Pat. No. 10,170,353

DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

GLOBALFOUNDRIES Inc., Gr...

1. An intermediate semiconductor device comprising:a wafer comprising
a silicon substrate,
at least one first oxide layer disposed on at least a portion of the wafer,
at least one silicon layer disposed on the at least one first oxide layer,
at least one second oxide layer disposed on the at least one silicon layer,
at least one recess in the wafer,
at least one third oxide layer disposed on the wafer, wherein the at least one recess in the wafer is filled with the at least one third oxide layer,
at least one opening in the at least one recess, the at least one opening having sidewalls and a bottom surface,
a high k dielectric layer disposed on the sidewalls and the bottom surface of the at least one opening,
a work function material (WFM) layer disposed on at least a portion of the high k dielectric layer, and
at least one cavity within the at least one opening, wherein the at least one cavity is filled with metal and the at least one opening is filled with oxide.

US Pat. No. 10,170,352

MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

ALPAD CORPORATION, Tokyo...

1. A manufacturing apparatus, comprising:a first supporting section configured to support a first tape section, the first tape section having a first surface facing away from the first supporting section;
a second supporting section configured to support a second tape section in a facing arrangement with the first tape section supported on the first supporting section, the second tape section having a second surface facing away from the second supporting section;
a ring element configured to be between the first and second supporting sections when the first and second tape sections are in the facing arrangement, the ring element disposed at a periphery of a space that is between the first and second tape sections when in the facing arrangement, and having a port allowing fluid communication between the space and an outlet port;
a first frame having a ring-like shape with an inner diameter that is greater than or equal to an outer diameter of the ring element; and
a second frame having a ring-like shape with an inner diameter that is greater than or equal to the outer diameter of the rind element, wherein
the first and second frames are configured such that when the first and second tape sections are in the facing arrangement, the first and second frames are between the first and second supporting sections, the ring element is disposed within the inner diameters of first and second frames, an outer peripheral portion of the first tape section is between the first frame and the first supporting section, and an outer peripheral portion of the second tape section is between the second frame and the second supporting section frame, and
the ring element has a planar thickness that is greater than a sum of a planar thickness of the first frame and a planar thickness of the second frame.

US Pat. No. 10,170,351

TRANSFERRING APPARATUS AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing an integrated circuit device using a transferring apparatus,wherein the transferring apparatus comprises:
a rail connected to a frame;
a travelling part including a wheel that travels along the rail and a loading part below the rail for loading an object below the rail; and
a particle collection receptacle provided at a side of the rail and configured to collect particles generated due to friction between the wheel and the rail when the wheel travels along the rail, the method including:
moving the travelling part to the object;
picking up the object with the loading part thereby loading the object on the loading part;
using the travelling part to move the object to a chamber; and
forming a semiconductor device using the object.

US Pat. No. 10,170,350

CORRELATION BETWEEN CONDUCTIVITY AND PH MEASUREMENTS FOR KOH TEXTURING SOLUTIONS AND ADDITIVES

NAURA AKRION INC.

1. A method of etching material from at least one substrate, the method comprising:a) immersing the at least one silicon substrate in an etchant solution comprising KOH in a concentration ranging from 0.5 wt. % to 20 wt. % within a process chamber, the process chamber operably coupled to a recirculation line to form a closed-loop circulation system;
b) circulating a circulation volume of the etchant solution through the closed-loop circulation system;
c) repetitively measuring conductivity of the circulation volume of the etchant solution that is circulating through the closed-loop circulation system with a conductivity sensor; and
d) upon detecting that the circulation volume of the etchant solution has an average measured conductivity over a predetermined period of time that is at or below a lower threshold of conductivity, automatically performing a feed-and-bleed event that comprises: (i) bleeding a volume of contaminated etchant solution from the circulation volume of the etchant solution; and (ii) adding fresh etchant solution to the circulation volume of the etchant solution to increase the conductivity of the circulation volume of the etchant solution to a value that is greater than the lower threshold of conductivity but less than or equal to an upper threshold of conductivity.

US Pat. No. 10,170,349

SUBSTRATE TREATING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate treating apparatus comprising:a first solution treating unit for performing solution treatment of substrates;
a second solution treating unit for performing solution treatment of the substrates;
a third solution treating unit arranged substantially in an up-down direction with the first solution treating unit for performing solution treatment of the substrates;
a fourth solution treating unit arranged substantially in an up-down direction with the second solution treating unit for performing solution treatment of the substrates;
a first chamber for housing the first solution treating unit and the second solution treating unit;
a second chamber for housing the third solution treating unit and the fourth solution treating unit;
a first individual gas supply device provided to correspond to the first solution treating unit, for supplying gas at a variable rate to the first solution treating unit;
a second individual gas supply device provided to correspond to the second solution treating unit, for supplying gas at a variable rate to the second solution treating unit;
a third individual gas supply device provided to correspond to the third solution treating unit, for supplying gas at a variable rate to the third solution treating unit;
a fourth individual gas supply device provided to correspond to the fourth solution treating unit, for supplying gas at a variable rate to the fourth solution treating unit;
a first distributing pipe for distributing the gas to the first individual gas supply device and the third individual gas supply device; and
a second distributing pipe for distributing the gas to the second individual gas supply device and the fourth individual gas supply device;
wherein
the first individual gas supply device includes:
a first supply pipe extending in a first direction from an interior of the first chamber to an exterior of the first chamber; and
a first supply adjuster for adjusting the rate of gas supply to the first solution treating unit;
the second individual gas supply device includes:
a second supply pipe extending in a second direction from the interior of the first chamber to the exterior of the first chamber; and
a second supply adjuster for adjusting the rate of gas supply to the second solution treating unit; and
the first direction is different from the second direction.

US Pat. No. 10,170,348

PRODUCTION SYSTEM FOR PRINTING ELECTRONIC DEVICES

KONICA MINOLTA, INC., To...

1. A printing production system for an electronic device, whereina transport chamber provided with a robot transport line in which a self-traveling robot that transports a base material in a sheet-fed manner in a free state travels is provided,
a plurality of processing chambers for forming the electronic device on the base material by printing are provided on at least one side of the transport chamber,
a plurality of base material transfer areas, each of the base material transfer areas performs loading of the base material to a respective processing chamber of the processing chambers from the self-traveling robot and unloading of the base material to the self-traveling robot from the respective processing chamber,
the transport chamber and each of the base material transfer areas communicate with each other through respective openings that allow loading and unloading of the base material to be performed, a one-way air flow is formed in each of the respective openings moving to a side where the respective processing chamber is located from a side where the transport chamber is located, and
the one-way air flow in the each of the respective openings is formed by making an adjustment such that an air pressure in the transport chamber becomes higher than an air pressure in each of the base material transfer areas, wherein an air pressure P1 in the clean room, an air pressure P2 in the base material transfer areas, and an air pressure P3 in the transport chamber satisfy a relationship: P1

US Pat. No. 10,170,347

SUBSTRATE PROCESSING SYSTEM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing system for performing a process with respect to a plurality of substrates, comprising:an annular process chamber configured to accommodate the plurality of substrates and to perform a predetermined process on the plurality of substrates, the annular process chamber having an inner lateral surface and an outer lateral surface;
a cassette mounting part configured to mount a cassette which accommodates the plurality of substrates;
a substrate transfer mechanism configured to transfer the plurality of substrates between the annular process chamber and the cassette mounting part; and
a gate valve is installed in the inner lateral surface of the annular process chamber facing the substrate transfer mechanism,
wherein the plurality of substrates is concentrically disposed within the annular process chamber in a plane view,
wherein the substrate transfer mechanism is disposed in a space surrounded by the inner lateral surface of the annular process chamber, and
wherein a vacuum transfer chamber is installed adjacent to the annular process chamber in the space surrounded by the inner lateral surface of the annular process chamber, and the substrate transfer mechanism is disposed within the vacuum transfer chamber.

US Pat. No. 10,170,346

RESIN SEALING APPARATUS AND RESIN SEALING METHOD

TOWA CORPORATION, Kyoto-...

1. A resin sealing apparatus for providing resin sealing for a component to be sealed by a sealing resin which is cured in a cavity, comprising:an upper mold on which a substrate is disposed, a component to be sealed being attached to the substrate;
a lower mold provided to face the upper mold;
a cavity provided at least in the lower mold;
a bottom surface member forming an inner bottom surface of the cavity;
a side surface member forming a side surface of the cavity;
an opening provided in the side surface member and corresponding to an outer circumference of the bottom surface member;
an opening circumferential edge portion provided in the side surface member and having an inner edge shape formed to correspond to an outer edge of an end surface planar shape, an end surface of the sealing resin having the end surface planar shape;
an inclined surface portion provided in the side surface member and inclined to expand upwardly from the opening circumferential edge portion,
a frame-like member provided to surround a mold having at least the upper mold and the lower mold;
a space surrounded by the frame-like member and including the cavity;
a seal member for shutting off the space from ambient air; and
a pressure reducing mechanism for reducing pressure of the space with the space being shut off from the ambient air, wherein
the side surface member is fitted to the outer circumference of the bottom surface member so as to be slidable on the outer circumference, and
during a period from when the space is shut off from the ambient air to when a step of clamping the upper mold and the lower mold is completed, the pressure of the space shut off from the ambient air is reduced by the pressure reducing mechanism.

US Pat. No. 10,170,345

SUBSTRATE PROCESSING APPARATUS

Ebara Corporation, Tokyo...

1. A substrate processing apparatus comprising:a substrate processing table;
a processing device configured to perform a predetermined processing on the substrate processing table;
a nozzle configured to drop a fluid at a position that corresponds to a fluid dropping position set on the substrate processing table and is lower than a top surface of the processing device;
a nozzle moving mechanism configured to move the nozzle above the processing device between a retreat position set outside the substrate processing table and the fluid dropping position; and
a nozzle tip retreating mechanism configured to bring a tip end of the nozzle into a retreated state above the top surface of the processing device when the nozzle moves between the fluid dropping position and the retreat position,
wherein the nozzle tip retreating mechanism is an extension/contraction mechanism that extends and contracts the tip end of the nozzle.

US Pat. No. 10,170,344

WASHING DEVICE AND WASHING METHOD

EBARA CORPORATION, Tokyo...

1. A washing device comprising:a substrate rotation mechanism configured to hold a substrate and rotate the substrate about a central axis of the substrate as a rotary axis; a rinse supply; a chemical supply, wherein the chemical liquid is different than the rinse liquid;
a first single tube nozzle configured to discharge the rinse liquid from the rinse liquid supply as a first washing liquid toward an upper surface of the substrate held by the substrate rotation mechanism; and
a second single tube nozzle configured to discharge the chemical liquid from the chemical liquid supply as a second washing liquid toward the upper surface of the substrate held by the substrate rotation mechanism,
wherein the first single tube nozzle is placed to discharge the first washing liquid so that the first washing liquid lands in front of the center of the substrate and the landed first washing liquid flows on the upper surface of the substrate toward the center of the substrate,
a liquid flow on the upper surface of the substrate after landing of the first washing liquid discharged from the first single tube nozzle passes through the center of the substrate,
the second single tube nozzle is placed to discharge the second washing liquid so that the second washing liquid lands in front of the center of the substrate and the landed second washing liquid flows on the upper surface of the substrate toward the center of the substrate,
a second liquid flow on the upper surface of the substrate after landing of the second washing liquid discharged from the second single tube nozzle passes through the center of the substrate,
discharging of the first washing liquid by the first single tube nozzle and discharging of the second washing liquid by the second single nozzle are simultaneously performed, and
the first single tube nozzle supplies the first washing liquid so that a liquid-landing position of the first washing liquid is located in an area up to a 180° rotation in a reverse direction of a rotational direction of the substrate from the liquid-landing position of the second washing liquid.

US Pat. No. 10,170,343

POST-CMP CLEANING APPARATUS AND METHOD WITH BRUSH SELF-CLEANING FUNCTION

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus for performing a post Chemical Mechanical Polish (CMP) cleaning, the apparatus comprising:a chamber configured to receive a wafer in need of having CMP residue removed;
a spray unit configured to apply a first cleaning solution to at least one surface of the wafer;
a brush cleaner configured to scrub the at least one surface of the wafer; and
at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner;
wherein the at least one inner tank comprises an inner compartment and an outer compartment, wherein the inner compartment is configured to store the second cleaning solution and receive the brush cleaner, and the outer compartment is configured to receive the second cleaning solution overflowing from the inner compartment.

US Pat. No. 10,170,342

FLOW CONTROLLED LINER HAVING SPATIALLY DISTRIBUTED GAS PASSAGES

Applied Materials, Inc., ...

1. A liner assembly, comprising:a lower liner having an outer surface, an inner surface defining a processing volume, an upper surface connecting the outer surface to the inner surface, and a plurality of gas passages connecting the outer surface to the processing volume, each of the plurality of gas passages comprising a first portion connected to a second portion, each first portion opening to the outer surface of the lower liner and each second portion having an upper end open to the upper surface and a lower end connected to the first portion; and
an upper liner disposed adjacent to the lower liner, the upper liner including a plurality of flow guides aligned with the plurality of gas passages.

US Pat. No. 10,170,341

RELEASE FILM AS ISOLATION FILM IN PACKAGE

Taiwan Semiconductor Manu...

1. A method comprising:forming a release film over a carrier;
attaching a device over the release film through a die-attach film;
encapsulating the device in an encapsulating material;
performing a planarization on the encapsulating material to expose the device;
forming redistribution lines to electrically couple to the device;
detaching the device and the encapsulating material from the carrier while the die-attach film remains attached to the device;
after the detaching of the device and the encapsulating material from the carrier, removing the die-attach film to expose a back surface of the device; and
applying a thermal conductive material on the back surface of the device.

US Pat. No. 10,170,338

VERTICAL NANORIBBON ARRAY (VERNA) THERMAL INTERFACE MATERIALS WITH ENHANCED THERMAL TRANSPORT PROPERTIES

Northrop Grumman Systems ...

1. A method of manufacturing a thermal interface material (TIM), comprising the steps of:growing a vertically aligned carbon nanotube (VACNT) array on a substrate;
placing the VACNT array in an electrolyte solution;
anodically treating the VACNT to longitudinally cleave the carbon nanotubes (CNTs) into vertical graphene oxide nanoribbons (GONRs); and
processing the GONRs to remove oxygen and create an array of vertically aligned graphene nanoribbons (VERNA).

US Pat. No. 10,170,337

IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:disposing a mask on a substrate;
etching the mask to form an opening in the mask;
etching a trench in the substrate beneath the opening in the mask;
implanting a dopant, by an implantation technique, in an area of the substrate beneath the opening of the mask such that the dopant extends within the substrate from a substantially vertical sidewall of the trench and substantially horizontal bottom endwall of the trench, the dopant capable of gettering mobile ions that can contaminate the substrate; and
simultaneous with implanting the dopant, implanting a source/drain region of an nFET device adjacent the trench with an element selected from the group consisting of arsenic and phosphorous.

US Pat. No. 10,170,334

REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate structure over the semiconductor substrate; and
a plurality of chemical mechanical polish (CMP) resistant structures embedded in a top surface of the gate structure, the CMP resistant structures having a CMP resistance property different from a CMP resistance property of the gate structure,
wherein the gate structure comprises a base portion and a plurality fins protruding from the base portion, and each of the fins is connected to the base portion,
wherein the CMP resistant structures and the fins are arranged in an alternating manner along a first lengthwise direction,
wherein the CMP resistant structures extend along a second lengthwise direction which is different from the first lengthwise direction.

US Pat. No. 10,170,333

GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT

Taiwan Semiconductor Manu...

1. A semiconductor arrangement, comprising:a first guard ring surrounding at least a portion of a device, the first guard ring comprising:
a first guard ring portion; and
a second guard ring portion, the second guard ring portion being discontinuous from the first guard ring portion and the first guard ring portion coupled to the second guard ring portion by a first metal layer; and
a first poly layer over the first guard ring.

US Pat. No. 10,170,332

FINFET THERMAL PROTECTION METHODS AND RELATED STRUCTURES

Taiwan Semiconductor Manu...

14. A method, comprising:providing a substrate including a plurality of fins and interposing dielectric features;
after providing the plurality of fins and interposing dielectric features, forming a dummy channel on an end of each of the plurality of fins, wherein the dummy channel has a different composition than each of the plurality of fins;
recessing the interposing dielectric features to expose the dummy channel;
after recessing the interposing dielectric features, forming a dummy gate stack over the exposed dummy channel and forming source/drain regions in each of the plurality of fins;
depositing a first inter-layer dielectric (ILD) layer on the substrate including the plurality of fins;
planarizing the first ILD layer to expose the dummy gate stack;
after planarizing the first ILD layer, removing the dummy gate stack and etching the dummy channel to form a recess in each of the plurality of fins; and
forming a material in the recess in each of the plurality of fins.

US Pat. No. 10,170,331

STACKED NANOWIRES

International Business Ma...

1. A method of forming silicon germanium (SiGe) nanowires, the method comprising the steps of:forming a stack of alternating silicon (Si) and SiGe layers on a wafer;
patterning fins in the stack;
selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape, wherein the SiGe layers in the fins are selectively thinned using an anisotropic wet etching process, and wherein the anisotropic wet etching process results in a v-shaped notching of the SiGe layers in the fin stack;
burying the fins in an oxide material; and
annealing the fins under conditions sufficient to diffuse germanium (Ge) from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires.

US Pat. No. 10,170,330

METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:providing a carbon-doped material layer within a recess of a semiconductor structure;
removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer, wherein the removing comprises subjecting the carbon-doped material layer to remote plasma to facilitate removing, in part, carbon therefrom, and wherein the remote plasma comprises ozone; and
recessing the carbon-depleted region of the carbon-doped material layer by an etching process, wherein the carbon-depleted region is recessed based upon, in part, the modified etch property thereof, leaving a portion of the carbon-doped material layer in a horizontal layer, adjacent to and contacting at least one vertical structure, the vertical structure including, at least in part, silicon.

US Pat. No. 10,170,329

SPACER FORMATION FOR SELF-ALIGNED MULTI-PATTERNING TECHNIQUE

Tokyo Electron Limited, ...

1. A method of forming a spacer pattern on a substrate, the method comprising:providing a substrate with a plurality of spacer cores having a conformal coating of spacer material thereon wherein the conformal coating includes bottom portions on the substrate between the plurality of spacer cores, sidewall portions on sidewalls of the plurality of spacer cores, top portions on top surfaces of the plurality of spacer cores, and shoulder portions joining the sidewall portions and the top portions;
performing a spacer freeze treatment process that forms a buildup of byproducts on the shoulder portions of the conformal coating while leaving the top and bottom portions exposed;
performing an etch and clean process on the substrate to remove the exposed top and bottom portions of the conformal coating and to remove the plurality of spacer cores to substantially leave the sidewall portions as the spacer pattern, wherein the buildup of byproducts serves as a protective layer to reduce etching of the sidewall portions; and
controlling one or more process parameters of the spacer freeze treatment process and the etch and clean process in order to achieve one or more spacer formation objectives selected from a target height of the spacer pattern, a target maximum facet depth on the spacer pattern, a target critical dimension of the spacer pattern, a target maximum height difference between the plurality of spacer cores and the spacer pattern, a target uniformity of the spacer pattern, and a target maximum amount of spacer footings in the spacer pattern.

US Pat. No. 10,170,327

FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES

International Business Ma...

1. A method for fabricating multigate devices comprising:forming a mandrel on a semiconductor substrate;
forming a first sidewall composed of a first material directly in contact with the mandrel previously formed on the semiconductor substrate; and
forming a second sidewall composed of a second material that is different from the first material directly in contact with the mandrel, wherein the second sidewall is opposite the first sidewall on the same mandrel.

US Pat. No. 10,170,326

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element fabrication method, comprising:patterning photoresist (PR) over an anti-reflective coating (ARC) disposed over a planarization layer (PL) and a substrate,
the patterning comprising forming the PR into PR device element and adjusted print resolution assist feature (APRAF) sections having first and second dimensions, respectively;
removing portions of the ARC and the PR device element and APRAF sections such that ARC device element and APRAF posts remain underneath remainders of the PR device element and APRAF sections having third and fourth dimensions based on the first and second dimensions, respectively;
removing the remainders of the PR device element and APRAF sections and portions of the PL such that PL device element and APRAF posts remain underneath the ARC device element and APRAF posts; and
removing the ARC device element and APRAF posts such that the PL device element and APRAF posts remain with fifth and sixth dimensions based on the third and fourth dimensions, respectively.

US Pat. No. 10,170,325

HARDMASK COMPOSITION AND METHOD OF FORMING PATTERN BY USING THE HARDMASK COMPOSITION

Samsung Electronics Co., ...

1. A hardmask composition comprising:a 2-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen, an intensity ratio of a D mode peak to a G mode peak obtained by Raman spectroscopy of the 2-dimensional carbon nanostructure being 2 or lower; and
a solvent, wherein
a fraction of sp2 carbon is equal to or a multiple of a fraction of sp3 carbon in the 2-dimensional carbon nanostructure.

US Pat. No. 10,170,324

TECHNIQUE TO TUNE SIDEWALL PASSIVATION DEPOSITION CONFORMALITY FOR HIGH ASPECT RATIO CYLINDER ETCH

Lam Research Corporation,...

1. A method of forming an etched feature in a substrate comprising dielectric material, the method comprising:(a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the substrate;
(b) after (a), depositing a protective film on sidewalls of the feature, wherein the protective film is deposited through a plasma assisted atomic layer deposition reaction comprising:
(i) exposing the substrate to a first deposition reactant and allowing the first deposition reactant to adsorb onto the sidewalls of the feature;
(ii) after (i), exposing the substrate to a second plasma comprising a second deposition reactant, wherein exposing the substrate to the second plasma drives a surface reaction between the first deposition reactant and the second deposition reactant, thereby forming the protective film on the sidewalls of the feature; and
(c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,170,323

TECHNIQUE TO DEPOSIT METAL-CONTAINING SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH

Lam Research Corporation,...

1. A method of etching a feature in a dielectric-containing stack on a substrate, the method comprising:(a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the dielectric-containing stack;
(b) after (a), depositing a protective film on sidewalls of the feature, the protective film comprising a metal, wherein the protective film comprises an electrically conductive film; and
(c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,170,322

ATOMIC LAYER DEPOSITION BASED PROCESS FOR CONTACT BARRIER LAYER

TAIWAN SEMICONDUCTOR MANU...

9. A method comprising:forming a contact opening in a dielectric layer;
performing at least one first cycle of a first nitrogen-containing plasma pulse and a first purge, thereby nitridizing surfaces of the dielectric layer that define the contact opening;
performing at least one second cycle of a titanium-containing pulse, a second purge, a second nitrogen-containing plasma pulse, and a third purge, thereby forming a titanium nitride layer on the nitridized surfaces of the dielectric layer that define the contact opening; and
forming a cobalt layer on the titanium nitride layer.

US Pat. No. 10,170,321

ALUMINUM CONTENT CONTROL OF TIAIN FILMS

Applied Materials, Inc., ...

1. A method of depositing a TiAlN film on a substrate surface, the method comprising:exposing the substrate surface to a titanium precursor to form a titanium-containing film on the substrate surface;
purging unreacted titanium precursor from the substrate surface;
exposing the titanium-containing film on the substrate surface to a nitrogen reactant to form a TiN film on the substrate surface;
purging unreacted nitrogen reactant from the substrate surface; and
exposing the TiN film on the substrate surface to an aluminum precursor to form a TiAlN film, wherein the titanium precursor comprises substantially only TiBr4.

US Pat. No. 10,170,320

FEATURE FILL WITH MULTI-STAGE NUCLEATION INHIBITION

Lam Research Corporation,...

1. A method comprising:providing a substrate including a feature having one or more feature openings and a feature interior; and
performing a multi-stage inhibition treatment comprising exposing the feature to a plasma generated from a treatment gas in multiple stages and multiple intervals, with successive stages separated by one of the multiple intervals, wherein one or more of a plasma source power, a substrate bias power, or a treatment gas flow rate is reduced at the start of each interval and increased at the end of the interval, and wherein the inhibition treatment preferentially inhibits nucleation of a metal at the feature openings.

US Pat. No. 10,170,319

FORMING A CONTACT FOR A TALL FIN TRANSISTOR

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a recessed fin in a substrate, a top surface of the recessed fin being flush with a top surface of the substrate, and the recessed fin having a uniform height along an entire length of the recessed fin;
performing an epitaxial growth process over the recessed fin to form a discrete source/drain over the recessed fin, the discrete source/drain having a width that is wider than a width of the recessed fin; and
disposing a conductive metal around the source/drain.

US Pat. No. 10,170,318

SELF-ALIGNED CONTACT AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

15. A device comprising:a gate stack over a semiconductor structure, the semiconductor structure having a first source/drain region, a second source/drain region, and a channel region interposed between the first source/drain region and the second source/drain region, the gate stack being over the channel region;
a gate mask over the gate stack, the gate mask comprising:
a first dielectric layer over the gate stack, the first dielectric layer having a first Cl content;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second Cl content, the first Cl content being different from the second Cl content; and
a third dielectric layer over the second dielectric layer, a first portion of the third dielectric layer having a lower etch rate than a second portion of the third dielectric layer; and
a capping layer over the gate mask.

US Pat. No. 10,170,317

SELF-PROTECTIVE LAYER FORMED ON HIGH-K DIELECTRIC LAYER

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a first gate structure and a second gate structure formed on a substrate; wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further comprises:
a gate dielectric layer;
a self-protective layer having metal phosphate; and
the first work function metal on the self-protective layer.

US Pat. No. 10,170,316

CONTROLLING THRESHOLD VOLTAGE IN NANOSHEET TRANSISTORS

International Business Ma...

1. A semiconductor device comprising:a nanosheet stack over a substrate, the nanosheet stack comprising a first nanosheet vertically stacked over a second nanosheet;
an inner nitride layer on a surface of each nanosheet; and
a doped transition metal layer on each inner nitride layer formed from alternating pulses of a first precursor comprising a transition metal and a second precursor comprising an aluminum carbide.

US Pat. No. 10,170,315

SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device comprising:a substrate;
a gate disposed over the substrate;
a local buried oxide region formed in the substrate such that the buried oxide region is formed entirely under the gate, the buried oxide region is dispose between vertically extending planes of sidewalls of the gate and the buried oxide region does not extend outwardly laterally beyond the vertically extending planes;
a channel defined in the substrate between the gate and the local buried oxide region, the channel having a first end and a second end;
a source defined at the first end of the channel; and
a drain defined at the second end of the channel.

US Pat. No. 10,170,314

PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN

Intel Corporation, Santa...

1. A transistor, comprising:a semiconductor substrate including a channel region disposed below a gate stack; and
semiconductor source/drain regions coupled to the channel region and disposed on opposite ends of the channel region with the gate stack disposed there between, wherein the semiconductor source/drain regions comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth, the super-activated dopant region having a higher activated dopant concentration than the activated dopant region, wherein the melt depth is substantially the same along the entirety of the semiconductor source/drain regions, and wherein the higher activated dopant concentration is a constant over the super-activated dopant region while the activated dopant concentration is not a constant over activated dopant region.

US Pat. No. 10,170,313

SYSTEMS AND METHODS FOR A TUNABLE ELECTROMAGNETIC FIELD APPARATUS TO IMPROVE DOPING UNIFORMITY

Taiwan Semiconductor Manu...

8. A dopant tool comprising:a chamber sized to contain a wafer;
a plasma generator to accelerate particles toward a wafer support structure; and
an electromagnetic structure disposed between the plasma generator and the wafer support structure, the electromagnetic structure encircling the wafer support structure, wherein the electromagnetic structure comprises a plurality of electromagnetic elements whose positions are movable independently of each other.

US Pat. No. 10,170,312

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, comprising:providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type;
forming a polysilicon layer over the front surface;
forming an oxide layer over a back surface of the semiconductor wafer;
removing the polysilicon layer from the front surface; and
depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature, the second dopant concentration being lower than the first dopant concentration,
wherein a defect density in a center portion of the semiconductor wafer is below 1E9/cm3 from a cross sectional perspective after depositing the epitaxial layer at the front surface.

US Pat. No. 10,170,311

METHOD FOR HANDLING THIN BRITTLE FILMS

International Business Ma...

1. A method comprising:providing a structure comprising:
a spalled layer having a first side and a second side; anda tape layer formed on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range, wherein the structure comprises providing a stressor layer on the first side of the spalled layer, and a providing the tape layer as a handle layer on the stressor layer;applying a temporary substrate layer to the second side of the spalled layer,
wherein the temporary substrate layer is applied at a second temperature range, and
wherein at least a portion of the second temperature range is lower than the first temperature range;
after applying the temporary substrate layer, separating the tape layer from the spalled layer; and
after separating the tape layer from the spalled layer, separating the stressor layer from the spalled layer.

US Pat. No. 10,170,310

METHOD OF FORMING PATTERNED STRUCTURE

UNITED MICROELECTRONICS C...

1. A method of forming a patterned structure, comprising:forming a dielectric layer and a material layer on a substrate sequentially;
forming a hard mask layer on the material layer, wherein the material of the hard mask layer is identical to the material of the dielectric layer;
forming a first patterned mask on the hard mask layer and performing a first etching process using the first patterned mask as a mask for forming at least one first opening in the hard mask layer, wherein the first opening exposes at least a part of the material layer;
removing the first patterned mask after the first etching process;
forming a second patterned mask on the hard mask layer and performing a second etching process using the second patterned mask as a mask after the first etching process for forming at least one second opening in the hard mask layer, wherein the second opening exposes at least a part of the material layer, and the second opening partially overlaps the first opening;
performing a third etching process to the material layer with the hard mask layer having the first opening and the second opening as a mask for removing the material layer exposed by the first opening and the second opening; and
performing a fourth etching process to the dielectric layer and the hard mask layer after the third etching process for removing the hard mask layer and forming a trench in the dielectric layer.

US Pat. No. 10,170,309

DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor device, comprising:forming a first masking layer over a semiconductor substrate, the first masking layer comprising first features; and
forming a second masking layer over the semiconductor substrate, the second masking layer comprising second features, wherein
a first portion of the first features are formed laterally adjacent to the second features, a second portion of the first features entirely overlie the second features, a first portion of the second features are formed laterally adjacent to the first features, and a second portion of the second features entirely overlie the first features, wherein the first features have a constant width and the second features have a constant width different from the width of the first features, and wherein the semiconductor device comprises an SRAM.

US Pat. No. 10,170,308

FABRICATING SEMICONDUCTOR DEVICES BY CROSS-LINKING AND REMOVING PORTIONS OF DEPOSITED HSQ

International Business Ma...

1. A method of manufacturing a semiconductor device, comprising:forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate;
forming a cap layer on the HSQ layer;
cross-linking a portion of the HSQ layer under the cap layer;
removing another portion of the HSQ layer which was not cross-linked;
forming a dielectric layer on the substrate, wherein the dielectric layer is positioned between the HSQ layer and the semiconductor substrate;
forming at least one opening exposing a portion of the semiconductor substrate through the cap layer, HSQ layer and dielectric layer; and
epitaxially growing a III-V semiconductor material from the exposed portion of the semiconductor substrate, wherein the III-V semiconductor material occupies a vacant area left by the removal of the other portion of the HSQ layer was not cross-linked;
wherein the removing comprises introducing a developer through the at least one opening to remove the other portion of the HSQ layer which was not cross-linked.

US Pat. No. 10,170,307

METHOD FOR PATTERNING SEMICONDUCTOR DEVICE USING MASKING LAYER

Taiwan Semiconductor Manu...

1. A method comprising:forming a first mask layer on a substrate;
patterning first spacers over the first mask layer;
forming an anti-reflective layer over the first spacers;
forming an etch stop layer over the anti-reflective layer;
forming a second mask layer over the etch stop layer;
patterning first openings in the second mask layer, each of the first openings overlying respective pairs of the first spacers;
after patterning the first openings, patterning second openings in the second mask layer, each of the second openings overlying respective pairs of the first spacers;
extending the first and second openings through the anti-reflective layer and between the respective pairs of the first spacers;
forming a reverse material over the second mask layer and in the first and second openings;
removing the anti-reflective layer, the etch stop layer, the second mask layer, and portions of the reverse material; and
patterning the first mask layer using the first spacers and remaining portions of the reverse material as a first etching mask.

US Pat. No. 10,170,306

METHOD OF DOUBLE PATTERNING LITHOGRAPHY PROCESS USING PLURALITY OF MANDRELS FOR INTEGRATED CIRCUIT APPLICATIONS

Taiwan Semiconductor Manu...

1. A method comprising:forming mandrels comprising a first mandrel strip, wherein the first mandrel strip comprises a first portion and a second portion separated from each other by a first opening;
depositing a blanket spacer layer over the first mandrel strip;
etching horizontal portions of the blanket spacer layer to form spacers, wherein the first opening is filled by a portion of the spacers;
etching the first portion and the second portion of the first mandrel strip to form a second opening and a third opening encircled by the mandrels and the spacers; and
using the mandrels and the spacers as an etching mask to etch a target layer, with trenches formed in the target layer.

US Pat. No. 10,170,305

SELECTIVE FILM GROWTH FOR BOTTOM-UP GAP FILLING

Taiwan Semiconductor Manu...

1. A method comprising:etching a portion of a semiconductor material between isolation regions to form a trench;
forming a first semiconductor seed layer extending on a bottom surface and sidewalls of the trench;
etching-back the first semiconductor seed layer until a top surface of the first semiconductor seed layer is lower than top surfaces of the isolation regions;
performing a first selective epitaxy to grow a first semiconductor region from the first semiconductor seed layer; and
forming an additional semiconductor region over the first semiconductor region to fill the trench.

US Pat. No. 10,170,304

SELF-ALIGNED NANOTUBE STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising at least one nanotube structure between adjacent fin structures and supported by a plurality of spacers, and an insulator material between the spacers which contacts the spacers at a bottom surface thereof, the spacers and the insulator material lining the adjacent fin structures.

US Pat. No. 10,170,303

GROUP IIIA NITRIDE GROWTH SYSTEM AND METHOD

1. A method for growing a gallium nitride (GaN) structure comprising:providing a template having a surface; and
growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes:
growing the at least first GaN layer under at least two surface conditions, wherein the two surface conditions include a gallium-rich surface condition and a gallium-lean surface condition, wherein the gallium-rich surface condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, wherein the gallium-lean surface condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value;
alternating between the two surface conditions for at least a first growing under a first of the two surface conditions, a second growing under a second of the two surface conditions after the first growing, and a third growing under the first of the two surface conditions after the second growing.

US Pat. No. 10,170,302

SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR

International Business Ma...

1. A method for forming a bipolar junction transistor, comprising:patterning an extrinsic base on a superlattice stack including a plurality of alternating layers of semiconductor material on a substrate;
etching an intrinsic base in the superlattice stack; and
growing a collector and emitter adjacent to the intrinsic base on opposite sides of the intrinsic base.

US Pat. No. 10,170,301

ADHESION OF POLYMERS ON SILICON SUBSTRATES

INTERNATIONAL BUSINESS MA...

1. A method for adhering a polymer to a surface of a substrate, the method comprising:forming a substrate;
forming a modified surface of the substrate, where the modified surface comprises X—H terminations;
forming a polymer on the modified surface of the substrate, the polymer comprising a self-crosslinkable organic planarization layer (OPL) comprising hydroxyl, alkene, or alkyne functional group functional groups; and
chemically bonding the polymer to the modified surface of the substrate.

US Pat. No. 10,170,300

PROTECTIVE FILM FORMING METHOD

Tokyo Electron Limited, ...

1. A protective film forming method, comprising steps of:depositing an oxide film of either an organic metal compound or an organic metalloid compound on a flat surface region between adjacent recessed shapes formed in a surface of a substrate; and
removing a lateral portion of the oxide film deposited on the flat surface region by etching.

US Pat. No. 10,170,299

METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK

Applied Materials, Inc., ...

1. A method for forming an interconnect on a substrate, comprising:depositing a continuous barrier layer on the substrate formed from SiOC;
depositing a transition layer on the barrier layer formed from SiCN after depositing the continuous barrier layer; and
depositing an etch-stop layer on the transition layer formed from AlN after depositing the transition layer, wherein the transition layer shares a first common element with every layer contacting a bottom surface of the transition layer, and wherein the transition layer shares a second common element with every layer contacting a top surface of the transition layer, the first common element different from the second common element.

US Pat. No. 10,170,298

HIGH TEMPERATURE SILICON OXIDE ATOMIC LAYER DEPOSITION TECHNOLOGY

APPLIED MATERIALS, INC., ...

1. A method of depositing a film, the method comprising:exposing a wafer surface to a silicon precursor that adsorbs onto the wafer surface, the silicon precursor comprising R3Si:NY3, wherein each R is independently selected from hydrogen, Cl, Br, I, a linear or branched C1-C10 alkyl group, a linear or branched C1-C10 alkoxy group, and a C6-C10 aryl group, and each Y is independently selected from the group consisting of Cl, Br, I, a linear or branched C1-C10 alkylsilyl group, and a C6-C10 aryl group;
heating the wafer surface to a temperature in the range of about 450° C. to about 650° C. to decompose the adsorbed silicon precursor on the wafer surface to form a monolayer or sub-monolayer silicon film; and
exposing the monolayer or sub-monolayer silicon film and wafer surface to an oxygen source, wherein the oxygen source reacts with the monolayer or sub-monolayer silicon film to form a monolayer or sub-monolayer SiO2 film.

US Pat. No. 10,170,296

TIN PULL-BACK AND CLEANING COMPOSITION

BASF SE, Ludwigshafen (D...

1. A composition, comprising the following components a)-f), based on total weight of the composition:a) 0.05-4 wt. % of an aliphatic or aromatic sulfonic acid;
b) 0.1 to 10 wt % of an inhibitor selected from the group consisting of imidazolidinones, imidazolidines, and 2-oxazolidinones;
c) 5 to 50 wt % of an aprotic solvent;
d) 1 to 60 wt % of a glycol ether;
e) water; and
an oxidant,
wherein a weight ratio of the aprotic solvent to the water is from 1:10 to 2:1 and wherein the oxidant is present in a volume ratio of components a) to e)to the oxidant ranging from 65:1 to 8:1.

US Pat. No. 10,170,295

FLUX RESIDUE CLEANING SYSTEM AND METHOD

Taiwan Semiconductor Manu...

11. A method comprising:softening an outer region of a flux residue formed around conductive connectors interposed between a wafer and a die by immersing the wafer and the die in a first chemical, the wafer having a first side, the die being disposed on the first side of the wafer;
after the softening the outer region of the flux residue, removing the outer region of the flux residue to expose an inner region of the flux residue by discharging a first chemical spray in a first spray chamber, the first chemical spray impinging on the flux residue, the removing the outer region of the flux residue comprising rotating the wafer during the impinging the first chemical spray upon the wafer in the first spray chamber;
after the removing the outer region of the flux residue, softening the inner region of the flux residue formed around conductive connectors interposed between the wafer and the die by immersing the wafer and the die in a second chemical, the second chemical comprising a surfactant; and
after the softening the inner region of the flux residue, removing the inner region of the flux residue by discharging a second chemical spray in a second spray chamber, the first chemical spray or the second chemical spray or both comprising deionized water.

US Pat. No. 10,170,294

CONDUCTIVE STRUCTURE, LIGHTING FIXTURE, AND LIGHTING FIXTURE ASSEMBLING METHOD

XIAMEN ECO LIGHTING CO. L...

1. A conductive structure, comprising:a plurality of conductive devices;
a first conductive spring sheet, comprising a first connecting point; and
a second conductive spring sheet, comprising a second connecting point;
wherein each of the conductive devices comprises a first conductive end and a second conductive end;
wherein the second conductive end is connected to the second connecting point, and the first conductive end is connected to the first connecting point corresponding to the second connecting point to which the second conductive end is connected.

US Pat. No. 10,170,293

ENHANCED LIGHTING CERAMIC METAL-HALIDE LAMP ASSEMBLY

1. An enhanced lighting ceramic metal-halide lamp assembly, the assembly comprising:an at least partially transparent container defined by an inner surface, an outer surface, a pair of sealed conductive ends, and an inner volume defined by a vacuum;
a plurality of ceramic arc tubes disposed in the inner volume of the at least partially transparent container, the ceramic arc tubes being filled with an ionizable gaseous mixture;
a ballast disposed in the inner volume of the ceramic arc tubes, the ballast comprising at least one electrode generating an electric arc through the ionizable gaseous mixture;
whereby the electric arc vaporizes the gaseous mixture to generate illumination;
whereby the ceramic arc tube produces about 630 watts of power when illuminating;
a wire extending between the pair of sealed conductive ends of the at least partially transparent container, the wire carrying an electrical current through the ballast;
two U-shaped coupling mechanisms integral to the wire, the two U-shaped coupling mechanisms connecting each of the ceramic arc tubes to one of the sealed conductive ends of the container, the two U-shaped coupling mechanisms defined by a conductive material, the two U-shaped coupling mechanisms being generally resilient;
whereby the two U-shaped coupling mechanisms provide conductivity and a buffering clearance between the ceramic arc tubes and the sealed conductive ends of the container; and
at least one fastening bracket defined by a first end and a second end, the first end engaging the inner surface of the at least partially transparent container for stabilizing the ceramic arc tubes, the second end engaging the ceramic arc tubes.

US Pat. No. 10,170,292

METHOD AND APPARATUS FOR INJECTION OF IONS INTO AN ELECTROSTATIC ION TRAP

Thermo Fisher Scientific ...

1. An apparatus for injecting ions into an electrostatic trap, comprising:an ion source for generating ions;
an ion store downstream of the ion source for receiving ions that have been generated in the ion source;
a non-trapping ion guide downstream of the ion store for receiving ions that have been released by the ion store and for accelerating the received ions into an orbital electrostatic trap downstream of the ion guide; and
a pulser configured to provide a voltage pulse in the ion guide for increasing the average velocity of the ions at the exit of the ion guide from the average velocity of the ions at the entrance to the ion guide, wherein a delay is arranged between releasing the ions from the ion store and providing the voltage pulse to the ion guide such that for ions of the same m/z forming an ion packet, the duration of the ion packet as it enters the electrostatic trap is substantially shorter than when the ion packet enters the ion guide from the ion store.

US Pat. No. 10,170,291

APPARATUS FOR ON-LINE MONITORING PARTICLE CONTAMINATION IN SPECIAL GASES

Industrial Technology Res...

1. An apparatus for on-line monitoring particle contamination in a special gas, comprising:a single particle inductively coupled plasma mass spectrometry (sp-ICPMS); and
a gas exchange device, coupled to the sp-ICPMS and comprising:
a corrosion resistant outer tube; and
a polytetrafluoroethylene (PTFE) inner tube, disposed inside the corrosion resistant outer tube, a gap being formed between the corrosion resistant outer tube and the PTFE inner tube, and a length of the PTFE inner tube being 1 meter or more, wherein
the gap is applied for flowing an argon gas, and the PTFE inner tube is applied for flowing the special gas.

US Pat. No. 10,170,290

SYSTEMS AND METHODS FOR GROUPING MS/MS TRANSITIONS

THERMO FINNIGAN LLC, San...

1. A method for analyzing a sample, comprising:identifying a plurality of precursors for analysis;
grouping the precursors into two or more groups, such that the precursors within a group conform to at least the following criteria:
a) masses of ions of the precursors in the group are within a first mass range;
b) masses of product ions of the precursors in the group are within a second mass range;
c) the number of precursors within the group is below a maximum allowable number of precursors; and
d) each precursor within the group has at least one unique product ion that differs from the product ions of all the other precursors within the group;
generating ions from the sample;
isolating precursor ions of a group;
fragmenting the ions of the group;
determining the mass-to-charge ratio of the fragment ions;
repeating the isolating, fragmenting, and determining steps for additional groups;
identifying or quantifying the presence of one or more precursors within the sample based on the presence of fragmented ions having a mass-to-charge ratio corresponding to the unique product ion for the precursor.

US Pat. No. 10,170,289

PHOTOTUBE AND METHOD OF MAKING IT

Shenzhen Genorivision Tec...

1. A phototube suitable for detecting a photon, the phototube comprising:an electron ejector configured for emitting electrons in response to an incident photon;
a detector configured for collecting the electrons and providing an output signal representative of the incident photon;
an electrode configured for applying a voltage to drive the electrons to the detector;
one or more sidewalls forming an envelope of a hole between the electrode and the detector, wherein the electron ejector is inside the hole and bonded to the electrode, wherein the hole is in a substrate; and
a metal wall at the one or more sidewalls, wherein the metal wall is configured for applying a voltage to drive the electrons away from the sidewalls.

US Pat. No. 10,170,288

SPUTTERING APPARATUS

Sakai Display Products Co...

1. A sputtering apparatus, comprising:a processing chamber;
a target disposed in the processing chamber;
a holding body for receiving a rear surface of a substrate to be disposed in the processing chamber so that a front surface of the substrate faces the target;
a substrate retainer for covering and pressing a peripheral portion of the front surface of the substrate, the substrate retainer defining an outer edge of a film deposition region of the front surface in which a metal film is to be formed by sputtering the target in the processing chamber;
a deposition preventive plate which covers the holding body including the substrate retainer without covering the film deposition region so as to prevent unnecessary formation of the metal film on the substrate retainer and the holding body; and
a stopper protrusion provided in a region where the deposition preventive plate directly faces the holding body, the stopper protrusion protruding from one of the deposition preventive plate and the holding body toward the other of the deposition preventive plate and the holding body so as to prevent the deposition preventive plate from contacting the substrate retainer.

US Pat. No. 10,170,287

TECHNIQUES FOR DETECTING MICRO-ARCING OCCURRING INSIDE A SEMICONDUCTOR PROCESSING CHAMBER

Taiwan Semiconductor Manu...

1. A system comprising:a radio frequency (RF) generator configured to output a RF signal;
a transmission line coupled to the RF generator;
a plasma chamber coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal; and
a micro-arc detecting element configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal;
wherein the micro-arc detecting element comprises:
a magnetic-field sensor configured to generate a magnetic-field signal based on the RF signal passing through the transmission line; and
analysis circuitry configured to evaluate the magnetic-field signal to determine whether the micro-arc has occurred in the plasma chamber.

US Pat. No. 10,170,286

IN-SITU CLEANING USING HYDROGEN PEROXIDE AS CO-GAS TO PRIMARY DOPANT OR PURGE GAS FOR MINIMIZING CARBON DEPOSITS IN AN ION SOURCE

Axcelis Technologies, Inc...

1. An ion source assembly for improving ion implantation performance, the ion source assembly comprising:an ion source chamber;
a source gas supply configured to provide a molecular carbon source gas to the ion source chamber;
a source gas flow controller configured to control a flow of the molecular carbon source gas to the ion source chamber during periods of ion implantation;
an excitation source configured to excite the molecular carbon source gas, therein forming carbon ions and residual carbon;
an extraction electrode configured to extract the carbon ions from the ion source chamber, therein forming an ion beam;
a hydrogen peroxide co-gas supply configured to provide a predetermined concentration of hydrogen peroxide gas to the ion source chamber;
a hydrogen peroxide co-gas flow controller configured to control a flow of the hydrogen peroxide gas to the ion source chamber as a purge gas during periods of non-implantation, wherein the hydrogen peroxide gas decomposes within the ion source chamber and reacts with the residual carbon from the molecular carbon source gas in the ion source chamber, therein forming hydrocarbons within the ion source chamber; and
a vacuum pump system configured to remove the hydrocarbons from the ion source chamber, wherein deposition of the residual carbon within the ion source chamber is reduced and a lifetime of the ion source chamber is increased.

US Pat. No. 10,170,285

METHOD OF OPERATING SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICES

BEIJING NAURA MICROELECTR...

1. A method of operating a semiconductor manufacturing apparatus that includes a match network, the method comprising:applying a radio frequency (RF) signal to the match network at a first terminal and a second terminal;
establishing an RF energy by the match network for generating plasma in response to the RF signal, the match network including a first inductive device coupled between the first terminal and a first voltage level, a second inductive device directly coupled between the second terminal and the first voltage level, and a first node being between the second terminal and the first voltage level;
configuring the first inductive device to output an adjusted voltage level according to an impedance of the match network;
providing a second voltage level at the first node, the second voltage level is greater than the first voltage level;
igniting the plasma at the second voltage level; and
adjusting the match network to achieve an impedance match between the RF signal and the inductive devices.

US Pat. No. 10,170,284

PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method comprising:preparing a plasma processing apparatus, the plasma processing apparatus comprising:
a chamber;
a lower electrode disposed in the chamber;
an upper electrode disposed in the chamber and facing the lower electrode;
a focus ring disposed in the chamber and surrounding a peripheral edge of the lower electrode; and
a plurality of annular coils disposed on an upper portion of the upper electrode and being concentric with a substrate to be placed on the lower electrode, one of the annular coils being disposed outside the peripheral edge of the lower electrode, the others of the annular coils being disposed inside the peripheral edge of the lower electrode;
placing the substrate on the lower electrode, with a peripheral edge of the substrate surrounded by the focus ring;
introducing process gas into the chamber;
applying high-frequency power across the upper electrode and the lower electrode to generate plasma of the process gas;
generating a magnetic field by supplying a current only to the one of the annular coils to level an interface of a plasma sheath on an upper portion of the substrate with the interface of the plasma sheath on an upper portion of the focus ring for reducing the occurrence of tilting in a pattern formed on the substrate by etching with the plasma, wherein a horizontal component of the magnetic field generated from the one of the annular coils has the highest value outside the peripheral edge of the substrate; and
varying the current to be supplied to the one of the annular coils according to a worn state of the focus ring.

US Pat. No. 10,170,283

FOCUS RING FOR PLASMA PROCESSING APPARATUS

COORSTEK KK, Tokyo (JP)

1. A focus ring made of silicon comprising:a plurality of arc-shaped members, each of the plurality of arc-shaped members including a flat plate portion having an arc shape, open-topped first depressions formed at both circumferential ends of the flat plate portion, a stepped portion formed with an open-topped second depression at an inner circumferential side of the flat plate portion, and convex fitting portions formed on bottom surfaces of the first depressions;
a plurality of connecting members connecting the plurality of arc-shaped members to form a ring shape without an adhesive, each of the plurality of connecting members including a plate-like main body having an arc shape to be accommodated within the first depressions of the adjacent arc-shaped members, a stepped portion formed with an open-topped depression at an inner circumferential side of the plate-like main body, and concave fitting portions formed in a lower surface of the plate-like main body and configured to engage with the respective convex fitting portions of the adjacent arc-shaped members,
wherein a thickness between an upper surface of the connecting member and a bottom surface of the concave fitting portion of the connecting member is greater than a thickness between an upper surface of the arc-shaped member and a bottom surface of the second depression of the arc-shaped member; and
wherein the plurality of arc-shaped members is disposed to be in contact with one another at opposing end portions of the arc-shaped members, thereby forming a ring shape, and the connecting members are accommodated in the first depressions of the adjacent arc-shaped members, and wherein the plurality of arc-shaped members is connected with the connecting members whereby the concave fitting portions of the connecting members are engaged with the convex fitting portions of the arc-shaped members,
wherein the concave fitting portions of the connecting members are not positioned above end surfaces of the opposing end portions of the adjacent arc-shaped members, and
wherein when the connecting member engages the arc-shaped members, a gap is formed between the convex fitting portion of the arc-shaped member and the concave fitting portion of the connecting member, the gap being equal to or greater than 50 ?m and equal to or less than 100 ?m.

US Pat. No. 10,170,282

INSULATED SEMICONDUCTOR FACEPLATE DESIGNS

Applied Materials, Inc., ...

1. A semiconductor processing chamber faceplate comprising:a conductive plate defining a plurality of apertures; and
a plurality of inserts, wherein each aperture of the plurality of apertures contains an insert of the plurality of inserts, wherein each insert of the plurality of inserts defines at least two channels there through, wherein each channel of the at least two channels independently extends vertically from a first end of an associated insert to a second end of the associated insert, wherein each channel of the at least two channels is radially offset from a central axis through the insert defining the at least two channels, and wherein the at least two channels are radially offset from one another about the central axis;
a plurality of first o-rings positioned within annular channels at least partially defined by the conductive plate within the plurality of aperture;
wherein a portion of each first o-ring of the plurality of first o-rings is seated within a first annular groove defined along a region of a corresponding insert between a top and bottom of the corresponding insert.

US Pat. No. 10,170,280

PLASMA REACTOR HAVING AN ARRAY OF PLURAL INDIVIDUALLY CONTROLLED GAS INJECTORS ARRANGED ALONG A CIRCULAR SIDE WALL

Applied Materials, Inc., ...

1. A plasma reactor comprising:a cylindrical vacuum chamber enclosure;
an RF plasma source power applicator and an RF source power generator coupled to said applicator;
plural passages extending in a radial direction through said vacuum chamber enclosure and being spaced apart along a circumference of said vacuum chamber enclosure;
a process gas supply;
a succession of detachable gas flow lines spaced from and outside of said vacuum chamber enclosure and arranged end-to-end around the circumference of said vacuum chamber enclosure, and a gas supply line coupled between said succession of detachable gas flow lines and said process gas supply;
plural external gas flow valves outside of said vacuum chamber enclosure and coupled between successive ones of said gas flow lines at respective locations spaced apart relative to said circumference of said vacuum chamber enclosure, each of said valves having: (a) a controlled gas output port individually coupled to a respective one of said plural passages, (b) a valve control input governing gas flow through said controlled gas output port, (c) an input flow-through port connected to a first one of a corresponding pair of said gas flow lines, (d) an output flow-through port connected to the other one of the corresponding pair of said gas flow lines, (e) a flow-through passage between said input and output flow-through ports, wherein each of said gas flow lines is separately disconnectable from the valve to which it is connected;
a workpiece support within said vacuum chamber enclosure having a support surface for supporting a workpiece; and
a gas valve configuration controller controlling the valve control input of each of said valves.

US Pat. No. 10,170,279

MULTIPLE COIL INDUCTIVELY COUPLED PLASMA SOURCE WITH OFFSET FREQUENCIES AND DOUBLE-WALLED SHIELDING

Applied Materials, Inc., ...

1. A plasma reactor comprisinga window assembly;
first and second coil antennas adjacent said window assembly;
a first current distributor coupled to said first coil antenna and a second current distributor coupled to said second coil antenna;
first and second RF feed terminals;
first and second RF power sources coupled to said first and second RF feed terminals respectively;
a conductive feed plate lying in a plane above said first and second coil antennas and coupled to said second RF feed terminal, and a plurality of axial rods coupled between a peripheral annular zone of said conductive feed plate and said second current distributor;
a conductive ground plate in a plane between said conductive feed plate and said first current distributor; and
a first radial conductive feed rod lying in a plane above said conductive ground plate and having an inner end coupled to said first current distributor and an outer end coupled to said first RF feed terminal.

US Pat. No. 10,170,278

INDUCTIVELY COUPLED PLASMA SOURCE

APPLIED MATERIALS, INC., ...

1. An inductively coupled plasma apparatus, comprising:a bottom wall comprising a hub having a plurality of radially outwardly directed spokes and a ring having a corresponding plurality of radially inwardly directed spokes, wherein each radially inwardly directed spoke lies along a common radius as a corresponding one of the plurality of radially outwardly directed spokes, wherein the hub and the ring are each electrically conductive, and wherein the hub has a central opening aligned with a central axis of the inductively coupled plasma apparatus;
a plurality of capacitors, one each disposed between and coupling respective ends of each radially outwardly directed spoke and corresponding radially inwardly directed spoke;
a top wall spaced apart from and above the bottom wall, wherein the top wall has a central opening aligned with the central axis, and wherein the top wall is electrically conductive;
a sidewall electrically connecting the ring to the top wall; and
a tube electrically connecting the hub to the top wall, the tube having a central opening aligned with the central axis.

US Pat. No. 10,170,277

APPARATUS AND METHODS FOR DRY ETCH WITH EDGE, SIDE AND BACK PROTECTION

Applied Materials, Inc., ...

1. An apparatus for processing a substrate, comprising:a chamber body having a chamber sidewall and a bottom defining a processing volume;
a supporting assembly disposed in the processing volume, wherein the supporting assembly comprises a raised portion for supporting the substrate during processing;
a plasma source configured to generating or supplying a plasma in the processing volume;
an edge protection plate movably disposed in the processing volume above and spaced apart from the supporting assembly, wherein the edge protection plate has a center opening formed in a central region and the center opening has substantially vertical walls, wherein the center opening has a size to shield only an edge of the substrate during processing, wherein the edge protection plate further includes a plurality of through holes formed therein, wherein the through holes are configured to allow a first plurality of supporting legs passing therethrough from the supporting assembly and the edge protection plate is spaced apart from the chamber sidewalls; and
an edge shield disposed against a periphery of the edge protection plate and spaced apart from the support assembly and the chamber sidewalls, the edge shield covering a vertical sidewall of the edge protection plate.

US Pat. No. 10,170,276

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

TAIWAN SEMICONDUCTOR MANU...

1. A method of semiconductor device fabrication, comprising:receiving an integrated circuit (IC) layout pattern including a plurality of templates;
identifying, from the plurality of templates, a first template having a first layout pattern with a first pattern density (PD) and a second template having a second layout pattern with a second PD less than the first PD;
splitting the first template into a plurality of subset templates, wherein each subset template of the plurality of subset templates includes a portion of the first layout pattern, and wherein each subset template has a subset PD that satisfies a PD target;
performing a PD uniformity (PDU) optimization to the second template; and
performing multiple individual electron beam (e-beam) lithography exposure processes with an e-beam lithography tool to a semiconductor substrate, using respective ones of the subset templates, thereby patterning the semiconductor substrate.

US Pat. No. 10,170,275

CRYOGENIC SPECIMEN PROCESSING IN A CHARGED PARTICLE MICROSCOPE

FEI Company, Hillsboro, ...

1. A method comprising:directing a charged-particle beam onto a portion of a specimen, situated in a vacuum chamber and maintained at a cryogenic temperature so as to perform a surface modification thereof;
providing a thin film monitor in the vacuum chamber and maintaining at least a detection surface thereof at a cryogenic temperature; and
using the thin film monitor to measure a precipitation rate of frozen condensate in the vacuum chamber,
wherein when either the precipitation rate falls below a first pre-defined threshold, the surface modification is initiated, or when the precipitation rate rises above a second pre-defined threshold, the surface modification is interrupted, or both.