US Pat. No. 10,171,140

MU-MIMO GROUP SELECTION

Hewlett Packard Enterpris...

1. A communications device, comprising:communications circuitry to wirelessly communicate with a number of client devices using multiple possible bandwidth settings; and
control circuitry to determine signal-to-interference-plus-noise ratios (SINRs) for the client devices based on compressed client-side channel state information received from the client devices, and to select a set of multi-user-multiple-input-multiple-output (MU-MIMO) groups and bandwidth settings respectively assigned thereto, by:
estimating, based on the SINRs, bandwidth-specific throughputs for potential MU-MIMO groups at a specified bandwidth setting from among the multiple-possible bandwidth settings, and
selecting the set of MU-MIMO groups together with their respectively assigned bandwidth settings based on the bandwidth-specific throughputs.

US Pat. No. 10,171,138

INDICATING OPTIONAL PARAMETER GROUPS

NOKIA TECHNOLOGIES OY, E...

1. A method, comprising:determining optional configurations for parameters that override or supplement a default configuration of the parameters, wherein the optional configurations are grouped into optional parameter groups;
determining a number of the optional parameter groups to be encoded so as to not exceed a container size of a physical broadcast channel;
encoding the optional parameter groups in a system information block; and
transmitting the system information block from a network node to a user equipment.

US Pat. No. 10,171,137

METHOD AND DEVICE FOR TRANSMITTING DATA BY USING SPATIAL MODULATION SCHEME IN WIRELESS ACCESS SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting data signals from a transmitter by using a spatial modulation (SM) scheme in a wireless access system, the method performed an enhanced Node-B (eNB) and comprising:selecting two or more transmitting antennas for transmitting the data signals by using two or more ranks;
deriving data bit streams by applying the SM scheme,
wherein the data bit streams correspond to the two or more ranks;
configuring the data signals by using the SM scheme on the basis of the data bit streams;
transmitting, to a user equipment (UE), an enhanced physical downlink control channel (E-PDCCH) and demodulation reference signals (DM-RSs) through one of the two or more transmitting antennas, the E-PDCCH including rank information indicating a number of rank used for transmitting the data signals; and
transmitting, to the UE, the configured data signals through the selected two or more transmitting antennas and DM-RSs matched with each of the selected two or more transmission antennas,
wherein each of the two or more transmission antennas uses different predetermined DM-RSs from each other,
wherein combinations of the rank information and the DM-RSs identify each of the two or more transmission antennas,
wherein, if the E-PDCCH is transmitted through a first transmission antenna of the two or more transmission antennas, this represents a positive acknowledgment (ACK) for uplink data transmitted from the UE, and
wherein, if the E-PDCCH is transmitted through a second transmission antenna of the two or more transmission antennas, this represents a negative acknowledgement (NACK) for the uplink data transmitted from the UE.

US Pat. No. 10,171,136

REDUCING INTERNAL SIGNALING BURDEN IN THE DISTRIBUTED ANTENNA SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for a user equipment (UE) to receive signals from a network, the method comprising:receiving a first information unit from the network by a first distributed unit (DU) among multiple DUs distributed within the UE;
reporting, by the first DU, reception information of the first information unit to a central unit (CU) of the UE before decoding the received first information unit, wherein the CU controls the multiple DUs;
receiving, at the first DU from the CU, a direction indicating whether the first DU is to decode the received first information unit or not, and indicating whether the first DU is to transfer the received first information unit to the CU or another DU within the UE,
wherein the CU sends the direction based on the reception information of the first received information unit; and
decoding and transferring, by the first DU, the received first information unit to the CU and the another DU within the UE when the direction indicates a specific value,
wherein the CU sends the direction with an indication that the first DU is to transfer the first information unit.

US Pat. No. 10,171,135

PRECODING METHOD, APPARATUS, AND SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A precoding method for a level 1 data center comprising:obtaining, by the level 1 data, center, a channel information signal between a terminal and the level 1 data center, wherein the channel information signal comprises a channel matrix;
encoding, by the level 1 data center, the channel matrix according to a precoding matrix to obtain an equivalent channel;
sending, by the level 1 data center, the equivalent channel to a level 2 data center for further processing when a frequency selectivity of the equivalent channel is less than or equal to a frequency selectivity of the channel; and
sending, by the level 1 data center, the channel matrix and the precoding matrix to the level 2 data center for further processing when the frequency selectivity of the equivalent channel is greater than the frequency selectivity of the channel.

US Pat. No. 10,171,134

ELECTRIC DEVICE AND OPERATION METHOD

Canon Kabushiki Kaisha, ...

1. An electric device for performing short distance wireless communication with a mobile terminal, comprising:an antenna configured to generate induced power by an RF signal from the mobile terminal;
a resistor configured to drop a peak voltage generated by the induced power;
a circuit driven by the voltage dropped by the resistor and configured to perform the short distance wireless communication; and
a light emission element driven by the voltage dropped by the resistor and configured to emit light, wherein
the resistor is series-connected between the circuit and the antenna.

US Pat. No. 10,171,132

CURRENT-MODE RECEIVERS FOR INDUCTION-BASED COMMUNICATION AND RELATED METHODS

MEDIATEK Singapore Pte. L...

1. A method comprising:generating a current with a transmitter of an integrated circuit (IC) and coupling the current to an inductor via an input/output (I/O) terminal of the IC; and
sensing information received at the IC through the inductor by sensing a variation in impedance seen at the I/O terminal, wherein sensing the variation in impedance comprises:
sensing the current coupled to the inductor;
converting the sensed current into a voltage; and
sensing a variation in the voltage with a receiver.

US Pat. No. 10,171,131

ELECTRONIC TUNING SYSTEM

William Redman-White, Al...

1. A circuit configured to control a resonant frequency of a tuned circuit so as to correspond with an applied excitation frequency over a continuous range of excitation frequencies, the tuned circuit comprising: an inductor; at least two capacitors; and at least one switch connected in combination with one of the at least two capacitors, wherein an apparent resonant frequency can be varied by controlling the duty cycle of an opening and closing of the at least one switch; and a source providing an excitation signal to the tuned circuit, the circuit configured to control the resonant frequency comprising:a voltage sensor configured to sense a voltage across two terminals of the at least one switch when the at least one switch is in an open state;
tuning control circuitry configured to derive a tuning control input signal from the sensed voltage; and
switch timing circuitry configured to control the timing of the opening and closing of the at least one switch in a manner based on the derived tuning control input signal, wherein the opening and closing instants of the said at least one switch are synchronous with the applied excitation signal and wherein the opening and closing instants of the said at least one switch are substantially equally spaced in time around a peak of a voltage at the connection between the inductor and the capacitors when the circuit is at resonance.

US Pat. No. 10,171,130

RECEIVER CIRCUIT

Power Integrations, Inc.,...

1. An analog receiver frontend, comprising:a first amplification circuit coupled to receive an input signal, wherein the first amplification stage is coupled to amplify a difference between the input signal and a threshold to generate the first signal;
a second amplification circuit coupled to receive the first signal from the first amplification circuit, wherein the second amplification circuit is coupled to amplify the first signal to generate a second signal;
an output circuit coupled to receive the second signal from the second amplification circuit, wherein the output circuit is coupled to output a recovered signal wherein the recovered signal is a pulse waveform of high and low sections; and
an input hysteresis circuit coupled to the output circuit to receive the recovered signal and generate a hysteresis signal, wherein one or both of the input signal and the threshold are level shifted by the hysteresis signal in response to the recovered signal.

US Pat. No. 10,171,129

PULSE SHAPING INTEROPERABILITY PROTOCOL FOR ULTRA WIDEBAND SYSTEMS

Apple Inc., Cupertino, C...

1. An electronic device comprising:a memory; and
one or more processors communicatively coupled to the memory and configured to:
receive pulse shape information from an other electronic device, wherein the pulse shape information is used in Ultra Wideband (UWB) communications between the electronic device and the other electronic device, and wherein the pulse shape information comprises a time-zero index that identifies a time instant reference to be used to process the UWB communications;
receive a ranging signal based at least in part on the pulse shape information; and
determine an estimated distance between the electronic device and the other electronic device based at least in part on the time-zero index and the ranging signal.

US Pat. No. 10,171,128

DATA TRANSMISSION METHOD AND APPARATUS

1. A data transmission method, comprising the following steps:determining a transmission resource to be used and a complex-valued spreading sequence to be used;
processing a data symbol to be sent by using the complex-valued spreading sequence to generate a symbol sequence; and
sending the symbol sequence through the transmission resource,
wherein each element of the complex-valued spreading sequence is a complex number, and values of a real part and an imaginary part of each element are both from an M-element real number set, wherein the M is an integer greater than or equal to 2, and the M-element real number set is selected from:
a set formed by M integers within a range of [?(M?1)/2, (M?1)/2], wherein the M is an odd number;
a set formed by M odd numbers within a range of [?(M?1), (M?1)], wherein the M is an even number;
a set formed by M real numbers obtained through multiplying respectively M integers within a range of [?(M?1)/2, (M?1)/2] by specified coefficient(s), wherein the M is an odd number; and
a set formed by M real numbers obtained through multiplying respectively M odd numbers within a range of [?(M?1), (M?1)] by specified coefficient(s), wherein the M is an even number.

US Pat. No. 10,171,127

METHOD, SYSTEM AND COMPUTER PROGRAM FOR SYNCHRONIZING PSEUDORANDOM BINARY SEQUENCE MODULES

1. A method for synchronizing a first pseudorandom binary sequence module of a receiver and a second pseudorandom binary sequence module of a transmitter, the method comprising:initializing the first pseudorandom binary sequence module with a first received bit sequence and performing bit sequence generation with the aid of the second pseudorandom binary sequence module;
comparing received remaining bits to bit sequences generated with the aid of the first pseudorandom binary sequence module to determine whether a bit error rate is below a predefined threshold;
accounting for phase ambiguities to check whether the bit error rate of each of a number of candidate phase positions for an initial phase is below the predefined threshold; and
in a case where there is no phase information available, testing each of a plurality of possible phase positions for the respective number of candidate phase positions.

US Pat. No. 10,171,126

APPARATUS FOR UPLINK MULTI-ANTENNA COMMUNICATION BASED ON A HYBRID COUPLER AND A TUNABLE PHASE SHIFTER

Intel IP Corporation, Sa...

1. Front end module (FEM) circuitry, comprising:a hybrid coupler to generate a first antenna transmit signal and a second antenna transmit signal based on hybrid coupler input signals; and
one or more tunable phase shifters to generate the hybrid coupler input signals based at least partly on an FEM input signal,
wherein the first antenna transmit signal is based on a first signal summation that comprises summation of a first hybrid coupler input signal and a second hybrid coupler input signal phase-shifted, by the hybrid coupler, according to a predetermined hybrid coupler phase shift, and
wherein the second antenna transmit signal is based on a second signal summation that comprises summation of the second hybrid coupler input signal and the first hybrid coupler input signal phase-shifted, by the hybrid coupler, according to the predetermined hybrid coupler phase shift.

US Pat. No. 10,171,125

TUNABLE ANTENNA SYSTEMS

Apple Inc., Cupertino, C...

1. An electronic device having a periphery, comprising:radio-frequency transceiver circuitry;
an antenna having an antenna feed and ground plane structures;
a transmission line path coupled between the radio-frequency transceiver circuitry and the antenna feed;
peripheral conductive housing structures that run along the periphery and surround the ground plane structures, wherein the peripheral conductive housing structures include a portion that forms at least part of the antenna;
storage and processing circuitry configured to generate a control signal; and
an adjustable electrical component coupled to the peripheral conductive housing structures, wherein the adjustable electrical component has a control input that receives the control signal and the adjustable electrical component is configured to adjust a frequency response of the antenna based on the control signal.

US Pat. No. 10,171,124

LOW NOISE AMPLIFIER ARBITER FOR LICENSE ASSISTED ACCESS SYSTEMS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a network interface configured to allow the electronic device to communicate over one or more channels of a wireless network;
a transceiver operably coupled to the network interface and configured to transmit data and to receive data over the one or more channels; and
a front end module (FEM) operably coupled to the transceiver and configured to receive licensed cellular signals and unlicensed cellular signals over the one or more channels, the FEM having an arbiter device configured to receive information related to the licensed cellular signals and the unlicensed cellular signals and to control at least one variable-gain amplifier and at least one gain adjustment device to independently amplify the licensed cellular signals and the unlicensed cellular signals.

US Pat. No. 10,171,123

TRIPLE-GATE PHEMT FOR MULTI-MODE MULTI-BAND SWITCH APPLICATIONS

SKYWORKS SOLUTIONS, INC.,...

1. A switch element comprising:a source including a plurality of source fingers and a drain including a plurality of drain fingers interleaved with the source fingers;
an active mesa region defined between at least one of the plurality of source fingers and an adjacent at least one of the plurality of drain fingers; and
a plurality of gates disposed between the at least one of the plurality of source fingers and the adjacent at least one of the plurality of drain fingers, at least one of the plurality of gates including a finger extending into the active mesa region from outside of the active mesa region and terminating within the active mesa region, the plurality of gates including a first gate, a second gate, and a third gate, a non-zero voltage difference across the source and the drain being evenly divided between the first gate, the second gate, and the third gate.

US Pat. No. 10,171,121

RUGGEDIZED PROTECTIVE CASE WITH INTEGRATED EASEL KICKSTAND FOR MOBILE DEVICE

MobileDemand LC, Hiawath...

1. A ruggedized protective case for a mobile computing device, comprising:an inner housing configured to partially enclose a mobile computing device, the inner housing fashioned of a rigid material;
an outer housing configured to partially enclose the inner housing, the outer housing fashioned of a flexible material and including one or more reinforced corners, each reinforced corner configured to provide impact protection to a corner of the mobile computing device;
a kickstand consisting of a rigid core entirely overmolded with the flexible material, the kickstand having an inner end hingedly coupled to the inner housing and an outer end coupled to the kickstand at a first angle and configured to hold the mobile computing device at a second angle to a flat surface, the kickstand positionable at a third angle of at most 170 degrees to the inner housing.

US Pat. No. 10,171,120

APPARATUS AND METHOD FOR SUPPRESSING INTERMODULATION DISTORTION COMPONENT IN RECEPTION SIGNAL, AND COMMUNICATION APPARATUS

FUJITSU LIMITED, Kawasak...

1. An apparatus for suppressing an intermodulation distortion component in a reception signal, the apparatus comprising:a memory; and
processor circuitry coupled to the memory and configured to
execute acquisition to acquire a plurality of transmission signals transmitted at frequencies different from each other,
execute reception to receive a reception signal including an intermodulation distortion component caused by the plurality of transmission signals,
execute generation to generate a replica of the intermodulation distortion component according to the plurality of transmission signals,
execute normalization to normalize the reception signal so that the reception signal has certain amplitude,
execute calculation to calculate a correlation value between the normalized reception signal and the replica,
execute adjustment to adjust delay in the replica relative to the reception signal according to the correlation value, and
execute combination to combine the replica for which the delay is adjusted with the reception signal.

US Pat. No. 10,171,118

METHOD FOR TRANSMITTING REFERENCE SIGNAL IN CELL THAT USES UNLICENSED FREQUENCY BAND AND DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A method for transmitting a reference signal in a cell that uses an unlicensed frequency band, comprising:determining a candidate resource set that is used when a first reference signal is transmitted in the cell that uses the unlicensed frequency band, wherein the candidate resource set comprises a preset resource and at least one flexible candidate resource, wherein the preset resource is a resource that is in a time window and that is required, when the cell is in an active state, for transmission of the first reference signal according to a first period, and wherein the flexible candidate resource is a candidate resource that is in the time window and that is obtained after the preset resource is translated in terms of time, wherein a period in which the time window emerges is a second period, and the second period is greater than the first period;
determining a first candidate resource that is used when the first reference signal is transmitted in the cell that uses the unlicensed frequency band, wherein a channel on the unlicensed frequency band corresponding to the first candidate resource is in an idle state, and wherein the first candidate resource is one of the preset resource or a flexible candidate resource in the candidate resource set; and
sending the first reference signal on the first candidate resource.

US Pat. No. 10,171,117

METHODS AND APPARATUS TO MEASURE EXPOSURE TO BROADCAST SIGNALS HAVING EMBEDDED DATA

The Nielsen Company (US),...

1. A broadcast signal exposure meter comprising:a first decoder to obtain an identifier of a broadcast station from an audio signal output by an end user broadcast receiver;
a radio to tune to a broadcast signal from the broadcast station associated with the identifier of the broadcast station;
a second decoder to obtain embedded data from the broadcast signal, the embedded data representing media contained in the broadcast signal;
a location detector to determine location information; and
an interface to provide the embedded data and the location information to a server, the server to determine audience measurement information for the media based on the provided embedded data.

US Pat. No. 10,171,116

DATA TRANSMISSION METHOD AND DEVICE

SOOCHOW UNIVERSITY, Suzh...

1. A data transmission method, comprising:establishing, by a transmitting end, N different first paths between the transmitting end and a receiving end in an established network, wherein N is an integer greater than 1;
splitting, by the transmitting end, a fixed-length data frame into N first fragments, wherein each of the first fragments corresponds to a different one of the first paths, and a length of an i-th first fragment is L*P(i)/?i=1NP(i), wherein L is the length of the data frame, P(i) is a random number generated from a pre-set key by a pre-set algorithm, P(i) is greater than 0 and less than 1, and ?i=1NP(i)=1;
transmitting, by the transmitting end, the first fragments to the receiving end through the corresponding first paths respectively, wherein the receiving end combines the first fragments based on the pre-set algorithm;
splitting, by the transmitting end, the data frame into N-M second fragments in a case that a failure occurs in M of the first paths during transmission of the data frame, wherein M is an integer not less than 1 and not greater than N?1, a length of an i-th second segment is L*P?(i)/?i=1N-MP?(i), P?(i) is a random number generated from the pre-set key by the pre-set algorithm, P?(i) is greater than 0 and less than 1, and ?i=1N-MP?(i)=1;
establishing, by the transmitting end, N-M different second paths between the transmitting end and the receiving end, wherein each of the second fragments corresponds to a different one of the second paths; and
transmitting, by the transmitting end, the second fragments to the receiving end through the corresponding second paths respectively, wherein the receiving end combines the second fragments based on the pre-set algorithm.

US Pat. No. 10,171,114

RADIO FREQUENCY SWITCH APPARATUS HAVING IMPROVED NOISE SUPPRESSION CHARACTERISTICS

Samsung Electro-Mechanics...

1. A radio frequency switch apparatus, comprising:a first switching circuit connected between an antenna terminal and a first signal terminal, comprising a first series switching circuit and a first shunt switching circuit configured to switch a first signal band on and off;
a second switching circuit connected between the antenna terminal and a second signal terminal, configured to switch a second signal band, different from the first signal band, on and off; and
an inductor circuit comprising a first inductor device connected between the first shunt switching circuit and a ground,
wherein the first inductor device suppresses noise, except for the first signal band and the second signal band, by being resonant with a capacitance present upon the first shunt switching circuit being turned off.

US Pat. No. 10,171,113

MULTIPLEXER, TRANSMISSION DEVICE, AND RECEPTION DEVICE

MURATA MANUFACTURING CO.,...

1. A multiplexer that transmits and receives high-frequency signals via an antenna element, the multiplexer comprising:a plurality of elastic wave filters with passbands different from each other;
a common terminal, with which at least one first circuit element is connected between a connection path of the common terminal and the antenna element, and a reference terminal, and at least one second circuit element is connected in series to the connection path; and
a first inductance element; wherein
one elastic wave filter of the plurality of elastic wave filters includes:
a series resonator connected between an input terminal and an output terminal; and
a parallel resonator connected between a connection path connecting the input terminal and the output terminal, and a reference terminal;
each of the plurality of elastic wave filters other than the one elastic wave filter includes a series resonator connected between an input terminal and an output terminal;
in the one elastic wave filter of the plurality of elastic wave filters, one of the input terminal and the output terminal of the one elastic wave filter, which is a terminal closer to the antenna element, is connected to the common terminal via the first inductance element that is connected to the terminal closer to the antenna element and the common terminal, and the terminal closer to the antenna element is connected to the parallel resonator; and
in each of the plurality of elastic wave filters other than the one elastic wave filter, one of the input terminal and the output terminal of the elastic wave filter, which is a terminal closer of to the antenna element, is connected to the common terminal, and is connected to the series resonator.

US Pat. No. 10,171,112

RF MULTIPLEXER WITH INTEGRATED DIRECTIONAL COUPLERS

QUALCOMM Incorporated, S...

1. A circuit comprising:an RF diplexer including a first channel and a second channel, wherein the first channel includes a first primary inductor and the second channel includes a second primary inductor;
a first directional coupler for the first channel including a first transformer that includes the first primary inductor and a first secondary inductor, wherein a first terminal for the first secondary inductor is a coupled port for the first directional coupler and a second terminal for the first secondary inductor is an isolated port for the first directional coupler;
a second directional coupler for the second channel including a second transformer that includes the second primary inductor and a second secondary inductor, wherein a first terminal for the second secondary inductor is a coupled port for the second directional coupler and a second terminal for the second secondary inductor is an isolated port for the second directional coupler;
an input port for the first channel coupled to a first terminal for the first primary inductor;
a first capacitor coupled between a second terminal for the first primary inductor and the second terminal for the first secondary inductor;
a second capacitor coupled between the input port for the first channel and ground;
a third capacitor coupled in parallel with the first primary inductor;
a first antenna;
a first inductor coupled between the second terminal of the first secondary inductor and the first antenna; and
a fourth capacitor coupled between the second terminal of the first secondary inductor and ground.

US Pat. No. 10,171,111

GENERATING ADDITIONAL SLICES BASED ON DATA ACCESS FREQUENCY

INTERNATIONAL BUSINESS MA...

1. A method for execution by a computing device of a dispersed storage network (DSN), the method comprises:determining whether a frequency of access via the DSN from one or more other computing devices to a set of encoded data slices that is stored in a set of storage units of the DSN exceeds a frequently accessed threshold, wherein a data segment of a data object is dispersed storage error encoded in accordance with first dispersed error encoding parameters including a first encoding matrix to produce the set of encoded data slices that is stored in the set of storage units of the DSN, wherein the set of encoded data slices includes a pillar width number and a decode threshold number, wherein the pillar width number corresponds to number of encoded data slices in the set of encoded data slices, and wherein the decode threshold number corresponds to a number of encoded data slices of the set of encoded data slices to retrieve a corresponding data segment of the data object;
when the frequency of access via the DSN from the one or more other computing devices to the set of encoded data slices that is stored in the set of storage units of the DSN exceeds the frequently accessed threshold, determining an access amount indicative of a degree in which the frequency of access exceeds the frequently accessed threshold;
generating a number of additional encoded data slices for the set of encoded data slices based on the access amount in accordance with second dispersed error encoding parameters including a second encoding matrix that includes at least one of more rows or more columns than the first encoding matrix;
storing the number of additional encoded data slices in a number of additional storage units within the DSN, wherein the set of storage units and the number of additional storage units produce an expanded set of storage units within the DSN that includes more storage units than the set of storage units; and
sending, via the DSN from at least one of the computing device or the one or more other computing devices, a plurality of data access requests for the set of encoded data slices to different respective subsets of the expanded set of storage units in a distributed manner to load balance the plurality of data access requests for the set of encoded data slices among the expanded set of storage units within the DSN, wherein, over time, each storage unit of the expanded set of storage units within the DSN receives approximately an equal number of the plurality of data access requests and less than all of the plurality of data access requests.

US Pat. No. 10,171,110

SEQUENTIAL POWER TRANSITIONING OF MULTIPLE DATA DECODERS

Seagate Technology LLC, ...

1. An apparatus comprising:a non-volatile memory (NVM) configured to store data in the form of code words, each code word comprising a user data payload and associated code bits;
a plurality of data decoder circuits each configured to use the code bits to detect and correct bit errors in the code words during a read operation; and
a power transition circuit configured to transition each of the data decoder circuits from a first power mode to a different, second power mode in accordance with a time varying profile in which each data decoder circuit is transitioned at a different time and at a conclusion of a predetermined time interval.

US Pat. No. 10,171,109

FAST ENCODING METHOD AND DEVICE FOR REED-SOLOMON CODES WITH A SMALL NUMBER OF REDUNDANCIES

Hefei High-Dimensional Da...

1. A fast encoding method for Reed-Solomon codes with a small number of redundancies, the method comprising:a step of setting parity-check matrices comprising:
presetting parity-check matrices H2 and H3; wherein the number of redundant symbols s in the Reed-Solomon codes is 2 or 3, and when s is 3, the preset parity-check matrix is:

when s is 2, the preset parity-check matrix is:

a step of constructing shortened Reed-Solomon codes comprising:
constructing (k, s) Reed-Solomon codes over a finite field GF(2m) that conform to the preset parity-check matrix; using k points {oi}i=1k in R-points input {oi}i=0R?1 as message symbols, and setting the remaining points to zero; setting the remaining points of the R points to zero, that is, o0=0 and ok+1=. . . =oR?1=0;
wherein m denotes the number of binary bits for each symbol, R=2r, r=? log2(k+1)?, k denotes the number of message symbols, s denotes the number of redundant symbols, i=0,1 , . . . , R?1, and oi denotes the message symbol;
a step of encoding comprising:
calculating s redundant symbols according to the R-points input and the base vector of the finite field, to achieve the encoding of Reed-Solomon codes with a small number of redundancies.

US Pat. No. 10,171,108

PARALLEL CRC CALCULATION FOR MULTIPLE PACKETS WITHOUT REQUIRING A SHIFTER

ALTERA CORPORATION, San ...

1. A programmable integrated circuit device for parallel calculation of cyclic redundancy check (“CRC”) values for a plurality of packets received in a clock cycle, the programmable integrated circuit device comprising:a padding bit-replacement block configured to:
receive a stream comprising the plurality of packets, wherein the plurality of packets have N packets;
generate N copies of the stream, wherein each copy of the stream is associated with a respective packet of the plurality of packets; and
for each respective copy of the N copies of the stream, replace with padding bits all packets but the respective packet associated with the respective copy to create a respective padded copy of a plurality of padded copies;
a CRC calculation block configured to:
receive the plurality of padded copies; and
calculate a packet CRC value for each packet of the plurality of packets to form a plurality of packet CRC values by calculating a respective CRC value for each respective padded copy of the plurality of padded copies; and
a matrix reverse block configured to iteratively merge each padded copy of the plurality of padded copies by removing the padding bits from each padded copy of the plurality of padded copies to produce a reformed stream.

US Pat. No. 10,171,107

GROUPS OF PHASE INVARIANT CODEWORDS

Hewlett-Packard Developme...

1. A system comprising:a lookup table (LUT) to store in a non-transitory computer readable medium (CRM) associations between phase invariant codewords and bit strings in which each phase invariant codeword belongs to a group of codewords having a particular property, wherein the particular property is a range of values defining a number of active bits in the phase invariant codeword, each bit string having a first length; and
an encoder which upon execution instructs at least one processor coupled to the CRM to:
read a message comprising a bit string of a second length longer than the first length;
divide the message into a plurality of substrings from the LUT such that each substring is of the first length; and
encode in a halftone image, on a data bearing medium, a composite codeword comprising each phase invariant codeword associated in the LUT with a substring from the message;
wherein less storage in the CRM is needed for messages of a given bit size than encoding schemes implemented in the CRM with a simple table including all non-composite phase invariant codewords packed in order.

US Pat. No. 10,171,106

SYSTEMS AND METHODS FOR MULTI-STAGE DATA SERIALIZATION IN A MEMORY SYSTEM

Micron Technology, Inc., ...

1. A memory system, comprising:a memory device configured to provide a set of data in parallel;
a memory controller configured to coordinate data transmission of a memory device;
multi-stage serializer circuitry configured to receive the set of data in parallel and provide, to the memory controller, the data serially as a serialized data burst;
wherein the multi-stage serializer circuit comprises a set of two or more double data rate (DDR) shift registers; and
wherein each of the two or more DDR shift registers comprises at least two single data rate (SDR) shift registers, wherein each of the at least two SDR shift registers comprises a series of data flip flops configured to load an error data control (EDC) hold pattern in parallel.

US Pat. No. 10,171,105

CARRY-LESS POPULATION COUNT

INTERNATIONAL BUSINESS MA...

1. A population count circuit that determines a population count of an n-bit input bit-string, wherein:the population count circuit is configured to output the population count, wherein the population count is a number of 1s in the n-bit input bit-string; and
the population count circuit comprises:
a carryless counter circuit configured to determine a pair of 3-bit counts of 1 s, one for each 4-bit nibble from a pair of 4-bit nibbles from an n-bit input bit-string input to the population count circuit; and
an adder circuit configured to determine the population count by summing the pair of 3-bit counts of 1s from the carryless counter circuit corresponding to each 4-bit nibble, the adder circuit comprising a plurality of adders that perform the summing without propagating a carry bit that results from a most significant bit (MSB) of a sum of the pair of 3-bit counts of 1s being added, the plurality of adders setup as a sequential tree to propagate the 3-bit counts, where the tree comprises log2(n/4) levels, and wherein:
at level k of the tree, k being 2 to log 2(n/4), the 3-bit counts from a level k?1 of the tree in consecutive pairs are used by a first adder to determine the MSB of the sum based on the MSBs of the 3-bit counts only, without depending on carry propagation;
at level k of the tree, results from the level k?1 of the tree are added by a second adder for sum bits other than the MSB; and
result of additions at level log 2(n/4) of the tree is output as the population count of the n-bit input bit-string.

US Pat. No. 10,171,104

ENCODING VARIABLE LENGTH INTEGERS FOR GRAPH COMPRESSION

INTERNATIONAL BUSINESS MA...

1. A graph compression system comprising:a memory unit configured to store graph data; and
an electronic hardware controller in signal communication with the memory unit, the electronic hardware controller configured to determine a distribution of a set of vertices in a graph, and to encode each vertex included in the set of vertices as a variable length integer (VLI) that includes a variable number of bytes,
wherein the variable number of bytes of each vertex is based on the determined distribution, and
wherein the memory unit stores each encoded vertex.

US Pat. No. 10,171,103

HARDWARE DATA COMPRESSION ARCHITECTURE INCLUDING SHIFT REGISTER AND METHOD THEREOF

Mellanox Technologies, Lt...

1. A hardware compression architecture, comprising:a shift register including a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage;
a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match;
logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and
an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.

US Pat. No. 10,171,101

MODULATORS

Cirrus Logic, Inc., Aust...

1. An analogue to digital converter comprising:a time-encoding modulator comprising:
a first controlled oscillator configured to receive a first oscillator driving signal and output a first oscillation signal;
an accumulator configured to provide an accumulator value based on a number of pulses of the first oscillation signal; and
a hysteretic comparator configured to output either a first output state or a second output state and to alternate between said first and second output states based on a hysteretic comparison of said accumulator value with a defined reference;
wherein the first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator; and
at least one further controlled oscillator and a counter, wherein the at least one further controlled oscillator is driven by the output state of the hysteretic comparator and the counter is configured to generate a count value based on the number of pulses in an output of the at least one further controlled oscillator in a frame period defined a received clock signal.

US Pat. No. 10,171,099

TIME-BASED DELAY LINE ANALOG TO DIGITAL CONVERTER

MICROCHIP TECHNOLOGY INCO...

1. A differential digital delay line analog-to-digital converter (ADC), comprising:a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a second circuit comprising another set of delay elements included in the differential digital delay lines; wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to calibrate a source to the differential digital delay lines based on an out of input range determination.

US Pat. No. 10,171,098

ANALOG-TO-DIGITAL CONVERTER (ADC) WITH IMPROVED POWER DISTURBANCE REDUCTION

SK Hynix Inc., Gyeonggi-...

1. An analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising:a first node of the input analog voltage;
nodes of a plurality of reference voltages;
a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage among the plurality of reference voltages;
a logic circuit block adapted to receive outputs of the plurality of comparators and generating the output digital code; and
a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages,
wherein the voltage stabilizer is configured to reduce a phase difference between a first disturb on the input analog voltage of the first node and a second disturb on the node of the first reference voltage.

US Pat. No. 10,171,097

CORRECTING DEVICE OF SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

REALTEK SEMICONDUCTOR COR...

1. A correcting device of successive approximation analog-to-digital conversion, comprising:a successive approximation register analog-to-digital converter (SAR ADC) configured to generate a digital output; and
a digital circuit configured to determine whether the digital output conforms to a metastable output, and configured to correct the digital output according to predetermined correction when the digital output conforms to the metastable output,
wherein the metastable output is related with a metastable binary comparison-results sequence including successive K comparison results, the successive K comparison results include a first comparison result, a second comparison result and M comparison results in turn, the first comparison result and the second comparison result are identical, the M comparison results are identical, each of the first comparison result and the second comparison result is different from any of the M comparison results, and each of the K and the M is a positive integer.

US Pat. No. 10,171,096

PIPELINED SAR WITH TDC CONVERTER

Taiwan Semiconductor Manu...

12. An analog-to-digital converter (ADC), comprising:a voltage-based signal processing element configured to receive an input signal and to generate a first digital signal and a residue voltage;
a residue offset circuit configured to provide a residue offset voltage to the residue voltage;
a voltage-to-time conversion element configured to use the residue voltage and the residue offset voltage to generate a time domain representation of the residue voltage; and
a time-based signal processing element configured to convert the time domain representation to a second digital signal.

US Pat. No. 10,171,095

ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, MOVING OBJECT, AND MANUFACTURING METHOD OF ATOMIC OSCILLATOR

Seiko Epson Corporation, ...

1. An atomic oscillator comprising:a cell which encapsulates metal atoms therein;
a light source which generates light for irradiation of the cell; and
a frequency modulation signal generator configured to generate a frequency modulation signal for causing the light source to generate the light, the light being frequency-modulated and including a resonance light pair, the resonance light pair causing an electromagnetically induced transparency phenomenon in the metal atoms,
wherein modulation indexes of the frequency modulation signal include a first modulation index, and
a first-order differential value of oscillation frequency deviation of the atomic oscillator is zero at the first modulation index.

US Pat. No. 10,171,094

HIGH ACCURACY CLOCK SYNCHRONIZATION CIRCUIT

SEIKO EPSON CORPORATION, ...

1. A circuit device comprising:a comparator that performs a comparison between an input signal based on an oscillation signal and a reference signal, the comparator including a counter that performs a count operation by using the input signal, and performs the comparison by comparing a count value in the counter in n (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers;
a processor that performs a signal process on frequency control data based on a result of the comparison; and
an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data having undergone the signal process.

US Pat. No. 10,171,093

SLEW RATE LOCKED LOOP

2. A slew rate locked loop circuit for controlling and maintaining a constant slew rate at an output of a buffer, wherein said buffer receives (i) a first input signal and (ii) at least one of a control voltage, said slew rate locked loop circuit comprising:a slew rate determining unit that comprises:
a first reference voltage generator that generates (i) an upper threshold voltage (Vh) and (ii) a lower threshold voltage (Vl);
a first comparator that compares said upper threshold voltage (Vh) with said output of said buffer to obtain a first output digital signal;
a second comparator, that compares said lower threshold voltage (Vl) with said output of said buffer to obtain a second output digital signal; and
a phase detector that determines a phase difference between said first output digital signal and said second output digital signal, wherein said phase difference is directly proportional to said slew rate at said output of said buffer;
a loop filter that produces a DC voltage from an output of said phase detector;
a second reference voltage generator that generates a reference voltage; and
an amplifier that (a) receives said DC voltage from said loop filter and said reference voltage generated by said second reference voltage generator, and (b) amplifies the difference between (i) said DC voltage from said loop filter and (ii) said reference voltage to obtain a control voltage, wherein said control voltage is fed back to said buffer, wherein said slew rate at said output of said buffer is determined using said control voltage.

US Pat. No. 10,171,091

PHASE INTERPOLATOR FOR INTERPOLATING PHASE OF DELAY CLOCK SIGNAL AND DEVICE INCLUDING THE SAME AND FOR PERFORMING DATA SAMPLING BY USING PHASE INTERPOLATED CLOCK SIGNAL

SAMSUNG ELECTRONICS CO., ...

1. A phase interpolator comprising:a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval;
a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and
a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.

US Pat. No. 10,171,090

OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

SEIKO EPSON CORPORATION, ...

1. An oscillator comprising:a vibrator element;
a container in which the vibrator element is housed;
a base substrate on which the container is mounted via one or more supporting bodies;
at least one of a heating element and a cooling body configured to control temperature on an inside of the container;
an oscillation circuit electrically connected to the vibrator element;
a D/A conversion circuit configured to control a frequency output by the oscillation circuit;
a first reference-voltage generation circuit configured to supply voltage to the D/A conversion circuit; and
a second reference-voltage generation circuit configured to generate, on the basis of a power supply voltage supplied from outside of the oscillator, a power supply voltage of the oscillation circuit, wherein
temperature of the first reference-voltage generation circuit is controlled by the at least one of the heating element and the cooling body, and
the container is elevated and separated from the base substrate by being supported by the one or more supporting bodies.

US Pat. No. 10,171,089

PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

Taiwan Semiconductor Manu...

1. A circuit, comprising:a time-to-digital converter (TDC) configured to generate a phase variation signal indicative of a phase difference between a first signal and a reference signal; and
a doubler electrically coupled to the TDC, wherein the doubler is configured to receive a first voltage signal and generate a second voltage signal, wherein the second voltage signal is provided to a voltage input of the TDC, and wherein the TDC generates one or more control signals configured to adjust the second voltage signal, wherein the doubler comprises:
a first ring oscillator;
a first flip-flop electrically coupled to the first ring oscillator; and
a first clock generator electrically coupled to an output of the first flip-flop.

US Pat. No. 10,171,088

QUANTUM CIRCUIT FOR SHIFTING PHASE OF TARGET QUBIT BASED ON CONTROL QUBIT

ELECTRONICS AND TELECOMMU...

1. A quantum circuit that shifts a phase of a target qubit by ?/2n?1 based on a control qubit, the quantum circuit comprising:a first auxiliary circuit configured to convert a first qubit state according to an entanglement of the control qubit, the target qubit, and an ancillary qubit having a |0> state to a second qubit state;
a rotation gate configured to shift a phase for at least one basis state of the second qubit state by ?/2n?1 to convert the second qubit state to a third qubit state; and
a second auxiliary circuit configured to convert the third qubit state to a fourth qubit state so as to shift the phase of the target qubit by ?/2n?1,
wherein the first auxiliary circuit determines a |111> basis state of the second qubit state based on a |110> basis state of the first qubit state, and the second auxiliary circuit determines a |110> basis state of the fourth qubit state based on a |111> basis state of the third qubit state.

US Pat. No. 10,171,087

LARGE FAN-IN RQL GATES

Northrop Grumman Systems ...

1. A reciprocal quantum logic (RQL) gate circuit comprising:an input stage having more than two logical inputs each configured to be asserted based on receiving a positive single flux quantum (SFQ) pulse, the input stage comprising, for each logical input, at least one storage loop associated with the logical input, each storage loop comprising at least one input Josephson junction (JJ), at least one inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs; and
an output stage configured to assert an output based on a triggering of the logical decision JJ in response to a combination of logical inputs.

US Pat. No. 10,171,086

SUPERCONDUCTING THREE-TERMINAL DEVICE AND LOGIC GATES

Massachusetts Institute o...

1. A three-terminal device comprising:a main channel connecting a first terminal and a second terminal;
a gate channel connecting a control terminal to the main channel; and
a low-resistance constriction formed in the gate channel between the control terminal and the main channel, wherein the constriction is configured to increase a gate current density proximal to the main channel and the constriction is located within approximately 200 nm of an edge of the main channel.

US Pat. No. 10,171,085

NOISE-IMMUNE REFERENCE (NREF) INTEGRATED IN A PROGRAMMABLE LOGIC DEVICE

AnDAPT, Inc., San Jose, ...

1. A reference voltage block comprising:an accumulator configured to receive a digital reference value and generate a carry out signal;
a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and
an analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal,
wherein the reference voltage block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper, and
wherein the digital reference value and the predetermined set of gains of the reference voltage block are programmable using the programmable fabric and fed to the reference voltage block via the signal wrapper.

US Pat. No. 10,171,084

SPARSE CODING WITH MEMRISTOR NETWORKS

The Regents of The Univer...

1. A system for sparse coding with an array of resistive memory devices, comprising:an array of resistive memory devices arranged in columns and rows to form a matrix, wherein each column represents a potential feature of an input;
an interface circuit electrically coupled to the matrix, wherein the interface circuit cooperatively operates with the array of resistive memory devices to perform computing in the array of resistive memory devices, wherein the interface circuit controls a computation of:
(a) a first dot product operation by feeding an input vector forward through the matrix to yield an output vector, where the input vector is a column vector with each element representing intensity of a pixel in an image and the output vector is row vector with each element representing the dot product between the input vector and a feature vector stored in a corresponding column of the matrix;
(b) a second dot product operation by feeding a neuron activity vector backward through the matrix to yield an intermediate result vector, where the neuron activity vector is a row vector representing a level of activity from all of the neurons in the matrix and the intermediate result vector is a column vector;
(c) a new input vector by subtracting the intermediate result vector from the input vector; and
(d) a third dot product operation by feeding the new input vector forward through the matrix to yield a new output vector, where the output vector is a row vector with each element representing the dot product between the input vector and the feature vector stored in the corresponding column of the matrix.

US Pat. No. 10,171,083

MEMRISTOR LOGIC DESIGN USING DRIVER CIRCUITRY

Board of Regents, The Uni...

1. A logic gate, comprising:a first memristor and a second memristor connected in series;
a switch, wherein a node of said second memristor is connected to said switch;
a third memristor connected to said switch in series;
a first voltage source connected to said first memristor via a first resistor;
a second voltage source connected in series to said switch and third memristor;
a second resistor connected to said second memristor and ground; and
a third resistor connected to said third memristor and said ground.

US Pat. No. 10,171,082

DRIVING CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A driving circuit which drives a subsequent stage circuit depending on a set signal and a reset signal that are inputted, comprising:a set side level shift circuit which operates depending on the set signal, and generates a set potential,
a reset side level shift circuit which operates depending on the reset signal, and generates a reset potential, and
a control circuit which generates a control signal depending on the set potential and the reset potential, and drives the subsequent stage circuit, wherein
each of the set side level shift circuit and the reset side level shift circuit has
an input transistor which is provided between a high potential and a reference potential, operates depending on the set signal or the reset signal, and outputs a drain potential as the set potential or the reset potential, and
a serial transistor unit which includes a first MOS transistor and a second MOS transistor which are connected in series between a drain terminal of the input transistor and the high potential,
the first MOS transistors in the set side level shift circuit and the reset side level shift circuit complementarily operate to each other corresponding to a logical value of the control signal which the control circuit outputs,
the set side level shift circuit further has a set side buffer which compares a level of the set potential with a threshold value of the set side buffer depending on the high potential, and controls the second MOS transistor of the reset side level shift circuit based on a result of the comparison of the level of the set potential with the threshold value of the set side buffer,
the reset side level shift circuit further has a reset side buffer which compares a level of the reset potential with a threshold value of the reset side buffer depending on the high potential, and controls the second MOS transistor of the set side level shift circuit based on a result of the comparison of the level of the reset potential with the threshold value of the reset side buffer.

US Pat. No. 10,171,081

ON-CHIP SUPPLY NOISE VOLTAGE REDUCTION OR MITIGATION USING LOCAL DETECTION LOOPS IN A PROCESSOR CORE

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a first voltage noise sensor located at a first unit of a processor core, wherein the first voltage noise sensor detects a first voltage droop at the first unit, and wherein the processor core is divided into the first unit and a second unit;
a global noise manager component located in the processor core and associated with a global control loop of the processor core, and that receives, from the first voltage noise sensor, an indication of the first voltage droop; and
a first local noise manager component located in the first unit and associated with a first local control loop of the first unit, where the first local noise manager component is distinct from the global noise manager component and:
receives, from the first voltage noise sensor, the indication of the first voltage droop; and
implements a first noise mitigation procedure at the first unit.

US Pat. No. 10,171,080

VOLTAGE LEVEL SHIFTER (VLS) CIRCUITS EMPLOYING A PRE-CONDITIONING CIRCUIT FOR PRE-CONDITIONING AN INPUT SIGNAL TO BE VOLTAGE LEVEL SHIFTED IN RESPONSE TO A PRE-CHARGE PHASE

QUALCOMM Incorporated, S...

1. A voltage level shifter (VLS) circuit, comprising:a pre-conditioning circuit configured to:
receive an input signal in a first voltage domain; and
generate a pre-conditioned input signal on an input node in the first voltage domain at a voltage level on an input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase;
a pre-charge circuit coupled to an output node and a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain, the pre-charge circuit configured to couple the first supply rail to the output node in response to a pre-charge control signal indicating the pre-charge phase;
a pull-up circuit coupled to the first supply rail and the output node, the pull-up circuit configured to couple the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state; and
a pull-down circuit coupled to the input node and the second supply rail, the pull-down circuit configured to:
decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase; and
couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of a discharge logic state in response to the pre-condition control signal having the voltage level of the discharge logic state indicating an evaluation phase.

US Pat. No. 10,171,079

METHODS AND APPARATUSES FOR DYNAMIC STEP SIZE FOR IMPEDANCE CALIBRATION OF A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a resistor; and
a chip comprising a driver impedance calibration circuit configured to determine an impedance of a driver based on an impedance of the resistor, wherein, during a calibration operation, the driver impedance calibration circuit is configured to adjust an impedance code that controls an impedance of the driver and to provide a next impedance code based on a comparison of a driver output voltage with a reference voltage, wherein an adjustment step size of the impedance code is determined based on a value of the impedance code, wherein the driver impedance calibration circuit comprises an adder/subtractor circuit configured to adjust the impedance code based on a comparison of a driver output voltage with a reference voltage and wherein the adder/subtractor circuit is configured to adjust the impedance code by a value equal to a value of a subset of most significant bits of the impedance code.

US Pat. No. 10,171,078

NONVOLATILE MEMORY DEVICES WITH ON DIE TERMINATION CIRCUITS AND CONTROL METHODS THEREOF

Samsung Electronics Co., ...

1. A method of operating a nonvolatile memory device, comprising:receiving a write command via data input/output terminals in synchronization with a write enable signal while a command latch enable signal (CLE) is enabled;
receiving an address via the data input/output terminals in synchronization with the write enable signal while an address latch enable signal (ALE) is enabled, wherein after the receiving the write command and the address, the CLE and the ALE are disabled;
after the CLE and the ALE are disabled, activating an on-die termination mode of the data input/output terminals in response to an initial falling edge of a data strobe signal and before a rising edge of the data strobe signal, the rising edge of the data strobe signal following the initial falling edge of the data strobe signal;
receiving write data in synchronization with the data strobe signal; and
deactivating the on-die termination mode of the data input/output terminals in response to a transition of at least one of a chip enable signal, the ALE, and the CLE;
wherein the activating the on-die termination mode of the data input/output terminals includes activating a pseudo differential signaling mode of the data input/output terminals and activating a differential signaling mode of the data strobe signal.

US Pat. No. 10,171,077

SCALABLE QUBIT DRIVE AND READOUT

INTERNATIONAL BUSINESS MA...

1. A system for qubit drive and readout, the system comprising:a lossless microwave signal distributor connected to a quantum system, wherein a first input line is connectable to the lossless microwave signal distributor;
a lossless microwave switch connected to the quantum system, wherein a second input line is connectable to the lossless microwave switch, wherein the second input line is configured to drive the quantum system via the lossless microwave switch and the first input line is configured to read out the quantum system via the lossless microwave signal distributor;
a first circulator configured to connect the first input to the lossless microwave signal distributor and configured to connect a quantum-limited amplifier to the lossless microwave signal distributor.

US Pat. No. 10,171,074

ELECTRONIC SYSTEM

CHICONY POWER TECHNOLOGY ...

1. An electronic system electrically connected to an alternative current (AC) power source, the electronic system comprising:a switch; and
a parallel power conversion device comprising:
a first power conversion module electrically connected to the AC power source and the switch and comprising a first current-sampling unit and a first sensing component arranged between the first current-sampling unit and the switch;
a second power conversion module electrically connected to the AC power source; and
a driver electrically connected to the second power conversion module and comprising an amplifier electrically connected to the first sensing component, a comparator electrically connected to the amplifier, a first semiconductor switch electrically connected to the second power conversion module, and a second semiconductor switch electrically connected to the second power conversion module,
wherein the driver makes the second power conversion module operate in a sleep mode to stop outputting a current and to reduce level of an outputting voltage when another current outputted from the first power conversion module is smaller than a specific value.

US Pat. No. 10,171,073

REGULATING TRANSITION SLOPE USING DIFFERENTIAL OUTPUT

SEMICONDUCTOR COMPONENTS ...

1. A circuit for producing a differential output signal pair, the circuit comprising:a first driver for a first output signal in the differential output signal pair;
a second driver for a second output signal in the differential output signal pair;
one or more monitor modules coupled to the first and second drivers to measure slope times of the first and second drivers during each transition;
a comparator coupled to the one or more monitor modules to compare the slope times of the first and second drivers;
one or more regulators coupled to the comparator and at least one of the first and second drivers to regulate at least one slope time of the first or second driver, based on output of the comparator, to provide the first and second output signals in the differential output signal pair with a constant average.

US Pat. No. 10,171,071

DEVICE AND METHOD FOR PRODUCING A DYNAMIC REFERENCE SIGNAL FOR A DRIVER CIRCUIT FOR A SEMICONDUCTOR POWER SWITCH

Power Integrations, Inc.,...

1. A device for producing a dynamic reference signal for a control circuit for a power semiconductor switch, wherein the device comprises:a reference signal generator for providing a dynamic reference signal having a steady-state signal level after a predetermined time has elapsed after a switchover process of the power semiconductor switch;
a passive charging circuit, which is configured to increase a signal level of the dynamic reference signal in reaction to a switchover of a control signal of the power semiconductor switch from an OFF state into an ON state for at least one part of the predetermined time above the steady-state signal level, in order to produce the dynamic reference signal; and
an output for tapping off the dynamic reference signal.

US Pat. No. 10,171,070

SIGNAL TRANSMISSION CIRCUIT AND POWER CONVERSION DEVICE

Mitsubishi Electric Corpo...

1. A signal transmission circuit comprising:a first circuit to output first and second transmission signals on the basis of an external input signal;
first and second transformers to receive said first and second transmission signals on a primary side and obtain first and second transformer output signals on a secondary side; and
a second circuit to generate an external output signal on the basis of said first and second transformer output signals,
wherein said external input signal has first and second logic levels, changes from the second logic level to the first logic level at a first transition time, and changes from the first logic level to the second logic level at a second transition time,
said first circuit outputs said first and second transmission signals such that said first transmission signal changes between the first and second logic levels in a first period when said external input signal is at the first logic level, is fixed to the second logic level when said external input signal is at the second logic level, and is set at the first logic level for a predetermined period at said first transition time of said external input signal, and
such that said second transmission signal changes between the first and second logic levels in a second period when said external input signal is at the second logic level, is fixed to the second logic level when said external input signal is at the first logic level, and is set at the first logic level for a predetermined period at said second transition time of said external input signal, and
said second circuit includes
first and second control protectors to invalidate said first and second transformer output signals for first and second mask periods on the basis of the first or second logic level of said external output signal,
a first signal shaping circuit to receive said first transformer output signal via said first control protector and generate a first logic setting signal indicating an active level for a first logic setting period exceeding a period for which said first transformer output signal indicates an active level,
a second signal shaping circuit to receive said second transformer output signal via said second control protector and generate a second logic setting signal indicating an active level for a second logic setting period exceeding a period for which said second transformer output signal indicates an active level,
a logic setting signal control circuit to receive said first and second logic setting signals and invalidate indication of an active level by said first and second logic setting signals when both said first and second logic setting signals indicate an active level, and
an output signal generation circuit to receive said first and second logic setting signals via said logic setting signal control circuit and generate said external output signal that is set at one logic level of first and second logic levels when said first logic setting signal indicates an active level, and set at the other logic level when said second logic setting signal indicates an active level.

US Pat. No. 10,171,069

SWITCH CONTROLLER FOR ADAPTIVE REVERSE CONDUCTION CONTROL IN SWITCH DEVICES

GENERAL ELECTRIC COMPANY,...

1. A switch controller configured to control a voltage-controlled power switch device, comprising:an output stage coupled to a control terminal of the voltage-controlled power switch device, wherein the output stage is configured to receive a driving signal and provide a driving voltage to the control terminal of the voltage-controlled power switch device;
a voltage sensor configured to provide a measurement of a voltage across the power switch device; and
a digital processing unit configured to receive a switching command and the measurement of the voltage, and to provide the driving signal to the output stage, wherein the digital processing unit is configured to:
compare the measurement with a limit voltage;
cause, using the driving signal, the output stage to provide a first voltage as the driving voltage when the digital processing unit receives the switching command and the measurement is above the limit voltage; and
cause, using the driving signal, the output stage to provide a second voltage as the driving voltage when the digital processing unit receives the switching command and the measurement is below the limit voltage.

US Pat. No. 10,171,068

INPUT INTERFACE CIRCUIT

MSTAR SEMICONDUCTOR, INC....

1. An input interface circuit, comprising:a power line, supplying a default operating voltage;
a ground line, supplying a ground voltage;
an input pad, receiving a pad voltage;
a clamping circuit, coupled between the input pad and a first node, the clamping circuit causing a voltage at the first node to be maintained at the default operating voltage when the pad voltage is higher than the default operating voltage;
a first inverter, having an input end and an output end, the input end coupled to the first node and the output end coupled to a second node;
a high-voltage buffering circuit, having a first input end, a second input end and an output end, the first input end coupled to the input pad, the second input end coupled to the second node, and the output end coupled to a third node, wherein a voltage at the third node is adjusted along with the pad voltage and a voltage at the second node, and the voltage at the third node has a same voltage change trend as the pad voltage;
a second inverter, having an input end and an output end, the input end coupled to the third node and the output end coupled to a fourth node;
a voltage recovery circuit, connected between the power line and the ground line, having an input end and an output end, the input end coupled to the fourth node and the output end coupled to the third node, the third node is selectively coupled to one of the power line and the ground line according to a voltage at the fourth node; and
a third inverter, having an input end thereof coupled to the fourth node and an output end thereof providing a converted voltage.

US Pat. No. 10,171,067

WAVEFORM SHAPING FILTER, INTEGRATED CIRCUIT, RADIATION DETECTION DEVICE, METHOD FOR ADJUSTING TIME CONSTANT OF WAVEFORM SHAPING FILTER, AND METHOD FOR ADJUSTING GAIN OF WAVEFORM SHAPING FILTER

KABUSHIKI KAISHA TOSHIBA,...

1. A waveform shaping filter comprising:a filter stage comprising:
a differentiation signal generation circuit which generates a differentiation signal by amplifying a signal obtained by differentiating an input signal,
a proportional signal generation circuit which generates a proportional signal by amplifying the input signal, and
an adder circuit which outputs an output signal obtained by adding the proportional signal and the differentiation signal; and
a control circuit connected to the filter stage, the control circuit comparing the output signal and a first value so as to detect an overshoot or an undershoot of the output signal, and controlling a time constant of the filter stage, based on whether the overshoot or the undershoot of the output signal has been detected.

US Pat. No. 10,171,066

COMPACT HIGH VOLTAGE RF GENERATOR USING A SELF-RESONANT INDUCTOR

SMITHS DETECTION-WATFORD ...

1. An RF circuit for providing a radio frequency signal, the circuit comprising:a dual inductor including one winding including an input and an output, and another winding including an input and an output;
wherein the one winding and the another winding are arranged to provide, between the one winding and the another winding, a parasitic capacitance selected to determine the frequency of the radio frequency signal; and
wherein the outputs of the windings are configured to electrically couple to a capacitive load.

US Pat. No. 10,171,065

PVT STABLE VOLTAGE REGULATOR

International Business Ma...

1. An apparatus comprising:a voltage regulation module configured to provide an output voltage signal (Vout);
an auto-calibration module configured to provide a calibration current signal (Isink) corresponding to a voltage difference between a target voltage signal (Vtarget) and the output voltage signal (Vout), wherein the output voltage signal (Vout) is substantially equal to the target voltage signal (Vtarget); and
the voltage regulation module configured to adjust the output voltage in response to changes in the calibration current signal.

US Pat. No. 10,171,064

ELASTIC WAVE DEVICE AND ELASTIC WAVE MODULE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a first piezoelectric substrate including a first principal surface and a second principal surface;
a second piezoelectric substrate including a first principal surface and a second principal surface, a thickness of the second piezoelectric substrate being greater than a thickness of the first piezoelectric substrate;
a plurality of first interdigital transducer (IDT) electrodes and a plurality of second IDT electrodes, the plurality of first IDT electrodes being located on the first principal surface of the first piezoelectric substrate, and the plurality of second IDT electrodes being located on the first principal surface of the second piezoelectric substrate; and
a plurality of external connection terminals located on the second principal surface of the first piezoelectric substrate; wherein
a first elastic wave filter including the plurality of first IDT electrodes is located on the first principal surface of the first piezoelectric substrate;
a second elastic wave filter including the plurality of second IDT electrodes is located on the first principal surface of the second piezoelectric substrate;
at least one of the plurality of external connection terminals is a ground terminal;
the first piezoelectric substrate and the second piezoelectric substrate are joined with a support member located therebetween, with the first principal surface of the first piezoelectric substrate and the first principal surface of the second piezoelectric substrate facing each other;
the support member surrounds a region where the first elastic wave filter and the second elastic wave filter are located, in a planar view;
out-of-band attenuation of the first elastic wave filter is greater than out-of-band attenuation of the second elastic wave filter; and
a maximum value of out-of-band attenuation in a frequency band in a range between about 0.85 times and about 1.15 times a center frequency of a passband of the first elastic wave filter, both inclusive, is greater than any out-of-band attenuation in a frequency band in a range between about 0.85 times and about 1.15 times a center frequency of a passband of the second elastic wave filter, both inclusive.

US Pat. No. 10,171,063

FILTER MODULE

WISOL CO., LTD., Osan-si...

14. A mobile communication terminal comprising:an antenna; and
a filter module connected to the antenna, wherein the filter module includes:
a substrate;
a plurality of filters formed on the substrate;
an amplifier formed on the substrate;
a connection part for connecting the plurality of filters and the amplifier to the substrate;
a cover layer formed on the substrate to cover the plurality of filters and the amplifier; and
a matching element formed on the substrate for matching impedances of the plurality of filters and the amplifier,
wherein the plurality of filters and the amplifier are simultaneously or sequentially packaged, and
wherein the matching element is formed in a shape of a layered spiral in a space between input terminals and output terminals of the plurality of filters.

US Pat. No. 10,171,062

VARIABLE-FREQUENCY FILTER

MURATA MANUFACTURING CO.,...

1. A variable-frequency filter allowing a pass band and an attenuation range to be adjusted, the filter comprising:a series-arm resonant circuit connected between a first input/output terminal and a second input/output terminal; and
a parallel-arm resonant circuit connected between a ground and a transmission line connecting one of the first input/output terminal and the second input/output terminal to the series-arm resonant circuit,
wherein each of the series-arm resonant circuit and the parallel-arm resonant circuit includes a piezoelectric resonator, an inductor connected to the piezoelectric resonator, and a variable capacitor connected to the piezoelectric resonator,
wherein the pass band or attenuation range is adjusted by using at least one of a sub-resonant point or a sub-anti-resonant point of the series-arm resonant circuit, or a sub-resonant point or a sub-anti-resonant point of the parallel-arm resonant circuit,
wherein the inductor of the parallel-arm resonant circuit is connected in parallel with the piezoelectric resonator of the parallel-arm resonant circuit, and generates sub-anti-resonance at a lower frequency than a resonant point of the parallel-arm resonant circuit, and
wherein the pass band is set by using the sub-anti-resonant point of the parallel-arm resonant circuit.

US Pat. No. 10,171,061

ELASTIC WAVE DEVICE

MURATA MANUFACTURING CO.,...

1. An elastic wave device comprising:a piezoelectric film;
a high acoustic velocity material in which an acoustic velocity of a bulk wave that propagates through the high acoustic velocity material is higher than that of an elastic wave that propagates through the piezoelectric film;
a low acoustic velocity film which is laminated on the high acoustic velocity material and in which an acoustic velocity of a bulk wave that propagates through the low acoustic velocity film is lower than that of the elastic wave that propagates through the piezoelectric film; and
an IDT electrode on one surface of the piezoelectric film; wherein
the piezoelectric film is laminated on the low acoustic velocity film;
the IDT electrode includes a first busbar, a second busbar that is spaced apart from the first busbar, a plurality of first electrode fingers with proximal ends electrically connected to the first busbar and distal ends extending towards the second busbar, and a plurality of second electrode fingers with proximal ends connected to the second busbar and distal ends extending towards the first busbar;
a direction that is perpendicular or substantially perpendicular to a direction in which the first electrode fingers and the second electrode fingers extend is a width direction, the first electrode fingers, or the second electrode fingers, or each of the first electrode fingers and the second electrode fingers, includes a wide width portion with a dimension in the width direction that is larger than a dimension at a center in a length direction of the first electrode fingers and the second electrode fingers and being provided closer to at least one of a side of the proximal end and a side of the distal end than a central region;
at least one of the first busbar and the second busbar includes a plurality of cavities that are distributed in a length direction of the first busbar or the second busbar; and
the first busbar, or the second busbar, or each of the first busbar and the second busbar, includes an inner busbar portion which is positioned closer to a side of the first electrode fingers or a side of the second electrode fingers than the cavities are and which extends in the length direction of the first busbar and the second busbar, a central busbar portion that includes the cavities, and an outer busbar portion that is positioned opposite to the inner busbar portion with the central busbar portion being interposed therebetween.

US Pat. No. 10,171,060

HIGH PASS FILTER

MURATA MANUFACTURING CO.,...

1. A high pass filter comprising:a first input and output terminal;
a second input and output terminal;
at least one ground terminal;
a signal path disposed between the first input and output terminal and the second input and output terminal;
a first LC series resonator including a first inductor, a first capacitor, a first end electrically connected to the signal path, and a second end electrically connected to the at least one ground terminal, the first inductor, and the first capacitor;
a second LC series resonator including a second inductor, a second capacitor, a third end electrically connected to the signal path, and a fourth end electrically connected to the at least one ground terminal, the second inductor, and the second capacitor;
a third capacitor; and
a multilayer body including a stack of a plurality of insulator layers in a stacking direction; wherein
one electrode of the third capacitor is connected between the first capacitor and the first inductor, and another electrode of the third capacitor is connected between the second capacitor and the second inductor;
the first LC series resonator includes at least one first conductor layer disposed on a corresponding one of the plurality of insulator layers;
the second LC series resonator includes at least one second conductor layer disposed on a corresponding one of the plurality of insulator layers;
the third capacitor includes a first capacitor conductor layer facing at least one of the at least one first conductor layer and the at least one second conductor layer, with a corresponding at least one of the plurality of insulator layers interposed therebetween;
the at least one first conductor layer includes at least one first inductor conductor layer wound in a predetermined direction when viewed in the stacking direction and a second capacitor conductor layer; and
the at least one second conductor layer includes at least one second inductor conductor layer wound in a direction opposite to the predetermined direction when viewed in the stacking direction and a third capacitor conductor layer.

US Pat. No. 10,171,059

COMPOSITE COMPONENT AND FRONT-END MODULE

MURATA MANUFACTURING CO.,...

1. A composite component adapted for being disposed on a mounting substrate, the composite component comprising:a transmitting filter;
a first substrate adapted for being disposed adjacent to the mounting substrate and electrically connected to the mounting substrate;
a second substrate disposed opposite to the first substrate;
a spacer member interposed between the first substrate and the second substrate to support the first substrate and the second substrate, the spacer member being configured to electrically connect the first substrate to the second substrate,
wherein the second substrate is adapted for being electrically connected to the mounting substrate through a second spacer member; and
the transmitting filter is disposed in an internal space and on a principal surface of the first substrate, the internal space being surrounded by the first substrate and the second substrate.

US Pat. No. 10,171,058

ELECTRONIC DEVICE WITH IN-POCKET AUDIO TRANSDUCER ADJUSTMENT AND CORRESPONDING METHODS

Motorola Mobility LLC, C...

1. A method in an electronic device, the method comprising:detecting, with one or more sensors of the electronic device, an enclosed condition;
determining, with one or more processors, an audio signal adjustment function for one or more audio transducers of the electronic device in response to the enclosed condition, wherein the one or more audio transducers comprise a plurality of microphones;
applying, with the one or more processors, the audio signal adjustment function to signals received from, or delivered to, the one or more audio transducers during the enclosed condition;
determining, with the one or more processors, which microphone of the plurality of microphones receives a least amount of enclosure noise; and
selecting, with the one or more processors, the microphone receiving the least amount of enclosure noise to capture audio input from an environment of the electronic device during the enclosed condition.

US Pat. No. 10,171,057

AUTOMATIC GAIN CONTROL LOOP

Elenion Technologies, LLC...

1. An optical receiver comprising:a photodetector for converting an optical signal into an input electrical current signal;
a transimpedance amplifier (TIA) for converting the input electrical current signal into an input voltage signal, the TIA including a variable feedback resistor and a variable gain feed-forward amplifier;
a variable gain amplifier (VGA) for amplifying the input voltage signal to a desired voltage level; and
an automatic gain control loop for generating a first gain control signal for controlling gain of the VGA, and a second gain control signal for controlling the gain of the TIA;
wherein the automatic gain control loop further comprises a signal conditioning circuit for generating the second gain control signal for controlling gain of the TIA based on the first gain control signal;
wherein the second gain control signal is capable of adjusting a value of the variable feedback resistor, whereby the TIA gain varies linearly with a level of the second gain control signal; and
wherein the second gain control signal is also capable of varying a feed forward gain Ao of the TIA.

US Pat. No. 10,171,056

APPARATUS AND METHOD FOR IMPROVING NONLINEARITY OF POWER AMPLIFIER IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for operating an apparatus comprising a transceiver and a power amplifier, in a wireless communication system, the method comprising:attenuating a power of a signal based on a gain compensation value corresponding to the power of the signal, if the power of the signal inputted to the transceiver coupled with the power amplifier is smaller than a reference value; and
transmitting the signal with the attenuated power to the power amplifier.

US Pat. No. 10,171,054

AUDIO ADJUSTMENT BASED ON DYNAMIC AND STATIC RULES

International Business Ma...

1. A method implemented by an information handling system that includes a processor and a memory accessible by the processor, the method comprising:prioritizing a plurality of dynamic rules and a plurality of static rules, wherein the dynamic rules and the static rules are included in a set of rules applied to an output of an audio system;
comparing a set of one or more inputs to the set of rules, wherein the comparing is performed according to the prioritization of the dynamic rules and the static rules;
retrieving at least one audio adjustment based on the comparisons; and
automatically adjusting the output of the audio system based on the retrieved audio adjustment.

US Pat. No. 10,171,053

APPARATUS AND METHODS FOR POWER AMPLIFIERS WITH AN INJECTION-LOCKED OSCILLATOR DRIVER STAGE

SKYWORKS SOLUTIONS, INC.,...

1. A multi-mode power amplifier comprising:a driver stage including an injection-locked oscillator configured to receive a radio frequency input signal and to generate an injection-locked radio frequency signal;
an output stage configured to amplify the injection-locked radio frequency signal to generate a radio frequency output signal, the output stage configured to receive power from an adjustable supply voltage; and
a supply control circuit configured to control a voltage level of the adjustable supply voltage based on a mode of the multi-mode power amplifier.

US Pat. No. 10,171,052

OPERATIONAL AMPLIFIER AND DIFFERENTIAL AMPLIFYING CIRCUIT THEREOF

REALTEK SEMICONDUCTOR COR...

1. An operational amplifier, having a differential input pair and a differential output pair, comprising:an output stage amplifying circuit, using a first terminal and a second terminal as an input port thereof and using said differential output pair as an output port thereof;
a first transistor pair, comprising a first transistor and a second transistor, wherein a first end of said first transistor and a first end of said second transistor are respectively coupled to a first input end and a second input end of said differential input pair, and a second end of said first transistor and a second end of said second transistor are respectively coupled to said first terminal and said second terminal;
a second transistor pair, comprising a third transistor and a fourth transistor, wherein a first end of said third transistor and a first end of said fourth transistor are respectively coupled to said first input end and said second input end of said differential input pair, and a second end of said third transistor and a second end of said fourth transistor are respectively coupled to said first terminal and said second terminal;
a first current source, coupled to said first terminal;
a second current source, coupled to said second terminal;
a third transistor pair, comprising a fifth transistor and a sixth transistor, wherein a first end of said fifth transistor and a first end of said sixth transistor respectively receive a control signal, and a second end of said fifth transistor and a second end of said sixth transistor are respectively coupled to said first terminal and said second terminal; and
a control circuit, coupled to said differential output pair, for generating said control signal according to voltages of said differential output pair and a common mode voltage.

US Pat. No. 10,171,051

AMPLIFICATION CIRCUIT, OPTICAL MODULE, AND AMPLIFICATION METHOD

FUJITSU LIMITED, Kawasak...

1. An amplification circuit coupled to a first circuit by alternating current (AC) coupling comprising:an amplifier that amplifies an input signal by gain A and outputs the amplified input signal as a first signal to a second circuit;
a loopback circuit that positively feeds back the first signal output from the amplifier to an input of the amplifier, the loopback circuit includes
a low pass filter that attenuates a high frequency component of the first signal and outputs the attenuated first signal as a second signal, and
a feedback circuit that attenuates the second signal output from the low pass filter by a feedback factor (gain) ? and positively feeds back to the input of the amplifier; and
a high pass filter using AC coupling is formed at an input of the amplification circuit,
a loop gain of the loopback circuit is represented as a product A·?, and the loop gain is designed so as to satisfy 0 the amplifier is a differential amplifier, and the feedback circuit includes
a first feedback circuit that positively feeds back a normal output of the differential amplifier to an input of the differential amplifier, and
a second feedback circuit that positively feeds back an inversion output of the differential amplifier to the input of the differential amplifier.

US Pat. No. 10,171,050

CIRCUITS FOR PROVIDING CLASS-E POWER AMPLIFIERS

The Trustees of Columbia ...

1. A circuit for forming an amplifier comprising:a first switch having a first side and a second side;
one of a first inductor and a first transmission line, the one of the first inductor and the transmission line having a first side connected to the first side of the first switch and having a second side connected to a non-ground power supply voltage;
one of a second inductor and a second transmission line, the one of the second inductor and the second transmission line having a first side and a second side, the second side of the one of the second inductor and the second transmission line connected to a non-ground power supply voltage; and
a second switch having a first side and a second side, the first side of the second switch being directly connected to the second side of the first switch and the first side of the one of the second inductor and the second transmission line.

US Pat. No. 10,171,049

CLASS-D AMPLIFIER CIRCUITS

Cirrus Logic, Inc., Aust...

1. A Class-D amplifier circuit for amplifying an input signal comprising:an output stage comprising at least first and second switches;
a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to control the duty cycles of said first and second switches within a switching cycle based on said input signal, wherein said switching cycle has a switching frequency based on said clock signal; and
a frequency controller configured to control the frequency of said first clock signal in response to an indication of amplitude of the input signal;
wherein the frequency controller is configured to implement a transition in frequency of said first clock signal from a first switching frequency to a second switching frequency over a period of time, such that the rate of change of switching frequency with time is variable during said transition.

US Pat. No. 10,171,048

POWER AMPLIFIER

Samsung Electro-Mechanics...

1. A power amplifier comprising:an amplifying circuit comprising
a first field effect transistor configured to amplify an input signal, and
a second field effect transistor connected to the first field effect transistor in a cascode structure, and configured to receive the signal amplified by the first field effect transistor and to output the received signal;
a feedback circuit connected to the amplifying circuit, and configured to feedback the signal amplified in the amplifying circuit into the amplifying circuit; and
a feedback controlling circuit connected to the feedback circuit, and configured to control a power of the signal fed-back by the feedback circuit based on a power of the input signal,
wherein the feedback controlling circuit is configured to control the feedback circuit to increase the power of the signal fed-back by the feedback circuit, in response to the power of the input signal input to the amplifying circuit being increased.

US Pat. No. 10,171,046

SYSTEM AND METHOD FOR LOW DISTORTION CAPACITIVE SIGNAL SOURCE AMPLIFIER

INFINEON TECHNOLOGIES AG,...

1. A method comprising:amplifying a signal provided by a capacitive signal source to form an amplified signal;
detecting a peak voltage of the amplified signal;
comparing the detected peak voltage to a predetermined threshold; and
adjusting a controllable bias voltage of the capacitive signal source in response to detecting the peak voltage, the controllable bias voltage of the capacitive signal source being adjusted to a value inversely proportional to the detected peak voltage, wherein adjusting the controllable bias voltage comprises
decreasing the controllable bias voltage at a first rate if the detected peak voltage exceeds the predetermined threshold, and
increasing the controllable bias voltage at a second rate if detected peak voltage does not exceed the predetermined threshold, wherein the first rate is greater than the second rate.

US Pat. No. 10,171,045

APPARATUS AND METHODS FOR LOW NOISE AMPLIFIERS WITH MID-NODE IMPEDANCE NETWORKS

SKYWORKS SOLUTIONS, INC.,...

1. A low noise amplifier comprising:a cascode device;
a transconductance device configured to generate an amplified signal based on amplifying an input signal received at an input node, the transconductance device further configured to provide the amplified signal to an output node via the cascode device; and
a mid-node impedance network electrically connected between the transconductance device and the cascode device, the mid-node impedance configured to compensate for a parasitic capacitance of the transconductance device, the mid-node impedance network including a resistor, a capacitor, and an inductor electrically connected in parallel with one another.

US Pat. No. 10,171,044

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit comprising:a first amplifier that is input with a first signal and outputs a second signal obtained by amplifying the first signal;
a bias circuit that supplies a bias current or a bias voltage to the first amplifier; and
a control voltage generating circuit that generates a control voltage in accordance with a signal level of the first signal,
wherein the bias circuit includes:
a first transistor, the bias current or bias voltage being output from an emitter or source of the first transistor,
a second transistor that is provided between the emitter or the source of the first transistor and ground; and
a third transistor, wherein the control voltage is supplied to a base or gate of the third transistor and an emitter or source of the third transistor supplies a first current or a first voltage to a base or gate of the second transistor,
wherein the control voltage generating circuit includes:
a second amplifier that is input with the first signal and outputs a third signal obtained by amplifying the first signal, and
a voltage outputting circuit that outputs the control voltage in accordance with the third signal, and
wherein the voltage outputting circuit includes:
a current-voltage converting circuit that outputs a second voltage in accordance with a current of the third signal, and
a voltage-level converting circuit that converts the second voltage into the control voltage such that the value of the first current or the first voltage is larger when the signal level of the first signal is the first level than when the signal level of the first signal is the second level.

US Pat. No. 10,171,043

AMPLIFICATION DEVICE INCORPORATING LIMITING

Telefonaktiebolaget LM Er...

1. An amplification device, comprising:an amplifier circuit comprising a signal input for an input signal to be amplified and a first signal output for a first output signal; and
a limiter, wherein the limiter comprises:
a differential amplifier comprising:
a first differential amplifier input for a threshold control signal;
a second differential amplifier input for a feedback signal; and
a differential amplifier output for a threshold signal indicative of a difference between the threshold control signal and the feedback signal;
a first diode having a first anode coupled to the first signal output and a first cathode coupled to the differential amplifier output; and
a feedback stage coupled between the differential amplifier output and the second differential amplifier input, wherein the feedback stage is configured to generate the feedback signal dependent on the threshold signal.

US Pat. No. 10,171,042

DEGENERATED TRANSIMPEDANCE AMPLIFIER WITH WIRE-BONDED PHOTODIODE FOR REDUCING GROUP DELAY DISTORTION

International Business Ma...

1. An integrated circuit comprising:a degeneration network configured to improve group delay across one or more variations;
wherein the degeneration network comprises:
one or more degeneration inductors; and
a transimpedance amplifier including the one or more degeneration inductors;
wherein the transimpedance amplifier includes at least two transistors, and the one or more degeneration inductors are connected between emitters of each of the at least two transistors.

US Pat. No. 10,171,039

DEVICES AND METHODS THAT FACILITATE POWER AMPLIFIER OFF STATE PERFORMANCE

Infineon Technologies AG,...

1. A peaking amplifier comprising:a driver stage having a load impedance and configured to generate a driver output signal based on an input signal;
a final stage having a final stage input impedance and configured to generate a peaking output signal at an output based on the driver output signal; and
an interstage matching network coupled to the driver stage and the final stage and configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is in an ON state and provide a short circuit from an output of the driver stage to an input of the final stage when the peaking amplifier is in an OFF state.

US Pat. No. 10,171,038

ENVELOPE-TRACKING POWER SUPPLY MODULATOR

REALTEK SEMICONDUCTOR COR...

1. An envelope-tracking power supply modulator (ETSM), supplying power to a radio frequency power amplifier (RFPA) of a radio frequency (RF) circuit according to a baseband envelope signal, comprising:a linear amplifier having an input terminal and an output terminal, wherein the input terminal receives the baseband envelope signal, and the output terminal is coupled to a power input of the RFPA;
a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to a reference voltage, and the second terminal is coupled to a power input of the linear amplifier;
a single-inductor multiple-output (SIMO) switch-mode converter having a first output terminal and a second output terminal, wherein the first output terminal is coupled to the capacitor and the power input of the linear amplifier, and the second output terminal is coupled to the output terminal of the linear amplifier and the power input of the RFPA; and
a controller, coupled to the linear amplifier, the capacitor, and the SIMO switch-mode converter, controlling the SIMO switch-mode converter.

US Pat. No. 10,171,036

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit comprising:an amplifier that amplifies an input signal and outputs an amplified signal;
a first bias circuit that supplies a first bias current or voltage to the amplifier;
a second bias circuit that supplies a second bias current or voltage to the amplifier;
a first control circuit that outputs a first current that controls a level of the first bias current or voltage; and
a second control circuit that outputs a second current that controls a level of the second bias current or voltage;
wherein a current supplying capacity of the first bias circuit is different from a current supplying capacity of the second bias circuit,
wherein the first bias circuit comprises a first transistor that outputs the first bias current or voltage in accordance with the first current,
wherein the second bias circuit comprises a second transistor that outputs the second bias current or voltage in accordance with the second current, and comprises a fourth transistor, wherein a collector of the fourth transistor is connected to a base or gate of the second transistor, a base of the fourth transistor is connected to an emitter or source of the second transistor, an emitter of the fourth transistor is connected to ground, and the second current is supplied to the collector of the fourth transistor, and
wherein a size of the first transistor is different from a size of the second transistor.

US Pat. No. 10,171,035

POWER FACTOR CORRECTION CIRCUIT AND MULTIPLIER

COSEMITECH (SHANGHAI) CO....

1. A multiplier comprising:a Gilbert multiplier circuit comprising a first differential input stage, a second differential input stage and an output stage; said output stage outputting the output current calculated by the input of said first differential input stage and the input of the second differential input stage;
a first differential voltage conversion circuit configured to generate a first differential voltage to bias said first differential input stage based on an error feedback voltage signal and a first reference voltage;
a second differential voltage conversion circuit configured to generate a second differential voltage to bias said second differential input stage based on an input voltage and a second reference voltage; and
a bias current generating circuit configured to generate a bias current to bias a first signal conversion circuit and a second signal conversion circuit;
wherein said output stage comprises:
a current mirror unit comprising two current input terminals and a current output terminal; and
a feedback control unit configured to ensure that the current output terminal does not output current when the voltage difference received by the multiplier is zero;
wherein the feedback control unit includes
a first operational amplifier comprising two input terminals connected to the current input terminals of said current mirror unit respectively;
a first switching element comprising a first terminal connected to the current output terminal of said current mirror unit, a second terminal connected to one input terminal of said first operational amplifier, and a control terminal connected to an output terminal of said first operational amplifier; and
a second switching element comprising a first terminal connected to the current output terminal of said current mirror unit, a second terminal configured to output said output current, and a control terminal connected to the output terminal of said first operational amplifier.

US Pat. No. 10,171,034

PHASE-ROTATED HARMONIC-REJECTION MIXER APPARATUS

MEDIATEK INC., Hsin-Chu ...

8. A harmonic-rejection mixer apparatus comprising:a mixing circuit, configured to receive a first input signal, a second input signal, and a local oscillator (LO) signal, and further configured to mix the first input signal and the LO signal to generate a first output signal and mix the second input signal and the LO signal to generate a second output signal, wherein the first input signal and the second input signal have a same peak amplitude but different phases; and
a combining circuit, configured to combine the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

US Pat. No. 10,171,033

CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY

Intel Corporation, Santa...

1. An apparatus comprising:a crystal having an input and an output;
a first interconnect having first and second ends, wherein the first end is coupled to the input;
a second interconnect having first and second ends, wherein the first end is coupled to the output;
a first capacitor coupled between the input and a ground; and
a second capacitor coupled to the second end of the second interconnect, wherein
the second capacitor is split between:
on-board and on-package; or
on-board and on-die.

US Pat. No. 10,171,032

APPARATUSES AND METHODS FOR TEMPERATURE INDEPENDENT OSCILLATORS

Micron Technology, Inc., ...

1. An apparatus, comprising:a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on first and second reference voltages, the pulse generator comprising:
the capacitor coupled between the first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the first node in response to the periodic pulse;
a resistor and a diode coupled in series between a second node and the second reference voltage; and
a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and a current.

US Pat. No. 10,171,031

OSCILLATOR PHASE NOISE USING ACTIVE DEVICE STACKING

International Business Ma...

1. An integrated electronic circuit, comprising:active decoupling circuits, including,
a first active device with a first capacitive device connected across the non-current control terminals of the first active device, and the current control terminal of the first active device connected to ground across a third capacitive device, wherein the current control terminal of the first active device is not electrically coupled to the non-current control terminals of the first active device; and
a second active device with a second capacitive device connected across the non-current control terminals of the second active device, and the current control terminal of the second active device connected to ground across a fourth capacitive device, wherein the current control terminal of the second active device is not electrically coupled to the non-current control terminals of the second active device, and wherein a first non-current control terminal of the first active device is electrically coupled to a first non-current control terminal of the second active device through an inductor.

US Pat. No. 10,171,030

METHOD OF AMPLIFYING POWER

IsoLine Component Company...

1. A method of amplifying power for components mounted on a printed circuit board using a printed circuit board-mounted power supply, the method comprising:optically coupling one or more than one photovoltaic device to a photoluminescent light source, wherein the one or more than one photovoltaic device receives light from the photoluminescent light source;
supplying light source electrical input power to the photoluminescent light source, wherein the light source electrical input power is received from a power source external to the printed circuit board-mounted power supply;
collecting photovoltaic-generated electrical output power from the one or more than one photovoltaic device;
providing the photovoltaic-generated electrical output power to components mounted on the printed circuit board; and
creating the photoluminescent light source, wherein the step of creating the photoluminescent light source comprises a step of optically coupling a light-emitting device that emits high energy light photons in response to receiving light source electrical input power to a photoluminescent material, wherein the photoluminescent material absorbs the high energy light photons emitted by the light-emitting device, and emits more than one low energy light photon for each of the high energy light photons absorbed.

US Pat. No. 10,171,029

SOILING MEASUREMENT DEVICE FOR PHOTOVOLTAIC ARRAYS EMPLOYING MICROSCOPIC IMAGING

1. A device comprisinga transparent window,
an imaging unit, and
a computing element coupled to said imaging unit,
wherein
said device is configured to allow soiling particles to accumulate on a surface of said transparent window,
said imaging unit is configured to capture an image of said surface, and
said computing element is configured to perform analysis of said image to determine a soiling level of said transparent window,
wherein said analysis comprises
determining a reference brightness of said image corresponding to a clean state of said transparent window, and
determining said soiling level based at least upon a brightness of said image relative to said reference brightness.

US Pat. No. 10,171,027

PHOTOVOLTAIC MODULE MOUNT

SunPower Corporation, Sa...

1. A photovoltaic (PV) module coupling, comprising:a body plate having an upper surf ace along a first plane between a first end and a second end;
a retainer extending downward from the second end, wherein the retainer includes a retention surface along a second plane orthogonal to the first plane; and
a toe extending orthogonal to the second plane from the retainer to a terminal edge, the PV module to couple to a module stand, wherein the module stand includes a base portion and an upright extending from the base portion to a support surface, wherein the module stand further includes a locking plate having a locking surf ace coupled to the upright, and wherein the locking plate includes a locking toe slot through the locking surface, wherein the module stand further includes a pair of alignment protrusions extending upward from the support surface, wherein the pair of alignment protrusions define a rail notch between the pair of alignment protrusions and the support surface, and wherein the rail notch is longitudinally aligned with the locking toe slot.

US Pat. No. 10,171,026

STRUCTURAL ATTACHMENT SEALING SYSTEM

Solsera, Inc., Phoenix, ...

1. A method of securing structural attachments comprising the steps of:a. placing a mount on a structure, the mount comprising:
i. a base that conforms to the shape of the surface of the structure, the base comprising an internal cavity further comprising at least one concave section wherein the at least one concave section forms an external cavity, the external cavity further comprising a base;
ii. a port hole coupled to the internal cavity that is accessible from an outer surface of the mount;
iii. a vent coupled to the internal cavity that is accessible from the outer surface of the mount;
iv. a bolt for securing the mount to the structure, the bolt further comprising a head, and a shaft extending from the head;
v. an opening through the external cavity of the at least one concave section, the opening configured to receive the bolt; and
vi. a generally U-shaped guide comprising a pair of vertical members, the vertical members extending from the at least one concave section forming an aperture that is configured to secure a solar panel mounting rail guide to the mount wherein each vertical member further comprising a front side and a rear side;
b. inserting the shaft of the bolt through the opening and through the volume of the internal cavity so that the head resides on the base of the external cavity thereby securing the mount to the structure; and
c. injecting a liquid into the port hole of the mount until the liquid fills the volume of the internal cavity.

US Pat. No. 10,171,025

APPARATUS AND METHOD FOR SOLAR PANEL MODULE MOUNTING INSERTS

LUMETA, LLC, Irvine, CA ...

1. A photovoltaic module, comprisingan upper transparent protective layer;
a photovoltaic layer positioned beneath the upper transparent protective layer, the photovoltaic layer comprising a plurality of electrically interconnected photovoltaic cells disposed in an array;
a rigid substrate layer positioned beneath the photovoltaic layer; and
a plurality of inserts configured to be fixedly attached to (i) a bottom surface of the rigid substrate and (ii) a surface of a roof, the plurality of inserts being disposed in an array, each insert having a substantially triangular-shaped cross section when viewed from a side orthogonal to a line of a roof downward slope, each insert having a thickness to maintain the entire bottom surface of the rigid substrate at about one inch from the surface of the roof, each insert having a thickness in the down-roof direction which is thinner than a thickness in an up-roof direction, at least one insert supporting two adjacent photovoltaic modules.

US Pat. No. 10,171,024

SOLAR ENERGY COLLECTOR

DIVERSIFIED SOLAR SYSTEMS...

1. A solar collector comprising:a frame for supporting a plurality of photovoltaic (PV) panels, wherein the frame is adapted to removably attach to a base;
a first panel assembly, including at least one of the plurality of PV panels, pivotally attached to the frame about a first axis; and
a second panel assembly, including at least one of the plurality of PV panels, pivotally attached to the first panel assembly to collectively move with the first panel assembly about the first axis and to pivot relative to the frame, and to pivot about a second axis that is substantially parallel to and radially offset from the first axis, to move between a deployed position and a retracted position.

US Pat. No. 10,171,023

MOTOR STARTER APPARATUS WITH START-UP FAULT DETECTION CAPABILITY

Eaton Intelligent Power L...

1. An apparatus comprising:at least one semiconductor switch;
at least one current sensor configured to sense a current provided to a load via the at least one semiconductor switch; and
a control circuit configured to cause the at least one semiconductor switch to couple a power source to the load for an interval having a duration of less than one-half of a period of an AC voltage of the power source and to detect a rate of change of the sensed current in response to the coupling.

US Pat. No. 10,171,022

MOTOR DRIVING DEVICE, AN AIR CONDITIONER INCLUDING SAME AND A CONTROL METHOD THEREFOR

SAMSUNG ELECTRONICS CO., ...

1. A motor driving device comprising:a rectifier configured to output an input voltage by rectifying alternating current (AC) power into direct current (DC) power;
a first buck-boost converter configured to convert the input voltage into a DC-link voltage by stepping down the input voltage in a buck mode or stepping up the input voltage in a boost mode;
an inverter configured to convert the DC-link voltage for driving a motor into an AC voltage and transfer the AC voltage to the motor; and
a controller configured to
receive motor information related to driving of the motor,
identify a DC-link voltage for driving the motor according to the motor information,
compare the input voltage with the identified DC-link voltage, to thereby produce a comparison result, and
based on the comparison result, control the first buck-boost converter to operate one of the buck mode and the boost mode for converting the input voltage into the identified DC-link voltage by switching one of a plurality of switches included in the first buck-boost converter,
wherein the controller is configured to
compare an instantaneous value of the input voltage with the identified DC-link voltage,
in response to the instantaneous value of the input voltage being larger than the identified DC-link voltage, control the first buck-boost converter to operate in the buck mode, and
in response to the instantaneous value of the input voltage being smaller than the identified DC-link voltage, control the first buck-boost converter to operate in the boost mode.

US Pat. No. 10,171,021

METHODS FOR DETERMINING A VOLTAGE COMMAND

GM GLOBAL TECHNOLOGY OPER...

1. A method comprising:providing a system with an electric machine that operates in response to a voltage command;
determining, based on characteristics of the system, a minimum voltage for the voltage command;
operating the electric machine only at or above the minimum voltage;
determining, based on capabilities of the system, a maximum voltage for the voltage command;
operating the electric machine only at or below the maximum voltage;
determining, by testing the system, a first representation of a first performance curve for the electric machine corresponding to the minimum voltage;
determining, by testing the system, a second representation of a second performance curve for the electric machine corresponding to the maximum voltage;
obtaining, by a controller and in response to a required torque and a required speed for the electric machine, an operating point of the electric machine to be achieved through the voltage command;
evaluating, by the controller, whether the operating point lies between the first and second representations;
when the operating point lies between the first and second representations, determining, by the controller, a magnitude of the voltage command, by evaluating which of a plurality of voltages corresponding to a third performance curve falling between the first and second representations is most efficient in operating the electric machine at the operating point;
supplying, by a power supply controlled by the controller and to the electric machine, the voltage command at the magnitude; and
operating the electric machine using the voltage command.

US Pat. No. 10,171,020

INTELLIGENT COOPERATIVE CONTROL SYSTEM AND METHOD FOR MULTI-UNIT PERMANENT MAGNET SYNCHRONOUS MOTOR

NORTHEASTERN UNIVERSITY, ...

1. An intelligent cooperative control system for a multi-unit permanent magnet synchronous motor, comprising a double-parallel PWM rectifier circuit, a first permanent magnet motor cooperative control unit, a second permanent magnet motor cooperative control unit, a third permanent magnet motor cooperative control unit and a multi-unit permanent magnet synchronous motor, wherein the first permanent magnet motor cooperative control unit, the second permanent magnet motor cooperative control unit and the third permanent magnet motor cooperative control unit cooperatively control three stator units of the multi-unit permanent magnet synchronous motor in a parallel connection manner,the first permanent magnet motor cooperative control unit, the second permanent magnet motor cooperative control unit and the third permanent magnet motor cooperative control unit adopt the same structure, each of which comprises a driving circuit, a control unit and an inverter unit, wherein the control units realize cooperative control of the multi-unit permanent magnet synchronous motor by mutual communications,
each of the control units comprises a distributed cooperative controller and a current control and speed estimation unit, wherein the current control and speed estimation unit is used for acquiring A phase, B phase and C phase current detection signals at an input end of the motor, obtaining rotor speed estimation values according to the acquired A Phase, B phase, and C phase current detection signals and simultaneously sending the rotor speed estimation values to the distributed cooperative controller of each control unit, and is also used for receiving output values of the distributed cooperative controllers, obtaining a direct-axis voltage reference value and a quadrature-axis voltage reference value in a two-phase stationary reference frame according to the output values, then obtaining PWM signals by using space vector pulse-width modulation, and sending the obtained PWM signals to the inverter unit through the driving circuits, the distributed cooperative controller is used for describing a communication structure of the three control units by using a method for constructing an undirected graph, obtaining an overall communication association matrix of each of the control units according to the constructed undirected graph, constructing an error function according to the rotor speed estimation value, a set rotor speed reference value and the overall communication association matrix of the control units, setting a real number matrix and real number items, and obtaining an output value of each of the distributed cooperative controllers according to the constructed error function.

US Pat. No. 10,171,016

MOTOR DRIVING CIRCUIT

ANPEC ELECTRONICS CORPORA...

1. A motor driving circuit, including an output end for outputting a first output current along a first direction and a second output current along a second direction to drive a motor, the motor driving circuit comprising: a driving module providing a switching driving signal; a first output switch including a first end, a second end and a third end, the first end of the first output switch being electrically connected to a first reference voltage, the third end of the first output switch being electrically connected to the output end of the motor driving circuit, wherein the second end of the first output switch receives a switching driving signal of the driving module;a second output switch including a first end, a second end and a third end, the first end of the second output switch being electrically connected to the third end of the first output switch and the output end of the motor driving circuit, the third end of the second output switch being electrically connected to a second reference voltage, wherein the second end of the second output switch receives the switching driving signal of the driving module;
a first adjusting module including a first adjusting end and a second adjusting end, the first adjusting end of the first adjusting module being electrically connected to the second end of the first output switch, the second adjusting end of the first adjusting module being electrically connected to the output end of the motor driving circuit, wherein the first adjusting module has a first adjusting parameter; and
a second adjusting module including a first adjusting end and a second adjusting end, the first adjusting end being electrically connected to the second end of the first output switch, the second adjusting end of the second adjusting module being electrically connected to the output end of the motor driving circuit, wherein the second adjusting module has a second adjusting parameter;
wherein a rising slew rate of the first output current along the first direction is adjusted according to the first adjusting parameter of the first adjusting module, a falling slew rate of the first output current along the first direction is adjusted according to the second adjusting parameter of the second adjusting module;
wherein the first adjusting module includes: a first current mirror unit, including:
a first current mirror switch having a first end, a second end and a third end, the first end of the first current mirror switch being electrically connected to a third reference voltage; and a second current mirror switch having a first end, a second end and a third end, the first end of the second current mirror switch being electrically connected to the third reference voltage; and a first adjusting unit, including:
a first adjusting capacitor having a first end and a second end; a first adjusting switch having a first end, a second end and a third end; and
a second adjusting switch having a first end, a second end and a third end, wherein the third end of the first adjusting switch and the third end of the second adjusting switch are electrically connected to a fourth reference voltage;
wherein the second end of the first current mirror switch is electrically connected to the second end and the third end of the second current mirror switch, the third end of the first current mirror switch is electrically connected to the first adjusting end of the first adjusting module, the third end of the second current mirror switch is electrically connected to the first end of the second adjusting switch, the first end of the first adjusting switch is electrically connected to the second end of the second adjusting switch, the first end of the first adjusting switch is electrically connected to the second end of the first adjusting capacitor, and the first end of the first adjusting capacitor is electrically connected to the second adjusting end of the first adjusting module.

US Pat. No. 10,171,014

SYSTEM AND METHOD FOR ELECTRIC MOTOR FIELD WEAKENING WITH VARIABLE MAGNET SKEW

GM GLOBAL TECHNOLOGY OPER...

1. An electric machine assembly comprising:a rotor assembly positioned inside of a stator core and rotatable relative to the stator core, the rotor assembly extending along a longitudinal axis and comprising a plurality of rotor parts including a reference rotor part and a first control rotor part, each rotor part rotatable about the longitudinal axis and mechanically separated from another rotor part along the longitudinal axis, the first control rotor part controllable to rotate while aligned with the reference rotor part with a zero or near zero skew angle relative to the reference rotor part, the first control rotor part controllable to rotate while unaligned with the reference rotor part with a non-zero skew angle relative to the reference rotor part; and
a rotor controller configured to control the first control rotor part to rotate while aligned with the reference rotor part with a zero or near zero skew angle relative to the reference rotor part and configured to control the first control rotor part to rotate while unaligned with the reference rotor part with a non-zero skew angle relative to the reference rotor part, the controller comprising a processor configured by programming instructions encoded on non-transitory computer readable media to control the degree of skew angle between the control rotor part and the reference rotor part.

US Pat. No. 10,171,013

SERVOMOTOR CONTROL DEVICE

FANUC CORPORATION, Yaman...

1. A servomotor control device comprising:a position control loop for feedback controlling a position of a servomotor;
a speed control loop for feedback controlling speed of the servomotor;
a position command creation part that creates a position command value for the servomotor;
a stop determination part that determines whether or not the servomotor is stopped;
a static-friction correction amount calculation part that calculates a static-friction correction amount of the servomotor; and
a static-friction correction amount modification part that performs a predetermined modification on the static-friction correction amount calculated by the static-friction correction amount calculation part, in a case of the servomotor stopping, and then starting to operate in the same direction as prior to stopping,
wherein the static-friction correction amount modification part performs the predetermined modification based on the command acceleration of the servomotor and a second-order derivative of the position command value created by the position command creation part.

US Pat. No. 10,171,012

AIR CONDITIONER AND STARTUP CONTROL METHOD AND SYSTEM FOR OUTDOOR FAN OF THE AIR CONDITIONER

Guangdong Welling Motor M...

1. A method for starting control over an outdoor fan of an air conditioner, wherein a motor of the outdoor fan is driven by a driver, and the method for starting control over the outdoor fan of the air conditioner comprises the following steps of:when a bootstrap capacitor in the driver is charged, detecting an initial rotating state of the motor in real time; and
after the bootstrap capacitor is charged, correspondingly controlling the motor to be started according to the detected initial rotating state;
wherein the step of correspondingly controlling the motor to be started according to the detected initial rotating state comprises the following steps:
Step a: when the initial rotating state of the motor is pneumatic forward direction rotation, judging according to the rotating speed of the motor whether a motor observer converges;
executing Step e if the motor observer converges, or else executing Step d;
Step b: when the initial rotating state of the motor is stillness, performing positioning control over the motor, and executing Step d;
Step c: when the initial rotating state of the motor is pneumatic counter rotation, controlling the motor according to a constant deceleration to stop rotating, and executing Step d;
Step d: controlling the motor to perform accelerated rotation in a vector control mode; and
Step e: controlling the motor to enter into a conventional operation state in a vector control mode.

US Pat. No. 10,171,010

METHOD AND APPARATUS FOR GENERATING ENERGY USING PIEZO ELEMENTS

GSI HELMHOLTZZENTRUM FUER...

1. An energy-generating apparatus comprising:at least one magnetic field interaction device;
at least one magnetic field-generating apparatus configured to undergo linear, reciprocal movements relative to the at least one magnetic field interaction device so as to at least intermittently generate a magnetic field that varies over time; and
at least one energy-generating device including a piezo element device.

US Pat. No. 10,171,009

APPARATUS AND METHOD FOR LIFTING OBJECTS

SIEMENS AKTIENGESELLSCHAF...

1. An apparatus for lifting an object, comprising:a plurality of piezo actuators that expand in directions upon activation to thereby generate pressure forces on an active side of each piezo actuator;
a hydraulic transmission device configured to:
convert the pressure forces of the piezo actuators into a vertical pressure force to move the object in a direction counter to a direction of gravity; and
transmit said converted pressure forces with a transmission ratio; and
a spring system connected between the object and the hydraulic transmission device, the spring system providing a spring force counter to the vertical pressure force of the hydraulic transmission device.

US Pat. No. 10,171,008

VIBRATION WAVE MOTOR AND DRIVING APPARATUS USING THE VIBRATION WAVE MOTOR

Canon Kabushiki Kaisha, ...

1. A vibration wave motor, comprising:a vibrating plate having a rectangular surface;
a piezoelectric device bonded onto the vibrating plate, and configured to vibrate at high frequency; and
a projection provided on one of the vibrating plate and the piezoelectric device, wherein
a natural vibration mode, which has a resonant frequency equal to or adjacent to a resonant frequency of torsional vibration in a natural vibration mode under a state in which the vibrating plate, the piezoelectric device, and the projection are integrated, is a natural vibration mode of bending vibration in one of a direction parallel to and a direction orthogonal to a torsion center axis of the torsional vibration in the natural vibration mode, and
the projection is provided at a position closer to an antinode than to a node, the node and the antinode being in the direction orthogonal to the torsion center axis of the torsional vibration in the natural vibration mode.

US Pat. No. 10,171,007

METHOD OF MANUFACTURING A DEVICE WITH A CAVITY

TAIWAN SEMICONDUCTOR MANU...

18. A method, comprising:providing a substrate having a first sacrificial oxide region;
depositing a first porous layer over the first sacrificial oxide region, the first porous layer being permeable to a vapor hydrofluroic acid (HF) etchant;
depositing a second sacrificial oxide region over the first porous layer;
depositing a second porous layer over the second sacrificial oxide region, the second porous layer being permeable to the vapor HF etchant; and
selectively etching the first and second sacrificial oxide regions through the first and second porous layers using the vapor HF etchant.

US Pat. No. 10,171,006

POWER POLE INVERTER

Eaton Intelligent Power L...

1. An arm assembly comprising:a plurality of electrical components;
a number of electrical buses;
each electrical component coupled to, and in electrical communication with, one said electrical bus;
a sealing compound applied to each said electrical bus and to a limited number of said electrical components;
wherein said limited number of said electrical components having said sealing compound applied thereto are enclosed components and any component without said sealing compound applied thereto is an exposed component; and
wherein said enclosed components are substantially sealed from an atmosphere.

US Pat. No. 10,171,005

INVERTER CONTROL DEVICE

Daikin Industries, Ltd., ...

1. An inverter control device that controls a voltage source inverter that converts a DC voltage into three-phase AC voltages, whereinsaid voltage source inverter includes three current paths connected in parallel to one another between first and second DC bus lines to which said DC voltage is applied, in which the potential of the first DC bus line is higher than that of the second DC bus line,
each of said current paths includes:
a connecting point for the corresponding current path;
an upper arm-side switch that is connected between said first DC bus line and the connecting point of the corresponding current path and flows a current from said first DC bus line to the connecting point of the corresponding current path at a first time of conduction;
a lower arm-side switch that is connected between the connecting point of the corresponding current path and said second DC bus line and flows a current from the connecting point of the corresponding current path to said second DC bus line at a second time of conduction;
an upper arm-side diode connected in antiparallel to said upper arm-side switch; and
a lower arm-side diode connected in antiparallel to said lower arm-side switch, said inverter control device includes:
a switching signal generation unit that generates a switching signal that causes any one of said upper arm-side switches and said lower arm-side switch to conduct exclusively of each other in each of said current paths while maintaining conduction/nonconduction of said upper arm-side switch in one cycle of a triangular wave on the basis of comparison between said triangular wave and a plurality of voltage commands included in first and second voltage command groups; and
a voltage command generation unit that generates said first and second voltage command groups,
said triangular wave exhibits a minimum value twice, a first maximal value once, and a second maximal value once in said one cycle,
said first voltage command group corresponds to said switching signal in which, in a first section including a first point of time when sums of periods while said upper arm-side switches in a pair of said current paths conduct in said one cycle are equal to each other at zero, a period while said upper arm-side switches in all of said current paths are nonconductive in said one cycle is adjacently sandwiched by a pair of periods while all of said upper arm-side switches in the pair of said current paths are nonconductive and other of said upper arm-side switch conducts, and
said second voltage command group corresponds to said switching signal in which, in a second section exclusive of said first section and including a second point of time when sums of periods while said upper arm-side switches in a pair of said current paths conduct in said one cycle are equal to each other at non-zero, a period while said upper arm-side switches in all of said current paths conduct in said one cycle is adjacently sandwiched by a pair of periods while all of said upper arm-side switches in the pair of said current paths conduct and other of said upper arm-side switch is nonconductive.

US Pat. No. 10,171,004

DC-DC CONVERTER

MURATA MANUFACTURING CO.,...

1. A direct current-to-direct current converter comprising:an input configured to receive a direct-current voltage V1;
an output configured to output a direct-current voltage V2;
a first full-bridge circuit connected to the input;
a second full-bridge circuit connected to the output;
a transformer having a first winding connected to the first full-bridge circuit and a second winding connected to the second full-bridge circuit; and
a controller configured to perform switching control of the first full-bridge circuit,
wherein the first full-bridge circuit includes:
a first series circuit including first, second, third and fourth switching elements sequentially connected in series to each other,
a second series circuit connected in parallel to the first series circuit and including fifth, sixth, seventh and eighth switching elements sequentially connected in series to each other,
a first floating capacitor connected to a first node between the first and second switching elements and a second node between the third and fourth switching elements, and
a second floating capacitor connected to a third node between the fifth and sixth switching elements and a fourth node between the seventh and eighth switching elements,
wherein a first end of the first winding of the transformer is connected to a fifth node between the second and third switching elements and a second end of the first winding of the transformer is connected to a sixth node between the sixth and seventh switching elements, and
wherein the controller performs the switching control of the first full-bridge circuit in at least two modes including a full-bridge operation mode in which the first to eighth switching elements are controlled so that the direct-current voltage V1 is applied to the first and second ends of the first winding of the transformer and a half-bridge operation mode in which the first to eighth switching elements are controlled so that half of the direct-current voltage V1 is applied to the first and second ends of the first winding of the transformer.

US Pat. No. 10,171,002

SWITCHING POWER SUPPLY AND IMAGE FORMING APPARATUS

BROTHER KOGYO KABUSHIKI K...

1. A switching power supply comprising:a main power supply;
a rectifying-and-smoothing circuit configured to rectify an AC voltage supplying from the main power supply, and to smooth the rectified AC voltage by a smoothing capacitor;
a transformer connected to the rectifying-and-smoothing circuit;
a first switching element connected to a primary coil of the transformer;
a switch controller configured to perform switching-control the first switching element to oscillate the primary side of the transformer, thereby inducing a voltage to a secondary side of the transformer; and
a second switching element connected in series with the smoothing capacitor of the rectifying-and-smoothing circuit and configured to switch between on-and-off states of energization by a control signal that is to be output from the switch controller,
wherein the switch controller is configured to limit an on-time period of the second switching element by the control signal during an output stop mode in which the oscillation of the transformer is to be stopped.

US Pat. No. 10,171,000

REDUCTION OF AUDIBLE NOISE IN A POWER CONVERTER

Power Integrations, Inc.,...

1. A controller for use in a power converter, comprising:a drive circuit coupled to generate a drive signal to control switching of a power switch of the power converter to control a transfer of energy from an input of the power converter to the output of the power converter, wherein the drive circuit generates the drive signal in response to a current sense signal representative of a current through the power switch, a current limit signal, a frequency skip signal, and a hold signal;
a current limit generator coupled to generate the current limit signal in response to a load coupled to the output of the power converter;
a frequency detection circuit coupled to generate the frequency skip signal in response to the drive signal to indicate when an intended frequency of the drive signal is within a frequency window such that the current limit signal is coupled to remain fixed for at least a switching cycle when the frequency skip signal indicates that the intended frequency of the drive signal is within the frequency window; and
a first latch coupled to generate the hold signal to control the current limit generator to hold the current limit signal, wherein the first latch is coupled to generate the hold signal in response to the frequency skip signal, and in response to a feedback signal representative of the output of the power converter.

US Pat. No. 10,170,997

SWITCHING POWER SUPPLY APPARATUS

DENSO CORPORATION, Kariy...

1. A switching power supply apparatus comprising:a main circuit including a switching element and an inductor, the switching element turning on to increase a current flowing in the inductor when a driving signal changes to an on-level and turning off to recirculate the current flowing in the inductor to an output side when the driving signal changes to an off-level;
a current detection circuit for outputting a current detection signal corresponding to the current flowing in the inductor through the switching element;
a voltage detection circuit for outputting a detection voltage corresponding to an output voltage of the main circuit;
an error amplification circuit for outputting an error signal in accordance with a difference between a reference voltage corresponding to a target output voltage of the main circuit and the detection voltage;
a PWM signal generation circuit for performing a current mode control to set a PWM signal to the on-level in synchronization with a clock signal and set the PWM signal to the off-level in synchronization with a normal reset signal, which changes a level when the current detection signal reaches the error signal;
a driver circuit for outputting the driving signal in response to the PWM signal;
a switching determination circuit for checking whether the output voltage reached a switching determination voltage higher than the target output voltage; and
a reset signal generation circuit for generating a reset signal for a short-pulse operation, which is delayed by a predetermined delay period from a time point of a change of the PWM signal to the on-level,
wherein the PWM signal generation circuit changes the PWM signal to the off-level in synchronization with the reset signal for short-pulse operation in place of the normal reset signal when the switching determination circuit determines that the output voltage reached the switching determination voltage.

US Pat. No. 10,170,994

VOLTAGE REGULATORS FOR AN INTEGRATED CIRCUIT CHIP

ADVANCED MICRO DEVICES, I...

1. An apparatus that controls voltages, comprising:an integrated circuit chip comprising a set of circuits;
a switching voltage regulator separate from the integrated circuit chip;
a plurality of low dropout (LDO) regulators fabricated on the integrated circuit chip, wherein the switching voltage regulator provides an output voltage that is received as an input voltage by each of the plurality of LDO regulators and wherein each LDO regulator of the plurality of LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits; and
a controller configured to:
for each LDO regulator, identify the local output voltage to be provided by the LDO regulator;
based on the local output voltage to be provided by each of the LDO regulators, identify the output voltage to be provided by the switching voltage regulator; and
configure the switching voltage regulator to provide the output voltage and each LDO regulator to provide the local output voltage to be provided by the LDO regulator.

US Pat. No. 10,170,993

CONTROL SYSTEM FOR TRANSITIONING A DC-DC VOLTAGE CONVERTER FROM A BUCK OPERATIONAL MODE TO A SAFE OPERATIONAL MODE

LG Chem, Ltd., Seoul (KR...

1. A control system for transitioning a DC-DC voltage converter from a buck operational mode to a safe operational mode, the DC-DC voltage converter having a high voltage switch, a low voltage switch, and a DC-DC voltage converter control circuit with a high side integrated circuit and a low side integrated circuit therein, the DC-DC voltage converter control circuit being electrically coupled between the high voltage switch and the low voltage switch; the high side integrated circuit having a first plurality of FET switches therein, the low side integrated circuit having a second plurality of FET switches therein, comprising:a microcontroller having a first application and a second application;
the first application commanding the microcontroller to generate a first control signal that is received at a first input pin on the high side integrated circuit to command the high side integrated circuit to transition each of the first plurality of FET switches therein to an open operational state, the first control signal being further received at a first input pin on the low side integrated circuit to command the low side integrated circuit to transition each of the second plurality of FET switches therein to the open operational state; and
the second application commanding the microcontroller to generate a second control signal that is received at a second input pin on the high side integrated circuit to command the high side integrated circuit to transition each of the first plurality of FET switches therein to the open operational state, the second control signal being further received at a second input pin on the low side integrated circuit to command the low side integrated circuit to transition each of the second plurality of FET switches therein to the open operational state.

US Pat. No. 10,170,991

CONTROL CIRCUIT AND CONTROL METHOD FOR A VOLTAGE CONVERTER

Silergy Semiconductor Tec...

1. A control circuit for a voltage converter having a plurality of input voltage signals and one output voltage signal, the control circuit comprising:a) a logic control circuit configured to receive an operation signal, and to generate an enable signal, a trigger signal, and an order signal;
b) a feedback control circuit configured to receive said plurality of input voltage signals, and said output voltage signal, and to generate a plurality of feedback control signals according to said enable signal, said trigger signal, and said order signal; and
c) a channel selection circuit configured to receive said order signal and said plurality of feedback control signals, and to generate a plurality of control signals to control switches in said voltage converter.

US Pat. No. 10,170,990

METHODS AND APPARATUS FOR A SINGLE INDUCTOR MULTIPLE OUTPUT (SIMO) DC-DC CONVERTER CIRCUIT

University of Virginia Pa...

1. A method, comprising:receiving information related to one or more of a processing power demand and an available energy level of an integrated circuit (IC) that includes a single-inductor multiple-output (SIMO) direct current-direct current (DC-DC) converter circuit and a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit,
the SIMO DC-DC converter circuit having a plurality of output nodes, each output node from the plurality of output nodes being uniquely associated with a supply voltage rail from a plurality of supply voltage rails, and
the PDVS circuit having a plurality of operational blocks; and
operating the PDVS circuit such that each operational block from the plurality of operational blocks draws power from one supply voltage rail from the plurality of supply voltage rails.

US Pat. No. 10,170,989

METHODS FOR FABRICATING AN INTEGRATED CIRCUIT WITH A VOLTAGE REGULATOR

SKYWORKS SOLUTIONS, INC.,...

1. A method of fabricating an integrated circuit, the method comprising:forming a primary regulator on a semiconductor substrate, including fabricating a switch, fabricating an amplifier for controlling the switch, and fabricating a voltage generator for biasing the amplifier to operate the primary regulator in a bypass mode or in a regulating mode, including forming a first stack of transistors that generate one or more bias voltages of the amplifier and forming a second stack of transistors that mirror a current through the first stack to generate a reference voltage of the amplifier;
forming an input terminal and an output terminal of the primary regulator on the semiconductor substrate;
forming a secondary regulator on the substrate;
forming an input terminal and an output terminal of the secondary regulator on the semiconductor substrate; and
forming an electrical connection between the output terminal of the primary regulator and the input terminal of the secondary regulator.

US Pat. No. 10,170,988

POWER SUPPLY SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. A power supply system comprising:an electric power line connected to a load;
a plurality of DC power supplies;
a power converter connected across said plurality of DC power supplies and said electric power line; and
a control device configured to control operation of said power converter, said power converter including a plurality of switching elements and being configured to control an output voltage on said electric power line by operating with one of a plurality of operation modes different in mode of power conversion between said plurality of DC power supplies and said electric power line applied,
said plurality of operation modes including
a first operation mode in which power distribution between said plurality of DC power supplies is controllable through said power converter, and
a second operation mode in which power distribution between said plurality of DC power supplies is determined in a fixed manner through said power converter,
said control device including
a mode selection unit configured to select an operation mode from among said plurality of operation modes in accordance with conditions of said load and said plurality of DC power supplies, and
an operation mode switching control unit configured to, when a present operation mode currently applied to said power converter and an operation mode after transition selected by said mode selection unit are different, control switching from said present operation mode to said operation mode after transition,
when said present operation mode is said first operation mode and said operation mode after transition is said second operation mode, said operation mode switching control unit controlling, in said first operation mode, power distribution between said plurality of DC power supplies to be performed at a power distribution ratio in a case where said operation mode after transition is applied, and then executing switching to said operation mode after transition,
wherein when electric power of each of said DC power supplies in accordance with the power distribution ratio in the case where said operation mode after transition is applied reaches a limiting value for each of said DC power supplies, said operation mode switching control unit prohibits switching to the operation mode after transition.

US Pat. No. 10,170,985

APPARATUS FOR CURRENT ESTIMATION OF DC/DC CONVERTER AND DC/DC CONVERTER ASSEMBLY

NATIONAL CHUNG SHAN INSTI...

1. An apparatus for current estimation of a DC/DC converter, comprising:a current sensing unit for sensing a current passing through a switch of the DC/DC converter and converting the current into a voltage signal;
a signal sampling unit, coupled to the current sensing unit, for sampling the voltage signal so as to output a sampled signal; and
a current estimator, coupled to the signal sampling unit, for determining a signal indicating estimated magnitude of an inductor current of the DC/DC converter, based on the sampled signal, a scale factor of the current sensing unit, a duty ratio of a driving signal for controlling the switch, an input voltage and an output voltage of the DC/DC converter,
wherein the signal sampling unit is configured to be synchronized to the driving signal, and the signal sampling unit samples the voltage signal at a middle of each ON period of the driving signal so as to output the sampled signal.

US Pat. No. 10,170,984

SWITCHED MODE POWER CONVERTER WITH PEAK CURRENT CONTROL

INFINEON TECHNOLOGIES AUS...

17. A power converter, comprising:an electronic switch connected in series with an inductor; and
a controller configured to operate the power converter in one of a first operation mode and a second operation mode and, in each of the first operation mode and the second operation mode, to drive the electronic switch in a plurality of successive drive cycles based on a drive parameter such that each of the plurality of successive drive cycles comprises an on-time in which the electronic switch is switched on and an off-time in which the electronic switch is switched off,
wherein the drive parameter is one of a duration of the drive cycle or a duration of the off-time,
wherein the drive parameter is predefined in the first operation mode, and
wherein the controller is configured to increase the drive parameter in the second operation mode as compared to the first operation mode such that a duration of the on-time in the second operation mode is above a predefined duration threshold.

US Pat. No. 10,170,983

DRIVING DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A load driver comprising:a voltage step-up and -down DC/DC converter controller block which controls a voltage step-up and -down DC/DC converter that generates an output voltage from an input voltage and feeds the output voltage to a load,
wherein the voltage step-up and -down DC/DC converter comprises:
a first switch of which a first terminal is connected to an application terminal of the input voltage, the first switch being an N-channel type field effect transistor;
a first diode of which a cathode is connected to a second terminal of the first switch and of which an anode is connected to a ground terminal;
an inductor of which a first terminal is connected to the second terminal of the first switch;
a second switch of which a first terminal is connected to a second terminal of the inductor and of which a second terminal is connected to the ground terminal;
a second diode of which an anode is connected to the second terminal of the inductor and of which a cathode is connected to a first terminal of the load;
a capacitor of which a first terminal is connected to the application terminal of the input voltage and of which a second terminal is connected to the ground terminal; and
a boot strap capacitor of which a first terminal is connected to the cathode of the first diode, and
wherein the voltage step-up and -down DC/DC converter controller block comprises:
a boot strap terminal arranged to be connected to a second terminal of the boot strap capacitor,
an output terminal arranged to be connected to a gate of the first switch,
a switching terminal arranged to be connected to the first terminal of the boot strap capacitor,
a constant voltage generation portion arranged to generate a constant voltage from a node voltage of a connection node disposed between the first terminal of the capacitor and the application terminal of the input voltage;
a first driver of which an upper power supply node is connected to the boot strap terminal, of which a lower power supply node is connected to the switching terminal, of which an output node is connected to the output terminal, and arranged to generate a first gate voltage of the first switch so as to turn the first switch on and off; and
a second driver arranged to generate a second gate voltage of the second switch so as to turn the second switch on and off, the driver further arranged to receive the constant voltage as a power supply voltage, a high level of the gate voltage of the second switch being the constant voltage, and wherein
the boot strap terminal, the output terminal and the switching terminal are arranged in the recited order.

US Pat. No. 10,170,982

CONTINUOUS COMPARATOR WITH IMPROVED CALIBRATION

1. A circuit comprising:a power switch;
a continuous comparator that monitors a current across the power switch;
a dynamic comparator which shares inputs of the continuous comparator;the dynamic comparator being adapted to provide a logic signal;a calibration control adapted to calibrate the continuous comparator;
wherein a clock for the dynamic comparator is coupled with a control signal for changing a state of the power switch; and
wherein the calibration control comprises a counter coupled with an output of the dynamic comparator and one of a variable comparator offset or a variable propagation delay that is directly connected to the continuous comparator; the counter being adapted to receive the logic signal;
wherein the counter operates to increment or decrement the variable comparator offset or the variable propagation delay.

US Pat. No. 10,170,981

CONFIGURABLE BI-DIRECTIONAL CHARGE PUMP DESIGN

Akustica, Inc., Pittsbur...

1. A bi-directional charge pump cell comprising:a p-type substrate having a main surface;
a first n-well formed in the p-type substrate, the first n? well including n+ doped regions formed in the first n? well at the main surface;
a first p-well formed in the first n? well, the first p? well including p+ doped regions formed in the first p-well at the main surface;
a second n-well formed in the first p-well, the second n-well including n+ doped regions and p regions formed at the main surface, the p regions forming p-type metal-oxide semiconductor (PMOS) transistors;
a second p-well formed in the first n-well, the second p-well including p+ doped regions formed in the second p-well at the main surface; and
a third p-well defined in the second p-well, the third p-well including p+ doped regions and n regions at the main surface, the n regions forming n-type metal-oxide semiconductor (NMOS) transistors.

US Pat. No. 10,170,979

POINT OF LOAD REGULATOR SYNCHRONIZATION AND PHASE OFFSET

International Business Ma...

1. An electronic system including at least three point of load (POL) regulators that supply a regulated voltage to a component within the electronic system, the electronic system comprising:a master POL regulator that operates under a reference phase and communicates a first SYNC OUT signal that is offset from the reference phase by a first phase offset to a first controlled POL regulator and communicates a second SYNC OUT signal that is offset from the reference phase by a second phase offset to a second controlled POL regulator.

US Pat. No. 10,170,978

SIGNAL TRANSMISSION CIRCUIT

DENSO CORPORATION, Kariy...

1. A signal transmission circuit comprising a transmission apparatus and a reception apparatus which are insulated from each other and between which a signal indicative of predetermined information is transmitted via an insulation element,wherein the transmission apparatus includes a first transmission unit transmitting a first signal indicative of first information based on the number of pulses consecutively outputted with a predetermined period and each having a first waveform with a duty cycle of less than 100% with respect to the period and a second transmission unit transmitting a second signal indicative of second information based on a pulse having a longer wavelength than the first waveform,
wherein the first transmission unit transmitting the first signal to the reception apparatus and the second transmission unit transmitting the second signal to the reception apparatus, via the insulation element common to the first transmission unit and the second transmission unit, and
wherein the second transmission unit transmits the second signal in synchrony with the pulse having the first waveform, and transmits the second signal indicative of the second information using a pulse having a wavelength which is longer than the first waveform and which is shorter than a period during which the pulse having the first waveform is consecutively outputted.

US Pat. No. 10,170,977

SUPPLEMENTAL CIRCUIT FOR POWER SUPPLY WITH POWER MANAGEMENT IC

Shenzhen China Star Optoe...

1. A supplemental circuit for a power supply equipped with a power management integrated circuit (PMIC), comprising:a detection circuit producing input signals;
a switch;
a signal generation circuit producing a control signal controlling the switch's open and close according to the input signals; and
a RC circuit;
wherein when the switch is closed, the PMIC and the RC circuit are series-connected to ground;
wherein the detection circuit comprises:
a first detection sub-circuit detecting an input current to the power supply and, according to the detected input current, producing a first input signal for controlling the switch's open and close;
a second detection sub-circuit detecting an output current from the power supply and, according to the detected output current, producing a second input signal for controlling the switch's open and close; and
a third detection sub-circuit detecting a mode of a display device incorporating the power supply and, according to the detected mode, producing a third input signal for controlling the switch's open and close;
wherein the signal generation circuit produces the control signal controlling the switch's open and close according to the first, second, and third input signals.

US Pat. No. 10,170,976

PHASE COMPENSATION METHOD FOR POWER FACTOR CORRECTION CIRCUIT

DELTA ELECTRONICS (THAILA...

1. A method for phase compensating a power factor correction circuit, the power factor correction circuit comprising a switching circuit and a control unit and receiving an input voltage and an input current, the switching circuit being alternately turned on or turned off to generate an output voltage and an output current under control of the control unit, the control unit comprising a low-pass filter, a differential controller and a cosine multiplier, the low-pass filter continuously receiving a sampled signal that reflects a present current value of the input current, the method comprising steps of:(a) the low-pass filter filtering the sampled signal;
(b) the differential controller predicting a present waveform of the input current corresponding to the present current value of the filtered sampled signal and a previous waveform of the input current corresponding to a previous current value of the filtered sampled signal and generating a current error signal according to a difference between the present waveform and the previous waveform;
wherein the differential controller stores a compensation factor;
wherein in the step (b), the difference between the present waveform and the previous waveform is multiplied by the compensation factor, so that the current error signal is generated;
(c) the cosine multiplier adjusting the current error signal, thereby generating an adjusted signal;
(d) adding a feedforward signal to the adjusted signal, thereby generating a phase compensation signal; and
(e) adding a current control signal to the phase compensation signal, thereby
generating a pulse width modulation signal to control the switching circuit.

US Pat. No. 10,170,974

VARIABLE FREQUENCY AND BURST MODE OPERATION OF PRIMARY RESONANT FLYBACK CONVERTERS

Apple Inc., Cupertino, C...

1. A primary resonant flyback converter comprising:a primary winding;
a secondary winding magnetically coupled to the primary winding and electrically coupled to an output rectifier, and an output terminal;
a resonant capacitor coupled in series with the primary winding;
a main switch configured to switch on to energize the primary winding and resonant capacitor from a DC voltage bus and to switch off to transfer energy stored in the primary winding to the secondary winding;
an auxiliary switch configured to switch on during an off time of the main switch thereby allowing a resonant current to circulate through the primary winding and the resonant capacitor; and
a control circuit configured to:
vary a duty cycle of the main switch and the auxiliary switch to produce a desired voltage at the output terminal; and
vary a switching frequency of the main switch and the auxiliary switch responsive to a change in output load on the primary resonant flyback converter in combination with at least one of an input voltage into the primary resonant flyback converter and a DC bus voltage of the primary resonant flyback converter.

US Pat. No. 10,170,973

SYNCHRONOUS RECTIFIER CIRCUIT AND SWITCHING POWER SUPPLY APPARATUS

FUJITSU LIMITED, Kawasak...

1. A synchronous rectifier circuit used in a switching power supply apparatus that performs synchronous rectification, the synchronous rectifier circuit comprising:a transistor configured to perform switching operation in accordance with a control voltage applied to a first terminal; and
a control circuit configured to include a second terminal and apply the control voltage to the first terminal, the second terminal being connected to a capacitor which stores electric charge to be supplied to the first terminal and being applied with a first direct-current voltage obtained through synchronous rectification and equal to or smaller than a withstand voltage of a gate of the transistor as well as equal to or larger than a threshold voltage of the transistor, a maximum value of the control voltage being the first direct-current voltage.

US Pat. No. 10,170,972

HALBACH ARRAY AND MAGNETIC SUSPENSION DAMPER USING SAME

SHANGHAI MICRO ELECTRONIC...

1. A Halbach magnetic array, comprising a plurality of first and second magnetic units alternately arranged in a width direction of the array, wherein:each of the plurality of first magnetic units comprises a plurality of first magnetic groups and first magnetic columns alternately arranged in a length direction of the array, each of the plurality of first magnetic groups includes four first magnetic bars arranged in a 2*2 matrix;
each of the plurality of second magnetic units comprises a plurality of second magnetic groups and second magnetic columns alternately arranged in the length direction of the array, each of the plurality of second magnetic groups includes four second magnetic bars arranged in a 2*2 matrix;
each of the plurality of first magnetic columns is magnetized in a height direction of the array, and each of the plurality of second magnetic columns is magnetized in a direction opposite to the height direction of the array.

US Pat. No. 10,170,971

DUAL POLE DUAL BUCKING MAGNET LINEAR ACTUATOR

Oracle International Corp...

1. A linear actuator comprising:a magnet assembly, the magnet assembly comprising:
a central magnet comprising a north pole and a south pole;
a pair of bucking magnets disposed on opposite ends of the central magnet, the pair of bucking magnets comprising a first bucking magnet and a second bucking magnet;
wherein the first bucking magnet is disposed adjacent to the central magnet such that a north pole of the first bucking magnet faces the north pole of the central magnet;
wherein the second bucking magnet is disposed adjacent to the central magnet such that a south pole of the second bucking magnet faces the south pole of the central magnet;
a coil-and-housing assembly, the coil-and-housing assembly comprising:
first coil portion disposed around a first portion of the central magnet and at least a portion of the first bucking magnet;
a second coil portion disposed around a second portion of the central magnet and at least a portion of the second bucking magnet;
a housing disposed around both the first coil portion and the second coil portion, the housing comprising (a) an inner wall facing the first coil portion and the second coil portion and (b) an outer wall;
wherein a current flowing in the first coil portion is in an opposite direction of a current flowing in the second coil portion.

US Pat. No. 10,170,970

STEPPER MOTOR

SANYO DENKI CO., LTD., T...

1. A stepper motor comprising:a rotor including a rotor core and a permanent magnet, the rotor core including a plurality of teeth; and
a stator arranged around the rotor while being spaced apart from the rotor and including eight magnetic poles, each of the magnetic poles including a plurality of teeth and projecting toward the rotor, wherein
a winding is wound around every other magnetic poles, and
a phase of the teeth of a pair of magnetic poles opposing each other and having no winding therearound is shifted by 180 degrees from a phase of the teeth of other pair of magnetic poles opposing each other and having no winding therearound.

US Pat. No. 10,170,968

VIBRATION MOTOR

AAC TECHNOLOGIES PTE. LTD...

1. A vibration motor, comprising:a housing having a receiving space;
a vibration unit accommodated in the receiving space, the vibration unit including a main weight, a main pole plate, a main magnet carried by the main pole plate, an auxiliary weight, an auxiliary pole plate, and an auxiliary magnet carried by the auxiliary pole plate, the main weight comprising a first weight, and a second weight opposed to and apart from the first weight;
a plurality of elastic members suspending the vibration unit in the receiving space; wherein
the main magnet is sandwiched between the first and second weights, and two ends of the main pole plate are respectively connected to the first weight and the second weight.

US Pat. No. 10,170,967

VIBRATION MOTOR

AAC TECHNOLOGIES PTE. LTD...

1. A vibration motor comprising:a housing;
an elastic connecting piece accommodated in the housing;
a fixed component;
a vibrating component suspended in the housing by the elastic connecting piece;
one of the fixed component and the vibrating component including a coil, and the other one of the fixed component and the vibrating component including a magnet; and
a damping piece integrated with the elastic connecting piece, wherein the elastic connecting piece comprises a first connecting part connecting with the vibrating component, a second connecting part connecting with the housing, and a middle connecting part connecting the first connecting part with the second connecting part, the damping piece is coated in a periphery of the middle connecting part.

US Pat. No. 10,170,966

VIBRATION MOTOR

AAC TECHNOLOGIES PTE. LTD...

1. A vibration motor, comprising:a housing forming an accommodation space, the housing including a first side wall extending along a vibration direction of the vibration motor and a second side wall connecting with the first side wall and extending along a direction vertical to vibration direction;
a vibration system accommodated in the accommodation space, the vibration system having an end surface arranged opposite to the second side wall;
an elastic part suspending the vibration system in the accommodation space elastically, the elastic part comprising a fixation portion connected with the end surface of the vibration system, and an elastic portion extending from two ends of the fixation portion for providing restoring force to the vibration system, wherein
the elastic portion includes a hindering portion for baffling the vibration system from vibration in the vibration direction;
the elastic portion includes a first connecting portion extending from the fixation portion, an abutting portion extending from the first connecting portion, a second connecting portion extending from the abutting portion, and an and the end portion extending from the second connecting portion; the end portion is connected with the second side wall fixedly; the abutting portion is propped against the first side wall; and the abutting portion serves as the hindering portion.

US Pat. No. 10,170,965

LINEAR VIBRATION MOTOR

AAC TECHNOLOGIES PTE. LTD...

1. A linear vibration motor, comprising:a housing having an accommodation space;
a vibrator accommodated in the housing;
an elastic part suspending the vibrator in the housing, the elastic part including a fixation part connecting with the vibrator, a connecting part connecting with the housing, and a bending part connecting the fixation part with the connecting part;
a plurality of pre-compressed springs arranged on two sides of the vibrator; one end of the spring being connected with the vibrator, and the other end being connected with the housing, a pre-compression direction of the spring being vertical to a vibration direction of the vibrator;
wherein the vibrator includes a plurality of flutes for receiving the pre-compressed springs.

US Pat. No. 10,170,963

ARMATURE FOR ELECTROMECHANICAL DEVICE WHICH CONVERTS ELECTRICAL ENERGY AND MECHANICAL ENERGY, AND METHOD FOR MANUFACTURING SAME

HAYASHI INDUSTRY CO., LTD...

1. An armature 100 that constitutes an electromechanical device that converts electrical and mechanical energy, the armature comprising:a plurality of distributedly wound coils 10, each coil 10 having a first storage section 11a, a second storage section 11b, and a first coil end 12a and a second coil end 12b that electrically connect the first storage section 11a and the second storage section 11b; and
a stator core or rotor 20 having a plurality of slots 22 in which the coils 10 are stored,
wherein in each coil 10, between a first radial section formed by a winding-start section 10a and a second radial section formed by a winding-end section 10b of windings 10A constituting the coil 10, circumferential lengths of winding lap sections formed by the windings 10A change in a continuous or stepped manner,
a first coil 10, the first storage section 11a and second storage section 11b of which are stored in two slots 22, has a twisted section 10d formed in each of its first coil end 12a and second coil end 12b, whereby sequences within the two slots 22 of the windings 10A constituting the first coil 10 are reversed with respect to each other,
a second coil 10, stored in next two slots 22 after the slots 22 in which the first coil 10 is stored, has twisted sections 10d that are shifted relative to the twisted sections 10d of the first coil 10 by an amount of pitch between the respective slots 22, whereby the twisted sections 10d of the first coil 10 and the second coil 10 become three-dimensionally entwined in a lap winding, and
the lap windings of the twisted sections 10d continue for a third coil 10 and subsequent coils 10, such that the first coil ends 12a and the second coil ends 12b of the coils 10 are continuous without spaces at an end face of the stator core or rotor 20.

US Pat. No. 10,170,962

LAMINATED IRON CORE AND MANUFACTURING METHOD OF LAMINATED IRON CORE

MITSUI HIGH-TEC, INC., F...

1. A laminated iron core comprising:a plurality of laminated iron core pieces, each iron core piece formed and blanked from a strip material; and
a plurality of coupling parts including through holes or recesses formed in a circumferential direction of the plurality of laminated iron core pieces so as to communicate in a lamination direction of the plurality of laminated iron core pieces, wherein
the coupling parts are filled with resins to mutually couple the iron core pieces adjacent in the lamination direction, and
the laminated iron core satisfies the following formula:
(T×S)/?>{(4×E×?×w×t3)/L3}×n,
where T is a strength (N/mm2) of the resin; S is a cross-sectional area (mm2) of the coupling part or the resin; E is a Young's modulus (N/mm2) of the strip material; ? is a distortion amount (mm) of the iron core piece; w is a width (mm) of the iron core piece in a radial direction; t is a plate thickness (mm) of the iron core piece; n is the number of laminated iron core pieces; L is a distance (mm) between the coupling parts adjacent in the circumferential direction; and ? is a safety factor greater than 1 and less than or equal to 3.

US Pat. No. 10,170,960

ENERGY HARVESTING SYSTEM

1. An energy harvesting system for converting kinetic energy to electrical power, the energy harvesting system comprising:a) an intake energy device comprising a housing and a plurality of fins, wherein the fins are positioned on an inner surface of the housing for receiving exhaust air and generating a vortex;
b) an impeller positioned proximal to an inlet of a compressor and in fluid communication with the intake energy device, the impeller configured to receive the generated vortex, the impeller has an impeller rotational axis and directs the exhaust air to flow radially outwardly from an axis defined by the impeller rotational axis of the impeller, wherein the generated vortex rotates the impeller; and
c) a generator rotatably connected to the impeller, wherein the generator is electrically connected to a regulating circuit;
wherein the inlet to the compressor is mounted radially relative to the impeller to receive the exhaust air from the impeller.

US Pat. No. 10,170,959

ELECTRICAL MACHINES AND METHODS OF ASSEMBLING THE SAME

Regal Beloit America, Inc...

1. A motor having an axis of rotation, said motor comprising:a housing having a first end cap and an opposite second end cap, wherein said first end cap and said second end cap define an internal cavity;
a first shaft coupled to said housing;
a second shaft rotationally coupled to said first shaft;
a stator coupled to said second end cap and positioned within said internal cavity, said stator comprising an outer circumferential surface and an inner circumferential surface, said inner circumferential surface defining a stator bore around the axis of rotation;
a gearbox coupled to said first shaft and to said second shaft and positioned within said stator bore within said internal cavity, said gearbox comprising a planetary gear system comprising a sun gear, a ring gear, and a plurality of planet gears, said ring gear coupled directly to said second end cap, said gearbox further comprising a fastener extending through at least one planet gear of said plurality of planet gears and said second shaft such that said plurality of planet gears are rotationally coupled to said second shaft; and
a rotor coupled directly to said first shaft and positioned within said internal cavity between said first end cap and said ring gear, said rotor configured to rotate said first shaft, wherein said rotor is offset from said stator in an axial direction.

US Pat. No. 10,170,958

BELT PULLEY ARRANGEMENT FOR A BELT DRIVE FOR DRIVING AUXILIARY UNITS OF A MOTOR VEHICLE, AND A METHOD FOR DRIVING A MOTOR VEHICLE AUXILIARY UNIT THAT IS CONNECTED BY MEANS OF A BELT PULLEY ARRANGEMENT

1. A belt pulley arrangement for a belt drive for driving auxiliary units in a motor vehicle, comprisinga belt pulley for introducing a torque that is provided by a traction mechanism,
a driven shaft for driving an auxiliary unit,
an electric machine for transferring torque between the belt pulley and the driven shaft, wherein the electric machine has a rotor connected to the belt pulley and a stator connected to the driven shaft, wherein the electric machine has an electrical connection to an electrical energy source for accelerating the driven shaft and an electrical energy sink for braking the driven shaft,
a first rotational speed measurement device that detects a time curve of a rotational speed of the belt pulley and a second rotational speed measurement device that detects a time curve of a rotational speed of the driven shaft, and
a controller connected to at least one of the electrical energy source or the electrical energy sink that is configured to control the time curve of the rotational speed of the driven shaft through a time limited electrical connection of at least one of the energy source or energy sink in reaction to at least one of the detected time curves.

US Pat. No. 10,170,957

CONTROLLING DEVICE INTEGRATED ROTATING ELECTRIC MACHINE

Mitsubishi Electric Corpo...

1. A controlling device integrated rotating electric machine comprising:a rotating electric machine's main body having a rotor winding and a stator winding,
a power converter circuit connected to the rotor winding and the stator winding and having a control board, a power module and a smoothing condenser,
a heat sink attached to a rear side of the rotating electric machine's main body and having heat radiating fins formed on a front side,
a case fixed to the rear side of the heat sink, the case containing the control board and the power module of the power converter circuit,
a container portion extending outward towards a front side from the case, and
a sealing resin body sealing the control board and the power module contained in the case,
wherein the smoothing condenser of the power converter circuit is contained in the container portion.

US Pat. No. 10,170,929

POWER NODE COMMUNICATION FOR DEVICE DETECTION AND CONTROL

Analog Devices Global, H...

1. An electronic circuit, comprising:a source circuit, comprising:
a direct current (DC) output terminal;
a current limiting circuit; and
a source control circuit configured to provide a current-limited DC output voltage to the DC output terminal using the current limiting circuit and configured to monitor the current-limited DC output voltage to detect a coded authentication signal generated by a load circuit and imposed at the DC output terminal by the load circuit, and in response to detecting the coded authentication signal imposed by the load circuit, the source control circuit configured to bypass the current limiting circuit.

US Pat. No. 10,170,918

ELECTRONIC DEVICE WIRELESS CHARGING SYSTEM

APPLE INC., Cupertino, C...

1. An electronic device, comprising:a battery; and
a wireless charging system in electronic communication with the battery, the wireless charging system configured to:
inductively couple to a wireless charging device;
predict an event time at which an event of the electronic device will occur;
determine a charge time at which charging should commence such that the battery reaches a threshold charge value at a threshold time that is prior to or substantially the same as the event time; and
initiate charging of the battery at the charge time.

US Pat. No. 10,170,916

ENERGY STORAGE DEVICE, POWER MANAGEMENT DEVICE, MOBILE TERMINAL AND METHOD FOR OPERATING THE SAME

LG ELECTRONICS INC., Seo...

1. An energy storage device comprising:at least one battery pack;
a communication module connected to the at least one battery pack, and configured to transmit power-on information or energy storage amount information to a power management device and to receive a charge command or a discharge command from the power management device;
a connector configured to receive alternating current (AC) power, supplied to an internal power network through a photovoltaic module, from the internal power network based on the charge command or to output AC power to the internal power network based on the discharge command; and
a power converter disposed between the connector and the at least one battery pack, and configured to, when the charge command is received from the power management device, convert the AC power from the internal power network into direct current (DC) power based on the charge command, or, when the discharge command is received from the power management device, convert DC power stored in the at least one battery pack into AC power based on the discharge command,
wherein the communication module transmits a pairing request signal as the power-on information to the power management device when the energy storage device is powered on, and then receives a pairing response signal including information about a radio channel allocated by the power management device from the power management device, and performs wireless data communication with the power management device over a radio channel different from that of another energy storage device, and
wherein after paring completion, the communication module receives the charge command or the discharge command from the power management device, and transmits energy storage amount information of energy stored in the at least one battery pack to the power management device.

US Pat. No. 10,170,915

ENERGY MANAGEMENT SYSTEM, ENERGY MANAGEMENT METHOD AND COMPUTER PROGRAM

SUMITOMO ELECTRIC INDUSTR...

1. A non-transitory computer readable storage medium storing a computer program for causing a computer to operate as an energy management system for managing an operation state of an electric power device including a storage battery connected to a power grid, the computer program comprising:a first step of acquiring static parameters to be used in controlling the electric power device; and
a second step of controlling the electric power device based on the acquired static parameters, wherein
the static parameters acquired in the first step are commonly used irrespective of whether the storage battery is circulation type or non-circulation type, and the static parameters are at least five types of parameters including:
a storage battery capacity, being an energy capacity of the storage battery that can be delivered from a fully charged state;
dischargeable power, being a limit value of power that the storage battery can discharge;
chargeable power, being a limit value of power that the storage battery can be charged;
discharge efficiency, being a proportion of output power relative to stored power when the storage battery discharges; and
charge efficiency, being a proportion of stored power relative to input power when the storage battery is charged.

US Pat. No. 10,170,914

VOLTAGE SOURCE CONVERTER (VSC) CONTROL SYSTEM WITH ACTIVE DAMPING

ABB SCHWEIZ AG, Baden (C...

1. A Voltage Source Converter control system for active damping of a resonance oscillation in a Voltage Source Converter (VSC), the resonance oscillation having a frequency which is above a synchronous frequency but less than two times said synchronous frequency, the control system comprising:a first Phase-Locked Loop (PLL) having a first PLL controller; and
a second PLL having a second PLL controller, the second PLL controller having a gain which is lower than a gain of the first PLL controller,
wherein the control system is arranged such that an imaginary part of an active damping signal is obtainable from the second PLL; and
wherein the second PLL is configured for having a closed-loop bandwidth which is less than the frequency of the resonance oscillation to be dampened in a synchronous dq frame.

US Pat. No. 10,170,913

STATIC SYNCHRONOUS COMPENSATOR DEVICE AND RELATED METHOD OF PHASE BALANCING A THREE-PHASE POWER SYSTEM

Mitsubishi Electric Power...

1. A static synchronous compensator device connected between a source and a load of a three-phase power system, comprising:a main feedback line configured to provide a main feedback signal from lines between the source and the load;
a mixer configured to mix the main feedback signal with a balance function to generate a balanced signal;
a signal controller configured to convert the balanced signal to a controlled signal;
a gain circuit configured to multiply the controlled signal by ?1 and to perform proportional gain and integral gain (P & I) processing on the controlled signal to generate an intermediate correction signal; and
a pulse width modulator configured to apply a pulse width modulation pattern to modulate the voltage source inverter to generate an AC waveform that is applied to the lines between the source and the load.

US Pat. No. 10,170,912

DYNAMIC HYBRID CONTROL

Kongsberg Maritime AS, K...

1. A system for controlling a power plant in a marine vessel, the power plant comprising;at least one switchboard including at least one switching device, and at least one consumer; and
at least one power generator supplying electrical energy to the at least one switchboard; and
at least one energy storage device coupled to the switchboard capable of storing excess energy from the switchboard, and capable of sourcing the stored energy through the switchboard to the at least one consumer;
wherein the at least one power generator, the at least one energy storage device, and the at least one consumer are coupled to a Dynamic Hybrid Control (DHC) unit, the control unit controlling the flow of energy on the at least one switchboard;
the DHC unit further comprising;
measurement means for monitoring predetermined power plant and vessel related parameters; and
computational means for computing and predicting power and energy requirements in the power plant for varying time spans into the future, based upon data including, the parameters monitored by the measurement means, pre-determined models, and expected energy flow trends related to the at least one power generator, the at least one energy storage element, and the at least one consumer,
wherein the system utilizes the power and energy requirements predicted by the computational means for pre-planning and allocating of power and energy between the at least one power generator, the at least one energy storage element and the at least one consumer for minimizing transients, including voltage, frequency variations in the power plant and load variations on the at least one power generator due to the transients; and,
wherein the system transmits feedforward signals for functions including, the prediction, the pre-planning and the allocation; the feedforward signals including,
power demand;
adapting energy storage devices for handling the transients;
adapting set-point of the at least one power generator; and setting load limitation on the at least one consumer.

US Pat. No. 10,170,911

PROVIDING PHASE SYNCHRONIZATION AND HARMONIC HARVESTING

Veritone Alpha, Inc., Co...

7. A system for reducing one or more harmonics in a high current signal, the system comprising:a step-down converter that uses the high current input signal to generate a low current input signal, wherein a current of the low current input signal is less than a current of the high current input signal;
a harmonic harvester system that includes one or more harmonic harvesters, wherein each harmonic harvester in operation uses one or more op amps to produce a damping signal that at least reduces one harmonic in the high current input signal, wherein the harmonic harvester system combines each damping signal produced by each harmonic harvester into a low current filtering signal, and wherein at least one harmonic harvester in operation satisfies a second-order differential equation with a transfer function given by:

wherein ? represents a harmonic to be reduced by the at least one harmonic harvester, wherein a value for k is chosen based on a voltage of the harmonic to be reduced, and wherein a value for ? is chosen to substantially prevent overshoot of the low current damping signal produced by the at least one harmonic harvester; and
a step-up converter that uses the low current filtering signal to generate a high current filtering signal, wherein a current of the low current filtering signal is less than a current of the high current filtering signal.

US Pat. No. 10,170,909

CONVERTER AND PHOTOVOLTAIC GENERATION SYSTEMS WITH CONVERTER

TAIYO YUDEN CO., LTD., T...

1. A converter for use in a distributed power system for stepping up or down a voltage of a power source connected thereto, the converter being a local converter directly attached to the power source, the converter comprising:a step up/down circuit that directly receives said voltage, steps up or steps down said voltage from the power source, and then outputs said stepped up/down voltage;
a control circuit directly connected to the step up/down circuit to direct said voltage from the power source and transmits a control signal for stepping up or stepping down said voltage to said step up/down circuit; and
a frontend circuit that communicates with another converter attached to another power source in the distributed power system when said another power source with said another converter is connected to the distributed power system,
wherein said control circuit generates an identification signal that identifies said converter and transmits said identification signal through the frontend circuit, and said control circuit is configured to receive an identification signal from said another converter through the frontend circuit without going through a central control system when said another power source with said another converter is connected to the distributed power system so as to detect the presence of said another converter without using the central control system.

US Pat. No. 10,170,908

PORTABLE DEVICE CONTROL AND MANAGEMENT

INTERNATIONAL BUSINESS MA...

1. An apparatus for managing and distributing battery power charge, comprising:multiple electronic devices each having at least one electronic device battery in need of charging;
a computing device having a computing device battery;
a signal receiving component within said computing device comprises multiple ports such that:
the signal receiving component receives at least input battery signal data from the multiple electronic devices, and
the signal receiving component transfers an allocated amount of battery power to each of the multiple electronic devices,
the input battery signal data including battery power level data of each electronic device battery in need of charging;
a monitoring component within said computing device continuously monitoring and receiving the input battery signal data from the signal receiving component;
a controller within said computing device receiving and analyzing the input battery signal data to determine, based on the battery power level data, the allocated amount of battery power charge required for charging each said electronic device battery to a desired battery charge level; and
a charge distribution unit within the computing device receiving each allocated amount of battery power charge, the computing device via the charge distribution unit transferring each allocated amount of battery power charge from the computing device battery to each electronic device battery of the multiple electronic devices to continuously maintain and ensure battery power is available on each electronic device at a time when needed.

US Pat. No. 10,170,907

DYNAMIC ESD PROTECTION SCHEME

Taiwan Semiconductor Manu...

1. An electrostatic discharge (ESD) protection circuit to protect a circuit from an ESD event, the ESD protection circuit comprising:a bipolar junction transistor (BJT) based ESD protection circuit including a field plate overlying a base region of the BJT based ESD protection circuit; and
a dynamic field plate bias circuit coupled to the field plate of the BJT based ESD protection circuit and configured to provide the field plate a field plate bias at transient different from a field plate bias at a normal operation.

US Pat. No. 10,170,906

SEMICONDUCTOR DEVICE FOR POWER SUPPLY CONTROL

MITSUMI ELECTRIC CO., LTD...

1. A semiconductor device for power supply control, that generates and outputs a driving pulse for controlling turning on or off of a switching element which supplies intermittent current to a primary-side winding wire of a transformer for voltage conversion, by inputting a voltage in proportion to the current flowing in the primary-side winding wire of the transformer and an output voltage detection signal from a secondary side of the transformer, the semiconductor device comprising:an on/off control signal generation circuit which generates a control signal for controlling turning on or off of the switching element;
a current detection terminal to which the voltage in proportion to the current flowing in the primary-side winding wire of the transformer is input;
a pull-up unit comprising a current source circuit, the pull-up unit being provided between the current detection terminal and a terminal to which an internal power supply voltage or a voltage in accordance with the internal power supply voltage is applied; and
a current detection terminal monitoring circuit which determines whether the current detection terminal is open or the transformer is short-circuited by comparing the voltage of the current detection terminal with a predetermined voltage, wherein the current detection terminal monitoring circuit determines that the current detection terminal is open or the transformer is short-circuited when detecting that the voltage of the current detection terminal is higher than the predetermined voltage,
wherein:
when the current detection terminal monitoring circuit has determined that the current detection terminal is open or the transformer is short-circuited, a signal generation operation of the on/off control signal generation circuit is stopped by a signal output from the current detection terminal monitoring circuit.

US Pat. No. 10,170,905

ELECTRONIC SWITCHING AND PROTECTION CIRCUIT WITH WAKEUP FUNCTION

INFINEON TECHNOLOGIES AG,...

1. An electronic circuit, comprising:an electronic switch comprising a load path; and
a control circuit configured to drive the electronic switch,
wherein the control circuit is configured to operate in one of a first operation mode and a second operation mode based at least on a level of a load current of the electronic switch,
wherein in the first operation mode the control circuit is configured to generate a first protection signal based on a current-time-characteristic of the load current and drive the electronic switch based on the first protection signal, and
wherein the control circuit is configured to generate a status signal such that the status signal has a wakeup pulse when the operation mode changes from the second operation mode to the first operation mode and, after the wakeup pulse, a signal level representing a level of the load current.

US Pat. No. 10,170,904

SURGE REDUCTION FILTER

PIVOT ELECTRONICS PTY LTD...

1. A surge reduction filter (SRF) comprising:a cartridge including a cartridge housing and a plurality of contact points;
a first active connection point for connection to an active line of an AC power supply, and a first neutral connection point for connection to a neutral line of the AC power supply, the active and neutral connection points being located to be accessible from outside the cartridge;
a first fuse and a first surge protection element electrically connected in series between the first active connection point and the first neutral connection point;
a status circuit to monitor the first surge protection element;
an indicator electrically connected to the status circuit to indicate at least a normal status and a fault status of the first surge protection element, the status circuit detecting a change in voltage at a point between the first fuse and the first surge protection element and creating a fault indication when a voltage change is detected due to the first fuse operating;
a cartridge tray into which the cartridge is insertable;
a plurality of connectors projecting from a base of the cartridge tray;
a plurality of co-operating connectors projecting from the cartridge and associated with the plurality of contact points of the cartridge, wherein the plurality of co-operating connectors co-operate with the plurality of connectors of the base to connect the status circuit to an external circuit comprising the AC supply, and wherein each of the active line and the neutral line of the AC power supply is a single piece of solid metal conductor with no intermediate joins or connections and being routed under the tray.

US Pat. No. 10,170,901

STACKED BUS ASSEMBLY WITH STEPPED PROFILE

Eaton Intelligent Power L...

1. A bus bar assembly, the bus bar assembly comprising:a stack of bus bars configured to be attached to a surface and insulated from one another, wherein the bus bars have aligned longitudinal centerlines and respective different widths in a direction perpendicular to the longitudinal centerlines and parallel to the surface that decrease along a direction perpendicular to the surface, wherein the stack of bus bars comprises:
a first bus bar having a first width;
a second bus bar overlying the first bus bar and having a second width less than the first width; and
a third bus bar overlying the second bus bar and having a third width less than the second width.

US Pat. No. 10,170,900

ELECTRICAL CONNECTION BOX

AutoNetworks Technologies...

1. An electrical connection box comprising:a bus bar;
a case to which the bus bar is fixed;
a terminal that is connected to the bus bar;
a fixing member that fixes a connection portion at which the terminal and the bus bar are connected to each other; and
a base member that holds the fixing member, the base member disposed on a portion of the case and underneath the connection portion;
wherein the fixing member and the base member are disposed at a position at which the fixing member and the base member overlap the connection portion of the bus bar, and when the connection portion at which the terminal and the bus bar are connected to each other is fixed, the base member moves in a direction in which the base member comes into contact with the bus bar, wherein an under surface of the base member is spaced apart and free from the portion of the case.

US Pat. No. 10,170,899

METHOD FOR CONNECTING AT LEAST TWO ELECTRIC CABLES AND CONNECTION DEVICE, KIT, ELECTRIC MACHINE AND ASSOCIATED VEHICLE

1. A connecting device including electric cables connected to an electric machine of a vehicle, said connecting device comprising:at least two contact elements;
a housing having a first housing wall provided with at least two first openings for allowing passage of the cables in a first direction and in a straight line within the housing to meet the contact elements for electrical connection therewith in one-to-one correspondence, and a second housing wall provided with at least two second openings for allowing passage of the cables in a second direction oriented in a straight line within the housing;
wherein only one of the cables directly meets one of the contact elements for electrical connection therewith, while a conductor bar electrically connects the other one of the cables to the other one of the contact elements; and
an isolating support provided in the housing,
said conductor bar being placed on the isolating support and on the other one of the contact elements and one side of the conductor bar connected with the other one of the contact elements, and the other one of the cables being attached to the conductor bar to establish electrical contact via the conductor bar,
wherein the electric cables are connected to the electric machine of the vehicle.

US Pat. No. 10,170,898

SIGNAL LEAKAGE PROOF HOUSING FOR SIGNAL DISTRIBUTORS

Signal Cable System Co., ...

1. A signal leakage proof housing for signal distributors, comprising:a metal case, comprising:
a plurality of signal connection terminals;
a circumferential side wall, comprising:
a top surface, comprising:
a plurality of fixing protrusions arranged at intervals on and around the top surface;
at least one rib on and around the top surface; and
a metal cover plate comprising:
a bottom surface, comprising;
a plurality of fixing holes on and around the bottom surface; wherein,
when the metal case and the metal cover plate are assembled together, the plurality of fixing protrusions each respectively pass through the corresponding fixing holes and fix with each other; wherein,
each one of the at least one rib is in direct contact with the bottom surface of the metal cover plate.

US Pat. No. 10,170,897

WIRE HARNESS EQUIPPED WITH PROTECTOR

SUMITOMO WIRING SYSTEMS, ...

1. A protector-equipped wire harness comprising,an electrical wire;
a protector that includes a plate-shaped portion, a slide supporting portion that is formed so as to extend inward in a first direction from one edge portion of the plate-shaped portion, and a receiver that is provided on a far side with respect to the slide supporting portion, the protector being provided so as to cover at least a portion of an outer circumferential surface of the electrical wire; and
an attachment member that includes a band that can be wound around the electrical wire, and a band lock portion that includes a slidable portion that is supported by the slide supporting portion so as to be slidable in the first direction, the band lock portion keeping the band in a state of being wound around the electrical wire,
wherein the protector and the attachment member are fixed to each other in a state where the band lock portion of the attachment member is in contact with the receiver, and
the protector includes a retaining protrusion that is locked to the band lock portion from a side to prevent the slidable portion from coming loose from the slide supporting portion in a state where the band lock portion is in contact with the receiver.

US Pat. No. 10,170,896

ENCLOSURE, AND WINDOW ASSEMBLY AND ASSEMBLING METHOD THEREFOR

EATON INTELLIGENT POWER L...

1. A window assembly for an enclosure, said window assembly comprising:a cover member;
a first frame member coupled to said cover member;
a second frame member coupled to said cover member; and
a window member coupled to and disposed between said cover member and said first frame member,
wherein said cover member is disposed between said second frame member and said window member
wherein said window assembly further comprises a number of elements extending through said cover member in order to couple said cover member, said first frame member, said second frame member, and said window member together.

US Pat. No. 10,170,895

CORONA IGNITION WITH SELF-TUNING POWER AMPLIFIER

Tenneco Inc., Lake Fores...

1. A power amplifier circuit for a corona ignition system, comprising:an RF transformer with a primary winding and a secondary winding, the primary winding and the secondary winding being wound around a magnetic core;
an inductor and capacitor connected to one end of the secondary winding; and
a current sensor connected to another end of the secondary winding, wherein
current through the secondary winding generates a magnetic flux in the core in opposing directions.

US Pat. No. 10,170,894

MULTIPOINT IGNITION DEVICE AND MULTIPOINT IGNITION ENGINE

Miyama, Inc., Nagano-shi...

1. A multipoint ignition device for igniting an air-fuel mixture in a combustion chamber of an engine, comprising:an insulating member formed in an annular shape such that an inner periphery thereof faces the combustion chamber; and
a plurality of electrodes held on the insulating member so as to form a plurality of ignition gaps in a circumferential direction inside the combustion chamber,
wherein the insulating member includes a plurality of divided insulating members formed in divided form, and
the divided insulating member close to an intake valve of the engine has a higher thermal conductivity than the divided insulating member close to an exhaust valve of the engine.

US Pat. No. 10,170,892

LASER UNIT AND LASER DEVICE

AMADA MIYACHI CO., LTD., ...

1. A laser unit comprising:a first stacked laser beam creation unit having a plurality of first single emitter laser diodes (LDs) disposed in a first direction at a plurality of different height positions with a predetermined pitch, each of the plurality of first single emitter LDs emitting a first single laser beam having a wavelength identical or proximate to a standard wavelength, a plurality of first single laser beams arranged in a stacked form and not contacting each other to create a first stacked laser beam bundle being shifted to one side from a predetermined center line (N) and propagating in parallel to the center line (N);
a second stacked laser beam creation unit disposed adjacent to the first stacked laser beam creation unit and having a plurality of second single emitter LDs disposed in the first direction at the plurality of different height positions with the predetermined pitch, each of the plurality of second single emitter LDs emitting a second single laser beam having a wavelength identical or proximate to the standard wavelength, a plurality of second single laser beams arranged in a stacked form and not contacting each other to create a second stacked laser beam bundle being shifted to another side from the center line (N) and propagating in parallel to the center line (N);
a first anamorphic prism that allows the first stacked laser beam bundle from the first stacked laser beam creation unit to pass therethrough, wherein a beam size of individual first single laser beams that form the first stacked laser beam bundle is compressed by a first compression ratio in one of a fast-axis direction and a slow-axis direction, and an optical path of the first stacked laser beam bundle is shifted so as to approach the center line (N); and
a second anamorphic prism that allows the second stacked laser beam bundle from the second stacked laser beam creation unit to pass therethrough, wherein a beam size of the individual second single laser beams that form the second stacked laser beam bundle is compressed by a second compression ratio in the one of the fast-axis direction and the slow-axis direction, and an optical path of the second stacked laser beam bundle is shifted so as to approach the center line (N), wherein
a combined stacked laser beam bundle combining the first stacked laser beam bundle and the second stacked laser beam bundle being arranged in two lines is obtained on a subsequent stage of first and second anamorphic prisms.

US Pat. No. 10,170,891

ALGAINP-BASED SEMICONDUCTOR LASER

USHIO OPTO SEMICONDUCTORS...

1. A semiconductor laser chip comprising:an n-type cladding layer having a composition of (AlxnGa1-xn)0.5In0.5P where 0.9 a p-type cladding layer having a composition of (AlxpGa1-xp)0.5In0.5P where 0.92 an active layer provided between the n-type cladding layer and the p-type cladding layer,
wherein the Al composition ratio xp of the p-type cladding layer and the Al composition ratio xn of the n-type cladding layer satisfies a relationship of xn wherein a difference between the Al composition ratio xp of the p-type cladding layer and the Al composition ratio xn of the n-type cladding layer satisfies a relationship of 0.03<=xp?xn<=0.06.

US Pat. No. 10,170,890

METHOD OF FABRICATING SEMICONDUCTOR OPTICAL DEVICE AND SURFACE-EMITTING SEMICONDUCTOR LASER

SUMITOMO ELECTRIC INDUSTR...

1. A surface-emitting semiconductor laser comprising: a substrate; a first stacked semiconductor layer disposed on the substrate and including a first distributed Bragg reflector; an active layer disposed on the first stacked semiconductor layer; and a second stacked semiconductor layer disposed on the active layer and including a second distributed Bragg reflector; a first electrode; and a second electrode, the substrate, the first and second stacked semiconductor layers and the active layer providing a semiconductor structure with a first structure side, a second structure side opposite to the first structure side, and a side structure surface that extends from the second structure side to the first structure side, the side structure surface having an upper side free of chipping, the first electrode and the second electrode each being provided on the first structure side of the semiconductor structure, the semiconductor structure being formed by:preparing a substrate product that includes a first side and a second side opposite to the first side, the first side including device sections arranged in an array and a street region extending between the device sections, at least one of the device sections including the first and second electrodes and the semiconductor structure for the surface-emitting semiconductor laser;
forming a first mask on the first side of the substrate product, the first mask having a pattern that includes device covering portions covering the respective device sections and an opening defining the device covering portions, the opening being provided in the street region;
etching the substrate product using the first mask so as to form a groove in the street region, the groove defining the device sections;
after removing the first mask, securing the first side of the substrate product to a first support member; and
after securing the first side of the substrate product to the first support member, forming an array of semiconductor chips on the first support member by removing part of the substrate product from the second side until the groove provided in the first side is exposed so as to separate the at least one device section including the first and second electrodes and the semiconductor structure from other device sections to provide the surface-emitting semiconductor laser.

US Pat. No. 10,170,888

DUAL-USE LASER SOURCE COMPRISING A CASCADED ARRAY OF HYBRID DISTRIBUTED FEEDBACK LASERS

Oracle International Corp...

1. A laser source, comprising:a silicon waveguide formed in a silicon layer; and
a cascaded array of hybrid distributed feedback (DFB) lasers formed by locating sections of III-V gain material over the silicon waveguide;
wherein each DFB laser in the cascaded array comprises,
a section of III-V gain material located over the silicon waveguide, wherein the section of III-V gain material includes an active region that generates light, and
a Bragg grating located on the silicon waveguide, wherein the Bragg grating has a resonance frequency within a gain bandwidth of the section of III-V material and is transparent to frequencies that differ from the resonance frequency,
wherein the DFB laser has a hybrid mode that resides partially in the III-V gain material and partially in silicon.

US Pat. No. 10,170,887

SURFACE EMITTING LASER ELEMENT AND ATOMIC OSCILLATOR

RICOH COMPANY, LTD., Tok...

1. A surface emitting laser element comprising:a lower Bragg reflection mirror;
an upper Bragg reflection mirror; and
a resonator region formed between the lower Bragg reflection mirror and the upper Bragg reflection mirror, and including an active layer,
wherein a wavelength adjustment region is formed in the lower Bragg reflection mirror or the upper Bragg reflection mirror,
wherein the wavelength adjustment region includes a second phase adjustment layer, a wavelength adjustment layer and a first phase adjustment layer, arranged in this order from a side where the resonator region is formed,
wherein an optical thickness of the wavelength adjustment region is approximately (2N+1)×?/4, and
wherein the wavelength adjustment layer is formed at a position where an optical distance from an end of the wavelength adjustment region on the side where the resonator region is formed is approximately M×?/2,
where ? is a wavelength of emitted light, M and N are positive integers, and M is less than or equal to N.