US Pat. No. 10,141,339

EMBEDDED SECURITY CIRCUIT FORMED BY DIRECTED SELF-ASSEMBLY

International Business Ma...

1. A method, comprising:defining at least two regions of a circuit structure on a substrate, wherein the at least two regions comprise a security region and a non-security region;
forming a guiding pattern on the substrate, wherein the guiding pattern comprises a plurality of raised features formed within the security and non-security regions, wherein the raised features of the guiding pattern formed within the non-security region are separated by a first distinct width, and wherein the raised features of the guiding pattern formed within the security region are separated by a second distinct width;
depositing a self-assembling material comprising at least one of a block copolymer and a block copolymer/homopolymer combination, within spaces between the raised features of the guiding pattern, wherein the self-assembling material comprises block materials that are configured to assemble into a block pattern with a natural pitch;
annealing the self-assembling material to initiate a self-assembly process directed by the plurality of raised features of the guiding pattern, and form block patterns of the block materials within the spaces between the raised features of the guiding pattern; and
selectively removing one of the block materials of the assembled block patterns to define a pattern of fin structures by the remaining block material in the spaces between the raised features of the guiding pattern;
wherein the pattern of fin structures comprises a pattern of unbroken fin structures within the non-security region, and a pattern of broken fin structures within the security region;
wherein the broken fin structures comprise discontinuous regions that are formed due to a dissimilarity between the second distinct width and the natural pitch of the block materials of the self-assembling material.

US Pat. No. 10,141,338

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

International Business Ma...

1. A FinFET device comprising:a strain relaxation buffer (SRB) substrate;
a set of cut silicon fins on the SRB substrate, each fin in the set of cut silicon fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;
a set of cut silicon germanium fins on the SRB substrate, each fin in the set of silicon germanium fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;
a set of tensile dielectric structures, wherein respective ones of the tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins; and
a set of compressive dielectric structures, wherein respective ones of the compressive dielectric structure bridge between the short vertical faces of respective pairs of the cut silicon germanium fins to maintain compressive strain at the fin ends of the pair of cut silicon germanium fins.

US Pat. No. 10,141,337

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising a silicon semiconductor layer including a first channel formation region;
an insulating layer comprising a first nitride insulating layer and a second nitride insulating layer over the first transistor;
a second transistor comprising an oxide semiconductor layer including a second channel formation region over the insulating layer; and
a third nitride insulating layer over the second transistor,
wherein the second nitride insulating layer is between the first nitride insulating layer and the oxide semiconductor layer,
wherein a density of the second nitride insulating layer is higher than or equal to 2.75 g/cm3, and
wherein a density of the third nitride insulating layer is higher than or equal to 2.75 g/cm3.

US Pat. No. 10,141,336

POWER GATE SWITCHING SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. A power gate switching system, comprising:a first row including a first virtual power line, a first power gate cell and a second power gate cell, wherein the first power gate cell includes a first gate electrode disposed between first and second diffusion regions, and at least one tab, wherein the second power gate cell includes a second gate electrode disposed between third and fourth diffusion regions and does not include a tab; and
a second row including a second virtual power line, a third power gate cell and a fourth power gate cell, wherein the third power gate cell includes a third gate electrode disposed between fifth and sixth diffusion regions, and at least one tab, and the fourth power gate cell includes a fourth gate electrode disposed between seventh and eighth diffusion regions and does not include a tab, and
wherein the fourth power gate cell is connected to the second power gate cell.

US Pat. No. 10,141,335

SEMICONDUCTOR CIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in and end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each of the first-metal structures having at least one adjacent first-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers;
at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit.

US Pat. No. 10,141,334

SEMICONDUCTOR CHIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST-METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each gate structure in the region having a substantially rectangular shape with a width of less than or equal to about 45 nanometers and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate structure positioned thereon, wherein each pair of gate structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers, wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure in the region having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each first-metal structure in the region having at least one adjacent first-metal structure positioned next to each of its sides in accordance with a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers; and
at least six contact structures formed within the region of the semiconductor chip, wherein at least six gate structures within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six contact structures, each of the at least six contact structures having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structures positioned and sized to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein the logic circuit includes electrical connections that collectively include first-metal structures positioned on at least five of the at least eight first-metal gridlines.

US Pat. No. 10,141,333

DOMAIN WALL CONTROL IN FERROELECTRIC DEVICES

International Business Ma...

1. A ferroelectric device comprising:a first electrode comprising one or more electrically conductive layers,
a second electrode comprising one or more electrically conductive layers;
a layer of ferroelectric material disposed between, and in electrical communication with, the first electrode and the second electrode;
wherein at least one of the first electrode and the second electrode comprises a recessed region and the layer of ferroelectric material comprises a corresponding region of increased thickness;
wherein a programming signal that is applied across the first and second electrodes does not change a polarity of a portion of the layer of ferroelectric material that is proximate to the region of increased thickness; and
wherein the programming signal that is applied across the first and second electrodes changes a polarity of one or more other portions of the layer of ferroelectric material.

US Pat. No. 10,141,332

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING HOLE PENETRATING STACK STRUCTURE

SK Hynix Inc., Gyeonggi-...

1. A method for manufacturing a semiconductor device, the method comprising:repeatedly stacking a first material layer and a second material layer to form a first stack structure;
forming a first hole passing through the first stack structure;
forming an overlay measurement pattern in the first hole, wherein the overlay measurement pattern includes a different material from the first material layer and the second material layer;
forming an etch stop layer in the first hole and over the overlay measurement pattern;
repeatedly stacking a third material layer and a fourth material layer over the first stack structure to form a second stack structure; and
forming a second hole passing through the second stack structure to expose the etch stop layer,
wherein the first hole includes an air-gap surrounded by the overlay measurement pattern and disposed below the etch stop layer.

US Pat. No. 10,141,331

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SUPPORT PILLARS UNDERNEATH A RETRO-STEPPED DIELECTRIC MATERIAL AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a memory array region and a terrace region;
memory stack structures extending through the memory array region of the alternating stack, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel contacting an inner sidewall of the respective memory film; and
support pillar structures extending through the terrace region of the alternating stack,
wherein the support pillar structures have different heights from each other;
wherein each of the support pillar structures has a respective topmost surface that is coplanar with a top surface of a respective one of the insulating layers in the alternating stack; and
wherein each of the support pillar structures comprises a dummy vertical semiconductor channel that is identical to the vertical semiconductor channels in material composition.

US Pat. No. 10,141,330

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES, SEMICONDUCTOR DEVICES, AND ELECTRONIC SYSTEMS

Micron Technology, Inc., ...

1. A method of forming a semiconductor device structure, comprising:forming a stack structure comprising stacked tiers, each of the stacked tiers comprising a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure;
forming a patterned hard mask structure over the stack structure;
forming dielectric structures within openings in the patterned hard mask structure;
forming a photoresist structure over the dielectric structures and the patterned hard mask structure;
subjecting the photoresist structure, the dielectric structures, and the stack structure to a series of material removal processes to selectively remove portions of the photoresist structure, portions of the dielectric structures not covered by remaining portions of the photoresist structure, and portions of the stack structure not covered by one or more of the patterned hard mask structure and the remaining portions of the photoresist structure to form apertures extending to different depths within the stack structure;
forming dielectric structures over side surfaces of the stack structure within the apertures, upper surfaces of the dielectric structures substantially coplanar with an upper surface of the patterned hard mask structure; and
forming conductive contact structures longitudinally extending to bottoms of the apertures.

US Pat. No. 10,141,329

METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A method for manufacturing a semiconductor memory device, comprising:forming, in a stacked body including a plurality of first layers and a plurality of second layers each of which is provided between the first layers, a plurality of first holes and a plurality of second holes in which a channel film is to be formed inside the first holes, the first holes and the second holes extending through the stacked body in a stacking direction of the stacked body and being arrayed in a first direction intersecting the stacking direction and in a direction oblique to the first direction;
etching a portion between the second holes next to each other in the stacked body to connect the second holes next to each other in the first direction and the second holes next to each other in the direction oblique to the first direction via the etched portion and form a trench in the stacked body.

US Pat. No. 10,141,328

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) memory device, comprising:a substrate;
a ridge-shaped stack, including a plurality of conductive strips stacked on the substrate along a first direction;
a memory layer, stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight angle with the first direction, and having a first narrow sidewall with a first long side extending along the first direction and a first narrow side extending along the second direction;
a channel layer, stacked on the memory layer along the second direction, the channel layer having a portion recessed in a third direction by an etch back process to form a second narrow sidewall having a second long side extending along the first direction and a second narrow side extending along the second direction, wherein the first narrow sidewall is separated from the second narrow sidewall along the third direction, and the third direction forms a non-straight angle with both the first direction and the second direction; and
a capping layer stacked on the second narrow sidewall along the third direction.

US Pat. No. 10,141,327

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a first insulating layer disposed on a semiconductor substrate;
a first semiconductor layer disposed on the semiconductor substrate;
a plurality of memory cells arranged three-dimensionally above the first insulating layer and disposed above the first semiconductor layer;
a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate;
a second insulating layer covering a side surface of a lowermost layer of the plurality of conductive layers;
an oxide layer disposed on a side surface of the first semiconductor layer and contacting the second insulating layer; and
a high permittivity layer provided between the first insulating layer and the second insulating layer, a permittivity of the high permittivity layer being higher than that of the first insulating layer and the high permittivity layer directly contacting the side surface of the first semiconductor layer.

US Pat. No. 10,141,326

SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a peripheral circuit element provided over a lower substrate;
an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element;
a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and
a plurality of transistors electrically coupling the gate lines to the peripheral circuit element,
the transistors comprising:
a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction;
a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and
gate dielectric layers disposed between the vertical channels and the gate electrode.

US Pat. No. 10,141,325

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising steps of:(a) providing a semiconductor substrate;
(b) forming a first resistor element comprised of polycrystalline silicon in a first region of a main surface of the semiconductor substrate;
(c) ion-implanting a first impurity, which is at least one selected from a group consisting of: a group 14 element, nitrogen, and a group 18 element, into the first resistor element; and
(d) after the step (c), forming an insulating film including a charge storage portion in a second region of the main surface of the semiconductor substrate; which is different from the first region;
(e) ion-implanting a second impurity into a third region of the main surface of the semiconductor substrate, which is different from the first and second regions; and
(f) after the step (e), performing a first heat treatment on the semiconductor substrate so as to activate the second impurity,
wherein, during the step (d), or after the step (d) and before the step (e), a second heat treatment is performed on the semiconductor substrate so as to improve a quality of the insulating film, and
wherein the second heat treatment has a longer duration than the first heat treatment.

US Pat. No. 10,141,324

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a main surface;
a first nonvolatile memory cell and a second nonvolatile memory cell formed on the main surface of the semiconductor substrate;
the first nonvolatile memory cell including a first memory transistor for storing data having a first memory gate electrode and a first select transistor for selecting the first memory transistor having a first select gate electrode; and
the second nonvolatile memory cell including a second memory transistor for storing data having a second memory gate electrode and a second select transistor for selecting the second memory transistor having a second select gate electrode;
wherein the first select gate electrode and the second select gate electrode extend in a first direction so as to be disposed next to each other in a second direction substantially perpendicular to the first direction in a plan view,
wherein the first memory gate electrode extends in the first direction so as to be disposed along a sidewall of the first select gate electrode,
wherein the second memory gate electrode extends in the first direction so as to be disposed along a sidewall of the second select gate electrode,
wherein the first memory gate electrode and the second memory gate electrode are disposed between the first select gate electrode and the second select gate electrode,
wherein the first memory gate electrode has a first contact portion extending in the second direction to provide an electrical contact to a first interconnect,
wherein the second memory gate electrode has a second contact portion extending in the second direction to provide an electrical contact to a second interconnect,
wherein the first contact portion is spaced apart from the second contact portion in the first direction in the plan view, and
wherein a first portion of the first contact portion and a second portion of the second contact portion are overlapped with each other in the second direction in the plan view.

US Pat. No. 10,141,323

NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

16. A non-volatile memory array, comprising:a first pair of memory cell wherein the first pair of memory cell further comprises:
a first MOSFET having a first gate region; and
a second MOSFET having a second gate region; and
a second pair of memory cell adjacent to the first pair of memory cell, wherein the second pair of memory cell includes a third MOSFET having a third gate region and a fourth MOSFET;
wherein the second MOSFET of the first pair of memory cell and third MOSFET of the second pair of memory cell are connected to a same bit line; and
wherein the first gate region and the second gate region of the first pair of memory cell extend over and connect to a first active region providing a first word line and the third gate region of the second pair of memory cell extends over and connects to a second active region providing a second word line different than the first word line.

US Pat. No. 10,141,322

METAL FLOATING GATE COMPOSITE 3D NAND MEMORY DEVICES AND ASSOCIATED METHODS

Intel Corporation, Santa...

1. A method of making a 3D NAND memory structure having improved process margin and enhanced performance, comprising:etching a cell pillar trench into a cell stack substrate having alternating layers of conducting and insulating materials disposed on a select gate source region;
etching a plurality of floating gate recesses into sidewalls of the cell pillar trench at the layers of conductive material;
forming an interpoly dielectric (IPD) layer in the plurality of floating gate recesses;
depositing a metal layer onto the IPD layer in the plurality of floating gate recesses;
depositing a floating gate layer onto the metal layer in the plurality of floating gate recesses to form a plurality of floating gate units having a floating gate core surrounded on at least three sides by the metal layer.

US Pat. No. 10,141,321

METHOD OF FORMING FLASH MEMORY WITH SEPARATE WORDLINE AND ERASE GATES

Silicon Storage Technolog...

1. A method of forming a non-volatile memory cell comprising:forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region there between;
forming a floating gate disposed over and insulated from a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region;
forming a tunnel oxide layer around the sharp edge;
forming an erase gate over and insulated from the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer; and
forming a word line gate disposed over and insulated from a second portion of the channel region which is adjacent to the second region, wherein the forming of the word line gate is entirely performed after the forming of the tunnel oxide layer and the forming of the erase gate.

US Pat. No. 10,141,320

MULTIPLE-BIT ELECTRICAL FUSES

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a nanosheet stack on a semiconductor substrate, the nanosheet stack comprising alternating layers of a first material and a second material on a substrate;
removing portions of the stack to form tapered stack sidewalls, wherein said sidewalls have a taper angle in relation to a horizontal surface of the substrate, the taper angle extending inward from the semiconductor substrate toward an upper surface of the nanosheet stack; and
converting the second material to a resistive material, wherein the layers comprising the resistive material form one or more electrical fuses,
wherein the taper angle sets a different breakdown voltage for each electrical fuse among the one or more electrical fuses.

US Pat. No. 10,141,319

LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A layout pattern of a static random access memory, comprising:a first inverter and a second inverter cross-coupled for data storage, each inverter including a pull-up device (PL) and a pull-down device (PD);
each inverter comprising a step-shaped structure disposed on a substrate, the step-shaped structure comprising a first part and a second part arranged along a first direction, and a bridge part connected to the first part and the second part, the bridge part is arranged along a second direction, wherein the first direction is perpendicular to the second direction, in addition, the first part is disposed at one side of the bridge part, and the second part is disposed at the opposite side of the bridge part along the first direction, and wherein the first part crosses over a first diffusion region, and the second part crosses over a second diffusion region to form the pull-down device (PD), wherein the first part crosses over a third diffusion region to form the pull-up device (PL);
each inverter has an inverter output, the inverter output connecting a first pass gate structure and a second pass gate structure disposed on the substrate, the first pass gate structure and the first part of the step-shaped structure being arranged along a same direction and comprising a same symmetry axis, the second pass gate structure and the second part of the step-shaped structure being arranged along a same direction and comprising a same symmetry axis, wherein the first pass gate structure crosses over the second diffusion region to form a first pass gate device (PG1), and the second pass gate structure crosses over the first diffusion region to form a second pass gate device (PG2), wherein a drain of the PG1 is connected to a drain of the PG2, and the bridge part of each step-shaped structure of each inverter is disposed between the first pass gate structure and the second pass gate structure; and
each inverter output comprising an extending contact structure at least crossing over one of the first diffusion region, the second diffusion region and the third diffusion region.

US Pat. No. 10,141,318

STRUCTURE AND METHOD FOR FINFET SRAM

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:four SRAM cells in four quadrants of a region of the semiconductor device,
wherein the four SRAM cells include FinFET transistors comprising gate features engaging fin active lines,
wherein each of the four SRAM cells includes at least one gate feature overlapping with three or more fin active lines,
wherein the fin active lines of the four SRAM cells have reflection symmetry with respect to an imaginary line dividing the four quadrants along a first direction,
wherein each of the four SRAM cells includes at least one fin active line over a first P-well adjacent one side of an N-well, and at least one fin active line over a second P-well adjacent another side of the N-well, and
wherein two of the four SRAM cells share all the fin active lines over the first and second P-wells.

US Pat. No. 10,141,317

METAL LAYERS FOR A THREE-PORT BIT CELL

QUALCOMM Incorporated, S...

1. A method comprising:patterning a first metal layer at a bit cell;
patterning a second metal layer between the first metal layer and a third metal layer, the second metal layer including two read word lines coupled to the bit cell; and
patterning the third metal layer, the third metal layer including a write word line coupled to the bit cell.

US Pat. No. 10,141,316

SEMICONDUCTOR DEVICE WITH PILLAR AND BACKGROUND PATTERNS AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other;
bit lines on the substrate, the bit lines including bit line contacts on the active regions;
a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, and the plurality of pillar patterns having a non-overlapping relationship with the bit line contacts; and
a background pattern on the substrate, the background pattern being completely peripheral with respect to all the plurality of pillar patterns in the pillar array pattern,
wherein the plurality of pillar patterns includes first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, and
wherein a distance between the background pattern and a most adjacent one of the plurality of pillar patterns is larger than a distance between two adjacent ones of the plurality of pillar patterns.

US Pat. No. 10,141,315

SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:an array of memory cells formed in a semiconductor, the array comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising:
a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, and the buried region is discontinuous along one direction;
wherein said floating body region stores a charge level indicative of a state of the memory cell selected from at least first and second states;
wherein said buried region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said buried region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and
first control circuitry configured to provide electrical signals to said buried region.

US Pat. No. 10,141,314

MEMORIES AND METHODS TO PROVIDE CONFIGURATION INFORMATION TO CONTROLLERS

Micron Technology, Inc., ...

1. A memory system, comprising:a memory controller; and
a memory module coupled to the memory controller, wherein the memory module comprises:
a memory package of a first type, wherein the memory package of the first type includes a first memory die and a second memory die coupled to the first memory die wherein the first memory die and second memory die are separate dies, the memory package of the first type configured to receive an external signal for the second memory die and further configured to couple the external signal to the second memory die through the first memory die; and
a signal presence detect unit including a memory module and configured to receive a configuration signal and to provide configuration data associated with a memory package of a second type to the memory controller in response to the configuration signal, wherein the configuration data includes control signal timings for accessing one or more memory dies in the memory package of the second type, wherein the control signal timings provided from the signal presence detection unit to the memory controller include timing relationships between clock enable, chip select, and on-die termination signals, wherein the memory package of the second type is configured to provide the external signal directly to a respective second memory die, the memory controller being configured to interface with the memory package of the first type utilizing the control signal timings of the second type, based, at least in part, on the configuration data of the second type and further configured to provide the external signal for the second memory die to the memory package of the first type.

US Pat. No. 10,141,313

FINFET WITH UNIFORM SHALLOW TRENCH ISOLATION RECESS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a dense region comprising at least two fins on a substrate, the dense region being arranged adjacent to an isolated region without fins;
depositing an oxide on the at least two fins of the dense region and on the isolated region of the substrate;
removing a portion of the oxide, removing more oxide in the isolated region, such that polishing results in forming a non-uniform oxide surface; and
performing an etch process to further recess the oxide in the dense region and the isolated region, such that a thickness of the oxide in the dense region and the isolated region is substantially uniform.

US Pat. No. 10,141,312

SEMICONDUCTOR DEVICES INCLUDING INSULATING MATERIALS IN FINS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a first substrate region and a second substrate region;
a first fin protruding from the first substrate region and comprising a first recess;
a first isolation layer in the first recess;
a first source/drain region on the first fin adjacent the first recess;
a second fin protruding from the second substrate region and comprising a second recess;
a second isolation layer in the second recess; and
a second source/drain region on the second fin adjacent the second recess,
wherein a bottom surface of the first recess is lower than a bottom surface of the second recess,
wherein an upper surface of the first isolation layer is coplanar with, or protrudes beyond, an upper surface of the first fin, and
wherein an upper surface of the second isolation layer is coplanar with, or protrudes beyond, an upper surface of the second fin.

US Pat. No. 10,141,311

TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE

INTEL CORPORATION, Santa...

1. An integrated circuit including at least one transistor device, the integrated circuit comprising:a first fin above and native to a substrate, the first fin having a channel region, wherein the first fin includes a first width (W1) in a sub-channel region below the channel region and a second width (W2) in the channel region, W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2; and
a second fin above and native to the substrate, the second fin having a channel region, wherein the second fin includes a third width (W3) in the channel region, and W3 is different from W2.

US Pat. No. 10,141,310

SHORT CHANNEL EFFECT SUPPRESSION

TAIWAN SEMICONDUCTOR MANU...

18. A semiconductor device comprising:a p-type region comprising:
a first set of fin structures, the fin structures of the first set varying in size, the fin structures of the first set each comprising:
a bottommost portion;
a channel portion disposed above the bottommost portion and having an n-type dopant at a first concentration; and
an epitaxially grown anti-punch-through feature extending from the bottommost portion to the channel portion and having an n-type dopant throughout at a second concentration greater than the first concentration, wherein the anti-punch-through feature of a first fin structure of the first set extends to a different depth than the anti-punch-through feature of a second fin structure of the first set;
a plurality of p-type transistors formed on the fin structures of the first set, the p-type transistors having varying dimensions; and
a number of isolation features positioned such that a top surface of the isolation features is below a first portion of each of the anti-punch-through features and above a second portion of each of the anti-punch-through features.

US Pat. No. 10,141,309

TIGHT PITCH INVERTER USING VERTICAL TRANSISTORS

International Business Ma...

1. A fabrication method for forming an inverter structure, comprising:obtaining a monolithic structure including a p-type region and an n-type region, the p-type region being electrically isolated from the n-type region;
forming a dummy gate on the monolithic structure;
epitaxially forming first and second semiconductor fins on the monolithic structure and within the dummy gate, the first semiconductor fin being formed on the p-type region and the second semiconductor fin being formed on the n-type region;
forming a first drain region on the first semiconductor fin and above the dummy gate, the first drain region having p-type conductivity;
forming a second drain region on the second semiconductor fin and above the dummy gate, the second drain region having n-type conductivity, and
replacing the dummy gate with a gate dielectric layer and an electrically conductive gate electrode on the gate dielectric layer such that the gate dielectric layer adjoins the first and second semiconductor fins and the gate electrode adjoins the gate dielectric layer, and further such that:
the p-type region, the first semiconductor fin, the first drain region, and the gate electrode form a vertical, p-type field-effect transistor,
the n-type region, the second semiconductor fin, the second drain region, and the gate electrode form a vertical, n-type field-effect transistor, and
the gate electrode is shared by the p-type field-effect transistor and the n-type field-effect transistor.

US Pat. No. 10,141,308

LOW RESISTANCE SOURCE/DRAIN CONTACTS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES

International Business Ma...

1. A semiconductor device, comprising:source/drain regions (S/D) in an n-type field effect transistor (NFET) region and in a p-type field effect transistor (PFET) region;
contacts formed to recrystallized layers of the S/D regions in the NFET and PFET regions; and
metastable recrystallized interface layers formed between the contacts and the S/D regions in respective NFET and PFET regions, the recrystallized interface layers including an alloy element concentration that exceeds solubility with a respective material of the S/D regions in the respective NFET and PFET regions.

US Pat. No. 10,141,307

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:an isolation insulating layer disposed over a substrate;
a first fin structure and a second fin structure, both disposed over the substrate, the first and second fin structures extending in a first direction in plan view, upper portions of the first and second fin structures being exposed from the isolation insulating layer;
a first gate structure disposed over parts of the first and second fin structures, the first gate structure extending in a second direction crossing the first direction;
first fin sidewall spacers covering a lower portion of the exposed first fin structure, and second fin sidewall spacers covering a lower portion of the exposed second fin structure; and
a source/drain structure formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation insulating layer, and wrapping side surfaces and a top surface of each of the exposed first and second fin structures, wherein:
a void is formed between the source/drain structure and the isolation insulating layer,
one of the first fin sidewall spacers and one of the second fin sidewall spacers are disposed in the void, and
an entirety of side surface of the one of the first fin sidewall spacers and an entirety of side surface of the one of the second fin sidewall spacers are exposed in the void.

US Pat. No. 10,141,306

SYSTEMS, METHODS, AND APPARATUS FOR IMPROVED FINFETS

QUALCOMM Incorporated, S...

1. A finFET comprising:a plurality of fins separated from each other to form a plurality of gaps between adjacent fins of the plurality of fins;
an oxide material located in the plurality of gaps, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material; and
wherein the first density is greater than the second density.

US Pat. No. 10,141,305

SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS

QUALCOMM Incorporated, S...

1. A semiconductor device, comprising:a substrate;
a plurality of channel structures disposed over the substrate, the plurality of channel structures of a first field effect transistor (FET);
one or more shallow trench isolation (STI) trenches, each STI trench formed between a corresponding pair of channel structures of the plurality of channel structures and comprising:
a bottom region filled with a lower quality oxide; and
a top region formed above the bottom region and filled with a higher quality oxide;
a gate of the first FET disposed over the plurality of channel structures and the top region of each STI trench of the one or more STI trenches;
a source of the first FET disposed on a first side the plurality of channel structures and the one or more STI trenches; and
a drain of the first FET disposed on a second side of the plurality of channel structures and the one or more STI trenches opposite of the first side,
wherein the top region of each STI trench of the one or more STI trenches is filled with the higher quality oxide such that a void is not formed in the top region, and
wherein the top region of each STI trench of the one or more STI trenches electrically isolates the gate from the source and the drain.

US Pat. No. 10,141,304

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
an upper electrode provided on an upper surface of the semiconductor substrate; and
a lower electrode provided on a lower surface of the semiconductor substrate;
wherein
an anode region and an upper Insulated Gate Bipolar Transistor (IGBT) structure are provided in a range in the semiconductor substrate that is exposed at the upper surface,
a trench is provided in the upper surface,
the anode region is separated from the upper IGBT structure by the trench, the anode region is in contact with the trench, and the upper IGBT structure is in contact with the trench,
the anode region is a p-type region connected to the upper electrode,
the upper IGBT structure includes an n-type emitter region and a p-type body region, the emitter region connected to the upper electrode, and the body region being in contact with the emitter region and connected to the upper electrode,
a gate insulating film and a gate electrode are provided in the trench,
a cathode region and a collector region are provided in a range in the semiconductor substrate that is exposed at the lower surface, the cathode region bordering the collector region at an interface;
the cathode region is an n-type region connected to the lower electrode and provided in at least a part of a region below the anode region,
the collector region is a p-type region connected to the lower electrode, provided in at least a part of a region below the upper IGBT structure, and being in contact with the cathode region,
an n-type drift region is provided between an upper structure including the anode region and the upper IGBT structure and a lower structure including the cathode region and the collector region,
a crystal defect region is provided across a portion of the drift region that is above the cathode region and a portion of the drift region that is above the collector region so that the crystal defect region is provided in a part of the portion of the drift region that is above the collector region,
the crystal defect region having a density of crystal defects higher than a density of crystal defects in a surrounding region of the crystal defect region,
the semiconductor substrate has a dimension that satisfies a relationship of y?0.007x2?1.09x+126 within a range of 165 ?m?x?60 ?m, where x is a number in the unit of ?m and represents a thickness of the semiconductor substrate and y is a number in the unit of ?m and represents a width of a portion of the crystal defect region that protrudes along a direction parallel to the upper surface of the semiconductor substrate from the portion of the drift region that is above the cathode region to the portion of the drift region that is above the collector region,
the trench and the interface are separate from each other when viewed in plan view, with the trench above the collector region and the interface below the anode region and without the interface directly below the trench, such that the anode region extends toward the upper IGBT structure more than the cathode region does, and
the portion of the crystal defect region does not protrude beyond the trench to a portion of the drift region that is below the upper IGBT structure.

US Pat. No. 10,141,303

RF AMPLIFIER PACKAGE WITH BIASING STRIP

Cree, Inc., Durham, NC (...

1. An RF amplifier package, comprising:a flange shaped body section,
an electrically conductive die pad centrally located on the body section;
an electrically insulating window frame disposed on an upper surface of the body section and surrounding the die pad;
a first electrically conductive lead disposed on the window frame adjacent to a first side of the die pad and extending away from the first side of the die pad towards a first edge side of the body section
a second electrically conductive lead disposed on the window frame adjacent to a second side of the die pad and extending away from the second side of the die pad towards a second edge side of the body section, the second side of the die pad being opposite the first side of the die pad; and
a first electrically conductive biasing strip that is: disposed on the window frame, continuously connected to the second lead, and extends along and a third side of the die pad, the third side of the die pad extending between the first and second sides of the die pad.

US Pat. No. 10,141,302

HIGH CURRENT, LOW SWITCHING LOSS SIC POWER MODULE

Cree, Inc., Durham, NC (...

1. A power module comprising:a housing with an interior chamber; and
a plurality of switch modules mounted within the interior chamber and interconnected to facilitate switching power to a load wherein each of the plurality of switch modules comprises at least one transistor and at least one diode and the power module is able to block at least 1200 volts, conduct at least 120 amperes, and has switching losses less than 25 milli-Joules.

US Pat. No. 10,141,301

CROSS-DOMAIN ESD PROTECTION

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:a triggering arrangement coupled to a first reference voltage node, the triggering arrangement having an output node for a triggering indication; and
interface circuitry coupled to a second reference voltage node different from the first reference voltage node, wherein the interface circuitry comprises a transistor having a body electrode biased to the output node of the triggering arrangement;
a second transistor coupled between the transistor and a third reference voltage node, wherein:
a gate electrode of the second transistor is biased to a triggering node of the triggering arrangement; and
the triggering indication at the output node is a logical inverse of a signal at the triggering node.

US Pat. No. 10,141,300

LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR

Alpha and Omega Semicondu...

1. A transient voltage suppressing (TVS) device comprising:a plurality of fingers of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the plurality of fingers comprising alternating fingers of a first type and fingers of a second type each extending in a second direction orthogonal to the first direction, the semiconductor regions in a first portion of a pair of adjacent fingers forming a silicon controlled rectifier and the semiconductor regions in a second portion of the pair of adjacent fingers forming a P-N junction diode, the first and second portions being arranged in the second direction orthogonal to the first direction on the major surface of the semiconductor layer,
wherein the plurality of fingers defining current conducting regions between each pair of adjacent fingers, each current conducting region including a first current path of the silicon controlled rectifier and a second current path of the P-N junction diode, the first current path of the silicon controlled rectifier being separated from the second current path of the P-N junction diode in each current conducting region in the second direction orthogonal to the first direction on the major surface of the semiconductor layer.

US Pat. No. 10,141,299

SEMICONDUCTOR DEVICE WITH PROTECTIVE ELEMENT PORTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor region of a second conductivity type selectively provided in a surface layer of a first principal surface of a semiconductor substrate of a first conductivity type;
an element structure of a semiconductor element provided in the first semiconductor region;
a second semiconductor region of the first conductivity type selectively provided in the first semiconductor region, the second semiconductor region constituting the element structure of the semiconductor element;
a third semiconductor region of the second conductivity type selectively provided to penetrate the first semiconductor region in a depth direction and to surround the element structure of the semiconductor element at a depth equal to or deeper than a depth of the first semiconductor region, the third semiconductor region having an impurity concentration that is higher than that of the first semiconductor region;
a fourth semiconductor region of the second conductivity type selectively provided in the surface layer of the first principal surface of the semiconductor substrate to be spaced apart from the first semiconductor region;
a fifth semiconductor region of the first conductivity type selectively provided in the fourth semiconductor region;
a sixth semiconductor region of the second conductivity type selectively provided to penetrate the fourth semiconductor region in the depth direction and to be at a depth equal to or deeper than a depth of the fourth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than that of the fourth semiconductor region;
a first electrode that is electrically connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and
a second electrode that is connected to a second principal surface of the semiconductor substrate.

US Pat. No. 10,141,298

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE RELATING TO AN ELECTRICAL OVER STRESS PROTECTING CIRCUIT

SK hynix Inc., Icheon-si...

1. A semiconductor integrated circuit device comprising:a first discharging unit connected between a first line having a first voltage level and a second line having a second voltage level different from the first voltage level to discharge an electrical over stress (EOS) generated in the first line through the second line; and
a second discharging unit connected between the first line and the second line to discharge the EOS in the first line to the second line, wherein the second discharging unit is driven in response to an output signal of the first discharging unit,
wherein the first discharging unit comprises a plurality of Ovonic threshold switch (OTS) units which are connected in series, each of the OTS units including a phase changeable layer having variable resistances in accordance with a voltage difference between the first line and the second line.

US Pat. No. 10,141,297

INTEGRATED DEVICE COMPRISING DEVICE LEVEL CELLS WITH VARIABLE SIZES FOR HEAT DISSIPATION AROUND HOTSPOTS

QUALCOMM Incorporated, S...

1. An integrated device comprising:a substrate;
a device level layer over the substrate, the device level layer including:
a plurality of first device level cells, each first device level cell including a first configuration, wherein the plurality of first device level cells includes standard device level cells that represent at least about 90 percent of all device level cells of the integrated device; and
a plurality of second device level cells, at least one second device level cell including a second configuration that is different than the first configuration, wherein the plurality of second device level cells is located over at least one region of the integrated device that includes at least one hotspot; and
an interconnect portion over the device level layer.

US Pat. No. 10,141,296

DUMMY FIN CELL PLACEMENT IN AN INTEGRATED CIRCUIT LAYOUT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit, comprising:a semiconductor device formed over a substrate;
a first plurality of dummy fin structures over a first portion of the substrate, wherein each of the first plurality of dummy fin structures has a first gate structure having a first gate width, and the first plurality of dummy fin structures being based on a first standard dummy fin cell; and
a second plurality of dummy fin structures over a second portion of the substrate, wherein each of the second plurality of dummy fin structures has a second gate structure having a second gate width different from the first gate width, and the second plurality of dummy fin structures being based on a second standard dummy fin cell,
wherein the second portion surrounds the semiconductor device and the first portion surrounds the second portion.

US Pat. No. 10,141,295

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,
wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, and
wherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface,
the (a) step including the steps of:
(a1) recognizing the recognition mark;
(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and
(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,
(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and
(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.

US Pat. No. 10,141,294

MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package including a module substrate, a first flip chip die attached to an upper surface of the module substrate, and a first mold compound over and surrounding the first flip chip die, wherein:
the first flip chip die comprises a first device layer, a plurality of first interconnects extending from a lower surface of the first device layer to the upper surface of the module substrate, a first dielectric layer over an upper surface of the first device layer, and a first silicon substrate over the first dielectric layer; and
the first device layer includes a first coupling component that is embedded in the first device layer;
thinning down the first mold compound to expose a backside of the first silicon substrate of the first flip chip die;
removing substantially the first silicon substrate to form a first opening within the first mold compound and provide a first thinned flip chip die with an upper surface, wherein:
the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction;
the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other; and
the upper surface of the first thinned flip chip die is exposed at a bottom of the first opening; and
placing a second die in the first opening to stack with the first thinned flip chip die, wherein:
the second die comprises a second coupling component embedded therein; and
the second coupling component is mirrored to the first coupling component.

US Pat. No. 10,141,293

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package, comprising:a package base substrate having first to fourth edges;
a plurality of bonding pads disposed on upper surface of the package base substrate, wherein first to fourth portions of the bonding pads are disposed adjacent to the first to fourth edges of the package base substrate, respectively;
a plurality of connection pads disposed on lower surface of the package base substrate;
four identical semiconductor chips disposed on upper surface of the package base substrate, each of the semiconductor chips including a plurality of first chip pads adjacent to a first edge of the semiconductor chip, and each of the first to fourth semiconductor chips being rotated by ninety degrees relative to adjacent semiconductor chips and thereby, first edges of the first to fourth semiconductor chips facing the first to fourth edges of the package base substrate respectively; and
bonding wires electrically connecting the first chip pads of the first to fourth semiconductor chips to the first to fourth portions of bonding pads respectively,
wherein each of semiconductor chips further includes a second chip pad, and the second chip pads of the first semiconductor chip and the third semiconductor chip are electrically connected by a first matching wire, and the second chip pads of the second semiconductor chip and the fourth semiconductor chip are electrically connected by a second matching wire.

US Pat. No. 10,141,292

DRIVING CHIP BUMP HAVING IRREGULAR SURFACE PROFILE, DISPLAY PANEL CONNECTED THERETO AND DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display panel driven to display an image, the display panel comprising a substrate, the substrate comprising a display area at which the image is displayed;
a terminal pad on the substrate and through which a driving signal is applied to the display area;
a driving chip through which the driving signal is applied to the terminal pad; and
a non-conductive film which fixes the driving chip to the substrate,
wherein the driving chip comprises:
an elastic support body projected from a surface of the driving chip;
a bump wiring on the elastic support body, the bump wiring directly contacting the terminal pad to apply the driving signal to the terminal pad; and
a dispersed particle on the elastic support body,
wherein
the dispersed particle is disposed inside a first portion of the bump wiring,
a second portion of the bump wiring is adjacent to the first portion thereof,
the first portion of the bump wiring at the dispersed particle protrudes further from the elastic support body than the second portion of the bump wiring adjacent to the first portion thereof, and
the protruded first portion of the bump wiring corresponds to a shape of the dispersed particle.

US Pat. No. 10,141,291

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, including:attaching a carrier wafer having a first wafer width to a front side of a die wafer having a second wafer width, the first wafer width being substantially identical to the second wafer width, the die wafer having a thickness of about 700 ?m when attaching to the carrier wafer;
thinning a back side of the die wafer, the back side of the die wafer being opposite to the front side of the die wafer;
singulating the carrier wafer and the die wafer concurrently when die wafer having the second wafer width, whereby singulated dies attached to singulated carrier dies are formed; and
bonding the singulated dies attached to singulated carrier dies to a bottom wafer, wherein a back side of each of the singulated dies is facing a front side of the bottom wafer.

US Pat. No. 10,141,290

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MIKRO MESA TECHNOLOGY CO....

1. A method for manufacturing a display device, the method comprising:forming at least two bottom conductive lines on an array substrate;
disposing at least four micro light emitting devices respectively on the bottom conductive lines;
forming at least one filling material covering the micro light emitting devices;
forming at least four openings in the filling material by photolithography, such that the micro light emitting devices are respectively exposed by the openings; and
forming at least two upper conductive lines on the filling material, wherein the upper conductive lines are electrically connected to the micro light emitting devices through the openings, the upper conductive lines and the bottom conductive lines cross at the micro light emitting devices, and a vertical projection of one of the bottom conductive lines on the array substrate overlaps with a vertical projection of each of the upper conductive lines on the array substrate.

US Pat. No. 10,141,289

SEMICONDUCTOR PACKAGES HAVING PACKAGE-ON-PACKAGE STRUCTURES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a lower package including a lower semiconductor chip on a lower package substrate;
an upper package, stacked on the lower package, including an upper semiconductor chip on an upper package substrate, the upper semiconductor chip having a plurality of chip pads and the upper package substrate having a plurality of substrate pads; and
connection terminals provided between the lower and upper packages,
wherein the chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch, and
wherein the upper package substrate comprises a plurality of connection lines that electrically connect the substrate pads to the chip pads,
wherein the lower package further including a lower mold layer and a plurality of connection patterns on the lower mold layer,
wherein the connection patterns are electrically connected to the connection lines,
wherein the lower mold layer comprises an opening exposing a portion of the lower package substrate, the opening being along a peripheral side of the lower mold layer and extending to a depth lower than that of the lower semiconductor chip on the lower package substrate,
wherein the connection patterns conformally extend along a sidewall of the opening to be electrically connected to the lower package substrate,
wherein the connection terminals are spaced apart from the opening in a plan view,
wherein the connection terminals are electrically connected to the substrate pads and the connection patterns, and
wherein the opening has a ring-type trench shape that continuously extends along lateral sides of the lower semiconductor chip and fully surrounds the lower semiconductor chip in the plan view.

US Pat. No. 10,141,288

SURFACE MOUNT DEVICE/INTEGRATED PASSIVE DEVICE ON PACKAGE OR DEVICE STRUCTURE AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A package structure comprising:an integrated circuit die embedded in an encapsulant;
a redistribution structure on the encapsulant and electrically coupled to the integrated circuit die, the redistribution structure comprising:
a metallization layer distal from the encapsulant and the integrated circuit die, wherein the metallization layer is an uppermost metallization layer of the redistribution structure, and
a dielectric layer on the metallization layer, wherein the dielectric layer is an uppermost dielectric layer of the redistribution structure;
a first under metallization structure on the dielectric layer, the first under metallization structure comprising:
a first under-terminal metallization including a first extending portion and a second extending portion, wherein the first extending portion extends through a first opening of the dielectric layer to a first pattern of the metallization layer, wherein the second extending portion extends through a second opening of the dielectric layer to a second pattern of the metallization layer, wherein the first under-terminal metallization further includes a first upper portion on an upper surface of the dielectric layer distal the encapsulant, the first upper portion extending continuously from the first extending portion to the second extending portion; and
a second under-terminal metallization including a third extending portion and a fourth extending portion, wherein the third extending portion extends through a third opening of the dielectric layer to a third pattern of the metallization layer, wherein the fourth extending portion extends through a fourth opening of the dielectric layer to a fourth pattern of the metallization layer, wherein the second under-terminal metallization further includes a second upper portion on the upper surface of the dielectric layer distal the encapsulant, the second upper portion extending continuously from the third extending portion to the fourth extending portion, wherein the first opening, the second opening, the third opening, and the fourth opening are physically separated from each other; and
a Surface Mount Device and/or Integrated Passive Device (SMD/IPD) attached to the first under metallization structure, wherein the SMD/IPD has a first connector formed of a first conductive material, wherein the first connector physically contacts the first extending portion and the second extending portion of the first under-terminal metallization, wherein the first conductive material extends continuously from the first extending portion to the second extending portion.

US Pat. No. 10,141,287

TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED

GOERTEK, INC., Weifang, ...

1. A method for transferring micro-LED, comprising:forming micro-LEDs on a laser-transparent original substrate, wherein the micro-LEDs are lateral micro-LEDs whose P electrodes and N electrodes are located on one side;
bringing the P electrodes and the N electrodes of the lateral micro-LEDs into contact with pads preset on a receiving substrate; and
irradiating the original substrate with laser from an original substrate side to lift-off the lateral micro-LEDs from the original substrate;
wherein the lateral micro-LEDs contain magnetic substance, and the P electrodes and the N electrodes of the lateral micro-LEDs are brought into contact with the pads preset on the receiving substrate by means of an action of electromagnetic force.

US Pat. No. 10,141,286

METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor package, the method comprising:manufacturing a semiconductor chip in a first semiconductor manufacturing environment;
mounting the semiconductor chip on an upper surface of a printed circuit board, the printed circuit board comprising a lower surface opposite the upper surface;
forming a molding member on the semiconductor chip in a second semiconductor manufacturing environment different from the first semiconductor manufacturing environment;
forming a capping member comprising a material different from the molding member and covering an exposed outer surface of the molding member;
attaching a carrier substrate onto the capping member, the semiconductor chip being between the printed circuit board and the carrier substrate;
forming a redistribution line layer on the lower surface of the printed circuit board in a third semiconductor manufacturing environment different from the second semiconductor manufacturing environment, the redistribution line layer being electrically connected to the semiconductor chip;
forming an external connection member on the redistribution line layer; and
removing the carrier substrate.

US Pat. No. 10,141,285

EXTERNALLY INDUCED CHARGE PATTERNING USING RECTIFYING DEVICES

Palo Alto Research Center...

1. A system for forming charge patterns on micro objects, said system comprising:a micro object including a rectifying device, the rectifying device exhibiting an asymmetric current-voltage (I-V) response curve, the micro object includes a substrate, and wherein the rectifying device is formed on or in the substrate; and
a device external to the micro object, configured to generate an electric or magnetic field to induce a flow of charge through the rectifying device, wherein the device external to the micro object induces the flow of charge through the rectifying device using capacitive or magnetic coupling, and wherein the device external to the micro object which generates the electric or magnetic field, uses at least a part of the electric or magnetic field to generate charge patterns, and wherein motion is induced as an interaction of the electric or magnetic field, induced charge and the micro-object.

US Pat. No. 10,141,284

METHOD OF BONDING SEMICONDUCTOR SUBSTRATES

IMEC vzw, Leuven (BE)

1. A method of bonding semiconductor substrates, the method comprising:providing a first semiconductor substrate and a second semiconductor substrate to be bonded;
pre-bond processing each of the first and second semiconductor substrates prior to bonding, pre-bond processing comprising:
depositing a dielectric layer on a major surface of the each of first and second semiconductor substrates,
chemical-mechanical polishing the dielectric layer of the each of the first and second semiconductor substrates to reduce the roughness of the dielectric layer,
depositing a silicon carbon nitride (SiCN) layer on the dielectric layer of the each of the first and second semiconductor substrates,
pre-bond annealing the each of the first and second semiconductor substrates, and
chemical-mechanical polishing the SiCN layer to reduce the roughness of the SiCN layer;
bonding the first and second semiconductor substrates, bonding comprising:
aligning the first and second substrates, and
contacting the SiCN layers of the first and second substrates, thereby forming an assembly of bonded substrates; and
post-bond annealing the assembly of bonded substrates.

US Pat. No. 10,141,283

SINTERABLE BONDING MATERIAL AND SEMICONDUCTOR DEVICE USING THE SAME

1. A sinterable bonding material comprising a silver filler and an organic base compound as a sintering promoter, wherein the silver filler comprises a flake-shaped filler, and wherein the organic base compound is a nitrogen containing hetero ring compound having an amidine moiety and/or a guanidine moiety.

US Pat. No. 10,141,281

SUBSTRATE AND PACKAGE STRUCTURE

Taiwan Semiconductor Manu...

1. A package structure, comprising:a chip comprising a plurality of pillar bumps;
a substrate, having a core area aligned with a center of the chip and a non-core area, and comprising a plurality of pads having at least one pad in the core area and at least one pad in the non-core area, the at least one pad in the core area having a first pad size and the at least one pad in the non-core area having a second pad size, the first pad size being greater than the second pad size;
wherein the at least one pad in the core area is bonded to a first pillar bump of the plurality of pillar bumps, the first pillar bump having a first bump size;
wherein the at least one pad in the non-core area is bonded to a second pillar bump of the plurality of pillar bumps, the second pillar bump having the first bump size;
wherein a ratio of the first pad size to the first bump size is greater than a ratio of the second pad size to the first bump size; and
wherein a width of the at least one pad in the core area is greater than a width of the at least one pad in the non-core area, and a height of the at least one pad in the core area is the same as a height of the at least one pad in the non-core area.

US Pat. No. 10,141,280

MECHANISMS FOR FORMING PACKAGE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A package structure, comprising:a semiconductor die; and
a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween, wherein:
the first bonding structure and the second bonding structure are next to each other,
the second bonding structure is wider than the first bonding structure,
the first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump,
the first UBM structure is between the first solder bump and the semiconductor die,
the first solder bump has a first end and a second end opposite to the first end,
the second end is in direct contact with the first UBM structure,
the second end is wider than the first end,
the second bonding structure has a second UBM structure and a second solder bump,
the second solder bump has a third end and a fourth end opposite to the third end,
the fourth end is in direct contact with the second UBM structure,
the third end of the second solder bump is as wide as the first end of the first solder bump,
the second UBM structure has a continuous linear portion extending across an entirety of the fourth end of the second solder bump,
the second UBM structure has a sidewall portion surrounding the continuous linear portion and extending along a side surface of the second solder bump,
the third end of the second solder bump and the first end of the first solder bump are substantially positioned at a plane that is parallel to a main surface of the substrate,
the second UBM structure is between the second solder bump and the semiconductor die, and
the second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.

US Pat. No. 10,141,279

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor provided on a main surface of the semiconductor substrate;
an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor; and
an external connection terminal connected to the portion of the conductor exposed from the opening, wherein
in a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.

US Pat. No. 10,141,278

CHIP MOUNTING STRUCTURE

International Business Ma...

1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip, the method comprising:providing the substrate;
mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;
measuring a distance B between a side of the chip and a nearest side of the substrate; and
cutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B,
wherein each square portion has sides of a length c, and wherein

US Pat. No. 10,141,277

MONOLITHIC DECOUPLING CAPACITOR BETWEEN SOLDER BUMPS

International Business Ma...

1. An integrated circuit, comprising:pads formed on a back end of the line surface;
decoupling capacitor stacks monolithically formed about the pads, each decoupling capacitor stack including dielectric layers, and a first conductive layer and a second conductive layer disposed between the dielectric layers, the first and second conductive layers including respective materials having different etch selectivities;
and solder balls formed on respective ones of the pads and connecting to respective ones of the first and second conductive layers to reduce noise and voltage spikes between the solder balls.

US Pat. No. 10,141,276

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A semiconductor package structure, comprising:a redistribution structure, having a first surface and a second surface opposite to the first surface;
at least one package structure over the first surface of the redistribution structure, wherein the at least one package structure comprises:
at least one die, having a plurality of first conductive terminals thereon;
a first encapsulant, encapsulating the at least one die, wherein the first encapsulant exposes at least part of the first conductive terminals;
a redistribution layer over the first encapsulant, wherein the redistribution layer is electrically connected to the first conductive terminals; and
a plurality of second conductive terminals, electrically connected between the redistribution layer and the redistribution structure; and
a second encapsulant, encapsulating the at least one package structure, wherein the second encapsulant exposes at least part of the second conductive terminals.

US Pat. No. 10,141,275

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method of manufacturing a semiconductor structure, comprising:providing a substrate;
disposing a pad over the substrate;
disposing a first passivation over the substrate to partially cover the pad;
disposing a conductive material over the first passivation and the pad to form a conductive line electrically connected to the pad;
disposing a second passivation over the first passivation to partially cover the conductive line; and
forming a plurality of first protrusions over the conductive line exposed from the second passivation;
wherein the method further comprising:
disposing a patterned mask including a plurality of openings over the first passivation;
removing portions of the first passivation exposed from the patterned mask to form a plurality of recesses over the first passivation;
removing the patterned mask; and
disposing the conductive material within the plurality of recesses to form a plurality of second protrusions protruded from the conductive line towards the substrate.

US Pat. No. 10,141,274

SEMICONDUCTOR CHIP WITH ANTI-REVERSE ENGINEERING FUNCTION

International Business Ma...

1. An anti-reverse engineering semiconductor structure, comprising:a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, said first wiring level closest to said semiconductor substrate and said last wiring level furthest from said semiconductor substrate, said stack of wiring levels including an intermediate wiring level between said first wiring level and said last wiring level, said semiconductor substrate and said first wiring level comprising active devices, wherein each wiring level of said stack of wiring levels comprises a dielectric layer containing electrically conductive wire;
active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire;
a liner on sidewalls and a bottom of a trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate, such that said trench comprises an open space;
a cap sealing a top of said open space of said trench, wherein each of said liner and said cap is configured to be damaged during a reverse engineering process such that said trench is exposed to said at least one wiring level of said stack of wiring levels; and
a chemical agent filling said open space of said trench, wherein said liner and said cap are chemically inert to said chemical agent, wherein portions of said at least one wiring level of said stack of wiring levels are not chemically inert to said chemical agent or a reaction product of said chemical agent, and wherein upon said liner or said cap being damaged during said reverse engineering process, said chemical agent is configured to damage wires, dielectric layers, dielectric materials, and said active devices of said at least one wiring level of said stack of wiring levels.

US Pat. No. 10,141,273

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface;
a first semiconductor chip which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, and is mounted on the wiring substrate so that the first front surface faces the first surface of the wiring substrate; and
a second semiconductor chip which includes a second front surface, a plurality of second front electrodes formed on the second front surface, and a second rear surface opposite to the second front surface, and is mounted on the first semiconductor chip so that the second front surface faces the first rear surface of the first semiconductor chip,
wherein the plurality of first terminals of the wiring substrate and the plurality of first front electrodes of the first semiconductor chip are electrically connected to each other via a plurality of first protrusion electrodes,
wherein the plurality of first rear electrodes of the first semiconductor chip and the plurality of second front electrodes of the second semiconductor chip are electrically connected to each other via a plurality of second protrusion electrodes,
wherein the plurality of first rear electrodes are formed in a first region of the first rear surface of the first semiconductor chip,
wherein a first metal pattern is formed in a second region on a peripheral side of the first rear surface relative to the first region,
wherein a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surfaces, and
wherein a first separation distance between the first rear surface of the first semiconductor chip and the second front surface of the second semiconductor chip in an outer periphery of the second region is smaller than a second separation distance between the first rear surface of the first semiconductor chip and the second front surface of the second semiconductor chip in the first region.

US Pat. No. 10,141,272

SEMICONDUCTOR APPARATUS, STACKED SEMICONDUCTOR APPARATUS AND ENCAPSULATED STACKED-SEMICONDUCTOR APPARATUS EACH HAVING PHOTO-CURABLE RESIN LAYER

SHIN-ETSU CHEMICAL CO., L...

1. A semiconductor apparatus comprising: a semiconductor device; an on-semiconductor-device metal pad electrically connected to the semiconductor device; a metal interconnect electrically connected to the semiconductor device; a through electrode electrically connected to the metal interconnect; a solder bump electrically connected to the metal interconnect; a first insulating layer on which the semiconductor device is placed; a second insulating layer formed on the semiconductor device; a third insulating layer formed on the second insulating layer, whereinthe through electrode penetrates at least the second insulating layer,
the metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second insulating layer, and the metal interconnect penetrates the second insulating layer from the upper surface of the second insulating layer and is electrically connected to the through electrode at an lower surface of the second insulating layer,
the first insulating layer is formed by a photo-curable dry film or a photo-curable resist coating film,
the second insulating layer is formed by the photo-curable dry film, and
the third insulating layer is formed by the photo-curable dry film or a photo-curable resist coating film; wherein
the photo-curable dry film has a photo-curable resin layer composed of a photo-curable resin composition containing: resin, crosslinking agents, a photo acid generator and a solvent, or
the photo-curable resist coating film is a photo-curable resin layer composed of a photo-curable resin composition containing: resin, crosslinking agents, a photo acid generator and a solvent.

US Pat. No. 10,141,271

SEMICONDUCTOR DEVICE HAVING ENHANCED HIGH-FREQUENCY CAPABILITY AND METHODS FOR MAKING SAME

COOLSTAR TECHNOLOGY, INC....

1. A method of reducing electromagnetic interference in a semiconductor device, comprising:forming at least one functional circuit in a substrate of the semiconductor device; and
forming an integrated micro-shielding structure in the semiconductor device, the integrated micro-shielding structure extending vertically through the substrate between a front surface and a back surface of the substrate and surrounding the at least one functional circuit, the integrated micro-shielding structure being configured to reduce at least one of radio frequency (RF) emissions in the semiconductor device and RF coupling between different functional parts of the at least one functional circuit;
wherein forming the integrated micro-shielding structure comprises:
forming at least a first trench in the front surface of the substrate and extending partially through the substrate;
forming a first conductive layer on at least a bottom and sidewalls of the first trench;
forming at least a second trench in the back surface of the substrate and extending partially through the substrate, the second trench underlying at least a portion of the first trench, respective depths of the first and second trenches being configured such that the first and second trenches are separated from one another by a prescribed vertical spacing; and
forming a second conductive layer on at least a bottom and sidewalls of the second trench;
wherein the prescribed vertical spacing between the first and second trenches is configured to be smaller than a wavelength of RF signals being isolated by the integrated micro-shielding structure.

US Pat. No. 10,141,270

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

Amkor Technology, Inc., ...

1. A semiconductor device comprising:a substrate having a top substrate surface, a bottom substrate surface, and lateral substrate surfaces extending between the top and bottom substrate surfaces;
a metal plane on the top substrate surface, the metal plane comprising first and second apertures extending completely and vertically through the metal plane;
a semiconductor die on the top substrate surface and positioned within the first aperture of the metal plane, the semiconductor die having a top die surface, a bottom die surface, and lateral die side surfaces extending between the top and bottom die surfaces, wherein the bottom die surface is coupled to the top substrate surface; and
an encapsulating material that encapsulates at least a portion of the lateral die side surfaces and at least a portion of the top substrate surface, wherein the encapsulating material extends through the second aperture of the metal plane,
wherein:
the second aperture is entirely laterally bounded by the metal plane; and
the second aperture is free of electronic components.

US Pat. No. 10,141,269

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE WIRE WITH INCREASED ATTACHMENT ANGLE AND METHOD

Amkor Technology, Inc., ...

1. A semiconductor device comprising:a substrate;
a semiconductor die mounted to the substrate;
a shielding wire spaced apart from a major surface the semiconductor die and formed across the major surface of the semiconductor die; and
an auxiliary structure supporting the shielding wire under the shielding wire, wherein:
the shielding wire comprises opposing ends attached to the substrate;
the auxiliary structure physically contacts the shielding wire at a location other than either of the opposing ends; and
the auxiliary structure is attached to the substrate along only one side of the semiconductor die without overlapping the major surface of the semiconductor die.

US Pat. No. 10,141,267

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first connection member including a redistribution layer;
a first semiconductor chip disposed on the first connection member and having an active surface having a first connection pad disposed thereon and an inactive surface opposing the active surface;
a first encapsulant disposed on the first connection member and encapsulating at least portions of the first semiconductor chip;
a second semiconductor chip disposed on the first encapsulant and having an active surface having a second connection pad disposed thereon and an inactive surface opposing the active surface;
a second encapsulant disposed on the first encapsulant and encapsulating at least portions of the second semiconductor chip; and
a second connection member having a through-hole,
wherein the active surfaces of the first semiconductor chip and the second semiconductor chip face the first connection member,
the first connection pad and the second connection pad are electrically connected to the redistribution layer of the first connection member through a first via and a second via that do not overlap each other, respectively,
the first semiconductor chip is disposed in the through-hole of the second connection member, and
the first encapsulant encapsulates at least portions of the second connection member.

US Pat. No. 10,141,266

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE

Siliconware Precision Ind...

1. A method of fabricating a semiconductor package structure, comprising:providing a release member that has opposing top and bottom surfaces;
forming a plurality of first conductive pads and a plurality of second conductive pads on the top surface of the release member;
disposing a semiconductor component on the first conductive pads and electrically connecting the semiconductor component to the first conductive pads, forming a plurality of conductive elements on the second conductive pads, each of the conductive elements having opposing first and second ends, and forming on the top surface of the release member a package body having opposing first and second surfaces and encapsulating the semiconductor component and the conductive elements, with the first and second conductive pads exposed from the first surface of the package body, and the second ends of the conductive elements exposed from the second surface of the package body; and
after forming the conductive elements on the second conductive pads, removing the release member.

US Pat. No. 10,141,265

BENT-BRIDGE SEMICONDUCTIVE APPARATUS

Intel IP Corporation, Sa...

1. A bent-bridge semiconductive apparatus comprising:a first semiconductive device;
a silicon bridge that is integrally part of the first semiconductive device, wherein the silicon bridge is deflected out of planarity with respect to the first semiconductive device, and
electrical connection selected from the group consisting of an electrical bump and a redistribution layer coupled to the first semiconductive device at metallization on an active surface thereof.

US Pat. No. 10,141,264

METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA

ALPHA AND OMEGA SEMICONDU...

1. A wafer level packaging structure with a large contact area, the wafer level packaging structure comprising:a plurality of first metal bonding pads and a second metal bonding pad formed at a front surface of a semiconductor chip;
a bottom metal layer covering a back surface of the semiconductor chip;
a bottom through hole formed in the semiconductor chip beneath the second metal bonding pad, the bottom through hole extending from the front surface of the semiconductor chip to the back surface of the semiconductor chip, wherein the bottom through hole is filled with a conductive material forming a bottom metal interconnecting structure, and wherein the bottom metal layer is electrically connected to the second metal bonding pad through the bottom metal interconnecting structure;
a top packaging layer covering the front surface of the semiconductor chip;
a bottom packaging layer covering the bottom metal layer;
a plurality of top metal interconnecting structures formed on and electrically connected to the plurality of first metal bonding pads and the second metal bonding pad; and
a plurality of contact bonding pads formed atop the top packaging layer, wherein a contact bonding pad of the plurality of contact bonding pads is electrically connected to one of the plurality of first metal bonding pads or the second metal bonding pad through at least one of the plurality of top metal interconnecting structures.

US Pat. No. 10,141,263

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:providing a substrate;
forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer;
performing a first etching process to remove part of the ILD layer for forming a recess;
performing a second etching process to remove part of the first spacer for expanding the recess after performing the first etching process; and
forming a contact plug in the recess.

US Pat. No. 10,141,262

ELECTRICALLY CONDUCTIVE LAMINATE STRUCTURES

Micron Technology, Inc., ...

1. An electrical interconnect, comprising:an electrically conductive laminate structure; the laminate structure comprising multiple regions nested within one another; one of said nested regions being a graphene region and others of the nested regions being non-graphene regions; the graphene region being sandwiched between a pair of non-graphene regions; the laminate structure comprising an uppermost surface that contains segments of the graphene region and of the non-graphene regions; at least one of the non-graphene regions being electrically conductive;
an electrically insulative material over the upper surface of the laminate structure, and having an opening extending therethrough to a portion of the laminate structure; said portion differing from other portions of the laminate structure by having space between the pair of non-graphene regions instead of having graphene between the non-graphene regions; and
electrically conductive material within the opening and within the space.

US Pat. No. 10,141,261

DEVICE COMPRISING NANOSTRUCTURES AND METHOD OF MANUFACTURING THEREOF

1. A device (300, 410-412) having individually addressable sets of nanostructures (207) comprising:a first substrate (200), wherein the first substrate comprises a first face (202) and a second face (203), wherein an insulating layer (201) comprising an insulating material arranged on said first face (202) of said first substrate (200);
a plurality of electrically conductive portions (208) within said insulating layer (201), said portions being spaced apart from each other;
a set of nanostructures (207) arranged on said first face (202) of the first substrate, such that the nanostructures are spatially separated and grown on top of the said first face (202), wherein said sets of nanostructures (207) are arranged on each of said electrically conductive portions (208) such that each electrically conductive portion is in electrical connection with a respective one of said sets of nanostructures;
a connecting structure (210) in a second substrate (209) underlying said second face (203) of said insulating layer (201), wherein the said connecting structure (210) is comprised of materials different than the composition materials of the conductive portions (208), the insulating material and the said second substrate (209), said connecting structure being connectable to an external device and configured to provide a first electrical connection to each of said electrically conductive portions (208), and thereby enabling individual addressing of each set of nano structures (207).

US Pat. No. 10,141,260

INTERCONNECTION STRUCTURE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming an interconnection structure, comprising:forming a dielectric structure over a non-insulator structure;
forming a hole in the dielectric structure to expose the non-insulator structure;
forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process;
forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process;
removing a first portion of the second diffusion barrier layer from a bottom of the hole; and
forming a metal over the first diffusion barrier layer.

US Pat. No. 10,141,259

SEMICONDUCTOR DEVICES HAVING ELECTRICALLY AND OPTICALLY CONDUCTIVE VIAS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a first semiconductor die having a first optical component for receiving and/or transmitting optical signals;
a second semiconductor die adjacent to the first semiconductor die and having a second optical component for receiving and/or transmitting optical signals; and
a via extending at least between the first optical component and the second optical component, the via having a transparent and electrically conductive material disposed therein, wherein the transparent and electrically conductive material (a) optically couples the first and second optical components and (b) electrically couples the first and second semiconductor dies.

US Pat. No. 10,141,258

SEMICONDUCTOR DEVICES HAVING STAGGERED AIR GAPS

Samsung Electronics Co., ...

9. A semiconductor device comprising:a substrate including a first region and a second region spaced apart from each other in a first direction;
lower conductive patterns disposed on the substrate and including first lower conductive patterns on the first region and second lower conductive patterns on the second region;
a first interlayer dielectric layer disposed between the first lower conductive patterns
a lower air gap provided in a space between the second lower conductive patterns;
a middle conductive pattern disposed on the lower conductive pattern in the second region;
upper conductive patterns including first upper conductive patterns disposed on the first lower conductive patterns and second upper conductive patterns disposed on the second lower conductive patterns; and
an upper air gap provided in a space between the second upper conductive patterns,
wherein the first interlayer dielectric layer completely fills a space between the first lower conductive patterns.

US Pat. No. 10,141,257

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A semiconductor integrated circuit device, comprising:(a) a first interconnect made of a first metal film and formed over a main surface of a semiconductor substrate;
(b) a first barrier insulating film formed on the first interconnect such that the first barrier insulating film contacts a top surface of the first interconnect;
(c) a first interlayer insulating film formed over the first barrier insulating film;
(d) a first via hole formed in the first interlayer insulating film and the first barrier insulating film such that the first via hole connects with the first interconnect;
(e) a first interconnect trench formed in the first interlayer insulating film over the first via hole and connected with the first via hole;
(f) a second interconnect formed by filling a second metal film in the first interconnect trench and the first via hole;
(g) a third interconnect made of a third metal film and formed over the second interconnect and the first interlayer insulating film;
(h) a second barrier insulating film formed on the third interconnect such that the second barrier insulating film contacts a top surface of the third interconnect;
(i) a second interlayer insulating film formed over the second barrier insulating film;
(j) a second via hole formed in the second interlayer insulating film and the second barrier insulating film such that the second via hole connects with the third interconnect;
(k) a second interconnect trench formed in the second interlayer insulating film over the second via hole and connected with the second via hole; and
(l) a fourth interconnect formed by filling a fourth metal film in the second interconnect trench and the second via hole,
wherein the second interlayer insulating film has an etching stopper film,
wherein the etching stopper film is arranged nearer to a bottom surface of the fourth interconnect than to a top surface of the third interconnect and a top surface of the fourth interconnect,
wherein the first interlayer insulating film does not have an etching stopper film,
wherein the second interlayer insulating film is thicker than the first interlayer insulating film,
wherein a depth of the second interconnect trench is greater than a depth of the first interconnect trench,
wherein a depth of the second via hole is greater than a depth of the first via hole,
wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film,
wherein the first barrier insulating film includes silicon, carbon and nitrogen,
wherein the second barrier insulating film includes silicon, carbon and nitrogen, and
wherein the etching stopper film includes silicon and nitrogen.

US Pat. No. 10,141,256

SEMICONDUCTOR DEVICE AND LAYOUT DESIGN THEREOF

Taiwan Semiconductor Manu...

1. A device, comprising:a substrate having formed therein an active region, the active region including an edge extending in a first direction;
a plurality of gates;
a first conductive segment over the active region,
wherein a first distance is present between a first gate of the gates and the first conductive segment, a second distance is present between a second gate of the gates and the first conductive segment, and the first distance is greater than the second distance, and further wherein the second gate of the gates has a major axis in the first direction that extends over the edge of the active region in the first direction; and
a via contacting the first conductive segment wherein the first conductive segment is between the via and the substrate; and further wherein
a third distance between the first gate of the gates and the via is different than the first distance and a fourth distance between the second gate of the gates and the via is different than the second distance.

US Pat. No. 10,141,255

CIRCUIT BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package substrate, comprising:an upper conductive pattern disposed on a top surface of the semiconductor package substrate, the upper conductive pattern including bonding pads and upper electric patterns; and
a lower conductive pattern disposed on a bottom surface of the semiconductor package substrate, the lower conductive pattern including ball lands and a lower electric pattern,
wherein the bonding pads are disposed in an upper window region of the top surface and at least one of the bonding pads is electrically connected to at least one of the upper electric patterns, and the lower electric pattern is disposed in a lower window region and is electrically connected to at least one of the bonding pads and at least one of the ball lands,
wherein the lower window region is defined by outer boundaries of the lower electric pattern along at least two perpendicular directions, and the upper window region is defined as an overlapped region with the lower window region, and
wherein the upper electric patterns and the lower electric pattern include the same metallic material, and a ratio of the area occupied by the lower electric pattern in the lower window region to the area occupied by the upper conductive pattern in the upper window region is less than or equal to 1.5.

US Pat. No. 10,141,254

DIRECT BONDED COPPER POWER MODULE WITH ELEVATED COMMON SOURCE INDUCTANCE

FORD GLOBAL TECHNOLOGIES,...

1. A half-bridge power module comprising:a first direct bonded copper substrate (DBC) with a first insulation layer, a first etched circuit layer on an inner surface, and a first heat transfer layer on an outer surface, wherein the first etched circuit layer includes a high-side plate with a high-side terminal pad;
a second direct bonded copper substrate (DBC) with a second insulation layer, a second etched circuit layer on an inner surface, and a second heat transfer layer on an outer surface, wherein the second etched circuit layer includes an output plate with a output terminal pad;
a high-side transistor die having a collector side soldered to the high-side plate; and
a low-side transistor die having a collector side soldered to the output plate;
wherein the high-side plate defines a first indented notch disposed between the high-side transistor die and the high-side terminal pad to concentrate a magnetic flux at the first indented notch induced by a current in the high-side plate; and
wherein one of the first or second etched circuit layers further includes a high-side gate trace connected to the high-side transistor die and overlapping the first indented notch.

US Pat. No. 10,141,253

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

16. A method comprising:receiving an interposer, the interposer comprising a first redistribution layer (RDL) over a first side of a substrate, and a plurality of external connectors attached to a second side of the substrate opposing the first side;
attaching a plurality of dies to the first RDL, wherein after attaching the plurality of dies, the first RDL is between the substrate and the plurality of dies;
filling a space between the plurality of dies and the first RDL with an underfill material;
forming a molding material over the first RDL and around the plurality of dies and the underfill material;
dispensing a polymer material on the second side of the substrate without covering top surfaces of the plurality of external connectors distal the substrate; and
curing the polymer material.

US Pat. No. 10,141,252

SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole further defined by a first sidewall and a second sidewall of the passivation layer;
a first conductive layer on the first surface of the passivation layer and the first sidewall;
a second conductive layer on the second surface of the passivation layer and the second sidewall; and
a third conductive layer between the first conductive layer and the second conductive layer,
wherein the third conductive layer comprises a first seed layer adjacent to the first conductive layer and a second seed layer adjacent to the second conductive layer,
wherein the passivation layer comprises a first polymer layer and a second polymer layer,
wherein the first seed layer is disposed between the first conductive layer and the first polymer layer and the second seed layer is disposed between the second conductive layer and the second polymer layer.

US Pat. No. 10,141,251

ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME

GENERAL ELECTRIC COMPANY,...

1. An electronic package, comprising:a substrate having a first side and a second side;
a seed metal layer disposed on at least a portion of the first side of the substrate;
a patterned resist layer disposed on at least a portion of the seed metal layer, wherein the patterned resist layer and the seed metal layer are at least partly removed exposing the first side of the substrate during formation of the electronic package to define a plurality of pre-defined via locations, a plurality of pre-defined via patterns, and a plurality of pre-defined trace patterns;
a metal built-up layer disposed on at least a portion of the seed metal layer corresponding to the plurality of pre-defined via locations and the plurality of pre-defined trace patterns, the metal built-up layer disposed on at least a portion of the seed metal layer such that the seed metal layer is disposed between the substrate and the metal built-up layer,
an adhesive layer disposed on at least a portion of the second side of the substrate;
a contact pad disposed on at least a portion of the adhesive layer and aligned with at least one of the plurality of pre-defined via locations;
an electronic device coupled to the contact pad and aligned with one of the plurality of pre-defined via locations, the plurality of pre-defined via patterns, and the plurality of pre-defined trace patterns, wherein the substrate and the adhesive layer are at least partly removed to extend the plurality of pre-defined via locations to the electronic device;
a first conductive layer disposed on at least a portion of the plurality of pre-defined via locations, the plurality of pre-defined via patterns, and the plurality of pre-defined trace patterns; and
a second conductive layer disposed on the first conductive layer such that the second conductive layer is disposed within the plurality of pre-defined via locations,
wherein a plurality of vias, a plurality of via patterns and a plurality of trace patterns are formed by selectively removing a portion of the first conductive layer and the second conductive layer disposed outside the plurality of pre-defined via locations, the plurality of pre-defined via patterns and the plurality of pre-defined trace patterns.

US Pat. No. 10,141,250

CHIP AND ELECTRONIC DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A chip comprising:a substrate;
a die wrapped together with the substrate by a package;
a plurality of conductive bumps disposed on the die;
an attachment point matrix arranged on a first surface of the substrate, the attachment point matrix comprising multiple attachment points;
a solder joint matrix arranged on a second surface of the substrate, the solder joint matrix comprising a plurality of solder joints comprising a first solder joint group and a second solder joint group; and
multiple substrate cables corresponding to the multiple attachment points, each of the multiple substrate cables extending through an entire thickness of the substrate and extending through a portion of a length of the substrate, each of the multiple substrate cables comprising a first end and a second end, each of the multiple substrate cables comprising at least one bend between the first end and the second end, each of the plurality of conductive bumps being electrically coupled to a corresponding one of the multiple attachment points, the first end of each of the multiple substrate cables being electrically coupled to a corresponding one of the multiple attachment points, the second end of each of the multiple substrate cables being electrically coupled to a corresponding one of the plurality of solder joints, the first solder joint group being arranged along a first parallel line, the second solder joint group being arranged along a second parallel line that is parallel to the first parallel line, a first subset of the multiple substrate cables electrically coupled to the first solder joint group being a first length value, a second subset of the multiple substrate cables electrically coupled to the second solder joint group being a second length value, and a difference between the first length value and the second length value equaling a predetermined value that is not equal to zero.

US Pat. No. 10,141,249

MOLDED INTELLIGENT POWER MODULE AND METHOD OF MAKING THE SAME

ALPHA AND OMEGA SEMICONDU...

1. An intelligent power module (IPM) for driving a motor, the IPM comprising:a first, second, third and fourth die paddles;
a first transistor attached to the first die paddle;
a second transistor attached to the second die paddle;
a third transistor attached to the third die paddle;
a fourth, fifth, and sixth transistors attached to the fourth die paddle;
a plurality of leads;
a metal slug;
a plurality of spacers disposed between the metal slug and the first, second, third and fourth die paddles; and
a molding encapsulation enclosing the first, second, third, and fourth die paddles, the first, second, third, fourth, fifth, and sixth transistors and the plurality of spacers;
wherein the plurality of leads are at least partially embedded in the molding encapsulation;
wherein a majority portion of the metal slug is embedded in the molding encapsulation; and
wherein a bottom surface of the metal slug is exposed from the molding encapsulation.

US Pat. No. 10,141,248

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first semiconductor chip having a first front surface on which a first electrode pad is formed;
a first chip mounting part on which the first semiconductor chip is mounted;
a first lead arranged in a region around the first semiconductor chip;
a first conductive member which is electrically connected to the first electrode pad of the first semiconductor chip via a first conductive adhesive, and is electrically connected to the first lead;
a first support part arranged over the first chip mounting part and supporting the first conductive member; and
a sealing member that seals the first semiconductor chip, the first conductive member and a portion of the first lead,
wherein the first conductive member includes a main body part and a first extension part which is continuous to the main body part and extends from the main body part in plan view,
wherein a first portion of the first extension part is disposed in the sealing member so as to overlap a first portion of the first support part in the sealing member in plan view,
wherein an end portion of the first support part is exposed from the sealing member,
wherein the sealing member has a first side extending along a first direction,
wherein a second portion of the first lead projects from the first side of the sealing member in plan view,
wherein the end portion of the first support part is exposed from the first side of the sealing member,
wherein the sealing member has a second side extending along a second direction intersecting with the first direction, and
wherein the first support part includes a bent part arranged between the end portion of the first support part and the first portion of the first support part, such that the bent part is bent closer to the main body part of the first conductive member than to the second side of the sealing member in plan view.

US Pat. No. 10,141,247

POWER SEMICONDUCTOR DEVICE

1. A power semiconductor device, comprising:a substrate and power semiconductor components arranged on the substrate and electrically conductively connected to the substrate;
an electrically conductive DC voltage bus bar system and comprising a capacitor electrically conductively connected to the DC voltage bus bar system;
wherein the power semiconductor device further comprises:
a capacitor securing apparatus for securing the capacitor and a receptacle device for receiving the capacitor, in which at least part of the capacitor is arranged;
wherein, from the DC voltage bus bar system, a plurality of electrically conductive bus bar system terminal elements are electrically conductively connected thereto and run in a direction of the substrate;
at least one elastic first deformation element is materially bonded to the capacitor securing apparatus and is formed from an elastomer and is arranged on a facing side of the capacitor securing apparatus facing the DC voltage bus bar system;
wherein the capacitor securing apparatus, via the at least one first deformation element, presses the DC voltage bus bar system in the direction of the substrate and thereby further presses the bus bar system terminal elements against designated electrically conductive contact areas of the substrate such that the bus bar system terminal elements are electrically conductively pressure-contacted with said contact areas of the substrate.

US Pat. No. 10,141,246

LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING

STMicroelectronics, Inc.,...

1. A method, comprising:removing portions of a metal layer on a first surface and a second surface of a leadframe;
forming a first plurality of recesses and a second plurality of recesses in the first surface of the leadframe;
coupling a solder ball to each of the first plurality of recesses;
coupling a die to the metal layer on the first surface of the leadframe;
coupling a plurality of wires between the die and the first surface of the leadframe;
encapsulating the die, the plurality of wires and at least a portion of each solder ball with an encapsulant, a portion of each solder ball extending from a sidewall of the leadframe and into a body of the encapsulant;
removing remaining portions of a body of the leadframe opposite the first plurality of recesses and the second plurality of recesses; and
cutting the encapsulant, the leadframe and the plurality of solder balls to form a leadframe package.

US Pat. No. 10,141,245

HIGH-POWER ACOUSTIC DEVICE WITH IMPROVED PERFORMANCE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a substrate comprising a substrate body and a die pad on a top surface of the substrate body;
a die-attach material applied over the die pad, wherein the die-attach material is a sintered material;
an acoustic die coupled to the die pad via the die-attach material, wherein:
the acoustic die includes a plurality of acoustic components, a die body and a metallization structure;
the plurality of acoustic components resides over a top surface of the die body and the metallization structure resides over a bottom surface of the die body; and
the metallization structure is vertically sandwiched between the die body and the die-attach material.

US Pat. No. 10,141,244

TSV LAYOUT STRUCTURE AND TSV INTERCONNECT STRUCTURE, AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of fabricating a TSV interconnect structure, comprising:providing a semiconductor substrate including a first region and a second region that have a total surface area equal to an area of a single chip;
forming a plurality of through-holes in both the first region and the second region by controlling a difference of an average area ratio of through-holes between the first region and the entire semiconductor substrate, such that a polishing rate difference of a metal layer in the through-holes between the first and second regions is reduced, wherein:
an average through-hole area ratio of the first region is greater than an average through-hole area ratio of the entire semiconductor substrate and the average through-hole area ratio of the entire semiconductor substrate is less than or equal to about 2%, and
the second region is a continuous region connecting to the first region and has an average through-hole area ratio less than the first region, and
through-holes in the first region are closely packed, while through-holes in the second region are loosely packed;
forming the metal layer to fill the plurality of through-holes in the semiconductor substrate; and
planarizing the metal layer by a chemical mechanical polishing process to form a TSV interconnect structure, wherein:
when the semiconductor substrate in the first region has a surface area of less than or equal to about 28 mm2 and greater than about 14 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 1.25%,
when the semiconductor substrate in the first region has the surface area of less than or equal to about 14 mm2 and greater than about 3 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 2.75%,
when the semiconductor substrate in the first region has the surface area of less than or equal to about 3 mm2 and greater than about 0.5 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 4.75%, and
when the semiconductor substrate in the first region has the surface area of less than or equal to about 0.5 mm2 and greater than about 0.16 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 6.75%.

US Pat. No. 10,141,243

THYRISTOR ASSEMBLY RADIATOR FOR DC CONVERTER VALVE

NR ELECTRIC CO., LTD, Ji...

1. A thyristor assembly radiator for a DC converter valve, comprising:radiators;
a thyristor being disposed between every two adjacent radiators, wherein
each of the radiators comprises a housing, a water feeding port is provided at an upper part of the housing, a water discharging port is provided at a lower part of the housing, and through holes in the housing of the radiator for accommodating damping resistors are provided between the water feeding port and the water discharging port;
a water discharging port of an Nth radiator is communicated with a water discharging port of an (N?2)th radiator via a (N?2)th water discharging pipeline, and a water feeding port of the Nth radiator is communicated with a water feeding port of an (N+2)th radiator via a Nth water feeding pipeline, or the water feeding port of the Nth radiator is communicated with a water feeding port of the (N?2)th radiator via a (N?2)th water feeding pipeline, and the water discharging port of the Nth radiator is communicated with a water discharging port of the (N+2)th radiator via a Nth water discharging pipeline, wherein N?3, and N is an odd number;
a water discharging port of an Mth radiator is communicated with a water discharging port of an (M?2)th radiator via a (M?2)th water discharging pipeline, and a water feeding port of the Mth radiator is communicated with a water feeding port of an (M+2)th radiator via a Mth water feeding pipeline, or the water feeding port of the Mth radiator is communicated with a water feeding port of the (M?2)th radiator via a (M?2)th water feeding pipeline, and the water discharging port of the Mth radiator is communicated with a water discharging port of the (M+2)th radiator via a Mth water discharging pipeline, wherein M?4, and M is an even number; and
water feeding ports of the last two radiators are communicated with each other via a water feeding pipeline.

US Pat. No. 10,141,242

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein
a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and
a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

US Pat. No. 10,141,241

MULTI-CHIP SELF ADJUSTING COOLING SOLUTION

Intel Corporation, Santa...

1. An apparatus comprising:a primary device and at least one secondary device coupled in a planar array to a substrate;
a first passive heat exchanger comprising a heatsink base and a fin structure disposed on the primary device and the heatsink base and the fin structure of the first passive heat exchanger both comprise an opening over an area corresponding to the at least one secondary device, wherein the heatsink base of the first passive heat exchanger has a bottommost surface;
at least one second passive heat exchanger comprising a heatsink base and a fin structure both disposed in the opening and on the at least one secondary device;
at least one first spring operable to apply a force to the first passive heat exchanger in a direction of the primary device, the at least one first spring between the substrate and the heatsink base of the first passive heat exchanger; and
at least one second spring operable to apply a force to the at least one second passive heat exchanger in a direction of the at least one secondary device, the at least one second spring between the heatsink base of the first passive heat exchanger and the heatsink base of the at least one second passive heat exchanger, wherein the at least one second spring extends below the bottommost surface of the heatsink base of the first passive heat exchanger.

US Pat. No. 10,141,240

SEMICONDUCTOR DEVICE, CORRESPONDING CIRCUIT AND METHOD

STMICROELECTRONICS S.R.L....

1. A semiconductor device comprising:at least one semiconductor die;
a package, the at least one semiconductor die embedded in the package, the at least one semiconductor die coupled to a thermally-conductive element, wherein the package includes a layered package including:
an intermediate layer, the at least one semiconductor die arranged in an opening in the intermediate layer;
first and second outer layers, the thermally-conductive element including a thermally-conductive inlay in the first outer layer, wherein the second outer layer is provided with electrical contact formations coupled to the at least one semiconductor die; and
a heat sink member thermally coupled to the thermally-conductive inlay.

US Pat. No. 10,141,239

THERMAL DISSIPATION THROUGH SEAL RINGS IN 3DIC STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a plurality of dies bonded to each other;
an interposer bonded to one of the plurality of dies;
a seal-ring comprising thermal path extending through each of the plurality of dies;
a metal line on the interposer, the metal line extending away from the plurality of dies in a direction parallel with a major surface of the interposer;
an interposer seal ring extending at least partially through the interposer; and
a through via extending at least partially through the interposer, the through via in thermal connection with the metal line through the interposer seal ring.

US Pat. No. 10,141,238

SEMICONDUCTOR POWER DEVICE INCLUDING ADJACENT THERMAL SUBSTRATE FOR THERMAL IMPEDANCE REDUCTION

Integra Technologies, Inc...

16. A gallium-nitride (GaN) on silicon carbide (SiC) high electron mobility transistor (HEMT), comprising:a base plate;
an input lead disposed on and electrically isolated from the base plate;
an output lead disposed on and electrically isolated from the base plate;
a semiconductor power die disposed on the base plate, wherein the semiconductor power die includes a set of one or more gate electrodes configured to receive an input signal by way of the input lead, a set of one or more source electrodes electrically coupled to the base plate, and a set of one or more drain electrodes configured to produce an output signal at the output lead;
a first thermal substrate disposed on the base plate, and thermally and electrically coupled to the set of one or more gate electrodes to reduce a temperature of an active region of the semiconductor power die;
a second thermal substrate disposed on the base plate, and thermally and electrically coupled to the set of one or more drain electrodes to reduce the temperature of the active region of the semiconductor power die;
a first set of one or more electrical conductors by way the set of one or more gate electrodes receive the input signal from the input lead;
a second set of one or more electrical conductors electrically connecting the set of one or more gate electrodes to a metallization layer on the first thermal substrate;
a third set of one or more electrical conductors electrically connecting the set of one or more source electrodes to the base plate;
a fourth set of one or more electrical conductors by way the set of one or more drain electrodes produce the output signal at the output lead; and
a fifth set of one or more electrical conductors electrically connecting the set of one or more drain electrodes to a second metallization layer of the second thermal substrate.

US Pat. No. 10,141,237

FINGERPRINT RECOGNITION MODULE AND MANUFACTURING METHOD THEREFOR

PRIMAX ELECTRONICS LTD., ...

1. A manufacturing method for a fingerprint recognition module, comprising the following steps:(a) directly connecting and fixing a die to a flexible printed circuit (FPC) board, and electrically connecting the die to the FPC board;
(b) coating an adhesive layer on an upper surface of the die;
(c) covering the adhesive layer with a cover plate, to adhere the cover plate to the adhesive layer; and
(d) applying low pressure injection modeling encapsulation to an encapsulation space defined between the cover plate and the FPC board, so as to form an encapsulation layer in the encapsulation space, wherein step (d) further comprises the following steps:
(d1) placing the FPC board, the die, the adhesive layer, and the cover plate together into a mold;
(d2) adjusting pressure of the mold into a range of 1.5 to 40 bars; and
(d3) injecting a hot melt material into the mold to make the hot melt material flow into the encapsulation space and be cured in the encapsulation space to form the encapsulation layer, wherein the encapsulation layer seals the die.

US Pat. No. 10,141,236

FLIP CHIP BALL GRID ARRAY WITH LOW IMPEDENCE AND GROUNDED LID

International Business Ma...

1. A process for providing electrical conductivity and heat transfer between an electrical substrate and an electrically conductive heat spreader comprising operatively associating said electrical substrate and said electrically conductive heat spreader with an article of manufacture comprising a contact spring so that said article of manufacture conducts heat and electricity from said electrical substrate to said electrically conductive heat spreader, wherein said article of manufacture comprises a contact spring structured to both conduct heat from said electrical substrate to said electrically conductive heat spreader and to electrically connect said electrical substrate and electrically conductive heat spreader, wherein said contact spring comprises a flat single element but configured as a plurality of polygons joined to one another, one edge of one polygon to one edge of a contiguous polygon to form a pattern of repeating polygons substantially lying in a plane and extending substantially in a straight line, the length of said contact spring being greater than its width, said contact spring comprising one or multiple device contacts in the body of said contact springthat extend at least from one side edge of said contact spring, or from at least one surface of said contact spring, or both said side edge and said surface said device contacts arranged so that said contact spring comprises at least one device contact to abut up against said electrically conductive heat spreader and at least one device contact to abut up against said electrical substrate.

US Pat. No. 10,141,235

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PANASONIC INTELLECTUAL PR...

1. A method for manufacturing a semiconductor device, the method comprising:a first step of preparing:
a semiconductor substrate;
a semiconductor layer disposed on the semiconductor substrate, the semiconductor layer comprising:
a plurality of well regions in top portions remote from the semiconductor substrate, the plurality of well regions each including a source region; and
a drift region in a part other than the plurality of well regions;
a gate insulating layer disposed on the semiconductor layer; and
a gate electrode disposed on the gate insulating layer;
a second step of removing part of the gate electrode overlapping each of the source regions of the plurality of well regions;
a third step of inspecting a defect produced in any of the first and the second steps, recording coordinates of the defect, and determining an ineffective region based on the coordinates of the defect;
a fourth step of removing the gate electrode in the ineffective region;
a fifth step of forming an insulating film on the gate electrode outside the ineffective region, forming the insulating film on at least part of the gate insulating layer inside the ineffective region, and forming two or more source contact holes in the insulating film both inside and outside the ineffective region so as to expose at least part of each of the source regions of the plurality of well regions; and
a sixth step of forming a source wire such that the source wire is covered the insulating film and is in contact with the exposed source regions of the plurality of well regions through the source contact holes both inside and outside the ineffective region.

US Pat. No. 10,141,234

FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR

International Business Ma...

1. A circuit comprising:a top supply rail and a top ground rail disposed within a top level of the circuit;
a bottom supply rail and a bottom ground rail disposed within a bottom level of the circuit;
at least one input line disposed within a middle level of the circuit;
an output line disposed within the top level of the circuit;
a plurality of p-type vertical FETs coupled to the at least one input line and having at least one p-type vertical FET coupled to the output line, where the plurality of p-type vertical FETs comprises an odd number of plurality of p-type vertical FETs, and wherein at least one p-type vertical FET in the plurality of p-type vertical FETs is coupled to the bottom supply rail; and
at least one n-type vertical FET coupled to one of the bottom ground rail and the top ground rail.

US Pat. No. 10,141,233

ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. An electronic package, comprising:a first circuit structure having a first surface and a second surface opposite to the first surface, wherein the first circuit structure has at least a first redistribution layer;
a plurality of first electronic elements disposed on and directly attached to the first surface of the first circuit structure;
at least a first conductive element disposed on the first surface of the first circuit structure;
a first encapsulant formed on the first surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant, wherein the first encapsulant is in direct contact with the first circuit structure and the first electronic elements;
a first metal layer formed on the first encapsulant, wherein the first metal layer is a circuit layer and in direct contact with the first conductive element and the first encapsulant;
a second circuit structure formed on and being in direct contact with the second surface of the first circuit structure, wherein the second circuit structure has at least a second redistribution layer;
a plurality of second electronic elements bonded to the second circuit structure, wherein each of the second electronic elements is an active element, a passive element, or a combination thereof; and
a second encapsulant formed on the second circuit structure and encapsulating the second electronic elements, wherein the second encapsulant is in direct contact with the second circuit structure and the second electronic elements.

US Pat. No. 10,141,232

VERTICAL CMOS DEVICES WITH COMMON GATE STACKS

International Business Ma...

1. A semiconductor structure, comprising:a first nanowire of a first material disposed on a top surface of a substrate;
at least a second nanowire of a second material different than the first material disposed on the top surface of the substrate; and
a common gate stack surrounding the first nanowire and the second nanowire;
wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the top surface of the substrate;
wherein the first nanowire forms at least a portion of a negative field-effect transistor (NFET) vertical transport channel of a complementary metal-oxide-semiconductor (CMOS) device;
wherein the second nanowire forms at least a portion of a positive field-effect transistor (PFET) vertical transport channel of the CMOS device; and
wherein the first material comprises a group III-V material and the second material comprises a group IV material.

US Pat. No. 10,141,231

FINFET DEVICE WITH WRAPPED-AROUND EPITAXIAL STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, the method comprising:forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region;
forming a gate stack engaging each fin at the respective channel region;
depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins;
performing an etching process to the one or more dielectric layers, wherein the etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surfaces of the gate stack still being covered by the one or more dielectric layers; and
growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.

US Pat. No. 10,141,230

METHOD AND STRUCTURE TO ENABLE DUAL CHANNEL FIN CRITICAL DIMENSION CONTROL

International Business Ma...

1. A semiconductor device, comprising:a substrate having a {100} crystallographic surface orientation;
a first plurality of fins comprising a first semiconductor material; and
a second plurality of fins comprising a second semiconductor material different from the first semiconductor material, wherein:
the first and second plurality of fins extend vertically with respect to the substrate;
the second plurality of fins each comprise a conformal semiconductor layer on lateral sides thereof; and
the first plurality of fins has the same or substantially the same lateral critical dimension as the second plurality of fins combined with the conformal semiconductor layer on the lateral sides thereof.

US Pat. No. 10,141,229

PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming semiconductor devices, the method comprising:epitaxially growing a portion of a first semiconductor layer above a buried insulating layer in a first device region, said first semiconductor layer having a first thickness after said epitaxial growth process is performed;
forming a second semiconductor layer of a second thickness above said buried insulating layer in a second device region, said second thickness differing from said first thickness, wherein forming said second semiconductor layer comprises, prior to epitaxially growing said portion of said first semiconductor layer, epitaxially growing a portion of said second semiconductor layer so as to obtain said second thickness, forming a growth mask above said second semiconductor layer, and selectively epitaxially growing said portion of said first semiconductor layer by using said growth mask;
forming a first transistor element in and on said first semiconductor layer; and
forming a second transistor element in and on said second semiconductor layer, said second transistor element comprising a fully depleted channel region.

US Pat. No. 10,141,228

FINFET DEVICE HAVING SINGLE DIFFUSION BREAK STRUCTURE

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a fin-shaped structure on a substrate;
a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion;
a gate structure on the first portion; and
a contact etch stop layer (CESL) adjacent to the gate structure and extending to cover and directly contacting a top surface of the SDB structure.

US Pat. No. 10,141,227

METHOD AND SYSTEM FOR ACHIEVING SEMICONDUCTOR-BASED CIRCUITS OR SYSTEMS HAVING MULTIPLE COMPONENTS WITH ONE OR MORE MATCHED OR SIMILAR CHARACTERISTICS OR FEATURES

NXP USA, INC., Austin, T...

1. A method of achieving at least one part of a semiconductor system having matched or similar components, the method comprising:directing a pick and place head mechanism, by way of a processing device associated with an assembly machine, to move to a first position at a first column of a first row of a singulated semiconductor wafer having a plurality of rows including the first row and a plurality of columns including a first set of columns each including a plurality of first dice of a first type and a second set of columns each including a plurality of second dice of a second type, the first set of columns including the first column;
directing the pick and place head mechanism to implement a first one of the first dice from the first position at a first location on one or more substrates, wherein the first one of the first dice includes a first component;
determining whether the first one of the first dice was implemented at the first location as directed;
subsequent to determining that the first one of the first dice was implemented at the first location as directed, determining that a first one of the second dice is present at a second position at a second column that is also within the first row and that satisfies a proximity criterion indicative of a maximum distance on the wafer that can separate matched or similar dice, the second set of columns including the second column; and
upon determining that the first one of the second dice is present at the second position at the second column that satisfies the proximity criterion, directing the pick and place head mechanism to implement the first one of the second dice from the second position at the second location, wherein the first one of the second dice includes a second component that is matched or similar to the first component due to the first and second type being matched or similar;
wherein, upon the first one of the first dice and the first one of the second dice being implemented on the one or more substrates, the one or more substrates constitutes or constitute the at least one part of the semiconductor system having the matched or similar components, the matched or similar components including the first and second components.

US Pat. No. 10,141,226

SELF-ALIGNED CONTACTS

Intel Corporation, Santa...

1. A nonplanar transistor comprising:a body;
a pair of spacers on the body;
a gate dielectric layer on a surface of the body between the pair of spacers and along sidewalls of the pair of spacers;
a gate electrode on the gate dielectric layer and between the pair of spacers, wherein the gate electrode is separated from the pair of spacers by portions of the gate dielectric layer along the sidewalls of the pair of spacers;
an insulating cap layer on the gate electrode between the pair of spacers and directly on the portions of the gate dielectric layer along the sidewalls of the pair of spacers; and
a pair of diffusion regions adjacent to the pair of spacers.

US Pat. No. 10,141,225

METAL GATES OF TRANSISTORS HAVING REDUCED RESISTIVITY

Taiwan Semiconductor Manu...

1. A method comprising:forming a transistor comprising:
forming a gate dielectric on a semiconductor region;
forming a gate electrode over the gate dielectric; and
forming a source/drain region extending into the semiconductor region;
forming a source/drain contact plug over and electrically coupling to the source/drain region; and
forming a gate contact plug over and in contact with the gate electrode, wherein at least one of the forming the gate electrode, the forming the source/drain contact plug, or the forming the gate contact plug comprises:
removing a hard mask between opposite portions of gate spacers;
forming a metal nitride barrier layer;
depositing a metal-containing layer over and in contact with the metal nitride barrier layer, wherein the metal-containing layer comprises at least one of a cobalt layer or a metal silicide layer, and wherein the metal nitride barrier layer and the metal-containing layer extend into an opening left by the removed hard mask; and
performing a planarization to remove excess portions of the metal nitride barrier layer and the metal-containing layer.

US Pat. No. 10,141,223

METHOD OF IMPROVING MICRO-LOADING EFFECT WHEN RECESS ETCHING TUNGSTEN LAYER

UNITED MICROELECTRONICS C...

1. A method for improving micro-loading effect when recess etching a tungsten layer, comprising:providing a semiconductor substrate having a main surface, wherein a plurality of trenches is formed in the semiconductor substrate;
blanket depositing a tungsten layer on the semiconductor substrate, wherein the plurality of trenches is filled with the tungsten layer;
subjecting the tungsten layer to a planarization process to form a planarization layer on the tungsten layer;
performing a first etching process to completely remove the planarization layer and partially remove the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1; and
performing a second etching process to etch remainder of the tungsten layer until a top surface of the tungsten layer is lower than the main surface of the semiconductor substrate.

US Pat. No. 10,141,222

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a carrier;
providing a semiconductor die;
disposing a first interconnect structure over an active surface of the semiconductor die;
disposing the semiconductor die over the carrier with the active surface of the semiconductor die oriented toward the carrier;
forming a second interconnect structure over a second surface of the semiconductor die opposite the active surface;
forming a first insulating layer over the second interconnect structure;
forming a protective layer on the first insulating layer;
forming a via in order through the protective layer, second interconnect structure, first interconnect structure, and partially into the carrier;
removing the protective layer after forming the via;
removing the carrier after forming the via;
forming a first conductive layer in the via and extending over the semiconductor die directly on a major surface of the first insulating layer; and
forming an opening in the first insulating layer, wherein the first conductive layer extends into the opening to contact the second interconnect structure.

US Pat. No. 10,141,221

METHOD FOR MANUFACTURING THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND STRUCTURE MANUFACTURED BY THE SAME

MACRONIX INTERNATIONAL CO...

1. A method of manufacturing a three-dimensional (3D) stacked semiconductor structure, comprising:forming a multi-layered stack above a substrate, and the multi-layered stack comprising a plurality of nitride layers and polysilicon layers arranged alternately;
forming a plurality of channel holes vertically to the substrate;
patterning the multi-layered stack to form linear spaces between the plurality of channel holes and vertical to the substrate, wherein the linear spaces extend downwardly to expose sidewalls of the plurality of nitride layers and the plurality of polysilicon layers;
replacing the plurality of polysilicon layers with insulating layers having air-gaps through the linear spaces; and
replacing the plurality of nitride layers with conductive layers through the linear spaces.

US Pat. No. 10,141,220

VIA PATTERNING USING MULTIPLE PHOTO MULTIPLE ETCH

Taiwan Semiconductor Manu...

1. A method comprising:forming a dielectric layer;
forming a trench in the dielectric layer;
forming a photo resist having a first portion over the dielectric layer, and a second portion in the trench;
forming a first mask layer over the photo resist;
forming a first opening in the first mask layer; and
etching the photo resist and the dielectric layer to extend the first opening to a bottom of the dielectric layer.

US Pat. No. 10,141,219

COMBINED PRODUCTION METHOD FOR SEPARATING A NUMBER OF THIN LAYERS OF SOLID MATERIAL FROM A THICK SOLID BODY

Siltectra GmbH, Dresden ...

1. A method for producing layers of solid material comprising:providing a solid body to be split into a number of layers of solid material, the solid body having a first level surface portion and a second level surface portion;
introducing or generating defects in the solid body using laser beams in order to determine a first detachment plane along which a first layer of solid material is separated from the solid body, the laser beams penetrating into the solid body via the second level surface portion;
providing a receiving layer for holding the layer of solid material on the second level surface portion of the solid body, the receiving layer being in the form of a polymer layer;
applying heat to the receiving layer in order to mechanically generate stresses in the solid body, the application of heat including cooling of the receiving layer to a temperature below ambient temperature, the cooling taking place such that the polymer layer undergoes a glass transition and such that due to the stresses a crack propagates in the solid body along the detachment plane, the crack separating the first layer of solid material from the solid body, wherein the second level surface portion is part of the first layer, wherein the first detachment plane is determined closer to the second level surface portion than to the first level surface portion;
introducing or generating defects in the solid body in order to determine a second detachment plane along which a second layer of solid material is separated from the solid body, then providing a second receiving layer for holding another layer of solid material on the solid body reduced by the first layer of solid material; and
applying heat to the second receiving layer in order to mechanically generate stresses in the solid body such that due to the stresses a crack propagates in the solid body along the second detachment plane, the crack separating the second layer of solid material from the solid body.

US Pat. No. 10,141,218

ROOM TEMPERATURE METAL DIRECT BONDING

INVENSAS BONDING TECHNOLO...

1. A method of bonding substrates, comprising:providing a first substrate having a first non-metallic region proximate to a first plurality of metallic pads;
providing a second substrate having a second non-metallic region proximate to a second plurality of metallic pads;
directly contacting the first non-metallic region with the second non-metallic region, wherein a first pad of the first plurality of metallic pads is spaced from a second pad of the second plurality of metallic pads by a gap after directly contacting the first non-metallic region with the second non-metallic region;
non-adhesively bonding the first non-metallic region to the second non-metallic region along an interface without an adhesive and without application of external pressure; and
after directly contacting the first non-metallic region with the second non-metallic region, directly contacting the first pad with the second pad to form a contact between the first pad and the second pad, the interface between the first non-metallic region and the second non-metallic region extending substantially to the contact.

US Pat. No. 10,141,217

DICING-TAPE INTEGRATED FILM FOR BACKSIDE OF SEMICONDUCTOR AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

NITTO DENKO CORPORATION, ...

1. A dicing-tape integrated film for a backside of a semiconductor havinga dicing tape having a substrate and pressure-sensitive adhesive layer formed on the substrate and
a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, wherein the pressure-sensitive adhesive layer comprises a silicone pressure-sensitive adhesive layer at the interface with the film for the backside of a flip-chip semiconductor, and wherein
the difference (?2??1) of the surface free energy ?2 and the surface free energy ?1 is 10 mJ/m2 or more, in which ?1 represents the surface free energy that is calculated from contact angles of water and iodomethane measured using a contact angle gauge according to a geometric mean method on the pressure-sensitive adhesive layer, and ?2 represents the surface free energy that is calculated from contact angles of water and iodomethane measured using a contact angle gauge according to a geometric mean method on the film for the backside of a flip-chip semiconductor after the pressure-sensitive adhesive layer and the film for the backside of a flip-chip semiconductor are peeled from each other at the interface.

US Pat. No. 10,141,215

COMPLIANT NEEDLE FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICES

1. An apparatus configured to transfer an electrically-actuatable element directly from a first side of a wafer tape to a product substrate having a circuit trace thereon, the apparatus comprising:a needle disposed adjacent a second side of the wafer tape opposite the first side of the wafer tape;
a needle actuator to move the needle to a position at which the needle presses on the second side of the wafer tape to press the electrically-actuatable element into contact with the circuit trace disposed adjacent the first side of the wafer tape; and
a dampener arranged with an end of the needle and an end of the needle actuator, the dampener dampening a force applied to the electrically-actuatable element when the needle presses the electrically-actuatable element into contact with the circuit trace.

US Pat. No. 10,141,213

APPARATUS FOR STORING AND HANDLING ARTICLE AT CEILING

DAIFUKU CO., LTD., Osaka...

1. An apparatus for storing and handling an article at a ceiling, comprising:an internal rail configured to hang on the ceiling;
a storage system configured to hang on the ceiling and including a shelf of a first row and a shelf of a second row disposed on both sides of the internal rail to face each other and a transport in/out port connected to any one of the shelf of the first row and the shelf of the second row; and
an internal transfer robot configured to be movably connected to the internal rail and convey the article between any one of the shelf of the first row and the shelf of the second row and the transport in/out port; and
a purge unit configured to supply purge gas to the article seated on the shelf of the first row and the shelf of the second row,
wherein the internal transfer robot includes:
a two-way sliding unit configured to slide a holding unit holding the article toward any one of the shelf of the first row and the shelf of the second row; and
an elevation-driving unit configured to elevate the two-way sliding unit along a height direction of the shelf of the first row and the shelf of the second row,
wherein the purge unit includes:
a gas tank configured to communicate with the article and providing the purge gas to the article;
a recovering pump configured to communicate with the article to recover the purge gas supplied to the article; and
a controller configured to operate the recovering pump when a predetermined time elapses after the purge gas is supplied to the article.

US Pat. No. 10,141,212

AUTOMATED MATERIAL HANDLING SYSTEM FOR SEMICONDUCTOR MANUFACTURING BASED ON A COMBINATION OF VERTICAL CAROUSELS AND OVERHEAD HOISTS

Murata Machinery Ltd., K...

7. A system comprising:an overhead rail in a semiconductor fabrication plant;
an overhead hoist transport (OHT) vehicle coupled to the overhead rail, wherein the OHT vehicle comprises:
a body;
a gripper configured to hold a material unit;
a hoist coupled to the movable stage and to the gripper;
a moveable stage coupled to the hoist and the body, wherein the OHT transport vehicle is configured to move the moveable stage along a horizontal axis to positions exterior to the body on either side of the body of OHT transport vehicle;
wherein the movable stage is configured to move along the horizontal axis from a first position within to the body to a second position that is exterior to the body of the OHT vehicle and adjacent to a side of the OHT vehicle; and
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage;
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage when the moveable stage is in the first position;
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage when the moveable stage is in the second position that is adjacent to a side of the OHT vehicle;
wherein the OHT vehicle is configured to move the material unit from a starting position to an ending position, wherein the starting position comprises a horizontal starting position and a vertical starting position, and the ending position comprises a horizontal ending position and a vertical ending position;
wherein the hoist is configured to move the gripper vertically to a work station; and
wherein the movable stage and the hoist are configured to work in concert to move the gripper to a fixed shelf.

US Pat. No. 10,141,211

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSFER METHOD

EBARA CORPORATION, Tokyo...

1. A substrate processing apparatus, comprising:a substrate holder configured to hold a substrate;
a fixing unit configured to mount and remove the substrate on and from the substrate holder,
a substrate dryer configured to dry the substrate;
a robot configured to transfer the substrate at least between the fixing unit and the substrate dryer;
a processing bath configured to process the substrate while the substrate holder is holding the substrate such that the substrate is in a vertical orientation; and
a substrate transfer device including a grasping section configured to grasp the substrate holder, and a transferring section configured to transfer the substrate holder grasped by the grasping section,
wherein the substrate transfer device is configured to transfer the substrate holder at least between the fixing unit and the processing bath,
the grasping section is configured to rotate the substrate holder between the vertical orientation and a horizontal orientation, which is angularly offset from the vertical orientation while the substrate holder is holding the substrate, and
the transferring section is configured to transfer the substrate holder and the substrate while the substrate holder is holding the substrate from the processing bath to the fixing unit, with the substrate in the horizontal orientation, along a path that is above the processing bath.

US Pat. No. 10,141,210

PURGE MODULE AND LOAD PORT HAVING THE SAME

RORZE SYSTEMS CORPORATION...

1. A purge module comprising:a jig detachably attached to an upper side of a stage of a load port, the jig comprising a gas inlet for providing a wafer carrier with gas and a gas outlet for receiving gas from the wafer carrier;
a gas control box detachably attached to the load port to control gas flow; and
pipes connecting the jig and the gas control box,
wherein at least one of the gas inlet and the gas outlet further comprises a sealing member making contact with the wafer carrier, when the wafer carrier is disposed thereon, the sealing member including an elastic material;
a sealing protection member disposed surrounding the sealing member; and
wherein the sealing protection member is higher than the sealing member with respect to a surface of the jig.

US Pat. No. 10,141,209

PROCESSING GAS GENERATING APPARATUS, PROCESSING GAS GENERATING METHOD, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. An apparatus for generating a processing gas by bubbling a raw material liquid with a carrier gas, the apparatus comprising:a raw material liquid tank configured to store the raw material liquid;
a raw material liquid supplying path provided between a raw material liquid bottle that stores the raw material liquid and the raw material liquid tank and configured to supply the raw material liquid into the raw material liquid tank from the raw material liquid bottle,
a cover provided at a top portion of the raw material liquid tank and configured to block an opening formed on a top surface of the raw material liquid tank;
a carrier gas source connected to the raw material liquid tank through a carrier gas supply path and configured to supply the carrier gas to the raw material liquid in the raw material liquid tank;
a taking-out path provided inside the cover and configured to take out the processing gas generated by the bubbling from a vapor-phase portion above a liquid-phase portion which is a region where the raw material liquid is stored in the raw material liquid tank, an end of the taking-out path being connected to the vapor-phase portion and the other end of the taking-out path being connected to a processing gas supply path to supply the processing gas to a substrate provided outside of the apparatus for generating the processing gas through the processing gas supply path;
a first temperature controller having a square column shape to cover a side wall and a bottom wall of the raw material liquid tank and configured to perform a temperature adjustment of the liquid-phase portion through at least one of the side wall and the bottom wall of the raw material liquid tank; and
a second temperature controller having a plate shape to cover an upper surface of the cover and configured to perform a temperature adjustment of the vapor-phase portion through the upper surface of the cover such that a temperature of the vapor-phase portion is higher than a temperature of the liquid-phase portion,
wherein the raw material liquid supplying path includes a raw material liquid temperature controller provided from an outside of a sidewall surface of the first temperature controller to an inside of the raw material liquid tank and configured to adjust a temperature of the raw material liquid such that the temperature of the raw material liquid supplied to the raw material liquid tank approaches the temperature of the liquid-phase portion.

US Pat. No. 10,141,208

VACUUM PROCESSING APPARATUS

Canon Anelva Corporation,...

1. A vacuum processing apparatus comprising:a vacuum vessel in which vacuum processing can be performed;
a substrate holder capable of holding a substrate;
a tilting unit capable of making said substrate holder pivot about a pivotal axis and tilting the substrate held by said substrate holder with respect to a process source provided in said vacuum vessel;
a cooling device provided in said substrate holder and configured to act together with a compression device provided outside said vacuum vessel to cool the substrate held by said substrate holder; and
a rotary joint provided in said tilting unit and including a supply path configured to supply a coolant gas from said compression device to said cooling device and an exhaust path configured to exhaust the coolant from said cooling device to said compression device,
wherein said rotary joint comprises:
a fixed portion fixed to said vacuum vessel;
a pivotal portion provided so as to pivot with respect to said fixed portion and fixed to said substrate holder; and
a gas guide path provided in one of said fixed portion and said pivotal portion and configured to communicate a space region formed between the supply path and the exhaust path and guide the coolant gas that has leaked from one of the supply path and the exhaust path in the space region, where said fixed portion faces said pivotal portion and the supply path and the exhaust path are separated, to an outside of said rotary joint.

US Pat. No. 10,141,207

OPERATION METHOD OF PLASMA PROCESSING APPARATUS

Hitachi High-Technologies...

1. An operation method of a vacuum processing apparatus, the apparatus comprising:a vacuum vessel having an inside configured to be decompressed;
a processing chamber that is arranged in an inner part of the vacuum vessel, wherein a wafer to be processed is arranged and processed inside thereof;
a plasma generating chamber that is arranged above the processing chamber, wherein plasma is generated by using processing gas supplied into an inner part thereof;
a sample stage that is arranged at a lower part inside of the processing chamber, the sample stage having a top surface for mounting the wafer;
a dielectric plate member that is arranged above the top surface of the sample stage between the processing chamber and the plasma generating chamber in the vacuum vessel, the dielectric plate member having a plurality of through-holes wherein particles of the plasma are introduced into the processing chamber therethrough; and
a ring-shaped window member that is arranged on an outer peripheral side of the plate member around the plate member above the processing chamber, the ring-shaped window member constituted of a lamp for irradiating and heating the wafer with an electromagnetic wave, and a member facing inside of the processing chamber and being configured to transmit the electromagnetic wave from the lamp, wherein
a side surface surrounding a lower surface of the window member and the plate member is constituted of a member that transmits the electromagnetic wave, of the window member, the method comprising:
performing a process of generating a reaction product on a surface of the wafer by supplying, from the through-holes to the wafer mounted on the sample stage, the particles of the plasma that has been generated in the plasma generating chamber by using the processing gas;
then performing a process of extinguishing the plasma in the plasma generating chamber and heating the wafer with the electromagnetic wave to desorb the reaction product; and
then performing a process of supplying a cleaning gas into the plasma generating chamber to supply particles of plasma of the cleaning gas generated in the plasma generating chamber into the processing chamber and to an inner wall surface of the window member facing an interior space of the processing chamber.

US Pat. No. 10,141,206

SUBSTRATE PROCESSING APPARATUS AND GAP WASHING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus comprising:a substrate holding unit which holds a substrate in a horizontal posture;
a body which includes an outer circumferential surface including an opposing portion opposite a central portion of an upper surface of the substrate, wherein the body is extended in an up/down direction, and the body has an outline that is cylindrical;
an opposing member which includes an inner circumferential surface that surrounds an outer circumference of the body and forms a cylindrical gap with the outer circumferential surface of the body and which opposes the upper surface of the substrate;
a washing liquid discharge port which is formed in the outer circumferential surface of the body and discharges a washing liquid downward in an oblique and radial direction of the body and towards the inner circumferential surface of the opposing member;
a washing liquid supply unit which supplies the washing liquid to the washing liquid discharge port;
a rotation unit which relatively rotates the opposing member and the body around a rotational axis passing through the central portion of the upper surface of the substrate; and
a washing control unit which controls the washing liquid supply unit and the rotation unit so as to wash the cylindrical gap,
wherein the washing control unit performs a rotation step of controlling the rotation unit so as to relatively rotate the opposing member and the body and a washing liquid discharging step of controlling the washing liquid supply unit so as to discharge the washing liquid from the washing liquid discharge port simultaneously with the rotation step.

US Pat. No. 10,141,205

APPARATUS AND METHOD FOR CLEANING SEMICONDUCTOR WAFER

ACM Research (Shanghai) I...

1. An apparatus for cleaning semiconductor wafer comprising:a brush module having a brush head for providing mechanical force on a surface of a wafer;
a swing arm of which an end mounts the brush module, wherein the brush module is vertically disposed and includes a brush base, a bearing, a flexible component, at least one damper, a mounting section, a brush shell and a coil spring, the brush head is mounted on the brush base, an end of the bearing connects with the brush base and the other end of the bearing penetrates into the brush shell and connects to a side of the flexible component, the other side of the flexible component connects with the damper which is mounted on the brush shell, the coil spring is received in the brush shell, an end of the coil sing is fixed on the side of the flexible component and the other end of the coil spring is fixed on the mounting section which is the top plate of the brush shell and opposite to the flexible component, the brush shell is fixed at the end of the swing arm, an elastic deformation of the coil spring generates a press force that the brush head acts on the surface of the wafer, and the elastic deformation of the coil spring is determined by a height of a process position of the brush module;
a rotating actuator connected with the other end of the swing arm, the rotating actuator driving the swing arm to swing across the whole surface of the wafer, which brings the brush head moving across the whole surface of the wafer; and
an elevating actuator connected with the other end of the swing arm, the elevating actuator driving the swing arm to rise or descend, which brings the brush module rising or descending.

US Pat. No. 10,141,203

ELECTRICAL INTERCONNECT STRUCTURE FOR AN EMBEDDED ELECTRONICS PACKAGE

General Electric Company,...

1. An electronics package comprising:an upper insulating layer;
at least one electrical component positioned within an opening in the upper insulating layer;
a patterned contact layer comprising at least one electrical connection formed on a first surface of the upper insulating layer;
a lower insulating layer coupled to the upper insulating layer and the at least one electrical component;
an upper interconnect layer formed on a second surface of the upper insulating layer and electrically coupled to the patterned contact layer; and
a lower interconnect layer formed on the lower insulating layer and electrically coupled to the upper interconnect layer and the at least one electrical component.

US Pat. No. 10,141,202

SEMICONDUCTOR DEVICE COMPRISING MOLD FOR TOP SIDE AND SIDEWALL PROTECTION

QUALCOMM Incorporated, S...

12. An apparatus comprising:a substrate;
a plurality of metal layers and dielectric layers coupled to the substrate;
a pad coupled to one of the plurality of metal layers;
a passivation layer on a surface of the plurality of metal layers and dielectric layers and coupled to the pad;
a first metal redistribution layer above the passivation layer and coupled to the pad;
a first insulation layer between the passivation layer and the first metal redistribution layer;
a second insulation layer at least partially above the first metal redistribution layer, wherein the second insulation layer further comprises a side formed by a trough;
an under bump metallization (UBM) layer above the second insulation layer, coupled to the first metal redistribution layer via a cavity in the second insulation layer; and
a means for protecting the apparatus from cracking during a cutting process, the means for protecting covering a first surface of the apparatus, at least a side portion of the apparatus including the side of the second insulation layer, and a portion of the UBM layer,
wherein at least a portion of the second insulation layer is between the first metal redistribution layer and the means for protecting,
wherein the side of the second insulation layer is spaced apart from a plane including both an exterior sidewall of the means for protecting and an exterior sidewall of the plurality of metal layers and dielectric layers by a portion of the means for protecting.

US Pat. No. 10,141,201

INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a workpiece, wherein forming the workpiece comprises:
attaching a first surface of an integrated circuit die to a carrier;
encapsulating the integrated circuit die in a first encapsulant, a second surface of the integrated circuit die being level with a surface of the first encapsulant, the second surface of the integrated circuit die being opposite the first surface of the integrated circuit die;
forming one or more redistribution layers over the integrated circuit die and the first encapsulant, the one or more redistribution layers physically contacting the second surface of the integrated circuit die and the surface of the first encapsulant; and
after forming the one or more redistribution layers, removing the carrier from the integrated circuit die and the first encapsulant;
after forming the workpiece, attaching the workpiece to a heat dissipation feature, the heat dissipation feature being directly attached to the first surface of the integrated circuit die using a thermal adhesive, wherein a width of the heat dissipation feature is greater than a width of the workpiece;
mounting the workpiece on a first side of a package substrate, the package substrate comprising a through hole, wherein the heat dissipation feature is not directly attached to the package substrate;
forming a second encapsulant on the first side of the package substrate, wherein the second encapsulant surrounds the workpiece;
planarizing a top surface of the second encapsulant to be level with a top surface of the heat dissipation feature; and
mounting a die stack to the workpiece, the die stack comprising one or more integrated circuit dies, wherein the die stack is at least partially disposed in the through hole of the package substrate.

US Pat. No. 10,141,200

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a plurality of conductive structures on a substrate, each of the conductive structures including a first conductive pattern and a hard mask sequentially stacked;
forming a plurality of preliminary spacer structures on sidewalls of the conductive structures, respectively, the preliminary spacer structures including first spacers, sacrificial spacers and second spacers sequentially stacked;
forming a plurality of pad structures on the substrate between the preliminary spacer structures, respectively, the plurality of pad structures defining openings exposing upper portions of the sacrificial spacers;
forming a capping layer on surfaces of the pad structures;
forming a first mask pattern on the pad structures, the first mask pattern covering the surfaces of the pad structures and exposing the upper portions of the sacrificial spacers; and
removing the sacrificial spacers to form first spacer structures having respective air spacers, the first spacer structures including the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

US Pat. No. 10,141,199

SELECTING A SUBSTRATE TO BE SOLDERED TO A CARRIER

Infineon Technologies AG,...

1. A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder, wherein the insulating substrate comprises a dielectric insulation carrier, a top side, and a bottom side opposite to the top side, the method comprising:selecting the insulating substrate based on a criterion which indicates that the insulating substrate having the solidus temperature of the solder, has a positive unevenness;
soldering the insulating substrate on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion; and
populating the top side of the insulating substrate with at least one semiconductor chip,
wherein the criterion indicates that when the insulating substrate is heated proceeding from an initial temperature which is lower than the solidus temperature of the solder up to a predefined maximum temperature which is higher than the liquidus temperature of the solder, and then cooled to the solidus temperature of the solder, such that the insulating substrate has a positive unevenness when the solidus temperature of the solder is reached again.

US Pat. No. 10,141,198

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

1. An electronic package, comprising:a middle patterned conductive layer having a first surface, a second surface opposite to the first surface and a plurality of middle conductive pads;
a first redistribution circuitry disposed on the first surface of the middle patterned conductive layer and comprising a first patterned conductive layer, wherein the first patterned conductive layer has a plurality of first conductive elements, each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section, and each of the first conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad; and
a second redistribution circuitry disposed on the second surface of the middle patterned conductive layer and comprising a second patterned conductive layer, wherein the second patterned conductive layer has a plurality of second conductive elements, each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section, and each of the second conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad.

US Pat. No. 10,141,197

THERMOSONICALLY BONDED CONNECTION FOR FLIP CHIP PACKAGES

STMICROELECTRONICS S.R.L....

1. A method of making a package, comprising:plating a plurality of finish plating layers on a first surface of a leadframe;
etching the first surface of the leadframe to form leads, wherein ends of the leads include the finish plating layers;
inserting the finish plating layers into openings in a passivation layer on a surface of a semiconductor die;
thermosonically bonding the finish plating layers directly to bond pads of the semiconductor die by a thermosonic bonding process, wherein the finish plating layers are bonded directly to the bond pads without conductive bumps or conductive bonding wires therebetween; and
encapsulating the semiconductor die and the leads in an encapsulant.

US Pat. No. 10,141,196

POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A method for manufacturing a power semiconductor device, the method comprising the following steps:providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side;
forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane (B; B?) parallel to the first main side;
forming an isolation layer on the first main side to cover the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane (A) parallel to the first main side;
after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and
thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel,
wherein the second plane (A) is at most 1 ?m further away from the wafer than the first plane (B; B?), wherein
the step of forming the metallization layer comprises:
a first step of forming a lower portion of the metallization layer on the first main side in the active cell area before the step of forming the isolation layer; and
a second step of forming an upper portion of the metallization layer on the lower portion of the metallization layer in the active cell area after the step of forming the isolation layer.

US Pat. No. 10,141,195

SUBSTRATE PROCESSING METHOD

Tokyo Electron Limited, ...

1. A substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, comprising:depositing a carbon-based deposit on the surface of the substrate;
removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which the first silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and
removing the deposited carbon-based deposit,
wherein the recess has an aspect ratio of 4 or more.

US Pat. No. 10,141,194

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

UNITED MICROELETRONICS CO...

1. A manufacturing method of a semiconductor structure, comprising:forming a first polysilicon layer on a substrate;
performing a planarization process to the first polysilicon layer;
performing a first etching back process to the first polysilicon layer after the planarization process, wherein the first polysilicon layer has a first thickness after the planarization process and before the first etching process;
performing a second etching back process to the first polysilicon layer after the first etching back process, wherein the thickness of the first polysilicon layer is reduced by the second etching back process, wherein the first polysilicon layer has a second thickness after the first etching back process and before the second etching back process, the first polysilicon layer has a third thickness after the second etching back process, and the difference between the first thickness and the second thickness is smaller than the difference between the second thickness and the third thickness; and
performing a first wet clean process to the first polysilicon layer after the first etching back process and before the second etching back process.

US Pat. No. 10,141,193

FABRICATING METHOD OF A SEMICONDUCTOR DEVICE WITH A HIGH-K DIELECTRIC LAYER HAVING A U-SHAPE PROFILE

UNITED MICROELECTRONICS C...

1. A fabricating method of a semiconductor device, comprising:forming an inter layer dielectric layer on a substrate;
forming a trench in the inter layer dielectric layer;
forming a high-k dielectric layer having a U-shape profile in the trench;
transforming two ends of the U-shape profile to a metal layer, wherein the transforming step is a reduction;
after transforming the two ends of the U-shape profile to the metal layer, forming a work function metal layer on the high-k dielectric layer and the metal layer; and
removing a portion of the metal layer to expose an upper portion of sidewalls of the trench.

US Pat. No. 10,141,192

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A manufacturing method of a semiconductor device including a nitride semiconductor layer, the manufacturing method comprising:implanting impurities into the nitride semiconductor layer;
performing a first annealing on the nitride semiconductor layer while an implantation surface on the nitride semiconductor layer remains exposed, the first annealing being at a first temperature within an atmosphere of a nitrogen atom containing gas;
forming a protective film on the nitride semiconductor layer after the first annealing; and
after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature.

US Pat. No. 10,141,191

METHOD OF THERMAL PROCESSING STRUCTURES FORMED ON A SUBSTRATE

APPLIED MATERIALS, INC., ...

1. A method of thermally processing a substrate, comprising:positioning the substrate on a substrate support comprising a heating element and increasing the temperature of the substrate;
delivering a first energy from a first energy source to the substrate; and
delivering a second energy from a second energy source to the substrate, wherein the first energy or the second energy is annealing energy and the annealing energy is polarized laser energy, and wherein the first energy and the second energy individually are insufficient to cause any portion of the substrate to melt.

US Pat. No. 10,141,190

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A method of manufacturing a semiconductor device comprising:forming a multilayer structure by stacking first insulating films and second insulating films or metal films;
forming a hole through the multilayer structure in a stacking direction;
forming a block insulating film, a charge storage film, and a tunnel insulating film on an inner surface of the hole;
forming the semiconductor layer containing the impurity on the tunnel insulating film on the inner surface of the hole;
forming an oxide film on the semiconductor layer containing an impurity;
performing a heat treatment on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or ultraviolet irradiation on the oxide film; and
removing the oxide film after the heat treatment.

US Pat. No. 10,141,189

METHODS FOR FORMING SEMICONDUCTORS BY DIFFUSION

ASM IP HOLDING B.V., Alm...

1. A method for making a semiconductor device, comprising:forming a transistor channel region, wherein forming the transistor channel region comprises:
providing a silicon protrusion;
forming an oxide layer on a surface of the silicon protrusion;
selectively removing, relative to other exposed materials, material forming exposed surfaces of the oxide layer to reduce an overall thickness of the oxide layer;
subsequently depositing silicon-germanium on the oxide layer; and
converting the silicon protrusion into a silicon germanium structure by annealing the silicon-germanium and silicon structure in an oxidizing environment to drive the germanium through the oxide layer and into the silicon protrusion.

US Pat. No. 10,141,188

RESIST HAVING TUNED INTERFACE HARDMASK LAYER FOR EUV EXPOSURE

International Business Ma...

1. A method to prepare a substrate for photolithography, comprising:forming an underlayer over a surface of the substrate;
depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and
forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where
the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer;
where depositing the interface hardmask layer is accomplished at a temperature less than a melting temperature of a material that comprises the underlayer.

US Pat. No. 10,141,187

MASK PATTERN FORMING METHOD, FINE PATTERN FORMING METHOD, AND FILM DEPOSITION APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A mask pattern forming method comprising steps of:loading a substrate which has a thin film and a pattern on the thin film, into a process chamber, the pattern having a line and a space therein;
slimming the pattern using a first oxygen-containing gas plasma in the process chamber for a predetermined period of time such that the line is slimmed to have a predetermined width; and
forming an oxide film on the slimmed pattern and the thin film in the process chamber by performing a cycle of adsorbing an aminosilane based precursor on the thin film and the slimmed pattern and oxidizing the aminosilane based precursor on the thin film and the slimmed pattern using a second oxygen-containing gas plasma a predetermined number of times such that the deposited oxide film has a predetermined thickness,
wherein the steps of slimming the pattern and forming the oxide film are performed in the same process chamber, and
wherein temperatures at which the pattern is slimmed and at which the oxide film is formed on the pattern are 100 degrees C. or less.

US Pat. No. 10,141,185

OXIDE SEMICONDUCTOR, COATING LIQUID, METHOD OF FORMING OXIDE SEMICONDUCTOR FILM, SEMICONDUCTOR ELEMENT, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE AND IMAGE DISPLAY SYSTEM

RICOH COMPANY, LTD., Tok...

1. An oxide semiconductor comprising an oxide having a layered structure expressed by an expression
wherein an atom A is a positive monovalent element, an atom Z is a positive divalent element, an atom B is a positive trivalent element, L is a positive integer, and mi and ni are independent integers greater than or equal to zero, that satisfy

US Pat. No. 10,141,184

METHOD OF PRODUCING SELF-SUPPORTING NITRIDE SEMICONDUCTOR SUBSTRATE

TOHOKU UNIVERSITY, Miyag...

1. A method of producing a free-standing nitride semiconductor substrate, comprising: a first step of forming a buffer layer of a nitride semiconductor that is one of GaN, AlN, InGaN, and InN on a main surface of a single crystalline substrate;a second step of forming a crystallized layer including a plurality of growth islands each of which is a hexagonal platelet with an N-polar upper surface, by annealing the buffer layer and thereby converting the buffer layer into a single crystal;
a third step of fabricating a continuous layer including the plurality of growth islands by promoting the lateral growth of the plurality of growth islands along the main surface of the single crystalline substrate and thereby performing coalescence of the plurality of growth islands;
a fourth step of forming a boule of the nitride semiconductor on the continuous layer by performing the crystal growth of the nitride semiconductor with an N-polar upper surface on the continuous layer;
a fifth step of removing the single crystalline substrate from the boule; and
a sixth step of fabricating a plurality of free-standing nitride semiconductor substrates by cutting the boule,
wherein the single crystalline substrate is made of a single crystalline ScAlMgO4,
wherein
the nitride semiconductor is one of GaN, InGaN, and InN, and
the fourth step includes steps of (a) forming an AlN layer on the continuous layer, (b) oxidizing a surface of the AlN layer, (c) nitriding the surface of the AlN layer which has been oxidized, and (d) performing the crystal growth of the nitride semiconductor with an N-polar upper surface on the AlN layer.

US Pat. No. 10,141,183

METHODS OF SPIN-ON DEPOSITION OF METAL OXIDES

Tokyo Electron Limited, ...

1. A method for depositing material on a substrate, the method comprising:receiving a substrate having a relief pattern that defines openings that uncover an underlying layer, the relief pattern providing sidewall surfaces that define the openings, the underlying layer providing floor surfaces that define the openings, the sidewall surfaces having a first surface energy value, the floor surfaces having a second surface energy value;
identifying a fill material comprising a metal hard mask material to fill the defined openings by being deposited on the substrate via spin-on deposition;
executing a surface energy modification treatment, the surface energy modification treatment modifying at least one of the first surface energy value and the second surface energy value such that a contact angle value of an interface between the fill material in liquid form and the sidewall surfaces or the floor surfaces is less than 60 degrees; and
depositing the fill material on the substrate via spin-on deposition after executing the surface energy modification treatment such that the fill material fills the defined openings being in contact with the sidewall surfaces and the floor surfaces.

US Pat. No. 10,141,182

MICROELECTRONIC SYSTEMS CONTAINING EMBEDDED HEAT DISSIPATION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A method for fabricating a microelectronic system, comprising:obtaining a substrate having a tunnel therethrough:
attaching a microelectronic component to a frontside of the substrate at a location enclosing the tunnel utilizing a solder material having a first thermal conductivity; and
producing an embedded heat dissipation structure at least partially contained within the tunnel after attaching the microelectronic component to the substrate, producing comprising:
applying a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate;
curing the bond layer precursor material to form a thermally-conductive component bond layer in contact with the microelectronic component; and
formulating the bond layer precursor material such that, after curing, the thermally-conductive component bond layer has a second thermal conductivity substantially equivalent to or exceeding the first thermal conductivity.

US Pat. No. 10,141,181

TIN PULL-BACK AND CLEANING COMPOSITION

BASF SE, Ludwigshafen (D...

1. A composition, comprising the following components a)-f), based on total weight of the composition:a) 0.05-4 wt. % of an aliphatic or aromatic sulfonic acid;
b) 0.1 to 10 wt % of an inhibitor selected from the group consisting of imidazolidinones, imidazolidines, and 2-oxazolidinones;
c) 5 to 50 wt % of an aprotic solvent;
d) 1 to 60 wt % of a glycol ether;
e) water; and
an oxidant,
wherein a weight ratio of the aprotic solvent to the water is from 1:10 to 2:1 and wherein the oxidant is present in a volume ratio of components a) to e)to the oxidant ranging from 65:1 to 8:1.

US Pat. No. 10,141,180

SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME

GLOBALWAFERS JAPAN CO., L...

1. A method of manufacturing a silicon wafer comprising:subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by a Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds and then cooled at a cooling rate of 3 to 5° C./second, wherein the rapid thermal process is performed in an oxygen-containing atmosphere comprising oxygen gas having a partial pressure of 20 to 100%;
calculating a surface layer of the wafer having a thickness of not less X [?m] according to the following equations (1) to (3):
X [?m]=a [?m]+b [?m]  (1);
a [?m]=(0.0031×(said maximum temperature) [° C.]?3.1)×6.4×(cooling rate)?0.4 [° C./second]  (2); and
b [?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]  (3); and
removing the surface layer having the thickness of not less than X,
to obtain a silicon wafer comprising a laser scattering tomography defect (LSTD) density of less than 1×10?1/cm2 and a slip dislocation length of 5 mm or less.

US Pat. No. 10,141,178

MINIATURE CHARGED PARTICLE TRAP WITH ELONGATED TRAPPING REGION FOR MASS SPECTROMETRY

The University of North C...

1. A mass spectrometry system, comprising:an ion source;
an ion detector; and
an ion trap positioned along a longitudinal axis of the system between the ion source and the ion detector,
wherein the ion trap comprises:
a central electrode extending in a plane and comprising a central aperture extending through the central electrode along the longitudinal axis for a distance of less than 10 mm, the central aperture having a length in the plane and a width in the plane; and
a first endcap electrode comprising a first aperture having a length and a width, wherein the first aperture length and the first aperture width are parallel to the central aperture length and the central aperture width, respectively;
wherein the central aperture comprises a linear aperture segment having a length and a width, the linear aperture segment length being measured between end points of the linear aperture segment in the plane of the central electrode, and the linear aperture segment width being measured in a direction perpendicular to the length in the plane;
wherein a ratio of the linear aperture segment length to the linear aperture segment width is greater than 1.5; and
wherein at least one of:
the first aperture length is greater than the central aperture length; and
the first aperture width is greater than the central aperture width.

US Pat. No. 10,141,177

MASS SPECTROMETER USING GASTIGHT RADIO FREQUENCY ION GUIDE

1. A mass spectrometer, comprising:(a) a vacuum recipient containing ion handling elements, the vacuum recipient having a plurality of walls which define a gastight volume and comprise at least one of an entrance and exit, wherein different portions of an ion path pass at least one of the entrance and exit and run through the gastight volume; and
(b) a gastight radio frequency ion guide having an ion passage along an axis and being mounted gastight to at least one of the entrance and exit as to extend the gastight volume and continue the ion path in its ion passage outside the vacuum recipient,
wherein the gastight radio frequency ion guide is located outside the vacuum recipient in an environment of ambient pressure in order to lower pumping requirements for the mass spectrometer.

US Pat. No. 10,141,176

MULTI-REFLECTION MASS SPECTROMETER WITH DECELERATION STAGE

Thermo Fisher Scientific ...

1. A multi-reflection mass spectrometer comprising two ion mirrors spaced apart and opposing each other in an X direction, each mirror elongated generally along a drift direction Y, the X direction being orthogonal to the drift direction Y, and an ion injector for injecting ions as an ion beam into the space between the ion mirrors at an inclination angle to the X direction, wherein along a first portion of their length in the drift direction Y the ion mirrors converge with a first degree of convergence and along a second portion of their length in the drift direction Y the ion mirrors converge with a second degree of convergence or are parallel, the first portion of their length being closer to the ion injector than the second portion and the first degree of convergence being greater than the second degree of convergence.

US Pat. No. 10,141,175

QUASI-PLANAR MULTI-REFLECTING TIME-OF-FLIGHT MASS SPECTROMETER

LECO Corporation, St. Jo...

1. A multi-reflecting time-of-flight mass spectrometer comprising:two quasi-planar electrostatic ion mirrors extended along a drift Z-direction and formed of parallel electrodes, wherein said mirrors are separated by a field-free region;
a pulsed ion source to release ion packets at a small angle to an X-direction which is orthogonal to the drift Z-direction, such that the ion packets are reflected between the ion mirrors and drift along the drift Z-direction direction;
a receiver to receive the ion packets;
wherein said mirrors are positioned to provide time-of-flight focusing on said receiver and provide spatial focusing in a Y-direction orthogonal to both the drift Z-direction and the ion injection X-direction;
wherein at least one of said mirrors has a periodic feature providing modulation of electrostatic field along the drift Z-direction for the purpose of periodic spatial focusing of the ion packets in the Z-direction; and
wherein said periodic feature comprises at least one of the following:
at least one mirror electrode having an opening varying in height in the Y-direction;
at least one mirror electrode with varying width along the X-direction; or
a set of periodic lenses incorporated into an internal electrode of at least one of said mirrors.

US Pat. No. 10,141,174

METHOD FOR EXAMINING A GAS BY MASS SPECTROMETRY AND MASS SPECTROMETER

Carl Zeiss SMT GmbH, Obe...

1. A method, comprising:producing ions by ionizing a gas;
storing at least some of the ions in an FT ion trap; and
detecting at least some of the ions in the FT ion trap,
wherein at least one of the following holds:
i) producing the ions comprises exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions;
ii) storing the ions in the FT ion trap comprises exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions; and
iii) before detecting the ions in the FT ion trap, exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions, and
wherein:
a degree of excitation and/or a phase angle of the IFT excitation are varied between a first excitation frequency and a second excitation frequency; and
both the first excitation frequency and the second excitation frequency deviate from a predetermined excitation frequency by no more than 10%.

US Pat. No. 10,141,173

SYSTEMS FOR SEPARATING IONS AND NEUTRALS AND METHODS OF OPERATING THE SAME

Rapiscan Systems, Inc., ...

1. A mass spectrometer system comprising:a sample injection device defining a sample injection aperture;
an ion trap defining an ion outlet aperture, said ion trap coupled to said sample injection device;
a detector positioned downstream of said ion outlet aperture, wherein the detector is positioned in a detector enclosure defining a detector chamber;
an ion source coupled to said ion trap, said ion source configured to ionize a sample injected into said ion trap and generate a plurality of ionized molecules within said ion trap, said ion trap configured to maintain said plurality of ionized molecules therein while a plurality of neutral molecules migrate out of said ion trap, and into the detector chamber, until a predetermined pressure is attained in said ion trap;
a first vacuum pump coupled to the ion trap wherein the first vacuum pump is configured to decrease a pressure in the ion trap; and
a second vacuum pump coupled to the detector chamber wherein the second vacuum pump is configured to decrease a pressure in the detector chamber such that a pressure in the detector chamber induced by the neutral molecules therein decays at a predetermined rate.

US Pat. No. 10,141,172

SYNCHRONISED VARIATION OF SOURCE CONDITIONS OF AN ATMOSPHERIC PRESSURE CHEMICAL IONISATION MASS SPECTROMETER COUPLED TO A GAS CHROMATOGRAPH TO IMPROVE STABILITY DURING ANALYSIS

MICROMASS UK LIMITED, Wi...

1. A mass spectrometer comprising:a gas chromatography separation device;
an atmospheric pressure ionisation ion source; and
a control system arranged and adapted:
(i) to operate said atmospheric pressure ionisation ion source at one or more first settings for a first period of time whilst one or more solvents elute from said gas chromatography separation device during a solvent front free of analytes which is prior to the elution of one or more analytes from said gas chromatography separation device; and then
(ii) to operate said atmospheric pressure ionisation ion source at one or more second different settings for a second subsequent period of time whilst said one or more analytes elute from said gas chromatography separation device.

US Pat. No. 10,141,171

METHOD AND KIT FOR DETERMINING METABOLITES ON DRIED BLOOD SPOT SAMPLES

AZIENDA OSPEDALIERO UNIVE...

1. A kit specially designed to be used for the preparation of a dried blood sample for a direct tandem MS analytical determination of Adenosine and Deoxyadenosine concurrently with more than one metabolite selected from the group consisting of amino acids, free carnitine, acylcarnitines and any combinations thereof, from said dried blood sample, said kit comprising:at least one container containing stable isotope-labelled Adenosine and Deoxyadenosine as internal standards and more than one additional internal standards selected from the group consisting of amino acids, acylcarnitines and free carnitine, wherein the isotope label is selected from the group consisting of 2H (D), 15N, 13C and 18O;
at least one dried blood spot as a control, wherein said dried blood spot is enriched with Adenosine and Deoxyadenosine at known concentrations and enriched with one or more metabolites selected from the group consisting of amino acids, free carnitine, acylcarnitines and any combinations thereof at known concentrations; and
at least one container containing an extraction solution comprising a C1-3 linear or branched chain monoalcohol.

US Pat. No. 10,141,170

DEVICE FOR MASS SPECTROMETRY

TOFWERK AG, Thun (CH)

1. A device for mass spectrometry comprising:a) an ionization source;
b) a mass analyzer fluidly coupled to the ionization source;
c) an electronic data acquisition system for processing signals provided by the mass analyzer;whereas the electronic data acquisition system comprisesd) at least one analog-to-digital converter producing digitized data from the signals obtained from the mass analyzer;
e) a fast processing unit receiving the digitized data from said analog-to-digital converter;whereinf) the fast processing unit is programmed to continuously, in real time inspect the digitized data for events of interest measured by the mass spectrometer, wherein said inspection is based on a filter definition, the filter definition comprising at least one region of interest including a selection of values of m/Q and further comprising at least one filter criterion to be applied to the at least one region of interest, wherein the selection of values of m/Q is a subsection of all values of m/Q of an entire mass spectrum; and
g) the electronic data acquisition system is programmed to forward the digitized data representing mass spectra relating to events of interest for further analysis and to reject the digitized data representing mass spectra not relating to events of interest.

US Pat. No. 10,141,168

METHOD FOR CHARACTERISING A SAMPLE BY MASS SPECTROMETRY IMAGING

IMABIOTECH, Loos (FR)

1. A process for identifying by mass spectrometry imaging (MSI) a molecule of interest in a sample of interest, the process comprising:analyzing a spatial arrangement of a plurality of ions in the sample of interest from MSI data of said ions in said sample to determine morphometric features and/or texture features associated with said ions in said sample, the morphometric features defining geometrical patterns formed by a presence of said ions and mathematical dimensions of the geometrical patterns, the texture features defining an arrangement of the geometrical patterns in said sample;
comparing the morphometric and/or texture features associated with the plurality of ions in said sample of interest with morphometric and/or texture data associated with a plurality of ions in a reference sample;
identifying at least one characteristic ion of the sample; and
identifying the molecule corresponding to said identified ion.

US Pat. No. 10,141,166

METHOD OF REAL TIME IN-SITU CHAMBER CONDITION MONITORING USING SENSORS AND RF COMMUNICATION

Applied Materials, Inc., ...

1. A reactor for processing a workpiece, the reactor comprising:a chamber comprising:
a cylindrical sidewall;
a ceiling;
a floor; and
a pedestal for supporting a workpiece inside said chamber;
plural wireless sensors each having a wireless transceiver and secured to said chamber and fixed in locations inside said chamber;
a process controller outside of said chamber and connected to said chamber to govern process parameters in said chamber, wherein said cylindrical sidewall, said ceiling, and said floor are conductive such that said chamber blocks wireless communication channels between respective ones of said sensors and said process controller;
a wireless communication hub inside of said chamber and programmed to maintain respective independent wireless communication channels between the wireless transceiver of respective ones of said sensors and said wireless communication hub; and
a communication path between said wireless communication hub and said process controller.

US Pat. No. 10,141,165

PLASMA PROCESSING APPARATUS AND SAMPLE STAGE THEREOF

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus comprising: a processing chamber disposed in a vacuum vessel in which a wafer located therein is processed using plasma generated therein; a sample stage disposed in the processing chamber on which the wafer is mounted on a top surface thereof; an electrode disposed in the sample stage which is constituted by an electrically conductive material; a radio frequency power supply which is electrically connected to the electrode in the sample stage and supplies the radio frequency power for generating a bias potential above the wafer mounted on the sample stage to the electrode; a plurality of heater units each of which are respectively disposed in each of a plurality of areas in a cylindrical interior of the sample stage, the plurality of areas including a central region of the cylindrical interior of the sample stage and a plurality of ring-shaped regions which are disposed on an outer circumference of the central region and surrounds the central region; one or more DC power supplies which is connected to each of the plurality of heater units disposed in each of the ring-shaped regions and is configured to supply DC power to each of the plurality of heater units; a plurality of arcuate heaters which constitutes each of the plurality of heater units disposed in each of the plurality of ring-shaped regions and is circumferentially disposed around the central region of the sample stage, the plurality of arcuate heaters in each of the heater units in each of the plurality of the ring-shaped regions being connected in series to the one or more DC power supplies which is connected to the one of the plurality of heater units disposed in the one or more ring-shaped regions and constituting a circuit; wherein each of the plurality of arcuate heaters constituting the circuit in the each of the heater units disposed in each of the plurality of the ring-shaped regions is connected to the adjacent arcuate heater by each of a plurality of connection portions and has a same length forming a same circumferential angle around the central region, and, the each of the heater units disposed in each of the plurality of the ring-shaped regions constitutes a loop, and the arcuate heaters disposed in one of the ring-shaped region closer to the center region form greater circumferential angle around the central region than those of the arcuate heaters disposed in the ring-shaped region outwardly located, and the apparatus further comprising: a plurality of adjusting devices each of which is connected with the circuit in front and behind of each of the plurality of the arcuate heaters in parallel thereto, the plurality of adjusting devices are configured to be capable of adjusting amounts of current from the one or more DC power supplies flowing through the each of the plurality of arcuate heaters to which the each of the plurality of adjusting devices is connected in parallel; a control unit which is configured to be enable to adjust amounts of heat generated by the one of the plurality of heater units disposed in the one or more ring-shaped regions by adjusting operations of the plurality of adjusting devices.

US Pat. No. 10,141,164

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a radio frequency (RF) power source connected between a reference electrode and a base stand to apply an RF voltage;
an electrostatic chuck arranged on the base stand;
a gas storage unit configured to store a gas, the gas storage unit being arranged in the base stand and including a gas introducing port;
a blocking mechanism configured to open and close the gas introducing port;
a control unit configured to control the blocking mechanism to open the gas introducing port; and
a connection unit configured to connect the gas storage unit and a space between a substrate set on the electrostatic chuck and the electrostatic chuck, wherein:
the apparatus is configured to introduce the gas into the gas storage unit from an outside gas source through the gas introducing port, and
the control unit is configured to open the gas introducing port when no RF voltage is applied between the reference electrode and the base stand by the RF power source.

US Pat. No. 10,141,163

CONTROLLING ION ENERGY WITHIN A PLASMA CHAMBER

Lam Research Corporation,...

1. A method comprising:generating a first sinusoidal radio frequency (RF) signal for providing to an upper electrode of a plasma chamber;
generating a second sinusoidal RF signal;
filtering the second sinusoidal RF signal to generate a nonsinusoidal RF signal having no off cycles;
amplifying the nonsinusoidal RF signal to generate an amplified nonsinusoidal RF signal;
filtering the amplified nonsinusoidal RF signal to generate a filtered nonsinusoidal RF signal having a series of pulses between consecutive off cycles; and
providing the filtered nonsinusoidal RF signal to a lower electrode of the plasma chamber.

US Pat. No. 10,141,162

PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

Panasonic Intellectual Pr...

1. A plasma processing apparatus which uses an inductively-coupled plasma torch, comprising:an annular chamber that includes a linear opening portion, and that communicates with the opening portion surrounded with a dielectric member except for the opening portion;
a coil that is disposed in the vicinity of the chamber;
a power source that is connected to the coil; and
a substrate mounting table,
wherein the chamber is continuously closed string shaped, includes two linear regions having a linear region adjacent to the linear opening portion and a linear region arranged parallel thereto,
wherein the coil includes two linear conductors arranged along only the two linear regions,
wherein in the dielectric member surrounding the chamber, a portion configuring a surface facing the substrate mounting table includes a cylinder arranged parallel to a linear direction of the opening portion, and
wherein the plasma processing apparatus further comprises a rotary mechanism that rotates the cylinder around an axis of the cylinder.

US Pat. No. 10,141,161

ANGLE CONTROL FOR RADICALS AND REACTIVE NEUTRAL ION BEAMS

Varian Semiconductor Equi...

1. A workpiece processing apparatus, comprising:a plasma generator;
a plasma chamber; and
one extraction plate having a first aperture and a second aperture;
wherein charged ions are extracted through the first aperture at a first selected extraction angle, and reactive neutrals are passed through the second aperture at a second selected extraction angle, where the second aperture is different than the first aperture and comprises a suppressor to minimize charged ions passing through the second aperture by repelling or neutralizing the charged ions.

US Pat. No. 10,141,160

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

HERMES MICROVISION, INC.,...

1. A multi-beam apparatus for observing a surface of a sample, comprising:an electron source;
a condenser lens below said electron source;
a source-conversion unit below said condenser lens;
an objective lens below said source-conversion unit;
a deflection scanning unit below said source-conversion unit;
a sample stage below said objective lens;
a beam separator below said source-conversion unit; and
a detection unit above said beam separator and comprising a secondary projection imaging system and an electron detection device with a plurality of detection elements,
wherein said electron source, said condenser lens, said source-conversion unit, said objective lens, said deflection scanning unit and said beam separator are aligned with a primary optical axis of said apparatus, said sample stage is configured to sustain said sample so that said surface faces to said objective lens, said detection unit is aligned with a secondary optical axis of said apparatus, and said secondary optical axis is not parallel to said primary optical axis,
wherein said plurality of detection elements is placed on a detection plane, said secondary projection imaging system comprises a zoom lens, an anti-scanning deflection unit and a projection lens,
wherein said electron source is configured to generate a primary electron beam along said primary optical axis, said condenser lens is configured to focus said primary electron beam, said source-conversion unit is configured to change said primary electron beam into a plurality of beamlets and make said plurality of beamlets form a plurality of first images of said electron source, said objective lens is configured to focus said plurality of beamlets to image said plurality of first images onto said surface and therefore form a plurality of probe spots thereon respectively, and said deflection scanning unit is configured to deflect said plurality of beamlets to scan said plurality of probe spots respectively over a plurality of scanned regions within an observed area on said surface,
wherein a plurality of secondary electron beams is generated by said plurality of probe spots respectively from said plurality of scanned regions and then incident to said objective lens, said objective lens is configured to in passing focus said plurality of secondary electron beams, and said beam separator is configured to deflect said plurality of secondary electron beams to enter said secondary projection imaging system along said secondary optical axis,
wherein said zoom lens is configured to focus said plurality of secondary electron beams onto a transfer plane, said transfer plane is between said zoom lens and said projection lens, and said plurality of secondary electron beams is configured to form a first crossover between said zoom lens and said transfer plane,
wherein said projection lens is configured to focus said plurality of secondary electron beams onto said detection plane, said plurality of secondary electron beams is configured to form a second crossover between said projection lens and said detection plane and a plurality of secondary-electron spots on said detection plane, said plurality of secondary-electron spots is inside said plurality of detection elements respectively, consequently a corresponding relationship between said plurality of probe spots and said plurality of detection elements is established, and accordingly each detection element is configured to generate an image signal of one corresponding scanned region,
wherein said anti-scanning deflection unit is configured to deflect said plurality of secondary electron beams in step with said plurality of probe spots scanning over said plurality of scanned regions to remain positions of said plurality of secondary-electron spots and thereby keeping said corresponding relationship all the time,
wherein an imaging magnification of said zoom lens is configured to be adjusted to keep said corresponding relationship when observing said surface in different conditions.

US Pat. No. 10,141,159

SAMPLE OBSERVATION DEVICE HAVING A SELECTABLE ACCELERATION VOLTAGE

Hitachi High-Technologies...

1. A sample observation device, comprising:a charged particle optical column configured to irradiate a sample with a charged particle beam at a first acceleration voltage, the sample having a target part to be observed which is a concave part;
a detector configured to detect charged particles obtained by irradiation with the charged particle beam;
an imaging system in communication with the detector, the imaging system being configured to form an image including the target part to be observed on the basis of an output of the detector and to extract brightness information of the concave part and a periphery part of the concave part from the formed image;
a controller in communication with the imaging system, the controller having a memory configured to store in advance, at each of a plurality of acceleration voltages, information indicating a relationship between a brightness ratio of the concave part to the periphery part of the concave part in a standard sample and a value indicating at least one of depth and aspect ratio of the concave part in the standard sample; and
a processor configured to: i) calculate the brightness ratio of the concave part and the periphery part based on the extracted brightness information, ii) compare the calculated brightness ratio with a brightness ratio stored in the memory, iii) select an acceleration voltage stored in association with the brightness ratio stored in the memory, and iv) generate a control signal that changes the acceleration voltage applied to the charged particle beam.

US Pat. No. 10,141,158

WAFER AND DUT INSPECTION APPARATUS AND METHOD USING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A wafer and a device under test (DUT) inspection apparatus, comprising:a vacuum chamber;
a stage disposed in the vacuum chamber and near a first end of the vacuum chamber, wherein the stage is configured to hold a wafer or DUT;
an electron gun disposed in the vacuum chamber and near a second end of the vacuum chamber opposite to the first end for providing an E-beam;
a lens system disposed between the stage and the electron gun, wherein the lens system is a total reflective achromatic lens system comprising:
a first lens having a first aperture; and
a second lens having a second aperture aligned with the first aperture, the second lens is disposed between the electron gun and the first lens;
an optical mirror disposed between the lens system and the electron gun, wherein the optical mirror has a slit aligned with the second aperture, thereby allowing the E-beam to pass through the slit, the first aperture and the second aperture;
a beam shaping aperture disposed between the electron gun and the optical mirror;
a grating horizontally aligned with the optical mirror and configured to reflect towards the detector cathodoluminescence reflected from the optical mirror; and
a detector aligned with the grating, wherein the detector is configured to detect the cathodoluminescence for forming an image.

US Pat. No. 10,141,157

METHOD FOR ADJUSTING HEIGHT OF SAMPLE AND OBSERVATION SYSTEM

Hitachi High-Technologies...

1. A method for adjusting the height of a sample in a charged particle beam device which includes a charged particle optical lens barrel that generates a charged particle beam, a first sample placement section, a diaphragm that separates a space where the first sample placement section is placed from the inside of the charged particle optical lens barrel, and a base table to which the diaphragm is fixed, wherein the method comprises:a first step of storing the height of the first sample placement section when a height adjustment member comes into contact with the diaphragm or the base table by moving the first sample placement section in the optical axis direction of the charged particle optical lens barrel;
a second step of adjusting a specific point that indicates a position at a predetermined distance from an optical device uniquely determined for the optical device so that the specific point is located on the surface of the height adjustment member by moving at least a part of the optical device to change the distance between the optical device and the height adjustment member;
a third step of placing a sample table with a Z-axis driving mechanism in the optical device and adjusting the height of the sample table with a Z-axis driving mechanism so that the surface of the sample is located at the position of the specific point of the optical device without changing the position of the specific point of the optical device adjusted in the second step; and
a fourth step of adjusting a distance between the sample and the diaphragm by adjusting the height of the first sample placement section of the charged particle beam device or the height of the sample table with a Z-axis driving mechanism using the height of the first sample placement section stored in the first step.

US Pat. No. 10,141,156

MEASUREMENT OF OVERLAY AND EDGE PLACEMENT ERRORS WITH AN ELECTRON BEAM COLUMN ARRAY

KLA-Tencor Corporation, ...

1. A metrology system comprising:a plurality of electron beam measurement columns, each spatially separated from an adjacent electron beam measurement column of the plurality of electron beam measurement columns by a fixed distance along a first direction, each electron beam measurement column including:
an electron beam source configured to generate a beam of primary electrons;
a beam deflector configured to adjust a location of incidence of the beam of primary electrons onto a specimen under measurement; and
a detector configured to detect secondary electrons from the specimen in response to the incident beam of primary electrons and generate an output signal based on the detected secondary electrons;
a specimen positioning subsystem configured to scan a specimen in a second direction aligned with a row of die disposed on the specimen, wherein the first direction is oriented at an oblique angle with respect to the second direction such that each of the plurality of electron beam columns performs a one dimensional measurement of the same row of features of a different row of die; and
a computing system configured to:
receive the output signals generated by each of the electron beam measurement columns; and
estimate an overlay value, an edge placement error value, or both, based on the output signals.

US Pat. No. 10,141,155

ELECTRON BEAM EMITTERS WITH RUTHENIUM COATING

KLA-Tencor Corporation, ...

1. An apparatus comprising:a silicon emitter, wherein the silicon emitter has a diameter of 100 nm or less; and
a protective cap layer disposed on an exterior surface of the silicon emitter, wherein the protective cap layer includes ruthenium.