US Pat. No. 11,114,433

3DIC STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...


1. A three dimensional integrated circuit (3DIC) structure, comprising:a first die having a first interconnect structure and a first pad electrically connected to the first interconnect structure;
a second die having a second interconnect structure and a second pad electrically connected to the second interconnect structure; and
a hybrid bonding structure bonding the first die and the second die, and disposed between the first interconnect structure and the second interconnect structure, wherein the hybrid bonding structure comprises a first bonding structure covering the first pad and a second bonding structure covering the second pad, the first bonding structure comprises:a first bonding dielectric layer; and
a first bonding metal layer, disposed in the first bonding dielectric layer, wherein the first bonding metal layer comprises a first via plug and a first metal feature disposed over and in direct contact with the first via plug, a height of the first metal feature is greater than a height of the first via plug,
wherein the first pad is laterally aside the first bonding metal layer, and separated from the second pad by the first bonding dielectric layer therebetween, and a bottom surface of the first metal feature contacting the first via plug is lower than a top surface of the first pad of the first die.


US Pat. No. 11,114,432

PROTECTION CIRCUIT WITH A FET DEVICE COUPLED FROM A PROTECTED BUS TO GROUND

Semtech Corporation, Cam...


1. A semiconductor device, comprising:a voltage input circuit node;
a ground voltage node;
a first transistor coupled between the voltage input circuit node and the ground voltage node, wherein the first transistor is a field-effect transistor (FET);
a first resistor coupled between a source or drain terminal of the first transistor and the voltage input circuit node, wherein the first resistor and first transistor are coupled between the voltage input circuit node and ground voltage node in series;
a second transistor coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor, wherein the second transistor is a FET, and wherein a source or drain terminal of the second transistor is coupled to a gate terminal of the first transistor;
a voltage-limiting circuit coupled between the source or drain terminal of the second transistor and the gate terminal of the first transistor, wherein the voltage-limiting circuit includes a fourth transistor comprising a first source, drain, emitter, or collector terminal coupled to the source or drain terminal of the second transistor and a second source, drain, emitter, or collector terminal of the fourth transistor is coupled to the gate terminal of the first transistor; and
a triggering circuit coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor, wherein a first circuit node of the triggering circuit is coupled to a gate terminal of the second transistor, and wherein the triggering circuit includes,a second resistor coupled between the first circuit node and the voltage input circuit node,
a third transistor comprising a first emitter or collector terminal coupled to the first circuit node and a second emitter or collector terminal coupled to the ground voltage node, wherein the third transistor is a bipolar junction transistor (BJT), and
a triggering diode comprising a cathode coupled to the first circuit node and an anode coupled to a base terminal of the third transistor.


US Pat. No. 11,114,431

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Semiconductor Manufacturi...


1. An electrostatic discharge (ESD) protection device, comprising:a substrate having an input region;
a plurality of fins on the substrate in the input region;
a well region, doped with first-type ions, in the plurality of fins and in the substrate;
an epitaxial layer on each fin in the input region;
a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer;
an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and
a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions, wherein a PN junction is formed between the counter-doped region and the extended drain region.

US Pat. No. 11,114,430

LEAKAGE CURRENT DETECTION AND PROTECTION DEVICE AND POWER CONNECTOR EMPLOYING THE SAME

Chengli Li, Suzhou (CN)


1. A leakage current detection and protection device coupled between an input end and an output end of power lines, the device comprising:a first switching module and a second switching module, wherein each of the first and second switching modules is coupled on the power lines between the input end and the output end, wherein the first and second switching modules are operable to connect or disconnect an electrical connection between the input and output ends such that the input end is electrically connected to the output end when both the first and second switching modules are in their connected state, and the input end is electrically disconnected from the output end when either of the first and second switching modules is in its disconnected state;
a leakage current detection module configured to detect a leakage current signal on the power lines and to generate a leakage fault signal in response to detecting the leakage current signal;
a self-test module configured to detect a fault of the leakage current detection module and to output a self-test fault signal when the fault in the leakage current detection module is detected;
a first drive module, coupled to the self-test module and the first switching module, and configured, in response to the self-test fault signal, to control the first switching module to disconnect the electrical connection between the input and output ends; and
a second drive module, coupled to the leakage current detection module and the second switching module, and configured, in response to the leakage fault signal, to control the second switching module to disconnect the electrical connection between the input and output ends, wherein the first and second drive modules are separate from each other and configured to separately control the first and second switching modules, respectively.

US Pat. No. 11,114,429

INTEGRATED CIRCUIT DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

XILINX, INC., San Jose, ...


1. An integrated circuit device comprising:a first die having a first body, the first body comprising a passive region and an active region;
a first contact pad exposed to a surface of the first body, the first contact pad configured to connect to a first supply voltage;
a second contact pad exposed to the surface of the first body, the second contact pad configured to connect to a second supply voltage or ground;
a first charge-sensitive circuitry formed in the first body and coupled between the first contact pad and the second contact pad;
a first RC clamp formed in the first body and coupled between the first contact pad and the second contact pad, the first RC clamp comprising:at least two BigFETs coupled between the first contact pad and the second contact pad; and
a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs;

a plurality of FEOL layers including an oxide layer, the oxide layer forming a gate oxide layer of a first BigFET of the at least two BigFETs; and
a second die having another BigFET in an RC clamp, the another BigFET of the RC clamp of the second die having an oxide gate layer thicker than the gate oxide layer of the first BigFET of the first die.

US Pat. No. 11,114,428

INTEGRATED CIRCUIT DEVICE

SAMSUNG ELECTRONICS CO., ...


1. An integrated circuit device comprising:a memory comprisinga memory stack,
a memory cell interconnection comprising a plurality of upper conductive patterns configured to be electrically connectable to the memory stack, and
a memory cell insulation surrounding the memory stack and the memory cell interconnection;

a peripheral circuit comprisinga peripheral circuit board,
a peripheral circuit region on the peripheral circuit board, and
a peripheral circuit interconnection comprising a plurality of lower conductive patterns between the peripheral circuit region and the memory and bonded to the memory cell interconnection;

a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, the plurality of conductive bonding structures being bonded plurality of first upper conductive patterns selected from among the plurality of upper conductive patterns and a respective plurality of first lower conductive patterns selected from among the plurality of lower conductive patterns; and
a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a second lower conductive pattern selected from among the plurality of lower conductive patterns in the vertical direction, in a second region, the second region overlapping the memory cell insulation in the vertical direction.

US Pat. No. 11,114,427

3D SEMICONDUCTOR PROCESSOR AND MEMORY DEVICE AND STRUCTURE

Monolithic 3D Inc., Klam...


1. A 3D semiconductor device, the device comprising:a first level comprising first single crystal transistors; and
a second level comprising second single crystal transistors,wherein said first level is overlaid by said second level,
wherein a vertical distance from said first single crystal transistors to said second single crystal transistors is less than four microns,
wherein said first level comprises a plurality of processors, and
wherein said second level comprises a plurality of memory cells.


US Pat. No. 11,114,426

BENDABLE PANEL AND METHOD OF FABRICATING SAME


1. A bendable panel, comprising:a flexible display panel comprising a flexible substrate as a base, wherein the flexible substrate comprises an active display area and a binding end positioned on a side of the active display area;
a driving chip disposed on the binding end, wherein the binding end is bent toward a direction away from a light emitting side of the flexible display panel, such that the driving chip is positioned on a back surface of the flexible substrate;
a back film layer disposed on the back surface of the flexible substrate, wherein the back film layer is configured to support and protect the flexible substrate;
a foam layer disposed on the back surface of the back film layer, wherein the foam layer is configured to protect the flexible substrate; and
a support plate;
wherein the binding end comprises a first terminal portion adjacent to the active display area, a second terminal portion adjacent to the driving chip, and a bent portion connected to the first terminal portion and the second terminal portion and having a bent shape; and
wherein a bent region disposed on an inner surface of the bent portion is provided with a glue;
wherein the support plate is attached to a back surface of the second terminal portion, the support plate covers at least the back surface of the second terminal portion on which the driving chip is disposed, a configuration of the support plate, the back surface of the second terminal portion, and the driving chip fills a height difference between the foam layer and the second terminal portion.

US Pat. No. 11,114,425

PACKAGING OF RADIATION DETECTORS IN AN IMAGE SENSOR

SHENZHEN XPECTVISION TECH...


1. An image sensor comprising:a first package comprising a plurality of radiation detectors mounted on a printed circuit board (PCB);
wherein a dead zone of the first package does not extend between neighboring radiation detectors among the plurality of radiation detectors;
wherein the radiation detectors have no guard rings or sidewall doping;
wherein each of the radiation detectors comprises an array of pixels;
wherein pixels on peripheries of the radiation detectors are configured to deduct a contribution of a dark current from energy of a radiation particle incident thereon.

US Pat. No. 11,114,424

DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...


1. A display substrate, comprising:a base substrate;
a display function layer located on a first surface of the base substrate, a first groove arranged in the first surface and recessed from the first surface toward the base substrate, and a first connection sub-line located in the first groove and covering a bottom and each side wall of the first groove, wherein the first connection sub-line is connected to a signal input terminal of the display function layer; and
an integrated circuit located on a second surface of the base substrate opposite to the first surface, a second groove arranged in the second surface and recessed from the second surface toward the base substrate to the first connection sub-line, and a second connection sub-line located in the second groove, wherein the second connection sub-line is connected to the first connection sub-line and a signal output terminal of the integrated circuit,
wherein an orthogonal projection of the first groove on the base substrate at least partially overlaps an orthogonal projection of the second groove on the base substrate, and the first groove and the second groove communicate with each other and together penetrate the base substrate.

US Pat. No. 11,114,423

IMAGE-FORMING ELEMENT

SHARP KABUSHIKI KAISHA, ...


1. An image-forming element that includes a plurality of pixels and projects and displays light emitted from the pixels, the element comprising:a light emitting element which includes a light source emitting the light; and
a mounting substrate on which a plurality of light emitting elements are provided on a mounting surface,
wherein a plurality of light sources which are segmented and included in at least one pixel are provided,
wherein each of the light sources includes one or a plurality of power supply electrodes provided on the same surface,
wherein the mounting substrate includes a drive circuit which drives the light source and electrodes which are provided on the mounting surface and are electrically connected to the power supply electrodes of the light source, and
wherein the drive circuit includes at least one non-volatile memory transistor to reduce a variation of light emission intensity between the light emitting elements.

US Pat. No. 11,114,421

INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FOR PLATFORM MINIATURIZATION

INTEL CORPORATION, Santa...


1. A computing system comprising:a processor having one or more processor cores;
a System in Package (SiP) board, wherein the SiP board comprises a plurality of logic components, wherein the plurality of logic components comprises the processor; and
an Input Output (IO) board coupled to the SiP board via a grid array,
wherein the plurality of logic components is to be provided on both a first side and a second side of the SiP board, wherein one or more of the plurality of logic components are to be positioned in an opening in the IO board, wherein at least one flexible cable is to couple one or more logic components on a second board to a first side of the SiP board to allow the one or more logic components of the second board to be folded in between one or more components on a second side of the SiP board.

US Pat. No. 11,114,420

UNIFORMING AN ARRAY OF LEDS HAVING ASYMMETRIC OPTICAL CHARACTERISTICS

Corning Incorporated, Co...


1. An apparatus comprising: an array of light emitting diodes (LEDs), each LED in the array having an asymmetric optical characteristic such that a maximum value of the optical characteristic is at a point other than a centroid of each LED, the array of light emitting diodes comprising a first subset of LEDs, a second subset of LEDs, and a third subset of LEDs,the first subset comprising at least a first LED and a second LED such that the first LED is disposed immediately adjacent to the second LED in a first row of LEDs,
the second subset comprising at least a third LED and a fourth LED such that the third LED is disposed immediately adjacent to the fourth LED in a second row of LEDs,
the third subset comprising at least a fifth LED and a sixth LED such that the fifth LED is disposed immediately adjacent to the sixth LED in a third row of LEDs,
the first row being immediately adjacent to the second row and the second row being immediately adjacent to the third row such that the first LED is immediately adjacent to the third LED and the third LED is immediately adjacent to the fifth LED,
the asymmetric optical characteristic of the fifth LED is oriented in the same direction as the asymmetric optical characteristic of the sixth LED,
the asymmetric optical characteristics of the first LED, the second LED, the third LED, and the fourth LED are each oriented in the same direction and in a different direction from the asymmetric optical characteristics of the fifth LED and the sixth LED, such that the asymmetric optical characteristics of the first LED, the second LED, the third LED, and the fourth LED are each oriented at an angle of 90°, 180°, or 270° with respect to the asymmetric optical characteristics of the fifth LED and the sixth LED in the array, and
the first row further comprising a seventh LED that is immediately adjacent to the second LED, the second row further comprising an eighth LED that is immediately adjacent to the fourth LED, and the asymmetric optical characteristics of the seventh LED and the eighth LED are each oriented in the same direction and in a different direction from the asymmetric optical characteristics of the first LED, the second LED, the third LED, and the fourth LED, such that the asymmetric optical characteristics of the seventh LED and the eighth LED are each oriented at an angle of 90°, 180°, or 270° with respect to the asymmetric optical characteristics of the first LED, the second LED, the third LED, and the fourth LED in the array.

US Pat. No. 11,114,419

MULTI-COLOR LED PIXEL UNIT AND MICRO-LED DISPLAY PANEL

Jade Bird Display (Shangh...


1. A multi-color light emitting pixel unit, comprising:a substrate;
a bottom conductive layer formed on the substrate and a top conductive layer formed over the bottom conductive layer; and
a light emitting layer formed between the top conductive layer and the bottom conductive layer,
wherein the light emitting layer includes a plurality of micro-gap structures, and
each one of the micro-gap structures is an air gap.

US Pat. No. 11,114,418

ELECTRONIC DEVICE, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC APPARATUS

FUJITSU LIMITED, Kawasak...


1. An electronic device comprising:a first layer that includes first electronic components in a group and has a first through space between adjacent ones of the first electronic components; and
a second layer that is stacked over the first layer and includes second electronic components which are coupled to the first electronic components and a second through space between adjacent ones of the second electronic components, the second through space being partially overlapping with the first through space,
wherein each of four ends of a specific second electronic component included in the second electronic components is stacked on a different first electronic component included in the first electronic components,
each of the first electronic components includes a first conduction via penetrating the each of the first electronic components in the stacking direction, and
each of the second electronic components includes a second conduction via penetrating the each of the second electronic components in the stacking direction, and the second conduction via is electrically connected to the first conduction via.

US Pat. No. 11,114,417

THROUGH-SILICON VIA (TSV) TEST CIRCUIT, TSV TEST METHOD AND INTEGRATED CIRCUITS (IC) CHIP

Changxin Memory Technolog...


1. An integrated circuit (IC) with a through-silicon via (TSV) test circuit, comprising a first TSV, a second TSV and a phase detector,a first end of the first TSV coupled to a predetermined signal output, and a second end of the first TSV coupled to a first end of the second TSV,
a second end of the second TSV coupled to a first input of the phase detector,
a second input of the phase detector coupled to the predetermined signal output,
wherein the phase detector is configured to determine a phase difference between a signal at the first input of the phase detector and a signal at the second input of the phase detector, and wherein a test result is determined by comparing the phase difference with a predetermined threshold,
wherein a stacked tier associated with the second end of the first TSV comprises a phase calibrator configured to apply a delay compensation to an operational signal output from the second end of the first TSV based on the phase difference output from the phase detector.

US Pat. No. 11,114,416

POWER AND TEMPERATURE MANAGEMENT FOR FUNCTIONAL BLOCKS IMPLEMENTED BY A 3D STACKED INTEGRATED CIRCUIT

Micron Technology, Inc., ...


1. An apparatus comprising:a non-volatile memory die;
a volatile memory die;
a logic die; and
a thermal management component having a different thermal conductivity than the dies,
wherein the non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked,
wherein the non-volatile memory die, the volatile memory die, and the logic die are arranged to form an array of functional blocks.

US Pat. No. 11,114,415

SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Micron Technology, Inc., ...


1. A semiconductor device, comprising:a first die;
a second die attached over the first die;
a first metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and
a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level;
wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

US Pat. No. 11,114,414

WAFER STRUCTURE WITH CAPACITIVE CHIP INTERCONNECTION, METHOD FOR MANUFACTURING THE SAME, AND CHIP STRUCTURE WITH CAPACITIVE CHIP INTERCONNECTION

Wuhan Xinxin Semiconducto...


1. A chip structure, comprising:a first chip, wherein the first chip comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer; and
a second chip, wherein the second chip comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer, wherein
the first chip is stacked with the second chip via the first bonding layer and the second bonding layer with a front surface of the first chip facing toward a front surface of the second chip, and the first capacitor plate is arranged facing toward the second capacitor plate with at least the second dielectric material and the fourth dielectric material being provided between the first capacitor plate and the second capacitor plate;
wherein the first plate interconnection structure comprises an interconnection layer connected to the first capacitor plate; and
wherein the first bonding layer is arranged with a bonding pad to lead out the interconnection layer of the first device interconnection structure, and the second bonding layer is arranged with a bonding pad to lead out an interconnection layer of the second device interconnection structure, and wherein the bonding pad of the first bonding layer is aligned with the bonding pad of the second bonding pad.

US Pat. No. 11,114,413

STACKING STRUCTURE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...


1. A package structure, comprising:a plurality of stacked die units stacked on top of one another, wherein each of the plurality of stacked die units comprises:
a first semiconductor die having a plurality of first bonding pads;
a first bonding chip stacked on the first semiconductor die and having a plurality of first bonding structures, wherein the plurality of first bonding structures is bonded to the plurality of first bonding pads;
a second bonding chip stacked on the first semiconductor die adjacent to the first bonding chip and having a plurality of second bonding structures, wherein the plurality of second bonding structures is bonded to the plurality of first bonding pads, and the second bonding chip is physically separated from the first bonding chip on the first semiconductor die;
an insulating encapsulant encapsulating the plurality of stacked die units and filling into a space between the first bonding chip and the second bonding chip.

US Pat. No. 11,114,412

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...


1. An electronic package, comprising:a first carrying structure defined with a first surface and a second surface opposing the first surface and having a first circuit layer;
a package module disposed on the first surface of the first carrying structure and electrically connected to the first circuit layer;
a first electronic component disposed on the first surface of the first carrying structure and electrically connected to the first circuit layer, wherein the first electronic component has a first active surface and a first inactive surface opposing the first active surface, the first inactive surface is adhered to the first surface of the first carrying structure, and a plurality of first electrode pads are disposed on the first active surface; and
a second electronic component stacked on and electrically connected to the first electronic component, wherein the second electronic component has a second active surface and a second inactive surface opposing the second active surface, the second active surface is disposed on the first active surface of the first electronic component, and a plurality of second electrode pads are disposed on the second active surface and electrically connected to the first electrode pads of the first electronic component.

US Pat. No. 11,114,411

SEMICONDUCTOR CHIP TRANSFER METHOD AND TRANSFER TOOL

OSRAM OLED GmbH, Regensb...


1. A method of transferring semiconductor chips comprising:providing a transfer tool having a plurality of segments, each segment having a liquid receiving area;
providing a plurality of semiconductor chips in a regular array on a source carrier;
providing a target carrier;
selectively arranging liquid drops on the liquid receiving areas of some of the segments;
causing the transfer tool to approach the source carrier, each liquid drop contacting and wetting a semiconductor chip;
lifting the transfer tool from the source carrier, wherein semiconductor chips wetted by liquid drops are lifted from the source carrier by the transfer tool;
causing the transfer tool to approach the target carrier such that the semiconductor chips arranged on the transfer tool contact the target carrier; and
lifting the transfer tool from the target carrier, the semiconductor chips contacting the target carrier remaining on the target carrier.

US Pat. No. 11,114,410

MULTI-CHIP PACKAGE STRUCTURES FORMED BY JOINING CHIPS TO PRE-POSITIONED CHIP INTERCONNECT BRIDGE DEVICES

International Business Ma...


1. A method for constructing a package structure, comprising:mounting a plurality of integrated circuit chips to a bridge wafer comprising a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device comprises wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device;
forming a wafer-level molding layer on the bridge wafer to encapsulate the plurality of integrated circuit chips mounted to the bridge wafer;
releasing the interconnect bridge devices from the bridge wafer; and
dicing the wafer-level molding layer to form a plurality of individual multi-chip modules.

US Pat. No. 11,114,409

CHIP ON WAFER ON SUBSTRATE OPTOELECTRONIC ASSEMBLY AND METHODS OF ASSEMBLY THEREOF

Hewlett Packard Enterpris...


1. A method of assembling an optoelectronic assembly via a CoWos process, the method comprising:fabricating an interposer with TSVs, the interposer having opposing first and second sides;
flip-chip assembling an electronic integrated circuit (EIC) having opposing first and second sides to the first side of the interposer;
coupling an enclosure to the first side of the interposer, the enclosure having a lid and four sidewalls, and a height greater than a height of the EIC;
depositing an overmold layer on the first side of the interposer, the overmold layer encapsulating the EIC;
planarizing the overmold layer, wherein the lid of the enclosure is removed during planarization of the overmold layer, the four sidewalls of the enclosure forming a cavity extending through the overmold layer and exposing a region of the first side of the interposer;
coupling an optical component to the first side of the interposer within the formed cavity; and
flip-chip assembling the interposer to a first side of a substrate.

US Pat. No. 11,114,408

SYSTEM AND METHOD FOR PROVIDING 3D WAFER ASSEMBLY WITH KNOWN-GOOD-DIES

Invensas Corporation, Sa...


1. A method, comprising:removing defective dies from a first wafer of a semiconductor material;
bonding a front surface of the first wafer to a temporary carrier;
bonding a front surface of one or more operational dies to the temporary carrier through holes in the first wafer at sites where the defective dies were removed;
bonding a backside of the first wafer to a second wafer; and
removing the temporary carrier.

US Pat. No. 11,114,407

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...


1. An integrated fan-out (InFO) package having an active region and a border region surrounding the active region, comprising:an encapsulant;
a die and a plurality of conductive structures encapsulated by the encapsulant, wherein the plurality of conductive structures surround the die;
a redistribution structure disposed on the encapsulant, wherein the redistribution structure comprises a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks, the plurality of conductive vias interconnect the plurality of routing patterns, at least one of the plurality of alignment marks is in physical contact with the encapsulant, the plurality of alignment marks are electrically floating, the plurality of conductive structures and the plurality of alignment marks are located at different level heights, the plurality of alignment marks are located in the border region, each of the plurality of alignment marks is vertically offset from one another in the same border region, and the border region is devoid of the die, the plurality of routing patterns, and the plurality of conductive vias.

US Pat. No. 11,114,406

WARPAGE-COMPENSATED BONDED STRUCTURE INCLUDING A SUPPORT CHIP AND A THREE-DIMENSIONAL MEMORY CHIP

SANDISK TECHNOLOGIES LLC,...


1. A method of forming a semiconductor structure, comprising:providing a first semiconductor die including first semiconductor devices, first metal interconnect structures, and first metal bonding pads having first concave top surfaces and embedded in a first pad-level dielectric layer;
forming metallic bump portions directly on the first concave top surfaces of the first metal bonding pads while a top surface of the first pad-level dielectric layer is physically exposed by selectively depositing a metallic material on the first concave top surfaces of the first metal bonding pads employing a selective metal deposition process while suppressing growth of the metallic material on the physically exposed top surface of the first pad-level dielectric layer;
providing a second semiconductor die including second semiconductor devices, second metal interconnect structures, and second metal bonding pads; and
attaching the second semiconductor die to the first semiconductor die by bonding the second metal bonding pads to the metallic bump portions via metal-to-metal bonding;
wherein:
the metallic bump portions have a greater thickness at a center portion than at an edge portion during the selective metal deposition process;
the second metal bonding pads have second concave top surfaces; and
the center portions of the metallic bump portions contact the second concave top surfaces of the second metal bonding pads.

US Pat. No. 11,114,405

SEMICONDUCTOR PACKAGE STRUCTURE WITH TWINNED COPPER

Taiwan Semiconductor Manu...


1. A semiconductor package structure, comprising:a chip structure; and
a first conductive structure over the chip structure, wherein the first conductive structure is electrically connected to the chip structure and comprises:a first transition layer over the chip structure;
a first conductive layer on the first transition layer, wherein the first conductive layer is substantially made of twinned copper; and
a second conductive layer over the first conductive layer, wherein a first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.


US Pat. No. 11,114,404

ELECTRONIC DEVICE INCLUDING ELECTRICAL CONNECTIONS ON AN ENCAPSULATION BLOCK

STMicroelectronics (Greno...


1. An electronic device, comprising:an integrated circuit chip having a front face provided with an electrical connection pad;
an overmolded encapsulation block for encapsulating the integrated circuit chip, the overmolded encapsulation block comprising a front layer at least partially covering the front face of the integrated circuit chip;
wherein the overmolded encapsulation block comprises a plastic material containing additive particles in the form of active metal grains;
wherein the overmolded encapsulation block includes a through-hole located above the electrical connection pad of the integrated circuit chip;
an inner metal layer covering a wall of the through-hole, wherein the inner metal layer is joined to the electrical connection pad of the integrated circuit chip and is attached or anchored to the active metal grains at the wall of the through-hole; and
a local front metal layer on a local zone of the front face of the overmolded encapsulation block, said local zone extending adjacent to the through-hole, wherein the local front metal layer is joined to the inner metal layer and is attached or anchored to the active metal grains at the local zone;
wherein the local front metal layer forms an electrical connection.

US Pat. No. 11,114,403

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...


19. A semiconductor device comprising:a first chip including a first substrate, a first cell array, a first interlayer insulating film, and a first bonding structure, wherein the first bonding structure includes a first bonding portion formed in the first substrate and a first through portion passing through the first interlayer insulating film and coupled to the first bonding portion as a single layer; and
a second chip, bonded to the first chip, including a second substrate, a second cell array, a second interlayer insulating film, and a second bonding structure, wherein the second bonding structure includes a second bonding portion formed in the second substrate and a second through portion passing through the second interlayer insulating film and coupled to the second bonding portion as a single layer,
wherein the first bonding portion of the first chip is bonded to the second through portion of the second chip.

US Pat. No. 11,114,402

SEMICONDUCTOR DEVICE WITH BACKMETAL AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...


1. A method for forming a semiconductor device comprising:forming a plurality of contact pads coupled to a first side of a wafer;
forming a recess in a second side of the wafer opposite the first side of the wafer through backgrinding the wafer;
forming a metal layer within the recess;
patterning the metal layer within the recess;
coupling a mold compound with the metal layer within the recess;
removing a portion of the wafer until the portion of the wafer is coplanar with a plane formed by a portion of the mold compound; and
singulating the wafer into a plurality of semiconductor devices.

US Pat. No. 11,114,401

BONDING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Wuhan Xinxin Semiconducto...


1. A method for manufacturing a bonding structure, comprising:providing a plurality of wafers, wherein each of the plurality of wafers has a first surface and a second surface opposite to the first surface; a plurality of chips arranged in an array is formed on the first surface, and each of the plurality of chips comprises a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure; and the first package pad layer is arranged at an edge region of the chip;
bonding the plurality of wafers via bonding layers, to form a wafer stack;
cutting the wafer stack along a scribe line located among the plurality of chips to obtain a chip stack;
exposing the first package pad layer at the edge region of each chip in the chip stack;
providing a package substrate, wherein the package substrate is provided with electrical connections and a second package pad layer electrically connected to the electrical connections; and
electrically connecting the first package pad layer of each chip in the chip stack to the second package pad layer of the package substrate.

US Pat. No. 11,114,400

SEMICONDUCTOR DEVICE WITH IMPROVED THERMAL DISSIPATION AND MANUFACTURING METHODS

AMKOR TECHNOLOGY SINGAPOR...


1. A semiconductor device, comprising:a semiconductor die comprising a die top side and a die bottom side;
a circuit integrated in the semiconductor die;
a bond pad comprising a bond pad top side and bond pad bottom side, wherein the bond pad top side is on the die bottom side, and wherein the bond pad is electrically coupled to the circuit via the bond pad top side;
a dummy pad comprising a dummy pad top side and dummy pad bottom side, wherein the dummy pad top side is on the die bottom side, and wherein the dummy pad is not electrically coupled to the circuit via the dummy pad top side;
a redistribution structure comprising an insulation layer over the die bottom side and a conductive trace separated from the die bottom side by the insulation layer, wherein the conductive trace extends laterally over the die bottom side from a first conductive trace portion coupled to the dummy pad toward a second conductive trace portion coupled to the bond pad; and
an interconnection structure coupled to the first conductive trace portion;
wherein the dummy pad provides a first thermal path that follows a straight line from the die bottom side through the dummy pad to the interconnection structures;
wherein the bond pad and the conductive trace provide a second thermal path between the semiconductor die and the interconnection structure; and
wherein the first thermal path provides greater thermal conductivity between the semiconductor die and the interconnection structure than the second thermal path provides.

US Pat. No. 11,114,399

SEMICONDUCTOR WAFER WITH VOID SUPPRESSION AND METHOD FOR PRODUCING SAME


1. A semiconductor wafer, including:a substrate provided thereon withan electrode pad;
a passivation film that covers the upper surface of the substrate and has an opening for exposing the electrode pad; and
an electrolessly-plated nickel film formed on the electrode pad, an electrolessly-plated palladium film formed on the electrolessly-plated nickel film, and an electrolessly-plated gold film formed on the electrolessly-plated palladium film,

wherein a void exists at an interface between the passivation film and the electrolessly-plated nickel film, the void having a length from a tip of the void to the surface of the electrode pad of 0.3 ?m or more and a width of 0.2 ?m or less, and the entire surface of the electrode pad is covered with the electrolessly-plated nickel film.

US Pat. No. 11,114,398

INTEGRATED CIRCUIT DEVICE INCLUDING SUPPORT PATTERNS AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. An integrated circuit device comprising:a lower electrode formed on a substrate; and
an upper support structure configured to support the lower electrode, the upper support structure disposed around the lower electrode,
wherein the upper support structure comprises:
an upper support pattern surrounding the lower electrode and extending in a lateral direction parallel to the substrate, the upper support pattern having a hole through which the lower electrode passes; and
an upper spacer support pattern between the upper support pattern and the lower electrode inside the hole and having an outer sidewall in contact with the upper support pattern and an inner sidewall in contact with the lower electrode, wherein a width of the upper spacer support pattern in the lateral direction decreases in a direction toward the substrate.

US Pat. No. 11,114,397

SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor package substrate comprising:a semiconductor chip comprising a connection pad;
an encapsulant encapsulating at least a portion of the semiconductor chip;
a connection member disposed on the semiconductor chip and a bottom surface of the encapsulant, the connection member comprising a redistribution layer that is electrically connected to the connection pad;
a first passivation layer disposed on the connection member; and
an adhesive layer disposed on a top surface of the encapsulant in a region outside of the semiconductor chip.

US Pat. No. 11,114,396

REDUCED-LENGTH BOND PADS FOR BROADBAND POWER AMPLIFIERS

Cree, Inc., Durham, NC (...


1. A Doherty amplifier, comprising:a substrate;
at least a first semiconductor die mounted on the substrate;
a main transistor formed on the first semiconductor die, comprisinga first plurality of drain fingers;
a first manifold electrically connecting the first plurality of drain fingers; and
a first bond pad electrically connected to the first manifold; and

a peak transistor, comprisinga second plurality of drain fingers;
a second manifold electrically connecting the second plurality of drain fingers; and
a second bond pad electrically connected to the second manifold; and

an impedance inverter connecting outputs of the main and peak transistors, the impedance inverter comprising parasitic capacitances of the first and second bond pads;
wherein at least one of the first and second bond pads extends a length less than the length of the respective first or second manifold, so as to alter an electrical length of the impedance inverter by reducing the parasitic capacitance.

US Pat. No. 11,114,395

POST PASSIVATION INTERCONNECT

TAIWAN SEMICONDUCTOR MANU...


1. An integrated circuit (IC) device comprising:a first passivation layer over a substrate;
a redistribution line over the first passivation layer, wherein the redistribution line has a barrel-shaped profile;
a second passivation layer over the redistribution line, wherein a distance from a bottommost surface of the second passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate; and
a polymer layer over the second passivation layer.

US Pat. No. 11,114,394

SIGNAL ROUTING CARRIER

Intel Corporation, Santa...


1. An article comprising:a substrate;
a semiconductor die thereon;
a routing carrier attached to the substrate; and
a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier,
wherein the transmission pathway has a loss of no more than 2.5 dB at a signaling speed of about 50 Gbpa to about 250 Gbps.

US Pat. No. 11,114,393

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...


1. An electronic package, comprising:a packaging structure, comprising:a carrier disposed with a circuit layer and having a first surface and a second surface opposing the first surface; and
a plurality of electronic components disposed on the first surface of the carrier and electrically connected to the circuit layer, wherein the plurality of electronic components are radio frequency semiconductor chips; and

at least one antenna structure stacked via a plurality of conductive elements on the second surface of the carrier and electrically connected to the circuit layer and one of the plurality of electronic components without being connected to any other of the plurality of electronic components.

US Pat. No. 11,114,392

WIRELESS COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...


1. A wireless communication device comprising:an RFIC element including a first terminal electrode and a second terminal electrode;
a first electrode connected to the first terminal electrode; and
a second electrode connected to the second terminal electrode,
wherein the first electrode extends in both a longitudinal direction and a lateral direction and includes a first portion connected to the first terminal electrode and a second portion facing the first portion and the second electrode, and
wherein the first portion of the first lateral electrode includes an extended portion that extends in the longitudinal direction and beyond a connection point where the second electrode is connected to the second terminal electrode of the RFIC element.

US Pat. No. 11,114,391

ANTENNA PACKAGE STRUCTURE AND ANTENNA PACKAGING METHOD

SJ Semiconductor (Jiangyi...


1. An antenna packaging method, comprising steps of:1) providing a support substrate, and forming a separation layer on the support substrate;
2) forming a rewiring layer on the separation layer, wherein the rewiring layer has a first surface connected to the separation layer and a second surface opposite to the first surface, wherein the rewiring layer comprises a first metal wiring layer and a first dielectric layer;
3) forming a metal connecting column on the first metal wiring layer of the rewiring layer;
4) disposing a packaging layer on the rewiring layer, and thinning the packaging layer, wherein the metal connecting column has a top portion protruding from the packaging layer so that the top portion of the metal connecting column is exposed from the packaging layer; and forming a second dielectric layer on a surface of the packaging layer, wherein a top surface of the metal connecting column is exposed from the second dielectric layer;
5) forming an antenna metal layer on a surface of the second dielectric layer, wherein the antenna metal layer is connected to the metal connecting column;
6) stripping off the separation layer to remove the support substrate, and to expose the first surface of the rewiring layer;
7) providing an antenna circuit chip, and bonding the antenna circuit chip to the first metal wiring layer of the rewiring layer, so that the antenna circuit chip is electrically connected to the antenna metal layer from the first metal wiring layer and the metal connecting column; and
8) forming a metal bump on the first metal wiring layer of the rewiring layer, to form electrical lead-out of the rewiring layer.

US Pat. No. 11,114,390

SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

UNITED MICROELECTRONICS C...


1. A semiconductor device, comprising:a substrate comprising a first part surrounding a second part at a top view;
a first isolation structure disposed between the first part and the second part, to isolate the first part from the second part;
a second isolation structure disposed at at least one corner of the first part; and
a dummy pattern disposed on the second isolation structure.

US Pat. No. 11,114,389

SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...


1. A method for manufacturing a semiconductor package, comprising:(a) providing a substrate structure, wherein the substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area, the upper side rail includes an upper stress relief structure and an upper reinforcing structure, the upper stress relief structure surrounds the upper chip attach area, the upper reinforcing structure surrounds the upper stress relief structure, wherein a stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure, and a structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure, wherein the upper stress relief structure includes copper, the upper reinforcing structure includes copper, and a residual copper ratio of the upper reinforcing structure is greater than a residual copper ratio of the upper stress relief structure;
(b) attaching at least one semiconductor chip to the chip attach area; and
(c) forming an encapsulant to cover the at least one semiconductor chip.

US Pat. No. 11,114,388

WARPAGE CONTROL FOR MICROELECTRONICS PACKAGES

INTEL CORPORATION, Santa...


1. A microelectronics package, comprising:a microelectronics die;
a warpage control layer comprising at least one stiffener, wherein:a thickness of the stiffener is approximately equal to a thickness of the microelectronics die, and
a coefficient of thermal expansion (CTE) of the stiffener is approximately equal to a CTE of the microelectronics die;

a coreless substrate positioned between the microelectronics die and the warpage control layer; and
a plurality of ball grid array (BGA) connection pads disposed on the bottom surface of the coreless substrate, wherein the at least one stiffener comprises a plurality of openings associated with the plurality of BGA connection pads.

US Pat. No. 11,114,387

ELECTRONIC PACKAGING STRUCTURE

INDUSTRIAL TECHNOLOGY RES...


1. An electronic packaging structure, comprising:a substrate;
a conductive layer disposed on the substrate;
a stress buffering material disposed on the substrate and adjacent to the conductive layer;
an electronic device disposed on the conductive layer and the stress buffering material; and
an intermetallic compound disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material,
wherein the intermetallic compound disposed between the electronic device and the conductive layer has a first thickness; a maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is a second thickness; and the second thickness is greater than the first thickness.

US Pat. No. 11,114,386

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

MITSUBISHI ELECTRIC CORPO...


1. A semiconductor device comprising:a single lead frame;
a semiconductor element that is joined onto one main surface of the single lead frame; and
a mold material that covers the one main surface of the single lead frame and seals the semiconductor element, wherein
the single lead frame includesa die-attach portion to which the semiconductor element is joined,
a signal terminal portion electrically joined to the semiconductor element through a thin metal wire, and
a ground terminal portion connected to a ground potential and disposed on an outer circumferential portion of the mold material in a plan view,

the die-attach portion, the signal terminal portion and the ground terminal portion are disposed directly below the mold material so as to be arranged in a direction along the one main surface, and
a groove portion formed in a partially removed portion of the single lead frame such that the groove portion passes through the single lead frame, the groove portion being provided between the die-attach portion and the ground terminal portion that are adjacent to each other and between the signal terminal portion and the ground terminal portion that are adjacent to each other, further comprising:
a coating film formed on an other main surface on an opposite side of the one main surface of each of the die-attach portion, the signal terminal portion and the ground terminal portion; and
an oxide film formed on a second side surface of the groove portion,
the die-attach portion, the signal terminal portion and the ground terminal portion being located to adjoin to the groove portion along the second side surface.

US Pat. No. 11,114,385

PLATE-SHAPED WORKPIECE PROCESSING METHOD

DISCO CORPORATION, Tokyo...


1. A plate-shaped workpiece processing method for dividing a plate-shaped workpiece into a plurality of individual packages along a plurality of crossing division lines, the workpiece including a wiring member having a first surface and a second surface opposite to the first surface, the first surface of the wiring member being partitioned into a plurality of regions by the plurality of crossing division lines, a plurality of terminals formed on each region of the first surface of the wiring member, a plurality of semiconductor chips mounted on the second surface of the wiring member by bonding, and a sealing layer formed on the second surface of the wiring member so as to seal the plurality of semiconductor chips, the sealing layer being formed from a sealing compound, the plate-shaped workpiece processing method comprising:a protective member attaching step of attaching a protective member to the first surface of the wiring member, the protective member having an adhesive layer for protecting the plurality of terminals and a base sheet attached to the adhesive layer;
a dividing step of dividing the plate-shaped workpiece and the protective member along each division line of the plurality of crossing division lines after performing the protective member attaching step, thereby obtaining the individual packages in a condition where the protective member is attached to each package of the plurality of individual packages, wherein the dividing step includes cutting through both the base sheet and the adhesive layer of the protective member;
a shield layer forming step of forming a conductive shield layer on an outer surface of each package of the plurality of individual packages after performing the dividing step; and
a protective member peeling step of peeling the protective member from each package of the plurality of individual packages after performing the shield layer forming step.

US Pat. No. 11,114,384

OXIDE-PEELING STOPPER

Infineon Technologies Aus...


1. A power semiconductor die, comprising:a semiconductor body;
an insulation layer on the semiconductor body;
a passivation structure arranged above the insulation layer so as to expose a first insulation layer subsection of the insulation layer that extends to an edge of the power semiconductor die;
an interruption structure in the first insulation layer subsection;
a plurality of trenches, wherein each of the trenches includes a trench electrode that is insulated from the semiconductor body by a trench insulator; and
a plurality of contact plugs for contacting the trench electrodes and/or the semiconductor body, wherein each of the contact plugs extends from the upper surface of the insulation layer to the lower surface of the insulation layer.

US Pat. No. 11,114,383

SEMICONDUCTOR DEVICES HAVING INTEGRATED OPTICAL COMPONENTS

Micron Technology, Inc., ...


17. A semiconductor device, comprising:a substrate having a front side, a plurality of circuit elements at the front side, and a back side opposite the front side;
through-substrate vias (TSVs) extending at least partially through the substrate; conductive material in the TSVs;
an optical routing layer on the back side of the substrate and configured to optically couple with an active optical component exterior to the optical routing layer, wherein the conductive material in at least a portion of the TSVs projects past the back side of the substrate and into the optical routing layer;
conductive pillars on the front side of the substrate over and electrically coupled to the conductive material in corresponding ones of the TSVs, wherein the conductive pillars have a first height; and
under bump metallization (UBM) features on the optical routing layer and electrically coupled to the conductive material in corresponding ones of the portion of the TSVs, wherein the UBM features have a second height less than the first height.

US Pat. No. 11,114,382

MIDDLE-OF-LINE INTERCONNECT HAVING LOW METAL-TO-METAL INTERFACE RESISTANCE

INTERNATIONAL BUSINESS MA...


1. A method of fabricating an interconnect structure, the method comprising:forming a dielectric layer over one or more contacts of one or more devices;
forming a trench in the dielectric layer over one or more contacts;
depositing a barrier layer on the dielectric layer, the trench, and the one or more contacts;
forming a cap layer on one or more portions of the barrier layer, wherein forming the cap layer comprises depositing the cap layer on one or more portions of the barrier layer outside the trench to expose one or more portions of the barrier layer disposed in the trench, wherein a bottom-most portion of the trench and one or more portions of sidewalls of the trench remain exposed while forming the cap layer, wherein forming the cap layer is performed by a plasma vapor deposition (PVD) Si deposition process;
removing the one or more portions of the barrier layer disposed in the trench;
removing the cap layer from the one or more portions of the barrier layer outside the trench; and
depositing a metal interconnect layer directly on the one or more contacts to form a metal-to-metal interface between the metal interconnect layer and the one or more contacts, wherein the metal interconnect layer directly contacts the one or more contacts, wherein depositing the metal interconnect layer is formed in a single metal deposition process.

US Pat. No. 11,114,381

POWER DISTRIBUTION NETWORK FOR 3D LOGIC AND MEMORY

Tokyo Electron Limited, ...


18. A semiconductor device, comprising:a plurality of transistor pairs that are stacked over a substrate, each transistor pair of the plurality of transistor pairs including a n-type transistor and a p-type transistor that are stacked over one another;
a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs;
a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs;
one or more conductive planes formed over the substrate, the one or more conductive planes being positioned adjacent to the plurality of transistor pairs, spanning a height of the plurality of transistor pairs and being electrically coupled to the plurality of transistor pairs; and
a plurality of power rails that are positioned over the substrate and electrically coupled to the one or more conductive planes.

US Pat. No. 11,114,380

MANUFACTURING METHOD OF MEMORY DEVICE

Winbond Electronics Corp....


1. A method of manufacturing a memory device, comprising:forming an active region, a word line, and an initial bit line contact structure in a substrate; and
forming a bit line on the substrate, and removing a portion of the initial bit line contact structure not overlapped with the bit line to form a bit line contact structure,
wherein the word line extends along a first direction, the bit line extends along a second direction intersected with the first direction, the active region is intersected with the word line and the bit line and extends along a third direction different from the first direction and the second direction, and the bit line contact structure is disposed between the active region and the bit line, and
wherein a lithography process for forming the initial bit line contact structure comprises using a free-form lens array to allow a light pass through the free-form lens array before the light is incident on a photomask, the free-form lens array comprises a plurality of lenses arranged along a parallelogram-like contour having a long axis, an angle between an extending direction of the long axis and the third direction is less than an angle between the extending direction of the long axis and the first direction and is less than an angle between the extending direction of the long axis and the second direction.

US Pat. No. 11,114,379

INTEGRATED CIRCUITRY, MEMORY INTEGRATED CIRCUITRY, AND METHODS USED IN FORMING INTEGRATED CIRCUITRY

Micron Technology, Inc., ...


1. Integrated circuitry comprising:a three-dimensional (3D) array comprising tiers of electronic components;
a circuit-operative stair-step structure;
an upper conductive landing adjacent and above the circuit-operative stair-step structure; and
the circuit-operative stair-step structure comprising a circuit-operative stair flight, the stair flight comprising:vertically alternating insulative tiers and conductive tiers;
a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier; and
an uppermost of the plurality of stairs that is below the upper conductive landing having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.


US Pat. No. 11,114,378

SEMICONDUCTOR STRUCTURE WITH ULTRA THICK METAL AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor structure, comprising:a logic substrate, comprising:a semiconductor device; and
an interconnection structure over the semiconductor device, the interconnection structure having a metal layer surrounded by a dielectric layer;

an ultra thick metal (UTM) over the metal layer, the UTM comprising a top surface; and
a photo-sensitive polymer layer surrounding the UTM, the top surface of the UTM being coplanar with a top surface of the photo-sensitive polymer layer, and the photo-sensitive polymer layer being different from the dielectric layer.

US Pat. No. 11,114,377

TRANSFORMER, TRANSFORMER MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...


1. A transformer manufacturing method comprising the steps of:laminating a lower insulating layer on a surface of a semiconductor substrate;
laminating a first conductor film on the lower insulating layer by a vacuum deposition method, a chemical vapor deposition method or sputtering;
subjecting the first conductor film to patterning to form a first lower linear conductor and a second lower linear conductor that are arranged side by side so as to be spaced from each other in plan view of the semiconductor substrate, and to form a third lower linear conductor and a fourth lower linear conductor that are arranged side by side so as to be spaced from each other in plan view of the semiconductor substrate;
laminating an upper insulating layer on the lower insulating layer in which the first through fourth lower linear conductors are formed;
providing a plurality of contact vias penetrating through the upper insulating layer so that the plurality of contact vias reach a first end and a second end of the first lower linear conductor, a third end and a fourth end of the second lower linear conductor, a fifth end and a sixth end of the third lower linear conductor, and a seventh end and an eighth end of the fourth lower linear conductor, the first end being adjacent to the third end, the second end being adjacent to the fourth end, the fifth end being adjacent to the seventh end, and the sixth end being adjacent to the eighth end;
laminating a second conductor film on the upper insulating layer by the vacuum deposition method, the chemical vapor deposition method or the sputtering; and
subjecting the second conductor film to patterning to form a first upper linear conductor, a second upper linear conductor, a third upper linear conductor, and a fourth upper linear conductor so that the first through fourth upper linear conductors are in contact with the plurality of contact vias, wherein
the first upper linear conductor is formed so as to connect a first contact via positioned at the first end of the first lower linear conductor to a second contact via positioned at the fourth end of the second lower linear conductor,
the second upper linear conductor is formed so as to connect with a third contact via positioned at the second end of the first lower linear conductor,
the third upper linear conductor is formed so as to connect a fourth contact via positioned at the fifth end of the third lower linear conductor to a fifth contact via positioned at the eighth end of the fourth lower linear conductor,
the fourth upper linear conductor is formed so as to connect with a sixth contact via positioned at the sixth end of the third lower linear conductor,
the first lower linear conductor, the second lower linear conductor, the first upper linear conductor and the second upper linear conductor are connected to one another via the plurality of contact vias, thereby forming a first winding conductor having a first center axis,
the third lower linear conductor, the fourth lower linear conductor, the third upper linear conductor and the fourth upper linear conductor are connected to one another via the plurality of contact vias, thereby forming a second winding conductor having a second center axis,
each of the first and second winding conductors have a quadrangle spiral shape having a respective center axis extending in a direction parallel to the surface of the semiconductor substrate,
the first and second winding conductors are spaced from one another and are magnetically coupled to each other, and
the second winding conductor encircles the first center axis and the first winding conductor encircles the second center axis, the second center axis being offset from the first center axis in a direction perpendicular to the first center axis.

US Pat. No. 11,114,376

SYSTEM FOR LAYOUT DESIGN OF STRUCTURE WITH INTER LAYER VIAS

TAIWAN SEMICONDUCTOR MANU...


1. A system for manufacturing a semiconductor device, the system comprising:at least one processor; and
at least one memory including computer program code for one or more programs; and
wherein, for a layout diagram stored on a non-transitory computer-readable medium, the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute a method which includes generating the layout diagram including:selecting a circuit cell which includes an active element;
bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit;
placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and
placing a metal pattern in a second device layer of the layout diagram; and

wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.

US Pat. No. 11,114,375

3D STACKED MEMORY AND VERTICAL INTERCONNECT STRUCTURES FOR 3D STACKED MEMORY


1. A 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate,wherein vertical memory stacks and a vertical interconnect structure are provided in the cell region,
wherein the vertical interconnect structure includes:
a via-hole formed along a vertical direction of the cell region;
a conductive pillar shaped by filling the via-hole with a conductive material; and
a gate insulating film stack, a semiconductor layer for forming a channel, and an insulating film which are sequentially arranged between an inner peripheral surface of the via-hole and the conductive pillar,
wherein the insulating film is configured to surround an outer peripheral surface of the conductive pillar, and
wherein a lower end of the vertical interconnect structure is electrically connected to a conductive wiring line, a conductive region provided on the substrate, or a specific wiring line region of a circuit portion.

US Pat. No. 11,114,374

GRAPHENE ENABLED SELECTIVE BARRIER LAYER FORMATION

TAIWAN SEMICONDUCTOR MANU...


1. An interconnect structure comprising:a first contact feature in a first dielectric layer;
a second dielectric layer over the first dielectric layer;
a second contact feature over the first contact feature;
a barrier layer between the second dielectric layer and the second contact feature; and
a carbon layer disposed between the second contact feature and the first contact feature, the carbon layer being in contact with the second contact feature,
wherein the barrier layer terminates over a top surface of the carbon layer and does not extend between the second contact feature and the carbon layer.

US Pat. No. 11,114,373

METAL-INSULATOR-METAL STRUCTURE

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device, comprising:a metal-insulator-metal structure comprising:a bottom conductor plate layer comprising a first opening and a second opening,
a first dielectric layer over the bottom conductor plate layer,
a middle conductor plate layer over the first dielectric layer, the middle conductor plate layer comprising a third opening, a first dummy plate disposed within the third opening, and a fourth opening,
a second dielectric layer over the middle conductor plate layer, and
a top conductor plate layer over the second dielectric layer, the top conductor plate layer comprising a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening,
wherein the first opening, the first dummy plate, and the second dummy plate are vertically aligned.


US Pat. No. 11,114,372

INTEGRATED CIRCUIT, CIRCUIT BOARD WITH INTEGRATED CIRCUIT, AND DISPLAY DEVICE USING THE SAME

LG DISPLAY CO., LTD., Se...


1. An integrated circuit comprising:a main body having a top and a bottom; and
upper pins placed on the top of the main body, and lower pins placed on the bottom of the main body,
wherein each of the upper pins has a first protruding portion protruding straightly toward outside from at least one side of the main body, and a first region extending from the first protruding portion and bent so that at least a portion of the first region faces and parallels the top of the main body, and
wherein each of the lower pins has a second protruding portion straightly protruding toward outside from the at least one side of the main body, and a second region extending from the second protruding portion and bent so that at least a portion of the second region faces and parallels the bottom of the main body.

US Pat. No. 11,114,371

SUBSTRATE-ON-SUBSTRATE STRUCTURE AND ELECTRONIC DEVICE COMPRISING THE SAME

SAMSUNG ELECTRO-MECHANICS...


1. A substrate-on-substrate structure, comprising:a first printed circuit board having a first side and a second side, opposite to the first side;
a second printed circuit board disposed on the second side of the first printed circuit board, the second printed circuit board having a first side connected to the second side of the first printed circuit board, and the second printed circuit board having a second side opposite to the first side of the second printed circuit board;
a reinforcing structure attached to the first side of the second printed circuit board, and spaced apart from the second side of the first printed circuit board; and
an underfill resin disposed between the second side of the first printed circuit board and the first side of the second printed circuit board, and covering at least a portion of the reinforcing structure,
wherein the underfill resin is disposed in at least a portion between the second side of the first printed circuit board and the reinforcing structure.

US Pat. No. 11,114,370

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...


1. A semiconductor device package, comprising:a substrate;
a redistribution structure disposed over the substrate and including a first dielectric layer and a first conductive layer;
a conductive pad disposed on a first surface of the first dielectric layer;
a conductive element disposed in the first dielectric layer and electrically connected to the conductive pad; and
a conductive via extending from the conductive pad toward the substrate through the conductive element and the first dielectric layer,
wherein the first conductive layer is separated from the conductive via,
wherein the redistribution structure further comprises:
a second dielectric layer disposed between the first dielectric layer and the substrate; and
a second conductive layer disposed in the first dielectric layer and the second dielectric layer, and electrically connected to the conductive element;
wherein the conductive via extends through the second dielectric layer and,
wherein the second conductive layer is separated from the conductive via.

US Pat. No. 11,114,369

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY SINGAPOR...


1. A semiconductor device, comprising:a substrate comprising:a dielectric layer comprising:a dielectric layer top side;
a dielectric layer bottom side opposite the dielectric layer top side; and
dielectric layer outermost sides that extend between the dielectric layer top side and the dielectric layer bottom side, the dielectric layer outermost sides defining a periphery of the dielectric layer;

a conductive pattern along the dielectric layer top side; and
a conductive edge structure at the periphery of the dielectric layer; and

a semiconductor die coupled to the conductive pattern, wherein:
the conductive edge structure comprises a lower conductive layer and an upper conductive layer in contact with the lower conductive layer;
the upper conductive layer comprises an upper conductive layer outermost side that provides a first portion of a substrate outermost side of a periphery of the substrate;
the upper conductive layer extends a first distance from a first dielectric layer outermost side of the dielectric layer outermost sides;
the upper conductive layer comprises an upper conductive layer top side that provides a first portion of a substrate top side;
the lower conductive layer comprises a lower conductive layer outermost side that provides a second portion of the substrate outermost side;
the lower conductive layer extends a second distance from the first dielectric layer outermost side;
the lower conductive layer comprises a lower conductive layer bottom side that provides a first portion of a substrate bottom side; and
the second distance is different from the first distance.

US Pat. No. 11,114,368

BASE MATERIAL, MOLD PACKAGE, BASE MATERIAL MANUFACTURING METHOD, AND MOLD PACKAGE MANUFACTURING METHOD

DENSO CORPORATION, Kariy...


1. A base material comprising:one surface; and
a side surface continuous with the one surface, wherein
each of the one surface and the side surface has a sealed region to be sealed with a mold resin,
the one surface includes a one surface rough region that has a rough shape in the sealed region,
the side surface includes a side surface rough region that has a rough shape in the sealed region,
each of the one surface rough region and the side surface rough region is provided by a plurality of metal particles stacked on one another,
the one surface includes a connection region to be connected to a connection member in the sealed region,
the one surface rough region is provided in a region different from the connection region,
the one surface rough region includes a first rough region disposed adjacent to the connection region, and a second rough region disposed on a side opposite to the connection region with respect to the first rough region,
the first rough region is provided by the plurality of metal particles stacked on one another, and
the second rough region is formed with a groove and is provided by the plurality of metal particles stacked in a region including the groove, and a height difference between protrusions and recesses of the second rough region is greater than that of the first rough region.

US Pat. No. 11,114,366

SEMICONDUCTOR STRUCTURE WITH BURIED CONDUCTIVE LINE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor structure, comprising:a first well region over a substrate;
an isolation structure over the first well region;
a first transistor over the first well region, wherein the first transistor comprises a gate structure and a gate spacer over sidewalls of the gate structure; and
a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor, wherein a top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure, and wherein a portion of the first buried conductive line is covered by the gate spacer.

US Pat. No. 11,114,365

ELECTRONIC ELEMENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

KYOCERA CORPORATION, Kyo...


1. An electronic element mounting substrate, the substrate comprising:a first substrate comprising a first main surface and a second main surface opposite to the first main surface; and
a plurality of second substrates each comprising a third main surface and a fourth main surface opposite to the third main surface,
the first substrate comprising a mounting portion for mounting an electronic element, positioned on the first main surface,
the mounting portion having a rectangular shape,
one end portion of the mounting portion in a longitudinal direction being positioned at an outer edge portion of the first main surface,
the plurality of second substrates being formed of a carbon material,
the third main face of the second substrate which is positioned closest to the first substrate facing the second main surface,
the plurality of second substrates are stacked in a thickness direction of the first substrate, whereina thermal conduction of the mounting portion in a direction perpendicular to the longitudinal direction is greater than a thermal conduction of the mounting portion in the longitudinal direction, in the third main surface of the second substrate which is positioned closest to the first substrate, in plan view,
two adjacent second substrates of the plurality of second substrates are so configured that a direction in which a thermal conductivity of one of the two adjacent second substrates increases and a direction in which a thermal conductivity of the other of the two adjacent second substrates increases are perpendicular to each other in plan view, and
each of the plurality of second substrates comprises a first side surface on a side where the one end portion is located in plan view, and is so configured that a thermal conduction in the first side surface in a thickness direction is greater than a thermal conduction in a direction perpendicular to the thickness direction.


US Pat. No. 11,114,364

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...


1. A semiconductor package, comprising:a first substrate;
a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall being spaced apart from the second sidewall in a first direction;
a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure;
a heat sink covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate;
a thermal interface material layer between the first semiconductor structure and the heat sink and between the second semiconductor structure and the heat sink, the thermal interface material layer including a first thermal interface material segment between the first and second semiconductor structures and a second thermal interface material segment that protrudes beyond the second sidewall, a first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first thermal interface material segment being less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second thermal interface material segment; and
a first under-fill layer between the first substrate and the first semiconductor structure,
wherein the first under-fill layer includes a first under-fill protrusion that protrudes beyond the first sidewall,
wherein the first thermal interface material segment is spaced apart from the first under-fill protrusion to provide an empty space therebetween,
wherein the first thermal interface material segment extends in a second direction perpendicular to the first direction, thereby protruding outwardly from a gap region between the first and second semiconductor structures, and
wherein the bottom surface of the first thermal interface material segment has a step difference.

US Pat. No. 11,114,363

ELECTRONIC PACKAGE ARRANGEMENTS AND RELATED METHODS

Qorvo US, Inc., Greensbo...


1. An electronic package comprising:a substrate forming a first face and a second face that opposes the first face;
a first electronic device mounted on the first face of the substrate;
an overmold body on the first face of the substrate and arranged around peripheral edges of the first electronic device, the overmold body forming a first recess that extends through the overmold body to the first face of the substrate;
a heat spreader arranged over the first electronic device such that the first electronic device is between the heat spreader and the substrate, and the heat spreader is further arranged within the first recess such that the heat spreader is thermally coupled to the first electronic device and the first face of the substrate; and
a bottom heat sink on the second face of the substrate, wherein a heat dissipation path is formed between the heat spreader and the bottom heat sink that extends through the first recess and the substrate.

US Pat. No. 11,114,362

STACKED SEMICONDUCTOR PACKAGE HAVING HEAT DISSIPATION STRUCTURE

SK hynix Inc., Icheon-si...


1. A stacked semiconductor package comprising:a first die;
a second die stacked on a surface of the first die;
a heat dissipation layer disposed on the surface;
a heat insulation layer disposed on the surface to cover the heat dissipation layer and the first die;
a heat sink disposed on the second die; and
a heat conduction structure spaced apart from the second die in a lateral direction on the surface to connect the heat dissipation layer to the heat sink,
wherein the heat insulation layer covers at least a portion of an upper surface of the heat dissipation layer, and
wherein the stacked semiconductor package further comprises a mold layer burying the second die and the heat conduction structure between the first die and the heat sink.

US Pat. No. 11,114,361

ELECTRONICS ASSEMBLIES AND METHODS OF MANUFACTURING ELECTRONICS ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE

INTELLIGENT PLATFORMS, LL...


1. An electronics assembly, comprising:a printed circuit board (PCB) comprising two or more cutouts;
an electronic device; and
a heat spreader arranged to dissipate heat generated by the electronic device and comprising a base surface and two or more legs extending outwardly from the base surface, each of the legs having an end portion soldered in a respective cutout of the two or more cutouts,
wherein the PCB further comprises two or more solder pads disposed in the two or more cutouts, respectively, and wherein the end portions are soldered to a respective solder pad.

US Pat. No. 11,114,360

MULTI-DIE DEVICE STRUCTURES AND METHODS

XILINX, INC., San Jose, ...


1. A method for forming a mufti-die structure, the method comprising:attaching a first die and a second die to an interposer, a first gap being defined by and between the first die and the second die;
etching at least one of the first die or the second die at the first gap, the etching defining a second gap defined by and between the first die and the second die; and
encapsulating the first die, the second die, and the interposer with an encapsulant, the encapsulant being disposed in the second gap.

US Pat. No. 11,114,359

WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE

Dialog Semiconductor (UK)...


1. A wafer level chip scale package comprising:a silicon die, comprising:at least one redistribution layer (RDL);
a passivation layer on said RDL; and
at least one copper post at a top surface of said silicon die, said at least one copper post contacting said at least one RDL through an opening in said passivation layer to said at least one RDL wherein said at least one copper post has a larger diameter than a diameter of said opening to said at least one RDL;

wherein a bottom surface of said silicon die is die attached to a metal substrate comprising:a solder substrate;
a copper layer on said solder substrate;
a copper or nickel-plated layer on said copper layer; and
a stopper layer on said copper or nickel-plated layer comprising epoxy-based composite or pre-impregnated composite fiber (PP) materials wherein said silicon die is above said copper or nickel-plated layer and said stopper layer lies between said silicon die and said copper or nickel-plated layer to prevent copper or nickel from penetrating into said silicon die; and
metal vias through a lamination layer spaced from sidewall of said copper layer by said copper or nickel-plated layer on sidewalls of said copper layer, on sidewalls and overlying said silicon die, and overlying said metal substrate, said metal vias providing connections to said at least one copper post on said silicon die and to at least one metal pad on said metal substrate.


US Pat. No. 11,114,358

SEMI-CONDUCTOR PACKAGE

Samsung Electro-Mechanics...


1. A semiconductor package, comprising:a substrate;
a plurality of electronic components mounted on a first surface of the substrate; and
an encapsulant disposed on the first surface of the substrate so that at least one of the plurality of electronic components is embedded in the encapsulant;
wherein the substrate comprises a flow preventing portion including at least one flow preventing groove disposed in the first surface and adjacent to the encapsulant and/or at least one dam disposed on the first surface and adjacent to the encapsulant, and
wherein the at least one flow preventing groove or the at least one dam is spaced apart from the encapsulant by 80 ?m to 100 ?m.

US Pat. No. 11,114,357

METHODS AND APPARATUS FOR PACKAGE WITH INTERPOSERS

Taiwan Semiconductor Manu...


1. A structure, comprising:a substrate, the substrate comprising a die attach region, an underfill region, and a connect region, wherein the underfill region includes the die attach region and an area surrounding the die attach region, and wherein the connect region is disposed outside the underfill region;
an embedded device, the embedded device disposed within the substrate;
a first contact pad and a second contact pad, wherein the first contact pad is disposed within the die attach region, wherein the second contact pad is disposed in the connect region, wherein the second contact pad is a nearest contact pad to the die attach region; and
a first dam over the substrate, the first dam comprising a first layer of conductive material, wherein the first dam surrounds the underfill region, wherein a cross-sectional width of the first dam is greater than or equal to a shortest distance between the first dam and the second contact pad.

US Pat. No. 11,114,356

GLASS SUBSTRATE AND LAMINATED SUBSTRATE

AGC Inc., Tokyo (JP)


1. A glass substrate, comprising a glass having a density of from 2.40 g/cm3 to 2.60 g/cm3; whereinthe glass substrate has a circular shape,
a value W/D of warpage W (unit: ?m) divided by the diameter D (unit: inch) of the circular glass substrate is from 1 to 13,

the glass substrate has a warpage of 2 ?m to 300 ?m,
a maximum local inclination angle due to the warpage of the glass substrate is from 0.0004° to 0.12°, and
a thickness deviation of the glass substrate is from 2.5 ?m to 15 ?m.

US Pat. No. 11,114,355

POWER MODULE AND METHOD FOR MANUFACTURING POWER MODULE

MURATA MANUFACTURING CO.,...


1. A power module comprising:a power wiring line provided with a power element;
a glass ceramic multilayer substrate provided with a control element to control the power element; and
a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate; wherein
the power wiring line is disposed at a same or substantially a same position in a thickness direction of the glass ceramic multilayer substrate as at least one layer of the glass ceramic multilayer substrate;
the power element is bonded to a first surface of the power wiring line; and
the glass ceramic multilayer substrate and the power wiring line are each disposed directly on a surface of the highly heat-conductive ceramic substrate such that a second surface of the power wiring line is at an interface between the highly heat-conductive ceramic substrate and the glass ceramic multilayer substrate.

US Pat. No. 11,114,354

PRINTED WIRING BOARD, PRINTED CIRCUIT BOARD, PREPREG

PANASONIC INTELLECTUAL PR...


1. A printed wiring board comprising:an inner insulating layer including a conductive wire;
a first outermost insulating layer disposed on a first surface of the inner insulating layer; and
a second outermost insulating layer disposed on a second surface of the inner insulating layer, wherein:each of the first outermost insulating layer and the second outermost insulating layer is a cured product of a prepreg, the prepreg including a thermosetting resin composition and a base material impregnated with the thermosetting resin composition,
the thermosetting resin composition includes an elasticity lowering agent,
the elasticity lowering agent includes at least one selected from the group consisting of ethylene-acrylic rubber including carboxyl group, nitrile rubber including carboxyl group, core-shell type rubber, acrylic rubber powers, and silicone powders,

a bending elastic modulus of each of the first outermost insulating layer and the second outermost insulating layer ranges from ¼ to ¾, inclusive, of a bending elastic modulus of the inner insulating layer, and
a glass transition temperature of each of the first outermost insulating layer and the second outermost insulating layer falls within ±20° C. of a glass transition temperature of the inner insulating layer.

US Pat. No. 11,114,353

HYBRID MICROELECTRONIC SUBSTRATES

Intel Corporation, Santa...


1. A hybrid microelectronic substrate, comprising:a low-density microelectronic substrate (LDMS) having a recess at a first surface, wherein the LDMS includes a first conductive pathway that extends to a bottom surface of the recess, and the LDMS is a printed circuit board (PCB); and
a high-density microelectronic substrate (HDMS) at least partially in the recess and coupled to the bottom surface of the recess via solder interconnects, wherein the HDMS has a first surface and an opposing second surface, the first surface of the HDMS is between the second surface of the HDMS and the bottom surface of the recess, the HDMS has a first conductive contact at the first surface of the HDMS, the first conductive contact is coupled to the first conductive pathway via a solder interconnect, the HDMS includes a second conductive pathway that extends between the second surface of the HDMS and the first conductive contact, the HDMS has a second conductive contact at the second surface of the HDMS, the HDMS does not include a semiconductor layer, the HDMS includes a stack of layers of dielectric material, and the stack extends from the first surface of the HDMS to the second surface of the HDMS.

US Pat. No. 11,114,352

PROCESS MONITOR CIRCUITRY WITH MEASUREMENT CAPABILITY


1. A circuit comprising:a process monitor circuit comprising a current source, at least one composite circuit element and an analog-to-digital converter (ADC), wherein current from said current source is dropped across said at least one composite circuit element generating a voltage which is measured as a measurement by said ADC, and said measurement yields information about at least one process dependent parameter,
wherein the current source comprises a switched capacitor current source that comprises a flying capacitor Cfl coupled to non-overlapping switches, which receive anti-phase frequency inputs from clocks ?1 and ?2, and said flying capacitor is switched between voltages Vfb and Vss, such that its current is:I=CflyVfbf

where f represents frequency; and said flying capacitor comprises an MOS device and said switched capacitor current is mirrored or driven across said composite device.

US Pat. No. 11,114,351

DUMMY ELEMENT AND METHOD OF EXAMINING DEFECT OF RESISTIVE ELEMENT

FUJI ELECTRIC CO., LTD., ...


1. A dummy element for simulating a defective state of a resistive element of a target to be examined, the dummy element comprising:a semiconductor substrate;
a lower insulating film deposited on the semiconductor substrate;
a first resistive layer deposited on the lower insulating film;
an interlayer insulating film covering the first resistive layer;
a first pad-forming electrode, deposited on the interlayer insulating film, having a contact portion directly connected to the first resistive layer, and an extending portion separate from the contact portion in Schottky contact with the semiconductor substrate so as to cause a short circuit between the first pad-forming electrode and the semiconductor substrate to simulate a Schottky contact state;
a relay wire connected on one side to the first resistive layer and connected at another portion to the semiconductor substrate with an ohmic contact; and
a counter electrode allocated under the semiconductor substrate,
wherein
the Schottky contact state corresponds to a state in which a corresponding lower insulating film of the resistive element and a corresponding interlayer insulating film of the resistive element are defective.

US Pat. No. 11,114,350

METHOD FOR REMOVING PHOTORESIST FROM PHOTOMASK SUBSTRATE

Applied Materials, Inc., ...


1. A method for removing a photoresist from a substrate in a chamber, comprising:generating a first plasma including first radicals from a first gas mixture supplied into a processing chamber;
exposing a first portion of the photoresist to the first radicals to remove the first portion of the photoresist from the substrate;
collecting a first signal at an OES detector, after exposing the first portion;
adjusting the first gas mixture supplied into the processing chamber based upon types of first radicals detected from the first signal;
generating a second plasma including second radicals from a second gas mixture supplied into the processing chamber, wherein the second radicals have a different composition than the first radicals;
exposing a second portion of the photoresist to the second radicals to remove the second portion of the photoresist from the substrate, wherein the second portion is a residual of the first portion;
collecting a second signal at the OES detector, after exposing the second portion;
adjusting the second gas mixture supplied into the processing chamber;
generating a first endpoint based upon an intensity of the first signal;
generating a second endpoint based upon an intensity of the second signal; and
removing the first portion based upon the first endpoint, and removing the second portion based upon the second endpoint.

US Pat. No. 11,114,349

SYSTEM AND METHOD FOR ALLOWING RESTORATION OF FIRST INTERCONNECTION OF DIE OF POWER MODULE

MITSUBISHI ELECTRIC CORPO...


1. A system for allowing the restoration of a first interconnection of a die of a power module connecting the die to an electric circuit, characterized in that the system comprises:at least one other interconnection of the power module,
a periodic current source that is connected to the at least one other interconnection for generating a high frequency periodic current flow through the at least one other interconnection in order to reach, in at least a part of the first interconnection, a predetermined temperature during a predetermined time duration in order to allow the restoration of the first interconnection by increasing the first interconnection temperature and by increasing the pressure along crack in the first interconnection and thereby increasing a rate of diffusion in cracks causing the crack to heal and wherein the interconnections are bond wires or the interconnections are copper vias, the periodic current source is connected to two other interconnections and the power module further comprises one induction coil that is connected to the two interconnections in order to reach, in at least a part of the first interconnection, the predetermined temperature during the predetermined time duration or the power module further comprises one magnetic structure that is connected to the two interconnections in order to reach, in at least a part of the first interconnection, the predetermined temperature during the predetermined time duration.

US Pat. No. 11,114,348

HYBRID HIGH-VOLTAGE LOW-VOLTAGE FINFET DEVICE

Microsemi SoC Corp., San...


1. An integrated circuit including a plurality of low-voltage FinFET transistors formed on a substrate, each low-voltage FinFET transistor including a first gate dielectric having a plurality of layers, the plurality of layers including a first dielectric layer formed from a first dielectric material having a first thickness and a second dielectric layer formed from a second dielectric material different from the first dielectric material and having a second thickness, the second dielectric material being a high-k dielectric material and overlying the first dielectric layer, the integrated circuit comprising:a plurality of hybrid FinFET transistors, each hybrid FinFET transistor formed on the substrate and including:
a respective fin extending upward from the substrate;
a second gate dielectric surrounding a portion of the fin, the second gate dielectric having a greater thickness than the thickness of the first gate dielectric layer in each of the plurality of low-voltage FinFET transistors, the second gate dielectric including a first layer formed from the first dielectric material having a third thickness, a second layer formed from the first dielectric material overlying the first layer of the first dielectric material that is the same layer as the first dielectric layer in the first gate and having the first thickness, and a third layer formed from the second dielectric material overlying the second layer of the first dielectric material that is the same layer as the high-k material second dielectric layer in the first gate and having the second thickness;
a gate electrode disposed over the second gate dielectric and surrounding a portion of the fin, a channel in the respective fin defined by a portion of the fin disposed surrounded by the gate electrode;
portions of the respective fin extending past opposite edges of the gate electrode forming source and drain regions,
the channel in the respective fin formed by:performing a low-voltage threshold implant in the channel regions of both the low-voltage FinFET transistors and the hybrid FinFET transistors; and
performing an additional implant in the channel region of each of the hybrid FinFET transistors.


US Pat. No. 11,114,347

SELF-PROTECTIVE LAYER FORMED ON HIGH-K DIELECTRIC LAYERS WITH DIFFERENT MATERIALS

Taiwan Semiconductor Manu...


1. A method of forming a semiconductor device, the method comprising:removing a first dummy gate structure disposed in a p-type device region to form a first opening;
removing a second dummy gate structure and a third dummy gate structure disposed in an n-type device region to form a second opening and a third opening, respectively, the third opening being between the first opening and the second opening, the first opening, the second opening, and the third opening being surrounded by a dielectric layer, wherein each of the first opening, the second opening, and the third opening exposes respective portions of a first fin and a second fin;
forming a first gate dielectric layer in the first opening and forming a second gate dielectric layer in the second opening and the third opening, the first gate dielectric layer having a different composition from the second gate dielectric layer, each of the first gate dielectric layer and the second gate dielectric layer being a single-layer dielectric material, wherein a first sidewall of the first gate dielectric layer contacts and extends along a second sidewall of the second gate dielectric layer;
forming a first work function layer over the first gate dielectric layer and over the second gate dielectric layer;
forming a first mask layer over the first work function layer, wherein the first mask layer covers the first work function layer in the second opening on the first fin, and exposes the first work function layer in the first and third openings on the first fin, wherein portions of the first mask layer extend into the third opening and cover the first work function layer in the third opening on the second fin;
removing exposed portions of the first work function layer from the first opening and from the third opening using an etching process performed with an etching solution, wherein the etching solution reacts with the first gate dielectric layer and the second gate dielectric layer, wherein the first mask layer protects underlying portions of the first work function layer from the etching solution, wherein after the etching process, the first work function layer in the third opening on the second fin remains, a first self-protective layer is formed in the first opening over the first gate dielectric layer by the etching process, and a second self-protective layer is formed in the third opening over the second gate dielectric layer by the etching process, wherein the first self-protective layer extends along sidewalls and upper surfaces of the first fin and the second fin in the first opening, wherein the second self-protective layer extends along the sidewalls and the upper surface of the first fin in the third opening, and the sidewalls and the upper surface of the second fin in the third opening are free of the second self-protective layer, wherein the first self-protective layer and the second self-protective layer have different compositions;
forming a second work function layer in the first opening over the first self-protective layer and in the third opening over the second self-protective layer, but not in the second opening, wherein the second work function layer in the first opening extends along the sidewalls and the upper surfaces of the first fin and the second fin, wherein the second work function layer in the third opening extends along the sidewalls and the upper surface of the first fin, wherein the sidewalls and the upper surface of the second fin in the third opening are free of the second work function layer; and
filling the first opening, the second opening, and the third opening with a conductive material to from a first gate electrode in the first opening, a second gate electrode in the second opening, and a third gate electrode in the third opening, wherein the first gate electrode contacts the second work function layer over the first fin and over the second fin, wherein the third gate electrode contacts the second work function layer over the first fin and contacts the first work function layer over the second fin.

US Pat. No. 11,114,346

HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING

Tokyo Electron Limited, ...


1. A method of forming transistor devices, the method comprising:forming a first transistor plane as a transistor-based circuit device on a substrate, the circuit device including a plurality of field effect transistors;
depositing a first insulator layer on the first transistor plane;
depositing a first layer of polycrystalline silicon on the first insulator layer; and
annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the first layer of polycrystalline silicon to form a first epitaxial-like silicon layer having a crystal orientation that is independent from the substrate.

US Pat. No. 11,114,345

IC INCLUDING STANDARD CELLS AND SRAM CELLS

TAIWAN SEMICONDUCTOR MANU...


1. An integrated circuit (IC), comprising:a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs), comprising:at least one first P-type GAA FET comprising a plurality of silicon (Si) channel regions vertically stacked over an N-type well region; and
at least one second P-type GAA FET comprising a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region;

at least one SRAM memory cell comprising the first P-type GAA FET; and
at least one standard cell or I/O cell comprising the second P-type GAA FET.

US Pat. No. 11,114,344

IC DIE WITH DUMMY STRUCTURES

XILINX, INC., San Jose, ...


1. An integrated circuit die comprising:a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone, the buffer zone free of active circuit devices that are part of either of the adjacent first and second circuit blocks;
the first circuit block having a first circuit block one (CB1) region adjacent the buffer zone having at least one transistor that is at least partially fabricated from a gate metal layer, the first CB1 region having a first gate metal per unit area (GMPUA);
the second circuit block having a first circuit block two (CB2) region disposed directly across the buffer zone from the first CB1 region, the first CB2 region having at least one transistor that is at least partially fabricated from the gate metal layer, the first CB2 region having a second GMPUA; and
a first dummy structure formed in a first buffer region of the buffer zone that extends from the first CB1 region to the first CB2 region, the first dummy structure at least partially fabricated from the gate metal layer, the first buffer region having a third GMPUA, wherein the first GMPUA is greater than or equal to the third GMPUA, and the third GMPUA is greater than the second GMPUA, wherein the first GMPUA is greater than the second GMPUA.

US Pat. No. 11,114,343

PARTIAL BACKSIDE METAL REMOVAL SINGULATION SYSTEM AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...


1. A method of singulating a plurality of die comprised in a substrate, the method comprising:forming a plurality of die on a first side of a substrate;
forming a backside metal layer on a second side of the substrate;
forming a groove only partially through a thickness of the backside metal layer, wherein the groove is located in a die street of the substrate; and
singulating the plurality of die comprised in the substrate through removing backmetal material in the die street and removing substrate material in the die street.

US Pat. No. 11,114,342

WAFER PROCESSING METHOD

DISCO CORPORATION, Tokyo...


1. A wafer processing method for dividing a wafer having streets demarcating a plurality of devices, the wafer processing method comprising:a step of providing a substrate having a first surface and an opposing second surface, and a functional layer laminated to the first surface;
a disposing step of disposing a protective member on the functional layer on the first surface of the substrate;
a cutting step of forming, along the streets, a cut groove having a depth exceeding a finished thickness of the wafer by making a cutting blade cut into the second surface of the substrate; and
a plasma etching step of extending the cut groove from a bottom surface of the cut groove to the functional layer on the first surface of the substrate to divide the substrate along the streets without dividing the functional layer, wherein in the plasma etching step, plasma etches the second surface in addition to the bottom surface of the cut groove.

US Pat. No. 11,114,341

LASER PROCESSING METHOD

DISCO CORPORATION, Tokyo...


1. A laser processing method for applying a laser beam to a back surface of a substrate with a device formed on a front surface thereof and including an electrode pad, to form a fine hole in the substrate that reaches the electrode pad, the method comprising:a laser beam applying step of applying the laser beam to the back surface of the substrate to form a fine hole in the substrate at a position corresponding to the electrode pad;
a detecting step of detecting, through a first optical path, first plasma light having a first wavelength emitted from the substrate at the same time that the fine hole is formed in the substrate by the laser beam applied thereto; and, through a second optical path, second plasma light having a second wavelength different from the first wavelength emitted from the electrode pad; and
a laser beam irradiation finishing step of stopping application of the laser beam when the second plasma light is detected in the detecting step,
wherein, in the laser beam applying step, a peak power density of the laser beam to be applied is set in a range from 175 GW/cm2 or less to 100 GW/cm2 or more.

US Pat. No. 11,114,340

METHOD FOR PRODUCING AN INTERCONNECTION COMPRISING A VIA EXTENDING THROUGH A SUBSTRATE


1. A method for producing an interconnection comprising a via extending through a substrate, said method comprising the following successive steps;depositing a layer of titanium nitride or tantalum nitride on a main surface of the substrate and on the inner surface of the at least one hole extending into at least part of the thickness of substrate;
depositing a layer of copper on said layer of titanium nitride or tantalum nitride;
filling the hole with copper;

said method being characterized in that, during step (a), the substrate is arranged in a first deposition chamber, and in that said step (a) comprises the injection of a titanium or tantalum precursor in a gaseous phase into the deposition chamber via a first injection path according to a first pulse sequence and the injection of a nitrogen-containing reactive gas into the deposition chamber via a second injection path different from the first injection path according to a second pulse sequence, the first pulse sequence and the second pulse sequence being out of phase, the pressure in the first deposition chamber being grater than 500 mTorr during the entire duration of step a), wherein the duration of a pulse in the first pulse sequence, respectively in the second pulse sequence, ranges from 0.02 s to 5 s; and the delay between two pulses in the first pulse sequence, respectively in the second pulse sequence, ranges from 0.02 s to 10 s, or from 0.5 s to 10 s.

US Pat. No. 11,114,339

METHOD FOR REDUCING METAL PLUG CORROSION AND DEVICE

Taiwan Semiconductor Manu...


1. A method comprising:forming a dielectric layer over a substrate, the dielectric layer having a recess;
forming a conductive layer over the dielectric layer, the conductive layer filling the recess;
planarizing the conductive layer using a CMP operation to form a conductive feature in the dielectric layer, the CMP operation having a CMP removal rate of the conductive layer greater than 30 nm/minute; and
during the CMP operation, exposing the conductive layer to a metal ion source solution, wherein a constituent metal of a metal ion in the metal ion source solution and a constituent metal of the conductive layer are the same, and wherein after the CMP operation an upper surface of the conductive feature is recessed from an upper surface of the dielectric layer by a depth of less than two nm.

US Pat. No. 11,114,338

FULLY ALIGNED VIA IN GROUND RULE REGION

GLOBALFOUNDRIES U.S. INC....


1. A method comprising:depositing a first conductive material to fill vias of minimum feature dimensions resulting in wire structures;
forming another wire structure with a larger width than the minimum feature dimensions, the another wire structure comprising a second conductive material;
recessing the first conductive material for the wire structures;
forming fully aligned vias with a selected one of the wire structures and the another wire structure with the larger width; and
depositing a conductive material in the fully aligned vias to be in electrical contact with the recessed first conductive material and the second conductive material of the another wire structure with the larger width.

US Pat. No. 11,114,337

METHOD FOR BONDING AND INTERCONNECTING SEMICONDUCTOR CHIPS

IMEC vzw, Leuven (BE)


1. A method of bonding a first semiconductor chip on a first substrate to a second semiconductor chip on a second substrate, comprising:providing a bonding layer on at least one of the first substrate and the second substrate, the bonding layer being formed of a dielectric bonding material, wherein the dielectric material is Hydrogen Silsesquioxane (HSQ), or an equivalent thereof;
bonding the first substrate to the second substrate and performing a thermal annealing, so as to obtain a stack of the substrates with a bond layer between the first substrate and the second substrate, wherein the first substrate is thinned either before or after the bonding, and wherein the thermal annealing takes place at a temperature below a temperature at which the dielectric bonding material transforms into silicon oxide;
after bonding, scanning an electron beam across an area of the thinned first substrate, an energy of the electron beam being sufficient for the electron beam to reach the bond layer and to transform the scanned dielectric bonding material of the bond layer into a silicon oxide, to thereby obtain a volume of the bond layer that is transformed into a silicon oxide, wherein the volume is essentially a closed wall extending over a full thickness of the bond layer, and enclosing a volume of bonding material, thereby separating that volume of bonding material from the rest of the bond layer;
etching a via opening through the thinned first substrate until reaching an interior of the closed wall, and a dielectric liner is formed on sidewalls of the via opening;
through the via opening, removing the dielectric bonding material from the interior of the closed wall, selectively with respect to the silicon oxide, so as to create a cavity in the bond layer and expose a conductor in the second substrate; and
filling the cavity and the via opening with an electrically conductive material, to thereby form an electrical connection that connects the conductor in the second substrate to a conductor present in the first substrate and/or to a contact present on top of the stack.

US Pat. No. 11,114,336

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...


1. A method of manufacturing a semiconductor device, the method comprising:forming a first source/drain structure over a substrate;
forming one or more first insulating layers over the first source/drain structure;
forming a first opening in the one or more first insulating layers;
filling the first opening with a first conductive material to form a first lower contact in contact with the first source/drain structure;
forming one or more second insulating layers over the first lower contact;
forming a second opening in the one or more second insulating layers to at least partially expose the first lower contact;
forming a first liner layer on at least a part of an inner side face of the second opening; and
filling the second opening with a second conductive material to form a first upper contact in contact with the first lower contact without the first liner layer interposed between the first upper contact and the first lower contact.

US Pat. No. 11,114,335

SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP STRUCTURE AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device structure, comprising:a first conductive contact and a second conductive contact disposed over a semiconductor substrate;
a first dielectric layer surrounding the first conductive contact and the second conductive contact; and
a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer, wherein the first dielectric layer is separated from the semiconductor substrate by a first air gap structure, and the first dielectric layer is separated from the second dielectric layer by a second air gap structure.

US Pat. No. 11,114,334

SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR PREPARING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device, comprising:a first bit line disposed over a semiconductor substrate;
a dielectric structure disposed over a sidewall of the first bit line;
a second bit line disposed over the semiconductor substrate, wherein the first bit line is between the second bit line and the dielectric structure, and the first bit line is separated from the second bit line by an air gap; and
a sealing dielectric layer disposed over the first bit line, the second bit line, the dielectric structure and the air gap;
wherein a top portion of the first bit line has a rounded corner, and a portion of the air gap extends between the sealing dielectric layer and the rounded corner of the first bit line.

US Pat. No. 11,114,333

METHOD FOR DEPOSITING AND REFLOW OF A HIGH QUALITY ETCH RESISTANT GAPFILL DIELECTRIC FILM

Micromaterials, LLC, Wil...


1. A method, comprising:filling one or more features formed over a substrate with a borophosphosilicate glass (BPSG) material;
treating the substrate with a high-pressure anneal in the presence of an oxidizer to heal seams within the BPSG material, comprising:supplying an oxygen-containing gas mixture into a processing chamber containing the substrate; and
thermally annealing the BPSG material in the presence of the oxygen-containing gas mixture to oxidize the BPSG material while maintaining the oxygen-containing gas mixture in the processing chamber at a process pressure greater than 2 bar; and

exposing the BPSG material to a dry anneal process to eliminate moisture.

US Pat. No. 11,114,332

SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A PLASMA NITRIDE LAYER AND METHOD OF MANUFACTURE THEREOF

GlobalWafers Co., Ltd., ...


1. A method of preparing a multilayer structure, the method comprising:depositing a handle semiconductor nitride layer on a handle dielectric layer in interfacial contact with a front surface of a single crystal silicon handle substrate, wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal silicon handle substrate, a central plane between the front surface and the back surface of the single crystal silicon handle substrate, and a bulk region between the front and back surfaces of the single crystal silicon handle substrate and further wherein the handle dielectric layer comprises a reflowable insulating layer, the reflowable insulating layer comprising a silicate glass selected from the group consisting of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, and any combination thereof; and
bonding a donor dielectric layer in interfacial contact with a front surface of a single crystal semiconductor donor substrate to the handle semiconductor nitride layer to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, a central plane between the front and back surfaces of the semiconductor donor substrate, and a bulk region between the front and back surfaces of the semiconductor donor substrate, and further wherein the single crystal semiconductor donor substrate comprises a cleave plane.

US Pat. No. 11,114,331

METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION

UNITED MICROELECTRONICS C...


1. A method for fabricating semiconductor device, comprising:forming a pad layer on a substrate, wherein the pad layer comprises:a first pad layer on the substrate; and
a second pad layer on the first pad layer;

removing part of the pad layer and the substrate to form a trench;
forming a liner in the trench after removing part of the pad layer;
performing a nitridation process to divide the liner into a first portion and a second portion, wherein the second portion comprises a lateral extending portion covering an end portion of the first portion and flush with a top surface of the substrate;
after the nitridation process, forming a dielectric layer to fill the trench;
performing a planarizing process to remove the dielectric layer so that the top surfaces of the dielectric layer and the pad layer are coplanar;
removing the second pad layer;
after removing the second pad layer, performing a dry etching process to remove the first pad layer, part of the liner, and part of the dielectric layer at the same time to form a shallow trench isolation (STI), wherein the dry etching process comprises a non-plasma etching process, and after the dry etching process, a top surface of the liner comprises a curve, and a top surface of the dielectric layer comprises a planar surface that is flush with the top surface of the substrate; and
performing an anneal process to remove residues on a top surface of the substrate after removing the first pad layer and part of the dielectric layer.

US Pat. No. 11,114,330

SUBSTRATE SUPPORT HAVING CUSTOMIZABLE AND REPLACEABLE FEATURES FOR ENHANCED BACKSIDE CONTAMINATION PERFORMANCE

Axcelis Technologies, Inc...


1. A workpiece support, comprising:an electrostatic chuck (ESC) having a support surface; and
one or more standoffs selectively removably coupled to the support surface, wherein the one or more standoffs are operable to support a workpiece at a predetermined standoff distance from the support surface.

US Pat. No. 11,114,329

METHODS FOR LOADING OR UNLOADING SUBSTRATE WITH EVAPORATOR PLANET

SEMICONDUCTOR COMPONENTS ...


9. A method for unloading a substrate from an evaporator dome, the method comprising:providing an evaporator planet comprising a plurality of pockets, each pocket comprising a substrate loaded thereon;
removing one of the plurality of substrates from one of the pockets in the planet using a robotic arm;
placing the substrate on a substrate aligner using the robotic arm and centering the substrate using the substrate aligner;
removing the substrate from the substrate aligner using the robotic arm; and
placing the substrate into a cassette using the robotic arm.

US Pat. No. 11,114,328

DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING

Micron Technology, Inc., ...


1. A system for enhancing bonding between a first substrate and a second substrate, the first substrate having a central portion and a perimeter portion, the system comprising:a unipolar electrostatic chuck configured to receive the first substrate, the chuck including a dielectric base and an electrode at least partially within the dielectric base, wherein a top surface of the electrode is configured to directly electrically contact the central portion and the perimeter portion of the first substrate;
a conductor configured to be electrically coupled to the second substrate; and
a power supply electrically coupled to the electrode and conductor, respectively, to apply an electrical bias between the electrode and conductor.

US Pat. No. 11,114,327

ESC SUBSTRATE SUPPORT WITH CHUCKING FORCE CONTROL

Applied Materials, Inc., ...


1. An apparatus for processing a substrate, the apparatus comprising a substrate support assembly, comprising:a substrate support comprising dielectric material having a sensor opening formed therethrough, wherein a surface of the dielectric material is patterned to form a recessed surface and a plurality of elevated features that extend upwardly from the recessed surface, and respective substrate-contact surfaces of the plurality of elevated features are substantially coplanar with one another; and
a sensor comprising:a sensor terminal disposed in the sensor opening, the sensor terminal comprising a transparent member disposed on an end of the sensor terminal that is proximate to the recessed surface, whereinthe sensor terminal is spaced apart from a wall of the sensor opening to define a gap therebetween,
the sensor terminal is secured to the wall of the sensor opening using one or more mounting members, and
the one or more mounting members are configured to allow a gas delivered to the sensor opening to flow around the sensor terminal towards the recessed surface;

a radiation source;
a radiation detector; and
a plurality of optical fibers coupling the radiation source and radiation detector to the sensor terminal.


US Pat. No. 11,114,326

SUBSTRATE CHUCKING AND DECHUCKING METHODS

Applied Materials, Inc., ...


9. A substrate chucking method, comprising:forming a plasma in a processing volume of a processing chamber; and
applying a chucking voltage to a chucking electrode embedded in a dielectric material of a substrate support disposed in the processing volume, the substrate support having a substrate disposed thereon,
wherein the chucking voltage applied to the chucking electrode is determined by a method comprising:positioning a contact force measurement substrate on the substrate support;
forming a plasma in the processing volume;
measuring a contact force between the contact force measurement substrate and the substrate support using one or more piezo-electric sensors disposed on the contact force measurement substrate; and
determining a chucking force correction factor, wherein the chucking force correction factor is a percent difference between the contact force determined using the contact force measurement substrate and a desired contact force at a chucking calibration voltage; and
adjusting one or both of a first chucking voltage or a second chucking voltage using the chucking force correction factor.


US Pat. No. 11,114,325

FUME-REMOVING DEVICE

Bum Je Woo, Seongnam-si ...


1. An apparatus for removing fume including:a wafer cassette;
an exhaust for exhausting the fume;
stacking shelves provided within said wafer cassette at both sides of said wafer cassette; and
a front opening provided in front of said wafer cassette,
wherein said stacking shelves include a first stacking shelf and a second stacking shelf below said first stacking shelf, and the first stacking shelf and the second stacking shelf are vertically spaced apart,
wherein said first stacking shelf includes:a purge gas inlet provided in said first stacking shelf;
a purge gas flow path provided within said first stacking shelf in a horizontal direction, for flowing purge gas supplied via said purge gas inlet, said purge gas flow path including a main flow path connected to said purge gas inlet and branch flow paths branched from said main flow path;
purge gas outlets formed on a side surface of said first stacking shelf and communicating with said branch flow paths, respectively, for supplying said purge gas into said wafer cassette, wherein some of the purge gas outlets are formed on a flat side of said side surface of said first stacking shelf and the rest of the purge gas outlets are formed on a curved side of said side surface of said first stacking shelf; and
a pin provided on said curved side where the rest of the purge gas outlets are formed for directly supporting a wafer,

wherein the apparatus further includes a side gas tube coupled to said purge gas inlet for supplying said purge gas to said purge gas inlet, and
wherein said first stacking shelf extends toward said wafer for limiting a vertical flow of said purge gas which is supplied through said purge gas outlets.

US Pat. No. 11,114,324

DEFECT CANDIDATE GENERATION FOR INSPECTION

KLA Corp., Milpitas, CA ...


1. A system configured to detect defect candidates on a specimen, comprising:an inspection subsystem configured for scanning energy over a specimen, detecting energy from the specimen during the scanning, and generating output responsive to the detected energy; and
a computer subsystem configured for:after the scanning of at least a majority of the specimen is completed, applying one or more segmentation methods to at least a substantial portion of the output generated during the scanning thereby generating two or more segments of the output;
separately detecting outliers in the two or more segments of the output; and
detecting defect candidates on the specimen by applying one or more predetermined criteria to results of said separately detecting to thereby designate a portion of the detected outliers as the defect candidates.


US Pat. No. 11,114,323

VEHICLE

Daifuku Co., Ltd., Osaka...


1. A vehicle configured to support an imaging device and to travel along a rail track, the vehicle comprising:one or more travel portions each configured to travel along at least one rail track;
a travel controller configured to perform an image recognition to determine a shape of a portion of the at least one rail track along a travel direction of the vehicle based on an image captured by the imaging device and to control the one or more travel portions based on a result of the image recognition;
an information obtaining portion configured to obtain position information of each of a plurality of locations that the one or more travel portions travel past as a result of traveling along the at least one rail track, and to obtain information on an order in which the position information of the plurality of locations is obtained; and
memory configured to store information obtained by the information obtaining portion,
wherein the travel controller is configured to:
(a) determine, based on the result of the image recognition, (i) whether a branching portion is present in which a rail track branches off from another rail track, and (ii) a configuration of the branching portion if present;
(b) select a travel direction to be taken; and
(c) control the one or more travel portions to cause the one or more travel portions to take the selected travel direction.

US Pat. No. 11,114,322

MOLD AND TRANSFER MOLDING APPARATUS

Toshiba Memory Corporatio...


1. A transfer molding apparatus, comprising:a mold;
a transfer part introducing a resin to the mold, and the transfer part configured to be movable between an initial position and a post-movement position; and
a sensor,
the mold includinga substrate clamping surface contacting a surface of a processing substrate;
a cavity recessed from the substrate clamping surface;
a suction part recessed from the substrate clamping surface;
a vent being provided on a path between the cavity and the suction part, communicating with the cavity, being recessed from the substrate clamping surface to a vent depth, and being used as an exhaust path of a gas inside the cavity;
an intermediate cavity being provided between the vent and the suction part on the path, communicating with the vent, and being recessed from the substrate clamping surface to an intermediate cavity depth deeper than the vent depth; and
an shut-off pin opening and closing the path and being provided between the intermediate cavity and the suction part on the path,

the transfer part filling the resin into the cavity in an open state of the shut-off pin,
the sensor positioned between an input of the vent and the intermediate cavity and sensing that at least a portion of the resin has passed through the vent and reached at least a portion of the intermediate cavity,
the shut-off pin being set to a closed state after the sensing by the sensor.

US Pat. No. 11,114,321

APPARATUS AND METHOD FOR REAL-TIME SENSING OF PROPERTIES IN INDUSTRIAL MANUFACTURING EQUIPMENT

Tokyo Electron Limited, ...


1. An apparatus for real-time sensing of properties within industrial manufacturing equipment, comprising:first plural sensors and second plural sensors mounted within a wafer in a processing environment of a manufacturing system, each sensor of the first plural sensors and the second plural sensors being assigned to a different region to monitor a physical or chemical property of the assigned region of the system; and
a reader system having componentry configured to simultaneously and wirelessly interrogate the first plural sensors and the second plural sensors using a single high frequency interrogation sequence that includes (1) transmitting a first request pulse signal to the first plural sensors and transmitting a second request pulse to the second plural sensors, the first request pulse signal being associated with a first frequency band, the second request pulse signal being associated with a second frequency band, and (2) receiving uniquely identifiable response signals from the first plural sensors and the second plural sensors that provide real-time monitoring of variations in the physical or chemical property at each assigned region of the system,
wherein the first plural sensors and the second plural sensors are made operable in the first frequency band and the second frequency band according to design rules that permit the simultaneous interrogation without collision between the response signals echoed from each sensor operating in the first frequency band and the second frequency band.

US Pat. No. 11,114,320

PROCESSING SYSTEM AND METHOD OF FORMING A CONTACT

APPLIED MATERIALS, INC., ...


1. A processing system comprising:a system controller;
a first process chamber, wherein the system controller is configured to cause the first process chamber to deposit a doped semiconductor layer and a metal silicide layer on an exposed surface of a source/drain region of a substrate, wherein the source/drain region is exposed through a trench formed in a dielectric material formed over the source/drain region, and the source/drain region has a first dopant concentration and the doped semiconductor layer has a second dopant concentration higher than the first dopant concentration;
a second process chamber, wherein the system controller is configured cause the second process chamber to form an anchor layer over the metal silicide layer and sidewalls of the trench;
a third process chamber, wherein the system controller is configured to cause the third process chamber to fill the trench with a conductor; and
a fourth process chamber, wherein the system controller is configured to cause the fourth process chamber to heat the substrate to reflow the conductor within the trench.

US Pat. No. 11,114,319

HEAT TREATMENT APPARATUS AND HEAT TREATMENT METHOD

TOKYO ELECTRON LIMITED, ...


1. A heat treatment apparatus comprising:a processing container configured to accommodate a substrate;
a heater provided around the processing container;
a plurality of blowing paths configured to blow a cooling medium into a space between the processing container and the heater; and
a shutter configured to simultaneously open/close at least two of the plurality of blowing units and including a slit formed corresponding to each of the blowing units.

US Pat. No. 11,114,318

ASSEMBLING APPARATUS AND ASSEMBLING METHOD FOR SEMICONDUCTOR MANUFACTURING APPARATUS

TOKYO ELECTRON LIMITED, ...


1. An assembling apparatus for a semiconductor manufacturing apparatus, the assembling apparatus comprising:a body;
a lift attached to the body and configured to move a reaction tube having an opening at a lower end portion thereof vertically;
a gas supply source configured to supply a gas into the reaction tube through the opening while the reaction tube is held by the lift; and
an exhaust path including a pump configured to exhaust an inside of the reaction tube through the opening, thereby performing a leakage test of the reaction tube while the reaction tube is held by the lift.

US Pat. No. 11,114,317

METHOD FOR CLEANING SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR WAFER USING THE METHOD FOR CLEANING

SUMCO CORPORATION, Tokyo...


1. A method for cleaning a semiconductor wafer in which the semiconductor wafer is immersed and cleaned in ozone water in a cleaning tank, the method comprising:supplying the ozone water into the cleaning tank from a lower part of the cleaning tank with the ozone water overflowing from an upper part of the cleaning tank to outside of the cleaning tank;
subsequently, stopping a supply of the ozone water;
subsequently, immersing the semiconductor wafer into the ozone water in the cleaning tank; and
subsequently, resupplying the ozone water into the cleaning tank from the lower part of the cleaning tank with the ozone water overflowing again from the upper part of the cleaning tank to the outside of the cleaning tank;
wherein:a period of time from when the supply of the ozone water is stopped until the ozone water is resupplied is set to 1 second or more to 30 seconds or less; and
a period of time from when the supply of the ozone water is stopped until a lower end of the semiconductor wafer contacts a liquid surface of the ozone water is set to 1 second or more to 10 seconds or less.


US Pat. No. 11,114,316

SUBSTRATE TREATING APPARATUS

SCREEN Holdings Co., Ltd....


1. A substrate treating apparatus that treats a substrate with processing liquids, the apparatus comprising:a substrate holder that holds a substrate horizontally;
a rotary drive that is connected to the substrate holder to rotate the substrate holder around a vertical axis;
a first processing liquid supplying nozzle that supplies a first processing liquid of the processing liquids to the substrate held with the substrate holder;
a second processing liquid supplying nozzle that supplies a second processing liquid of the processing liquids to the substrate held with the substrate holder;
an exterior cup surrounding a lateral side of the substrate holder; and
an interior cup disposed between the substrate holder and the exterior cup,
the interior cup including an interior cup body having an annular shape in plan view, and an interior cup outlet that is disposed on a lower portion of the interior cup body and discharges the first processing liquid and gas within the interior cup body, and
the exterior cup including an exterior cup body having an annular shape in plan view, an exterior bottom cup that forms a bottom of the exterior cup body, a first drain outlet that is formed in a bottom face of the exterior bottom cup and drains the first processing liquid from the interior cup outlet, a first exhaust port that is formed in the exterior bottom cup and exhausts the gas from the interior cup outlet, a second drain outlet formed in the bottom face of the exterior bottom cup and drains the second processing liquid within the exterior cup body, a second exhaust port that is formed in the exterior bottom cup and exhausts the gas in the exterior cup body, and a separation partition that is erected on the bottom face of the exterior bottom cup in an annular shape in plan view and separates the first drain outlet and the second drain outlet,
the apparatus further comprising:
an annular member formed separately from the interior cup body, having an annular shape in plan view, movable upwardly/downwardly along an outer periphery inside the exterior cup body and connected to the interior cup body so as not to close the interior cup outlet;
a shifting drive which engages and moves the annular member to shift the interior cup body between a collecting position where the interior cup collects the processing liquid and a retracting position where the exterior cup collects the processing liquid, wherein
the annular member includes a plurality of connectors that connect to the interior cup body at a corresponding plurality of points located at equal angular intervals from the center in plan view.

US Pat. No. 11,114,315

CHIP PACKAGING METHOD AND PACKAGE STRUCTURE

PEP INNOVATION PTE. LTD.,...


1. A chip package structure, comprising:at least one die;
a protective layer provided on a die active surface of the at least one die, the protective layer comprises a composite protective layer with filler particles, wherein a plurality of conductive filled vias are provided in the protective layer, and at least one of the conductive filled vias is electrically connected with die pads provided on the die active surface, wherein side protective layer surfaces are substantially aligned with side die surfaces;
an encapsulation layer, the encapsulation layer encapsulating the at least one die;
a conductive layer, at least partially provided on a surface of the protective layer, wherein at least a part of the conductive layer is electrically connected with the conductive filled vias;
a dielectric layer, provided on the conductive layer; and
wherein the protective layer comprisesYoung's Modulus and a protective layer thickness which are configured toprovide buffering and support for the conductive layer to prevent die breakage,
and prevent burring and chipping from a singulation process to separate a wafer processed with dies into individual dies, and

a coefficient of thermal expansion configured to prevent interface stress and interface fatigue between the die and the protective layer.


US Pat. No. 11,114,314

METHOD FOR FABRICATION OF A SEMICONDUCTOR STRUCTURE INCLUDING AN INTERPOSER FREE FROM ANY THROUGH VIA

Soitec, Bernin (FR)


1. A method of forming a semiconductor structure, the method comprising:introducing, at selected conditions, hydrogen and helium species in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support;
forming an interconnection layer on the temporary support, the interconnection layer comprising contact pads separated by a dielectric material and electrically conductive paths between the contact pads connecting the contact pads through the dielectric material;
placing at least one semiconductor chip on the interconnection layer to electrically couple conductive features of the chip with contact pads of the interconnection layer;
assembling a stiffener on a back side of the at least one semiconductor chip; and
providing energy to the temporary support to detach the residual part and provide the semiconductor structure.

US Pat. No. 11,114,313

WAFER LEVEL MOLD CHASE

TAIWAN SEMICONDUCTOR MANU...


1. A mold chase, comprising:a lower mold support;
an upper mold support, wherein the upper mold support and the lower mold support are configured to be pressed together to form a mold cavity therebetween for receiving a wafer level substrate;
a plurality of gates disposed along a periphery of the mold cavity and configured to allow a mold material to be injected into the mold cavity;
at least one vent disposed along the periphery of the mold cavity and configured to release gas from the mold cavity;
a plurality of trenches formed on the upper mold support and arranged along the periphery of the mold cavity, configured to communicate the mold cavity with the at least one vent;
a shutter pin configured to control the opening and closing of the trenches; and
a storage tank formed between the shutter pin and the at least one vent and configured to collect the mold material from the mold cavity;
wherein a distance between one of the gates and the closest vent is less than a diameter of the mold cavity.

US Pat. No. 11,114,312

METHOD FOR MANUFACTURING AN ENCAPSULATION COVER FOR AN ELECTRONIC PACKAGE AND ELECTRONIC PACKAGE COMPRISING A COVER

STMicroelectronics (Greno...


1. A method for manufacturing, comprising the following steps:placing at least one insert having opposite faces in a cavity of a mold having opposite surfaces, said insert positioned such that at least part of one of the opposite faces of the insert makes contact with at least part of one of the opposite surfaces of the mold;
injecting a coating material into said cavity; and
setting the coating material in order to obtain an overmolded substrate within which said insert is at least partly included to form an encapsulation cover comprising the at least one insert and at least a portion of said overmolded substrate.

US Pat. No. 11,114,311

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...


1. A method for forming a chip package structure, comprising:forming a wiring layer in a dielectric layer, wherein the dielectric layer is made of polymer;
forming a conductive structure over the dielectric layer, wherein the conductive structure is electrically connected to the wiring layer;
forming a first molding layer over the dielectric layer and surrounding the conductive structure and the dielectric layer, wherein a bottom surface of the dielectric layer and a bottom surface of the first molding layer face an identical direction;
forming a redistribution structure over the first molding layer and the conductive structure; and
bonding a chip structure to the redistribution structure to form the chip package structure, wherein the bottom surface of the dielectric layer and the bottom surface of the first molding layer are exposed from the chip package structure.

US Pat. No. 11,114,310

EMBEDDED PACKAGING METHOD CAPABLE OF REALIZING HEAT DISSIPATION

ZHUHAI ACCESS SEMICONDUCT...


1. An embedded packaging method capable of realizing heat dissipation, comprising following steps of:S1: providing a frame having at least one through hole, the frame being vertically provided with a certain number of first copper pillars, and a lower surface of the frame being a first surface;
S2: attaching a tape on the first surface so that an adhesive surface of the tape is attached to the first surface, and placing a device in the through hole with a contact of the device being attached to the tape;
S3: completely filling the through hole with photosensitive insulating material and covering a second surface opposite to the first surface, exposing the first surface and the second surface with different energies, completely curing the photosensitive insulating material in a lower portion of the through hole while not completely curing the photosensitive insulating material in an upper portion of the through hole and covered on the second surface, exposing an upper surface of the device and at least part of a side surface of the device by developing, and forming holes in regions, corresponding to the first copper pillars, of the photosensitive insulating material covered on the second surface;
S4: removing the tape, electroplating on the first surface to form a first metal layer, and electroplating on the upper surface and side surface of the device, an upper surface of the photosensitive insulating material and an upper end face of each of the first copper pillars to form a second metal layer, the second metal layer covering the upper end face of each of the first copper pillars and the upper surface and at least part of the side surface of the device; and
S5: etching the first metal layer and the second metal layer to obtain a first circuit layer and a second circuit layer, respectively, the contact of the device being electrically connected to the first circuit layer, and an upper end and a lower end of each of the first copper pillars being electrically connected to the second circuit layer and the first circuit layer, respectively.

US Pat. No. 11,114,309

ARTICLES AND METHODS OF FORMING VIAS IN SUBSTRATES

Corning Incorporated, Co...


1. An article comprising:a substrate comprising a first surface and a second surface separated by a thickness T;
at least one damage region within the substrate and extending from the first surface; and
a first film layer disposed on an undamaged region of the first surface of the substrate, the first film layer selected from a group consisting of diphenylsilicon, phenylsilicon, methylphenylsilicon, and diamond-like carbon (DLC),
wherein the first film layer is configured to be removed via oxidation from the first surface of the substrate without increasing a surface roughness (Rq) of the first surface of the substrate beyond Van der Waal bonding capability with an additional surface.

US Pat. No. 11,114,308

CONTROLLING OF HEIGHT OF HIGH-DENSITY INTERCONNECTION STRUCTURE ON SUBSTRATE

INTERNATIONAL BUSINESS MA...


1. A method for fabricating an interconnection layer carrying structure used for transferring an interconnection layer onto a substrate, the method comprising:applying a release layer onto a support substrate;
building a set of pads on the release layer;
forming an organic insulating material layer over and above the set of the pads, the organic insulating material layer being formed within a predefined area on the support substrate, wherein the organic insulating material layer overlays a base part of the support substrate corresponding to the predefined area and an extended part of the substrate laterally beyond the predefined area is free from the organic insulating material layer; and
building a plurality of traces on the organic insulating material layer.

US Pat. No. 11,114,307

METHOD OF PRODUCING A WAFER FROM AN INGOT INCLUDING A PEEL-OFF DETECTING STEP

DISCO CORPORATION, Tokyo...


1. A method of producing a wafer from a hexagonal single-crystal ingot, comprising the steps of:forming a peel-off layer in the hexagonal single-crystal ingot by applying a laser beam having a wavelength transmittable through the hexagonal single-crystal ingot while positioning a focal point of the laser beam in the hexagonal single-crystal ingot at a depth corresponding to a thickness of a wafer to be produced from an end face of the hexagonal single-crystal ingot;
generating ultrasonic waves from an ultrasonic wave generating unit positioned in facing relation to the wafer to be produced across a water layer interposed therebetween, thereby to break the peel-off layer; and
positioning an image capturing unit sideways of the wafer to be produced and detecting when the wafer to be produced is peeled off the hexagonal single-crystal ingot
wherein the image capturing unit is configured and arranged to capture an image of a gap between the wafer to be produced and an upper surface of a remaining portion of the hexagonal single-crystal ingot.

US Pat. No. 11,114,306

METHODS FOR DEPOSITING DIELECTRIC MATERIAL

APPLIED MATERIALS, INC., ...


1. A method of depositing a dielectric material comprising:providing a first gas to form a gas mixture delivered to an interior processing region of the processing chamber having a substrate disposed therein;
forming a remote plasma in a remote plasma source connected to a lid of the processing chamber and delivering the remote plasma to the interior processing region defined in the processing chamber;
applying an RF bias power to a substrate support member disposed in the processing chamber in pulsed mode; and
depositing the dielectric material, while applying the RF bias power, in an opening defined in a material layer disposed on an interface layer of the substrate in the presence of the gas mixture and the remote plasma,
wherein the dielectric material is either a silicon nitride material or a silicon carbide material.

US Pat. No. 11,114,305

ETCHING METHOD AND SEMICONDUCTOR MANUFACTURING METHOD

SHOWA DENKO K.K., Tokyo ...


1. An etching method, comprising treating a workpiece having a stacked film of a silicon oxide layer and a silicon nitride layer with an etching gas containing an unsaturated halon represented by the following chemical formula: C2HxF(3?x)Br (in the chemical formula, x stands for 0, 1, or 2) to etch both the silicon oxide layer and the silicon nitride layer.

US Pat. No. 11,114,304

SUBSTRATE PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...


1. A substrate processing method comprising:forming a film on a substrate having a pattern using plasma, wherein the film includes a silicon-containing film, and wherein forming of the film is controlled to control a film forming area and to control a film forming amount in the film forming area;
after forming of the film, generating plasma in a processing chamber where the substrate is disposed to form a reaction layer on a surface of the film, wherein the reaction layer includes ammonium fluorosilicate; and
applying energy to the substrate where the reaction layer is formed on the surface of the film to remove the reaction layer,
wherein, in the generating of the plasma, the substrate is set to be 100° C. or lower, and
in the applying energy to the substrate, the substrate is set to be 100° C. or higher,
the method further including changing a size and/or shape of the pattern by removing a portion of the pattern.

US Pat. No. 11,114,303

GATE ALL AROUND DEVICE, METHOD FOR MANUFACTURING FINFET DEVICE, AND METHOD FOR MANUFACTURING GATE ALL AROUND DEVICE

TAIWAN SEMICONDUCTOR MANU...


1. A method, comprising:forming a patterned hard mask and a patterned protective layer over a semiconductor substrate;
etching a semiconductor substrate by using the patterned hard mask and the patterned protective layer as etching masks to form a trench, such that the trench defines a channel portion;
depositing a hard mask layer over sidewalls of the channel portion and covering the patterned hard mask and the patterned protective layer such that a thickness of the hard mask layer is in a range from about 0.1 nm to about 10 nm;
anisotropically etching the semiconductor substrate to deepen the trench, such that the deepened trench further defines a base portion under the channel portion and the hard mask layer, wherein anisotropically etching the semiconductor substrate comprises removing the patterned protective layer to expose the patterned hard mask;
removing the hard mask layer from the sidewalls of the channel portion;
filling the deepened trench with an isolation material; and
recessing the isolation material to form an isolation structure, wherein the channel portion protrudes from the isolation structure.

US Pat. No. 11,114,302

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....


1. A substrate processing apparatus for treating a substrate, the substrate processing apparatus comprising:a substrate holder that holds a substrate in a horizontal posture, and rotates around a rotation axis parallel to a vertical direction;
a rotary drive unit that rotates the substrate holder;
a processing unit that supplies a treatment liquid to the substrate held by the substrate holder to treat the substrate;
a cup part having a first tubular portion and a second tubular portion, being formed each in a tubular shape capable of surrounding the substrate held by the substrate holder, the first tubular portion being connected on one side in the vertical direction to the second tubular portion, the first tubular portion receiving the treatment liquid shaken off from the substrate in a first treatment, the second tubular portion receiving the treatment liquid shaken off from the substrate in a second treatment, the second tubular portion being connected to an upper side of the first tubular portion; and
a relative movement mechanism that moves the cup part and the substrate holder relative to each other in the vertical direction, stops the relative movement at a first relative position where the first tubular portion surrounds the substrate held by the substrate holder in the first treatment, and stops the relative movement at a second relative position where the second tubular portion surrounds the substrate held by the substrate holder in the second treatment, wherein
the cup part has an inner peripheral surface including a first inner peripheral surface of the first tubular portion and a second inner peripheral surface of the second tubular portion, and the inner peripheral surface of the cup part has a shape in which the treatment liquid received by the second inner peripheral surface flows down along the second inner peripheral surface and the first inner peripheral surface in this order in the second treatment, wherein the first tubular portion has a portion with an inner width smaller than that of the second tubular portion,
further comprising:
an annular part that is provided in a vertically intermediate portion of the cup part while projecting inward of the cup part from the first inner peripheral surface of the first tubular portion, and that has an inner edge portion provided with a hole allowing the substrate holder to pass through the hole in the vertical direction; and
a connecting part connecting the first tubular portion and the annular part while forming a gap between the first tubular portion and the annular part.

US Pat. No. 11,114,301

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device, comprising:a semiconductor substrate;
a gate structure comprising:an yttrium oxide layer over the semiconductor substrate;
an aluminum oxide layer over the yttrium oxide layer;
a first high-k dielectric layer over the aluminum oxide layer, wherein the first high-k dielectric layer is made of a material different than the aluminum oxide layer and the yttrium oxide layer; and
a gate electrode on the first high-k dielectric layer; and

source/drain regions on the semiconductor substrate and on opposite sides of the gate structure.

US Pat. No. 11,114,300

LASER ANNEALING APPARATUS, INSPECTION METHOD OF SUBSTRATE WITH CRYSTALLIZED FILM, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

THE JAPAN STEEL WORKS, LT...


1. An inspection method of a substrate with a crystallized film, the method comprising the steps of:(A) irradiating an amorphous film over the substrate with a laser beam to crystallize the amorphous film and to form the crystallized film;
(B) irradiating the crystallized film with a probe beam;
(C) detecting, by a photodetector, the probe beam transmitted through the crystallized film;
(D) changing an irradiation position of the probe beam onto the crystallized film to acquire a plurality of detection values of a detection signal from the photodetector; and
(E) determining, based on a standard deviation of the plurality of detection values, a crystalline state of the crystallized film,
wherein the laser beam passes through a projection lens and forms a linear irradiation region on the amorphous film by the projection lens, and
the photodetector detects the probe beam having passes through the projection lens.

US Pat. No. 11,114,299

TECHNIQUES FOR REDUCING TIP TO TIP SHORTING AND CRITICAL DIMENSION VARIATION DURING NANOSCALE PATTERNING

Applied Materials, Inc., ...


11. A method of forming surface features in a hardmask layer, comprising:etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension and having lateral sidewalls extending in a first direction and longitudinal sidewalls extending in a second direction perpendicular to the first direction;
etching a second surface feature into the hardmask layer, the second surface feature spaced apart from the first surface feature a first distance in the first direction, the second surface feature having a second critical dimension and having lateral sidewalls extending in the first direction and longitudinal sidewalls extending in the second direction;
performing an ion implantation process on the lateral sidewalls of the first and second surface features to make the lateral sidewalls resistant to subsequent etching processes; and
performing an etching process on the first and second surface features, wherein the longitudinal sidewalls of the first and second surface features are etched to shorten a spacing between the first and second surface features from the first distance to a second distance, and wherein the lateral sidewalls are unaffected by the etching process and the first and second critical dimensions are maintained.

US Pat. No. 11,114,297

METHOD FOR FORMING SEMICONDUCTOR FILM AND FILM FORMING DEVICE

TOKYO ELECTRON LIMITED, ...


1. A method for forming a crystallized semiconductor film having a specific grain size on a substrate, comprising:forming a seed layer on the substrate accommodated in a processing container;
vacuuming an interior of the processing container to a medium vacuum or less in a state in which the substrate, on which the seed layer is formed, is accommodated in the processing container;
forming an amorphous semiconductor film on the seed layer after vacuuming the interior of the processing container; and
crystallizing the amorphous semiconductor film by heat processing,
wherein vacuuming the interior of the processing container comprises exhausting a gas from the interior of the processing container, and
wherein vacuuming the interior of the processing container is performed for a time period associated with the specific grain size.

US Pat. No. 11,114,296

SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, METHOD OF PERFORMING INSPECTION ON SEMICONDUCTOR WAFER, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE

SUMITOMO CHEMICAL COMPANY...


1. A semiconductor wafer comprising:a substrate;
a buffer layer;
a first crystalline layer; and
a second layer, wherein
the substrate, the buffer layer, the first crystalline layer, and the second layer are positioned in order of the substrate, the buffer layer, the first crystalline layer and the second layer,
the buffer layer and the first crystalline layer are made of a group III nitride layer,
a bandgap of the first crystalline layer is smaller than a bandgap of the second layer,
when the semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer, and
with a first electrode and a second electrode, electrically connected to the channel, provided closer to a front surface than the channel is, and with a third electrode, at which an electric field is applicable to a spatial region positioned between the channel and the substrate, provided closer to a back surface than the channel is, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

US Pat. No. 11,114,295

EPITAXIAL SILICON CARBIDE SINGLE CRYSTAL WAFER AND PROCESS FOR PRODUCING THE SAME

SHOWA DENKO K.K., Tokyo ...


1. An epitaxial silicon carbide single crystal wafer comprising:a silicon carbide single crystal substrate having an off angle of 4° or less, which is an angle tilted in the <11-20> direction with respect to a (0001) plane;
a buffer layer, formed on the silicon carbide single crystal substrate, having a doping density of 1×1018 atms/cm3 or more and 1×1019 atms/cm3 or less and consisting of a silicon carbide epitaxial film having a thickness of 5 ?m or more and 10 ?m or less; and
a drift layer, formed on the buffer layer, having a doping density of 1×1015 atms/cm3 or more and 1×1017 atms/cm3 or less and consisting of a silicon carbide epitaxial film having a thickness of 10 ?m or more and 30 ?m or less,
wherein a depth of shallow pits on the surface of the drift layer is 19 nm or less, and
wherein the shallow pits are formed by a screw dislocation of the silicon carbide single crystal wafer.

US Pat. No. 11,114,294

STRUCTURE INCLUDING SIOC LAYER AND METHOD OF FORMING SAME

ASM IP Holding B.V., Alm...


1. A method of forming a structure, the method comprising the steps of:providing a substrate within a reaction chamber, the substrate comprising a surface comprising a first material and a second material, the first material comprising a metal and the second material comprising one or more of an oxide, a nitride, and an oxynitride;
selectively depositing a layer comprising silicon nitride on the first material relative to the second material; and
depositing a layer comprising SiOC overlying the layer comprising silicon nitride.

US Pat. No. 11,114,293

SPACE-TIME BUFFER FOR ION PROCESSING PIPELINES

THERMO FINNIGAN LLC, San...


1. A mass spectrometry system comprising:an ion source configured to generate ions from a sample;
an ion separator configured to separate ions based on a property of the ions;
a space-time buffer including a plurality of discrete trapping regions configured to trap ions as individual trapping regions or as combinations of trapping regions;
a mass filter configured to select ions within a mass-to-charge range;
a collision cell configured to fragment ions;
a mass analyzer configured to determine the mass-to-charge ratio of the fragmented ions; and
a controller configured to:generate ions from a sample using the ion source;
separate ions into a plurality of ion groups using the ion separator;
combine at least a portion of the plurality of trapping regions into a larger trap region;
fill the larger trap region with a plurality of ions;
split the larger trap region into individual trapping regions each containing a portion of the plurality of ions;
eject ions from the trapping regions to the mass filter;
select ions within a mass-to-charge range using the mass filter;
fragment ions within a mass-to-charge range using the collision cell; and
analyze the ions using the mass analyzer.


US Pat. No. 11,114,292

SEGMENTED LINEAR ION TRAP FOR ENHANCED ION ACTIVATION AND STORAGE


1. A linear ion trap system comprising:a linear ion trap having at least two discrete trapping regions for processing ions;
an RF electrical potential generator for producing two RF waveforms, each applied to a pair of pole electrodes of the linear ion trap forming a RF trapping field component to trap ions radially;
a multi-output DC electrical potential generator for producing a first set of multiple DC field components superimposed to the RF trapping field component and distributed across the length of the linear ion trap to control ions axially and for producing a second set of multiple DC field components distributed across the length of an ion mobility spectrometer; and
a control unit configured to switch the DC electrical potentials and corresponding DC field components collectively forming a first trapping region of the at least two discrete trapping regions that is populated with ions to alter ion potential energy from a first level to a second level, and to enable at least a first ion processing step in at least one of the first and second levels.

US Pat. No. 11,114,291

METHOD OF SEPARATING DIFFERENT IONS HAVING SIMILAR MASS TO CHARGE RATIOS

MICROMASS UK LIMITED, Wi...


20. A method of filtering ions comprising:providing an ion filter having an ion entrance, an ion exit and a plurality of electrodes, wherein an ion transmission axis through the ion filter joins the ion entrance and the ion exit;
urging a plurality of ions to travel from the ion entrance along the ion transmission axis towards the ion exit, the plurality of ions comprising first ions and second ions, wherein the second ions have substantially the same mass to charge ratio as the first ions but a lower mass than the first ions;
applying an AC and/or RF voltage to at least a first electrode of the plurality of electrodes so as to generate a pseudo-potential barrier around the ion transmission axis for inhibiting the motion of ions radially outwards from within the ion filter; and
urging the plurality of ions radially outwards towards the pseudo-potential barrier as they travel from the ion entrance towards the ion exit whilst maintaining the ion filter at a pressure, wherein the pressure is such that, when the plurality of ions are urged radially outwards towards the pseudo-potential barrier:
the first ions are prevented from passing through the pseudo-potential barrier by being repelled by the pseudo-potential barrier such that the first ions are maintained within the ion filter until the first ions are transmitted along the ion transmission axis through the ion filter to said ion exit, whereas the second ions are not prevented from passing through the pseudo-potential barrier by being repelled by the pseudo-potential barrier such that the second ions are not maintained within the ion filter and do not reach said ion exit.

US Pat. No. 11,114,290

ION FUNNELS AND SYSTEMS INCORPORATING ION FUNNELS

THERMO FINNIGAN LLC, San...


1. An atmosphere-to-vacuum ion transport system comprising:an ion transfer tube extending between an atmospheric-pressure ionization chamber and a partially evacuated chamber;
an ion tunnel within the partially evacuated chamber configured to receive gas and charged particles from the ion transfer tube, comprising:a first plurality of plate electrodes configured as a stack, each electrode of the first plurality of electrodes having an aperture therein, all apertures of the first plurality of electrodes having a same diameter, ?T; and

an ion funnel within the partially evacuated chamber configured to receive the charged particles from the ion tunnel, comprising:a first funnel portion comprising a second plurality of plate electrodes configured as a stack, each electrode of the second plurality of electrodes comprising an aperture therein, each aperture having a respective diameter, ?, where ???T;

wherein the aperture diameter, ?, of each of the second plurality of plate electrodes is greater than or equal to three times an inter-electrode pitch, d, of the second plurality of plate electrodes; and
an exit electrode configured to receive the charged particles from the ion funnel and to deliver the charged particles to a high-vacuum chamber, wherein no DC electrical potential gradient is applied between the exit electrode and an adjacent one of the first plurality of plate electrodes.

US Pat. No. 11,114,289

NON-DISAPPEARING ANODE FOR USE WITH DIELECTRIC DEPOSITION

Applied Materials, Inc., ...


1. A process kit for a plasma processing chamber, comprising:a conductive cylindrical body, wherein the conductive cylindrical body is configured as a cylindrical shield, the conductive cylindrical body having an internal surface and an external surface, the conductive cylindrical body having orientation when the conductive cylindrical body is in use in the plasma processing chamber that defines a top of the conductive cylindrical body and a vertical centerline, the top of the conductive cylindrical body configured to be supported by the plasma processing chamber and extending radially from the vertical centerline, the conductive cylindrical body having an array of features formed within the internal surface of the conductive cylindrical body that is exposed to a plasma when in use in the plasma processing chamber, each feature within the array of features is defined by:
a protrusion extending beyond the internal surface,
an opening formed in the internal surface of the cylindrical body: and
an indentation extending away from the opening into the conductive cylindrical body toward the external surface, the indentation exposing an inner surface of the conductive cylindrical body the indentation having a geometric centerline extending through the opening equidistant from the inner surface, the geometric centerline extending away from the top of the conductive cylindrical body through the opening toward the vertical centerline and the geometric centerline forming an obtuse angle with the vertical centerline of the conductive cylindrical body, wherein each feature has an orientation of the geometric centerline and is oriented toward a bottom of the conductive cylindrical body.

US Pat. No. 11,114,288

PHYSICAL VAPOR DEPOSITION APPARATUS

APPLIED MATERIALS, INC., ...


1. A PVD apparatus, comprising:a chamber including a chamber wall;
a magnetron including a plurality of magnets configured to produce a magnetic field within the chamber;
a pedestal configured to support a substrate;
a shield; and
a target assembly comprising a target made of gold and supported on the chamber wall via a backing plate coupled to a back surface of the target so that a front surface of the target faces the substrate,
wherein a distance from an inside corner of an upper portion of the shield to an upper corner, which meets a front surface of the backing plate, of a peripheral sidewall of the target is about 2.73 mm to about 3.23 mm,
wherein a distance between a back surface of the backing plate and a bottom surface of the plurality of magnets is about 3.95 mm to about 4.45 mm, and
wherein a distance between the front surface of the target and a front surface of the substrate is about 60.25 mm to about 60.75 mm.

US Pat. No. 11,114,287

RADICAL OUTPUT MONITOR FOR A REMOTE PLASMA SOURCE AND METHOD OF USE

MKS INSTRUMENTS, INC., A...


1. A plasma source for a processing system, comprising:at least one gas source configured to provide at least one gas;
a plasma source body defining at least one gas inlet in fluid communication with the at least one gas source and at least one gas outlet, the plasma source having at least one passage having at least one passage surface formed within the plasma source body, the at least one passage in fluid communication with the at least one gas inlet and the at least one gas outlet and configured to have at least one plasma region formed therein;
at least one power source surrounding at least a portion of the plasma source body and configured to generate the at least one plasma region within the plasma source body, the at least one plasma region configured to disassociate the at least one gas flowing within the passage forming at least one disassociated gas;
a first thermal sensor receiver formed within the plasma source body proximate to the at least one passage surface of the at least one passage;
a first thermal sensor positioned within the first thermal sensor receiver, the first thermal sensor configured to measure a first temperature of at least one passage surface of the at least one passage at a first location;
a second thermal sensor receiver formed within the plasma source body proximate to the at least one passage surface of the at least one passage, the second thermal sensor receiver formed within the plasma source body proximate to the at least one gas outlet; and
a second thermal sensor positioned within the second thermal sensor receiver, the second thermal sensor configured to measure a second temperature of the at least one passage surface of the at least one passage at a second location.

US Pat. No. 11,114,286

IN-SITU OPTICAL CHAMBER SURFACE AND PROCESS SENSOR

Applied Materials, Inc., ...


6. The optical sensor system of claim 1, wherein the light source and the sensor are integrated into the housing.

US Pat. No. 11,114,285

APPARATUS FOR EXHAUST COOLING

APPLIED MATERIALS, INC., ...


5. An exhaust cooling apparatus, comprising:a body having a wall, a first end, a second end, an inlet, and an outlet, wherein the first end and the second end are on opposite sides of the body from each other, and wherein the inlet and the outlet are at least partially disposed between the first and second ends;
a cooling plate disposed within the body, wherein the cooling plate is connected to the first end, and wherein a gap separates the cooling plate and the second end; and
a first liner disposed over the cooling plate, wherein the first liner is between the inlet and the cooling plate and comprises:a plate coupled to an end of the wall; and
a plurality of fins extending from the plate and extending away from the cooling plate, wherein the plurality of fins comprises:a center fin forming a first angle with respect to the plate;
a first angled fin forming a second angle with respect to the plate, the second angle is an acute angle facing the center fin; and
a second angled fin forming a third angle with respect to the plate, the third angle is an acute angle facing the center fin, and the second angle is greater than the third angle.



US Pat. No. 11,114,284

PLASMA REACTOR WITH ELECTRODE ARRAY IN CEILING

Applied Materials, Inc., ...


1. A plasma reactor comprising:a chamber body having an interior space that provides a plasma chamber;
a gas distributor to deliver a processing gas to the plasma chamber;
a workpiece support to hold a workpiece;
an electrode assembly comprising a plurality of conductors extending laterally in parallel across at least a region spanning an expected position of the workpiece on the workpiece support in a coplanar array;
a RF power source to supply a first RF power to the electrode assembly;
a dielectric bottom plate between the electrode assembly and the workpiece support, the dielectric bottom plate providing an RF window between the electrode assembly and the plasma chamber;
a dielectric top plate having a lower surface with a plurality of parallel grooves; and
a plurality of filaments in the plurality of grooves between the dielectric top plate and the RF window, each filament comprising a single conductor from the plurality of conductors and a non-metallic shell surrounding the single conductor and positioned between the dielectric top plate and the RF window, wherein the shell forms a conduit and the single conductor extends through the conduit as a solid wire and is suspended in the conduit with a gap surrounding and separating the single conductor from the shell such that the single conductor is spaced apart from an inner floor of the shell.

US Pat. No. 11,114,283

REACTOR, SYSTEM INCLUDING THE REACTOR, AND METHODS OF MANUFACTURING AND USING SAME

ASM IP Holding B.V., Alm...


1. A method of forming a semiconductor etching reactor, the method comprising:providing a reaction chamber, the reaction chamber being made of a first material;
providing a susceptor, the susceptor being made of a second material and being configured to hold a substrate for processing;
providing a showerhead, the showerhead being made of a third material;
based on the first material, the second material, and the third material, selecting and providing a first gas source that is specifically configured for etching the first material, the second material, and the third material, the first gas source configured to provide a first gas precursor to the reaction chamber for a process of etching a film on the substrate;
reacting the first material, the second material, and the third material with the first gas precursor to etch the first material, the second material, and the third material and form a volatile gas compound; and
removing the volatile gas compound from the reaction chamber.

US Pat. No. 11,114,282

PHASED ARRAY MODULAR HIGH-FREQUENCY SOURCE

Applied Materials, Inc., ...


1. A modular high-frequency emission source, comprising:a plurality of high-frequency emission modules, wherein each high-frequency emission module comprises:an oscillator module;
an amplification module; and
an applicator, wherein the applicator comprises a dielectric body with a monopole antenna extending into an axial center of the dielectric body.


US Pat. No. 11,114,281

METHOD AND DEVICE FOR RADIO FREQUENCY IMPEDANCE MATCHING, AND SEMICONDUCTOR PROCESSING APPARATUS

BEIJING NAURA MICROELECTR...


1. A method for radio frequency (RF) impedance matching for a radio frequency including M pulse periods, each of the M pulse periods including N pulse phases, M and N being integers greater than 1, wherein the method comprises:performing frequency scanning matching by using first n pulse phases of each of first m pulse periods as frequency scanning stages each corresponding to one of the first m pulse periods, a start value of a frequency scanning parameter of the frequency scanning stage of an (i+1)-th pulse period being consistent with an end value of the frequency scanning parameter of the frequency scanning stage of an i-th pulse period to make an end value of the frequency scanning parameter of the frequency scanning stage of an m-th pulse period to match a target value of the frequency scanning parameter, m and n being integers greater than 0, m maintaining the frequency scanning parameter of pulse phases, corresponding to the first n pulse phases, of each pulse period from an (m+1)-th pulse period to an M-th pulse period to be unchanged, the frequency scanning parameter of the pulse phases of each pulse period from the (m+1)-th pulse period to the M-th pulse period being consistent with the end value of the frequency scanning parameter of the frequency scanning stage of the m-th pulse period.

US Pat. No. 11,114,280

IMPEDANCE MATCHING WITH MULTI-LEVEL POWER SETPOINT

RENO TECHNOLOGIES, INC.


1. A method for impedance matching comprising:positioning a matching network between a radio frequency (RF) source and a load, wherein:the RF source is configured to provide at least two non-zero pulse levels; and
the matching network comprises at least one electronically variable capacitor (EVC) configured to alter its capacitance to provide a match configuration;

for each of the at least two pulse levels, at a regular time interval, regardless of whether the pulse level is detected, determining a parameter-related value that is based on a parameter related to the load;
repeatedly detecting which of the at least two non-zero pulse levels is being provided by the RF source; and
upon detecting one of the at least two non-zero pulse levels, for the detected pulse level:measuring the parameter related to the load to determine a measured parameter value;
determining the parameter-related value based on the measured parameter value; and
altering the at least one EVC to provide the match configuration, the match configuration based on the parameter-related value.


US Pat. No. 11,114,279

ARC SUPPRESSION DEVICE FOR PLASMA PROCESSING EQUIPMENT

COMET TECHNOLOGIES USA, I...


1. A device, comprising:a first network;
a second network;
each of the first network and the second network comprising:a switching element to engage upon receiving a triggering signal; and
a power dissipater to be engaged by the switching element to dissipate both stored and delivered energy when the switching element engages; and

an impedance transformer coupled to the power dissipater to perform an impedance transformation that, when the switching element of the first network and the switching element of the second network are engaged in conjunction with the power dissipater, reduces a reflection coefficient at an input of the device, the first network and the second network being disposed symmetrically with respect to the impedance transformer.

US Pat. No. 11,114,278

POWER SUPPLY DEVICE FOR PLASMA, PLASMA DEVICE, AND METHOD FOR CONTROLLING POWER SUPPLY DEVICE FOR PLASMA

FUJI CORPORATION, Chiryu...


1. A plasma power supply device comprising:an AC power supply configured to generate an AC voltage of a predetermined frequency to be applied to a pair of electrodes configured to generate a plasma by way of an unshielded power supply harness that includes a pair of conductors constituting a core, each conductor being detachably coupled to a respective electrode from the pair of electrodes; and
a control section configured to set the predetermined frequency of the AC power supply so that the frequency becomes lower as the power supply harness becomes longer,
wherein the control section is further configured to (i) receive information indicating a wiring length of the power supply harness, and (ii) set the predetermined frequency of the AC power supply based on the wiring length of the power supply harness.

US Pat. No. 11,114,277

DUAL CATHODE ION SOURCE

Varian Semiconductor Equi...


1. An ion implanter, comprising:an ion source, comprising:a first end wall and a second end wall;
chamber walls connected to the first end wall and the second end wall to define an ion source chamber, wherein one of the chamber walls comprises an extraction aperture, wherein a ribbon ion beam is extracted through the extraction aperture;
a first cathode disposed proximate the first end wall;
a first filament disposed between the first end wall and the first cathode;
a first bias power supply to bias the first cathode relative to the first filament;
a second cathode disposed proximate the second end wall;
a second filament disposed between the second end wall and the second cathode; and
a second bias power supply, different from the first bias power supply, to bias the second cathode relative to the second filament;

a beam profiler for measuring a beam current of the ribbon ion beam as a function of beam position; and
a controller in communication with the ion source and the beam profiler, wherein the controller determines a profile of beam current of the ribbon ion beam based on input from the beam profiler and, based on the profile, independently controls an output of the first bias power supply and the second bias power supply so as to adjust the profile of beam current of the ribbon ion beam.

US Pat. No. 11,114,276

APPARATUS, METHOD, AND PROGRAM FOR PROCESSING AND OBSERVING CROSS SECTION, AND METHOD OF MEASURING SHAPE

HITACHI HIGH-TECH SCIENCE...


1. An apparatus for processing and observing a cross section, the apparatus comprising:a sample bed holding a sample;
a focused ion beam column irradiating the sample with a focused ion beam;
an electron beam column irradiating the sample with an electron beam in a direction perpendicular to a direction of irradiation of the focused ion beam;
an electron detector detecting secondary electrons or reflection electrons generated from the sample;
an irradiation position controller controlling irradiation positions of the focused ion beam and the electron beam based on target irradiation position information which is information showing target irradiation positions of beams on the sample, stored in a memory unit;
a process controller controlling, for each irradiation position that is controlled by the irradiation position controller, a cross section-exposing process that exposes a cross section of the sample by irradiating the sample with the focused ion beam and a cross section image-obtaining process that obtains a cross section image of the cross section by irradiating the cross section with the electron beam, for the irradiation positions that are controlled by the irradiation position controller and storing the cross section image obtained in relation to a first target irradiation position in the memory unit as a reference image quality information which is information showing reference image quality of the cross-section image; and
an image quality corrector correcting image quality of the cross section image obtained for the irradiation positions,
wherein the image quality corrector corrects the image quality of the cross section image for a second target irradiation position which is an irradiation position next to the first target irradiation position, based on the reference image quality information and
wherein the image quality of the cross section is at least one of brightness, contrast, or luminance of the cross section.

US Pat. No. 11,114,275

METHODS AND SYSTEMS FOR ACQUIRING ELECTRON BACKSCATTER DIFFRACTION PATTERNS

FEI Company, Hillsboro, ...


1. A method for imaging a sample, comprising:performing a first scan by directing a charged particle beam towards multiple impact points within a ROI of the sample, and detecting particles scattered from each impact point of the multiple impact points;
calculating a signal quality of each impact point of the multiple impact points based on the detected particles scattered from the impact point, wherein the signal quality of the impact point indicates an accuracy for extracting structural information;
calculating a signal quality of the ROI based on the signal quality of each impact point;
responsive to the signal quality of the ROI lower than a threshold signal quality, performing a second scan by directing the charged particle beam towards one or more of the multiple impact points within the ROI, and detecting particles scattered from the one or more of the multiple impact points within the ROI;
forming an electron backscattered diffraction (EBSD) pattern for each impact point of the multiple impact points based on the detected particles scattered from the impact point during the first scan and the second scan; and
forming a structural image of the ROI based on the EBSD pattern.

US Pat. No. 11,114,274

METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT

Carl Zeiss SMT GmbH, Obe...


1. A method, comprising:a) applying an electric test pattern to an integrated circuit (IC);
b) delivering a beam primary electrons to a side of the IC on an active region comprising active structures of the IC;
c) detecting light resulting from cathodoluminescence initiated by secondary electrons in the IC; and
d) analyzing the detected light to correlate the detected light with the electric test pattern applied to the IC,
wherein the electron beam has a resolution, the resolution is about a size of the active structure, and the resolution is less than a spacing between active structures of the IC.

US Pat. No. 11,114,273

SCREENING METHOD AND APPARATUS FOR DETECTING AN OBJECT OF INTEREST


1. Screening method, comprising the steps of:providing a sample, wherein the sample comprises a sample carrier with a surface structure, as well as an object of interest;
acquiring an image of the sample;
providing information on a surface structure of the sample carrier, and manipulating the acquired image using the information; and
screening the manipulated image for the object of interest.

US Pat. No. 11,114,272

PULSED CFE ELECTRON SOURCE WITH FAST BLANKER FOR ULTRAFAST TEM APPLICATIONS

FEI Company, Hillsboro, ...


1. A charged-particle-beam (CPB) system, comprising:a CPB source adapted to produce a CPB having a pulsed CPB component or a continuous CPB component, or both a pulsed CPB component and a continuous CPB component;
a CPB lens situated to receive the CPB from the CPB source; and
a controller coupled to the CPB lens and configured to:select either a first CPB beam focus or a second CPB focus, wherein the first CPB focus is situated to substantially attenuate a CPB at a beam limiting aperture, and the second CPB focus is situated so that the CPB is substantially transmitted by the beam limiting aperture;
with the first CPB focus selected, activate the CPB source to produce at least a continuous component of the CPB and direct the continuous component to a target; and
with the second CPB focus selected, produce at least a pulsed component of the CPB and direct the pulsed component to the target.


US Pat. No. 11,114,271

SIXTH-ORDER AND ABOVE CORRECTED STEM MULTIPOLE CORRECTORS

FEI Company, Hillsboro, ...


1. A corrector for correcting axial aberrations in a charged particle microscope system, the corrector comprising:a first primary hexapole that generates a first primary hexapole field when a first excitation is applied to the first primary hexapole;
a second primary hexapole that generates a second primary hexapole field when a second excitation is applied to the second primary hexapole, wherein the second primary hexapole is positioned between the first primary hexapole and a lens which is the main source of spherical aberration when used in the charged particle microscope system, and wherein the first primary hexapole is not imaged onto the second primary hexapole such that a combination fourth-order aberration is created; and
a secondary hexapole for correcting the fourth-order aberration and a sixth-order aberration, wherein the secondary hexapole is positioned between the second primary hexapole and the lens when used in the charged particle microscope system.

US Pat. No. 11,114,270

SCANNING MAGNET DESIGN WITH ENHANCED EFFICIENCY

Axcelis Technologies, Inc...


1. A scanning magnet for magnetically scanning an ion beam, the scanning magnet comprising:a yoke having a channel defined therein, the yoke having a first side and a second side defining a respective entrance and exit of the ion beam passing along a beam path through the channel, the yoke comprising a plurality of laminations stacked from the first side to the second side, and wherein at least a portion of the plurality of laminations associated with the first side and second side comprise one or more slotted laminations, wherein the one or more slotted laminations have a plurality of tines extending toward the channel, wherein a plurality of slots are defined between the plurality of tines;
one or more liners positioned within the channel, wherein the one or more liners are comprised of graphite and generally isolate the yoke and scanner coil from the ion beam, wherein the one or more liners further comprise one or more liner slots defined therein, wherein the one or more liner slots extend generally perpendicular to the beam path and are configured to generally reduce eddy currents within the one or more liners; and
a scanner coil comprising a first wire wrapped around the yoke.

US Pat. No. 11,114,269

BREMSSTRAHLUNG TARGET FOR RADIATION THERAPY SYSTEM

Accuray Incorporated, Sa...


1. A medical linear accelerator comprising:an electromagnetic wave source to receive a beam current of electrons and to generate an electromagnetic wave;
an accelerator structure to receive the electromagnetic wave and to generate an output therapy dose rate of electrons having a beam energy between 4-25 mega-electronvolts (MeV), wherein the accelerator is a standing wave accelerator; and
an accelerator target structure to receive the output dose of electrons comprised of:an x-ray emitting target to emit x-rays in response to receiving the output dose rate of electrons, wherein the x-ray emitting target is less than 0.2 radiation lengths.


US Pat. No. 11,114,268

X-RAY GENERATING TUBE, X-RAY GENERATING APPARATUS, AND RADIOGRAPHY SYSTEM

Canon Kabushiki Kaisha, ...


1. An X-ray generating tube comprising:an anode including an anode member and a target secured to the anode member configured to generate X rays in response to electronic irradiation;
a cathode including a cathode member;
an electron gun secured to the cathode member configured to generate electron beams toward the target; and
an insulating tube secured to each one of the anode member and the cathode member and configured to electrically insulate between the anode and the cathode,
wherein the electron gun includes an electron emitting portion configured to emit electrons, a plurality of grid electrodes with openings configured to define static potentials in the openings and form an electron beam passing path, and an insulating support member located outside with respect to the openings in a radius direction and configured to electrically insulate and support at least two out of the plurality of grid electrodes,
wherein the insulating support member is concealed from the electron beam passing path by the plurality of grid electrodes configured not to be directly viewed from the electron beam passing through the openings.

US Pat. No. 11,114,267

SINGLE HAND CONTROLLER

Measurement Systems, Inc....


1. A single hand controller, comprising:a front surface and a back surface, having disposed between a first and second side surface;
a lower surface interconnected with the front surface, back surface and first and second side surfaces;
an upper surface interconnected with the front surface, back surface and first and second side surfaces;
the upper surface has disposed thereon a joystick;
the front surface has disposed therein a push button and at least one switch; and
a palm safety actuator disposed on the back surface enabling at least one functionality when depressed;
wherein the front surface, back surface, first side surface and second side surface are shaped such that when a user places a first through fourth digits of a hand against the front surface and a thenar eminence of the hand against the back surface, the user's thumb is disposed against the joystick and the user's second digit is disposed against the push button.

US Pat. No. 11,114,266

ELEMENT SUB-STRUCTURE

Littelfuse, Inc., Chicag...


1. A molded structure to support an electrical element, the molded structure comprising:a first end bell coupled to a first copper terminal;
a second end bell coupled to a second copper terminal;
a plurality of ribs disposed alongside the electrical element to protect the electrical element;
a substantially cylindrical shape, wherein the molded structure fits into an enclosure body such that the end bells and the plurality of ribs rest against an inner surface of the enclosure body;

andan aperture for receiving the electrical element such that one end of the electrical element is coupled to the first copper terminal and a second end of the electrical element is coupled to the second copper terminal.

US Pat. No. 11,114,265

THERMAL MANAGEMENT IN HIGH POWER RF MEMS SWITCHES

Cavendish Kinetics, Inc.,...


1. A MEMS device, comprising:a substrate having a plurality of electrodes formed therein, wherein the plurality of electrodes comprises at least an anchor electrode, a pull-in electrode and an RF electrode;
a first insulating layer disposed over the plurality of electrodes and the substrate;
a switching element disposed over the first insulating layer, wherein the switching element includes an anchor portion, a leg portion and a bridge portion and wherein the anchor portion is electrically coupled to the anchor electrode;
a first post coupled to the RF electrode, wherein the first post comprises an electrically conductive material and the first post is disposed directly on both the RF electrode and the first insulating layer; and
a second post electrically coupled to the anchor electrode through a first opening formed in the first insulating layer, wherein the switching element is movable between a first position spaced from the first post and the second post, and a second position in contact with the first post and the second post.

US Pat. No. 11,114,264

INSERTION STRUCTURE BETWEEN STATIC SPRING AND BOBBIN

Xiamen Hongfa Automotive ...


1. An insertion structure between a stationary spring and a bobbin, comprising:A stationary spring and a bobbin; wherein the stationary spring is inserted into the bobbin by a flip-chip method, and the bobbin is provided with slots, each of the slots having a groove shape with a laterally open is formed by an L-shaped side wall connecting with a convex wall, and each of two sides of the stationary spring is provided with a convex part respectively, and two convex parts of the stationary spring are respectively fitted in two opposite slots; wherein a first blocking wall is further provided along a horizontally extending direction of protruding of the convex wall of the bobbin, and a second blocking wall is further provided between the first blocking wall and the L-shaped side wall to connect the first blocking wall and the L-shaped side wall, and the convex parts of the stationary spring are mounted at the second blocking wall, so that shaving debris generated when the convex parts of the stationary spring are inserted into the slots of the bobbin falls into a cavity enclosed by the first blocking wall, the second blocking wall, the L-shaped side wall and the convex wall.

US Pat. No. 11,114,263

MAGNETIC ELECTRICAL SWITCH

Eaton Intelligent Power L...


14. A magnetic electrical switch apparatus comprising:a switch assembly comprising:a switch body housing comprising a stationary contact;
a shaft configured to move relative to the switch body housing, the shaft comprising:a moveable contact; and
a first magnet, wherein the moveable contact and the first magnet are configured to move with the shaft; and


a moveable support member comprising a second magnet, whereinmoving the moveable support member moves the second magnet relative to the first magnet, and a magnetic interaction between the second magnet and the first magnet moves the moveable contact relative to the stationary contact to thereby change a state of the switch assembly, and
the moveable support member and switch assembly are physically separated and do not make direct physical contact with each other.


US Pat. No. 11,114,262

CONTACT SYSTEM FOR ELECTRICAL CURRENT CONDUCTION AND BUS TRANSFER SWITCHING IN A SWITCHGEAR

ABB Power Grids Switzerla...


1. A switchgear having a turn and twist mechanism for electrical connection and disconnection, the switchgear comprising a contact system for electrical current conduction and bus transfer switching, the contact system comprising:at least one fixed contact assembly, comprising a fixed main contact and a fixed arcing contact, wherein the fixed arcing contact is provided for bus transfer switching, and wherein the fixed arcing contact is a finger comprising a contacting element for engaging with a corresponding contacting element of a movable arcing contact of the contact system during the bus transfer switching; and
at least one movable contact assembly comprising a current path pipe and an end piece, wherein the current path pipe is a cylindrical pipe and the end piece is a rectangular block attached at an end of the cylindrical pipe, wherein the at least one movable contact assembly comprises a movable main contact and the movable arcing contact, wherein the movable main contact is for engaging with the fixed main contact for current conduction, and the movable arcing contact is for the bus transfer switching, wherein the movable main contact is provided on the rectangular block, and the movable arcing contact is provided at the end of the cylindrical pipe on a portion about a periphery of the cylindrical pipe,
wherein during engagement of the at least one movable contact assembly with the at least one fixed contact assembly, the cylindrical pipe turns about a first axis to bring the at least one movable contact assembly proximal to the fixed contact assembly, and then twists about a second axis for engagement of the movable main contact with the fixed main contact, wherein during the engagement of the at least one movable contact assembly and the fixed contact assembly, the fixed arcing contact and the movable arcing contact for the bus transfer switching are contacts that are first to engage and are disengaged when the movable main contact and the fixed main contact are engaged.

US Pat. No. 11,114,261

ELECTRICAL CONNECTOR FOR IGNITER FOR EXOTHERMIC WELDING

ERICO International Corpo...


1. An electrical connector for an igniter for exothermic welding, the electrical connector comprising:a housing;
a first conductor enclosed by the housing; and
a second conductor enclosed by and movable within the housing;
the housing providing:a first opening to receive the igniter for engagement with the first and second conductor;
a housing wall that is movable, via manual contact from outside of the housing, to move the second conductor within the housing between a resting orientation and an actuated orientation; and
a first window that provides visual access to an interior area of the housing to verify engagement of the igniter with the first and second conductors;

a contact area of the second conductor being spaced farther from the first conductor when the second conductor is in the actuated orientation than when the second conductor is in the resting orientation; and
the contact area being disposed, when the second conductor is in the resting orientation, to contact a first side of the igniter, with a second side of the igniter in contact with the first conductor.

US Pat. No. 11,114,260

SCISSOR-LEG STRUCTURAL KEY AND ITS SWITCH DEVICE, AND A KEYBOARD APPLYING THE KEY


1. A switch device comprising resettable scissor-legs which include a male leg and a female leg, forming a scissor structure, and a mounting receptacle, a first end of the male leg hinged to the mounting receptacle, and a first end of the female leg slidably arranged in the mounting receptacle a reset assistant part arranged a second end of the male leg, the reset assistant part provided with a holding station, both sidewalls of which are each provided with a saddle: a ram, both sides of which are provided with a cam matching with the saddle, the ram hanged from the saddles through the two cams; the mounting receptacle provided with a recess portion for receiving the ram; the ram arranged on the sidewalls of the recess portion when the scissor-leg structure is in an original position, and moved in a direction capable of dropping into the recess portion when the scissor-leg structure is depressed, and dropped in the recess portion after the scissor-legs are depressed into a stagnation point, and the saddle resetting the ram during the scissor-leg structure reset.

US Pat. No. 11,114,259

SWITCH BODY

PANASONIC INTELLECTUAL PR...


1. A switch body comprising:a base including a first fixed electrode, a second fixed electrode placed next to the first fixed electrode to be electrically independent from the first fixed electrode, a third fixed electrode placed next to the second fixed electrode and on an opposite side of the second fixed electrode from the first fixed electrode, and a fourth fixed electrode placed next to the first fixed electrode and on an opposite side of the first fixed electrode from the second fixed electrode; and
a movable electrode including a pressure receiving part opposite from the second fixed electrode of the base, a first outer edge facing the first fixed electrode, and a second outer edge facing the third fixed electrode, and the movable electrode being designed to allow movement of an opposite surface from the pressure receiving part toward the second fixed electrode when the pressure receiving part is pressed toward the base and then deformed
a spacer holding the movable electrode with position thereof limited on the base,
the fourth fixed electrode being formed in a region outside a projection region, wherein the projection region being a projection of the movable electrode on the base and the fourth fixed electrode is placed so that a distance between inner edges of the second fixed electrode and the fourth fixed electrode is shorter than a distance between the first outer edge and the second outer edge and a distance between outer edges of the second fixed electrode and the fourth fixed electrode is longer than the distance between the first outer edge and the second outer edge,
the spacer including a flat region, the spacer being placed over the base to cover all of the fourth fixed electrode with the flat region.

US Pat. No. 11,114,258

SWITCHING APPARATUS FOR CARRYING AND DISCONNECTING ELECTRIC CURRENTS, AND SWITCHGEAR HAVING A SWITCHING APPARATUS OF THIS KIND

EATON INTELLIGENT POWER L...


1. A switching apparatus for carrying and disconnecting electric currents, comprising:a first mechanical contact arrangement;
a second mechanical contact arrangement which is connected in series with the first mechanical contact arrangement;
a semiconductor switch which is connected in parallel to the first mechanical contact arrangement;
a switching electronics system configured to switch on and switch off the semiconductor switch; and
a control circuit configured to ascertain a voltage across the first mechanical contact arrangement as an ascertained voltage and to generate an actuation signal for the switching electronics system, which actuation signal switches on the semiconductor switch, depending on the ascertained voltage,
wherein the switching apparatus is configured such that during a switching process the two mechanical contact arrangements are closed with a time delay in relation to one another,
wherein the control circuit comprises a switch and a low-pass filter connected upstream of the switch, and
wherein the switch is configured to generate the actuation signal for the switching electronics system.

US Pat. No. 11,114,256

SWITCHING APPARATUS AND ASSOCIATED SWITCH

ABB Schweiz AG, Baden (C...


1. A switching apparatus, comprising:a handle shaft coupled to a handle and arranged rotatable in a circumferential direction in response to an operation to the handle;
a locking plate arranged movable in a first direction in association with a rotation of the handle shaft, and
a hook coupled to the locking plate, wherein the hook includes an end oriented in a longitudinal direction, the end passing through a hole on the locking plate,
wherein the handle shaft and the locking plate are operable to limit the rotation of the handle shaft, when the handle shaft arrives at an off position of the switching apparatus,
wherein the handle shaft includes a first pin, and the locking plate includes a first slot,
wherein the first pin is received by the first slot when the handle shaft arrives at the off position to prevent a further rotation of the first pin in a positive circumferential direction,
wherein the handle shaft includes a cam that is separated from the first pin by a first distance in the circumferential direction and by a second distance in the longitudinal direction, and
wherein the cam is in non-contact with the end of the hook when the first pin is received by the first slot.

US Pat. No. 11,114,255

ANTI-REBOUNDING LEVER WITHIN A SWITCHING DEVICE

Schneider Electric Indust...


1. An electrical switching device with separable contacts, comprising a switching apparatus including:a fixed electrical contact and a mobile electrical contact that can be moved between a closing position and an opening position;
a control lever mechanically coupled to the mobile electrical contact, the control lever being rotatable, about a first axis of rotation, between a first position and a second position, the movement of the control lever from the first position to the second position causing a movement of the mobile contact from the closing position to the opening position; and
an anti-rebound lever, that is mounted on the control lever by a pivoting link and can be rotated about a second axis that is an axis of the pivoting link and that is parallel to the first axis of rotation, between a rest position and an opened-out position,
wherein the anti-rebound lever is configured to move from the rest position to the opened-out position when the control lever reaches the second position,
the anti-rebound lever is configured to engage a stop of the switching apparatus with a convex edge thereof when the anti-rebound lever is in the opened-out position thereof and when the control lever is in the second position to prevent the control lever from leaving the second position, and
the anti-rebound lever includes a first lobe and a second lobe, and the anti-rebound lever is formed to have a center of gravity located in a smaller of the first lobe and the second lobe.