US Pat. No. 10,971,407

METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE HAVING FIN FIELD EFFECT TRANSISTORS WITH A COMMON METAL GATE

INTERNATIONAL BUSINESS MA...

1. A method of forming a complementary metal oxide semiconductor (CMOS) device, comprising:forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer;
forming a protective liner layer on the gate structures;
heat treating the pair of gate structures;
replacing the protective liner layer with an encapsulation layer;
exposing a portion of the gate dielectric layer by recessing the encapsulation layer;
forming a top source/drain on the top surface of one of the pair of vertical fins; and
subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

US Pat. No. 10,971,406

METHOD OF FORMING SOURCE/DRAIN REGIONS OF TRANSISTORS

Taiwan Semiconductor Manu...

1. A method for fabricating a semiconductor device, the method comprising:providing a first structure and a second structure on a substrate, each of the first structure and the second structure having a first semiconductor material layer and a second semiconductor material layer, the second semiconductor material layer being different composition than the first semiconductor material layer;
removing the second semiconductor material layer from the first structure;
forming a first type of transistor having a gate structure disposed on the first semiconductor material layer of the first structure wherein the forming the first type of transistor in the first semiconductor material layer includes:
removing a portion of the first semiconductor material layer,
forming a source/drain material in a first region defined by the removed portion, wherein the first region has a shape with a tip extending toward a channel region under the gate structure of the first type of transistor; and
forming a higher concentration of a dopant of boron in the tip of the first region than a remaining portion of the first region; and
forming a second type of transistor in the second semiconductor material layer of the second structure.

US Pat. No. 10,971,405

SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:providing a base substrate, including a first region, a second region, and a third region, wherein the first region is adjacent to the second region and located on each side of the second region, the third region located between the first region and the second region, a plurality of discrete fin structures is formed on the base substrate, and the plurality of discrete fin structures includes a first plurality of fins structures in the first region, and a second plurality of fin structures in the second region, and a third plurality of fin structures in the third region;
forming a first doped region in the first plurality of fin structures in the first region;
forming a second doped region in the second plurality of fin structures in the second region, wherein a concentration of doping ions in the first doped region is lower than a concentration of doping ions in the second doped region, and the doping ions in the first doped region have a same doping type as the doping ions in the second doped region;
forming a third doped region in the third plurality of fin structures in the third region; and
after forming the first doped region and the second doped region, forming a plurality of gate structures on the first doped region and the second doped region across the plurality of discrete fin structures.

US Pat. No. 10,971,404

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate; and
a first transistor having a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate;
wherein a dopant is used to form the first lightly doped source/drain region and the first channel region, a concentration of the first channel region ranges from 4×1014 particles/cm3 to 2×1015 particles/cm3, the concentration of the first channel region is less than a concentration of the first lightly doped source/drain region, and a doping ratio determined as the concentration of the first lightly doped source/drain region divided by the concentration of the first channel region ranges from 1.0×1013 to 1.0×1017.

US Pat. No. 10,971,403

STRUCTURE AND METHOD OF FORMING FIN DEVICE HAVING IMPROVED FIN LINER

Varian Semiconductor Equi...

1. A semiconductor device, comprising:a semiconductor fin, disposed on a substrate,
wherein the semiconductor fin comprises a lower portion, the lower portion having a first width, and an upper portion, the upper portion having a second width, wherein the semiconductor fin defines a fin recess, comprising an abrupt change in width of the semiconductor fin between the lower portion and the upper portion;
a liner, disposed on the lower portion of the semiconductor fin, the liner comprising an insulator, wherein the liner is not disposed above the fin recess on the upper portion; and
an isolation layer disposed on the substrate adjacent the semiconductor fin, up to a level of the fin recess.

US Pat. No. 10,971,402

SEMICONDUCTOR DEVICE INCLUDING INTERFACE LAYER AND METHOD OF FABRICATING THEREOF

Taiwan Semiconductor Manu...

1. A method comprising:providing a substrate having a channel region;
growing an oxide layer on the channel region, wherein the growing the oxide layer includes:
introducing a first source gas providing oxygen;
introducing a second source gas providing hydrogen, the second source gas being different than the first source gas;
bonding the oxygen to a semiconductor element of the channel region to form the oxide layer; and
bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct;
forming a gate dielectric layer over the oxide layer; and
forming a gate electrode over the gate dielectric layer.

US Pat. No. 10,971,401

SYSTEMS AND METHODS FOR PRECISION FABRICATION OF AN ORIFICE WITHIN AN INTEGRATED CIRCUIT

Cerebras Systems Inc., L...

1. A method comprising:adding a sacrificial layer to a first surface of a semiconductor substrate; and
along an orifice axis normal to the first surface, subsequently:
fabricating a cavity in the semiconductor substrate using a first material removal technique, the cavity comprising a first radius about the orifice axis and a first depth along the orifice axis; and
subsequently fabricating an orifice in the semiconductor substrate using a second material removal technique, the orifice comprising a second radius about the orifice axis, the orifice extending from the first depth, along the orifice axis, wherein the second radial distance defines a diameter of about 2 millimeters, wherein the second radius has a second radial distance that is smaller than a first radial distance of first radius,
wherein the first and second material removal techniques remove material in the same direction along the orifice axis.

US Pat. No. 10,971,400

SEMICONDUCTOR DEVICE, SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a device layer including a semiconductor element and a wiring layer;
a first structure comprising a first substrate having the device layer formed on a first surface thereof, and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer;
a second structure at an outer periphery of the first structure, having a thickness smaller than that of the first structure and having two surfaces on opposite sides thereof, the two surfaces including a substantially flat surface and another surface that is farther from the device layer than the substantially flat surface;
a conductive layer that physically contacts the first structure and the flat surface of the second structure; and
an insulating film pattern formed on the conductive layer covering the first structure and on the conductive layer covering the second structure.

US Pat. No. 10,971,399

OXYGEN-FREE REPLACEMENT LINER FOR IMPROVED TRANSISTOR PERFORMANCE

INTERNATIONAL BUSINESS MA...

1. A method of forming an interconnect structure, the method comprising:forming a transistor over a substrate;
forming a dielectric region over the transistor and the substrate;
forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench comprises a gate spacer of the transistor;
increasing a volume of the trench by removing the gate spacer from the sidewall of the trench; and
depositing a first liner and a conductive plug within the trench such that the first liner and the conductive trench are only present within a bottom portion of the trench.

US Pat. No. 10,971,398

COBALT INTERCONNECT STRUCTURE INCLUDING NOBLE METAL LAYER

INTERNATIONAL BUSINESS MA...

1. A process for forming a metal interconnect layer, the process comprising:lithographically patterning and etching a dielectric layer to form one or more openings, wherein the one or more openings exposes a conductive region of an underlying interconnect structure or substrate;
conformally depositing a liner layer;
conformally depositing a noble metal layer onto the liner layer, wherein the noble metal layer comprises iridium or rhodium;
conformally depositing one or more layers of cobalt onto the noble metal layer; and
thermally annealing at a temperature and time effective to reflow the cobalt to at least partially fill the one or more openings to form one or more partially cobalt filled openings;
wherein the conformally deposited noble metal layer partially fills the one or more openings and exposing side surfaces.

US Pat. No. 10,971,397

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A method of fabricating a semiconductor device, comprising:providing a substrate, the substrate comprising:
a pixel region having a first conductive region; and
a logic region having a second conductive region;
forming a dielectric layer on the substrate to cover the first conductive region;
forming a first contact opening in the dielectric layer to expose the first conductive region;
forming a doped polysilicon layer in the first contact opening;
forming a first metal silicide layer on the doped polysilicon layer;
forming a second contact opening in the dielectric layer to expose the second conductive region; and
forming a barrier layer and a metal layer respectively in the first contact opening and the second contact opening.

US Pat. No. 10,971,396

CONDUCTIVE FEATURE FORMATION AND STRUCTURE

Taiwan Semiconductor Manu...

1. A structure comprising:a dielectric layer over an underlying layer, the dielectric layer having a sidewall;
a barrier layer along the sidewall, an upper surface of the barrier layer being below a top surface of the dielectric layer, a thickness of an upper portion of the barrier layer being less than a thickness of a lower portion of the barrier layer; and
a conductive material on the barrier layer and over the upper surface of the barrier layer, the barrier layer extending along a sidewall and an entirety of a bottom surface of the conductive material, the barrier layer completely separating the conductive material from the underlying layer, the conductive material having a top surface that is coplanar with the top surface of the dielectric layer.

US Pat. No. 10,971,395

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method for fabricating a semiconductor device, the method comprising:forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate;
forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer; and
forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein:
the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas and a second gas that contains hydrogen,
the first gas includes one or more of SiD4, D2O, ND3, Si2D6, or (C2H5)3SiD, and
forming the second wiring layer includes:
forming the second metal wiring on the first via layer, forming the second metal wiring including forming a second metal wiring material on the second interlayer insulating film and then patterning the second metal wiring material; and
after patterning the second metal wiring material, forming the third interlayer insulating film so as to wrap the second metal wiring.

US Pat. No. 10,971,394

MASKLESS AIR GAP TO PREVENT VIA PUNCH THROUGH

Intel Corporation, Santa...

1. An electronic device comprising:a first etch stop layer on a top surface of a plurality of conductive features, the plurality of conductive features on an insulating layer on a substrate;
a second etch stop layer over an air gap between the conductive features, the second etch stop layer laterally adjacent to the first etch stop layer; and
a via adjacent to the second etch stop layer to contact at least one of the conductive features.

US Pat. No. 10,971,393

METAL-INSULATOR-METAL (MIM) STRUCTURE SUPPORTING HIGH VOLTAGE APPLICATIONS AND LOW VOLTAGE APPLICATIONS

Intel Corporation, Santa...

1. An integrated circuit (IC) structure, comprising:a first stack comprising a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, wherein a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers;
a second stack comprising at least the middle and upper layers of conductive material with one of the insulator layers therebetween;
a first via comprising conductive material and over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween; and
a second via comprising conductive material and over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer, the second via isolated from a sidewall of the upper layer by a spacer comprising a dielectric material.

US Pat. No. 10,971,392

AMORPHOUS METAL THIN FILM NONLINEAR RESISTOR

Amorphyx, Inc., Corvalli...

1. A device, comprising:a substrate;
a first, second, and third amorphous metal thin film interconnect on the substrate;
a first conductive interconnect overlapping the first and second amorphous metal thin film interconnects;
a second conductive interconnect overlapping the second and third amorphous metal thin film interconnects;
a first terminal overlapping the first amorphous metal thin film interconnect; and
a second terminal overlapping the third amorphous metal thin film interconnect.

US Pat. No. 10,971,391

DIELECTRIC GAP FILL

Taiwan Semiconductor Manu...

1. A method of semiconductor processing, the method comprising:conformally depositing a first dielectric material in a first trench and a second trench using an atomic layer deposition (ALD) process;
after conformally depositing the first dielectric material, converting the first dielectric material to a second dielectric material, wherein after converting the first dielectric material to the second dielectric material, the first trench is completely filled; and
after converting the first dielectric material to the second dielectric material, depositing a third dielectric material over the second dielectric material in the second trench.

US Pat. No. 10,971,390

METHODS OF MINIMIZING WAFER BACKSIDE DAMAGE IN SEMICONDUCTOR WAFER PROCESSING

Applied Materials, Inc., ...

1. A substrate support, comprising:a ceramic body comprising a substrate chucking surface;
an RF electrode disposed within the ceramic body;
a heating element embedded in the ceramic body;
a plurality of substrate supporting features formed on the substrate chucking surface, the plurality of substrate supporting features comprises:
a first group of supporting features radially disposed in an inner region of the substrate chucking surface at a first radial distance, the first group of supporting features having a first constant density; and
a second group of supporting features radially disposed in an outer region of the substrate chucking surface at a second radial distance, the second group of supporting features having a second constant density, wherein the outer region surrounds the inner region, the second constant density is greater than the first constant density, and a ratio of the first radial distance to the second radial distance is between 1:1 and 4:1, and wherein a ratio of the second constant density to the first constant density is about 4:1 to about 10:1; and
a seasoning layer formed on the plurality of the substrate supporting features, the seasoning layer comprising silicon nitride, silicon, or silicon oxide.

US Pat. No. 10,971,389

MULTI-ZONE PEDESTAL FOR PLASMA PROCESSING

APPLIED MATERIALS, INC., ...

1. A pedestal for a semiconductor processing chamber, comprising:a body comprising a ceramic material;
a plurality of heater elements encapsulated within the body, wherein each of the plurality of heater elements are separated by a gap; and
a shaft coupled to the body, the shaft including a plurality of channels formed therein, a portion of the channels having a curved guide portion formed therein that align a respective channel of the plurality of channels to a groove formed in a surface of the body.

US Pat. No. 10,971,388

CHUCK FOR EDGE BEVEL REMOVAL AND METHOD FOR CENTERING A WAFER PRIOR TO EDGE BEVEL REMOVAL

Lam Research Corporation,...

1. A method of centering a semiconductor wafer, the method comprising:(a) transferring a wafer above a rotatable chuck having at least three support arms with support pins at outer portions of the support arms;
(b) lowering the wafer onto the support pins;
(c) supplying pressurized gas to gas passages within the support pins, the support pins having gas outlets in an upper surface of the support pins such that the wafer floats on gas cushions formed by gas flowing out of the gas outlets in the upper surfaces of the support pins;
(d) centering the wafer by moving the wafer across the support pins while the wafer floats on the gas cushions; and
(e) applying vacuum to the gas passages within the support pins such that the water is vacuum clamped to the upper surface of each support pin, thereby enabling at least one cycle of wafer flotation and vacuum clamping of the same water on the same support pins during a wafer treatment process.

US Pat. No. 10,971,387

MASK-INTEGRATED SURFACE PROTECTIVE TAPE

FURUKAWA ELECTRIC CO., LT...

1. A process for producing semiconductor chips using a mask-integrated surface protective tape, wherein the mask-integrated surface protective tape comprises a base film and a mask material layer on the base film, said process comprising:(a) a step of, in a state of having laminated the mask-integrated surface protective tape on a side of a patterned surface of a semiconductor wafer, grinding a backing-face side of the semiconductor wafer; laminating a water fixing tape on the backing-face side of the semiconductor wafer; and supporting and fixing the semiconductor wafer to a ring flame;
(b) a step of, after peeling the base film of the mask-integrated surface protective tape, thereby exposing the mask material layer on top, forming an opening of a street of the semiconductor water by cutting a portion of the mask material layer corresponding to the street of the semiconductor wafer by laser;
(c) a plasma-dicing step of segmentalizing the semiconductor wafer on the street by a SF6 plasma, thereby singulating the semiconductor wafer into semiconductor chips; and
(d) an ashing step of removing the mask material layer by an O2 plasma,
wherein a wetting tension of the base film on a side from which the mask material layer is peeled is 20.0 mN/m or more and 48.0 mN/m or less, and wherein a surface roughness Ra of the base film on the side from which the mask material layer is peeled is within a range of 0.05 ?m or more and 2.0 ?m or less when measured in conformity to JIS B0601.

US Pat. No. 10,971,386

DEVICE POSITIONING USING SENSORS

TAIWAN SEMICONDUCTOR MANU...

1. A method for positioning a mobile device relative to a stationary device in a semiconductor manufacturing environment, comprising:moving the mobile device, from a first mobile device position, relative to the stationary device until an image acquired from a sensor affixed to the mobile device indicates that a target affixed to the stationary device is within a field of view of the sensor;
determining a first position coordinate offset value and a second position coordinate offset value of the target relative to a center position within the image based upon a location of the target in the image relative to the center position within the image;
moving the mobile device to a second mobile device position relative to the stationary device based upon the first position coordinate offset value and the second position coordinate offset value until the target is located within the image at a specified position relative to the center position; and
saving the second mobile device position for subsequently moving the mobile device relative to the stationary device.

US Pat. No. 10,971,385

SUBSTRATE PROCESSING APPARATUS AND TRANSFER POSITION CORRECTING METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a transfer device configured to transfer a substrate, the transfer device having a first pick configured to support the substrate;
a detecting device configured to detect a position of the substrate transferred by the transfer device;
a processing chamber connected to a transfer chamber in which the transfer device and the detecting device are accommodated;
a susceptor configured to place the substrate thereon, the susceptor being provided within the processing chamber;
an elevating device configured to move the substrate up and down, the elevating device being configured to be protruded from and retreated into the susceptor; and
a control device configured to control the transfer device and the elevating device,
wherein the control device comprises:
an adjuster configured to perform a teaching processing of adjusting a position of the first pick of the transfer device;
a detector configured to deliver the substrate from the first pick to the susceptor and from the susceptor to the first pick by controlling the transfer device and the elevating device, and configured to detect a first position of the substrate, which is delivered from the susceptor to the first pick, by the detecting device; and
a corrector configured to correct the position of the first pick based on a deviation amount between the first position of the substrate and a previously detected reference position,
wherein the transfer device further comprises a second pick configured to hold the substrate,
the adjuster performs the teaching processing of adjusting the position of the first pick and a position of the second pick of the transfer device,
the detector delivers the substrate from the first pick to the susceptor, from the susceptor to the second pick and from the second pick to the first pick by controlling the transfer device and the elevating device, and detects a second position of the substrate, which is delivered from the second pick to the first pick, by the detecting device, and
the corrector corrects the position of the second pick based on a deviation amount between the second position of the substrate and the first position of the substrate.

US Pat. No. 10,971,384

AUTO-CALIBRATED PROCESS INDEPENDENT FEEDFORWARD CONTROL FOR PROCESSING SUBSTRATES

Lam Research Corporation,...

1. A substrate processing system comprising:a sensor to generate sensed values of a parameter of the substrate processing system;
an actuator to adjust the parameter of the substrate processing system; and
a controller in communication with the sensor and the actuator and configured to
process a first substrate using the sensed values to adjust control values for controlling the actuator without feedforward control during a process,
automatically calibrate feedforward values for processing a second substrate based on the sensed values and the control values, wherein the automatic calibration of the feedforward values comprises
time-shifting the sensed values by a delay period to generate time-shifted sensed values,
determining changes in the time-shifted sensed values during a plurality of etch or deposition steps of the process,
determining an average value for one of the control values,
determining a scaled value based on one of the changes in the time-shifted sensed values and a duration of one of the plurality of etch or deposition steps, and
determining one of the feedforward values based on a difference between the average value and the scaled value, and
process the second substrate while controlling the actuator using the feedforward values.

US Pat. No. 10,971,383

FLUORESCENCE BASED THERMOMETRY FOR PACKAGING APPLICATIONS

APPLIED MATERIALS, INC., ...

1. A substrate for forming an electronics package, comprising:a body having an upper surface area;
an array of microcircuit dies disposed in the body and substantially covering the upper surface area;
an epoxy resin disposed between adjacent microcircuit dies and along a periphery of the body, away from the array of microcircuit dies
one or more chips, wherein the one or more chips comprise memory chips, logic chips, communication chips and sensors;
a redistribution layer (RDL) comprising a polymer layer and one or more conductive traces disposed through the polymer layer; and
one or more contact pads disposed on each of the one or more chips, wherein the one or more contact pads are coupled to the one or more conductive traces of the RDL.

US Pat. No. 10,971,382

LOADLOCK MODULE AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor manufacturing apparatus comprising:a loadlock module comprising a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and
a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate,
wherein the loadlock module comprises:
a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container;
an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container; and
a stage configured to support the substrate container, the stage comprising a plate on which the substrate container is placed and a locking lever pivotably mounted on the plate,
wherein the locking lever is configured to pivot between a fixing position at which the locking lever is engaged by a protrusion of the substrate container to fix the substrate container and a releasing position at which the locking lever is separated from the protrusion of the substrate container to release the substrate container,
wherein the plate includes an upper plate and a lower plate located under the upper plate, wherein a distance between the upper plate and the lower plate is adjustable,
wherein the locking lever comprises a first link pivotably mounted on the lower plate and a second link pivotably mounted on the upper plate, and
wherein the first link is configured to pivot while the distance between the upper plate and the lower plate is adjusted, and the second link is configured to pivot between the fixing position and the releasing position while the first link pivots.

US Pat. No. 10,971,381

TRANSFER CHAMBERS WITH AN INCREASED NUMBER OF SIDES, SEMICONDUCTOR DEVICE MANUFACTURING PROCESSING TOOLS, AND PROCESSING METHODS

Applied Materials, Inc., ...

1. A substrate processing system comprising:a transfer chamber comprising:
a first side to interface with an interface unit;
a second side, opposite the first side, to interface with a pass-through unit;
a set of third sides that are coupled between the first side and the second side, each of the set of third sides configured to couple to one or more processing chambers, wherein the first side and the second side are of an elongated width compared to widths of each of the set of third sides; and
a single robot to pass substrates through the first side, the second side, and the set of third sides; and
the interface unit comprising an integral unit body that comprises:
a mating piece, having three interface sides, that mates with the first side of the transfer chamber, wherein a first interface side of the three interface sides is parallel to the first side, and a second interface side and a third interface side of the three interface sides are each connected to, and form an acute angle with respect to, the first interface side; and
three batch load locks coupled to the three interface sides, respectively, wherein each of the three interface sides comprises at least one slot through which to pass substrates to or from a corresponding batch load lock of the three batch load locks.

US Pat. No. 10,971,380

DE-BONDING LEVELING DEVICE AND DE-BONDING METHOD

Shanghai Micro Electronic...

1. A debonding leveling device for leveling during a process for debonding a first object and a second object, the first and second objects fixed to a first fixation plate and a second fixation plate, respectively, wherein the debonding leveling device comprises:a mounting plate, disposed at an outer side of one of the first and second fixation plates;
a connecting rod assembly fixed to the mounting plate around a center position, the connecting rod assembly connected to the one of the first and second fixation plates sequentially via a sliding pair and a spherical pair connected to the sliding pair; and
at least three elastic assemblies disposed between the mounting plate and the one of the first and second fixation plates, each of the elastic assemblies coupled to the mounting plate and the one of the first and second fixation plates.

US Pat. No. 10,971,379

WAFER BONDING APPARATUS AND WAFER BONDING SYSTEM USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A wafer bonding apparatus, comprising:a first bonding chuck to fix a first wafer arranged on a first surface thereof;
a second bonding chuck to fix a second wafer on a second surface thereof, the second surface facing the first surface;
a bonding initiation member at a center of the first bonding chuck to push the first wafer towards the second surface; and
a membrane member having a protrusion protruding from a center portion of the second surface towards the first surface and a planar portion defining the protrusion in an outer region surrounding the center portion of the second surface.

US Pat. No. 10,971,378

METHOD AND DEVICE FOR BONDING SUBSTRATES

EV Group E. Thallner GmbH...

1. A bonding device for bonding a first substrate to a second substrate, the bonding device comprising:a first chuck configured to hold the first substrate and/or apply pressure to the first substrate, the first chuck including a first surface configured to contact a substrate surface of the first substrate;
a second chuck configured to hold the second substrate and/or apply pressure to the second substrate, the second chuck including a second surface configured to contact a substrate surface of the second substrate, at least one of the first surface and the second surface being formed by a plurality of protrusions;
flow channels located between the protrusions of the least one of the first surface and the second surface;
a gas supply configured to introduce gas into the flow channels to provide convective and/or conductive heating; and
an arm bounding an entire radial peripheral area of the protrusions of the at least one of the first surface and the second surface, the arm including a passage configured to control leakage of an excess amount of the introduced gas from the flow channels.

US Pat. No. 10,971,377

SEMICONDUCTOR CHIP

Murata Manufacturing Co.,...

1. A semiconductor chip comprising:a first transistor which amplifies a first signal and outputs a second signal;
a second transistor which amplifies the second signal and outputs a third signal; and
a semiconductor substrate which has a main surface parallel to a plane defined by a first direction and a second direction intersecting with the first direction and which has the first transistor and the second transistor formed thereon, the main surface of the semiconductor substrate that has a first side and a second side, which are parallel to the first direction, and a third side and a fourth side, which are parallel to the second direction, a centerline of the chip being provided at a point that is a midpoint between the third side and the fourth side and the centerline intersecting each of the first side and the second side,
the main surface of the semiconductor substrate being provided with:
a first bump electrically connected to a collector or a drain of the first transistor;
a second bump electrically connected to an emitter or a source of the first transistor;
a third bump electrically connected to a collector or a drain of the second transistor;
a fourth bump electrically connected to an emitter or a source of the second transistor; and
a sixth bump provided on the main surface of the semiconductor substrate, wherein in a planar view of the main surface of the semiconductor substrate,
an area of each of the second and the fourth bumps is larger than an area of the first bump,
the third bump is disposed closer to the first side than to the second side, such that a long side direction of the third bump is substantially parallel to the first direction, and
the sixth bump is disposed closer to the first side than the second side.

US Pat. No. 10,971,376

PRINTED CIRCUIT BOARD WITH PROTECTIVE MEMBER AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a semiconductor package, the method comprising:providing a substrate main body to which external connection terminals are attached;
attaching a protective member to the substrate main body to cover the external connection terminals;
mounting a semiconductor chip on a surface of the substrate main body that is opposite from the protective member;
removing the protective member from the substrate main body, wherein side surfaces and a bottom surface of the external connection terminals are exposed; and
forming solder balls by processing the exposed external connection terminals, after removing the protective member.

US Pat. No. 10,971,375

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

STMICROELECTRONICS S.R.L....

1. A method, comprising:coupling a back surface of a semiconductor die to a support member, the semiconductor die having a front surface having a plurality of die pads;
forming a plurality of recesses in the support member by applying a vacuum to the support member;
arranging a plurality of electrically-conductive bodies into the plurality of recesses, respectively, formed in the support member, wherein the plurality of electrically- conductive bodies are laterally arranged with respect to the semiconductor die;
molding a molding material over the support member between the semiconductor die and the plurality of electrically-conductive bodies, and
forming a plurality of electrically-conductive lines on the molding material, the plurality of electrically-conductive lines extending between respective ones of the plurality of die pads of the semiconductor die and respective ones of the plurality of electrically-conductive bodies.

US Pat. No. 10,971,374

SEMI-INSULATING COMPOUND SEMICONDUCTOR SUBSTRATE AND SEMI-INSULATING COMPOUND SEMICONDUCTOR SINGLE CRYSTAL

SUMITOMO ELECTRIC INDUSTR...

1. A semi-insulating compound semiconductor substrate comprising a semi-insulating compound semiconductor,the semi-insulating compound semiconductor substrate being configured such that, on a major plane having a plane orientation of (100), a standard deviation/average value of specific resistance measured at intervals of 0.1 mm along four directions of [01-1], [0-1-1], [0-11], and [011] from a center of the major plane, and a standard deviation/average value of specific resistance measured at intervals of 0.1 mm along four directions of [010], [00-1], [0-10], and [001] from the center of the major plane are each not more than 0.1.

US Pat. No. 10,971,373

METHODS FOR CYCLIC ETCHING OF A PATTERNED LAYER

Tokyo Electron Limited, ...

1. A method for treating a substrate, comprising:receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer;
forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed;
removing, concurrently, the first layer and the second layer from the substrate; and
alternating between the forming and the removing until portions of the underlying layer are exposed,
wherein the first layer and the second layer have different compositions, and
wherein the forming comprises exposing the substrate to fluorocarbon (CxFy) gas.

US Pat. No. 10,971,372

GAS PHASE ETCH WITH CONTROLLABLE ETCH SELECTIVITY OF SI-CONTAINING ARC OR SILICON OXYNITRIDE TO DIFFERENT FILMS OR MASKS

TOKYO ELECTRON LIMITED, ...

1. A method for the dry removal of a material on a microelectronic workpiece, comprising:receiving a workpiece having a multi-layer mask that includes: (i) a patterned layer and (ii) a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen;
placing the workpiece in a processing chamber consisting of a dry, non-plasma etch chamber and locating the workpiece on a workpiece holder; and
operating the dry, non-plasma etch chamber to selectively remove at least a portion of the target layer from the workpiece by performing the following:
exposing the surface of the workpiece to a chemical environment containing a gaseous mixture that includes N, H, and F at a first workpiece setpoint temperature to chemically alter a surface region of the target layer and to chemically alter a depth within the target layer such that, after the exposing, the target layer includes a chemically altered surface region and a chemically altered depth within the target layer; wherein the N, H, and F are introduced to the dry, non-plasma etch chamber simultaneously,
establishing the surface of the workpiece at the first workpiece setpoint temperature by flowing a heat transfer fluid through the workpiece holder at a first fluid setpoint temperature;
monitoring, by a temperature sensing device, a temperature of the workpiece holder; and
after establishing the surface of the workpiece at the first workpiece setpoint temperature, elevating the temperature of the workpiece to a second workpiece setpoint temperature by adjusting a flow rate of the heat transfer fluid flowing through the workpiece holder based on the monitored temperature of the workpiece holder by the temperature sensing device, wherein prior to elevating the temperature of the workpiece to the second workpiece setpoint temperature, the target layer includes the chemically altered surface region and the chemically altered depth within the target layer;
wherein the selectively removing of at least a portion of the target layer is performed selectively relative to silicon oxide, silicon nitride, crystalline silicon, amorphous silicon, amorphous carbon, and organic materials; and
wherein the target layer comprises SiOxNy, x and y being real numbers greater than zero, and wherein an etch selectivity of the target layer relative to silicon oxide, silicon nitride, crystalline silicon, amorphous silicon, amorphous carbon, and organic materials exceeds unity.

US Pat. No. 10,971,371

MULTI-CHIP STRUCTURE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. A device comprising:a molding compound layer, the molding compound layer having a first sidewall and a second sidewall opposite to the first sidewall;
a first chip embedded in the molding compound layer, wherein a first sidewall of the first chip is coplanar with the first sidewall of the molding compound layer, and wherein a second sidewall of the first chip is spaced apart from the second sidewall of the molding compound layer; and
a second chip over the first chip and embedded in the molding compound layer, wherein a first sidewall of the second chip is coplanar with the second sidewall of the molding compound layer, and wherein a second sidewall of the second chip is spaced apart from the first sidewall of the molding compound layer.

US Pat. No. 10,971,370

HARD MASK REMOVAL METHOD

Taiwan Semiconductor Manu...

1. A method, comprising:forming a first plurality of gate stacks on a substrate, wherein gate stacks of the first plurality of gate stacks each comprise a first hard mask layer over a first dielectric layer, and after the first plurality of gate stacks are formed the gate stacks of the first plurality of gate stacks each have a first height;
forming a second plurality of gate stacks on the substrate, wherein gate stacks of the second plurality of gate stacks each comprise a second hard mask layer over a second dielectric layer, and after the second plurality of gate stacks are formed the gate stacks of the second plurality of gate stacks have a second height that is different than the first height;
depositing a third dielectric layer on exposed surfaces of the substrate, the first plurality of gate stacks, and the second plurality of gate stacks, wherein a loading of the third dielectric layer is greater over the first plurality of gate stacks than over the second plurality of gate stacks;
performing a chemical mechanical polishing (CMP) process on the third dielectric layer, the first hard mask layer of each of the first plurality of gate stacks, the second hard mask layer of each of the second plurality of gate stacks, and the second dielectric layer of each of the second plurality of gate stacks, wherein after the CMP process is performed the first hard mask layer of each of the first plurality of gate stacks and the second hard mask layer of each of the second plurality of gate stacks have been removed; and
after performing the CMP process, etching the third dielectric layer to remove the third dielectric layer and expose portions of the substrate.

US Pat. No. 10,971,369

PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

HITACHI HIGH-TECH CORPORA...

1. A plasma processing method for etching a film to be etched by repeating a depositing process, the method comprising:a first step of depositing a layer over the film to be etched;
a second step of removing a reaction product of the deposited layer and the film to be etched; and
a monitoring process for monitoring a change amount of a film thickness of the deposited layer during said first step of depositing said layer using change of a coherent light that is obtained by irradiating a polarized light polarized to a predetermined angle with respect to a mask pattern of the film to be etched and is reflected by the mask pattern.

US Pat. No. 10,971,368

TECHNIQUES FOR PROCESSING SUBSTRATES USING DIRECTIONAL REACTIVE ION ETCHING

Varian Semiconductor Equi...

1. A method of treating a substrate, comprising:providing a surface feature in the substrate, wherein the surface feature comprises a first material, disposed as a liner along a second material, the surface feature comprising a first sidewall and a second sidewall opposite the first sidewall and facing the first sidewall, the first sidewall and the second sidewall being separated by a first distance, wherein the first sidewall and the second sidewall define a reentrant profile; and
directing first ions to the first sidewall along at least one non-zero angle with respect to a perpendicular to a substrate plane in a presence of a reactive ambient containing a reactive species,
directing second ions to the second sidewall along at least one non-zero angle with respect to the perpendicular to a substrate plane in the presence of the reactive ambient containing a reactive species,
wherein the first sidewall and the second sidewall are etched by the ions in combination with the reactive ambient, wherein a first portion of the first material is etched, wherein at least a portion of the first material remains as the liner along the first sidewall, after the directing the ions, and
wherein a distance between an upper part of the first sidewall and an upper part of the second sidewall is increased, while a distance between a lower part of the first sidewall and a lower part of the second sidewall is not increased.

US Pat. No. 10,971,367

METHOD FOR FABRICATING VERTICAL TRANSISTOR HAVING A SILICIDED BOTTOM

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device, comprising:providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate;
sequentially forming a first protective layer and a second protective layer on the substrate structure;
etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column;
removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column;
removing a remaining portion of the second protective layer; and
forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column.

US Pat. No. 10,971,366

METHODS FOR SILICIDE DEPOSITION

Applied Materials, Inc., ...

1. A method for depositing a metal silicide, comprising:heating a substrate having a silicon-containing surface to a deposition temperature; and
exposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process, wherein the deposition gas comprises a silicon precursor, a titanium precursor, and a phosphorus precursor;
wherein the silicide film has a Ti:Si atomic ratio from about 2:1 to about 15:1 and a P:Si atomic ratio about 2:1 to about 12:1.

US Pat. No. 10,971,365

METHOD AND DEVICE FOR BONDING SUBSTRATES

EV Group E. Thallner GmbH...

1. A method for bonding a first substrate with a second substrate, said method comprising:producing a first amorphous layer on the first substrate and/or producing a second amorphous layer on the second substrate,
bonding of the first substrate with the second substrate at the first amorphous layer and/or the second amorphous layer to form a substrate stack,
irradiating the first amorphous layer and/or the second amorphous layer with a radiation having a radiant energy such that at least a portion of the first amorphous layer and/or the second amorphous layer is/are transformed into a crystalline layer or crystalline layers,
wherein the first amorphous layer and/or the second amorphous layer in a particle energy region between 1.8 eV and 3.0 eV have an amorphous phase with an absorption capacity that is higher than an absorption capacity of a crystalline phase by a factor in a range of 0.2 to 18.

US Pat. No. 10,971,364

ULTRA-HIGH MODULUS AND ETCH SELECTIVITY BORON CARBON HARDMASK FILMS

Applied Materials, Inc., ...

1. A semiconductor device, comprising:a boron-carbon amorphous film deposited over a substrate, the boron-carbon amorphous film comprising:
from about 30 to about 70 atomic percentage of boron;
from about 30 to about 70 atomic percentage of carbon; and
from about 10 to about 25 atomic percentage of hydrogen,
wherein the boron-carbon amorphous film has an elastic modulus (GPa) from about 200 to about 400 GPa, and
wherein the boron-carbon amorphous film has a stress (MPa) from about ?100 MPa to about 100 MPa, and a refractive index (n) of greater than 2.5.

US Pat. No. 10,971,363

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

16. A method for forming a semiconductor device structure, comprising:forming a first layer over a substrate, wherein the first layer has a first trench and a second trench;
forming first spacers over first inner walls of the first trench and second inner walls of the second trench, wherein a first top surface of the first spacer is substantially aligned with a second top surface of the first layer;
removing a portion of the first spacers;
forming a filling layer into the first trench and the second trench, wherein the filling layer and the first spacers in the first trench together form a first strip structure, and the filling layer and the first spacers in the second trench together form a second strip structure;
removing the first layer; and
forming second spacers over two opposite first sidewalls of the first strip structure and two opposite second sidewalls of the second strip structure.

US Pat. No. 10,971,362

EXTREME ULTRAVIOLET PATTERNING PROCESS WITH RESIST HARDENING

International Business Ma...

1. A method of forming a photolithographic patterning structure, the method comprising:patterning at least a photoresist layer of a photolithographic patterning stack, the patterning exposing portions of a silicon germanium layer of the photolithographic patterning stack;
forming a germanium oxide layer in contact with the patterned photoresist layer and the portions of the silicon germanium layer; and
forming, from the germanium oxide layer, a plurality of silicon oxide layers each in contact with one of the portions of the silicon germanium layer.

US Pat. No. 10,971,361

LASER ANNEALING METHOD, LASER ANNEALING APPARATUS, AND THIN FILM TRANSISTOR SUBSTRATE

V TECHNOLOGY CO., LTD., ...

1. A laser annealing apparatus for irradiating an amorphous silicon film formed on a substrate with laser beams and crystallizing the amorphous silicon film, the apparatus comprising:scanning means including a plurality of flotation units arranged in a row, the scanning means being configured to hold edges of the substrate and scan the substrate with the substrate floated above a scanning surface of the scanning means by the flotation units;
a light shielding mask which is disposed facing the scanning surface of the scanning means and provided with a plurality of mask patterns corresponding to first and second thin film transistor formation portions on the substrate; and
a projecting optical system which is provided on a scanning means side of the light shielding mask and which is configured to form images of the plurality of mask patterns on the substrate,
wherein:
the plurality of mask patterns are arranged in a matrix with columns extending in a scanning direction of the substrate and rows extending in a direction orthogonal to the scanning direction, and
a number of mask patterns, among the plurality of mask patterns, that are arranged in each of the columns extending in the scanning direction, so as to correspond to the second thin film transistor formation portions, is smaller than a number of mask patterns, among the plurality of mask patterns, that are arranged in each of the columns extending in the scanning direction so as to correspond to the first thin film transistor formation portions, and
wherein the apparatus is configured to:
perform multiple irradiation of pulse laser beams on the first thin film transistor formation portions through the number of mask patterns that are arranged in each of the columns extending in the scanning direction for the first thin film transistor formation portions, to cause crystallization of the amorphous silicon film in the first thin film transistor formation portions into a polysilicon film having a crystalline state, and
perform multiple irradiation of pulse laser beams on the second thin film transistor formation portions through the number of mask patterns that are arranged in each of the columns extending in the scanning direction for the second thin film transistor formation portions, to cause crystallization of the amorphous silicon film in the second thin film transistor formation portions into a polysilicon film having another crystalline state that is different from that of the polysilicon film in the first thin film transistor formation portions.

US Pat. No. 10,971,360

METHODS OF FORMING A CHANNEL REGION OF A TRANSISTOR AND METHODS USED IN FORMING A MEMORY ARRAY

Micron Technology, Inc., ...

1. A method used in forming a memory array, comprising:forming an assembly comprising a vertical stack comprising alternating tiers of different composition materials, one of the different composition materials and corresponding of the alternating tiers being insulative, the assembly comprising a hollow tube of amorphous channel material extending elevationally through the stack;
forming a hollow tube of first insulating material adjacent a radially-inner side of the hollow tube of the amorphous channel material below a crystallization temperature at and above which the amorphous channel material would become crystalline;
forming a hollow tube of second insulating material adjacent a radially-inner side of the hollow tube of the first insulating material;
subjecting the amorphous channel material having the first insulating material there-adjacent to a temperature at or above the crystallization temperature to transform the amorphous channel material into crystalline channel material.

US Pat. No. 10,971,359

MANAGED SUBSTRATE EFFECTS FOR STABILIZED SOI FETS

pSemi Corporation, San D...

1. An integrated circuit structure including:(a) a high resistivity silicon substrate;
(b) a layer that includes at least one trap rich region and at least one non-trap rich region formed on the substrate;
(c) an insulator layer formed on the layer that includes at least one trap rich region and at least one non-trap rich region;
(d) an active layer formed on the insulator layer;
(e) first circuitry fabricated in and/or on the active layer above at least one non-trap rich region, the first circuitry including circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry; and
(f) second circuitry fabricated in and/or on the active layer above the at least one trap rich layer, the second circuitry including circuitry that can benefit from the characteristics of the trap rich layer.

US Pat. No. 10,971,358

METHOD OF MAKING A PEELED MAGNESIUM OXIDE SUBSTRATE USING LASER IRRADIATION

SHIN-ETSU POLYMER CO., LT...

1. A substrate manufacturing method, comprising:a first step of disposing a condenser for condensing a laser beam in a non-contact manner on an irradiated surface of a single crystal member of magnesium oxide to be irradiated;
a second step of irradiating the laser beam to the surface of the single crystal member and condensing the laser beam into the inner portion of the single crystal member under designated irradiation conditions using the condenser, and at a same time, two-dimensionally moving the condenser and the single crystal member relatively to each other, and sequentially forming processing mark lines in parallel; and
a third step of irradiating the laser beam to the surface of the single crystal member and condensing the laser beam into the inner portion of the single crystal member under designated irradiation conditions using the condenser, and at a same time, two-dimensionally moving the condenser and the single crystal member relatively to each other, and forming new processing mark lines between the adjacent processing mark lines formed by the irradiation in the second step to allow planar separation,
wherein, in the second step, the laser beam is condensed to form a reflection layer that reflects the laser beam,
wherein in the third step, the laser beam is reflected on the reflection layer,
and wherein the reflection layer is formed at an lower separation plane, holes are formed on an upper separation plane due to the reflection of the laser beam from the reflection layer, and a molten scattered substance from the upper separation layer is formed on the lower separation plane.

US Pat. No. 10,971,357

THIN FILM TREATMENT PROCESS

Applied Materials, Inc., ...

20. A method of modifying a film in a semiconductor device, comprising:exposing a surface of the film disposed on a surface of a substrate to a first plasma formed from a first process gas that comprises helium, while the substrate is heated to a first temperature between about 150° C. and about 500° C., wherein the first plasma is created by applying a first source power to the first process gas, and the first plasma has an average ion density over the surface of film during processing of between about 1×1010 and 1×1012 ions per cubic centimeter (cm?3); and
exposing the surface of the film disposed on the surface of the substrate to a second plasma formed from a second process gas that comprises helium and oxygen, wherein the second plasma is created by applying a second source power greater than the first source power to the second process gas.

US Pat. No. 10,971,356

STACK VIABAR STRUCTURES

International Business Ma...

1. A method for fabricating an electrical contact in a BEOL metallization layer for a semiconductor structure, the method comprising:providing a semiconductor stack disposed on a circuit supporting substrate, a top layer of the semiconductor stack including a semiconductor contact located in the top layer; and
patterning a second BEOL metallization layer disposed directly on a first BEOL metallization layer including metallization contact located in the first BEOL metallization layer such that a location of the metallization contact is vertically mismatched from the location of the semiconductor contact, followed by deposition of a metal fill material filling a via trench in the first BEOL metallization layer and the second BEOL metallization layer, to provide a super viabar structure that forms an electrical interconnect, in the second BEOL metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first BEOL metallization layer.

US Pat. No. 10,971,355

SUBSTRATES AND METHODS FOR FORMING THE SAME

Vanguard International Se...

1. A substrate, comprising:a ceramic core;
a first adhesion layer encapsulating the ceramic core and comprising silicon oxynitride, wherein an atomic number ratio of oxygen to nitrogen in silicon oxynitride of the first adhesion layer has a first ratio;
a barrier layer encapsulating the first adhesion layer and comprising silicon oxynitride, wherein an atomic number ratio of oxygen to nitrogen in silicon oxynitride of the barrier layer has a second ratio that is different from the first ratio; and
a second adhesion layer encapsulating the barrier layer and comprising silicon oxynitride, wherein an atomic number ratio of oxygen to nitrogen in silicon oxynitride of the second adhesion layer has a third ratio that is different from the second ratio.

US Pat. No. 10,971,354

DRYING HIGH ASPECT RATIO FEATURES

Applied Materials, Inc., ...

1. A method of drying a semiconductor substrate, the method comprising:applying a drying agent to a semiconductor substrate, wherein the drying agent wets the semiconductor substrate;
pressure-sealing the semiconductor substrate within the chamber;
heating the chamber housing the semiconductor substrate to a temperature above an atmospheric pressure boiling point of the drying agent until vapor-liquid equilibrium between liquid and vapor phases of the drying agent is reached within the chamber; and
venting the chamber, wherein the venting vaporizes the drying agent liquid phase from the semiconductor substrate.

US Pat. No. 10,971,353

METHOD FOR DEHYDRATING SEMICONDUCTOR STRUCTURE AND DEHYDRATING METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

15. A method for dehydrating a substrate, comprising:providing a substrate; dispensing diluted fluoride over the substrate;
dispensing deionized water over the substrate subsequent to dispensing diluted fluoride;
dispensing isopropanol into the trench subsequent to dispensing deionized water;
dispensing an agent in liquid form over the substrate;
solidify the agent;
vaporizing the agent from solid form to vapor form inside a chamber; and
providing gaseous H2O steam in the chamber subsequent to vaporizing the agent.

US Pat. No. 10,971,352

CLEANING METHOD AND APPARATUS

TAIWAN SEMICONDUCTOR MANU...

18. An apparatus, comprising:a chuck having a hole;
a lifting pin penetrating through the hole of the chuck, wherein the lifting pin comprises an inner gas passage and an outer gas passage concentrically arranged in the lifting pin, and wherein the lifting pin comprises a first opening on a top surface of the lifting pin and at least one second opening on a sidewall of the lifting pin, the first opening in gaseous communication with the inner gas passage, and the at least one second opening in gaseous communication with the outer gas passage;
a vacuum source in gaseous communication with the inner gas passage in the lifting pin; and
a gas source in gaseous communication with the outer gas passage in the lifting pin.

US Pat. No. 10,971,351

WAFER SURFACE BEVELING METHOD, METHOD OF MANUFACTURING WAFER, AND WAFER

SUMCO CORPORATION, Tokyo...

1. A method of polishing a chamfered surface of a wafer, the method comprising:beveling the wafer to generate the chamfered surface, the generated chamfered surface being inclined with respect to a main surface of the wafer by an angle ?; and
polishing the chamfered surface with a polishing pad by inclining a longitudinal surface of the polishing pad by an angle ? with respect to the chamfered surface during the polishing;
wherein:
the angle ? is smaller than the angle ?;
the wafer includes a front wafer surface and a rear wafer surface;
the beveling the wafer comprises generating a front chamfered surface and a rear chamfered surface; and
after the polishing, a degree of corner burring inhibition at least at one of a boundary between the front wafer surface and the front chamfered surface and at a boundary between the rear wafer surface and the rear chamfer surface is 180 ?m or more.

US Pat. No. 10,971,350

WAFER HOLDING APPARATUS AND WAFER PROCESSING METHOD USING THE SAME

DISCO CORPORATION, Tokyo...

1. A wafer processing method for processing a wafer having a first surface and a second surface opposite to the first surface, the wafer processing method using a wafer holding apparatus includinga holding portion having a holding surface for holding the wafer having undulation, the holding portion being composed of a plurality of length changing elements having suction holes selectively connected to a vacuum source, the length changing elements having front end surfaces collected to form the holding surface,
a frame member supporting the holding portion, and
a control unit controlling a length of each of the length changing elements according to the undulation of the wafer,
the wafer processing method comprising:
an undulation detecting step of detecting undulation of the first surface of the wafer;
an undulation producing step of controlling the length of each of the length changing elements of the wafer holding apparatus according to the undulation of the wafer, thereby producing undulation on the holding surface;
a holding step of holding the wafer on the holding surface in a condition where the undulation of the wafer is made to coincide with the undulation of the holding surface;
a resin applying step of applying a gel resin to a substrate having a flat surface;
a resin curing step of opposing the second surface of the wafer to the flat surface of the substrate, next pressing the gel resin applied to the flat surface of the substrate, next transferring the gel resin to the second surface of the wafer, and finally curing the gel resin to form a resin layer on the second surface of the wafer; and
a separating step of separating the wafer with the resin layer from the substrate.

US Pat. No. 10,971,349

ION ANALYZER

Shimadzu Corporation, Ky...

1. An ion analyzer comprising:a sample placement unit on which a sample is to be placed;
an excitation beam irradiation unit configured to irradiate the sample placed on the sample placement unit with an excitation beam having a central axis that is perpendicular to a surface of the sample to generate ions from the sample;
an analysis unit configured to capture the ions and subsequently to separate and measure the ions in accordance with a predetermined physical quantity, the ions flying along a measurement axis which is perpendicular to the central axis;
a deflection unit including a first pair of rod electrodes or plate electrodes positioned on both sides of the central axis and a second pair of rod electrodes or plate electrodes positioned on both sides of the measurement axis, the deflection unit configured to make at least some of ions generated from the sample to fly in a direction of the measurement axis toward the analysis unit;
an extraction electrode interposed between the deflection unit and the sample placement unit, the extraction electrode configured to extract the ions at the surface of the sample away from the sample in a direction of the central axis; and
an image acquiring unit configured to acquire an image of the surface of the sample, wherein an optical axis of the image acquiring unit is coincident with the central axis.

US Pat. No. 10,971,348

APPARATUS FOR DELIVERING REAGENT IONS TO A MASS SPECTROMETER

Thermo Finnigan, San Jos...

1. An apparatus for delivering reagent ions to a mass spectrometer, comprising:a carrier gas supply coupled to a first reagent reservoir, the first reagent reservoir holding a volume of first reagent material in condensed phase;
a first flow restrictor having an inlet end coupled to the first reagent reservoir;
a first variable pressure regulator having an inlet coupled to the carrier gas supply;
a second flow restrictor having an inlet end coupled to an outlet of the first variable pressure regulator;
a mixing junction having a first inlet coupled to the outlet of the first flow restrictor and a second inlet coupled to the outlet of the second flow restrictor;
a third flow restrictor having an inlet end coupled to the mixing junction and an outlet end coupled to an inlet of a reagent transfer junction; and
a reagent ionizer, having an inlet coupled to an outlet of the reagent transfer junction, the reagent ionizer being configured to ionize first reagent vapor received from the reagent transfer junction.

US Pat. No. 10,971,347

CHARGED PARTICLE BEAM APPARATUS

HITACHI HIGH-TECH CORPORA...

1. A charged particle beam apparatus comprising:a charged particle gun;
a scanning deflector configured to scan a charged particle beam emitted from the charged particle gun onto a sample;
a scanning control voltage generator for generating a scanning control voltage to be input to the scanning deflector;
a detector configured to detect an external scanning control voltage, which is input from an outside into the scanning deflector and is different from the scanning control voltage;
an arithmetic unit configured to calculate, based on the detected external scanning control voltage, irradiation pixel coordinates for the charged particle beam;
an irradiation controller configured to control irradiation of the sample with the charged particle beam according to the irradiation pixel coordinates.

US Pat. No. 10,971,346

LIQUID TRAP OR SEPARATOR FOR ELECTROSURGICAL APPLICATIONS

Micromass UK Limited, Wi...

1. An apparatus for mass spectrometry and/or ion mobility spectroscopy comprising:a first device arranged and adapted to generate aerosol, smoke or vapour from a target,
wherein said first device comprises one or more electrodes, and wherein said first device is arranged and adapted to generate said aerosol, smoke or vapour from said target by contacting said target with said one or more electrodes;
a device arranged and adapted to apply an AC or RF voltage to said one or more electrodes in order to generate said aerosol, smoke or vapour;
one or more second devices arranged and adapted to aspirate aerosol, smoke or vapour and/or liquid to or towards a mass and/or ion mobility analyser; and
a liquid trap or separator located between said first device and said mass and/or ion mobility analyser, wherein said liquid trap or separator is arranged and adapted to capture and/or discard liquid aspirated by said one or more second devices.

US Pat. No. 10,971,345

MASS SPECTROMETER AND MASS SPECTROMETRY METHOD

HAMAMATSU PHOTONICS K.K.,...

1. A mass spectrometer comprising:a chamber configured to form a space to be evacuated;
a support configured to, in a state in which, in a sample support body that includes a substrate in which a plurality of through-holes open in first and second surfaces facing each other are formed and a conductive layer that is at least provided on the first surface, the second surface thereof is in contact with a sample, support at least the sample and the sample support body;
a laser beam irradiation part configured to irradiate the first surface with a laser beam;
a voltage application part configured to apply a voltage to the conductive layer;
an ion detection part configured to, in a state in which components of the sample have moved toward the first surface via the plurality of through-holes by a capillary phenomenon, detect the components ionized by irradiating the first surface with the laser beam while applying a voltage to the conductive layer in a space inside the chamber;
a first light irradiation part configured to irradiate the sample with a first light from a side of the substrate; and
an imaging part configured to obtain a reflected light image of the sample by the first light.

US Pat. No. 10,971,344

OPTIMIZED STEPPED COLLISION ENERGY SCHEME FOR TANDEM MASS SPECTROMETRY

Thermo Finnigan LLC, San...

1. A method for mass spectrometry comprising:receiving or generating a respective value of an optimal collision energy for generating each one of a plurality of n product-ion species of interest from at least one precursor-ion species, each optimal collision energy corresponding to a respective maximum fragmentation efficiency; and
performing a mass spectrometric analysis that includes fragmenting the at least one precursor-ion species in a collision cell by imparting, in sequence, each of and only the n optimal collision energy values to ions received from an ion source.

US Pat. No. 10,971,343

APPARATUS FOR MONITORING PROCESS CHAMBER

Samsung Electronics Co., ...

1. A sensor assembly comprising:a sensor module configured to monitor a process status of a process chamber, the sensor module including,
a cover section including a pinhole, the cover section having a first length in a direction toward a center of the process chamber,
a sensor configured to monitor a first region at an interior of the process chamber determined based on the first length through the pinhole, and
a main body including a fixing section and an insertion section, the fixing section configured to removably support the sensor, and the insertion section configured to be coupled to the cover section,
wherein the cover section is configured to protrude from an inner wall of the process chamber and extend toward a center of the process chamber from a position at which an inner wall of a liner is provided.

US Pat. No. 10,971,342

CONTROLLING MULTIPLE PLASMA PROCESSES

TRUMPF Huettinger Sp. z o...

1. A power converter configured to convert an electrical input power into a bipolar output power and to deliver the bipolar output power to at least two independent plasma processing chambers, the power converter comprising:a power input port for connection to an electrical power delivering grid;
at least two power output ports each for connection to a respective one of the plasma processing chambers; and
a controller configured to control delivering the bipolar output power to the power output ports, using at least one control parameter selected from a list comprising power, voltage, current, excitation frequency, and protection threshold,
wherein the controller is configured to:
obtain a full set of desired values for the at least one control parameter for the power output ports,
determine whether a respective desired value for the at least one control parameter is capable of being delivered to each of the power output ports, and
in response to determining that the respective desired values for the at least one control parameter are capable of being delivered to the power output ports, calculate a sequence of pulses of power delivery to the power output ports to supply the bipolar output power to plasma processes in the plasma processing chambers.

US Pat. No. 10,971,341

PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a processing vessel;
an upper structure that is provided on an upper portion of the processing vessel and generates plasma in a lower region thereof;
a structure holding ring that is fixed around the upper structure;
an arm that supports the ring and is movable up and down;
a screw that is fixed to one of the ring and the arm, and has a tip abutting the other; and
a pin that is provided in the ring or the arm, and passes through a hole for restricting horizontal movement of the ring, wherein
the pin is movable within the hole,
the screw does not fix the ring to the arm, and
the tip of the screw is slidable in a horizontal direction on a reference surface that the tip abuts.

US Pat. No. 10,971,340

GAS INJECTOR FOR REACTION REGIONS

1. A gas injector for supplying a gas or a gas mixture to a reaction region, comprising:a base body;
a gas channel formed within the base body;
a plurality of openings in the base body via which the gas or the gas mixture passes from the gas channel into the reaction region, including
a first opening or a first group arrangement of openings and
a second opening or a second group arrangement of openings; and
a plurality of gas supplies, including
a first gas supply allocated to the first opening or group arrangement of openings in the base body, and
a second gas supply allocated to the second opening or group arrangement of openings in the base body,
wherein the second gas supply is provided as a bypass of the first gas supply, the bypass being arranged in the base body, and
wherein the gas injector has an annular or polygonal structure, and
wherein exit angles (?, ?) of the openings are each centrally aligned.

US Pat. No. 10,971,339

ION SOURCE AND CLEANING METHOD THEREOF

NISSIN ION EQUIPMENT CO.,...

1. An ion source comprising:a plasma chamber, and a suppression electrode disposed downstream of the plasma chamber, wherein the ion source is operable to continuously irradiate the suppression electrode with an ion beam produced from a cleaning gas to clean the suppression electrode, and wherein the ion source further comprises:
a drive mechanism that adjusts a distance between the plasma chamber and the suppression electrode; and
a control device configured to, prior to cleaning the suppression electrode, control the drive mechanism to move the suppression electrode or the plasma chamber in a first direction to increase the distance.

US Pat. No. 10,971,338

ACTIVE GAS GENERATING APPARATUS

TOSHIBA MITSUBISHI-ELECTR...

1. An active gas generating apparatus for generating an active gas obtained by activating a source gas supplied to a discharge space, said active gas generating apparatus comprising:a first integrated electrode unit;
a second integrated electrode unit that is provided below said first integrated electrode unit; and
an alternating current source that applies an alternating current voltage to said first integrated electrode unit and said second integrated electrode unit in order to cause said first integrated electrode unit to be supplied with a high voltage, wherein
said alternating current source applies said alternating current voltage to form the discharge space between said first integrated electrode unit and said second integrated electrode unit,
the discharge space is supplied with the source gas that is activated to result in an active gas, said active gas being ejected from a gas ejection port that is provided in said second integrated electrode unit,
said first integrated electrode unit includes a first dielectric electrode, and a first metal electrode that is selectively formed on an upper face of said first dielectric electrode, and
said second integrated electrode unit includes a second dielectric electrode, and a second metal electrode that is selectively formed on a bottom face of said second dielectric electrode,
said active gas generating apparatus further comprising:
a first power feeding unit that is provided above said first metal electrode and configured to transmit said alternating current voltage to said first metal electrode; and
a second power feeding unit that is provided below said second metal electrode and configured to transmit said alternating current voltage to said second metal electrode, wherein
said second metal electrode includes a pair of second metal electrode parts that are formed opposite each other across a central region on said second dielectric electrode in plan view,
said first metal electrode includes a pair of first metal electrode parts, one of said pair of first metal electrode parts having a region overlapping one of said pair of second metal electrode parts in plan view, and other of said pair of first metal electrode parts having a region overlapping other of said pair of second metal electrode parts in plan view,
a part of said first power feeding unit is in contact with said first metal electrode and a part of said second power feeding unit is in contact with said second metal electrode,
said first power feeding unit includes a first projection and a second projection, each of said first projection and said second projection being selectively projected downward, a bottom face of said first projection being in contact with an upper face of one of said pair of first metal electrode parts, and a bottom face of said second projection being in contact with an upper face of other of said pair of first metal electrode parts, and
said first power feeding unit has a shape covering said first metal electrode entirely in plan view.

US Pat. No. 10,971,337

MICROWAVE OUTPUT DEVICE AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A microwave output device comprising:a microwave generation unit configured to generate a microwave having a center frequency and a bandwidth respectively corresponding to a setting frequency and a setting bandwidth instructed by a controller, the microwave having power pulse-modulated such that a pulse frequency, a duty ratio, a high level and a low level respectively corresponding to a pulse frequency, a setting duty ratio, high level setting power and low level setting power instructed by the controller;
an output unit configured to output the microwave propagating from the microwave generation unit;
a first directional coupler configured to output parts of travelling waves propagating from the microwave generation unit to the output unit; and
a measurement unit configured to determine a first high measured value and a first low measured value respectively indicating a high level and a low level of power of the travelling waves in the output unit on the basis of the parts of the travelling waves output from the first directional coupler,
wherein the microwave generation unit
averages the first high measured value and the first low measured value with a predetermined movement average time and a predetermined sampling interval,
controls high level power of the pulse-modulated microwave on the basis of the averaged first high measured value and the high level setting power, and
controls low level power of the pulse-modulated microwave on the basis of the averaged first low measured value and the low level setting power.

US Pat. No. 10,971,336

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus, comprising:a processing vessel;
a carrier wave group generating unit configured to generate a carrier wave group including multiple carrier waves having different frequencies belonging to a preset frequency band centered around a predetermined center frequency; and
a plasma generating unit configured to generate plasma within the processing vessel by using the carrier wave group,
wherein the frequencies of the multiple carrier waves are arranged at a regular interval, and
the regular interval is equal to or less than 1/24,500 with respect to the predetermined center frequency.

US Pat. No. 10,971,335

RADIO FREQUENCY (RF) POWER MONITORING DEVICE AND PLASMA ENHANCED (PE) SYSTEM INCLUDING THE SAME

Samsung Electronics Co., ...

1. A radio frequency (RF) power monitoring device, comprising:an RF sensor to monitor RF power from an RF generator that is transferred to a target load, and to monitor an impedance of the target load, the RF sensor being between the RF generator and the target load; and
a transmission line between the RF sensor and the target load to electrically connect the RF sensor to the target load and to transfer the RF power to the target load, wherein:
the transmission line between the RF sensor and the target load is configured such that a phase (?z) of the impedance of the target load sensed by the sensor is adjusted to satisfy a range of ?30°+180° * n

US Pat. No. 10,971,334

HIGH FREQUENCY ANTENNA AND PLASMA PROCESSING DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A high-frequency antenna provided on an outer surface of a window which is formed in a chamber, the high-frequency antenna being configured to generate an induction electric field in a processing space inside the chamber when a high-frequency current flows, and configured to generate plasma in the processing space by the induction electric field, the high-frequency antenna comprising:a first antenna element that extends along a circumferential direction over a first angle range in the circumferential direction;
a second antenna element that extends along the circumferential direction over a second angle range which deviates from the first angle range in the circumferential direction, and that is arranged away from the window compared to the first antenna element and arranged on an outer peripheral side with respect to the first antenna element; and
a first relaying portion that extends from the first antenna element toward a side away from the window;
a second relaying portion that extends toward the outer peripheral side from the first relaying portion to the second antenna element, and that is arranged away from the window compared to the first antenna element.

US Pat. No. 10,971,333

ANTENNAS, CIRCUITS FOR GENERATING PLASMA, PLASMA PROCESSING APPARATUS, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME

Samsung Electronics Co., ...

1. A plasma generating circuit comprising:first and second radio-frequency power sources configured to generate first and second radio-frequency powers respectively;
first and second antennas configured to receive the first and second radio-frequency powers to generate plasma, respectively, the first and second antennas disposed next to each other and magnetically coupled to have a first mutual inductance;
a first matching circuit connected between the first radio-frequency power source and the first antenna;
a second matching circuit connected between the second radio-frequency power source and the second antenna;
a first inductor connected in series between the first antenna and the first matching circuit; and
a second inductor connected in series between the second antenna and the second matching circuit,
wherein the first and second inductors are disposed next to each other and magnetically coupled to have a second mutual inductance to cancel the first mutual inductances,
wherein either the first mutual inductance has a positive value and the second mutual inductance has a negative value or the first mutual inductance has a negative value and the second mutual inductance has a positive value,
wherein each of the first and second antennas comprises:
an input electrode;
branch electrodes connected to the input electrode, wherein the branch electrodes are provided in plurality; and
coil electrodes connected to opposite ends of the branch electrodes, respectively, the coil electrodes extending and connecting the ends of the branch electrodes,
wherein a number of turns of the coil electrodes of the first antenna is equal to a number of turns of the coil electrodes of the second antenna,
wherein the coil electrodes are eccentric coil electrodes, and
wherein each of the eccentric coil electrodes comprises:
a top coil;
a connection electrode connected to the top coil; and
a bottom coil that is connected to the connection electrode and that is under the top coil.

US Pat. No. 10,971,332

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

CANON ANELVA CORPORATION,...

1. A plasma processing apparatus comprising:a processing chamber configured to process a substrate;
a plasma generator configured to generate a plasma;
a transport unit configured to transport, to the processing chamber, the plasma generated by the plasma generator; and
a scanning magnetic field generator configured to generate a magnetic field which deflects the plasma so as to scan the substrate by the plasma, wherein the scanning magnetic field generator is configured to be capable of adjusting a center of a locus of the plasma,
wherein the scanning magnetic field generator includes a first magnetic field generator configured to generate a first magnetic field parallel to a first direction, a second magnetic field generator configured to generate a second magnetic field parallel to a second direction crossing the first direction, a first power supply configured to supply a first current to the first magnetic field generator, and a second power supply configured to supply a second current to the second magnetic field generator, and
the first power supply supplies, as the first current, a current obtained by superimposing a first DC component on a first sinusoidal wave to the first magnetic field generator, the second power supply supplies, as the second current, a current obtained by superimposing a second DC component on a second sinusoidal wave to the second magnetic field generator, the first DC component and the second DC component being adjustable.

US Pat. No. 10,971,331

WRITING DATA GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAM IS RECORDED, AND MULTI-CHARGED PARTICLE BEAM WRITING APPARATUS

NuFlare Technology, Inc.,...

1. A charged particle beam writing method comprising:referring to library data in which a vertex sequence including a plurality of vertices is registered;
extracting a portion of an outer line of a figure contained in design data, the portion corresponding to the vertex sequence;
representing the extracted portion by information which identifies the vertex sequence and information which indicates a connection method for the plurality of vertices of the vertex sequence;
generating writing data based upon the information which identifies the vertex sequence and the information which indicates the connection method for the plurality of vertices of the vertex sequence; and
controlling a charged particle beam writing apparatus using the writing data to write a pattern by irradiating a substrate with the charged particle beam wherein the connection method describes a line segment shape, angle or direction.

US Pat. No. 10,971,330

AUTOMATIC PROCESSING DEVICE

HITACHI HIGH-TECH SCIENCE...

1. An automatic working apparatus comprising:a charge particle beam column configured to irradiate a sample with a charged particle beam to produce a sample piece;
an input device configured to receive an operation of an operator; and
a controller connected to the input device and, based on the input device receiving a working start instruction, the controller is configured to:
obtain structure information indicating a structure of the sample before working;
obtain end position specifying information that specifies an end position of working corresponding to the structure of the sample;
control the charged particle beam column to irradiate the sample with the charged particle beam to perform working on the sample;
obtain a working surface image, the working surface image being obtained by imaging a working surface that appears at a position where the sample is irradiated with the charged particle beam;
determine whether a working position of the charged particle beam has reached the end position specified by the end position specifying information on the basis of a comparison between the obtained working surface image and the obtained structure information; and
finish the working on the sample in response to it being determined in the determining that the working position of the charged particle beam has reached the end position.

US Pat. No. 10,971,329

FIELD IONIZATION SOURCE, ION BEAM APPARATUS, AND BEAM IRRADIATION METHOD

HITACHI HIGH-TECH CORPORA...

9. A gas field ionization source, comprising:an emitter tip that has a needle-shaped apex;
an extraction electrode that has an opening facing the emitter tip and located at a distance from the emitter tip;
gas feed piping for feeding gas into an area around the emitter tip;
a unit that applies and adjusts a voltage between the emitter tip and the extraction electrode to produce an electric field for ionization of the gas; and
a unit that cools the emitter tip,
wherein the gas is a gas containing hydrogen, and the gas field ionization source has an operating status in which an extraction voltage is applied between an emitter electrode and an extraction electrode; and
wherein the extraction voltage is set around a second voltage higher than a first voltage, the first voltage giving a first maximum of an ion current per the extraction voltage, and the second voltage giving a second maximum of an ion current per the extraction voltage, such that an abundance ratio of a H3+ ion in a probe current is the highest in ion species emitted from the emitter tip, and an energy width of the H3+ ion is smaller than an energy width of a H2+ ion, and
wherein the ion species include a H+ ion, the H2+ ion and the H3+ ion.

US Pat. No. 10,971,328

CHARGED PARTICLE BEAM DEVICE

Hitachi High-Tech Corpora...

1. A charged particle beam device comprising:a charged particle source that generates a primary charged particle beam;
an objective lens that focuses the primary charged particle beam on a sample;
four detectors that are disposed closer to a side of the charged particle source than. the objective lens, are disposed symmetrically around an optical axis of the primary charged particle beam, and detect secondary particles emitted by irradiating the sample with the primary charged particle beam;
an electrode, including four electrodes arranged in a circumferential direction. around. the optical axis of the primary charged particle beam, that forms an electric field in a direction corresponding to each of the four detectors between travel routes of secondary particles from the sample to the four detectors;
wherein the electric field acts in an azimuth direction of the secondary particles, and deflects the secondary particles emitted toward a region between the four detectors into a direction of a detection surface of each of the four detectors.

US Pat. No. 10,971,327

CRYOGENIC HEAT TRANSFER SYSTEM

Applied Materials, Inc., ...

1. A cryogenic heat transfer system comprising:a platen supported by a rotatable shaft; and
a housing surrounding a portion of the rotatable shaft, the housing comprising:
an annular heat sink surrounding the rotatable shaft and defining a heat transfer gap between the heat sink and the rotatable shaft, the heat sink including a fluid conduit extending therethrough for circulating a first cooling fluid through the heat sink;
a first dynamic seal arrangement extending from a first axial end of the heat sink and surrounding the rotatable shaft; and
a second dynamic seal arrangement extending from a second axial end of the heat sink opposite the first axial end and radially surrounding the rotatable shaft;
wherein the heat sink and the first and second dynamic seal arrangements define a fluidically sealed volume surrounding the rotatable shaft, the fluidically sealed volume containing a second cooling fluid.

US Pat. No. 10,971,326

MULTI-ELECTRON-BEAM IMAGING APPARATUS WITH IMPROVED PERFORMANCE

FEI Company, Hillsboro, ...

1. An electron beam imaging apparatus comprising:an electron source, for producing a precursor electron beam;
an aperture plate comprising an array of apertures, the aperture plate for producing an array of electron beams from said precursor electron beam;
an electron beam column for directing said array of electron beams onto a specimen,
wherein said electron beam column is configured to have a length less than 300 mm, said electron beam column including:
a single individual beam crossover plane in which each of said electron beams forms an intermediate image of said electron source; and
a single common beam crossover plane in which the electron beams in the array cross each other.

US Pat. No. 10,971,325

DEFECT OBSERVATION SYSTEM AND DEFECT OBSERVATION METHOD FOR SEMICONDUCTOR WAFER

HITACHI HIGH-TECH CORPORA...

1. A defect observation system for a semiconductor wafer, comprising:a stage on which the semiconductor wafer is placed and which is movable in an XY direction; and
a processor configured to control an electron source which irradiates the semiconductor wafer with an electron beam to obtain a plurality of images each having a portion including an edge of the semiconductor wafer, each said image being obtained while moving the semiconductor wafer in an XY direction on a plane,
wherein the processor is further configured to, with respect to said plurality of obtained images, output a plurality of selected images which are selected from among said plurality of obtained images and in which edges of the semiconductor wafer are substantially in parallel, and to detect a defect of the semiconductor wafer in the output images in which edges of the semiconductor wafer are substantially parallel.

US Pat. No. 10,971,324

TREATMENT METHOD FOR INHIBITING PLATELET ATTACHMENT AND ARTICLES TREATED THEREBY

Exogenesis Corporation, ...

1. A method of modifying a surface of a medical device object so as to inhibit attachment of platelets thereto, the method comprising:forming a Neutral Beam of monomers derived from a gas-cluster ion-beam which is accelerated in a reduced-pressure chamber and treated for dissociation to establish monomers content by separating charged particles and clusters therefrom;
introducing said medical device object into the reduced-pressure chamber;
and irradiating at least a portion of the surface of said medical device object with the Neutral Beam to inhibit attachment of platelets thereto.

US Pat. No. 10,971,323

SEMICONDUCTOR X-RAY TARGET

EXCILLUM AB, Kista (SE)

1. An X-ray source, comprising:an X-ray target;
an electron source operable to generate an electron beam interacting with the X-ray target to generate X-ray radiation with an energy within the range 9 to 12 key;
wherein the X-ray target comprises:
a first element selected from a list consisting of trivalent elements;
a second element selected from a list consisting of pentavalent elements forming a compound with said first element;
a first region including the compound formed of the first and second material; and
a second region supporting the first region;
wherein the first region generates X-ray radiation upon interaction with the electron beam, and heat conduction between the first and second region is dominantly phonon heat conduction.

US Pat. No. 10,971,322

ELECTRON GUN, X-RAY GENERATION APPARATUS, AND X-RAY IMAGING APPARATUS

CANON ANELVA CORPORATION,...

1. An electron gun comprising a cathode including an electron emitting portion, an extraction electrode configured to extract electrons emitted from the electron emitting portion, and a focusing electrode configured to focus the electrons extracted by the extraction electrode, whereinthe focusing electrode includes an outside electrode having a tubular shape, and an inside electrode arranged inside the outside electrode so as to be surrounded by the outside electrode, the inside electrode defines a first space having a columnar shape, and includes a first surface on a side of the cathode, and a second surface on an opposite side of the first surface, and an inside surface of the outside electrode and the second surface of the inside electrode define a second space, and
the inside electrode includes an electron passage hole through which the electrons pass, and a communicating portion arranged apart from the electron passage hole and configured to make the first space and the second space communicate with each other.

US Pat. No. 10,971,321

PROTECTION DEVICE AND BATTERY PACK

Pao-Hsuan Chen, Taoyuan ...

1. A protection device, comprising:a plurality of terminal electrodes, comprising a first terminal electrode and a second terminal electrode;
a fusible conductor, wherein a lower surface of the fusible conductor is respectively disposed on the first terminal electrode and the second terminal electrode, and the fusible conductor is supported by the first terminal electrode and the second terminal electrode, and two ends of the fusible conductor are electrically connected to the first terminal electrode and the second terminal electrode, respectively, so as to form a two-way current path between the first terminal electrode and the second terminal electrode; and
a first heat generating element, wherein one end of the first heat generating element is coupled to another surface of the fusible conductor different to the lower surface of the fusible conductor, or one end of the first heat generating element is coupled to a surface of any one of the first terminal electrode and the second terminal electrode.

US Pat. No. 10,971,320

SWITCHING DEVICE AND CONTROL METHOD

EATON INTELLIGENT POWER L...

1. A switching device, comprising:an electronic trip unit;
an actuator;
a switching mechanism connected via the actuator to the electronic trip unit;
a stationary contact;
a mobile contact, which is coupled to the switching mechanism; and
an alarm module, the alarm module comprising:
a first, a second, and a third connector;
a first relay having a first contact which is connected to the first connector and having a second contact which is connected to the second connector;
a second relay with a first contact which is connected to the third connector; and
a control unit which is coupled on an output side to a control side of the first relay and to a control side of the second relay, and on an input side to the electronic trip unit.

US Pat. No. 10,971,319

SNAP FIT CIRCUIT BREAKER AND LOAD CENTER SYSTEM

Leviton Manufacturing Co....

1. A modular base pan for use in a load center, the base pan comprising:a plurality of line phase electrical connections, a plurality of line neutral electrical connections, a plurality of load neutral electrical connections, and a plurality of load phase electrical connections, the plurality of line phase electrical connections, the plurality of line neutral electrical connections, the plurality of load neutral electrical connections and the plurality of load phase electrical connections are arranged and configured to electrically couple corresponding electrical connections of one or more circuit breakers positioned within the load center;
wherein the base pan includes a top pan portion and a bottom pan portion directly fastened together to form a base pan assembly, wherein each of the plurality of line phase electrical connections, the plurality of line neutral electrical connections, the plurality of load neutral electrical connections and the plurality of load phase electrical connections are secured to the base pan assembly.

US Pat. No. 10,971,318

ELECTRIC CIRCUIT BREAKER DEVICE

DAICEL CORPORATION, Osak...

1. An electric circuit breaker device, comprising:in a housing made of synthetic resin,
an igniter, a rod-like projectile made of synthetic resin, and a conductor portion configured to form a portion of an electric circuit disposed in a cylindrical space formed in the housing in this order from a first end portion side toward a second end portion side opposite the first end portion side in a housing axial direction; and
an insulating closed space formed between a second end portion of the housing and the conductor portion; wherein
the conductor portion is a plate portion comprising a first connection portion and a second connection portion at opposing ends and a cut portion in an intermediate portion between the first connection portion and the second connection portion, a surface of the cut portion being orientated orthogonal to the housing axial direction;
the rod-like projectile is disposed aligned with a surface of the cut portion of the conductor portion in the housing axial direction; and
a width (W1) of the insulating closed space and a width (W2) of an end portion of the rod-like projectile have relationships W1>W2 and W1?W2?0.25 mm.

US Pat. No. 10,971,317

MECHANICAL CLOSING OF A CURRENT INTERRUPTER

ABB Schweiz AG, Baden (C...

1. An apparatus comprising:a current interrupter;
an electromagnet actuator;
a pushrod coupled to the current interrupter and to the electromagnet actuator, the pushrod being displaceable between at least one of a closed position and an open position in response to a supply of an electrical current to the electromagnet actuator; and
a closing mechanism comprising at least one closer body and at least one mechanical biasing element, the closing mechanism being selectively dischargeable from a charged state to a discharged state,
wherein the at least one mechanical biasing element is charged and the at least one closer body is disengaged out of contact with the pushrod when the closing mechanism is in the charged state, and
wherein the at least one mechanical biasing element is discharged to release a first force that displaces the at least one closer body into contact with the pushrod and that displaces the pushrod from the open position to the closed position when the closing mechanism is discharged to the discharged state.

US Pat. No. 10,971,316

PRESSURE TRIP UNIT FOR AN ELECTRICAL SWITCH AND ELECTRICAL SWITCH WITH SUCH A PRESSURE TRIP UNIT

SIEMENS AKTIENGESELLSCHAF...

1. A pressure trip unit for an electrical switch, comprising:an actuating element;
at least one flow channel, each at least one flow channel respectively corresponding to each of at least one electrical pole of the electrical switch,
wherein each at least one pole of the electrical switch includes at least two switching contacts for making or disconnecting a flow path,
wherein the at least two switching contacts of each at least one pole of the electrical switch are disconnectable via the actuating element, the actuating element being configured to respond to a pressure generated in a disconnection zone of each respective switching contact of the at least two switching contacts by an electric arc drawn in an event of an electrodynamic recoil of each of the at least two switching contacts,
wherein the disconnection zone of each respective switching contact is connectable to the actuating element via the at least one flow channel, the at least one flow channel including a non-return valve to permit a flow only from the disconnection zone in a direction of the actuating element, and
wherein the non-return valve of the at least one flow channel includes a tongue, the tongue, in an inoperative state, covering the at least one flow channel and the tongue, in an event of pressure in an associated disconnection zone, being configured to open up the at least one flow channel; and
a housing, including a first housing part and a second housing part, the tongue being held between the first housing part and the second housing part, and the tongue being manufactured from aramid, wherein a response behavior of the non-return valve is set by at least one of an angle and a bending radius of a holding zone of the tongue of the first housing part and the second housing part.

US Pat. No. 10,971,315

KEY MODULE

LITE-ON ELECTRONICS (GUAN...

1. A key module, comprising:a bottom plate;
a keycap, disposed above the bottom plate, comprising a pivoting member protruding from a bottom surface of the keycap and a sliding member, wherein the pivoting member has a pivot hole and a hollowed-out area communicating with the pivot hole; and
a scissor structure, disposed between the bottom plate and the keycap, and comprising a first leg and a second leg pivotally connected to each other, wherein a first side of the first leg and a second side of the second leg are connected to the bottom plate, a third side of the first leg is rotatably connected to the pivoting member of the keycap, and a fourth side of the second leg is slidably connected to the sliding member of the keycap, wherein the pivoting member comprises two projections and a connecting portion connected to the two projections, the two projections and the connecting portion encircle the pivot hole together, and the hollowed-out area is formed at the connecting portion, wherein a thickness of the projection in an extending direction on the third side of the first leg is between 0.7 mm and 1 mm, a thickness of the connecting portion in the extending direction is between 0.3 mm and 0.6 mm.

US Pat. No. 10,971,314

KEY SWITCH

DARFON ELECTRONICS CORP.,...

1. A key switch comprising:a base;
a key cap disposed with respect to the base;
a first support member disposed between the key cap and the base, the first support member having a first linkage structure, the first linkage structure comprising a first engaging portion and a first engaging plate;
a second support member disposed between the key cap and the base and with respect to the first support member, the second support member having a second linkage structure, the second linkage structure comprising a second engaging portion; and
a third support member disposed between the key cap and the base and with respect to the first support member, the third support member having a third linkage structure, the third linkage structure comprising a second engaging plate;
wherein the first engaging plate engages with the second engaging portion, such that the first linkage structure and the second linkage structure abut against each other, and the first support member and the second support member rotate synchronously with respect to a horizontal axis; the second engaging plate engages with the first engaging portion, such that the first linkage structure and the third linkage structure abut against each other, and the first support member and the third support member rotate synchronously with respect to the horizontal axis; when one of the first support member and the second support member horizontally moves with respect to the other one of the first support member and the second support member within a predetermined range along the horizontal axis, the first linkage structure and the second linkage structure keep abutting against each other; the predetermined range is a length range of the first engaging plate along the horizontal axis, and wherein a length of the first engaging plate along the horizontal axis is larger than a length of the second engaging portion along the horizontal axis.

US Pat. No. 10,971,313

SWITCH DEVICE

Valeo Japan Co., Ltd.

1. A switch device comprising:a rod movable forward/backward along an axis line in an axis line direction in association with an operation of a brake pedal;
a main body case in which one end side of the rod in a longitudinal direction is disposed and which supports the rod such that the rod is movable in the axis line direction;
a movable board disposed in the main body case such that the movable board is displaceable in the axis line direction;
a connecting mechanism configured to connect the rod and the movable board;
the movable board displaceable in the axis line direction via the forward/backward movement of the rod in the axis line direction such that a movable contact point provided in the movable board is in contact with or separate from a fixed contact point;
a holder disposed in the main body case to support the rod to be incapable of rotating relatively and to be movable in the axis line direction;
the connecting mechanism including:
a protruding portion radially protruding from an outer periphery of the rod; and
a wall portion provided in the movable board and surrounding the outer periphery of the rod, the wall portion configured such that, when the rod is rotated around the axis line after pushing the rod into the main body case by a predetermined length from an initial position, a tooth portion disposed on an outer periphery of the protruding portion is meshed with a tooth portion disposed on an inner periphery of the wall portion connecting the rod and the movable board;
wherein, in the main body case, the holder is rotatable relative to the main body case within a predetermined angle range from a reference position around the axis line; and
wherein, when the holder is located in the reference position, the protruding portion and the wall portion are disposed to be shifted in a phase in a circumferential direction around the axis line.

US Pat. No. 10,971,312

DYE-SENSITIZED SOLAR CELL AND A METHOD FOR MANUFACTURING THE SOLAR CELL

Exeger Operations AB, St...

1. A method for manufacturing a dye-sensitized solar cell comprising a first and a second conducting layer (2,3) and a porous insulating layer (5b) disposed between the first and second conducting layer, wherein the method comprises:depositing a blocking agent on a top side of a porous substrate (8) made of an insulating material, to form a blocking layer (10) in a portion (8b) of the substrate,
infiltrating the porous substrate from a bottom side of the substrate with conducting particles having a size smaller than the pore size of the substrate to form a third conducting layer (6b) in another portion (8a) of the substrate,
depositing a porous conductive layer on the top side of the porous substrate to form the first conducting layer,
depositing a light absorbing layer comprising TiO2 on the first conducting layer,
depositing an ink comprising conductive particles on the bottom side of the porous substrate to form the second conducting layer, and
heat treating the substrate to burn off the blocking layer thus forming the porous insulating layer.

US Pat. No. 10,971,311

VARIABLE CAPACITOR

1. A variable capacitor, comprising:a multi-layer ceramic capacitor member, the multi-layer ceramic capacitor member comprising:
one or two external electrode(s);
a ceramic dielectric; and
a plurality of electrode layers positioned inside the ceramic dielectric in an interlacing manner; and
a capacitance varying mechanism, the capacitance varying mechanism comprising:
an electrical conductor, positioned aside and approximate to the ceramic dielectric, wherein the electrical conductor made of elastic or flexible material which is deformable responsive to a pressure applied thereon by a mechanical driving structure, and an area of the electrical conductor in contact with the ceramic dielectric varies in accordance with the pressure, thus varying a capacitance value between the external electrode(s) and the electrical conductor,
wherein an auxiliary insulation member is provided between the multi-layer ceramic capacitor member and the electrical conductor so as to form a gap, the external electrode(s) serve(s) as fixed electrode(s) of the variable capacitor, and the electrical conductor serves as a moving electrode of the variable capacitor.

US Pat. No. 10,971,310

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a linear inner conductor having first and second end faces;
a dielectric layer on a surface of the inner conductor;
a conductor layer covering the dielectric layer;
a magnetic body portion covering the conductor layer and peripheral portions of the inner conductor;
first and second outer electrodes electrically coupled to the first and second end faces of the inner conductor, respectively; and
a third outer electrode electrically coupled to the conductor layer.

US Pat. No. 10,971,309

CAPACITOR

PANASONIC INTELLECTUAL PR...

1. A capacitor comprising:a capacitor element;
an insulation coated lead wire connected to an electrode of the capacitor element; and
a resin covering the capacitor element and the insulation coated lead wire in a state that one end of the insulation coated lead wire is exposed from the resin, wherein:
the insulation coated lead wire includes: a stranded wire in which a plurality of conductive wires are twisted with each other; and an insulator covering the stranded wire,
an exposed part of the stranded wire is connected to the electrode of the capacitor element, the exposed part being exposed from the insulator at another end of the insulation coated lead wire,
the exposed part is entirely covered with solder, and
the solder covers an outer peripheral surface of the insulator.

US Pat. No. 10,971,308

MULTILAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a body including a plurality of internal electrodes alternately laminated with dielectric layers interposed therebetween in a lamination direction; and
external electrodes on external surfaces of the body and electrically connected to respective internal electrodes of the plurality of internal electrodes,
wherein the body includes a central portion, an upper cover portion above the central portion in the lamination direction, and a lower cover portion below the central portion in the lamination direction,
wherein the upper and lower cover portions have rounded edges extending from upper and lower surfaces of the body, respectively, to opposing side surfaces of the body to define respective upper and lower rounded regions in the lamination direction,
wherein the body has a thickness T in the lamination direction and each of the rounded edges has a respective radius of curvature R that satisfies 10 ?m?R?T/4,
wherein a first internal electrode of the plurality of internal electrodes in the upper cover portion has a first width in a width direction, substantially perpendicular to the lamination direction, a second internal electrode of the plurality of internal electrodes in the lower cover portion has a second width in the width direction, a third internal electrode of the plurality of internal electrodes in the central portion has a third width in the width direction, and the first and second widths are each less than the third width,
wherein at least one of the first internal electrode or the second internal electrode is arranged in the upper rounded region or the lower rounded region, respectively,
wherein a margin region, between the plurality of internal electrodes and a side surface of the body in the width direction, includes an inner dielectric region with a first compactness and an outer dielectric region, closer to the plurality of internal electrodes than the outer layer of dielectric, with a second compactness, and
the first compactness of the inner dielectric region is greater than the second compactness of the outer dielectric region.

US Pat. No. 10,971,307

MULTI-LAYER CERAMIC CAPACITOR AND METHOD OF PRODUCING A MULTI-LAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic capacitor, comprising:a multi-layer unit including
ceramic layers that are laminated in a first direction, and
internal electrodes that are disposed between the ceramic layers and include a base metal material as a main component;
a side margin that includes ceramics as a main component and covers the multi-layer unit from a second direction orthogonal to the first direction; and
a bonding unit that is disposed between the ceramic layers and the side margin, the bonding unit having a maximum dimension in the first direction and being made of an oxide including the base metal material in common with the internal electrodes, the maximum dimension being equal to or larger than 50% of an average dimension of the ceramic layers in the first direction.

US Pat. No. 10,971,306

ELECTRONIC COMPONENT HAVING AN EXTERNAL ELECTRODE WITH A CONDUCTIVE RESIN LAYER

TDK CORPORATION, Tokyo (...

1. An electronic component, comprising:an element body of a rectangular parallelepiped shape including a first principal surface arranged to constitute a mounting surface, a second principal surface opposing the first principal surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction; and
two external electrodes respectively disposed at both end portions of the element body in the third direction, one of the external electrodes including:
a conductive resin layer continuously covering one part of the first principal surface, one part of the end surface, and one part of each of the pair of side surfaces; and
a sintered metal layer disposed on the end portion of the element body to be positioned between the element body and the conductive resin layer, the sintered metal layer including an exposed region exposed from the conductive resin layer and a covered region covered with the conductive resin layer, the covered region being closer to the first principal surface than is the exposed region,
wherein for the one external electrode:
the conductive resin layer is disposed on the sintered metal layer and on the one part of the first principal surface, and includes a portion positioned on the first principal surface,
the portion positioned on the first principal surface includes a maximum thickness position,
a first length of the conductive resin layer in the third direction is smaller than a second length of the conductive resin layer in the first direction,
a third length from the maximum thickness position to an end edge of the conductive resin layer, in the third direction is larger than a fourth length from the maximum thickness position to an end edge of the sintered metal layer, in the third direction, and
the end edge of the sintered metal layer on the first principal surface is positioned closer to the end surface than the maximum thickness position, in the third direction.

US Pat. No. 10,971,305

METHOD FOR MANUFACTURING CERAMIC ELECTRONIC COMPONENT AND CERAMIC ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. A method for manufacturing a ceramic electronic component, the method comprising:preparing a ceramic base body containing a titanium-containing metal oxide;
forming a low-resistance section by modifying the metal oxide through irradiation of part of a surface layer portion of the ceramic base body with a pulse laser; and
forming an electrode on the low-resistance section by electroplating,
wherein the irradiation with the pulse laser is performed with a peak power density of 1×106 W/cm2 to 1×109 W/cm2 and a frequency of 500 kHz or less.

US Pat. No. 10,971,304

ELECTRONIC COMPONENT HAVING METAL FRAMES

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a body;
external electrodes respectively disposed on opposing surfaces of the body in a first direction of the body; and
a pair of metal frames connected to the external electrodes, respectively,
wherein
each of the pair of metal frames includes a support portion bonded to the external electrodes, and a mounting portion extending in the first direction from a lower end of the support portion and spaced apart from the body and the external electrodes,
a length of the mounting portion in a second direction perpendicular to the first direction is greater than a maximum length of the support portion in the second direction,
the support portion includes an upper portion and a lower portion, the lower portion being connected to the mounting portion,
the length of the lower portion in the second direction is greater than a length of each of the external electrodes in the second direction, and
a length of the upper portion of the support portion in the second direction is substantially similar to a length of each of the external electrodes in the second direction, and the lower portion of the support portion is formed to have a rectangular shape.

US Pat. No. 10,971,303

MULTILAYER ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component, comprising:a body having a multilayer structure which includes:
a plurality of dielectric layers; and
first and second internal electrodes separated by the plurality of dielectric layers; and
first and second external electrodes disposed on one surface of the body and connected to the first and second internal electrodes, respectively, the first internal electrode and the first external electrode being connected by a first via disposed within the body, the second internal electrode and the second external electrode being connected by a second via disposed within the body, the first internal electrode including first and second through portions, and the second internal electrode including third and fourth through portions, the first via penetrating alternately through the first through portion and the third through portion, the second via penetrating alternately through the second through portion and the fourth through portion, and a lead portion of the first via being connected to one end portion of the first external electrode, and a lead portion of the second via being connected to one end portion of the second external electrode,
wherein the one end portion of the first external electrode and the one end portion of the second external electrode are arranged so that a distance therebetween is equal to or greater than a distance between the first via which is directly connected to the first external electrode and the second via which is directly connected to with the second external electrode.

US Pat. No. 10,971,302

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF THE SAME

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and each of the plurality of internal electrode layers is alternately exposed to two end faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic; and
a pair of external electrodes that are formed on the two end faces;
wherein:
the pair of external electrodes have a structure in which a plated layer is formed on a ground layer of which a main component is a metal or an alloy including at least one of Ni and Cu;
the ground layer includes Mo; and
wherein a relationship “M??0.00002×EM+0.0012” is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [?m] and a ratio of Mo [atm %] to a B site element [atm %] of a main component ceramic in the end margins is M,
wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip,
wherein a concentration of Mo of the ground layer is higher than that of the end margin.

US Pat. No. 10,971,301

CHIP ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A chip electronic component comprising:a chip component body including a mounting surface facing a mounting board;
at least two outer electrodes disposed on outer surfaces of the component body; and
at least two spacers respectively electrically connected to the at least two outer electrodes and at least partially disposed along the mounting surface of the component body; wherein
each of the at least two spacers have a predetermined thickness direction dimension on the mounting surface in a direction perpendicular or substantially perpendicular to the mounting surface;
each of the at least two spacers contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal; and
the intermetallic compound is an intermetallic compound provided by a reaction between the Sn and a Cu—Ni alloy.

US Pat. No. 10,971,300

DOUBLE CONDUCTOR SINGLE PHASE INDUCTIVE POWER TRANSFER TRACKS

Auckland UniServices Limi...

1. An IPT track arrangement comprising:one or more inverters; and
a conductor electrically connected to at least one of the one or more inverters, the conductor including a plurality of loops located adjacent one another and in a plane, and thus the at least one of the one or more inverters are electrically connected to the plurality of loops, and
wherein the conductor overlaps itself at a plurality of crossing points including at least a first crossing point proximate to at least one of the one or more inverters and a second crossing point distal to the at least one of the one or more inverters, the plurality of crossing points arranged so that the polarity in adjacent portions of the loops is the same to reduce opposition of magnetic flux in adjacent conductor portions.

US Pat. No. 10,971,299

BIORTHOGONAL WINDINGS ON TRANSFORMER AND COMMON MODE CHOKE FOR NETWORK PORT

CISCO TECHNOLOGY, INC., ...

1. An apparatus comprising:a plurality of transformers; and
a plurality of common mode chokes, each of the transformers and the common mode chokes comprising a magnetic core and windings wound around the magnetic core at opposite sides thereof;
wherein said plurality of transformers and said plurality of common mode chokes are arranged in an array with the windings on each of the magnetic cores positioned offset from a position of the windings of adjacent magnetic cores in a same plane of the array to reduce crosstalk and improve common mode noise rejection.

US Pat. No. 10,971,298

PASSIVE COMPONENT STRUCTURE

PIN SHINE INDUSTRIAL CO.,...

1. A passive component structure, comprising:an insulating substrate having a centered hollow portion and being provided on a surface with a coil holding zone;
at least one coil being located in the coil holding zone of the insulating substrate and including a winding portion connected to a first terminal and a second terminal;
an insulating encapsulation member covering at least the insulating substrate and the winding portion of the coil; and
a magnetic unit being engaged with the hollow portion of the insulating substrate;
wherein two coils are held in the coil holding zone of the insulating substrate, and the coil holding zone is provided with two spiral receiving recesses, which respectively have an end serving as a first terminal receiving recess; and the winding portions of the two coils being separately received in the two spiral receiving recesses and the first terminals being separately received in the two first terminal receiving recesses; whereby the passive component structure is configured into a transformer;
wherein the insulating substrate is in the form of a round plate and further provided on another opposite surface with two second terminal receiving recesses, the two spiral receiving recesses are respectively provided with a passage section communicating with the insulating substrate, and the insulating encapsulation member is provided with two first and two second notch sections located corresponding to the first and the second terminals, respectively, and includes a through hole located corresponding to the hollow portion of the insulating substrate; and the winding portions of the two coils respectively including a conducting section separately located in the two passage sections, and the second terminals being separately received in the two second terminal receiving recesses and connected to the two conducting sections.

US Pat. No. 10,971,297

PASSIVE COMPONENT AND ELECTRONIC DEVICE

TAIYO YUDEN CO., LTD., T...

1. A passive component being a surface mounting component, comprising: a substrate body having insulation property, whose outer shape is constituted by multiple planar surfaces; an internal conductor embedded in the substrate body; and a pair of external electrodes attached, away from each other, to a same planar surface which is one of the multiple planar surfaces and constitutes a mounting surface of the substrate body, said pair of external electrodes being electrically connected to the internal conductor; wherein each external electrode has a planar principal face substantially parallel with and attached to the mounting surface of the substrate body, and at least one dome-shaped projection that is provided on the planar principal face and bulges in an outward direction from the planar principal face away from the mounting surface of the substrate body, said outward direction being a direction orthogonal to the mounting surface, and wherein an area of a total footprint of the at least one dome-shaped projection on the planar principal face is equal to or smaller than one-ninth but equal to or greater than one-twenty-fifth an area of the planar principal face of the external electrode, which is a coil component wherein the internal conductor is constituted by a coil conductor.

US Pat. No. 10,971,296

COMPACT VERTICAL INDUCTORS EXTENDING IN VERTICAL PLANES

Taiwan Semiconductor Manu...

1. An inductor comprising:a first inductor, the first inductor comprising:
a first spiral pattern about a first axis, the first axis being parallel to a major surface of a substrate, wherein the first spiral pattern comprises:
a first spiral feature in a first plane over a substrate;
a second spiral feature in a second plane over the substrate; and
a third spiral feature in a third plane over the substrate, each of the first plane, the second plane, and the third plane being perpendicular to a major surface of the substrate, wherein each of the first spiral feature and the second spiral feature comprises a first metal line and a second metal line discontinuous from the first metal line, the first metal line extending continuously between adjacent spiral features of the first spiral feature, the second spiral feature, and the third spiral feature, the first metal line forming a part of each of adjacent spiral features, wherein a gap in the first plane between the first metal line and the second metal line is in a different location than a gap in the second plane between the first metal line and the second metal line such that a length of the first metal line in the first plane is different than a length of the first metal line in the second plane, wherein the first metal line and the second metal line in each of the first spiral feature, the second spiral feature, and the third spiral feature are in a same metallization layer; and
a first port extending along a line parallel to the first axis;
a second inductor, the second inductor comprising:
a second spiral pattern about a second axis, the second axis being parallel to the major surface of the substrate, the first axis not intersecting the second inductor; and
a second port extending along a line parallel to the second axis; and
a conductive tab electrically coupling the first inductor to the second inductor.

US Pat. No. 10,971,295

TWO PART CLAMPING AND SUSPENSION MECHANISM FOR A SPLIT TOROIDAL CURRENT TRANSFORMER

Schweitzer Engineering La...

1. A current transformer (CT), comprising:a split core comprising a first core half having a first plurality of faces and a second core half having a second plurality of faces, wherein each face of the first core half is configured to contact a corresponding face of the second core half to allow magnetic flux to flow through the split core to induce current on windings of the CT;
a first housing configured to house the first core half;
a second housing rotatably coupled to the first housing and configured to house the second core half, wherein the first housing and the second housing, when rotated to an open position, form an opening to allow a conductor to be inserted between the first core half and the second core half, and when rotated to a closed position, close the opening between the first core half and the second core half to form an annulus around the conductor;
a biasing element configured to bias the second core half towards the first core half to ensure that each face of the second core half contacts the corresponding face of the first core half, wherein the biasing element is configured to position each face of the first plurality of faces to be parallel to the corresponding face of the second plurality of faces to account for differences in surfaces between the first plurality of faces and the second plurality of faces
a first overmold configured to secure windings of the CT to the first core half; and
a second overmold configured to secure windings of the CT to the second core half, wherein the second overmold comprises a protrusion to support the second overmold on the biasing element and a boss configured to engage an axial opening of the biasing element to stabilize the overmold on the biasing element.

US Pat. No. 10,971,294

FRACTAL SWITCHING SYSTEMS AND RELATED ELECTROMECHANICAL DEVICES

Fractal Antenna Systems, ...

1. A method of actuation using a fractal actuator, the method comprising:providing a core including a fractal surface, wherein the core has a longitudinal axis and the fractal surface has a fractal perimeter in a radial direction relative to the longitudinal axis; and
disposing a plurality of windings around the core, wherein the plurality of windings is configured to receive and conduct an electric current;
wherein the core is movable with respect to the plurality of windings and in response to a current passing through the windings;
applying an electric current to the plurality of windings and thereby effecting movement of the core with respect to the plurality of windings.

US Pat. No. 10,971,293

SPIN-ORBIT-TORQUE MAGNETIZATION ROTATIONAL ELEMENT, SPIN-ORBIT-TORQUE MAGNETORESISTANCE EFFECT ELEMENT, AND SPIN-ORBIT-TORQUE MAGNETIZATION ROTATIONAL ELEMENT MANUFACTURING METHOD

TDK CORPORATION, Tokyo (...

1. A spin-orbit-torque magnetization rotational element comprising:a spin-orbit torque wiring layer which extends in an X direction and comprises nonmagnetic material; and
a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer,
wherein:
the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and
an easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on the plane in which the spin-orbit torque wiring layer extends.

US Pat. No. 10,971,292

AXISYMMETRIC ELECTROPERMANENT MAGNETS

University of Florida Res...

1. A switchable magnet, comprising:a magnet assembly,
wherein the magnet assembly comprises:
at least one fixed magnet having a first direction of magnetization from a south end of the at least one fixed magnet to a north end of the at least one fixed magnet,
wherein the first direction of magnetization is in a first direction;
at least one switching magnet having a second direction of magnetization from a south end of the at least one switching magnet to a north end of the at least one switching magnet,
wherein the at least one fixed magnet and the at least one switching magnet are permanent magnets, and
wherein:
(i) one or more fixed magnets of the at least one fixed magnet are positioned at least partially within a corresponding one or more bores through a first switching magnet of the at least one switching magnet; or
(ii) one or more switchable magnets of the at least one switching magnet are positioned at least partially within a corresponding one or more bores through a first fixed magnet of the at least one fixed magnet,
wherein:
(i) when the second direction of magnetization is in the first direction and an on-to-off switching magnetic field is positioned with respect to the magnet assembly for a first period of time, the on-to-off switching magnetic field switches the second direction of magnetization from the first direction to a second direction, where the second direction is an opposite to the first direction, and does not switch the first direction of magnetization; and
(ii) when the second direction of magnetization is in the second direction and an off-to-on switching magnetic field, where the off-to-on switching magnetic field is in an opposite direction to the on-to-off switching magnetic field, is positioned with respect to the magnet assembly for a second period of time, the off-to-on switching magnetic field switches the second direction of magnetization from the second direction to the first direction, and does not switch the first direction of magnetization.

US Pat. No. 10,971,291

SYSTEM AND METHOD FOR OPERATING A BULK SUPERCONDUCTOR DEVICE

THE BOEING COMPANY, Chic...

1. A bulk superconductor device comprising:a chamber;
a bulk superconductor disposed within the chamber, the bulk superconductor having a first surface, a second surface opposite the first surface, at least one side surface that extends from the first surface to the second surface, and a cavity formed in the bulk superconductor that extends from a center of the first surface toward the second surface;
at least one coil that surrounds the at least one side surface; and
a heating element coupled to the bulk superconductor, wherein a first portion of the heating element is positioned in the cavity, wherein a second portion of the heating element is coupled to the first surface, and wherein the second portion surrounds an opening of the cavity.

US Pat. No. 10,971,290

MAGNETIC ASSEMBLY AND POWER SUPPLY SYSTEM WITH SAME

DELTA ELECTRONICS (SHANGH...

1. A power supply system comprising plural converters, wherein the plural converters are connected with each other in parallel, and the plural converters receive an input voltage and convert the input voltage into an output voltage, wherein the plural converters comprise a magnetic assembly, and the magnetic assembly comprises:plural first magnetic cores stacked over each other from bottom to top, wherein each of the plural first magnetic cores comprises plural legs and a first connection part, and the first connection part is connected with first terminals of the plural legs, wherein the first connection part of the first magnetic core at an upper position is located adjacent to second terminals of the plural legs of the adjacent first magnetic core at a lower position;
plural coil windings, wherein each coil winding is wound around at least one leg of the plural legs of the corresponding first magnetic core so as to form a magnetic element of the corresponding converter; and
a second magnetic core stacked over the plural first magnetic cores, wherein the second magnetic core is located adjacent to the second terminals of the legs of the topmost first magnetic core;
wherein electric currents flowing through the plural coil windings are in the same direction, and magnetic fluxes through the first connection part of the first magnetic core at the upper position, which correspond to two coil windings of two adjacent first magnetic cores, are in opposite directions.

US Pat. No. 10,971,289

COMPOSITE R-FE-B SERIES RARE EARTH SINTERED MAGNET COMPRISING PR AND W

XIAMEN TUNGSTEN CO., LTD....

1. A composite R—Fe—B based rare-earth sintered magnet comprising Pr and W, wherein:the composite R—Fe—B based rare-earth sintered magnet comprises an R2Fe14B main phase,
R is a rare-earth element comprising at least Pr,
raw material components of the composite R—Fe—B based rare-earth sintered magnet comprise more than or equal to 2 wt % of Pr, 0.008 wt % to less than 0.03 wt % of W, and 0.8 wt % to 1.3 wt % of B, and
the composite R—Fe—B based rare-earth sintered magnet is made through a process comprising:
preparing molten liquid of the raw material components into a quenched alloy;
grinding the quenched alloy into powder;
obtaining a shaped body from the powder by using a magnetic field; and
sintering the shaped body.

US Pat. No. 10,971,287

COMPOSITE CIRCUIT PROTECTION DEVICE

FUZETEC TECHNOLOGY CO., L...

1. A composite circuit protection device, comprising:a positive temperature coefficient (PTC) component formed with a first hole, the PTC component including:
a PTC layer having two opposite PTC surfaces, and
first and second electrode layers, each having an electrode surface connecting to a respective one of said two opposite PTC surfaces of said PTC layer, said first hole being formed in said PTC layer;
a voltage-dependent resistor formed with a second hole, the voltage-dependent resistor including:
a voltage-dependent resistor layer having two opposite resistor surfaces,
a third electrode layer having an electrode surface disposed between and connecting to one of said two opposite resistor surfaces of said voltage-dependent resistor layer and said second electrode layer of said PTC component, and
a fourth electrode layer having an electrode surface connecting to the other one of said two opposite resistor surfaces of said voltage-dependent resistor layer;
a first conductive lead that is bonded to said first electrode layer of said PTC component; and
a second conductive lead that is bonded to one of said third and fourth electrode layers of said voltage-dependent resistor,
wherein said electrode surface of each of said first and second electrode layers has an area that is smaller than an area of a respective one of said PTC surfaces, or said electrode surface of each of said third and fourth electrode layers has an area that is smaller than an area of a respective one of said resistor surfaces.

US Pat. No. 10,971,286

THERMAL-INSULATED MULTI-WALLED PIPE FOR SUPERCONDUCTING POWER TRANSMISSION

JFE STEEL CORPORATION, T...

1. A thermal-insulated multi-walled pipe for superconducting power transmission, comprising:a superconducting cable; and
a multi-walled pipe that houses the superconducting cable,
wherein the multi-walled pipe is composed of a plurality of straight pipes,
at least one of the plurality of straight pipes has, at a surface thereof, a coating layer containing a metal powder, and
a content of the metal powder in the coating layer is 35 mass % to 98 mass %.

US Pat. No. 10,971,285

THREE-WIRE COMMUNICATION CABLE

GENERAL CABLE TECHNOLOGIE...

1. A three-wire communication cable comprising:three insulated wires twisted together at a pitch rate, each of the three insulated wires comprising a conductive wire and an insulation layer, and wherein all of the three insulated wires are in contact with each other; and
a jacket layer surrounding the three insulated wires, the jacket layer comprising one or more of thermoplastic elastic (“TPE”) and thermoplastic polyurethane (“TPU”);
wherein the pitch rate comprises a pitch of about 8 mm to about 30 mm.

US Pat. No. 10,971,284

POWER AND COMMUNICATIONS CABLE FOR COILED TUBING OPERATIONS

Halliburton Energy Servic...

1. A system, comprising:a coiled tubing locatable in a wellbore;
a power and communications cable positioned along the coiled tubing and comprising:
an electromagnetic waveguide;
an inner metallic tubular surrounding the electromagnetic waveguide;
an electrically conductive material surrounding the inner metallic tubular;
an electrically insulating material surrounding the electrically conductive material; and
an outer metallic tubular resistant to corrosion and abrasion and surrounding the electrically insulating material;
an electrical device locatable in the wellbore and coupled to the power and communications cable; and
a control unit coupled to the power and communications cable and operable to supply power to and communicate with the electrical device via the inner metallic tubular, the electrically conductive material, and the outer metallic tubular.

US Pat. No. 10,971,283

FLEX FLAT CABLE STRUCTURE AND FIXING STRUCTURE OF CABLE CONNECTOR AND FLEX FLAT CABLE

Energy Full Electronics C...

1. A flex flat cable (FFC) electrical connector fix structure, comprising:an electrical connector, comprising:
a housing;
a printed circuit board (PCB), comprising a plurality of conductive portions and a plurality of connecting portions, and the plurality of conductive portions being electrically connected to the plurality of corresponding connecting portions respectively;
a plurality of terminals, one end of the plurality of terminals being connected to the plurality of connecting portions, wherein the plurality of terminals comprise a plurality of first terminals arranged in a first row and a plurality of second terminals arranged in a second row, and a number of the first terminals is different from a number of the second terminals; and
a shell, assembled onto the housing; and
an FFC structure, comprising:
a plurality of metallic transmission lines, being arranged parallel, and comprising one or more power line and a plurality of signal lines; the power line being configured to transmit power; the plurality of signal lines being configured to transmit a data signal;
a plurality of first insulating jackets, each of the plurality of first insulating jackets enclosing one of the plurality of metallic transmission lines;
a second insulating jacket, surrounding the plurality of first insulating jackets;
a third insulating jacket, enclosing the plurality of first insulating jackets without any gap, and the second insulating jacket enclosing the third insulating jacket; and
a shield layer, configured to isolate the second insulating jacket from the third insulating jacket, comprising:
an insulating film, comprising a first side and a second side, and the first side and the second side being on opposite sides of the insulating film;
a first block layer, adhering to the first side of the insulating film; and
a second block layer, adhering to and contacting the first block layer,
wherein the first block layer and the second block layer are made of different materials,
wherein all of the plurality of metallic transmission wires are respectively connected to all of the plurality of conductive portions on one surface of the PCB.

US Pat. No. 10,971,282

FLEX FLAT CABLE STRUCTURE AND FLEX FLAT CABLE ELECTRICAL CONNECTOR FIX STRUCTURE

Energy Full Electronics C...

1. A flex flat cable (FFC) electrical connector fix structure, comprising:an electrical connector, comprising:
a housing;
a printed circuit board (PCB), comprising a plurality of conductive portions and a plurality of connecting portions, and the plurality of conductive portions being electrically connected to the plurality of corresponding connecting portions respectively; and
a plurality of terminals, one end of the plurality of terminals correspondingly connected to the plurality of connecting portions, wherein the plurality of terminals comprise a plurality of first terminals arranged in a first row and a plurality of second terminals arranged in a second row, and a number of the first terminals is different from a number of the second terminals; and
an FFC structure, comprising:
a plurality of metallic transmission wires, arranged parallel, comprising one or more power wires and a plurality of signal wires; the power wire being configured to transmit power; the plurality of signal wires being configured to transmit a data signal;
a plurality of first insulating jackets, and each of the plurality of first insulating jackets encloses one of the plurality of metallic transmission wires;
a second insulating jacket, surrounding the plurality of first insulating jackets; an embossment pattern being arranged directly on an external surface of the second insulating jacket; the embossment pattern comprising a plurality of meander lines in a top-view direction and in an extending direction for the plurality of metallic transmission wires; the plurality of meander lines being not arranged parallel; and
wherein all of the conductive portions are on one surface of the PCB, and the plurality of metallic transmission wires are connected to the plurality of conductive portions.

US Pat. No. 10,971,281

CONDUCTING POLYMER COMPOSITE CONTAINING ULTRA-LOW LOADING OF GRAPHENE

Global Graphene Group, In...

1. A polymer matrix composite containing graphene sheets homogeneously dispersed in a polymer matrix wherein said polymer matrix composite exhibits a percolation threshold from 0.0001% to 0.1% by volume of graphene sheets to form a 3D network of interconnected graphene sheets or network of electron-conducting pathways, wherein said polymer matrix exhibits an impact strength Ep and said polymer matrix composite exhibits an impact strength Ec, and wherein Ec/Ep is from 1.2 to 20.

US Pat. No. 10,971,279

MANUFACTURING METHOD OF HIGH THERMAL CONDUCTIVE HYBRID FILM

NATIONAL TSING HUA UNIVER...

1. A manufacturing method of a high thermal conductive hybrid film, and the manufacturing method comprising:preparing a graphene oxide solution, wherein the graphene oxide solution comprises a plurality of graphene oxides;
preparing a nano-particle solution, wherein the nano-particle solution comprises a plurality of nano initial hybrid structures, and each of the nano initial hybrid structures comprises a nanodiamond and a polydopamine layer coating the nanodiamond, the nanodiamonds are dispersed in a tris-hydrochloride buffer to disperse the nanodiamonds evenly and then mixed with a dopamine hydrochloride to form the nano initial hybrid structures, and then the nano initial hybrid structures are dispersed in an ammonia to form the nano-particle solution;
providing a mixing process, wherein the mixing process is for mixing the graphene oxide solution and the nano-particle solution to obtain a mixing solution;
providing a preliminary-film forming process, wherein the preliminary-film forming process is for filtrating the mixing solution and then remaining a mixture of the graphene oxides and the nano initial hybrid structures to form a preliminary film; and
providing a heating process, wherein the heating process is for heating the preliminary-film to reduce the graphene oxides as a plurality of reduced graphene oxides and convert the polydopamine layers into a plurality of carbon layers, so as to convert the nano initial hybrid structures into a plurality of nano hybrid structures;
whereby, the high thermal conductive hybrid film is formed.

US Pat. No. 10,971,278

SUPERCONDUCTING WIRE AND SUPERCONDUCTING COIL

MITSUBISHI MATERIALS CORP...

1. A superconducting wire comprising:a strand including a superconducting material; and
a stabilizer material for superconductor arranged in contact with the strand, wherein
the stabilizer material for superconductor includes a copper material which contains one or more of additive elements selected from the group consisting of Ca, Sr, Ba, and rare earth elements (RE) in a total amount of 3 ppm by mass or more and 400 ppm by mass or less, with a remainder being Cu and unavoidable impurities,
a total concentration of the unavoidable impurities is 5 ppm by mass or more and 100 ppm by mass or less, said unavoidable impurities not including O, H, C, N, and S, which are gas components, and
one or more compounds selected from the group consisting of CaS, CaSO4, SrS, SrSO4, BaS, BaSO4, (RE)S, and (RE)2SO2 are present in a matrix of the copper material.

US Pat. No. 10,971,277

METHODS TO INCORPORATE SILVER NANOWIRE-BASED TRANSPARENT CONDUCTORS IN ELECTRONIC DEVICES

CAMBRIOS FILM SOLUTIONS C...

1. An optical stack, comprising: a substrate;a nanostructure layer having a plurality of silver nanostructures; one or more photo-stabilizers comprising benzothiazole; an edge seal laterally co-planar with the nanostructure layer; and a barrier film, wherein: the nanostructure layer is disposed between the substrate and the barrier film, a layer comprising the benzothiazole is formed according to a method comprising: applying a solution comprising the benzothiazole to the layer; at least partially drying the solution on the layer; and rinsing the layer using methanol after the solution is at least partially dry, and the layer comprises at least one of the nanostructure layer, the barrier film, or any other layer of the optical stack in which the one or more photo-stabilizers are incorporated.

US Pat. No. 10,971,276

COMPOSITION FOR REMOVING RADIONUCLIDE AND METHOD FOR REMOVING RADIONUCLIDE USING THE SAME

KOREA ATOMIC ENERGY RESEA...

1. A method for removing a radionuclide, the method comprising:(a) preparing a first aqueous solution containing a first polymer comprising a hydroxy group;
(b) preparing a second aqueous solution containing a second polymer into which a boronic acid group is introduced as a functional group via a covalent bond;
(c) forming a reversibly cross-linked hydrogel in which the radionuclide is adsorbed by spraying or applying each of the first solution and the second solution onto a radionuclide-contaminated surface, and then reversibly cross-linking the first polymer and the second polymer to each other via a dehydration condensation reaction under a pH condition of 5 to 12, wherein the boronic acid group is in an anionic state, and wherein a borate-ester bond is formed between the first polymer and the second polymer from the hydroxy group and the boronic acid group; and
(d) selectively dissolving only the hydrogel by disintegrating the cross-linking via an immersion of the hydrogel in which the radionuclide is adsorbed in water,
wherein an adsorbent for removing the radionuclide is further contained in the first solution or the second solution,
wherein in step (c), at a frequency of 100 rad/s, the hydrogel in which the radionuclide is adsorbed has a storage modulus of 2,000 Pa to 10,000 Pa and a loss modulus of 100 Pa to 5,000 Pa.

US Pat. No. 10,971,275

PASSIVE ELECTRICAL COMPONENT FOR SAFETY SYSTEM SHUTDOWN USING AMPERE'S LAW

GE-HITACHI NUCLEAR ENERGY...

1. An electro-technical device, comprising:a circuit including a coil connected to a voltage source for receiving a current therefrom and connected to an output device;
the circuit including a breakable junction;
the circuit including a photodiode for receiving a light signal from a fiber optic cable receiving a light signal from a sensor; and
a permanent magnet having a pole end opposing a common pole end of the coil, wherein when the coil receives an increased current from the photodiode, the coil creates an magnetic flux that repels against the common pole of the permanent magnet in order to cause the breakable junction to break and disrupt a connection between the voltage source and the output device.

US Pat. No. 10,971,274

TOROIDAL FIELD COIL ARRANGEMENT WITH CENTRAL COLUMN HAVING EXFOLIATED HTS TAPES AND RETURN LIMBS HAVING SUBSTRATED HTS TAPES

Tokamak Energy Ltd., Oxf...

1. A toroidal field coil for use in a spherical tokamak, the toroidal field coil comprising a central column and a plurality of return limbs,the central column comprising a plurality of exfoliated high temperature superconductor (HTS) tapes;
the return limbs comprising a plurality of substrated HTS tapes;
wherein:
each exfoliated HTS tape comprises a rare earth barium copper oxide (ReBCO) layer bonded to respective metal interface layers on each side of the ReBCO layer, each metal interface layer being bonded to a metal stabiliser layer, and
each substrated HTS tape comprises a ReBCO layer bonded on one side to a metal interface layer and on the other side to an oxide buffer stack, the metal interface layer being bonded to a metal stabiliser layer and the oxide buffer stack being bonded to a substrate.

US Pat. No. 10,971,273

IDENTIFICATION OF CO-LOCATED ARTIFACTS IN COGNITIVELY ANALYZED CORPORA

International Business Ma...

1. A method comprising:generating a plurality of vector representations by processing a plurality of documents in a corpus using a passage encoder, wherein the plurality of vector representations correspond to respective documents of the plurality of documents;
identifying one or more concepts in the plurality of documents by processing the plurality of documents with the passage encoder, wherein the one or more concepts are assigned respective importance scores by the passage encoder;
receiving a selection of a first target document and a second target document from the plurality of documents to be used to generate a sub-corpus of documents from the corpus;
generating an aggregate vector representation for the first and second target documents by averaging vector representations for the first and second target documents;
generating the sub-corpus of documents from the corpus by computing a similarity measure between the aggregate vector representation of the first and second target documents and vector representations of each other document in the plurality of documents in the corpus;
identifying a first plurality of concepts present in the sub-corpus;
generating an overall importance score for a first concept of the first plurality of concepts indicating how important the first concept is with respect to the generated sub-corpus, by:
identifying a first importance score of the first concept with respect to a first document in the sub-corpus;
identifying a second importance score of the first concept with respect to a second document in the sub-corpus; and
generating the overall importance score by averaging the first and second importance scores; and
providing an indication of the generated overall importance score.

US Pat. No. 10,971,272

METHOD AND APPARATUS FOR EVALUATING A HEART PATIENT

1. A method of enabling a physician to conduct a clinical evaluation of a cardiology patient comprising steps of:(a) providing a computer having a first and second data bases, wherein the first database having patient data including a plurality of historical studies containing values of selectable patient parameters for the patient, wherein the second database having a first set of cardiology guidelines;
(b) providing a user interface
connected to the computer
that includes a display screen, and the computer receiving test data from testing of a patient for one or more cardiac modalities;
(c) simultaneously displaying
multiple selectable icons on the display screen,
each icon of the multiple selectable icons being a pictorial anatomical designation of a different anatomical portion of a human heart;
(d) enabling the physician to select one of the icons;
(e) the selection of an icon in step “c” generating an enlarged version of the selected pictorial anatomical icon to be displayed on the display screen, the enlarged pictorial anatomical designation itself containing a plurality of additionally selectable anatomical portions, enabling the physician to select one of the plurality of additionally selectable anatomical portions, the selection of one of these additionally selectable anatomical portions generating a display on the display screen
of patient data that corresponds
to the portion of the patient's heart that is represented by the particular additionally selected anatomical portion; and
(f) wherein the patient data of step “e” includes
optional selectable patient parameters, and wherein a selection of one of the optional selectable patient parameters causes a graphical comparison to be displayed on the display screen comparing a current value of the selected one of the optional selected patient parameters to a plurality of past values of the selected one of the optional selected patient parameters obtained from the plurality of historical studies; and
(g) based at least in part on the test data received in step “b”,
the computer determining a second set of cardiology guidelines which are applicable to the patient wherein the second set cardiology guidelines are a subset of the first set of cardiology guidelines, and providing an option to the physician of displaying on the display screen a text of one or more cardiology guidelines contained in the second set of cardiology guidelines;
(h) based on the second set of cardiology guidelines of step “g”, the computer requesting a guideline specific input from the physician;
(i) based on the input from the physician in step “h”, the computer determining a third set of cardiology guidelines wherein the third set is a subset of the second set of cardiology guidelines;
(j) wherein report findings are automatically generated
as part of a report containing the patient data and the cardiology guidelines
relative to the portion of the heart selected in step “e” and
responsive to a selection of the parameters of step “f” and the input by the physician in steps “d” and “i”.

US Pat. No. 10,971,271

METHOD AND SYSTEM FOR PERSONALIZED BLOOD FLOW MODELING BASED ON WEARABLE SENSOR NETWORKS

Siemens Healthcare GmbH, ...

1. A method for simulating blood flow to estimate one or more hemodynamic measures of interest for a patient, comprising:generating a patient-specific anatomical model of vessels of a patient based on patient data;
receiving one or more continuous cardiovascular measurements of the patient from a wearable sensor network on the patient;
personalizing a computational blood flow model for simulating blood flow in the patient-specific anatomical model of the vessels of the patient by personalizing arterial wall properties, an inlet boundary condition, and outlet boundary conditions of the computational blood flow model based on the one or more continuous cardiovascular measurements from the wearable sensor network, wherein the inlet boundary condition is personalized by estimating a continuous cardiac output based on the one or more continuous cardiovascular measurements and scaling a population-averaged aortic inlet profile using the estimated continuous cardiac output to generate a personalized time-varying flow rate profile at an aortic inlet;
simulating blood flow and pressure in the patient-specific anatomical model of the vessels of the patient using the personalized computational blood flow model; and
computing one or more hemodynamic measures of interest for the patient based on the simulated blood flow and pressure.

US Pat. No. 10,971,270

TREATMENT RECOMMENDATION DECISION SUPPORT USING COMMERCIAL TRANSACTIONS

International Business Ma...

1. A method, in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions executed by the at least one processor to cause the at least one processor to implement a cognitive medical decision support system, wherein the cognitive medical decision support system operates to:configure and train a lifestyle behavior pattern analyzer by performing a machine learning process on a first set of commercial transaction data to learn weightings of lifestyle behavior factors present in the commercial transaction data relative to one another, to categorize a lifestyle behavior according to a predetermined set of lifestyle behavior pattern categories based on a pattern of categories of products or services identified by the commercial transaction data;
analyze, by artificial intelligence logic of the cognitive medical decision support system, a set of commercial transaction data structures defining a second set of commercial transactions executed by a patient to identify commercial transaction data elements corresponding to at least one of products or services purchased during each commercial transaction;
categorize, by the cognitive medical decision support system, the products or services corresponding to the commercial transaction data elements into one or more predefined categories of types of products or services, to generate a set of product/service categories for the set of commercial transaction data structures;
determine, by the artificial intelligence logic of the cognitive medical decision support system, whether the set of product/service categories comprise one or more predefined conflicting categories that conflict with a current medical treatment of the patient;
generate, in response to identifying the conflict, by the artificial intelligence logic, a prediction of an impact of the conflict on at least one of a specific medical condition of the patient or a specific previously prescribed treatment of the patient, at least by processing the set of commercial transaction data structures by the configured and trained lifestyle behavior pattern analyzer to generate one or more categories of lifestyle behavior based on at least one pattern of categories of the products or services in the set of product/service categories and predicting the impact based on the one or more categories of lifestyle behavior; and
output, by the cognitive medical decision support system, a notification indicating the one or more products or services that have been categorized into one or more predefined conflicting categories and the prediction of the impact of the conflict.

US Pat. No. 10,971,269

TREATMENT RECOMMENDATION DECISION SUPPORT USING COMMERCIAL TRANSACTIONS

International Business Ma...

1. A method, in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions executed by the at least one processor to cause the at least one processor to implement a cognitive medical decision support system, wherein the cognitive medical decision support system operates to:configure and train each of a plurality of lifestyle behavior pattern analyzers, by performing a machine learning process on a first set of commercial transaction data to learn weightings of lifestyle behavior factors present in the commercial transaction data relative to one another, to categorize a lifestyle behavior according to a predetermined set of lifestyle behavior pattern categories, and wherein each lifestyle data pattern analyzer is configured and trained by the machine learning process to identify patterns of data in commercial transactions indicative of lifestyle behavior patterns for a corresponding different category of commercial transaction data elements in commercial transaction data;
analyze, by artificial intelligence logic of the cognitive medical decision support system, a set of commercial transaction data structures defining a second set of commercial transactions executed by a patient to identify commercial transaction data elements corresponding to at least one of products or services purchased during each commercial transaction, or an activity, associated with the commercial transaction, engaged in by the patient;
determine, by the configured and trained plurality of lifestyle behavior pattern analyzers, a lifestyle behavior pattern of the patient based on detected patterns of commercial transaction data elements corresponding to at least one of products, services, or activities associated with the commercial transactions in the second set of commercial transactions;
evaluate, by the artificial intelligence logic of the cognitive medical decision support system, an impact of the lifestyle behavior pattern on at least one of a specific medical condition of the patient or a specific previously prescribed treatment of the patient, wherein the evaluation comprises processing the lifestyle behavior pattern of the patient, determined by the plurality of lifestyle behavior pattern analyzers, and patient electronic medical record data indicating at least one of the specific medical condition or specific previously prescribed medical treatment, through at least one cognitive analysis pipeline implementing the artificial intelligence logic of the cognitive medical decision support system; and
output, by the cognitive medical decision support system, a notification indicating the impact of the lifestyle behavior pattern.

US Pat. No. 10,971,268

METHOD OF PROVIDING INFORMATION FOR THE DIAGNOSIS OF PANCREATIC CANCER USING BAYESIAN NETWORK BASED ON ARTIFICIAL INTELLIGENCE, COMPUTER PROGRAM, AND COMPUTER-READABLE RECORDING MEDIA USING THE SAME

1. A method of providing information for a diagnosis of pancreatic cancer using Bayesian network based on artificial intelligence, the method comprising:generating a statistical report by learning medical information of a patient with pancreatic cancer, wherein the medical information is configured to have a probability of developing pancreatic cancer for at least one item of, abdominal pain, nausea and vomiting, weight loss, jaundice, acute diabetes, CA 19-9 cancer marker, smoking status, family history, male and female, which is statistical data obtained through artificial intelligence or machine learning;
constructing a conditional probability table using statistics for each symptom of an actual pancreatic cancer patient;
constructing a Bayesian network using the conditional probability table constructed using the statistics for each symptom;
applying a Bayesian conditional probability to the Bayesian network; and
deriving a probability of getting pancreatic cancer when a specific symptom is present from the pancreatic cancer patient,
wherein the Bayesian network is a graph which expresses knowledge of a specific situation in a form of cause and effect, displaying what corresponds to a proposition as an elliptical node, gives a name representing the proposition, and is a directed acyclic graph wherein an edge is drawn from a proposition being the cause to a proposition being the effect so both the cause and the effect are connected in only one direction.

US Pat. No. 10,971,267

SYSTEMS AND METHODS FOR AGGREGATION OF AUTOMATICALLY GENERATED LABORATORY TEST RESULTS

Medial Research Ltd., Kf...

1. A system for providing a client terminal with a numerical value of at least one target pathological indication in response to an indication of current laboratory test results of a patient, comprising:a non-transitory memory having stored thereon a code for execution by at least one hardware processor of a computing device associated with a database storing a plurality of classifiers and associated with at least one automated laboratory testing device via a network, the code comprising:
code for receiving an indication of values of a plurality of current laboratory test results calculated based on an automated analysis of at least one laboratory sample collected from a target individual;
code for receiving at least one additional patient parameter;
code for selecting at least one classifier from the plurality of classifiers according to at least one target pathological indication obtainable from the indication of values of the plurality of current laboratory test results,
wherein each of the plurality of classifiers is trained on a respective training dataset to output a respective different pathological indication, the respective training dataset including, for each of a plurality of sample individuals, a plurality of historical laboratory test results, the at least one additional patient parameter, and a corresponding numerical value of the respective pathological indication denoting an aggregation of the historical laboratory test results indicative of a state of the respective sample individual;
code for determining at least one additional laboratory test according to tests missing from the plurality of current laboratory tests for input into the selected at least one classifier;
code for automatically sending a control signals to the at least one second automatic laboratory testing device to perform the at least one additional laboratory test selected from a group consisting of: liver function test, renal function test, diabetic associated test, complete blood count (CBC), blood coagulation test, urinalysis, biochemistry test, electrolyte test, blood gas test, blood glucose level, and cell analysis, the at least one additional test performed on blood and/or urine comprising at least a portion of the at least one laboratory sample collected from the target individual to obtain a second indication of a second value of the at least one additional laboratory test, when the determining indicates that the at least one additional laboratory test is missing from the plurality of current laboratory tests and that the at least one additional laboratory test is for input into the selected at least one classifier;
code for evaluating a numerical value of a plurality of candidate numerical values of the at least one target pathological indication by applying the selected at least one classifier to the indication of values of the plurality of current laboratory test results, the second indication of the second value of the at least one additional laboratory test result, and to the at least one additional patient parameter,
wherein the numerical value of the target pathological indication is indicative of a state of the patient, and denotes an aggregation of the plurality of current laboratory test results, the second indication of the second value of the at least one additional laboratory test result, and the at least one additional patient parameter; and
code for outputting the numerical value of the at least one target pathological indication for presentation by the client terminal.

US Pat. No. 10,971,266

TRANSFER OF BREATHING ASSISTANCE APPARATUS DATA

1. A method of providing access to data from a medical apparatus for review and storage on a computer system, wherein the medical apparatus generates a barcode, the barcode encoding a URL comprising an access address for a computer system and patient-specific data from the medical apparatus as a sub-path appended to the access address, wherein the sub path was updated based on the use of the medical apparatus by the patient over a period of time, wherein a mobile telecommunications device extracts the URL from the barcode, wherein the mobile telecommunications device sends a request for access to the computer system, the request comprising the URL, the method comprising:executed at the computer system, receiving the request for access from the mobile telecommunication device,
in a pre-processor of the computer system, intercepting the request comprising the URL rather than using the sub path of the URL to return a static web page to the mobile telecommunications device;
in the pre-processor of the computer system, extracting the sub path from the URL;
in the pre-processor of the computer system, extracting the patient-specific data from the sub path;
in the pre-processor of the computer system, storing the extracted patient-specific data on a database of the computer system;
in the pre-processor of the computer system, dynamically composing a web page from the patient-specific extracted data; and
returning the dynamically composed web page to the mobile telecommunications device as though the mobile telecommunications device has accessed a static web page.

US Pat. No. 10,971,265

TAGS FOR AUTOMATED LOCATION AND MONITORING OF MOVEABLE OBJECTS AND RELATED SYSTEMS

TeleTracking Technologies...

1. A method, comprising:transmitting, from a hub, a request for information stored by at least one receiver, the request for information requesting information related to at least one tag affixed to a moveable object;
receiving, at the hub from the at least one receiver, (i) presence information from the at least one tag affixed to a moveable object and (ii) identifying information of the at least one tag identifying the at least one tag and the moveable object corresponding to the at least one tag, wherein the presence information is received by the at least one receiver when the at least one tag is within a defined perimeter of the at least one receiver;
receiving, at the hub from at least one receiver, use state information identifying a current use state of the moveable object received from the at least one tag; and
storing, within a database associated with the hub, the presence information, identifying information, and use state information for the at least one tag and the moveable object, wherein the storing comprises updating a status of the at least one tag and the moveable object within the database with the presence information, identifying information, and use state information.

US Pat. No. 10,971,264

PATIENT TRACKING AND DYNAMIC UPDATING OF PATIENT PROFILE

INTRADO CORPORATION, Oma...

1. A method comprising:retrieving a monitoring schedule associated with a predefined location from a memory, the schedule associated with sensor data being received from a plurality of sensors and comprising times for performing at least one of meal delivery, medication administration, blood draw, sleep, or a medical procedure;
retrieving patient preferences associated with a patient from the memory;
applying one or more patient preferences to the monitoring schedule;
receiving sensor data from the plurality of sensors at a sensor data receive time, the sensor data including information indicating that the plurality of sensors were triggered at the predefined location;
receiving information regarding a time that the sensor data is received from each of the plurality of sensors;
comparing the sensor data to the monitoring schedule;
identifying a time discrepancy between the monitoring schedule and the sensor data receive time;
identifying time gaps between the sensor data received from each of the plurality of sensors;
creating a sensor trigger pattern identifying a behavior of the patient at the predefined location based on the identified time gaps and on information from the plurality of sensors identifying the predefined location; and
automatically creating a new monitoring schedule for the predefined location based on the new sensor trigger pattern associated with the predefined location.

US Pat. No. 10,971,263

METHODS AND APPARATUS FOR RECORDING ANONYMIZED VOLUMETRIC DATA FROM MEDICAL IMAGE VISUALIZATION SOFTWARE

General Electric Company,...

1. A method comprising:anonymizing, by executing an instruction with a processor, a medical image outside of a region of interest based on an extraction parameter by degrading the medical image outside a region corresponding to the region of interest and maintaining a resolution of the medical image inside the region corresponding to the region of interest, wherein the extraction parameter is generated based on at least an image capture parameter; and
generating, by executing an instruction with the processor, a compressed local archive based on the anonymized medical image.

US Pat. No. 10,971,262

PERSONALIZED TRAINING BASED ON PLANNED COURSE AND PERSONAL ASSESSMENT

International Business Ma...

1. A method, in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions executed by the at least one processor to cause the at least one processor to implement a cognitive computing system, the method comprising:receiving, by the cognitive computing system, a request, from a client computing device associated with a user, to generate a personalized training regimen for a specified athletic event occurring at a future time;
extracting, by the cognitive computing system, event information comprising one or more characteristics of one or more geographical segments of the specified athletic event, wherein the one or more characteristics specify at least one physical feature or environmental feature of each of the one or more geographical segments;
identifying, by the cognitive computing system, based on the event information, geographical region information from a knowledge base, for one or more portions of a geographical region, within a specified geographical range of a home location associated with the user, that approximate the at least one physical feature or environmental feature of each of the one or more geographical segments of the specified athletic event within a predetermined tolerance, wherein the identification of the geographical region information from the knowledge base is based on a cognitive comparison of the one or more characteristics of one or more geographical segments of the specified athletic event to the one or more portions of the geographical region within the specified geographical range of the home location associated with the user using machine learning logic that learns different types of features through a machine learning process and applies the different types of features present in the one or more portions of the geographical region within the specified geographical range of the home location associated with the user to the one or more characteristics of one or more geographical segments of the specified athletic event;
generating, by the cognitive computing system, a training course at least by combining a selected set of portions of the one or more portions of the geographical region based on an evaluation, by the cognitive computing system, of a level of matching, for each portion in the selected set of portions, of characteristics of the portion to the at least one physical feature or environmental feature of the one or more geographical segments of the specified athletic event, wherein the training course provides conditions that assist the user in training for encountering the at least one physical feature or environmental feature of the one or more geographical segments of the specified athletic event at the future time; and
transmitting, by the cognitive computing system, the generated training course to the client computing device for presentation to the user as the personalized training regimen for use by the user in preparing for the specified athletic event.

US Pat. No. 10,971,261

OPTIMAL SLEEP PHASE SELECTION SYSTEM

DP Technologies, Inc., S...

1. A method comprising:determining a current sleep phase of a user based on sensor data from at least one sensor;
determining an optimal next sleep phase for the user based on at least remote data received via a network, wherein the remote data comprises one or more of: data from home environment controls, data from a home automation system, and data from a remote sensor; and
determining whether the user should be moved to the optimal next sleep phase, and when the user should be moved to the optimal next sleep phase, utilizing an output system to adjust one or more conditions in the user's environment to guide the user to the optimal next sleep phase.

US Pat. No. 10,971,260

SYSTEM AND METHOD FOR CAPTURING DOSE INFORMATION

BECTON, DICKINSON AND COM...

1. A device for capturing delivered dose information, comprising:a medication delivery device comprising a syringe barrel and a plunger;
a dose information capture device adapted to be removably attached to the syringe barrel of the medication delivery device; the dose information capture device comprising a Hall-effect sensor having a substantially linear analog output voltage; and
a target element adapted to be removably attached to the plunger of the medication delivery device;
wherein the target element comprises a magnet or a ferrous element inside the syringe barrel, and the target element attaches to the medication delivery device on the plunger of the medication delivery device, and
wherein the dose information capture device includes the Hall-effect sensor adapted to output a substantially linear analog output voltage in response to a position of the target element relative to the magnetic position sensor, the magnetic position sensor generating a signal with a magnitude that changes substantially linearly as a distance from the target element to the magnetic position sensor changes.

US Pat. No. 10,971,259

MEDICATION DELIVERY MANAGEMENT

CareFusion 303, Inc., Sa...

1. A system for managing a delivery of prepared medications, the system comprising:one or more processors; and
a machine-readable memory having instructions stored thereon that, when executed by the one or more processors, cause a first computing device to perform operations comprising:
receiving a first indication that a first medication is available for delivery to a first location within a healthcare facility, the first indication being received from a reader device and including information obtained from an active identification device affixed to a container of the first medication, the active identification device configured to automatically transmit the information wirelessly to the reader device when within a proximity of the reader device without a further action taken by a participant;
identifying a preparation status of a second medication designated for delivery within the healthcare facility;
determining a delivery time for the first medication and a completion time for the second medication;
determining, based on the delivery time and the completion time, whether the first medication should be delivered prior to completing the preparation of the second medication; and
providing, for display at a display device, when determining that the first medication should not be delivered prior to completing the preparation of the second medication, a notification to wait for the preparation of the second medication before delivering the first medication.

US Pat. No. 10,971,258

SYSTEMS, METHODS, AND APPARATUSES FOR MANAGING ADHERENCE TO A REGIMEN

1. A device that removably attaches to a medication container, the device comprising:a housing;
a processor;
a memory configured to store medication information;
a notification module;
one or more single-function detection buttons configured to be pressed in the same motion performed to open the medication container;
a detection module configured to detect when at least one of the detection buttons is pressed and store at least the time the button is pressed in the memory.

US Pat. No. 10,971,257

IMAGE ACQUISITION FOR MEDICAL DOSE PREPARATION SYSTEM

BAXTER CORPORATION ENGLEW...

1. A work station for use in a system for medical dose preparation management, the work station comprising:a base;
a medication preparation staging region disposed relative to the base and operable to supportively engage at least one medication receptacle;
an imaging device having an imaging field encompassing at least a portion of the medication preparation staging region, wherein the imaging device is operable to output a video data stream of the imaging field;
a processor in operative communication with the imaging device to receive the video data stream of the imaging field;
a user control device in operative communication with the processor to initiate a capture of a medical dose preparation image from the video data stream in response to a user input received at the user control device;
a scale in operative communication with the processor and operable to output a weight corresponding to a medication receptacle that is supportably disposed in the medication preparation staging region; and
a memory in operative communication with the processor,
wherein upon receipt of the user input, the weight is recorded by the processor from the scale at substantially the same time as the capture of the medical dose preparation image, and wherein the weight and the medical dose preparation image are associatively stored in the memory.

US Pat. No. 10,971,256

SYSTEM AND METHOD FOR IMPROVING HEALTHCARE THROUGH SOCIAL ROBOTICS

Humana Inc., Louisville,...

1. A system for improving the healthcare of a patient comprising:a programmable autonomous social robot configured to move in ways that give the appearance of various behaviors and emotional reactions and to play various sounds in sequence with said movements, said robot comprising a series of signaling devices and a series of corresponding touch sensors;
a wireless healthcare device configured to receive data regarding one or more health activities performed by the patient using the wireless healthcare device; and
a computer configured to receive data from the wireless healthcare device, said computer comprising data representing healthcare goals for the one or more health activities, a schedule for performing the one or more health activities, and executable software instructions, which when executed configure the robot to:
perform a positive emotional reaction skit when data received from the wireless healthcare device indicates progress towards the respective health goal, and
perform a negative emotional reaction skit when data received from the wireless healthcare device indicates regression from the respective health goal.

US Pat. No. 10,971,255

MULTIMODAL LEARNING FRAMEWORK FOR ANALYSIS OF CLINICAL TRIALS

ZASTI INC., Oakton, VA (...

1. A method for forecasting a clinical outcome for a subject patient based on a clinical trial involving a group of patients, comprising:obtaining patient image data for patients of the group;
extracting features from the obtained patient image data for patients of the group, wherein the features are extracted by using a scale invariant feature transform;
obtaining patient electronic health record data for patients of the group;
extracting features from the obtained electronic health record data for patients of the group;
for each patient of the group, concatenating the extracted features;
obtaining a value of the clinical outcome for patients of the group;
using the extracted features concatenated for each member of the group, and clinical outcome values obtained for each member of the group, training a random survival forest regression model that forecasts the clinical outcome;
obtaining patient image data for the subject patient;
extracting features from the obtained patient image data for the subject patient;
obtaining patient electronic health record data for the subject patient;
extracting features from the obtained electronic health record data for the subject patient;
concatenating the extracted features for the subject patient;
applying the random forest regression model to the concatenated extracted features for the subject patient to obtain a prediction of the clinical outcome for the subject patient; and
causing a treatment plan of the subject patient to be altered based, at least in part, on the prediction of the clinical outcome for the subject patient, the alteration being with respect to operation of a treatment device.

US Pat. No. 10,971,254

MEDICAL CONDITION INDEPENDENT ENGINE FOR MEDICAL TREATMENT RECOMMENDATION SYSTEM

International Business Ma...

1. A method, in a data processing system comprising at least one processor and at least one memory, wherein the at least one memory comprises instructions which are executed by the at least one processor to specifically configure the data processing system to implement a medical treatment recommendation system, the method comprising:configuring, by a medical condition independent score evaluation engine of the medical treatment recommendation system, a medical condition independent treatment recommendation model, wherein the medical condition independent treatment recommendation model is trained on, and operates on, a set of medical condition independent scoring features that are independent of any specific medical condition, wherein the set of medical condition independent scoring features comprise an inclusion criteria score feature, an exclusion criteria score feature, and a preference score feature;
loading, by a medical condition cartridge interface of the medical treatment recommendation system, a pluggable medical condition cartridge into a cognitive system to be utilized in a machine learning process to provide a set of medical condition specific evaluation features that are specific to a particular medical condition, wherein the machine learning process that provides the set of medical condition specific evaluation features that are specific to the particular medical condition is trained by:
adjusting one or more parameters utilized to evaluate an aggregate of the inclusion criteria score feature, the exclusion criteria score feature, and the preference score feature so as to provide an output as indicated by either a ground truth or golden set of data that not specific to any particular medical condition or particular treatment for a medical condition;
mapping, by a medical condition independent score feature engine of the medical treatment recommendation system, each of the set of medical condition specific evaluation features to a medical condition independent scoring feature in the set of medical condition independent scoring features;
processing, by the medical condition independent score evaluation engine, patient information for a patient based on application of the mapping of the set of medical condition specific evaluation features, associated with the pluggable medical condition cartridge, and the medical condition independent treatment recommendation model of the medical treatment recommendation system, to generate at least one treatment recommendation for a patient medical condition associated with the patient; and
outputting, by the data processing system to a client device, the at least one treatment recommendation for the patient.

US Pat. No. 10,971,253

CLIMATE CONTROL SYSTEM INCLUDING INDOOR AND SETPOINT TEMPERATURE DIFFERENCE AND EXTERIOR TEMPERATURE BASED HVAC MODE SWITCHING AND RELATED METHODS

K4CONNECT INC., Raleigh,...

1. A climate control system comprising:a heating, ventilation, and air conditioning (HVAC) system for an indoor building area being switchable between operating modes for heating and cooling;
a home automation (HA) thermostat device in the indoor building area and comprising
a housing,
an indoor temperature sensor carried by said housing and configured to sense an indoor temperature of the indoor building area, and
a temperature controller carried by said housing and configured to
obtain a setpoint temperature for the indoor building area,
obtain an external temperature from external to the indoor building area,
determine a crossing of the external temperature of the setpoint temperature, and
switch said HVAC system between operating modes based upon the crossing of the external temperature of the setpoint temperature and the indoor temperature moving beyond the setpoint temperature by a threshold temperature difference.

US Pat. No. 10,971,252

LINKING ENTITY RECORDS BASED ON EVENT INFORMATION

International Business Ma...

1. A system for linking data objects associated with a common entity comprising:at least one processor configured to:
compare data objects associated with an entity and corresponding to a plurality of events for the entity, wherein the data objects are stored within a plurality of different source systems, wherein data objects are compared in a pair-wise fashion to determine a likelihood score that indicates a likelihood of compared data objects being associated with a common event, wherein determining the likelihood score comprises comparing information in fields of the data objects pertaining to one or more from a group of: dates, locations, healthcare providers, medical procedures, medical diagnoses, laboratory tests, and medications, wherein each field is associated with one or more weight values corresponding to one or more matching levels of the information in the field, wherein higher weight values are associated with higher matching levels of the compared information in the fields of the data objects, and wherein the likelihood score is determined by adding one or more weight values determined according to the one or more matching levels of the information in the fields of the compared data objects;
identify candidate data objects associated with a common event for the entity based on the comparing, wherein candidate data objects are identified as associated with a common event based on the likelihood score exceeding a threshold, and wherein the common event includes one of a stay at a medical facility, an external laboratory test, and a medical insurance claim; and
link the candidate data objects to form a set of data objects, wherein each of the linked candidate data objects in the set of data objects is associated with the common event for the entity.

US Pat. No. 10,971,251

PROXIMITY-BASED HEALTHCARE MANAGEMENT SYSTEM WITH AUTOMATIC ACCESS TO PRIVATE INFORMATION

Proxense, LLC, Bend, OR ...

1. A system comprising:a first reader configured to wirelessly communicate within a proximity zone of the first reader;
a first personal digital key configured to wirelessly communicate with the first reader within the proximity zone of the first reader, the first personal digital key having a first unique identifier, the first personal digital key uniquely associated with a patient, the first personal digital key configured to send the first unique identifier wirelessly to the first reader;
a second personal digital key configured to wirelessly communicate with the first reader within the proximity zone of the first reader, the second personal digital key having a second unique identifier, the second personal digital key uniquely associated with a healthcare provider, the second personal digital key configured to send authentication data to the first reader subsequent to the second personal digital key entering the proximity zone of the first reader; and
a server having an input for receiving data and an output for providing data, the input of the server coupled to the first reader to receive the authentication data from the first reader, the server using the authentication data to access private healthcare information associated with the patient from a personal health record system, the access restricted to a set of authorized users including the healthcare provider, the access permitting retrieval of the private healthcare information and annotation of the private healthcare information, and wherein the access is temporary in that the private healthcare information is accessible to the healthcare provider as long as the first personal digital key and the second personal digital key are within the proximity zone of the first reader.

US Pat. No. 10,971,250

DYNAMIC AND ACCRETIVE COMPOSITION OF PATIENT ENGAGEMENT INSTRUMENTS FOR PERSONALIZED PLAN GENERATION

International Business Ma...

1. A system of selecting patient engagement instruments for individualized care, comprising:one or more hardware processors;
an analytics engine operable to execute on one or more of the hardware processors, the analytics engine further operable to retrieve a patient's data from a patient database stored in a memory device, the patient database connected to a hospital information system, the analytics engine further operable to classify the patient's condition based on the patient's data into a care dimension category; and
a questionnaire engine operable to execute on one or more of the hardware processors, the questionnaire engine further operable to select a set of initial instrument items associated with an initially determined level of self-efficacy based on the care dimension category classified by the analytics engine;
a literacy application module operable to execute on the one or more hardware processor and further operable to invoke the analytics engine and the questionnaire engine, and further operable to receive responses associated with the one or more initial instrument items from the patient,
the analytics engine further operable to receive medical results of lab tests performed associated with the patient, the analytics engine further operable to synthesize and analyze the responses and the medical results, the analytics engine further operable to determine a self-efficacy measure associated with the patient based on the synthesizing and the analyzing, the self-efficacy measure representing how well the patient understands the patient's conditions and the patient's level of knowledge on care management along one of a plurality of care dimensions comprising healthy diet, being active, monitoring, taking medication, problem solving, healthy coping and reducing risks, wherein the self-efficacy measure represents a patient's literacy score per dimension of care, and wherein based on the self-efficacy measure, the analytics engine further determines a dimension from the plurality of care dimensions to test and educate the patient, the analytics engine further operable to adjust the initially determined level of self-efficacy to another level according to the self-efficacy measure,
the questionnaire engine further operable to select a next set of instrument items associated with said another level, said another level used to select a difficulty level and the next set of instrument items correspond to the difficulty level,
the literacy application module further operable to present the next set of instrument items to the patient,
wherein the next set of instrument items comprising questionnaires and health education material are dynamically composed corresponding to said another level, reducing redundancy of presenting instrument items currently inapplicable to the patient based on dynamic changes in patient's self-efficacy measure,
wherein the analytics engine is operable to run a batch computer process to dynamically estimate a current self-efficacy level iteratively while the literacy application module is operable to present the next set of instrument items iteratively, estimating the current self-efficacy levels including at least modeling responses over time, assessment items and patient characteristics with the level of self-efficacy, the modeling including an evolution variance parameter which indicates a dependency among self-efficacy levels obtained at different time points,
wherein the literacy application module is further operable to present a multi-dimensional graphical view including at least a 3-dimensional display view including x-y-z axes representing a multitude of co-morbid conditions in a first dimension, different literacy levels in a second dimension, across different care management interventions in a third dimension, the graphical view updated dynamically based on the dynamic changes in the patient's self-efficacy measure,
the literacy application module running as a mobile application and communicating with the analytics engine and the questionnaire engine in providing the next set of instrument items,
the literacy application being integrated with the hospital information system and a kiosk at a point of service to at least dynamically determine the care dimension category in selecting the next set of instrument items,
wherein at least one of the hardware processors determines surprising levels of changes in each dimension of care using a sliding window in a fitted model showing a posterior density of the patient's self-efficacy measure, the surprising levels of the changes allowing for dynamically determining the care dimension category for selecting the next set of instrument items,
wherein a care plan is created at least based on the patient's self-efficacy measure, wherein creating of the care plan triggers via the literacy application an activation of a task in the care plan,
wherein the multi-dimensional graphical view is generated and updated based on dynamic categorization and care plan generation.

US Pat. No. 10,971,248

BAMBAM: PARALLEL COMPARATIVE ANALYSIS OF HIGH-THROUGHPUT SEQUENCING DATA

The Regents of the Univer...

1. A parallel genomic comparative analysis system comprising:a computer-readable memory; and
an sequence analysis engine having at least one processor coupled with the computer-readable memory and configured to:
identify a genomic position within a reference genome;
access a first file storing tumor sequence data including reads associated with a tumor tissue;
access a second file storing matched normal sequence data including reads associated with a matched normal tissue;
store, in the computer-readable memory, a tumor dataset having tumor read sequences from the first file, where the tumor read sequences overlap the genomic position;
store, in the computer-readable memory, a matched normal dataset having matched normal read sequences from the second file, where the matched normal read sequences overlap the genomic position, wherein the computer-readable memory is configured to store the tumor dataset and the matched normal dataset simultaneously, and wherein at least one of the tumor dataset and matched normal dataset includes all the reads from their respective files that overlap the genomic position;
select a tumor genotype and a matched normal genotype that maximize a likelihood as a function of at least one the tumor read sequences and the matched normal read sequences at the genomic position; and
store a difference associated with at least one of the tumor genotype and the matched normal genotype in a device memory.

US Pat. No. 10,971,247

SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS, AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A method of replacing a memory cell in a first column of a memory block in a memory device including a plurality of memory blocks and at least a first redundancy block, the method including:replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block;
reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device; and,
replacing an address of a second normal memory cell in a first column of a second memory block with an address of a second destination memory cell in a second column of the second memory block, wherein the second destination memory cell is a normal memory cell, wherein;
the first column of the first memory block and the first column of the second memory block have the same relative location with respect to the columns of their respective memory blocks, and
the second column of the first memory block and the second column of the second memory block have a different relative location with respect to the columns of their respective memory blocks.

US Pat. No. 10,971,246

PERFORMING ERROR CORRECTION IN COMPUTER MEMORY

International Business Ma...

1. A method of performing error correction in computer memory, the method comprising:receiving a read request targeting a read address within the computer memory;
accessing a mark table comprising a plurality of entries, each entry corresponding to a detected error at a memory address in a physical location of computer memory, each entry including a field specifying a memory region size identifying a hierarchical memory level within the computer memory, a field specifying a match address, and a field specifying a mark location;
performing a lookup of the mark table using the read address including, for each entry in the mark table:
generating a mask based on the memory region size stored in the entry;
determining, based on the mask, whether the read address is within a memory region specified by the match address and memory region size stored in the entry; and
if the read address is within the memory region specified by the match address and memory region size stored in the entry, performing error correction using the mark location stored in the entry.

US Pat. No. 10,971,245

MEASUREMENT OF MTJ IN A COMPACT MEMORY ARRAY

SPIN MEMORY, INC., Fremo...

1. A magnetic memory device, comprising:a magnetic bit cell array including a first plurality of magnetic tunnel junction elements;
a reference bit cell array including a second plurality of magnetic tunnel junction elements;
circuitry connected with the bit cell array and the reference bit cell array, the circuitry being configured to:
read a signal from the bit cell array to determine an electrical resistance associated with first magnetic tunnel junction element that is one of the first plurality of magnetic tunnel junction elements;
read a signal from the reference bit cell array to determine an electrical resistance associated with a second magnetic tunnel junction element that is one of the second plurality of magnetic tunnel junction elements;
determine a parasitic resistance associated with the first magnetic tunnel junction element to determine an electrical resistance of the first magnetic tunnel junction element without the parasitic resistance, and comparing the resistance of the first magnetic tunnel junction element with a reference value; wherein
the circuitry includes one or more switches for switching between a first configuration wherein individual signals are read from each of the bit cell array and reference bit cell array and a second configuration wherein signals from the bit cell array and reference bit cell array are combined and further include a resistance from a reference resistor.

US Pat. No. 10,971,244

STRUCTURE AND METHOD FOR TESTING THREE-DIMENSIONAL MEMORY DEVICE

Yangtze Memory Technologi...

1. A method for testing a memory device, comprising:applying an input signal to a first conductive pad of the memory device by a first probe of a probe card;
transmitting, through at least the first conductive pad, a first through array contact (TAC) of the memory device, a first interconnect structure passing through a bonding interface between a memory array structure and a peripheral device structure of the memory device, and at least one of a memory array contact and a test circuit, the input signal to a test structure of the memory device;
receiving, through at least a second interconnect structure passing through the bonding interface, a second TAC of the memory device, and the at least one of the memory array contact and the test circuit, an output signal from the test structure;
measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and
determining a characteristic of the test structure based on the input signal and the output signal.

US Pat. No. 10,971,243

BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER

INTERNATIONAL BUSINESS MA...

1. A method, comprising:in executing a test pattern during a first time for a first built-in-self-test (BIST) run, masking, in a pattern mask register of a BIST engine, each test pattern of a plurality of test patterns that indicates a pass status in the pattern mask register;
reprogramming the pattern mask register before a second BIST run; and
in the second BIST run, for each test pattern of the plurality of test patterns:
determining whether or not the test pattern is masked in the pattern mask register of the BIST engine;
in response to determining that the test pattern is not masked in the pattern mask register of the BIST engine, executing the test pattern a second time which includes:
determining whether there is a FAIL for the test pattern after the test pattern is executed the second time; and
sending fail information to the BIST engine for latching and storing the fail information in the pattern mask register in response to a determination that there is the FAIL for the test pattern; and
in response to determining that the test pattern is masked in the pattern mask register of the BIST engine, skipping the executing the test pattern the second time.

US Pat. No. 10,971,242

SEQUENTIAL ERROR CAPTURE DURING MEMORY TEST

INTERNATIONAL BUSINESS MA...

1. A system for testing a memory array having self-test circuitry, the system comprising:a register comprising a plurality of register latches operable to receive a plurality of error logic signals having respective first states or second states, the register latches being arranged in series respectively having a plurality of latch inputs cascaded with a plurality of preceding latch outputs operable to shift the error logic signals according to a control signal that is common to the register latches to a serial output as a first state or second state based on the error logic signals;
an aggregate latch operable to receive the serial output and having input logic configured to maintain the first state within the aggregate latch until the serial output is the second state; and
a built-in self-test (BIST) engine comprising a plurality of stored instructions operable upon execution by the BIST engine to output the control signal.

US Pat. No. 10,971,241

PERFORMANCE BASED METHOD AND SYSTEM FOR PATROLLING READ DISTURB ERRORS IN A MEMORY UNIT

TOSHIBA MEMORY CORPORATIO...

1. A method for handling read disturb errors in a memory, the method comprising:retrieving, by a memory management system, status information related to each of a plurality of memory blocks in the memory from a memory status table associated with the memory, wherein the status information includes a block erase count and a number of one or more valid pages in each of the plurality of memory blocks;
identifying, by the memory management system, one or more target memory blocks with the one or more valid pages and having a highest block erase count among the plurality of memory blocks;
patrolling, by the memory management system, each of the one or more valid pages in the one or more target memory blocks for identifying the read disturb errors in the one or more valid pages, wherein at least three different threshold counters are considered during initialization and execution of the patrolling, (1) a first threshold counter corresponding to a first predetermined threshold value for initializing the patrolling based on a number of read-write memory operations, (2) a second threshold counter corresponding to a second predetermined threshold value for a user to trigger the patrolling based on a count of page read-write memory operations, and (3) a third threshold counter corresponding to a third predetermined threshold value for the user to set a number of valid pages to be patrolled when the patrolling is triggered and initialized; and
recycling, by the memory management system, the one or more valid pages having the read disturb errors for handling the read disturb errors in the memory, wherein
a status of patrolling of one or more of the plurality of memory blocks is set as patrolled when the one or more of the plurality of memory blocks are being used by an application running on the memory management system during the patrolling of the one or more of the plurality of memory blocks, and
the status of the patrolling is stored in a patrol status table in the memory, wherein the patrol status table includes information related to the one or more valid pages which are not patrolled and target block information including at least a memory address of the one or more target memory blocks and a number of the one or more valid pages pending to be patrolled in the one or more target memory blocks.

US Pat. No. 10,971,240

WORDLINE SMART TRACKING VERIFY

SanDisk Technologies LLC

1. A storage device, comprising:a non-volatile memory coupled to a controller;
the non-volatile memory including control circuits and including a memory array;
the memory array including a plurality of word lines;
wherein the controller is configured to:
determine a first programming voltage by performing at least one program-verify iteration on at least a portion of a first word line of the plurality of word lines using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed,
determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount; and
perform at least one program-verify iteration on at least a portion of a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.

US Pat. No. 10,971,239

MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETS

SUNRISE MEMORY CORPORATIO...

1. In a memory circuit under control of a system controller, a method for rapidly determining the location of a file, comprising:associating the file with a timestamp and a unique identifier index number when the file is stored or updated in the memory circuit, and storing in a look-up table in the memory circuit the associated timestamp and an address associated with where the file is stored;
receiving from the system controller a search request that specifies a unique identifier index number of a file to be located; and
using exclusive-or (XOR) circuits or content addressable memory (CAM) circuits to compare the unique identifier index number in the search request with the unique identifier index number stored in the look-up table, and reporting to the system controller, when a match is found between the unique identifier index number in the search request and the unique identifier index number stored in the look-up table, the timestamp and address associated with the match.

US Pat. No. 10,971,238

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME

Samsung Electronics Co., ...

1. A three-dimensional (3D) semiconductor memory device comprising a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line,wherein each of the cell strings comprises a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line,
wherein, in each of the word line blocks, the string selection transistors of the cell strings are electrically separated from each other, and ones of the ground selection transistors that are located at a same vertical level are controlled in common, and
wherein, in each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage.

US Pat. No. 10,971,237

SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device having stored therein a plurality of bits of fixed data, the semiconductor device comprising:a plurality of memory elements that correspond, respectively, to the plurality of bits of the fixed data, and that acquire, store, and output a value of each bit received at an input terminal of each of the memory elements according to a timing signal; and
an initialization control unit that feeds, to the plurality of memory elements, an initialization signal upon receipt of a fixed data setting signal,
wherein each of the plurality of memory elements is initialized to a state of storing a corresponding value represented by a bit of the fixed data according to the initialization signal.

US Pat. No. 10,971,236

SEMICONDUCTOR DEVICE WITH A FUNCTION OF GENERATING INHERENT INFORMATION

Winbond Electronics Corp....

1. A semiconductor device, comprisinga memory array comprising NAND-type strings;
a selection means selecting a specific area of the memory array;
a readout means reading out a specific area selected by the selection means;
a detection means detecting a potential difference of a bit line pair of a specific area read by the readout means; and
a generation means generating inherent data of the semiconductor device based on the detection result of the detection means;
wherein the specific area is a block that is physically farthest from the readout means,
wherein the selection means applies a voltage to all word lines within a selected block, the voltage is independent of memory states of memory cells and turns on the memory cells, and the voltage is higher than a threshold value to turn on an erase memory cell and a program memory cell.

US Pat. No. 10,971,235

METHODS OF OPERATING MEMORY DEVICES BASED ON SUB-BLOCK POSITIONS AND RELATED MEMORY SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. A method of operating a memory device including a memory block having at least two sub-blocks, the memory block connected to a plurality of ground select lines configured to control coupling to a common source line and connected to a plurality of string select lines configured to control coupling to a plurality of bit lines, the method comprising:receiving a program command from outside the memory device;
determining if a plurality of selected word lines configured to activate memory cells responsive to the program command are included in a first sub-block or are included in a second sub-block to provide a selected program sub-block;
performing a program operation using a first sequence of a plurality of first selected word lines extending in a first direction from the plurality of ground select lines toward the plurality of string select lines responsive to determining that the plurality of selected word lines are included in the first sub-block; and
performing the program operation using a second sequence of a plurality of second selected word lines extending in a second direction from the plurality of string select lines toward the plurality of ground select lines responsive to determining that the plurality of selected word lines are included in the second sub-block,
wherein the first and second sub-blocks are configured to be classified based on a position of a first reference word line of the at least two sub-blocks during the program operation, and
wherein the first reference word line is included in the plurality of first or second selected word lines.

US Pat. No. 10,971,234

PAGE BUFFER, A MEMORY DEVICE HAVING PAGE BUFFER, AND A METHOD OF OPERATING THE MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A memory device, comprising:a voltage generator configured to generate operating voltages for operating a plurality of memory cells;
a program and verify circuit configured to apply the operating voltages to respective word lines and bit lines coupled to the plurality of memory cells and configured to perform a program operation and a verify operation on the plurality of memory cells; and
a program operation controller configured to control the program and verify circuit and the voltage generator to perform a bit line precharge operation and to perform a bit line discharge operation after the bit line precharge operation has been completed,
wherein the bit line precharge operation increases a potential of a bit line coupled to a program-inhibited cell, among the plurality of memory cells, to a program inhibition voltage and increases potentials of bit lines coupled to first and second program cells to a first program permission voltage, and
wherein the bit line discharge operation decreases the potential of the bit line coupled to the first program cell to a second program permission voltage.

US Pat. No. 10,971,233

READ WINDOW BUDGET BASED DYNAMIC PROGRAM STEP CHARACTERISTIC ADJUSTMENT

Micron Technology, Inc., ...

1. A system, comprising:a memory component including a group of memory cells; and
a processing device coupled to the memory component and configured to:
compare a read window budget (RWB) corresponding to the group of memory cells to a target RWB; and
in response to the RWB being different than the target RWB, adjust a program step size associated with the group of memory cells to adjust the RWB corresponding to the group of memory cells toward the target RWB, wherein the program step size corresponds to a voltage difference between consecutive programming signals of a series of programming signals applied to the group of memory cells to program the group of memory cells to a particular data state.

US Pat. No. 10,971,232

NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD OF THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A program method of a nonvolatile memory device comprising a plurality of cell strings each cell string having a plurality of memory cells, the program method comprising:performing a plurality of program loops for a first selected memory cell of a first selected cell string of the plurality of cell strings,
wherein a first program loop of the plurality of program loops is performed by a first program method comprising a method of performing F-N tunneling, and
wherein a second program loop of the plurality of program loops after the first program loop is performed by a second program method comprising a method of performing a hot carrier injection (HCl) program operation,
wherein the first program loop uses a first program voltage applied to the first selected memory cell, and
wherein a level of the first program voltage is less than and closest to a level of a reference voltage among program voltages applied to the first selected memory cell during one or more program loops of the plurality of program loops before the second program loop.

US Pat. No. 10,971,231

ADAPTIVE VPASS FOR 3D FLASH MEMORY WITH PAIR STRING STRUCTURE

SANDISK TECHNOLOGIES LLC,...

1. An apparatus, comprising:a word line driver circuit configured to connect to a first set of NAND strings and a second set of NAND strings, the first set of NAND strings and the second set of NAND strings are connected to a common bit line, the first set of NAND strings includes a first NAND string with a first drain-side select gate connected to the common bit line, the second set of NAND strings includes a second NAND string with a second drain-side select gate connected to the common bit line, the first set of NAND strings connects to a first source line and the second set of NAND strings connects to a second source line; and
one or more control circuits configured to be in communication with the word line driver circuit, the one or more control circuits are configured to determine a selected word line connected to a first group of memory cells within the first set of NAND strings and connected to a second group of memory cells within the second set of NAND strings, the one or more control circuits are configured to determine a first pass voltage and a second pass voltage greater than the first pass voltage, the one or more control circuits are configured to cause the first group of memory cells to be programmed while the first pass voltage is applied to one or more other word lines connected to other memory cells within the first set of NAND strings, the one or more control circuits are configured to cause the first group of memory cells to be programmed while the first drain-side select gate is set into a conducting state and the second drain-side select gate is set into a non-conducting state, the one or more control circuits are configured to cause the second group of memory cells to be programmed while the second pass voltage is applied to the one or more other word lines, the one or more control circuits are configured to cause the second group of memory cells to be programmed while the first drain-side select gate is set into the non-conducting state and the second drain-side select gate is set into the conducting state.

US Pat. No. 10,971,230

NONVOLATILE MEMORY DEVICE AND METHOD OF PROCESSING IN MEMORY (PIM) USING THE SAME

Samsung Electronics Co., ...

1. A nonvolatile memory device comprising:a memory cell array including a plurality of NAND strings storing multiplicand data, first ends of the plurality of NAND strings connected to a plurality of bitlines, second ends of the plurality of NAND strings outputting a plurality of multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the plurality of NAND strings and multiplier data loaded on the plurality of bitlines;
an input current generator configured to generate a plurality of input currents;
an operation cell array including a plurality of switching transistors, gate electrodes of the plurality of switching transistors connected to the second ends of the plurality of NAND strings, the plurality of switching transistors selectively summing the plurality of input currents based on the plurality of multiplication bits to output a plurality of output currents; and
an analog-to-digital converter configured to convert the plurality of output currents to a plurality of digital values.