US Pat. No. 10,692,961

DISPLAY DEVICE AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:first and second transistors over a resin;
first and second wirings over the resin; and
an electroluminescent element over the resin,
wherein the first wiring is electrically connected to one of a source and a drain of the first transistor,
wherein the second wiring is electrically connected to one of a source and a drain of the second transistor,
wherein the electroluminescent element is electrically connected to the other of the source and the drain of the first transistor,
wherein a channel formation region of the first transistor comprises a region through which carriers flow in a first direction,
wherein a semiconductor layer comprising the channel formation region of the first transistor has a bent shape,
wherein the first wiring is configured to transmit current flowing the electroluminescent element through the first transistor,
wherein the first wiring comprises a region overlapping with the semiconductor layer,
wherein the first wiring has a shape which is long along a direction intersecting with the first direction,
wherein the second transistor is configured to supply a signal from the second wiring to the first transistor,
wherein the second wiring comprises a region overlapping with the semiconductor layer,
wherein the channel formation region of the first transistor comprises crystal silicon, and
wherein a channel formation region of the second transistor comprises crystal silicon.

US Pat. No. 10,692,960

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus, comprising:a substrate;
a plurality of pixels that are on the substrate and include at least one display device;
a separation area that is on the substrate and includes a first separation area and a second separation area; and
a penetrating portion that penetrates the substrate and includes a first penetrating portion and a second penetrating portion,
wherein the first separation area includes an area between two pixels adjacent in a first direction selected from among the plurality of pixels, the second separation area includes an area between two pixels adjacent in a second direction intersecting the first direction selected from among the plurality of pixels,
wherein the first penetrating portion is in the first separation area and not in the second separation area, the second penetrating portion is in the second separation area and not in the first separation area, and the first penetrating portion and the second penetrating portion are spaced apart from each other, and
wherein the plurality of pixels each includes a plurality of sub-pixels, the plurality of sub-pixels of at least one pixel of the plurality of pixels are arranged in the first direction, and the plurality of sub-pixels of a pixel adjacent to the at least one pixel are arranged in the second direction intersecting the first direction.

US Pat. No. 10,692,959

ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device, comprising:a substrate on which a display area and a non-display area are defined;
a thin film transistor in the display area on the substrate;
a light-emitting diode connected to the thin film transistor and including a first electrode, a light-emitting layer and a second electrode;
a first link line disposed in the non-display area and configured to apply a first voltage to the first electrode;
a second link line spaced apart from the first link line in the non-display area; and
a conductive pattern disposed in the non-display area and connected to the second electrode to apply a second voltage, the conductive pattern having an opening corresponding to the first link line.

US Pat. No. 10,692,958

ORGANIC LIGHT EMITTING DIODE DISPLAY

LG Display Co., Ltd., Se...

1. An organic light emitting diode display, comprising:a first substrate and a second substrate facing each other; and
a conductive filler layer interposed between the first substrate and the second substrate,
wherein the first substrate includes:
a bank layer having an opening exposing at least a portion of an anode;
a spacer disposed on the bank layer;
an organic compound layer and a cathode disposed on the anode, the bank layer, and the spacer, the organic compound layer and the cathode being sequentially stacked;
an inorganic layer disposed on the cathode, the inorganic layer including a first open hole exposing at least a portion of the cathode positioned on the spacer; and
an organic layer disposed on the inorganic layer, the organic layer including a second open hole exposing at least a portion of the cathode positioned on the spacer, wherein an upper surface of the organic layer is positioned on the same plane as an upper surface of the inorganic layer, wherein the exposed portion of the cathode directly contacts the conductive filler layer;
wherein the second substrate includes a power line electrically connected to a portion of the exposed cathode through the conductive filler layer.

US Pat. No. 10,692,957

ORGANIC LIGHT EMITTING DISPLAY DEVICE FOR PROTECTING AN ELECTROSTATIC DISCHARGING CIRCUIT

LG Display Co., Ltd., Se...

1. An organic light emitting display device, comprising:at least one driving element which is connected to a data line and a gate line on a substrate, wherein the substrate is a flexible substrate in which a bending area is included;
a planarization layer which covers the driving element;
an organic light emitting diode which is disposed on the planarization layer and is connected to the driving element;
an electrostatic discharging circuit which is connected to the data line or the gate line; and
a wiring electrode in the bending area,
wherein the electrostatic discharging circuit is covered by a protective layer, and
wherein the wiring electrode is the same material as an electrode selected from electrodes which configure the driving element.

US Pat. No. 10,692,956

DISPLAY DEVICE INCLUDING A CONTROL LINE WITH A DETOUR PART

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a scan line extending in a first direction;
a plurality of data lines crossing the scan line;
a driving voltage line crossing the scan line;
an active pattern including a plurality of channel regions and a plurality of conductive regions; and
a control line crossing the plurality of data lines and the driving voltage line,
wherein the control line includes a plurality of main line parts each extending in the first direction, and a detour part connecting two adjacent main line parts of the plurality of main line parts to each other,
wherein the active pattern includes a shielding part overlapping at least one data line of the plurality of data lines, a longitudinal part crossing the plurality of main line parts, and a connection part connecting the longitudinal part to the shielding part, and
wherein the detour part extends along a periphery of the active pattern, crosses the at least one data line of the plurality of data lines, and does not overlap the shielding part.

US Pat. No. 10,692,955

AMOLED DISPLAY PANEL AND DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. An AMOLED display panel, comprising:a plurality of pixel structures, arranged in a matrix;
a plurality of power lines, configured to provide a driving power to the pixel structures;
a plurality of data lines and a plurality of scan lines crisscrossed to form a plurality of areas;
a first main power line; and
a second main power line,
wherein two adjacent rows or two adjacent columns of the pixel structures is a period unit, each period unit is disposed corresponding to one of the power lines, the one of the power lines is disposed between the two adjacent rows or the two adjacent columns of the pixel structures, and the one of the power lines provides the driving power to the two adjacent rows or the two adjacent columns of the pixel structures disposed at two side of the one of the power lines, the pixel structures are disposed in the areas, the power lines are parallel to the data lines and perpendicular to the scan lines, and the one of the power lines is disposed between the two adjacent columns of the pixel structures, the first main power line and the second main power line are disposed outside the pixel structures, wherein the first main power line and the second main power line respectively extend along a direction perpendicular to the data lines, an end of the power lines is connected to the first main power line, and another end of the power lines is connected to the second main power line.

US Pat. No. 10,692,954

BACKPLANE FOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A method of manufacturing a backplane for a display device including a display region and a pad region, the method comprising:forming an insulation layer on a substrate;
forming a pad electrode layer on the insulation layer;
forming a photoresist pattern on the pad electrode layer in the pad region;
etching the pad electrode layer and a portion of the insulation layer by the photoresist pattern as an etch-stop layer so as to simultaneously form a pad electrode and a side protection layer which covers a sidewall of the pad electrode; and
stripping the photoresist pattern,
wherein a height of the side protection layer measured in a vertical direction substantially perpendicular to the extension direction of the substrate is substantially the same as a height of the pad electrode, and the side protection layer is not disposed on any top surface defining the pad electrode.

US Pat. No. 10,692,953

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate comprising a bending area between a first area and a second area;
an inorganic insulating layer arranged over the substrate, the inorganic insulating layer having an opening or a groove corresponding to the bending area;
a wiring unit extending to the second area through the bending area, the wiring unit arranged on the inorganic insulating layer and at least a portion thereof overlapping the opening or the groove; and
an organic material layer between the inorganic insulating layer and the wiring unit, the organic material layer configured to fill the opening or the groove,
wherein the wiring unit comprises a first wire and a second wire that are adjacent to each other, and a smallest width in which the opening or the groove overlaps the first wire is different from a smallest width in which the opening or the groove overlaps the second wire.

US Pat. No. 10,692,952

OLED SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode (OLED) substrate, comprising a base substrate, and a thin-film transistor, a first electrode, and a light-emitting layer arranged in sequence on the base substrate, wherein the OLED substrate further comprises a light-shielding layer arranged between an active layer of the thin-film transistor and the first electrode,wherein a material of the light-shielding layer comprises amorphous silicon, and the OLED substrate further comprises side layers arranged on two opposite sides of the light-shielding layer and in contact with the light-shielding layer, and wherein a material of the side layers is an insulating material,
wherein the material of the light-shielding layer further comprises sulfur doped in the amorphous silicon.

US Pat. No. 10,692,951

BACK PLATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A back plate, comprising a base substrate and a driving thin film transistor (TFT) arranged on the base substrate, wherein the driving TFT comprises a light-shielding layer, a buffer layer and an active layer arranged sequentially on the base substrate;a gate insulation layer, a gate electrode, a source electrode, a drain electrode and an interlayer dielectric layer are arranged on the active layer; and
the buffer layer is provided with a first protrusion, and an orthogonal projection of the first protrusion onto the base substrate is located within an orthogonal projection of the gate electrode onto the base substrate.

US Pat. No. 10,692,950

OLED DISPLAY PANEL HAVING A FIRST BARRIER CLOSED RING AND A SECOND BARRIER CLOSED RING

WUHAN CHINA STAR OPTOELEC...

1. An organic light emitting diode (OLED) display panel, including a display region and a non-display region, the display region configured to display images, the non-display region surrounding the display region, the display panel comprising:a thin-film transistor (TFT) array substrate, comprising an insulating layer stacked structure in the non-display region, the insulating layer stacked structure comprising a plurality of overlapped insulating layers;
a plurality of organic light emitting units, disposed on the TFT array substrate and located in the display region;
a first barrier, disposed on the TFT array substrate, the first barrier located in the non-display region and surrounding the display region;
a second barrier, disposed on the TFT array substrate, the second barrier located in the non-display region and surrounding the first barrier, the first barrier and the second barrier distanced away from each other, the first barrier comprising a first closed ring structure, the second barrier comprising a second closed ring structure, the first closed ring structure disposed inside the second closed ring structure, the first barrier and the second barrier constructing a ring structure, a straight-edge region and a corner region defined on the ring structure;
a trench, disposed in the straight-edge region of the ring structure and between the first closed ring structure and the second closed ring structure, the trench disposed in the insulating layer stacked structure of the TFT array substrate and having an exposed opening, a height of the TFT array substrate in the straight-edge region lower than a height of the TFT array substrate in the corner region; and
a thin film packaging structure, having one or more organic layers and one or more inorganic layers that are overlapped, the thin film packaging structure covering the TFT array substrate, the plural organic light emitting units, the first barrier, the second barrier, and the exposed opening of the trench in the straight-edge region disposed on the ring structure.

US Pat. No. 10,692,949

ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device, comprising:a substrate including first, second and third pixel regions, the second and third pixel regions being adjacent to the first pixel region along a first direction and a second direction substantially perpendicular to the first direction, respectively;
an insulating layer over the substrate and including a groove between the first and second pixel regions;
a first electrode on the insulating layer and in each of the first to third pixel regions, the first electrode including a first edge along a major axis of each of the first, second and third pixel regions and a second edge along a minor axis of each of the first, second and third pixel regions;
a bank covering the first and second edges of the first electrode and disposed between the first pixel region and the second pixel region and between the first pixel region and the third pixel region;
an emitting layer on the first electrode; and
a second electrode on the emitting layer,
wherein the bank has a double-layered structure of a first bank and a second bank on the first bank and is disposed between the first and second pixels regions along the first direction and between the first and third pixel regions along the second direction,
wherein a major side surface of the second bank disposed along the major axis of the first pixel region has a first height extending from an uppermost surface of the first bank on the first edge of the first electrode to an uppermost surface of the second bank in an area adjacent a long side of the first pixel region,
wherein a minor side surface of the second bank disposed along the minor axis of the first pixel region has a second height extending from an uppermost surface of the first bank on the second edge of the first electrode to an uppermost surface of the second bank in an area adjacent a short side of the first pixel region, the second height being greater than the first height, and
wherein a portion of a bottom surface of the first bank along the major axis of the first pixel region is disposed inside the groove such that the portion of the bottom surface of the first bank is positioned to be lower than a bottom surface of the first electrode.

US Pat. No. 10,692,948

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

4. A method of manufacturing an array substrate, comprising the steps of:step S1, patterning a gate layer prepared on the substrate to obtain gates of the driver thin film transistor and the switch thin film transistor;
step S2, forming a barrier layer on the gate of the driver thin film transistor;
step S3, depositing a gate insulating layer on the substrate;
step S4, forming an active layer on the gate insulating layer above the gates of the driver thin film transistor and the switch thin film transistor;
step S5, fabricating a source and a drain on the active layer;
step S6, forming a passivation layer on the substrate, the passivation layer covering the source and the drain;
step S7, fabricating a planarization layer different from the passivation layer on the passivation layer; and
step S8, forming an anode on the planarization layer, the anode is directly connected to the source and the drain of the driver thin film transistor through via holes of the planarization layer and the passivation layer.

US Pat. No. 10,692,947

LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. A light emitting display device comprising:a plurality of pixels, each of the pixels including:
a transistor having a gate electrode, an active layer overlapping the gate electrode, a source electrode connected to one side of the active layer, and a drain electrode connected to another side of the active layer; and
a light emitting device having a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer;
a contact hole, the first electrodes of at least two of the pixels being electrically connected to side surfaces of respective source electrodes or to side surfaces of respective drain electrodes in the contact hole;
a dummy electrode on a floor of the contact hole, the dummy electrode being electrically isolated from the first electrodes of the at least two pixels;
a bank that at least partially fills the contact hole; and
a first planarization layer between the first electrode and at least one of the source electrode and the drain electrode,
wherein the dummy electrode is on the first planarization layer in the contact hole.

US Pat. No. 10,692,946

ORGANIC EL DISPLAY PANEL AND METHOD FOR PRODUCING SAME

JOLED INC., Tokyo (JP)

1. An organic electroluminescence (EL) display panel including pixels arranged in a matrix of rows and columns, the organic EL display panel comprising:a substrate;
pixel electrode layers that are made of a light-reflective material and are arranged on the substrate in the matrix;
an insulating layer that is provided above the substrate and the pixel electrode layers, and has elongated openings and a grooved portion for each of the pixels, the openings extending in a column direction and being arranged in a row direction, the grooved portion having an upper opening and a bottom and being communicated with at least one of the openings in plan view;
organic functional layers that are provided above the pixel electrode layers, and include light-emitting layers in which organic electroluminescence occurs in the openings; and
a light-transmissive counter electrode layer that is provided above the organic functional layers, wherein
cross-sectional profiles of the openings taken along the row direction are uniform in the column direction.

US Pat. No. 10,692,945

MANUFACTURING METHOD FOR AN INKJET PRINTING AMOLED DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method for an inkjet printing active-matrix organic light emitting diode (AMOLED) display panel, comprising steps of:manufacturing a thin-film transistor (TFT) backplane, and manufacturing an anode on the TFT backplane;
manufacturing a spacer layer covering the anode;
manufacturing a pixel definition layer on the TFT backplane, wherein the pixel definition layer covers the spacer layer and the spacer layer isolates the anode from the pixel definition layer;
patterning the pixel definition layer to form a notch in order to expose the spacer layer;
etching the spacer layer below the notch by an etching solution; and
forming an ink layer on the anode by an inkjet printing method,
wherein the spacer layer is a metal film layer that is of a single-layered structure and the etching solution is applied to etch through the single-layered structure of the metal film layer to expose the anode.

US Pat. No. 10,692,944

DISPLAY DEVICE INCLUDING A SENSING SIGNAL TRANSMITTER AND A SENSING SIGNAL RECEIVER

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate including a display area including pixels and a non-display area adjacent to the display area;
a circuit layer disposed on the display area and the non-display area;
a light emitting layer disposed in the display area and including a light emitting element defining the pixels;
a transmitter disposed on the circuit layer in the non-display area and transmitting a sensing signal; and
a receiver disposed in the display area separated from the transmitter and receiving the sensing signal,
wherein a pixel control circuit for controlling the light emitting element is disposed in the circuit layer in the display area and a driving control circuit is disposed in the circuit layer in the non-display area to be electrically connected to the transmitter.

US Pat. No. 10,692,943

TOUCH ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND IN-CELL TOUCH ORGANIC LIGHT-EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A touch organic light-emitting display device, comprising:a substrate comprising:
a display area; and
a non-display area;
a lower base crossing the display area and the non-display area;
an upper base opposite the lower base, the upper base crossing the display area and the non-display area;
a thin-film transistor array on the display area of the lower base;
an organic light-emitting array on the thin-film transistor array, the organic light-emitting array comprising:
a first electrode;
a bank insulation film;
a spacer;
an emission layer; and
a second electrode;
an adhesive layer between the lower base and the upper base; and
a pad portion in the non-display area,
wherein the upper base comprises a plurality of concave patterns and at least one upper dam at a position corresponding to a region between the pad portion and the display area,
wherein the upper base further comprises a flexible material,
wherein the lower base comprises at least two lower dams, at least one of the at least two lower dams being at a position corresponding to a corresponding one of the at least one upper dam,
wherein the plurality of concave patterns and the at least one upper dam are formed by patterning the upper base, and
wherein the at least two lower dams comprises:
a first lower dam, and
a second lower dam.

US Pat. No. 10,692,942

ORGANIC LIGHT EMITTING DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting display device comprising:a substrate including a plurality of pixel areas and a pixel separating area between the pixel areas;
a plurality of pixels corresponding to each of the plurality of pixel. areas, each of the pixels including a pixel electrode, an opposite electrode, and an organic light emitting layer disposed between the pixel electrode and the opposite electrode;
a plurality of spacers disposed in the pixel separating area and spaced apart from each other; and
a touch electrode unit disposed over the plurality of pixels and the plurality of spacers, the touch electrode unit including first touch electrodes arranged in a first direction and second touch electrodes arranged in a second direction perpendicular to the first direction, wherein:
the touch electrode unit includes a plurality of touch pattern unit blocks repeatedly arranged and each touch pattern unit block includes portions of each of neighboring first touch electrodes and portions of each of neighboring second touch electrodes; and
an arrangement of the spacers of each touch pattern unit block corresponds to a plurality of spacer pattern unit blocks repeatedly arranged and each spacer pattern unit block includes at least one spacer and is smaller than the touch pattern unit block,
wherein the plurality of pixels includes a plurality of pixel pattern unit blocks repeatedly arranged, each pixel pattern unit block includes at least a first pixel, a second pixel, and a third pixel that emit light corresponding to different colors, and
wherein an arrangement of the pixels of each spacer pattern unit block corresponds to K of the pixel pattern unit blocks arranged in the first direction, and L of the pixel pattern unit blocks arranged in the second direction, where K and L are natural numbers,
wherein an arrangement of the pixels of each touch pattern unit block corresponds to M of the K of the pixel pattern unit blocks arranged in the first direction, and N of the pixel pattern unit blocks arranged in the second direction, where M is a natural number and an integer multiple of the K, and N is a natural number and an integer multiple of the L.

US Pat. No. 10,692,941

ORGANIC LIGHT EMITTING DIODE DISPLAY

Shenzhen China Star Optoe...

1. An organic light emitting diode display, comprising a thin film transistor substrate, a white organic light emitting diode layer disposed on one side of the thin film transistor substrate, a quantum dot photoluminescence film disposed on one side of the thin film transistor substrate away from the white organic light emitting diode layer or on one side of the white organic light emitting diode layer away from the thin film transistor substrate and a color filter film disposed on one side of the quantum dot photoluminescence film away from the white organic light emitting diode layer; wherein the quantum dot photoluminescence film is located on a light exit side of the white organic light emitting diode layer;wherein the organic light emitting diode display comprises a plurality of sub-pixels arranged in sequence, and the plurality of sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel;
wherein a region of the quantum dot photoluminescence film corresponding to the red sub-pixel is provided with red quantum dots, and a region corresponding to the green sub-pixel is provided with green quantum dots;
wherein the color filter film comprises a red color resistance, a green color resistance, and a blue color resistance respectively corresponding to the red sub-pixel, the green sub-pixel and the blue sub-pixel;
wherein the color filter film further comprises a second substrate and a second black matrix, and the second black matrix is disposed on the second substrate and are provided with a plurality of second openings corresponding to the plurality of sub-pixels, and the red color resistance, the green color resistance and the blue color resistance are all disposed on the second substrate, and the red color resistance is disposed in the second opening of the second black matrix corresponding to the red sub-pixel, and the green color resistance is disposed in the second opening of the second black matrix corresponding to the green sub-pixel, and the blue color resistance is disposed in the second opening of the second black matrix corresponding to the blue sub-pixel;
wherein the white organic light emitting diode layer comprises an anode, a hole injection layer, a first hole transport layer, a first light emitting layer, a first electron transport layer, a first electron generation layer, a first hole generation layer, a second hole transport layer, a second light emitting layer, a second electron transport layer, a second electron generation layer, a second hole generation layer, a third hole transport layer, a third light emitting layer, a third electron transport layer, an electron injection layer and a cathode, which are sequentially disposed.

US Pat. No. 10,692,940

PIXEL STRUCTURE AND DISPLAY PANEL HAVING THE SAME

KUNSHAN GO-VISIONOX OPTO-...

1. A pixel structure, comprising a plurality of pixel units arranged in an array, the plurality of pixel units being arranged respectively along a first direction and a second direction perpendicular to the first direction, each of the pixel units comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel having different colors;in the second direction, a distance between the third sub-pixels being different from a distance between the first sub-pixels and being different from a distance between the second sub-pixels,
wherein in each pixel unit, a total size of the first sub-pixel and the second sub-pixel is greater than a size of the third sub-pixel in the second direction.

US Pat. No. 10,692,939

MULTI-VIEW DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A multi-view display device comprising:first to third red subpixels, first to third green subpixels and first to third blue subpixels disposed on an array substrate and constituting a single unit pixel;
a red color filter corresponding to the first to third red subpixels, a green color filter corresponding to the first to third green subpixels, a blue color filter corresponding to the first to third blue subpixels, wherein the red, green and blue color filters are on a color filter encapsulation substrate facing the array substrate; and
a black matrix disposed on the color filter encapsulation substrate, having first red, green, and blue openings respectively corresponding to the first red, green, and blue subpixels, and overlapping the second and third red, green, and blue subpixels,
wherein the first to third red subpixels respectively display a first-first view image, a first-second view image, and a first-third view image, the first to third green subpixels respectively display a second-first view image, a second-second view image, and a second-third view image, and the first to third blue subpixels respectively display a third-first view image, a third-second view image, and a third-third view image, and
wherein the first-first view image, the second-first view image, and the third-first view image realize a first view image, the first-second view image, the second-second view image, and the third-second view image realize a second view image, and the first-third view image, the second-third view image, and the third-third view image realize a third view image.

US Pat. No. 10,692,938

LIGHT EMITTING DISPLAY DEVICE SLOPED ELECTRODE

LG Display Co., Ltd., Se...

1. A light emitting display device, comprising:a first pixel on a substrate comprising:
a first sub pixel extending in a horizontal direction, the first sub pixel including:
a first sub pixel thin film transistor (TFT) disposed at a first side of an active area of the first sub pixel, and
a first sub electrode coupled to the first sub pixel TFT, the first sub electrode having a first slope with respect to the substrate in an emission area of the first sub pixel,
wherein the first sub electrode is disposed over the first sub pixel TFT, from the first side of the active area of the first sub pixel to a second side of the active area of the first sub pixel, wherein the second side of the active area of the first sub pixel is opposite to the first side of the active area of the first sub pixel along a vertical direction, and
wherein a distance between the first sub electrode and the substrate at the first side of the active area of the first sub pixel over the first sub pixel TFT is greater than a distance between the first sub electrode and the substrate at the second side of the active area of the first sub pixel,
a second sub pixel extending in the horizontal direction, the second sub pixel next to the first sub pixel in the vertical direction, the second sub pixel including:
a second sub pixel TFT disposed at a second side of the active area of the second sub pixel, and
a second sub electrode coupled to the second sub pixel TFT, the second sub electrode having a second slope with respect to the substrate in an emission area of the second sub pixel, the second slope having a tilting direction opposite to the first slope,
wherein the second sub electrode is disposed over the second sub pixel TFT, from the second side of the active area of the second sub pixel to a first side of the active area of the second sub pixel,
wherein the second side of the active area of the second sub pixel is opposite to the first side of the active area of the second sub pixel along the vertical direction, and
wherein a distance between the second sub electrode and the substrate at the second side of the active area of the second sub pixel over the second sub pixel TFT is greater than a distance between the second sub electrode and the substrate at the first side of the active area of the second sub pixel, and
a third sub pixel extending in the vertical direction, third sub pixel including a third sub electrode coupled to a third sub pixel TFT; and
a second pixel on the substrate and adjacent to the first pixel in the horizontal direction, the second pixel comprising:
a fourth sub pixel extending in the horizontal direction, the fourth sub pixel including:
a fourth sub pixel TFT disposed at a second side of an active area of the fourth sub pixel, and
a fourth sub electrode coupled to the fourth sub pixel TFT, the fourth sub electrode having the second slope with respect to the substrate in an emission area of the fourth sub pixel, the second slope having the tilting direction opposite to the first slope,
wherein the fourth sub electrode is disposed over the fourth sub pixel TFT, from the second side of the active area of the fourth sub pixel to a first side of the active area of the fourth sub pixel, wherein the second side of the active area of the fourth sub pixel is opposite to the first side of the active area of the fourth sub pixel along the vertical direction,
wherein a distance between the fourth sub electrode and the substrate at the second side of the active area of the fourth sub pixel over the fourth sub pixel TFT is greater than a distance between the fourth sub electrode and the substrate at the first side of the active area of the fourth sub pixel, and
wherein the first sub pixel and the fourth sub pixel display different colors,
a fifth sub pixel extending in a horizontal direction, the fifth sub pixel next to the fourth sub pixel in the vertical direction, the fifth sub pixel including:
a fifth sub pixel TFT disposed at a first side of an active area of the fifth sub pixel, and
a fifth sub electrode coupled to the fifth sub pixel TFT, the fifth sub electrode having the first slope with respect to the substrate in an emission area of the fifth sub pixel,
wherein the fifth sub electrode is disposed over the fifth sub pixel TFT, from the first side of the active area of the fifth sub pixel to a second side of the active area of the fifth sub pixel, wherein the second side of the active area of the fifth sub pixel is opposite to the first side of the active area of the fifth sub pixel along a vertical direction, and
wherein a distance between the fifth sub electrode and the substrate at the first side of the active area of the fifth sub pixel over the fifth sub pixel TFT is greater than a distance between the fifth sub electrode and the substrate at the second side of the active area of the fifth sub pixel, and
wherein the first sub pixel and the fifth sub pixel display the same color,
wherein the tilting direction is in the vertical direction.

US Pat. No. 10,692,937

MANUFACTURING METHOD OF OLED DISPLAY PANEL WITH STACKS STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of an OLED display panel, comprising the steps of:forming a first anode layer on a substrate;
forming a conductive layer on the first anode layer, wherein a first end of the conductive layer is electrically connected to the first anode layer;
forming a first pixel defining layer on the periphery of the conductive layer;
covering a second end of the conductive layer with a protective layer;
forming a first OLED pixel layer on the first anode layer;
forming a first cathode layer on the first OLED pixel layer;
forming a second anode layer on the first cathode layer;
forming a second OLED pixel layer on the second anode layer;
removing the protective layer;
forming a second pixel defining layer; and
forming a second cathode layer on the second OLED pixel layer, so that the second cathode layer is electrically connected to the first anode layer through the conductive layer.

US Pat. No. 10,692,936

IMAGE SENSORS

Samsung Electronics Co., ...

1. An image sensor comprising:a substrate, the substrate including a unit pixel region, the unit pixel region including a pixel transistor formation region and at least one pixel region, the substrate including a first surface and a second surface, the first surface and the second surface facing each other, the second surface configured to be a light-incident surface;
a first semiconductor photoelectric conversion element disposed inside the substrate such that the first semiconductor photoelectric conversion element is at least partially enclosed by the substrate;
an organic photoelectric conversion element formed on the second surface of the substrate;
a first floating diffusion region formed on the first surface of the substrate;
a first transfer transistor having a first end connected to the first semiconductor photoelectric conversion element and a second end connected to the first floating diffusion region;
a second transfer transistor having a first end connected to the organic photoelectric conversion element and a second end connected to the first floating diffusion region;
a first penetration electrode connected to the organic photoelectric conversion element, the first penetration electrode including at least a first portion and a second portion, the first portion of the first penetration electrode extending from the first surface of the substrate to the second surface of the substrate;
a first contact extending from the first surface of the substrate in a first direction, the first contact including a first surface and a second surface, the second surface of the first contact facing the first surface of the first contact, the second surface of the first contact is in contact with the first penetration electrode; and
a second contact extending from the first surface of the substrate in the first direction, the second contact including a third surface and a fourth surface, the fourth surface facing the third surface, the fourth surface in contact with a source region of the second transfer transistor,
wherein the at least one pixel region includes a first pixel region, and the first semiconductor photoelectric conversion element, the first floating diffusion region, and the first transfer transistor and the second transfer transistor are in the first pixel region.

US Pat. No. 10,692,935

3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME

CENTER FOR ADVANCED SOFT ...

1. A method of manufacturing a 3D static RAM core cell having a vertically stacked structure containing thin-film transistors, consisting essentially of:(a) forming a first transistor layer including two of the thin-film transistors;
(b) after forming the first transistor layer, forming a second transistor layer including two of the thin-film transistors on the first transistor layer; and
(c) after forming the second transistor layer, forming a third transistor layer including two of the thin-film transistors on the second transistor layer,
wherein the step (a) consists of:
(a-1) forming a first source electrode and a first drain electrode on a substrate through printing;
(a-2) forming a first electrode channel film comprising a first organic semiconductor between the first source electrode and the first drain electrode through printing;
(a-3) forming a first insulating film on the first electrode channel film through deposition; and
(a-4) forming a first gate electrode on the first insulating film through printing,
wherein the first electrode channel film, the first insulating film, and the first gate electrode are sequentially disposed upwards,
the step (b) consists of:
(b-1) forming a second source electrode and a second drain electrode on the first transistor layer through printing;
(b-2) forming a second electrode channel film comprising a second organic semiconductor between the second source electrode and the second drain electrode through printing;
(b-3) forming a second insulating film on the second electrode channel film through deposition; and
(b-4) forming a second gate electrode on the second insulating film through printing,
wherein, the second electrode channel film, the second insulating film, and the second gate electrode are sequentially disposed upwards,
the step (c) consists of:
(c-1) forming a third insulating film on the second gate electrode through deposition;
(c-2) forming a third source electrode and a third drain electrode on the third insulating film through printing; and
(c-3) forming a third electrode channel film comprising a third organic semiconductor between the third source electrode and the third drain electrode through printing,
wherein, the third electrode channel film and the third insulating film are sequentially disposed downwards, and
at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other.

US Pat. No. 10,692,934

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device, comprising:a first conductive layer;
a second conductive layer, a direction from the first conductive layer toward the second conductive layer being aligned with a first direction; and
a first layer provided between the first conductive layer and the second conductive layer,
the first layer including
a first region including titanium and oxygen,
a second region including aluminum and oxygen and being provided between the first conductive layer and the first region, and
a third region including aluminum and oxygen and being provided between the first region and the second conductive layer,
a surface area in a first plane of a brookite region included in the first region being 58 percent or more of a surface area in the first plane of the first region, the first plane crossing the first direction.

US Pat. No. 10,692,933

VARIABLE RESISTANCE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

11. A variable resistance memory device, comprising:a plurality of stacked structures each including a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another, wherein each of the plurality of stacked structures has a U-shape;
a mold pattern filling a space between the plurality of stacked structures; and
a selection pattern on the middle electrode of each of the plurality of stacked structures,
wherein an upper portion of the mold pattern includes a surface treated layer and a lower portion of the mold pattern include a non-surface treated layer.

US Pat. No. 10,692,932

METHOD TO FORM MEMORY CELLS SEPARATED BY A VOID-FREE DIELECTRIC STRUCTURE

Taiwan Semiconductor Manu...

1. An integrated chip comprising:a pair of wires;
a first memory cell structure and a second memory cell structure over the wires;
an inter-cell filler layer separating the first and second memory cell structures and having a top surface recessed below a top surface of the first memory cell structure, wherein the inter-cell filler layer is on a first side of the first memory cell structure facing the second memory cell structure, but is not on a second side of the first memory cell structure opposite the first side; and
an interconnect dielectric layer overlying the first and second memory cell structures and the inter-cell filler layer, and further extending towards the top surface of the inter-cell filler layer to below the top surface of the first memory cell structure.

US Pat. No. 10,692,931

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Icheon (K...

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:stack structures, each of the stack structures including a memory pattern;
a gap-fill layer filling spaces between the stack structures;
a protective layer interposed between the stack structures and the gap-fill layer; and
nanopores located in the gap-fill layer and the protective layer, the nanopores being distributed in a portion of the gap-fill layer and a portion of the protective layer that are located at a level corresponding to where the memory pattern is located in each of the stack structures,
wherein the gap-fill layer includes a material having an etch selectivity that is higher than that of the protective layer.

US Pat. No. 10,692,930

SELF-ALIGNED CROSS-POINT PHASE CHANGE MEMORY-SWITCH ARRAY

Micron Technology, Inc., ...

1. A memory device comprising:a plurality of memory structures, each memory structure of the plurality of memory structures comprising a phase change memory layer between a first memory electrode layer and a second memory electrode layer, and the phase change memory layer and the second memory electrode layer being isolated from neighboring memory structures in a first direction and a second direction, wherein the first memory electrode layer has a same width as an electrically conductive line of a first plurality of electrically conductive lines extending in the first direction, and wherein the electrically conductive line directly contacts the first memory electrode layer; and
a plurality of switch structures over the plurality of memory structures, each switch structure of the plurality of switch structures comprising a switch layer that comprises a chalcogenide material and is isolated from neighboring switch structures in the first direction and the second direction, wherein the switch layer has a same width as the electrically conductive line of the first plurality of electrically conductive lines extending in the first direction.

US Pat. No. 10,692,929

INTEGRATED CIRCUIT INCLUDING RESISTIVE RANDOM-ACCESS MEMORY CELL AND RESISTOR CELL AND FORMING METHOD THEREOF

United Semiconductor (Xia...

1. An integrated circuit comprising a resistive random-access memory cell and a resistor cell, comprising:a substrate having a resistive random-access memory area and a resistor area;
a first dielectric layer and a second dielectric layer sequentially disposed on the substrate;
a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer;
a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby the patterned stacked structure in the resistive random-access memory area constituting the resistive random-access memory cell;
a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby the patterned stacked structure in the resistor area constituting the resistor cell; and
a cap layer covering the patterned stacked structure.

US Pat. No. 10,692,928

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:forming a dummy gate on a substrate;
forming a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate;
forming a first source/drain region between the dummy gate and the first control gate; and
performing a treatment process so that a threshold voltage of the dummy gate is greater than a threshold voltage of the first control gate, wherein the treatment process comprises:
forming a doped region directly under the dummy gate, wherein a top surface of the doped region is lower than a bottom surface of the first source/drain region.

US Pat. No. 10,692,927

DOUBLE MTJ STACK WITH SYNTHETIC ANTI-FERROMAGNETIC FREE LAYER AND ALN BOTTOM BARRIER LAYER

International Business Ma...

1. A double magnetic tunnel junction (MTJ) stack comprising:a bottom tunnel barrier layer having hexagonal symmetry and composed of AlN located on a bottom magnetic pinned layer;
a magnetic free layer stack located on the bottom tunnel barrier layer, wherein the magnetic free layer stack comprises a first magnetic layer, a synthetic anti-ferromagnetic coupling layer, and a second magnetic layer;
a top tunnel barrier layer having cubic symmetry located on the second magnetic layer of the magnetic free layer stack; and
a top magnetic pinned layer located on the top tunnel barrier layer.

US Pat. No. 10,692,926

MAGNETORESISTIVE STACK WITH SEED REGION AND METHOD OF MANUFACTURING THE SAME

Everspin Technologies, In...

1. A magnetoresistive stack comprising:a seed region disposed at least partially on an electrically conductive material, wherein the seed region includes:
a plurality of alloy layers, wherein each alloy layer of the plurality of alloy layers includes nickel and chromium; and
a plurality of auxiliary layers;
a fixed magnetic region disposed above the seed region, wherein the fixed magnetic region includes a synthetic antiferromagnetic structure comprising:
a first ferromagnetic region disposed above the seed region;
a coupling layer disposed on and in contact with the first ferromagnetic region; and
a second ferromagnetic region disposed on and in contact with the coupling layer;
one or more dielectric layers disposed on and in contact with the second ferromagnetic region; and
a free magnetic region disposed above the one or more dielectric layers.

US Pat. No. 10,692,925

DIELECTRIC FILL FOR MEMORY PILLAR ELEMENTS

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, comprising:forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar; and
depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry.

US Pat. No. 10,692,924

ADVANCED PROCESSING APPARATUS COMPRISING A PLURALITY OF QUANTUM PROCESSING ELEMENTS

NewSouth Innovations Pty ...

1. An advanced processing apparatus, comprising:a plurality of quantum processing elements arranged in a 2D matrix; each processing element comprising silicon and a dielectric material forming an interface and an electrode arrangement suitable to confine one or more electrons or holes in the silicon, for each quantum processing element, to form a quantum dot operable as a qubit;
a plurality of interconnected control members forming a matrix of control members; each control member comprising a silicon metal-oxide-semiconductor transistor disposed above a respective quantum processing element and configured to interact with the electrode arrangement to perform quantum operations with the processing element; and
a plurality of control lines; each control line being connected to a plurality of control members via the metal-oxide-semiconductor transistors to enable simultaneous operation of a plurality of processing elements.

US Pat. No. 10,692,923

SYSTEMS AND METHODS FOR TRANSFER OF MICRO-DEVICES

Applied Materials, Inc., ...

1. A method of transferring micro-devices to a destination substrate, comprising:selectively dispensing adhesive onto selected micro-devices on a donor substrate based on a desired spacing of the selected micro-devices on the destination substrate such that droplets of adhesive are ejected onto less than all of the micro-devices on the donor substrate, wherein selectively dispensing adhesive comprises ejecting droplets of adhesive onto the micro-devices;
engaging the adhesive on the donor substrate with a transfer surface to cause the selected micro-devices to adhere to the transfer surface; and
transferring each of the selected micro-devices from the donor substrate to the destination substrate using the transfer surface and in accordance to the desired spacing of the selected micro-devices on the destination substrate, wherein transferring the selected micro-devices includes:
withdrawing the transfer surface from the donor substrate such that the selected micro-devices detach from the donor substrate and remain adhered by the adhesive to the transfer surface,
lowering the transfer surface toward the destination substrate so that the selected micro-devices engage the destination substrate, and
withdrawing the transfer surface from the destination substrate with the selected micro-devices remaining on the destination substrate.

US Pat. No. 10,692,922

PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND EQUIPMENT

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion device, comprising:a photoelectric converter arranged in a semiconductor substrate made of silicon; and
a transistor arranged on a surface of the semiconductor substrate, wherein
the photoelectric converter includes a first region which is of a first conductivity type and is configured to accumulate charges and a second region of a second conductivity type different from the first conductivity type, and the first region is arranged between the surface and the second region,
the semiconductor substrate includes a third region which functions as a source and/or a drain of the transistor,
the semiconductor substrate includes, in a position which is below the third region and is apart from the third region, an impurity region containing a group 14 element other than silicon, and
a depth from the surface, of a peak position in a density distribution of the group 14 element in the impurity region is smaller than a depth from the surface, of a peak position in a density distribution of a majority carrier in the second region.

US Pat. No. 10,692,921

METHOD OF MANUFACTURING AN IMAGER AND IMAGER DEVICE

Infineon Technologies AG,...

1. A method of manufacturing a depth imager, comprising:providing a substrate having a light-sensitive area;
forming on the substrate a metal layer stack; and
depositing a passivation layer onto the metal layer stack, the passivation layer extending at least in an area over the light-sensitive area,
wherein the passivation layer has a matched reduced thickness in the light-sensitive area to provide anti-reflective behavior with respect to the light-sensitive area.

US Pat. No. 10,692,920

INTEGRATED CIRCUITS WITH IMAGE SENSORS AND METHODS FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:a photodetector comprising an impingement photodetector well and a base photodetector well;
a transfer transistor overlying the photodetector, wherein the transfer transistor comprises a transfer gate, a source, and a drain; and
a source contact electrically connected to the source, wherein the source contact is also electrically connected to the photodetector.

US Pat. No. 10,692,919

SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A solid-state imaging element, comprising:a pixel array comprising a plurality of pixels,
wherein each pixel of the plurality of pixels comprises:
a photoelectric conversion region configured to generate a charge by photoelectric conversion based on an amount of incident light;
a charge accumulation region configured to accumulate the charge generated by the photoelectric conversion region; and
a charge voltage conversion region configured to convert the accumulated charge into a voltage,
wherein a center of the photoelectric conversion region is shifted from a center of the charge accumulation region;
a pixel transistor configured to output a pixel signal based on the voltage converted by the charge voltage conversion region; and
a plurality of electrodes configured to form a transfer gradient to transfer the charge accumulated in the charge accumulation region, wherein
a plurality of connection terminals associated with the plurality of electrodes are in a column of the pixel array, and
the column comprises the charge voltage conversion region and the pixel transistor.

US Pat. No. 10,692,918

ELECTRONIC DEVICE PACKAGE AND FABRICATING METHOD THEREOF

Amkor Technology, Inc., ...

1. A sensor device comprising:a semiconductor die comprising a first die side, a second die side opposite the first die side, and lateral die sides extending between the first and second die sides, where the first die side comprises sensor circuitry and a bond pad;
a lateral structure that laterally covers a first lateral die side of the lateral die sides, wherein the lateral structure comprises first dielectric material (DM1) that comprises a first DM1 side, a second DM1 side, and lateral DM1 sides extending between the first and second DM1 sides;
a conductive via structure passing through the first dielectric material;
first conductive path extending over the first die side and over the first DM1 side, and coupled to the bond pad and to a first via end of the conductive via structure;
second conductive path coupled to a second end of the conductive via structure; and
a first dielectric structure that covers the first die side and the first DM1 side, wherein the first dielectric structure comprises:
a first aperture that extends through the first dielectric structure and through which the first conductive path is coupled to the bond pad; and
a second aperture that extends through the first dielectric structure and through which the first conductive path is coupled to the first via end.

US Pat. No. 10,692,917

SENSOR PACKAGE STRUCTURE

KINGPAK TECHNOLOGY INC., ...

1. A sensor package structure, comprising:a substrate having an upper surface and a lower surface opposite to the upper surface, wherein the substrate includes a plurality of welding pads formed on the upper surface;
a sensor chip and a chip-bonding adhesive, wherein the sensor chip has a top surface, a bottom surface opposite to the top surface, and a lateral side arranged between the top surface and the bottom surface, the bottom surface of the sensor chip is entirely adhered to the upper surface of the substrate through the chip-bonding adhesive, and the chip-bonding adhesive protrudes from the lateral side of the sensor chip so as to ensure no bubble generated between the bottom surface of the sensor chip and the upper surface of the substrate, and wherein the top surface has a sensing region and a spacing region arranged around the sensing region, the top surface has a plurality of edges, and the sensor chip includes a plurality of connecting pads formed on a portion of the top surface between the spacing region and at least one of the edges;
a plurality of metal wires, wherein one ends of the metal wires are respectively connected to the welding pads, and the other ends of the metal wires are respectively connected to the connecting pads, wherein each of the metal wires has a diameter within a range of 0.8-1.1 mil, and includes:
a first segment connected to the corresponding welding pad; and
a second segment connected to the corresponding connecting pad, wherein in each of the metal wires, the second segment integrally and curvedly extends from an end of the first segment away from the corresponding welding pad, and the second segment and the top surface of the sensor chip have a sloping angle there-between that is within a range of 5-45 degrees,
wherein a portion of each of the welding pads connected to the first segment of the corresponding metal wire is spaced apart from the lateral side of the sensor chip by a distance that is within a range of 210-660 ?m so as to allow the welding pads being spaced apart from the chip-bonding adhesive;
a combining layer disposed on the portion of the top surface between the at least one of the edges of the top surface and the spacing region, wherein a part of the second segment of each of the metal wires is embedded in the combining layer;
a light-permeable layer having a first surface and a second surface opposite to the first surface, a portion of the second surface of the light-permeable layer being adhered to the combining layer, wherein the second surface has a fixing region arranged outside the portion of the second surface adhered to the combining layer, and a projecting area defined by orthogonally projecting the sensor chip onto the second surface is entirely located in the second surface; and
a packaging compound disposed on the upper surface of the substrate and covering the lateral side of the sensor chip, a lateral side of the combining layer, and a lateral side and the fixing region of the light-permeable layer, wherein the first segment and the other part of the second segment of each of the metal wires and each of the welding pads are embedded in the packaging compound.

US Pat. No. 10,692,916

IMAGE-CAPTURING UNIT AND IMAGE-CAPTURING APPARATUS

NIKON CORPORATION, Tokyo...

1. An image-capturing unit comprising:an image-capturing chip that includes a photoelectric converter that converts light to electrical charges;
an electronic component for feeding electrical power for driving the image-capturing chip;
wiring to which the electrical power fed to the image-capturing chip from the electronic component is outputted;
an adjusting unit that is provided to the wiring, and adjusts an electrical current flowing from the electronic component to the image-capturing chip so that the electrical current becomes smaller when a leakage current of the image-capturing chip is being measured, as compared to when the leakage current of the image-capturing chip is not being measured; and
a substrate that has a first surface on which the image-capturing chip is arranged and a second surface, opposite the first surface, on which the electronic component, the wiring, and the adjusting unit are arranged.

US Pat. No. 10,692,915

IMAGING DEVICE AND METHOD OF MANUFACTURING IMAGING DEVICE

CANON KABUSHIKI KAISHA, ...

1. An imaging device comprising:a first substrate including a photoelectric conversion layer which includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type and in which a plurality of photoelectric conversion units are provided;
a second substrate which is joined to the first substrate and in which a readout circuit that outputs a signal based on information detected by the plurality of photoelectric conversion units is provided; and
an element isolation portion defined by a first opening provided so as to penetrate the second substrate and at least one of the first semiconductor layer and the second semiconductor layer,
wherein each of the plurality of photoelectric conversion units is separated from each other by the element isolation portion.

US Pat. No. 10,692,914

IMPLANT DAMAGE FREE IMAGE SENSOR AND METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. An image sensor, comprising:an epitaxial layer having a front side and a back side;
an interconnect structure at the front side of the epitaxial layer;
a color filter layer in physical contact with the back side of the epitaxial layer;
a plurality of plug structures formed in the epitaxial layer, the plug structures extending to a higher level than the front side of the epitaxial layer and in physical contact with the interconnect structure at one end, and being level with the back side of the epitaxial layer and in physical contact with the color filter at the other end; and
a plurality of doped regions in the epitaxial layer and conformally around the plug structures respectively, all the doped regions being of the same type of doping.

US Pat. No. 10,692,913

PHOTOELECTRIC CONVERSION ELEMENT, IMAGE PICKUP ELEMENT, LAMINATED IMAGE PICKUP ELEMENT, AND IMAGE PICKUP DEVICE

SONY CORPORATION, Tokyo ...

1. An image pickup element, comprising:at least an anode, a carrier blocking layer, an organic photoelectric conversion layer, and a cathode laminated in order, wherein
the organic photoelectric conversion layer includes an organic semiconductor material, and
the carrier blocking layer includes:
a part of the organic semiconductor material; and
a specific material having the following structural formula (1):

US Pat. No. 10,692,912

OPTICAL DEVICE FOR EXPOSURE OF A SENSOR DEVICE FOR A VEHICLE

1. An optical device for exposure of a sensor device for a vehicle with an optical structure which comprises an arrangement of optical micro elements in order to bundle incident light by the optical micro elements and direct the light to sensor elements of the sensor device respectively, wherein the optical structure is configured such that light which is directed to the sensor elements is concentrated for light active areas of the sensor elements, wherein the sensor device is electrically connected with a control or evaluation device and is controlled in a clocked manner such that time-of-flight recordings are performed,wherein a detection area (5) is monitored by the sensor device, wherein the detection area (5) is located outside the vehicle (1), in order to determine a proximity and a gesture of a user (4) and wherein in case of a detection of the proximity and the gesture of the user, a function of the vehicle (2) is triggered,
wherein the gesture detection is conducted by the control or evaluation device based on image information captured by the sensor device,
wherein the proximity detection is a distance detection performed by measurement of the time of flight of the light, conducted by the control or evaluation device through a synchronized activation of a light source and the sensor device (10), and
wherein recognition and evaluation of gestures of the user (4) is conducted by acquisition and comparison of a plurality of images, the images acquisition is initiated by the sensor device (10) caused by an approach of the user (4) or by a detection of an identification device (6).

US Pat. No. 10,692,911

POLARIZERS FOR IMAGE SENSOR DEVICES

Taiwan Semiconductor Manu...

1. A composite grid structure, comprising:a first group of cells comprising a first color filter;
a second group of cells comprising a second color filter different from the first color filter;
a third group of cells comprising a third color filter different from the first and second color filters, wherein cells from the first, second, and third groups are disposed next to each other;
a first cell comprising first grating elements aligned at a first angle;
a second cell comprising second grating elements aligned at a second angle;
a third cell comprising third grating elements aligned at a third angle; and
a fourth cell comprising fourth grating elements aligned at a fourth angle, wherein each of the first, second, third, and fourth angles are different from each other and wherein the first, second, third, or fourth cells are disposed between the cells of the first, second, and third groups.

US Pat. No. 10,692,910

SOLID-STATE IMAGING ELEMENT AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A solid-state imaging element, comprising:a plurality of pixels;
a photoelectric conversion unit for each pixel of the plurality of pixels, wherein the photoelectric conversion unit is configured to convert incident light into a charge;
a charge storage unit configured to temporarily hold the charge;
a first light shielding unit between the plurality of pixels and having a determined length in a thickness direction of a substrate, wherein
the charge storage unit is below a cross portion where the first light shielding unit between a plurality of first pixels adjacent to each other in a longitudinal direction crosses the first light shielding unit between a plurality of second pixels adjacent to each other in a lateral direction; and
a second light shielding unit covering a light incident surface side of the cross portion.

US Pat. No. 10,692,909

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND CAMERA WITH ALTERNATIVELY ARRANGED PIXEL COMBINATIONS

Sony Semiconductor Soluti...

1. An imaging device, comprising:a pixel array including a plurality of sub-arrays, respective ones of the plurality of sub-arrays including four pixels arranged in a 2×2 matrix, respective ones of the pixels including a photodiode and a transfer transistor; and
a plurality of on-chip lenses, wherein
each pixel of a first sub-array of the plurality of sub-arrays and a second sub-array of the plurality of sub-arrays includes a green-light-transmitting filter,
each pixel of a third sub-array of the plurality of sub-arrays includes a blue-light-transmitting filter,
each pixel of a fourth sub-array of the plurality of sub-arrays includes a red-light-transmitting filter,
the first sub-array is disposed diagonally to the second sub-array,
the third sub-array is disposed diagonally to the fourth sub-array, and
each of the plurality of on-chip lenses is disposed corresponding to the respective ones of pixels in each of the first, second, third, and fourth sub-arrays.

US Pat. No. 10,692,908

CMOS IMAGE SENSOR ENCAPSULATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Pioneer Materials Inc. Ch...

1. A method for manufacturing a CMOS image sensor encapsulation structure, comprising:forming a blind hole in a combined layer formed by a first insulating layer and a wafer, wherein the blind hole passes through the first insulating layer with its hole bottom located on the wafer, and a surface of the first insulating layer facing away from the wafer has a micro convex lens;
forming a second insulating layer on a hole wall of the blind hole, then filling an electrically conductive material in the blind hole having the second insulating layer, and making a conductor in the combined layer extend to a surface of the first insulating layer to be electrically connected to the electrically conductive material, with the conductor in signal connection with the micro convex lens and an IC; and
fixing a transparent substrate material on a surface of the first insulating layer, with the surface having the micro convex lens, forming a dummy wafer on a surface of the transparent substrate material, and then thinning the wafer by grinding such that the electrically conductive material in the blind hole is exposed,
wherein the dummy wafer is formed on a side of the first insulating layer, with the side away from the wafer, and the dummy wafer is fixed to the transparent substrate material.

US Pat. No. 10,692,907

CMOS IMAGE SENSOR ENCAPSULATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Pioneer Materials inc. Ch...

1. A method for manufacturing a CMOS image sensor encapsulation structure, comprising:forming a blind hole in a combined layer formed by a first insulating layer and a wafer, wherein the blind hole passes through the first insulating layer with its hole bottom located on the wafer, a surface of the first insulating layer is provided with a micro convex lens, with the surface facing away from the wafer;
areas where the micro convex lens and the blind hole are located are a first installation area and a second installation area, respectively, the first installation area and the second installation area do not overlap each other;
forming a second insulating layer on a hole wall of the blind hole, filling an electrically conductive material in the blind hole having the second insulating layer, and making a conductor in the combined layer extend to the surface of the first insulating layer to be electrically connected to the electrically conductive material, with the conductor in signal connection with the micro convex lens and an IC;
fixing a transparent substrate material on the surface of the first insulating layer, with the surface having the micro convex lens, and providing the transparent substrate material in the first installation area, wherein the transparent substrate material is fixed to a surface of the first insulating layer by a light-transmissive adhesive glue;
forming a dummy wafer on a surface of the transparent substrate material, and thinning the wafer by grinding such that the electrically conductive material in the blind hole is exposed; and
forming a third insulating layer on a surface of the wafer that is thinned by grinding and exposing the electrically conductive material, forming metal projections on the third insulating layer and electrically connecting the metal projections to the electrically conductive material, fixing solder balls on the metal projections, and after removing the dummy wafer, forming a protection glue layer on the first insulating layer, wherein the protection glue layer is located in the second installation area.

US Pat. No. 10,692,906

CAMERA

Axis AB, Lund (SE)

1. A camera comprising:a sensor holder;
an image sensor mounted on the sensor holder;
a mount holder; and
a lens mount being adapted to receive a lens array and being mounted to the mount holder,
wherein the sensor holder is attached to the mount holder,
wherein a gap having an extension along an optical axis of the camera is defined between the sensor holder and the lens mount, and
wherein the sensor holder is provided with a thermally conducting protrusion bridging the gap and contacting the lens mount at an interface allowing relative motion along the optical axis between the lens mount and the thermally conducting protrusion while maintaining contact between the lens mount and the thermally conducting protrusion.

US Pat. No. 10,692,905

OPTICAL COMPONENT, OPTICAL ASSEMBLY AND OPTICAL MODULE

AZUREWAVE TECHNOLOGIES, I...

1. An optical module, comprising:an electronic assembly including a chip component and a circuit board; and
an optical assembly disposed on the electronic assembly, including a bracket and an optical component, the bracket surrounding the chip component and including at least two conductive layers separated from each other, the conductive layers extending to the bottom of the bracket and being electrically connected to the electronic assembly, the optical assembly being disposed on the bracket and including at least one light-transmissive conductive layer which is electrically connected to the conductive layers;
wherein the optical component further includes an optical component body, the at least one light-transmissive conductive layer is disposed on one of the upper surface and the lower surface of the optical component body, and the at least one light-transmissive conductive layer includes two conductive ends disposed at two sides of the optical component body, respectively; and the conductive layers are configured on one of the outer surface, the inner surface, and the interior of the bracket; wherein the at least one light-transmissive conductive layer is electrically disconnected from the conductive layers when the optical component is detached from the bracket.

US Pat. No. 10,692,904

SOLID-STATE IMAGE SENSING DEVICE, DRIVE METHOD, AND ELECTRONIC APPARATUS

SONY SEMICONDUCTOR SOLUTI...

1. An imaging device, comprising:a first photoelectric conversion region in a semiconductor substrate, the first photoelectric conversion region being electrically coupled to a first amplification transistor at a first surface of the semiconductor substrate; and
a second photoelectric conversion region in the semiconductor substrate, the second photoelectric conversion region being electrically coupled to a second amplification transistor at the first surface of the semiconductor substrate, wherein
the first photoelectric conversion region is between a part of the second photoelectric conversion region and the first surface of the semiconductor substrate, and
at least one of the first photoelectric conversion region and the second photoelectric conversion region is divided into two portions in a plan view.

US Pat. No. 10,692,903

COLOR FILTER FOR IMAGE SENSOR, IMAGE SENSOR, AND METHOD OF MANUFACTURING COLOR FILTER FOR IMAGE SENSOR

FUJIFILM Corporation, To...

1. A color filter for an image sensor comprising:two or more absorbing color filters that absorb light components having different wavelength ranges;
a cholesteric reflecting layer in which a right circularly polarized light cholesteric layer having right circularly polarized light reflecting properties and a left circularly polarized light cholesteric layer having left circularly polarized light reflecting properties are laminated; and
a microlens provided between the absorbing color filters and the cholesteric reflecting layer;
wherein a gap between the absorbing color filters and the cholesteric reflecting layer is 100 ?m or less.

US Pat. No. 10,692,902

IMAGE SENSING DEVICE AND IMAGE SENSING METHOD

Eagle Vision Tech Limited...

1. An image sensing device, comprising:an image sensing array, partitioned into at least two or more first pixel capturing areas, wherein each of the first pixel capturing areas is compliant with a resolution of a standard-definition television format or compliant with a resolution of a conventional surveillance camera;
a plurality of first signal converters, wherein each of the first signal converters is coupled to a corresponding first pixel capturing area of the first pixel capturing areas, receives an analog image signal from the corresponding first pixel capturing area, converts the analog image signal in an analog format into a first digital image signal in a digital format, and converts the first digital image signal from a parallel format into a serial format; and
a plurality of first image processing apparatuses, wherein each of the first image processing apparatuses is coupled to a corresponding first signal converter of the first signal converters and converts the first digital image signal in the serial format of the corresponding first signal converter into a video signal compliant with a specific video format,
wherein each image sensing array captures an image based on a temporal sequence compliant with the standard-definition television format.

US Pat. No. 10,692,901

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

HKC CORPORATION LIMITED, ...

1. A manufacturing method of an array substrate, comprising steps of:providing a first substrate;
providing a first mask and arranging active switches on the first substrate;
providing a second mask and forming a photoresist layer on the active switches and then sequentially performing steps of:
performing a first wet etching on the active switches,
performing a first ashing treatment on the photoresist layer,
performing a first dry etching on the active switches,
performing a second wet etching on the active switches,
performing a second ashing treatment on the photoresist layer, and
performing a second dry etching on the active switches;
providing a third mask and forming a protective layer on a metal layer of the active switches;
providing a fourth mask and forming a pixel electrode layer on the protective layer;
wherein the steps of providing a first mask and arranging active switches on the first substrate comprise:
depositing a gate electrode layer on the first substrate;
depositing an insulating layer on the gate electrode layer;
depositing an amorphous silicon layer on the insulating layer;
depositing an ohmic contact layer on the amorphous silicon layer;
depositing the metal layer on the ohmic contact layer;
wherein the protective layer comprises a first protective layer and a second protective layer; the insulating layer, the amorphous silicon layer and the ohmic contact layer constitute a combination layer; the first protective layer is disposed between the combination layer and the metal layer, and the second protective layer is disposed on the metal layer.

US Pat. No. 10,692,900

METHOD OF MANUFACTURING ARRAY SUBSTRATE AND DISPLAY PANEL

HKC CORPORATION LIMITED, ...

1. A method of manufacturing array substrate, comprising steps of:sequentially forming a gate electrode, a gate insulation layer, a semiconductor layer and a metal layer on a substrate sequentially;
coating a photoresist on the metal layer and forming an non-exposure area, a partial exposure area and a full exposure area through exposure and developing;
performing a first ashing treatment to remove photoresist in the partial exposure area, and uncover the metal layer corresponding to the partial exposure area;
performing a wet etching to the uncovered metal layer of the partial exposure area to form a metal layer recess and uncover the semiconductor layer, and some of residual photoresist in the metal layer recess being formed;
performing a second ashing treatment to etch off the residual photoresist which remains in the metal layer recess after the first ashing treatment; and
performing a dry etching to form a pattern of a thin film transistor channel region.

US Pat. No. 10,692,899

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a first substrate comprising a display area and a non-display area;
a dummy color layer disposed on the first substrate in the non-display area;
an organic layer disposed on the dummy color layer, the organic layer covering an upper surface of the dummy color layer, and a first side surface and a second side surface of the dummy color layer, the first side surface facing the second side surface;
a light-blocking pattern disposed on the organic layer and the first substrate in the non-display area, the light-blocking pattern comprising an opening part overlapping the dummy color layer;
a sealing member disposed on the light-blocking pattern in the non-display area;
a common voltage line disposed between the dummy color layer and the light-blocking pattern, a portion of the common voltage line exposed by the opening part; and
a second substrate disposed on the sealing member;
wherein the sealing member overlaps the opening part and the dummy color layer,
wherein the opening part, and the dummy color layer and the sealing member are each formed as a continuous line shape extending lengthwise in a direction along an edge of the display area,
wherein the organic layer directly contacts the first side surface and the second side surface of the dummy color layer,
wherein the light-blocking pattern is disposed between the organic layer and the sealing member,
wherein an upper surface of the organic layer faces the sealing member,
wherein the common voltage line directly contacts the upper surface of the organic layer, and
wherein the light-blocking pattern directly contacts the common voltage line and a portion of the upper surface of the organic layer.

US Pat. No. 10,692,898

DISPLAY PANEL AND DISPLAY DEVICE

HKC CORPORATION LIMITED, ...

1. A display panel, comprising an array substrate, wherein the array substrate comprises:a source driver, which is disposed at a first end of the array substrate;
a gate driver, which is disposed at a second end of the array substrate, wherein the second end is opposite to the first end;
a plurality of spaced-apart data lines, wherein the plurality of spaced-apart data lines are respectively connected to the source driver;
a plurality of spaced-apart scan lines, wherein the plurality of spaced-apart scan lines intersect with the plurality of spaced-apart data lines respectively; and
a plurality of spaced-apart connecting lines, wherein the plurality of spaced-apart connecting lines are respectively connected to one of the spaced-apart scan lines;
lengths of the plurality of spaced-apart connecting lines gradually increase from a first side of the array substrate to a second side of the array substrate, the plurality of spaced-apart connecting lines are sequentially connected with the plurality of spaced-apart scan lines from the first side of the array substrate, and the first side is opposite to the second side;
the plurality of spaced-apart connecting lines are arranged in parallel with each other; the plurality of spaced-apart connecting lines and the plurality of spaced-apart data lines are arranged in parallel; each of the spaced-apart connecting lines is disposed between two adjacent data lines;
the display panel comprises a first conductive layer and a second conductive layer; the spaced-apart scan lines are located at the first conductive layer; the spaced-apart connecting lines are disposed at the second conductive layer; conductive holes are formed in the positions where the spaced-apart connecting lines and the corresponding spaced-apart scan line intersect; and the spaced-apart connecting lines are electrically connected with the corresponding spaced-apart scan line through the conductive holes;
the spaced-apart data line comprises a first data line and a second data line which are adjacent, the spaced-apart connecting line comprises a first connecting line, the spaced-apart scan line comprises a first scan line, the array substrate comprises a first active switch and a first pixel, and the first active switch is respectively coupled to the first scan line, the first data line, and the first pixel; the first active switch and the first pixel are disposed between the first data line and the second data line, the first connecting line is connected to the first scan line, and the first connecting line is disposed between the first pixel and the second data line;
a pin of the source driver is bound to the edge of the array substrate; and a length of the gate driver is less than or equal to that of a display area in the display panel.

US Pat. No. 10,692,897

FLEXIBLE DISPLAY HAVING SPACER DISPOSED BETWEEN TWO ADJACENT THIN FILM TRANSISTORS AND HAVING WIRE DISPOSED IN SPACER FOR ELECTRICAL CONNECTION BETWEEN THE TRANSISTORS

WUHAN CHINA STAR OPTOELEC...

9. A flexible display, comprising:a substrate;
a plurality of thin film transistors spacedly arranged apart from each other and disposed along a first direction on the substrate;
a plurality of spacers spacedly arranged apart from each other and disposed along the first direction on the substrate, wherein each of the spacers is disposed between two adjacent thin film transistors; and
at least one wire configured to electrically connect the two adjacent thin film transistors, wherein the at least one wire is disposed in a corresponding spacer.

US Pat. No. 10,692,896

DISPLAY PANEL HAVING LIQUID CRYSTAL CAPACITOR AND SIGNAL LINES

Samsung Display Co., Ltd....

1. A display panel, comprising:a first signal line extending in a first direction;
a second signal line extending in the first direction and spaced apart from the first signal line when viewed in a plan view;
a third signal line insulated from and crossing the first signal line and the second signal line, the third signal line extending in a second direction crossing the first direction;
a first thin-film transistor connected to the first signal line;
a second thin-film transistor connected to the second signal line; and
a first liquid crystal capacitor and a second liquid crystal capacitor arranged in the first direction and respectively connected to the first thin-film transistor and the second thin-film transistor,
wherein each of the first liquid crystal capacitor and the second liquid crystal capacitor comprises a pixel electrode, a common electrode, and a liquid crystal layer,
wherein each of the pixel electrodes of the first liquid crystal capacitor and the second liquid crystal capacitor comprises:
a vertical portion extending in the first direction;
a horizontal portion connected to the vertical portion, the horizontal portion extending in the second direction; and
a plurality of branch portions, each of which is connected to the horizontal portion or the vertical portion, the plurality of branch portions extending in a direction crossing the horizontal portion and the vertical portion, and
wherein each of the first signal line and the second signal line overlaps, when viewed in a plan view, the pixel electrode of the first liquid crystal capacitor and is disposed closer to the vertical portion than to an outer edge of the pixel electrode of the first liquid crystal capacitor in the second direction.

US Pat. No. 10,692,895

ARRAY SUBSTRATES, DISPLAY PANELS, AND DISPLAY APPARATUSES

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a first signal line;
a second signal line;
a first Thin Film Transistor (TFT) electrically connected to the first signal line and the second signal line; and
a second TFT electrically connected to the first signal line and the second signal line;
wherein the first TFT comprises:
a first conductive layer; and
a second conductive layer configured to be electrically connected to the first conductive layer through a first via hole and to be at least partly overlapped with the first conductive layer, wherein the first via hole is located in a first region where the second conductive layer is overlapped with the first conductive layer; and
wherein the second TFT comprises:
a third conductive layer; and
a fourth conductive layer configured to be electrically connected to the third conductive layer through a second via hole and to be at least partly overlapped with the third conductive layer, wherein the second via hole is located in a second region where the fourth conductive layer is overlapped with the third conductive layer;
wherein the first conductive layer is connected to the first signal line, and the third conductive layer is connected to the second signal line,
wherein the first TFT has a gate located in the first conductive layer, a source located in the second conductive layer, and a drain located in the fourth conductive layer, and
wherein the second TFT has a gate located in the third conductive layer, a drain located in the second conductive layer, and a source located in the fourth conductive layer.

US Pat. No. 10,692,894

OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a pixel portion comprising a transistor,
the transistor comprising:
a gate;
a first insulating layer over the gate;
a second insulating layer over and in contact with the first insulating layer;
a semiconductor layer over and in contact with the second insulating layer;
a third insulating layer over and in contact with the semiconductor layer;
a fourth insulating layer over and in contact with the third insulating layer; and
a source and a drain each electrically connected to the semiconductor layer; and
a display element comprising:
a first electrode electrically connected to one of the source and the drain through a contact hole in the third insulating layer; and
a second electrode over the first electrode,
wherein:
the semiconductor layer includes an oxide semiconductor containing In, Ga, and Zn,
the second insulating layer and the third insulating layer each contain silicon and oxygen,
the first insulating layer and the fourth insulating layer each contain silicon and nitrogen, and
in a channel length direction of the transistor, the second insulating layer and the third insulating layer are in contact with each other with the semiconductor layer therebetween.

US Pat. No. 10,692,893

SUBSTRATE FOR DISPLAY DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. A display device, comprising:a substrate;
a pixel on the substrate, the pixel including:
a first thin film transistor (TFT) on the substrate, the first TFT including a first active layer; and
a second thin film transistor (TFT) on the substrate, the second TFT including:
a gate electrode,
a second active layer on the substrate,
a source electrode, and
a drain electrode contacting a top surface of the second active layer;
a first interlayer insulation film, a second interlayer insulation film, and a third interlayer insulation film between the first active layer and the second active layer, wherein the second interlayer insulation film is formed of SiNx and the third interlayer insulation film is formed of SiOx;
a light-emitting device electrically connected to the second TFT; and
a connection electrode contacting both the drain electrode of the second TFT and an anode electrode of the light-emitting device between the drain electrode of the second TFT and the anode electrode.

US Pat. No. 10,692,892

METHOD OF PROVIDING AN IMAGING SYSTEM AND IMAGING SYSTEM THEREOF

ARIZONA BOARD OF REGENTS ...

1. An imaging system comprising:a scintillator structure; and
an electronic device engaged with the scintillator structure, wherein:
the scintillator structure comprises:
a scintillator support layer; and
a scintillator layer;
the scintillator support layer comprises:
a first substantially non-planar surface;
a second substantially non-planar surface, the first substantially non-planar surface being approximately parallel to the second substantially non-planar surface; and
a scintillator support layer thickness greater than approximately 200 micrometers and less than or equal to approximately 300 micrometers;
the scintillator layer comprises:
a first surface;
a second surface opposite the first surface, the second surface being configured to scintillate; and
one or more granular phosphor materials comprising a diameter of greater than or equal to approximately 2 micrometers and less than or equal to approximately 30 micrometers;
the first surface of the scintillator layer is coupled to the second substantially non-planar surface of the scintillator support layer such that the second surface of the scintillator layer comprises a contour of the second substantially non-planar surface of the scintillator support layer;
the electronic device comprises a device substrate and one or more active sections;
the device substrate comprises a first surface and a second surface opposite the first surface of the device substrate;
the one or more active sections are at the second surface of the device substrate; and
the second surface of the device substrate and the one or more active sections conform to the second surface of the scintillator layer.

US Pat. No. 10,692,891

DISPLAY DEVICE

Semiconductor Energy Labo...

1. An electronic appliance comprising:a flexible film;
a first scan line driver circuit over the flexible film;
a second scan line driver circuit over the flexible film;
a display portion over the flexible film;
an external connecting wiring having a function of transmitting a signal to the display portion; and
an IC over the external connecting wiring,
wherein the display portion comprises a pixel electrode,
wherein each of the first scan line driver circuit and the second scan line driver circuit comprises a transistor,
wherein the flexible film comprises a first side and a second side in a first direction,
wherein the flexible film comprises a third side in a second direction intersecting with the first direction,
wherein the first scan line driver circuit is provided along the first side,
wherein the second scan line driver circuit is provided along the second side,
wherein the flexible film comprises a first curved portion curved in the second direction and provided along the first side,
wherein the flexible film comprises a second curved portion curved in the second direction and provided along the second side,
wherein the flexible film comprises a third curved portion curved in the first direction and provided along the third side,
wherein the first curved portion comprises a region between the display portion and the first scan line driver circuit, and
wherein the second curved portion comprises a region between the display portion and the second scan line driver circuit.

US Pat. No. 10,692,890

DISPLAY DEVICE, STACKED SUBSTRATE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A method for manufacturing a display device, comprising:providing a carrier substrate;
forming a soluble layer on the carrier substrate, the soluble layer comprising a material that dissolves in a washing solution;
forming a cover layer on a top surface of the soluble layer and a side surface of the soluble layer;
forming a display panel on the cover layer, the display panel comprising a base layer;
removing a portion of the cover layer from the side surface of the soluble layer to form a remaining part of the cover layer;
providing the washing solution to the soluble layer to remove the soluble layer; and
separating the display panel and the remaining part from the carrier substrate.

US Pat. No. 10,692,889

THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AS WELL AS DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A thin film transistor array substrate, comprising a glass substrate, a buffer layer and a pixel structure layer disposed on a first surface of the glass substrate, wherein the first surface of the glass substrate are patterned and formed a plurality of three-dimensional microstructures on the first surface of the glass substrate, and the buffer layer and the first surface are mutually intermeshed, and wherein the pixel structure layer includes a gate electrode disposed on the buffer layer and a pixel electrode disposed on the gate electrode, and the three-dimensional microstructures are correspond to the gate electrode and the pixel electrode.

US Pat. No. 10,692,888

HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a high voltage transistor comprising:
a gate electrode over a semiconductor fin, the gate electrode having a first side opposite a second side;
a first gate dielectric between the semiconductor fin of the high voltage transistor and the gate electrode of the high voltage transistor, wherein the first gate dielectric comprises a first high-k dielectric layer, and wherein the first high-k dielectric layer is further along sides of the gate electrode of the high voltage transistor; and
a first source or drain region at the first side of the gate electrode; and
a second source or drain region at the second side of the gate electrode; and
a low voltage transistor comprising:
a gate electrode over a semiconductor fin, the gate electrode having a first side opposite a second side;
a second gate dielectric between the semiconductor fin of the low voltage transistor and the gate electrode of the low voltage transistor, wherein the second gate dielectric comprises a second high-k dielectric layer, and wherein the second high-k dielectric layer is further along sides of the gate electrode of the low voltage transistor; and
a first source or drain region at the first side of the gate electrode; and
a second source or drain region at the second side of the gate electrode;
a first conductive contact on the first source or drain region of the high voltage transistor, the first conductive contact laterally spaced apart from the first side of the gate electrode of the high voltage transistor by a first distance;
a second conductive contact on the second source or drain region of the high voltage transistor, the second conductive contact laterally spaced apart from the second side of the gate electrode of the high voltage transistor by approximately the first distance;
a third conductive contact on the first source or drain region of the low voltage transistor, the third conductive contact laterally spaced apart from the first side of the gate electrode of the low voltage transistor by a second distance, the second distance less than the first distance; and
a fourth conductive contact on the second source or drain region of the low voltage transistor, the fourth conductive contact laterally spaced apart from the second side of the gate electrode of the low voltage transistor by approximately the second distance.

US Pat. No. 10,692,887

METHODS USED IN FORMING AN ARRAY OF MEMORY CELLS

Micron Technology, Inc., ...

1. A method used in forming an array of memory cells, comprising:providing a substrate comprising rows and columns of transistors, an access line interconnecting multiple of the transistors along individual of the rows in a row direction, the transistors individually comprising first and second pedestals joined to one another through a valley region, the first and second pedestals individually comprising an upper source/drain region, the valley region comprising a channel region, a transistor gate operatively laterally proximate at least one side of the channel region and comprising a portion of the access line; and
using no more than two photolithographic masking steps in forming both:
(a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain region of multiple of the second pedestals in the column direction, each of the sense lines having a first overall width extending in the row direction; and
(b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain region of multiple of the first pedestals, each via having a second overall width extending along the row direction, the first overall width being greater than the second overall width, the spaced elevationally-extending vias being formed after the sense lines and extending to elevationally above an uppermost surface of the sense lines.

US Pat. No. 10,692,886

SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL SEMICONDUCTOR FILMS WITH NARROWING WIDTHS AND GATE INSULATING FILMS WITH DIFFERENT THICKNESS

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a plurality of first gate electrodes that are arranged in a first direction intersecting a surface of the substrate and extend in a second direction intersecting the first direction;
a first semiconductor film that extends in the first direction and faces the plurality of first gate electrodes, a width in the second direction of one end on a substrate side of the first semiconductor film being smaller than a width in the second direction of an other end of the first semiconductor film;
a first gate insulating film that extends in the first direction and is provided between the plurality of first gate electrodes and the first semiconductor film;
a plurality of second gate electrodes that are arranged in the first direction, extend in the second direction, and are further from the substrate than the plurality of first gate electrodes are;
a second semiconductor film that extends in the first direction and faces the plurality of second gate electrodes, a width in the second direction of one end on the substrate side of the second semiconductor film being smaller than the width in the second direction of the other end of the first semiconductor film, a width in the second direction of an other end of the second semiconductor film being larger than the width in the second direction of the one end of the second semiconductor film, and the one end of the second semiconductor film being connected to the other end of the first semiconductor film;
a second gate insulating film that extends in the first direction and is provided between the plurality of second gate electrodes and the second semiconductor film;
a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, extends in the second direction, and faces the other end of the first semiconductor film at a surface on the substrate side; and
a third gate insulating film that is provided between the third gate electrode and the other end of the first semiconductor film, and is connected to the first gate insulating film and the second gate insulating film,
the third gate electrode facing the second semiconductor film via the second gate insulating film, and facing the other end of the first semiconductor film via the third gate insulating film, and
a thickness in the first direction of the third gate insulating film being larger than a thickness in the second direction of the first gate insulating film and the second gate insulating film.

US Pat. No. 10,692,885

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor device, comprising:stack structures each including a first conductive layer including a first type impurity;
a substrate disposed under the stack structures and including a second type impurity different from the first type impurity;
first impurity regions disposed in the substrate and including the first type impurity; and
at least one trench passing through the stack structures and disposed above the first impurity regions.

US Pat. No. 10,692,884

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BOTTLE-SHAPED MEMORY STACK STRUCTURES AND DRAIN-SELECT GATE ELECTRODES HAVING CYLINDRICAL PORTIONS

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
drain-select-level gate electrodes located over the alternating stack;
memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes; and
memory opening fill structures located in the memory openings,
wherein each of the memory opening fill structures comprises a respective semiconductor channel;
wherein each semiconductor channel comprises:
a respective first vertically-extending portion extending through levels of the electrically conductive layers and having a first maximum lateral channel dimension, and
a respective second vertically-extending portion located at a level of the drain-select-level gate electrodes and having a second maximum lateral channel dimension that is less than the first maximum lateral channel dimension; and
wherein each of the drain-select-level gate electrodes comprises:
a planar portion having two sets of vertical sidewall segments; and
a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures.

US Pat. No. 10,692,883

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a substrate;
a stacked body provided on the substrate, the stacked body comprising a first stacked body formed of a plurality of stacked first electrode layers and a second stacked body provided on the first stacked body, the second stacked body including at least one second electrode layer;
a hole that passes through the first stacked body and the second stacked body in a first direction perpendicular to the substrate and has a first insulator;
a semiconductor layer that is located between the first insulator and the first electrode layers and between the first insulator and the second electrode layer, the channel film having a first portion and a second portion which face each other, with the first insulator placed therebetween;
a first memory located between the first electrode layers and the first portion, and a second memory located between the first electrode layers and the second portion, the first memory and the second memory being electrically insulated from each other; and
a third memory located between the second electrode layer and the first portion and a fourth memory located between the second electrode layer and the second portion, the third memory and the fourth memory being electrically connected to each other.

US Pat. No. 10,692,882

METHODS FOR SOLVING EPITAXIAL GROWTH LOADING EFFECT AT DIFFERENT PATTERN DENSITY REGIONS

Yangtze Memory Technologi...

1. A patterned device, comprising:a substrate;
a first insulating layer over the substrate;
a low pattern density region comprising a first trench in the first insulating layer and the substrate;
a high pattern density region comprising a second trench in the first insulating layer and the substrate;
a second insulating layer formed in the first trench; and
an epitaxial grown layer formed in the second trench,
wherein the first trench has a larger cross-sectional area than the second trench,
wherein the first trench extends through the first insulating layer to the substrate,
wherein the second insulating layer contacts the substrate, and
wherein a top end of the second trench, opposite the substrate, remains exposed.

US Pat. No. 10,692,881

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor memory device comprising:a body conductive layer including a cell array portion and a peripheral circuit portion;
an electrode structure on the cell array portion of the body conductive layer, the electrode structure including a plurality of electrodes that are stacked on top of each other;
vertical structures penetrating the electrode structure, the vertical structures connected to the cell array portion of the body conductive layer;
a residual substrate on the peripheral circuit portion of the body conductive layer; and
a connection conductive pattern penetrating the residual substrate, the connection conductive pattern connected to the peripheral circuit portion of the body conductive layer, wherein the body conductive layer includes a polycrystalline semiconductor layer.

US Pat. No. 10,692,880

3D NAND HIGH ASPECT RATIO STRUCTURE ETCH

APPLIED MATERIALS, INC., ...

1. A method for processing a substrate in a process chamber, comprising:forming one or more features extending in a multi-material layer formed on a substrate to expose a portion of a top surface of the substrate by exposing the substrate to radicals of a remotely formed plasma, the one or more features each including top portions of sidewalls of the multi-material layer, bottom portions of the sidewalls of the multi-material layer, and the exposed portion of the top surface of the substrate, and the multi-material layer comprising alternating layers of a first dielectric layer and a second dielectric layer,
wherein the remotely formed plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and
wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about ?100° C. to about 100° C.;
subsequent to the forming of the one or more features, selectively oxidizing the top portions of the sidewalls of the multi-material layer and not oxidizing the bottom portions of the sidewalls of the multi-material layer, wherein a ratio of the height of the oxidized top portions to a depth of the one or more features is about 1:2 to about 1:8; and
subjecting the multi-material layer to an etch process.

US Pat. No. 10,692,879

SEMICONDUCTOR DEVICE INCLUDING DIFFERENT ORIENTATIONS OF MEMORY CELL ARRAY AND PERIPHERAL CIRCUIT TRANSISTORS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a plurality of memory cells on a first region of a substrate;
a peripheral circuit on a second region of the substrate; and
a dummy active region on a dummy region between the first region and the second region of the substrate, wherein a top surface of the dummy active region is disposed substantially a same level as a top surface of the substrate,
wherein each of the memory cells comprises a word line extending in a first direction, and
wherein a longitudinal direction of the dummy active region is different from the first direction.

US Pat. No. 10,692,878

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a main surface; and
a first memory cell and a second memory cell formed on the main surface and arranged in a first direction along the main surface,
wherein the first memory cell comprises:
a first gate insulating film formed on the main surface;
a first control gate electrode formed on the first gate insulating film and extending in a second direction intersecting with the first direction;
a second gate insulating film formed on the main surface and having a first charge storage portion;
a first memory gate electrode formed on the second gate insulating film and extending in the second direction so as to be adjacent to the first control gate electrode; and
an impurity region formed in the semiconductor substrate and positioned on the first memory gate electrode side,
wherein the second memory cell comprises:
a third gate insulating film formed on the main surface;
a second control gate electrode formed on the third gate insulating film and extending in the second direction;
a fourth gate insulating film formed on the main surface and having a second charge storage portion;
a second memory gate electrode formed on the fourth gate insulating film and extending in the second direction so as to be adjacent to the second control gate electrode; and
the impurity region positioned on the second memory gate electrode side,
wherein the first memory gate electrode has a first contact portion extending toward the second memory gate electrode in the first direction,
wherein the second memory gate electrode has a second contact portion extending toward the first memory gate electrode in the first direction, and
wherein the first contact portion is spaced apart from the second contact portion in the second direction in a plan view.

US Pat. No. 10,692,877

NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS

Cypress Semiconductor Cor...

1. A memory device comprising:a substrate comprising:
a plurality of bit lines, and
a plurality of body regions, wherein the pluralities of bit lines and body regions alternate along at least one axis;
a dielectric stack formed on at least one body region, the dielectric stack comprising an extended foot of a nitride layer of the dielectric stack; and
a gate layer formed on the dielectric stack.

US Pat. No. 10,692,876

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a first film that includes a plurality of first electrode layers stacked so as to be separated from each other in a first direction and extending in a second direction and a third direction each crossing the first direction;
a plurality of first columnar portions that are provided in the first film, include a charge storage layer and a first semiconductor layer, and extend in the first direction through the first electrode layers;
a second film that is provided on the first film and includes a plurality of second electrode layers stacked so as to be separated from each other in the first direction and extending in the second direction and the third direction;
a plurality of second columnar portions that are provided in the second film and on the first columnar portions, include a second semiconductor layer, and extend in the first direction through the second electrode layers; and
a plurality of first insulating films that are provided in the second film so as to be separated from the second columnar portions in the third direction and extend in the first direction through the second electrode layers and the second direction,
wherein the first columnar portions are arranged in a triangular lattice pattern in first regions and in a square or rectangular lattice pattern in second regions that are separate from the first regions and are aligned with the first insulating films in the first direction.

US Pat. No. 10,692,875

MEMORY STRUCTURE

United Microelectronics C...

1. A memory structure, comprising:a substrate;
at least one stacked gate structure located on the substrate and comprising a control gate, wherein the control gate extends in a first direction;
a first spacer conductive layer located on one sidewall of the control gate and electrically insulated from the control gate, wherein the first spacer conductive layer comprises a first merged spacer portion and a first non-merged spacer portion, and a line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion; and
a first contact connected to the first merged spacer portion.

US Pat. No. 10,692,874

3-DIMENSIONAL NOR STRING ARRAYS IN SEGMENTED STACKS

SUNRISE MEMORY CORPORATIO...

1. A memory structure, comprising:a semiconductor substrate having a planar surface, the semiconductor substrate having circuitry formed therein and thereon;
first and second memory modules provided above the planar surface, the second memory module being provided on top of the first memory module, wherein each memory module comprises:
a plurality of stacks of active strips, the stacks being spaced from each other along a first direction substantially parallel the planar surface, each active strip running lengthwise along a second direction that is also substantially parallel the planar surface but orthogonal to the first direction, the active strips within each stack being provided one on top of another along a third direction that is substantially perpendicular to the planar surface, each active strip comprising semiconductor layers that form drain, source and channel regions of thin-film storage transistors organized as NOR strings; and
a set of local word line conductors each running along the third direction to provide as gate electrodes to storage transistors in a designated one of the stacks of active strips; and
a first set of global word line conductors provided between the first memory module and the second memory module, wherein the global word line conductors in the first set of global word line conductors are (i) spaced from each other along the second direction and each running along the first direction, and (ii) each in direct contact with selected local word line conductors of both the first and second memory modules.

US Pat. No. 10,692,873

GATE FORMATION SCHEME FOR NANOSHEET TRANSISTORS HAVING DIFFERENT WORK FUNCTION METALS AND DIFFERENT NANOSHEET WIDTH DIMENSIONS

INTERNATIONAL BUSINESS MA...

1. A configuration of nanosheet field effect transistor (FET) devices formed on a substrate, the nanosheet FET devices comprising;a first nanosheet FET comprising:
a first channel nanosheet;
a second channel nanosheet over the first channel nanosheet;
a first gate structure around the first channel nanosheet; and
a second gate structure around the second channel nanosheet, wherein a first air gap is between the first gate structure and the second gate structure.

US Pat. No. 10,692,872

DEVICE STRUCTURE FOR FORMING SEMICONDUCTOR DEVICE HAVING ANGLED CONTACTS

Varian Semiconductor Equi...

1. A memory device, comprising:an active device region, comprising a first active area row and a second active area row, disposed at least partially in a first level;
a first storage capacitor, arranged in a capacitor row, and a second storage capacitor, arranged in the capacitor row, the first storage capacitor and the second storage capacitor being disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane;
a first contact via, the first contact via extending between the first storage capacitor and the first active area row, and defining a first non-zero angle of inclination with respect to a perpendicular to the substrate plane; and
a second contact via, the second contact via extending between the second storage capacitor and the second active area row, and defining a second non-zero angle of inclination with respect to the perpendicular to the substrate plane,
wherein the first contact via is angled in a first direction, and
wherein the second contact via is angled in a second direction, different from the first direction.

US Pat. No. 10,692,871

METHODS OF FORMING MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a memory device, comprising:providing a substrate having rows of semiconductor material fins; the rows of semiconductor material fins being spaced from one another by insulative material fill; individual semiconductor material fins within the rows of semiconductor material fins comprising a first pedestal and a second pedestal joined to one another through a valley region; each row of semiconductor material fins having a left side and a right side when viewed end on; the left and right sides being in opposing relation to one another;
forming a first heavily doped region in an upper portion of each first pedestal and forming a second heavily doped region in an upper portion of each second pedestal;
forming first wordlines on either the right sides or the left sides of each of the rows of semiconductor material fins while leaving the insulative material fill along the opposing sides of each the rows of semiconductor material fins; and
after forming the first wordlines, forming second wordlines on the opposing sides of each of the rows of semiconductor material fins.

US Pat. No. 10,692,870

THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH

Micron Technology, Inc., ...

1. A method of manufacturing a semiconductor apparatus, the method comprising:forming a memory structure including conductor material levels and dielectric material levels alternately stacked on a surface of a substrate in a memory array region, each of the conductor material levels being separated from an adjacent one of the conductor material levels by one of the dielectric material levels;
epitaxially forming a peripheral structure over a peripheral portion of the substrate for peripheral circuits adjacent to the memory structure, the peripheral structure including silicon, the peripheral structure forming a continuous interface with the substrate, the peripheral structure having an upper surface elevated above the substrate surface, the peripheral structure including circuit components formed at least in part within the peripheral structure, wherein a bottom of the circuit components are spaced above a top surface of the substrate; and
forming contacts and interconnects coupling one or more circuit components of the peripheral circuits to the memory structure.

US Pat. No. 10,692,869

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first memory cell over a substrate; and
a second memory cell over the first memory cell,
wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,
wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to one electrode of the first capacitor,
wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein an axis in a channel length direction of the first transistor corresponds to an axis in a channel length direction of the third transistor, and
wherein an axis in a channel length direction of the second transistor corresponds to an axis in a channel length direction of the fourth transistor.

US Pat. No. 10,692,868

CONTACT FORMATION THROUGH LOW-TEMPERATURE EPITAXIAL DEPOSITION IN SEMICONDUCTOR DEVICES

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:an n-type transistor device with an n-type source/drain region and a p-type transistor device with a p-type source/drain region formed on a substrate, and contact trenches formed through an inter-level dielectric layer to the respective source/drain regions, the inter-level dielectric layer being formed over the n-type transistor device and the p-type transistor device, wherein
the p-type source/drain regions contain a first metastable semiconductor-dopant alloy with a first concentration of p-type dopant,
the n-type source/drain regions contain a second metastable semiconductor-dopant alloy with a second concentration of n-type dopant,
the contact trenches contain a metallic material,
and the second dopant concentration is larger than the first dopant concentration.

US Pat. No. 10,692,867

METHOD AND STRUCTURE FOR FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a first fin structure disposed on a substrate, the first fin structure including:
a first semiconductor layer as its upper portion;
a second semiconductor layer as its middle portion, the middle portion having a semiconductor oxide feature as its outer layer; and
the substrate as its bottom portion; and
a first gate disposed over the first fin structure, the first gate including a high-k dielectric layer and a metal gate electrode.

US Pat. No. 10,692,866

CO-INTEGRATED CHANNEL AND GATE FORMATION SCHEME FOR NANOSHEET TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a semiconductor device, the method comprising:performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate;
wherein the first fabrication operations include:
forming a first channel nanosheet;
forming a second channel nanosheet over the first channel nanosheet;
forming a first gate structure around the first channel nanosheet;
forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure; and
applying a dopant to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.

US Pat. No. 10,692,865

SEMICONDUCTOR DEVICE AND FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first semiconductor layer over a substrate;
forming a second semiconductor layer over the first semiconductor layer;
forming a third semiconductor layer adjacent the first and second semiconductor layers to form a first source/drain feature, the third semiconductor layer being formed of a different material than the first and second semiconductor layers;
after the forming of the third semiconductor layer adjacent the first and second semiconductor layers to form the first source/drain feature, selectively removing a first portion of the first semiconductor layer, wherein the selectively removing of the first portion of the first semiconductor layer includes:
performing an oxidation process on the first semiconductor layer and the second semiconductor layer such that the second semiconductor layer is oxidized, the first portion of the first semiconductor layer is oxidized, and a second portion of the first semiconductor layer is not oxidized; and
selectively removing the oxidized second semiconductor layer and the oxidized first portion of the first semiconductor layer; and
forming a first gate stack around the second portion of the first semiconductor layer.

US Pat. No. 10,692,864

SEMICONDUCTOR DEVICE HAVING ASYMMETRIC FIN-SHAPED PATTERN

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first fin pattern on a substrate, the first fin pattern including first and second sidewalls opposite one another;
a second fin pattern on the substrate, the second fin pattern including third and fourth sidewalls opposite one another;
a third fin pattern on the substrate, between the first fin pattern and the second fin pattern;
a field insulating film contacting at least a portion of the first fin pattern, at least a portion of the second fin pattern, and at least a portion of the third fin pattern; and
a gate structure including a gate insulating film and a gate electrode on the gate insulating film, and crossing at least one of the first through third fin patterns, the gate insulating film being in direct contact with an upper surface of the field insulating film,
wherein the first fin pattern comprises:
a lower portion of the first fin pattern contacting the field insulating film; and
an upper portion of the first fin pattern directly on the lower portion of the first fin pattern, wherein the first sidewall of the upper portion of the first fin pattern and the second sidewall of the upper portion of the first fin pattern are asymmetric with respect to a first fin center line, and wherein the upper portion of the first fin pattern does not contact the field insulating film,
wherein the second fin pattern comprises:
a lower portion of the second fin pattern contacting the field insulating film; and
an upper portion of the second fin pattern directly on the lower portion of the second fin pattern, wherein the third sidewall of the upper portion of the second fin pattern and the fourth sidewall of the upper portion of the second fin pattern are asymmetric with respect to a second fin center line, and wherein the upper portion of the second fin pattern does not contact the field insulating film, and
wherein the first fin center line extends perpendicular from the substrate and meets a top of the first fin pattern, and the second fin center line extends perpendicular from the substrate and meets a top of the second fin pattern.

US Pat. No. 10,692,863

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:an enhancement-mode first p-channel MISFET;
an enhancement-mode second p-channel MISFET; and
a semiconductor layer having a common p type drain region for the first p-channel MISFET and the second p-channel MISFET, the semiconductor layer further comprising a first active region for the first p-channel MISFET and a second active region for the second p-channel MISFET arranged adjacent to the first active region, wherein
the first p-channel MISFET includes a first n type body region formed on a surface portion of the semiconductor layer, a first p type source region formed on a surface portion of the first n type body region, a first gate trench passing through the first p type source region and the first n type body region from the surface of the semiconductor layer, a first gate electrode embedded in the first gate trench, and a first source electrode connected to the first p type source region,
the second p-channel MISFET includes a second n type body region formed on the surface portion of the semiconductor layer, a second p type source region formed on a surface portion of the second n type body region, a second gate trench passing through the second p type source region and the second n type body region from the surface of the semiconductor layer, a second gate electrode embedded in the second gate trench, and a second source electrode connected to the second p type source region, and
the semiconductor device further comprises:
a third gate trench formed between the first gate trench and the second gate trench, the third gate trench commonly connecting the first gate trench and the second gate trench;
a third gate electrode embedded in the third gate trench, the third gate electrode commonly connecting the first gate electrode and the second gate electrode such that the first gate electrode, the second gate electrode and the third gate electrode are brought to the same electric potential;
a third n type body region formed at least one of (a) between the first gate trench and the third gate trench, and (b) between the second gate trench and the third gate trench; and
a drain electrode formed on a back surface of the semiconductor layer and connected to the p type drain region, wherein
the third n type body region is exposed from an inner surface of the third gate trench from a bottom portion of the third gate trench to the surface of the semiconductor layer in a depth direction of the third gate trench such that the third n type body region is exposed from the surface of the semiconductor layer,
a gate insulation film is sandwiched between the third gate electrode and the third n type body region, and
the third gate electrode faces the third n type body region through the gate insulation film from the bottom portion of the third gate trench to the surface of the semiconductor layer in the depth direction of the third gate trench.

US Pat. No. 10,692,862

ASYMMETRIC VARACTOR

1. A frequency multiplier comprising:an asymmetric varactor;
the asymmetric varactor comprising:
a first varactor of the asymmetric varactor, and
a second varactor of the asymmetric varactor;
the first varactor of the asymmetric varactor comprising:
a first layer, and
a third layer;
the second varactor of the asymmetric varactor comprising:
a first layer, and,
a third layer;
the first layer of the first varactor of the asymmetric varactor electrically connected to the first layer of the second varactor of the asymmetric varactor and to a first bias signal;
the third layer of the first varactor of the asymmetric varactor connected to a potential;
the third layer of the second varactor of the asymmetric varactor connected to a second bias signal;
in response to the first bias signal, the second bias signal, and an input signal, the asymmetric varactor:
exhibits an adaptive capacitance-voltage characteristic curve comprising a first portion with increasing capacitance that is not responsive to a change in a level of the second bias signal and a second portion that shifts in response to the change in the level of the second bias signal; and,
generates an output signal comprising an output frequency that is an even order multiple of an input frequency of the input signal.

US Pat. No. 10,692,861

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:an IGBT (Insulated Gate Bipolar Semiconductor) including:
a semiconductor layer having a first surface and a second surface;
a first conductive-type collector region formed such that the collector region is exposed on the second surface of the semiconductor layer;
a second conductive-type base region formed closer to the first surface of the semiconductor layer with respect to the collector region such that the base region is in contact with the collector region;
a first conductive-type channel region formed closer to the first surface of the semiconductor layer with respect to the base region such that the channel region is in contact with the base region;
a second conductive-type emitter region formed closer to the first surface of the semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region forming a portion of the first surface of the semiconductor layer;
a collector electrode formed such that the collector electrode is in contact with the second surface of the semiconductor layer, the collector electrode connected to the collector region;
a gate electrode formed on the first surface of the semiconductor layer such that an insulating film is formed between the gate electrode and the semiconductor layer; and
an emitter electrode formed such that the emitter electrode is in contact with the first surface of the semiconductor layer, the emitter electrode connected to the emitter region, and
a Schottky joint portion forming a Schottky junction with the first surface of the semiconductor layer using the emitter electrode as an anode electrode in the vicinity of the IGBT.

US Pat. No. 10,692,860

POWER MODULE AND POWER CONVERTER

HITACHI, LTD., Tokyo (JP...

1. A power module comprising:a plurality of semiconductor chips each including a diode and a transistor that are electrically connected to each other, the semiconductor chips being electrically connected in parallel; and
a substrate on which the semiconductor chips are mounted,
wherein a gate electrode of the transistor that each of the semiconductor chips has is electrically connected to a gate resistance,
wherein, in any two of the semiconductor chips, the gate resistance electrically connected to the semiconductor chip whose current value is smaller when a predetermined voltage is applied in the forward direction of the diode, is greater than the gate resistance electrically connected to the semiconductor chip whose current value is larger when the predetermined voltage is applied in the forward direction of the diode,
wherein the gate resistance is built in each of the semiconductor chips,
wherein each of the semiconductor chips has a MOSFET with an epitaxial layer, and
wherein, of the semiconductor chips, the resistance of the MOSFET that the semiconductor chip including the gate resistance with the greater resistance value has is greater than the resistance of the MOSFET that the semiconductor chip including the gate resistance with the smaller resistance value has.

US Pat. No. 10,692,859

LARGE AREA DIODE CO-INTEGRATED WITH VERTICAL FIELD-EFFECT-TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure comprising:a substrate;
a source contact layer on the substrate;
a bottom spacer layer on the source contact layer;
a vertical field-effect transistor including a first epitaxially grown channel layer having a first doped material; and
a diode including a second epitaxially grown channel layer having a second doped material that is opposite the doping of the first doped material;
wherein the first doped material extends continuously between first and second ends of the first epitaxially grown channel layer and the second doped material extends continuously between first and second ends of the second epitaxially grown channel layer, and
wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure, and
wherein each of the first and second epitaxially grown channel layers comprises a narrowed portion above a bottom surface of a top spacer layer that extends above a top surface of the top spacer layer, and
wherein a metal gate is in contact with sidewalls of the first epitaxially grown channel layer, a top surface of the bottom spacer layer, and a bottom surface of the top spacer layer.

US Pat. No. 10,692,858

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A method of fabricating a semiconductor device, comprising:providing a substrate, the substrate including a device isolation layer;
forming a first semiconductor pattern and a second semiconductor pattern on the substrate; and
forming a channel gate structure on a side surface of the second semiconductor pattern,
wherein the first semiconductor pattern and the second semiconductor pattern are isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate,
wherein the device isolation layer is between the first semiconductor pattern and the second semiconductor pattern in the first direction,
wherein each given semiconductor pattern, of the first semiconductor pattern and the second semiconductor pattern, includes a lower doped region and an upper doped region in lower and upper portions of the given semiconductor pattern, respectively,
wherein the first semiconductor pattern includes a base region between the upper doped region and the lower doped region of the first semiconductor pattern, and a base contact region that is isolated from direct contact with the upper doped region of the first semiconductor pattern in the first direction,
wherein the base region and the base contact region are associated with a first conductivity type, and
wherein the upper doped region and the lower doped region of each given semiconductor pattern are associated with a second conductivity type that is different from the first conductivity type.

US Pat. No. 10,692,857

SEMICONDUCTOR DEVICE COMBINING PASSIVE COMPONENTS WITH HEMT

VANGUARD INTERNATIONAL SE...

1. A semiconductor structure, comprising:a substrate, wherein a top of the substrate comprises a first region and a second region;
a first III-V compound layer, deposited in the first region;
a second III-V compound layer, deposited over the first III-V compound layer, wherein a first carrier channel is formed at an interface between the first III-V compound layer and the second III-V compound layer, wherein the second III-V compound layer has a first thickness;
a third III-V compound layer, deposited in the second region; and
a fourth III-V compound layer, deposited over the third III-V compound layer, wherein a second carrier channel is formed at an interface between the fourth III-V compound layer and the third III-V compound layer, wherein the fourth III-V compound layer has a second thickness, wherein the second thickness is less than the first thickness;
a first electrode, deposited over the third III-V compound layer; and
a second electrode, deposited over the third III-V compound layer, wherein the second carrier channel extends between the first electrode and the second electrode, wherein a resistor is formed in the second region, wherein conductivity of the resistor is positively correlated to the second thickness, wherein resistance of the resistor is negatively correlated to the second thickness.

US Pat. No. 10,692,856

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor integrated circuit device, comprising:a semiconductor chip including an internal circuit and a plurality of I/O cells, wherein:
the plurality of I/O cells are provided on a periphery area of the semiconductor chip,
each of the plurality of I/O cells includes a first region to which first voltage is supplied and a second region to which second voltage is supplied, wherein the second voltage is lower than the first voltage, the first region including a protective circuit for protecting the internal circuit from discharge of static electricity,
the first region is disposed closer to an outermost edge of the semiconductor chip than the second region,
each of the plurality of I/O cells includes a level shift circuit operated with the first and second voltage,
each of the plurality of I/O cells has a corresponding electrode pad overlapping the I/O cell in plan view and connected to the corresponding protective circuit,
electrode pads of the plurality of I/O cells are arranged in a first row and a second row, the first row being disposed closer to the outermost edge of the semiconductor chip than the second row, and
the protective circuit of each of the plurality of I/O cells includes:
a power source-side protective circuit provided between the corresponding electrode pad and a power source wiring; and
a ground-side protective circuit provided between the corresponding electrode pad and a ground wiring.

US Pat. No. 10,692,855

ESD PROTECTION DEVICE STRUCTURE COMPATIBLE WITH CMOS PROCESS

EGALAX_EMPIA TECHNOLOGY I...

1. An electrostatic discharge (ESD) protection device structure compatible with CMOS process, and the ESD protection device structure comprising an I/O circuit and an ESD clamp circuit:wherein the I/O circuit comprises a power source I/O unit, and the power source I/O unit comprises a high-voltage power terminal pad, a first power line electrically connected to the high-voltage power terminal pad, a high voltage ground terminal pad, and a second power line electrically connected to the high voltage ground terminal pad;
wherein the electrostatic discharge clamp circuit comprises a P-type substrate, and at least three low-voltage PMOS structures formed on the P-type substrate and electrically connected in series, and a plurality of low-voltage N-type wells formed on the P-type substrate correspondingly in position to the low-voltage PMOS structures, respectively, and each of the plurality of low-voltage PMOS structures comprises gate, source and drain formed on one of the plurality of low-voltage N-type wells corresponding thereto, the source and the gate of each of the plurality of low-voltage PMOS structures are electrically connected to each other, wherein among the plurality of low-voltage PMOS structures, source and gate of a first low-voltage PMOS structure are electrically connected to the high-voltage power terminal pad through the first power line, and a drain of a final low-voltage PMOS structure is electrically connected to the high voltage ground terminal pad through the second power line, so as to form an ESD current discharge path.

US Pat. No. 10,692,854

METHOD AND DEVICE FOR ELECTRICAL OVERSTRESS AND ELECTROSTATIC DISCHARGE PROTECTION

Semtech Corporation, Cam...

1. A semiconductor device, comprising:a signal source;
a load;
a transmission line coupled between the signal source and load;
a series protection circuit electrically coupled in series along the transmission line between the signal source and the load, wherein the series protection circuit includes,
a junction field-effect transistor (JFET), and
a resistor disposed between the JFET and load, wherein the JFET, resistor, and transmission line are electrically coupled in series between the signal source and load; and
a parallel protection circuit electrically coupled between the transmission line and a ground node, wherein the parallel protection circuit is directly coupled to a gate terminal of the JFET.

US Pat. No. 10,692,853

ELECTROSTATIC DISCHARGE (ESD) ROBUST TRANSISTORS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. An electrostatic discharge robust semiconductor transistor, comprising:a semiconductor substrate of a first conductivity type;
a substrate contact region of the first conductivity type coupled with the semiconductor substrate;
a source region of a second conductivity type coupled with the semiconductor substrate;
a channel region of the second conductivity type;
a gate region of the first conductivity type;
a drain region comprising a first drain region of the first conductivity type and a second drain region of the second conductivity type, and;
an electrical conductor directly coupled to and over the second drain region and a portion of the first drain region;
wherein a portion of the first drain region is not covered by the electrical conductor and becomes a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses, and;
wherein the transistor comprises a silicon controlled rectifier junction field effect transistor (SCR JFET).

US Pat. No. 10,692,852

SILICON-CONTROLLED RECTIFIERS WITH WELLS LATERALLY ISOLATED BY TRENCH ISOLATION REGIONS

GLOBALFOUNDRIES INC., Gr...

1. A device structure for a silicon-controlled rectifier, the device structure comprising:a substrate having a top surface;
a first well of a first conductivity type arranged in the substrate;
a second well of a second conductivity type arranged in the substrate between the first well and the top surface of the substrate, the second well adjoined with the first well along a first interface;
a third well of the second conductivity type arranged in the substrate between the first well and the top surface of the substrate, the third well adjoined with the first well along a second interface;
a first deep trench isolation region laterally arranged in the substrate between the third well of the second conductivity type and the second well of the second conductivity type, the first deep trench isolation region extending from the top surface of the substrate past the first interface and the second interface and into the first well; and
a first doped region of the first conductivity type arranged in the substrate between the second well and the top surface of the substrate,
wherein the first well extends continuously beneath the first deep trench isolation region.

US Pat. No. 10,692,851

HIGH SURGE BI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR

ALPHA AND OMEGA SEMICONDU...

1. A transient voltage suppressing (TVS) device, comprising:a semiconductor substrate of a first conductivity type, the substrate being heavily doped;
a first epitaxial layer of the first conductivity type formed on the substrate, the first epitaxial layer having a first thickness;
a second epitaxial layer of a second conductivity type, the second conductivity type opposite the first conductivity type, formed on the first epitaxial layer;
a first body region of the second conductivity type formed at a first surface in the second epitaxial layer;
a first heavily doped region of the first conductivity type formed in the first body region at the first surface of the second epitaxial layer; and
a second body region of the second conductivity type formed at a junction of the first heavily doped region and the first body region, the second body region being more heavily doped than the first body region,
wherein the semiconductor substrate forms an emitter, the first heavily doped region forms a collector, and the second epitaxial layer, the first body region and the second body region form a base of the TVS device, the first body region and the second body region and the first heavily doped region forming a collector-base junction being an avalanche junction.

US Pat. No. 10,692,850

SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING ELECTRODE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
an element region including an active element formed at the semiconductor substrate;
a channel stopper of the first conductivity type, the channel stopper formed in an outer peripheral region of the semiconductor substrate so as to surround the element region;
an insulating film formed so as to cover a surface of the semiconductor substrate, the insulating film having a first contact hole by which the channel stopper is exposed;
a second conductivity type layer formed in a region of the semiconductor substrate beneath the channel stopper and the first contact hole, the second conductivity type layer being entirely overlapped within an area defined by a periphery of the channel stopper when viewed perpendicularly to the surface of the substrate;
a first field plate formed on the insulating film, the first field plate facing the semiconductor substrate between the channel stopper and the element region through the insulating film;
a second field plate made of a polysilicon film and embedded in the insulating film, the second field plate facing the semiconductor substrate between the first field plate and the channel stopper through the insulating film;
an equipotential ring electrode formed along an outer peripheral region of the semiconductor substrate, the equipotential ring electrode connected to the channel stopper through the first contact hole, the equipotential ring electrode connected to the first field plate, the equipotential ring electrode connected to the second field plate through a second contact hole formed in the insulating film;
a MOSFET formed in the element region, the MOSFET including a channel region of a second conductivity type that is opposite to the first conductivity type; and
a protection diode connected between a gate and a source of the MOSFET,
wherein the protection diode is made of a polysilicon film formed in a same layer as the second field plate so as to face the semiconductor substrate through the insulating film,
wherein the insulating film includes a first insulating layer in contact with a bottom surface of the second field plate and a second insulating layer in contact with the top surface of the second field plate, and the protection diode is formed between the first and second insulating layers,
wherein the equipotential ring electrode has a protrusion extending through the first contact hole to a depth of the semiconductor substrate such that the protrusion penetrates the channel stopper and reaches the second conductivity type layer, and the protrusion has a bottom end that is positioned beneath the channel stopper and within the second conductivity type layer.

US Pat. No. 10,692,849

SEMICONDUCTOR DEVICE HAVING A FIRST CELL ROW AND A SECOND CELL ROW

SOCIONEXT INC., Kanagawa...

1. A semiconductor integrated circuit device comprising:a first cell row comprising a first standard cell and a second standard cell arranged in a first direction; and
a second cell row comprising a third standard cell and a fourth standard cell arranged in the first direction, and disposed adjacent to the first cell row in a second direction perpendicular to the first direction, wherein
the first standard cell comprises a first active transistor with a fin structure having a first fin extending in the first direction and disposed closest to a cell row boundary between the first and second cell rows,
the second standard cell comprises a dummy fin extending in the first direction and disposed at the same position in the second direction as the first fin, and an active fin extending in the first direction and disposed at the same position in the second direction as the first fin,
the third standard cell comprises a second fin extending in the first direction, and
the fourth standard cell comprises a third fin extending in the first direction and disposed at the same position in the second direction as the second fin.

US Pat. No. 10,692,848

STRESS REDUCTION APPARATUS AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:depositing a protection layer over a first substrate, wherein the first substrate is a part of a first semiconductor die;
forming an under bump metallization structure over the protection layer;
forming a connector over the under bump metallization structure;
forming a first dummy plane horizontally over a top surface of the first semiconductor die and along a first edge of the top surface of the first semiconductor die, wherein the first dummy plane has a long side and a short side, and wherein an outermost edge of the long side of the first dummy plane is vertically aligned with the first edge of the top surface of the first semiconductor die; and
forming a second dummy plane horizontally along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region, wherein the first dummy plane and the second dummy plane form a triangular corner region, and wherein the connector is located in the triangular corner region.

US Pat. No. 10,692,847

INORGANIC INTERPOSER FOR MULTI-CHIP PACKAGING

Intel Corporation, Santa...

1. A multi-chip device comprising:a substrate including low density interconnect circuitry therein;
an inorganic interposer on and in contact with the substrate, the inorganic interposer including high density interconnect circuitry, the high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including the high density interconnect circuitry in first and second stacks of inorganic materials, and each of the first and second stacks of inorganic materials including a silicon nitride and a silicon oxide on and in contact with the silicon nitride, the silicon nitride of the first stack on and in contact with a surface of the substrate and the silicon nitride of the second stack on and in contact with a surface of the silicon oxide of the first stack; and
two or more chips electrically connected to the inorganic interposer, the two or more chips directly electrically connected to each other through the high density interconnect circuitry.

US Pat. No. 10,692,846

PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A package-on-package (PoP) semiconductor package, comprising:an upper package; and
a lower package including:
a first semiconductor device in a first area;
a second semiconductor device in a second area; and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area, wherein:
the first semiconductor device includes a controller of the PoP semiconductor package, and
the second semiconductor device includes a power management integrated circuit of the PoP semiconductor package.

US Pat. No. 10,692,845

METHOD FOR ARRAYING MICRO-LED CHIPS FOR MANUFACTURING LED DISPLAY PANEL AND MULTI-CHIP CARRIER USED IN THE METHOD

LUMENS CO., LTD., Yongin...

1. A method for arraying micro-LED chips comprising:preparing a chip carrier formed with a plurality of chip pockets whose internal pressure is reduced through a plurality of suction holes;
capturing the micro-LED chips in the corresponding chip pockets such that the micro-LED chips are in close contact with the bottoms of the chip pockets;
placing the micro-LED chips captured in the chip pockets on a base body; and
half-turning the chip carrier in which the captured micro-LED chips are aligned in the corresponding chip pockets,
wherein each of the chip pockets comprises a slope through which an inlet having a larger width than the bottom is connected to the bottom and wherein the distances between the centers of the adjacent micro-LED chips placed on the base body are the same as those between the centers of the corresponding chip pockets.

US Pat. No. 10,692,844

MICRO-TRANSFER PRINTED LED AND COLOR FILTER STRUCTURES

X Display Company Technol...

1. A micro-transfer printed color-filter structure, comprising:a color filter; and
a fractured color-filter tether attached to the color filter or layers formed in contact with the color filter.

US Pat. No. 10,692,843

FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE WITH LARGE AREA CONDUIT

3M INNOVATIVE PROPERTIES ...

1. An article comprising:a flexible polymeric dielectric layer having top and bottom major surfaces, the top major surface having a conductive layer thereon, the dielectric layer having at least first, second and third openings through the dielectric layer, each of the first, second and third openings extending from the bottom major surface to the top major surface, the conductive layer comprising first, second and third conductive features substantially aligned with the respective first, second and third openings;
first, second and third pluralities of light emitting semiconductor devices supported by the respective first, second and third conductive features;
a single electrically insulative encapsulant dam disposed on the conductive layer and defining lateral boundaries of a laterally confined space, the first, second and third pluralities of light emitting semiconductor devices being encircled by the single electrically insulative encapsulant dam; and
a single encapsulant disposed in the laterally confined space and encapsulating the first, second and third pluralities of light emitting semiconductor devices,
wherein the first, second and third pluralities of light emitting semiconductor devices emit different first, second and third colors, respectively.

US Pat. No. 10,692,842

MICROELECTRONIC PACKAGE INCLUDING MICROELECTRONIC ELEMENTS HAVING STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS

Invensas Corporation, Sa...

1. A microelectronic package, comprising:a substrate having first and second opposed surfaces and first, second, third, and fourth substrate contacts exposed at the first surface, the first and second surfaces each extending in a first direction and in a second direction transverse thereto;
first, second, third, and fourth microelectronic elements each having memory storage array function, each microelectronic element having a rear face facing the first surface, a front face opposite the first surface, parallel first edges each extending in the first direction and between the front and rear faces, and parallel second edges each extending in the second direction and between the front and rear faces, each microelectronic element having one or more columns of element contacts exposed at the respective front face, each column extending in the first direction along the respective front face;
conductive structure extending above the front faces electrically connecting the element contacts of the first, second, third, and fourth microelectronic elements with the first, second, third, and fourth substrate contacts, respectively; and
a plurality of terminals exposed at the second surface and electrically connected with the substrate contacts,
wherein the first, second, third, and fourth microelectronic elements are horizontally spaced apart from one another on the first surface of the substrate such that the front faces of the microelectronic elements are arranged in a single plane parallel to the first surface, and
wherein the plurality of terminals include first and second groups of data terminals, each of the first and second groups having at least eight data terminals disposed on first and second opposite sides of an axis, respectively, each of the data terminals of the first and second groups being configured to carry data signals for read and write access to random access addressable memory locations of a memory storage array within one or more of the microelectronic elements, and the data terminals of the first group having modulo-X symmetry about the axis with the second group of the data terminals, X being an integer greater than two.

US Pat. No. 10,692,841

SEMICONDUCTOR DEVICES HAVING THROUGH-STACK INTERCONNECTS FOR FACILITATING CONNECTIVITY TESTING

Micron Technology, Inc., ...

1. A method for testing a stack of semiconductor dies, the method comprising:determining a resistance of a first through-stack interconnect extending through a first portion of the stack of semiconductor dies; and
based on the determined resistance, determining a connectivity of a plurality of second through-stack interconnects extending through a second portion of the stack of semiconductor dies, wherein the second portion of the stack of semiconductor dies is less prone to connectivity defects than the first portion of the stack of semiconductor dies.

US Pat. No. 10,692,840

MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a module substrate having an upper surface;
a first thinned flip chip die comprising a first device layer, a first dielectric layer and a plurality of first interconnects, wherein:
the first device layer includes a first coupling component embedded therein;
the first dielectric layer resides over an upper surface of the first device layer; and
the plurality of first interconnects extends from a lower surface of the first device layer and is coupled to the upper surface of the module substrate;
a first mold compound residing over the upper surface of the module substrate, surrounding the first thinned flip chip die, and extending above an upper surface of the first thinned flip chip die to define a first opening within the first mold compound and vertically above the first thinned flip chip die, wherein:
the first mold compound does not reside over the first thinned flip chip die and provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction;
the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other; and
the upper surface of the first thinned flip chip die is at a bottom of the first opening; and
a second die stacked with the first thinned flip chip die and in the first opening, wherein:
the first thinned flip chip die and the second die do not have electrical connections;
the second die comprises a second coupling component embedded therein; and
the second coupling component is mirrored to the first coupling component.

US Pat. No. 10,692,839

GAN DEVICES ON ENGINEERED SILICON SUBSTRATES

Intel Corporation, Santa...

1. A semiconductor device structure, comprising:one or more single-crystalline III-N semiconductor material layers in a first region of over a front-side of a substrate comprising silicon;
one or more silicon-channeled MOSFETs in a second region over the front-side of the substrate;
a microelectronic device over the front-side of the substrate and incorporating at least one of the III-N semiconductor material layers; and
a first stress-tuning material within a first trench on a back-side of the substrate opposite the first region and a second stress-tuning material, different than the first stress-tuning material, within a second trench on a back-side of the substrate opposite the second region, at least the first stress-tuning material to counter stress in the substrate induced by the III-N semiconductor material layers.

US Pat. No. 10,692,838

SEMICONDUCTOR PACKAGES

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a first chip and a second chip;
a first adhesive layer on a first surface of the first chip and a second adhesive layer on a second surface of the second chip, wherein the first adhesive layer and the second adhesive layer have different thickness, and a total thickness of the first chip and the first adhesive layer is substantially equal to a total thickness of the second chip and the second adhesive layer; and
a molding layer encapsulating the first chip, the second chip, the first adhesive layer and the second adhesive layer.

US Pat. No. 10,692,837

CHIP PACKAGE ASSEMBLY WITH MODULAR CORE DICE

XILINX, INC., San Jose, ...

1. A chip package assembly comprising:a first wafer segment having a first die spaced from a second die by a first scribe lane, sidewalls of the first die, the second die, and the first scribe lane physically contact by silicon of the first wafer segment;
an interconnect substrate stacked below the first wafer segment, the interconnect substrate having conductive routing electrically connected to the first die and the second die through die connections; and
a first diced die mechanically and electrically connected to the first die through die connections, wherein the first diced die is detached from all other dice along the scribe lanes bounding all sides of the first diced die such that first diced die is a single, independent and unitary die.

US Pat. No. 10,692,836

THIN 3D FAN-OUT EMBEDDED WAFER LEVEL PACKAGE (EWLB) FOR APPLICATION PROCESSOR AND MEMORY INTEGRATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first semiconductor die;
depositing an encapsulant around the first semiconductor die;
forming thin-film interconnect structure including a plurality of insulating layers over the first semiconductor die and encapsulant;
forming a conductive via through the plurality of insulating layers and extending from a top surface of the thin-film interconnect structure to a bottom surface of the thin-film interconnect structure, wherein the conductive via physically contacts an active surface of the first semiconductor die;
providing a second semiconductor die including a first interconnect structure formed over an active surface of the second semiconductor die; and
disposing the second semiconductor die over the first semiconductor die with the conductive via extending to the first interconnect structure.

US Pat. No. 10,692,835

BALL BOND ATTACHMENT FOR A SEMICONDUCTOR DIE

TEXAS INSTRUMENTS INCORPO...

1. A method for forming a ball bond for an integrated circuit formed on a semiconductor die, comprising:forming a ball at a first end of a conductive wire inserted in a capillary tool;
lowering the capillary tool toward a pad on the semiconductor die positioned on a support surface;
moving, using a motor, the support surface relative to the capillary tool to thereby bond the ball using a scrubbing action of the ball relative to the pad, and, without using ultrasound, to the pad; and
raising the capillary tool.

US Pat. No. 10,692,834

METHOD FOR REPLACING CAPILLARY

SAMSUNG ELECTRONICS CO., ...

1. A method for replacing a capillary of a wire bonding apparatus that includes a holding unit that holds a capillary, the method comprising:transferring a capillary replacing unit to the wire bonding apparatus by a mobile robot in response to receiving a capillary replacement start signal from the wire bonding apparatus;
separating, by the capillary replacing unit, the capillary corresponding to the replacement start signal from the wire bonding apparatus;
acquiring, by the wire bonding apparatus, an image of a new capillary gripped in a gripper of the capillary replacing unit to obtain position information of the new capillary;
aligning an insertion hole of the holding unit and the new capillary with each other using the position information, and
installing, by the capillary replacing unit, the new capillary in the wire bonding apparatus.

US Pat. No. 10,692,833

APPARATUS FOR CORRECTING A PARALLELISM BETWEEN A BONDING HEAD AND A STAGE, AND A CHIP BONDER INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A bonding apparatus, comprising:a bonding head including a bonding shaft;
a collet attached to the bonding head;
a stage, wherein a package substrate is disposed on the stage;
a detector circuit that determines whether the collet and the stage are parallel to each other during a bonding process, wherein the bonding head is configured to bond a semiconductor chip to the package substrate; and
a correcting unit including a first correcting block and a second correcting block disposed on the first correcting block, wherein the first correcting block is attached to the bonding shaft and includes a first curved surface, wherein the second correcting block includes a second curved surface, wherein the collet is disposed on the second correcting block, wherein the correcting unit adjusts at least one of the collet or the stage based on the determination of the detector circuit during the bonding process, wherein, when it is determined that the collet and stage are not parallel to each other, the second correcting block is configured to detach, with the collet, from the first correcting block to be disposed on the stage and away from the package substrate, and then, to reattach, with the collet, to the first correcting block so as to be removed from the stage.

US Pat. No. 10,692,832

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor structure, comprising:providing a semiconductor substrate, having a first active pad and a dummy pad on a first top surface of the semiconductor substrate;
providing a circuit board having a second active pad and a non-metallic surface, wherein a second top surface of the second active pad is at substantially same level as the non-metallic surface;
providing a first solder ball and a second solder ball on the second top surface and the non-metallic surface respectively;
attaching the first active pad and the dummy pad on the first solder ball and the second solder ball respectively; and
reflowing the first solder ball and the second solder ball to form a first bump wetted on the second top surface and a second bump not wetted on the non-metallic surface, and to elongate the first bump,wherein the first active pad and the first bump are electrically connected to an internal circuit of the semiconductor substrate, and the dummy pad and the second bump are electrically insulated from the internal circuit.

US Pat. No. 10,692,831

STUD BUMPS FOR POST-MEASUREMENT QUBIT FREQUENCY MODIFICATION

INTERNATIONAL BUSINESS MA...

1. A method of producing a quantum computer chip, comprising:performing a frequency measurement on a qubit chip bonded to a test interposer chip for qubits on the qubit chip at an operating temperature of the qubit chip;
pulling the qubit chip apart from the test interposer chip after performing the frequency measurement;
modifying a frequency of a subset of qubits after pulling the qubit chip apart from the test interposer chip; and
bonding the qubit chip to a device interposer chip after modifying the frequency of the subset of qubits.

US Pat. No. 10,692,830

MULTILAYERS OF NICKEL ALLOYS AS DIFFUSION BARRIER LAYERS

TEXAS INSTRUMENTS INCORPO...

12. An integrated circuit package comprising:a die; and
a bump electrically connected to the die, the bump comprising:
a copper (Cu) layer;
a first nickel tungsten (NiW) layer, with a Ni grain size a1, formed over the Cu layer;
a second NiW layer, with a Ni grain size a2, formed over the first NiW layer;
a third NiW layer, with a Ni grain size a3, formed over the second NiW layer, wherein a1 a tin (Sn) layer formed over the third NiW layer, wherein the first NiW layer and the second NiW layer comprise an element from a lanthanoid group.

US Pat. No. 10,692,829

METHOD OF FORMING A SOLDER BUMP STRUCTURE

INTERNATIONAL BUSINESS MA...

1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; and
solder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.

US Pat. No. 10,692,828

PACKAGE STRUCTURE WITH PROTRUSION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A package structure, comprising:a first under bump metallurgy (UBM) layer formed over a first substrate;
a first protrusion structure formed over the first UBM layer, wherein the first protrusion structure extends upward away from the first UBM layer;
a first electrical connector formed over the first protrusion structure, wherein the first electrical connector is surrounded by the first protrusion structure, and the first protrusion structure has a convex outer surface and a concave inner surface, the convex outer surface of the first protrusion structure is aligned with an outer surface of the first UBM layer, and the convex outer surface and the concave inner surface face toward to a center of the first UBM layer;
a second substrate formed over the first electrical connector, wherein the first electrical connector is electrically connected to a conductive pad of the second substrate;
a through via structure formed over the first substrate;
a second UBM layer formed below the through via structure, wherein the first UBM layer and the second UBM layer are at opposite sides of the through via structure;
a second protrusion structure formed below the second UBM layer; and
a second electrical connector formed below the second protrusion structure.

US Pat. No. 10,692,827

PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES

Micron Technology, Inc., ...

1. A system, comprising:at least one of a processor and a memory device, wherein at least one of the processor and the memory device includes a semiconductor component comprising—
an interposer substrate including a plurality of first terminals;
a microelectronic die having an active side, a back side opposite the active side and facing toward the interposer substrate, integrated circuitry, and a plurality of second terminals at the active side and electrically coupled to the integrated circuitry, and wherein the second terminals at the active side of the microelectronic die are electrically coupled to corresponding first terminals of the interposer substrate with a plurality of wire bonds; and
a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die, wherein the connection structure is attached to both the interposer substrate and the back side of the microelectronic die,
wherein the connection structure includes at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die.

US Pat. No. 10,692,826

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first semiconductor device, wherein the first semiconductor device comprises:
a first conductive layer formed over a first substrate;
a first etching stop layer formed over the first conductive layer, wherein the first etching stop layer is in direct contact with the first conductive layer;
a first bonding layer formed over the first etching stop layer;
a first bonding via formed through the first bonding layer and the first etching stop layer, wherein the first bonding via is electrically connected to the first conductive layer;
a first dummy pad formed in the first bonding layer;
a second semiconductor device, wherein the second semiconductor device comprises:
a second conductive layer formed over a second substrate;
a second etching stop layer formed over the second conductive layer, wherein the second etching stop layer is in direct contact with the second conductive layer;
a second bonding layer formed over the second etching stop layer;
a second bonding via formed through the second bonding layer and the second etching stop layer, wherein the second bonding via is electrically connected to the second conductive layer;
a second dummy pad formed in the second bonding layer; and
a bonding structure between the first substrate and the second substrate, wherein the bonding structure comprises the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.

US Pat. No. 10,692,825

LIGHT-EMITTING CHIP PACKAGE

HLJ TECHNOLOGY CO., LTD.,...

1. A light emitting chip package having a light emergent side and a bottom side opposite to the light emergent side and comprising:a light-emitting chip including an emission zone, a first electrode, and a second electrode, wherein the second electrode is located at the light emergent side;
a molding compound covering at least a sidewall of the light-emitting chip and supporting the light-emitting chip; and
a redistribution wiring structure disposed in the molding compound, wherein the redistribution wiring structure includes a first interconnect wiring structure electrically connected to the first electrode and a second interconnect wiring structure electrically connected to the second electrode, the first interconnect wiring structure and the second interconnect wiring structure respectively include a first pad and a second pad, and the first pad and the second pad are located at the same side of the light emitting chip package;
wherein the first pad and the second pad are located at the bottom side, and the second interconnect wiring structure further includes a second conductive layer located at the light emergent side and a second conductive post passing through the molding compound, and the second electrode is electrically connected to the second pad through the second conductive layer and the second conductive post.

US Pat. No. 10,692,824

RADAR MODULE WITH WAFER LEVEL PACKAGE AND UNDERFILL

Infineon Technologies AG,...

1. A semiconductor radar module comprising:an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device;
an interface layer abutting the IC radar device at a first portion, and abutting the wafer level package compound layer at a second portion,
wherein the interface layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally,
wherein the redistribution layer comprises at least one of an antenna or an antenna feed extending in the first and second portion, and
an underfill material extending at least in the second portion between the interface layer and an external substrate, the underfill material abutting the interface layer and the external substrate,
wherein the interface layer is disposed between the wafer level package compound layer and the underfill material, and
wherein the underfill material only partially fills an air cavity formed between the interface layer and the external substrate.

US Pat. No. 10,692,823

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A semiconductor device, comprising:a wiring substrate;
a wiring layer on an upper surface of the wiring substrate;
a semiconductor chip on the wiring layer, wherein a lower surface of the semiconductor chip faces the upper surface of the wiring substrate;
a bump on the lower surface of the semiconductor chip;
a resin portion between the wiring substrate and the semiconductor chip; and
a circuit element, wherein
an entirety of the circuit element is inside the resin portion,
the circuit element includes:
a first terminal connected to the wiring layer; and
a second terminal connected to the bump, and
the first terminal faces the upper surface of the wiring substrate and the second terminal faces the lower surface of the semiconductor chip.

US Pat. No. 10,692,822

ZERO CAPACITANCE ELECTROSTATIC DISCHARGE DEVICE

TEXAS INSTRUMENTS INCORPO...

1. An electrostatic discharge (ESD) device, comprising:a substrate layer;
a transition layer positioned on the substrate layer;
a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers; and
a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, wherein a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, wherein the plurality of doped contact structures are to generate a zero capacitance ESD device.

US Pat. No. 10,692,821

SEMICONDUCTOR CHIP HAVING TAMPERING FEATURE

International Business Ma...

1. An integrated circuit comprising:a structure including a semiconductor layer and an electrically insulating layer having a top surface and a bottom surface, the semiconductor layer adjoining the top surface of the electrically insulating layer;
electronic circuitry on the semiconductor layer;
a triggering circuit including a normally-OFF heterojunction field-effect photo-transistor on the structure, the normally-OFF heterojunction field-effect photo-transistor including a channel comprised of a portion of the semiconductor layer;
a heating or light emitting element electrically connected to the normally-OFF heterojunction field-effect photo-transistor,
an encapsulating layer adjoining the structure; and
a reactive chemical layer within the encapsulating layer and configured for disabling the electronic circuitry, the reactive chemical layer being reactive to heat or light generated by the heating or light emitting element by current flowing through the normally-OFF heterojunction field-effect photo-transistor and the heating or light emitting element.

US Pat. No. 10,692,819

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

ENKRIS SEMICONDUCTOR, INC...

1. A semiconductor structure, comprising:a substrate; and
at least one composition adjusting layer disposed above the substrate;
wherein each of the at least one composition adjusting layer is made of a semiconductor compound, the semiconductor compound at least comprises a first element and a second element, and an atomic number of the first element is less than an atomic number of the second element;
wherein in each of the at least one composition adjusting layer, along an epitaxial direction of the substrate, an atomic percentage of the first element in a compound composition is gradually decreased at first and then gradually increased, a total thickness of a gradual decrease section is greater than a total thickness of a gradual increase section, and the atomic percentage at the end of the gradual increase section is less than or equal to the atomic percentage at the beginning of the gradual decrease section.

US Pat. No. 10,692,818

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the semiconductor chip;
a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads;
a passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer;
metal members disposed in the openings of the passivation layer and connected to the exposed redistribution layer, wherein each metal member is distinct from the redistribution layer so as to define a boundary therebetween; and
electrical connection structures disposed on the passivation layer and respectively connected to the metal members,
wherein the electrical connection structures include first electrical connection structures and second electrical connection structures having different heights from each other, and
wherein the metal members include first discrete metal members respectively connected to the first electrical connection structures and second discrete metal members respectively connected to the second electrical connection structures, and
wherein the first and second metal members have different sizes from each other in a plan view of the fan-out semiconductor package.

US Pat. No. 10,692,817

SEMICONDUCTOR DEVICE WITH SHIELDING STRUCTURE FOR CROSS-TALK REDUCTION

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a die embedded in a molding material;
a first dielectric layer over the die and the molding material;
a conductive line along an upper surface of the first dielectric layer distal to the die;
a second dielectric layer over the first dielectric layer and the conductive line; and
a first conductive structure and a second conductive feature on opposing sides of the conductive line and spaced apart from the conductive line, wherein the first conductive feature and the second conductive feature extend through at least the first dielectric layer or the second dielectric layer, wherein a first longitudinal axis of the first conductive feature and a second longitudinal axis of the second conductive feature are parallel to a third longitudinal axis of the conductive line.

US Pat. No. 10,692,816

SEMICONDUCTOR PACKAGES INCLUDING DIE OVER-SHIFT INDICATING PATTERNS

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a package substrate including a die attachment region;
a semiconductor die attached to the die attachment region; and
a die over-shift indicating pattern disposed in the package substrate and spaced apart from the die attachment region on only one side of the semiconductor die,
wherein the die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die.

US Pat. No. 10,692,815

CHIP ON GLASS PACKAGE ASSEMBLY

Novatek Microelectronics ...

1. A chip on glass package assembly, comprising:a glass substrate comprising an active area and a peripheral area connected to the active area, wherein the peripheral area is disposed at a peripheral side of the active area, and lower surfaces and upper surfaces of the peripheral area and the active area are coplanar respectively;
a pixel array disposed directly on the upper surface of the active area of the glass substrate;
a first type chip mounted on the upper surface of the peripheral area and comprising a processor, wherein the first type chip is electrically connected to the pixel array;
a second type chip mounted on the upper surface of the peripheral area and located on a side of the first type chip, wherein the second type chip is different from the first type chip; and
a plurality of connecting lines disposed on the peripheral area and connecting the first type chip and the second type chip.

US Pat. No. 10,692,814

CHEMICAL DIRECT PATTERN PLATING METHOD

Taiwan Semiconductor Manu...

1. A method for forming a metal interconnect or via, comprising:providing a substrate having a planar upper surface; and
forming an interconnect layer over the planar upper surface, wherein the forming the interconnect layer comprises:
forming a patterned seed layer having a first feature and a second feature over the planar upper surface,
selectively depositing a first metal line over the first feature and a second metal line over the second feature, wherein a width of the first metal line is less than a height of the first metal line, and a width of the second metal line is at least five times a height of the second metal line, and
depositing a dielectric layer between the first and second metal lines, wherein the first and second metal lines are deposited by a method that comprises chemical direct plating.

US Pat. No. 10,692,813

SEMICONDUCTOR PACKAGE WITH DUMMY BUMPS CONNECTED TO NON-SOLDER MASK DEFINED PADS

Taiwan Semiconductor Manu...

15. A semiconductor package, comprising:a semiconductor device comprising:
an integrated circuit having a plurality of connecting pads;
connecting terminals disposed on and electrically connected to the integrated circuit by the plurality of connecting pads; and
dummy conductors disposed on and electrically isolated from the integrated circuit;
a circuit substrate bonded to the semiconductor device and comprising:
a solder mask layer having first recesses and second recesses formed therein;
first conductive pads, each comprising:
a first portion, partially exposed by one of the first recesses, wherein the first portion is connected to a respective one of the connecting terminals; and
a second portion, connecting to the first portion and located in the one of the first recesses, wherein the second portion is extended to a surface of the solder mask layer facing toward the semiconductor device; and
second conductive pads, each separated from the first conductive pads and entirely exposed by the second recesses, wherein each of the second conductive pads is spaced apart from a sidewall of a corresponding one of the second recesses and is connected to a respective one of the dummy conductors,
wherein the connecting terminals are respectively connected to the first conductive pads, the dummy conductors are respectively connected to the second conductive pads, and there is a level difference between horizontal interfaces of the connecting terminals and the first conductive pads and horizontal interfaces of the dummy conductors and the second conductive pads along a stacking direction of the semiconductor device and the circuit substrate.

US Pat. No. 10,692,812

INTERCONNECTS WITH VARIABLE SPACE MANDREL CUTS FORMED BY BLOCK PATTERNING

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:depositing a hardmask over an interlayer dielectric layer;
forming a first block mask that covers a first area on the hardmask;
forming a sacrificial layer over the first block mask and the hardmask;
patterning the sacrificial layer to form a first mandrel that extends across the first block mask; and
forming a sidewall spacer located on the hardmask and adjacent to the first mandrel,
wherein the first block mask and the sidewall spacer are comprised of titanium oxide.

US Pat. No. 10,692,811

SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a first anti-fuse structure;
a second anti-fuse structure over the first anti-fuse structure, wherein the second anti-fuse structure comprises:
at least one bottom electrode having an inner portion, an outer portion surrounding the inner portion, and a junction portion under the inner portion and the outer portion, where each of the inner portion and the outer portion is a hollow columnar elongated along a longitudinal axis that is perpendicular to a plane of the first anti-fuse structure, and the junction portion is connected with the inner portion and the outer portion,
a second dielectric layer conformally covering the bottom electrode, and
a top electrode covering the second dielectric layer, wherein the top electrode includes a first portion inserted into the bottom electrode and a second portion over the first portion; and
a first metal layer between the first anti-fuse structure and the second anti-fuse structure.

US Pat. No. 10,692,810

SEMICONDUCTOR MODULE

SHINDENGEN ELECTRIC MANUF...

1. A semiconductor module comprising:a first electronic device in which one terminal is connected to a first wiring line, the other terminal is connected to a second wiring line, and a first device current flows in a first current direction from the first wiring line to the second wiring line;
a second electronic device in which one terminal is connected to a third wiring line, the other terminal is connected to a fourth wiring line, and a second device current flows in a second current direction from the third wiring line to the fourth wiring line;
a regulation wiring line in which a regulation current that is different from the first device current and the second device current flows;
a third electronic device in which one terminal is connected to a fifth wiring line, the other terminal is connected to a sixth wiring line, and a third device current flows in a third current direction from the fifth wiring line to the sixth wiring line; and
a fourth electronic device in which one terminal is connected to a seventh wiring line, the other terminal is connected to a eighth wiring line, and a fourth device current flows in a fourth current direction from the seventh wiring line to the eighth wiring line,
wherein:
the first electronic device and the second electronic device are arranged so that at least part of a first magnetic flux generated by the first device current flowing in the first current direction cancels at least part of a second magnetic flux generated by the second device current flowing in the second current direction to reduce mutual inductance;
the third electronic device and the fourth electronic device are arranged so that at least part of a third magnetic flux generated by the third device current flowing in the third current direction cancels at least part of a fourth magnetic flux generated by the fourth device current flowing in the fourth current direction to reduce mutual inductance;
the regulation wiring line is arranged so that at least part of a magnetic flux generated by the regulation current flowing in the regulation wiring line cancels at least part of the first magnetic flux to reduce mutual inductance;
the first current direction in which the first device current flows and the second current direction in which the second device current flows are parallel to each other, and a value of the first device current is the same as a value of the second device current;
the first electronic device is a first switching device in which one terminal is connected to a first power supply terminal and the other terminal is connected to a first output terminal;
the second electronic device is a second switching device in which one terminal is connected to a second output terminal and the other terminal is connected to a second power supply terminal, the second electronic device being controlled to be turned on or off in synchronization with the first switching device;
the third electronic device is a third switching device in which one terminal is connected to the first output terminal and the other terminal is connected to the second power supply terminal;
the fourth electronic device is a fourth switching device in which one terminal is connected to the first power supply terminal and the other terminal is connected to the second output terminal, the fourth electronic device being controlled to be turned on or off in synchronization with the third switching device; and
the first switching device and the third switching device are controlled to be complementarily turned on or off.

US Pat. No. 10,692,809

MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:providing a substrate;
disposing a die over the substrate;
forming a molding over the substrate and around the die;
disposing a first dielectric layer over the die and the molding;
curing the first dielectric layer under a first curing condition;
disposing a second dielectric layer over the first dielectric layer; and
curing the first dielectric layer and the second dielectric layer under the first curing condition.

US Pat. No. 10,692,808

HIGH PERFORMANCE CELL DESIGN IN A TECHNOLOGY WITH HIGH DENSITY METAL ROUTING

QUALCOMM Incorporated, S...

1. A semiconductor die, comprising:a first doped region;
a second doped region;
a first contact over the first doped region;
a second contact over the second doped region, wherein the first contact and the second contact are in a first contact middle of line (MOL) layer of the semiconductor die;
an interconnect formed from the first contact MOL layer, wherein the interconnect is spaced apart from the first contact and the second contact in a first lateral direction, and the interconnect extends in a second lateral direction that is perpendicular to the first lateral direction;
a first bridge between the first contact and the interconnect, wherein the first bridge electrically couples the first contact to the interconnect;
a second bridge between the second contact and the interconnect, wherein the second bridge electrically couples the second contact to the interconnect;
a first metal line formed from a first interconnect metal layer; and
a first via electrically coupling the interconnect to the first metal line,
wherein the first and second contacts are formed from the first contact MOL layer, and the first and second bridges are formed from a second MOL layer.

US Pat. No. 10,692,807

CHIP-ON-FILM PACKAGE STRUCTURE AND DISPLAY DEVICE

Au Optronics Corporation,...

1. A chip-on-film package structure, comprising:a first chip-on-film, comprising:
a first flexible substrate, having a first external terminal and a first internal terminal opposite to each other;
a plurality of first outer leads disposed at the first external terminal;
a plurality of first inner leads disposed at the first internal terminal; and
a first chip disposed between the first external terminal and the first internal terminal; and
a second chip-on-film, comprising:
a second flexible substrate, having a second external terminal and a second internal terminal opposite to each other;
a plurality of second outer leads disposed at the second external terminal;
a plurality of second inner leads disposed at the second internal terminal; and
a second chip disposed between the second external terminal and the second internal terminal,
wherein the first chip-on-film is partially overlapped with the second chip-on-film,
wherein the first external terminal and the second external terminal are disposed at two opposite sides of a normal line, and the first internal terminal and the second internal terminal are at least partially overlapped.

US Pat. No. 10,692,806

SEMICONDUCTOR ARRANGEMENT WITH RELIABLY SWITCHING CONTROLLABLE SEMICONDUCTOR ELEMENTS

Infineon Technologies AG,...

1. A semiconductor arrangement, comprising:a circuit board comprising a metallization layer with a first conductor track and a second conductor track; and
a plurality of individual semiconductor chips each comprising a controllable semiconductor element, a first load electrode, a second load electrode and a control electrode, the first load electrodes of the individual semiconductor chips electrically connected to one another, the second load electrodes of the individual semiconductor chips electrically connected to one another, and the control electrodes of the individual semiconductor chips electrically connected to one another,
wherein:
the first conductor track comprises a base section and a first, second and third section, the third section arranged between the first and second sections;
the second conductor track comprises a first and a second section;
the first section of the second conductor track is arranged between the first and the third section of the first conductor track;
the second section of the second conductor track is arranged between the second and the third section of the first conductor track;
the third section of the first conductor track is arranged between the first and the second section of the second conductor track;
a first subset and a second subset of the plurality of semiconductor chips are arranged on the first section of the second conductor track;
a third subset and a fourth subset of the plurality of semiconductor chips are arranged on the second section of the second conductor track;
the first load electrode of each of the semiconductor chips of the first and the second subset is, via at least one first electrical connection, electrically connected to the first section of the first conductor track and, via at least one second electrical connection, to the third section of the first conductor track; and
the first load electrode of each of the semiconductor chips of the third and the fourth subset is, via at least one third electrical connection, electrically connected to the third section of the first metallization and, via at least one fourth electrical connection, to the second section of the first conductor track.

US Pat. No. 10,692,805

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; and
a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a first wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a first via penetrating through the first insulating layer and electrically connecting the connection pads to the first wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the first wiring pattern,
wherein a side surface of the first wiring pattern has an angle of 90° or smaller with respect to an interface of the first insulating layer and the first wiring pattern, and
wherein a portion of the first wiring pattern has a pitch of 10 ?m or less.

US Pat. No. 10,692,804

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:an interposer having a sidewall defining a space;
a first semiconductor device disposed within the space and in contact with the sidewall; and
a second semiconductor device disposed within the space and on the first semiconductor device.

US Pat. No. 10,692,803

DIE EMBEDDING

Infineon Technologies Aus...

14. A power semiconductor device package, comprising:a package top side;
a package footprint side;
a power semiconductor die having a first load terminal at a die frontside and a second load terminal at a die backside;
a first terminal interface and a second terminal interface arranged at the package footprint side, the first terminal interface being electrically connected with the first load terminal;
an insulating core layer having a main cavity, wherein the power semiconductor die is provided in the main cavity, and wherein the main cavity has a cavity sidewall;
a conductive material at the cavity sidewall;
an insulation structure in the main cavity and embedding the power semiconductor die, wherein the die backside faces the package top side; and
an electrical connection between the second load terminal and the second terminal interface, the electrical connection being formed by at least the conductive material at the cavity sidewall.

US Pat. No. 10,692,802

FLEXIBLE SEMICONDUCTOR DEVICE WITH GRAPHENE TAPE

NXP USA, INC., Austin, T...

1. A flexible semiconductor device, comprising:a first tape having a plurality of bonding pads and a plurality of conductive traces formed thereon, wherein the plurality of bonding pads and the plurality of conductive traces comprise graphene, wherein the plurality of bonding pads are formed in a first center area of the first tape, and the plurality of conductive traces are formed in the first center area in electrical contact with a bottom surface of respective ones of the bonding pads and extending from the bonding pads to a first peripheral area surrounding the first center area;
a first semiconductor die attached to the first tape and electrically connected to the plurality of bond pads by way of a plurality of die electrical contacts; and
a second tape having a second center area attached to the first semiconductor die, and a second peripheral area that surrounds the second center area, wherein the second peripheral area is attached to the first peripheral area of the first tape, such that the first and second tapes encapsulate the first semiconductor die, the plurality of die electrical contacts, and the plurality of conductive traces.

US Pat. No. 10,692,801

BOND PAD AND CLIP CONFIGURATION FOR PACKAGED SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A semiconductor device package, comprising:a die pad comprising a die attach surface;
a first lead that is spaced apart and extends away from a first side of the die pad;
a semiconductor die mounted on the die attach surface, the semiconductor die comprising a first bond pad and a second bond pad, each being disposed on an upper side of the semiconductor die that is opposite the die attach surface;
a first clip that electrically connects the first lead to the first bond pad;
wherein the first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad,
wherein the semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip, the first current flow direction extending between the first bond pad and the first lead,
wherein the second bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the second bond pad,
wherein the second bond pad is spaced apart from the first bond pad,
wherein the first and second bond pads collectively provide a single terminal of the semiconductor die, and
wherein the first clip comprises an end portion extending from the first bond pad to the second bond pad in the first current flow direction, the end portion of the first clip covering and electrically contacting the first and second bond pads.

US Pat. No. 10,692,800

SEMICONDUCTOR DEVICE HAVING SUBSTRATE AND BASE PLATE JOINED BY JOINING MEMBER

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a substrate having a front surface and a rear surface, and including
a conductive pattern having a first side surface,
an electrical insulating board having the conductive pattern on a front surface thereof, and having a second side surface parallel to the first side surface, and
a metal plate disposed on a rear surface of the electrical insulating board, having a third side surface parallel to the first and second side surfaces, the metal plate having a size that is smaller than a size of the electrical insulating board in a plan view so that the electrical insulating board extends beyond the metal plate;
a base plate having a principal surface;
a joining member disposed between the metal plate and the base plate to join the metal plate to the base plate; and
a resist member formed in a stripe shape on the base plate in parallel to the first side surface in a plan view, the resist member having a continuous linear structure,
wherein the base plate has first, second, and third positions, defined thereon in a cross-sectional view, the first position being outwardly away from the third position, the second position being directly under the second side surface, the third position being directly under the third side surface,
wherein the resist member has a marginal edge on a side closer to the substrate, and the marginal edge is located between the third position and the first position in the cross-sectional view, and
wherein the first position is away from the second position by a distance calculated by dividing “a height from the principal surface of the base plate to the front surface of the electrical insulating board” by “a tangent of a contact angle between the base plate and the joining member”,
wherein the second side surface of the electrical insulating board is located closer to the first position than is the third side surface of the metal plate, and
wherein the joining member on the base plate entirely covers the rear surface and the third side surface of the metal plate, and covers a rear surface of the electrical insulating board from the third side surface of the metal plate toward the second side surface of the electrical insulating board.

US Pat. No. 10,692,799

SEMICONDUCTOR ELECTRONIC DEVICE

InnoLux Corporation, Chu...

1. An electronic device, comprising:a substrate comprising a first through hole;
a first connecting element disposed in the first through hole;
a first insulating layer disposed on the substrate and comprising a first via;
a semiconductor layer disposed on the first insulating layer; and
a first conductive layer disposed on the first insulating layer, wherein the first conductive layer comprises a first conductive element extending into the first via to electrically connect the first connecting element and the semiconductor layer;
wherein a concentration of Cu element in the first connecting element is greater than a concentration of Cu element in the first conductive element.

US Pat. No. 10,692,798

MULTIPLE FLOW ENTRANCE HEAT SINK

Advanced Thermal Solution...

1. An apparatus comprising:a base having a perimeter with a first base edge and an opposite second base edge;
a flow barrier extending from the base and comprising: opposite first and second barrier sides facing and spaced from the first and second base edges, respectively, a barrier length parallel to the first and second barrier sides, a barrier height perpendicular to the barrier length and to the base, and a relatively uniform barrier thickness between the first and second barrier sides and perpendicular to the barrier length and the barrier height;
a first fin field positioned between the first base edge and the first barrier side, the first fin field comprising a plurality of first fins extending from the base and each having a respective first fin length extending parallel to the base and a respective first fin thickness that is perpendicular to the first fin length and less than the barrier thickness, the first fins collectively providing:
a first fin sub-section that is positioned distal to the flow barrier, the first fin sub-section having a first fin sub-section height that is perpendicular to the first fin length and the first fin thickness and that is substantially equal to the barrier height; and
a second fin sub-section that is proximate to the flow barrier, the second fin sub-section having a second fin sub-section height that is perpendicular to the first fin length and the first fin thickness and that is less than the first fin sub-section height and the barrier height; and
a second fin field separated from the first fin field by the flow barrier and positioned between the second base edge and the second barrier side, the second fin field comprising a plurality of second fins extending from the base and each having a respective second fin length extending parallel to the base and a respective second fin thickness that is perpendicular to the second fin length and less than the barrier thickness,
wherein the flow barrier is configured and arranged to prevent a fluid flow mix across the first and second fin fields.

US Pat. No. 10,692,796

SEMICONDUCTOR PACKAGE HAVING STACKED SUBSTRATES WITH CAVITIES

Technische Hochschule Ing...

1. A semiconductor package, the package comprising:a first substrate comprising, at a front cavity side, a plurality of cavities, each of the cavities having a bottom wall and side walls, and having a conductive path forming an electric contact surface located at the inner side of the bottom wall of the cavity,
a plurality of semiconductor elements, each of the semiconductor elements comprising a first electric contact surface on a first side and a second electric contact surface on a second side opposite to the first side, wherein at least one of the semiconductor elements is placed within a corresponding cavity at the front cavity side of the first substrate, wherein the first electric contact of the semiconductor element and the electric contact surface at the inner side of the bottom wall of the corresponding cavity are electrically conductive bonded in a material-locking manner,
a second substrate, the second substrate being attached with a connection side to the front cavity side of the first substrate, thereby encapsulating the semiconductor elements located within the corresponding cavities at the front cavity side of the first substrate, and
a third substrate, the third substrate being attached with a connection side to the first substrate or to the second substrate,
wherein the second substrate comprises two opposed connection sides, wherein the third substrate further comprises, on a cavity side which is the connection side, a plurality of cavities, each of the cavities having a bottom wall, side walls, and a conductive path forming an electric contact surface located at the inner side of the bottom wall of the cavity, wherein at least one of the plurality of semiconductor elements is placed within a corresponding cavity at the cavity side of the third substrate, wherein the first electric contact of the semiconductor element and the electric contact surface at the inner side of the bottom wall of the corresponding cavity are electrically conductive bonded in a material-locking manner, and
wherein the third substrate is attached with the cavity side to a connection side of the second substrate, thereby encapsulating the semiconductor elements located within the corresponding cavities at the cavity side of the third substrate.

US Pat. No. 10,692,795

FLIP CHIP ASSEMBLY OF QUANTUM COMPUTING DEVICES

INTERNATIONAL BUSINESS MA...

1. A quantum device comprising:an interposer layer comprising a set of vias;
a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias;
a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip comprising:
a plurality of qubits on a first side of the qubit chip; and
a plurality of protrusions on a second side of the qubit chip; and
a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.

US Pat. No. 10,692,794

RADIATION PLATE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING RADIATION PLATE STRUCTURE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a radiation plate including a plurality of radiation plate through-holes;
a solder resist disposed on a main surface of the radiation plate and comprising at least one opening;
an insulating substrate comprising a circuit pattern soldered to the radiation plate within the opening of the solder resist; and
a semiconductor element disposed on the insulating substrate, wherein
ends of the insulating substrate extend to be positioned above the solder resist;
the solder resist has a thickness greater than a thickness of solder with which the radiation plate is joined to the insulating substrate, the thickness of the solder resist being smaller than a sum of the thickness of the solder and a thickness of the circuit pattern in at least an overlap between the solder resist and the insulating substrate, and
the solder resist partially surrounds each of the radiation plate through-holes by extending to an edge of the radiation plate.

US Pat. No. 10,692,793

ELECTRONIC DEVICE WITH A PACKAGE-LEVEL THERMAL REGULATOR MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Micron Technology, Inc., ...

1. An electronic device, comprising:a substrate;
a die attached to the substrate;
an encapsulation covering the substrate and the die, wherein:
the die is embedded within the encapsulation, and
the encapsulation includes thermal-conduction component suspended therein and configured to enhance distribution of the thermal energy through the encapsulation and to the die;
a heater embedded within the encapsulation, wherein the heater configured to provide thermal energy to the die; and
a thermal-isolation component directly contacting the encapsulation opposite the die, the thermal-isolation component configured to contain the thermal energy within the electronic device and provide a barrier between the die and a cryogenic environment.

US Pat. No. 10,692,792

ELECTRONIC DEVICE

DENSO CORPORATION, Kariy...

1. An electronic device, comprising:at least one electronic component;
a sealing resin body sealing the electronic component; and
a plurality of conductive members electrically connected to the electronic component in the sealing resin body, including respective portions exposed from the sealing resin body to an outside of the sealing resin body, and having different potentials, wherein
the plurality of conductive members include a heat sink and a terminal, the terminal extending from an inside of the sealing resin body to the outside of the sealing resin body,
a surface of the terminal includes a higher adhesion surface and a lower adhesion surface, the higher adhesion surface and the lower adhesion surface being covered with the sealing resin body, and the lower adhesion surface has an adhesion strength to the sealing resin body that is lower than an adhesion strength of the higher adhesion surface to the sealing resin body, and
the lower adhesion surface is provided in an entire portion of a back surface of the terminal, the back surface being opposite to a connection surface of the terminal which is adjacent to a connection part electrically connected to the electronic component, and
the higher adhesion surface is provided in the connection surface.

US Pat. No. 10,692,791

ELECTRONIC COMPONENT PACKAGE WITH ELECTROMAGNETIC WAVE SHIELDING

SAMSUNG ELECTRONICS CO., ...

1. An electronic component package, comprising:a core member including an insulating layer, and having a first through-hole passing through the insulating layer;
a semiconductor chip disposed in the first through-hole, and having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;
an encapsulant covering at least a portion of each of the core member and the inactive surface of the semiconductor chip, and filling at least a portion of the first through-hole;
a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad;
a backside metal layer disposed on the encapsulant, and covering at least the inactive surface of the semiconductor chip; and
a backside metal via passing through the encapsulant, and connecting the backside metal layer to one side of the insulating layer,
wherein a lowermost surface of the backside metal via is in contact with the one side of the insulating layer.

US Pat. No. 10,692,790

WAFER-LEVEL PACKAGING FOR ENHANCED PERFORMANCE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a device layer with a plurality of input/output (I/O) contacts at a top surface of the device layer;
a plurality of first bump structures formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;
a first mold compound residing over the device layer, wherein a portion of each of the plurality of first bump structures is exposed through the first mold compound;
a stop layer formed underneath the device layer, wherein:
the stop layer comprises silicon oxide; and
the plurality of first bump structures and the device layer are located at a same side of the stop layer; and
a second mold compound residing underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

US Pat. No. 10,692,789

STACKED FAN-OUT PACKAGE STRUCTURE

MediaTek Inc., Hsin-Chu ...

1. A semiconductor package structure, comprising:a first semiconductor die having a first surface and a second surface opposite thereto;
a film disposed on the first surface of the first semiconductor die via an adhesion layer;
a first molding compound surrounding the first semiconductor die and in contact with the film;
a first redistribution layer (RDL) structure disposed on the second surface of the first semiconductor die and laterally extending on the first molding compound;
a second semiconductor die disposed on the first RDL structure and having a first surface and a second surface opposite thereto;
a second molding compound surrounding the second semiconductor die and in contact with the film;
a third semiconductor die disposed on a second RDL structure and having a first surface and a second surface opposite thereto;
a third molding compound surrounding the third semiconductor die and in contact with the film; and
a third RDL structure disposed on the second surface of the third semiconductor die and laterally extending on the third molding compound,
wherein the first and second surfaces of the third semiconductor die are exposed from the third molding compound.

US Pat. No. 10,692,788

DEVICE TO DECREASE FLICKER NOISE IN CONDUCTOR-INSULATOR-SEMICONDUCTOR (CIS) DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor substrate;
a pair of source/drain regions in the semiconductor substrate, wherein the source/drain regions are laterally spaced;
a selectively-conductive channel in the semiconductor substrate, wherein the selectively-conductive channel extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions;
an isolation structure extending into a top of the semiconductor substrate and demarcating a device region of the semiconductor substrate, wherein the source/drain regions and the selectively-conductive channel are in the device region, wherein the isolation structure has a pair of isolation edges extending laterally in the first direction, and wherein the isolation edges are respectively on opposite sides of the device region;
a gate electrode comprising a pair of peripheral segments and a central segment, wherein the peripheral segments are respectively on the opposite sides of the device region and extend laterally in parallel along individual axes in the first direction, wherein the axes are disposed respectively at width-wise centers of the peripheral segments, wherein the central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments, wherein the central segment is an only segment of the gate electrode extending from the one of the peripheral segments to the another one of the peripheral segments, and wherein the isolation edges are laterally spaced from and between the axes in the second direction; and
multiple gate contact vias on a single one of the peripheral segments of the gate electrode, wherein the multiple gate contact vias are the only vias on the gate electrode, are spaced laterally between opposite sidewalls of the central segment, and are disposed laterally between a sidewall of the single one of the peripheral segments and a single one of the isolation edges neighboring the single one of the peripheral segments, wherein the sidewall of the single one of the peripheral segments overlies the isolation structure, and wherein the multiple gate contact vias are laterally between and laterally spaced from the axis of the single one of the peripheral segments and the sidewall of the single one of the peripheral segments.

US Pat. No. 10,692,787

RESIN SUBSTRATE, COMPONENT-MOUNTING RESIN SUBSTRATE, AND METHOD OF MANUFACTURING COMPONENT-MOUNTING RESIN SUBSTRATE

MURATA MANUFACTURING CO.,...

1. A resin substrate comprising:a thermoplastic resin body including a mounting area in which a component is to be mounted by hot pressing;
a cavity defined in the mounting area of the resin body and extending from a front surface to a back surface of the resin body; and
a plating layer disposed on a wall surface of the cavity and including a material harder than the resin body; wherein
a space in the cavity connecting the front surface and the back surface is defined by the plating layer disposed on the wall surface of the cavity;
the resin body includes thermoplastic resin layers that are stacked in a stacking direction;
the resin body includes conductor patterns extending in a direction perpendicular or substantially perpendicular to the stacking direction; and
the conductor patterns are physically connected to the plating layer.

US Pat. No. 10,692,786

SEMICONDUCTOR STRUCTURES

Vanguard International Se...

1. A semiconductor structure, comprising:a substrate having a chip region and a seal ring region;
a first insulating layer disposed on the substrate;
a second insulating layer disposed on the first insulating layer;
a first seal ring structure disposed in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure comprises a stack of metal layers;
a second seal ring structure disposed in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure comprises a polysilicon ring structure; and
a passivation layer disposed on the second insulating layer and the first seal ring structure;
wherein from a top view, the seal ring region surrounds the chip region, wherein the second seal ring structure surrounds the chip region and the first seal ring structure surrounds the second seal ring structure.

US Pat. No. 10,692,785

SEMICONDUCTOR PATTERN FOR MONITORING OVERLAY AND CRITICAL DIMENSION AT POST-ETCHING STAGE AND METROLOGY METHOD OF THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor pattern for monitoring an overlay and a critical dimension at a post-etching stage, comprising:a first inverted-T shaped pattern with a base portion extending in a first direction and a middle portion extending from said base portion in a second direction orthogonal to said first direction; and
a second pattern adjacent and spaced apart from said base portion of said first inverted-T shaped pattern, wherein said first inverted-T shaped pattern is composed of a plurality of first spacer patterns spaced apart from each other and extending in said second direction, and said second pattern is composed of a plurality of second spacer patterns spaced apart from each other and extending in said second direction.