US Pat. No. 10,658,644

BATTERY

Ningde Amperex Technology...

1. A battery comprising:an electrode assembly;
a package film packaging the electrode assembly;
wherein the package film comprises a folding portion, the folding portion comprises a first segment attached to an end face of the electrode assembly and a second segment connected to the first segment;
the first segment is arranged between the second segment and the electrode assembly, and the second segment comprises a plurality of multilayer package films, wherein the electrode assembly comprises a separator, and at least a portion of the separator is located between the plurality of multilayer package films of the second segment.

US Pat. No. 10,658,643

ELECTRODE ASSEMBLY AND METHOD OF MANUFACTURING ELECTRODE ASSEMBLY

KABUSHIKI KAISHA TOYOTA J...

1. An electrode assembly comprising:positive electrode plates, each of which includes a front positive electrode active material layer provided on a front surface of a positive electrode metal foil and a rear positive electrode active material layer provided on a rear surface of the positive electrode metal foil;
negative electrode plates, each of which includes a front negative electrode active material layer provided on a front surface of a negative electrode metal foil and a rear negative electrode active material layer provided on a rear surface of the negative electrode metal foil; and
separators, each of which is interposed between each of the positive electrode plates and each of the negative electrode plates,
wherein the front positive electrode active material layer has a positive electrode large tapered portion that extends at an incline from one edge of the front surface of the positive electrode metal foil to an inner side of the positive electrode plate at a positive electrode large inclination angle,
wherein the rear positive electrode active material layer has a positive electrode small tapered portion that extends at an incline from one edge of the rear surface of the positive electrode metal foil to the inner side of the positive electrode plate at a positive electrode small inclination angle, which is smaller than the positive electrode large inclination angle,
wherein the front negative electrode active material layer has a negative electrode large tapered portion that at an incline from one edge of the front surface of the negative electrode metal foil to an inner side of the negative electrode plate at a negative electrode large inclination angle,
wherein the rear negative electrode active material layer has a negative electrode small tapered portion that extends at an incline from one edge of the rear surface of the negative electrode metal foil to the inner side of the negative electrode plate at a negative electrode small inclination angle, which is smaller than the negative electrode large inclination angle,
wherein the positive electrode plates and the negative electrode plates are alternately laminated with the separator or separators interposed therebetween such that the front surface of the positive electrode plates having the positive electrode large tapered portion and the front surface of the negative electrode plates having the negative electrode large tapered portion are oriented in the same direction in a rear-to-front directional axis along a thickness of the positive electrode plates and the negative electrode plates,
wherein one of the positive electrode plates or the negative electrode plates constitutes an electrode plate unit enveloped by a separator forming a bag shape with the separator having a larger surface area than that of the one of the positive electrodes or negative electrode plates,
wherein the positive electrode large inclination angle is set to be smaller than the negative electrode large inclination angle in the case where one of the positive electrode plates constitutes the electrode plate unit, and
wherein the negative electrode large inclination angle is set to be smaller than the positive electrode large inclination angle in the case where one of the negative electrode plates constitutes the electrode plate unit.

US Pat. No. 10,658,642

CARBON MATRIX- AND CARBON MATRIX COMPOSITE-BASED DENDRITE-INTERCEPTING LAYER FOR ALKALI METAL SECONDARY BATTERY

Global Graphene Group, In...

1. A dendrite penetration-resistant layer for a rechargeable alkali metal battery, said layer comprising an amorphous carbon matrix, a carbon-containing reinforcement phase dispersed in said matrix, and a sodium-containing species that is chemically bonded to said matrix to form an integral layer that prevents dendrite penetration through said integral layer in said alkali metal battery, wherein the sodium-containing species is selected from Na2CO3, Na2O, Na2C2O4, NaOH, NaX, ROCO2Na, HCONa, RONa, (ROCO2Na)2, (CH2OCO2Na)2, Na2S, NaxSOy, or combinations thereof, wherein X=F, Cl, I, or Br, R=a hydrocarbon group, 0

US Pat. No. 10,658,641

SEPARATOR COMPRISING COATING LAYER, AND BATTERY USING SAME

Samsung SDI Co., Ltd., Y...

1. A separator comprising a base film and a coating layer including an organic binder and an inorganic particle on one surface or both surfaces of the base film,wherein the organic binder includes an acryl-based copolymer and a polyvinylidene fluoride-based binder, wherein a weight ratio of the acryl-based copolymer and the polyvinylidene fluoride-based binder is 5:5 to 8:2,
wherein the polyvinylidene fluoride-based binder has a weight average molecular weight of 500,000 g/mol to 1,500,000 g/mol,
wherein the acryl-based copolymer has a glass transition temperature (Tg) of 30° C. to less than 60° C.,
wherein the acryl-based copolymer includes a repeating unit derived from a butyl (meth)acrylate monomer and a methyl (meth)acrylate monomer and a repeating unit derived from a vinyl acetate monomer,
wherein the acryl-based copolymer is prepared by polymerizing the butyl (meth)acrylate monomer, the methyl (meth)acrylate monomer, and the vinyl acetate monomer in a mole ratio of 3.5 to 4.5:0.5 to 1.5:4 to 6, and
wherein a rate of a thickness change of the separator according to Equation 1 is less than or equal to 3%,
Rate of a thickness change (%)=[(T2?T1)/T1]×100  [Equation 1]
wherein, in Equation 1, T1 is a thickness of an electrode assembly that is provided by interposing a separator between a positive electrode and a negative electrode, sequentially stacking the positive electrode, the separator, and the negative electrode, winding the stack several times to have a size of 7 cm (length)×6.5 cm (width) to provide a jelly-roll shaped electrode assembly, and pressing the electrode assembly at 60° C. to 100° C. with a pressure of 10 kgf/cm2 to 50 kgf/cm2 for 1 second to 5 seconds, and T2 is a thickness of an electrode assembly that is provided by being allowed to stand at 15° C. to 30° C. for 48 hours after the pressing.

US Pat. No. 10,658,640

POLYOLEFIN MICROPOROUS MEMBRANE, PRODUCTION METHOD THEREOF, SEPARATOR FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

TORAY INDUSTRIES, INC., ...

1. A polyolefin microporous membrane, comprising: a temperature difference not less than 7.2° C. between a shutdown shrinkage temperature and a maximum shrinkage temperature in a direction transverse to a machine direction (TD) as measured by a thermomechanical analyzer (TMA);a rate difference less than 25% between a shutdown shrinkage rate and a maximum shrinkage rate in the TD;
a pin puncture strength at a membrane thickness of 16 ?m being not less than 400 gf; and
a ratio of pin puncture strength to air permeation resistance at a membrane thickness of 16 ?m being from 2.0 to 4.0 (gf/(sec/100 cc)).

US Pat. No. 10,658,639

METHOD OF PREPARING MICROPOROUS MEMBRANE, MICROPOROUS MEMBRANE, BATTERY SEPARATOR, AND SECONDARY BATTERY

Toray Industries, Inc., ...

1. A method of producing a microporous membrane comprising:1) melt-kneading a) a primary material comprising a high density polyethylene having an average particle diameter of 105 ?m or more and having a molecular weight (Mw) of less than 1.0×106, b) a secondary material comprising an ultrahigh molecular weight polyethylene having an average particle diameter of 90 ?m or more and having a molecular weight of 1.0×106 or more and less than 4.0×106, and c) a plasticizer, wherein the plasticizer is added in two or more places during melt-kneading and 50 to 95 wt % of the plasticizer is added at an upstream side of the melt-kneading;
2) extruding the molten mixture obtained in step 1) through a spinneret to mold into a sheet shape;
3) stretching the sheet obtained in step 2) by a sequential stretching method including a roll system or a tenter system; and
4) extracting the plasticizer from the stretched film obtained in step 3) to produce a polyolefin microporous membrane,
wherein, when an endothermic quantity of a mixture of the primary material and the plasticizer and an endothermic quantity of a mixture of the secondary material and the plasticizer are denoted as Q1 and Q2, respectively, a ratio of the endothermic quantity Q2 to the endothermic quantity Q1, (endothermic quantity Q2/endothermic quantity Q1), is 1 or more over a temperature range of 110 to 118° C.,
a ratio of the average particle diameter of the primary material to the average particle diameter of the secondary material is 0.3 to 1.5,
a proportion of the ultrahigh molecular weight polyethylene to the primary and secondary materials is 6 mass % or more, and
a content of the primary and secondary materials is 10 to 50 wt % based on the weight of the primary and secondary materials and the plasticizer.

US Pat. No. 10,658,638

RECHARGEABLE BATTERY

Samsung SDI Co., Ltd., Y...

1. A rechargeable battery comprising:an electrode assembly;
a case configured to accommodate the electrode assembly and having an opening at one side thereof; and
a cap assembly comprising:
a cap plate configured to close and seal the opening of the case, the cap plate having a vent portion and defining a vent opening that is configured to discharge an internal gas generated inside the case to outside of the case, the vent portion comprising:
a vent plate configured to close and seal the vent opening, the vent plate comprising:
a connecting portion located below the cap plate at the vent opening; and
a rupture portion having a notch at a lower portion thereof, the notch facing inside the case; and
a bending portion that is raised from the vent plate and encloses the rupture portion; and
an electrode terminal at an upper portion of the cap plate and electrically connected to the electrode assembly.

US Pat. No. 10,658,637

APPARATUS FOR INCREASING SAFETY WHEN USING BATTERY SYSTEMS

Robert Bosch GmbH, Stutt...

1. A battery system, comprising:at least one battery apparatus, having at least one safety apparatus configured to increase safety when using a degassing apparatus,
wherein the degassing apparatus is configured to degas battery apparatuses in a controlled manner, and
wherein the battery apparatus and the safety apparatus are surrounded by a housing and the degassing apparatus is inserted into a wall of the housing,
wherein the safety apparatus produces a gap between the battery apparatus and the degassing apparatus such that a space is kept free between the battery apparatus and the degassing apparatus so as to dissipate substances that escape from the battery apparatus in an area surrounding the battery system,
wherein the safety apparatus is configured to generate a force effect on the degassing apparatus in dependence upon a state of the battery apparatus, and the effect of the force causes the degassing apparatus to open, and
wherein the safety apparatus includes a mechanical bursting element opener configured to generate the force effect on the degassing apparatus via action of the mechanical bursting element opener on the degassing apparatus.

US Pat. No. 10,658,636

POWER STORAGE DEVICE

PANASONIC INTELLECTUAL PR...

1. A power storage device comprising:a plurality of battery modules;
a rack for arranging and housing the plurality of battery modules; and
a wall plate attached to one side-surface of the rack, and
a fan for generating a flow of air to cool the battery module attached to the wall plate, the wall plate facing a connector terminal detachably connected to each of the battery modules, and being transparent at least in part,
wherein the wall plate includes
a transparent resin plate that faces the connector terminal, being made of a transparent plate material, and
a metal plate that does not face the connector terminal, being made of a metal plate, and
the fan is attached to the transparent resin plate.

US Pat. No. 10,658,635

BATTERY PACK AND VEHICLE EQUIPPED WITH SAME

SANYO ELECTRIC CO., LTD.,...

1. A battery pack comprising:a cell stacked body including a plurality of stacked rectangular cells;
a first end plate disposed at a first end of the cell stacked body in a stacking direction of the plurality of rectangular cells;
a second end plate disposed at a second end of the cell stacked body in the stacking direction of the plurality of rectangular cells; and
a connection member coupled to the first end plate and the second end plate,
wherein at least one of the first end plate and the second end plate includes a first member made of a first metal material and a second member made of a second metal material different from the first metal material,
wherein the first member and the second member are stacked in the stacking direction of the plurality of rectangular cells,
wherein a rigidity of the second metal material is higher than a rigidity of the first metal material,
wherein a specific gravity of the first metal material is lower than a specific gravity of the second metal material, and
wherein the second member is disposed between the first member and the cell stacked body, and a vertical length of the second member is less than a height of the first member such that the second member presses a part of an adjacent one of the rectangular cells other than an upper end thereof.

US Pat. No. 10,658,634

COLLAR FOR SEALING A BATTERY MODULE

CPS Technology Holdings, ...

1. A battery module, comprising:a housing comprising a first absorptive material configured to absorb a laser emission;
a cover comprising a second absorptive material configured to absorb the laser emission; and
a collar coupled to the housing and coupled to the cover via a laser weld, wherein the collar comprises a transparent material configured to transmit the laser emission through the collar and toward the housing and the cover, and wherein the laser weld is formed by a process comprising:
disposing the cover over a receptacle region of the housing;
disposing the collar around a first perimeter of the housing and a second perimeter of the cover;
directing a laser toward a third perimeter of the collar such that the laser is transmitted through the transparent material and is absorbed by the first absorptive material and the second absorptive material;
heating the first absorptive material and the second absorptive material such that a first portion of the first absorptive material increases in temperature and forms a first molten material and a second portion of the second absorptive material increases in temperature and forms a second molten material; and
cooling the first molten material and the second molten material to adhere the housing to the collar and adhere the cover to the collar.

US Pat. No. 10,658,633

BATTERY AND MANUFACTURING METHOD OF THE BATTERY

Panasonic Intellectual Pr...

1. A battery, comprising:a first electrode plate;
a second electrode plate having polarity opposite to that of the first electrode plate;
a separator interposed between the first and second electrode plates;
a closed-end cylindrical metal case configured to accommodate the first electrode plate, the second electrode plate, and the separator; and
a sealing member configured to seal an opening of the metal case with an insulating member interposed therebetween, wherein
the first and second electrode plates are wound with the separator interposed therebetween to form a wound electrode group,
the first electrode plate includes a first electrode core material, a first electrode active material which is disposed on the first electrode core material,
a center axis portion of the wound electrode group includes a center axis of a cylinder of the metal case, and contains no power-generating element,
the metal case is a first electrode terminal, and the sealing member is a second electrode terminal,
a first current collector lead electrically coupled to the first electrode core material extends toward the opening of the metal case, and joined to an inner sidewall surface of the metal case,
a second current collector lead electrically coupled to the second electrode plate extends toward the opening of the metal case, and joined to the sealing member,
the first current collector lead is joined to the inner sidewall surface of the metal case at a welding point which is located at a position closer to the opening of the metal case than an uppermost portion of the wound electrode group when viewed along a longitudinal axis of the metal case, and
a length of the first current collector lead in a circumferential direction of the wound electrode group ranges from 10% to 30%, both inclusive, of a length of an outer periphery of the wound electrode group.

US Pat. No. 10,658,632

BATTERY HOUSINGS FOR ACCOMMODATING SWELLING OF ELECTRODE ASSEMBLIES

1. A battery, comprising:an electrode assembly comprising a cathode and an anode;
a receptacle comprising at least one feedthrough disposed through one or more sides of the receptacle; and
a lid sealed to the receptacle;
wherein the receptacle, the at least one feedthrough, and the lid form a sealed volume in which the electrode assembly and an electrolyte are disposed;
wherein the lid is configured to displace from a first position to a second position in response to a swelling of the electrode assembly within the sealed volume; and
wherein the receptacle is configured to strain less than the lid during the swelling of the electrode assembly.

US Pat. No. 10,658,631

SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:an electrode assembly having a curved shape and comprising a first electrode plate, a second electrode plate, and a separator located between the first electrode plate and the second electrode plate,
an exterior member comprising a first exterior member on a first surface of the electrode assembly, a second exterior member on a second surface of the electrode assembly, and exterior member wings providing a sealing surface by coupling the first exterior member and the second exterior member, the exterior member wings being folded to extend perpendicular to the first and second surfaces of the electrode assembly, and
a label covering an outer surface of the exterior member, wherein the label comprises:
a label body sheet that is attached to the first exterior member,
a plurality of label wings that are folded from a first edge of the label body sheet in a first direction and cover the exterior member including the folded exterior member wings from side surfaces of the exterior member to the second exterior member to prevent the folded exterior member wings from unfolding, and
at least one cutting slot, wherein the at least one cutting slot is located between adjacent ones of the label wings such that the label wings are independently foldable, the at least one cutting slot is defined to extend past a periphery of a respective one of the label wings, and the at least one cutting slot is formed across the respective label wing from a first edge of the label wing toward the label body sheet.

US Pat. No. 10,658,630

EVAPORATION PLATE FOR DEPOSITING DEPOSITION MATERIAL ON SUBSTRATE, EVAPORATION APPARATUS, AND METHOD OF DEPOSITING DEPOSITION MATERIAL ON SUBSTRATE

BOE Technology Group Co.,...

1. An evaporation plate for depositing a deposition material on a substrate, comprising a sequentially stacked structure:wherein the sequentially stacked structure comprises:
a first heating layer;
a first cooling layer;
a main body plate;
a second cooling layer; and
a second heating layer;
wherein the first cooling layer and the first heating layer are sequentially stacked on a first side of the main body plate;
the second cooling layer and the second heating layer are sequentially stacked on a second side of the main body plate;
the second side is opposite to the first side;
the main body plate is between the first cooling layer and the second cooling layer;
the first cooling layer is between the first heating layer and the main body plate, and is configured to cool the first heating layer on the first side of the main body plate;
the first heating layer is configured to heat a first material deposited on the first side of the main body plate;
the second cooling layer is between the second heating layer and the main body plate, and is configured to cool the second heating layer on the second side of the main body plate; and
the second heating layer is configured to heat a second material deposited on the second side of the main body plate.

US Pat. No. 10,658,629

ORGANIC ELECTROLUMINESCENT ELEMENT, ORGANIC ELECTROLUMINESCENT PANEL, ORGANIC ELECTROLUMINESCENT DEVICE AND ELECTRONIC APPARATUS

JOLED INC., Tokyo (JP)

1. An organic electroluminescent panel, comprising:a plurality of pixels, wherein
each pixel of the plurality of pixels has a plurality of sub-pixels,
each sub-pixel of the plurality of sub-pixels has an organic electroluminescent element,
the organic electroluminescent element comprises:
a first electrode;
a hole transport layer;
a first light emitting layer that comprises:
a second light emitting layer, and
a third light emitting layer;
an electron transport layer; and
a second electrode, wherein
the first light emitting layer is a hybrid of the second light emitting layer on the third light emitting layer,
the second light emitting layer is a first coating film on a hole transport layer side of the first light emitting layer, and
the third light emitting layer is a first vapor-deposited film on an electron transport layer side of the first light emitting layer
the plurality of sub-pixels includes a first sub-pixel adapted to emit red light, a second sub-pixel adapted to emit green light, and a third sub-pixel adapted to emit blue light,
the third sub-pixel includes the first light emitting layer,
each of the first sub-pixel and the second sub-pixel have a fourth light emitting layer including a third coating film, and
the third light emitting layer is over whole surface of the fourth light emitting layer.

US Pat. No. 10,658,628

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND A METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting display (OLED) device, comprising:a substrate comprising a display region including a pixel region and a peripheral region surrounding the pixel region, a pad region that is spaced apart from the display region, and a bending region that is positioned between the display region and the pad region;
a buffer layer disposed on the substrate, the buffer layer including a first opening exposing an upper surface of the substrate that is positioned in the bending region;
pixel structures in the pixel region on the buffer layer;
an insulation layer structure disposed on the buffer layer, the insulation layer structure including a second opening exposing the upper surface of the substrate that is positioned in the bending region and a first portion of the buffer layer that is positioned adjacent to the bending region;
a fan-out wiring positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed;
a passivation layer disposed on the fan-out wiring, side walls of the insulation layer structure that is positioned adjacent to the bending region, and the first portion of the buffer layer, the passivation layer including a third opening exposing the upper surface of the substrate that is positioned in the bending region; and
a connection electrode in the bending region, the connection electrode being positioned above the substrate, the connection electrode being in direct contact with the fan-out wiring, and the connection electrode being electrically connected to the pixel structure and an external device,
wherein the passivation layer includes a first contact hole that is positioned n the peripheral region and a second contact hole that is positioned in the pad region, and
wherein the fan-out writing is in direct contact with the connection electrode through the first and second contact holes.

US Pat. No. 10,658,627

METHOD FOR MANUFACTURING A DISPLAY APPARATUS

Sakai Display Products Co...

1. A method for manufacturing a display apparatus comprising:forming a display panel by forming a plurality of display elements on a substrate having flexibility;
preparing a holding member to be engaged with an outer periphery of the display panel;
preparing a supporting member having a surface on which the substrate of the display panel is to be placed;
placing the substrate on the surface of the supporting member;
bonding the holding member to the surface of the supporting member;
bringing the substrate into close contact with the surface of the supporting member at a strength lower than a bonding strength between the holding member and the surface of the supporting member; and
engaging the holding member with an entire of an outer edge of the display panel before or after or simultaneously with placing the substrate on the surface,
wherein the holding member is prepared so as to have a frame shape along the entire of the outer edge of the display panel, and a suction port is formed at the holding member, the suction port communicating with inside of the frame shape of the holding member and communicating with outside of the frame shape of the holding member; and
the substrate is brought into close contact with the surface of the supporting member by suctioning gas from the inside of the frame shape of the holding member by using the suction port after bonding the holding member to the surface of the supporting member.

US Pat. No. 10,658,626

ORGANIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. An organic light emitting device comprising:a flexible substrate;
an organic light emitting element on the flexible substrate in a display area of the flexible substrate;
a thin film encapsulating film covering the organic light emitting element; and
a bottom protecting film attached to a bottom of the flexible substrate, the bottom protecting film comprising a light blocking layer for blocking external light, an adhesive layer between the light blocking layer and the flexible substrate, a heat dissipating plate, and an additional adhesive layer between the heat dissipating plate and the light blocking layer,
wherein the heat dissipating plate and the light blocking layer directly contact the additional adhesive layer in a region overlapping the display area along a direction perpendicular to the display area.

US Pat. No. 10,658,625

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a substrate;
a first organic light-emitting diode including a first electrode provided above the substrate for each of pixels, a second electrode, and a first light-emitting layer provided between the first electrode and the second electrode, and
a heat source resistor provided in one of the pixels where the first organic light-emitting diode is disposed, wherein
one end of the heat source resistor is connected to a first heat-source power supply line control circuit controlling a potential at the one end of the heat source resistor,
the other end of the heat source resistor is connected to the second electrode, and
the first heat-source power supply line control circuit controls, in supplying heat to the first light-emitting layer, the potential at the one end of the heat source resistor so as to be different from a potential of the second electrode.

US Pat. No. 10,658,624

ELECTRONIC DEVICE HAVING AN ORGANIC LIGHT EMITTING DISPLAY

Intel Corporation, Santa...

1. An electronic device comprising:an organic light emitting display (OLED) having a first end and a second end; and
a heat generating device to provide signals to the OLED; and
a heat spreading device between the OLED and the heat generating device, the heat spreading device being immediately adjacent to the OLED extending from the first end of the OLED to the second end of the OLED, and the heat generating device being in direct contact with the heat spreading device, wherein the heat spreading device is configured to dissipate heat generated by the heat generating device.

US Pat. No. 10,658,623

ELECTROLUMINESCENT DISPLAY DEVICE HAVING A PLURALITY OF LOW-REFRACTIVE MEMBERS

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device comprising:an overcoat layer on a substrate;
a plurality of low-refractive members formed of an inorganic matter and disposed on the overcoat layer;
a first electrode on the overcoat layer and the plurality of low-refractive members;
a bank layer disposed on the overcoat layer and the first electrode and including an opening configured to expose the first electrode;
an emitting layer disposed on the first electrode; and
a second electrode disposed on the emitting layer,
wherein each of the plurality of low-refractive members includes a first flat surface overlaid by the first electrode, a second flat surface below the first flat surface, the second flat surface having an area greater than that of the first flat surface and overlying the overcoat layer, the low-refractive member including first and second inclined surfaces extending between the first flat surface and the second flat surface, and
wherein a refractive index of each of the plurality of low-refractive members is lower than those of the overcoat layer and the first electrode.

US Pat. No. 10,658,622

DISPLAY DEVICE WITH SUB-PIXEL REGIONS INCLUDING ZONE PLATES HAVING PLURALITY OF RING GROUPS AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising:a display panel and a light ray control component disposed on a light emergent side of the display panel, wherein the light ray control component comprises a plurality of zone plates,
wherein the display panel comprises a plurality of pixel regions, each pixel region comprises a plurality of sub-pixel regions, each sub-pixel region corresponds to one of the plurality of zone plates, and the one of the plurality of zone plates corresponding to any sub-pixel region in the plurality of sub-pixel regions is used to control a direction of light rays emitted from the any sub-pixel region,
wherein the plurality of zone plates are made of a transparent material, the one of the plurality of zone plates corresponding to the any sub-pixel region comprises a first ring group and a second ring group, rings in the first ring group and rings in the second ring group are alternately disposed from inside to outside along a radial direction of the one of the plurality of zone plate; and
wherein thicknesses of the plurality of zone plates at the rings in the first ring group each have a first thickness, thicknesses of the plurality of zone plates at the rings in the second ring group each have a second thickness, the absolute value of a thickness difference between the first thickness of the one of the plurality of zone plates at the rings in the first ring group and the second thickness of the one of the plurality of zone plates at the rings in the second ring group meets nd=?/2, wherein n is a refractive index of a material of the one of the plurality of zone plates, d is the thickness difference, and ? is a wavelength of the light rays emitted from the any sub-pixel region.

US Pat. No. 10,658,621

OLED PANEL AND MANUFACTURING METHOD THEREOF AND OLED DISPLAY

Wuhan China Star Optoelec...

1. An organic light-emitting diode (OLED) panel, comprising:a thin film transistor (TFT) substrate;
a pixel defining layer located on the TFT substrate, wherein the pixel defining layer defines a plurality of light-emitting regions of the OLED panel on the TFT substrate;
a reflecting wall located between two adjacent light-emitting regions and within the pixel defining layer; and
a package layer located on a top surface of the pixel defining layer; wherein a top of the reflecting wall extends to the package layer;
wherein a bottom of the reflecting wall extends to the TFT substrate.

US Pat. No. 10,658,620

ELECTRO-OPTICAL DEVICE AND ELECTRONIC EQUIPMENT

SEIKO EPSON CORPORATION, ...

1. An electro-optical device comprising:a reflective layer;
a semitransparent reflective layer;
a first pixel having a first optical path length adjustment layer provided between the reflective layer and the semitransparent reflective layer, and a first luminescence functional layer provided between the reflective layer and the semitransparent reflective layer; and
a second pixel having a second optical path length adjustment layer provided between the reflective layer and the semitransparent reflective layer, and a second luminescence functional layer provided between the reflective layer and the semitransparent reflective layer, wherein:
the first optical path length adjustment layer includes a luminance adjustment layer, and the second optical path length adjustment layer does not include the luminance adjustment layer, and
the luminance adjustment layer of the first pixel includes a metal layer.

US Pat. No. 10,658,619

ELECTROLUMINESCENT DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An electroluminescent display device, comprising:an overcoat layer above a substrate including a plurality of subpixel regions;
a first electrode on the overcoat layer and disposed in each of the plurality of subpixel regions, the first electrode including a plurality of holes exposing the overcoat layer within respective subpixel regions;
at least one light extraction pattern in at least one of the plurality of holes and on the overcoat layer;
an emission layer on the first electrode and the at least one light extraction pattern; and
a second electrode on the emission layer.

US Pat. No. 10,658,618

DISPLAY DEVICE AND PACKAGING METHOD THEREOF, DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising a base substrate; and a light-emitting unit and a packaging unit sequentially disposed on the base substrate;the packaging unit comprising a first packaging film layer, a second packaging film layer as well as a plurality of water-absorbing functional layers and an organic film layer located between the first packaging film layer and the second packaging film layer, the water-absorbing functional layers at least comprising a first water-absorbing functional layer and a second water-absorbing functional layer;
the water-absorbing functional layer being mainly formed of a self-healing material with water absorbability, wherein
both of the first packaging film layer and the second packaging film layer are inorganic film layers;
the water-absorbing functional layer is arranged between every adjacent film layers in the packaging unit, the first water-absorbing functional layer is in direct contact with both of the first packaging film layer and the organic film layer, and the second water-absorbing functional layer is in direct contact with both of the second packaging film layer and the organic film layer, and wherein
the self-healing material with water absorbability of the water-absorbing functional layer comprises a composite material of konjac glucomannan, polyacrylamide and nano-clay.

US Pat. No. 10,658,617

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a substrate having flexibility and including a first surface and a second surface opposing the first surface, and an outer edge;
a display area on the first surface of the substrate and including a plurality of pixels;
a periphery area on an outer side of the display area on the first surface; and
a sealing layer covering the display area and the periphery area, wherein
the display area and the periphery area comprise a first elements layer and a second elements layer, wherein, within the display area, the first elements layer includes a first plurality of transistors and the second elements layer includes a plurality of light emitting elements and one or more insulating layers, and within the periphery area, the first elements layer includes a second plurality of transistors and the second elements layer includes at least one or the one or more insulating layers, and the second elements layer is arranged on the first elements layer,
a groove passes through the first and second elements layers between the display area and the periphery area,
the sealing layer includes a first part that covers the first and second elements layers and a second part that runs through the groove and covers opposing edges of the first and second elements layers formed by the groove,
the periphery area includes a wiring part, wherein the first elements layer, the second elements layer and the sealing layer are arranged, the periphery area includes first opening part through the first and second elements layers, and the periphery area includes a second opening which penetrates the substrate and is arranged directly below the first opening part, and
a part of the wiring part, the first opening part, the second part of the sealing layer and the display area are arranged in a sequential order from the outer edge of the substrate.

US Pat. No. 10,658,616

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:an organic light emitting device; and
an encapsulation member on the organic light emitting device to seal the organic light emitting device,
wherein the encapsulation member comprises:
a lower encapsulation layer on the organic light emitting device, the lower encapsulation layer including oxynitride and nitride;
an organic layer on the lower encapsulation layer; and
an upper encapsulation layer on the organic layer,
wherein a content of oxynitride in the lower encapsulation layer increases with decreasing distance from the organic layer, the lower encapsulation layer including both oxynitride and nitride at a first distance from the organic layer along a thickness direction of the lower encapsulation layer.

US Pat. No. 10,658,615

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a display panel; and
a window coating layer disposed directly on an upper surface of the display panel,
wherein
the window coating layer comprises a first region which has an increasing elastic modulus in a direction from the display panel toward the window coating layer,
the window coating layer further comprises a second region and a third region, which are spaced apart from each other in the direction from the display panel toward the window coating layer with the first region interposed therebetween, and
each of the second region and the third region has a constant elastic modulus.

US Pat. No. 10,658,614

METHOD OF ENCAPSULATING A FLEXIBLE OLED PANEL AND ENCAPSULATION STRUCTURE

SHENZHEN CHINA STAR OPTOE...

6. An encapsulation structure of a flexible OLED panel, comprising:a TFT substrate;
an OLED device, disposed on the TFT substrate;
a first inorganic barrier layer, disposed on the TFT substrate and covering the OLED device;
a liquid metal layer, disposed on the first inorganic barrier layer;
a liquid metal oxide layer, covering a surface of the liquid metal layer;
an organic buffer layer, disposed on the first inorganic barrier layer and covering the liquid metal oxide layer; and
a second inorganic barrier layer, disposed on the first inorganic barrier layer and covering the organic buffer layer.

US Pat. No. 10,658,613

ORGANIC LIGHT EMITTING DIODE ENCAPSULATION STRUCTURE, DISPLAY APPARATUS AND ENCAPSULATION METHOD OF ORGANIC LIGHT EMITTING DIODE

BOE Technology Group Co.,...

1. An organic light emitting diode encapsulation structure, comprising:a base substrate provided with an organic light emitting diode device;
an encapsulation cover plate opposite to the base substrate; and
a first sealant and a second sealant,
wherein both the first sealant and the second sealant are between the encapsulation cover plate and the base substrate; the first sealant is at a side, which faces the base substrate, of the encapsulation cover plate, and the first sealant comprises a plurality of portions which are spaced apart with each other; the second sealant covers the organic light emitting diode device and at least a portion of the first sealant so that the organic light emitting diode device is sealed;
the second sealant is an integral structure which is continuously distributed, the second sealant covers all surfaces, which do not contact the encapsulation cover plate, of the plurality of protrusion portions of the first sealant, and at least a portion of the second sealant is between the first sealant and the organic light emitting diode device, so that the first sealant is spaced apart from the organic light emitting diode device by the second sealant;
the first sealant includes a filling material, the filling material comprises at least one selected from a group consisting of a moisture absorbing material, a heat dissipating material and an oxygen absorbing material, and the second sealant does not include the filling material.

US Pat. No. 10,658,612

DISPLAY PANEL HAVING PASSIVATION LAYER WITH PROTRUDING PORTIONS IN PERIPHERAL AREA FOR SEALANT

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:a first substrate; and
a second substrate facing the first substrate;
wherein the first substrate comprises:
a base substrate; and
an insulating passivation layer on the base substrate, the insulating passivation layer comprising a base portion extending from a display area of the display panel into a peripheral area of the display panel, and a protruding portion in the peripheral area and on a side of the base portion in the peripheral area away from the base substrate;
wherein the display panel further comprises:
a sealant layer on a side of the protruding portion away from the base portion, the sealant layer in the peripheral area of the display panel, and configured to seal the first substrate and the second substrate together to form a cell;
an organic light emitting layer in the display area and on a side of the insulating passivation layer away from the base substrate; and
an encapsulating film on a side of the organic light emitting layer away from the base substrate for encapsulating the organic light emitting layer;
wherein the protruding portion encloses the display area of the display panel;
the insulating passivation layer in a region having the protruding portion has a first total thickness greater than a second total thickness of the insulating passivation layer in regions outside the region having the protruding portion;
the first total thickness comprises a thickness of the base portion in the region having the protruding portion and a thickness of the protruding portion;
the sealant layer is in direct contact with the protruding portion and is limited in the region having the protruding portion;
lateral sides of the sealant layer and the protruding portion in the peripheral area are in direct contact with the encapsulating film; and
a maximum height of the protruding portion relative to the base substrate is greater than a maximum height of the organic light emitting layer relative to the base substrate.

US Pat. No. 10,658,611

ENCAPSULATION METHOD OF OLED PANEL AND A ENCAPSULATION STRUCTURE THEREOF

SHENZHEN CHINA STAR OPTOE...

7. A encapsulation structure of an OLED panel, comprising: a TFT substrate; an OLED device disposed on the TFT substrate; a encapsulation cover plate disposed above the TFT substrate, a sealant disposed between the TFT substrate and the encapsulation cover plate outside the OLED device, an inorganic insulating layer disposed on the TFT substrate between the OLED device and the sealant, and a liquid metal disposed between the inorganic insulating layer and the encapsulation cover plate.

US Pat. No. 10,658,610

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus comprising:a display member comprising a base substrate and a plurality of pixels disposed on the base substrate to display an image;
a window member disposed on the display member and comprising a transparent part through which the image is transmitted and a bezel part disposed between the transparent part and the display member and contacting the transparent part; and
a filling member disposed between the window member and the base substrate and contacting the bezel part,
wherein the bezel part comprises a first layer contacting the transparent part and a second layer disposed between the first layer and the filling member,
wherein the second layer has an opening that overlaps the filling member in a plan view, and
wherein the filling member is disposed in the opening.

US Pat. No. 10,658,609

ARRAY SUBSTRATE AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising:a plurality of pixel units which are arranged in an array, and which comprise a plurality of pixel electrodes arranged at intervals, respectively, wherein a third equivalent capacitance is formed between two adjacent ones of the plurality of pixel electrodes;
a conductive layer disposed above or below the two adjacent pixel electrodes, and configured such that when a preset electric potential is applied to the conductive layer, a first equivalent capacitance is formed between the conductive layer and a first one of the two adjacent pixel electrodes and a second equivalent capacitance is formed between the conductive layer and a second one of the two adjacent pixel electrodes, so that a total equivalent capacitance formed between the two adjacent pixel electrodes is less than the third equivalent capacitance;
wherein:
an orthogonal projection of each of the plurality of pixel electrodes on a plane in which the plurality of pixel electrodes are located has a rectangular shape, and an orthogonal projection of the conductive layer on the plane has a rectangular shape,
the first equivalent capacitance is calculated by a formula: CA=?*WA*LA/TA, where CA is the first equivalent capacitance, ? is a conductivity of a dielectric between the conductive layer and the first pixel electrode, between the conductive layer and the second pixel electrode, and between the first pixel electrode and the second pixel electrode, WA is a width of an overlap between the conductive layer and the first pixel electrode, LA is a length of the overlap between the conductive layer and the first pixel electrode, and TA is a distance between the conductive layer and the first pixel electrode;
the second equivalent capacitance is calculated by a formula: CB=?*WB*LB/TB, where CB is the second equivalent capacitance, WB is a width of an overlap between the conductive layer and the second pixel electrode, LB is a length of the overlap between the conductive layer and the second pixel electrode, and TB is a distance between the conductive layer and the second pixel electrode; and
the third equivalent capacitance is calculated by a formula: C=?*TO*L/D, where C is the third equivalent capacitance, TO is a thickness of each pixel electrode, D is a distance between the two adjacent pixel electrodes, and L is a length of each of the first pixel electrode and the second pixel electrode.

US Pat. No. 10,658,608

METHOD AND DEVICE FOR COUPLING MULTIPLE GROUND PLANES

Intel Corporation, Santa...

1. An electrically conductive apparatus, comprising:a channel shaped structure that comprises:
a base member extending along and parallel to a first plane and having an opening through the base member;
a first sidewall member disposed along a first side of the base member and extending a first distance from the base member; and
a second sidewall member disposed along a second side of the base member and extending a second distance from the base member, wherein:
the first sidewall member and the second sidewall member are parallel to one another; and
the second side of the base member is transversely opposed to the first side of base member across a width of the base member;
a first flexible member having a first longitudinal portion and a second longitudinal portion, wherein:
the first flexible member extends from the first sidewall member along a first path; and
the first longitudinal portion of the first flexible member physically couples to the first sidewall member;
a second flexible member having a third longitudinal portion and a forth longitudinal portion, wherein:
the second flexible member extends from the second sidewall member along a second path; and
the third longitudinal portion of the second flexible member physically couples to the second sidewall member; and
a third flexible member having a fifth longitudinal portion and a sixth longitudinal portion, wherein:
the third flexible member extends from the base member along a third path; and
the fifth longitudinal portion of the third flexible member is physically coupled to the base member; and
wherein:
the first path comprises a first curvilinear path and extends from the first sidewall member with at least a portion of the first flexible member extending below the first plane; and
the third path comprises a second curvilinear path and extends from the base member with at least a portion of the third flexible member extending above the first plane.

US Pat. No. 10,658,607

LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, METHOD FOR MANUFACTURING LIGHT-EMITTING ELEMENT, AND LIGHT EMISSION METHOD

SHARP KABUSHIKI KAISHA, ...

1. A light-emitting element comprising;a first electrode;
a second electrode; and
a functional layer containing at least a first light-emitting layer and a second light-emitting layer, the functional layer being disposed between the first electrode and the second electrode, wherein
the first light-emitting layer has an emission peak wavelength shorter than an emission peak wavelength of the second light-emitting layer, and contains a host material and a triplet-triplet-fusion (TTF) material or at least the TTF material, the TTF material being a delayed fluorescent material that causes a TTF phenomenon by the TTF material alone or in cooperation with the host material,
the second light-emitting layer is adjacent to the first light-emitting layer, and contains at least a thermally activated delayed fluorescent material, the thermally activated delayed fluorescent material being a delayed fluorescent material in which reverse intersystem crossing occurs from an excited triplet level to an excited singlet level by thermal activation, and
an excited triplet level of at least one of the host material and the TTF material contained in the first light-emitting layer is lower than the excited triplet level of the thermally activated delayed fluorescent material contained in the second light-emitting layer.

US Pat. No. 10,658,606

QUANTUM DOT LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND QUANTUM DOT LIGHT EMITTING DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A quantum dot light emitting device comprising:a first electrode and a second electrode;
a quantum dot light emitting layer interposed between the first electrode and the second electrode; and
a filling layer located on the quantum dot light emitting layer and embedded in the quantum dot light emitting layer,
wherein the filling layer has a thickness less than 5 nanometers (nm).

US Pat. No. 10,658,605

LIGHT EMITTING ASSEMBLY AND DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A light emitting assembly comprising:a plurality of pixels, wherein each of the plurality of pixels comprises:
a switching transistor that transfers a data voltage in response to a scan signal;
a storage capacitor that stores the data voltage transferred by the switching transistor;
a driving transistor coupled to a first power supply voltage line, and that generates a driving current based on the data voltage stored in the storage capacitor;
a plurality of light emitting elements that emit light based on the driving current, the light emitting elements having an ohmic contact resistance at anodes and cathodes of the light emitting elements;
a first sensing transistor that couples the light emitting elements to a sensing line in response to a sensing signal when a sensing operation for sensing the ohmic contact resistance of the light emitting elements is performed; and
a second sensing transistor that decouples the light emitting elements from a second power supply voltage line in response to an inverted sensing signal when the sensing operation is performed,
wherein the sensing signal is different from the scan signal, and
wherein the sensing signal having a voltage level to turn the first sensing transistor do not overlap the scan signal having the voltage level.

US Pat. No. 10,658,604

LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:a light-emitting layer comprising:
a first organic compound; and
a second organic compound,
wherein one of the first organic compound and the second organic compound has a LUMO level higher than or equal to a LUMO level of the other of the first organic compound and the second organic compound, and has a HOMO level higher than or equal to a HOMO level of the other of the first organic compound and the second organic compound,
wherein the first organic compound is configured to convert triplet excitation energy into light emission, and
wherein a relation 0 eV

US Pat. No. 10,658,603

ELECTRODE AND AN ORGANIC ELECTROLUMINESCENT DEVICE USING THE SAME

Kunshan New Flat Panel Di...

1. An electrode, comprising a first layer and a second layer arranged in a stacked manner, the first layer is an alkali earth metal alloy layer, and the second layer has a work function of 2.0 eV to 3.5 eV, wherein the second layer is a Yb2O3 layer, a doped layer of YbN and Yb, or a doped layer of Yb and Ce2O.

US Pat. No. 10,658,602

ORGANIC EL ELEMENT PRODUCTION METHOD AND ORGANIC EL ELEMENT HAVING CONDUCTIVE MEMBER ON EXTERNAL CONNECTION AREA OF FIRST ELECTRODE

SUMITOMO CHEMICAL COMPANY...

1. An organic EL element comprising:a supporting substrate;
a first electrode section provided on a main surface of the supporting substrate;
an organic EL section provided on the first electrode section and including a light-emitting layer; and
a second electrode section provided on the organic EL section and configured to supply electric power to the organic EL section in conjunction with the first electrode section,
wherein the first electrode section includes:
an organic EL section arrangement area on which the organic EL section is arranged; and
an external connection area being in contact with the organic EL section arrangement area in a predetermined direction and for externally connecting the organic EL section arrangement area, and
wherein a conductive member is provided on the external connection area, arranged apart from the second electrode section in the predetermined direction, and formed of the same material as a material of the second electrode section,
wherein the organic EL element further comprises a sealing member provided on the second electrode section, the conductive member and a clearance between the second electrode section and the conductive member,
wherein a width of the sealing member is shorter than a width of the supporting substrate in the predetermined direction, and
wherein, when the organic EL element is viewed from a thickness direction thereof, a side of an end of the second electrode section opposite to the clearance and a side of an end of the conductive member opposite to the clearance in the predetermined direction are exposed from the sealing member.

US Pat. No. 10,658,601

ORGANIC LIGHT-EMITTING DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. An organic light-emitting display panel, comprising:an array substrate comprising a plurality of driving units; and
a plurality of organic light-emitting units arranged to correspond to the plurality of driving units, wherein each of the plurality of organic light-emitting units comprises an anode, a cathode, and an organic functional layer arranged between the anode and the cathode,
wherein the organic functional layer comprises an organic light-emitting layer, a first electron transmission layer arranged between the cathode and the organic light-emitting layer, and a first hole transmission layer arranged between the anode and the organic light-emitting layer;
wherein the first electron transmission layer comprises a first electron transmission matrix and a first dopant, the first dopant comprising one or more substances selected from a group consisting of an alkaline earth metal element and a rare earth metal element; and
wherein the organic light-emitting layer comprises a blue light-emitting layer comprising a blue host material, and an electron mobility and a hole mobility of the blue host material satisfy:
the electron mobility of the blue host material>(the hole mobility of the blue host material)×102 under an electric field of 0.2 MV/cm.

US Pat. No. 10,658,600

METHOD OF FABRICATING FLEXIBLE SUBSTRATE HAVING LAMINATED MATERIAL MADE OF SILICON OXIDE AND AMORPHOUS SILICON

WUHAN CHINA STAR OPTOELEC...

1. A fabricating method of a flexible substrate, comprising the following steps:step 1: fabricating a first flexible base;
step 2: fabricating at least one layer of a laminated material made of silicon oxide and amorphous silicon on the first flexible base;
step 3: performing a dehydrogenation treatment to heat the laminated material and the first flexible base; and
step 4: fabricating a second flexible base on the laminated material to obtain a flexible substrate;
wherein a thickness of the first flexible base is greater than a thickness of the second flexible base, and a material of the first flexible base and the second flexible base is polyimide;
wherein the dehydrogenation treatment is performed under a protective atmosphere, a heating temperature under the protective atmosphere is of 420-550° C. and the heating time is of 15-60 min; and
wherein the first flexible base in step 1 and the second flexible base in step 4 are specifically fabricated by coating and curing, a curing temperature is higher than 20° C. and lower than the heating temperature during the dehydrogenation treatment.

US Pat. No. 10,658,599

SEMICONDUCTING MATERIAL AND NAPHTHOFURANE MATRIX COMPOUND FOR IT

Novaled GmbH, Dresden (D...

1. Semiconducting material comprisingan electron transport matrix compound comprising at least one electron transporting structural moiety and at least one polar structural moiety, the at least one polar structural moiety being selected
a) from a structural moiety consisting of one atom of 15th group of the Periodic Table and one atom of 16th group of the Periodic Table linked together by a covalent bond, or
b) from a heteroaryl that is unsubstituted and selected from pyridine-2-yl, pyridine-4-yl, quinoline-4-yl, or 1,3,5-triazine-2-yl, or
c) from a benzimidazolyl moiety having formula (Ia) or (Ib)

wherein the dashed line represents the bond attaching the benzimidazolyl moiety of formula (Ia) or (Ib) to other structural moieties of the molecule, R1 and R2 are selected from
(i) C1-C24 alkyl,
(ii) C3-C24 cycloalkyl,
(iii) C6-C24 aryl,
(iv) C7-C24 arylalkyl,
(v) C3-C24 heteroalkyl or C4-C24 heterocycloalkyl or C8-C24 aryl-heteroalkyl each comprising at least one heteroatom selected from Si or Ge,
(vi) C2-C24 heteroalkyl or C3-C24 heterocycloalkyl or C7-C24 aryl-heteroalkyl each comprising at least one heteroatom selected from B or P, or
(vii) C2-C24 heteroaryl comprising up to 4 heteroatoms independently selected from N, O, or S; wherein
the at least one electron transporting structural moiety comprises a benzo-naphthofurane structural moiety,
wherein the benzonaphthofurane structural moiety is a dinaphthofurane structural moiety and the dinaphthofurane structural moiety has the structure according to formula (II)

US Pat. No. 10,658,598

FLUORINATED AROMATIC SMALL MOLECULES AS FUNCTIONAL ADDITIVES FOR DISPERSION OF CONDUCTIVE POLYMERS

1. A composition comprisingI) at least one conductive polymer, wherein the conductive polymer comprises a complex of poly(3,4-ethylenedioxythiophene) (PEDOT) and polystyrenesulfonic acid (PSS),
II) water, and
III) at least one compound selected from the group consisting of formulae Xa to Xf, or a salt thereof

US Pat. No. 10,658,597

ORGANIC ELECTRONIC ELEMENT COMPRISING COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, AND ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound represented by Formula 1:
wherein
X and Y are independently O or S,
Ar1 and Ar2 are each independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group and combinations thereof,
q is an integer of 2, wherein Ar1s and Ar2s may be the same or different,
L is selected from the group consisting of a C6-C60 arylene group, a fluorenylene group, a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
R1 to R4 are i) each independently selected from the group consisting of hydrogen, deuterium, halogen, a C6-C60 aryl group, a fluorenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring, C1-C50 alkyl group, C2-C20 alkenyl group, C2-C20 alkynyl group, C1-C30 alkoxy group, C6-C30 aryloxy group, -L?-N(Ra)(Rb) and combinations thereof, or ii) at least one of adjacent R1s to R4s, when m, n, o and p are each an integer of 2 or more, may optionally form a ring, and R1 to R4 not forming a ring are the same as defined above,
m and n are each an integer from 0 to 4, o and p are each an integer of 0 to 3, when m, n, o and p are each an integer of 2 or more, each of plural R1s, R2s, R3s and R4s may be the same or different,
L? is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring, and C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, and
Ra and Rb may be each independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
where Ar1 and Ar2 are the aryl group or fluorenyl group, Ar1 and Ar2 are each optionally substituted with one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a siloxane group, a boron group, a germanium group, a cyano group, a nitro group, a C1-C20 alkylthio group, a C1-C20 alkoxy group, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, a fluorenyl group, a C3-C20 cycloalkyl group, a C7-C20 arylalkyl group, and a C8-C20 arylalkenyl group,
where L is the arylene group, fluorenylene group, fused ring group or hetero cyclic group, L is optionally substituted with one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a siloxane group, a boron group, a germanium group, a cyano group, a nitro group, a C1-C20 alkylthio group, a C1-C20 alkoxy group, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted with deuterium, a fluorenyl group, a C2-C20 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C3-C20 cycloalkyl group, a C7-C20 arylalkyl group, and a C8-C20 arylalkenyl group,
where R1 to R4 are the aryl group, fluorenyl group, hetero cyclic group, fused ring group, alkyl group, alkenyl group, alkynyl group, alkoxy group, or aryloxy group, R1 to R4 are each optionally substituted with one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a siloxane group, a boron group, a germanium group, a cyano group, a nitro group, a C1-C20 alkylthio group, a C1-C20 alkoxy group, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted with deuterium, a fluorenyl group, a C2-C20 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C3-C20 cycloalkyl group, a C7-C20 arylalkyl group, and a C8-C20 arylalkenyl group.

US Pat. No. 10,658,596

ORGANIC ELECTROLUMINESCENT DEVICE

KYUSHU UNIVERSITY, NATION...

1. An organic electroluminescent device comprising an anode, a cathode, and at least one organic layer including a light emitting layer between the anode and the cathode,the light emitting layer containing a first organic compound, a second organic compound, and at least one third organic compound that satisfy the following expressions (A) and (B), the second organic compound being a delayed fluorescent material, the second organic compound having an energy difference ?Est between a lowest singlet excited state and a lowest triplet excited state at 77 K of 0.3 eV or less, and the third organic compound being a light emitting material:
ES1(A)>ES1(B)>ES1(C)  (A)
 wherein ES1(A) represents a lowest singlet excitation energy level of the first organic compound; ES1(B) represents a lowest singlet excitation energy level of the second organic compound; and ES1(C) represents a lowest singlet excitation energy level of the third organic compound;
ET1(A)>ET1(B)  (B)
 wherein ET1(A) represents a lowest triplet excitation energy level at 77 K of the first organic compound; and ET1(B) represents a lowest triplet excitation energy level at 77 K of the second organic compound.

US Pat. No. 10,658,595

ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME

Samsung Display Co., Ltd....

1. An organic light emitting diode comprising:a first electrode;
a second electrode facing the first electrode;
a light emission layer between the first electrode and the second electrode;
an electron injection layer between the second electrode and the light emission layer;
a hole transport layer between the light emission layer and the first electrode; and
a hole injection layer between the hole transport layer and the first electrode,
wherein the electron injection layer comprises a dipolar material comprising a combination of a first component and a second component having different polarities and a first metal that is distinct from the first component and the second component,
wherein the first component comprises one selected from the group consisting of alkali metals, alkaline earth metals, rare earth metals, and transition metals of the periodic table, and
the hole injection layer comprises a dipolar material in which a metal or a non-metal having a work function of 4.3 eV or more is combined with a halogen.

US Pat. No. 10,658,594

ORGANIC ELECTROLUMINESCENCE DEVICE AND NOVEL COMPOUND

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by the following formula (3-I):
wherein in the formula (3-I),
one or more pairs of adjacent two or more of R1 to R7 and R10 to R16 may form a substituted or unsubstituted, saturated or unsaturated ring;
R1 to R7 and R10 to R16 that do not form the substituted or unsubstituted, saturated or unsaturated ring are independently a hydrogen atom, a substituted or unsubstituted alkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted haloalkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted alkenyl group including 2 to 50 carbon atoms, a substituted or unsubstituted alkynyl group including 2 to 50 carbon atoms, a substituted or unsubstituted cycloalkyl group including 3 to 50 ring carbon atoms, a substituted or unsubstituted alkoxy group including 1 to 50 carbon atoms, a substituted or unsubstituted alkylthio group including 1 to 50 carbon atoms, a substituted or unsubstituted aryloxy group including 6 to 50 ring carbon atoms, a substituted or unsubstituted arylthio group including 6 to 50 ring carbon atoms, a substituted or unsubstituted aralkyl group including 7 to 50 carbon atoms, —Si(R31)(R32)(R33), —C(?O)R34, —COOR35, —N(R36)(R37), a halogen atom, a cyano group, a nitro group, a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms, provided that one couple selected from R2 and R11, R4 and R13, and R5 and R14 are both —N(R36)(R37),
R17 is a hydrogen atom, a substituted or unsubstituted alkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted haloalkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted alkenyl group including 2 to 50 carbon atoms, a substituted or unsubstituted alkynyl group including 2 to 50 carbon atoms, a substituted or unsubstituted cycloalkyl group including 3 to 50 ring carbon atoms, a substituted or unsubstituted alkoxy group including 1 to 50 carbon atoms, a substituted or unsubstituted alkylthio group including 1 to 50 carbon atoms, a substituted or unsubstituted aryloxy group including 6 to 50 ring carbon atoms, a substituted or unsubstituted arylthio group including 6 to 50 ring carbon atoms, a substituted or unsubstituted aralkyl group including 7 to 50 carbon atoms, —Si(R31)(R32)(R33), —C(?O)R34, —COOR35, —N(R36)(R37), a halogen atom, a cyano group, a nitro group, a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms;
two R17s may be the same or different;
R31 to R35 are independently a hydrogen atom, a substituted or unsubstituted alkyl group including 1 to 50 carbon atoms, a substituted or unsubstituted cycloalkyl group including 3 to 50 ring carbon atoms, a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms;
R36 and R37 are independently a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms, provided that at least one of R36 and R37 is a substituted or unsubstituted monovalent heterocyclic group including 5 to 50 ring atoms;
when each of R31 to R37 is present in plural, each of the plural R31s to R37s may be the same or different.

US Pat. No. 10,658,593

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD, Seo...

1. An organic light emitting display device, comprising:at least one light emitting part between an anode and a cathode, the at least one light emitting part having at least one organic layer and a light emitting layer,
wherein the at least one organic layer comprises a hole injection layer,
wherein the hole injection layer comprises a compound represented by Chemical Formula 2:

in the Chemical Formula 2, R1 to R6 include independently one among hydrogen, a substituted or unsubstituted aryl group with 6 to 12 carbon atoms, a substituted or unsubstituted heteroaryl group with 1 to 12 carbon atoms and 1 to 4 heteroatoms one among O, N, S, and Si, a substituted or unsubstituted alkyl group with 1 to 12 carbon atoms, a substituted or unsubstituted alkoxy group with 1 to 12 carbon atoms, a substituted or unsubstituted ether group with 1 to 12 carbon atoms, a cyano group, a fluorine group, a trifluoromethyl group, a trifluoromethoxy group, and a trimethylsilyl group, and at least one of R1 to R6 comprises a cyano group, and
in Chemical Formula 2, Z1 and Z2 are independently represented by the following Chemical Formula 3:

where A and B independently represent one among a hydrogen atom, a substituted or unsubstituted aryl group with 6 to 12 carbon atoms, a substituted or unsubstituted heteroaryl group with 1 to 12 carbon atoms and 1 to 4 heteroatoms one among O, N, S, and Si, a substituted or unsubstituted alkyl group with 1 to 12 carbon atoms, a substituted or unsubstituted alkoxy group with 1 to 12 carbon atoms, a substituted or unsubstituted ether group with 1 to 12 carbon atoms, a cyano group, a fluorine group, a trifluoromethyl group, a trifluoromethoxy group, and a trimethylsilyl group,
wherein Z1 and Z2 are attached via a double bond between a carbon atom bound to A and B of Chemical Formula 3 and the indacene ring of Chemical Formula 2.

US Pat. No. 10,658,592

METHOD FOR FABRICATING FLEXIBLE DISPLAY DEVICE, FLEXIBLE DISPLAY DEVICE, AND DISPLAY APPARATUS

Wuhan China Star Optoelec...

1. A method for fabricating a flexible display device, comprising:disposing a separation layer on a surface of a baseboard;
disposing a flexible substrate on a surface of the separation layer away from the baseboard;
disposing a display assembly on a surface of the flexible substrate away from the separation layer;
separating the flexible substrate from the separation layer to obtain the flexible display device; and
wherein an adhesion between the flexible substrate and the surface of the baseboard is greater than an adhesion between the separation layer and the surface of the flexible substrate, an adhesion between the separation layer and the surface of the baseboard is greater than the adhesion between the separation layer and the surface of the flexible substrate;
wherein, disposing a display assembly on a surface of the flexible substrate away from the separation layer comprises: depositing an inorganic film layer, a flexible baseplate, a barrier layer, a buffer layer, a display panel, and an encapsulation layer sequentially on the surface of the flexible substrate away from the separation layer;
wherein, the step of separating the flexible substrate from the separation layer further comprises:
cutting boundaries of the separation layer and the flexible substrate by laser to form cutting lines; wherein, the cutting lines cut sequentially into the encapsulation layer, the display panel, the buffer layer, the barrier layer, the flexible baseplate, the inorganic film layer, the flexible substrate and the separation layer to reduce film shrinkage.

US Pat. No. 10,658,591

METHOD FOR PRODUCING DEPOSITION MASK

Sakai Display Products Co...

1. A method for producing a deposition mask including a quadrangular mask substrate secured so as to define an xy plane and a plurality of active region formation portions provided on the mask substrate and arrayed in p rows by q columns, the plurality of active region formation portions each including a plurality of openings arrayed in m rows by n columns, the method comprising:a step of preparing the mask substrate secured so as to define the xy plane; and
an opening formation step of forming the plurality of active region formation portions on the mask substrate, wherein
the mask substrate includes a resin layer and the opening formation step includes a step of directing laser light to the resin layer to form the plurality of openings, and wherein
the opening formation step includes:
step A of forming openings of “a” number of continual columns included in a first region including at least the (n/2)th column or the {(n+1)/2}th column;
step B of forming openings of “b” number of continual columns included in a second region adjacent to the first region in a ?x direction with a first gap region being sandwiched between the first region and the second region, the first gap region including “sa” number of continual columns; and
step C of forming openings of “c” number of continual columns included in a third region adjacent to the first region in an x direction with a second gap region being sandwiched between the first region and the third region, the second gap region including “sb” number of continual columns; and
the step B and the step C are performed after the step A.

US Pat. No. 10,658,590

TECHNIQUES FOR FORMING RRAM CELLS

International Business Ma...

1. A method of forming a resistive random access memory (RRAM) device, the method comprising the steps of:providing an underlayer disposed on a substrate;
patterning trenches in the underlayer;
forming bottom electrodes at two different levels of the underlayer whereby the bottom electrodes comprise first bottom electrodes at bottoms of the trenches and second bottom electrodes along a top surface of the underlayer in between the trenches;
depositing an insulating layer on the first and second bottom electrodes; and
forming top electrodes on the insulating layer over the first and second bottom electrodes, wherein the top electrodes comprise word lines, wherein the first and second bottom electrodes comprise bit lines that are orthogonal to the word lines, and wherein the first and second bottom electrodes, the insulating layer, and the top electrodes form the RRAM device having an array of cells, each cell comprising one of the first or second bottom electrodes separated from one of the top electrodes by the insulating layer.

US Pat. No. 10,658,589

ALIGNMENT THROUGH TOPOGRAPHY ON INTERMEDIATE COMPONENT FOR MEMORY DEVICE PATTERNING

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a semiconductor device, the method comprising:forming a conductive interconnect in a first area of the semiconductor device;
depositing a first electrode layer on the conductive interconnect;
depositing a film comprising a non-metallic material on the first electrode layer, and removing a portion of the film to form an alignment assisting marker in a second area of the semiconductor device, the alignment assisting marker being a raised portion of the film arranged directly on the first electrode layer;
depositing a dielectric layer and a second electrode layer on the alignment assisting marker in the second area and on the conductive interconnect in the first area;
depositing a hard mask layer on the dielectric layer and the second electrode layer to create a raised area of topography over the alignment assisting marker;
depositing and patterning a resist on the hard mask layer, using the raised area of topography created by the hard mask layer over the alignment assisting marker to align the resist over the conductive interconnect in the first area of the semiconductor device; and
etching to form a memory stack over the conductive interconnect by transferring the pattern of the resist into the first electrode layer, the dielectric layer, and the second electrode layer in the first area of the semiconductor device.

US Pat. No. 10,658,588

MEMORY CELL SWITCH DEVICE

Sony Corporation, Tokyo ...

1. A method for producing a first electrode of a memory cell, comprising:depositing a layer of TiN on a substrate;
depositing a layer of AlN on the substrate;
repeating the steps of depositing a layer of TiN and of depositing a layer of AlN multiple times; and
after repeating the steps of depositing a layer of TiN and of depositing a layer of AlN multiple times, performing NH3 annealing of the deposited layers,
wherein the first electrode includes titanium aluminum nitride (TiAlN).

US Pat. No. 10,658,587

CEM SWITCHING DEVICE

Arm Limited, Cambridge (...

1. A method for the manufacture of a CEM switching device, which method comprises forming a conductive substrate and forming a layer of correlated electron material (CEM) on or over the conductive substrate, wherein the forming of the CEM layer comprises forming a layer of a correlated electron material comprising a doped metal compound of a d- or f-block element comprising ions of the same d- or f-block element in different oxidation states and less than 5 atom % of free d- or f-block element, the free d- or f-block element being unbound and in a zero oxidation state.

US Pat. No. 10,658,586

RRAM DEVICES AND THEIR METHODS OF FABRICATION

Intel Corporation, Santa...

1. An apparatus, comprising:a conductive interconnect disposed in a dielectric layer above a substrate;
a resistive random access memory (RRAM) device coupled to the conductive interconnect, the RRAM device comprising:
a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer;
a conductive layer disposed on the bottom electrode, the conductive layer separate and distinct from the bottom electrode layer, and a material different from the bottom electrode layer;
a switching layer including a metal oxide and disposed on the conductive layer;
an oxygen exchange layer disposed on the switching layer; and
a top electrode disposed on the oxygen exchange layer.

US Pat. No. 10,658,585

DEDICATED CONTACTS FOR CONTROLLED ELECTROFORMING OF MEMORY CELLS IN RESISTIVE RANDOM-ACCESS MEMORY ARRAY

International Business Ma...

1. A memory device, comprising:a lower conductive line disposed in an interlayer dielectric layer;
a lower electrode disposed on the lower conductive line;
an isolation layer to isolate the lower electrode, wherein an upper surface of the isolation layer is coplanar with an upper surface of the lower electrode;
a stack structure disposed on the lower electrode, wherein the stack structure comprises a metal-oxide layer disposed on the lower electrode, and an upper electrode disposed on the metal-oxide layer;
insulating spacers disposed on sidewalls of the stack structure;
wherein the lower electrode, the metal-oxide layer, and the upper electrode comprise a resistive memory cell, and wherein the lower electrode has a footprint which is greater than a footprint of the upper electrode;
an upper conductive line disposed in contact with the upper electrode, wherein the upper conductive line is arranged orthogonal to the lower conductive line; and
a dedicated electroforming contact in contact with an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.

US Pat. No. 10,658,584

ELECTROCHEMICALLY ACTUATABLE ELECTRONIC COMPONENT AND PROCESS FOR PRODUCING THE ACTUATABLE ELECTRONIC COMPONENT

1. An electrochemically actuatable electronic component comprising:a substrate;
at least one first and one second actuating electrodes;
at least one first and one second measuring electrodes that are electrically independent from the first and second actuating electrodes;
at least one storing electrode configured to free ions under the action of the actuating electrodes;
at least one ionic conductor that is able to conduct said ions and that is located in a region placed between said measuring electrodes;
said measuring electrodes being configured to measure at least one characteristic of said region placed between the first and second measuring electrodes;
a device suitable for:
applying a voltage or a current between the first and second actuating electrodes in order to allow either the migration of ions from the storing electrode to the first actuating electrode forming thereon an electrochemical deposition through the ionic conductor or the at least partial dissolution of the electrochemical deposition and
for measuring, between the first and second measuring electrodes, a modification of at least one characteristic of the region placed between the first and second measuring electrodes, induced by the formation of the electrochemical deposition or by the at least partial dissolution thereof, so as to determine at least one characteristic of said electronic component.

US Pat. No. 10,658,583

FORMING RRAM CELL STRUCTURE WITH FILAMENT CONFINEMENT

INTERNATIONAL BUSINESS MA...

1. A method for forming a memory device with confined filament, comprising:forming at least one set of self-aligned corner tips of at least one set of bottom electrodes;
depositing at least one set of top electrodes intersecting the bottom electrodes, wherein a dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode; and
depositing at least one set of contacts to contact the at least one set of electrodes.

US Pat. No. 10,658,582

VERTICAL RESISTIVE PROCESSING UNIT WITH AIR GAP

INTERNATIONAL BUSINESS MA...

1. A vertical resistive unit, comprising:a first resistive random access memory (ReRAM) cell comprising first vertically aligned horizontal electrode layers and first vertical electrodes operably extending through respective entire vertical thicknesses of each of the first vertically aligned horizontal electrode layers to make physical contact with each of the first vertically aligned horizontal electrode layers; and
a second ReRAM cell comprising second vertically aligned horizontal electrode layers and second vertical electrodes operably extending through respective entire vertical thicknesses of each of the second vertically aligned horizontal electrode layers to make physical contact with each of the second vertically aligned horizontal electrode layers,
the first and second ReRAM cells being disposed to define an air gap between the first and second ReRAM cells.

US Pat. No. 10,658,581

SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE RESISTANCE VARIABLE LAYERS

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a semiconductor substrate;
a lower electrode over the semiconductor substrate;
a first oxide layer over the lower electrode, wherein the first oxide layer contains a first element and a second element other than the first element, the first element is selected from one of a first group of elements comprising aluminum, silicon, tantalum, yttrium, and vanadium, and the second element is selected from one of a second group of elements comprising zirconium, hafnium, titanium, lanthanum, and tantalum;
a second oxide layer over the first oxide layer, wherein the second oxide layer contains a third element and a fourth element other than the third element, the third element is selected from one of the first group of elements, and the fourth element is selected from one of the second group of elements;
a third oxide layer over the second oxide layer, wherein the third oxide layer contains a fifth element and a sixth element other than the fifth element, the fifth element is selected from one of the first group of elements, the sixth element is selected from one of the second group of elements, an atomic concentration of the third element of the second oxide layer is greater than an atomic concentration of the first element of the first oxide layer, and the atomic concentration of the third element of the second oxide layer is greater than an atomic concentration of the fifth element of the third oxide layer; and
an upper electrode over the third oxide layer.

US Pat. No. 10,658,580

SEMICONDUCTOR STRUCTURES INCLUDING MULTI-PORTION LINERS

Micron Technology, Inc., ...

1. A semiconductor structure, comprising:stack structures comprising electrode materials and chalcogenide materials on a substrate; and
a liner on at least a portion of the stack structures, the liner comprising a protective portion and a conformal portion directly contacting the protective portion and comprising a different material than the protective portion, the protective portion comprising aluminum oxide, silicon carbonitride, or silicon carboxynitride, the conformal portion comprising silicon carbonitride or silicon carboxynitride, the liner exhibiting an interfacial fracture energy of greater than or equal to about 3 J/m2 between the protective portion of the liner and the stack structures, and the liners of adjacent stack structures separated by a dielectric material.

US Pat. No. 10,658,579

STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A storage device, comprising:a first conductive layer including a first element;
a second conductive layer including a second element; and
a first intermediate layer between the first conductive layer and the second conductive layer in a first direction, the first intermediate layer including a first compound region and a second compound region between the first compound region and the second conductive layer in the first direction, the second compound region comprising an oxide of the second element, wherein
the first compound region includes a first partial region and a second partial region adjacent to the first partial region in a second direction intersecting the first direction, and the second compound region includes a third partial region and a fourth partial region adjacent to the third partial region in the second direction;
an electrical resistance between the first conductive layer and the second conductive layer is higher in a first state of the first intermediate layer than an electrical resistance between the first conductive layer and the second conductive layer in a second state of the first intermediate layer, the first and second states being caused by opposite polarity potentials being applied across the first intermediate layer;
in the first state, a concentration of the first element in the first partial region is higher than a concentration of the first element in the second partial region; and
the thickness, in the first direction, of the third partial region in the first state is greater than the thickness, in the first direction, of the fourth partial region in the first state.

US Pat. No. 10,658,578

MEMORY CELL COMPRISING A PHASE-CHANGE MATERIAL

STMicroelectronics (Croll...

1. A memory cell, comprising:a via connected to a transistor;
a phase-change material;
a heating element extending between the via and the phase-change material, said heating element configured to heat the phase-change material; and
positioned between the via and the heating element, at least one layer made of a material which is one of electrically insulating or having an electric resistivity greater than 2.5×10?5 ?·m;
wherein interfaces between two surfaces of said at least one layer and materials of the via and the heating element in contact with the two surfaces of said at least one layer form a thermal barrier;
wherein said at least one layer has a thickness such that said at least one layer is crossable by an electric current due to a tunnel-type effect.

US Pat. No. 10,658,576

MAGNETORESISTIVE STACK/STRUCTURE AND METHOD OF MANUFACTURING SAME

Everspin Technologies, In...

1. A method of manufacturing a magnetoresistive structure including an intermediate layer disposed between a first magnetic region and a second magnetic region, comprising:(a) etching through the second magnetic region to form exposed surfaces, wherein (i) the exposed surfaces include at least a portion of the intermediate layer, and (ii) after the etching, at least a portion of the exposed surfaces includes re-deposited material;
(b) forming a first encapsulation layer on the exposed surfaces after step (a);
(c) removing at least a portion of the re-deposited material after step (b);
(d) etching through the intermediate layer after step (c); and
(e) forming a second encapsulation layer after step (d).

US Pat. No. 10,658,575

METHOD FOR MAGNETIC DEVICE ALIGNMENT ON AN INTEGRATED CIRCUIT

Everspin Technologies, In...

1. A method of manufacturing a magnetoresistive device, comprising:depositing a plurality of layers corresponding to the magnetoresistive device, wherein depositing the plurality of layers corresponding to the magnetoresistive device obscures alignment marks underlying the plurality of layers;
forming a first layer of photoresist over the plurality of layers corresponding to the magnetoresistive device;
patterning the first layer of photoresist to produce a first patterned layer of photoresist;
etching at least a portion of the plurality of layers corresponding to the magnetoresistive device using the first patterned layer of photoresist as a template, wherein etching the at least a portion of the plurality of layers corresponding to the magnetoresistive device exposes the alignment marks underlying the plurality of layers;
after etching the at least a first portion of the plurality of layers corresponding to the magnetoresistive device, forming a layer of encapsulating material that obscures the alignment marks;
after forming the layer of encapsulating material, selectively removing portions of the encapsulating material to expose the alignment marks; and
after selectively removing portions of the encapsulating material, etching a second portion of the plurality of layers corresponding to the magnetoresistive device.

US Pat. No. 10,658,574

SYNTHETIC ANTIFERROMAGNETIC LAYER, MAGNETIC TUNNEL JUNCTION AND SPINTRONIC DEVICE USING SAID SYNTHETIC ANTIFERROMAGNETIC LAYER

CENTRE NATIONAL DE LA REC...

1. A synthetic antiferromagnetic layer comprising:a first ferromagnetic layer containing an amorphizing element, said first ferromagnetic layer having a first structural symmetry;
a second ferromagnetic layer having a second structural symmetry;wherein the first and the second ferromagnetic layers are antiferromagnetically coupled by a trifunctional non-magnetic multi-layered structure, the antiferromagnetic coupling being an Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling, said non-magnetic multi-layered structure comprising at least two non-magnetic layers, said non-magnetic multilayered structure being at least partially nano-crystalline or amorphous in order to ensure a structural transition between the first ferromagnetic layer having the first structural symmetry and the second ferromagnetic layer having the second structural symmetry, said non-magnetic multilayered structure being adapted to absorb at least part of the amorphizing element out of the first ferromagnetic layer in contact with the non-magnetic multi-layered structure.

US Pat. No. 10,658,573

MAGNETIC MEMORY

TDK CORPORATION, Tokyo (...

1. A magnetic memory comprising:a magnetoresistance effect element that includes a first ferromagnetic metal layer in which a magnetization direction is fixed, a second ferromagnetic metal layer for a magnetization direction to be changed, and a nonmagnetic layer that is provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer;
a plurality of drive elements, each of which is connected to the second ferromagnetic metal layer of the magnetoresistance effect element and includes spin-orbit torque wirings extending in a direction intersecting a lamination direction of the magnetoresistance effect element;
a plurality of first control elements that are connected to each of the first ferromagnetic metal layers of the plurality of drive elements;
at least one second control element that is connected to a first connection point of spin-orbit torque wirings of at least two drive elements among the plurality of drive elements; and
a plurality of first cell selection elements, each of which is connected to each of second connection points of the spin-orbit torque wirings of the plurality of drive elements, respectively,
wherein the spin-orbit torque wirings include a nonmagnetic metal having a d electron or a f electron in the outermost shell and having an atomic number of 39 or higher.

US Pat. No. 10,658,572

MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY

TOHOKU UNIVERSITY, Senda...

1. A magnetoresistance effect element, comprising:a first magnetic layer having a magnetization direction perpendicular to a surface of the first magnetic layer, the first magnetic layer containing at least one ferromagnetic metal element included in 3d transition metal elements;
a first non-magnetic layer disposed directly on the first magnetic layer; and
a second magnetic layer disposed directly on the first magnetic layer at a side opposite to a side where the first non-magnetic layer is disposed, the second magnetic layer having a magnetization direction parallel to the magnetization direction of the first magnetic layer, the second magnetic layer containing at least one ferromagnetic metal element included in 3d transition metal elements;
a third magnetic layer disposed directly on the second magnetic layer at a side opposite to a side where the first magnetic layer is disposed, the third magnetic layer having a magnetization direction parallel to the magnetization direction of the first magnetic layer, the third magnetic layer containing at least one ferromagnetic metal element included in 3d transition metal elements; and
a second non-magnetic layer disposed directly on the third magnetic layer at a side opposite to a side where the second magnetic layer is disposed, wherein
a second atomic fraction of all magnetic elements to all magnetic and non-magnetic elements included in the second magnetic layer is smaller than a first atomic fraction of all magnetic elements to magnetic and non-magnetic elements included in the first magnetic layer, and
the second magnetic layer has a thickness equal to or greater than 1.5 times of a thickness of each of the first and third magnetic layers.

US Pat. No. 10,658,571

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, the method comprising:providing a substrate;
depositing a first electrode layer over the substrate;
depositing a magnetic tunneling junction (MTJ) layer on the first electrode layer;
depositing a second electrode layer on the MTJ layer;
patterning the first electrode layer, the MTJ layer, and the second electrode layer to form a first electrode, an MTJ and a second electrode;
forming a first dielectric layer over the first electrode, the MTJ, and the second electrode;
removing a portion of the first dielectric layer; and
forming a second dielectric layer over the first electrode, the MTJ, the second electrode, and an unremoved portion of the first dielectric layer,
wherein prior to the removing the portion of the first dielectric layer, the first dielectric layer at a sidewall of the MTJ is thinner than the first dielectric layer at a top surface of the second electrode.

US Pat. No. 10,658,570

METHOD FOR PRODUCING COMPOSITE WAFER HAVING OXIDE SINGLE-CRYSTAL FILM

SHIN-ETSU CHEMICAL CO., L...

1. A method of producing a composite wafer having an oxide single-crystal film on a support wafer, comprising steps of:implanting hydrogen atom ions or hydrogen molecule ions into an oxide single-crystal wafer through a surface thereof, which wafer is a lithium tantalate or lithium niobate wafer, to form an ion-implanted layer inside the oxide single-crystal wafer;
subjecting at least one of the surface of the oxide single-crystal wafer and a surface of a support wafer to be laminated with the oxide single-crystal wafer to surface activation treatment;
after the surface activation treatment, bonding the surface of the oxide single-crystal wafer to the surface of the support wafer to obtain a laminate;
heat-treating the laminate at a temperature of 90° C. or higher at which cracking is not caused; and
applying ultrasonic vibration to the heat-treated laminate to split the laminate along the ion-implanted layer to obtain an oxide single-crystal film transferred onto the support wafer;wherein an implantation dose of the hydrogen atom ions is from 5.0×1016 atom/cm2 to 2.75×1017 atom/cm2 and an implantation dose of the hydrogen molecule ions is from 2.5×1016 atoms/cm2 to 1.37×1017 atoms/cm2.

US Pat. No. 10,658,569

METHOD FOR MANUFACTURING NIOBATE-SYSTEM FERROELECTRIC THIN-FILM DEVICE

SUMITOMO CHEMICAL COMPANY...

1. A method for manufacturing a niobate-system ferroelectric thin film device comprising:a lower electrode film formation step of forming a lower electrode film on a substrate;
a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film;
an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film;
an etchant preparation step of preparing an alkaline etchant comprising a predetermined chelating agent, an aqueous alkaline solution and an aqueous hydrogen peroxide solution; and
a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using the alkaline etchant,
wherein the predetermined chelating agent comprises at least one selected from ethylenediamine tetra(methylene phosphonic acid), nitrilotris(methylene phosphonic acid), cyclohexane diamine tetraacetic acid, 1-hydroxyethane-1,1-diphosphonic acid(etidronic acid), glycine-N,N-bis(methylene phosphonic acid), diethylenetriamine penta(methylene phosphonic acid), and citric acid; and the aqueous alkaline solution comprises an aqueous ammonia solution, and
wherein the etchant preparation step is a two-liquid mixing process in that a separately prepared concentrated solution containing the predetermined chelating agent and the aqueous alkaline solution is mixed and diluted with the aqueous hydrogen peroxide solution.

US Pat. No. 10,658,568

METHOD FOR PRODUCING COMPOSITE WAFER HAVING OXIDE SINGLE-CRYSTAL FILM

SHIN-ETSU CHEMICAL CO., L...

1. A method of producing a composite wafer having an oxide single-crystal film on a support wafer, the method comprising steps of:implanting hydrogen atom ions or hydrogen molecule ions into an oxide single-crystal wafer through a surface thereof, which wafer is a lithium tantalate or lithium niobate wafer, to form an ion-implanted layer inside the oxide single-crystal wafer;
subjecting at least one of the surface of the oxide single-crystal wafer and a surface of a support wafer to be laminated with the oxide single-crystal wafer to surface activation treatment;
after the surface activation treatment, bonding the surface of the oxide single-crystal wafer to the surface of the support wafer to obtain a laminate;
heat-treating the laminate at a temperature of 90° C. or higher at which cracking; is not caused; and
applying a mechanical impact to the ion-implanted layer of the heat-treated laminate to split the laminate along the ion-implanted layer to obtain an oxide single-crystal film transferred onto the support wafer,
wherein an implantation dose of the hydrogen atom ions is from 5.0×1016 atom/cm2 to 2.75×1017 atom/cm2 and an implantation dose of the hydrogen molecule ions is from 2.5×1016 atoms/cm2 to 1.37×1017 atoms/cm2.

US Pat. No. 10,658,567

COMPOSITE MATERIAL USED AS A STRAIN GAUGE

NANO COMPOSITE PRODUCTS, ...

1. A porous nanoparticle-polymer composite structure comprising:a cured polymer;
conductive nanoparticles; and
conductive fibers,
wherein the nanoparticle-polymer composite structure is cured into a shape from a mixture including a curable liquid polymer, the conductive nanoparticles, and the conductive fibers.

US Pat. No. 10,658,566

PIEZOELECTRIC DRIVEN SWITCHES INTEGRATED IN ORGANIC, FLEXIBLE DISPLAYS

Intel Corporation, Santa...

1. A piezoelectrically actuated switch for modulating a background color in a display, comprising:a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display, wherein the blinds include a first surface and a second surface;
an anchor spaced away from an edge of the photonic crystal; and
a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal.

US Pat. No. 10,658,565

ACTUATOR ASSEMBLIES, MECHANICAL ASSEMBLIES INCLUDING THE ACTUATOR ASSEMBLIES, AND METHODS OF FABRICATING THE SAME

The Boeing Company, Chic...

1. An actuator assembly, comprising:a piezoelectric element having a first side and an opposed second side;
a first electrode in electrical communication with the first side, wherein the first electrode includes a flexible, electrically conductive membrane; and
a second electrode in electrical communication with the second side.

US Pat. No. 10,658,564

SURFACE ACOUSTIC WAVE DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A surface acoustic wave device comprising:a high acoustic velocity layer;
a piezoelectric layer coupled to the high acoustic velocity layer;
at least one transducer between the piezoelectric layer and the high acoustic velocity layer, the at least one transducer being configured to propagate a surface acoustic wave having an operating wavelength (?) along a surface of the piezoelectric layer, each of the at least one transducer having a plurality of interdigital transducer (IDT) electrodes, the IDT electrodes each having an IDT thickness; and
a thin metallic layer coupled to the piezoelectric layer and electrically isolated from the at least one transducer;
wherein the piezoelectric layer is a scandium-doped aluminum-nitride (ScAlN) layer; and
wherein the thickness of the piezoelectric layer is approximately 0.15?-0.25? and the IDT thickness is less than 0.02?.

US Pat. No. 10,658,563

ULTRASOUND TRANSDUCER AND MANUFACTURING METHOD THEREOF

Siemens Medical Solutions...

1. An ultrasound transducer comprising:a backing block;
a piezoelectric layer placed on the backing block;
a matching layer placed on the piezoelectric layer; and
a ground layer placed between the piezoelectric layer and the matching layer,
wherein the backing layer comprises a connector that connects to a transmitting unit and a receiving unit of an ultrasound system, and a wiring area that connects the piezoelectric layer and the connector, the wiring area comprising conductors filling etched portions of the backing material of the backing layer.

US Pat. No. 10,658,562

THERMOELECTRIC CONVERSION MATERIAL, METHOD FOR PRODUCING SAME, AND THERMOELECTRIC CONVERSION MODULE

HITACHI METALS, LTD., To...

1. A thermoelectric conversion material comprising a full-Heusler alloy containing Fe, Ti, and Si as main raw materials, having:secondary crystal grains having an Fe2TiSi type composition; and
a coating layer covering the circumference of the secondary crystal grains and containing an element other than Fe, Ti, and Si as a main component, wherein
the coating layer has a composition containing an element being dissolvable in a crystal structure of the Fe2TiSi type composition and having an electric resistivity lower than the secondary crystal grains.

US Pat. No. 10,658,560

THERMOELECTRIC MATERIALS BASED ON TETRAHEDRITE STRUCTURE FOR THERMOELECTRIC DEVICES

Board of Trustees of Mich...

1. A thermoelectric composition comprising Cu12-xMxSb4-yAsyS13, where M is Zn and 0

US Pat. No. 10,658,559

LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting element comprising:a semiconductor layered body including
a first semiconductor layer,
a light emitting layer, and
a second semiconductor layer, with the light emitting layer being positioned between the first semiconductor layer and the second semiconductor layer,
the first semiconductor layer being exposed from the light emitting layer and the second semiconductor layer at a plurality of exposed parts when viewed from a second semiconductor layer side of the semiconductor layered body;
an insulating film covering the semiconductor layered body, the insulating film defining a plurality of openings respectively arranged above the plurality of exposed parts of the first semiconductor layer;
a first electrode connected to the first semiconductor layer at the exposed parts through the openings in the insulating film, and partially arranged on the second semiconductor layer via the insulating film;
a second electrode electrically connected to the second semiconductor layer;
a plurality of first external connecting parts connected to the first electrode, the first external connecting parts being spaced apart from the exposed parts in a plan view; and
at least one second external connecting part connected to the second electrode, wherein
a group comprising at least one of the first external connecting parts and other group comprising at least one of the first external connecting parts respectively surround adjacent ones of the exposed parts while being spaced apart from each other in the plan view.

US Pat. No. 10,658,558

LED PACKAGE INCLUDING CONVERTER CONFINEMENT

Lumileds LLC, San Jose, ...

1. A light-emitting device, comprising:a light-emitting diode (LED) on a first surface of a crystalline growth substrate;
a fence structure having a bottom mounted to a limited portion of a second surface of the crystalline growth substrate that is opposite the first surface of the crystalline growth substrate, the fence structure including a plurality of walls, between which a hole passes from a top of the fence structure to the bottom of the fence structure to define a cell;
a light-converting structure on the second surface of the crystalline growth substrate in the cell; and
a reflective layer directly contacting an outer surface of the plurality of walls of the fence structure; and
a reflective pattern formed on the second surface of the crystalline growth substrate, the reflective pattern including a plurality of lines, each line being at least partially coincident with a different wall of the fence structure and formed between the wall of the fence structure and the substrate, the each line comprising a distributed Bragg reflector (DBR) comprising an alternating stack of materials having differing refractive indices.

US Pat. No. 10,658,557

TRANSPARENT LIGHT EMITTING DEVICE WITH LIGHT EMITTING DIODES

THE REGENTS OF THE UNIVER...

1. A light emitting device, comprising:a sapphire plate, a cathode on a first end of the sapphire plate and an anode on a second end of the sapphire plate, wherein the cathode and anode provide structural support to the sapphire plate and are adapted to provide an electrical connection between the light emitting device and a structure outside the light emitting device;
a plurality of III-nitride light emitting diodes (LEDs), each comprising a sapphire growth substrate and each in mechanical communication with the sapphire plate, and the LEDs and sapphire plate configured to extract light emitted by the LEDs through the sapphire plate; and
a molding comprising a phosphor and surrounding the LEDs, the molding configured to extract light from both a front side of the light emitting device and a back side of the light emitting device.

US Pat. No. 10,658,556

LED PACKAGE STRUCTURE AND MULTILAYER CIRCUIT BOARD

LITE-ON OPTO TECHNOLOGY (...

1. A multilayer circuit board, comprising:a conductive layer having a first surface and a second surface opposite to the first surface, a mounting region of the conductive layer being arranged on the first surface, wherein the conductive layer has a first conductive portion and a plurality of first extending arms extending from the first conductive portion;
a first resin layer having two surfaces opposite to each other, wherein one of the two surfaces of the first resin layer is disposed on the first surface of the conductive layer, and has a first opening exposing the mounting region of the conductive layer; and
an insulating portion arranged around a side wall of the first conductive portion and a side wall of each of the first extending arms, wherein an end surface of each of the first extending arms is flush with a side surface of the insulating portion adjacent thereto, a top surface of the first conductive portion is coplanar with a top surface of the insulating portion, and a bottom surface of the first conductive portion is coplanar with a bottom surface of the insulating portion.

US Pat. No. 10,658,555

OPTICAL SEMICONDUCTOR APPARATUS

HOYA CANDEO OPTRONICS COR...

1. An optical semiconductor apparatus, comprising, in the order recited:an optical semiconductor device that has a surface that emits light;
a buffer layer that is light-permeable, that comprises a first silicone resin that is cured and has a high-hardness, that has a thickness ranging from 1 ?m to 300 ?m, and that covers at least part of the surface of the optical semiconductor device that emits light;
a sealing layer that is flexible, that comprises a second silicone resin which is cured and which has a hardness that is lower than that of the buffer layer, and that covers the optical semiconductor device and the buffer layer.

US Pat. No. 10,658,554

LED LAMP WITH SILOXANE PARTICLE MATERIAL

Inkron Oy, Espoo (FI)

1. A method making an LED lamp, comprising:forming a light emitting diode by providing a semiconductor material on a first substrate and doping the semiconductor material;
providing a supporting substrate;
providing an adhesive composition comprising a siloxane polymer having silicon and oxygen in the polymer backbone, as well as aryl groups and functional cross-linking groups bound thereto, the adhesive composition further comprising particles having an average particle size of less than 10 microns, wherein the particles comprise a late transition metal selected from groups 8 to 11 of the periodic table, and a catalyst;
depositing the adhesive composition so as to adhere the first substrate to the supporting substrate;
applying temperature and/or light so as to activate the cross-linking groups of the siloxane polymer in order to further polymerize the siloxane polymer and harden the polymer while at the same time adhering the first substrate and supporting substrate together;
wherein the polymerized and hardened siloxane polymer has a mass of at least 96% after polymerization as compared to before polymerization; and
wherein the siloxane polymer does not absorb more than 25% of visible light incident thereon;
wherein the particles comprise a first particle group and a second particle group, the first particle group having an average particle size greater than that of the second particle group,
wherein the applying temperature and/or light comprises applying a first lower temperature so as to melt the particles of the second particle group, followed by applying a second higher temperature to cause activation of the cross-linking functional groups in the siloxane polymer, and wherein both the first and second temperatures are less than 175° C.

US Pat. No. 10,658,553

LIGHT SOURCE MODULE

PRIMAX ELECTRONICS LTD., ...

1. A light source module, comprising:a LED die emitting a light beam;
a supporting base electrically connected with the LED die, and supporting the LED die, wherein after a portion of the light beam is projected to and reflected by the supporting base, the portion of the light beam is projected to surroundings through the LED die; and
an encapsulation layer covering the LED die and a portion of the supporting base to protect the LED die, wherein a light pattern of the light beam is adjustable according to a shape of the encapsulation layer,
wherein the LED die comprises:
a substrate;
a first covering layer disposed on a bottom surface of the substrate and electrically connected with the supporting base, wherein a first current flows through the first covering layer;
a second covering layer located under the first covering layer and electrically connected with the supporting base, wherein a second current flows through the second covering layer; and
a luminous layer arranged between the first covering layer and the second covering layer, wherein the luminous layer emits the light beam in response to the first current and the second current, and the light beam is projected to the surroundings through the substrate,
wherein the supporting base comprises:
a plate body;
a first metal connection layer disposed on a top surface of the plate body;
a second metal connection layer disposed on the first metal connection layer, wherein the first metal connection layer and the second metal connection layer are combined together to reflect the light beam; and
a passivation layer disposed on the second metal connection layer to protect the plate body, the first metal connection layer and the second metal connection layer, wherein after the portion of the light beam projected to the supporting base is reflected by the passivation layer, the portion of the light beam is projected to the surroundings through the substrate.

US Pat. No. 10,658,552

BLUE EMITTING PHOSPHOR CONVERTED LED WITH BLUE PIGMENT

Koninklijke Philips N.V.,...

1. A LED package configured to generate blue LED package light, wherein the LED package comprisesa solid state light source configured to generate blue light source light,
a luminescent material configured to convert part of the light source light into luminescent material light comprising green light, and
a blue pigment configured to absorb part of the luminescent material light, wherein the luminescent material comprises one or more of:
(Lu(1-x),Cex)3(Al(1-y),Gay)5O12, with 0.005?x?0.08 and 0?y?0.7;
Si(6-x)AlxOyN(6-y):Eu wherein 0 an alkaline earth metal orthosilicate doped with europium;
BaMgAl10O17:Eu,Mn;
BaMg2Al16O27:Eu,Mn; and
Sr4Al14O25:Eu.

US Pat. No. 10,658,551

WAVELENGTH-CONVERTING FILM AND SEMICONDUCTOR LIGHT EMITTING APPARATUS HAVING THE SAME

Samsung Electronics Co., ...

1. A wavelength-converting film, comprising:a sintered body including
a glass composition, and
a wavelength-converting material located within the glass composition,
the wavelength-converting material including
a quantum dot having a core-shell structure and
a protective layer coating a surface of the quantum dot,
wherein a shell of the quantum dot contains at least one of S and Se, and the protective layer does not contain S or Se, and
the glass composition includes a SnO2—P2O5—SiO2-based composition, and
wherein the protective layer is configured to prevent direct contact between a Sn component of the glass composition and a S or Se component of the shell.

US Pat. No. 10,658,550

ULTRAVIOLET LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF

1. A light-emitting diode (LED) package structure comprising:a support;
an LED chip; and
a package cover,
wherein:
a support circuit is formed over the support;
the LED chip is arranged over the support and electrically coupled to the support circuit;
a lower surface periphery of the package cover is provided with a groove structure entirely filled with organic binder;
the package cover is arranged over the LED chip and connected to the support via the organic binder; and
wherein the groove structure does not extend entirely through the package cover.

US Pat. No. 10,658,549

UNIT SUBSTRATE FOR OPTICAL DEVICE AND OPTICAL DEVICE PACKAGE HAVING SAME

POINT ENGINEERING CO., LT...

1. A unit substrate for an optical device, the unit substrate comprising:first and second metal substrates bonded to each other with a vertical insulating layer interposed therebetween;
a cavity provided on first portions of upper surfaces of the bonded first and second metal substrates;
an optical device-mounting region provided on a bottom surface of the cavity;
an upper insulation portion provided on second portions of the upper surfaces of the bonded first and second metal substrates; and
a side insulation portion provided along side surfaces of the bonded first and second metal substrates,
wherein lower surfaces of the bonded first and second metal substrates are electrically connected to the optical device-mounting region, respectively, and
wherein the side surfaces and the second portions of the upper surfaces of the bonded first and second metal substrates are electrically isolated from the optical device-mounting region, and
wherein the side insulation portion surrounds substantially the entire side surfaces of the bonded first and second metal substrates.

US Pat. No. 10,658,548

METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIP

OSRAM OLED GMBH, Regensb...

1. A method for producing an optoelectronic semiconductor chip comprising the steps of:A) providing a semiconductor layer stack comprising a semiconductor layer of a first type, a semiconductor layer of a second type and an active layer arranged between the semiconductor layer of the first type and the semiconductor layer of the second type,
A0) applying an electrically conductive layer over the semiconductor layer of the first type or over the semiconductor layer of the second type,
A1) applying a patterned mask on the semiconductor layer of the first type or on the semiconductor layer of the second type,
B) forming a mesa structure in the semiconductor layer of the first type, the semiconductor layer of the second type and the active layer,
B3) at least partially removing the electrically conductive layer in a region which directly adjoins the mesa structure and partially extends under the mask, by means of a wet-chemical etching process, and
C) applying a passivation layer to the mesa structure by means of vapor deposition or sputtering, wherein the passivation layer comprises a dielectric layer stack.

US Pat. No. 10,658,547

LIGHT EMITTING DIODE HAVING PATTERNED MIRROR LAYER

Epistar Corporation, Hsi...

1. A light emitting diode (LED) structure, comprising:a stacked semiconductor layer comprising:
a first type doped layer;
a second type doped layer; and
an active layer disposed between the first type doped layer and the second type doped layer;
a recess penetrating the second type doped layer and the active layer, wherein a bottom of the recess exposes the first type doped layer;
a contact layer disposed on the second type doped layer;
a dielectric reflective layer covering the contact layer and the first type doped layer by extending into the recess, the dielectric reflective layer comprising a cave formed on the second type doped layer and on the contact layer;
a patterned mirror layer formed on the contact layer, one part of the patterned mirror layer connecting to the cave of the dielectric reflective layer and another one part of the patterned mirror layer being covered by the dielectric reflective layer, wherein in a cross-sectional view of the light emitting diode (LED) structure the one part of the patterned mirror layer comprises a width larger than that of the another one part of the patterned mirror layer;
a conductive layer contacting the first doped layer and electrically connected to the first doped layer through the recess; and
an electrode layer disposed on the dielectric reflective layer, wherein the electrode layer comprises a first electrode region and a second electrode region, wherein the first electrode region comprises a first top surface comprising a first concave portion corresponding to the recess, and wherein the second electrode region comprises a second top surface comprising a second concave portion corresponding to the cave.

US Pat. No. 10,658,546

HIGH EFFICIENCY LEDS AND METHODS OF MANUFACTURING

Cree, Inc., Durham, NC (...

1. A light emitting diode (LED) chip, comprising:an active LED structure comprising an active region between two oppositely doped layers, said active region emitting light in response to an electrical signal applied to at least one of said oppositely doped layers;
a first reflective layer on one of said oppositely doped layers;
a second reflective layer, said first reflective layer between said active region and said second reflective layer said second reflective layer reflecting light not reflected by said first reflective layer, wherein said second reflective layer extends beyond an outer edge of said active LED structure and into a street, said street outside of said active region, wherein said first and second reflective layers are spaced away from said active LED structure such that neither of said first and second reflective layers directly contacts said active LED structure; and
a contact in said street and on a portion of said second reflective layer that extends beyond said outer edge of said active LED structure and into said street, wherein said contact extends through said first reflective layer and contacts a top of said portion of said second reflective layer.

US Pat. No. 10,658,545

LIGHT EMITTING DEVICE IN WHICH LIGHT EMITTING ELEMENT AND LIGHT TRANSMISSIVE MEMBER ARE DIRECTLY BONDED

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a light transmissive member;
a light emitting element having a semiconductor stacked layer portion; and
electrodes respectively disposed on the semiconductor stacked layer portion, in this order;
wherein:
the light emitting element has, from the light transmissive member side, a first region and a second region,
the light transmissive member has, from the light emitting element side, a third region and a fourth region,
the first region has an irregular atomic arrangement compared with the second region,
the third region has an irregular atomic arrangement compared with the fourth region,
the first region and the third region are directly bonded, and
an area of the light transmissive member at a viewing side is larger than a bonding area of the light emitting element and the light transmissive member.

US Pat. No. 10,658,544

LIGHT-EMITTING DEVICES

EPISTAR CORPORATION, Hsi...

1. A light-emitting device, comprising:a semiconductor layer sequence comprising a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer;
a beveled trench formed in the semiconductor layer sequence, comprising a top end, a bottom end exposing the first semiconductor layer and an inner sidewall connecting the top end and the bottom end;
a protruding structure comprising metal formed at a position corresponding to that of the beveled trench;
a dielectric layer formed on the second semiconductor layer and on the inner sidewall of the beveled trench;
a reflecting layer comprising one portion contacting a main side of the second semiconductor layer, and another portion extended outside a sidewall of semiconductor layer sequence, wherein the another portion comprises a surface coplanar with the main side of the second semiconductor layer;
an electrode formed on the surface of the another portion of the reflecting layer, wherein the electrode is separated from the sidewall of semiconductor layer sequence by a distance; and
a metal layer formed along the inner sidewall of the beveled trench to extend outside the beveled trench.

US Pat. No. 10,658,543

SEMICONDUCTOR OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME

DOWA Electronics Material...

1. A semiconductor optical device comprising a semiconductor layer and a wiring electrode portion on a surface of the semiconductor layer that serves as one of a light emitting surface and a light receiving surface,wherein a line width of the wiring electrode portion is 2 ?m or more and 5 ?m or less,
the wiring electrode portion has a metal layer on the semiconductor layer and a conductive hard film on the metal layer,
the conductive hard film is harder than the metal layer, and
a thickness of the conductive hard film is 0.7 ?m or more and 1.5 ?m or less.

US Pat. No. 10,658,542

QUANTUM DOT LIGHT-EMITTING DEVICE

Samsung Display Co., Ltd....

1. A light-emitting device comprising:a first electrode;
a second electrode opposite to the first electrode;
an emission layer between the first electrode and the second electrode, the emission layer comprising quantum dots;
a hole transport region between the first electrode and the emission layer; and
an inorganic layer between the emission layer and the second electrode,
wherein the inorganic layer comprises a metal halide and the metal halide comprises an alkaline earth metal halide, a transition metal halide, a post-transition metal halide, or any combination thereof,
wherein the hole transport region include metal oxide nanoparticles, and
an energy band gap of the inorganic layer is about 3.1 eV to about 4.6 eV.

US Pat. No. 10,658,541

SELECTIVE GROWTH OF NITRIDE BUFFER LAYER

Xiamen Changelight Co., L...

1. A method of manufacturing semiconductor wafers, comprising:selectively growing a nitride buffer layer on a first surface of a patterned substrate by disposing a sacrificial layer on the first surface and a second surface of the patterned substrate, the patterned substrate including at least the first surface and the second surface having different normal directions, and the sacrificial layer including a first portion disposed on the first surface and a second portion disposed on the second surface;
exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface;
growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer;
removing a top portion of the original nitride buffer layer to expose a top portion of the second portion of the sacrificial layer; and
lifting off the second portion of the sacrificial layer disposed on the second surface and a portion of the original nitride buffer layer disposed on the second portion of the sacrificial layer; and
growing an epitaxial layer on the nitride buffer layer, wherein a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.

US Pat. No. 10,658,540

MICRO-LIGHT-EMITTING DIODE DEVICE

AU OPTRONICS CORPORATION,...

1. A micro-light-emitting diode device comprising:a first semiconductor layer having a first bottom surface;
an active layer disposed on the first semiconductor layer;
a second semiconductor layer disposed on the active layer and having a top surface opposite to the active layer, wherein the second semiconductor layer and the active layer have an interface, a distance between the top surface and the interface decreases from a central axis of the second semiconductor layer to an edge of the second semiconductor layer, and a light passes through the top surface of the micro-light-emitting diode device configured to redirect or focus the light that would otherwise be trapped or absorbed in the micro-light-emitting diode device, and vertical-projection zones of the first semiconductor layer, the active layer, and the second semiconductor layer on the first bottom surface are substantially the same, wherein the second semiconductor has a second bottom surface, a shape of the first bottom surface of the first semiconductor layer is a circle or a polygon, and the shape and a size of the first bottom surface are substantially the same as a shape and a size of the second bottom surface, wherein the size of the first bottom surface is between 25 square micrometers and 10000 square micrometers, and a side length of the micro-light-emitting diode device is less than 100 micrometers, wherein the top surface has an apex, a vertical distance between the second bottom surface and the apex is a maximum thickness of the second semiconductor layer, and a vertical distance between the second bottom surface and a point of the top surface except the apex is less than the maximum thickness; and
an electrode layer disposed on and in contact with the top surface to form a convex interface therebetween, wherein the convex interface protrudes from the second semiconductor layer toward the electrode layer, the electrode layer has a smooth conductive surface opposite the convex interface, and the electrode layer is formed on the entire top surface of the second semiconductor layer.

US Pat. No. 10,658,539

LIGHT EMITTING DIODE DEVICE

Hewlett Packard Enterpris...

1. A method for forming a light emitting diode device, comprising:receiving a semiconductor, a parabolic reflective optical element, and a transmissive collimating optical element; and
disposing the semiconductor having a pn junction between the parabolic reflective optical element, and the transmissive collimating optical element, wherein the semiconductor is configured to emit light in response to electrical stimulation, wherein the parabolic reflective optical element and the transmissive collimating optical element each comprise a planar non-periodic high-index-contrast grating, and
wherein the semiconductor is disposed such that some of the light is to be directed towards the transmissive collimating optical element and some of the light is to be directed towards the reflective optical element, which is then to be directed back along a path from which the light came and towards the transmissive collimating optical element.

US Pat. No. 10,658,538

OPTICAL DETECTION DEVICE

Electronics and Telecommu...

1. An optical detection device comprising:a first ohmic contact layer of a first conductivity type;
a second ohmic contact layer of a second conductivity type; and
first and second mesa structures stacked between the first and second ohmic contact layers,
wherein the first mesa structure comprises:
an electric field buffer layer;
a diffusion layer formed in the electric field buffer layer, the diffusion layer including a first diffusion layer and a second diffusion layer surrounding a portion of the first diffusion layer, the first diffusion layer having a greater depth than the second diffusion layer; and
an amplification layer disposed between the first diffusion layer and second mesa structure, the amplification layer narrower than the first diffusion layer to have a width smaller than a width of the first diffusion layer,
wherein the second mesa structure comprises:
a light absorbing layer; and
a grading layer on the light absorbing layer.

US Pat. No. 10,658,537

METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE

KANEKA CORPORATION, Osak...

1. A method for manufacturing a crystalline silicon-based solar cell comprising a conductive single-crystalline silicon substrate, an intrinsic silicon-based thin-film, and a conductive silicon-based thin-film, the method comprising:disposing a plurality of conductive single-crystalline silicon substrates, each provided with an intrinsic silicon-based thin-film on a surface thereof, in a chemical vapor deposition (CVD) chamber; and
performing a plasma treatment by introducing a hydrogen gas and a silicon-containing gas into the CVD chamber, wherein a surface of the intrinsic silicon-based thin-film is exposed to a hydrogen plasma,
wherein an amount of the hydrogen gas introduced into the CVD chamber during the plasma treatment is 150 to 2500 times an amount of the silicon-containing gas introduced into the CVD chamber, and
a power density during the plasma treatment is 55 to 1000 mW/cm2.

US Pat. No. 10,658,536

SOLAR CELL MODULE

ZEON CORPORATION, Chiyod...

1. A solar cell module comprising:one or more photoelectric conversion cells in which a first electrode at a side of a first base plate and a second electrode at a side of a second base plate are in opposition via a functional layer;
at least one barrier packaging material that is sealed by a barrier packaging material seal and encloses the one or more photoelectric conversion cells;
a first lead-out electrode connected to the first electrode via a first electrical connector; and
a second lead-out electrode connected to the second electrode via a second electrical connector, wherein
the first electrical connector and the second electrical connector are separated from the functional layer in a base plate surface direction that includes a surface direction of the first base plate and a surface direction of the second base plate,
the barrier packaging material includes, in an outer surface aligned with the base plate surface direction, a first lead-out electrode exposing part and a second lead-out electrode exposing part that respectively expose the first lead-out electrode and the second lead-out electrode from the solar cell module, where the first lead-out electrode exposing part and the second lead-out electrode exposing part are each sealed by at least one exposing part seal, and
the first lead-out electrode exposing part and the first electrical connector are separated in the base plate surface direction, and the second lead-out electrode exposing part and the second electrical connector are separated in the base plate surface direction.

US Pat. No. 10,658,535

SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME

KABUSHIKI KAISHA TOYOTA J...

1. A solar cell module comprising:a first cover in a form of a plate having a transparent portion and a colored portion that is opaque and shields visible light;
a second cover disposed to face the first cover;
at least one solar cell disposed between the first cover and the second cover;
a sealing material which fills a space between the first cover and the second cover and joins them together to thus seal the at least one solar cell, wherein the sealing material contacts the first cover and the second cover;
a conductor electrically connected to the at least one solar cell;
a positioning portion integrally extending from the colored portion of the first cover into a through hole of the conductor in order to fix the conductor to the colored portion of the first cover,
wherein a tip, located between the second cover and the conductor, of the positioning portion has a diameter larger than a diameter of the through hole,
wherein the conductor is in direct contact with the positioning portion and in direct contact with the colored portion of the first cover,
wherein the sealing material contacts the tip of the positioning portion that extends from the colored portion of the first cover,
wherein the sealing material is not disposed between the conductor and the first cover, and
wherein the positioning portion is formed of resin material, wherein the colored portion of the first cover is formed as a surrounding frame that surrounds the at least one solar cell as viewed in a plan view.

US Pat. No. 10,658,534

BI-FACIAL PHOTOVOLTAIC POWER GENERATION MODULE

1. A bi-facial photovoltaic power generation module, comprising a transparent box, and a cell string and a mounting base which are installed inside the transparent box, wherein the transparent box is internally provided with a positive terminal and a negative terminal passing through two side faces of the transparent box, respectively, the cell string is formed by connecting several N-type bi-facial monocrystalline silicon cells in series or in parallel, with one end of the cell string connected to a positive wire and the other end thereof connected to a negative wire; the positive wire is welded on the positive terminal and the negative wire is welded on the negative terminal; and the mounting base is provided with several parallel strip-shaped slots in which the N-type bi-facial monocrystalline silicon cells are vertically plugged.

US Pat. No. 10,658,533

RELIABLE INTERCONNECTION OF SOLAR CELLS

SolAero Technologies Corp...

13. A method of making an interconnection between a solar cell and an adjoining discrete bypass diode comprising:providing a solar cell comprising a top surface including a contact of a first polarity type disposed along a first peripheral edge thereof, and a rear surface including a contact of a second polarity type;
providing a bypass diode comprising a top surface including a contact of a first polarity type, and a rear surface including a contact of a second polarity type;
providing a metallic first interconnect element comprising: a first end comprising at least three members, each member having a pair of parallel gap apertures for mounting the adjoining bypass diode; a second opposing end comprising at least two members, each member having a pair of parallel gap apertures for mounting the adjoining solar cell; and one or more interconnect connecting portions to attach the first end of the interconnect element to the second end of the interconnect element;
aligning the metallic first interconnect element with respect to the solar cell and the bypass diode so that the second opposing end of the interconnect element extends over a portion of the rear surface of the solar cell, and the first end of the interconnect element extends over a portion of the rear surface of the bypass diode;
welding the first interconnect element to the rear surface of the bypass diode at a first weld point at the location of a pair of parallel gap apertures adapted for use in a parallel gap welding process at the first end of the interconnect element that extends over a portion of the rear surface of the bypass diode;
welding the first interconnect element to the rear surface of the bypass diode at a second weld point at the location of a pair of parallel gap apertures adapted for use in a parallel gap welding process at the first end of the interconnect element that extends over a portion of the rear surface of the bypass diode;
welding the interconnect element to a portion of the rear surface of the solar cell at a first weld point at the location of a pair of parallel gap apertures adapted for use in a parallel gap welding process at the second opposing end of the interconnect element that extends over a portion of the rear surface of the solar cell; and
welding the interconnect element to a portion of the rear surface of the solar cell at a second weld point at the location of a pair of parallel gap apertures adapted for use in a parallel gap welding process at the second opposing end of the interconnect element that extends over a portion of the rear surface of the solar cell.

US Pat. No. 10,658,532

FABRICATING THIN-FILM OPTOELECTRONIC DEVICES WITH ADDED RUBIDIUM AND/OR CESIUM

FLISOM AG, Niederhasli (...

1. A thin-film optoelectronic device, comprising:an alkali-nondiffusing substrate;
a back-contact layer disposed over the alkali-nondiffusing substrate;
an absorber layer disposed over the back-contact layer, wherein the absorber layer is made of an ABC material, wherein A comprises Cu or Ag, B comprises In, Ga or Al, and C comprises S, Se or Te; and
a front-contact layer disposed over the absorber layer, wherein a concentration of Rb or Cs in the absorber layer and the front-contact layer is from 500 atoms per million atoms to 2,500 atoms per million atoms (ppm).

US Pat. No. 10,658,531

SPALLING TECHNIQUES FOR MANUFACTURING PHOTODIODES

International Business Ma...

1. A method for forming an optical semiconductor device, the method comprising:forming an optical device semiconductor material layer on a substrate;
depositing a metal stressor layer on top of the optical device semiconductor material layer;
attaching a first handle layer to the metal stressor layer;
removing the optical device semiconductor material layer from the substrate by pulling the first handle layer away from the substrate and with it a stack comprising the metal stressor layer and a portion of the substrate;
removing the first handle layer and the metal stressor layer from the stack; and
forming a second handle layer on the remaining portion of the substrate, wherein the second handle layer is UV transparent.

US Pat. No. 10,658,530

MULTI-WELL SELENIUM DEVICE AND METHOD FOR FABRICATION THEREOF

The Research Foundation f...

1. A nanopattern, multi-well, solid-state a-Se radiation detector comprising:a semiconductor;
a pixel electrode;
at least three dielectric layers; and
at least two conductive grid electrode layers,
wherein the pixel electrode is deposited adjacent to a substrate,
wherein a first conductive grid electrode layer of the at least two conductive grid electrode layers is deposited on a first dielectric layer of the at least three dielectric layers,
wherein a second dielectric layer of the at least three dielectric layers is deposited on the first conductive grid electrode layer,
wherein a second conductive grid electrode layer of the at least two conductive grid electrode layers is deposited on the second dielectric layer,
wherein a third dielectric layer of the at least three dielectric layers is deposited on the second conductive grid electrode layer,
wherein an etch mask is deposited on the third dielectric layer,
wherein a first etching forms at least two pillars with at least one well therebetween,
wherein an oxide dielectric layer is deposited on the at least two pillars and on a bottom of the at least one well, and
wherein a second etching removes the oxide dielectric layer from the bottom of the at least one well.

US Pat. No. 10,658,529

SOLAR CELL AND MANUFACTURING METHOD THEREOF

LG ELECTRONICS INC., Seo...

1. A manufacturing method of a back contact solar cell, the manufacturing method comprising:forming a tunneling oxide layer on one surface of a single crystalline silicon substrate;
depositing an amorphous silicon layer on the tunneling oxide layer, wherein the amorphous silicon layer is hydrogenated amorphous silicon;
doping the amorphous silicon layer with a first conductive dopant and a second conductive dopant to form a first conductive semiconductor layer and a second conductive semiconductor layer;
forming an insulation layer on the amorphous silicon layer having the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the insulation layer has a hydrogen content of 1 at % to 25 at %;
hydrogenating the amorphous silicon layer and the tunneling oxide layer by diffusing hydrogen of the insulation layer into the amorphous silicon layer, wherein the amorphous silicon layer has a hydrogen content of 7 at % to 20 at % after the hydrogenating;
forming a first opening and a second opening in the insulation layer, forming a first electrode to contact the first conductive semiconductor layer through the first opening; and
forming a second electrode to contact the second conductive semiconductor layer through the second opening.

US Pat. No. 10,658,528

CONDUCTIVE PASTE COMPOSITION AND SEMICONDUCTOR DEVICES MADE THEREWITH

DUPONT ELECTRONICS, INC.,...

1. A paste composition for use in forming a conductive structure situated on a semiconductor substrate having an insulating layer on a major surface thereof, the paste composition comprising:an inorganic solids portion that comprises:
(a) 93 to 99% by weight of the solids of a source of electrically conductive metal, and
(b) 1 to 7% by weight of the solids of an oxide-based fusible material, and
an organic vehicle in which the constituents of the inorganic solids portion are dispersed,
wherein the oxide-based fusible material comprises, by cation percent of the oxides:
20 to 35% PbO,
35 to 48% TeO2,
5 to 12% Bi2O3,
3.5 to 6.5% WO3,
0 to 2% B2O3,
10 to 20% Li2O, and
0.5 to 8% Na2O,
with the proviso that a ratio of the cation percentage of TeO2 to the cation percentage of WO3 in the fusible material ranges from 7.5:1 to 10:1,
and wherein the paste composition, when deposited on the insulating layer and fired, is capable of penetrating the insulating layer and forming the conductive structure electrically connected to the semiconductor substrate.

US Pat. No. 10,658,527

SOLAR CELL AND SOLAR CELL MANUFACTURING METHOD

HANWHA Q CELLS GMBH, Bit...

1. A solar cell comprising:a semiconductor substrate;
a paste metallization arranged on a substrate surface of the semiconductor substrate; and
a tunnel layer arranged between the substrate surface and the paste metallization and being a dielectric layer in which there are precipitates present;
wherein the paste metallization and the tunnel layer are in direct contact with one another, and the paste metallization and the tunnel layer cover substantially the entire substrate surface.

US Pat. No. 10,658,526

PHOTOVOLTAIC DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A photovoltaic device comprising:a semiconductor substrate;
first amorphous semiconductor strips provided on one of faces of the semiconductor substrate, the first amorphous semiconductor strips having a first conductivity type;
second amorphous semiconductor strips provided on the one of faces of the semiconductor substrate, the second amorphous semiconductor strips having a second conductivity type that differs from the first conductivity type;
a plurality of first electrodes including at least two first electrodes provided discontinuously on each of the first amorphous semiconductor strips; and
a plurality of second electrodes including at least two second electrodes provided discontinuously on each of the second amorphous semiconductor strips,
wherein the second amorphous semiconductor strips are adjacent, in a first direction in an in-plane direction of the semiconductor substrate, to the first amorphous semiconductor strips, and
wherein the first amorphous semiconductor strips are spaced apart from each other in a second direction that differs from the first direction, and the second amorphous semiconductor strips are spaced apart from each other in the second direction.

US Pat. No. 10,658,525

SOLAR CELLS WITH IMPROVED LIFETIME, PASSIVATION AND/OR EFFICIENCY

SunPower Corporation, Sa...

1. A method of fabricating a solar cell, the solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, the method comprising:forming a dielectric region on a back side of a silicon substrate;
forming a first emitter region over the dielectric region;
forming a dopant region on a front side of the silicon substrate; and
heating the silicon substrate at a temperature above 900 degrees Celsius to getter contaminants to a portion of the silicon substrate, to getter contaminants to the emitter region, and to drive dopants from the dopant region to the portion of the silicon substrate; and
prior to heating the silicon substrate at the temperature above 900 degrees Celsius, performing at least one other separate and distinct heating operation at a temperature below 900 degrees Celsius.

US Pat. No. 10,658,524

SCHOTTKY BARRIER DIODE

ROHM CO., LTD., Kyoto (J...

1. A Schottky barrier diode comprising:a semiconductor layer, having a major surface;
a diode region of a first conductivity type, formed in a surface layer portion of the semiconductor layer;
a first conductivity type impurity region, formed in the surface layer portion of the semiconductor layer and electrically connected to the diode region;
a first electrode layer, formed on the major surface of the semiconductor layer and forming a Schottky junction with the diode region;
a second electrode layer, formed on the major surface of the semiconductor layer and forming an ohmic junction with the first conductivity type impurity region; and
a contact electrode layer, formed on a peripheral region of the major surface of the semiconductor layer surrounding the first electrode layer so as to be electrically connected to the diode region via the semiconductor layer and being electrically connected to the second electrode layer;
wherein a breakdown voltage between the first electrode layer and the second electrode layer is not less than 20 V.

US Pat. No. 10,658,523

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an n-type semiconductor substrate;
a p-type anode layer provided in a front surface of the n-type semiconductor substrate;
an anode electrode provided on the p-type anode layer; and
a plurality of wires each connected to the anode electrode, wherein
the p-type anode layer includes:
a plurality of first p-type anode layers each disposed in a position right under a portion where a respective one of the plurality of wires is connected; and
a plurality of second p-type anode layers each disposed between respective ones of the plurality of first p-type anode layers to exclude positions right under portions where each of the wires is connected, and
an impurity concentration of the first p-type anode layers is higher than an impurity concentration of the second p-type anode layers.

US Pat. No. 10,658,522

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor stacked layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer;
a gate electrode layer; and
a gate insulating film between the gate electrode layer and the oxide semiconductor stacked layer,
wherein the gate electrode layer and the oxide semiconductor stacked layer overlap each other,
wherein the third oxide semiconductor layer is in direct contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer, and
wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise indium and zinc.

US Pat. No. 10,658,521

ENABLING RESIDUE FREE GAP FILL BETWEEN NANOSHEETS

International Business Ma...

1. A method for forming a semiconductor structure, the method comprising at least:depositing a gap fill material over a plurality of channel regions such that the gap fill material surrounds and directly contacts gate structures surrounding nanosheet channel layers in each of the plurality of channel regions and further filling gaps between the gate structures;
etching away portions of the gap fill material situated between each of the plurality of channel regions and in contact with sidewalls of each of the gate structures in the plurality of channel regions, the etching forming a respective gap fill material layer between and in contact with the gate structures in each of the plurality of channel regions; and
after the portions of the gap fill material have been etched away, forming a masking layer over at least the gate structures and the gap fill material layer in at least a first channel region of the plurality of channel regions, wherein the gate structures and the gap fill material layer in at least a second channel region of the plurality of channel regions remain exposed.

US Pat. No. 10,658,520

SEMICONDUCTOR DEVICE COMPRISING ROUNDED SOURCE AND DRAIN ELECTRODES

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor comprising:
a semiconductor layer;
a first conductor over the semiconductor layer;
a second conductor over the semiconductor layer;
a gate insulating film over the semiconductor layer, the first conductor, and the second conductor; and
a gate electrode over the gate insulating film,
wherein, in a plan view of the semiconductor device, each of the first conductor and the second conductor comprises a first side surface, a second side surface, a first curved corner between the first side surface and the second side surface, a third side surface, a second curved corner between the first side surface and the third side surface, a fourth side surface, a third curved corner between the second side surface and the fourth side surface, a fifth side surface, and a fourth curved corner between the third side surface and the fifth side surface,
wherein, in the plan view of the semiconductor device, the first side surface, the second side surface the third side surface the fourth side surface the fifth side surface the first curved corner, the second curved corner, the third curved corner, and the fourth curved corner of each of the first conductor and the second conductor overlap with the semiconductor layer,
wherein, in the plan view of the semiconductor device, the first curved corner and the second curved corner of each of the first conductor and the second conductor overlap with the gate electrode,
wherein, in the plan view of the semiconductor device, the third curved corner and the fourth curved corner of each of the first conductor and the second conductor do not overlap with the gate electrode, and
wherein each of an angle between the first side surface of the first conductor and the second side surface of the first conductor, an angle between the first side surface of the first conductor and the third side surface of the first conductor, an angle between the first side surface of the second conductor and the second side surface of the second conductor, and an angle between the first side surface of the second conductor and the third side surface of the second conductor is greater than 90° and less than or equal to 150°.

US Pat. No. 10,658,519

SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, MODULE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming a second insulator over a first insulator;
forming a first opening whose bottom portion reaches the first insulator in the second insulator;
forming a first gate electrode in the first opening;
forming a first gate insulator over the second insulator and the first gate electrode;
forming a first oxide over the first gate insulator;
forming a second oxide over the first oxide;
forming a third oxide over the second oxide;
forming a conductor over the third oxide;
forming a first layer over the conductor;
forming a second opening by processing the first layer by a lithography method so that the conductor is exposed in a bottom portion of the second opening;
forming a second layer comprising the second opening, the third oxide, the conductor, and the first layer by processing the third oxide, the conductor, and the first layer by a lithography method;
processing the second oxide and the first oxide with use of the second layer as an etching mask;
removing the third oxide and the conductor exposed in the bottom portion of the second opening to expose the second oxide in the bottom portion of the second opening, to divide the conductor into a source electrode and a drain electrode, the third oxide into a fourth oxide and a fifth oxide, and the first layer into a third layer and a fourth layer, and to form a fifth layer comprising the first oxide, the second oxide, the source electrode, the drain electrode, the fourth oxide, the fifth oxide, the third layer, and the fourth layer;
performing plasma treatment using an oxidizing gas to release and reduce an impurity included in the first oxide and the second oxide;
performing heat treatment in an atmosphere comprising a nitrogen gas and heat treatment in an atmosphere comprising an oxygen gas to release and reduce hydrogen and water included in the first oxide and the second oxide;
forming a sixth oxide over the fifth layer;
forming a second gate insulator over the sixth oxide;
forming a seventh oxide over the second gate insulator; and
forming a second gate electrode over the seventh oxide,
wherein oxygen is added to the second gate insulator in the step of forming the seventh oxide.

US Pat. No. 10,658,518

MAGNESIUM ZINC OXIDE-BASED HIGH VOLTAGE THIN FILM TRANSISTOR

RUTGERS, THE STATE UNIVER...

1. A Magnesium Zinc Oxide, MgxZn1-xO (MZO)-based High Voltage Thin Film Transistor (MZO HVTFT) having a concentric circular structure, comprisinga substrate;
a ring-shaped gate electrode deposited on the substrate;
a circular dielectric insulating layer deposited and patterned over the gate electrode;
a circular MgyZn1-yO transition layer (MZO-TL) over the dielectric insulating layer;
a MgxZn1-xO (MZO) ring-shaped channel layer deposited and patterned over the transition layer (TL) so as to be concentric with the gate electrode;
a circular electrode deposited over the channel layer so as to be concentric with the gate electrode to serve as a drain for the MZO HVTFT;
a ring-shaped electrode deposited over the channel layer so as to be concentric with the gate electrode to serve as a source for the MZO HVTFT; and
a passivation layer deposited on the MZO HVTFT;
wherein a first offset region (LGD) is defined between the gate and the drain, and a second offset region (LGS) is defined between the gate and the source, further wherein the gate electrode, the source and the drain are arranged in a concentric alignment; and
wherein 0

US Pat. No. 10,658,517

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming an oxide semiconductor film having a tapered end face portion over a substrate having an insulating surface;
forming a conductive film over the oxide semiconductor film;
etching the conductive film with an etching gas comprising halogen to form a source electrode layer and a drain electrode layer each overlapping with the oxide semiconductor film and a part of the tapered end face portion;
removing an element contained in the etching gas from the exposed rest of the tapered end face portion after etching the conductive film;
forming a gate insulating film over the oxide semiconductor film; and
forming a gate electrode layer over the gate insulating film.

US Pat. No. 10,658,516

THIN FILM TRANSISTOR, ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A method for manufacturing a thin film transistor, comprising:forming a source and drain on a base substrate;
forming a semiconductor layer; and
between forming the source and drain and forming the semiconductor layer, the method further comprises:
forming a diffusion barrier layer, wherein metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed, wherein the metal silicide comprises the metal atoms diffused from the source and drain,
wherein the source and drain is separated from the metal transition layer by the diffusion barrier layer, and
wherein the part of the semiconductor layer is configured to become the metal transition layer, and another part of the semiconductor layer is configured to be an active layer of the thin film transistor.

US Pat. No. 10,658,515

ELECTRONIC DEVICE INCLUDING LIGHT DETECTION DEVICE AND OPERATION METHOD THEREOF

Samsung Electronics Co., ...

1. An electronic device comprising:a display;
a proximity sensor disposed behind the display, the proximity sensor configured to emit and receive a light of a specific wavelength band;
a memory storing instructions; and
a processor configured to execute the instructions to:
receive a phone call while the display is activated;
while a plurality of pixels of the display disposed correspondingly to a position of the proximity sensor are activated during the phone call, refrain from emitting any light using the proximity sensor, and
while the plurality of pixels of the display are deactivated during the phone call, emit the light of the specific wavelength band through a portion of the display corresponding to the plurality of pixels using the proximity sensor and receive the light of the specific wavelength band, emitted by the proximity sensor and reflected by an object, using the proximity sensor to identify a distance between the electronic device and the object,
wherein the portion of the display corresponding to the plurality of pixels is configured to allow light to pass therethrough.

US Pat. No. 10,658,514

GATE-ALL-AROUND FIN DEVICE

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a doped well in a substrate of a first conductivity type;
forming a doped continuous well of a second conductivity type in the substrate of the first conductivity type;
forming a source contact of the first conductivity type to contact a gate structure over the doped continuous well of the second conductivity type; and
forming drain regions of the second conductivity type to contact the gate structure over the doped continuous well,
wherein the drain regions include alternating p regions and n regions.

US Pat. No. 10,658,513

FORMATION OF FINFET JUNCTION

International Business Ma...

1. A finFET structure comprising:a fin, wherein the fin comprises a source/drain region and a channel region, wherein a portion of the fin in the source/drain region is silicon germanium;
an epitaxial layer located above the source/drain region; a spacer layer located above the source/drain region and adjacent to the epitaxial layer; and
a dielectric layer above the channel region of the fin, wherein a first portion of a vertical surface of the dielectric layer is in direct contact with the spacer layer and above the channel region of the fin, wherein a second portion of the vertical surface of the dielectric layer is in direct contact with the source/drain region of the fin, and wherein a horizontal surface of the dielectric layer is in direct contact with the entire channel region.

US Pat. No. 10,658,512

FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A fabrication method of a fin field effect transistor, comprising:forming a base substrate including a substrate and fins protruding from the substrate, wherein:
the substrate includes a first region and a second region;
the fins include at least a first fin protruding from the substrate in the first region, and at least a second fin protruding from the substrate in the second region; and
the second fin includes a sacrificial layer and a semiconductor layer covering the sacrificial layer;
forming a first dummy gate oxidation layer on a portion of the first fin by an in-situ steam generation-decouple plasma nitrogen (ISSG-DPN) treatment process; and
forming a second dummy gate oxidation layer on a portion of the second fin.

US Pat. No. 10,658,511

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor device, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate, and
a first fin and a second fin positioned on the substrate;
depositing a first interlayer dielectric layer on the semiconductor structure;
performing first partial etching on the first interlayer dielectric layer to expose a top of the first fin;
after the top of the first fin is exposed, removing a part of the first fin to form a first groove;
epitaxially growing a first electrode in the first groove;
performing second partial etching on the first interlayer dielectric layer to expose a top of the second fin;
after the top of the second fin is exposed, removing a part of the second fin to form a second groove, wherein the second groove is separated from the first groove; and
epitaxially growing a second electrode in the second groove.

US Pat. No. 10,658,510

SOURCE/DRAIN STRUCTURE

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium;
implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure;
implanting a second dopant into the amorphous region containing the first dopant; and
heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

US Pat. No. 10,658,509

FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a first fin structure extending from a top surface of a substrate to a first height, the first fin structure having a first width at a first interface with the top surface of the substrate and a second width away from the top surface of the substrate, the first width being greater than the second width;
a second fin structure extending from the top surface of the substrate to a second height that is different than the first height, the second fin structure having a convex upper surface, the second fin structure having the first width at a second interface with the top surface of the substrate; and
a dielectric layer disposed on the substrate and extending from the first fin to the second fin, wherein the dielectric layer has a third width at a third interface with the top surface of the substrate and a fourth width away from the top surface of the substrate, wherein the third width is smaller than the fourth width.

US Pat. No. 10,658,508

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH LOW RESISTANCE CONTACT

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:forming a fin structure over a semiconductor substrate;
forming a gate stack over the fin structure;
forming an epitaxial structure over the fin structure, wherein the epitaxial structure is adjacent to the gate stack;
forming a dielectric layer over the epitaxial structure and the gate stack;
forming an opening in the dielectric layer to expose the epitaxial structure;
forming a modified region in the epitaxial structure, wherein the modified region has lower crystallinity than an inner portion of the epitaxial structure, the modified region is formed by generating and introducing plasma into the opening, the plasma includes ions with different charges and is directly introduced into the opening without being filtered out, and the modified region extends along an entirety of an exposed surface of the epitaxial structure;
forming a semiconductor-metal compound region on the epitaxial structure, wherein at least a portion of the modified region is transformed into the semiconductor-metal compound region; and
forming a conductive structure over the semiconductor-metal compound region, wherein the conductive structure is in direct contact with the semiconductor-metal compound region.

US Pat. No. 10,658,507

VERTICAL TRANSISTOR PASS GATE DEVICE

INTERNATIONAL BUSINESS MA...

1. A device comprising:a first source/drain region having a first semiconductor material with a diamond shaped geometry is present at a first end of a fin structure, the fin structure being present on a substrate;
a second source/drain region having a second semiconductor material with said diamond shaped geometry that is present at the second end of the fin structure; and
a fin channel region between the first and second source/drain regions, wherein the first source/drain region, the fin channel region, and second source/drain region are arranged perpendicular to the plane of an upper surface of the substrate, wherein a size for the first semiconductor material with the diamond geometry is different than a size for the second semiconductor material with the diamond geometry.

US Pat. No. 10,658,506

FIN CUT LAST METHOD FOR FORMING A VERTICAL FINFET DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A vertical FinFET structure, comprising:a pair of fins disposed over a semiconductor substrate;
a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each fins is in contact with the bottom source/drain region;
a bottom spacer disposed over the bottom source/drain region;
a gate stack disposed over sidewalls of the fins, the gate stack extending laterally over the bottom spacer on opposing sides of each fin;
a top spacer disposed over the gate stack;
a first dielectric layer disposed over the top spacer;
a top source/drain region disposed over an upper portion of each of the fins; and
an isolation structure comprising an isolation dielectric layer disposed between the pair of fins, wherein the isolation structure includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each fin, and a middle portion above a bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width.

US Pat. No. 10,658,505

HIGH VOLTAGE DEVICE AND A METHOD FOR FORMING THE HIGH VOLTAGE DEVICE

GLOBALFOUNDRIES Singapore...

1. A high voltage device comprising: a substrate comprising a recessed region, the recessed region comprising a recessed surface arranged lower than a top surface of the substrate; a source region at least partially arranged within the substrate under the recessed surface; a drain region at least partially arranged within the substrate under the top surface and at a higher position than the source region; a gate structure comprising a first portion and a second portion arranged over the recessed region, wherein the first portion is nearer to the source region, and wherein the second portion is nearer to the drain region; and an oxide layer comprising a first part arranged between the first portion of the gate structure and the recessed surface of the recessed region and a second part arranged between the second portion of the gate structure and the recessed surface of the recessed region, wherein the second part of the oxide layer is thicker than the first part of the oxide layer, and wherein the first portion of the gate structure including a gate electrode portion, is in direct contact with an upper surface of the first part of the oxide layer.

US Pat. No. 10,658,504

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit device comprising:a first second-conductivity-type well region of a second conductivity type provided in a surface layer of a first-conductivity-type semiconductor layer of a first conductivity type;
a circuit region formed in the first second-conductivity-type well region;
a second second-conductivity-type well region of the second conductivity type provided in the surface layer of the first-conductivity-type semiconductor layer and in contact with the first second-conductivity-type well region, the second second-conductivity-type well region surrounding a periphery of the first second-conductivity-type well region and having an impurity concentration that is lower than that of the first second-conductivity-type well region;
a first-conductivity-type well region of the first conductivity type provided in the surface layer of the first-conductivity-type semiconductor layer and in contact with the second second-conductivity-type well region, the first-conductivity-type well region surrounding a periphery of the second second-conductivity-type well region;
a first isolating region of the first conductivity type provided separated from and at a distance farther inward than is the first-conductivity-type well region, the first isolating region having a part that in an opened layout, is interposed between the circuit region and the first-conductivity-type well region and that is provided at a depth reaching the first-conductivity-type semiconductor layer from a surface of the first second-conductivity-type well region or the second second-conductivity-type well region;
a second-conductivity-type high concentration region of the second conductivity type provided in the first second-conductivity-type well region and having an impurity concentration that is higher than that of the first second-conductivity-type well region;
a first electrode in contact with the second-conductivity-type high concentration region;
a first field plate that is a part of the first electrode extended farther outward than is an outer periphery of the first second-conductivity-type well region; and
an insulated gate semiconductor element having, as a drain region, a second-conductivity-type region of the second conductivity type of the first second-conductivity-type well region or the second second-conductivity-type well region, the second-conductivity-type region being provided at a distance farther inward than is the first isolating region; the insulated gate semiconductor element having, as a drift region, the first second-conductivity-type well region or the second second-conductivity-type well region, or first second-conductivity-type well region and the second second-conductivity-type well region, and the insulated gate semiconductor element having, as a base region, the first-conductivity-type well region, wherein
the first isolating region includes any one of:
a protruding part at a location other than inside the drain region and protruding farther outward than is the outer periphery of the first second-conductivity-type well region, and
an additional part provided separated from and farther outward than is the first isolating region,
the protruding part sandwiches the interlayer insulating film with the first field plate and is covered by the first field plate, the protruding part being positioned farther inward than is the outer periphery of the first field plate and the protruding part being near the outer periphery of the first field plate, and
the additional part sandwiches the interlayer insulating film with the first field plate and is covered by the first field plate, the additional part being positioned farther inward than is the outer periphery of the first field plate and the additional part being near the outer periphery of the first field plate.

US Pat. No. 10,658,503

DIODE, SEMICONDUCTOR DEVICE, AND MOSFET

TOYOTA JIDOSHA KABUSHIKI ...

1. A diode comprising:a cathode electrode;
a cathode region made of a first conductivity type semiconductor;
a drift region made of the first conductivity type semiconductor and having an impurity concentration lower than that of the cathode region;
an anode region made of a second conductivity type semiconductor;
an anode electrode;
a barrier region formed between the drift region and the anode region, made of the first conductivity type semiconductor, and having an impurity concentration higher than that of the drift region;
a pillar electrode made of metal and formed so as to connect the barrier region to the anode electrode; and
a Schottky junction connecting the barrier region and the pillar electrode.

US Pat. No. 10,658,502

VERTICAL III-N TRANSISTORS WITH LATERAL OVERGROWTH OVER A PROTRUDING III-N SEMICONDUCTOR STRUCTURE

Intel Corporation, Santa...

11. A method of forming a III-N transistor, the method comprising:epitaxially growing a first III-N material on a substrate, the first III-N material comprising a first concentration of donor impurities;
epitaxially growing a second III-N material from a surface of the first III-N material to backfill a trench in an amorphous layer that is over a portion of the first III-N material, wherein the second III-N material has a second concentration of donor impurities, less than the first concentration;
epitaxially growing a third III-N material from a surface of the second III-N material;
forming a gate electrode over the third III-N material;
forming drain contact metallization through the amorphous layer and contacting the first III-N material; and
forming source contact metallization coupled to the third III-N material.

US Pat. No. 10,658,501

VERTICALLY STACKED MULTICHANNEL PYRAMID TRANSISTOR

Mitsubishi Electric Resea...

1. A high electron mobility transistor (HEMT), comprising:a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack, wherein the stack of layers includes a first layer and a second layer, wherein a magnitude of polarization of the first layer is greater than a magnitude of polarization of the second layer arranged in the stack below the first layer, and wherein the width of the first layer is less than the width of the second layer to form a staircase profile of the channel semiconductor structure;
a source semiconductor structure including a heavily doped semiconductor material, the source semiconductor structure is electrically connected to the channel semiconductor structure to provide carriers to all carrier channels;
a drain semiconductor structure including the heavily doped semiconductor material, the drain semiconductor structure is electrically connected to the channel semiconductor structure to receive the carriers on all carrier channels; and
a source electrode arranged on the source semiconductor structure to make electrical contacts with each carrier channel;
a drain electrode arranged on the drain semiconductor structure to make electrical contacts with each carrier channel; and
a gate electrode arranged between the source electrode and the drain electrode along the length of the HEMT to modulate the conductivity of the carrier channels, wherein the gate electrode has a staircase shape having trends and risers tracking the staircase profile of the semiconductor structure, wherein the risers have different heights.

US Pat. No. 10,658,500

LAYER STRUCTURE FOR A GROUP-III-NITRIDE NORMALLY-OFF TRANSISTOR

AZURSPACE Solar Power Gmb...

1. A group-III-nitride layer structure for a normally-off transistor, the layer structure comprising:an electron-supply layer made of at least one first group-III-nitride material having a first band-gap energy;
a back-barrier layer made of at least one second group-III-nitride material having a second band-gap energy; and
a channel layer arranged between the electron-supply layer and the back barrier layer and being made of a third group-III-nitride material having a third band-gap energy that is lower first and second band-gap energies,
wherein the second group-III-nitride material of the back-barrier layer is of a p-type conductivity, while the first group-III-nitride material of the electron-supply layer and the third group-III-material of the channel layer are not of the p-type conductivity,
wherein the first band-gap energy of the first group-III-nitride material of the electron-supply layer is smaller than the second band-gap energy of the second group-III-nitride material of the back-barrier layer,
wherein, in absence of an external voltage applied to the layer structure, a lower conduction band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the third group-III-nitride material in the channel layer,
wherein the group-III-nitride layer structure further comprises a spacer layer between the channel layer and the electron-supply layer, the spacer layer having a thickness of not more than 3 nanometers and being made of AlN or AlGaN having a higher Al mole fraction than the electron-supply layer, and
wherein the group-III-nitride layer structure further comprising exactly two recesses reaching vertically down to a channel region of the channel layer, each recess accommodating either the source contact or the drain contact.

US Pat. No. 10,658,499

INSULATED GATE BIPOLAR TRANSISTOR AND DIODE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer having a first principal surface on one side and a second principal surface on the other side;
a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer;
an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer;
a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer;
a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer; and
a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer and having a line-shaped pattern including a first line extending along a first direction and a second line extending along a second direction intersecting the first direction and connected to the first line as viewed in plan,
wherein the line-shaped pattern of the cathode region includes a pattern extending in a meandering form as viewed in plan.

US Pat. No. 10,658,498

SEMICONDUCTOR DEVICE INCLUDING DIODE STRUCTURE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a semiconductor substrate;
an upper electrode provided on an upper surface of the semiconductor substrate; and
a lower electrode provided on a lower surface of the semiconductor substrate located opposite to the upper surface,
wherein the semiconductor substrate comprises:
a p-type anode region being in contact with the upper electrode;
an n-type cathode region being in contact with the lower electrode;
an n-type drift region interposed between the anode region and the cathode region, a carrier density of the drift region being lower than a carrier density of the cathode region,
a barrier region interposed between the anode region and the drift region; and
an n-type pillar region extending between the barrier region and the upper electrode, the pillar region being in Schottky contact with the upper electrode,
the barrier region comprises a multi-layer structure comprising an n-type first barrier layer, a p-type second barrier layer and an n-type third barrier layer, wherein the second barrier layer is interposed between the first barrier layer and the third barrier layer,
carrier densities of the first and third barrier layers are each higher than the carrier density of the drift region, and
the first barrier layer is in contact with the anode region and is connected to the upper electrode via the pillar region.

US Pat. No. 10,658,497

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES WITH SUPERJUNCTION STRUCTURES

Infineon Technologies Aus...

1. A method for manufacturing semiconductor devices, the method comprising:providing a semiconductor substrate having a surface region at a first side of the semiconductor substrate, the surface region having an initial surface oxygen concentration of less than 6×1017 cm?3;
forming an epitaxial layer on the first side of the semiconductor substrate; and
forming a plurality of superjunction semiconductor device structures in the epitaxial layer,
wherein the semiconductor substrate has an initial oxygen bulk concentration of at least 6×1017 cm?3, the method further comprising:
prior to forming the epitaxial layer, subjecting the semiconductor substrate to a thermal oxygen-out-diffusion anneal in an ambient containing one or more of oxygen, argon, hydrogen and nitrogen at a temperature sufficient to reduce the oxygen concentration at least in the surface region of the semiconductor substrate, to reduce the mean oxygen concentration below 6×1017 cm?3 in the surface region,
wherein the surface region extends from the first side to a depth in the semiconductor substrate of at least 10 ?m.

US Pat. No. 10,658,496

HIGH-SPEED SUPERJUNCTION LATERAL INSULATED GATE BIPOLAR TRANSISTOR

Chongqing University, Ch...

1. A high-speed superjunction lateral insulated gate bipolar transistor, characterized in that a cell structure of the transistor comprises:a semiconductor first substrate region;
a voltage-sustaining region, which is located on a surface of the semiconductor first substrate region, and comprises mutually alternating semiconductor first drift regions and semiconductor second drift regions of different conductivity types, the semiconductor first drift region has a conductivity type the same as that of the semiconductor first substrate region, and the semiconductor second drift region has a conductivity type opposite to that of the semiconductor first substrate region, the conductivity type being N type or P type;
a semiconductor field stop region having a conductivity type the same as that of the semiconductor first substrate region and located on a surface of the semiconductor first substrate region, wherein at least one semiconductor collector region having a conductivity type opposite to that of the semiconductor first substrate region is provided in the semiconductor field stop region, and a portion of a surface of the semiconductor collector region is covered with a conductor to form a collector of the transistor;
a semiconductor body region having a conductivity type opposite to that of the semiconductor first substrate region;
a semiconductor emitter region having a conductivity type the same as that of the semiconductor first substrate region and located in the semiconductor body region, a portion of the semiconductor body region and a portion of the semiconductor emitter region being connected by a conductor to form an emitter of the transistor;
a gate insulating layer covering a portion of a surface of the semiconductor emitter region, a portion of a surface of the semiconductor body region, and a portion of a surface of the voltage-sustaining region, wherein a semiconductor polysilicon gate region covering a surface of the gate insulating layer and a conductor covering the semiconductor polysilicon gate region form a gate electrode of the transistor, the gate region has a conductivity type the same as that of the semiconductor first substrate region; and a portion of the semiconductor emitter region, a portion of the semiconductor body region, the gate insulating layer, the semiconductor polysilicon gate region, the gate electrode and a portion of the voltage-sustaining region form a gate structure of the transistor;
wherein the semiconductor first drift region and the semiconductor second drift region are in contact with each other and contact surfaces are perpendicular to the semiconductor first substrate region and the semiconductor field stop region;
the voltage-sustaining region and the semiconductor field stop region are in contact with each other and a contact surface is perpendicular to the semiconductor first substrate region.

US Pat. No. 10,658,495

VERTICAL FIN TYPE BIPOLAR JUNCTION TRANSISTOR (BJT) DEVICE WITH A SELF-ALIGNED BASE CONTACT

INTERNATIONAL BUSINESS MA...

1. A method of forming a silicon-germanium heterojunction bipolar transistor (HBT) device, comprising:forming a stack of four doped semiconductor layers on a semiconductor substrate;
forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers;
removing portions of the second, third, and fourth semiconductor layers to form a vertical fin;
recessing the second doped semiconductor layer and fourth doped semiconductor layer;
depositing a condensation layer on the exposed surfaces of the second doped semiconductor layer, third doped semiconductor layer, and fourth doped semiconductor layer; and
reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion of the third doped semiconductor layer.

US Pat. No. 10,658,494

TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:obtaining an intermediate semiconductor device having a substrate comprising a doped silicon substrate, a first insulator disposed above the substrate, a gate material layer over the first insulator, a second insulator above the gate material layer, and a first hardmask;
etching a first plurality of vertical trenches through the first hardmask, the first insulator, the second insulator, and the gate material layer to the substrate;
epitaxially growing a plurality of silicon nanowires from the substrate at a bottom surface of the first plurality of vertical trenches;
etching a second plurality of vertical trenches through the first hardmask and the second insulator to expose the gate material layer;
applying a mask covering a portion of the first hardmask that includes the second plurality of vertical trenches;
after applying the mask, etching a third plurality of vertical trenches through the mask, the first hardmask, the first insulator, and the second insulator to the substrate;
depositing an insulating spacer material on a plurality of sidewalls of the second plurality of vertical trenches and the third plurality of vertical trenches;
forming a plurality of drain contacts on the plurality of silicon nanowires;
forming a plurality of gate contacts in the second plurality of vertical trenches; and
forming a plurality of source contacts in the third plurality of vertical trenches.

US Pat. No. 10,658,493

GATE SPACER AND INNER SPACER FORMATION FOR NANOSHEET TRANSISTORS HAVING RELATIVELY SMALL SPACE BETWEEN GATES

INTERNATIONAL BUSINESS MA...

1. A nanosheet field effect transistor (FET) device comprising:a gate spacer; and
an inner spacer;
wherein the gate spacer comprises an upper segment and a lower segment;
wherein the inner spacer has a first selectivity to etch compositions used in predetermined fabrication operations for forming the lower segment and the inner spacer;
wherein the lower segment has the first selectivity to the etch compositions used in the predetermined fabrication operations for forming the lower segment and the inner spacer;
wherein the upper segment has a second selectivity to etch compositions used in the predetermined fabrication operations for forming the lower segment and the inner spacer; and
wherein the first etch selectivity is greater than the second etch selectivity such that the upper segment functions as a first mask in the predetermined fabrication operations for forming the lower segment.

US Pat. No. 10,658,492

POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a dielectric isolation structure disposed on a semiconductor substrate;
a passive device disposed entirely over the dielectric isolation structure, wherein the passive device is a device selected from the group consisting of a resistor and a fuse, the passive device including:
a polysilicon feature;
a dielectric sidewall spacer disposed along a sidewall of the polysilicon feature; and
a first electrode at least partially disposed within the polysilicon feature, wherein a first portion of the polysilicon feature is disposed on a first side of the first electrode and a second portion of the polysilicon feature is disposed on a second side of the of the first electrode, the first side of the first electrode opposing the second side of the first electrode, wherein the first portion of the polysilicon feature is disposed between the first side of the first electrode and the dielectric sidewall spacer; and
a first gate stack disposed over the semiconductor substrate, the first gate stack including a first gate electrode, wherein the first gate electrode of the first gate stack and the first electrode of the passive device are formed of the same material.

US Pat. No. 10,658,491

CONTROLLING PROFILES OF REPLACEMENT GATES

Taiwan Semiconductor Manu...

1. A method comprising:forming a dummy gate electrode layer over a semiconductor region;
forming a mask strip over the dummy gate electrode layer;
performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer, with a remaining portion of the upper portion of the dummy gate electrode layer forming an upper part of a dummy gate electrode;
forming a protection layer on sidewalls of the upper part of the dummy gate electrode;
performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, wherein the protection layer and the mask strip in combination are used as a second etching mask; and
replacing the dummy gate electrode and an underlying dummy gate dielectric with a replacement gate stack.

US Pat. No. 10,658,490

STRUCTURE AND FORMATION METHOD OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:a fin structure over a semiconductor substrate;
active gate stacks over covering a top and sidewalls of the fin structure, wherein each of the active gate stacks comprises a gate electrode with a first width;
a dummy gate stack over covering a top and sidewalls the fin structure, wherein the dummy gate stack is between the active gate stacks, wherein the dummy gate stack comprises a gate electrode with a second width that is equal to the first width;
a source or drain (S/D) structure in the fin structure;
a dielectric layer between the dummy gate stack and at least one of the active gate stacks;
spacer elements over sidewalls of the dummy gate stack and the active gate stacks;
a continuous capping layer separating the dielectric layer from the spacer element over the sidewall of the dummy gate stack and from the spacer element over the sidewall of the at least one of the active gate stacks; and
an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements, wherein the isolation feature extends into the fin structure from a bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure, wherein only one side of the isolation feature is in direct contact with the S/D structure, and wherein the isolation feature has two opposing sloped sidewalls that intersect each other in the fin structure.

US Pat. No. 10,658,489

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method of forming a semiconductor device, comprising:providing a substrate;
providing a gate structure on the substrate and a first protective layer on the gate structure;
forming an initial sidewall spacer on a sidewall of the gate structure and a sidewall of the first protective layer;
forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first sidewall spacer and the initial sidewall spacer being made of different materials;
forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer, wherein the second sidewall spacer has a top surface level with a top surface of the gate structure; and
forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material, wherein the same material has a lower etching selectivity and a weaker isolation performance than a material of the second sidewall spacer, and the second protective layer has a top surface level with a top surface of the first protective layer and a bottom surface level with the top surface of the gate structure.

US Pat. No. 10,658,488

ATOMIC LAYER DEPOSITION METHODS AND STRUCTURES THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate including a gate stack formed thereon, wherein the gate stack comprises:
a gate dielectric layer disposed over the substrate;
a treated work-function metal layer disposed over the gate dielectric layer, wherein the treated work-function layer includes a Cl-based precursor treated layer, and wherein the treated work-function layer has an oxide-free top surface; and
an ALD-deposited subsequent metal layer disposed over the oxide-free top surface of the treated work-function metal layer, wherein the ALD-deposited subsequent metal layer is substantially void-free.

US Pat. No. 10,658,487

SEMICONDUCTOR DEVICES HAVING RUTHENIUM PHOSPHORUS THIN FILMS

Intel Corporation, Santa...

1. A semiconductor device, comprising:one or more transistors with a gate having a gate stack including
a fin including a semiconductor substrate material,
a high-kappa dielectric material layer adjacent to and in contact with the fin,
a ruthenium-phosphorus (Ru—P) thin film adjacent to and conformally in contact with the high-kappa dielectric material layer, and
a single layer of gate material adjacent to and in contact with the Ru—P thin film, wherein the Ru—P thin film is to function as a diffusion barrier, a nucleation layer, a conductive liner, and an adhesion layer; and
electrical circuitry coupled to the one or more transistors.

US Pat. No. 10,658,486

MITIGATION OF TIME DEPENDENT DIELECTRIC BREAKDOWN

Taiwan Semiconductor Manu...

8. A structure, comprising:a substrate;
two opposing spacers on the substrate;
a first dielectric disposed over the substrate between the two opposing spacers;
a second dielectric conformally deposited between the two opposing spacers and over the first dielectric;
a multilayer gate metal stack conformally deposited over the second dielectric, wherein the multilayer gate metal stack comprises a first recess with side surfaces and a bottom surface between the side surfaces, wherein the side surfaces and the bottom surface expose a topmost layer of the multilayer gate metal stack;
a spacer layer disposed over the side surfaces of the first recess to form a second recess smaller than the first recess, wherein the spacer layer comprises a third dielectric; and
a metal deposited into the second recess.

US Pat. No. 10,658,485

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a plurality of fin structures extending in a first direction disposed on a semiconductor substrate, wherein a lower portion of the fin structures is embedded in a first insulating layer;
a first gate electrode structure and a second gate electrode structure extending in a second direction substantially perpendicular to the first direction disposed over the plurality of fin structures and the first insulating layer, wherein the first gate electrode structure and second gate electrode structure are spaced apart from each other and extend along a line in a same direction;
first and second insulating sidewall spacers arranged on opposing side surfaces of the first and second gate electrode structures, wherein each of the first and second insulating sidewall spacers contiguously extend along the second direction;
a second insulating layer disposed in a region between the first gate electrode structure and second gate electrode structure, wherein the second insulating layer separates the first gate electrode structure from the second gate electrode structure; and
a third insulating layer disposed in the region between the first gate electrode structure and the second gate electrode structure, wherein the third insulating layer is formed of a different material than the second insulating layer.

US Pat. No. 10,658,484

NON-PLANAR FIELD EFFECT TRANSISTOR DEVICES WITH WRAP-AROUND SOURCE/DRAIN CONTACTS

International Business Ma...

1. A semiconductor integrated circuit device, comprising:a non-planar field effect transistor (FET) device disposed on a semiconductor substrate, wherein the non-planar FET device comprises a semiconductor channel layer, and a gate structure in contact with at least an upper surface and sidewall surfaces of the semiconductor channel layer;
a first epitaxial source/drain layer disposed adjacent to a first side of the gate structure and in contact with a first end of the semiconductor channel layer exposed through a gate sidewall spacer of the gate structure;
a second epitaxial source/drain layer disposed adjacent to a second side of the gate structure, opposite the first side of the gate structure, and in contact with a second end of the semiconductor channel layer exposed through the gate sidewall spacer of the gate structure;
a first recess formed in an isolation layer below a bottom surface of the first epitaxial source/drain layer;
a second recess formed in the isolation layer below a bottom surface of the second epitaxial source/drain layer;
a first source/drain contact formed in contact with an upper surface, sidewalls surfaces, and the bottom surface of the first epitaxial source/drain layer, wherein the first source/drain contact comprises metallic material that is disposed within the first recess in the isolation layer to make contact with the bottom surface of the first epitaxial source/drain layer; and
a second source/drain contact formed in contact with an upper surface, sidewalls surfaces, and the bottom surface of the second epitaxial source/drain layer, wherein the second source/drain contact comprises metallic material that is disposed within the second recess in the isolation layer to make contact with the bottom surface of the second epitaxial source/drain layer.

US Pat. No. 10,658,483

NON-PLANAR FIELD EFFECT TRANSISTOR DEVICES WITH WRAP-AROUND SOURCE/DRAIN CONTACTS

International Business Ma...

1. A method for fabricating a semiconductor device, comprising:forming a non-planar field effect transistor (FET) device on a semiconductor substrate, wherein the non-planar FET device comprises a semiconductor channel layer, and a gate structure in contact with at least an upper surface and sidewall surfaces of the semiconductor channel layer;
forming a first epitaxial source/drain layer which is disposed adjacent to a first side of the gate structure and in contact with a first end of the semiconductor channel layer exposed through a gate sidewall spacer of the gate structure;
forming a second epitaxial source/drain layer which is disposed adjacent to a second side of the gate structure, opposite the first side of the gate structure, and in contact with a second end of the semiconductor channel layer exposed through the gate sidewall spacer of the gate structure;
forming a first recess in an isolation layer below a bottom surface of the first epitaxial source/drain layer;
forming a second recess in the isolation layer below a bottom surface of the second epitaxial source/drain layer; and
depositing a layer of metallic material to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second epitaxial source/drain layers, respectively.

US Pat. No. 10,658,482

PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

18. A semiconductor device comprising:a semiconductor substrate comprising a device region;
an isolation structure extending laterally in a closed path to demarcate the device region;
a first source/drain region and a second source/drain region disposed in the device region, wherein the first and second source/drain regions share a first doping type and are laterally spaced;
a selectively-conductive channel disposed in the device region and extending laterally from the first source/drain region to the second source/drain region;
a first gate region disposed in the device region, wherein the first gate region adjoins a first side of the selectively-conductive channel between the first and second source/drain regions; and
a polysilicon plate comprising a first doped region having the first doping type, a second doped region having a second doping type opposite the first doping type, and a third doped region having the first doping type, wherein the first doped region wraps around at least three sides of the first source/drain region, wherein the third doped region wraps around at least three sides of the second source/drain region, and wherein the second doped region wraps around at least three sides of the first gate region.

US Pat. No. 10,658,481

SELF-ALIGNED GATE CUT IN DIRECT STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR (VTFET)

International Business Ma...

1. A semiconductor structure, comprising:a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension;
a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension;
a second VTFET comprising a second self-aligned gate on the dielectric fin extension; and
a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.

US Pat. No. 10,658,480

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a plurality of electrode layers that are stacked in a first direction;
a semiconductor layer that intersects with the plurality of electrode layers and extends in the first direction;
a first insulating film that is provided between the semiconductor layer and at least one electrode layer among the plurality of electrode layers and extends along the semiconductor layer in the first direction;
a charge trapping film that is provided between the electrode layer and the first insulating film; and
a second insulating film that is provided between the charge trapping film and the first insulating film and is in contact with the first insulating film, wherein
in a flat band state, the charge trapping film has a first trap level located at a level deeper than a conduction band of the semiconductor layer and the second insulating film has a second trap level located at a level closer to the conduction band of the semiconductor layer than the first trap level, and
the charge trapping film includes a metal film.

US Pat. No. 10,658,479

FLASH MEMORY CELL STRUCTURE WITH STEP-SHAPED FLOATING GATE

Taiwan Semiconductor Manu...

1. A flash memory cell, comprising:a substrate;
a floating gate structure over the substrate, wherein the floating gate structure comprises:
a first portion having a first top surface and a first thickness;
a second portion having a second top surface and a second thickness that is different from the first thickness; and
a sidewall surface connecting the first and second top surfaces, Wherein a first angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle; and
a word line and an erase gate over the substrate and on opposite outer sidewalls of the floating gate structure,
a control gate structure over the first and second portions of the floating gate structure.

US Pat. No. 10,658,478

SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a composite gate structure formed over a semiconductor substrate, wherein the composite gate structure comprises:
a gate dielectric layer;
a metal layer disposed on the gate dielectric layer; and
a semiconductor layer disposed on the gate dielectric layer, wherein the metal layer surrounds the semiconductor layer.

US Pat. No. 10,658,477

JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET) HAVING SOURCE/DRAIN AND GATE ISOLATION REGIONS

Taiwan Semiconductor Manu...

11. A method comprising:forming an isolation region extending into a substrate;
forming a first source/drain region in the substrate;
forming a second source/drain region in the substrate;
forming a channel region in the substrate, the channel region extending from the first source/drain region to the second source/drain region;
defining a gate region in the substrate, the gate region contacting the first source/drain region at a first interface, the gate region isolated from the second source/drain region by the isolation region;
depositing a dielectric layer over the substrate; and
patterning the dielectric layer to expose a portion of the gate region and a portion the first source/drain region, wherein after patterning the dielectric layer, the dielectric layer covers the first interface.

US Pat. No. 10,658,476

SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN EPITAXIAL LAYER HAVING FACETS AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a fin structure disposed over a substrate, the fin structure including a channel layer and extending in a first direction;
a gate structure disposed over the fin structure and including a gate electrode layer and a gate dielectric layer;
sidewall spacers disposed on opposite sides of the gate structure; and
a source/drain structure including an epitaxial layer having at least seven facets, as interfaces between the epitaxial layer and the fin structure, in a cross section along the first direction.

US Pat. No. 10,658,475

TRANSISTORS WITH VERTICALLY OPPOSED SOURCE AND DRAIN METAL INTERCONNECT LAYERS

INTEL CORPORATION, Santa...

1. An integrated circuit, comprising:a device layer including a transistor, the transistor having a gate structure between a source region and a drain region;
a first interconnect layer above the device layer, the first interconnect layer comprising metal and connected to one of the source region or drain region of the transistor; and
a second interconnect layer below the device layer, the second interconnect layer comprising metal and connected to the other of the source region or drain region of the transistor.

US Pat. No. 10,658,474

METHOD FOR FORMING THIN SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor-on-insulator (SOI) substrate, the method comprising:epitaxially forming a device layer on a sacrificial substrate;
bonding the sacrificial substrate to a handle substrate, such that the device layer is between the sacrificial and handle substrates;
removing the sacrificial substrate; and
cyclically thinning the device layer until the device layer has a target thickness using multiple thinning cycles, wherein each of the multiple thinning cycles comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing, and wherein a first thinning cycle of the multiple thinning cycles removes a greater thickness of the device layer than a last thinning cycle of the multiple thinning cycles.

US Pat. No. 10,658,473

GATE CUT DEVICE FABRICATION WITH EXTENDED HEIGHT GATES

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first dielectric layer formed over a source and drain region;
a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface and an internal structure that is the result of a thermal oxidation process and has a higher quality than an internal structure of the first dielectric layer; and
a gate stack that passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.

US Pat. No. 10,658,472

DIRECT FORMATION OF HEXAGONAL BORON NITRIDE ON SILICON BASED DIELECTRICS

GlobalWafers Co., Ltd., ...

1. A method of forming a multilayer structure, the method comprising:contacting a front surface of a layer comprising silicon nitride with (i) a boron-containing gas or a boron-containing vapor and (ii) a nitrogen-containing gas or nitrogen-containing vapor at a temperature sufficient to directly deposit a layer comprising hexagonal boron nitride in interfacial contact with the front surface of the layer comprising silicon nitride to thereby prepare the multilayer structure comprising the layer comprising hexagonal boron nitride in interfacial contact with the layer comprising silicon nitride.

US Pat. No. 10,658,471

TRANSITION METAL DICHALCOGENIDES (TMDCS) OVER III-NITRIDE HETEROEPITAXIAL LAYERS

Intel Corporation, Santa...

1. A heteroepitaxial structure, comprising:a substrate layer comprising silicon;
a crystalline III-N material over the substrate layer, wherein the III-N material interfaces with the substrate layer at a bottom of a trench within an amorphous material that is over a portion of the substrate layer, and the III-N material extends laterally over the amorphous material; and
a layer comprising a transition metal dichalcogenide (TMDC) over the III-N material.

US Pat. No. 10,658,470

DEVICE WITH DOPED PHOSPHORENE AND METHOD FOR DOPING PHOSPHORENE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a black phosphorus (BP) layer over a substrate;
forming a dopant source layer over a source/drain region of the BP layer, wherein a channel region of the BP layer is free from coverage by the dopant source layer;
annealing the dopant source layer to drive a dopant from the dopant source layer into the BP layer; and
forming a conductive contact over the dopant source layer.

US Pat. No. 10,658,469

SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF NITRIDE SEMICONDUCTOR LAYERS

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a first nitride semiconductor layer formed on top of a substrate;
a second nitride semiconductor layer formed on top of the first nitride semiconductor layer;
a third nitride semiconductor layer formed on the second nitride semiconductor layer;
a trench penetrating the third nitride semiconductor layer to reach the second nitride semiconductor layer; and
a gate electrode disposed in the trench with a gate insulating film interposed therebetween,
wherein an electron affinity of the third nitride semiconductor layer is lower than an electron affinity of the second nitride semiconductor layer,
the electron affinity of the second nitride semiconductor layer is higher than an electron affinity of the first nitride semiconductor layer,
the gate insulating film is made of aluminum oxide formed on a bottom surface and a side wall of the trench and hafnium oxide formed on the aluminum oxide,
the second nitride semiconductor layer is GaN,
the aluminum oxide is thicker than the hafnium oxide,
a film thickness of the hafnium oxide is 3 nm or larger and 10 nm or smaller, and
a threshold potential is positive.

US Pat. No. 10,658,468

EPITAXIAL GROWTH METHODS AND STRUCTURES THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of semiconductor device fabrication, comprising:while a semiconductor wafer is loaded within a CVD reactor, performing a first baking process at a first pressure and first temperature;
after the first baking process, performing a second baking process at a second pressure and second temperature, wherein the second pressure is less than the first pressure; and
after the second baking process, flowing a precursor gas into the CVD reactor, while at a growth temperature, to deposit an epitaxial layer on the semiconductor wafer, wherein the growth temperature is greater than the first and second temperatures.