US Pat. No. 10,600,778

METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device comprising:receiving a substrate structure including a substrate, the substrate structure further including a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate, the substrate structure further including a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion;
applying a mask to the portion of the bottom spacer formed on the first bottom source/drain of the vertical transistor portion;
removing the portion of the bottom spacer formed on the second bottom source/drain of the varactor portion;
removing the mask from the portion of the bottom spacer formed on the first bottom source/drain of the vertical transistor portion; and
depositing a gate oxide on the vertical transistor portion and the varactor portion.

US Pat. No. 10,600,777

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising:a semiconductor body including a first semiconductor layer of a first conductivity type;
a first electrode provided on the semiconductor body;
a second electrode provided on the semiconductor body with a first insulating film interposed, the second electrode being provided at a position surrounded with the first electrode when viewed from above, and being separated from the first electrode;
a third electrode provided on the semiconductor body at a position surrounded with the second electrode when viewed from above, and being separated from the second electrode; and
a control electrode provided between the semiconductor body and the first electrode, the control electrode being electrically connected to the second electrode, the control electrode being electrically insulated from the semiconductor body with a second insulating film interposed, and being electrically insulated from the first electrode with a third insulating film interposed,
the semiconductor body further including a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, and a sixth semiconductor layer of the first conductivity type,
the second semiconductor layer being selectively provided between the first semiconductor layer and the first electrode,
the third semiconductor layer being selectively provided between the second semiconductor layer and the first electrode and electrically connected to the first electrode,
the fourth semiconductor layer including a major portion and an outer edge portion, the major portion being provided between the first semiconductor layer and the second electrode and between the first semiconductor layer and the third electrode, the outer edge portion being provided between the first semiconductor layer and the first electrode,
the fifth semiconductor layer being selectively provided in the fourth semiconductor layer, the fifth semiconductor layer being positioned between the outer edge portion of the fourth semiconductor layer and the first electrode, and including a portion electrically connected to the first electrode,
the sixth semiconductor layer being provided at a position away from the fifth semiconductor layer in the fourth semiconductor layer, the sixth semiconductor layer being positioned between the major portion of the fourth semiconductor layer and the third electrode, and including a portion electrically connected to the third electrode,
the control electrode being disposed at a position capable of facing the first semiconductor layer, the second semiconductor layer and the third semiconductor layer with the second insulating film interposed.

US Pat. No. 10,600,776

DEVICE AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:a first bipolar device connected to a first node;
a second bipolar device connected to the first bipolar device and to a second node; and
a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes, wherein the first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure, wherein the deep well structure comprises a deep N-well layer that is formed on top of a substrate layer and below an N-well, and wherein the N-well is in contact with the deep N-well layer and in contact with the substrate layer.

US Pat. No. 10,600,775

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Macronix International Co...

1. An electrostatic discharge protection device comprising:a semiconductor substrate;
a first N-type doped well and a second N-type doped well on the substrate, each of the first N-type doped well and the second N-type doped well comprising a first N+ region and a first P+ region;
a P-type doped well between the first N-type doped well and the second N-typed doped well on the substrate, the P-type doped well comprising a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and
a first contact and a second contact positioned above a surface of the first N-type doped well and above a surface of the second N-type doped well, respectively, between the first N+ region and the first P+ region;
a poly resistor connected between the first N-type doped well and the second N-typed doped well.

US Pat. No. 10,600,774

SYSTEMS AND METHODS FOR FABRICATION OF GATED DIODES WITH SELECTIVE EPITAXIAL GROWTH

QUALCOMM Incorporated, S...

1. An integrated circuit (IC) comprising:a logic region comprising at least one Field-Effect Transistor (FET), the at least one FET comprising a plurality of FET fins, each of the plurality of FET fins comprising a respective FET fin epitaxial bump; and
an input/output (I/O) region comprising at least one I/O gated diode, the at least one I/O gated diode comprising a plurality of diode fins, wherein at least one of the plurality of diode fins comprises a source and a drain, and wherein at least one of the source and the drain does not comprise an epitaxial bump.

US Pat. No. 10,600,773

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device manufacturing method comprising:forming a chip stacked body by stacking a second semiconductor chip on a first surface of a first semiconductor chip, a first bump electrode being between and contacting the first surface and the second semiconductor chip, and stacking a third semiconductor chip on the second semiconductor chip, a second bump electrode being between and contacting the second semiconductor chip and the third semiconductor chip;
stacking a fourth semiconductor chip on the chip stacked body;
connecting the first bump electrode to a first through silicon via of the second semiconductor chip by reflowing the first bump electrode;
connecting the second bump electrode to the first through silicon via of the second semiconductor chip and a second through silicon via of the third semiconductor chip by reflowing the second bump electrode;
connecting the chip stacked body to a first substrate by using a first adhesive such that the first surface of the first semiconductor chip faces a second surface of the first substrate;
connecting the chip stacked body to a second substrate by using a second adhesive and a third bump electrode, the second adhesive being provided between the chip stacked body and the second substrate, in a direction perpendicular to the second substrate, and between the third bump electrode and the fourth semiconductor chip in a direction parallel to the second substrate, such that a gap is left between the chip stacked body and the second substrate and between the fourth semiconductor chip and the second substrate; and
after connecting the chip stacked body to the second substrate by using the second adhesive and the third bump electrode, sealing the second surface, the first, second, third, and fourth semiconductor chips with a resin that also enters the gap left between the chip stacked body and the second substrate and between the fourth semiconductor chip and the second substrate.

US Pat. No. 10,600,772

SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Micron Technology, Inc., ...

1. An apparatus comprising:a first semiconductor chip comprising:
a first plurality of memory cell arrays, each disposed on an associated one of intersections of first and second signal lines;
a first plurality of bonding electrodes electrically connected respectively to corresponding first signal lines; and
a first plurality of switches configured to respectively couple one of the second signal lines to a corresponding one of the first plurality of bonding electrodes; and
a second semiconductor chip comprising:
a second plurality of memory cell arrays, each disposed on an associated one of intersections of third and fourth signal lines;
a second plurality of bonding electrodes respectively coupled to the first plurality of bonding electrodes of the first semiconductor chip and electrically connected respectively to corresponding third signal lines;
a third plurality of bonding electrodes electrically connected respectively to corresponding third signal lines and coupled to a logic chip; and
a second plurality of switches configured to respectively couple one of the fourth signal lines to a corresponding one of the second and third plurality of bonding electrodes;
wherein the first and second plurality of switches are configured to turn on/off so that one memory cell array of the first semiconductor chip and the second semiconductor chip is accessed through a corresponding one of the third plurality of bonding electrodes to the logic chip.

US Pat. No. 10,600,771

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first interconnection including a first extending portion that extends in a first direction, and a first curved portion that is curved with respect to the first extending portion;
a second interconnection including a second extending portion that extends in the first direction and is adjacent to the first extending portion in a second direction perpendicular to the first direction, and a second curved portion that is curved with respect to the second extending portion;
a first plug provided on the first curved portion, or provided on a first non-opposite portion that is included in the first extending portion and is not opposite to the second extending portion in the second direction; and
a second plug provided on the second curved portion, or provided on a second non-opposite portion that is included in the second extending portion and is not opposite to the first extending portion in the second direction.

US Pat. No. 10,600,770

SEMICONDUCTOR DICE ASSEMBLIES, PACKAGES AND SYSTEMS, AND METHODS OF OPERATION

Micron Technology, Inc., ...

1. An assembly, comprising:an interposer comprising a glass material;
a semiconductor die comprising a logic die having a proximity coupling on a side of the interposer; and
at least one other semiconductor die comprising a proximity coupling configured for
communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer, the at least one other die comprising a number of stacked memory dice, each of the logic die and the memory dice comprising a proximity coupling for mutual signal communication;
wherein:
the logic die is in electrically conductive communication with conductive traces of the interposer for communicating power and ground/bias;
the number of stacked memory dice comprises memory dice stacked in stair-step fashion with exposed bond pads on treads of stairs; and
further comprising wire bonds respectively extending from the exposed bond pads to conductive traces of the interposer for communicating power and ground/bias; and
the interposer comprises an optical waveguide for signal communication with an optical I/O of the logic die and extends to a socket for optical signal communication with higher level packaging.

US Pat. No. 10,600,769

ELECTRONIC COMPONENT

AIROHA TECHNOLOGY GROUP, ...

1. An electronic component, comprising:a substrate comprising a metal layer and at least one via connecting with the metal layer;
an III-V die disposed on the metal layer; and
a silicon die stacked to the III-V die, the silicon die comprises a plurality of conductive contacts on an active surface of the silicon die, and the silicon die is coupled to the III-V die in a face-down orientation and electrically connected to the III-V die via the conductive contacts,
wherein the active surface of the silicon die faces toward the substrate.

US Pat. No. 10,600,768

LIGHT EMITTING DEVICE WITH LED STACK FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME

Seoul Viosys Co., Ltd., ...

1. A light emitting device for a display, comprising:a first substrate;
a first LED sub-unit disposed under the first substrate;
a second LED sub-unit disposed under the first LED sub-unit;
a third LED sub-unit disposed under the second LED sub-unit;
a first transparent electrode interposed between the first and second LED sub-units, and in ohmic contact with a lower surface of the first LED sub-unit;
a second transparent electrode interposed between the second and third LED sub-units, and in ohmic contact with a lower surface of the second LED sub-unit;
a third transparent electrode interposed between the second transparent electrode and the third LED sub-unit, and in ohmic contact with an upper surface of the third LED sub-unit;
at least one current spreader connected to at least one of the first, second, and third LED sub-units;
electrode pads disposed on the first substrate; and
through-hole vias formed through the first substrate to electrically connect the electrode pads to the first, second, and third LED sub-units,
wherein at least one of the through-hole vias is formed through the first substrate, the first LED sub-unit, and the second LED sub-unit.

US Pat. No. 10,600,767

MAKING SEMICONDUCTOR DEVICES BY STACKING STRATA OF MICRO LEDS

Hong Kong Beida Jade Bird...

1. A method for fabricating a micro-LED display chip, comprising:providing a substrate supporting an array of pixel drivers; and
fabricating two or more strata stacked on top of the substrate and pixel drivers, with a planar interface between adjacent strata, by:
for a bottom stratum: bonding, using metal layers, an unpatterned epitaxial structure on top of the substrate and pixel drivers; and for any other stratum: bonding, using metal layers, an unpatterned epitaxial structure on top of a previous stratum;
patterning the epitaxial structure to form micro LEDs and patterning the bonding metal layers to form metal pads, some of the metal pads functioning as lower contact metal pads electrically connected to bottoms of the micro LEDs;
for all strata except a top stratum, filling and planarizing the stratum to create a planar top interface, the top interface including electrical connections to tops of the micro LEDs;
filling and planarizing the top stratum to create a planar top interface, the planar top interface including electrical connections to tops of the micro LEDs; and
fabricating a common electrode on top of the planar top interface of the top stratum, the tops of the micro LEDs electrically connected to the common electrode, wherein the common electrode is further electrically connected to one or more of the metal pads of the bottom stratum.

US Pat. No. 10,600,766

DUAL-CHANNEL HEAT-CONDUCTING ENCAPSULATION STRUCTURE AND ENCAPSULATION METHOD OF A SOLID-STATE PHOSPHOR INTEGRATED LIGHT SOURCE

FUJIAN CAS-CERAMIC OPTOEL...

1. A solid-state phosphor integrated light source, comprising a solid-state phosphor, a transparent organic silica gel, a plurality of LED chips, a plurality of heat-conducting columns, and a substrate,wherein each of the plurality of heat-conducting columns has a first end in contact with the solid-state phosphor and a second end in contact with the substrate so as to form a pap between the solid-state phosphor and the substrate, wherein the plurality of LED chips are disposed on the substrate inside the gap, the transparent organic silica gel fills a space in the gap, and
wherein each of the plurality of heat-conducting columns is located in an interspace between two or more of the plurality of LED chips.

US Pat. No. 10,600,765

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a plurality of semiconductor chips provided on a circuit pattern within a case defined by an outer frame in a plan view, said case having a longer side extending along a longer-side direction and a shorter side that is shorter than said longer side and extends along a shorter-side direction that is transverse to the longer-side direction and within the same plane as the longer-side direction;
bonding wires for electrically connecting said plurality of semiconductor chips and said circuit pattern together;
a plurality of main electrodes provided within said case and disposed to extend along the longer-side direction of said case; and
two complex elements, each of said complex elements including two of said plurality of semiconductor chips connected to each other,
wherein one of said two complex elements is configured such that said two of said plurality of semiconductor chips are connected by a plurality of the bonding wires via a via-circuit pattern provided on a place interposed between said two of said plurality of semiconductor chips in a plan view, and
wherein another one of said two complex elements is configured such that said two of said plurality of semiconductor chips of said another one of said two complex elements are connected directly by another plurality of the bonding wires,
wherein each said main electrode is disposed proximate to an edge of said longer side extending in the longer-side direction of said case and spaced away from said complex elements at a location between said edge of said longer side and said complex elements,
wherein said plurality of semiconductor chips are arranged along the longer-side direction of said case,
wherein said bonding wires are strung along the longer-side direction of said case,
wherein each said main electrode is disposed in a vicinity of one of sides extending in the longer-side direction of said case,
wherein each said main electrode and said circuit pattern are connected together by ultra-sonic bonding, soldering, or brazing,
wherein said case has a recessed portion on a top surface of said case, and
wherein each said main electrode has an edge extended from said recessed portion and bent at a bend location of said main electrode such that said edge extends from said bend location to a free end of said edge in an inward direction of said case toward said circuit pattern in a plan view in said recessed portion, and said free end of said edge overlaps said circuit pattern and said bend location is proximate to said longer side of said case.

US Pat. No. 10,600,764

SEMICONDUCTOR POWER MODULE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor power module comprising:an insulating substrate having one surface and another surface;
an output side terminal arranged at a one surface side of the insulating substrate;
a first power supply terminal arranged at the one surface side of the insulating substrate;
a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at an other surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate;
a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal; and
a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal;
wherein a direction of a current flowing through the first power supply terminal and a direction of a current flowing through the second power supply terminal are made opposite across the insulating substrate.

US Pat. No. 10,600,763

MULTI-DECK THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Yangtze Memory Technologi...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a first substrate;
forming a first channel structure extending vertically through the first dielectric deck;
forming a heterogeneous interface in a second substrate;
bonding the second substrate and the first substrate in a face-to-face manner;
splitting a single-crystal silicon layer from the second substrate along the heterogeneous interface in the second substrate to leave the single-crystal silicon layer bonded on the first dielectric deck;
patterning a first inter-deck plug comprising single-crystal silicon in the single-crystal silicon layer, such that the first inter-deck plug is above and in contact with the first channel structure;
forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers above the first inter-deck plug;
forming a second channel structure extending vertically through the second dielectric deck, such that the second channel structure is above and in contact with the first inter-deck plug; and
forming a first memory deck and a second memory deck each comprising interleaved conductor layers and the dielectric layers by replacing the sacrificial layers in the first dielectric deck and the second dielectric deck with the conductor layers.

US Pat. No. 10,600,762

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus comprising a first die and a second die, each of the first and second dies including a face-side and a back-side, the face-side of the first die being defined by first and second edges substantially parallel to each other, and the face-side of the second die being defined by third and fourth edges substantially parallel to each other;wherein the first die comprises, on the face-side thereof:
at least one first interconnection region between the first and second edges;
at least one first probe pad between the at least one first interconnection region and the first edge at a position that is closer to the at least one first interconnection region than the first edge;
at least one first coupling region between the at least one first interconnection region and the second edge; and
at least one first redistribution wiring including a first portion electrically coupling the at least one first interconnection region to the at least one first probe pad and a second portion electrically coupling the at least one first interconnection region to the at least one first coupling region;
wherein the second die comprises, on the face-side thereof:
at least one second interconnection region between the third and fourth edges;
at least one second probe pad between the at least one second interconnection region and the fourth side edge at a position that is closer to the at least one second interconnection region than the fourth edge;
at least one second coupling region between the at least one second interconnection region and the at least one second probe pad; and
at least one second redistribution wiring including a third portion electrically coupling the at least one second interconnection region to the at least one second coupling region and a fourth portion electrically coupling the at least one coupling region to the at least one second probe pad;
wherein a distance between the at least one first interconnection region and the at least one first probe pad is substantially equal to a distance between the at least one second interconnection region and the at least one second probe pad; and
wherein the first die is bonded to the second die in a face-to-face relationship such that the at least one first interconnection region and the at least one second interconnection region are between the at least one first probe pad and the at least one second probe pad, and the at least one first coupling region is electrically coupled to the at least one second coupling region.

US Pat. No. 10,600,761

NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;
removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;
filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;
joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;
removing the substrate from the second surface of the insulating layer;
joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer; and
forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors, wherein the plurality of nanoscale conductors are arranged without regard to a specific alignment of the plurality of nanoscale conductors to either the plurality of first element contacts or the plurality of second element contacts.

US Pat. No. 10,600,760

ULTRATHIN LAYER FOR FORMING A CAPACITIVE INTERFACE BETWEEN JOINED INTEGRATED CIRCUIT COMPONENT

Invensas Corporation, Sa...

1. A wafer-level package, comprising:first and second integrated circuit dies, each integrated circuit die
interfacing a single ultrathin layer of a first dielectric material between respective bonding surfaces of the first and second integrated circuit dies, each respective bonding surface partly comprising respective second dielectric layers of a second dielectric material;
each integrated circuit die comprising at least one conductive pad recessed from each respective bonding surface, wherein the respective conductive pads of the first and second integrated circuit dies are on opposing sides of the single ultrathin layer of the first dielectric material;
an instance of a third layer of a third dielectric material between each recessed conductive pad and each respective bonding surface of the first and second integrated circuit dies, each instance of the third layer of the third dielectric material filling-in respective recesses between the respective recessed conductive pads and the respective bonding surfaces;
a total thickness of the single ultrathin layer of the first dielectric material and two respective instances of the third layer of the third dielectric material being 25 nanometers or less, wherein the total thickness also comprises a distance between the respective recessed conductive pads on opposing sides of the single ultrathin layer;
a capacitive interface comprising the single ultrathin layer of the first dielectric material, the two respective instances of the third layer of the third dielectric material in the respective recesses, and the respective recessed conductive pads of the first and second integrated circuit dies;
a conductive power connection between the first and second integrated circuit dies, the conductive power connection disposed only through the second layer of the second dielectric material and through the single ultrathin layer of the first dielectric material; and
a conductive ground connection between the first and second integrated circuit dies, the conductive ground connection disposed only through the second layer of the second dielectric material and through the single ultrathin layer of the first dielectric material.

US Pat. No. 10,600,759

POWER AND GROUND DESIGN FOR THROUGH-SILICON VIA STRUCTURE

ADVANCED SEMICONDUCTOR EN...

11. A semiconductor package, comprising:a first substrate;
a semiconductor device on the first substrate and comprising:
a second substrate including a first surface and a second surface opposite the first surface;
active circuitry on the first surface of the second substrate;
a first conductive layer extending from the second surface of the second substrate toward the active circuitry and electrically connected to the active circuitry and defining a space in the semiconductor device; and
an encapsulation layer in the space defined in the semiconductor device,
wherein the active circuitry comprises a second conductive layer and a first dielectric layer, wherein the second conductive layer comprises a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer.

US Pat. No. 10,600,758

SEMICONDUCTOR SENSOR PACKAGE

STMICROELECTRONICS PTE LT...

1. A method, comprising: forming a plurality of through holes in a substrate, the substrate including a first surface and a second surface;forming a plurality of first trenches in the first surface of the substrate, each first trench of the plurality of first trenches being substantially parallel to each other, each first trench of the plurality of first trenches is overlapping and aligned with a number of through holes of the plurality of through holes;
forming a plurality of second trenches in the first surface of the substrate, each second trench of the plurality of second trenches being transverse to the plurality of first trenches and overlapping at least one of the through holes of the plurality of through holes; and
forming a non-conductive material in the plurality of through holes, the plurality of first trenches, and the plurality of second trenches.

US Pat. No. 10,600,757

SEMICONDUCTOR PACKAGE

Chengwei Wu, New Taipei ...

1. A semiconductor package, comprising:a first die, the first die having an active surface and a back surface, the first die comprising a first connection end and a second connection end on the active surface, the first connection end being closer to a side edge of the first die than the second connection end;
a second die, the second die having an active side and a back side, the second die comprising a third connection end and a fourth connection end on the active surface, the fourth connection end being closer to a side edge of the second die than the third connection end;
a first set of metal pillars;
a second set of metal pillars;
a first redistribution structure, the first redistribution structure comprising at least two insulating layers, a first trace, and a second trace, the first die being connected to the first redistribution structure through the first set of metal pillars, the second die being connected to the first redistribution structure through the second set of metal pillars, the first trace being connected between the first connection end and the third connection end, the second trace being connected between the second connection end and the fourth connection end; and
a first molding material, wherein the first molding material is beside the first die and the second die.

US Pat. No. 10,600,756

WIRE BONDING TECHNIQUE FOR INTEGRATED CIRCUIT BOARD CONNECTIONS

United States of America,...

1. A method for connecting a chip die to a circuit board with a capillary dispenser to deposit gold, said dispenser forming a free air ball (FAB) at a depositing tip, said method comprising:forming a first bond by depositing the gold at the FAB from the tip to a board pad on the circuit board;
forming a second bond by depositing the gold at the FAB from the tip to a die pad on the chip die;
extruding a filament of the gold by the tip in a normal direction from said second bond;
rotating said filament laterally away from said first bond along a first radius;
extruding said filament while rotating said filament towards said first bond along a second radius; and
forming a third bond by depositing the gold at the FAB by the tip on said first bond to form said third bond.

US Pat. No. 10,600,755

METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY

Amkor Technology, Inc., ...

11. A method of manufacturing an electronic device, the method comprising:providing a substrate comprising a substrate conductive interconnection structure;
providing a semiconductor die comprising a die conductive interconnection structure protruding from a first side of the die; and
pressing a first surface of the die conductive interconnection structure and a first surface of the substrate conductive interconnection structure together with an interface layer comprising at least one layer of ink at an interface between the first surface of the die conductive interconnection structure and the first surface of the substrate conductive interconnection structure,
wherein after said pressing, the interface layer has a substantially consistent thickness,
wherein said pressing comprises performing said pressing utilizing a thermocompression bonding process.

US Pat. No. 10,600,754

BONDING METHOD

KAIJO CORPORATION, Tokyo...

1. A bonding method using a bonding apparatus including a rotation drive mechanism for rotating a bonding stage about a ?-axis, the method comprising the steps of:(e) locking said bonding stage with respect to said ?-axis, and bonding a wire or bump onto a certain area of a substrate held on said bonding stage;
(f) unlocking the bonding stage with respect to said ?-axis, and rotating said bonding stage about said ?-axis with said rotation drive mechanism; and
(g) locking said bonding stage with respect to said ?-axis, and bonding a wire or bump onto a remaining region of said substrate.

US Pat. No. 10,600,753

FLIP CHIP BACKSIDE MECHANICAL DIE GROUNDING TECHNIQUES

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) package comprising:a semiconductor die including a first side and a second side opposite the first side, the first side including active circuitry;
a sheet attached to the second side, the sheet including a tip that electrically connects with the second side; and
a lid attached to a substrate, and contacting the sheet;
wherein the tip includes two parallel surfaces, and wherein each of the two parallel surfaces forms an acute angle with respect to a plane along a surface of the sheet, and wherein the tip extends from an edge of a hole in the sheet.

US Pat. No. 10,600,752

RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ABLIC Inc., (JP)

1. A method of manufacturing a resin-encapsulated semiconductor device,the resin-encapsulated semiconductor device including:
a resin encapsulation body having a first surface and a second surface that is opposite to the first surface;
a semiconductor chip embedded in the resin encapsulation body; and
an external terminal formed on an element surface of the semiconductor chip, and embedded in the resin encapsulation body,
the method comprising:
preparing a substrate having a first main surface and a second main surface that is opposite to the first main surface;
forming a conductive layer on the first main surface;
forming the external terminal by connecting a bump electrode formed on the semiconductor chip to the conductive layer;
forming the resin encapsulation body on the first main surface by covering the external terminal and the semiconductor chip with resin;
exposing a surface of the semiconductor chip that is opposite to the element surface by grinding the resin encapsulation body and the semiconductor chip from a surface of the resin encapsulation body that is opposite to a surface thereof in contact with the first main surface;
forming a metal layer on the exposed surface of the semiconductor chip;
exposing the external terminal and the first surface of the resin encapsulation body; and
performing singulation by cutting the resin encapsulation body between adjacent semiconductor chips to obtain the resin-encapsulated semiconductor device.

US Pat. No. 10,600,751

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A pillar-type connection comprising:a first conductive layer that includes a hollow core;
a second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core; and
a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,600,750

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

11. A semiconductor die, comprising:a substrate;
a contact exposed at a surface of the substrate;
an interconnect structure electrically coupled to the contact, wherein the interconnect structure includes a top surface having a first portion over the contact and a second portion laterally offset from the contact; and
a solder material disposed at least partially on the second portion of the top surface of the interconnect structure.

US Pat. No. 10,600,749

CONTACT HOLE STRUCTURE AND FABRICATING METHOD OF CONTACT HOLE AND FUSE HOLE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor structure, comprising:providing a dielectric layer having a conductive pad and a fuse formed therein, wherein the dielectric layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer;
forming a first mask covering the dielectric layer and having a first opening directly over the conductive pad;
performing a first removing process using the first mask as a mask to remove a portion of the dielectric layer to form a first trench, wherein the conductive pad is directly under the first trench and is not exposed from the first trench;
removing the first mask;
forming a second mask covering the dielectric layer and having a second opening exposing the first trench and a third opening directly over the fuse; and
performing a second removing process using the second mask as a mask to remove the dielectric layer directly under the first trench and the dielectric layer directly over the fuse thereby forming a contact hole and a fuse hole respectively, wherein the conductive pad is exposed from the contact hole.

US Pat. No. 10,600,748

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;
a second interconnection member disposed on a portion of the encapsulant and on the active surface of the semiconductor chip;
a first passivation layer disposed on the second interconnection member,
wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip,
the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and
the first passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member,
wherein the first passivation layer is an outermost insulating layer of the fan-out semiconductor package.

US Pat. No. 10,600,747

VERTICAL CAPACITORS FOR MICROELECTRONICS

Invensas Corporation, Sa...

1. An apparatus, comprising:a capacitor layer to underlie a semiconductor chip, a die, or an integrated circuit;
vertical capacitor plates in the capacitor layer interleaved with vertical dielectric layers;
electrodes of each vertical capacitor plate at a top surface and a bottom surface of the capacitor layer; and
power pass-throughs or ground pass-throughs on the top surface and the bottom surface of the capacitor layer.

US Pat. No. 10,600,746

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING GAPS AND/OR ISOLATION STRUCTURES BETWEEN GROUPS OF UNIT CELL TRANSISTORS

Cree, Inc., Durham, NC (...

1. A multi-cell transistor, comprising:a semiconductor structure; and
a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure,
wherein the unit cell transistors are spaced apart from each other along a second direction and arranged in a plurality of groups, wherein a first distance in the second direction between two adjacent unit cell transistors in a first of the groups is less than a second distance in the second direction between a first unit cell transistor that is at one end of the first of the groups and a second unit cell transistor that is in a second of the groups, where the second unit cell transistor is adjacent the first unit cell transistor,
wherein the multi-cell transistor further comprises a metal isolation structure that extends above the semiconductor structure in the first direction between the first of the groups and the second of the groups, and
wherein the metal isolation structure is electrically connected to source regions of the unit cell transistors.

US Pat. No. 10,600,745

COMPENSATING FOR MEMORY INPUT CAPACITANCE

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
an access line comprising a first portion in contact with the substrate and a second portion;
a memory die coupled with the substrate via the second portion of the access line;
a memory controller coupled with the access line and configured to transmit, through the access line to the memory die, a signal having an amplitude level and modulated with a modulation scheme having at least two levels; and
an inductive region coupled with the access line and configured to change a first noise level associated with the amplitude level of the signal to a second noise level based at least in part on altering a capacitance of the access line.

US Pat. No. 10,600,744

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a lead frame;
a transistor including a plurality of drain electrode pads, a plurality of source electrode pads, and a gate electrode pad on one surface, the plurality of drain electrode pads, the plurality of source electrode pads, and the gate electrode pad facing a front surface of the lead frame and being connected to the lead frame; and
an encapsulation resin that has a rectangular-plate shape and encapsulates the transistor and the lead frame so that a part of the lead frame is exposed from a back surface of the encapsulation resin, wherein
the lead frame includes a drain frame electrically connected to the plurality of drain electrode pads, a source frame electrically connected to the plurality of source electrode pads, and a gate frame electrically connected to the gate electrode pad,
the drain frame includes a plurality of drain frame fingers,
the plurality of drain frame fingers are spaced apart from each other in a first direction, extended in a second direction that is orthogonal to the first direction in a plan view, and each one of the plurality of the drain frame fingers is connected to a respective one of the plurality of drain electrode pads,
the source frame includes a plurality of source frame fingers,
the plurality of source frame fingers are spaced apart from each other in the first direction, extended in the second direction, and each one of the plurality of the source frame fingers is connected to a respective one of the plurality of source electrode pads,
each one of the plurality of the drain frame fingers and each one of the plurality of the source frame fingers are alternately arranged in the first direction and overlap each other as viewed in the first direction,
in a region where the plurality of drain frame fingers and the plurality of source frame fingers overlap one another as viewed in the first direction, at least either one of the plurality of drain frame fingers and the plurality of source frame fingers are not exposed from the back surface of the encapsulation resin, and
in the region where the plurality of drain frame fingers and the plurality of source frame fingers overlap one another as viewed in the first direction, either one of the plurality of drain frame fingers and the plurality of source frame fingers are exposed from the back surface of the encapsulation resin, and the other one of the plurality of drain frame fingers and the plurality of source frame fingers are not exposed from the back surface of the encapsulation resin.

US Pat. No. 10,600,743

ULTRA-THIN THERMALLY ENHANCED ELECTRO-MAGNETIC INTERFERENCE SHIELD PACKAGE

Inari Semiconductor Labs ...

1. A method of fabricating an electronic package, comprising the steps of:connecting a plurality of semiconductor chips to at least one surface of a substrate using a connect pad;
encapsulating the semiconductor chips with a non-conductive material by a first molding process;
reducing a thickness of the semiconductor chips by a process of trimming or grinding from a top encapsulation layer of the semiconductor chips to form thin semiconductor chips; and
forming an electro-magnetic interference shield layer over the thin semiconductor chips by a second molding process.

US Pat. No. 10,600,742

CHIP WITH CIRCUIT FOR DETECTING AN ATTACK ON THE CHIP

Infineon Technologies AG,...

1. A chip, comprising:a substrate region having a substrate contact;
an RS latch having two complementary nodes representing a storage state of the RS latch;
a control circuit comprising a control input connected directly to the substrate contact and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input; and
an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

US Pat. No. 10,600,741

SEMICONDUCTOR PACKAGE WITH PLATED METAL SHIELDING AND A METHOD THEREOF

Utac Headquarters PTE. LT...

1. A method of manufacturing semiconductor devices, comprising:obtaining a molded array that includes a package side and an interfacing side, wherein the molded array includes a plurality of dies coupled to a substrate and molding compound encapsulating the plurality of dies, wherein surfaces of the molding compound has have a natural surface roughness;
coupling the interfacing side of the molded array with a tape;
performing a cut through procedure from the package side to the interfacing side, thereby forming a plurality of singulated semiconductor devices on the tape;
performing an abrasion procedure to roughen all surfaces of the molding compound such that, after the abrasion procedure, all surfaces of the molding compound have an unnatural surface roughness that is rougher than the natural surface roughness, wherein the abrasion procedure comprises:
i. coating all exposed surfaces of the molding compound with an adhesion promoter material;
ii. heating the molded array with the adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film; and
iii. etching away the baked film, resulting in the molding compound having the roughened surfaces;
adhering a metal layer on the roughened surfaces; and
removing the plurality of singulated semiconductor devices from the tape.

US Pat. No. 10,600,740

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH EPITAXIAL LAYERS AND AN ALIGNMENT MARK

Infineon Technologies Aus...

1. A semiconductor substrate, comprising:an alignment mark contained within in a kerf region of a semiconductor wafer or in an inactive region of a semiconductor die, the alignment mark comprising a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m in a process surface of a semiconductor layer, and at least one fin within the groove at a distance of at least 60 ?m to a closest inner corner of the groove.

US Pat. No. 10,600,739

INTERPOSER WITH INTERCONNECTS AND METHODS OF MANUFACTURING THE SAME

HRL Laboratories, LLC, M...

1. An interposer, comprising:an interposer substrate comprising a plurality of vias, the interposer substrate having a first surface and a second surface opposite the first surface; and
a plurality of metallic interconnects in the plurality of vias,
wherein the interposer substrate comprises a dielectric material,
wherein a first pitch of the plurality of vias at a first end of the plurality of vias is different than a second pitch of the plurality of vias at a second end of the plurality of vias,
wherein the plurality of metallic interconnects are slanted at angles relative to the first surface of the interposer substrate,
wherein the angles at which the plurality of metallic interconnects are slanted relative to the first surface of the interposer substrate varies between the plurality of metallic interconnects, and
wherein the angle of at least one metallic interconnect of the plurality of metallic interconnects varies non-uniformly.

US Pat. No. 10,600,738

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
an insulating film formed to cover the semiconductor substrate;
a first electric conductor formed on the insulating film;
a second electric conductor formed on the insulating film at a distance from the first electric conductor;
an embedded body formed to fill space between the first electric conductor and the second electric conductor;
a protective film formed to cover the first electric conductor, the second electric conductor and the embedded body;
a solder layer formed to cover the protective film; and
a glass coating film covering an upper surface of each of the first electric conductor and the second electric conductor,
a position of an upper surface of the embedded body being matched to a position of an upper surface of the glass coating film, and
the first electrical conductor is electrically isolated from the second electrical conductor.

US Pat. No. 10,600,737

PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A process, comprising:forming an opening in a porous material dielectric region, said opening having a side wall and a bottom wall;
depositing a non-porous dielectric barrier on said side wall and said bottom wall;
performing an anisotropic etch to completely remove a portion of the non-porous dielectric barrier along the bottom wall, wherein performing the anisotropic etch comprises performing a plasma etch; and
filling the opening with metal material to form an electrically conductive element that is laterally separated from an upper portion of the porous material dielectric region by the non-porous dielectric barrier along the side wall but is in contact with a lower portion of the porous material dielectric region along the bottom wall.

US Pat. No. 10,600,736

SEMICONDUCTOR BACKMETAL (BM) AND OVER PAD METALLIZATION (OPM) STRUCTURES AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device, comprising:a semiconductor layer having a first side and a second side opposite the first side;
one or more electrically conductive pads coupled at the second side;
one or more electrically insulative layers coupled at the second side and having one or more openings providing access to the one or more electrically conductive pads;
an electrically conductive layer coupled on the first side of the semiconductor layer;
one or more backmetal (BM) layers coupled on the electrically conductive layer;
one or more over-pad metallization (OPM) layers coupled over the one or more electrically conductive pads, the one or more OPM layers comprising a nickel layer, and;
a diffusion barrier layer coupled over the one or more OPM layers;
wherein the semiconductor device comprises one of an insulated gate bipolar transistor (IGBT) or a diode;
wherein a perimeter of each of the one or more OPM layers is entirely within a perimeter of each of the one or more electrically conductive pads; and
wherein a largest planar surface of the electrically conductive layer and a side surface of the electrically conductive layer substantially perpendicular to the largest planar surface of the electrically conductive layer are both directly coupled to the semiconductor layer.

US Pat. No. 10,600,735

3D CHIP SHARING DATA BUS

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate; and
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, wherein at least one particular second-set interconnect layer comprises a plurality of interconnect segments that form a data bus for supplying data signals to the first IC die.

US Pat. No. 10,600,734

TRANSISTOR STRUCTURE IN LOW NOISE AMPLIFIER

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first gate line and a second gate line extending along a first direction;
a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line;
a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line; and
first contact plugs on the first gate line; and
a first doped region between the first gate line and the third gate line, a second doped region between the second gate line and the fourth gate line, and a third doped region between the third gate line and the fourth gate line, wherein the first doped region and the second doped region comprise same conductive type, the first doped region and the third doped region comprise different conductive type, wherein a first edge of the third doped region is merged in plan view with an edge of the third gate line and a second edge of the third doped region is merged in plan view with an edge of the fourth gate line.

US Pat. No. 10,600,721

HEAT EXCHANGER FOR DUAL-SIDED COOLING OF ELECTRONIC MODULES

Dana Canada Corporation, ...

1. A heat exchanger assembly comprising:a first heat sink element and a second heat sink element separated by a space, wherein the first heat sink element defines a first fluid flow passage and the second heat sink element defines a second fluid flow passage, and wherein the first and second heat sink elements are parallel to one another;
at least one heat-generating electronic component located in said space and sandwiched between the first and second heat sink elements, wherein each said heat-generating electronic component has a first side surface in thermal contact with an inner surface of the first heat sink element and an opposite side surface in thermal contact with the inner surface of the second heat sink element; and
a clamping assembly, comprising:
(a) a first spring element arranged in contact with an outer surface of the first heat sink element; and
(b) a second spring element arranged in contact with an outer surface of the second heat sink element;
wherein the first and second heat sink elements are sandwiched between the first and second spring elements, and wherein the first and second spring elements are joined together so as to apply compressive forces to the first and second heat sink elements and thereby cause the at least one heat-generating electronic component to be clamped between the first and second heat sink elements;
wherein each said spring element comprises one or more discrete force application regions for applying force to one of the heat sink elements, and a plurality of fastening regions for maintaining the position of the spring element relative to the outer surface of the heat sink element with which it is in contact;
wherein the force application regions are located such that at least some of the force application regions are positioned approximately centrally above or below a side surface of one of the heat-generating electronic components; and
wherein the force application regions are spaced apart along the longitudinal axis by a center-to-center distance between adjacent heat-generating electronic components.

US Pat. No. 10,600,720

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor module comprising a semiconductor element, a resin package sealing the semiconductor element, and a heat sink located at a main surface of the resin package, the resin package comprising a pair of side surfaces each adjacent to the main surface and opposite to each other;
an insulating sheet covering the heat sink;
a cooling plate which is constituted of resin containing heat transfer fillers, the cooling plate having a first surface and a second surface opposite from the first surface, wherein the first surface covers the insulating sheet and is in direct contact with the main surface of the resin package around the insulating sheet, and the second surface is provided with fins; and
a cooler constituted of resin and at least partly defining a coolant passage configured to flow coolant along the fins, wherein the cooler surrounds the cooling plate in a view along a normal direction of the cooling plate, and is in direct contact with each of the pair of side surfaces of the resin package,
wherein
a peripheral edge of the cooling plate is separated from the cooler by a gap;
the gap extends from the coolant passage to the main surface of the resin package such that the coolant passage is partly defined by the main surface of the resin package;
the cooler directly contacts the main surface of the resin package around the peripheral edge of the cooling plate; and
the cooler comprises an outer cylinder at least partly defining the coolant passage and at least two beams provided in the outer cylinder and being in direct contact with the pair of side surfaces and the main surface of the resin package.

US Pat. No. 10,600,719

BONDED BODY, POWER MODULE SUBSTRATE WITH HEAT SINK, HEAT SINK, METHOD OF MANUFACTURING BONDED BODY, METHOD OF MANUFACTURING POWER MODULE SUBSTRATE WITH HEAT SINK, AND METHOD OF MANUFACTURING HEAT SINK

MITSUBISHI MATERIALS CORP...

1. A bonded body, comprising:an aluminum member which is constituted by an aluminum alloy; and
a metal member which is constituted by copper,
wherein the aluminum member and the metal member are bonded to each other,
wherein the aluminum member is constituted by the aluminum alloy in which a solidus temperature is set to be less than a eutectic temperature of a metal element that constitutes the metal member and aluminum,
a Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding,
a Cu—Ti layer is formed at a bonding interface between the metal member and the Ti layer, and a thickness of the Cu—Ti layer is 1 ?m to 8 ?m,
the aluminum member includes 9.6 mass % to 12.0 mass % of Si, and an Al—Ti—Si layer in which Si is solid-soluted in Al3Ti is formed at a bonding interface between the aluminum member and the Ti layer,
the Al—Ti—Si sub-layer includes a second Al—Ti—Si sub-layer that is in direct contact with the aluminum member, and a first Al—Ti—Si sub-layer that is in between the second Al—Ti—Si sub-layer and the Ti layer, and
a Si concentration of the second Al—Ti—Si sub-layer is lower than a Si concentration of the first Al—Ti—Si sub-layer.

US Pat. No. 10,600,718

HEAT SINK PACKAGE

II-VI Delaware, Inc., Wi...

1. A semiconductor device package comprising:a silicon substrate for supporting an integrated circuit mounted in a flip-chip fashion;
a high electron mobility transistor (HEMT) formed in a layer of Gallium Nitride (GaN) having a first major active device surface mounted in the flip-chip fashion on the silicon substrate;
an interconnect making thermal contact with the layer of GaN on its first major active device surface, said interconnect comprising a high areal density ohmic contact layer covering a high percentage of the first major active device surface;
a first high areal density heat sink/heat spreader disposed across a majority of the interconnect, and in electrical and thermal contact with said interconnect; and
a second high areal density heat sink/heat spreader embedded within the silicon substrate and in electrical and thermal contact with the first heat sink/heat spreader.

US Pat. No. 10,600,717

SEMICONDUCTOR DEVICE

Toyota Jidosha Kabushiki ...

1. A semiconductor device comprising:a first semiconductor element;
a first heat dissipation plate connected to the first semiconductor element;
a sealing body that integrally holds the first semiconductor element and the first heat dissipation plate; and
a first terminal that is electrically connected to the first semiconductor element and protrudes from the sealing body, wherein:
the first heat dissipation plate has
a first insulating substrate,
a first inner conductor layer that is located on a first side of the first insulating substrate and is electrically connected to the first semiconductor element, and
a first outer conductor layer that is located on a second side of the first insulating substrate;
the first outer conductor layer is exposed on a first main surface of the sealing body;
the first terminal protrudes from a first side surface adjacent to the first main surface of the sealing body;
on the first main surface of the sealing body, at least one first groove extending in a direction along the first side surface is provided in a range located between the first outer conductor layer and the first side surface;
wherein the at least one first groove includes a plurality of first grooves; and
a groove located closer to the first side surface among the first grooves has a larger depth.

US Pat. No. 10,600,688

METHODS OF PRODUCING SELF-ALIGNED VIAS

Micromaterials LLC, Wilm...

1. A method to provide a self-aligned via, the method comprising:forming a seed gapfill layer on recessed first insulating layers positioned between first conductive lines, the first conductive lines extending along a first direction;
forming pillars from the seed gapfill layer, the pillars extending above the first conductive lines;
depositing a second insulating layer in gaps between the pillars on the first conductive lines;
removing the pillars to form gaps in the second insulating layer;
depositing a third insulating layer in the gaps in the second insulating layer, onto the recessed first insulating layers and on the second insulating layer to form an overburden of third insulating layer on the second insulating layer; and
selectively etching a portion of the overburden of the third insulating layer and some of the second insulating layer to expose the first conductive lines and form vias and a trench extending in a second direction different from the first direction.

US Pat. No. 10,600,661

RAPID HEAT TREATMENT APPARATUS

ULTECH CO., LTD., Daegu ...

1. A rapid heat treatment apparatus, comprising:a chamber for rapid heat treatment;
a support stage which is disposed on an lower inner side of the chamber and supports and rotates a substrate for rapid heat treatment;
a heat source device which is disposed on an upper inner side of the chamber and radiates light to rapidly heat the substrate for rapid heat treatment;
a substrate for temperature measurement which is placed apart at a distance above a part of the substrate for rapid heat treatment, and is made of a same material as the substrate for rapid heat treatment;
a thermocouple for temperature measurement which is installed at the substrate for temperature measurement to measure a temperature of the substrate for temperature measurement;
a support part of a light transmitting material which supports the substrate for temperature measurement; and
a light transmitting plate which is disposed between the support part and the heat source device to isolate the two internal space parts of the chamber,
wherein the temperature of the substrate for temperature measurement measured by the thermocouple is regarded as temperature of the substrate for rapid heat treatment.

US Pat. No. 10,600,586

INTERLOCKING DEVICE FOR CIRCUIT BREAKER

ZHEJIANG CHINT ELECTRICS ...

1. An interlocking device for a circuit breaker, comprising a control assembly and an interlocking assembly which are connected with each other in a driving manner; the control assembly can be connected with a connecting rod assembly and a cam assembly of an energy storage operation mechanism of the circuit breaker in a latching manner, thereby controlling the energy storage operation mechanism to finish a switching-on/switching-off operation; the control assembly comprises a switching-off half-shaft, a switching-off latch, a switching-on half-shaft and a switching-on latch; the interlocking assembly comprises a switching-on guide rod, a switching-off guide rod and a driving guide rod;the control assembly further comprises a switching-on button; the switching-on latch can be connected with the cam assembly in a latching manner, the driving guide rod is connected with the switching-on button in a driving manner; in the switching-on operation, one end part of the switching-on guide rod can be arranged between the driving guide rod and the switching-on half-shaft, and after the switching-on button is pushed, the switching-on guide rod drives the switching-on latch to be tripped from the cam assembly;
the control assembly further comprises a switching-off button; one end of the switching-off latch is connected with the switching-off half-shaft in a latching manner, and the other end of the switching-off latch is connected with the connecting rod assembly in a latching and limiting manner; in the switching-off operation, after the switching-off button is pushed, the switching-off guide rod drives the switching-off half-shaft to rotate and to trip the switching-off half-shaft from the switching-off latch, and to trip the switching-off latch from the connecting rod assembly;
one end of the switching-on half-shaft is connected with the switching-on latch in a driving manner, and the other end of the switching-on half-shaft and the driving guide rod face each other;
the interlocking assembly further comprises an interlocking guide rod and an energy storage indicator; the energy storage operation mechanism of the circuit breaker comprises a rotating shaft assembly for driving the switching-on/switching-off operation; a middle part of the interlocking guide rod is rotatably mounted on the energy storage operation mechanism; one end of the interlocking guide rod is a limiting portion which corresponds to the rotating shaft assembly and the energy storage indicator, and another end of the interlocking guide rod is a driving portion which is in contact and connection with the switching-on guide rod; the rotating shaft assembly and the energy storage indicator can be in contact and matched with the limiting portion of the interlocking guide rod, such that the interlocking guide rod acts on the switching-on guide rod; when the energy storage operation mechanism is in a switching-off energy storage state, the driving portion of the interlocking guide rod does not limit a switching-on interlocking portion of the switching-on guide rod the energy storage operation mechanism further comprises a driving shaft for mounting the connecting rod assembly and the cam assembly, wherein the rotating shaft assembly and the interlocking assembly are mounted at two sides of the driving shaft respectively.

US Pat. No. 10,600,585

GEAR UNIT HOUSING COVER INTERCONNECT WITHIN A CIRCUIT BREAKER

Siemens Aktiengesellschaf...

1. A gear unit housing for a gear unit having a two-sided control lever for moving two switch contacts of a circuit breaker in mutually opposite directions, the gear unit housing comprising:a housing cassette having a housing base;
a cover plate lying opposite to said housing base;
screw connections detachably interconnecting said cover plate and said housing cassette;
a bearing shaft connected to said housing cassette and to said cover plate, said bearing shaft extending between said housing base and said cover plate for mounting the control lever rotatably about said bearing shaft; and
at least one stud element form-lockingly interconnecting said housing cassette and said cover plate.

US Pat. No. 10,600,584

TRIGGER ACTIVATED TOOLS HAVING ACTIVATION LOCKOUTS

Hubbel Incorporated, She...

1. A trigger activated tool, comprising:an activatable device;
an activation trigger depending from a handle portion for movement about a first axis between a first position and a second position, the activation trigger being configured to activate the activateable device in the second position;
a lockout depending from the activation trigger for movement about a second axis between a locked state and an unlocked state, the locked state preventing activation of the activatable device by the activation trigger; and
a drain trigger depending from the handle portion for movement about the first axis, the drain trigger being configured to relieve potential energy within the activatable device when the lockout is in both the locked and unlocked states, the drain trigger being configured to relieve potential energy within the activatable device when the activation trigger is in the first position, but not the second position, wherein the first and second axes are offset from one another.

US Pat. No. 10,600,583

METHOD OF MAKING A POROUS NITROGEN-DOPED CARBON ELECTRODE FROM BIOMASS

King Saud University, Ri...

1. A method of making a porous nitrogen-doped carbon electrode from date palm (Phoenix dactylifera L.) pollen grains, comprising the steps of:stirring a volume of date palm (Phoenix dactylifera L.) pollen grains into an aqueous solution of potassium hydroxide (KOH) for one hour to produce a precursor carbon solution;
drying the precursor carbon solution for a period of six hours at a temperature of 80° C. to produce precursor carbon;
heating the precursor carbon at a temperature of 800° C. for two hours under an argon atmosphere to produce porous nitrogen-doped graphite carbon;
washing the porous nitrogen-doped graphite carbon in an aqueous solution of HCl, deionized water, and ethanol;
drying the porous nitrogen-doped graphite carbon for 24 hours at a temperature of 80° C.;
mixing the porous nitrogen-doped graphite carbon with a polyvinylidene difluoride (PVDF) binder and carbon black in an isopropanol solvent to form a slurry; and
coating nickel foam with the slurry to form a porous nitrogen-doped carbon electrode and dried at a temperature of 100° C., wherein the dried nitrogen-doped carbon electrode has a porous, cage-type structure wherein the pore volume is at least 0.8 cm3/g, having a Brunauer-Emmett-Teller (BET) surface area within about 86-87 m2/g, a wall thickness of at least about 30.8-80.0 nm and a mean pore diameter in the range of about 50 to about 450 nm.

US Pat. No. 10,600,582

COMPOSITE ELECTRODE

FASTCAP SYSTEMS CORPORATI...

1. An energy storage apparatus comprising:an active layer comprising:
a network of carbon nanotubes defining void spaces; and
a carbonaceous material located in the void spaces and bound by the network of carbon nanotubes; and
an adhesion layer disposed between the active layer and an electrically conductive layer, wherein the adhesion layer comprises at least ninety percent single wall carbon nanotubes (SWNT) by weight;
wherein the active layer is configured to provide energy storage;
wherein the active layer is substantially free from binding agents and consists essentially of carbonaceous material;
wherein the active layer is bound together and to the adhesion layer by forces between the carbon nanotubes and the carbonaceous material;
wherein the network of carbon nanotubes makes up less than ten percent by weight of the active layer;
wherein the network of carbon nanotubes comprises an electrically interconnected network of carbon nanotubes exhibiting connectivity above a percolation threshold
wherein the interconnected network of carbon nanotubes comprises one or more highly conductive pathways, the pathways comprising a length greater than 100 ?m;
wherein the interconnected network of carbon nanotubes includes one or more structures formed of the carbon nanotubes, the structure comprising an overall length at least ten times the average length of component carbon nanotubes making up the structure.

US Pat. No. 10,600,581

ELECTRIC DOUBLE LAYER CAPACITANCE DEVICE

BASF SE, Ludwigshafen (D...

1. An electrode comprising a binder and activated carbon, wherein the activated carbon comprises:a surface area of greater than 1500 m2/g, as determined by nitrogen sorption at 77 K and BET analysis; and
a pore structure comprising mesopores having a diameter ranging from 2.0 nm to 10.0 nm and a pore volume ranging from 0.01 cc/g to 0.25 cc/g for pores having a pore diameter of 0.6 nm to 1.0 nm, as determined from N2 sorption derived DFT,
wherein the electrode has a specific capacitance of at least 100 F/g and a specific power of at least 25 W/g when each of the specific capacitance and specific power is measured in an electric double layer capacitor device comprising an electrolyte comprising equal volumes of propylene carbonate and dimethylcarbonate and further comprising 1.0 M tetraethylammonium tetrafluoroborate.

US Pat. No. 10,600,580

EXPLOSION-PROOF APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. An explosion-proof apparatus comprising:a stopper having a hollow cylindrical shape that is open at a first side and closed at a second side opposite to the first side, the stopper being configured to be combined with an electrolytic condenser by surrounding a top side of the electrolytic condenser and a lateral side of the electrolytic condenser connected to the top side, through the first side of the stopper; and
a holder provided on the stopper and configured to support the stopper to be combined to the electrolytic condenser,
wherein the first side of the stopper is spaced apart from the top side of the electrolytic condenser.

US Pat. No. 10,600,579

ELECTROLYTIC CAPACITOR INCLUDING HYDROXY COMPOUND AND MANUFACTURING METHOD THEREFOR

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising:an anode body including a dielectric layer; and
a solid electrolyte layer covering at least a part of the dielectric layer, wherein:
the solid electrolyte layer includes:
a first conductive polymer layer covering at least a part of the dielectric layer and including a first conductive polymer; and
a second conductive polymer layer covering at least a part of the first conductive polymer layer and including a second conductive polymer,
the second conductive polymer layer is a layer in which the second conductive polymer, a polymer dopant, and a hydroxy compound are mixed,
the hydroxy compound has two or more alcoholic hydroxy groups or two or more phenolic hydroxy groups, the hydroxy compound having a melting point ranging from 40° C. to 150° C., inclusive,
the first conductive polymer layer further includes the hydroxy compound, and
a concentration of the hydroxy compound included in the second conductive polymer layer is higher than a concentration of the hydroxy compound included in the first conductive polymer layer.

US Pat. No. 10,600,578

ELECTRIC VEHICLE INVERTER MODULE CAPACITORS

SF MOTORS, INC., Santa C...

1. A capacitor module of an inverter module to provide electrical power to an electric vehicle, comprising:a capacitor housing;
a plurality of positive terminals coupled with a first surface of the capacitor housing and extending from the first surface at a first angle;
a plurality of negative terminals coupled with the first surface of the capacitor housing;
a divider coupled with the first surface of the capacitor housing, the divider disposed between the plurality of positive terminals and the plurality of negative terminals, and the divider electrically isolates the plurality of positive terminals from the plurality of negative terminals;
a plurality of mounting holes formed on an outer surface of the capacitor housing;
a first plurality of separating elements formed on a first side surface of the divider, each separating element of the first plurality of separating elements disposed between a pair of positive terminals of the plurality of positive terminals; and
a second plurality of separating elements formed on a second side surface of the divider, each separating element of the second plurality of separating elements disposed between a pair of negative terminals of the plurality of negative terminals.

US Pat. No. 10,600,577

ELECTRIC VEHICLE INVERTER MODULE CAPACITORS

SF MOTORS, INC., Santa C...

1. A capacitor module of an inverter module to provide electrical power to an electric vehicle, comprising:a capacitor housing;
a plurality of positive terminals coupled with a first surface of the capacitor housing and extending from the first surface at a first angle;
a plurality of negative terminals coupled with the first surface of the capacitor housing; a divider coupled with the first surface of the capacitor housing, the divider disposed between the plurality of positive terminals and the plurality of negative terminals, and the divider electrically isolates the plurality of positive terminals from the plurality of negative terminals;
a plurality of mounting holes formed on an outer surface of the capacitor housing;
an extension portion of the divider, the extension portion disposed between the plurality of positive terminals and the plurality of negative terminals to electrically insulate the plurality of positive terminals from the plurality of negative terminals, and wherein the plurality of positive terminals are adjacent to a first side surface of the extension portion and the plurality of negative terminals are adjacent to a second side surface of the extension portion;
a first divider support member to hold the plurality of positive terminals and the plurality of negative terminals; and
a second divider support member to hold the plurality of positive terminals and the plurality of negative terminals.

US Pat. No. 10,600,576

VOLUMETRIC EFFICIENCY WET ELECTROLYTE CAPACITOR HAVING A FILL PORT AND TERMINATIONS FOR SURFACE MOUNTING

VISHAY SPRAGUE, INC., Be...

1. A wet electrolytic capacitor, comprising:a body defining an interior area and comprising a fill port formed through a wall of the body, the body having a first portion and a second portion;
a compressible fill port plug positioned adjacent the fill port;
a fill port cover welded to the body and covering the fill port plug and configured to compress the fill port plug against the fill port to seal the fill port.

US Pat. No. 10,600,575

MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic capacitor comprising:a laminated body including a plurality of dielectric layers and a plurality of internal electrodes laminated in a lamination direction; and
a plurality of external electrodes electrically connected to respective ones of the internal electrodes; wherein
the laminated body includes a first principal surface and a second principal surface opposed in the lamination direction, a first side surface and a second side surface opposed in a width direction perpendicular or substantially perpendicular to the lamination direction, and a first end surface and a second end surface opposed in a length direction perpendicular or substantially perpendicular to both the lamination direction and the width direction;
the plurality of internal electrodes include first internal electrodes exposed at the first end surface, and second internal electrodes exposed at the second end surface;
the laminated body includes outer layer portions provided at a top and a bottom of the laminated body in the lamination direction, and an inner layer portion between the outer layer portions;
the plurality of external electrodes include a first external electrode covering the first end surface and electrically connected to the first internal electrodes, and a second external electrode covering the second end surface and electrically connected to the second internal electrodes;
side margin portions sandwich the plurality of dielectric layers in the width direction;
in the width direction from a respective one of the first and second side surfaces to the plurality of the dielectric layers, each of the side margin portions includes at least one outer side margin layer and at least one inner side margin layer in that order;
at least one region of the laminated body extends in the width direction from the respective one of the first and second side surfaces to a location within the inner layer portion, and Si is included at at least one location in the at least one region; and
each of the at least one inner side margin layer and the at least one outer side margin layer extends from the first principal surface to the second principal surface to define at least a portion of the first principal surface and at least a portion of the second principal surface.

US Pat. No. 10,600,574

ORGANIC COMPOUND, CRYSTAL DIELECTRIC LAYER AND CAPACITOR

CAPACITOR SCIENCES INCORP...

1. An organic compound characterized by electronic polarizability and having a general structural formula selected from:
wherein:
R1 is independently selected from the group consisting of hetero-alkyl C1-C18, hetero-alkenyl C1-C18, hetero-alkynyl C1-C18, hetero-aryl C1-C18, unsubstituted C1-C18 alkyl, substituted C1-C18 alkyl, unsubstituted C2-C18 alkenyl, substituted C2-C18 alkenyl, unsubstituted C2-C18 alkynyl, substituted C2-C18 alkynyl, unsubstituted C4-C18 aryl, substituted C4-C18 aryl, fluorinated alkyl, chlorinated alkyl, branched alkyl, branched fluorinated alkyl, and branched chlorinated alkyl;
wherein the core has flat anisometric form and R2 are selected from hydrogen and nucleophilic groups and R3 and R4 are independently selected from hydrogen and electrophilic groups or vice versa R3 and R4 are independently selected from hydrogen and nucleophilic groups.

US Pat. No. 10,600,573

CAPACITOR COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body in which a dielectric layer and an internal electrode are alternately stacked; and
an external electrode disposed on the body and connected to the internal electrode,
wherein the dielectric layer includes a composite layer including a first dielectric material and a metallic particle and first and second protective layers spaced apart by the composite layer and including a second dielectric material; and
wherein a thickness of each of the first and second protective layers is equal to or greater than ? of a thickness of the dielectric layer.

US Pat. No. 10,600,572

DIELECTRIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR CONTAINING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor comprising:a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and
first and second external electrodes disposed on an external surface of the ceramic body,
wherein each dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell including Ba(Ti1-xSnx)O3, the shell covering at least 30% of a surface of the core, and the shell having a thickness within a range of 2 nm to 50 nm.

US Pat. No. 10,600,571

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and first and second internal electrodes alternately laminated with the dielectric layers disposed therebetween in a stacking direction, the first and second internal electrodes being exposed to first and second external surfaces of the ceramic body, respectively, in a length direction; and
first and second external electrodes disposed on the first and second external surfaces of the ceramic body to be electrically connected to the first and second internal electrodes, respectively, the first and second external electrodes extending along a surface of the ceramic body in the length direction,
wherein Lb/La is greater than zero and less than or equal to 0.6, where a longest distance from the first external electrode to the second external electrode in the length direction is denoted by “La”, and a shortest distance from the first external electrode to the second external electrode in the length direction is denoted by “Lb”,
wherein BWd is greater than BWc, where an average length of an extending portion of each of the first and second external electrodes in the length direction, corresponding to an edge of the ceramic body, is denoted by “BWc”, and an average length of an extending portion of each of the first and second external electrodes in the length direction, corresponding to a center of the surface of the ceramic body is denoted by “BWd”,
wherein the ceramic body has a hexahedral shape having at least one rounded corner, and
wherein 0

US Pat. No. 10,600,570

ELECTRONIC COMPONENT

TDK CORPORATION, Tokyo (...

1. An electronic component, comprising:an element body of a rectangular parallelepiped shape including a first principal surface arranged to constitute a mounting surface, a second principal surface opposing the first principal surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction; and
a plurality of external electrodes disposed at both end portions of the element body in the third direction, wherein
the plurality of external electrodes includes a plating layer including a first portion covering the first principal surface and a pair of second portions covering the pair of side surfaces, and
a thickness of the first portion is smaller than each thickness of the pair of second portions.

US Pat. No. 10,600,569

FINGER METAL-ON-METAL CAPACITOR CONTAINING NEGATIVE CAPACITANCE MATERIAL

QUALCOMM Incorporated, S...

9. An integrated circuit, comprising:a first layer comprising a plurality of electrodes;
a dielectric layer deposited in a channel between at least one set of electrodes of the first layer and formed on sidewalls of the plurality of electrodes of the first layer, the channel extending between a sidewall of a first electrode and a sidewall of a second electrode of the at least one set of electrodes;
a negative capacitance material deposited in the channel;
a second dielectric layer formed across an upper surface of the plurality of electrodes, an upper surface of the dielectric layer, and an upper surface of the negative capacitance material;
a second layer comprising a plurality of electrodes formed on the second dielectric layer;
a third dielectric layer deposited in a channel between at least one set of electrodes of the plurality of electrodes of the second layer and formed on sidewalls of the plurality of electrodes of the second layer, the channel extending between a sidewall of a third electrode and a sidewall of a fourth electrode of the at least one set of electrodes of the plurality of electrodes of the second layer; and
a second negative capacitance material deposited in the channel between the at least one set of electrodes of the plurality of electrodes of the second layer.

US Pat. No. 10,600,568

CAPACITOR AND METHOD OF FABRICATING THE SAME

United Microelectronics C...

1. A capacitor, comprising:a first electrode located on a top surface of a dielectric layer;
a dielectric covering a sidewall and a top surface of the first electrode; and
a second electrode covering the dielectric and the dielectric layer, wherein an orthographic projection area of the second electrode on the dielectric layer is greater than an orthographic projection area of the first electrode on the dielectric layer, and a bottommost surface of the second electrode is in direct physical contact with the dielectric layer, wherein the bottommost surface of the second electrode is coplanar with a bottommost surface of the first electrode and a bottommost surface of the dielectric.

US Pat. No. 10,600,567

MULTILAYER CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer capacitor comprising:a capacitor body; and
a plurality of outer connectors provided on outer surfaces of the capacitor body; wherein
the capacitor body includes a plurality of dielectric layers and a plurality of conductor layers stacked alternatingly along a height direction;
the capacitor body includes a first principal surface and a second principal surface that face each other in the height direction, a first side surface and a second side surface that face each other in a length direction that is perpendicular or substantially perpendicular to the height direction, and a third side surface and a fourth side surface that face each other in a width direction that is perpendicular or substantially perpendicular to the height direction and the length direction;
the plurality of outer connectors includes:
a first outer connector that covers a first portion of the first side surface, a first portion of the third side surface, and a first portion of at least one of the first and second principal surfaces;
a second outer connector that covers a first portion of the second side surface, a first portion of the fourth side surface, and a second portion of at least one of the first and second principal surfaces;
a third outer connector that covers a second portion of the second side surface, a second portion of the third side surface, and a third portion of at least one of the first and second principal surfaces; and
a fourth outer connector that covers a second portion of the first side surface, a second portion of the fourth side surface, and a fourth portion of at least one of the first and second principal surfaces;
the plurality of conductor layers includes a plurality of first conductor layers connected to the first and second outer connectors and a plurality of second conductor layers connected to the third and fourth outer connectors;
the capacitor body includes an effective portion defined by electrostatic capacitance portions stacked along the height direction, each of the electrostatic capacitance portions being defined by one of the plurality of first conductor layers and one of the plurality of second conductor layers being disposed opposite to each other with one of the plurality of dielectric layers interposed therebetween;
in a case where L0 is a maximum external dimension of the multilayer capacitor in the length direction, W0 is a maximum external dimension of the multilayer capacitor in the width direction, and H0 is a maximum external dimension of the multilayer capacitor in the height direction, L0, W0, and H0 satisfy a condition of 2.67?L0/H0 and further satisfy a condition of 1/1.72?L0/W0?1.72; and
the effective portion overlaps with one or more of portions of the first, second, third, and fourth outer connectors that cover one or more of the first, second, third and fourth portions of the at least one of the first principal surface and the second principal surface when viewed in the height direction.

US Pat. No. 10,600,566

METHOD FOR FORMING A PLANAR, CLOSED LOOP MAGNETIC STRUCTURE

INTERNATIONAL BUSINESS MA...

1. A method for forming a planar, closed loop magnetic structure, comprising:forming a first antiferromagnetic layer at a first blocking temperature for a closed magnetic loop to define a first pin direction for first magnetic moments;
forming a second antiferromagnetic layer at a second blocking temperature lower than the first blocking temperature for the closed magnetic loop to define a second pin direction different from the first pin direction for second magnetic moments; and
forming a coil around at least one core segment of the closed magnetic loop such that when the coil is energized the first and second magnetic moments rotate to follow a contour of the closed magnetic loop.

US Pat. No. 10,600,565

MANUFACTURE METHOD OF COIL COMPONENT, AND COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a base insulating resin;
a first spiral wiring stacked on the base insulating resin;
a first insulating resin that is stacked on the first spiral wiring, the first insulating resin covering the first spiral wiring;
a second spiral wiring that is stacked directly on and in direct contact with the first insulating resin, the second spiral wiring being connected to the first spiral wiring through a via wiring extending in a layer stacking direction;
a second insulating resin that is stacked on the second spiral wiring, the second insulating resin covering the second spiral wiring; and
a magnetic resin that covers a lower surface of the base insulating resin and an upper surface of the second insulating resin, the magnetic resin being in direct contact with a surface of the base insulating resin opposite to the first insulating resin,
wherein the first spiral wiring is stacked on and in direct contact with the base insulating resin, and
an innermost side edge of the first and second insulating resins have a tapered cross-section.

US Pat. No. 10,600,564

INDUCTIVE POWER TRANSFER SYSTEM PRIMARY TRACK TOPOLOGIES

AUCKLAND UNISERVICES LIMI...

1. A multiphase Inductive Power Transfer (IPT) primary track conductor arrangement comprising phase conductors including a first phase conductor and a second phase conductor, the phase conductors being arranged substantially in a plane and being operable to provide a magnetic field for inductive power transfer on one side of the plane, the phase conductors also being arranged to overlap each other such that there is minimal mutual coupling between the phase conductors, and the arrangement being associated with a magnetically permeable member, the magnetically permeable member being provided on an opposite side of the plane,wherein a forward current path of the first phase conductor and a return current path of the first phase conductor are arranged to produce a first series of alternating pole areas, and a forward current path of the second phase conductor and a return current path of the second phase conductor are arranged to produce a second series of alternating pole areas, and wherein the magnetically permeable member is configured to channel flux between adjacent pole areas.

US Pat. No. 10,600,563

MAGNETIC-SHIELD-TYPE CONVERTER

AMOGREENTECH CO., LTD., ...

1. A magnetically shielded current transformer comprising:a magnetic core module comprising:
a core formed in a ring shape by winding plate shape amorphous alloy ribbon a plurality of times;
a bobbin configured to accommodate the core; and
a coil configured to be wound along an outer circumferential surface of the bobbin;
a shielding member configured to surround an outer circumferential surface and both end surfaces of the magnetic core module, the shielding member including through-holes at centers of the both end surfaces, and formed of iron; and
an outer case configured to protect the magnetic core module and the shielding member,
wherein the bobbin comprises:
a bobbin case having a cylindrical shape of which a side is open and configured to accommodate a coil in a space between an inner cylindrical sidewall and the outer circumferential surface; and
a bobbin cover configured to cover the bobbin case, the bobbin cover comprising a plate type ring shape with a through-hole at a center,
wherein the bobbin case further comprises:
a first stepped part provided at an inner side of the cylindrical sidewall; and
a second stepped part provided at an inner side of the outer circumferential surface, and
wherein the bobbin cover comprises a protruding part extending along the through-hole toward the bobbin case,
wherein an outer circumferential side of the bobbin cover is configured to be placed on the second stepped part,
wherein the protruding part is configured to be placed on the first stepped part, and
wherein the bobbin case and the bobbin cover are configured to be combined with each other by interference fit.

US Pat. No. 10,600,562

MANUFACTURING METHOD OF MAGNETIC ELEMENT

FSP TECHNOLOGY INC., Tao...

1. A manufacturing method of a magnetic element, comprising:(a) forming a block with magneto-conductive materials, wherein the block comprises a central post and two lateral posts;
(b) cutting the block along a first plane passing through the central post and the lateral posts to form and to be divided into a first body and a second body;
(c) after cutting the block, adhering the first body with the second body to form a first air gap between the central post of the first body and the central post of the second body and two second air gaps between the lateral posts of the first body and the lateral posts of the second body; and
(d) cutting and grinding the adhered first body and second body along a second plane passing through the central post and the lateral posts to form a third body comprising the first air gap and the second air gaps.

US Pat. No. 10,600,561

COIL DEVICE

IHI CORPORATION, Tokyo (...

1. A first coil device that faces a second coil device in a first direction and wirelessly performs power transmission or power reception, the first coil device comprising:a first coil portion that faces a second coil portion of the second coil device in the first direction and includes a conductive wire;
at least one nonmagnetic member that includes a protrusion protruding to an outside of the first coil portion in a second direction orthogonal to the first direction;
the nonmagnetic member includes an eddy current interrupter that interrupts a part of an eddy current generated in the nonmagnetic member;
the nonmagnetic member includes a hollow portion recessed to an opposite side from a side facing the second coil portion in the first direction such that the protrusion extends from within the recessed hollow portion, down a side wall defining the recess of the hollow portion and outward from the recessed hollow Portion in the second direction;
the protrusion having a discontinuous portion in a portion of the protrusion extending down the side wall such that the hollow portion is disconnected from a portion of the protrusion that extends outward from the recessed hollow portion in the second direction; and
the first coil portion is located within the hollow portion.

US Pat. No. 10,600,560

ELECTRONIC COMPONENT INCLUDING OUTER ELECTRODES AND A SHIELD ELECTRODE

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a main body having a rectangular or substantially rectangular parallelepiped shape;
an inner conductor that is provided inside the main body;
one or more outer electrodes that are provided on a bottom surface of the main body and are not provided on four side surfaces of the main body; and
a shield electrode that covers the four side surfaces of the main body and has a rectangular or substantially rectangular cylindrical shape; wherein
the shield electrode is not physically connected to the one or more outer electrodes at a surface of the main body and is physically connected to the inner conductor at a surface of the main body; and
the main body includes a stack of a plurality of insulator layers on top of one another in a stacking direction that connects the top surface and the bottom surface of the main body;
the plurality of insulator layers include a first insulator layer; and
the electronic component further comprises;
one or more passive elements that are provided in the main body; and
a first ground conductor that is provided on the first insulator layer, which is positioned closer to the top surface of the main body than the one or more passive elements.

US Pat. No. 10,600,559

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a drum-shaped core including a winding core portion and a pair of flange portions disposed at respective end portions of the winding core portion, each of the flange portions having an inner surface that faces a winding core portion and is in contact with the corresponding end portion of the winding core portion, an outer surface that faces oppositely and is opposite to the inner surface, a bottom surface that connects the inner surface and the outer surface to each other and faces a mounting substrate during mounting, an upper surface that is opposite to the bottom surface, and a pair of side surfaces that are opposite to each other and extend in a direction so as to connect the bottom surface and the upper surface to each other;
a wire wound around the winding core portion; and
a terminal electrode electrically connected to an end portion of the wire and secured to one of the flange portions with an adhesive,
wherein the terminal electrode includes a base disposed on the outer surface of the flange portion, a wire connection extending from a first portion of the base, and a mounting portion extending from a second portion of the base, for an electrical connection with a conductive portion of the mounting substrate, that is disposed to cover a portion of a bottom surface of the flange portion and extends from a bent portion extending from the base and covering a ridge line along which the outer surface and the bottom surface meet,
wherein the wire is connected to the wire connection,
wherein the mounting portion is not secured to the flange portion to permit freedom of deformation between the mounting portion and the flange portion, and
wherein a difference in height in the thickness direction between the wire connection and the mounting portion is greater than a width of the wire.

US Pat. No. 10,600,558

ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a body containing glass;
external conductors including a first external electrode and a second external electrode each disposed on an external surface of the body;
a spiral conductor disposed within the body; and
extended conductors including a first extended conductor and a second extended conductor each disposed within the body,
wherein one end portion of the spiral conductor is electrically connected to the first external electrode with the first extended conductor therebetween and another end portion of the spiral conductor is electrically connected to the second external electrode with the second extended conductor therebetween, and
wherein the spiral conductor contains Ag and at least one oxide selected from the group consisting of Al2O3, SiO2, ZnO, TiO2, and ZrO2, and the extended conductors contain Ag, but none of Al2O3, SiO2, ZnO, TiO2, and ZrO2.

US Pat. No. 10,600,557

REACTOR HAVING AIR DISCHARGE PATHS

AUTONETWORKS TECHNOLOGIES...

1. A reactor comprising:a coil having winding portions;
a magnetic core having inner core portions arranged inside the winding portions, and outer core portions arranged outside the winding portions;
inner resin portions filling gaps between inner peripheral faces of the winding portions and the inner core portions, and being continuous along an axial direction of the winding portions; and
inner interposed members that are interposed between the inner peripheral faces of the winding portions and the inner core portions, and forming resin flow paths configured to provide flow paths of resin for forming the inner resin portions, wherein:
the inner interposed members have spacers arranged between the winding portions and the inner core portions, and
at least one of the spacers include at least one air discharge path extending from a surface of one inner core portion to the at least one end face side of the winding portions, the at least one air discharge path being: (i) disposed between the surface of one inner core portion and the at least one end face side of the winding portion, and (ii) in communication with one of the resin flow paths.

US Pat. No. 10,600,556

INDUCTOR STRUCTURE

VANGUARD INTERNATIONAL SE...

1. An inductor structure formed on a substrate and disposed in a first region, a second region, a third region and a fourth region, wherein the first region comprises a first boundary, a second boundary, a third boundary and a fourth boundary, the second region comprises a fifth boundary, a sixth boundary, a seventh boundary and an eighth boundary, the third region comprises a ninth boundary, a tenth boundary, an eleventh boundary and a twelfth boundary, and the fourth region comprises a thirteenth boundary, a fourteenth boundary, a fifteenth boundary and a sixteenth boundary, comprising:a first conducting line;
a second conducting line; and
a third conducting line connected between the first conducting line and the second conducting line and comprising:
a first portion sequentially extended along the first, the third, the thirteenth, the sixteenth, the sixth, the eighth, the tenth and the eleventh boundaries; and
a second portion sequentially extended along the ninth, the twelfth, the fifth, the seventh, the fourteenth, the fifteenth, the second and the fourth boundaries,
wherein the first boundary is parallel to the second boundary, the third boundary is parallel to the fourth boundary, and the first and second boundaries are vertical to the third and the fourth boundaries,
wherein the fifth boundary is parallel to the sixth boundary, the seventh boundary is parallel to the eighth boundary, and the fifth and sixth boundaries are vertical to the seventh and the eighth boundaries,
wherein the ninth boundary is parallel to the tenth boundary, the eleventh boundary is parallel to the twelfth boundary, and the ninth and tenth boundaries are vertical to the eleventh and the twelfth boundaries, and
wherein the thirteenth boundary is parallel to the fourteenth boundary, the fifteenth boundary is parallel to the sixteenth boundary, and the thirteenth and fourteenth boundaries are vertical to the fifteenth and the sixteenth boundaries,
wherein the first portion of the third conducting line comprises a first segment directly connected to the first conducting line and extended along the first boundary, and the second portion of the third conducting line comprises a ninth segment directly connected to the first conducting line and extended along the ninth boundary.

US Pat. No. 10,600,555

COMMON MODE FILTER

TDK CORPORATION, Tokyo (...

1. A device, comprising:a core having a first end and a second end; and
first and second wires wound around the core, each of the first and second wires having 1st to Nth turns counting from the first end to the second end, the 1st to Nth turns including an i?1th turn, an ith turn, a jth turn, and a j+1th turn, where j is greater than i,
wherein the ith turn of the first wire is closer to the first end than the ith turn of the second wire, the i?1th turn of the second wire is closer to the first end than the ith turn of the first wire, and the i?1th turn of the first wire is closer to the first end than the i?1th turn of the second wire,
wherein the jth turn of the first wire is closer to the second end than the jth turn of the second wire, the j+1th turn of the second wire is closer to the second end than the jth turn of the first wire, and the j+1th turn of the first wire is closer to the second end than the j+1th turn of the second wire,
wherein the first and second wires form a first winding layer on the core and a second winding layer on the first layer,
wherein each of the i?1th turn, the ith turn, the jth turn, and the j+1th turn of the first wire is positioned at the first winding layer,
wherein each of the ith turn and the jth turn of the second wire is positioned at the first winding layer, and
wherein each of the i?1th turn and the j+1th turn of the second wire is positioned at the second winding layer.

US Pat. No. 10,600,554

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a drum-shaped core including a winding core portion and first and second flange portions disposed at respective opposing first and second end portions of the winding core portion; and
first and second wires that are wound around the winding core portion and are not electrically connected to each other, wherein
the first and second wires form a wire assembly by being wound around the winding core portion together,
the wire assembly includes a twisted wire portion at which the first and second wires are twisted together, an inner layer portion that is in contact with and wound around a circumferential surface of the winding core portion, an outer layer portion wound around an outer circumference of the inner layer portion, a plurality of outward transition portions each extending from the inner layer portion to the outer layer portion, and an inward transition portion extending from the outer layer portion to the inner layer portion,
the outer layer portion includes
a plurality of first outer layer portions that are each connected to a respective one of the outward transition portions extending from a position of the inner layer portion that is between end portions of the inner layer portion in a winding axial direction and connected to the inward transition portion, and
a second outer layer portion that is connected to an outward transition portion extending from an end position of the inner layer portion near the second end portion in the winding axial direction,
the inward transition portion extends to another position of the inner layer portion that is between the end portions of the inner layer portion in the winding axial direction, and
a number of windings included in the second outer layer portion is less than a number of windings in at least one of the first outer layer portions.

US Pat. No. 10,600,553

INDUCTOR HAVING VIA CONNECTION LAYER

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body including a coil part therein,
wherein the coil part includes:
a first coil layer electrically connected to a first via;
a second coil layer disposed below the first coil layer and electrically connected to a second via laterally displaced from the first via; and
a via connection layer disposed between the first coil layer and the second coil layer and electrically connected to the first and second vias,
wherein each of the first and second coil layers has a spiral shape including a plurality of turns,
wherein a collective line width of the via connection layer is wider than a line width of each turn of at least one of the first or second coil layer, and
wherein the via connection layer includes a first coil pattern having a ½ turn.

US Pat. No. 10,600,552

SURFACE-MOUNTED REACTOR AND MANUFACTURING METHOD THEREFOR

HITACHI METALS, LTD., To...

1. A surface mountable reactor, comprising:a coil;
a first magnetic core comprising an axial portion around which the coil is disposed and flange portions at both ends of the axial portion;
a second magnetic core that is disposed outside the coil to connect the flange portions of the first magnetic core; and
a resin mount disposed outside the coil, wherein the second magnetic core comprises a plurality of components separable toward outside the coil,
a circumference of the coil is surrounded by the second magnetic core and the resin mount,
the coil is housed in a space surrounded by (i) the flange portions of the first magnetic core, (ii) the second magnetic core, and (iii) the resin mount, and
the coil has end portions disposed outside the resin mount to form mount terminals.

US Pat. No. 10,600,551

REACTION HAVING OUTER PERIPHERAL IRON CORE

FANUC CORPORATION, Yaman...

1. A reactor, comprising:a core body, the core body comprising:
an outer peripheral iron core composed of a plurality of outer peripheral iron core portions, at least three iron cores coupled to inner surfaces of the plurality of outer peripheral iron core portions, and coils wound around the at least three iron cores, radially inner ends of each of the at least three iron cores being arranged in the vicinity of a center of the outer peripheral iron core and converging toward the center of the outer peripheral iron core; wherein
gaps, which can be magnetically coupled, are formed between one of the at least three iron cores and another iron core adjacent thereto, and the radially inner ends of the at least three iron cores are spaced from each other via the gaps, which can be magnetically coupled; the reactor further comprising:
a fixture which extends, through the interior of the outer peripheral iron core in a region between the outer peripheral iron core and the gaps to fasten opposite ends of the at least three iron cores to each other in the axial direction of the core body.

US Pat. No. 10,600,550

COIL COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil component comprising:a body having a volume of 2.4 mm3 or less and including at least one coil member embedded therein; and
first and second external electrodes partially or entirely formed on first and second surfaces of the body opposing each other, respectively,
wherein a product of inductance Ls (?H) and S/1 (mm) is in a range from 0.45 ?H·mm to 0.75 ?H·mm, inclusive, wherein S (mm2) is an area of regions of the first and second external electrodes disposed on the first and second surfaces of the body, and 1 (mm) is a minimum spaced distance between the first and second external electrodes formed on the first and second surfaces of the body.

US Pat. No. 10,600,549

GLASS-CERAMIC-FERRITE COMPOSITION AND ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. A glass-ceramic-ferrite composition, comprising:a glass;
a ferrite; and
a ceramic filler, wherein
the glass contains, by weight, about 0.5% or more and about 5.0% or less R2O (where R represents at least one selected from the group consisting of Li, Na, and K), about 5.0% or less Al2O3, about 10.0% or more and about 25.0% or less B2O3, and about 70.0% or more and about 85.0% or less SiO2 with respect to a total weight of the glass,
a percentage by weight of the ferrite is about 10% or more and about 80% or less with respect to a total weight of the glass-ceramic-ferrite composition,
the ceramic filler contains at least forsterite selected from forsterite and quartz,
a percentage by weight of the forsterite is about 1% or more and about 10% or less with respect to the total weight of the glass-ceramic-ferrite composition,
a percentage by weight of the quartz is about 40% or less with respect to the total weight of the glass-ceramic-ferrite composition, and
a percentage of a total weight of the ferrite and the ceramic filler is about 85% or less with respect to the total weight of the glass-ceramic-ferrite composition.

US Pat. No. 10,600,548

LIQUID COOLED MAGNETIC ELEMENT

Prippell Technologies, LL...

1. A magnetic element, comprising:a first electrically conductive coil, having a first annular surface and a second annular surface;
a second electrically conductive coil, having a first annular surface and a second annular surface; and
a spacer between the first electrically conductive coil and the second electrically conductive coil, and
the spacer having a first flat face, the first flat face being separated from the first annular surface of the first coil by a first gap,
the magnetic element comprising:
a plurality of pairs of coils including the first coil and the second coil, each coil having an inner end and an outer end, the inner ends of each pair being connected together,
a plurality of first spacers including the spacer; and
a plurality of second spacers,
one of the first spacers having two flat faces and being between the two coils of a respective pair of coils, and
one of the second spacers being between a coil of one pair of coils and a coil of another pair of coils.

US Pat. No. 10,600,547

INDUCTION TYPE POWER SUPPLY SYSTEM AND COIL MODULE THEREOF

Fu Da Tong Technology Co....

1. A coil module for an induction type power supply system comprising:a metal frame;
a coil, disposed on a first surface of the metal frame;
a circuit board, disposed on a second surface of the metal frame, the circuit board comprising a control circuit for controlling operations of the coil; and
an upper lid, for covering the coil, the upper lid composed of a non-metal material and having an arc structure.

US Pat. No. 10,600,546

INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body including:
a support member including a through hole,
a coil including a plurality of coil patterns disposed on the support member and connected to each other to have an overall spiral shape, each of the plurality of coil patterns including a first plating layer and a second plating layer stacked on the first plating layer,
a first insulating wall being at least partial contact with an innermost coil pattern among the plurality of coil patterns,
a second insulating wall being at least partial contact with an outermost coil pattern among the plurality of coil patterns, and
an insulating film filling spaces between the plurality of coil patterns and covering upper surfaces of the first and second insulating walls; and
first and second external electrodes disposed on an external surface of the body and connected to the coil,
wherein each of the first and second insulating walls is a single insulating layer,
the first insulating wall includes a distal portion spaced apart from the support member and from the first and second plating layers of the innermost coil pattern, and
the second insulating wall includes a distal portion spaced apart from the support member and from the first and second plating layers of the outermost coil pattern.

US Pat. No. 10,600,545

COIL ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component, comprising:a body;
coil patterns stacked in a stacking direction and embedded in the body; and
an external electrode disposed on a side surface of the body, connected to one of the coil patterns, and extending on upper and lower surfaces of the body in the stacking direction,
wherein the body includes a base layer and buildup layers disposed on the base layer,
the buildup layers cover the coil patterns, respectively,
the lower surface is an exterior surface of the base layer, and the upper surface is an exterior surface of an uppermost one of the buildup layers,
the buildup layers have sintering properties different from those of the base layer,
the base layer has a sintered density higher than that of at least a portion of the buildup layers including portions disposed between the coil patterns and separating the coil patterns from each other in the stacking direction, and
in a rectangle bounding a cross-section of each coil pattern and a respective buildup layer embedding the coil pattern, an area of conductive portions of each coil pattern of the coil patterns is at least 80% of an entire area of the rectangle bounding the cross-section of each coil pattern and the respective buildup layer embedding the coil pattern.

US Pat. No. 10,600,544

STACKED BODY AND METHOD OF PRODUCING STACKED BODY

MURATA MANUFACTURING CO.,...

1. A stacked body comprising:a base including a plurality of insulating base material layers made of thermoplastic resin;
a conductive pattern located on the plurality of insulating base material layers; and
a dummy pattern electrically isolated from the conductive pattern and extending along at least a portion of the conductive pattern outside of the conductive pattern on the plurality of insulating base material layers on which the conductive pattern is located in a plan view; wherein
the plurality of insulating base material layers are stacked on each other;
the conductive pattern includes a plurality of linear portions at an outermost side of the conductive pattern in a plan view;
the dummy pattern is located along the conductive pattern; and
a bent portion or a wide portion, which has a larger width than the other linear portions in a direction perpendicular or substantially perpendicular to a direction in which a linear portion extends, in a plan view, is located on at least one of the linear portion of the conductive pattern and the dummy pattern extending along the linear portion, excluding an end portion of the linear portion and an end portion of the dummy pattern.

US Pat. No. 10,600,543

ELECTROMECHANICAL ASSEMBLY CONTROLLED BY SENSED VOLTAGE

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:an electronics rack;
an electromechanical assembly disposed within the electronics rack and coupled to a system, comprising a motor, with the electromechanical assembly monitoring voltage at the motor, the electromechanical assembly comprising:
a control circuit coupled to sense the voltage at the motor;
an electromechanical actuator energized by the voltage sensed by the control circuit at the motor; and
a movable interlock element associated with and movable by the electromechanical actuator, the electromechanical actuator moving the movable interlock element from an operational position physically interlocking one or more components of the system to a quiesced position not physically interlocking the one or more components when the voltage sensed by the control circuit at the motor falls below a quiesced threshold, the one or more components comprising an air-moving assembly, and the motor being part of the air-moving assembly.

US Pat. No. 10,600,542

POLARITY-SWITCHING MAGNET DIODE

1. A polarity-switching magnetic diode comprising:a first non-magnetized ferrous element magnetically coupled to a magnetic flux element;
a second non-magnetized ferrous element magnetically coupled to the magnetic flux element;
wherein the magnetic flux element comprises a first effective pole, a second effective pole, and a first gap; and
a control coil wrapped around a portion of the magnetic flux element such that the first gap extends at least partially into the control coil, wherein the control coil has a first active magnetic state and a second active magnetic state,
wherein the first active magnetic state directs a north temporary polarity from the first non-magnetized ferrous element along the magnetic flux element towards the first effective pole and directs a south temporary polarity from the second non-magnetized ferrous element along the magnetic flux element towards the second effective pole; and
wherein the second active magnetic state directs the north temporary polarity from the first non-magnetized ferrous element along the magnetic flux element towards the second effective pole and directs the south temporary polarity from the second non-magnetized ferrous element along the magnetic flux element towards the first effective pole.

US Pat. No. 10,600,541

COMPRESSION-BONDED MAGNET WITH CASE AND METHOD FOR PRODUCING THE SAME

NTN CORPORATION, Osaka (...

1. A compression-bonded magnet with a case, comprising a compression-bonded magnet including a rare earth magnet powder and a resin binder of a thermosetting resin, a case for inserting the compression-bonded magnet, and a sealing member, whereinthe compression-bonded magnet is formed by compression-molding a mixture comprising the rare earth magnet powder and the resin binder into a green compact and curing the resin binder contained in the green compact,
the sealing member is fixed at an insertion opening part for the compression-bonded magnet provided in the case,
the compression-bonded magnet is hermetically sealed by the sealing member and the case, and
the case is a sintered part made of a non-magnetic material.

US Pat. No. 10,600,540

LAMINATED COIL COMPONENT

TDK CORPORATION, Tokyo (...

1. A laminated coil component comprising:an element assembly formed by laminating a plurality of insulation layers; and
a coil unit formed inside the element assembly by a plurality of coil conductors, wherein:
the element assembly includes (1) a coil unit arrangement layer which has the coil unit arranged therein and is made from glass ceramic and (2) a crystalline shape retention layer which is made from glass-ceramic;
the coil unit arrangement layer contains no SrO and has a softening point of below 1050° C.;
no conductor is arranged in the shape retention layer; and
when baked, the coil unit arrangement layer becomes amorphous but retains its shape because of the crystalline shape retention layer which is not softened during baking.

US Pat. No. 10,600,539

CONTOURED-FIELD MAGNETS

Magnetic Technologies AG,...

1. A sintered hard magnet having a magnetic axis that traverses from a first region of the magnet to a second region of the magnet, the magnet comprising:a plurality of first sintered grains in the first region having first magnetic easy directions aligned together substantially parallel to the axis; and
a plurality of second sintered grains in the second region and set apart from the axis, the second sintered grains having second magnetic easy directions that are inclined away from the axis.

US Pat. No. 10,600,538

PERMANENT MAGNET COMPRISING A STACK OF N PATTERNS

1. A magnet comprising a stack of N patterns stacked immediately one above the other in a stacking direction, where N is an integer number greater than or equal to two, each pattern comprising:i) an antiferromagnetic layer made of antiferromagnetic material,
ii) a ferromagnetic layer made of ferromagnetic material,
wherein
the direction of magnetization of the ferromagnetic layer is fixed by an exchange coupling with the antiferromagnetic layer of this pattern, and
the direction of magnetization of the ferromagnetic layer of N-1 patterns is fixed by an exchange coupling with the antiferromagnetic layer of an immediately adjacent pattern in the stack,
wherein the directions of magnetization of the ferromagnetic layers of all the patterns in said stack are identical to one another,
wherein at least one ferromagnetic layer in said stack comprises:
a first sub-layer made of CoFeB whose thickness is greater than 0.05 nm, and
a second sub-layer made of a ferromagnetic material different from CoFeB and whose thickness is greater than the thickness of the first sub-layer,
wherein the magnet is a permanent magnet and wherein the permanent magnet has a total magnetic moment per unit area greater than 50×10?3 A.

US Pat. No. 10,600,537

ELECTRICAL CABLE

TE CONNECTIVITY CORPORATI...

1. An electrical cable comprising:a conductor assembly having a first conductor, a second conductor, and an insulator structure surrounding the first conductor and the second conductor, the first and second conductors carrying differential signals, the insulator structure having an outer surface; and
a cable shield wrapped around the conductor assembly and engaging the outer surface of the insulator structure, the cable shield having an inner edge and a flap covering the inner edge, the cable shield forming a void at the inner edge, the void being located closer to the first conductor than the second conductor, the void compromising the first conductor by reducing an effective dielectric constant surrounding the first conductor;
wherein the first conductor is shifted closer to the cable shield a shift distance compared to the second conductor to increase capacitance of the first conductor compared to the second conductor, the shift distance being selected based on the size of the void and the volume of air introduced in to the void along the first conductor compared to the second conductor along the length of the electrical cable.

US Pat. No. 10,600,536

ELECTRICAL CABLE

TE CONNECTIVITY CORPORATI...

1. An electrical cable comprising:a conductor assembly having a first conductor, a second conductor, a first insulator surrounding the first conductor and a second insulator surrounding the second conductor, the first and second conductors carrying differential signals, the first insulator having an outer surface, the first insulator having a first effective dielectric constant, the second insulator having an outer surface, the second insulator having a second effective dielectric constant, the second effective dielectric constant being less than the first effective dielectric constant; and
a cable shield wrapped around the conductor assembly and engaging the outer surface of the first insulator along a first segment and engaging the outer surface of the second insulator along a second segment, the cable shield having an inner edge and a flap covering the inner edge, the cable shield forming a void at the inner edge, the void being located closer to the first conductor than the second conductor;
wherein a difference between the first effective dielectric constant and the second effective dielectric constant is selected to balance skew effects of the void on the first conductor compared to the second conductor along a length of the electrical cable.

US Pat. No. 10,600,535

ELECTRICAL TRANSPORT WIRE MADE OF AN ALUMINUM ALLOY, HAVING HIGH ELECTRICAL CONDUCTIVITY

NEXANS, Courbevoie (FR)

1. An electrical transportation wire made of aluminum alloy, wherein said electrical transportation wire comprises:aluminum,
from 0.2% to 0.6% by weight of zirconium and
from 0.25% to 0.4% by weight of iron,
from 0.12% to 0.35% be weight of copper, and
unavoidable impurities, said unavoidable impurities including Mn and Si, and
wherein said alloy comprises at least 80 parts by weight of zirconium in the form of precipitates Al3Zr per 100 parts by weight of zirconium in said aluminum alloy,
wherein the aluminum alloy has at most 0.08% by weight of Mn and at most 0.08% by weight of Si, and
wherein said alloy has an electrical conductivity of at least 57% IACS, and
wherein said electrical transportation wire comprises, at the surface, a porous layer of alumina hydroxide.

US Pat. No. 10,600,534

CABLE, DEVICE AND METHOD OF SUPPLYING POWER

1. A cable comprising:an original cable having an insulating sheath as an outermost layer;
a first material provided on the insulating sheath of the original cable; and
a metal sheath provided on the first material and made of aluminum, magnesium, copper, rhodium, silver or gold,
wherein the first material is at least one of a hygroscopic fiber, an inorganic ion exchanger influence fiber, a supercritical influence fiber, and a composite fiber obtained by mixing two or more among the mentioned fibers, and
wherein the first material is impregnated with a silver ion nano-colloidal solution and a tungsten oxide containing solution.

US Pat. No. 10,600,533

MULTI-MEMBER CABLE WITH IMPROVED MID-SPAN ACCESS

CommScope, Inc. of North ...

1. A multi-member cable comprising:a central strength member approximately centered on a center axis of said multi-member cable;
a first cable element;
a second cable element;
a third cable element;
a fourth cable element, wherein said first, second, third and fourth cable elements twist around said central strength member three hundred sixty degrees in the counterclockwise direction multiple times to said first reversal point, then said first, second, third and fourth cable elements twist around said central strength member three hundred sixty degrees in a clockwise direction multiple times until said second reversal point, and wherein said first, second, third and fourth cable elements repeat the pattern of counterclockwise and clockwise twists about said central strength member between multiple first and second reversal points along a length of said multi-member cable;
a coupling formed between said first and second cable elements along the length of said multi-member cable, wherein said coupling is constant between said first and second cable elements along the length of said multi-member cable; and
an outer jacket formed over said central strength member and said first, second, third and fourth cable elements, wherein an outer surface of said first cable element is directly melted to an outer surface of said second cable element to form said coupling without any adhesive.

US Pat. No. 10,600,532

SERVICE LOOP FOR TOP DRIVE EQUIPMENT HAVING AN EMBEDDED LAY LINE

NEXANS, Courbevoie (FR)

1. A top drive service loop cable assembly comprising:a plurality of cabled internal cable components;
a jacket covering said internal cable components;
a flange connected to said jacket and supporting said internal cable components,
wherein said jacket has a recessed embedded lay line embossed into said cable and aligned with internal cable components,
wherein said recessed embedded lay line is impressed into uncured rubber of said jacket with a nylon tape coated with a release agent which is impressed into said uncured rubber via a mold extruder, during extrusion, and
wherein said jacket is vulcanized and then said nylon tape is removed, leaving said embossed and recessed embedded lay line in said jacket.

US Pat. No. 10,600,531

HIGHLY BENDABLE INSULATED ELECTRIC WIRE

YAZAKI CORPORATION, Mina...

1. A highly bendable insulated electric wire comprising:a conducting wire formed by stranding a plurality of metal strands; and
an insulator covering the conducting wire,
wherein a twist pitch ratio of the conducting wire (a twist pitch/an outer diameter of the conducting wire) is 10.8 or less,
the insulator is made of a resin composition containing a vinyl chloride resin and having an elongation rate of 130% or higher at ?40° C., and
an adhesion strength between the conducting wire and the insulator is 20 N or less.

US Pat. No. 10,600,530

CONDUCTIVE MEMBER

SUMITOMO WIRING SYSTEMS, ...

1. A conductive member to be routed in a vehicle, comprising:a tubular conductor having conductivity and opposite ends;
a first flexible conductor having first and second opposite ends, the first flexible conductor is more flexible than the tubular conductor, the first end of the first flexible conductor is electrically connected to the one end of the tubular conductor;
a first terminal that is connected to the second end of the first flexible conductor,
a second flexible conductor having first and second opposite ends, the second flexible conductor is more flexible than the tubular conductor, the first end of the second flexible conductor is electrically connected to another end of the tubular conductor; and
a second terminal that is connected to the second end of the second flexible conductor,
wherein the first and second flexible conductors and first and second terminals are connected at the opposite ends of the tubular conductor, and
a region extending from a portion at one of the ends of the tubular conductor where the first flexible conductor and the first terminal are connected, to a portion at the other end of the tubular conductor where the second flexible conductor and the second terminal are connected is covered by a tubular insulating waterproof covering.

US Pat. No. 10,600,529

METHOD OF MANUFACTURING A RADIATION SOURCE

General Electric Company,...

8. A method of preparing a radiation source comprising a radioactive substance wherein said radioactive substance is osmium and wherein said method comprises the following steps:(i) irradiating enriched 190Os to form a mixture comprising 191Os;
(ii) oxidizing said mixture to produce gaseous OsO4;
(iii) trapping said gaseous OsO4 in aqueous base followed by an osmium reduction step to precipitate osmate as osmate particles;
(iv) formulating said osmate particles into an epoxy matrix to form a formulation;
(v) placing said formulation into a mold;
(vi) curing said formulation in said mold into epoxy rods wherein said curing step comprises mixing said formulation in said mold; and
(vii) cutting said epoxy rods to form cut epoxy rods.

US Pat. No. 10,600,528

PROCESS FOR PRODUCING GALLIUM-68 THROUGH THE IRRADIATION OF A SOLUTION TARGET

Ion Beam Applications S.A...

1. A process for producing and purifying 68Gallium radioisotope, the process comprising:irradiating a target containing a target solution comprising zinc using an accelerated particle beam;
diluting the irradiated target solution with water;
feeding the diluted target solution into a strong cation exchanger;
washing the strong cation exchanger;
eluting zinc isotopes from the strong cation exchanger with a zinc elution solution including acetone;
washing the strong cation exchanger;
eluting 68Gallium isotope from the strong cation exchanger with hydrochloric acid solution to obtain an eluted solution;
feeding the eluted solution into a strong anion exchanger,
washing the strong anion exchanger; and
eluting 68Gallium isotope from the strong anion exchanger with hydrochloric acid solution to obtain a final solution
wherein the irradiated target solution is diluted between 5 and 15 volume times with water.

US Pat. No. 10,600,526

CASK TRANSPORT ASSEMBLY

1. A system for transporting a cask comprising:a cask transport device including:
a support assembly including a plurality of support assembly wheels and a support frame coupled to and supported by the support assembly wheels;
a tower disposed above the support assembly;
an upper beam assembly coupled to the tower frame;
a bottom block assembly coupled to the upper beam assembly, the bottom block assembly movable from a first vertical position relative to the upper beam assembly to a second vertical position relative to the upper beam assembly; and
a controller; and
a low profile transport device having
a frame having a top surface and a recess disposed along the top surface to hold and transport an object;
a plurality of wheels disposed below the frame that support the frame;
a plurality of pivotable wheel struts coupled to the wheels, wherein the wheel struts are each individually adjustable relative to the frame from a first position relative to the frame to a second position relative to the frame to allow the low profile transport device to climb an obstacle without tilting the frame; and
a motor that generates movement of the wheels;
wherein movement of the low profile transport device is controllable via the controller on the cask transport device.

US Pat. No. 10,600,525

GAS PERMEABLE HYDROPHOBIC MATERIAL

Triad National Security, ...

1. A porous material configured for use as a filter material in a nuclear material storage container, the porous material comprising an aluminosilicate substrate and a coating having a thickness of greater than zero to 5 microns, the coating comprising a copper oxide coating, a copper oxide nanowire coating, a fluorine coating, a fluoride coating, or combinations thereof.

US Pat. No. 10,600,524

RADIATION PROTECTION DEVICE AND METHODS THEREOF

STEMRAD LTD., Tel Aviv (...

32. A radiation protection belt providing protection of active bone marrow from external ionizing radiation, comprising:a gamma radiation attenuating component configured to be placed adjacent to and externally cover at least one of the waist and the pelvis of a user so as to reduce a radiation dose absorbed in the active bone marrow in the pelvis, comprising radiation attenuating material of at least one of varying thickness and density to provide varying radiation levels across the gamma radiation attenuating component, such that the varying radiation attenuation level at each point on the radiation attenuating component is inversely related to radiation attenuation levels of tissue present between the point of the radiation attenuating component and the active bone marrow in the pelvis.

US Pat. No. 10,600,523

PANEL ASSEMBLY HAVING VARIABLE TRANSMISSIVITY AND STRUCTURAL RIGIDITY

Westinghouse Electric Com...

1. A panel assembly that is transparent to a preselected form of radiation and that is configured to selectively vary the transmissivity of the preselected form of radiation through the panel assembly, the panel assembly comprising:a first transparent sub panel including a plurality of generally parallel, spaced, first wires extending therethrough from a first edge to an opposite, second edge with at least an end of each first wire connected to an end of an adjacent first wire at one of the first edge or the second edge to form a plurality of U-shaped conductive elements, each U-shaped conductive element having an electromagnetic coil wound thereabout at or about the first edge or the second edge of the first transparent sub panel to form a “horseshoe” electromagnet at each of the connected first wires;
a second transparent sub panel including a plurality of generally parallel, spaced, second wires extending therethrough from a third edge to an opposite, fourth edge with at least an end of each second wire connected to an end of an adjacent second wire at one of the third edge or the fourth edge to form a second plurality of U-shaped conductive elements, each U-shaped conductive element of the second plurality having an electromagnetic coil wound thereabout at or about the third edge or the fourth edge of the second transparent sub panel to form a “horseshoe” electromagnet at each of the connected second wires; and
a magneto-rheological fluid reservoir sandwiched between the first transparent sub panel and the second transparent panel, the reservoir being structured to house a volume of a magneto-rheological fluid.

US Pat. No. 10,600,522

METHOD OF MAKING THIN ATOMIC (Z) GRADE SHIELDS

United States of America ...

1. A method of making a radiation-shielded structural enclosure member, the method comprising:bonding first and second layers of a first material onto first and second opposite sides, respectively, of a third layer of a second material;
securing a fourth layer of a third material to at least one of the first and second layers of the first material to form a structural enclosure member having an areal density of at least about 0.50 g/cm2 and a thickness of no more than about 0.11 inches.

US Pat. No. 10,600,521

POWDER-TRANSFER DEVICE WITH IMPROVED FLOW

1. A transfer device for transferring a given powder or a mixture of given powders, the transfer device comprising:a hopper configured to contain the given powder or the mixture of given powders, said hopper comprising a side wall and at least one discharge opening, said hopper having an axisymmetric shape and having a substantially vertical axis of revolution, said hopper being arranged such that the at least one discharge opening is located in a lower portion of said hopper; and
a device configured to displace the hopper in rotation about an axis of revolution thereof, whereon the at least one discharge opening is located, said device including a control unit being configured such that the device configured to displace the hopper in rotation imposes a first moving phase on at least one movable portion of the side wall of the hopper, wherein an acceleration greater than or equal to a minimum acceleration configured to cause the given powder or the mixture of given powders to slide relative to the at least one movable portion is applied to the at least one movable portion,
wherein the control unit is further configured such that the device configured to displace the hopper in rotation:
repeats the first moving phase successively, separated by phases at constant speed, and
periodically inverts a direction of rotation of the at least one movable portion between two successive first moving phases.

US Pat. No. 10,600,520

RISER CONE APPARATUS TO PROVIDE COMPLIANCE BETWEEN REACTOR COMPONENTS AND MINIMIZE REACTOR COOLANT BYPASS FLOW

BWXT mPower, Inc., Charl...

1. A riser for defining a coolant flow path in a nuclear reactor including a hot leg flowing inside the riser and a cold leg flowing outside the riser, the riser comprising:a hollow cylindrical upper riser section having a smaller diameter;
a hollow cylindrical lower riser section having a larger diameter that is larger than the smaller diameter of the hollow cylindrical upper riser section; and
a riser cone compressed between a lower end of the hollow cylindrical upper riser section and an upper end of the hollow cylindrical lower riser section, the riser cone including a frustoconical body having a lower end mating with the upper end of the hollow cylindrical lower riser section, a sealing ring including an upper end mating with the lower end of the hollow cylindrical upper riser section, and a spring compressed between the sealing ring and an upper end of the frustoconical body so that the riser cone provides sealing between the lower end of the hollow cylindrical upper riser section and the upper end of the hollow cylindrical lower riser section.

US Pat. No. 10,600,519

NUCLEAR REACTOR MODULE

ROLLS-ROYCE plc, London ...

1. A method of constructing a nuclear reactor module, the method comprising:providing a first formwork defining a chamber in which is mounted a nuclear reactor comprising a nuclear reactor pressure vessel configured to contain nuclear fuel when in use;
providing a second formwork defining a containment structure configured to contain an internal pressure generated by an escape of coolant from a reactor coolant circuit, the first formwork being housed within the second formwork;
filling one or more voids within the first formwork with concrete through at least one concrete supply pipe that extends from outside of the second formwork, through the second formwork, and through a wall of the first formwork so as to open into the one or more voids of the first formwork;
forming the containment structure by filling one or more voids within the second formwork with concrete; and
venting the one or more voids within the first formwork through one or more vent pipes, thereby forming a concrete support structure for the nuclear reactor,
wherein the filling of the one or more voids within the second formwork occurs after the filling of the one or more voids within the first formwork.

US Pat. No. 10,600,518

CONTROL ROD/CONTROL ROD DRIVE MECHANISM COUPLINGS

BWXT mPower, Inc., Charl...

1. An apparatus comprising:a connecting rod of a control rod assembly of a nuclear reactor, the connecting rod including:
a hollow or partially hollow connecting rod tube defining an interior volume and comprising a first material having a first density at room temperature, and
a filler disposed in the interior volume of the hollow or partially hollow connecting rod tube, the filler comprising a second material having a second density at room temperature that is greater than the first density,
wherein the connecting rod further comprises a welded plug sealing off the interior volume of the hollow or partially hollow connecting rod tube.

US Pat. No. 10,600,517

NETWORK SYSTEM OF INDIVIDUAL USER DEVICES TO GENERATE GROUP IMPLEMENTED TREATMENT PLAN

Medsphere Systems Corpora...

1. A method executed on a computing device to reduce redundant interventions during the generation and implementation of a collaborative medical treatment plan on a patient, the method comprising:receiving a plurality of selected diagnostic categories and a list of selected team members from a computing device in communication with a treatment plan server;
generating an initial treatment plan stored on the treatment plan server based on the selected diagnostic categories;
permitting client devices associated to the selected team members collaborating virtually to access the initial treatment plan on the treatment plan server, wherein the client devices are heterogeneous and networked;
updating the treatment plan periodically on the treatment plan server for access by the selected team members, wherein updating the treatment plan comprises:
(i) receiving a plurality of treatment objectives and a plurality of interventions based on the initial treatment plan from the client devices, each treatment objective being associated to one or more interventions; and
(ii) generating a completed treatment plan by:
(1) associating each individual team member to one or more interventions,
(2) generating a matrix of the individual team members and their associated one or more interventions, and
(3) assigning the interventions to the team members based on the matrix such that one or more individual interventions assigned to a single team member is shared between multiple treatment objectives; and
directing the plurality of client devices to present the updated treatment plan to the selected team members through the native user interfaces of the client devices, wherein said graphical user interfaces for the updated treatment plan are individualized for each selected team member.

US Pat. No. 10,600,516

HEALTHCARE ADMINISTRATION METHOD FOR COMPLEX CASE AND DISEASE MANAGEMENT

ADVANCED HEALTHCARE SYSTE...

1. A system, comprising:at least one mobile device operable by a healthcare professional, comprising a network connection including internet access, loaded with, and operative to run, video teleconferencing software;
a plurality of databases located on servers connected to the network, the servers located in a plurality of medical facilities comprising hospitals, skilled nursing facilities, free standing surgery centers, dialysis centers, urgent care centers, facilities for performing radiology, and laboratory facilities;
a central database, stored on at least one server, the central database in communication with the plurality of databases, wherein the central database transfers data from the plurality of databases and transforms the data from the plurality of databases into patient files corresponding to each patient of the patient population, and wherein the central database is adapted to be routinely updated, by the plurality of databases, to provide up-to-date healthcare information for each patient within the patient population;
at least one complex case management application, implemented on the at least one server, in communication with the central database, and accessible by the mobile device, the at least one complex case management application programmed to identify a sub-population of patients within a patient population, the sub-population being afflicted with a complex medical condition, and programmed to place the sub-population of patients in to a complex care management regime, said complex medical condition defined by:
three or more chronic medical conditions selected from the group consisting of asthma, congestive heart failure, chronic obstructive pulmonary disease, diabetes, obesity, AIDS/HIV, anticoagulation, hypertension, peripheral artery disease, coronary artery disease, end-stage renal disease, and chronic kidney disease, and one high risk criteria selected from the group consisting of poor social support, poor functional status, poor nutritional status, two or more hospitalizations in the preceding twelve months, and three or more emergency room visits in the preceding twelve months; or
a predetermined range of complexity scores calculated by a scoring module of the at least one complex case management application from an assignment of points based on criteria including:
demographic information including the patient's age, sex, and residence, the residence selected from the group consisting of home, assisted living, skilled nursing facility, and board and care facility;
total number of ER visits and hospital admissions in the last six months;
major organ system dysfunction including cardiovascular, respiratory, renal, nervous system, hematology/oncology, digestive, urinary, infectious disease, endocrine, and musculoskeletal;
total number of drug classifications;
overall functional status including functional limitations; and
support network including social support and caregiver network;
wherein the mobile device is operable to display a plurality of screens of a user interface operable in the at least one complex case management application and implemented using Hyper Text Markup Language and/or JavaScript, the plurality of screens including selected data from the patient files, the plurality of screens including:
a summary page including demographic information, a clinical profile, and support network information;
a complex case management complexity profile linked to the summary page, the complex case management complexity profile including residence information, the number of ER visits and hospital admissions in the last six months, a major organ failure section, the total number of drug classifications currently prescribed for the patient, a listing of the drug classifications, a functional status summary, a listing of limitations regarding functional status; a summary of the patient's support network, and a complexity score;
a chronic conditions list;
a disease management member summary including actions taken, follow-up plans, and open items; and
a complexity profile report and trend including patient name and complexity scores over time;
at least one remote computer terminal linked to the at least one mobile device, the at least one remote computer terminal loaded with, and operable to run, the video teleconferencing software, and the at least one remote computer terminal accessible to patients in the complex care management regime and operative to provide direct, real time communication between a patient in the complex care management regime operating the at least one remote computer terminal and a healthcare professional operating the mobile device, the direct, real time communication concerning an acute condition being experienced by the patient of the sub-population of patients, and for the patient in the complex care management regime to initiate a request for care; and
a cloud-hosted main login table of an access management application, the access management application implemented on the at least one server, the main login table separately hosted from the access management application, the main login table limiting healthcare provider access in the disease management member summary screen of the user interface to open items that the healthcare provider has rights to close out;
wherein the at least one mobile device is configured to display the video teleconference and display the user interface regarding the patient, and wherein the patient files contain a medical history of each patient of the identified sub-population, the mobile device being operable to perform a remote screening process related to said request for care initiated by the patient in the complex care management regime, said remote screening process being performed by evaluating said patient's up-to-date medical information stored in the central database and by assessing said patient's medical case complexities taking into account said complex case management complexity profile accessed on the mobile device via the user interface, determining whether medical treatment for the complex medical condition being experienced by the patient is warranted, pursuant to a determination that medical treatment is warranted, determining whether the complex medical condition being experienced by the patient can be managed in a residential environment, pursuant to a determination that the complex medical condition can be managed in said residential environment, coordinating an appropriate home-based medical treatment in response to the patient's request for care, and, pursuant to a determination that medical treatment is warranted, then, to the extent that a home-based medical treatment is not available, issuing an authorization request for medical treatment of the patient in a medical facility.

US Pat. No. 10,600,515

OPERATIVELY TUNING IMPLANTS FOR INCREASED PERFORMANCE

1. A process for preoperatively selecting an implant optimized to a particular patient's biomechanical characterization, comprising:obtaining, from at least one of a CT device, an MRI device, a radiological device, an ultrasound device and an X-ray device, image data of a patient;
deriving, using a computing device, from the image data, a plurality of dimensions including at least one dimension that includes at least one of anatomic landmark data and soft tissue attachment data;
accessing a database containing a correlation of anatomic data and biomechanical function related to a plurality of implant designs;
executing, using the computer device, a plurality of iterative simulations of a model of the patient created from the plurality of dimensions and data from the database concerning at least one of the implant designs, wherein at least one parameter concerning a configuration of the at least one implant relative to the model of the patient is changed between iterations; and
calculating, from the plurality of iterative simulations, and outputting by the computing device a recommendation of at least one of implant size, implant position, and ligamentous releases.

US Pat. No. 10,600,514

INTUITIVE AUTOMATION IN PATIENT MODELING

Varian Medical Systems, I...

1. A method of automatic structure delineation, the method comprising:causing display, by a computer system, of an image from medical image data;
causing display, by the computer system, of a graphical user interface, the graphical user interface comprising a list of structures corresponding to an area of interest displayed in the image and one or more operations available to be performed;
receiving user supplied input through the graphical user interface, the user supplied input corresponding to a selection of structures from the list of structures;
determining and performing a Boolean operation based on the user supplied input, wherein the Boolean operation comprises a union of or an intersection of each structure of the selection of structures indicated by the user supplied input for inclusion in the Boolean operation;
generating a graphical delineation of the structures resulting from the Boolean operation;
storing the graphical delineation as one or more corresponding output structures; and
updating the display to include the graphical delineation of the one or more output structures.

US Pat. No. 10,600,513

MEDICATION TRACKING

Kit Check, Inc., Washing...

1. A system comprising:an RFID reader configured to query an RFID tag of a label coupled to a medicinal container associated with a drug and receive a unique identifier from the RFID tag, wherein the unique identifier uniquely identifies the medicinal container from other medicinal containers, wherein the label comprises a transparent portion including an adhesive, an RFID portion that includes the RFID tag, a first opaque portion comprising an adhesive and a second opaque portion comprising an adhesive, wherein a length of the transparent portion extends along a length of the RFID portion wherein the first opaque portion and the second opaque portion are detachably coupled to the RFID portion; and
a computing device coupled to the RFID reader and configured to:
receive the unique identifier,
query a remotely located database for drug data of the drug using the unique identifier,
receive drug usage information based at least in part on user input,
determine a drug expiration date of the drug, wherein to determine the drug expiration date, the computing device is configured to:
determine a first expiration date based at least in part on the drug data, wherein the first expiration date corresponds to at least one of an expiration based at least in part on a sealed seal, an expiration based at least in part on refrigeration, or an expiration based at least in part on a vial expiration,
determine a second expiration date based at least in part on the drug usage information, wherein the second expiration date corresponds to at least one of an expiration based at least in part on a broken seal, an expiration based at least in part on non-refrigeration, or an expiration based at least in part on a syringe expiration, and
identify the drug expiration date as the earlier of the first expiration date and the second expiration date, and
update the drug data of the remotely located database to associate the drug expiration date with the unique identifier and mark the drug as at least one of an opened drug, an un-refrigerated drug, or a syringe drug.

US Pat. No. 10,600,512

NETWORK-BASED CALCULATION OF PREVALENCE OF REPEATED MEDICAL IMAGING

Medigate Tech Ltd., Tel-...

1. A system configured to calculate prevalence of repeated medical imaging, comprising:a computer configured to:
receive packets transmitted over a communication network, wherein the packets comprise data related to operation of one or more medical imaging devices at a medical facility;
perform deep packet inspection (DPI) of the packets;
extract, from results of the DPI, values indicative of medical images acquired using the one or more medical imaging devices;
identify, based on the values, instances of repeated images; wherein a repeated image involves acquiring images of the same patient and body part multiple times, utilizing a certain type of medical imaging device within a predetermined period; and
calculate, based on the instances, a value indicative of the prevalence of repeated medical imaging at the medical facility.

US Pat. No. 10,600,511

ACCELERATING HUMAN UNDERSTANDING OF MEDICAL IMAGES BY DYNAMIC IMAGE ALTERATION

International Business Ma...

1. A method for dynamically altering at least one image, comprising:receiving a plurality of data, wherein the received plurality of data includes at least one existing medical image;
determining that one or more user instructions for the received existing image were received;
implementing the one or more user instructions on the received existing medical image; and
altering the received existing medical image based on the one or more implemented user instructions and a medical knowledge base,
wherein in response to determining at least one medical condition in connection with the received plurality of data, determining a plurality of progressions and a plurality of regressions based on the determined medical condition,
wherein the existing medical image is determined based on the determined plurality of progressions and determined plurality of regressions to the determined medical condition,
wherein the user dynamically switches the generated plurality of progressions and the generated plurality of regressions of the received existing medical image.

US Pat. No. 10,600,510

VIDEO CONTENT SEARCHES IN A MEDICAL CONTEXT

Intuitive Surgical Operat...

1. A method comprising:receiving a user command that includes a user description of a medical procedure event of interest, to locate one or more video clips showing the medical procedure event of interest, that is a portion of a medical procedure performed on a medical system, from one or more medical procedure video recordings of the medical procedure;
identifying, from one or more medical system event logs that associate medical system events with user descriptions of medical procedure events, that each is associated with one or more medical procedure video recordings having timestamped frames, that each records occurrences of medical system events, during performance of medical procedures on the medical system, and that each records times of occurrence of medical system events on the medical system, one or more medical system events occurring on the medical system during the medical procedure that correspond to the occurrence of the medical procedure event of interest;
identifying one or more candidate video clips from the one or more medical procedure video recordings having timespans corresponding to timestamps of one or more frames that correspond to the medical procedure of interest and that correspond to one or more timestamps corresponding to each of the one or more identified medical system events occurring on the medical system;
determining, by searching the image data of the one or more candidate video clips for patterns in pixels that are indicative of the medical procedure event of interest, whether each of the one or more candidate video segments is an identified video segment that contains the medical procedure event of interest; and
presenting to a user at least one identified video segment.

US Pat. No. 10,600,509

WEARABLE DEVICE FOR AUTOMATED CONSTRUCTION OF TRAINING PLANS AND METHOD OF USING THE SAME

INTERNATIONAL BUSINESS MA...

1. A system for automatically generating an athletic training schedule, comprising:a wearable device, including one or more sensors for determining a quantity of athletic training performed by a user wearing the wearable device and an athletic performance of the user; and
a processor configured to:
receive the quantity of athletic training performed and the athletic performance data from the wearable device, and to estimate a relationship between the quantity of athletic training performed and an increase in the athletic performance by fitting a known curve relating athletic training performed and an increase in athletic performance to the received quantity of athletic training performed and the athletic performance data from the wearable device, wherein the athletic performance data is an indication of athletic speed or a time required to complete an athletic event;
receive a selection of a competitive target;
estimating a performance level of the selected competitive target;
determine a minimum level of training needed to meet or exceed the estimated performance level, based on the estimated relationship between the quantity of athletic training performed and the athletic performance; and
automatically generate the athletic training schedule based on the determined minimum level of training.

US Pat. No. 10,600,508

TEMPORARY IDENTIFICATION SYSTEMS FOR A HEALTHCARE PROVIDER

BODYGUARD ID, LLC, Kansa...

1. A method for temporarily displaying information about a patient to a healthcare provider, comprising:providing a computing system comprising an input device and a processor in data communication with memory comprising a code generator;
inputting, via the input device, patient specific information into the memory for a first patient;
accessing the code generator to generate a first code for the first patient, the first code being based on the patient specific information for the first patient;
providing a temporary cosmetic ink (TCI) printer having TCI, the TCI printer being in communication with the computing system;
placing the TCI printer on a first area of the first patient;
activating the TCI printer to print the first code on the first area of the first patient;
providing a scanner having a scanning module, the scanner being in communication with the computing system;
providing a display in communication with the scanning module;
placing the scanner at the first area of the first patient;
activating the scanning module of the scanner to read and decode the first code of the first patient to provide a first decoded image;
activating the display;
displaying the first decoded image on the display;
accessing the code generator to generate a customizable indicia; and
activating the TCI printer to print the customizable indicia on the patient.

US Pat. No. 10,600,507

COGNITIVE NOTIFICATION FOR MENTAL SUPPORT

INTERNATIONAL BUSINESS MA...

1. A computer implemented method, comprising:A computer implemented method, comprising:
monitoring, by a computer device, biometric data of a user;
monitoring, by the computer device, social media content of the user; and
determining, by the computer device and based on the biometric data and the social media content, that the user has experienced a changed mental state;
wherein the determining that the user has a changed mental state is based on the monitoring of the biometric data by monitoring the user's heart rate using a heart rate sensor, and by monitoring the social media content by performing a contextual analysis of the social media content to determine a topic of the social media content and a sentiment of the user while engaging in communicating on social media regarding the topic of the social media content,
wherein the sentiment of the user is determined by using at least one selected from a group consisting of: facial analysis using a camera; and tonal analysis using a microphone, and
wherein the determining that the user has experienced a changed mental state comprises:
correlating the social media content and the biometric data; and
determining that the biometric data deviates from a normal range of the heart rate concurrently with the determined topic of the social media content matching a predefined topic and the determined sentiment matching a predefined sentiment,
further comprising:
selecting a caregiver from among a plurality of caregivers based on a biometric feedback loop analysis using the biometric data for the determined topic and an evaluation of past effectiveness of each of the caregivers in providing a positive impact on the user's sentiments in the past with regard to the determined topic, wherein the positive impact is determined by improvements in the user's biometric data and in determined sentiments of the user for the determined topic of the social media content; and
notifying, by the computer device, the selected caregiver of the changed mental state.

US Pat. No. 10,600,506

SYSTEM AND METHOD FOR CREATION OF PERSISTENT PATIENT IDENTIFICATION

IQVIA Inc., Parsippany, ...

1. A method comprising:accessing, with a source-side system, a record of healthcare data, wherein the record includes patient identifying information (PII) associated with one or more persons to whom the healthcare data pertains;
extracting, with the source-side system, portions of PII included in the accessed record of healthcare data;
encrypting, with the source-side system, the extracted portions of PII;
creating, with the source-side system, one or more hashed tokens by applying one or more hashing functions to the extracted portions of PII;
providing, by the source-side system, the one or more hashed tokens to a collection-side system;
determining, by the collection-side system, a match between:
a first hashed token of the one or more hashed tokens received from the source-side system, and
a second hashed token for a previously processed de-identified healthcare record; and
generating, by the collection-side system, a source-specific identifier based on the determined match, wherein the source-specific identifier is generated by:
retrieving an indexing tag that is stored in association with the previously processed de-identified healthcare record; and
encoding the indexing tag to link de-identified healthcare records that correspond to the same person, wherein the indexing tag is encoded,
(i) using a computing rule specific to the source-side system, wherein the computing rule is used to encode the indexing tag with reference to a formatting of the portions of PII extracted from the accessed record of healthcare data, and
(ii) based on a hashing function used to create the first hashed token;
receiving, with the source-side system, the source-specific identifier from the collection-side system; and
storing an association between the source-specific identifier and the accessed record of healthcare data.

US Pat. No. 10,600,505

INTELLIGENT PROMPTING OF PROTOCOLS

MEDICOMP SYSTEMS, INC., ...

1. A method of generating a user interface for use in documenting a patient encounter, the method comprising:automatically identifying, with a computing device, at least one documentation protocol based on at least one element of the patient's medical record;
assigning a score to each documentation protocol identified in the act of identifying documentation protocols; and
generating a user interface including at least one of the identified documentation protocols, the at least one identified documentation protocol identifying at least one medical finding, the at least one identified documentation protocol having a score equal to or greater than a predetermined threshold score.

US Pat. No. 10,600,504

SYSTEMS AND METHODS FOR SORTING FINDINGS TO MEDICAL CODERS

APIXIO, INC., San Mateo,...

1. In a health information management system, a computerized method for sorting findings to users, wherein all steps are performed by a processor, comprising:receiving information about a user, including identification, a role, and historical activity;
receiving a plurality of findings in a plurality of medical records, wherein each finding is assigned a monetary reimbursement value and a label as either suspect or not;
calculating a predictive measure of the user's coding by identifying a rate the coder's coding is recoded during a quality assurance process using the user's historical activity;
calculating the user's speed of coding using the user's historical activity;
calculating the user's value per time responsive to the speed of coding in the user's historical activity and value of the codes found by the user;
selecting one finding from the plurality of findings determined by when the predictive measure is above an accuracy threshold selecting a finding with the suspect label, and when the user's speed is above a speed threshold and the predictive measure is below the accuracy threshold selecting a finding without the suspect label;
providing the selected finding, along with evidence associated with the selected finding, to the user via the interface of the health information management system, wherein the evidence associated with the finding is a subset of processed medical information; and
restricting access to the user to the health information management system when a fatigue indicator for the user is identified, wherein the fatigue indicator includes at least one of duration of continuous coding by the user, and acceleration of an increase in error rates by the user, increasing time spent per coding by the user.

US Pat. No. 10,600,503

SYSTEMS MEDICINE PLATFORM FOR PERSONALIZED ONCOLOGY

GEORGETOWN UNIVERSITY, W...

1. A method for providing data relating to cancer, the method comprising:(a) receiving, into a processing device, raw data of a plurality of data types selected from the group consisting of mRNA expression data, miRNA expression data, metabolomics data, DNA copy number data, and next-generation sequencing;
(b) in the processing device, normalizing the raw data into normalized data of a single data type, wherein said normalization comprises background correction, normalization between arrays, and offset, wherein the offset is calculated to shrink log ratios to zero at lower intensities to reduce variability of the log ratios for low intensity spots;
(c) storing the normalized data in a database, wherein said database is comprised of a correlation of the plurality of data types to clinical outcomes, wherein the normalized data are pre-processed and mapped to existing data structures prior to storage in said database;
(d) receiving a query for the data from a device used by a user into the database;
(e) performing the query through the normalized data in the database to locate the data; and
(f) outputting the data from the database to the device used by the user, wherein said output is comprised of a personalized clinical outcome comprising a cytobands display and a heatmap view.

US Pat. No. 10,600,502

SYSTEMS AND METHODS FOR DISPENSING A STATIN MEDICATION OVER THE COUNTER

AstraZeneca UK Ltd., Lon...

1. A method of managing cholesterol in a human subject with who was previously qualified for delivery of an over the counter statin pharmaceutical composition, the method comprising:a) receiving a re-order request from the subject for the statin pharmaceutical composition, at a computer system having a processor programmed to receive the re-order request;
b) providing a survey for obtaining a plurality of survey results from the subject, via a computer system having a processor programmed to perform the survey, wherein the plurality of survey results comprises:
whether the subject has experienced a muscle irregularity since taking the statin pharmaceutical composition,
whether the subject is pregnant,
whether the subject is taking a medication that interacts with the statin pharmaceutical composition, and
whether the subject had an atherosclerotic cardiovascular event or a heart procedure since last ordering the statin pharmaceutical composition;
c) receiving the plurality of survey results, at a computer system having a processor programmed to receive the survey results;
d) applying an algorithm to the plurality of survey results, via a computer system having a processor programmed to perform the algorithm, wherein the algorithm:
i) runs all or a portion of the plurality of survey results against a plurality of filters, wherein, when a respective filter in the plurality of filters is fired, the re-fulfillment process is terminated or the subject is provided with a warning corresponding to the respective filter, and wherein the plurality of filters comprises:
a pregnancy filter,
a muscle irregularity filter,
a drug interaction filter, and
an atherosclerotic cardiovascular event filter;
ii) obtains, when the re-fulfillment process is not terminated, acknowledgment from the subject for each warning issued to the subject by any filter in the plurality of filters, and
iii) proceeds with the re-fulfillment process when (1) the re-fulfillment process is not already terminated by the firing of a filter in the plurality of filters and (2) the subject has acknowledged each warning associated with each filter in the plurality of filters that was fired and that is associated with a warning, wherein the re-fulfillment process further comprises:
storing an indication in a subject profile of a re-order for the statin pharmaceutical composition,
communicating an over the counter drug facts label for the statin pharmaceutical composition to the subject, and
authorizing, upon confirmation from the subject that the over the counter drug facts label has been received and read, a re-order provision of the statin pharmaceutical composition to the subject, wherein the re-order provision includes a destination of the subject; and
e) administering, upon authorization of the re-order provision, the statin pharmaceutical composition to manage cholesterol in the human subject.

US Pat. No. 10,600,500

BAMBAM: PARALLEL COMPARATIVE ANALYSIS OF HIGH-THROUGHPUT SEQUENCING DATA

The Regents of the Univer...

1. A sequence analysis computer system comprising:a file system storing a first digital sequence file and a different, second digital sequence file wherein each file includes sequence short reads that are aligned with respect to sequence locations; and
at least one computer operating as a sequence analysis engine that is configured to:
identify in the first and second digital sequence files a first common sequence location from the sequence locations;
read from the first digital sequence file a first set of sequence short reads that overlap with the first common sequence location, thereby forming a first pileup stored in a memory;
read from the second digital sequence file a second set of sequence short reads that overlap with the first common sequence location, thereby forming a second pileup stored in the memory;
identify at least one variant as a difference among inferred bases at the first common sequence location as a function of the sequence short reads in the first pileup and the sequence short reads in the second pileup that overlap the first common sequence location by optimizing likelihoods of the inferred bases based on observed bases of the first pileup and the second pileup at the first common sequence location; and
output the at least one variant in a file as a sequence difference between the first digital sequence file and the second digital sequence file.

US Pat. No. 10,600,498

REDUCED FOOTPRINT FUSE CIRCUIT

Micron Technology, Inc., ...

1. A memory device, comprising:a memory bank accessible via a plurality of memory addresses; and
a fuse array comprising a plurality of fuse banks, wherein a first fuse bank of the plurality of fuse banks comprises a first fuse circuit, wherein the first fuse circuit comprises:
a first fuse latch comprising first input circuitry, wherein the first fuse latch is configured to store a first bit of a first memory address of the plurality of memory addresses received at the first input circuitry; and
a first matching circuit communicatively coupled to the first input circuitry, wherein the first matching circuit is configured to:
receive, at the first input circuitry, a first bit of a second memory address of the plurality of memory addresses; and
output, at output circuitry of the first matching circuit, a first comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.

US Pat. No. 10,600,497

TIMING-DRIFT CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A dynamic random access memory (DRAM) chip having a memory core, the memory core including a plurality of storage cells, the DRAM chip comprising:a signaling interface to receive an instruction from a memory controller that is separate from the DRAM chip;
an oscillator circuit to generate an oscillating signal; and
a counter circuit coupled to the oscillator circuit, wherein, in response to the instruction, the counter circuit is to begin a count of a number of edges of the oscillating signal, and wherein the counter circuit is to count the number of edges of the oscillating signal during a measurement duration period.

US Pat. No. 10,600,496

MODIFYING MEMORY BANK OPERATING PARAMETERS

Micron Technology, Inc., ...

1. A method, comprising:determining that an operating parameter of a memory bank of a plurality of memory banks is below a threshold;
storing, in a first fuse set that is coupled with the memory bank, first information for adjusting the operating parameter of the memory bank based at least in part on the determining;
adjusting the operating parameter for the memory bank based at least in part on the first information stored in the first fuse set; and
adjusting the operating parameter for the plurality of memory banks in a memory system based at least in part on second information stored in a second fuse set.

US Pat. No. 10,600,495

PARALLEL MEMORY SELF-TESTING

TEXAS INSTRUMENTS INCORPO...

1. Circuitry to perform parallel testing of a plurality of memories, comprising:a plurality of local adapters; and
a controller to generate a sequence of commands to be applied to one or more of the plurality of local adapters, each given command of the sequence of commands including expected data, and a command address;
each local adapter being coupled with the controller and with an associated memory of the plurality of memories to:
translate the given command to a memory type of the associated memory;
map the command address to a local address of the associated memory;
transfer the expected data to the local address of the associated memory; and
provide test results to the controller according to read data from the local address of the associated memory and the expected data of the given command.

US Pat. No. 10,600,494

METHODS AND APPARATUSES FOR SELF-TRIMMING OF A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a semiconductor device comprising a self-trimming circuit configured to receive a reference voltage and a test command signal, the self-trimming circuit configured to convert the reference voltage to a target voltage based on the test command signal and further configured to adjust a voltage trim code until an internal voltage matches the target voltage to determine a trim level associated with the internal voltage.

US Pat. No. 10,600,493

SEMICONDUCTOR DEVICE INCLUDING MULTIPLE-INPUT SHIFT REGISTER CIRCUIT

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and
a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.

US Pat. No. 10,600,492

HIGH STABILITY SHIFT REGISTER WITH ADJUSTABLE PULSE WIDTH

INT TECH CO., LTD., Hsin...

1. A high stability shift register with adjustable pulse width, comprising:a first signal processor, configured to receive a first voltage and generate a first signal and a second signal in response to a first sub-control signal and a second sub-control signal;
a second signal processor, configured to receive the first voltage, and generate a third signal and a fourth signal in response to a third sub-control signal, the first signal and the second signal; and
a third signal processor, configured to receive the first voltage and a second voltage having a voltage level different from that of the first voltage and generate an output signal in response to the third signal and the fourth signal;
wherein the first signal processor comprises:
a first transistor, having a first source terminal that is applied with the first voltage and a first gate terminal that is applied with the first sub-control signal;
a sixth transistor, having a sixth source terminal that is applied with the first sub-control signal and a sixth gate terminal that is applied with the second sub-control signal; and
a capacitor, having a first electrode that is applied with the second sub-control signal and a second electrode that is connected with a first node electrically connected with a first drain terminal of the first transistor,
wherein the first signal is outputted from the first node, and the second signal is outputted from a sixth drain terminal of the sixth transistor.

US Pat. No. 10,600,491

METHOD FOR MANAGING DATA BLOCKS AND METHOD OF DATA MANAGEMENT FOR DATA STORAGE DEVICE

SILICON MOTION, INC., Jh...

1. A method of data management of a data storage device, comprising steps of:reading a data from a data programming unit of a data erase unit;
increasing and storing an access count;
determining whether the access count is greater than an access count threshold;
when it is determined that the access count is greater than an access count threshold, storing the data into a data programming unit of another data erase unit;
determining whether an erase count is greater than an erase count threshold; and
when it is determined that the erase count is greater than the erase count threshold, decreasing the access count threshold of the data erase unit and increasing the erase count threshold of the data erase unit;
wherein the access count threshold and the erase count threshold of the data erase unit are updated in negative correlation;
wherein the access count threshold of the data erase unit is updated by multiplying a predetermined access count threshold by a set ratio, where the set ratio is obtained according to a proportion between the erase count and an average erase endurance;
wherein the erase count threshold of the data erase unit is updated in a proportion of the average erase endurance.

US Pat. No. 10,600,490

PROGRAMMING OF MEMORY CELLS IN THREE-DIMENSIONAL MEMORY DEVICES

YANGTZE MEMORY TECHNOLOGI...

1. A three-dimensional (3D) memory device, comprising:a NAND memory string extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series; and
a peripheral circuit configured to program the memory cells based on incremental step pulse programming (ISPP), wherein different verification voltages of the ISPP are applied to at least two of the memory cells,
wherein a first verification voltage applied to a first one of the memory cells is smaller than a second verification voltage applied to a second one of the memory cells that is above the first one of the memory cells in the NAND memory string, and
verification voltages applied to each of the memory cells increase from bottom to top of the NAND memory string.

US Pat. No. 10,600,489

MEMORY SYSTEM, READING METHOD, PROGRAM, AND MEMORY CONTROLLER

TOSHIBA MEMORY CORPORATIO...

1. A memory system, comprising:a plurality of memory cells capable of having data written therein at a plurality of write levels; and
a memory controller configured to detect first data of the plurality of memory cells, then apply a first voltage that is lower than a voltage used for writing the data, to the plurality of memory cells, detect second data of the plurality of memory cells after the first voltage has been applied, and estimate a write level for the data written to the plurality of memory cells based on a comparison of the first data and the second data.

US Pat. No. 10,600,488

NON-VOLATILE MEMORY DEVICE INCLUDING DECOUPLING CIRCUIT

Samsung Electronics Co., ...

1. A method of sensing a memory cell comprised in a non-volatile memory cell array, the method comprising:precharging a first node to a precharge voltage, the precharge voltage being greater than a ground voltage and less than a supply voltage;
discharging a first decoupling capacitor to the ground voltage, the first decoupling capacitor arranged so the first node is between the memory cell and the first decoupling capacitor; and
developing the first node to a develop voltage through charge sharing between the first node and the first decoupling capacitor, the develop voltage being greater than the ground voltage and less than the precharge voltage.

US Pat. No. 10,600,487

METHODS OF ERASING DATA IN NONVOLATILE MEMORY DEVICES AND NONVOLATILE MEMORY DEVICES PERFORMING THE SAME

Samsung Electronics Co., ...

1. A method of erasing data in a nonvolatile memory device, comprising:applying an erase voltage to an erase source terminal of a memory block having a plurality of memory cells therein, which are stacked in a vertical direction relative to an underlying substrate;
applying a first voltage to a first selection line among a plurality of selection lines in the memory block, the first voltage being higher than the erase voltage, the first selection line being disposed closest to the erase source terminal among the plurality of selection lines and being used for selecting the memory block as an erase target block; and
applying a second voltage to a second selection line among the plurality of selection lines, the second voltage being lower than the erase voltage, the second selection line being disposed farther from the erase source terminal than the first selection line and being used for selecting the memory block as the erase target block.

US Pat. No. 10,600,486

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

SK hynix Inc, Gyeonggi-d...

1. A semiconductor memory device comprising:a memory block including a plurality of memory cell strings;
a peripheral circuit configured to perform an erase operation on the memory block; and
a control logic configured to control the peripheral circuit to apply operation voltages including first and second source line control voltages, a pre-erase voltage, and an erase voltage to a source line of the memory block sequentially to form a trap,
wherein the pre-erase voltage is configured to be applied to the source line to generate a gate induced drain leakage current,
wherein the erase voltage is configured to be applied to the source line to control memory cells of the memory block from a floating state to a ground voltage state, and
wherein the first source line control voltage has a greater level than the second source line control voltage.

US Pat. No. 10,600,485

MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS VERIFY OPERATIONS USING VARIOUS VERIFY VOLTAGES

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:a semiconductor memory device that includes a plurality of memory cells and a word line, the plurality of memory cells including a page of memory cells, the plurality of memory cells comprising first, second, third, and fourth memory cells, the word line being electrically connected to gates of the first, second, third, and fourth memory cells; and
a controller configured to read data from the page of memory cells and issue a first write command or a second write command to the semiconductor memory device, wherein
the semiconductor memory device, in response to the issued first write command, executes a first program operation on the page of memory cells and a first verify operation on the memory cells of the page using a first verify voltage, and
the semiconductor memory device, in response to the issued second write command, executes a second program operation on a first subset of the memory cells of the page, the first subset of the memory cells including the first and second memory cells, and a second verify operation on the first subset of the memory cells using a second verify voltage when the issued second write command corresponds to the first subset of the memory cells, and executes the second program operation on a second subset of the memory cells of the page, the second subset of the memory cells including the third and fourth memory cells, and a third verify operation on the second subset of the memory cells using a third verify voltage when the issued second write command corresponds to the second subset of the memory cells.

US Pat. No. 10,600,484

SYSTEM AND METHOD FOR MINIMIZING FLOATING GATE TO FLOATING GATE COUPLING EFFECTS DURING PROGRAMMING IN FLASH MEMORY

Silicon Storage Technolog...

1. A memory device, comprising:an array of non-volatile memory cells, wherein each of the non-volatile memory cells includes a floating gate, and
a controller configured to:
identify programming values associated with incoming data, wherein each of the programming values is associated with a relative amount of electrons to be placed onto one of the floating gates;
perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

US Pat. No. 10,600,483

TERNARY CONTENT ADDRESSABLE MEMORY WITH MATCH LINE CIRCUIT FOR CONTROLLING POTENTIAL OF MATCH REALIZING HIGHER SPEED OF SEARCH ACCESS

RENESAS ELECTRONICS CORPO...

1. A content addressable memory, comprising:a plurality of memory cells;
a match line coupled to the plurality of memory cells;
a search line coupled to each of the plurality of memory cells;
a match line output circuit coupled to the match line; and
a potential changing circuit coupled to the match line and changing the potential of the match line,
wherein the potential changing circuit comprises:
a first P-channel MOS transistor including a gate coupled to the match line, a source supplied with a first reference potential, and a drain coupled to a common coupling node;
a first N-channel MOS transistor including a gate coupled to the match line and a drain coupled to the common coupling node;
a second N-channel MOS transistor including a drain coupled to a source of the first N-channel MOS transistor and a source supplied with a second reference potential lower than the first potential;
a second P-channel MOS transistor including a gate coupled to the common coupling node, a source supplied with the first reference potential, and a drain coupled to the match line;
a third N-channel MOS transistor including a gate coupled to the common coupling node and a drain coupled to the match line; and
a fourth N-channel MOS transistor including a drain coupled to a source of the third N-channel MOS transistor and a source supplied with the second potential.

US Pat. No. 10,600,482

QUANTUM MEMORY DEVICE

OXFORD UNIVERSITY INNOVAT...

1. A quantum memory device for storing one or more modes of electromagnetic radiation, the quantum memory device comprising:an atomic ensemble comprising atomic valence electrons having a first state, a second state and a third state, wherein the second state has a higher energy than, and is linked to, the first state by an atomic transition, and the third state has a higher energy than, and is linked to, the second state by one or more atomic transitions;
a signal source of electromagnetic radiation arranged to generate one or more modes of electromagnetic radiation to be stored having a frequency corresponding to an off-resonant atomic transition between the first state and the second state of atomic valence electrons in the atomic ensemble, wherein the one or more modes of electromagnetic radiation from the signal source are arranged to be incident upon the atomic ensemble to stimulate off-resonant transitions of the atomic valence electrons in the atomic ensemble between the first state and the second state, and wherein the signal source electromagnetic radiation has a bandwidth of greater than 1 GHz;
one or more control sources of electromagnetic radiation each arranged to generate electromagnetic radiation having a frequency corresponding to an off-resonant atomic transition from the one or more atomic transitions linking the second state and the third state of atomic valence electrons in the atomic ensemble, wherein the electromagnetic radiation from the one or more control sources is arranged to be incident upon the atomic ensemble to stimulate off-resonant transitions of the atomic valence electrons in the atomic ensemble between the second state and the third state, and wherein the electromagnetic radiation from each of the one or more control sources has a bandwidth of greater than 1 GHz; and
wherein the quantum memory device is arranged such that on incidence of one or more modes of electromagnetic radiation from the signal source and electromagnetic radiation from each of the one or more control sources to the atomic ensemble, a coherent excitation of the transition between the first state and the third state is created that stores the one or more modes of electromagnetic radiation from the signal source in the atomic ensemble, and subsequent incidence of electromagnetic radiation from each of the one or more control sources upon the atomic ensemble stimulates emission of the one or more stored modes of electromagnetic radiation from the atomic ensemble.

US Pat. No. 10,600,481

APPARATUSES INCLUDING MEMORY CELLS AND METHODS OF OPERATION OF SAME

Micron Technology, Inc., ...

1. A method comprising:applying first and second portions of a programming pulse across a memory cell to program a logic state to a memory element of the memory cell based, at least in part, on a current or voltage magnitude of the programming pulse, the first and second portions applied, respectively, in first and second polarities across the memory cell;
applying a read pulse across the memory cell in a first polarity; and
providing the logic state of the memory element responsive to the read pulse applied across the memory cell in the first polarity.

US Pat. No. 10,600,480

AUTO-REFERENCED MEMORY CELL READ TECHNIQUES

Micron Technology, Inc., ...

1. A method, comprising:initializing a first counter and a second counter in a controller coupled with a memory array that comprises a first portion of memory cells and a second portion of memory cells;
activating a first subset of the first portion of memory cells by applying a first read voltage to the memory array and a second subset of the second portion of memory cells by applying a second read voltage to the memory array;
updating the first counter to a first value based at least in part on activating the first subset of the first portion of memory cells and the second counter to a second value based at least in part on activating the second subset of the second portion of memory cells; and
reading one or more memory cells of the first portion of memory cells based at least in part on updating the first counter and the second counter.

US Pat. No. 10,600,479

DEVICE FOR SWITCHING BETWEEN DIFFERENT READING MODES OF A NON-VOLATILE MEMORY AND METHOD FOR READING A NON-VOLATILE MEMORY

STMICROELECTRONICS S.R.L....

1. A memory device, comprising:a memory array comprising a first sector and a second sector, each of the first sector and the sector comprising a respective plurality of memory cells arranged in rows and columns, a respective plurality of word lines, and a respective plurality of local bit lines;
a plurality of main bit lines selectively coupled to local bit lines;
a first sense amplifier and a second sense amplifier; and
a routing circuit arranged between the plurality of main bit lines and the first sense amplifier and the second sense amplifier, wherein the routing circuit comprises:
a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier;
a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier;
a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier;
a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier;
a lower coupling circuit coupling a second lower main bit line to a second input of the first sense amplifier; and
an upper coupling circuit coupling a second upper main bit line to a second input of the second sense amplifier.

US Pat. No. 10,600,478

MULTI-BIT CELL READ-OUT TECHNIQUES FOR MRAM CELLS WITH MIXED PINNED MAGNETIZATION ORIENTATIONS

Spin Memory, Inc., Fremo...

1. A memory device comprising:an array of Multi-Bit Cells (MBCs), the MBCs each including a plurality of cell elements having different sets of state parameter values, wherein a pinned magnetization polarization of a first cell of the plurality of cell elements is opposite a pinned magnetization polarization of a second cell of the plurality of cell elements;
one or more memory circuits configured to;
sequentially apply different successive sets of state programming conditions to a selected plurality of the MBCs, wherein a respective set of state programming conditions programs a corresponding one of the plurality of cell elements to a respective state parameter value;
determine, after applying each of the set of programming conditions, a state change result for the selected plurality of the MBCs; and
determine a read state of the selected plurality of MBCs based on the determined state change results.

US Pat. No. 10,600,477

COUPLING COMPENSATION CIRCUITRY

Arm Limited, Cambridge (...

1. An integrated circuit, comprising:a bitcell coupled to a bitline;
a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver;
a first signal line coupled to a gate of the column multiplexer device that provides a first transition signal;
a second signal line coupled to an input of the write driver that provides a second transition signal, wherein the second transition signal is substantially similar to the first transition signal; and
a coupling device coupled between the first signal line and the second signal line.

US Pat. No. 10,600,476

ROW BASED MEMORY WRITE ASSIST AND ACTIVE SLEEP BIAS

Intel Corporation, Santa...

1. An apparatus comprising:an interconnect comprising a poly extending in a first direction;
a plurality of power supply rails extending in a second direction, wherein the second direction is parallel to the first direction, wherein the plurality of power supply rails include ground power supply rails; and
a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, and wherein the memory array comprises bit-cells that are organized such that there are no gap bit-cells in the array.

US Pat. No. 10,600,475

METHOD AND APPARATUS FOR STORING AND ACCESSING MATRICES AND ARRAYS BY COLUMNS AND ROWS IN A PROCESSING UNIT

1. A matrix space comprising:a first array of storage cells, wherein the first array of storage cells comprises:
a plurality of row bit lines comprising a set of row values;
a plurality of row logic switches controlled by one or more row address lines;
a plurality of column bit lines comprising a set of column values; and
a plurality of column logic switches controlled by one or more column address lines, wherein the plurality of row bit lines are coupled to the storage cells via the plurality of row logic switches, and wherein the plurality of column bit lines are coupled to the storage cells via the plurality of column logic switches; and
logic to perform one or more operations with one or more selected column bit lines, selected row bit lines, and selected storage cells, wherein writing via the plurality of row bit lines and writing via the plurality of column bit lines occur into separate and non-intersecting selection of the selected storage cells.

US Pat. No. 10,600,474

WRITE ASSIST

GLOBALFOUNDRIES INC., Gr...

1. A device, comprising:a core comprising a memory array, the memory array comprising memory cells having bitlines, the memory array being arranged in columns, wherein the core includes a metallization layer comprising connections to the memory array, and wherein the metallization layer is devoid of memory cells;
digit lines connected to the bitlines of a column of the memory array;
a write driver connected to the digit lines;
a write assist circuit connected to the write driver; and
a wire bridge located in the metallization layer of the core connecting the write assist circuit to the write driver,
the write assist circuit comprising:
a first precharge transistor connected to a first digit line, the first precharge transistor maintaining a first voltage on the first digit line prior to write operations,
a second precharge transistor connected to a second digit line, the second precharge transistor maintaining a second voltage on the second digit line prior to write operations,
a first boost signal connected to the first digit line, the first boost signal providing a first boost voltage to the first digit line during write operations, and
a second boost signal connected to the second digit line, the second boost signal providing a second boost voltage to the second digit line during write operations.

US Pat. No. 10,600,473

APPARATUSES AND METHODS TO PERFORM LOGICAL OPERATIONS USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. An apparatus, comprising:sensing circuitry including a sense amplifier and a compute component;
selection logic circuitry coupled to the sense amplifier via a pair of complementary sense lines and coupled to a first compute component storage location via a first pair of complementary signal lines and a second compute component storage location via a second pair of complementary signal lines; and
a controller coupled to the sensing circuitry and selection logic circuitry and configured to cause performance of a logical operation between an operand in the first compute component storage location or the second compute component storage location and an operand sensed by the sense amplifier.

US Pat. No. 10,600,472

SYSTEMS AND METHODS FOR MEMORY CELL ARRAY INITIALIZATION

Micron Technology, Inc., ...

1. An apparatus comprising:at least one mode register configured to enable an array reset mode;
a memory cell array including one or more sense amplifiers, each of the one or more sense amplifier including at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line;
control logic coupled to the memory cell array, and in communication with the at least one mode register, the control logic configured to:
drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage, wherein the bit-line precharge voltage corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines, wherein the at least one mode register is further configured to enable a self-refresh mode, wherein the control logic is further configured to generate, in response to the self-refresh mode being enabled, an internal self-refresh pulse, wherein the internal self-refresh pulse causes a current row address of the memory cell array to be activated; and
a refresh counter comparator, wherein the at least one mode register further comprises a valid data register, and wherein the refresh counter comparator is configured to set, at a first row address of the refresh counter, the valid data register to a first state indicating that all memory cells of the memory cell array have not been reset, and wherein when the refresh counter outputs the first row address a second time, resetting the valid data register to a second state indicating that all memory cells of the memory cell array have been reset and resetting the mode register.

US Pat. No. 10,600,471

SEMICONDUCTOR DEVICE PERFORMING ROW HAMMER REFRESH OPERATION

Micron Technology, Inc., ...

1. An apparatus comprising:a memory cell array including a plurality of word lines each coupled to a plurality of memory cells; and
a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command,
wherein a first number of the plurality of word lines are selected in response to the first internal signal, and
wherein a second number of the plurality of word lines are selected in response to the second internal signal, the second number is smaller than the first number.

US Pat. No. 10,600,470

MEMORY DEVICE AND MEMORY SYSTEM PERFORMING A HAMMER REFRESH OPERATION AND ASSOCIATED OPERATIONS

SAMSUNG ELECTRONICS CO., ...

1. A memory system comprising:a memory controller configured to determine and provide a hammer address, wherein the hammer address is an address that has an activation number or frequency greater than a predetermined threshold; and
a memory device configured to generate a hammer refresh signal representing a timing for a hammer refresh operation to refresh a first row of the memory device that is physically adjacent to a second row of the memory device corresponding to the hammer address, and configured to perform the hammer refresh operation using the hammer address provided from the memory controller and the hammer refresh signal generated by the memory device.

US Pat. No. 10,600,469

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising a memory module comprising:a first memory cell comprising a first memory node;
a second memory cell comprising a second memory node;
a selection transistor; and
a first wiring,
wherein:
one end of the first memory cell is electrically connected to the first wiring through the selection transistor,
the other end of the first memory cell is electrically connected to one end of the second memory cell,
the other end of the second memory cell is electrically connected to the first wiring,
each of the first memory node and the second memory node is configured to retain a voltage as a signal,
when the selection transistor is on, the first memory node is configured so that the voltage retained in the first memory node is rewritten through the selection transistor by a signal supplied to the first wiring, and the second memory node is configured so that the voltage retained in the second memory node is rewritten through the selection transistor and the first memory node by a signal supplied to the first wiring, and
when the selection transistor is off, the first memory node is configured so that the voltage retained in the first memory node is rewritten through the second memory node by a signal supplied to the first wiring, and the second memory node is configured so that the voltage retained in the second memory node is rewritten by a signal supplied to the first wiring.

US Pat. No. 10,600,468

METHODS FOR OPERATING FERROELECTRIC MEMORY CELLS EACH HAVING MULTIPLE CAPACITORS

WUXI PETABYTE TECHNOLOGIE...

1. A method for writing a ferroelectric memory cell comprising a transistor and N capacitors, where N is a positive integer greater than 1, wherein the transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective one of N plate lines in parallel, the method comprising:applying a plate line signal pulsed between 0 V and a supply voltage (Vdd) of the ferroelectric memory cell to each of the N plate lines according to a plate line time sequence; and
applying a bit line signal pulsed between 0 V and the Vdd to the bit line according to a bit line time sequence to write a valid state of data into the N capacitors, wherein
the data consists of N+1 valid states that can be written into the N capacitors;
the valid states of the data are determined based on the plate line time sequence; and
the bit line time sequence is determined based on the valid state of the data written into the N capacitors.

US Pat. No. 10,600,467

OFFSET COMPENSATION FOR FERROELECTRIC MEMORY CELL SENSING

Micron Technology, Inc., ...

1. A method, comprising:activating a first switching component to couple a digit line with a virtual ground;
deactivating a second switching component to discharge a first charge of an offset capacitor to a gate of a third switching component based at least in part on activating the second switching component;
activating the third switching component to couple the digit line with a sense component based at least in part on discharging the first charge of the offset capacitor; and
transferring a second charge stored by a memory cell to the sense component based at least in part on activating the third switching component.

US Pat. No. 10,600,466

RESISTIVE MEMORY DEVICE HAVING REDUCED CHIP SIZE AND OPERATION METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a voltage generator generating a write word line voltage according to activation of a write enable signal;
a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage;
a word line power path connected to the switch circuit to receive the output word line voltage; and
a word line driver driving a word line of the memory device according to a voltage applied to the word line power path, wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable signal in response to the received write command,
wherein at least one read command is further received during the activation period of the write enable signal, and
wherein only a read command is received during a deactivation period of the write enable signal.

US Pat. No. 10,600,465

SPIN-ORBIT TORQUE (SOT) MAGNETIC MEMORY WITH VOLTAGE OR CURRENT ASSISTED SWITCHING

SPIN MEMORY, INC., Wilmi...

1. A magnetic storage device, comprising:a first wire extending along a first direction;
a plurality of spin orbit torque magnetic random access memory (SOT-MRAM) devices, each of the plurality of SOT-MRAM devices disposed at a respective position along the first wire;
write circuitry, including:
a first transistor coupled to the first wire to apply a first write current along the first wire in the first direction; and
a second transistor to select an individual SOT-MRAM device and apply a second write current to the individual SOT-MRAM device concurrently with the application of the first write current, wherein the second write current is along an axis of the individual SOT-MRAM device; and
readout circuitry to read a data value stored by the individual SOT-MRAM device.

US Pat. No. 10,600,464

SEMICONDUCTOR STORAGE DEVICE, DRIVING METHOD, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A semiconductor storage device, comprising:at least one or more selection transistors;
a resistance change element, wherein one end of the resistance change element is connected to a bit line and the other end of the resistance change element is connected to a drain terminal of a selection transistor, wherein a resistance value of the resistance change element changes in response to flowing a current of a predetermined value or larger through the resistance change element; and
a write control unit connected to a connection point between the selection transistor and the resistance change element, wherein the write control unit controls the current flowing through the resistance change element when data is written in the resistance change element, wherein the write control unit is a write control transistor, wherein a gate terminal of the write control transistor is short-circuited to one of a source terminal and a drain terminal of the write control transistor, wherein the one of a source terminal and a drain terminal of the write control transistor is connected to the connection point between the selection transistor and the resistance change element and the other of a source terminal and a drain terminal of the write control transistor is connected to a write control wiring, and wherein the selection transistor and the write control transistor have polarities that are different from each other.

US Pat. No. 10,600,463

MAGNETIC STORAGE DEVICE HAVING A MEMORY CELL INCLUDING A MAGNETORESISTIVE EFFECT ELEMENT AND A SELECTOR WHICH INCLUDES TITANIUM (TI), GERMANIUM (GE) AND TELLURIUM (TE)

TOSHIBA MEMORY CORPORATIO...

1. A magnetic storage device comprising:a first memory cell including a magnetoresistive effect element and a selector, the selector including titanium (Ti), germanium (Ge) and tellurium (Te).

US Pat. No. 10,600,462

BITCELL STATE RETENTION

Intel Corporation, Santa...

1. An apparatus comprising:a magnetoresistive random access memory (MRAM) array having first and second rows of bitcells, respective bitcells separately including a ferromagnetic device having a polarization that indicates a first or a second bit value storage state;
a first word line coupled with bitcells of the first row;
a second word line coupled with bitcells of the second row; and
control circuitry including logic, the logic to:
cause an access to a bitcell of the first row, the access to generate a first magnetic field;
cause a second magnetic field to be generated in the bitcell of the second row to compensate for the first magnetic field to mitigate an impact of the first magnetic field on the bit value storage state of the bitcell of the second row;
generate a first word line control signal of a first polarity on the first word line, the first word line control signal to cause the first magnetic field;
generate a word line compensation control signal of a second polarity on the second word line to cause the second magnetic field to be generated in the bitcell of the second row to compensate for the first magnetic field;
determine whether the access to the bitcell of the first row causes a count of consecutive accesses to the bitcell of the first row to exceed a threshold value; and
suspend one or more subsequent accesses to the bitcell of the first row for a suspension interval if the count exceeds the threshold value, to mitigate an impact of the first magnetic field on a bit value storage state of the bitcell of the second row.

US Pat. No. 10,600,461

MAGNETIC DOMAIN WALL DISPLACEMENT TYPE MAGNETIC RECORDING ELEMENT AND MAGNETIC RECORDING ARRAY

TDK CORPORATION, Tokyo (...

1. A magnetic domain wall displacement type magnetic recording element comprising:a first ferromagnetic layer including a ferromagnetic material;
a magnetic recording layer configured to extend in a first direction crossing a laminating direction of the first ferromagnetic layer and including a magnetic domain wall; and
a nonmagnetic layer sandwiched between the first ferromagnetic layer and the magnetic recording layer,
wherein the first ferromagnetic layer has a magnetic flux supply region at least at a first end in the first direction, and
a second ferromagnetic layer exhibiting a magnetization state of the magnetic recording layer is provided between the magnetic recording layer and the nonmagnetic layer.