US Pat. No. 10,461,334

GAS DIFFUSION ELECTRODE AND FUEL CELL

TORAY INDUSTRIES, INC., ...

1. A gas diffusion electrode comprising a microporous layer on at least one surface of an electrically conductive porous substrate, whereinthe microporous layer includes a first microporous layer that is in contact with the electrically conductive porous substrate, and a dense layer that is in contact with the first microporous layer, the dense layer having a thickness of 1 ?m or more, and
an average number density B of pores having a pore diameter of 0.15 ?m or more and 1 ?m or less in the dense layer is 1.3A or more where A is an average number density of pores having a pore diameter of 0.15 ?m or more and 1 ?m or less in the microporous layer disposed on at least one surface of the electrically conductive porous substrate.

US Pat. No. 10,461,333

ELECTROCHEMICAL CELLS COMPRISING FIBRIL MATERIALS

Sion Power Corporation, ...

1. An electrochemical cell, comprising:a negative electrode;
a positive electrode; and
an electrolyte in electrochemical communication with the negative electrode and the positive electrode,
wherein the electrolyte comprises a plurality of fibrils comprising cellulose or a cellulose derivative having maximum cross-sectional diameters of less than about 100 nanometers and aspect ratios of at least about 10:1.

US Pat. No. 10,461,332

GRAPHENE AND POWER STORAGE DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

6. A power storage device comprising:an electrolyte comprising lithium salt; and
an electrode comprising:
a current collector; and
an active material layer over the current collector, the active material layer comprising:
a particle of an active material; and
a graphene comprising hydrogen atoms, carbon atoms and oxygen atoms,
wherein the graphene is a one-atom-thick sheet or a stack of 2 to 100 layers of the sheet,
wherein the graphene has a two-dimensional structure and has a sheet-like shape,
wherein a proportion of the carbon atoms measured by X-ray photoelectron spectroscopy is higher than or equal to 80% and lower than 90%,
wherein a proportion of the oxygen atoms measured by X-ray photoelectron spectroscopy is higher than or equal to 10% and lower than 20%,
wherein a sum of the proportion of the carbon atoms and the proportion of the oxygen atoms is lower than 100%,
wherein, in bonds of the carbon atoms, a proportion of sp2-bonded carbon atoms among the carbon atoms measured by X-ray photoelectron spectroscopy is higher than or equal to 50% and lower than or equal to 80%, and
wherein the graphene and the particle of the active material are randomly dispersed in the active material layer.

US Pat. No. 10,461,330

POSITIVE-ELECTRODE ACTIVE MATERIAL FOR SECONDARY CELL, AND METHOD FOR MANUFACTURING SAME

TAIHEIYO CEMENT CORPORATI...

1. A positive-electrode active material for a secondary cell, comprising a compound particle represented by the following formula (A):LiFeaMnbM1cPO4  (A)
wherein in formula (A), M1 represents Mg, Ca, Sr, Y, Zr, Mo, Ba, Pb, Bi, La, Ce, Nd or Gd; and a, b and c represent numbers satisfying 0.01?a?0.99, 0.01?v?0.99, and 0?c?0.3, a and b are not simultaneously 0, and 2a+2b+(valence of M1)×c=2 is satisfied; and
carbon,
wherein the carbon is derived from a cellulose nanofiber and is supported on the compound particle,
wherein an amount of the carbon derived from the cellulose nanofiber and supported on the compound particle is from 0.3 to 6 mass %, and
the positive-electrode active material is a product obtained by pyrolyzing a granule S comprising the compound particle and the cellulose nanofiber and having a particle size (D50value) of 1 to 15 ?m.

US Pat. No. 10,461,329

HIGH CAPACITY PHOSPHOROUS SULFIDE BASED CATHODE MATERIALS FOR MAGNESIUM BATTERIES

1. An electrode material, comprising:a composite of formula (I)
MxPySz  (I)
wherein M is at least one metal selected from the group consisting of Mg, Ag, Cu, Fe, Ni, Co, Cr, and Mn;
x is independently a number from 2-10,
y is independently a number from 1-15, and
z is independently a number from 4-30; and
wherein the composite, the material, or both do not comprise an oxide species.

US Pat. No. 10,461,328

CATHODE ACTIVE MATERIAL USED FOR LITHIUM ION SECONDARY BATTERY AND LITHIUM ION SECONDARY BATTERY USING SAME

HITACHI METALS, LTD., To...

1. A cathode active material used for a lithium ion secondary battery, comprising a plurality of secondary particles formed via agglomeration of a plurality of primary particles of a lithium transition metal composite oxide, whereinspreading resistance distributions of the secondary particles observed in cross-sections at three selected positions of the cathode active material are measured, and average values of spreading resistance of the secondary particles observed in the cross sections are calculated;
the calculated three average values of spreading resistance are further averaged; and
when an averaged value thus obtained is defined as a value of spreading resistance of the cathode active material, the averaged value thus defined is 1.0×106 ?/cm or more and 1.0×1010 ?/cm or less.

US Pat. No. 10,461,327

POSITIVE ELECTRODE FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A positive electrode for a non-aqueous electrolyte secondary battery, the positive electrode comprising:a positive current collector;
a coating layer including graphite, the coating layer coating the positive current collector;
a positive active material having a composition represented by Chemical Formula 1; and
a conductive auxiliary agent having a BET specific surface area of about 39 m2/g to about 215 m2/g,
LixNiyMn2-y-zMzO4  Chemical Formula 1
wherein,
M is at least one metal element selected from a transition metal, aluminum, magnesium, gallium, indium, and lanthanum, the transition metal being a transition metal other than nickel (Ni) or manganese (Mn), and
x, y, and z are within the ranges: 0.02?x?1.10, 0.25?y?0.6, and 0.0?z?0.10.

US Pat. No. 10,461,326

NEGATIVE ELECTRODE INCLUDING SIOX PARTICLES HAVING CARBON COATING, CARBONACEOUS ACTIVE MATERIAL PARTICLES, AND COMPOUND HAVING CARBOXYL OR HYDROXYL GROUP AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERIES

SANYO Electric Co., Ltd.,...

1. A negative electrode for nonaqueous electrolyte secondary batteries comprising a negative electrode current collector and a negative electrode mixture layer disposed on the current collector, whereinthe negative electrode mixture layer includes SiOx 0.5?x?1.5 particles having a carbon coating on a particle surface, carbonaceous active material particles, and a compound having at least one of a carboxyl group and a hydroxyl group and having an average number of etherifying agent moieties present per unit molecule of not more than 0.8, and
the carbon coating includes a first coating disposed on the surface of the SiOx particles and a second coating disposed on the first coating and including carbon having higher crystallinity than the carbon forming the first coating, wherein a thickness of the second coating is 10 to 200 nm.

US Pat. No. 10,461,325

SILICON-CARBIDE REINFORCED CARBON-SILICON COMPOSITES

Nanostar, Inc., New Orle...

1. A particulate comprising:a carbon matrix carrying a plurality of silicon nanocrystals and a plurality of SiC nanofibers;
wherein the carbon matrix is the thermolysis product of a carbon matrix precursor.

US Pat. No. 10,461,324

ENERGY STORAGE DEVICES

CF TRAVERSE LLC, San Fra...

1. An electrode comprising:a conductive substrate;
a plurality of carbon fibers;
an intercalation material dispersed with the plurality of carbon fibers, wherein the intercalation material is configured to reversibly adsorb charge carriers within a bulk of the intercalation material; and
a plurality of nanoparticles that catalyze intercalation of the charge carriers into the bulk of the intercalation material.

US Pat. No. 10,461,323

COMPOSITE LITHIUM BORATES AND/OR PHOSPHATES AND POLYMER COATINGS FOR ACTIVE MATERIAL PARTICLES

Storedot Ltd., Herzeliya...

1. Anode active material particles comprising:metalloid cores comprising at least one of Si, Ge and Sn, having diameter in a range of 20-500 nm, and
a composite coating on said metalloid cores, said composite coating comprising lithium borates and/or lithium phosphates and polymer molecules,
wherein the lithium borates and/or lithium phosphates alternate with polymer molecules within the composite coating, with the lithium borates and/or lithium phosphates interconnecting the polymer molecules, and
wherein the polymer molecules are anchored by the lithium borates and/or lithium phosphates to the metalloid cores.

US Pat. No. 10,461,322

COMPOSITE ANODE MATERIAL MADE OF IONIC-CONDUCTING ELECTRICALLY INSULATING MATERIAL

StoreDot Ltd., Herzeliya...

1. A method of making an anode for a lithium ion cell comprising:producing core-shell particles to receive and release lithium ions at their metalloid-based cores and to allow for core expansion within their shells upon lithiation, wherein the core-shell particles comprise a single metalloid-based core per shell, wherein the producing comprises making the shells of the core-shell particles from ionic conducting material which is an electrically insulating material, and wherein the metalloid-based cores comprise at least one of Si, Ge and Sn, and
interconnecting the metalloid-based cores of the core-shell particles by electrically conductive material comprising conductive carbon fibers and/or CNTs.

US Pat. No. 10,461,321

ALKALI METAL-SULFUR SECONDARY BATTERY CONTAINING A PRE-SULFURIZED CATHODE AND PRODUCTION PROCESS

Nanotek Instruments, Inc....

1. An electrochemical method of producing a pre-sulfurized active cathode layer for a rechargeable alkali metal-sulfur cell, said method comprising:(a) preparing an integral layer of a meso-porous structure of a carbon, graphite, metal, or conductive polymer, wherein said meso-porous structure comprises meso-scaled pores of 2-50 nm and a specific surface area greater than 100 m2/g and wherein said carbon, graphite, metal, or conductive polymer is selected from chemically etched or expanded soft carbon, chemically etched or expanded hard carbon, exfoliated activated carbon, chemically etched or expanded carbon black, chemically etched multi-walled carbon nanotube, nitrogen-doped carbon nanotube, boron-doped carbon nanotube, chemically doped carbon nanotube, ion-implanted carbon nanotube, chemically treated multi-walled carbon nanotube with an inter-planar separation no less than 0.4 nm, chemically expanded carbon nanofiber, chemically activated carbon nanotube, chemically activated graphite fiber, chemically activated carbonized polymer fiber, chemically treated coke, activated meso-phase carbon, meso-porous carbon, electro-spun conductive nanofiber, highly separated vapor-grown carbon or graphite nanofiber, highly separated carbon nanotube, carbon nanowire, metal nanowire, metal-coated nanowire or nanofiber, conductive polymer-coated nanowire or nanofiber, or a combination thereof, and wherein said meso-porous structure comprises 0-49% by weight of sulfur or sulfur-containing compound pre-loaded therein and an optional binder material of 0-10% by weight;
(b) preparing an electrolyte comprising a non-aqueous solvent and a sulfur source dissolved or dispersed in said solvent;
(c) preparing an anode;
(d) bringing said integral layer of meso-porous structure and said anode in ionic contact with said electrolyte and imposing an electric current between said anode and said integral layer of meso-porous structure, serving as a cathode, with a sufficient current density for a sufficient period of time to electrochemically deposit nano-scaled sulfur particles or coating in said meso-pores to form said pre-sulfurized active cathode layer, wherein said particles or coating have a thickness or diameter smaller than 3 nm and occupy a weight fraction of greater than 80% based on the total weights of said sulfur particles or coating and said integral layer combined, have a thickness or diameter smaller than 5 nm and occupy a weight fraction of greater than 90% based on the total weights of said sulfur particles or coating and said integral layer combined, or have a thickness or diameter smaller than 10 nm and occupy a weight fraction of greater than 95% based on the total weights of said sulfur particles or coating and said integral layer combined; and
(e) depositing an element Z to said meso-porous structure and said Z element is selected from Sn, Sb, and/or Bi.

US Pat. No. 10,461,320

FORMATION OF SILICON-CARBIDE REINFORCED CARBON-SILICON COMPOSITES

Nanostar, Inc., New Orle...

1. A process of preparing a material for use in an anode of a lithium ion battery, the process comprising:thermalizing an admixture of a plurality of silicon nanocrystals, a carbon matrix precursor, and a catalyst or catalyst precursor;
wherein thermalizing the admixture includes forming SIC nanofibers.

US Pat. No. 10,461,319

ELEMENTAL METAL AND CARBON MIXTURES FOR ENERGY STORAGE DEVICES

Maxwell Technologies, Inc...

1. An energy storage device comprising:a first electrode;
a second electrode; and
a separator between the first electrode and the second electrode,
wherein at least one of the first electrode and the second electrode comprises carbon particles, elemental metal and a fibrillizable binder;
wherein the carbon particles comprise porous carbon particles, each porous carbon particle having a plurality of pores, wherein at least some of the plurality of pores receive at least some elemental metal;
wherein the porous carbon particles comprise a particle size distribution D50 value of about 1 ?m to about 20 ?m; and
wherein at least one of the first electrode and the second electrode is substantially free of solvent residue.

US Pat. No. 10,461,318

SYSTEMS AND METHODS FOR LITHIUM-ION CELL MANUFACTURING TO REDUCE CELL CONTAMINATION

GM Global Technology Oper...

1. A method comprising:wetting, via a wetting mechanism, an electrode material with a liquid to form a wet precursor;
removing a portion of the electrode material from the wet precursor with a debris generating tool to form a pre-electrode; and
eliminating, via a conditioner, the liquid from the pre-electrode to thereby form an electrode,
wherein the liquid is water and eliminating the liquid comprises applying an organic solvent to the pre-electrode, and
wherein the organic solvent is applied to the pre-electrode in a gaseous phase.

US Pat. No. 10,461,317

SOLID ELECTRODE INCLUDING ELECTROLYTE-IMPREGNATED ACTIVE MATERIAL PARTICLES

Robert Bosch GmbH, Stutt...

23. A method for manufacturing an all-solid-state alkali metal sulfur cell, the method comprising:for each of two electrodes, forming the respective electrode by:
impregnating porous active material particles using an ion-conducting liquid by adding to the ion-conducting liquid a plurality of the porous active material particles that are detached from one another in the form of individually separate particles; and
forming the respective electrode from the impregnated active material particles by adding at least one solid electrolyte; and
arranging a separator between the two electrodes, wherein one of the two electrodes is a solid cathode and the other of the two electrodes is a solid anode.

US Pat. No. 10,461,316

REINFORCED METAL FOIL ELECTRODE

Oxis Energy Limited, Oxf...

1. A lithium-sulphur electrochemical cell comprising a metal foil electrode as the anode, a sulphur-containing cathode and an electrolyte, the metal foil electrode comprising:i) a reinforcement layer comprising a porous substrate, and
ii) first and second layers of metal foil comprising lithium and/or sodium, wherein the reinforcement layer is disposed between the first and second metal foil layers and bonded together to form a composite structure having a thickness of 100 microns or less; and
wherein the porous substrate comprises a non-conducting fibrous material.

US Pat. No. 10,461,315

METHOD OF PRODUCING ELECTRODE

TOYOTA JIDOSHA KABUSHIKI ...

1. A method of producing an electrode comprising:preparing a temperature responsive polymer swelling when the temperature responsive polymer absorbs a solvent at a temperature that is lower than a lower critical solution temperature of the temperature responsive polymer and contracting when the temperature responsive polymer releases the solvent at a temperature that is equal to or higher than the lower critical solution temperature;
preparing wet granules by mixing the temperature responsive polymer, the solvent, and active material particles;
molding an active material film by sandwiching the wet granules between a first molding tool and a second molding tool, the first molding tool being maintained at a temperature that is lower than the lower critical solution temperature, the second molding tool being maintained at a temperature that is equal to or higher than the lower critical solution temperature, the active material film including a first main surface and a second main surface, the first main surface being molded by the first molding tool, and the second main surface being molded by the second molding tool; and
compressing the active material film by sandwiching the active material film between a third molding tool and a fourth molding tool, the third molding tool and the fourth molding tool being maintained at a temperature that is equal to or higher than the lower critical solution temperature; and
disposing the active material film on a surface of a current collector such that the first main surface is positioned on a side of the active material film opposite to the current collector.

US Pat. No. 10,461,314

NONAQUEOUS ELECTROLYTE BATTERY AND BATTERY PACK

KABUSHIKI KAISHA TOSHIBA,...

1. A nonaqueous electrolyte battery comprising:an electrode group formed by winding a positive electrode, a negative electrode, and a separator arranged between the positive electrode and the negative electrode, and
a nonaqueous electrolyte,
wherein a tension modulus of the separator in a winding direction is 200 (N/mm2) to 2,000 (N/mm2).

US Pat. No. 10,461,312

POSITIVE-ELECTRODE ACTIVE MATERIAL FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY AND METHOD FOR PRODUCING THE SAME, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO METAL MINING CO....

1. A cathode active material for a nonaqueous electrolyte secondary battery represented by a general formula:LitNi1-x-y-zCoxAlyTizO2
wherein 0.98?t?1.10, 0?x?0.30, 0.03?y?0.15, 0.001?z?0.03; and comprising a hexagonal lithium-containing composite oxide with a layer structure of secondary particles having primary particles,
wherein the cathode active material is made by firing the lithium-containing composite oxide at over 760° C. and not higher than 780° C. thereby forming an intermediate of a lithium titanium oxide and a lithium nickel dioxide in a grain boundary between the primary particles.

US Pat. No. 10,461,311

DEVICES, SYSTEMS, AND METHODS FOR MOLTEN FLUID ELECTRODE APPARATUS MANAGEMENT

Vissers Battery Corporati...

1. An apparatus comprising:a plurality of negative electrode reservoirs configured to contain a negative electrode material;
a plurality of positive electrode reservoirs configured to contain a positive electrode material;
a heating system configured to heat negative electrode material within a selected negative electrode reservoir of the plurality of negative electrode reservoirs to maintain the negative electrode material contained in the selected negative electrode reservoir in a fluid state and configured to heat positive electrode material in a selected positive electrode reservoir to maintain the positive electrode material contained in the selected positive electrode reservoir in the fluid state while maintaining, in a non-fluid state, negative electrode material in a non-selected negative electrode reservoir and positive electrode material in a non-selected positive electrode reservoir;
a reaction chamber comprising a solid electrolyte positioned in the reaction chamber to form a positive electrode region on a first side of the solid electrolyte and to form a negative electrode region on a second side of the solid electrolyte; and
an electrode material distribution system configured to cycle fluid positive electrode material between the selected positive electrode reservoir and the positive electrode region and configured to transfer, during a discharge state of the apparatus, fluid negative electrode material from the selected negative electrode reservoir to the negative electrode region.

US Pat. No. 10,461,310

MANUFACTURING METHOD FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A manufacturing method for a non-aqueous electrolyte secondary battery comprising:forming a mixture containing a binder, inorganic filler particles, and a solvent;
wet granulating the mixture by stirring and crushing the mixture to obtain granules containing composite particles and a solvent,
wherein the composite particles contain the inorganic filler particles and the binder, and the granules have a particle size of 10 ?m to 200 ?m;
pressing the granules in a state in which the solvent remains to form a green compact sheet; and
disposing the green compact sheet on a surface of a positive electrode mixture layer or a negative electrode mixture layer,
wherein a solid content concentration of the granules is equal to or higher than 70 mass % and lower than 100 mass %, and
the particle size is a particle size at a cumulative value of 50% in a volume-based particle size distribution measured according to a laser diffraction/scattering method.

US Pat. No. 10,461,308

SEALED BATTERY AND METHOD OF MANUFACTURE

TOYOTA JIDOSHA KABUSHIKI ...

1. A sealed battery comprising:a case provided with a case body having an opening therein and a lid that is sized so as to be capable of closing the opening and that has an electrolyte fill port;
an electrode assembly that is housed in the case; and
an electrolyte solution,
wherein the lid is provided with a filler plug that is welded to the lid so as to close the fill port, and an outside surface of the lid has a surface treated region forming an electrolyte-repelling region surrounding the weld where the filler plug is welded and another surface treated region forming an electrolyte-affinity region near the electrolyte-repelling region, and
wherein,
upon the electrolyte solution contacting the electrolyte-repelling region of the outside surface of the lid, the electrolyte-repelling region imparts a contact angle of 100° or more between a surface of the electrolyte-repelling region and the electrolyte solution, and
upon the electrolyte solution contacting the electrolyte-affinity region of the outside surface of the lid, the electrolyte-affinity region imparts a contact angle of 80° or less between a surface of the electrolyte-affinity region and the electrolyte solution, and
the electrolyte repellency of the electrolyte-repelling region is higher than the electrolyte-affinity region, and the electrolyte affinity of the electrolyte-affinity region is higher than the electrolyte-repelling region.

US Pat. No. 10,461,307

DEVICE FOR PROTECTING RECHARGEABLE BATTERY

Samsung SDI Co., Ltd., Y...

1. A device for protecting a rechargeable battery comprising:a plurality of unit cells contained in a module case and coupled in series between a first module electrode terminal and a second module electrode terminal;
a plurality of bypass switches separated from the plurality of unit cells, electrically connected to each other, having a portion thereof physically contacting a first electrode terminal of a respective one of the unit cells, and configured to close according to an internal pressure of the respective one of the unit cells; and
a plurality of bypass fuses for connecting adjacent ones of the plurality of unit cells, and for connecting a last unit cell of the plurality of unit cells and the second module electrode terminal, respectively.

US Pat. No. 10,461,306

BATTERY AND METHOD OF ATTACHING SAME TO A GARMENT

KONINKLIJKE PHILIPS N.V.,...

1. A battery comprising:a source of voltage;
at least one positive voltage connection on the source of voltage;
at least one negative voltage connection on the source of voltage;
a first magnetic element that is collocated with the at least one positive voltage connection; and
a second magnetic element that is collocated with the at least one negative voltage connection; wherein the battery comprises a first surface and a second surface that is opposite the first surface;
wherein the at least one positive voltage connection comprises a first positive voltage connection on the first surface and a second positive voltage connection on the second surface;
wherein the at least one negative voltage connection comprises a first negative voltage connection on the first surface and a second negative voltage connection on the second surface; and
wherein the first and second magnetic elements have an “N” pole on the first surface and an “S” pole on the second surface.

US Pat. No. 10,461,305

BATTERY CELL AND BATTERY SYSTEM

Robert Bosch GmbH, Stutt...

1. A battery cell (2) comprising a prismatically-designed cell housing (3) having a cover surface (31), on which a negative terminal (11) and a positive terminal (12) are arranged projecting outwardly from the cover surface (31), and comprising at least one electrode coil (10) arranged within the cell housing (3), the electrode coil having a cathode (14), which has cathode contact lugs (24), and the electrode coil having an anode (16), which has anode contact lugs (26), wherein the cathode contact lugs (24) and the anode contact lugs (26) extend adjacently from the electrode coil (10) toward precisely one end surface (35, 36) of the cell housing (3), and wherein the end surface (35, 36) is oriented at right-angles to the cover surface (31).

US Pat. No. 10,461,304

CYLINDRICAL BATTERY

SANYO Electric Co., Ltd.,...

1. A cylindrical battery comprising: an electrode body in which a negative electrode plate and a positive electrode plate to which a plurality of positive electrode leads is connected are wound with a separator interposed therebetween; an upper insulating plate disposed on the electrode body; a sealing body; a current collector plate disposed between the upper insulating plate and the sealing body; and an outer can,wherein the upper insulating plate has at least one through-hole,
the plurality of positive electrode leads includes at least one first positive electrode lead disposed at an inner circumference side of the upper insulating plate and at least one second positive electrode lead disposed at an outer circumference side of the upper insulating plate,
the first positive electrode lead extends between the upper insulating plate and the current collector plate after passing through the through-hole of the upper insulating plate and is bent onto the current collector plate at an outer circumference portion thereof,
the second positive electrode lead extends along the outside of the outer circumference portion of the upper insulating plate and is bent onto the current collector plate at the outer circumference portion thereof,
the first positive electrode lead and the second positive electrode lead are connected to the current collector plate, and
the current collector plate is electrically connected to the sealing body.

US Pat. No. 10,461,303

ELECTRODE STACK STRUCTURE AND BATTERY HAVING ELECTRODE STACK STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. An electrode stack structure comprising:a plurality of first electrode layers, each first electrode layer having a first polarity;
a plurality of second electrode layers, each second electrode layer having a second polarity, which is different than the first polarity, wherein the first electrode layers and the second electrode layers are alternately disposed; and
a separator, which is disposed between each first electrode layer and second electrode layer,
wherein the first electrode layers and the second electrode layers have multiple tabs
comprising a first tab and a second tab that is spaced apart from the first tab,
wherein the first tabs of the first electrode layers are connected to a first lead, and
wherein the second tabs of the first electrode layers are electrically connected to each other by a first connection unit which is different from the first lead, and
wherein the first tabs of the second electrode layers are connected to a second lead, and
wherein the second tabs of the second electrode layers are electrically connected to each other by a second connection unit which is different from the second lead,
the electrode stack structure further comprising
a first electrode line that electrically connects the first lead with at least one second tab of the first electrode layers and has a width smaller than the width of the first lead, wherein an end of the first electrode line is connected to the first lead and spaced from the first tabs of the first electrode layers; and
a second electrode line that electrically connects the second lead with at least one second tab of the second electrode layers and has a width smaller than the width of the second lead, wherein an end of the second electrode line is connected to the second lead and spaced from the first tabs of the second electrode layers.

US Pat. No. 10,461,302

BATTERY WIRING MODULE

SUMITOMO WIRING SYSTEMS, ...

1. A battery wiring module comprising:a housing that is to be attached to a secondary battery for a vehicle;
bus bars to be connected to electrodes of the secondary battery that are inserted into the inside of the housing; and
electrical wires connected to the bus bars,
the housing including a first divided housing and a second divided housing each having a bus bar housing portion that houses one of the bus bars, a first cover portion that is provided in one piece with the first divided housing and covers an opening of the bus bar housing portion of the first divided housing, a second cover portion that is provided in one piece with the second divided housing and covers an opening of the bus bar housing portion of the second divided housing, the bus bar housing portions of the first and second divided housings being adjacent to each other, and the first and second cover portions being adjacent to each other,
wherein the first cover portion is provided with a tongue piece having a first extending portion and a second extending portion, the first extending portion extends from the first cover portion toward the bus bar housing portion, and the second extending portion extends from an end of the first extending portion toward the second cover portion and overlaps the second cover portion in the opening direction of the bus bar housing portion.

US Pat. No. 10,461,301

BATTERY PACK FOR A HAND-HELD POWER TOOL AND METHOD FOR MANUFACTURING A CURRENT-CARRYING CONNECTION, PREFERABLY A CELL CONNECTOR OF A BATTERY PACK FOR A HAND-HELD POWER TOOL

Robert Bosch GmbH, Stutt...

1. A battery pack for a hand-held power tool, comprising:a battery pack housing accommodating at least two battery cells, each battery cell having a lateral surface running parallel to a longitudinal axis, the lateral surface being delimited by two end faces extending perpendicularly to the longitudinal axis, wherein an electrical pole of the battery cell is located on each end face, and wherein the lateral surfaces of the battery cells are parallel to each other; and
at least one cell connector to connect two battery cells of the at least two battery cells in at least one of parallel and series, the cell connector being connected to an electrical pole of the first battery cell and to an electrical pole of the second battery cell using a welding method, wherein the cell connector has at least two at least partially overlapping, current-carrying cross-sectional areas in an unwelded area between the electrical poles of the battery cells so that a current which flows between the electrical poles of the two battery cells is fed at a low electrical resistance into the at least two cross-sectional areas,
wherein the cell connector is configured to connect the battery cells only on one lateral side of the cell connector,
wherein:
the cell connector includes a conductor;
the connection of the cell connector to the pole of the first battery cell is by a welded connection of a first end area of the conductor to the pole of the first battery cell;
the connection of the cell connector to the pole of the second battery cell is by a welded connection of a second end area of the conductor to the pole of the second battery cell;
an edge of the conductor that is not welded to the poles of the first and second battery cells is bent over, along an x axis with a bend that has a bending angle of between 170° and 190°, onto, and welded to, the first and second end areas of the conductor; and
the x axis is parallel or orthogonal to a connecting z axis between the poles of the first and second battery cells.

US Pat. No. 10,461,300

BATTERY MODULE

KABUSHIKI KAISHA TOYOTA J...

1. A battery module comprising:an array body in which a plurality of battery cells are arranged;
a plurality of harnesses extending in an array direction of the battery cells in the array body and having connecting terminals of tips connected to electrode terminals of the plurality of battery cells;
a binding member configured to bind the plurality of harnesses in a harness bundle; and
an elastic body disposed at one array end of the battery cells in the array body, wherein
the plurality of harnesses branched off from the binding member have flexure between a position at which the plurality of harnesses are bound by the binding member and connecting positions of the electrode terminals and the connecting terminals,
the plurality of harnesses are pulled toward the array body from the one array end side at which the elastic body is disposed, and
the position at which the plurality of harnesses are bound by the binding member is disposed closer to the elastic body than the connecting position of the electrode terminal and the connecting terminal.

US Pat. No. 10,461,299

BATTERY PACK DESIGN FOR HIGH TEMPERATURE AND SHOCK AND VIBRATION APPLICATIONS

Electrochem Solutions, In...

1. A modular battery assembly, comprising:a) a first electrochemical cell, comprising:
i) a first casing enclosing a first anode in electrochemical association with a first cathode,
ii) wherein the first casing has a casing reservoir having a reservoir surrounding edge residing along an imaginary reservoir plane;
b) a first terminal pin electrically connected to one of the first anode and the first cathode to thereby serve as a first cell first terminal, wherein the first terminal pin is electrically isolated from the first casing and comprises a first terminal pin distal portion extending outside the first casing, but residing in the casing reservoir, spaced inwardly from the imaginary reservoir plane;
c) an interconnect assembly, comprising:
i) a flexible interconnect extending from an interconnect proximal portion to an interconnect distal portion;
ii) a proximal electrically conductive contact plate connected to the interconnect proximal portion in a first connection; and
iii) a distal electrically conductive contact plate connected to the interconnect distal portion,
d) wherein the proximal contact plate is physically connected to the first terminal pin distal portion in a second connection, and wherein the first and second connections reside in the casing reservoir, spaced inwardly from the imaginary reservoir plane;
e) an encapsulate material residing in the casing reservoir and encapsulating the first and second connections of the proximal contact plate to the respective interconnect proximal portion and the first terminal pin distal portion, wherein the encapsulate material does not encapsulate the distal contact plate; and
f) a second electrochemical cell, comprising:
i) a second casing enclosing a second anode in electrochemical association with a second cathode;
ii) a second terminal pin electrically connected to one of the second anode and the second cathode to thereby serve as a second cell first terminal, wherein the second cell first terminal is electrically isolated from the second casing and is of the same polarity as the first terminal pin serving as the first cell first terminal,
iii) wherein the second casing is connected to the other of the second anode and the second cathode not electrically connected to the second terminal pin to thereby serve as a second cell second terminal having a polarity that is opposite that of the second terminal pin, and
iv) wherein the distal contact plate connected to the interconnect distal portion is directly contacted to the second casing of the second electrochemical cell so that the first and second electrochemical cells are electrically connected in series, and
v) wherein the flexibility of the interconnect of the interconnect assembly is configured so that the first and second electrochemical cells to move with respect to each under mechanical shock and vibration conditions.

US Pat. No. 10,461,298

BATTERY SEPARATOR WITH DIELECTRIC COATING

APPLIED MATERIALS, INC., ...

1. A battery comprising:an anode containing at least one of lithium metal, lithium-alloy, a mixture of lithium metal and lithium alloy;
a cathode; and
a separator disposed between the anode and the cathode, wherein the separator comprises:
at least one dielectric layer capable of conducting ions, wherein the at least one dielectric layer has a thickness of 1 nanometer to 2,000 nanometers and is and formed directly on a surface of the anode, a surface of the cathode, or both the surface of the anode and the surface of the cathode, wherein the at least one dielectric layer comprises:
a plurality of dielectric columnar projections comprising dielectric material; and
a nanoporous structure formed between the dielectric columnar projections and comprising the dielectric material.

US Pat. No. 10,461,297

LAMINATED BODY

SUMITOMO CHEMICAL COMPANY...

1. A laminated body, comprising:a porous base material containing a polyolefin-based resin as a main component; and
a porous layer on at least one surface of the porous base material, the porous layer containing a polyvinylidene fluoride-based resin,
the porous base material having a parameter X of not more than 20, the parameter X being calculated in accordance with a formula below, where MD tan ? represents a tan ? measured in a machine direction through a viscoelasticity measurement performed at a frequency of 10 Hz and a temperature of 90° C., and TD tan ? represents a tan ? measured in a transverse direction through the viscoelasticity measurement,
X=100×|MD tan ??TD tan ?|/{(MD tan ?+TD tan ?)/2}
the polyvinylidene fluoride-based resin containing crystal form ? in an amount of not less than 36 mol % with respect to 100 mol % of a total amount of the crystal form ? and crystal form ? contained in the polyvinylidene fluoride-based resin,
where the amount of the crystal form ? is calculated from an absorption intensity at around 765 cm?1 in an IR spectrum of the porous layer, and an amount of the crystal form ? is calculated from an absorption intensity at around 840 cm?1 in the IR spectrum of the porous layer.

US Pat. No. 10,461,296

BATTERY SEPARATOR FILM, NONAQUEOUS ELECTROLYTE SECONDARY BATTERY SEPARATOR, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO CHEMICAL COMPANY...

1. A battery separator film which curls with respect to a width direction of the battery separator film, the battery separator film being a laminated porous film including a functional layer having a uniform thickness comprising a wholly aromatic polyamide, wherein the functional layer is provided on only one surface of the laminated porous film;wherein the battery separator film exhibits a difference of not more than 5 mm between (i) a width of the battery separator film and (ii)
a projection width of a part of the battery separator film which part is smallest in projection width when seen from a direction perpendicular to a surface of the battery separator film while the battery separator film, to which a tension of 90 N/m is applied, is stretched between two rollers that are provided in parallel with each other at an interval of 1 m at a temperature of 23 degrees Celsius and a relative humidity of 50%.

US Pat. No. 10,461,295

SEPARATOR CAPABLE OF SELECTIVE ION MIGRATION, AND SECONDARY BATTERY COMPRISING SAME

REKRIX CO., LTD., Seoul ...

5. A zinc-air battery, comprising:a positive electrode;
a negative electrode;
a separator interposed between the positive electrode and the negative electrode; and
an electrolyte including zinc for impregnating the negative electrode, the separator and a part of the positive electrode, the electrolyte comprising an electromigration-promoting ion,
wherein the separator is formed of a porous material having a plurality of pores formed therein, and each of the plurality of pores has a size smaller than the size of an electromigration-promoting ion contained in the electrolyte, and thus the electromigration-promoting ion does not pass through the plurality of pores such that the electromigration-promoting ion is prevented from migrating to the positive electrode side,
wherein the zinc-air battery operates by a migration of electrons generated when zinc contained in the electrolyte reacts with oxygen in the air and is changed into zinc oxide.

US Pat. No. 10,461,293

MICROPOROUS MEMBRANES, SEPARATORS, LITHIUM BATTERIES, AND RELATED METHODS

Celgard, LLC, Charlotte,...

1. A microporous battery separator membrane comprising:a microporous polyolefin separator membrane modified with low energy electron beam radiation in a dosage ?70 kGy and ?120 kGy in a nitrogen atmosphere, and having a thickness less than about 14 ?m and wherein:
said microporous polyolefin separator membrane has an onset of thermal shutdown occurring at a temperature ?138° C.;
said microporous polyolefin separator membrane has % machine direction thermal shrinkage at 120° C. for one hour of ?7.5%; and/or
said microporous polyolefin separator membrane has % transverse direction thermal shrinkage at 120° C. for one hour ?1%.

US Pat. No. 10,461,292

ENERGY STORAGE APPARATUS AND COVER MEMBER

GS YUASA INTERNATIONAL LT...

1. An energy storage apparatus comprising:a spacer;
an energy storage device disposed adjacently to the spacer in a first direction and having an external terminal on an end surface thereof in a second direction orthogonal to the first direction; and
a cover member holding a bus bar connected to the external terminal and extending along the end surface of the energy storage device having the external terminal,
wherein the spacer has a first connecting portion to which the cover member is connected on an end portion thereof in the second direction, and
the cover member has a second connecting portion which engages with the first connecting portion in a state where movement of the cover member in a direction away from the spacer in the second direction is restricted,
wherein the first connecting portion is disposed on the end portion of spacer at an intermediate position in a third direction orthogonal to the first and the second directions.

US Pat. No. 10,461,291

CURRENT-INTERRUPT DEVICE FOR BATTERY CELL

Ford Global Technologies,...

1. A current-interrupt device for a battery cell, the current-interrupt comprising:a plate defining a hole;
a diaphragm joined to the plate and covering a top of the hole;
a cover sealing a bottom of the hole; and
a dielectric fluid disposed in the hole, wherein, the diaphragm and the cover are movable, responsive to cell pressure exceeding a threshold, separating the diaphragm from the plate forming a gap therebetween and releasing the fluid into the gap, and preventing current from arching across the gap.

US Pat. No. 10,461,290

ELECTRIC STORAGE APPARATUS, AND METHOD FOR PRODUCING ELECTRIC STORAGE APPARATUS

GS YUASA INTERNATIONAL LT...

1. An electric storage apparatus, comprising: a plurality of electric storage devices which are arranged in a first direction; and an abutment arranged in alignment with, and disposed on both ends of the electric storage devices in the first direction, wherein each of the abutments includes at least three members stacked in the first direction, wherein each of the members includes a positioning part including a first surface forming a recess recessed in the first direction and a back surface of the first surface forming a projection projecting opposite to the plurality of electric storage devices, in the first direction,wherein the positioning parts of the members are arranged at positions corresponding to one another such that a first one of the positioning parts, a second one of the positioning parts, and a third one of the positioning parts are sequentially arranged in the first direction,
wherein adjacent members are relatively positioned by inserting a positioning part of one of the adjacent members into a positioning part of an other of the adjacent members,
wherein the first one of the positioning parts that is arranged on a side closest to the electric storage devices includes an insulating member, and the second one of the positioning parts and the third one of the positioning parts comprise a metal including a molded metal plate subjected to a metal plating, and
wherein, in the first direction, the second one of the positioning parts is disposed between the recess of the first one of the positioning parts and the recess of the third one of the positioning parts of the members.

US Pat. No. 10,461,289

PORTABLE BATTERY PACK COMPRISING A BATTERY ENCLOSED BY A WEARABLE AND REPLACEABLE POUCH OR SKIN

LAT ENTERPRISES, INC., R...

1. A portable battery pack comprising:a wearable pouch and one or more batteries enclosed in the wearable pouch;
wherein the one or more batteries include:
at least one battery element;
a battery cover including one or more channels to accommodate wires of one or more flexible omnidirectional leads and a compartment sized to receive the at least one battery element;
a battery back plate attached to the battery cover; and
the one or more flexible omnidirectional leads including a connection portion and a wiring portion, wherein a flexible spring is provided around the wiring portion, wherein the wiring portion and the flexible spring are held securely in the one or more channels in the battery cover such that a portion of the flexible spring is positioned inside the battery cover and a portion of the flexible spring is positioned outside the battery cover;
wherein the wearable pouch includes:
a closeable opening through which the one or more batteries are operable to be removed from the wearable pouch; and
one or more openings through which the one or more flexible omnidirectional leads from the one or more batteries can be accessed.

US Pat. No. 10,461,288

BATTERY MODULE AND BATTERY PACK INCLUDING SAME

LG CHEM, LTD., Seoul (KR...

1. A battery module comprising:a cartridge stack comprising a plurality of secondary batteries which each comprise an electrode lead, and a plurality of cartridges which each accommodate at least one of the plurality of secondary batteries such that at least a portion of each electrode lead of each secondary battery protrudes outwardly, and which are stacked in a plurality of stages; and
an interconnect board (“ICB”) housing comprising a stepped connection end, a power terminal installed fixedly to the stepped connection end, and a bus bar electrically connecting each electrode lead with the power terminal, and mounted on a surface of the cartridge stack,
wherein the bus bar comprises a first connection part which is provided in opposition to the power terminal, having the stepped connection end therebetween, and is connected with each electrode lead, a second connection part which is provided in opposition to the first connection part, having the stepped connection end therebetween, and is connected with the power terminal, and a connection part which connects the first connection part with the second connection part and is embedded in the stepped connection end such that the connection part is hidden by the stepped connection end.

US Pat. No. 10,461,287

BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A battery pack comprising:secondary batteries;
a case accommodating the secondary batteries, the case comprising:
an upper case;
a lower case; and
plates disposed on each of the upper case and the lower case and each of the plates having holes, wherein each hole corresponds to an end of each of a single one of the secondary batteries;
alignment members attached to the plate of the upper case; and
a conductive coupling tap,
wherein each of the alignment members comprises a protrusion covering at least a portion of one or more holes,
wherein the alignment member is a separate component from the conductive coupling tap
wherein the conductive coupling tap is configured to electrically couple to the ends of corresponding ones of secondary batteries corresponding to the one or more holes,
wherein a width of each of the alignment members is greater than an internal interval between two adjacent ones of the secondary batteries, and
wherein each of the alignment members covers portions of at least two adjacent holes of the plates.

US Pat. No. 10,461,286

BATTERY PACK

LG CHEM, LTD., Seoul (KR...

1. A battery pack comprising:a battery module comprising battery cells sequentially stacked, air flow paths between the battery cells, and at least one cooling duct located on an outermost side of the battery cells to define an air flow space configured to communicate with the air flow paths, the at least one cooling duct having an air passing hole open toward an upper portion of the battery module to communicate with the air flow space;
a lower case configured to load the battery module and the at least one cooling duct therein, the lower case being separate from the at least one cooling duct; and
an upper case coupled to the lower case and configured to cover the battery module and the at least one cooling duct, the upper case having a vent structure on each cooling duct of the at least one cooling duct,
wherein the at least one cooling duct is located between the lower case and the battery cells, and
wherein the vent structure comprises an inner air passage unit configured to define an air passage and having a rectangular-tunnel-type window frame configured to communicate with the air passing hole through one side of the air passage and penetrate a sidewall of the upper case through the other side of the air passage, and an outer air passage unit detachably inserted along an inner wall of the window frame, the outer air passage unit having through holes in a front wall located on a front side of the window frame and in a rear wall located on a rear side of the window frame, and the outer air passage unit is entirely located within an outermost perimeter of a sidewall of the lower case.

US Pat. No. 10,461,285

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SEIKO INSTRUMENTS INC., ...

1. A nonaqueous electrolyte secondary battery, comprising:a bottomed cylindrical positive electrode casing; and
a negative electrode casing fixed to an opening of the positive electrode casing through a gasket, such that an accommodation space is defined between the positive electrode casing and the negative electrode casing,
wherein the opening of the positive electrode casing is sealed to the negative electrode casing side by a caulking material of the gasket to seal the accommodation space,
where the caulking material has a uniform compression ratio of at least 50%, and
where a caulking tip end of the positive electrode casing in the opening is inward of a tip end of the negative electrode casing, and
a diameter d of the nonaqueous electrolyte secondary battery is in a range of 6.6 mm to 7.0 mm, a height h1 of the nonaqueous electrolyte secondary battery is in a range of 1.9 mm to 2.3 mm, at least a part of a side surface portion of the positive electrode casing on an opening side has a curved surface, a radius of curvature R of the curved surface is in a range of 0.8 mm to 1.1 mm, and a height h2 of the positive electrode casing is in a range of 65% to 73% with respect to the height h1 of the nonaqueous electrolyte secondary battery.

US Pat. No. 10,461,283

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND REPAIR METHOD THEREOF

LG DISPLAY CO., LTD., Se...

1. A repair method of an organic light emitting display device including a plurality of pixels, each pixel among the plurality of pixels including an organic light emitting diode (OLED) in every pixel area defined as a plurality of scan lines and a plurality of data lines intersecting with each other, and the organic light emitting display device further including a repair structure in a horizontal direction by one or more repair lines between two or more adjacent pixels among the plurality of pixels, the repair method comprising:cutting a connection between a driving thin-film transistor (TFT) defective in operation and an anode electrode of an OLED of a first pixel among the two or more adjacent pixels;
repairing a source electrode of an in-defective driving TFT of a second pixel and the anode electrode of the OLED of the first pixel by welding the repair line and the source electrode of the driving TFT of the second pixel adjacent to the first pixel; and
operating the OLED of the first pixel through the in-defective driving TFT of the second pixel,
wherein the repair line extends from the end of the anode electrode of the OLED of the first pixel to overlap the source electrode of the driving TFT of the second pixel, and
wherein the repairing includes welding the repair line and the source electrode of the driving TFT of the second pixel to connect the repair line and the source electrode of the driving TFT of the second pixel.

US Pat. No. 10,461,282

METHOD FOR DEPOSITING PROTECTION FILM OF LIGHT-EMITTING ELEMENT

TES CO., LTD, Yongin, Gy...

1. A method of depositing a protection film for a light emitting diode (LED), the method comprising:depositing a first inorganic protection layer on an LED of a substrate; and
depositing a second inorganic protection layer on the first inorganic protection layer, wherein internal stress of the second inorganic protection layer is smaller than internal stress of the first inorganic protection layer,
wherein the depositing of the first inorganic protection layer and the depositing of the second inorganic protection layer comprise depositing an aluminum oxide (AlOx) layer by atomic layer deposition (ALD), and
wherein the depositing of the first inorganic protection layer and the depositing of the second inorganic protection layer are continuously performed using the same source gas and different reaction gases in one chamber.

US Pat. No. 10,461,281

LIGHT EMITTING DEVICE

Industrial Technology Res...

1. A light emitting device, comprising:a substrate;
a first electrode disposed on the substrate;
a light emitting layer disposed on the first electrode;
a second electrode disposed on the light emitting layer, wherein the first electrode, the light emitting layer, and the second electrode are sequentially stacked on the substrate to constitute a light emitting unit;
a heat shrinkable film disposed on the light emitting unit;
a first adhesive layer disposed between the heat shrinkable film and the second electrode;
a gas barrier substrate, wherein the light emitting unit, the first adhesive layer and the heat shrinkable film are disposed between the substrate and the gas barrier substrate; and
a second adhesive layer disposed between the heat shrinkable film and the gas barrier substrate, wherein an adhesion strength between the second adhesive layer and the heat shrinkable film is smaller than an adhesion strength between the first adhesive layer and the heat shrinkable film.

US Pat. No. 10,461,280

DOUBLE-SIDED ELECTROLUMINESCENT DISPLAY PANEL AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A double-sided electroluminescent display panel, comprising:a double-sided light-emitting transparent electroluminescent structure;
a first absorption polarization structure disposed on a first light-emitting surface of the transparent electroluminescent structure; and
a first reflective polarization structure disposed on a second light-emitting surface of the transparent electroluminescent structure, wherein transmission axes of the first absorption polarization structure and the first reflective polarization structure are perpendicular to each other, the first absorption polarization structure is configured to absorb light of a first wave component and transmit light of a second wave component, and the first reflective polarization structure is configured to transmit the light of the first wave component and reflect the light of the second wave component.

US Pat. No. 10,461,279

TOP-OLEDS WITH MULTILAYER OUTPUT COUPLING UNIT AND FLAT PANEL DISPLAY DEVICES USING THE SAME

Shenzhen China Star Optoe...

1. A top organic light emitting diode (Top-OLED), comprising:a light emitting unit;
a light output coupling unit configured on a light output surface of the light emitting unit, wherein the light output coupling unit is configured with a first light emitting coupling layer and a second first light emitting coupling layer configured on the light output surface of the light emitting unit in sequence, and a refractive index of the first light emitting coupling layer is greater than a refractive index of the second light emitting coupling layer;
the light output coupling unit further comprises a third light emitting coupling layer being stacked on the second first light emitting coupling layer, wherein the refractive index of the second light emitting coupling layer is greater than a refractive index of the third light emitting coupling layer;
wherein the first light emitting coupling layer is a first NPB layer having the refractive index greater than 1.75, the second light emitting coupling layer is a single layer structure having the refractive index in a range from 1.4 to 1.75 and formed by conducting a co-vapor deposition process of NPB and LiF in a ratio 1:1, and the third light emitting coupling layer is a first LiF layer having the refractive index in a range from 1.1 to 1.4.

US Pat. No. 10,461,278

LIGHT-EMITTING DEVICE, DISPLAY APPARATUS, AND ILLUMINATION APPARATUS

SONY CORPORATION, Tokyo ...

1. A light-emitting device comprising: a first electrode;a second electrode; and an organic layer that is provided between the first electrode and the second electrode and is formed by stacking a first light-emitting layer and a second light-emitting layer in order from the first electrode side,
wherein light emitted from the organic layer is reflected by a first reflective interface formed between the first light-emitting layer and the first electrode, passes through the second electrode, and is emitted to the outside of the light-emitting device,
a first light-transmitting layer, a second light-transmitting layer, and a third light-transmitting layer are provided on a side of the second light-emitting layer opposite to the first light-emitting layer in order from the second light-emitting layer side,
a second reflective interface is formed at an interface of the first light-transmitting layer on the second light-emitting layer side,
a third reflective interface is formed between the first light-transmitting layer and the second light-transmitting layer,
a fourth reflective interface is formed between the second light-transmitting layer and the third light-transmitting layer,
an interference filter is formed by the first reflective interface, the second reflective interface, the third reflective interface, and the fourth reflective interface,
the first reflective interface is arranged so as to satisfy a first condition, and
the second reflective interface, the third reflective interface, and the fourth reflective interface are arranged so as to satisfy either or both of a second condition and a third condition,
wherein the first condition is that reflection of light rays, which are emitted from the first light-emitting layer, on the first reflective interface is reinforced, and reflection of light rays, which are emitted from the second light-emitting layer, on the first reflective interface is reinforced,
wherein the second condition is that reflection of light rays, which are emitted from the first light-emitting layer, on the second reflective interface is weakened, reflection of light rays, which are emitted from the first light-emitting layer, on the third reflective interface is reinforced, and reflection of light rays, which are emitted from the first light-emitting layer, on the fourth reflective interface is reinforced, and
wherein the third condition is that reflection of light rays, which are emitted from the second light-emitting layer, on the second reflective interface is weakened, reflection of light rays, which are emitted from the second light-emitting layer, on the third reflective interface is reinforced, and reflection of light rays, which are emitted from the second light-emitting layer, on the fourth reflective interface is reinforced.

US Pat. No. 10,461,277

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a display region arranged with a plurality of pixels; anda sealing layer covering the display region,wherein
the plurality of pixels are arranged along a first direction and a second direction intersecting the first direction;
the sealing layer includes an insulation layer having a density pattern;
the density pattern includes a sparse region being a low density region and a dense region being a high density region;
the low density region has the insulation layer with a lower density than an average density within the display region;
the high density region has the insulation layer with a higher density than an average density within the display region;
the high density region is comprised of a plurality of island shaped regions;
the plurality of island shaped regions are individually separated; and
a region other than the high density region is comprised of the low density region in a plan view of the display region.

US Pat. No. 10,461,276

ORGANIC OPTOELECTRONIC COMPONENT AND METHOD OF PREVENTING THE ANALYSIS OF THE MATERIAL COMPOSITION OF AN ORGANIC OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...

1. A method of preventing an analysis of the material composition of an organic optoelectronic component comprising:A) providing an organic optoelectronic component comprising a functional component part and a camouflage layer, and
B) determining an overall analysis spectrum of the organic optoelectronic component by IR or X-ray radiation,
wherein the overall analysis spectrum is composed of a first analysis spectrum of the functional component part and a second analysis spectrum of the camouflage layer, and
determination of the first and/or second analysis spectrum from the overall analysis spectrum is prevented so that, due to the camouflage layer, determination of the material composition of the functional component part is prevented.

US Pat. No. 10,461,274

FLEXIBLE DISPLAY DEVICE INCLUDING NOTCH PATTERN IN FOLDING AREA AND FLEXIBLE ELECTRONIC DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel comprising a flexible substrate, the flexible substrate comprising:
a first portion corresponding to a display area of the display panel, the display area being configured to display an image; and
a second portion extending from the first portion, the second portion corresponding to a non-display area of the display panel adjacent to the display area,
wherein the display panel is configured to bend in a folding area based on a folding line extending in a width direction of the display panel and overlapping the flexible substrate such that a first non-folding area of the display panel and a second non-folding area of the display panel are positioned at opposite sides of the folding area, and
wherein a first notch pattern is formed in the flexible substrate of the display panel in an overlapping area in which a part of the second portion of the flexible substrate is removed in a region corresponding to a part of the folding area such that the first notch pattern reduces a width of the display panel in a region comprising the overlapping area.

US Pat. No. 10,461,273

DISPLAY DEVICE HAVING A STRUCTURE TO PREVENT DAMAGE TO A BENT PORTION OF A FLEXIBLE DISPLAY

Japan Display Inc., Mina...

1. A display device comprising:a flexible display including a display region and a peripheral region arranged in a length direction, the flexible display being bent in the peripheral region around an axis extending in a width direction orthogonal to the length direction, the flexible display being provided with a light-emitting element layer in the display region; and
a spacer disposed inside a bend of the flexible display and including both end portions on both sides in the width direction, the spacer including a guide surface regulating the bend,
a first reinforcement film on the display region of the flexible display;
a second reinforcement film on the peripheral region of the flexible display;
a semiconductor circuit chip on the peripheral region; and
a flexible board on the peripheral region, wherein
the both end portions of the spacer project from the flexible display in the width direction,
a side end portion of the first reinforcement film is in contact with a first side end portion of the second reinforcement film,
a second side end portion of the second reinforcement film is in contact with one side of the semiconductor circuit chip,
a third side end portion of the second reinforcement film is in contact with another side of the semiconductor circuit chip,
the second reinforcement film is continuously formed from the first side end portion to the second side end portion, and
the first reinforcement film, the first side end portion, the second side end portion, the semiconductor circuit chip, the third side end portion, and the flexible board are arranged in this order along a surface of the flexible display.

US Pat. No. 10,461,272

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a display device, the method comprising:preparing a first substrate;
disposing a pixel defining layer on the first substrate, the pixel defining layer configured to define an emissive area and a transmissive area;
disposing a first electrode in the emissive area;
disposing an organic light emitting layer on the first electrode;
disposing a second electrode in the emissive area and the transmissive area;
disposing a mask on the second electrode and injecting a modifying agent; and
disposing a second substrate facing the first substrate,
wherein the mask has a blocking portion corresponding to the emissive area, a transmissive portion corresponding to the transmissive area, and a stopper disposed on a rear surface of the mask at a boundary between the blocking portion and the transmissive portion.

US Pat. No. 10,461,271

LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:a pair of electrodes,
a first light-emitting layer; and
a second light-emitting layer,
wherein the first light-emitting layer comprises a first fluorescent material and a first host material,
wherein a second fluorescent material, a first organic compound and a second organic compound are mixed in the second light-emitting layer,
wherein a triplet excited energy level of the first host material is lower than a triplet excited energy level of the first fluorescent material,
wherein the triplet excited energy level of the first host material is lower than triplet excited energy levels of the first organic compound and the second organic compound, and
wherein light emitted from the light-emitting element comprises delayed fluorescence.

US Pat. No. 10,461,270

ORGANIC EL DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An organic EL display device comprising:an organic EL display panel including a plastic substrate exhibiting flexibility and an organic EL element formed on the plastic substrate;
a first inorganic layer provided on an upper surface of the organic EL display panel; and
a second inorganic layer provided on a lower surface of the organic EL display panel as a surface of the plastic substrate opposite to a first inorganic layer side, wherein
an entire thickness of the organic EL display device is equal to or less than 74 ?m; and
distortion rates of the first inorganic layer and the second inorganic layer in a case where a bending radius of the organic EL display device is 3.5 mm are ?1 to +1%.

US Pat. No. 10,461,268

FLEXIBLE DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. A flexible display panel, comprisinga substrate;
an inorganic layer disposed on a side of the substrate, wherein the inorganic layer comprises a recessed region and a non-recessed region, and the recessed region comprises a recess with an opening facing away from the substrate; and
an organic layer disposed on a side of the inorganic layer away from the substrate, wherein the organic layer comprises a filling portion, and a projection of the filling portion in a direction perpendicular to the substrate is located in the recess of the recessed region;
wherein a surface of the filling portion away from the substrate is a concave surface, and the concave surface is recessed toward the substrate, wherein the flexible display panel comprises a bending region and a non-bending region,
wherein in at least one first cross-section, the surface of the filling portion away from the substrate is a concave surface recessed toward the substrate, and an projection of the recessed region in the direction perpendicular to the substrate covers the bending region, and
wherein the at least one first cross-section is perpendicular to the substrate, and the at least one first cross-section intersects an extension direction of a bending axis of the bending region.

US Pat. No. 10,461,267

FLEXIBLE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A flexible display panel comprising:a flexible substrate including a display area and a peripheral area outside of the display area;
a wire or an organic layer disposed over the flexible substrate;
a polarizer disposed over the flexible substrate;
a lower film under the flexible substrate; and
an acryl-based resin layer disposed in the peripheral area, not disposed in the display area, and having a curvature radius which is greater than a curvature radius of the wire or the organic layer overlapping the acryl-based resin layer in a first direction perpendicular to an upper surface of the flexible substrate,
wherein:
the peripheral area of the flexible substrate in which the acryl-based resin layer is disposed is bent along a first bending line towards a rear side of the display area,
the acryl-based resin layer overlaps the first bending line in the first direction,
a side surface of the acryl-based resin layer is in contact with a side surface of the polarizer, and
a bottom side of the lower film includes at least one depression.

US Pat. No. 10,461,266

LUMINESCENT COMPOUNDS AND METHODS OF USING SAME

1. A compound having general formula (1):
wherein G is oxygen, aliphatic, methylene, carbonyl, amine, silylene, phosphine, phosphine oxide, sulfur, sulfonyl, or a combination thereof;
R1 and R2 are independently a hydrogen, an aliphatic moiety, or fluorine, with the proviso that if one of R1 and R2 is aliphatic, CF3, or fluoro, then the other is hydrogen;
R3 is independently H, or a substituted or unsubstituted aliphatic moiety, substituted or unsubstituted aryl moiety, a substituted or unsubstituted amine, halo, thioether, ether, or any combination thereof, and the R3 of one triazolyl ring can be joined to the R3 of the other triazolyl ring; and
R4 is optionally further substituted, and is a non-aromatic carbocycle or heterocycle, an aryl group (which includes a heteroaryl) that is attached as a fused ring or as a substituent, a hydroxy group, nitro, amino, halo, BR2, B(aryl)2, aryl-B(aryl)2, NR2, OR, a nitrile group, —C(halo)3, and R, where R is a substituted or unsubstituted aliphatic group having 1-24 carbon atoms which may be straight, branched or cyclic H, a substituted or unsubstituted aliphatic moiety, halo, a substituted or unsubstituted aryl moiety, or any combination thereof.

US Pat. No. 10,461,265

ORGANOMETALLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An organometallic compound represented by Formula 1:
wherein, in Formula 1,
M is selected from Ir, Eu, Tb, and Tm;
X11 and X14 are each independently selected from C and N;
X12 and X13 are C;
A11 is selected from C1-C20 heterocyclic groups;
A12 is selected from a C5-C20 cyclic group and a C1-C20 heterocyclic group;
A13 is selected from a pyrrole and an indole;
R11 to R13 are each independently selected from a hydrogen, a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —C(?O)(Q1), —Si(Q1)(Q2)(Q3), and —N(Q1)(Q2), wherein R11 and R12 are optionally linked to each other to form a saturated or unsaturated ring; and Q1 to Q3 are each independently selected from a hydrogen, a deuterium, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C6-C20 aryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group;
n is selected from 1 and 2;
L is is a ligand represented by one of Formulae 2-1 to 2-6:

wherein, in Formulae 2-1 to 2-6,
A21 is selected from a C5-C20 cyclic group and a C1-C20 heterocyclic group;
X21 and X22 are each independently selected from C and N;
Y21 is selected from a single bond, a double bond, a substituted or unsubstituted C1-C5 alkylene group, a substituted or unsubstituted C2-C5 alkenylene group, and a substituted or unsubstituted C6-C10 arylene group;
Z21 and Z22 are each independently selected from N, O, N(R25), P(R25)(R26), and As(R25) (R26) ,
Z23 is selected from P and As;
R21 to R26 are each independently selected from a hydrogen, a deuterium, —F, —CI, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group;
b21 to b24 are each independently selected from 1, 2, and 3; and
* and *? are each independently a binding site with an adjacent atom; and
m is selected from 1, 2, 3, and 4.

US Pat. No. 10,461,264

ORGANIC ELECTROLUMINESCENT ELEMENT

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device comprising a pair of electrodes and an organic compound layer therebetween, the organic compound layer comprising an emitting layer comprising: a first material; a second material; and a third material, whereinsinglet energy EgS(H1) of the first material, singlet energy EgS(H2) of the second material, and singlet energy EgS(D) of the third material satisfy a relationship of numerical formulae (1) and (2) below,
the singlet energy EgS(H1) of the first material and the singlet energy EgS(H2) of the second material satisfy a relationship of numerical formula (8) below,
a difference ?ST(H1) between the singlet energy EgS(H1) of the first material and an energy gap Eg77K(H1) at 77K of the first material satisfies a relationship of a numerical formula (3) below, and
the third material is a fluorescent material,
EgS(H1)>EgS(D)  (1)
EgS(H2)>EgS(D)  (2)
?ST(H1)=EgS(H1)?Eg77K(H1)<0.3 [eV]  (3)
EgS(H2)?EgS(H1)  (8).

US Pat. No. 10,461,263

CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A condensed cyclic compound represented by Formula 1:
wherein A1 in Formula 1 is selected from groups represented by Formulae 2A to 2F,
m1 in Formula 1 is an integer from 1 to 5,
A2 in Formulae 2A to 2F is selected from groups represented by Formulae 3A to 3C,
m2 in Formulae 2A to 2F is an integer from 1 to 5,
rings B1, B2, B11, and B12 in Formulae 2A to 2F and 3B are each independently a C5-C60 carbocyclic group or a C1-C60 heterocyclic group,
X1 in Formulae 2B, 2D, and 2F is selected from O, S, C(R23)(R24), N(R25), and Si(R26)(R27),
L1, L2, L11, L21, and L22 in Formulae 1, 2A to 2F, and 3C are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene group, a substituted or unsubstituted C1-C10 heterocycloalkylene group, a substituted or unsubstituted C3-C10 cycloalkenylene group, a substituted or unsubstituted C1-C10 heterocycloalkenylene group, a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a1, a2, a11, a21, and a22 in Formulae 1, 2A to 2F, and 3C are each independently an integer from 0 to 5,
Ar11, Ar21, and Ar22 in Formulae 2A to 2D and 3C are each independently selected from a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group,
b11, b21, and b22 in Formulae 2A to 2D and 3C are each independently an integer from 1 to 5,
R1 to R10, R21 to R27, R31, and R32 in Formulae 1, 2A to 2F, 3A, and 3B are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, Si(Q1)(Q2)(Q3), —N(Q1)(Q2), —B(Q1)(Q2), —C(?O)(Q1), —S(?O)2(Q1), and —P(?O)(Q1)(Q2),
c21 to c27, c31, and c32 in Formulae 2A to 2F, 3A, and 3B are each independently an integer from 0 to 5,
n1 in Formulae 2A to 2F is an integer from 0 to 5,
* in Formulae 2A to 2F and 3A to 3C is a binding site to a neighboring atom, and
at least one substituent of the substituted C3-C10 cycloalkylene group, the substituted C1-C10 heterocycloalkylene group, the substituted C3-C10 cycloalkenylene group, the substituted C1-C10 heterocycloalkenylene group, the substituted C6-C60 arylene group, the substituted C1-C60 heteroarylene group, the substituted divalent non-aromatic condensed polycyclic group, the substituted divalent non-aromatic condensed heteropolycyclic group, the substituted C1-C60 alkyl group, the substituted C2-C60 alkenyl group, the substituted C2-C60 alkynyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13), —N(Q11)(Q12), —B(Q11)(Q12), —C(?O)(Q11), —S(?O)2(Q11), and —P(?O)(Q11)(Q12);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, and a terphenyl group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q21)(Q22)(Q23), —N(Q21)(Q22), —B(Q21)(Q22), —C(?O)(Q21), —S(?O)2(Q21), and —P(?O)(Q21)(Q22); and
—Si(Q31)(Q32)(Q33), —N(Q31)(Q32), —B(Q31)(Q32), —C(?O)(Q31), —S(?O)2(Q31), and —P(?O)(Q31)(Q32),
wherein Q1 to Q3, Q11 to Q13, Q21 to Q23, and Q31 to Q33 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryl group substituted with a C1-C60 alkyl group, a C6-C60 aryl group substituted with a C6-C60 aryl group, a terphenyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryl group substituted with a C1-C60 alkyl group, a C1-C60 heteroaryl group substituted with a C6-C60 aryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,461,262

CONDENSED CYCLIC COMPOUND AND AN ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A condensed cyclic compound represented by Formula 1:
wherein, in Formulae 1 and 2,
X1 is N or C(R11), X2 is N or C(R12), and X3 is N or C(R13), and at least one of X1 to X3 is N;
L1 to L3 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene, a substituted or unsubstituted C1-C10 heterocycloalkylene, a substituted or unsubstituted C3-C 10 cycloalkenylene, a substituted or unsubstituted C1-C10 heterocycloalkenylene, a substituted or unsubstituted C6-C60 arylene, a substituted or unsubstituted C1-C60 beteroarylene, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, or a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group;
a1 to a3 are each independently an integer selected front 0 to 3, wherein, when a1 is 2 or greater, at least 2 or L1(s) are the same as or different from each other, when a2 is 2 or greater, at least 2 L2(s) are the same as or different from each other, and when a3 is 2 or greater, at least 2 L3(s) are the same as or different from each other;
Ar1 and Ar2 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C1 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted-C6-C60 aryl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, or a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group;
one of R1 and R2 is a group represented by Formula 2 and the other of R1 and R2 is hydrogen;
R3, R4, R5 and R6 are each hydrogen;
R7, R8 and R11 to R13 are each independently selected from a group represented by Formula 2, hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C 10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —Si(Q1)(Q2)(Q3), —N(Q1)(Q2), —B(Q1)(Q2),—C(?O)(Q1), —S(?O)2(Q1), or —P(?O)(Q1)(Q2);
R7 and R8 are optionally linked to form a saturated or unsaturated ring;
at least one of R1 or R2 is a group represented by Formula 2;
* indicates a binding site to a neighboring atom; and
at least one substituent of the substituted C3-C10 cycloalkylene group, substituted C1-C10 heterocycloalkylene group, substituted C3-C10 cycloalkenylene group, substituted C1-C10 heterocycloalkenylene group, substituted C6 -C60 arylene group, substituted C1-C60 heteroarylene group, a substituted divalent non-aromatic condensed polycyclic group, a substituted divalent non-aromatic condensed heteropolycyclic group, substituted C1-C60 alkyl group, substituted C2-C60 alkenyl group, substituted C2-C60 alkynyl group, substituted C1-C60 alkoxy group, substituted C3-C10 cycloalkyl group, substituted C1-C10 heterocycloalkyl group, substituted C3-C10 cycloalkenyl group, substituted C1-C10 heterocycloalkenyl group, substituted C6-C60 aryl group, substituted C6-C60 aryloxy group, substituted C6-C60 arylthio group, substituted C1-C60 heteroaryl group, substituted monovalent non-aromatic condensed polycyclic group, or substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, or a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C3-C 10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6 -C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13),—N(Q11)(Q12), —B(Q11)(Q12), —C(?O)(Q11), —S(?O)2(Q11), and —P(?O)(Q11)(Q12);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6 -C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a biphenyl group, or a terphenyl group;
a C3-C10 cycloalkyl group. a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6 C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, 13 Si(Q21)(Q22)(Q23), —N(Q21)(Q22), —B(Q21)(Q22), —C(?O)(Q21), —S(?O)2(Q21), and —P(?O)(Q21)(Q22); or
—Si(Q31)(Q32)(Q33), —N (Q31)(Q32), —B(Q31)(Q32), —C(?O)(Q31), —S(?O)2(Q31), or —P(?O)(Q31)(Q32),
wherein Q1 to Q3, Q11 to Q13, Q21 to Q23, and Q31 to Q33 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazino group, a hydrazono group, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10cycloalkenyl group, a C1-C60 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryl group substituted with a C1-C60 alkyl group, a C6-C60 aryl group substituted with a C6-C60 aryl group, a terphenyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryl group substituted with a C1-C60 alkyl group, a C1-C60 heteroaryl group substituted with a C6-C60 aryl group, a monovalent non-aromatic condensed polycyclic group, or a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,461,261

COMPOUND, LIGHT EMITTING MATERIAL, AND ORGANIC LIGHT EMITTING DEVICE

KYUSHU UNIVERSITY, NATION...

1. A compound represented by the following generalformula (2):
wherein in the general formula (2), R1 to R5 each independently represent a hydrogen atom, a cyano group or an alkyl group having from 1 to 10 carbon atoms, provided that R2 and at least one of R1, R4 and R5 represent a cyano group; R6 to R10 each independently represent a hydrogen atom, a cyano group or an alkyl group having from 1 to 10 carbon atoms, provided that at least R7 and two of R6, R9 and R10 represents a cyano group; and R11 to R17 and R21 to R27 each independently represent a hydrogen atom or an alkyl group having from 1 to 10 carbon atoms.

US Pat. No. 10,461,260

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

Universal Display Corpora...

1. A first device comprising a first organic light emitting device, the first organic light emitting device comprising:an anode;
a cathode; and
an emissive layer, disposed between the anode and the cathode, wherein the emissive layer comprises a first light emitting compound having a structure according to Formula 1:

wherein Rf is hydrogen and Ra to Re, Rg, R1 and R2 are independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; and
wherein Ar1 is

wherein Ar2 and Ar3 are independently substituted or unsubstituted aryl or heteroaryl, and Ar1, Ar2, and Ar3 are not connected to one another to form fused ring(s),
wherein L is a direct bond or a linker;
wherein the first light emitting compound emits a luminescent radiation at room temperature when a voltage is applied across the organic light emitting device; and
wherein the luminescent radiation comprises a delayed fluorescence process.

US Pat. No. 10,461,259

ORGANIC LIGHT EMITTING DEVICE

LG CHEM, LTD., Seoul (KR...

1. An organic light emitting device comprising:a first electrode;
a hole transport layer;
a light emitting layer;
a power efficiency enhancement layer;
a gradation enhancement layer; and
a second electrode,
wherein the power efficiency enhancement layer comprises a compound represented by Chemical Formula 1 below, and
the gradation enhancement layer comprises a compound represented by Chemical Formula 2 below:

in Chemical Formula 1,
Ar1 and Ar2 are each independently a substituted or unsubstituted C6-60 aryl; or a substituted or unsubstituted C2-60 heteroaryl containing at least one of O, N, Si and S,
each L is independently a direct bond, or a substituted or unsubstituted C6-60 arylene,
each A is independently a substituted or unsubstituted C6-60 arylene having a meta- or ortho-linking group,
each B is independently a substituted or unsubstituted C6-60 aryl; or a substituted or unsubstituted C2-60 heteroaryl containing at least one of O, N, Si and S,
l is an integer of 0 to 2,
a is an integer of 1 or 2, and
h is an integer of 1 or 2,

in Chemical Formula 2,
Ar3 and Ar4 are each independently a substituted or unsubstituted C6-60 aryl; or a substituted or unsubstituted C2-60 heteroaryl containing at least one of O, N, Si and S,
each P is independently a direct bond, or a substituted or unsubstituted C6-60 arylene,
each Q is independently a substituted or unsubstituted C6-60 arylene having a para-linking group,
each R is independently a substituted or unsubstituted C6-60 aryl; or a substituted or unsubstituted C2-60 heteroaryl containing at least one of O, N, Si and S,
p is an integer of 0 to 2,
q is an integer of 1 or 2, and
r is an integer of 1 or 2.

US Pat. No. 10,461,258

COMPOUND

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by the following formula (1):
wherein in the formula (1), Xs are independently a nitrogen atom or CH, and at least two Xs are nitrogen atoms;
Ar1 and Ar2 are independently a substituted or unsubstituted aromatic hydrocarbon group including 6 to 30 ring carbon atoms or a substituted or unsubstituted aromatic heterocyclic group including 5 to 30 ring atoms;
L1 and L2 are independently a single bond or a substituted or unsubstituted aromatic hydrocarbon group including 6 to 30 ring carbon atoms;
Ar3 is a substituted or unsubstituted aromatic hydrocarbon group including 6 to 15 ring carbon atoms;
Ar4 is a substituted or unsubstituted 6-membered nitrogen-containing aromatic monocyclic group or a substituted or unsubstituted nitrogen-containing aromatic fused ring group in which two or more 6-membered rings are fused; and
Ar5 is represented by any of the following formulas (11) to (13):

wherein in the formula (11), any one of A1 to A12 is a carbon atom that is used for bonding with Ar3, any two of A1 to A12 that are not used for bonding with Ar3 are CR1s, the two R1s are bonded with each other to form a substituted or unsubstituted 6-membered ring, and remaining A1 to A12 are independently a nitrogen atom or CR2; and
R2 is a hydrogen atom or a substituent;
wherein in the formula (12), any one of A21 to A32 is a carbon atom that is used for bonding with Ar3, any two of A21 to A32 that are not used for bonding with Ar3 are CR1s, the two R1s are bonded with each other to form a substituted or unsubstituted 6-membered ring, and remaining A21 to A32 are independently a nitrogen atom or CR2; and
wherein in the formula (13), any one of A41 to A52 is a carbon atom that is used for bonding with Ar3, any two of A41 to A52 that are not used for bonding with Ar3 are CR1s, the two R1s are bonded with each other to form a substituted or unsubstituted 6-membered ring, and remaining A41 to A52 are independently a nitrogen atom or CR2.

US Pat. No. 10,461,257

ANTHRACENE DERIVATIVES, LUMINESCENT MATERIALS AND ORGANIC ELECTROLUMINESCENT DEVICES

IDEMITSU KOSAN CO., LTD.,...

1. An anthracene derivative comprising a phenanthryl group, the anthracene derivative being represented by formula (1-1):
wherein:
L1 represents a single bond in formula (1-1),
Ar1 represents a group represented by formula (2):

or a substituted or unsubstituted fused aromatic ring group having 10 to 50 ring-forming carbon atoms,
wherein the phenanthryl group is bound to the anthracene group of formula (1-1) via a 3 position or 4 position of the phenanthryl group, and wherein when Ar1 represents a group other than a group represented by the above-mentioned general formula (2), and a 3-position of the phenanthryl group is bonded to the anthracene skeleton, Ar1 represents a group other than an unsubstituted 3-phenanthryl group;
wherein substituents Rx, Ra, and Rb each independently represent a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkenyl group having 2 to 50 carbon atoms, a substituted or unsubstituted alkynyl group having 2 to 50 carbon atoms, a substituted or unsubstituted aralkyl group having 7 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 20 carbon atoms, a substituted or unsubstituted alkoxyl group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 20 ring-forming carbon atoms, a substituted or unsubstituted aryl group having 6 to 50 ring-forming carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 50 ring-forming atoms, a substituted or unsubstituted alkylsilyl group having 1 to 30 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 50 ring-forming carbon atoms, a substituted or unsubstituted alkylgermanium group having 1 to 50 carbon atoms, or a substituted or unsubstituted arylgermanium group having 6 to 50 ring-forming carbon atoms;
“p” represents an integer of 0 to 8, “q” represents an integer of 0 to 9, and “y” represents an integer of 0 to 4, and when “p” represents 2 to 8, “q” represents 2 to 9, or “y” represents 2 to 4, a plurality of Rx's a plurality of Ra's, or a plurality of Rb's may be identical to or different from each other, provided that a case where all Rx, Ra, and Rb each represent an anthracenyl group is excluded; and
Arz represents a substituent selected from the group consisting of a substituted or unsubstituted naphthyl group, a substituted or unsubstituted phenanthryl group, a substituted or unsubstituted anthracenyl group, a substituted or unsubstituted benzanthracenyl group, a substituted or unsubstituted naphthacenyl group, a substituted or unsubstituted fluoranthenyl group, a substituted or unsubstituted benzofluoranthenyl group, a substituted or unsubstituted triphenylenyl group, a substituted or unsubstituted chrysenyl group, a substituted or unsubstituted pyrenyl group, a substituted or unsubstituted benzophenanthryl group, a substituted or unsubstituted benzochrysenyl group, and a substituted or unsubstituted heterocycle-containing group having 3 to 50 nucleus forming atoms, when Arz has a plurality of substituents, a plurality of adjacent substituents may be bonded to each other to form in a saturated or unsaturated divalent group that completes a ring.

US Pat. No. 10,461,256

COMPOUND AND PHOTOELECTRIC DEVICE, IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A compound represented by Chemical Formula 1:
wherein, in Chemical Formula 1,
Ar1 to Ar3 are independently one of a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C6 to C30 arene group, a substituted or unsubstituted C3 to C30 heterocyclic group, and a combination thereof in a condensed ring,
R3 is one of hydrogen, deuterium, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C1 to C30 alkoxy group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C3 to C30 heteroaryl group, a halogen, a cyano group, a cyano-containing group, and a combination thereof,
G is one of a single bond, —O—, —S—, —Se—, —N?, —(CRfRg)k—, —NRh—, —SiRiRj—, —GeRkRl, —(C(Rm)?C(Rn))—, and SnRoRp wherein Rf, Rg, Rh, Ri, Rj, Rk, Rl, Rm, Rn, Ro and Rp are independently one of hydrogen, a halogen, a substituted or unsubstituted C1 to C10 alkyl group, a substituted or unsubstituted C1 to C10 alkoxy group, and a substituted or unsubstituted C6 to C12 aryl group, and Ri and Rj, Rk and Rl, Rm and Rn, and Ro and Rp are independently present or linked with each other to provide a ring, and k is one of 1 and 2,
Z1 is one of O or CRbRc, wherein Rb and Rc are independently one of hydrogen, a substituted or unsubstituted C1 to C10 alkyl group, a cyano group, and a cyano-containing group, provided that at least one of Rb and Rc is a cyano group or a cyano-containing group, and
L1 is one of linking groups of Group 1,

wherein, in Group 1,
X1 is one of —Se—, —Te—, —O—, —S(?O)—, —S(?O)2—, —NRa—, —SiRbRc—, and —GeRdRe—,
X2 and X3 are independently one of —S—, —Se—, —Te—, —O—, —S(?O)—, —S(?O)2—, —NRa—, —SiRbRc—, and —GeRdRe—,
Ra to Re are independently one of hydrogen and a substituted or unsubstituted C1l to C10 alkyl group,
R1, R2, R4, and R5 are independently one of hydrogen, deuterium, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C1 to C30 alkoxy group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C3 to C30 heteroaryl group, a halogen, a cyano group, a cyano-containing group, and a combination thereof, and
* is a linking point.

US Pat. No. 10,461,255

ORGANIC LIGHT EMITTING DIODE DISPLAY

Samsung Display Co., Ltd....

1. An organic light emitting diode (OLED) display comprising:a first substrate;
an organic light emitting element disposed on the first substrate;
a first adhesive layer disposed on the organic light emitting element, covering sides of the organic light emitting element;
a second adhesive layer disposed on the first adhesive layer, and the entirety of which does not contact the organic light emitting element; and
a second substrate disposed on the second adhesive layer,
wherein the first adhesive layer and the second adhesive layer include a thermally curable resin or a photocurable resin, respectively,
wherein the second adhesive layer comprises more than about 5 to about 50 parts by weight of a hygroscopic material based on 100 parts by weight of the thermally curable resin or the photocurable resin, and
wherein the first adhesive layer includes a bisphenol-based epoxy resin as the thermally curable resin or the photocurable resin.

US Pat. No. 10,461,254

METHODS OF GRAPHENE GROWTH AND RELATED STRUCTURES

Taiwan Semiconductor Manu...

1. A device, comprising:a substrate having a first surface that includes a curved region;
a conformal graphene layer disposed over the substrate, wherein the conformal graphene layer includes a second surface that follows a first surface contour of the curved region to provide a curved graphene layer within the curved region; and
a source/drain electrode in contact with the conformal graphene layer outside the curved region.

US Pat. No. 10,461,253

HIGH RELIABILITY RF SWITCH BASED ON PHASE-CHANGE MATERIAL

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) switch comprising:a heating element;
a thermally resistive material adjacent to first and second sides of said heating element;
a heat valve under said heating element;
a heat spreader under said heat valve and over a substrate;
a nugget comprising a thermally conductive and electrically insulating material situated on top of said heating element;
a phase-change material having an active segment situated approximately over said nugget and passive segments situated approximately under input/output contacts of said RF switch.

US Pat. No. 10,461,252

RESISTIVE RANDOM ACCESS MEMORY

National Sun Yat-Sen Univ...

1. A resistive random access memory comprising:a first electrode;
a second electrode separate from the first electrode;
an enclosing layer forming a first via-hole; and
an oxygen-containing resistance changing layer arranged for the first via-hole, wherein the first and second electrodes and the enclosing layer jointly enclose the oxygen-containing resistance changing layer, wherein each of the first electrode, the second electrode and the enclosing layer is made of an element not containing oxygen, wherein each of the first electrode, the second electrode and the enclosing layer abuts with the oxygen-containing resistance changing layer, wherein the enclosing layer is mounted on one of the first and second electrodes, and
wherein the oxygen-containing resistance changing layer is formed from oxides doped with chlorine and is completely located in the first via-hole, wherein the first electrode is not parallel to the second electrode, wherein the enclosing layer encloses the first electrode but does not enclose the second electrode, and wherein the enclosing layer is in contact with a bottom face of the second electrode.

US Pat. No. 10,461,251

METHOD OF MANUFACTURING INTEGRATED CIRCUIT USING ENCAPSULATION DURING AN ETCH PROCESS

EVERSPIN TECHNOLOGIES, IN...

1. A method of fabricating a magnetoresistive bit from a magnetoresistive stack including (i) a first magnetic region, (ii) an intermediate region disposed over the first magnetic region, and (iii) a second magnetic region disposed over the intermediate region, the method comprising:etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls, wherein at least a portion of the sidewalls includes redeposited material after the etching;
modifying at least a portion of the redeposited material on the sidewalls, wherein the modifying step includes rendering at least a portion of the redeposited material on the sidewalls electrically-nonconductive; and
etching through a second portion of the magnetoresistive stack after the modifying step.

US Pat. No. 10,461,250

MAGNETORESISTIVE STACK/STRUCTURE AND METHOD OF MANUFACTURING SAME

EVERSPIN TECHNOLOGIES, IN...

1. A method of manufacturing a magnetoresistive stack/structure from: (i) a first magnetic region including one or more layers of magnetic material, (ii) an intermediate layer disposed over the first magnetic region, and (iii) a second magnetic region including one or snore layers of magnetic material, wherein the second magnetic region is disposed over the intermediate layer, the method comprising:using a first etch process to etch through the second magnetic region to form one or more first sidewalls and expose an area of the intermediate layer, wherein the one or more first sidewalls and the area of the intermediate layer exposed by the first etch process form exposed surfaces, and wherein at least a portion of the exposed surfaces, after the first etch process, includes re-deposited material;
depositing a first encapsulation layer on the exposed surfaces after the first etch process;
after depositing the first encapsulation layer, using a second etch process to remove at least a portion of the re-deposited material from the exposed surfaces; and
after removing at least a portion of the re-deposited material, etching through the intermediate layer to form one or more second sidewalls; and
depositing a second encapsulation layer on the one or more second sidewalls.

US Pat. No. 10,461,249

MANUFACTURING METHOD OF MAGNETO-RESISTIVE EFFECT DEVICE

CANON ANELVA CORPORATION,...

1. A manufacturing method of a magneto-resistive effect device, the manufacturing method comprising steps of:forming an Mg film on a substrate on which a reference layer is formed, and oxidizing the Mg film to form an MgO layer on the reference layer;
heating the substrate on which the MgO layer is formed;
forming an Mg layer on the MgO layer after the step of heating;
cooling the substrate on which the Mg layer is formed;
forming a first free layer on the Mg layer in a state where the substrate is cooled by the cooling step; and
forming a second free layer on the first free layer at a room temperature after the step of cooling,
wherein the step of forming the Mg layer, the step of cooling, and the step of forming the first free layer are performed in the same process chamber, and the step of forming the second free layer is performed in a process chamber that is different from the same process chamber.

US Pat. No. 10,461,248

BOTTOM ELECTRODE FOR MRAM APPLICATIONS

INTERNATIONAL BUSINESS MA...

1. A process of forming a bottom electrode in a magnetoresistive random access memory (MRAM) device, the process comprising:providing a structure comprising a dielectric layer including a patterned feature lined with a barrier layer and a metal conductor;
planarizing a surface of the structure stopping at the dielectric layer to remove an overburden of the metal conductor;
forming a recess in the metal conductor;
depositing a conductive liner material in the recess of the metal conductor and on the dielectric layer;
depositing tantalum nitride cap layer in the recess on the conductive liner material and on the dielectric layer; and
polishing the tantalum nitride cap layer to the dielectric layer with a chemical mechanical planarization process to form the bottom electrode, wherein a height differential between upper surfaces of the tantalum nitride cap layer and the dielectric layer is less than 3 nanometers, wherein the conductive liner material is harder than the tantalum nitride.

US Pat. No. 10,461,247

INTEGRATED MAGNETIC RANDOM ACCESS MEMORY WITH LOGIC DEVICE HAVING LOW-K INTERCONNECTS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate defined with at least first, second and third regions, wherein the substrate includes a first interlevel dielectric (ILD) layer;
a first upper dielectric layer disposed over the first ILD layer, wherein the first upper dielectric layer serves as a lower portion of a via level of a second ILD layer above the first ILD layer, the first upper dielectric layer includes a bottom electrode trench disposed in the second region and an alignment trench disposed in the third region, the bottom electrode trench exposes a metal line in the first ILD layer, the alignment trench has an alignment trench depth which is deeper than a bottom electrode trench depth of the bottom electrode trench, and the alignment trench extends into the first ILD layer;
a bottom electrode disposed in the bottom electrode trench;
a bottom electrode alignment mark disposed in the alignment trench; and
a magnetic tunnel junction (MTJ) element disposed on the bottom electrode,
wherein the bottom electrode comprises a bottom electrode material disposed in the bottom electrode trench, and the bottom electrode alignment mark comprises the bottom electrode material disposed in the alignment trench.

US Pat. No. 10,461,246

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:a bottom electrode;
a resistance switching element over the bottom electrode;
a top electrode over the resistance switching element;
an interlayer dielectric layer surrounding the resistance switching element;
a first spacer between the interlayer dielectric layer and a sidewall of the resistance switching element, wherein a bottom surface of the first spacer is over a top surface of the bottom electrode; and
a metal-containing compound layer between the interlayer dielectric layer and the sidewall of the resistance switching element.

US Pat. No. 10,461,245

MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A magnetic memory device comprising:a stack structure which is formed on an underlying area and includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer;
a protective insulating film covering the stack structure and provided along upper and side surfaces of the stack structure; and
an interlayer insulating film covering upper and side surfaces of the protective insulating film,
wherein:
a portion of the protective insulating film formed on the side surface of the stack structure is thicker than a portion of the protective insulating film formed on the upper surface of the stack structure,
the protective insulating film includes a first protective insulating film formed along the side surface of the stack structure, and a second protective insulating film covering the stack structure and the first protective insulating film,
a side surface of the first magnetic layer, a side surface of the nonmagnetic layer, and a side surface of the second magnetic layer are provided continuously without a step,
the first protective insulating film covers the side surfaces of the first magnetic layer, the nonmagnetic layer, and the second magnetic layer, and
an oxygen concentration at a boundary between the first protective insulating film and the second protective insulating film is higher than that within the first protective insulating film and that within the second protective insulating film.

US Pat. No. 10,461,244

LAMINATED STRUCTURE AND SPIN MODULATION ELEMENT

TDK CORPORATION, Tokyo (...

1. A laminated structure, comprising:a ferromagnetic layer; and
a multiferroic layer formed on one surface of the ferromagnetic layer,
wherein a surface of the multiferroic layer on the ferromagnetic layer side includes a first region, a crystalline phase of which is rhombohedral, and a second region, a crystalline phase of which is tetragonal,
a proportion of the first region occupying the surface is 30% or more and 70% or less, and
a proportion of the second region occupying the surface is 30% or more and 70% or less.

US Pat. No. 10,461,243

TUNING MAGNETIC ANISOTROPY FOR SPIN-TORQUE MEMORY

Everspin Technologies, In...

13. A magnetoresistive device, comprising:a fixed portion, wherein a magnetic state for the fixed portion is in a predetermined state;
a free portion, wherein the free portion includes:
a first magnetic layer having a first perpendicular magnetic anisotropy field parameter, wherein the first perpendicular magnetic anisotropy field parameter corresponds to a first magnetic field that is required to move a magnetic state of the first magnetic layer from a position along an easy axis of the first magnetic layer to a position perpendicular to the easy axis of the first magnetic layer;
a second magnetic layer having second perpendicular magnetic anisotropy field parameter, wherein the second perpendicular magnetic anisotropy field parameter corresponds to a second magnetic field that is required to move a magnetic state of the second magnetic layer from a position along an easy axis of the second magnetic layer to a position perpendicular to the easy axis of the second magnetic layer, wherein the second magnetic layer is more susceptible to changes in magnetic state in response to a spin-torque switching current than the first magnetic layer; and
a coupling layer between the first magnetic layer and the second magnetic layer; and
a first dielectric layer adjacent the second magnetic layer, wherein the first dielectric layer is between the fixed portion and the free portion.

US Pat. No. 10,461,242

ANTIFERROMAGNETIC EXCHANGE COUPLING ENHANCEMENT IN PERPENDICULAR MAGNETIC TUNNEL JUNCTION STACKS FOR MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS

SPIN MEMORY, INC., Fremo...

1. A magnetic memory element, comprising:a magnetic free layer;
a magnetic reference layer;
a non-magnetic barrier layer located between the magnetic reference layer and the magnetic free layer; and
a synthetic antiferromagnetic structure exchange coupled with the magnetic reference layer, the synthetic antiferromagnetic structure further comprising:
a first magnetic structure;
a second magnetic structure; and
an antiferromagnetic exchange coupling structure located between the first and second magnetic structures, the antiferromagnetic exchange coupling structure including a layer of Ru located between first and second layers of Pt.

US Pat. No. 10,461,241

METHOD FOR MANUFACTURING RECTANGULAR PARALLELEPIPED-SHAPED SINGLE CRYSTAL, RECTANGULAR PARALLELEPIPED-SHAPED SINGLE CRYSTAL, METHOD FOR MANUFACTURING CERAMICS, CERAMICS, PIEZOELECTRIC ELEMENT, PIEZOELECTRIC DEVICE, AND ELECTRONIC DEVICE

Canon Kabushiki Kaisha, ...

1. A rectangular parallelepiped-shaped single crystal containing sodium niobate of a perovskite structure as a main component, whereinthe rectangular parallelpiped-shaped single crystal contains bismuth in an amount of 0.05 mol or more and 0.15 mol or less per mole of the sodium niobate,
a Na/Nb ratio of the rectangular parallelepiped-shaped single crystal is 0.82 or more and 1.00 or less, and
a ratio of a longest side length (Lmax) to a shortest side length (Lmin) of the rectangular parallelepiped is in a range of Lmax/Lmin of 4.0?Lmax/Lmin?8.5.

US Pat. No. 10,461,240

PIEZOELECTRIC SENSORS AND METHODS FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A piezoelectric sensor, comprising a first electrode layer, a second electrode layer and a piezoelectric thin film layer between the first electrode layer and the second electrode layer, the piezoelectric sensor further comprising:a first functional module and a second functional module, both of which are connected to the second electrode layer, wherein the first functional module is configured to sense a pressure applied to the piezoelectric sensor in a first direction, and the second functional module is configured to sense a pressure applied to the piezoelectric sensor in a second direction, and the first direction and the second direction are perpendicular to each other.

US Pat. No. 10,461,239

MICROSCALE SENSOR STRUCTURE WITH BACKSIDE CONTACTS AND PACKAGING OF THE SAME

INTERDISCIPLINARY CONSULT...

1. A microscale sensor comprising: a device layer having a front side and a back side, the front side of the device layer being positioned for exposure to a passing fluid; a support substrate at the back side of the device layer, the support substrate having contact openings for accessing a conductive backside surface at the back side of the device layer, wherein electrical connection to the device layer is not formed with a through-wafer via; and wherein the microscale sensor is configured to be flush mounted.

US Pat. No. 10,461,238

THERMOELECTRIC CONVERSION STRUCTURE AND METHOD FOR MAKING THE SAME

NEC Corporation, Tokyo (...

1. A thermoelectric conversion structure, comprising:a plurality of thermoelectric conversion unit structures, wherein each thermoelectric conversion unit structure comprises a magnetic fine particle comprising a magnetic material that exhibits a spin Seebeck effect and an electromotive body that covers the magnetic fine particle,
wherein the electromotive bodies of the plurality of thermoelectric conversion unit structures are connected to each other,
the plurality of thermoelectric conversion unit structures forms an aggregate, and
all surfaces of each of the magnetic fine particles are in direct physical contact with the aggregate.

US Pat. No. 10,461,237

THERMOELECTRIC DEVICE

Mahle International GmbH,...

1. A thermoelectric device, comprising:a plurality of electrically conductive first threads and a plurality of electrically insulating second threads structured and arranged to define a fabric;
at least one first thread of the plurality of electrically conductive first threads including a plurality of p-doped thread sections and a plurality of n-doped thread sections arranged in alternating relationship with one another; and
the plurality of electrically conductive first threads extending in a wavy course defining a plurality of curvature-turning points;
wherein the plurality of p-doped thread sections and the plurality of n-doped thread sections are arranged in a respective curvature-turning point of the plurality of curvature-turning points; wherein one of: the plurality of electrically conductive first threads are arranged as warp threads of the fabric, and the plurality of electrically insulating second threads are arranged as weft threads of the fabric; and the plurality of electrically conductive first threads are arranged as the weft threads of the fabric, and the plurality of electrically insulating second threads are arranged as the warp threads of the fabric.

US Pat. No. 10,461,236

THERMOELECTRIC GENERATOR

KABUSHIKI KAISHA TOSHIBA,...

1. A thermoelectric generator comprising:a thermoelectric device that converts heat energy into electric energy; and
a DC to DC converter that converts an input voltage applied by the thermoelectric device to a voltage higher than the input voltage applied by the thermoelectric device, wherein
the input voltage applied by the thermoelectric device is higher than a voltage which is half an open voltage of the thermoelectric device,
the DC to DC converter includes:
a first switch which is ON/OFF-controlled in accordance with a switch control signal whose ON time is variable;
an inductor connected to the first switch;
a second switch that switches between a state where a current is supplied from the thermoelectric device to the inductor and a state where no current is supplied from the thermoelectric device to the inductor; and
a sample and hold circuit that samples the open voltage of the thermoelectric device when the second switch is in the state where no current is supplied from the thermoelectric device to the inductor, and holds the sampled open voltage of the thermoelectric device,
the input voltage applied by the thermoelectric device increases or decreases in accordance with the ON time,
the ON time is subjected to feedback control such that the input voltage applied by the thermoelectric device approaches to a value obtained by multiplying the held open voltage of the thermoelectric device by a gain, and
the gain is determined based on an output resistance of the thermoelectric device, a parasitic resistance of the inductor, a parasitic resistance of the first switch, and a parasitic resistance of the second switch.

US Pat. No. 10,461,235

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a semiconductor device, the method comprising:disposing a substrate metal film on an upper surface of a substrate made of a metal;
disposing a first element metal film on a lower surface of a first element;
disposing a second element metal film on a lower surface of a second element;
after disposing the substrate metal film, the first element metal film and the second element metal film, bonding the first element and the second element to the substrate so that an upper surface of the substrate metal film is in contact with a lower surface of the first element metal film and a lower surface of the second element metal film;
after bonding the first element and the second element to the substrate, oxidizing at least a portion of a region of the upper surface of the substrate metal film other than regions in contact with the first element metal film and the second element metal film; and
after oxidizing the at least portion of the region of the upper surface of the substrate metal film other than the regions in contact with the first element metal film and the second element metal film, disposing a wiring electrically connecting the first element and the second element, across and above a region including the region oxidized in the oxidizing step.

US Pat. No. 10,461,234

METAL-BASE SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A method for manufacturing a metal-base substrate comprising:preparing a film substrate by forming a wiring layer on a first surface of the film substrate;
forming a through hole on a ground part of the wiring layer, with the through hole piercing through the film substrate in a thickness direction of the film substrate; and
after the forming of the through hole, sticking a metal plate on a second surface of the film substrate opposite from the first surface, with an adhesive layer being interposed between the metal plate and the film substrate.

US Pat. No. 10,461,233

LIGHT EMITTING DEVICE PACKAGE AND LIGHTING DEVICE

LG INNOTEK CO., LTD., Se...

1. A light emitting device package, comprising:a first lead frame;
a light emitting device disposed on the first lead frame;
a second lead frame spaced apart from the first lead frame in a first direction;
a protective device disposed on the second lead frame; and
a body coupled to the first and second lead frames,
wherein the body including a cavity exposing a portion of an upper surface of the first lead frame and an upper surface of the second lead frame,
wherein the cavity includes first to fourth inner side surfaces which are inclined, respectively,
wherein the first inner side surface faces the second inner side surface in the first direction,
wherein the third inner side surface faces to the fourth inner side surface in a second direction,
wherein the first to fourth inner side surfaces face the first to fourth sides of the light emitting device, respectively,
wherein the cavity has a first bottom surface that exposes a part of an upper surface of the first lead frame; a second bottom surface on which a part of an upper surface of the second lead frame is exposed and on which the protection device is disposed; and a third bottom surface on which a part of the upper surface of the second lead frame is exposed and spaced apart from the second bottom surface,
wherein the first lead frame comprises a first stepped portion disposed along an edge of a lower surface thereof and at least one first through hole,
wherein the first through hole includes a second stepped portion disposed at an inner side thereof,
wherein the cavity includes a first recess portion exposing the second lead frame and a second recess portion exposing the first lead frame,
wherein the second lead frame comprises a third stepped portion disposed along an edge of a lower surface thereof, and a mounting region of the protective device which is not overlapped in a vertical direction and spaced apart from the third stepped portion,
wherein a part of the second recess portion is overlapped with the third stepped portion in the vertical direction,
wherein a minimum distance between the first recess portion and the second recess portion is greater than a length of one side of the light emitting device, and
wherein the first recess portion is not overlapped with a second side of the light emitting device in the first direction.

US Pat. No. 10,461,231

METHOD FOR FABRICATING LED PACKAGE

LUMENS CO., LTD., Yongin...

1. A method for fabricating light emitting device packages, comprising:preparing light emitting device units formed by arranging a plurality of light emitting devices on a sheet, filling a light transmitting material between the light emitting devices arranged on the sheet to form a light-transmitting member, curing the light-transmitting material, obliquely cutting the light-transmitting material relative to the individual light emitting devices and separating the individual light emitting devices from the sheet;
mounting and arranging the light emitting device units on a substrate; attaching wavelength converting members to the respective light emitting device units mounted and arranged on the substrate;
filling a reflective material between the light emitting device units attached with the wavelength converting members to form a reflective member; and
vertically cutting the reflective material such that the reflective material surrounds the individual light emitting device units attached with the wavelength converting members.

US Pat. No. 10,461,230

LIGHT EMITTING DIODE COMPONENT

Koninklijke Philips N.V.,...

1. A method, comprising:providing a light emitting semiconductor structure grown on a growth substrate;
removing at least a portion of the growth substrate; and
forming a multilayer structure arranged to guide light out from a surface of the light emitting semiconductor structure, the multilayer structure covering the surface of the light emitting structure, the multilayer structure comprising a plurality of layers, wherein an i+1:th layer is arranged on top an i:th layer in a sequence as seen from the light emitting semiconductor structure, wherein a refractive index, ni, of the i:th layer is greater than a refractive index, ni+1, of the i+1:th layer, wherein the value of i is selected from the set of positive integers, wherein a thickness of the i+1:th layer is greater than a thickness of the i:th layer.

US Pat. No. 10,461,229

PACKAGE FOR ULTRAVIOLET EMITTING DEVICES

RayVio Corporation, Hayw...

1. A device comprising:a light emitting diode comprising a semiconductor structure comprising an active layer disposed between an n-type region and a p-type region, wherein the active layer emits UV radiation;
a mount, wherein the light emitting diode is disposed on the mount, the mount comprising a support structure that surrounds the light emitting diode;
the support structure defining a cavity within which the light emitting diode is located, the support structure providing a first surface surrounding a top of the cavity;
a transparent optic disposed over the light emitting diode, the transparent optic comprising tabs extending from a top portion of the optic, where the tabs rest on the first surface of the support structure; and
the optic being a pre-formed solid structure that is positioned within the cavity such that the optic only takes up a portion of the cavity, wherein there is a gap between sidewalls of the cavity and the optic, the optic tapering inward as it approaches the light emitting diode within the cavity.

US Pat. No. 10,461,227

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device, comprising:a light emitting element,
a package having a recess in which the light emitting element is located, and
a sealing resin filling the recess,
wherein the package includes a projection extending from an upper surface of the package, the projection at least partially surrounding the recess,
wherein a roughened surface section is formed on an upper surface of the projection,
wherein the upper surface of the projection on which the roughened surface section is formed is inclined in a direction away from the light emitting element, and
wherein the upper surface of the projection has an inner edge and an outer edge, and the roughened surface section on the upper surface of the projection extends from the inner edge to the outer edge.

US Pat. No. 10,461,226

SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor light emitting device package comprising:a substrate;
a semiconductor light emitting device on the substrate; and
an encapsulation layer which covers the semiconductor light emitting device,
wherein the encapsulation layer comprises:
a plurality of ring portions which are disposed sequentially from an edge toward a center of the substrate, in a plan view; and
a center portion which is surrounded by an innermost one of the plurality of ring portions,
wherein the semiconductor light emitting device package further comprises a dam structure which extends along an outer sidewall of an outermost one of the plurality of ring portions, and
wherein the dam structure is substantially transparent.

US Pat. No. 10,461,225

METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE INCLUDING SEALING MATERIALS WITH PHOSPHOR PARTICLES

TOYODA GOSEI CO., LTD., ...

1. A method of manufacturing a light-emitting device, the method comprising:providing a case comprising a recessed portion and mounting a light-emitting element on a bottom of the recessed portion;
putting a first sealing material comprising a first phosphor particle into the recessed portion;
putting a second sealing material comprising a second phosphor particle on the first sealing material in the recessed portion;
precipitating the second phosphor particle before curing the second sealing material; and
curing the first sealing material and the second sealing material after the precipitating of the second phosphor particle,
wherein the second phosphor particle is located above the first phosphor particle after the first and second sealing materials cure,
wherein the precipitating of the second phosphor particle is conducted so as to form a layer of the second phosphor particle at a bottom of the second sealing material before the curing of the first sealing material and the second sealing material, and
wherein the first phosphor particle and the second phosphor particle are different in a degree of precipitation.

US Pat. No. 10,461,224

MOLDED NANOPARTICLE PHOSPHOR FOR LIGHT EMITTING APPLICATIONS

Nanoco Technologies Ltd.,...

1. A light emitting device, the device comprising:a light emitting diode (LED) package, the LED package comprising:
a housing; and
an LED located within the housing; and
a phosphor composition disposed within the housing and in optical communication with the LED, the phosphor composition comprising:
a molded matrix material;
a plurality of nanoparticles suspended within the molded matrix material; and
a gas barrier material coated upon every surface of the molded matrix material.

US Pat. No. 10,461,223

SEMICONDUCTOR DEVICE

Epistar Corporation, Hsi...

1. A semiconductor device, comprising:a semiconductor stack comprising a surface; and
an electrode structure comprising an electrode pad formed on the surface, wherein the electrode structure further comprises a first extending electrode, a second extending electrode and a third extending electrode connecting to the electrode pad, and the first extending electrode is closer to a periphery of the surface than the third extending electrode is, and the second extending electrode is between the first extending electrode and the third extending electrode;
wherein, from a top view of the semiconductor device, the first extending electrode, the second extending electrode and the third extending electrode respectively comprise a first curve having a first angle ?1, a second curve having a second angle ?2 and a third curve having a third angle ?3, wherein ?3>?2>?1 .

US Pat. No. 10,461,222

LIGHT-EMITTING ELEMENT COMPRISING SAPPHIRE SUBSTRATE WITH CONVEX PORTIONS

NICHIA CORPORATION, Anan...

1. A light-emitting element comprising:a sapphire substrate having a c-plane at a main surface thereof; and
a semiconductor layer located on a main surface side of the sapphire substrate,
wherein the sapphire substrate comprises:
a first convex portion located at the main surface and having two longitudinal sides along a first m-axis of the sapphire substrate,
a second convex portion located at the main surface and having two longitudinal sides along a second m-axis of the sapphire substrate, and
a third convex portion located at the main surface and having two longitudinal sides along a third m-axis of the sapphire substrate,
wherein the second m-axis is rotated counterclockwise by 120° from the first m-axis, and the third m-axis is rotated counterclockwise by 120° from the second m-axis,
wherein a first line extending through the third convex portion and parallel to the third m-axis passes through the first convex portion in a plan view;
wherein a second line extending parallel to the second m-axis and tangent to an end of the first convex portion at a second-convex-portion side does not pass through the third convex portion; and
wherein the first convex portion and the third convex portion are on opposite sides of the second line.

US Pat. No. 10,461,221

SEMICONDUCTOR DEVICE WITH IMPROVED LIGHT PROPAGATION

Sensor Electronic Technol...

1. A semiconductor structure comprising:a layer transparent to radiation having a target wavelength, wherein radiation of the target wavelength enters the transparent layer through a first side and exits the transparent layer through a second side, and wherein the second side comprises a profiled surface, the profiled surface including a plurality of vacancies fabricated in the material of the layer, wherein each vacancy comprises side walls configured for at least partial diffusive scattering of the radiation of the target wavelength, wherein an average thickness of each of the plurality of vacancies is approximately one tenth of an average distance between adjacent vacancies in the plurality of vacancies.

US Pat. No. 10,461,220

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

IMEC, Leuven (BE)

1. A method of fabricating a light-emitting semiconductor device, the method comprising:providing a light-emitting layer stack;
forming a stop layer over the light-emitting layer stack;
forming a light-transmission layer on the stop layer, the light-transmission layer formed of a crystalline III-V semiconductor material that is optically transmissive to emission wavelengths of the light-emitting layer stack;
patterning a mask layer on the light-transmission layer such that portions of the light-transmission layer are exposed;
thermally texturing in an atmosphere comprising molecular hydrogen (H2) and ammonia, the thermally texturing comprises decomposing the light-transmission layer at the exposed portions into chemical constituents of the III-V semiconductor material and redepositing to form a plurality of crystals of the III-V semiconductor material having triangular crystal facets; and
stopping the thermal texturing by locally stopping the decomposing and redepositing at an interface formed by the stop layer and the light-transmission layer,
wherein the stop layer has a decomposition temperature that is higher than that of the light-transmission layer such that texturing is prevented from extending into the stop layer.

US Pat. No. 10,461,219

LIGHT EMITTING ELEMENT

NICHIA CORPORATION, Anan...

1. A light emitting element comprising:a semiconductor layered structure comprising an n-side semiconductor layer and a p-side semiconductor layer each made of a nitride semiconductor and at least partially overlapped with each other;
an n-pad electrode disposed on an upper surface of the n-side semiconductor layer in a different region from where the p-side semiconductor layer is disposed;
a light-transmissive electrically conductive film disposed on an upper surface of the p-side semiconductor layer; and
a p-pad electrode disposed on an upper surface of the light-transmissive electrically conductive film,
wherein, when viewed in a plan view,
an outer peripheral shape of the semiconductor layered structure has a pentagonal shape having a first side, a second side adjacent to the first side at a right angle to the first side, a third side adjacent to the first side at a right angle to the first side, a fourth side adjacent to the second side at an obtuse angle to the second side, and a fifth side adjacent to the third side and the fourth side at an obtuse angle to the third side, the fourth side and the fifth side meet to form a first vertex,
the n-pad electrode is disposed closer to the first side than to the first vertex, and
the p-pad electrode is disposed closer to the first vertex than the n-pad electrode is disposed to the first vertex.

US Pat. No. 10,461,218

SEMICONDUCTOR DEVICE

LG INNOTEK CO., LTD., Se...

1. A semiconductor device comprising:a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a plurality of recesses through which a lower portion of the first conductive semiconductor layer is exposed;
at least one pad arranged outside the light emitting structure, and arranged to be adjacent to at least one edge; and
a plurality of insulation patterns arranged inside the recesses and extending to a lower surface of the light emitting structure,
wherein widths of the plurality of insulation patterns are reduced as the insulation patterns become further away from the pad,
wherein the pad includes a first pad arranged to be adjacent to a first edge and a second pad arranged to be adjacent to a second edge, and
wherein widths of the plurality of insulation patterns are reduced as the insulation patterns go from the first edge toward a third edge in a diagonal direction.

US Pat. No. 10,461,217

VERTICAL STRUCTURE LEDS

LG INNOTEK CO., LTD., Se...

20. A method for manufacturing a light emitting diode, comprising:forming a GaN-based semiconductor structure with a thickness of a less than 5 microns on a substrate, the GaN-based semiconductor layer comprising:
a p-type GaN-based semiconductor layer;
an active layer on the p-type GaN-based semiconductor layer; and
an n-type GaN-based semiconductor layer on the active layer;
forming a p-type electrode having multiple metal layers on the p-type GaN-based semiconductor layer with contacting a bottom surface of the Gall-based semiconductor structure;
forming a metal support layer comprising Ti and non-metal material on the p-type electrode, a top surface of the metal support layer contacting the p-type electrode;
removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure;
forming an n-type electrode comprising Ti and Al on the upper surface of the GaN-based semiconductor structure, with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure;
forming an insulating layer including at least one of SiO2 or Si3N4, on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure;
forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and
forming a metal pad layer at the open space, an uppermost surface of the metal pad layer being formed at a higher position than the first part of the insulating layer,
wherein a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

US Pat. No. 10,461,216

GALLIUM NITRIDE CROSS-GAP LIGHT EMITTERS BASED ON UNIPOLAR-DOPED TUNNELING STRUCTURES

Wright State University, ...

1. A solid-state device, comprising:a unipolar doped light emitting diode or laser diode comprising:
a bottom n-type layer;
a top n-type layer;
an undoped or n-type doped middle layer inserted between the top layer and bottom layer, where the middle layer comprises at least two materials which serve as one or more heterojunction tunnel barriers;
and where the top layer and the middle layer, the bottom layer and the middle layer, or both form an interband tunnel barrier for electrons that generate holes by interband Zener tunneling through the forbidden energy gap, and where the middle layer forms at least one intraband tunnel barrier to control the interband Zener tunneling within the active region of the light emitting diode or the laser diode.

US Pat. No. 10,461,215

METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light-emitting device, the method comprising:directly bonding a plurality of light-emitting elements to a collective light-transmissive member having a plate shape, each light-emitting element comprising a plurality of electrodes;
subsequently, forming stud bumps on each electrode of each light-emitting element;
subsequently, dividing the collective light-transmissive member to obtain a plurality of light-transmissive members on each of which one or more of the light-emitting elements are bonded; and
subsequently, mounting the light-emitting elements on or above a mounting base by a flip-chip technique.

US Pat. No. 10,461,214

METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE

TOYODA GOSEI CO., LTD., ...

1. A method for producing a Group III nitride semiconductor light-emitting device, the method comprising:forming an oxide film containing Al atoms, N atoms, and O atoms by uniformly oxidizing an entire surface of at least one substrate of an AlN substrate and an AlGaN substrate;
forming a first Group III nitride layer on the oxide film;
forming a first conductive type first semiconductor layer on the first Group III nitride layer;
forming a light-emitting layer on the first semiconductor layer; and
forming a second conductive type second semiconductor layer on the light-emitting layer,
wherein, in the forming the first Group III nitride layer, the AlN layer or the AlGaN layer is formed as the first Group III nitride layer under a condition that a temperature of the substrate is 1200° C. to 1450° C.,
wherein, in the forming the oxide film, AlON or AlGaON is formed as the oxide film for inverting a polarity, and the polarity is inverted between the substrate and the first Group III nitride layer formed on the oxide film by the oxide film, and
wherein, in the forming the oxide film, octahedral crystals of O and Al are formed as the oxide film.

US Pat. No. 10,461,213

METHOD OF MANUFACTURING SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A method of manufacturing a solar cell, the method comprising:forming a photoelectric converter including an amorphous semiconductor layer;
forming an electrode connected to the photoelectric converter; and
performing a post-treatment by providing light to the photoelectric converter and the electrode,
wherein, in the performing of the post-treatment, a plasma lighting system (PLS) is used as a light source, and a processing temperature is within a range from about 100° C. to about 300° C.,
wherein a cover substrate is located on a front surface of the light source, and
wherein the cover substrate includes a plurality of substrates having different indices of refraction.

US Pat. No. 10,461,212

METHOD FOR PROCESSING SILICON MATERIAL

NewSouth Innovations Pty ...

1. A method for manufacturing a photovoltaic device, the method comprising the steps of:providing a substrate that comprises a silicon p-n junction;
annealing the substrate at a temperature between 500° C. and 700° C. in the presence of a hydrogen source for a first predetermined period of time to allow hydrogen atoms to penetrate into silicon material of the silicon p-n junction; and
exposing the substrate to electromagnetic radiation while the substrate is kept at a temperature between 150° C. and 400° C. in a manner such that photons with an energy higher than that of a bandgap of the silicon material are provided at a radiation intensity of at least 20 mW/cm2 and an excess of minority carriers is created in the silicon material;
wherein, during the steps of annealing the substrate and exposing the substrate to electromagnetic radiation, electrically active defects in the silicon material are passivated.

US Pat. No. 10,461,211

PROCESS FOR PRODUCING AN ARRAY OF MESA-STRUCTURED PHOTODIODES

1. A process for producing an array of mesa-structured photodiodes, including at least the following steps:a) producing a layer, referred to as the useful layer, including an upper face and an opposite lower face, resting on a carrier layer via the lower face, including a stack of a first zone located at the upper face and having a first doping type, and of a second zone located between the first zone and the carrier layer having a second doping type, opposite the first type;
b) producing an etch mask positioned on said upper face, formed of a plurality of pads, referred to as etch pads which are distinct from one another;
c) wet-etching a part of the useful layer located between the etch pads, thus forming a plurality of mesa-structured photodiodes, each having an upper surface on which one of said etch pads rests, said wet etch being adapted so that the upper surface of each photodiode has a mean lateral dimension that is smaller than that of the corresponding etch pad, thus forming a recess between the etch pad and the corresponding photodiode;
d) conformally depositing, on the etch pads and the photodiodes, a passivation layer made of at least one dielectric or semiconductor material, with deposition conditions chosen so that the passivation layer has a local thickness that is less than or equal to 200 nm below the recess, and a columnar polycrystalline structure, the columns of which extend longitudinally along the thickness of the passivation layer with a constant transverse dimension, and are separated laterally from one another by grain boundaries;
e) removing the etch pads by chemical dissolution, thus leaving the upper surface exposed, a surface, referred to as the lateral surface of the photodiodes, which surrounds the upper surface, being covered by the passivation layer;
f) producing electrically conductive pads on and in contact with the upper surface.

US Pat. No. 10,461,210

METHOD FOR MANUFACTURING A DETECTION DEVICE WITH TWO SUBSTRATES AND SUCH A DETECTION DEVICE

1. A method for manufacturing a device for detecting electromagnetic radiation, the method including the following steps:supplying a first substrate, the first substrate integrating a reading circuit and comprising a first surface and a second surface, the first substrate further including at least two first contact plugs connected to the reading circuit and at least one first annular bonding element surrounding the first contact plugs, the first contact plugs and the first annular bonding element each being at least in part exposed on the first surface of the first substrate,
supplying a second substrate, the second substrate including:
a first surface of the second substrate and a second surface of the second substrate,
at least one detection structure, for the detection of electromagnetic radiation, provided with at least two connecting arms each extending by a second contact plug complementary to one corresponding first contact plug,
a sacrificial material enclosing the detection structure, the first connecting arm and the second connecting arm,
a cap including the first surface of the second substrate,
at least one annular side wall extending from the cap, the annular side wall forming with the cap a cavity housing the detection structure and the sacrificial material, the annular side wall being provided, on one end opposite to the cap, with a second annular bonding element complementary to the first annular bonding element,
wherein the second contact plugs and the second annular bonding element are each at least in part exposed on the second surface of the second substrate,
bonding the second surface of the second substrate on the first surface of the first substrate by bonding the second annular bonding element on the first annular bonding element and bonding the first contact plugs on the second contact plugs,
arranging at least one opening in the second substrate,
selective elimination of the sacrificial material,
closing said opening under at least a primary vacuum whereby the device for detecting electromagnetic radiation is formed.

US Pat. No. 10,461,209

AVALANCHE PHOTODIODE FOR DETECTING ULTRAVIOLET RADIATION AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. An avalanche photodiode for detecting ultraviolet radiation, comprising:a semiconductor body having a front surface and forms including:
a silicon carbide substrate having a first type of conductivity at a first dopant level;
a first silicon carbide epitaxial layer having the first type of conductivity at a second dopant level less than the first dopant level;
a second silicon carbide epitaxial layer having a third dopant level between the first and second dopant levels, the first silicon carbide epitaxial layer being positioned between the silicon carbide substrate and the second silicon carbide epitaxial layer, at least a portion of the second silicon carbide epitaxial layer being a cathode region; and
a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer and having a fourth dopant level less than the third dopant level;
an anode region extending completely through the third silicon carbide epitaxial layer and having a second type of conductivity, which extends into said semiconductor body starting from the front surface and contacts the cathode region; and
a guard ring having the second type of conductivity, which extends into said semiconductor body starting from the front surface and completely laterally surrounds the anode region.

US Pat. No. 10,461,208

SOLAR CELL AND METHOD FOR PRODUCING SAME

REC SOLAR PTE. LTD., Sin...

1. A method for fabricating a rear contacted heterojunction intrinsic thin layer solar cell wherein the rear side is formed by at least:providing a silicon substrate with a front surface and a rear surface;
depositing a continuous thin layer of intrinsic amorphous silicon over the entire rear surface of the silicon substrate, the intrinsic amorphous silicon layer having a front surface adjacent to the rear surface of the silicon substrate and the intrinsic amorphous silicon layer having a back surface opposite to the front surface of the intrinsic amorphous silicon layer;
depositing a separation layer comprising an electrically insulating material wherein the separation layer is deposited through a mask such that it covers separation portions of the back surface of the intrinsic amorphous silicon layer;
depositing an emitter layer comprising a doped semiconducting material of a first doping polarity wherein the emitter layer is deposited through a mask such that it covers an emitter portion of the back surface of the intrinsic amorphous silicon layer adjacent to the separation portions;
depositing a base layer comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and with higher doping concentration than the silicon substrate wherein the base layer is deposited though a mask such that it covers a base portion of the back surface of the intrinsic amorphous silicon layer adjacent to the separation portions.

US Pat. No. 10,461,207

PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING

First Solar, Inc., Tempe...

1. A photovoltaic device comprising:a substrate;
a transparent conductive oxide (TCO) layer formed on the substrate;
a back contact;
a CdSeTe absorber layer formed between the TCO layer and the back contact, wherein:
the CdSeTe absorber layer contacts the back contact,
the CdSeTe absorber layer is composed of cadmium, selenium, and tellurium in varying amounts,
a ratio of Te atoms to a sum of Se atoms and the Te atoms throughout the CdSeTe absorber layer compound is between about 99 to 100 and about 60 to 100; and
a buffer layer formed between the TCO layer and the CdSeTe absorber layer,
and wherein the buffer layer comprises magnesium,
and wherein a peak concentration of Se is located at an interface between the buffer layer and the CdSeTe absorber layer.

US Pat. No. 10,461,206

SOLAR PHOTOVOLTAIC-THERMAL SYSTEM

Changzhou Almaden Co., Lt...

1. A solar photovoltaic-thermal system comprising:a solar cell assembly comprising a transparent glass front cover, a transparent encapsulating material, a transparent glass back sheet and a photovoltaic component situated between the transparent glass front cover and the transparent glass back sheet and encapsulated by the transparent encapsulating material;
a plurality of light guides, located below the transparent glass back sheet of the solar cell assembly and each having a plane with a slant angle with respect to the transparent glass back sheet, an arc surface or a parabolic surface; and
a light reflecting plate disposed below the solar cell assembly and the light guides, wherein the light reflecting plate, two adjacent light guides and the transparent glass back sheet form a fully enclosed space and confine a light collection cavity;
a heat exchanger disposed in the light collection cavity; and
an outer frame;wherein the transparent glass back sheet is supported only by the outer frame and the light guides, andwherein the heat exchanger is not vertically shaded by the photovoltaic component, and the heat exchanger is heated by radiation heat and conduction heat from the light collection cavity.

US Pat. No. 10,461,205

SOLAR PANEL HOUSING

1. A housing for a solar panel comprising:a glazed element; and
a tray; said tray including:
a plate;
a pair of side walls extending generally vertical from said plate and from opposing ends of said plate, said pair of side walls include at least one first aperture, said at least one first aperture configured to allow passage of a tube or conduit;
a top end cap extending generally vertical from said plate;
a bottom end cap extending generally vertical from said plate at an opposite end from said top end cap;
a top surface of said pair of side walls, said top end cap and said bottom end cap;
a lip, said lip positioned proximate a junction of said top surface of said pair of side walls, said top end cap and said bottom end cap and an interior wall of said pair of side walls, said top end cap and said bottom end cap, said lip including a seating surface that is positioned below said top surface of said pair of side walls, said top end cap and said bottom end cap, said lip extending the interior perimeter of each of said pair of side walls, said top end cap and said bottom end cap, and said lip configured to seat said glazed element such that a top surface of said glazed element is flush to said top surface of said pair of side walls, said top end cap and said bottom end cap;
wherein said plate, said pair of side walls, said top end cap, said bottom end cap, said top surface of said pair of side walls, said top end cap and said bottom end cap and said lip are formed of a single material and as a single integral component; and
wherein said plate, said pair of side walls, said top end cap and said bottom end cap collectively form a cavity; and
wherein said top end cap includes a top header, said top header extending the length of said top end cap, said top header extending outward from said top end cap and in a direction away from said cavity, said top header including:
at least one pipe extending outwardly from said top header at both ends of said top header and extending the length of said top header and throughout an interior space of said top header;
at least one void extending the length of said top header and throughout the interior space of said top header, said void positioned proximate the exterior of said pipe and distinct from said pipe; and
at least one hole extending from said void through said top end cap to said cavity.

US Pat. No. 10,461,204

DEFORMABLE PAPER ORIGAMI OPTOELECTRONIC DEVICES

KING ABDULLAH UNIVERSITY ...

1. A deformable optoelectronic device comprising:a paper substrate comprising a plurality of fold segments arranged in a deformable pattern;
first and second electrode layers attached to a surface of the substrate; and
plural semiconductor nanowire layers configured to detect light and act as photodetectors,
wherein the plural semiconductor nanowire layers are electrically connected, along parallel branches, between the first and second electrode layers, each branch including a subset of the plural semiconductor nanowire layers electrically connected in series, and
wherein the substrate is folded along plural fold lines to form a 3-dimensional structure.

US Pat. No. 10,461,203

SEMICONDUCTOR DEVICES, A FLUID SENSOR AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Infineon Technologie AG, ...

1. A semiconductor device, comprising:a quantum well layer stack comprising a plurality of first quantum well layers and a plurality of second quantum well layers, wherein first quantum well layers of the plurality of first quantum well layers and second quantum well layers of the plurality of second quantum well layers are arranged alternatingly on a first semiconductor layer structure,
wherein the first quantum well layers of the plurality of first quantum well layers comprise silicon-germanium and the second quantum well layers of the plurality of second quantum well layers comprise silicon,
wherein the first quantum well layers of the plurality of first quantum well layers and the second quantum well layers of the plurality of second quantum well layers have a thickness of below 100 nm, and
wherein the quantum well layer stack is configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.

US Pat. No. 10,461,202

IN-PLANE RESONANT-CAVITY INFRARED PHOTODETECTORS WITH FULLY-DEPLETED ABSORBERS

The Government of the Uni...

1. A hybrid waveguide comprising a III-V resonant-cavity infrared detector (RCID) photodiode ridge integrated with a waveguide,the waveguide comprising:
a first cladding layer disposed on a substrate;
a core layer disposed on the first cladding layer; and
a second cladding layer disposed on the core layer;
the core layer and second cladding layer being patterned to form air or dielectric regions on each lateral side of the hybrid waveguide, the air or dielectric regions being configured to laterally confine light propagating in the waveguide such that propagation is in a single lateral mode;
and the RCID ridge comprising:
a p+ bottom contact layer disposed on an upper surface of the second cladding layer;
a p-type region disposed on a first area of an upper surface of the bottom contact layer;
an absorber region having a thickness of less than 100 nm disposed on an upper surface of the p-type region;
an n-type region disposed on an upper surface of the absorber region; and
an n+ top contact layer disposed on an upper surface of the n-type region;
the hybrid waveguide further comprising a first distributed Bragg reflector (DBR) grating at a first end and a second DBR grating at a second end, the first and second DBR gratings forming a resonant cavity within the RCID photodiode extending along a length of the hybrid waveguide, the resonant cavity having a resonant wavelength ?R; and
wherein the RCID photodiode is configured to detect infrared light propagating within the hybrid waveguide, the resonant cavity formed by the first and second DBR gratings being configured to increase an effective absorption path of light having at the resonant wavelength ?R travelling through the hybrid waveguide.

US Pat. No. 10,461,201

HIGHLY-FLUORESCENT AND PHOTO-STABLE CHROMOPHORES FOR WAVELENGTH CONVERSION

Nitto Denko Corporation, ...

1. A chromophore represented by formula (I):
wherein:
each L is independently C1-8 alkyl or C6-10 aryl;
D1 is selected from the group consisting of:
(1) hydrogen;
(2) C6-10 aryl, substituted by C1-6 alkoxy;
(3) C6-10 aryl-NR?R?; and
(4) C6-10 aryl-C6-10 aryl-NR?R?;
D2 is selected from the group consisting of:
(1) hydrogen;
(2) C6-10 aryl, substituted by C1-6 alkoxy;
(3) C6-10 aryl-NR?R?; and
(4) C6-10 aryl-C6-10 aryl-NR?R?;
R? is C1-8 alkyl or C6-10 aryl, wherein the C6-10 aryl is optionally substituted by C1-8 alkyl, C1-6 alkoxy or —C(?O)R; or
R?, together with the C6-10 aryl to which the nitrogen atom is attached to, forms a fused C1-8 heterocyclic ring comprising nitrogen;
R? is C1-8 alkyl or C6-10 aryl, wherein the C6-10 aryl is optionally substituted by C1-8 alkyl, C1-6 alkoxy or —C(?O)R; or
R?, together with the C6-10 aryl to which the nitrogen atom is attached to, forms a fused C1-8 heterocyclic ring comprising nitrogen; or
R? and R?, together with the C6-10 aryl to which the nitrogen atom is attached to, forms a fused C1-8 heterocyclic ring comprising nitrogen;
Het is selected from the group consisting of:

X is —N(A0)-;
A0 is selected from the group consisting of:
(1) hydrogen;
(2) C1-8 alkyl, optionally substituted by halo or C1-6 alkoxy;
(3) C2-8 alkenyl, optionally substituted by halo, C1-8 alkyl or C1-6 alkoxy;
(4) C1-6 alkoxy, optionally substituted by halo; and
(5) C6-10 aryl, optionally substituted by halo, C1-8 alkyl or C1-6 alkoxy;
Ra is selected from the group consisting of:
(1) hydrogen;
(2) C1-8 alkyl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-6 alkoxy;
(d) C6-10 aryloxy, optionally substituted by CN or —C(?O)R;
(e) C3-10 cycloalkyl; or
(f) C6-10 aryl, optionally substituted by halo or CN;
(3) C6-10 aryl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-8 alkyl;
(d) C1-6 alkoxy; or
(e) C(?O)R; and
(4) C6-10 heteroaryl, optionally substituted by:
(a) halo;
(b) CN; or
(c) C1-8 alkyl;
wherein the C6-10 heteroaryl contains one or more nitrogen heteroatoms;
Rb is selected from the group consisting of:
(1) hydrogen;
(2) C1-8 alkyl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-6 alkoxy;
(d) C6-10 aryloxy, optionally substituted by CN or —C(?O)R;
(e) C3-10 cycloalkyl; or
(f) C6-10 aryl, optionally substituted by halo or CN;
(3) C6-10 aryl, optionally substituted by:
(a) halo;
(b) CN;
(c) C1-8 alkyl;
(d) C1-6 alkoxy; or
(e) C(?O)R; and
(4) C6-10 heteroaryl, optionally substituted by:
(a) halo;
(b) CN; or
(c) C1-8 alkyl;
wherein the C6-10 heteroaryl contains one or more nitrogen heteroatoms; or
Ra and Rb, together with the carbon atoms to which they are attached, form a monocyclic ring or a polycyclic ring system selected from the group consisting of:
C3-10 cycloalkyl, C6-10 aryl,

wherein the monocyclic ring or polycyclic ring system is optionally substituted by:
(a) halo;
(b) C1-8 alkyl;
(c) C1-6 alkoxy; or
(d) C6-10 aryl, optionally substituted by C1-6 alkoxy;
each R is independently C1-8 alkyl, C1-6 alkoxy or C6-10 aryl, wherein the C6-10 aryl is optionally substituted by C1-8 alkyl; and
i is 0;
with the proviso that D1 and D2 are not both hydrogen.

US Pat. No. 10,461,200

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

United Microelectronics C...

1. A semiconductor structure, comprising:a substrate;
a light sensing device, disposed in the substrate; and
a light-guiding structure, located above the light sensing device, having a top surface and a bottom surface opposite to each other, wherein the bottom surface is closer to the substrate than the top surface and a position of a minimum width of the light-guiding structure is located between the top surface and the bottom surface.

US Pat. No. 10,461,199

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A thin film transistor manufacturing method, comprising:forming a gate layer on a substrate;
forming a gate insulating layer on the gate layer and the substrate;
forming an active layer on the gate insulating layer; and
simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method;
wherein the simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method comprises:
coating a photoresist layer on the gate insulating layer and the active layer;
patterning the photoresist layer to remove a photoresist layer at a position where the source and the drain are to be formed to expose the active layer;
doping the exposed portion of the active layer to form a first conductor portion and a second conductor portion; and disposing the source on the first conductor portion, and disposing the drain on the second conductor portion;
using a chemical plating method to form a metal film layer on a remaining photoresist layer and an exposed portion of the active layer; and
stripping the remaining photoresist layer with a stripping liquid to peel off the metal film layer on the remaining photoresist layer to form the source and the drain.

US Pat. No. 10,461,198

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE

INDUSTRY-UNIVERSITY COOPE...

1. A method for manufacturing a thin film transistor substrate comprising:forming a first protection film on a base substrate, the first protection film comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer which are sequentially stacked;
after forming the first protection film, forming an oxide semiconductor layer on the first protection film;
forming source and drain electrodes provided at a predetermined interval from each other and connected with the oxide semiconductor layer;
forming a gate electrode insulated from the oxide semiconductor layer and partially overlapped with at least one portion of the oxide semiconductor layer; and
performing a thermal treatment at less than 350° C.,
wherein the oxide semiconductor layer has a hydrogen content of 2.4 at % (atomic % or atom %)˜2.6 at %.

US Pat. No. 10,461,197

SPUTTERING TARGET, OXIDE SEMICONDUCTOR, OXYNITRIDE SEMICONDUCTOR, AND TRANSISTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxynitride semiconductor layer comprising:
a plurality of first regions; and
a second region,
wherein each region of the plurality of first regions comprises an element M,
wherein the element M is one or more of Al, Si, Y, B, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu,
wherein each region of the plurality of first regions comprises an insulating material as a first main component,
wherein the second region comprises a conductive material as a second main component,
wherein the second region comprises indium,
wherein each region of the plurality of first regions is surrounded by the second region in plan view, and
wherein the plurality of first regions and the second region are arranged in a mosaic pattern.

US Pat. No. 10,461,196

CONTROL OF LENGTH IN GATE REGION DURING PROCESSING OF VFET STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a vertical FinFET, the method comprising:forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof;
laterally recessing the semiconductor fin causing the fin mask to overhang above the fin;
forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner;
forming a gate mask laterally adjacent to the second portion of the conformal gate liner;
removing the first portion of the conformal gate liner, wherein the second portion of the conformal gate liner remains intact after the removing of the first portion;
removing the gate mask to expose the remaining second portion of the conformal gate liner;
forming a nitride liner on the remaining second portion of the conformal gate liner, exposed portion of the semiconductor fin above the second portion of the conformal gate liner, and the fin mask, after removing the gate mask to expose the remaining second portion of the conformal gate liner;
forming an intermediate mask on a portion of the nitride liner that is above the fin mask to vertically cover a vertical section of the first portion of the conformal gate liner adjacent to the recessed semiconductor fin and the nitride liner on top thereof;
applying a directional etching to remove portions of the conformal gate liner and the nitride liner on top thereof, that are above the substrate and not vertically covered by the intermediate mask;
removing the intermediate mask; and
forming a gate contact to the remaining second portion of the conformal gate liner, wherein a length of the gate is determined by the remaining second portion of the conformal gate liner.

US Pat. No. 10,461,195

SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate;
a gate electrode running across the channel semiconductor patterns;
source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns;
an interlayer dielectric layer covering the source/drain regions; and
air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate,
wherein, when viewed in cross section, top surfaces of the air gaps are defined by the bottom surfaces of the source/drain regions, and side surfaces of the air gaps are defined by the interlayer dielectric layer,
wherein the substrate comprises on its upper portion a fin-shaped active pattern including a first region under the gate electrode and second regions on the opposite sides of the gate electrode,
wherein the channel semiconductor patterns are disposed on the first region, and
wherein the bottom surfaces of the source/drain regions are lower than a bottom surface of a lowermost one of the channel semiconductor patterns and higher than top surfaces of the second regions.

US Pat. No. 10,461,194

THRESHOLD VOLTAGE CONTROL USING CHANNEL DIGITAL ETCH

International Business Ma...

1. A method for fine-tuning a threshold voltage of a nanosheet structure, the method comprising:forming a nanosheet stack including a plurality of sacrificial layers and a plurality of nanowires;
forming a sacrificial gate structure over the nanosheet stack;
partially etching one or more of the plurality of sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers;
removing the sacrificial gate structure;
removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires;
forming an oxidation channel directly contacting the exposed surface of each of the plurality of nanowires on only either a top side or a bottom side of each of the plurality of nanowires; and
removing the oxidation channels to form a recess on each of the plurality of nanowires.

US Pat. No. 10,461,193

APPARATUS AND METHODS TO CREATE A BUFFER WHICH EXTENDS INTO A GATED REGION OF A TRANSISTOR

Intel Corporation, Santa...

1. A microelectronic structure, comprising:a substrate;
a low band-gap active channel;
a high band-gap sub-structure disposed between the substrate and the low band-gap active channel, wherein the high band-gap sub-structure abuts the low band-gap active channel;
at least one isolation structure abutting the high band-gap sub-structure, wherein a portion of the high band-gap sub-structure extends from the at least one isolation structure and wherein another portion of the high band-gap sub-structure extends into the substrate;
a gated region comprising the low band-gap active channel and the portion of the high band-gap sub-structure extending from the at least one isolation structure; and
a gate on the gated region, wherein the gate comprises a gate dielectric layer and a gate electrode, and wherein the gate dielectric layer contacts both the low band-gap active channel and the portion of the high band-gap sub-structure extending from the at least one isolation structure.

US Pat. No. 10,461,192

METAL OXIDE PROTECTION STRUCTURE OF A SEMICONDUCTOR DEVICE

Samsung Display Co., Ltd....

1. A semiconductor device comprising:a gate electrode disposed on a substrate;
a gate insulation layer disposed on the substrate to cover the gate electrode;
an active layer disposed on the gate insulation layer, the active layer comprising an oxide semiconductor;
an insulating interlayer disposed on the gate insulation layer and configured to cover the active layer;
a protection structure disposed on the insulating interlayer; and
a source electrode and a drain electrode disposed on the protection structure, the source electrode and the drain electrode contacting a source region and a drain region of the active layer, respectively,
wherein:
the protection structure comprises a first metal oxide layer disposed on the insulating interlayer, and a second metal oxide layer disposed on the first metal oxide layer;
the first metal oxide layer has a first oxygen content greater than a second oxygen content of the second metal oxide layer;
the second oxygen content abruptly varies from the first oxygen content at an interface between the first metal oxide layer and the second metal oxide layer;
the first metal oxide layer has a first composition of MOx1 (where M represents aluminum, titanium, tantalum or zirconium, O denotes oxygen, and x means a positive real number) having a first oxygen content, and the second metal oxide layer has a second composition of MOx2 having a second oxygen content; and
a thickness ratio between the first metal oxide layer and the second metal oxide layer is in a range of about 1.0:0.03 to 1.0:0.6.

US Pat. No. 10,461,191

SEMICONDUCTOR DEVICE WITH UNDERCUTTED-GATE AND METHOD OF FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A method of fabricating a semiconductor device, comprising following operations:(i) providing a semiconductor substrate having an active area, a shallow trench isolation (STI) structure surrounding the active area, and a doped region located in the active area;
(ii) etching the semiconductor substrate to form a first protrusion structure, a source semiconductor feature, a drain semiconductor feature, and an etched STI structure, wherein the etched STI structure comprises a first portion and a second portion, the second portion of the etched STI structure has a top surface that is higher than a top surface of the first protrusion structure, and the top surface of the first protrusion structure is higher than a top surface of the first portion of the etched STI structure;
(iii) etching the first protrusion structure to form a second protrusion structure, wherein the second protrusion structure has an undercut at a periphery of the active area;
(iv) conformally forming a dielectric layer over the second protrusion structure; and
(v) forming a gate structure crossing over the second protrusion structure, wherein the gate structure extends in a first direction, and the undercut extends in a second direction that is substantially perpendicular to the first direction.

US Pat. No. 10,461,190

METHOD FOR REDUCING CONTACT RESISTANCE IN SEMICONDUCTOR STRUCTURES

Taiwan Semiconductor Manu...

1. A method, comprising:forming a fin over a substrate;
forming, on the fin, a gate structure having a sidewall;
forming a sidewall spacer adjacent to the sidewall;
doping a source/drain (S/D) region adjacent to the sidewall spacer;
depositing a layer of doped amorphous material over the gate structure, the sidewall spacer, and the S/D region; and
crystallizing a portion of the layer of doped amorphous material to form a region of crystallized material that comprises a doping concentration higher than a doping concentration of the S/D region.

US Pat. No. 10,461,189

FIN FIELD EFFECT TRANSISTORS HAVING LINERS BETWEEN DEVICE ISOLATION LAYERS AND ACTIVE AREAS OF THE DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit device comprising:a substrate;
a first fin active area protruding from the substrate;
a second fin active area protruding from the substrate;
a first insulating liner disposed on a first portion of the substrate and on a sidewall of the first fin active area;
a first stress liner disposed on the first insulating liner;
a first device isolation layer disposed on the first stress liner;
a second insulating liner disposed on a second portion of the substrate and on a sidewall of the second fin active area;
a second stress liner disposed on the second insulating liner; and
a second device isolation layer disposed on the second stress liner,
wherein the first stress liner is a single layer formed between the first device isolation layer and the first insulating liner,
the second stress liner is a single layer formed between the second device isolation layer and the second insulating liner,
a thickness of the first insulating liner is greater than a thickness of the second insulating liner,
an upper surface of the first device isolation layer has an inclined edge portion, the inclined edge portion being closer to the substrate as a distance from the first tin active area increases, and
wherein an upper surface of the inclined edge portion is lower than an upper surface of an end portion of the first stress liner.

US Pat. No. 10,461,188

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, comprising:providing a substrate structure, wherein the substrate structure comprises:
a substrate having a first device region and a second device region,
a first dummy gate structure at the first device region,
a second dummy gate structure at the second device region, and
a Lightly Doped Drain (LDD) region below the first dummy gate structure,
wherein the first dummy gate structure comprises:
a first dummy gate dielectric layer at the first device region,
a first dummy gate on the first dummy gate dielectric layer, and
a first spacer layer at a side wall of the first dummy gate, and
wherein the second dummy gate structure comprises:
a second dummy gate dielectric layer at the second device region,
a second dummy gate on the second dummy gate dielectric layer, and
a second spacer layer at a side wall of the second dummy gate;
removing the first dummy gate;
etching back the first spacer layer to reduce a thickness of the first spacer layer such that the thickness of the first spacer layer is smaller than a thickness of the second spacer layer;
removing an exposed portion of the first dummy gate dielectric layer to form a first trench;
removing the second dummy gate after removing the first dummy gate;
removing an exposed portion of the second dummy gate dielectric layer to form a second trench;
depositing a gate dielectric layer to cover a bottom portion and a side wall of the first trench and a bottom portion and a side wall of the second trench; and
before depositing the gate dielectric layer, forming a gate oxide layer only at the bottom portion of the first trench.

US Pat. No. 10,461,187

INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit device comprising:a substrate comprising a main surface;
a transistor (TR) comprising a first section, a vertical channel region, and a second section on the main surface; and
a gate electrode on the vertical channel region,
wherein the first section, the vertical channel region, and the second section extend from the main surface in a first direction perpendicular to the main surface, wherein the vertical channel region and the first and second sections have the same composition as each other and have different crystal phases from each other, and wherein the vertical channel region has a first width in a second direction parallel to the main surface and the first section has a second width in the second direction, the first width being narrower than the second width.

US Pat. No. 10,461,186

METHODS OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED CONTACTS AND THE RESULTING STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a transistor, an isolation region, and an additional isolation region, wherein the transistor has a first end and a second end opposite the first end and comprises: a semiconductor fin that extends vertically between a lower source/drain region in a substrate and an upper source/drain region and horizontally from adjacent the first end of the transistor to adjacent the second end of the transistor; a spacer layer on the lower source/drain region around the semiconductor fin; a gate on the spacer layer around the semiconductor fin; and a source/drain sidewall spacer on the gate around the upper source/drain region and a cap layer on the upper source/drain region, wherein the isolation region extends from within the substrate through the spacer layer and is positioned laterally adjacent to the second end of the transistor, and wherein the additional isolation region is on the spacer layer and positioned laterally adjacent to the first end of the transistor;
forming a dielectric layer on the transistor, the isolation region and the additional isolation region; and
forming a gate contact that extends vertically through the dielectric layer and into the isolation region, the gate contact being positioned laterally immediately adjacent to the gate at the second end of the transistor and having a bottom above a level of the spacer layer.

US Pat. No. 10,461,185

ASSEMBLIES HAVING CONDUCTIVE STRUCTURES ALONG PILLARS OF SEMICONDUCTOR MATERIAL

Micron Technology, Inc., ...

1. An assembly, comprising:pillars of semiconductor material over a base, the pillars of semiconductor material being arranged in rows that extend along a first direction;
the rows further comprising an intervening spacing regions between the pillars of semiconductor material such that the intervening spacing regions alternate with the silicon pillars within each of the rows,
the pillars of semiconductor material having top surfaces at a first maximum height above the base, and the intervening spacing regions comprising spacing structures having top surfaces at a second maximum height above the base, the second maximum height being below the first maximum height;
the rows being spaced from each other by gap regions;
conductive structures within the gap regions between the rows, the conductive structures each extending along the first direction along a plurality of the pillars of semiconductive material, two of the conductive structures being within each of the gap regions and being spaced apart from one another by a separating region, the separating region having a bottom surface that undulates across semiconductor segments and insulative segments, a height of each of the semiconductor segments being higher than that of each of the insulative segments relative to the base;
channel regions within the pillars of semiconductor material;
gates within the conductive structures; and
transistors, with each of the transistors comprising one of the channel regions and at least one of the gates.

US Pat. No. 10,461,184

TRANSISTOR HAVING REDUCED GATE-INDUCED DRAIN-LEAKAGE CURRENT

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a semiconductor fin that extends vertically from a first source or drain (S/D) region of the semiconductor device, the semiconductor fin comprising a first type of semiconductor material having a first band gap;
converting an upper portion of the semiconductor fin into a second semiconductor material having a second band gap that is greater than the first band gap; and
forming a second S/D region on the second semiconductor material so that the second semiconductor material is interposed between a non-converted portion of the semiconductor fin and the second S/D region.

US Pat. No. 10,461,183

ULTRA HIGH VOLTAGE SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE CAPABILITIES

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first layer over a semiconductor substrate;
a drain region in the first layer, the drain region comprising
a drain rectangular portion;
a first drain end portion contiguous with the drain rectangular portion and extending from the drain rectangular portion away from a center of the drain region; and
a second drain end portion contiguous with the drain rectangular portion and extending from the drain rectangular portion away from the center of the drain region; and
a source region spaced a distance from and surrounding the drain region in the first layer,
wherein the first drain end portion and the second drain end portion have a same doping type and each of the first drain end portion and the second drain end portion have different doping concentrations from the drain rectangular portion.

US Pat. No. 10,461,182

DRAIN CENTERED LDMOS TRANSISTOR WITH INTEGRATED DUMMY PATTERNS

TEXAS INSTRUMENTS INCORPO...

1. A drain extended transistor, comprisinga plurality of substantially parallel transistor finger structures formed in an active region of a semiconductor substrate, the plurality of transistor finger structures including: a plurality of body region fingers; a plurality of source fingers; a plurality of oxide fingers, a plurality of drain fingers; a plurality of drift region fingers, and a plurality of gate fingers;
individual ones of the plurality of body region fingers including a body region that extends along a first direction into a semiconductor substrate, the body region including: majority carrier dopants of a first type; and a channel portion;
individual ones of the plurality of source fingers including a source region that extends along the first direction into the semiconductor substrate from a first side of the semiconductor substrate, the source region adjacent a first side of the channel portion of the body region, the source region including majority carrier dopants of a second type;
individual ones of the plurality of drain fingers including a drain region that extends along the first direction into the semiconductor substrate from the first side, the drain region including: majority carrier dopants of the second type, and a first end;
individual ones of the plurality of oxide fingers including an oxide structure that extends along the first side of the semiconductor substrate, the oxide structure including: a first end spaced along a second direction from the channel portion of the body region; and a second end adjacent the first end of the drain region, the second direction being orthogonal to the first direction;
individual ones of the plurality of drift region fingers including a drift region, the drift region including majority carrier dopants of the second type, the drift region extending along the first direction into the semiconductor substrate from the first side, the drift region extending along the second direction from the channel portion of the body region to the drain region; the drift region including a drift region portion separated from the first side along the first direction by at least a portion of the oxide structure; and
individual ones of the plurality of gate fingers including a gate structure, the gate structure including: a gate dielectric layer formed over the first side of the substrate; and a gate electrode on the gate dielectric layer at least partially above the channel portion of the body region;
wherein one of the drain fingers is positioned at a center of the drain extended transistor along the second direction.

US Pat. No. 10,461,181

HIGH VOLTAGE SEMICONDUCTOR DEVICE

MagnaChip Semiconductor, ...

1. A high voltage semiconductor device, comprising:a semiconductor substrate;
a first region formed in the semiconductor substrate, comprising:
an N-type first semiconductor region;
an N-type drain region formed in the N-type first semiconductor region;
a P-type first body region;
an N-type source region formed in the P-type first body region; and
a gate electrode formed between the N-type source region and the N-type drain region;
a second region formed in the semiconductor substrate, comprising:
an N-type second semiconductor region;
an N-type second well region formed in the N-type second semiconductor region; and
a P-type second body region formed in the N-type second semiconductor region; and
an interconnection region disposed between the first region and the second region, comprising:
a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region;
a metal interconnection formed on the first insulation layer; and
a P-type junction isolation region formed and disposed below the first insulation layer,
wherein the N-type second well region is in contact with the first insulation layer.

US Pat. No. 10,461,180

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first conductivity type drift region formed on a semiconductor substrate;
a gate trench portion provided reaching from an upper surface of the semiconductor substrate to an inner part of the semiconductor substrate and provided extending in a predetermined extending direction from the upper surface;
a first mesa portion being in direct contact with one of two side walls of the gate trench portion;
a second mesa portion being in direct contact with an opposite side of the one of two side walls of the gate trench portion;
a first conductivity type accumulation region having doping concentration higher than that in the drift region, which is provided being in direct contact with the gate trench portion above the drift region;
a second conductivity type base region provided being in direct contact with the gate trench portion above the accumulation region;
a first conductivity type emitter region having doping concentration higher than that in the drift region, which is provided on the upper surface of the semiconductor substrate such that it is in direct contact with the one of two side walls of the gate trench portion in at least the first mesa portion; and
an electrically floating second conductivity type floating region provided below the base region in the second mesa portion and at a position shallower than a bottom of the gate trench portion.

US Pat. No. 10,461,179

DEVICES HAVING A SEMICONDUCTOR MATERIAL THAT IS SEMIMETAL IN BULK AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming an isolation region in a substrate, wherein the isolation region is between a first and second region of the substrate, and wherein at least a portion of the isolation region is configured to extend from a top surface of the substrate;
forming a first highly doped source/drain contact region in the first region of the substrate and a second highly doped source/drain contact region in the second region of the substrate;
forming a first gate electrode over the first highly doped source/drain contact region;
forming a second gate electrode over the second highly doped source/drain contact region;
forming a first opening through the first gate electrode and to the first highly doped source/drain contact region;
forming a second opening through the second gate electrode and to the second highly doped source/drain contact region;
depositing a first bismuth-containing semiconductor material in the first opening to form a first bismuth-containing channel structure, the first bismuth-containing channel structure being connected to the first highly doped source/drain contact region;
depositing a second bismuth-containing semiconductor material in the second opening to form a second bismuth-containing channel structure, the second bismuth-containing channel structure being connected to the second highly doped source/drain contact region;
forming a third source/drain contact region over and connected to the first bismuth-containing channel structure;
forming a fourth source/drain contact region over and connected to the second bismuth-containing channel structure;
forming a dielectric layer over the third source/drain contact region and the fourth source/drain contact region; and
crystallizing the first and second bismuth-containing semiconductor materials, the crystallizing comprising performing an anneal.

US Pat. No. 10,461,178

METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an array substrate, comprising steps of:forming patterns of a gate metal layer and a gate insulating layer successively on a base plate;
forming a pattern of a semiconductor layer, wherein the semiconductor layer comprises a first oxide layer and a second oxide layer stacked on the first oxide layer, the first oxide layer is an insulative oxide layer and the second oxide layer is a semiconductive oxide layer, and the first oxide layer is located between the gate insulating layer and the second oxide layer;
forming a pattern of a source and drain metal layer; and
the first oxide layer including a first active region and a first pixel electrode region, the second oxide layer including a second active region and a second pixel electrode region, subjecting the second pixel electrode region of the second oxide layer to plasma treatment, to convert the second pixel electrode region of the second oxide layer into a conductor to form a pixel electrode.

US Pat. No. 10,461,177

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a semiconductor fin above and continuous with a semiconductor substrate, the semiconductor fin comprising a channel region having an uppermost surface;
an isolation structure above the semiconductor substrate and adjacent to lower portions of the semiconductor fin, wherein an upper portion of the semiconductor fin protrudes above an uppermost surface of the isolation structure;
epitaxial source or drain regions adjacent to the channel region in the upper portion of the semiconductor fin, wherein the epitaxial source or drain regions have substantially vertical sidewalls, and wherein the epitaxial source and drain regions do not extend laterally over the isolation structure, wherein the epitaxial source and drain regions have an uppermost surface above the uppermost surface of the channel of the semiconductor fin, and wherein the epitaxial source or drain regions have a bottom surface below the uppermost surface of the isolation structure; and
a gate electrode over the channel region of the semiconductor fin.

US Pat. No. 10,461,176

FINFET DEVICE INCLUDING A STEM REGION OF A FIN ELEMENT

TAIWAN SEMICONDUCTOR MANU...

1. A fin-type field effect transistor (finFET) device, comprising:a substrate;
a fin disposed on the substrate, wherein the fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region, wherein the stem region has a first width and the active region has a second width, the first width being less than the second width; and wherein the stem region has a first composition and the active region has a second composition, the second composition being different than the first composition, and wherein the first composition is an oxide;
a gate structure disposed on the active region, the gate structure including a gate electrode physically contacting the first composition of oxide of the stem region; and
a source region and a drain region adjacent the gate structure, wherein the first composition of oxide of the stem region extends under a bottommost edge of at least one of the source region or the drain region.

US Pat. No. 10,461,175

TFT-CONTAINING BACKPLATE AND METHOD FOR FABRICATING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method or fabricating a TFT-containing backplate, comprising: forming a top-gate TFT on a substrate, wherein the top-gate TFT comprises a gate insulating layer which comprises a negative silicone light shielding material,wherein forming the top-gate TFT on the substrate comprises:
depositing a first metal layer on the substrate, and patterning the first metal layer to form a source and a drain;
depositing a metal oxide layer on the substrate on which the source and the drain have been formed;
depositing a first insulating layer on the metal oxide layer, and patterning the first insulating layer by self-alignment exposure to form the gate insulating layer which has an inverted trapezoid cross-sectional shape; and
depositing a second metal layer to form a gate on the gate insulating layer.

US Pat. No. 10,461,174

VERTICAL FIELD EFFECT TRANSISTORS WITH SELF ALIGNED GATE AND SOURCE/DRAIN CONTACTS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a bottom source or drain (S/D) layer on a substrate;
forming a bottom spacer layer on the bottom S/D layer;
forming a vertical transistor channel on the bottom S/D layer, the vertical transistor channel passing through the bottom spacer layer;
forming a high-k metal gate layer on sides of the vertical transistor channel and above the bottom S/D layer;
forming a gate spacer on sides of the vertical transistor channel and on top of the high-k metal gate layer;
removing portions of the high-k metal gate layer with a timed etch;
covering the high-k metal gate layer, the vertical transistor channel and bottom S/D layer with an interlayer dielectric (ILD);
forming with a non-self-aligned contact (SAC) etch a bottom S/D recess through the ILD to expose the bottom S/D layer, the etch removing at least portion of the gate spacer and the high-k metal gate layer;
forming a bottom S/D contact spacer on sides of the bottom S/D recess; and
forming a bottom S/D contact in the bottom S/D recess.

US Pat. No. 10,461,173

METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FORMING SOURCE AND DRAIN REGIONS IN A VERTICAL FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a fin above a semiconductor substrate;
forming a structure on a middle portion of each sidewall of the fin, whereby a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; and
forming a first epitaxial region on at least the top of the fin for forming a top source/drain (S/D) region, and a second epitaxial region on the lower portion of each sidewall and on the semiconductor substrate for forming a bottom S/D region, such that the bottom S/D region comprises an elevated subregion on the lower portion of each sidewall of each fin, wherein the elevated subregion is vertically aligned with the top S/D region.

US Pat. No. 10,461,172

VERTICAL TRANSISTORS HAVING IMPROVED GATE LENGTH CONTROL USING UNIFORMLY DEPOSITED SPACERS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a channel fin structure across from a major surface of a substrate, wherein the channel fin structure comprises a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing;
forming an initial gate structure over the plurality of channel fins;
forming spacers along vertical sidewall portions of the initial gate structure, each of the spacers having a predetermined spacer height dimension, wherein a thickness dimension of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing; and
subsequent to forming the spacers along the vertical sidewall portions of the initial gate structure, removing portions of the initial gate structure where the vertical sidewall portions of the initial gate structure are not covered by the spacers to define a plurality of gate structures each having a gate structure height dimension defined by the spacer height dimension;
wherein a gate length dimension of each of the plurality of gate structures comprises the gate height dimension.

US Pat. No. 10,461,171

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACKS

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack;
removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer;
respectively forming a first metal gate stack and a second metal gate stack in the first trench and the second trench;
partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess, wherein the recess penetrates through the first metal gate stack and the second metal gate stack; and
forming an insulating structure to at least partially fill the recess, wherein the insulating structure has a first portion between two parts of the first metal gate stack, a second portion between two parts of the second metal gate stack, and a third portion linking the first portion and the second portion.

US Pat. No. 10,461,170

METHOD OF FORMING MOSFET STRUCTURE

Taiwan Semiconductor Manu...

1. A method comprising:providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer;
providing a gate layer adjacent to the epitaxial layer and the cap layer;
providing a dielectric layer above the cap layer and the gate layer;
forming a trench above the cap layer by patterning a portion of the dielectric layer above the cap layer, wherein sidewalls of the trench comprise the gate layer and the dielectric layer above the gate layer;
filling the trench with a protection layer; and
removing the protection layer.

US Pat. No. 10,461,169

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a metal gate electrode structure and an insulating layer over a semiconductor substrate, wherein the insulating layer surrounds the metal gate electrode structure; and
nitrifying a first top portion of the metal gate electrode structure to transform the first top portion into a metal nitride layer while nitrifying a second top portion of the insulating layer to transform the second top portion of the insulating layer to a dielectric nitride layer.

US Pat. No. 10,461,168

SEMICONDUCTOR DEVICE FOR COMPENSATING INTERNAL DELAY, METHODS THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a Fin Field Effect Transistor (FinFET), the method comprising:providing a substrate;
forming an elevated source and an elevated drain on the substrate;
forming a first dielectric layer on the substrate, the first dielectric layer including a gate oxide layer and a high-k dielectric layer disposed on the gate oxide layer, the high-k dielectric layer being U-shaped;
forming a metal buffer layer on the first dielectric layer, the metal buffer layer being U-shaped;
forming a metal gate on the metal buffer layer, the metal gate contacting the metal buffer layer; and
forming a second dielectric layer on the substrate after generating at least a first opening next to the first dielectric layer such that the second dielectric layer contacts the first dielectric layer, wherein
a dielectric constant of the second dielectric layer is less than that of the first dielectric layer, and
a first portion of the first dielectric layer is disposed between the metal buffer layer and the second dielectric layer, and blocks the metal buffer layer to contact the second dielectric layer.

US Pat. No. 10,461,167

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first transistor on a substrate; and
a second transistor on the substrate,
wherein each of the first and second transistors includes,
a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and
a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns, wherein
the work function pattern of the first transistor includes a first work function metal layer,
the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer,
the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and
the first transistor has a threshold voltage less than that of the second transistor.

US Pat. No. 10,461,166

ELECTRICAL CONTACT

National University of Si...

1. An electrical contact comprising:(a) a top electrode comprising a non-Newtonian liquid metal alloy; and
(b) a bottom electrode comprising a self-assembled monolayer of molecules (SAM) formed on a metal substrate,
wherein the surface of the SAM layer of the bottom electrode contacting the top electrode is a template-stripped non-patterned surface and the electrical contact has no edge effect;
and the surface of the liquid metal alloy contacting the SAM layer is contained in a polymer insulator and the area of the electrical contact between the liquid metal alloy surface and the SAM layer is determined by modulating the diameter of the liquid metal alloy surface contacting the SAM layer, the diameter being between 15 ?m and 55 ?m.

US Pat. No. 10,461,165

SEMICONDUCTOR DEVICE AND METHOD OF FORMATION

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, comprising:forming a first tube material over a first channel material, the first channel material over a dielectric layer;
forming a second channel material over the first tube material such that the second channel material is in contact with the first channel material;
removing at least some of the dielectric layer from under the first channel material to form a first gate opening;
forming a gate in the first gate opening under the first channel material and around the second channel material; and
performing an annealing operation to form a dielectric tube from the first tube material and to form a channel from the first channel material and the second channel material, wherein the channel surrounds the dielectric tube to enclose an outer perimeter of the dielectric tube.

US Pat. No. 10,461,164

COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE

QUALCOMM Incorporated, S...

1. A compound semiconductor field effect transistor (FET), comprising:gallium nitride (GaN) and alloy material layers;
a pair of L-shaped contacts on the GaN and alloy material layers;
a pair of gate spacers between the pair of L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the pair of L-shaped contacts; and
a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts is self-aligned with the base gate, and in which the pair of L-shaped contacts comprises a planar portion on a GaN cap layer of the GaN and alloy material layers and an orthogonal portion on the GaN cap layer and in contact with sidewalls of the pair of gate spacers, the orthogonal portion of the pair of L-shaped contacts extending toward a coplanar surface of the base gate and the pair of gate spacers, distal from the GaN cap layer of the GaN and alloy material layers.

US Pat. No. 10,461,163

THREE-DIMENSIONAL MEMORY DEVICE WITH THICKENED WORD LINES IN TERRACE REGION AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers has a respective first thickness in a memory array region and a respective second thickness that is greater than the respective first thickness in a stepped terrace region;
memory stack structures located in the memory array region and vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
contact via structures located in the terrace region and contacting a respective one of the electrically conductive layers.

US Pat. No. 10,461,162

TRANSISTOR DEVICE

Nanya Technology Corporat...

1. A transistor device comprising:an active region surrounded by an isolation structure;
a gate structure disposed over the active region and the isolation structure, the gate structure comprising:
a body portion extending in a first direction;
a first head portion and a second head portion extending in a second direction perpendicular to the first direction, wherein the first head portion and the second head portion are disposed at two opposite ends of the body portion;
a pair of first wing portions disposed at two opposite sides of the body portion, wherein each of the first wing portions is in contact with the first head portion and the body portion; and
a pair of second wing portions disposed at two opposite sides of the body portion, wherein each of the second wing portions is in contact with the second head portion and the body portion; and
a source/drain disposed in the active region;
wherein the first head portion comprises a first side extending in the first direction, the body portion comprises a second side extending in the first direction, and the second head portion comprises a third side extending in the first direction;
wherein each of the first wing portions comprises a fourth side in contact with the first side of the first head portion and the second side of the body portion, and each of the second wing portions comprises a fifth side in contact with the third side of the second head portion and the second side of the body portion;
wherein the second side of the body portion and the fourth side of the first wing portion form a first included angle, the second side of the body portion and the fifth side of the second wing portion form a second included angle, and the first included angle and the second included angle are obtuse angles;
wherein the first included angle and the second included angle are between 130° and 165°, respectively.

US Pat. No. 10,461,161

GAN DEVICE WITH FLOATING FIELD PLATES

NAVITAS SEMICONDUCTOR, IN...

1. A semiconductor device comprising:a substrate including a transition layer that can form a two-dimensional electron gas;
a source electrode ohmically coupled to the transition layer;
a drain electrode ohmically coupled to the transition layer;
a gate stack formed on the transition layer; and
a field termination structure spaced apart from the transition layer and positioned between the gate stack and the drain electrode, wherein the field termination structure includes a source plate electrically connected to the source electrode and at least one capacitively coupled floating plate.

US Pat. No. 10,461,160

SEMICONDUCTING COMPONENT

INSTITUTT FOR ENERGITEKNI...

1. An electronic semiconductive device comprising at least one transparent, complete n- or p-type semiconductive metal hydride layer containing a semiconductive metal hydride having a chosen dopant; wherein said semiconductive metal hydride has a band gap in the range of 3 eV to 7 eV, and wherein said electronic semiconductive device does not comprise a silicon layer.

US Pat. No. 10,461,159

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, the method comprising the steps of:(a) forming a second nitride semiconductor layer on a first nitride semiconductor layer;
(b) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(c) forming a fourth mesa-type nitride semiconductor layer on the third nitride semiconductor layer;
(d) forming a gate insulating film on the fourth mesa-type nitride semiconductor layer; and
(e) forming a gate electrode on the gate insulating film;
wherein the second nitride semiconductor layer has an electron affinity equal to or larger than electron affinity of the first nitride semiconductor layer,
wherein the third nitride semiconductor layer has an electron affinity smaller than the electron affinity of the first nitride semiconductor layer,
wherein the fourth nitride semiconductor layer has an electron affinity equal to or smaller than the electron affinity of the second nitride semiconductor layer, and
wherein the step (d) includes the steps of:
(d1) forming a first film including a first insulator on the fourth mesa-type nitride semiconductor layer by a sputtering process using a target including the first insulator; and
(d2) forming a second film including a second insulator on the first film by a CVD process.

US Pat. No. 10,461,158

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating film, comprising the steps of:(a) forming a dummy gate electrode of a MISFET over the semiconductor layer;
(b) after the step (a), forming an offset spacer over a side surface of the dummy gate electrode;
(c) after the step (b), forming a side wall over the side surface of the dummy gate electrode via the offset spacer;
(d) after the step (c), forming an interlayer insulating film so as to cover the dummy gate electrode, the offset spacer and the side wall;
(e) after the step (d), exposing an upper surface of the dummy gate electrode and an upper surface of the offset spacer by polishing the interlayer insulating film;
(f) after the step (e), removing the offset spacer in order to form a first opening beside the dummy gate electrode;
(g) after the step (f), forming a first impurity region having a first conductivity type in the semiconductor substrate by an ion implantation method through the first opening;
(h) after the step (g), forming a second impurity region having a second conductivity type opposite to the first conductivity type in the semiconductor layer by an ion implantation method through the first opening; and
(i) after the step (h), replacing the dummy gate electrode with a metal material, thereby to form a metal gate electrode of the MISFET.

US Pat. No. 10,461,157

FLAT GATE COMMUTATED THYRISTOR

ABB Schweiz AG, Baden (C...

1. A turn-off power semiconductor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a plurality of thyristor cells, each of the plurality of thyristor cells comprising in the order from the first main side to the second main side:
(a) a cathode region of a first conductivity type;
(b) a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region;
(c) a drift layer of the first conductivity type forming a second p-n junction with the base layer; and
(d) an anode layer of the second conductivity type separated from the base layer by the drift layer,
wherein each thyristor cell comprises: a gate electrode which is arranged lateral to the cathode region and forms an ohmic contact with the base layer; a cathode electrode arranged on the first main side and forming an ohmic contact with the cathode region; and an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer,
wherein interfaces between the cathode regions and the cathode electrodes and interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar, and
wherein the base layer includes a gate well region extending from its contact with the gate electrode to a depth (dW) which is at least half of a depth (dC) of the cathode region,
wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 ?m from the cathode region, and
the base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein a ratio between the density of first conductivity type impurities and the net doping concentration in the compensated region is at least 0.4.

US Pat. No. 10,461,156

LDMOS TRANSISTOR AND METHOD OF FORMING THE LDMOS TRANSISTOR WITH IMPROVED RDS*CGD

TEXAS INSTRUMENTS INCORPO...

1. A transistor, comprising:a semiconductor substrate having a top surface;
a gate positioned above the top surface;
a first drain drift region positioned near the top surface and extending partially under the gate;
a first back gate region staggering with the first drain drift region under the gate;
a second drain drift region positioned directly under the first drain drift region and staggering with the first back gate region under the gate; and
a second back gate region positioned directly under the first back gate region and the second drain drift region,
a first drain dopant concentration peak (DCP) between the top surface and the first drain drift region, the first drain DCP extending partially under the gate;
a first back gate DCP between the top surface and the first back gate region, the first back gate DCP extending partially under the first drain DCP;
a second drain DCP between the first drain drift region and the second drain drift region, the second drain DCP extending partially under the first backgate DCP;
a second back gate DCP between the first back gate region and the second back gate region, the second back gate DCP extending partially under the second drain DCP; and
a third back gate DCP below the second back gate region, the third back gate DCP extending under and across the second drain DCP.

US Pat. No. 10,461,155

EPITAXIAL REGION FOR EMBEDDED SOURCE/DRAIN REGION HAVING UNIFORM THICKNESS

GLOBALFOUNDRIES INC., Gr...

9. A method of forming a source/drain region comprising:forming a first spacer material layer on a P-type field effect transistor (PFET) region of a substrate and an N-type field effect transistor (NFET) region of the substrate, the NFET region including a gate structure positioned on the substrate;
forming a mask above the first spacer material layer in the PFET region;
forming an opening in the first spacer material layer and the substrate adjacent to the gate structure in the NFET region;
removing the mask;
forming a first epitaxial region in at least a portion of the opening;
forming a second spacer material layer on the first spacer material layer and on a portion of an uppermost surface of the first epitaxial region adjacent to the gate structure;
removing a first portion of the first epitaxial region using the second spacer material layer as a mask, wherein after removing the first portion a remaining portion of the first epitaxial region includes a substantially uniform sidewall thickness; and
forming a second epitaxial region abutting the remaining portion of the first epitaxial region in the opening to form the source/drain region.

US Pat. No. 10,461,154

BOTTOM ISOLATION FOR NANOSHEET TRANSISTORS ON BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method of forming nanosheets comprising:providing at least two stacks of semiconductor material layers on a supporting bulk semiconductor substrate, wherein the at least two stacks of semiconductor material layers includes a sacrificial semiconductor layer of a first composition, and a nanosheet semiconductor layer of a second composition, and removing the sacrificial semiconductor layer to provide nanosheets composed of the nanosheet semiconductor layer;
forming a first undercut region filled with a first dielectric material extending from an opening into the supporting bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers; and
forming a second undercut region into the supporting bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layers at which the first undercut region is positioned, wherein the first and second dielectric materials provide an isolation region.

US Pat. No. 10,461,153

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor memory device comprising;a substrate including active regions;
word lines in the substrate, each of the word lines extending in a first direction parallel to an upper surface of the substrate;
bit line structures connected to the active regions, respectively, each of the bit line structures extending in a second direction crossing the first direction; and
spacer structures on sidewalls of respective ones of the bit line structures,
each of the spacer structures including a first spacer, a second spacer, and a third spacer,
the second spacer being disposed between the first spacer and the third spacer,
the second spacer including a void, and
a height of the second spacer being greater than a height of the void with respect to the upper surface of the substrate,
the second spacer filling a bottom portion of a gap region defined by the first spacer and the third spacer;
contact plugs between each of the bit line structures, the contact plugs being connected to the active regions, respectively;
connection pads on the contact plugs, respectively; and
a separation layer between each of the connection pads, wherein
a lowermost surface of the separation layer is higher than an uppermost surface of the second spacer with respect to the upper surface of the substrate,
an upper surface of the third spacer is lower than an upper surface of the first spacer with respect to the upper surface of the substrate,
an upper surface of the second spacer is lower than the upper surface of the third spacer with respect to the upper surface of the substrate, and
each of the spacer structures further includes a fourth spacer on a sidewall of the first spacer and on the upper surface of the second spacer.

US Pat. No. 10,461,152

RADIO FREQUENCY SWITCHES WITH AIR GAP STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising a substrate with at least one trench structure extending from a surface of the substrate to at least one airgap structure formed in a well region of the substrate and under at least one gate structure having a channel extending continuously into the well region, the at least one airgap devoid of a lining and which extends within the substrate to a junction formed by a source/drain region in the substrate of the at least one gate structure, and the at least one trench is capped with insulator material which seals the at least one airgap structure to prevent moisture from entering into the at least one airgap structure.

US Pat. No. 10,461,151

LOCALIZED STRAIN RELIEF FOR AN INTEGRATED CIRCUIT

Analog Devices Global, H...

1. An integrated circuit comprising:a semiconductor die;
one or more circuit components formed in a surface of the semiconductor die;
a protective layer deposited over the one or more circuit components in the semiconductor die;
a cap disposed over the one or more circuit components to protect the one or more circuit components, the cap mechanically coupled with the protective layer;
one or more trenches at least partially surrounding the one or more circuit components, the one or more trenches spaced apart by at least one gap;
a connecting line passing through the at least one gap to connect the one or more circuit components to another circuit component outside an area at least partially surrounded by the one or more trenches, the connecting line comprising at least one turn such that the connecting line is disposed along at least two different directions; and
an encapsulating material disposed over the cap and the protective layer.