US Pat. No. 10,431,642

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

LG DISPLAY CO., LTD., Se...

1. A method for fabricating a display device, the method comprising:providing a base film on an auxiliary substrate, wherein the base film includes a display area, and a first pad area;
providing a plurality of thin film transistors on the display area of the base film;
providing first pads on the first pad area of the base film;
providing a plurality of organic light emitting diodes connected with the plurality of thin film transistors;
providing an encapsulation layer for covering the plurality of organic light emitting diodes;
attaching a plurality of source flexible films onto the first pads, respectively;
separating the base film from the auxiliary substrate; and
cutting a part of the base film between each of the plurality of source flexible films.

US Pat. No. 10,431,641

THIN FILM TRANSISTOR SUBSTRATE, AN ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE SAME, AND A METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR SUBSTRATE

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor (TFT) substrate comprising:a substrate;
a first electrode disposed on the substrate, wherein the first electrode is one of a source electrode and a drain electrode;
a first insulating layer disposed on the first electrode, wherein the first insulating layer exposes an upper surface of the first electrode;
a second electrode disposed on the first insulating layer, wherein the second electrode is the other one of the source electrode and the drain electrode, wherein the first insulating layer is disposed between the upper surface of the first electrode and a lower surface of the second electrode;
a semiconductor layer disposed on the first electrode, a side of the first insulating layer, and the second electrode;
a second insulating layer disposed on the semiconductor layer;
a gate electrode disposed on the second insulating layer and overlapping the semiconductor layer; and
a pixel electrode that comprises a same material as the gate electrode and is electrically connected to the second electrode.

US Pat. No. 10,431,640

DISPLAY DEVICE

Samsung Display Co., Ltd....

17. A display device comprising:a substrate comprising a display area including a plurality of pixels, and a peripheral area outside the display area and including a bending area;
a first conductive layer over the substrate;
a first insulating layer over the first conductive layer;
a second insulating layer over the first insulating layer, overlapping the bending area in a plan view, and having a first edge positioned around the bending area;
a second conductive layer over the second insulating layer such that the second insulating layer is between the second conductive layer and the first insulating layer in a sectional view; and
a third insulating layer over the second conductive layer,
wherein the first conductive layer includes a first signal wire in the peripheral area, extending to cross the first edge of the second insulating layer in the plan view, and not overlapping the bending area,
wherein the first signal wire includes a first portion that does not overlap by the second insulating layer in the plan view, and
wherein the third insulating layer includes a protector that overlaps at least a portion of the first portion, and has an edge that is parallel with an edge of the first portion in the plan view.

US Pat. No. 10,431,639

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising:a base substrate;
a pixel definition layer pattern disposed on the base substrate, wherein the pixel definition layer pattern comprises a main layer proximal to the base substrate and an oxide layer distal to the base substrate, a material layer for forming the pixel definition layer pattern is partially oxidized to obtain the main layer and the oxide layer;
the pixel definition layer pattern is made of siloxane based organic material, and the siloxane based organic material comprises at least one of hydroxylated polydimethylsiloxane or polystyrene block polydimethylsiloxane.

US Pat. No. 10,431,638

ARRAY SUBSTRATE AND OLED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising: a thin-film transistor (TFT) substrate and a plurality of driver integrated circuits (ICs), wherein the TFT substrate comprises a substrate and a plurality of pixel units disposed on one surface of the substrate; the driver ICs are disposed on the other surface of the substrate and configured to transmit signals to the pixel units, and via holes provided with a conductive material are formed in the substrate and the conductive material is protruded out from the via holes and a protruding portion of the conductive material is connected with output ends of the driver ICs, the pixel units comprise TFTs and pixel electrodes; and the TFTs comprise gate electrodes, active layers, source electrodes and drain electrodes, the gate electrodes are disposed on the substrate; the active layers are disposed over the gate electrodes; channels are provided between the source electrodes and the drain electrodes; the drain electrodes are connected with the pixel electrodes, the pixel units further comprise a gate insulating layer disposed between the gate electrodes and the active layers; through holes corresponding to the via holes are formed in the gate insulating layer and provided with the conductive material, the through holes only pass through the gate insulating layer and the conductive material is in connection with the source electrodes through the via holes and the through holes.

US Pat. No. 10,431,637

TOUCH DISPLAY PANEL AND DISPLAY APPARATUS

SHANGHAI TIANMA AM-OLED C...

1. A touch display panel, comprising:a substrate;
a first retaining wall, located on the substrate, wherein the substrate is divided into a first region and a second region by the first retaining wall, the first region is surrounded by the first retaining wall, the first region and the second region are communicated through a first opening or a first notch of the first retaining wall;
an organic light emitting structure located in the first region;
a thin film encapsulation layer disposed on the organic light-emitting structure and the first retaining wall, wherein the thin film encapsulation layer has a slope part extending from the first region into the second region through the first opening or the first notch, a thickness of the slope part is gradually reduced in an extending direction of the slope part;
a plurality of touch electrodes disposed on the thin film encapsulation layer in the first region;
a first auxiliary retaining wall and a second auxiliary retaining wall in the second region, wherein the first auxiliary retaining wall is connected to the first auxiliary retaining wall at a first end of the first opening or the first notch, and the second auxiliary retaining wall is connected to the first auxiliary retaining wall at a second end of the first opening or the first notch, the first auxiliary retaining wall and the second auxiliary retaining wall are perpendicular to the first retaining wall;
a plurality of pads disposed on the substrate in the second region; and
a plurality of touch lines connecting the plurality of touch electrodes to the plurality of pads, wherein the plurality of touch lines are located on a top surface of the slope part;
wherein the extending direction of the slope part is parallel to the first auxiliary retaining wall and the second auxiliary retaining wall, and the slope part is between the first auxiliary retaining wall and the second auxiliary retaining wall.

US Pat. No. 10,431,636

ELECTRONIC DEVICES HAVING DISPLAYS WITH OPENINGS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a housing;
a display mounted in the housing, wherein the display has an active area, an inactive area, an array of pixels in the active area, and a region in the active area; and
a light sensor located behind the display, wherein the light sensor detects light through the region in the active area.

US Pat. No. 10,431,635

FOLDABLE OLED DEVICE WITH COMPATIBLE FLEXURAL STIFFNESS OF LAYERS

3M INNOVATIVE PROPERTIES ...

1. A flexible organic light emitting diode (OLED) display device, comprising:an upper module having a cover window film;
a lower module;
a display module between the upper module and the lower module, the display module including an OLED and an OLED substrate between the OLED and the lower module;
a touch sensor between the OLED and the upper module;
a first coupling layer between the cover window film and the touch sensor;
a second coupling layer between the touch sensor and the OLED; and
a third coupling layer between the OLED substrate and the lower module,
wherein a shear modulus of the first coupling layer is less than 70 kPa at room temperature,
wherein the upper module has a first Young's modulus, the lower module has a second Young's modulus, and the first Young's modulus is different from the second Young's modulus,
wherein 100>(LS/TW)>0.001, where L is a flexural stiffness of the lower module, S is a flexural stiffness of the OLED substrate, T is a flexural stiffness of the touch sensor, and W is a flexural stiffness of the cover window film.

US Pat. No. 10,431,634

ORGANIC ELECTROLUMINESCENCE DEVICE WITH RECESSES FILLED WITH A PHOSPHOR FILLING LAYER IN THE BASE MATERIAL

SHARP KABUSHIKI KAISHA, ...

1. An organic electroluminescence device comprising:a base material including a recessed portion on a surface side;
a reflective layer;
a filling layer having optical transparency;
a first electrode having optical transparency;
an organic layer including at least a light emitting layer; and
a second electrode having optical transparency and light reflectivity,
the reflective layer being disposed at least along a surface of the recessed portion, the filling layer being disposed in the recessed portion through the reflective layer, the first electrode being disposed at least on an upper-layer side of the filling layer, the organic layer being disposed on an upper-layer side of the first electrode, and the second electrode being disposed on an upper-layer side of the organic layer, wherein
the filling layer includes at least one type of phosphor, and
a lower face of the first electrode at a position inside the recessed portion is positioned lower than a plane including the surface side of the base material.

US Pat. No. 10,431,633

METHOD FOR PRODUCING A MULTI-COLORED LIGHT EMITTING COMPONENT

1. A method for producing a component comprising a substrate configured to emit an electromagnetic radiation in a first wavelength range and an electromagnetic radiation in a second wavelength range within one surface area, the method comprising:providing the substrate having a surface on which a plurality of electrodes are formed within the one surface area;
depositing a first layer stack on the entire one surface area, the first layer stack comprising at least one layer configured to cause emission of the electromagnetic radiation in the first wavelength range, and a first cover layer;
removing the first layer stack from a partial surface area comprising at least one of the electrodes;
depositing a second layer stack on the entire one surface area after the first layer stack was removed from the partial surface area, the second layer stack comprising at least one layer configured to cause emission of the electromagnetic radiation in the second wavelength range and a second cover layer; and
producing an electrically conductive connection between the first and second cover layers, the first and second cover layers configured to act as a counterelectrode, wherein the at least one layer of the second layer stack deposited on the first layer stack is short circuited so as not to emit the electromagnetic radiation in the second wavelength range.

US Pat. No. 10,431,632

LIGHT-EMITTING DEVICE, ELECTRONIC APPLIANCE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first light-emitting element including a first electrode, a first transparent conductive layer in contact with the first electrode, an EL layer in contact with the first transparent conductive layer, and a second electrode in contact with the EL layer;
a second light-emitting element including a third electrode, a second transparent conductive layer in contact with the third electrode, the EL layer in contact with the second transparent conductive layer, and the second electrode in contact with the EL layer; and
a third light-emitting element including a fourth electrode, the EL layer in contact with the fourth electrode, and the second electrode in contact with the EL layer,
wherein the EL layer includes a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer,
wherein the light with the wavelength ?1 is emitted from the first light-emitting element,
wherein the light with the wavelength ?2 is emitted from the second light-emitting element,
wherein the light with the wavelength ?3 is emitted from the third light-emitting element,
wherein a wavelength relation of ?3>?1>?2 is satisfied,
wherein an optical path length from the first electrode to the second light-emitting layer is 3?1/4, and an optical path length from the first electrode to the second electrode is ?1 in the first light-emitting element,
wherein an optical path length from the third electrode to the third light-emitting layer is 3?2/4, and an optical path length from the third electrode to the second electrode is ?2 in the second light-emitting element, and
wherein an optical path length from the fourth electrode to the first light-emitting layer is ?3/4, and an optical path length from the fourth electrode to the second electrode is ?3/2 in the third light-emitting element.

US Pat. No. 10,431,631

STACKED OLED DEVICE AND METHOD OF MAKING THE SAME

WUHAN CHINA STAR OPTOELEC...

1. A stacked OLED device, comprisinga first forward OLED structure, a first reverse OLED structure and a second forward OLED structure stacked in order from bottom to top on a substrate;
a charge generation layer disposed between the first forward OLED structure and the first reverse OLED structure as a common cathode of the first forward OLED structure and the first reverse OLED structure, and each organic functional layer in the first forward OLED structure and each organic functional layer in the first reverse OLED structure are symmetrical with the charge generation layer;
a transparent insulating layer disposed between the first reverse OLED structure and the second forward OLED structure;
an anode of the first forward OLED structure and an anode of the second forward OLED structure are connected through a conductive layer.

US Pat. No. 10,431,630

METHOD FOR PRODUCING TRANSISTORS, IN PARTICULAR SELECTION TRANSISTORS FOR NON-VOLATILE MEMORY, AND CORRESPONDING DEVICE

STMicroelectronics (Rouss...

11. A method for producing a plurality of MOS transistors commonly controlled by two vertical gates, comprising:etching a semiconductor substrate to form trenches which surround a rectangular semiconductor zone doped with a first type of conductivity providing a common channel region for the plurality of MOS transistors and having a buried region doped with a second type of conductivity providing a common source region for the plurality of MOS transistors, said rectangular semiconductor zone having opposed first sides and opposed second sides, wherein the opposed first sides are longer than the opposed second sides;
forming an isolated region comprising a gate material in first ones of said trenches on at least the opposed first sides of the rectangular semiconductor zone to form the two vertical gates for the plurality of MOS transistors;
making an electrically conductive connection in second ones of said trenches trench between the two vertical gates along the opposed second sides of the rectangular semiconductor zone; and
forming, at a top surface of the surrounded rectangular semiconductor zone providing the common channel region, a plurality of drain regions for the plurality of MOS transistors, wherein the drain regions are insulated from each other and doped with the second type of conductivity.

US Pat. No. 10,431,629

MEMORY ARRAYS AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS

Micron Technology, Inc., ...

12. A method of forming an array of memory cells, comprising:forming access lines relative to a substrate;
forming lines of spaced sense line contacts between and along first pairs of the access lines and forming lines of spaced inner electrode material between and along second pairs of the access lines;
forming lines of covering material that are elevationally over and along the lines of the spaced sense line contacts and between the lines of spaced inner electrode material;
forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material and elevationally over and along the lines of spaced inner electrode material;
removing the covering material over the spaced sense line contacts and exposing the spaced sense line contacts; and
forming sense lines that are electrically coupled to the spaced sense line contacts.

US Pat. No. 10,431,628

DUAL CHANNEL/GATE VERTICAL FIELD-EFFECT TRANSISTOR (FET) FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)

SPIN MEMORY, INC., Fremo...

1. A method, comprising:forming a drain material above a substrate in a film thickness direction;
forming and patterning a first masking layer above the drain material in the film thickness direction, the first masking layer being patterned to expose a portion of the drain material having a circular cross-section along a plane perpendicular to the film thickness direction;
removing all portions of the drain material except for the exposed portion of the drain material and portions positioned directly therebelow in the film thickness direction using the first masking layer;
removing the first masking layer during or after removal of the portions of the drain material;
forming a first insulative layer above portions of the substrate not covered by the drain material to a thickness consistent with an upper surface of the drain material;
forming a second insulative layer above the first insulative layer and the drain material in the film thickness direction to a desired thickness;
placing the first masking layer above the second insulative layer aligned with previous placement of the first masking layer above the substrate to expose a portion of the second insulative layer having the circular cross-section along the plane perpendicular to the film thickness direction;
removing the exposed portion of the second insulative layer to expose the upper surface of the drain material;
removing the first masking layer during or after removal of the exposed portion of the second insulative layer;
growing the second insulative layer along the plane perpendicular to the film thickness direction to shrink a diameter of a hole through the second insulative layer having the circular cross-section along the plane perpendicular to the film thickness direction;
removing exposed portions of the drain material through the hole of the second insulative layer to form a drain contact having a circular cross-sectional hole in a center thereof along the plane perpendicular to the film thickness direction;
removing the first insulative layer and the second insulative layer;
removing portions of the substrate positioned directly below the drain contact to a desired level in the film thickness direction to form a channel having the circular cross-section with a hole in a center thereof along the plane perpendicular to the film thickness direction;
forming gate dielectric layers above the drain contact and on sides of the drain contact and the channel, the gate dielectric layers having concentric circular cross-sections along the plane perpendicular to the film thickness direction, wherein the circular cross-section of the drain contact has one circular cross-sectional portion of the gate dielectric layers in direct contact on either side thereof;
forming a source layer below the channel in the film thickness direction, the source layer being electrically coupled to the channel;
forming and patterning a second masking layer above the gate dielectric layers positioned above the drain contact and above the hole in the center of the drain contact in the film thickness direction, wherein the second masking layer has a rectangular cross-section along the plane perpendicular to the film thickness direction that is positioned above a plurality of drain contacts;
removing portions of the source layer and substrate not covered by the second masking layer in the film thickness direction to form a source line that is electrically coupled to a plurality of channels along the plane perpendicular to the film thickness direction;
removing the second masking layer;
forming a third insulative layer having a thickness in the film thickness direction that corresponds to a desired height of a lower surface of subsequently formed gate layers;
forming the gate layers above the third insulative layer on sides of the gate dielectric layers to a thickness coincident with a lower surface of the drain contact in the film thickness direction, wherein an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane perpendicular to the film thickness direction, and wherein an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane perpendicular to the film thickness direction;
removing an upper portion of the gate dielectric layers above the drain contact to expose an upper surface of the drain contact;
forming an electrode above the upper surface of the drain contact; and
forming a fourth insulative layer above the third insulative layer and the gate layers in the film thickness direction, and along sides of the electrode along the plane perpendicular to the film thickness direction.

US Pat. No. 10,431,627

MAGNETIC MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A magnetic memory device comprising:a magnetic tunnel junction pattern comprising a free pattern, a reference pattern and a tunnel barrier pattern between the free pattern and the reference pattern, the free pattern comprising:
a first sub-free pattern;
a second sub-free pattern; and
a third sub-free pattern,
wherein the first sub-free pattern is between the tunnel barrier pattern and the third sub-free pattern;
wherein the second sub-free pattern is between the first sub-free pattern and the third sub-free pattern and includes nickel-cobalt-iron-boron (NiCoFeB);
wherein the third sub-free pattern includes nickel-iron-boron (NiFeB);
wherein a thickness of the first sub-free pattern is greater than a thickness of the second sub-free pattern and a thickness of the third sub-free pattern;
wherein a nickel content of the first sub-free pattern is smaller than a nickel content of the second sub-free pattern and a nickel content of the third sub-free pattern; and
wherein a cobalt content of the third sub-free pattern is smaller than a cobalt content of the second sub-free pattern.

US Pat. No. 10,431,626

IMAGE SENSOR DEVICES

Silicon Optronics, Inc., ...

1. An image sensor device, comprising:a substrate;
a plurality of photoelectric conversion units for collecting image signals disposed in the substrate;
a first dielectric layer disposed upon the substrate;
a plurality of metal layers disposed in the first dielectric layer, wherein each metal layer adjacent to the substrate is defined as a first metal layer, and each metal layer adjacent to the top of the first dielectric layer is defined as a top metal layer;
a trench disposed in the first dielectric layer and located between adjacent metal layers, extending from the top of the first dielectric layer towards the substrate to the first metal layer;
a filling material filled in the trench;
a second dielectric layer disposed upon the first dielectric layer and the trench, and directly contacting with the first dielectric layer and the trench; and
a light source or a detected object disposed over the second dielectric layer.

US Pat. No. 10,431,625

IMAGE SENSOR AND METHOD OF FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. An image sensor comprising:a substrate including a first element;
a trench formed in the substrate, the trench defining a light receiving region and a readout region isolated from each other by the trench;
an impurity region formed in the substrate in contact with the trench; and
a re-crystallization layer formed in the substrate in contact with bottom and side surfaces of the trench and a surface of the substrate, the re-crystallization layer having a first portion disposed in the light receiving region and a second portion disposed in the readout region,
wherein the first portion of the re-crystallization layer includes a second element,
wherein the second portion of the re-crystallization layer includes a third element which is different from the second element, and
wherein the second and third elements are different from the first element wherein the second element contained in the first re-crystallization layer disposed in the light receiving region includes at least one of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn); and
wherein the third element contained in the first re-crystallization layer disposed in the readout region includes at least one of carbon (C), silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), and fluorine (F).

US Pat. No. 10,431,624

METHOD OF MANUFACTURING IMAGE SENSOR INCLUDING NANOSTRUCTURE COLOR FILTER

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing an image sensor, the method comprising:preparing a sensor substrate comprising:
a sensor layer comprising a photosensitive cell that receives light and generates electric signals; and
a signal line layer comprising lines to receive the electric signals from the photosensitive cell;
forming a first material layer having a first refractive index on the sensor substrate; and
forming a nanopattern layer on the first material layer, the nanopattern layer comprising a material having a second refractive index greater than the first refractive index,
wherein the sensor layer is disposed between the signal line layer and the first material layer.

US Pat. No. 10,431,623

METHOD APPLIED TO BJT PIXEL OF IMAGE SENSOR APPARATUS AND IMAGE SENSOR APPARATUS

PixArt Imaging Inc., Hsi...

1. A method applied to a BJT pixel of a pixel array of an image sensor apparatus, comprising:obtaining at least one of a surface quality signal of a first image sensed by the BJT pixel and a shutter turn-on time corresponding to the first image; and
adaptively adjusting a pre-flash time of the BJT pixel for sensing of a second image according to the at least one of the surface quality signal of the first image and the shutter turn-on time corresponding to the first image;
wherein the second image follows the first image.

US Pat. No. 10,431,621

SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device, comprising:a first substrate including a photodiode, a floating diffusion, a first plurality of transistors and a first electrode at a first surface side of the first substrate opposite to a light incident surface side; and
a second substrate including a second electrode at a first surface side of the second substrate and a second plurality of transistors,
wherein the first substrate and the second substrate are bonded to each other such that the first surface side of the first substrate and the first surface side of the second substrate are facing to each other,
wherein a side of the first electrode is covered by a first insulating film,
wherein a portion of the first electrode and a portion of the first insulating film are bonded to the second electrode, and
wherein, except for a bonding face of the first electrode, the first electrode is covered by the first insulating film.

US Pat. No. 10,431,620

SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a first semiconductor substrate electrically connected to a second semiconductor substrate,
a diffusion prevention film that prevents diffusion of a dangling bond terminating atom used for reducing an interface state of the first semiconductor substrate and the second semiconductor substrate, and
an atom supply film that supplies the dangling bond terminating atom,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with the diffusion prevention film and the atom supply film between the first semiconductor substrate and the second semiconductor substrate; and
wherein the interface state of the first semiconductor substrate is lower than that of the second semiconductor substrate.

US Pat. No. 10,431,619

SOLID-STATE IMAGE PICKUP DEVICE HAVING A PIXEL SEPARATION WALL

Sony Corporation, Tokyo ...

1. A solid-state image pickup device, comprising:a plurality of pixels that perform photoelectric conversion on light, the light entering the respective pixels from a back surface of the solid-state image pickup device via different lenses for each pixel, wherein at least some of the pixels in the plurality of pixels are phase difference detection pixels;
a wiring layer provided on a front surface of the solid-state image pickup device, wherein each phase difference detection pixel includes:
a first photoelectric conversion device;
a second photoelectric conversion device;
a divided pixel separation wall extending between at least portions of the first photoelectric conversion device and the second photoelectric conversion device; and
a floating diffusion,
wherein the divided pixel separation wall includes a front-side trench formed from the front surface and a backside trench formed from the back surface.

US Pat. No. 10,431,618

STACKED LENS STRUCTURE METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A stacked lens structure comprising:a plurality of substrates including a first substrate having a first through-hole, a second substrate having a second through-hole, and a third substrate having a third through-hole; and
a plurality of lenses including a first lens disposed in the first through-hole, a second lens disposed in the second through-hole, and a third lens disposed in the third through-hole;
wherein,
the first substrate is directly bonded to the second substrate via a first insulating layer to form a first bonding surface,
the second substrate is directly bonded to the third substrate via a second insulating layer to form a second bonding surface, and
a first distance from a central line to the first bonding surface is different than a second distance from the central line to the second bonding surface, the central line passing through a central point of the stacked lens structure and running in a plane direction of the first to third substrates, the central point being a center of the stacked lens structure in a thickness direction of the stacked lens structure.

US Pat. No. 10,431,617

PHOTOELECTRIC CONVERSION DEVICE AND APPARATUS

Canon Kabushiki Kaisha, ...

1. A photoelectric conversion device, comprising:a substrate including a photoelectric conversion area in which a plurality of photoelectric conversion portions are arranged along a main surface;
a film that is disposed on the photoelectric conversion area, and includes an inner surface on a side of the substrate and an outer surface on a side opposite to the side of the substrate;
a first member that is disposed between the film and the photoelectric conversion area, includes a bottom surface located on the side of the substrate, a top surface located on the side opposite to the side of the substrate, and a side surface connecting the bottom surface and the top surface, and includes a light shielding body;
a second member disposed at least between the film and the top surface; and
a color filter that is disposed above the substrate so that the film is arranged between the color filter and a photoelectric conversion portion in the photoelectric conversion area,
wherein a distance from the main surface to the top surface is smaller than a distance from the main surface to the color filter,
wherein the film includes a first part, a second part, and a third part, the first part overlapping at least a part of each of the photoelectric conversion portions in a normal direction to the main surface of the substrate, the second part overlapping the top surface in the normal direction, and the third part locating between the first part and the second part,
wherein a distance from the main surface to the inner surface at the first part is smaller than the distance from the main surface to the top surface, a distance from the main surface to the outer surface at the first part is smaller than a distance from the main surface to the outer surface at the second part, and the outer surface at the third part inclines to the top surface,
wherein a front surface of the second member on a side of the film inclines to the top surface, between the film and the top surface in the normal direction, and
wherein one or both of the following (A) and (B) are satisfied,
(A) the second member has a refractive index lower than a refractive index of the film, and
(B) the film and the second member each include a silicon compound, and the second member includes lower nitrogen concentration and/or higher oxygen concentration as compared with the film.

US Pat. No. 10,431,616

COLOR FILTER ARRAYS FOR IMAGE SENSORS

Google LLC, Mountain Vie...

1. An imaging device comprising:a color filter array arranged to filter incident light, the color filter array having a repeating pattern of color filter elements, the color filter elements including yellow filter elements, green filter elements, and blue filter elements;
an image sensor having photosensitive regions corresponding to the color filter elements, the photosensitive regions being configured to respectively generate electrical signals indicative of intensity of the color-filtered light at the photosensitive regions; and
one or more processors configured to generate color image data based on the electrical signals from the photosensitive regions and determine a red intensity for a pixel of the image data based on a green intensity of a first photosensitive region corresponding to a particular green filter element of the green filter elements and an average of yellow intensities of a second photosensitive region and a third photosensitive region corresponding to two particular yellow filter elements of the yellow filter elements, where the first, second, and third photosensitive regions are adjacent to each other.

US Pat. No. 10,431,615

FAN-OUT SENSOR PACKAGE AND CAMERA MODULE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A fan-out sensor package comprising:a first interconnection member having a through-hole and including an electrical connection structure;
a sensor disposed in the through-hole of the first interconnection member and having an active surface having connection pads and microlenses disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first interconnection member and the active surface of the sensor and filling the through-hole of the first interconnection member, the sensor and the first interconnection member being spaced apart by the encapsulant;
a rear redistribution layer disposed on the encapsulant;
rear vias penetrating through the encapsulant and electrically connecting the connection pads of the sensor and the rear redistribution layer to each other; and
a second interconnection member disposed on the first interconnection member and the inactive surface of the sensor, the sensor and the first interconnection member being disposed between the rear distribution layer and the second interconnection member,
wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the sensor through at least the electrical connection structure of the first interconnection member, the rear redistribution layer, and the rear vias.

US Pat. No. 10,431,614

EDGE SEALS FOR SEMICONDUCTOR PACKAGES

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor package comprising:a digital signal processor comprising a first side and a second side;
an image sensor array comprising a first side and a second side, the first side of the image sensor array coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and a first edge seal coupled directly with the HBI bond pads;
an etch stop layer comprised in the second side of the digital signal processor; and
one or more first openings extending from the second side of the image sensor array into the second side of the digital signal processor and to the etch stop layer in the second side of the digital signal processor, the one or more first openings coated with a sealing material, the one or more first openings forming a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor;
wherein the first edge seal is comprised of a first metal stack comprised within the digital signal processor directly coupled to a second metal stack comprised within the image sensor array.

US Pat. No. 10,431,613

IMAGE SENSOR COMPRISING NANOANTENNA

SAMSUNG ELECTRONICS CO., ...

1. An image sensor in which a plurality of nanoantennas are arranged so as to satisfy a sub-wavelength condition, wherein each of the plurality of nanoantennas comprises:a respective diode comprising a first conductive semiconductor layer and a second conductive semiconductor layer; and
a respective transistor comprising a third conductive semiconductor layer that is in contact with the second conductive semiconductor layer, a gate electrode that is in contact with each of the third conductive semiconductor layer and the second conductive semiconductor layer, and a diffusion node that is in contact with the third conductive semiconductor layer and is not in contact with the second conductive semiconductor layer,
wherein the respective diode is disposed on a first surface of the third conductive semiconductor layer and the diffusion node is disposed on a second surface of the third conductive semiconductor which opposes the first surface of the third conductive semiconductor.

US Pat. No. 10,431,612

SWITCHES WITH MULTIPLE FIELD-EFFECT TRANSISTORS HAVING PROXIMITY ELECTRODES

SKYWORKS SOLUTIONS, INC.,...

1. A field-effect transistor (FET) device comprising:an insulator layer;
a substrate layer implemented under the insulator layer;
an active silicon layer implemented over the insulator layer with a first active FET and a second active FET formed from the active silicon layer, each of the first active FET and the second active FET including a source terminal, a drain terminal, and a gate terminal;
a first proximity electrode implemented adjacent to the first active FET, the first proximity electrode configured to receive a voltage and to generate an electric field between the first proximity electrode and a region generally underneath the first active FET; and
a second proximity electrode implemented adjacent to the second active FET, the second proximity electrode configured to receive a voltage and to generate an electric field between the second proximity electrode and a region generally underneath the second active FET.

US Pat. No. 10,431,611

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a thin film transistor, comprising:forming an active layer on a base substrate;
forming a metal layer on a surface of the active layer;
processing the metal layer using a patterning process for one time and an oxidation treatment process to form a source electrode, a drain electrode and a passivation layer, the source electrode and the drain electrode are in contact with the active layer, and the passivation layer is formed on a side of the source electrode and the drain electrode away from the active layer, which includes:
forming a photoresist layer on a surface of the metal layer;
processing the photoresist layer using the patterning process for one time to form a photoresist completely-removed region, photoresist partly-reserved regions and a photoresist completely-reserved region; wherein the photoresist partly-reserved regions are connected to the photoresist completely-reserved region;
performing a complete oxidation treatment on a region of the metal layer corresponding to the photoresist completely-removed region to form a first passivation portion;
removing a photoresist in the photoresist partly-reserved regions;
performing a partial oxidation treatment on a region of the metal layer corresponding to the photoresist partly-reserved regions to form the source electrode, the drain electrode and a second passivation portion; wherein the source electrode and drain electrode are in contact with the active layer, and the second passivation portion is formed on a side of the source electrode and the drain electrode away from the active layer; the first passivation portion and the second passivation portion form the passivation layer;
removing a photoresist in the photoresist completely-reserved region to form a conductive portion connected to the source electrode and the drain electrode.

US Pat. No. 10,431,610

X-RAY DETECTING PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. An X-ray detecting panel comprising:a substrate;
m gate lines on the substrate;
n data lines on the substrate and intersecting the m gate lines;
a thin film transistor in an area between adjacent gate lines of the first gate line to the (m?1 )th gate line on the substrate;
a non-driving element in an area between the (m?1)th gate line and the mth gate line on the substrate; and
a photoelectric converter connected to the thin film transistor, wherein the thin film transistor and the non-driving element are connected to different ones of the gate lines, wherein the non-driving element includes a gate electrode connected to the mth gate line and a semiconductor layer insulated from the gate electrode, and does not include a source electrode and a drain electrode.

US Pat. No. 10,431,609

ARRAY SUBSTRATE, DISPLAY PANEL WITH FRIT AT CUTTING EDGE FOR NARROW BEZEL

SHANGHAI TIANMA AM-OLED C...

1. An array substrate, comprising:a display region; and
an encapsulation region divided into a first region away from the display region and a second region adjacent to the display region,
wherein:
the encapsulation region includes a metal layer configured only in the second region, a frit solution layer configured in both the first region and the second region, and a cutting edge configured in the first region, the cutting edge disposed along a part of the frit solution layer in the first region and having a distance from a border line of the first region away from the second region; and
the array substrate is cut along the cutting edge.

US Pat. No. 10,431,608

DUAL CONVERSION GAIN HIGH DYNAMIC RANGE READOUT FOR COMPARATOR OF DOUBLE RAMP ANALOG TO DIGITAL CONVERTER

OmniVision Technologies, ...

1. A comparator comprising:a second stage coupled to provide an output in response to an intermediate voltage;
a first stage coupled to provide the intermediate voltage in response to an input, the first stage comprising:
a pair of cascode devices coupled to a current mirror;
a low gain input coupled to first and second inputs of the first stage via first and second switches, and further selectively coupled to the pair of cascode devices via third and fourth switches; and
a high gain input coupled to the first and second inputs of the first stage via the first and second switches, and further selectively coupled to the pair of cascode devices via fifth and sixth switches,
wherein, based on a low conversion gain mode, the low gain input is coupled to the first and second inputs by the first and second switches, and further coupled to the pair of cascode devices by the third in fourth switches in response to a control signal being in a first state, and
wherein, based on a high conversion gain mode, the high gain input is coupled to the first and second inputs by the first and second switches, and further coupled to the pair of cascode device by the fifth and sixth switch in response to the control signal being in a second state.

US Pat. No. 10,431,607

DISPLAY SUBSTRATE HAVING AN ORGANIC LAYER AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A method of fabricating a display substrate having an organic layer, comprising:forming the organic layer on a base substrate to reduce parasitic capacitance between electrodes in different layers of the display substrate;
subsequent to forming the organic layer, forming a first electrode layer on a side of the organic layer away from the base substrate, the first electrode layer formed in direct contact with the organic layer;
subjecting the organic layer to a surface treatment process to descum organic residues from a surface of the organic layer; and
subsequent to forming the first electrode layer and subsequent to subjecting the organic layer to the surface treatment process, forming an inorganic insulating passivation layer on a side of the organic layer and the first electrode layer away from the base substrate, wherein the inorganic insulating passivation layer is formed in direct contact with the first electrode layer and in direct contact with the organic layer, the inorganic insulating passivation layer is formed so that an orthographic projection of the inorganic insulating passivation layer on the base substrate substantially covers orthographic projections of the first electrode layer and the organic layer.

US Pat. No. 10,431,606

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a display region, and a peripheral region that is outside of the display region;
a first dummy pad and a second dummy pad at the peripheral region, the first dummy pad vertically overlapping the second dummy pad;
an insulating layer completely covering the first and second dummy pads such that each of the first and second dummy pads does not contact a conductive layer, wherein a top surface of a first portion of the insulating layer above a center of the first and second dummy pads is higher than a top surface of a second portion of the insulating layer adjacent the first and second dummy pads; and
a pad over the second portion of the insulating layer at the peripheral region, the pad being electrically connected to an electronic chip or a printed circuit board.

US Pat. No. 10,431,605

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A method of manufacturing a thin film transistor array panel, the method comprising:providing a gate line and a data line comprising a drain electrode on an insulating substrate;
providing an organic insulating layer, through which a first contact hole is formed, on the gate line and the data line;
providing a common electrode, through which a second contact hole is formed, on the organic insulating layer;
providing a passivation layer on the common electrode;
forming a third contact hole through the passivation layer to expose an end of the drain electrode; and
providing a pixel electrode on the passivation layer to be in contact with the drain electrode through the third contact hole,
wherein the third contact hole is formed to be adjacent to one surface of the first contact hole.

US Pat. No. 10,431,604

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate including:
a main display portion;
an edge portion disposed at one of edges of the main display portion; and
a first side portion bent from the edge portion;
scan lines disposed on the substrate;
data lines disposed on the substrate;
transistors connected to the scan lines and the data lines; and
a data voltage transmission line connected to a data line disposed in the first side portion and disposed on both the edge portion and the main display portion,
wherein the data line and the data voltage transmission line are disposed in different layers from each other.

US Pat. No. 10,431,603

SEMICONDUCTOR DEVICE

JOLED INC., Tokyo (JP)

1. A semiconductor device comprising:a substrate including a first region, a second region, and a third region that are provided adjacently in this order in a predetermined direction;
a first wiring line that is provided on the substrate and provided in each of the first region, the second region, and the third region;
a semiconductor film having a low-resistance region in at least a portion of the semiconductor film, the semiconductor film being provided between the first wiring line and the substrate in the first region, and being in direct physical contact with the first wiring line in the second region;
a second wiring line that is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region; and
an insulating film provided between the first wiring line in the first region and the semiconductor film in the first region.

US Pat. No. 10,431,602

ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display area; and
a surrounding area having a first signal line, and a second signal line disposed over, insulated from, and staggered at a staggering region with, the first signal line, the surrounding area encircling the display area;
wherein:
the surrounding area comprises a first zone and a second zone, wherein the first zone and the second zone are configured to have a height difference to form a substantially uneven upper surface of the array substrate to thereby allow a sealant to be securely attached onto the array substrate; and
an upper surface of the first zone is substantially flat across the first zone from over a side of the second signal line to an opposing side of the second signal line.

US Pat. No. 10,431,601

METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. A method for manufacturing an array substrate, comprising:forming, on one side of a substrate, a gate electrode layer, a gate insulation layer located on the gate electrode layer and a semiconductor layer located on the gate insulation layer, wherein the gate electrode layer has a same pattern as the semiconductor layer;
forming an etching stop layer on the semiconductor layer;
forming a first through hole, a second through hole and a third through hole in the etching stop layer by patterning the etching stop layer;
forming a source electrode layer on the etching stop layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; and
forming an active layer by etching the semiconductor layer at a location corresponding to the third through hole, wherein the gate electrode layer comprises a first part at the location corresponding to the third through hole and a second part, the second part of the gate electrode layer using a same pattern as the active layer and being different from the first part;
wherein the forming, on one side of the substrate, the gate electrode layer, the gate insulation layer located on the gate electrode layer and the semiconductor layer located on the gate insulation layer comprises:
forming a first metal layer on the substrate, and forming the gate electrode layer by patterning the first metal layer;
forming the gate insulation layer on the gate electrode layer;
forming a semiconductor material layer on the gate insulation layer; and
forming the semiconductor layer by patterning the semiconductor material layer by taking the gate electrode layer as a mask.

US Pat. No. 10,431,600

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A METAL OXIDE FILM

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor film at a first temperature;
processing the oxide semiconductor film into an island shape;
depositing a material to be a source electrode and a drain electrode over the oxide semiconductor film by a sputtering method;
processing the material to form the source electrode and the drain electrode;
forming a protective insulating film over the oxide semiconductor film, the source electrode and the drain electrode;
heating the protective insulating film at a second temperature which is higher than the first temperature;
forming a metal oxide film over the protective insulating film by a sputtering method; and
heating the protective insulating film at a third temperature which is higher than the first temperature,
wherein at least one of the second temperature and the third temperature is the highest in the method.

US Pat. No. 10,431,599

SUBSTRATE FOR DISPLAY DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. A display device, comprising:a substrate;
a pixel on the substrate, the pixel including:
a first TFT on the substrate, the first TFT including:
a first active layer formed of oxide semiconductor; and
a second thin film transistor (TFT) on the substrate, the second TFT including:
a gate electrode on the substrate,
at least a first part of a gate insulating film on the gate electrode,
a second active layer formed of polycrystalline silicon on the first part of the gate insulating film, wherein a bottom surface of the second active layer faces the gate electrode, and
a source electrode and a drain electrode contacting a top surface of the second active layer;
a light-emitting device electrically connected to the second TFT; and
a connection electrode contacting both of the drain electrode of the second TFT and an anode electrode of the light-emitting device between the drain electrode of the second TFT and the anode electrode.

US Pat. No. 10,431,598

VERTICAL SEMICONDUCTOR DEVICE WITH THINNED SUBSTRATE

QUALCOMM Incorporated, S...

1. An integrated circuit chip comprising:an active semiconductor region having a plurality of fabricated semiconductor structures comprising a source, drain and channel that form a vertical semiconductor device, the active semiconductor region being exposed on a bottom side by the absence of substrate material such that the drain and channel of the semiconductor structures are exposed semiconductor structures that provide the vertical semiconductor device with an electrical contact; and
a bottom side electrode connected to the drain or the channel, wherein:
the channel isolates the source from the drain;
the channel has a bottom boundary and a side boundary extending downward from a top surface of the active semiconductor region to the bottom boundary; and
the drain and channel are in contact along the side boundary and are not in contact along the bottom boundary, further wherein:
the source has a second bottom boundary and a second side boundary extending downward from the top surface of the active semiconductor region to the second bottom boundary; and
the source and the channel are in contact along the second side boundary and are not in contact along the second bottom boundary.

US Pat. No. 10,431,597

RF ELECTRONIC CIRCUIT COMPRISING CAVITIES BURIED UNDER RF ELECTRONIC COMPONENTS OF THE CIRCUIT

1. An RF electronic circuit comprising:a single unitary substrate comprising at least one support layer and a semiconducting surface layer located on the support layer;
at least one electronic component able to carry out at least one of an RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the semiconducting surface layer; and
a matrix of cavities located in at least one first region of the support layer located under the first region of the semiconducting surface layer and not in the semiconducting surface layer, facing at least the electronic component, and such that internal volumes of the cavities are separated and isolated from each other by portions of the support layer,
wherein one lateral dimension of each said cavity is greater than or equal to about 10 ?m, and
wherein the cavities are aligned underneath said at least one electronic component.

US Pat. No. 10,431,596

STAGGERED WORD LINE ARCHITECTURE FOR REDUCED DISTURB IN 3-DIMENSIONAL NOR MEMORY ARRAYS

SUNRISE MEMORY CORPORATIO...

1. A memory structure, comprising:a semiconductor substrate having a planar surface;
an array of memory cells sharing a common bit line that extends along a first direction substantially parallel the planar surface of the semiconductor substrate, wherein a first group of the memory cells are provided on a first side of the common bit line and wherein a second group of the memory cells are provided on a second side of the common bit line opposite the first side and wherein each memory cell comprises a storage layer;
a first plurality of conductors provided above the semiconductor substrate and below the array of memory cells, each conductor in the first plurality of conductors extending along a second direction that is parallel the planar surface and substantially perpendicular to the first direction, wherein the conductors of the first plurality of conductors are separated from each other by a first distance;
a second plurality of conductors provided above the array of memory cells, each conductor in the second plurality of conductors extending along the second direction, wherein the conductors of the second plurality of conductors are separated from each other by the first distance, and wherein the second plurality of conductors are offset from the first set of conductors by substantially half the first distance along the first direction;
a third plurality of conductors each extending along a third direction substantially perpendicular to the planar surface, wherein a first group of the third plurality of conductors each contact a conductor in the first plurality of conductors and wherein a second group of the third plurality of conductors each contact a conductor in the second plurality of conductors, wherein each conductor in the first and second groups of the third plurality of conductors are provided in contact with a storage layer of a memory cell in the first group or the second group of the memory cells, serving as a gate electrode for the memory cell.

US Pat. No. 10,431,595

MEMORY DEVICES HAVING VERTICALLY EXTENDING CHANNEL STRUCTURES THEREIN

Samsung Electronics Co., ...

1. A memory device comprising:a substrate having a first source film thereon;
an upper stacked structure on the first source film;
an electrically conductive channel structure extending through the upper stacked structure and the first source film, said channel structure comprising a channel pattern, which extends vertically through the upper stacked structure and the first source film, and an information storage pattern on a sidewall of the channel pattern;
a second source film extending between the first source film and a surface of said substrate, said second source film contacting the channel pattern and comprising an upward extending protrusion, which extends underneath the information storage pattern; and
a channel protective film extending between at least a portion of the protrusion and at least a portion of the information storage pattern.

US Pat. No. 10,431,594

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a lower stack;
a first upper stack disposed on the lower stack;
a second upper stack disposed on the lower stack, and spaced apart from the first upper stack by a select line separation trench;
first plugs configured to pass through the first upper stack and the lower stack, each of the first plugs including a sidewall protruding further into the select line separation trench than a sidewall of the first upper stack facing the select line separation trench to define a sidewall of the select line separation trench;
second plugs configured to pass through the second upper stack and the lower stack, each of the second plugs including a sidewall protruding further into the select line separation trench than a sidewall of the second upper stack facing the select line separation trench to define a sidewall of the select line separation trench; and
a select line separation layer formed along a contour of the protruded sidewalls of the first and second plugs in the select line separation trench.

US Pat. No. 10,431,593

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor memory device, comprising:a substrate; and
a first channel group, a second channel group, a third channel group, and a fourth channel group each arranged in a first direction on the substrate,
the first channel group to the fourth channel group being spaced apart from each other along a second direction on the substrate that crosses the first direction,
each of the first channel group, the second channel group, the third channel group, and the fourth channel group including a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate,
the first channel group and the second channel group being adjacent to each other in the second direction and spaced apart by a first distance in the second direction,
the second channel group and the third channel group being adjacent to each other in the second direction and spaced apart by a second distance less than the first distance in the second direction, and
the third channel group and the fourth channel group being adjacent to each other in the second direction and spaced apart by a third distance less than the second distance in the second direction.

US Pat. No. 10,431,592

3D MEMORY DEVICE

Trinandable S.r.l., Mila...

1. A 3D memory device comprising:a substrate;
at least one first group of four first “U”-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and
at least one second group of four second “U”-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string portion, each of the second “U”-shaped memory cells strings including memory cells stacks along the second source line selector side string portion and along the second bit line selector side string portion;
wherein the first and second source line selector side string portions are between the first and second bit line selector side string portions;
wherein a first pair of the first “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the first “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of first “U”-shaped memory cells strings and one surrounded by the other, a first pair of the second “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the second “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of second “U”-shaped memory cells strings and one surrounded by the other;
wherein first bit line selectors surround the first bit line selector side string portions and second bit line selectors surround the second bit line selector side string portions, and wherein the first bit line selectors comprise one first bit line selector for each of the first bit line selector side string portions and the second bit line selectors comprise one second bit line selector for each of the second bit line selector side string portions;
wherein the 3D memory device comprises a first, a second, a third and a fourth bit lines operatively associated to the first and second groups of four first and second “U”-shaped memory cells strings, wherein:
the first bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of one of the first pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of one of the first pair of the second “U”-shaped memory cells strings;
the second bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of the other one of the first pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of the other one of the first pair of the second “U”-shaped memory cells strings;
the third bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of one of the second pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of one of the second pair of the second “U”-shaped memory cells strings, and
the fourth bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of the other one of the second pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of the other one of the second pair of the second “U”-shaped memory cells strings.

US Pat. No. 10,431,591

NAND MEMORY ARRAYS

Micron Technology, Inc., ...

1. A NAND memory array, comprising:a vertical stack of alternating insulative levels and wordline levels, the wordline levels having terminal ends corresponding to control gate regions;
charge-trapping material along the control gate regions of the wordline levels, and being spaced form the control gate regions by charge-blocking material; the charge-trapping material along the wordline levels being charge-trapping material segments; the charge-trapping material segments being vertically spaced from one another by intervening regions; charge migration being impeded along said intervening regions relative to charge migration within the charge-trapping material segments; and
channel material extending vertically along the stack and being spaced from the charge-trapping material segments by charge-tunneling material.

US Pat. No. 10,431,590

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a stacked body including
a first stacked unit and a second stacked unit stacked above the first stacked unit, each of the first and second stacked units including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween, and
a first intermediate layer provided above the first stacked unit and below the second stacked unit, a thickness of the first intermediate layer being greater than a thickness of the first insulating layers;
a semiconductor pillar piercing the stacked body in a stacking direction of the stacked body, the semiconductor pillar including a first semiconductor film portion covering an outer periphery of a first core insulator part extending in the a first stacked unit and a second semiconductor film portion covering an outer periphery of a second core insulator part extending in the a second stacked unit, the first semiconductor film portion and the second semiconductor film portion having asymmetric configurations with respect to the first intermediate layer;
a first charge storage film provided between the first semiconductor film portion and one part of the first electrode layers included in the first stacked unit; and
a second charge storage film provided between the second semiconductor film portion and another part of the first electrode layers included in the second stacked unit, wherein
the first semiconductor film portion is electrically connected to the second semiconductor film portion via a third semiconductor film portion provided in the first intermediate layer,
the first charge storage film is discontinuous with the second charge storage film, and
the first charge storage film and the second charge storage film are not provided between the third semiconductor film portion and the first intermediate layer.

US Pat. No. 10,431,589

MEMORY CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

FLOADIA CORPORATION, Tok...

10. A method for manufacturing a semiconductor integrated circuit device including:a memory circuit region in which a memory cell including a memory gate structure between a first select gate structure and a second select gate structure is disposed; and
a peripheral circuit region in which a peripheral circuit including a logic gate structure is disposed,
the method comprising:
a first dummy electrode layer forming process of forming a layered lower memory gate insulating film and a layered charge storage layer in this order on a semiconductor substrate in the memory circuit region, and then stacking a layered first insulating film and a layered logic dummy electrode layer in this order on the charge storage layer in the memory circuit region and the semiconductor substrate in the peripheral circuit region;
a dummy memory gate structure forming process of patterning the logic dummy electrode layer, the first insulating film, the charge storage layer, and the lower memory gate insulating film in the memory circuit region by using a patterned resist so that a dummy memory gate structure in which the lower memory gate insulating film, the charge storage layer, an upper memory gate insulating film, and a dummy memory gate electrode provided by patterning are stacked in this order is formed in the memory circuit region and the first insulating film and the logic dummy electrode layer remain intact in the peripheral circuit region using the resist;
a sidewall insulating film forming process of forming a layered sidewall insulating film across the memory circuit region and the peripheral circuit region, and then etching back the layered sidewall insulating film to expose the semiconductor substrate, thereby forming sidewall insulating films along facing sidewalls of the dummy memory gate structure in the memory circuit region;
a second dummy electrode layer forming process of forming a layered second insulating film across the memory circuit region and the peripheral circuit region to form sidewall spacers composed of the sidewall insulating films and the second insulating film on the respective facing sidewalls of the dummy memory gate structure, stacking a layered memory dummy electrode layer on the second insulating film, and removing the memory dummy electrode layer and the second insulating film in this order in the peripheral circuit region by using a patterned resist so that the second insulating film and the memory dummy electrode layer remain in the memory circuit region;
a dummy gate electrode forming process of patterning the logic dummy electrode layer and the first insulating film in the peripheral circuit region by using another patterned resist to form a dummy logic gate structure in which a dummy logic gate electrode is stacked on the semiconductor substrate through a logic gate insulating film, and etching back the memory dummy electrode layer and the second insulating film in the memory circuit region so that a sidewall-shaped dummy first select gate electrode is formed along one of the sidewall spacers of the dummy memory gate structure whereas the second insulating film remains below the dummy first select gate electrode to form a first select gate insulating film, and a sidewall-shaped dummy second select gate electrode is formed along the other sidewall spacer of the dummy memory gate structure whereas the second insulating film remains below the dummy second select gate electrode to form a second select gate insulating film;
an electrode exposing process of forming an interlayer insulating layer in the memory circuit region and the peripheral circuit region, and then processing the interlayer insulating layer to expose, on the interlayer insulating layer, top surfaces of the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode; and
a metal gate electrode forming process of removing the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode, and then forming, in electrode formation spaces in which the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode have been formed, a metal memory gate electrode, a metal first select gate electrode, a metal second select gate electrode, and a metal logic gate electrode each containing a metallic material.

US Pat. No. 10,431,587

SEMICONDUCTOR DEVICE FOR AVOIDING SHORT CIRCUIT BETWEEN ADJACENT STORAGE NODES AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate comprising a plurality of active regions, wherein each of the active regions comprises two source/drain regions, and each of the source/drain regions is disposed at a respective end of the active area;
a plurality of word lines disposed in the substrate, wherein each of the word lines is disposed elongated in a first direction;
a plurality of bit lines disposed on the substrate, wherein each of the bit lines is disposed elongated in a second direction and straddling the word lines, and each of the source/drain regions is disposed in a region surrounded by two of the word lines adjacent to each other and two of the bit lines adjacent to each other;
a plurality of storage node contacts disposed on the source/drain regions respectively, wherein a width of a top surface of each of the storage node contacts in the second direction is smaller than a width of a bottom surface of each of the storage node contacts in the second direction; and
a cap layer disposed on the word lines, wherein each of the storage node contacts is disposed on a plane of a top surface of the cap layer, and each of the storage node contacts has a trapezoid shape in the second direction.

US Pat. No. 10,431,586

SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
a first fin on the substrate;
a first source/drain on the first fin; and
a first contact plug on the first source/drain,
wherein a center of the first contact plug is offset from a center of the first fin,
wherein a bottom surface of the first contact plug is inclined with respect to a top surface of the substrate,
wherein the bottom surface of the first contact plug includes a first edge and a second edge opposite to the first edge, and
wherein the first edge is at a different level than the second edge.

US Pat. No. 10,431,585

SEMICONDUCTOR DEVICES WITH MULTI-GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,
wherein the first transistor comprises: a first nanowire having a first channel region; a first gate electrode surrounding the first nanowire; a first gate dielectric layer between the first nanowire and the first gate electrode; a first source/drain region connected to an edge of the first nanowire; and an inner-insulating spacer between the first gate dielectric layer and the first source/drain region,
the second transistor comprises: a second nanowire having a second channel region; a second gate electrode surrounding the second nanowire; a second gate dielectric layer between the second nanowire and the second gate electrode; and a second source/drain region connected to an edge of the second nanowire,
the second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region, and
the first source/drain region is not in contact with the first gate dielectric layer.

US Pat. No. 10,431,584

SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A fin field effect transistor (FinFET), comprising:a fin structure which has a first region made of a first semiconductor material, a second region made of a second semiconductor material different from the first semiconductor material, and a channel region made of a third semiconductor material different from the second semiconductor material;
an isolation region in which the first region and the second region are embedded, and from which at least an upper port of the channel region is exposed; and
a gate structure disposed over the channel region, wherein:
an interface between the second region and the first region is located below an upper surface of the isolation region,
the first semiconductor material includes a first Ge based semiconductor material,
the second semiconductor material includes a Si or a Si based semiconductor material,
the third semiconductor material includes a second Ge based semiconductor material, and
Ge contents of the first and second Ge based semiconductor materials are greater than a Ge content of the second semiconductor material.

US Pat. No. 10,431,582

HIGH SPEED SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a fin extending from a substrate;
a first source/drain feature;
a second source/drain feature;
a gate structure on the fin, wherein a first distance between the gate structure and the first source/drain feature is different from a second distance between the gate structure and the second source/drain feature; and
a buried channel extending from a sidewall of the first source/drain feature to a sidewall of the second source/drain feature, wherein a top surface of the buried channel is spaced from a top surface of the substrate and a bottom surface of the buried channel is closer to the top surface of the substrate than a bottom surface of the first source/drain feature;
dopants in the buried channel, wherein a highest concentration of the dopants is under the gate structure.

US Pat. No. 10,431,581

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) INTEGRATION WITH COMPOUND SEMICONDUCTOR DEVICES

QUALCOMM Incorporated, S...

1. A semiconductor device comprising:a substrate;
a well region disposed adjacent to the substrate;
a first fin disposed above the well region;
a second fin disposed above the substrate;
a gate region disposed adjacent to each of the first fin and the second fin;
at least one third fin disposed above the substrate;
a support layer disposed above the at least one third fin; and
a compound semiconductor device disposed above the support layer.

US Pat. No. 10,431,579

DISPLAY PANEL INCLUDING ELECTROSTATIC PROTECTION CIRCUIT, DRIVING METHOD OF THE SAME, AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A display panel, comprising:a plurality of pixel circuits arranged in a display area of the display panel, wherein the plurality of pixel circuits is arranged in rows and columns, the display area of the display panel comprises a first display area and a second display area arranged along a row direction, and an outer edge of the second display area extends stepwise along a column direction;
a plurality of data lines each extending along the column direction, wherein the plurality of data lines corresponds to a plurality of columns of the plurality of pixel circuits in one-to-one correspondence;
a plurality of signal line groups, wherein the plurality of signal line groups corresponds to a plurality of rows of the plurality of pixel circuits in one-to-one correspondence, and each of the plurality of signal line groups comprises a scan line and a light-emitting control signal line each extending along the row direction; and
a plurality of first electrostatic protection circuits, wherein the plurality of first electrostatic protection circuits corresponds and is connected to the data lines in the second display area in one-to-one correspondence, each of the plurality of first electrostatic protection circuits is electrically connected to a scan line and a light-emitting control signal line of a same signal line group, and each of the plurality of first electrostatic protection circuits is used to discharge static electricity on a data line connected to the first electrostatic protection circuit to the scan line or the light-emitting control signal line connected to the first electrostatic protection circuit.

US Pat. No. 10,431,578

ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes,
wherein an emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor; and
an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node,
wherein a gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor.

US Pat. No. 10,431,577

METHODS OF FORMING CIRCUIT-PROTECTION DEVICES

Micron Technology, Inc., ...

1. A method of forming a circuit-protection device, comprising:forming a dielectric having a first thickness and having a second thickness, greater than the first thickness, over a semiconductor;
forming the dielectric further having a third thickness greater than the second thickness, over the semiconductor;
forming a conductor over the dielectric;
patterning the conductor to retain a first portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness; and
patterning the conductor to further retain a second portion of the conductor over a portion of the dielectric having the third thickness;
wherein the retained first portion of the conductor defines a control gate of a first field-effect transistor of the circuit-protection device; and
wherein the retained second portion of the conductor defines a control gate of a second field-effect transistor of the circuit-protection device connected in series with the first field-effect transistor.

US Pat. No. 10,431,576

MEMORY CELL ARRAY AND METHOD OF MANUFACTURING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a memory cell array, the method comprising:generating a first set of tiles extending in a first direction, wherein the generating the first set of tiles comprises:
generating a first layout design of a first set of memory cells, each tile of the first set of tiles corresponds to the first layout design of the first set of memory cells, and each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction;
generating a second set of tiles, wherein the generating the second set of tiles comprises:
generating a second layout design of a second set of memory cells, each tile of the second set of tiles corresponds to the second layout design of the second set of memory cells, and each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction,
wherein each tile of the first set of tiles extends in a third direction different from the first direction and the second direction, the first set of tiles and the second set of tiles alternate with each other in the second direction, and each tile of the second set of tiles extends in the third direction, and at least one of the above generating operations is performed by a hardware processor, and the first layout design is stored in a non-transitory computer-readable medium; and
manufacturing the memory cell array based on at least the first layout design.

US Pat. No. 10,431,575

MULTI-DIE ARRAY DEVICE

NXP B.V., Eindhoven (NL)...

1. A method for fabricating a multi-die package, the method comprising:placing a plurality of flip chip dies and a plurality of splitter dies on a sacrificial carrier, each flip chip die and each splitter die positioned in an active side down orientation on the sacrificial carrier;
performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier, wherein the sacrificial carrier comprises test probe circuitry;
testing the plurality of flip chip dies and the plurality of splitter dies in a probe test using the test probe circuitry;
replacing any faulty flip chip dies and any faulty splitter dies as indicated by the testing;
overmolding the plurality of flip chip dies and the plurality of splitter dies on the sacrificial carrier to form a panel of embedded dies;
planarizing the panel of embedded dies to expose a back surface of each flip chip die and each splitter die in a back surface of the panel of embedded dies;
forming a metallization layer across the back surface of the panel of embedded dies that contacts the back surface of each flip chip die and each splitter die; and
removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and each splitter die is exposed in the front surface of the panel of embedded dies.

US Pat. No. 10,431,574

METHODS AND SYSTEMS FOR PACKAGING SEMICONDUCTOR DEVICES TO IMPROVE YIELD

Marvell World Trade Ltd.,...

1. A method for packaging semiconductor devices in a chamber, the method comprising:arranging a carrier substrate including a first semiconductor device and a second semiconductor device within the chamber;
flowing a molding compound into the chamber to cover surfaces of the first semiconductor device, the second semiconductor device, and the carrier substrate; and
flowing a forming gas into the chamber while curing the molding compound, wherein the forming gas includes a reactive gas configured to react with the first semiconductor device and the second semiconductor device during curing,
wherein the forming gas reforms broken bonds of the first semiconductor device and the second semiconductor device resulting from the curing.

US Pat. No. 10,431,573

METHOD FOR STACKING CORE AND UNCORE DIES HAVING LANDING SLOTS

Intel Corporation, Santa...

1. A method comprising:mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus;
vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die; and
vertically coupling a second cores die comprising a second plurality of cores on top of the uncore die, the cores of the second plurality spaced on the second cores die to correspond to a second subset of the landing slots on the uncore die different from the first subset, each of the cores on the second cores die having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the second cores die is vertically coupled on top of the uncore die with the first cores die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.

US Pat. No. 10,431,572

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a base comprising:
a first lead,
a second lead, and
a supporting member that supports the first lead and the second lead, and electrically isolates the first lead from the second lead;
a light emitting element mounted on an upper surface of the first lead;
a protection element mounted on an upper surface of the second lead, the protection element comprising a first terminal electrode and a second terminal electrode;
a wire including a first end and a second end, wherein the first end is connected to the upper surface of the first lead, and the second end is connected to the first terminal electrode of the protection element;
a resin frame located on an upper surface of the base, wherein the resin frame covers at least part of the protection element and surrounds the light emitting element and the first end of the wire;
a first resin member surrounded by the resin frame and covering the light emitting element and the first end of the wire; and
a second resin member covering the resin frame and the first resin member,
wherein part of the protection element is positioned outside the resin frame and covered by the second resin member.

US Pat. No. 10,431,571

OPTO-ELECTRONIC MODULES, IN PARTICULAR FLASH MODULES, AND METHOD FOR MANUFACTURING THE SAME

ams Sensors Singapore Pte...

1. An opto-electronic module comprising:a substrate member;
at least two emission members mounted on said substrate member;
at least one detecting member mounted on said substrate member;
an optics member comprising a first lens and a second lens; and
a spacer member arranged between said substrate member and said optics member, the spacer member abutting a first side of the substrate member and a first side of the optics member, and establishing a well-defined distance between the substrate member and the optics member, wherein the first side of the substrate member faces the first side of the optics member;
wherein the first lens is assigned to a first of said at least two emission members and the second lens is assigned to a second of said at least two emission members, said first lens and said first emission member being arranged such that light emitted from said first emission member traverses predominantly said first lens, and said second lens and said second emission member being arranged such that light emitted from said second emission member traverses predominantly said second lens, wherein a light intensity distribution of light emitted by said first emission member through said first lens leaving the opto-electronic module is different from a light intensity distribution of light emitted by said second emission member through said second lens leaving the opto-electronic module.

US Pat. No. 10,431,570

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYODA GOSEI CO., LTD., ...

1. A light emitting device, comprising:a substrate;
a plurality of light emitting elements disposed on the substrate;
a transparent resin embedded only in a space between the plurality of light emitting elements; and
a phosphor containing resin layer formed on the plurality of light emitting elements and the transparent resin,
wherein the transparent resin includes no phosphor,
wherein the phosphor containing resin layer comprises a plurality of regions comprising different kinds of phosphors,
wherein each one of the plurality of regions is disposed on each one of the plurality of light emitting elements,
wherein the plurality of light emitting elements are disposed on the substrate in a stacking direction of the phosphor containing resin layer on the plurality of light emitting elements, and
wherein, in the stacking direction, a bottom surface of the phosphor containing resin layer and a border of the plurality of regions of the phosphor containing resin layer are disposed on a top surface of the transparent resin.

US Pat. No. 10,431,569

METHOD OF TRANSFERRING MICRO DEVICES

PlayNitride Inc., Tainan...

1. A method of transferring micro devices, comprising:providing a carrier substrate, on which a buffer layer and a plurality of micro devices are disposed, the buffer layer being located between the carrier substrate and the micro devices, an upper surface of each of the micro devices is entirely in contact with the buffer layer, the micro devices being separated from one another and positioned on the carrier substrate through the buffer layer;
providing a bonding layer between the micro devices and a receiving substrate;
making a receiving substrate contact the micro devices on the carrier substrate;
after the micro devices contact the receiving substrate, reducing bonding force between at least a portion of the micro devices and the carrier substrate by melting the buffer layer through raising a temperature of the carrier substrate; and
liquefying the bonding layer by raising a temperature of the receiving substrate such that adhesive force between the at least a portion of the micro devices and the bonding layer is greater than bonding force between the at least a portion of the micro devices and the carrier substrate, so that the at least a portion of the micro devices are released from the carrier substrate and transferred onto the receiving substrate, wherein a number of the at least a portion of the micro devices is in a range from 1000 to 2000000.

US Pat. No. 10,431,568

LIGHT EMITTING DIODES, COMPONENTS AND RELATED METHODS

Cree, Inc., Durham, NC (...

1. A light emitting diode (LED) device comprising:a submount comprising an upper surface and a bottom surface;
a plurality of LEDs disposed on the upper surface of the submount, the plurality of LEDs each comprising an upper surface of a diode and one or more sides, the LEDs being spaced apart with a gap between the LEDs;
an encapsulant comprising an upper curved surface and one or more planar side surfaces, the upper curved surface having a radius curvature that is greater than half a length or width of the submount, wherein the one or more planar side surfaces comprise truncated sections of the upper curved surface so that the encapsulant does not overhang an outermost edge of the submount, at least a portion of each of the one or more planar side surfaces extending to a respective outermost edge of the upper surface of the submount; and
a phosphor layer disposed on the upper surface of the diodes, on one or more sides of the plurality of LEDs and in the gap between the LEDs,
wherein the gap between the LEDs ranges from about 1 to about 300 micrometers (?m),
wherein a ratio of a particle size of phosphor in the gap to a width of the gap between the LEDs is approximately 30% to approximately 75%,
wherein the device, based on the gap between the LEDs and the ratio of the particle size of phosphor in the gap to the width of the gap, is configured to produce an emission pattern devoid of a deadspot.

US Pat. No. 10,431,567

WHITE CERAMIC LED PACKAGE

CREE, INC., Durham, NC (...

1. An emitter package, comprising:a casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of light emitting devices (LEDs) on said first set of bond pads, with said light emitting devices and portions of said bond pads exposed through said cavity;
a plurality of electrodes at least on the bottom surface of said casing; and
through-holes integral to each of said bond pads, wherein said through-holes are embedded within said casing and extend into each of said bond pads and said electrodes to provide electrical paths between said bond pads and said electrodes;
wherein at least one of said chip carrier parts or connection parts is at least partially defined by an indentation.

US Pat. No. 10,431,565

WAFER EDGE PARTIAL DIE ENGINEERED FOR STACKED DIE YIELD

XILINX, INC., San Jose, ...

1. A method for forming a stacked wafer assembly, the method comprising:contacting an exposed dielectric material layer of a first wafer to an exposed dielectric material layer of a second wafer;
pressing the first wafer against the second wafer to cause the dielectric material layers to create a bond between the first wafer and the second wafer; and
forming electrical connections between bond pads formed over a first inductor of a partial die residing on the first wafer and bond pads formed on a partial die residing on the second wafer; and
forming electrical connections between bond pads of a full die residing on the first wafer and bond pads formed on a full die residing on the second wafer, wherein the full die and the partial die are structurally different.

US Pat. No. 10,431,564

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE STRUCTURE

MediaTek Inc., Hsin-Chu ...

1. A chip package structure, comprising:a first chip package over a printed circuit board;
a second chip package over the first chip package;
a plurality of conductive bumps extending between a substrate of the first chip package and the printed circuit board;
a plurality of thermal conductive elements extending between the substrate of the first chip package and the printed circuit board, each of the thermally conductive elements being formed of metal foil and exhibiting a sidewall perpendicular to the printed circuit board;
a first bonding layer between the plurality of thermal conductive elements and the first chip package; and
a second bonding layer between the plurality of thermal conductive elements and the printed circuit board;
wherein each of the thermal conductive elements has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps,
wherein the thermal conductive elements are connected to conductive pads, the conductive pads being positioned under a source of heat such that the thermally conductive elements connected thereto dissipate heat from the source of heat, with at least some of the thermal conductive elements exhibiting different shapes or sizes.

US Pat. No. 10,431,563

CARRIER AND INTEGRATED MEMORY

International Business Ma...

1. A method of integrated circuit (IC) carrier fabrication comprising:joining a memory, a heat spreader, and a IC chip carrier with a dielectric material such that the heat spreader contacts a sidewall of the memory and such that a contact surface of the memory and an IC chip facing surface of the dielectric material are coplanar with a IC chip facing surface of the carrier;
forming a vertical interconnect access (VIA) within the heat spreader and within the dielectric material from the IC chip facing surface of the dielectric material to a system facing surface of the dielectric material;
forming a first carrier interconnect upon the contact surface of the memory, upon the IC chip facing surface of the dielectric material, and upon the IC chip facing surface of the carrier, the first carrier interconnect electrically connecting a signal contact of the memory and a wiring line within the IC chip carrier; and
forming a second carrier interconnect upon the IC chip facing surface of the dielectric material, the second carrier interconnect electrically connecting a power or ground contact of the memory and the VIA.

US Pat. No. 10,431,562

BACK SIDE METALLIZATION

Advanced Micro Devices, I...

1. A method of forming a metallization structure on a back side of a silicon wafer substrate, the silicon wafer substrate including a plurality of integrated circuits formed on a front side of the silicon wafer substrate, the method comprising:forming a first adhesion layer on the back side of the silicon wafer substrate, the first adhesion layer including at least one of: silicon dioxide and silicon nitride;
forming a first barrier layer including titanium metal over the first adhesion layer;
forming a second barrier layer including nickel over the first barrier layer; and
forming a second adhesion layer over the second barrier layer, the second adhesion layer including at least one of: silver, gold, and tin.

US Pat. No. 10,431,561

PRE-CONDUCTIVE ARRAY DISPOSED ON TARGET CIRCUIT SUBSTRATE AND CONDUCTIVE STRUCTURE ARRAY THEREOF

ULTRA DISPLAY TECHNOLOGY ...

1. A pre-conductive array disposed on a target circuit substrate, comprising:a plurality of conductive electrode groups disposed on the target circuit substrate, wherein a first distance is provided between every two of the conductive electrode groups, and each of the conductive electrode groups comprises at least a pair of conductive electrodes; and
at least a conductive particle dispose on each of the conductive electrodes of a part or all of the conductive electrode groups;
wherein the conductive particle and the corresponding pair of the conductive electrodes form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array;
wherein a first density is defined to represent a number of the conductive particles within a unit area of each of the pre-conductive structures, a second density is defined to represent a number of the conductive particles within a unit area between two of the pre-conductive structures, and the first density is greater than the second density.

US Pat. No. 10,431,560

MOLDED SEMICONDUCTOR PACKAGE HAVING AN OPTICAL INSPECTION FEATURE

Infineon Technologies AG,...

1. A molded semiconductor package, comprising:a mold compound having a first main surface, a second main surface opposite the main surface, and an edge extending between the first and the second main surfaces;
a semiconductor die embedded in the mold compound; and
a plurality of metal pads embedded in the mold compound and electrically connected to the semiconductor die,
wherein the metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound,
wherein the metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound,
wherein the entire side face of each metal pad disposed around the periphery of the molded package is plated and recessed inward from the edge of the mold compound.

US Pat. No. 10,431,559

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method of manufacturing a semiconductor structure, comprising:providing a carrier including a recess;
disposing a second dielectric layer of a first passivation over the carrier and filling the recess;
providing a substrate including a pad and a first dielectric layer of the first passivation disposed thereon, wherein the pad is covered with the first dielectric layer before bonding the first dielectric layer with the second dielectric layer;
bonding the first dielectric layer with the second dielectric layer;
removing the carrier;
removing a portion of the first passivation to expose a portion of the pad;
disposing a conductive layer over the first passivation and the portion of the pad;
disposing a second passivation over the conductive layer,
wherein the first passivation includes a protrusion protruded from the first passivation and away from the substrate, and the conductive layer disposed over the protrusion is exposed from the second passivation.

US Pat. No. 10,431,557

SECURE SEMICONDUCTOR CHIP BY PIEZOELECTRICITY

INTERNATIONAL BUSINESS MA...

1. An apparatus, comprising:a power source; and
a semiconductor chip comprising at least one circuit and a pass transistor that electrically couples the power source and the at least one circuit, wherein the pass transistor comprises a piezoelectric gate comprising a piezoelectric material that produces a voltage that causes the pass transistor to remain in an on-state based on application of a mechanical force to the piezoelectric gate.

US Pat. No. 10,431,555

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

DISCO CORPORATION, Tokyo...

12. A method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin, comprising the steps of:preparing a wiring board having a plurality of mounts for mounting semiconductor chips thereon, the mounts being disposed in respective areas demarcated on an upper surface of a wiring board by a plurality of projected dicing lines which cross each other, upstanding encircling walls disposed between said mounts and said projected dicing lines in surrounding relation to said mounts individually, and side-surface shield layers for blocking electromagnetic waves, disposed individually in said upstanding encircling walls in surrounding relation to said mounts and extending in thicknesswise directions of said upstanding encircling walls;
mounting the semiconductor chips individually on said mounts on said wiring hoard;
supplying synthetic resin to spaces surrounded by said upstanding encircling walls over the semiconductor chips mounted on said mounts on said wiring board to seal said semiconductor chips, thereby producing a sealed board;
after said sealed board has been produced, dividing said sealed board along said projected dicing lines into individual semiconductor packages;
after said sealed board has been produced, forming an upper-surface shield layer for blocking electromagnetic waves on upper surfaces of the sealing synthetic resin of said semiconductor packages; and
after said sealed board has been produced, removing the sealing synthetic resin supplied to upper surfaces of said upstanding encircling walls along the side-surface shield layers, thereby exposing tip ends of the side-surface shield layers disposed individually in said upstanding encircling walls.

US Pat. No. 10,431,554

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier;
an electronic component disposed over a top surface of the carrier;
a package body disposed over the top surface of the carrier and covering the electronic component; and
a shield layer, comprising a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer,
wherein the first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer,
wherein a permeability of the first electrically conductive layer is lower than each of a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.

US Pat. No. 10,431,553

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a semiconductor substrate having a primary surface;
an insulator filling a recess in the primary surface;
a semiconductor element disposed on the primary surface, the semiconductor element being sandwiched by the insulator in a plan view; and
an alignment mark overlapping with the insulator in a plan view,
wherein a distance between a bottom surface and a top surface of the insulator that sandwiches the semiconductor element in a plan view is equal to a distance between a bottom surface and a top surface of the insulator overlapping the alignment mark in a plan view.

US Pat. No. 10,431,552

DISPLAY PANEL

HannStar Display Corporat...

1. A display panel having a display area and a non-display area, wherein the display panel comprises:a first substrate, wherein a metal layer is disposed on the first substrate, the metal layer has a plurality of first alignment patterns in the non-display area, and each of the first alignment patterns comprises a first portion and a second portion; and
a second substrate, wherein a light shielding layer is disposed on the second substrate, the light shielding layer has a plurality of second alignment patterns in the non-display area, and each of the second alignment patterns comprises a third portion and a fourth portion,
wherein the second alignment patterns respectively correspond to the first alignment patterns, and the third portions respectively correspond to the first portions, and the fourth portions respectively correspond to the second portions,
wherein there is a first length difference between a length of each of the first portions along a first direction and a length of the corresponding third portion along the first direction, and at least two of the first length differences are different,
wherein there is a second length difference between a length of each of the second portions along a second direction and a length of the corresponding fourth portion along the second direction, and at least two of the second length differences are different,
wherein the light shielding layer has a plurality of openings in the non-display area, and one of the openings encompasses one of the first alignment patterns and one of the second alignment patterns.

US Pat. No. 10,431,551

VISUAL IDENTIFICATION OF SEMICONDUCTOR DIES

TEXAS INSTRUMENTS INCORPO...

1. An electronic device, comprising:a die; and
a package surrounding the die, wherein the electronic device includes a unique visual identification mark, wherein a first character of a set of characters in the unique visual identification mark includes at least one line that connects two adjacent sides of a bond pad of the die, wherein the unique visual identification mark encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

US Pat. No. 10,431,549

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A semiconductor package, comprising:a stacked-die structure comprising:
a first semiconductor die comprising a first active surface;
a circuit layer disposed on and not extending laterally beyond the first active surface of the first semiconductor die;
a second semiconductor die electrically connected to the first semiconductor die through the circuit layer and comprising a second active surface facing towards the first active surface of the first semiconductor die;
a plurality of conductive features disposed on the circuit layer and the first semiconductor die and electrically connected to the first semiconductor die and the second semiconductor die, wherein
a portion of the plurality of conductive features laterally surrounds the second semiconductor die, and
the plurality of conductive features comprise a first coupling structure disposed between the first semiconductor die and the second semiconductor die and a second coupling structure surrounding the first coupling structure; and
a first encapsulant encapsulating the second semiconductor die and the plurality of conductive features;
a second encapsulant laterally encapsulating the stacked-die structure, wherein a second back surface of the second semiconductor die opposite to the second active surface and a top surface of the second coupling structure are coplanar with a top surface of the first encapsulant and a top surface of the second encapsulant; and
a redistribution layer disposed on the second encapsulant and the staked-die structure, wherein
the redistribution layer is electrically connected to the staked-die structure, and
the second coupling structure is electrically connected to the first semiconductor die and the redistribution layer.

US Pat. No. 10,431,548

ELECTRONIC COMPONENT MODULE AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. An electronic device module, comprising:a first substrate;
electronic devices mounted on the first substrate;
a second substrate coupled to a lower surface of the first substrate, the second substrate comprising a device accommodating portion;
a sealing portion configured to seal an electronic device in the device accommodating portion, and comprising a lower surface sealing portion configured to cover a lower surface of the second substrate; and
an external connection terminal bonded to an electrode pad disposed in a lower surface of the second substrate, wherein side surfaces of the electrode pad are embedded by the sealing portion,
wherein bonding surfaces of the electrode pad and the external connection terminal are disposed on a same plane as a lower surface of the lower surface sealing portion.

US Pat. No. 10,431,547

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a package substrate;
a first semiconductor chip disposed on the package substrate, the first semiconductor chip including a first surface and a second surface opposite to each other;
a plurality of first connection terminals disposed on the first surface of the first semiconductor chip and in contact with an upper surface of the package substrate;
a second semiconductor chip overlying the second surface of the first semiconductor chip, the second semiconductor chip including a third surface and a fourth surface opposite to each other; and
a plurality of second connection terminals disposed on the third surface of the second semiconductor chip and in contact with the second surface of the first semiconductor chip,
wherein an absolute value between a first area which is a sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate and a second area which is a sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip is equal to or less than about 0.3 of the first area.

US Pat. No. 10,431,546

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

CANON KABUSHIKI KAISHA, ...

1. A method for manufacturing a laminate, the method comprising:preparing a first wafer and a second wafer, the first wafer comprising a first semiconductor substrate and a first wiring structure on the first semiconductor substrate, the second wafer comprising a second semiconductor substrate and a second wiring structure on the second semiconductor substrate, the first wiring structure and the second wiring structure are arranged between the first substrate and the second substrate, the first wiring structure including a first plurality of conductive lines, and the second wiring structure including a second plurality of conductive lines; and
forming a connecting member configured to electrically connect a first conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines,
wherein the forming of the connecting member comprises:forming a first hole and a second hole each of which penetrates at least the first semiconductor substrate so that a part of the first semiconductor substrate is arranged between the first hole and the second hole, at least one of the first conductive line and the second conductive line exposes to the first hole, and at least the one of the first conductive line and the second conductive line exposes to the second hole; and disposing a conductive material in the first hole and the second hole.

US Pat. No. 10,431,545

CROSS-CONNECTED MULTI-CHIP MODULES COUPLED BY SILICON BENT-BRIDGE INTERCONNECTS AND METHODS OF ASSEMBLING SAME

Intel IP Corporation, Sa...

1. A multi-chip module, comprising:a central component;
a first component, wherein the first component is coupled to the central component by a first silicon bent-bridge interconnect; and
a subsequent component, wherein the subsequent component is coupled to the central component by a subsequent silicon-bridge interconnect wherein the first silicon bent-bridge interconnect and the subsequent silicon bent-bridge interconnect are torsioned to form an overall helical form factor.

US Pat. No. 10,431,542

LOW RESISTANCE SEED ENHANCEMENT SPACERS FOR VOIDLESS INTERCONNECT STRUCTURES

International Business Ma...

1. A structure comprising a first interconnect level, the first interconnect level comprising:a first interconnect dielectric material layer containing a first opening having vertical sidewalls and a bottom wall;
a first diffusion barrier liner located in the first opening and lining the vertical sidewalls and the bottom wall of the first opening;
a first seed enhancement spacer directly contacting each inner sidewall of the first diffusion barrier liner and comprising a metal or metal alloy that facilitates movement of an interconnect metal or metal alloy during a reflow anneal process, and is selected from the group consisting of at least one of ruthenium, rhodium, iridium, osmium and cobalt; and
a first interconnect metal or metal alloy structure directly contacting inner sidewalls of each first seed enhancement spacer and directly contacting a horizontal portion of the first diffusion barrier liner that is located on the bottom wall of the first opening.

US Pat. No. 10,431,541

SEMICONDUCTOR DEVICE, LAYOUT PATTERN AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:an interconnect structure, made of conductive material, and comprising a first interconnect portion and a second interconnect portion, wherein the second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion; and
a first conductive line, arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure, wherein a distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end, and the first conductive line is arranged within the first interconnect portion and formed between the first end and the second end.

US Pat. No. 10,431,540

METAL-OXIDE-METAL CAPACITOR WITH REDUCED PARASITIC CAPACITANCE

QUALCOMM Incorporated, S...

1. A semiconductor device, comprising:a semiconductor substrate;
a capacitor; and
a magnetic material layer between the semiconductor substrate and the capacitor in which the magnetic material layer includes a first surface on the semiconductor substrate and a second surface opposite the first surface, in which a perimeter of the capacitor is within a perimeter of the second surface of the magnetic material layer.

US Pat. No. 10,431,538

TRANSISTOR PACKAGES

Hamilton Sundstrand Corpo...

1. A transistor package comprising:a die case having a top surface and a bottom surface opposite from the top surface;
a source bus tab extending from a first side of the die case, wherein a portion of the source bus tab that extends from the first side is spaced apart from the top surface and the bottom surface in a direction perpendicular to the top surface;
a drain bus tab extending from a second side of the die case opposite from the first side, wherein a portion of the drain bus tab that extends from the second side is spaced apart from the top surface and the bottom surface in the direction perpendicular to the top surface; and
a gate extending from a third side of the die case, wherein the gate includes a first element and a second element, wherein the first element of the gate extends in a first direction from the die case and the second element of the gate extends in a second direction from the first element, wherein the third side of the die case is perpendicular to both the first side of the die case and the second side of the die case, wherein a portion of the gate that extends from the third side is spaced apart from the top surface and the bottom surface in the direction perpendicular to the top surface, and wherein the portions of the source bus tab and the drain bus tab that extend from the die case are spaced apart from an exterior surface of the third side in a direction perpendicular to the exterior surface of the third side.

US Pat. No. 10,431,537

ELECTROMIGRATION RESISTANT AND PROFILE CONSISTENT CONTACT ARRAYS

Intel Corporation, Santa...

1. A package assembly comprising:a substrate extending from a first substrate end to a second substrate end, the substrate includes a plurality of conductive traces;
one or more die coupled along the substrate, at least a first die of the one or more die includes a first array of contacts; and
a plurality of via assemblies interposed between at least the first array of contacts and the plurality of conductive traces, and each via assembly between the first array and the plurality of conductive traces includes:
a base pad in communication with a conductive trace of the plurality of conductive traces, the base pad includes at least a first conductive material,
a cap in communication with a contact of the first array of contacts, the cap includes at least a second conductive material different from the first conductive material, and
an electromigration resistant via within a via passage between the base pad and the cap, the electromigration resistant via is configured to isolate each of the base pad and the cap from intermetallic compound growth and includes a third conductive material different from the first and second conductive materials.

US Pat. No. 10,431,536

INTERPOSER SUBSTRATE AND SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate;
a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate; and
an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip,
wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess in a region overlapped with the lower semiconductor chip, and
wherein the dummy wiring layer is electrically floating.

US Pat. No. 10,431,535

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. A method for fabricating an electronic package, comprising:providing a packaging substrate having a circuit structure and an antenna structure, wherein the circuit structure has a first side and a second side opposite to the first side, the circuit structure comprises at least one dielectric layer and a circuit layer formed on the dielectric layer, and the antenna structure is in contact with the first side of the circuit structure, without an antenna on the second side of the circuit structure; and
disposing at least one electronic component on the second side of the circuit structure and electrically connecting the electronic component to the second side of the circuit structure, wherein the electronic component is a semiconductor chip, wherein the circuit structure further comprises a core layer.

US Pat. No. 10,431,534

PACKAGE WITH SUPPORT STRUCTURE

NXP USA, Inc., Austin, T...

1. A packaged semiconductor device comprising:a package body comprising a semiconductor die;
a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure;
a plurality of external connections attached to the plurality of contact pads; and
a support structure comprising an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.

US Pat. No. 10,431,533

CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS

ATI Technologies ULC, Ma...

1. A method of manufacturing, comprising:forming a solder mask on a circuit board with a first opening having a sidewall;
forming a solder interconnect pad in the first opening; and
whereby the sidewall sets the lateral extent of the solder interconnect pad during the formation of the solder interconnect pad.

US Pat. No. 10,431,532

SEMICONDUCTOR DEVICE WITH NOTCHED MAIN LEAD

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a main lead on which the semiconductor element is disposed;
a first auxiliary lead and a second auxiliary lead, the first auxiliary lead and the second auxiliary lead each being electrically connected to the semiconductor element;
a first wire electrically connecting the semiconductor element to the first auxiliary lead;
a second wire electrically connecting the semiconductor element to the second auxiliary lead; and
a resin package covering the semiconductor element, the main lead, the first auxiliary lead, and the second auxiliary lead,
wherein the main lead includes a main full thickness part and a main eave part that is smaller in size in a thickness direction of the semiconductor element than the main full thickness part,
the semiconductor element overlaps with each of the main full thickness part and the main eave part in plan view,
the main eave part includes an end face that faces the first auxiliary lead and the second auxiliary lead and that is formed with a notch recessed toward a center of the main lead in plan view,
the first auxiliary lead includes a first auxiliary full thickness part and a first auxiliary eave part that is smaller in size in the thickness direction of the semiconductor element than the first auxiliary full thickness part,
the second auxiliary lead includes a second auxiliary full thickness part and a second auxiliary eave part that is smaller in size in the thickness direction of the semiconductor element than the second auxiliary full thickness part,
the first wire is bonded at a position overlapping with the first auxiliary full thickness part in plan view, and the second wire is bonded at a position overlapping with the second auxiliary full thickness part in plan view,
the first wire has an end bonded to the semiconductor element, the end of the first wire being bonded to the semiconductor element at a position that overlaps with the main full thickness part in plan view,
the main eave part is formed with a pair of main lateral connecting parts that project in mutually opposite directions from a main body of the main eave part, the main lateral connecting parts including respective front faces and respective back faces opposite to the respective front faces, the front faces being flush with the end face of the main eave part, and
the second wire has an end bonded to the semiconductor element, the end of the second wire being bonded to the semiconductor element at a position that overlaps with the main eave part in plan view and is located between the main full thickness part and an imaginary straight line connecting the back faces of the main lateral connecting parts in plan view.

US Pat. No. 10,431,531

SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method comprising:electrically connecting one or more leadfingers of a leadframe to a semiconductor die;
encapsulating the semiconductor die, a removable tie, and a support paddle with an encapsulant, wherein the removable tie connects the support paddle to the leadframe, and wherein the support paddle is attached to the semiconductor die; and
removing a frame portion of the leadframe and at least portion of the removable tie from the encapsulated semiconductor die and support paddle.

US Pat. No. 10,431,530

POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

MagnaChip Semiconductor, ...

1. A method of manufacturing a power semiconductor module, the method comprising:preparing a Direct Bonded Copper (DBC) substrate comprising a metal pattern;
forming the power semiconductor module by wire bonding the metal pattern of the DBC substrate and an electrode of a power semiconductor element;
testing whether the power semiconductor module is defective;
coupling the DBC substrate to a base plate; and
coupling the DBC substrate and a lead frame,
wherein the lead frame comprises a first body connected to a first terminal, a second body connected to a second terminal, and third and fourth bodies connected to a third common terminal having a length larger than a length of the first terminal or the second terminal.

US Pat. No. 10,431,528

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor element; and
a leadframe on which the semiconductor element is mounted,
the leadframe including a die pad on which the semiconductor element is mounted, a first suspension lead, a second suspension lead, and a frame, a main surface of the die pad and a main surface of the frame being located on different planes, the die pad and the frame being connected to each other by the first and second suspension leads,
a first boundary line between the first suspension lead and the die pad running on a straight line different from a second boundary line between the second suspension lead and the die pad,
a third boundary line between the first suspension lead and the frame running on a straight line different from a fourth boundary line between the second suspension lead and the frame.

US Pat. No. 10,431,527

SEMICONDUCTOR DEVICE WITH ISLAND AND ASSOCIATED LEADS

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a resin package having a first corner portion, a second corner portion, a third corner portion and a fourth corner portion, and a package line which connects the first and the second corner portions;
an island having an exposed portion which is partly exposed from the resin package in a bottom view of the resin package, the exposed portion having a first exposed corner portion, a second exposed corner portion, a third exposed corner portion and a fourth exposed corner portion;
a semiconductor chip disposed on a surface of the island;
a first lead disposed in a vicinity of the first corner portion in the bottom view of the resin package, the first lead having a short side and a long side, both of the short side and the long side of the first lead being substantially parallel to a first exposed diagonal line imagined by connecting the first and third corner portions;
a second lead disposed in a vicinity of the second corner portion in the bottom view of the resin package, the second lead having a short side and a long side, both of the short side and the long side of the second lead being substantially parallel to the first exposed diagonal line;
a third lead disposed in a vicinity of the third corner portion in the bottom view of the resin package, the third lead having a short side and a long side, both of the short side and the long side of the third lead being substantially parallel to the first exposed diagonal line; and
a fourth lead disposed in a vicinity of the fourth corner portion in the bottom view of the resin package, the fourth lead having a short side and a long side, both of the short side and the long side of the fourth lead being substantially parallel to the first exposed diagonal line, wherein
a distance between the first exposed corner portion and the package line is longer than a length of the short side of the first lead; and
the distance between the first exposed corner portion and the package line is shorter than a length of the long side of the first lead.

US Pat. No. 10,431,525

BOND-OVER-ACTIVE CIRCUITY GALLIUM NITRIDE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a first layer with a plurality of cells, each cell comprising a drain finger, a source finger and a gate ring; and
a second layer comprising a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad;
wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer;
wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact; and
wherein one of the drain pad or the source pad is positioned over one of the drain finger or the source finger.

US Pat. No. 10,431,523

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein
a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and
a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

US Pat. No. 10,431,522

THERMAL INTERFACE MATERIAL LAYER AND PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor package device having a package-on-package (PoP) structure, the semiconductor package device comprising:a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted on the lower package substrate;
an upper semiconductor package including an upper package substrate and a first upper semiconductor chip on the upper package substrate;
a connection solder bump between the upper package substrate and the lower package substrate, the connection solder bump electrically connecting the upper semiconductor package and the lower semiconductor package;
a thermal conductive material between the lower semiconductor package and the upper semiconductor package, the thermal conductive material including a resin layer and filler particles distributed in the resin layer, the filler particles include a plurality of filler particles including at least two layers; and
a lower mold layer covering a sidewall of the lower semiconductor chip, and not covering a top surface of the lower semiconductor chip.

US Pat. No. 10,431,520

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a package portion;
a metal base which is housed in the package portion and is exposed at a lower surface of the package portion;
a semiconductor chip which is housed in the package portion and is placed above the metal base; and
a frame portion provided to surround a penetration space penetrating the package portion, wherein
a lower end of the frame portion protrudes below the lower surface of the package portion and a lower surface of the metal base, and
the frame portion has a wider portion outside the package portion, the wider portion having a greater width than a portion inserted in the penetration space of the package portion.

US Pat. No. 10,431,519

CARRIER REMOVAL BY USE OF MULTILAYER FOIL

Micron Technology, Inc., ...

1. A semiconductor device assembly comprising:a semiconductor device having a first side and a second side;
a substrate;
a foil layer attached to a surface of the substrate;
a release layer attached to the foil layer, the foil layer positioned between the release layer and the surface of the substrate; and
a layer of adhesive configured to connect the semiconductor device to the substrate, the layer of adhesive positioned between the first side of the semiconductor device and the release layer, wherein upon the application of an energy pulse to the foil layer, the foil layer is configured to generate heat to cause the release layer to selectively release the substrate from the adhesive layer, wherein the foil layer is a multilayer foil comprised of alternating layers of two materials.

US Pat. No. 10,431,518

RFIC DEVICE AND METHOD OF FABRICATING SAME

NINGBO SEMICONDUCTOR INTE...

1. A radio frequency integrated circuit (RFIC) device, comprising:a first semiconductor layer having a first surface and a second surface;
a first dielectric layer on the first surface of the first semiconductor layer;
a semiconductor component within the first semiconductor layer and the first dielectric layer, the semiconductor component including at least one transistor;
a second dielectric layer on the second surface of the first semiconductor layer; and
a sheet-like heat sink, formed of a material at least including a dielectric material on a surface of the second dielectric layer opposite to the first semiconductor layer and configured to dissipate heat from the semiconductor component, wherein the sheet-like heat sink includes a first heat sink sheet arranged in a vertical projection area of the at least one transistor.

US Pat. No. 10,431,517

ARRANGEMENT AND THERMAL MANAGEMENT OF 3D STACKED DIES

Advanced Micro Devices, I...

1. A semiconductor chip device, comprising:a first semiconductor chip having a side and a floor plan with a high heat producing area and a low heat producing area;
at least one second semiconductor chip stacked on the side and on the low heat producing area; and
means for thermally contacting the side and transferring heat from the high heat producing area.

US Pat. No. 10,431,516

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip having a passivation film;
a stress relieving layer provided over the passivation film for absorbing and relieving an externally applied stress; and
a sealing resin layer provided on the stress relieving layer for sealing a front side of the semiconductor chip, wherein:
the semiconductor chip has a groove formed therein from a front surface thereof at a peripheral edge portion of the front surface,
in a sectional view of the semiconductor device perpendicular to the groove, a portion of the front surface separates the groove from one side surface of the semiconductor device that is closer to the groove than another side surface of the semiconductor device,
the portion of the front surface has a first portion and a second portion facing the first portion across the groove, and
the sealing resin layer has a side surface which is substantially flush with a side surface of the stress relieving layer.

US Pat. No. 10,431,514

SEMICONDUCTOR PACKAGES HAVING DUAL ENCAPSULATION MATERIAL

STMicroelectronics (Malta...

1. A semiconductor package comprising:a substrate having a center portion and a perimeter portion, the perimeter portion having a surface and first and second thicknesses exposed at the surface, wherein the first and second thicknesses are different from each other, at least one of the first and second thicknesses being less than a third thickness of the center portion;
a first die of semiconductor material mounted to the substrate at the center portion;
a transparent encapsulation material on the center portion of the substrate and around the first die; and
an opaque encapsulation material on the perimeter portion of the substrate,
wherein the surface of the perimeter portion is coplanar with an outer surface of the opaque encapsulation material.

US Pat. No. 10,431,513

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Micron Technology, Inc., ...

12. A stacked microelectronic device, comprising:a first microelectronic device, including:
a first lower substrate with a footprint,
a first microelectronic die carried on the first lower substrate and electrically coupled to the first lower substrate by a first plurality of wirebonds, and
a first upper substrate disposed over the first microelectronic die and electrically coupled to the first lower substrate by a second plurality of wirebonds,
wherein the first microelectronic die includes a first perimeter array of bond-pads on an upper side thereof, and wherein the first upper substrate is positioned inboard of the first perimeter array; and
a second microelectronic device disposed over the first microelectronic device, the second microelectronic device including:
a second lower substrate with the footprint,
a second microelectronic die carried on the second lower substrate and electrically coupled to the second lower substrate by a third plurality of wirebonds, and
a second upper substrate disposed over the second microelectronic die and electrically coupled to the second lower substrate by a fourth plurality of wirebonds,
wherein the second microelectronic die includes a second perimeter array of bond-pads on an upper side thereof, and wherein the second upper substrate is positioned inboard of the second perimeter array;
wherein the second lower substrate is electrically coupled to the first upper substrate by a plurality of solder connections.

US Pat. No. 10,431,512

SEMICONDUCTOR PACKAGE WITH BARRIER FOR RADIO FREQUENCY ABSORBER

Analog Devices, Inc., No...

1. A semiconductor package comprising:a substrate;
a frame;
an integrated device die mounted to the substrate, the integrated device die comprising a transmitter die; and
a lid comprising a ventilation hole, the lid mounted to at least one of the frame and substrate over the integrated device die, wherein the lid, frame, and substrate at least partly define a cavity in which the integrated device die is disposed, the lid comprising a compartment formed therein, the compartment separated from the cavity by a partition,
wherein the ventilation hole provides fluid communication between the compartment and the outside environs.

US Pat. No. 10,431,511

POWER AMPLIFIER WITH RF STRUCTURE

QUALCOMM Incorporated, S...

1. A shield structure, comprising:a first substrate;
a second substrate located above the first substrate;
a power amplifier on the first substrate and configured to output a drive current;
a first inductor embedded in the first substrate and coupled to the power amplifier;
a second inductor embedded in the second substrate and coupled to the first inductor, the first inductor and the second inductor configured to match an impedance of the power amplifier; and
a ground wall surrounding the first inductor and the second inductor, the ground wall configured to isolate a magnetic field produced by the first inductor and the second inductor.

US Pat. No. 10,431,510

HERMETIC LID SEAL PRINTING METHOD

Global Circuit Innovation...

1. A method, comprising:securing a die into a cavity of a hermetic package base;
providing one or more bond connections to the die;
placing a hermetic package lid on the package base;
3D printing, by a 3D printer, hermetic lid seal material to a joint between the hermetic package base and the hermetic package lid, at a temperature at or below 100 degrees Celsius; and
3D printing, by the 3D printer, a hermetic overcoat over the hermetic lid seal material in order to completely cover the hermetic lid seal material, a thickness of the hermetic overcoat less than a thickness of the hermetic lid seal material.

US Pat. No. 10,431,508

METHODS AND SYSTEMS TO IMPROVE PRINTED ELECTRICAL COMPONENTS AND FOR INTEGRATION IN CIRCUITS

VQ RESEARCH, INC., Palo ...

1. An integrated circuit, comprising:a circuit die;
a lid covering a top surface of the circuit die;
a ceramic matrix packaging, and
wherein the ceramic matrix packaging comprises at least one of an embedded resistor, capacitor, inductor, and multi-property device disposed within the ceramic matrix packaging,
wherein formation of the integrated circuit is specified by successive additions of a plurality of voxels of material through a deposit of droplets, and
wherein the at least one of an embedded resistor, capacitor, inductor, and multi-property device is oriented at an angle to minimize a parasitic effect.

US Pat. No. 10,431,506

METHOD OF PROCESSING SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of processing a substrate, comprising:forming a mask layer on the substrate having an etched region and a non-etched region defined by the etched region;
inspecting the mask layer to detect defects in the mask layer using Raman spectrum analysis;
determining whether the defects are on the etched region or the non-etched region if the defects are in the mask layer;
removing the mask layer on the etched region and the non-etched region of the substrate if the defects are on the non-etched region; and
etching a portion of the mask layer on the etched region to form a mask pattern on the non-etched region if the defects are on the etched region.

US Pat. No. 10,431,505

METHOD OF INSPECTING SURFACE HAVING A MINUTE PATTERN BASED ON DETECTING LIGHT REFLECTED FROM METAL LAYER ON THE SURFACE

Samsung Electronics Co., ...

1. A method, comprising:forming a metal layer on a surface of an inspection target device, the inspection target device including a pattern, such that the metal layer is formed on the pattern and an outer surface of the metal layer is distal to the surface of the inspection target device;
emitting light incident on the outer surface of the metal layer, and adjusting the emitted light to be incident to the outer surface of the metal layer and normal to the outer surface of the metal layer;
detecting a spectrum of the light reflected from the outer surface of the metal layer; and
generating, based on the detected spectrum, information associated with a structural characteristic of the pattern formed on the surface of the inspection target device,
wherein the pattern includes a plurality of patterns, the patterns being spaced apart according to a particular period,
wherein the generating includes measuring a width of at least one pattern of the plurality of patterns and a distance between adjacent patterns, based on a material of the metal layer.

US Pat. No. 10,431,504

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY BONDING A SEMICONDUCTOR DISK ON A BASE SUBSTRATE, COMPOSITE WAFER AND SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A method of manufacturing semiconductor devices, the method comprising:attaching, by adhesion bonding, a semiconductor disk of a first crystalline material on a process surface of a base substrate, wherein the first crystalline material has a first lattice system and wherein a bonding layer is formed between the semiconductor disk and the base substrate; and
forming by epitaxy a second semiconductor layer of a second crystalline material with a second, different lattice system on a first semiconductor layer formed from the semiconductor disk,
wherein the attaching, by adhesion bonding uses ceramic-forming polymers and the bonding layer includes a ceramic as main constituent.

US Pat. No. 10,431,503

SACRIFICIAL CAP FOR FORMING SEMICONDUCTOR CONTACT

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first semiconductor fin and a second semiconductor fin;
a gate stack arranged over a channel region of the first semiconductor fin and the second semiconductor fin;
a source/drain region comprising a crystalline material having top faceted surfaces and bottom faceted surfaces, the bottom faceted surfaces contacting the first semiconductor fin and the second semiconductor fin, wherein the source/drain region comprises an undulating or non-planar surface;
an air gap formed conformally and in direct contact with the top faceted surfaces and the bottom faceted surfaces of the source/drain region; and
a conductive contact material in contact with the top faceted surfaces of the crystalline material.

US Pat. No. 10,431,502

MASKLESS EPITAXIAL GROWTH OF PHOSPHORUS-DOPED SI AND BORON-DOPED SIGE (GE) FOR ADVANCED SOURCE/DRAIN CONTACT

International Business Ma...

1. A method for forming a transistor having reduced parasitic contact resistance, the method comprising:forming a first device over a semiconductor structure;
forming a second device adjacent the first device, the first and second devices separated from each other by a sidewall trench isolation (STI) structure;
forming an interlayer dielectric (ILD) over the first and second devices;
forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device;
forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device;
removing remaining portions of the first dielectric layer;
forming an epitaxial layer over the source/drain regions of the first device; and
removing the second dielectric layers formed over the source/drain regions of the second device.

US Pat. No. 10,431,501

SEMICONDUCTOR DEVICE WITH HIGH-K GATE DIELECTRIC LAYER AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:forming an interlayer dielectric layer on a base substrate;
forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to one second opening, the one first opening being between the one second opening and the base substrate to expose the base substrate;
forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings;
forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer;
forming an amorphous silicon layer on the cap layer and at least on the bottom surfaces of the first openings, wherein forming the amorphous silicon layer comprises:
forming an amorphous silicon film on the cap layer on the side and bottom surfaces of the first openings and the side surfaces of the second openings;
forming a filling layer to fill the first openings;
etching portions of the amorphous silicon film on the side surfaces of the second openings using the filling layer as an etching mask; and
removing the filling layer;
after forming the amorphous silicon layer, performing a thermal annealing process on the cap layer and the high-K gate dielectric layer through the amorphous silicon layer to cause the oxygen ions to diffuse into the high-K gate dielectric layer and the amorphous silicon layer to absorb the oxygen ions;
removing the amorphous silicon layer; and
forming a metal layer to fill the first openings and the second openings.

US Pat. No. 10,431,500

MULTI-STEP INSULATOR FORMATION IN TRENCHES TO AVOID SEAMS IN INSULATORS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a trench in a material;
forming a conductor in a lower portion of the trench;
performing a first atomic layer deposition (ALD) of a first liner material to line a middle portion and an upper portion of the trench, the middle portion is between the lower portion and the upper portion;
flowing a fill material comprising an insulator to fill the middle portion and the upper portion of the trench;
removing the fill material from the upper portion of the trench to leave the fill material in the middle portion of the trench; and
performing a second ALD of a second material to fill the upper portion of the trench with the second material.

US Pat. No. 10,431,499

INSULATING GATE SEPARATION STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit product, comprising:a first final gate structure for a first transistor device;
a second final gate structure for a second transistor device, said first and second transistors having a gate width direction and a gate length direction that is substantially normal to said gate width direction; and
an insulating gate separation structure positioned between said first and second final gate structures, said insulating gate separation structure comprising an upper portion and a lower portion, said lower portion having a first lateral width in said gate width direction that is substantially uniform throughout a vertical height of said lower portion, said upper portion having a substantially uniform second lateral width in said gate width direction that is substantially uniform throughout a vertical height of said upper portion, wherein said second lateral width is less than said first lateral width and wherein said insulating gate separation structure has a substantially uniform third lateral width in said gate length direction throughout an overall vertical height of said gate separation structure, wherein there is a stepped transition between said upper portion and said lower portion of said gate separation structure.

US Pat. No. 10,431,498

SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF

Semiconductor Manufacturi...

15. A semiconductor structure, comprising:a base substrate;
a plurality of gate structures formed on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode;
a sacrificial layer formed on the sidewall spacers on each side surface of the gate electrode; and
source/drain doped regions formed in the base substrate on opposite sides of each gate structure, wherein
each of the source/drain doped regions includes an amorphous layer exposed by the sacrificial layer from an ion implantation using the sacrificial layer as a mask and a remaining portion of each of the source/drain doped regions directly covered by the sacrificial layer, and
the amorphous layer and the remaining portion of each of the source/drain doped regions are divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures.

US Pat. No. 10,431,497

MANUFACTURING METHOD OF EPITAXIAL FIN-SHAPED STRUCTURE

UNITED MICROELECTRONICS C...

1. A manufacturing method of an epitaxial fin-shaped structure, comprising:providing a substrate;
forming a recess in the substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer is partly formed in the recess and partly formed outside the recess, and the epitaxial layer comprises a dent formed on the top surface of the epitaxial layer and formed corresponding to the recess in a thickness direction of the substrate;
forming a nitride layer conformally on the epitaxial layer;
forming an oxide layer on the nitride layer;
performing a first planarization process to remove a part of the oxide layer, wherein the first planarization process is stopped on the nitride layer; and
patterning the epitaxial layer in the recess for forming at least one epitaxial fin-shaped structure.

US Pat. No. 10,431,496

DEVICE CHIP PACKAGE MANUFACTURING METHOD

DISCO CORPORATION, Tokyo...

1. A device chip package manufacturing method comprising:a cutting step of forming cut grooves having a depth reaching a finished thickness of device chips by cutting a device wafer from a top surface of the device wafer along a plurality of intersecting streets formed on the top surface by a cutting blade, the device wafer having devices formed in respective regions demarcated by the streets;
a cut groove inclination state detecting step of detecting an inclination state of the cut grooves that is performed after the cutting step is performed;
a sealing resin layer forming step of forming a sealing resin layer coating the top surface and the cut grooves of the device wafer by supplying a sealing resin to the top surface of the device wafer after the cutting step and the cut groove inclination state detecting step are performed;
a grinding step of thinning the device wafer to the finished thickness of the device chips by grinding an undersurface of the device wafer after the sealing resin layer forming step is performed; and
a laser processing step of dividing the device wafer into individual chips and forming device chip packages by holding the device wafer by a holding surface of a chuck table and applying a laser beam having a wavelength absorbable by the sealing resin layer along the cut grooves of the device wafer held by the chuck table after the grinding step is performed;
the laser processing step applying the laser beam in parallel with the cut grooves while the holding surface of the chuck table and the laser beam are inclined relative to each other on the basis of the inclination state of the cut grooves, the inclination state being detected in the cut groove inclination state detecting step.

US Pat. No. 10,431,495

SEMICONDUCTOR DEVICE WITH LOCAL CONNECTION

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:forming a first trench silicide (TS) coupled to a first source or drain (S/D), a second TS coupled to a second S/D, and a gate metal separated from the first and second TS;
forming a trench above and on sides of the gate metal;
forming a local connection metal in the trench such that the gate metal is coupled to the first TS and the second TS; and
forming a local connection cap on top of the local connection metal.

US Pat. No. 10,431,493

DOPING CONTROL OF METAL NITRIDE FILMS

APPLIED MATERIALS, INC., ...

1. A method for controlling doping of a tantalum nitride film, the method comprising:controlling a temperature during deposition of a tantalum nitride film to control a density of the deposited tantalum nitride film, the density of the tantalum nitride film less than or equal to about 9.5 g/cm3; and
exposing the tantalum nitride film to a dopant metal precursor to form a doped tantalum nitride film,
wherein there is no plasma treatment during deposition of the tantalum nitride film or between deposition of the tantalum nitride film and doping of the tantalum nitride film.

US Pat. No. 10,431,491

SEMICONDUCTOR DEVICE HAVING A TRIPLE INSULATING FILM SURROUNDED VOID

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first semiconductor region extending in a first direction and having a first conductivity type;
a second semiconductor region extending in the first direction, disposed with the first semiconductor region in a second direction crossing the first direction, surrounding a void, and having a second conductivity type;
an insulating section provided between the void and the second semiconductor region, and including a first insulating film including silicon oxide, a second insulating film including silicon nitride, and a third insulating film including silicon oxide;
a third semiconductor region provided on the first semiconductor region and the second semiconductor region, and having the second conductivity type; and
a cover film provided on the void, the insulating section being located between the third semiconductor region and the cover film.

US Pat. No. 10,431,490

WAFER SCALE PACKAGING

Akoustis, Inc., Huntersv...

1. A method for packaging a resonator device, the method using a wafer scale packaging process, the method comprising:providing a single crystal acoustic resonator device formed on a silicon substrate having a first thickness, the single crystal acoustic resonator device comprising a resonator structure and a contact structure;
forming a patterned solder structure configured overlying the single crystal acoustic resonator device and the surface region to form a first air gap region provided from the patterned solder structure and configured between the resonator structure and a first portion of a mounting substrate member, wherein the first air gap region having a height of 10 um to 50 um, the patterned solder structure having a patterned upper surface region;
forming a thickness of an epoxy material overlying the patterned upper surface region, while maintaining the resonator structure free from any of the epoxy material;
positioning the mounting substrate member to the epoxy material;
curing the epoxy material to mate the single crystal acoustic resonator device to the mounting substrate member, the mounting substrate member being optically transparent, the mounting substrate member comprising a surface region; and
processing the silicon substrate to remove a portion of the silicon substrate to form a resulting silicon substrate of a second thickness, the second thickness being less than the first thickness, the resulting silicon substrate having a silicon backside region.

US Pat. No. 10,431,488

LIFT PIN AND METHOD FOR MANUFACTURING SAME

KOMICO CO., LTD., Anseon...

1. A lift pin passing through a hole of a susceptor on which a wafer is placed inside a process chamber in which an epitaxial process for the wafer is performed, to support the wafer, and having a surface formed of a glassy carbon material, the lift pin comprising:a pin head formed at an upper part of the lift pin, the upper part contacting the wafer;
a shaft passing through the hole of the susceptor; and
a pin neck comprising, between the pin head and the shaft, an outer circumferential surface inclinedly formed to be gradually narrower from the pin head to the shaft, wherein the lift pin includes a base member formed of ceramic material, and the glassy carbon material coated on the base member,
wherein a mirror surface treatment is performed on the glassy carbon material of the lift pin to reduce a friction among the lift pin, the wafer, and the susceptor to stably prevent a generation of particles caused by the friction,
wherein a heat conductivity of the glassy carbon is relatively lower than a heat conductivity of the base member made of the ceramic material in order to prevent the portion of the wafer contacting the lift pin from deteriorating.

US Pat. No. 10,431,485

ARTICLE TRANSPORT FACILITY

Daifuku Co., Ltd., Osaka...

1. An article transport facility comprising:a fixed support portion that is provided in a fixed state and supports an article;
a moving member that moves along a moving path that extends via a stop position that is set for the fixed support portion;
a transfer apparatus that is provided with a moving support portion configured to move integrally with the moving member along a widthwise direction that is orthogonal to a lengthwise direction of the moving path within a horizontal plane, and receives and supplies an article from and to the fixed support portion while the moving support portion moves to protrude and retract between a retracted position at which the moving support portion is housed within the moving path in terms of the widthwise direction and a protruding position at which the moving support portion protrudes outward from the moving path in the widthwise direction; and
a control unit that controls movement of the moving member and a transfer operation that is performed by the transfer apparatus, the control unit configured to execute a stopping control to stop the moving member at the stop position, and a protrusion control to move the moving support portion of the transfer apparatus from the retracted position to the protruding position,
wherein the article transport facility further comprises:
a detection target member that is provided at a position corresponding to the stop position, and has a length that is equal to a length of an acceptable stop range that is an acceptable range of the stop position, in the lengthwise direction; and
a detection unit that is provided on the moving member, at a fixed position relative to the retracted position, and detects the detection target member with the moving member being located within the acceptable stop range, and
the control unit is configured to start execution of the protrusion control upon the moving member reaching a protrusion start position as a result of the stopping control, the protrusion start position being set upstream of the stop position in a direction in which the moving member moves, and after the moving member has reached a protrusion monitoring start position that is set downstream of the protrusion start position in the direction in which the moving member moves toward the stop position, the control unit is configured to continue execution of the protrusion control as long as the detection unit is detecting the detection target member.

US Pat. No. 10,431,484

METHOD AND STATION FOR MEASURING THE CONTAMINATION OF A TRANSPORT BOX FOR THE ATMOSPHERIC CONVEYANCE AND STORAGE OF SUBSTRATES

PFEIFFER VACUUM, Annecy ...

1. A method for measuring contamination of a transport box for atmospheric conveyance and storage of substrates, the method comprising:measuring a concentration of at least one gaseous species inside the transport box by a measurement device comprising at least one gas analyzer and a measurement line connecting the at least one gas analyzer to an interface, the interface placing the measurement line in communication with an internal atmosphere of the transport box; and
supplying a gas flow containing water vapor to the measurement device.

US Pat. No. 10,431,480

EXTERNAL SUBSTRATE ROTATION IN A SEMICONDUCTOR PROCESSING SYSTEM

APPLIED MATERIALS, INC., ...

1. A processing system for semiconductor processing, the processing system comprising:two transfer chambers;
a processing chamber coupled to one of the two transfer chambers; and
a rotation module positioned between the transfer chambers, the rotation module comprising:
a plurality of sidewalls;
a ceiling, wherein an interior volume is bounded by the plurality of sidewalls and the ceiling; and
a substrate support comprising a single substrate platform;
wherein a first portion of the single substrate platform is disposed within the interior volume of the rotation module and a second portion of the single substrate platform extends into an interior volume of a first transfer chamber and a second transfer chamber of the two transfer chambers, the rotation module configured to rotate a substrate while the second portion is extended into the first and second transfer chambers.

US Pat. No. 10,431,477

METHOD OF PACKAGING CHIP AND CHIP PACKAGE STRUCTURE

Pep Innovation PTE Ltd., ...

1. A method of packaging a chip, comprising:mounting at least one chip to be packaged and at least one electrically conductive module on a carrier, wherein the at least one chip to be packaged has a back surface facing upwards and an active surface facing towards the carrier, and the at least one electrically conductive module is in the vicinity of the at least one chip to be packaged;
forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the at least one electrically conductive module, wherein the first encapsulation layer is disposed with at least one concave first cavity and at least one concave second cavity, wherein the at least one chip is located in the at least one first cavity, the back surface of the at least one chip facing towards the first encapsulation layer, and the at least one electrically conductive module is located in the at least one second cavity, wherein the first encapsulation layer encapsulates the at least one electrically conductive module and wherein the at least one electrically conductive module comprises an electrically conductive array formed by a plurality of electrically conductive studs, the electrically conductive array being integrally packaged by an insulating material;
detaching the carrier to expose the active surface of the at least one chip to be packaged and a first surface of the at least one electrically conductive module; and
completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged and the first surface of the at least one electrically conductive module, wherein a rewiring structure is formed on the active surface of the at least one chip and the first surface of the at least one electrically conductive module for leading out pads on the active surface of the at least one chip and the first surface of the at least one electrically conductive module.

US Pat. No. 10,431,476

METHOD OF MAKING A PLURALITY OF PACKAGED SEMICONDUCTOR DEVICES

NXP B.V., Eindhoven (NL)...

1. A method of making a plurality of packaged semiconductor devices, the method comprising:providing a carrier blank having a die receiving surface and an underside;
mounting a plurality of semiconductor dies on the die receiving surface of the carrier blank,
wherein the dies extend to a first height above the die receiving surface;
depositing an encapsulant on the die receiving surface,
wherein an upper surface of the encapsulant is located above said first height,
whereby the encapsulant covers the plurality of semiconductor dies; and
singulating the carrier blank and encapsulant to form the plurality of packaged semiconductor devices by:
sawing into the underside of the carrier to saw through the carrier blank and
saw partially through the encapsulant to a saw depth intermediate the first height and the upper surface of the encapsulant,
wherein said sawing separates the carrier blank into a plurality of carriers,
each carrier having
an underside corresponding to the underside of the carrier blank and
a die receiving surface corresponding to the die receiving surface of the carrier blank,
wherein the die receiving surface of each carrier has at least one of said semiconductor dies mounted thereon; and
removing encapsulant from upper surface of the encapsulant at least until said saw depth is reached;
further comprising contacting an electrical probe to the underside of at least some of the carriers to test the packaged semiconductor devices; and
performing solder reflow;
wherein said solder reflow is performed after said testing the packaged semiconductor devices;
further comprising contacting an electrical probe to the underside of at least some of the carriers to re-test the packaged semiconductor devices after said solder reflow is performed.

US Pat. No. 10,431,475

COLD PLATE WITH DAM ISOLATION

Intel Corporation, Santa...

1. A cold plate, comprising: a base; and a lid affixed to the base via a braze joint, wherein the braze joint extends around a perimeter of the lid, and wherein one of the lid or the base includes: a dam having a perimeter located inside of the perimeter of the lid, wherein the dam is compressed against another of the lid or the base and is liquid-tight to the other of the lid or the base, wherein the dam is unitary with the lid or the base, and wherein a cavity is located between the base and the lid within the perimeter of the dam to provide a circulation passage for a liquid coolant; wherein the base includes a first side and a second side opposite to the first side, wherein the lid is affixed to the first side of the base, wherein the first side of the base includes a first surface and a second surface, wherein the second surface is further from the second side than the first surface is from the second side, and wherein the braze joint affixes the lid to the first surface and the dam is compressed against the second surface.

US Pat. No. 10,431,474

METHOD FOR FORMING A CAVITY AND A COMPONENT HAVING A CAVITY

Robert Bosch GmbH, Stutt...

1. A method for forming a cavity in a silicon substrate, comprising:providing the silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate;
situating an etching mask on the surface of the silicon substrate, the etching mask having a mask opening having a first transverse edge and a second transverse edge parallel to the first transverse edge, the first transverse edge being situated in the first plane of the silicon substrate, the etching mask having a first retarding structure that protrudes into the mask opening, the etching mask having a first etching projection region, and all further edges of the mask opening outside the first etching projection region being situated parallel to {111} planes of the silicon substrate; and
anisotropically etching the silicon substrate during a defined etching duration, an etching rate in the <111> directions of the silicon substrate being lower than in other spatial directions, the first retarding structure being undercut going out from the first etching projection region in a first undercut direction, the first undercut direction being oriented parallel to the first transverse edge and the second transverse edge of the mask opening, the etching duration being defined such that through the anisotropic etching, a cavity forms in the silicon substrate hat has an opening on the surface of the silicon substrate, the opening of the cavity being limited at two sides by the first transverse edge and the second transverse edge of the mask opening, and at a further side by a first longitudinal edge, perpendicular to the first and to the second transverse edge, that is produced by the undercutting of the first retarding structure, and the etching duration moreover being defined such that after elapsing of the etching duration, the first plane of the silicon substrate is exposed and forms a floor surface of the cavity.

US Pat. No. 10,431,473

FINFET WITH SOURCE/DRAIN STRUCTURE AND METHOD OF FABRICATION THEREOF

Taiwan Semiconductor Manu...

1. A method of semiconductor device fabrication, comprising:providing a plurality of adjacent first fins extending from a substrate, wherein the plurality of adjacent first fins include at least two inner first-fin sidewalls facing each other and two outer first-fin sidewalls facing away from the plurality of adjacent first fins;
depositing a first spacer layer over the plurality of adjacent first fins, wherein the first spacer layer includes a first region disposed along the at least two inner first-fin sidewalls and a second region disposed over the top of the plurality of adjacent first fins and along the two outer first-fin sidewalls;
performing a tilted implantation process to the first spacer layer so that the second region and a top portion of the first region of the first spacer layer have a first dopant concentration corresponding to a first etch rate and a bottom portion of the first region has a second dopant concentration corresponding to a second etch rate greater than the first etch rate;
performing an etching process to remove a top portion of the second region to form two outer first-fin spacers along the two outer first-fin sidewalls, remove a top portion of the plurality of adjacent first fins, and remove at least partially the first region; and
forming a first epitaxial layer over a remaining portion of the plurality of adjacent first fins, wherein the forming of at least a portion of the first epitaxial layer is laterally constrained by the two outer first-fin spacers.

US Pat. No. 10,431,471

METHOD OF PLANARIZING A SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER

Infineon Technologies AG,...

1. A method of planarizing a semiconductor wafer, wherein the method comprises:providing a semiconductor wafer comprising a surface;
forming a mask layer directly on the surface of the semiconductor wafer, wherein a thickness of the mask layer is smaller in thinning areas, which are to be thinned for planarizing, than in areas which are not to be thinned for planarizing,
wherein the forming of the mask layer comprises forming a raw mask layer and subsequently removing portions of the raw mask layer in the thinning areas by polishing, wherein a greater amount of material of the raw mask layer is removed in the thinning areas than in other areas; and
removing material of the semiconductor wafer in the thinning areas by a polishing process and an etching process, wherein the material of the semiconductor wafer is removed faster than the material of the mask layer.

US Pat. No. 10,431,469

METHOD FOR HIGH ASPECT RATIO PHOTORESIST REMOVAL IN PURE REDUCING PLASMA

Mattson Technology, Inc.,...

1. A method for removing photoresist and an-oxidation layer-from a semiconductor substrate, comprising:placing a substrate in a processing chamber, the processing chamber located downstream from a plasma chamber for generating a non-oxidizing plasma to be used in treating the substrate, the processing chamber separated from the plasma chamber by a separation grid, the separation grid configured to be transparent to neutral particles and not transparent to plasma;
generating a first non-oxidizing plasma from a first reactant gas and a first carrier gas in the plasma chamber, wherein the first non-oxidizing plasma comprises from about 10% to about 40% of the first reactant gas, wherein the first reactant gas has a flow rate of from about 0.05 standard cubic centimeters per minute per square centimeter of the substrate to about 12.5 standard cubic centimeters per minute per square centimeter of the substrate, and wherein the first carrier gas has a flow rate of from about 0.25 standard cubic centimeters per minute per square centimeter of the substrate to about 15 standard cubic centimeters per minute per square centimeter of the substrate, wherein the first reactant gas comprises ammonia, and the first carrier gas comprises nitrogen;
channeling neutral particles of the first non-oxidizing plasma through the separation grid to the surface of the substrate;
treating the substrate by exposing the substrate to the neutral particles of the first non-oxidizing plasma in the processing chamber to at least partially remove the photoresist layer from the substrate;
wherein the substrate contains high aspect ratio channels having an aspect ratio of greater than about 50;
subsequent to removing the photoresist from the substrate, generating a second non-oxidizing plasma from a second reactant gas and a second carrier gas in the plasma chamber, wherein the second non-oxidizing plasma comprises from about 10% to about 40% of the second reactant gas, wherein the second reactant gas has a flow rate of from about 100 standard cubic centimeters per minute to about 15,000 standard cubic centimeters per minute, and wherein the second carrier gas has a flow rate of from about 500 standard cubic centimeters to about 20,000 standard cubic centimeters per minute, wherein the second reactant gas comprises hydrogen, and the second carrier gas comprises argon;
channeling neutral particles of the second non-oxidizing plasma through the separation grid to the surface of the substrate; and
treating the substrate by exposing the substrate to the neutral particles of the second non-oxidizing plasma in the processing chamber to at least partially remove the oxidation layer from the substrate.

US Pat. No. 10,431,468

LOCATION-SPECIFIC TUNING OF STRESS TO CONTROL BOW TO CONTROL OVERLAY IN SEMICONDUCTOR PROCESSING

Tokyo Electron Limited, ...

1. A method for correcting wafer overlay, the method comprising:receiving a substrate having a working surface and having a backside surface opposite to the working surface, the substrate having an initial overlay error resulting from one or more micro fabrication processing steps that have been executed to create at least part of a semiconductor device on the working surface of the substrate;
receiving an initial bow measurement of the substrate that maps z-height deviations on the substrate relative to one or more reference z-height values;
generating an overlay correction pattern that defines adjustments to internal stresses at specific locations on the substrate based on the initial bow measurement of the substrate, wherein a first given location on the substrate has a different internal stress adjustment defined as compared to a second given location on the substrate in the overlay correction pattern; and
physically modifying internal stresses on the substrate at specific locations on the substrate according to the overlay correction pattern resulting in a modified bow of the substrate, the substrate with the modified bow having a second overlay error, the second overlay error having reduced overlay error as compared to the initial overlay error.

US Pat. No. 10,431,467

MODULE INCLUDING METALLIZED CERAMIC TUBES FOR RF AND GAS DELIVERY

Lam Research Corporation,...

1. A module useful for processing semiconductor substrates in a vacuum chamber including a processing zone in which a semiconductor substrate may be processed, the module comprising:a ceramic body;
a stem made of ceramic material having a flange bonded to the ceramic body; and
at least one metallized ceramic tube configured to supply gas to the ceramic body and supply power to an electrode embedded in the ceramic body.

US Pat. No. 10,431,466

HYDROGENATION AND NITRIDIZATION PROCESSES FOR MODIFYING EFFECTIVE OXIDE THICKNESS OF A FILM

APPLIED MATERIALS, INC., ...

1. A method of forming a structure in a semiconductor device, the method comprising:depositing a metal nitride layer on a high-k dielectric layer formed on a semiconductor substrate to form a portion of the structure, wherein the semiconductor substrate is disposed over a substrate supporting surface of a pedestal disposed in a first processing chamber in a cluster tool;
sequentially exposing an exposed surface of the deposited metal nitride layer formed on the semiconductor substrate to a non-oxidizing plasma-excited hydrogen species followed by a plasma-excited nitrogen species while a bias is applied to the semiconductor substrate, which is disposed over a substrate supporting surface of a pedestal disposed in a second processing chamber in the cluster tool;
depositing a silicon-containing layer on the exposed surface;
performing a thermal anneal process on the silicon-containing layer; and
removing the silicon-containing layer.

US Pat. No. 10,431,465

SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor structure, comprising:a semiconductor substrate;
a trench disposed in the semiconductor substrate; and
a doped semiconductor material filled in the trench, wherein a top surface of the doped semiconductor material is planar with a top surface of the semiconductor substrate, and a dopant in the doped semiconductor material has a decreasing concentration gradient in a depth direction of the trench,
wherein the dopant in a top portion of the doped semiconductor material has a concentration between 15 wt % and 40 wt % and the dopant in a bottom portion of the doped semiconductor material is between 0 wt % and 35 wt %.

US Pat. No. 10,431,464

LINER PLANARIZATION-FREE PROCESS FLOW FOR FABRICATING METALLIC INTERCONNECT STRUCTURES

International Business Ma...

1. A method for fabricating a device, comprising:forming a dielectric layer on a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
depositing a first layer of metallic material over the dielectric layer to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening;
depositing a second layer of metallic material to fill the opening with metallic material;
removing an overburden portion of the second layer of metallic material by planarizing the second layer of metallic material down to an overburden portion of the liner layer on the upper surface of the dielectric layer;
applying a surface treatment to the overburden portion of the liner layer on the upper surface of the dielectric layer to convert the overburden portion of the liner layer into a layer of metal nitride material, wherein the portion of the liner layer deposited on exposed surfaces within the opening is not converted into the layer of metal nitride material; and
wherein applying a surface treatment comprises performing a plasma nitridation surface treatment to infuse nitrogen atoms into the overburden portion of the liner layer; and selectively etching away the layer of metal nitride material.

US Pat. No. 10,431,463

SUBSTRATE HOLDING DEVICE, LITHOGRAPHY APPARATUS, AND ARTICLE PRODUCTION METHOD

Canon Kabushiki Kaisha, ...

1. A substrate holding device configured to hold a substrate, the substrate holding device comprising:a holding member including a center part having a hole through which gas is exhausted from a space between the substrate and the holding member and an outer peripheral part surrounding the center part;
a moving unit configured to relatively move the substrate and the holding member in a direction perpendicular to a substrate holding surface of the center part; and
a seal member provided on the outer peripheral part, configured to seal the space and configured to be deformed in response to a distance between the substrate and the holding member relatively moved by the moving unit,
wherein at least one of the outer peripheral part and the seal member has a through hole, and
wherein a first end of the through hole faces the space and a second end of the through hole faces an atmosphere.

US Pat. No. 10,431,462

PLASMA ASSISTED DOPING ON GERMANIUM

Lam Research Corporation,...

1. A method for forming a junction in a germanium (Ge) layer of a substrate, comprising:arranging the substrate in a processing chamber;
forming the junction in the germanium (Ge) layer by plasma doping including:
one or more plasma treatments using a first plasma gas mixture including a phosphorus (P) gas species during a predetermined P doping period; and
one or more plasma treatments using a second plasma gas mixture including an antimony (Sb) gas species during a predetermined Sb doping period; and
annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.

US Pat. No. 10,431,460

METHOD FOR PRODUCING SIC COMPOSITE SUBSTRATE

SHIN-ETSU CHEMICAL CO., L...

1. A method for producing a SiC composite substrate comprising a monocrystalline SiC layer on a polycrystalline SiC substrate, the method comprising the steps of in order: providing a monocrystalline SiC layer on the front side of a support substrate that is made of silicon and has a silicon oxide film on front and back sides thereof so as to produce a monocrystalline SiC layer carrier; removing some or all of the thickness of the silicon oxide film over some region or all of the back side of the support substrate in the monocrystalline SiC layer carrier so as to impart warpage to the monocrystalline SiC layer carrier; depositing polycrystalline SiC onto the monocrystalline SiC layer by chemical vapor deposition so as to form a polycrystalline Sic substrate; and physically and/or chemically removing the support substrate.

US Pat. No. 10,431,459

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device, the method comprising:forming an etching target layer on a substrate;
forming an upper mask layer on the etching target layer;
forming a plurality of preliminary mask patterns on the upper mask layer, two neighboring preliminary mask patterns of the plurality of preliminary mask patterns defining a preliminary opening; and
performing an ion beam etching process on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns,
wherein the first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

US Pat. No. 10,431,458

MASK SHRINK LAYER FOR HIGH ASPECT RATIO DIELECTRIC ETCH

LAM RESEARCH CORPORATION,...

1. A method of forming an etched feature in a dielectric-containing stack on a semiconductor substrate, the method comprising:(a) receiving a substrate comprising the dielectric-containing stack and a mask layer positioned over the dielectric-containing stack, the mask layer including a pattern comprising openings in the mask layer;
(b) depositing a mask shrink layer on the mask layer, wherein the mask shrink layer is formed through a vapor deposition process and comprises tungsten, and wherein the mask shrink layer lines the openings in the mask layer;
(c) generating an etching plasma comprising an etching reactant, exposing the substrate to the etching plasma, and etching the feature in the dielectric-containing stack, wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,431,457

METHOD FOR FORMING PATTERNED STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for forming a patterned structure, comprising:providing a layout pattern, wherein the layout pattern comprises:
a plurality of first lines, wherein each of the first lines is elongated in a first direction; and
a plurality of second lines, wherein each of the second lines is elongate in a second direction, wherein the first direction is orthogonal to the second direction;
decomposing the layout pattern for forming:
a first mask comprising:
a plurality of first line patterns corresponding to the first lines; and
a first block pattern corresponding to the second lines; and
a second mask comprising:
a plurality of second line patterns corresponding to the second lines; and
a second block pattern corresponding to the first lines; and
performing a first photolithography process with the first mask and a second photolithography process with the second mask for forming a patterned structure comprising:
a plurality of first line structures, wherein each of the first line structures is elongated in the first direction, and the first line structures are defined by and structurally confined to a region where the first line patterns and the second block pattern overlap with one another; and
a plurality of second line structures, wherein each of the second line structures is elongated in the second direction, and the second line structures are defined by and structurally confined to a region where the second line patterns and the first block pattern overlap with one another.

US Pat. No. 10,431,456

IMPRINT APPARATUS AND METHOD

SAMSUNG DISPLAY CO., LTD....

1. An imprint method comprising:applying a material layer for forming a patterned layer having a pattern, to a substrate;
feeding a stamp film including a stamp pattern corresponding to the pattern of the patterned layer, along a pressure roller and an idle roller, to dispose the stamp pattern of the stamp film facing the material layer on the substrate;
forming the patterned layer having the pattern, comprising:
the pressure roller pressing the stamp film including the stamp pattern toward the material layer on the substrate to contact the stamp pattern of the stamp film with the material layer and form the pattern in the material layer,
curing the material layer in contact with the stamp pattern of the stamp film, and
moving the pressure roller and the idle roller to peel the stamp film including the stamp pattern off the material layer which is cured, by a peeling force, to form the patterned layer having the pattern from the material layer which is cured; and
detecting a defect in the pattern of the formed patterned layer, during the peeling of the stamp film off the material layer which is cured, by sensing the peeling force in real time by a pressure sensor connected to the pressure roller.

US Pat. No. 10,431,455

FEMTOSECOND LASER-INDUCED FORMATION OF SINGLE CRYSTAL PATTERNED SEMICONDUCTOR SURFACE

THE REGENTS OF THE UNIVER...

1. A method of manufacturing a surface corrugation in a material using light energy, said method comprising:applying a plurality of laser energy pulses focused at a surface of the material, each of said plurality of laser energy pulses being about 150 femtoseconds in duration, said plurality of laser energy inducing point defect accumulation and diffusion in the material resulting in epitaxial surface corrugation, the epitaxial surface corrugation having a period less than 0.3 times a wavelength of the laser.

US Pat. No. 10,431,454

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

Nuvoton Technology Corpor...

1. A semiconductor substrate, comprising:a base;
a buffer layer, disposed on the base, wherein doped regions are disposed in a portion of a surface of the buffer layer and the doped regions are separated from each other;
a mask layer, disposed on the buffer layer and located on the doped regions; and
a first GaN layer, disposed on the buffer layer and covering the mask layer.

US Pat. No. 10,431,453

ELECTRIC FIELD ASSISTED PLACEMENT OF NANOMATERIALS THROUGH DIELECTRIC ENGINEERING

INTERNATIONAL BUSINESS MA...

1. A method of positioning nanomaterials comprising:patterning guiding dielectric structures from a single material layer on a substrate including electrodes, wherein an exposed portion of the substrate between the guiding dielectric structures provides a deposition surface;
producing an electric field by the electrodes that is attenuated through the guiding dielectric structures to create an attractive dielectrophoretic force that guides at least one nanostructure to be positioned directly on the deposition surface of the substrate, the at least one nanostructure abutting the guiding dielectric structures, but is not positioned directly atop the guiding dielectric structures; and
removing the guiding dielectric surfaces.

US Pat. No. 10,431,452

PROTECTIVE FILM FORMING METHOD

Tokyo Electron Limited, ...

1. A protective film forming method, comprising steps of:causing an entire surface of a silicon-containing underfilm to be terminated with fluorine by supplying an activated fluorine-containing gas to the silicon-containing underfilm formed on a substrate having a surface including a plurality of recesses and a flat surface provided between the adjacent recesses, the substrate being provided in a process chamber;
nitriding a surface of the silicon-containing underfilm formed on the flat surface of the substrate by supplying a nitriding gas converted to plasma to the silicon-containing underfilm terminated with fluorine such that a silicon adsorption site is formed on the surface of the silicon-containing underfilm formed on the flat surface of the substrate;
adsorbing a silicon-containing gas on the silicon adsorption site by supplying the silicon-containing gas to the silicon-containing underfilm;
changing a rotational speed of the turntable between the steps of causing the entire surface of the silicon-containing underfilm to be terminated with fluorine and nitriding the surface of the silicon-containing underfilm,
wherein the substrate is arranged on a turntable along a circumferential direction thereof,
wherein a fluorine-containing gas supply region configured to supply the activated fluorine-containing gas to the substrate, a silicon-containing gas supply region configured to supply the silicon-containing gas to the substrate, and a nitriding gas supply region configured to supply the nitriding gas to the substrate are arranged above the turntable, along the circumferential direction, and apart from each other,
wherein the step of causing the entire surface of the silicon-containing underfilm to be terminated with fluorine is performed by stopping the supply of the silicon-containing gas in the silicon-containing gas supply region and the supply of the nitriding gas in the nitriding gas supply region and supplying the activated fluorine-containing gas to the substrate in the fluorine-containing gas supply region while rotating the turntable at least one time,
wherein the step of nitriding the surface of the silicon-containing underfilm is performed by stopping the supply of the activated fluorine-containing gas in the fluorine-containing gas supply region and supplying the nitriding gas converted to the plasma in the nitriding gas supply region while rotating the turntable a plurality of times, and
wherein the step of adsorbing the silicon-containing gas on the silicon adsorption site is performed by stopping the supply of the activated fluorine-containing gas in the fluorine-containing gas supply region and supplying the silicon-containing gas to the substrate in the silicon-containing gas supply region while rotating the turntable a plurality of times.

US Pat. No. 10,431,450

FILM FORMING METHOD

TOKYO ELECTRON LIMITED, ...

1. A film forming method for a target object including a main surface and grooves formed in the main surface, the method comprising:accommodating the target object in a processing chamber of a plasma processing apparatus;
after the accommodating, supplying a first gas into the processing chamber; and
after the supplying the first gas, supplying a second gas and a high frequency power for plasma generation in the processing chamber by using a gas that includes the second gas in the processing chamber,
wherein:
the first gas comprises an oxidizing agent that does not include a hydrogen atom;
the second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom;
a film containing silicon and oxygen is selectively formed on the main surface of the target object except the grooves; and
a temperature of the target object during the supplying the second gas is lower than 450° C.

US Pat. No. 10,431,448

WET ETCHING METHOD, SUBSTRATE LIQUID PROCESSING APPARATUS, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A wet etching method for wet-etching a substrate including a first surface and a second surface opposite to the first surface and formed with a first layer as a lower layer and a second layer as an upper layer that are laminated on at least a peripheral edge portion of the first surface of the substrate, the method comprising:a process of rotating the substrate;
a process of supplying a chemical liquid capable of etching both the first layer and the second layer, to the first surface of the rotating substrate; and
a first process of supplying an etching inhibiting liquid to the second surface of the substrate while supplying the chemical liquid to the substrate;
wherein in the first process, the etching inhibiting liquid is supplied while rotating the substrate such that the etching inhibiting liquid wraps around the first surface through an edge of the substrate and reaches a first region extending from the edge of the substrate on the peripheral edge portion of the first surface to a first radial position located radially inward from the edge on the first surface.

US Pat. No. 10,431,447

POLYSILICON CHIP RECLAMATION ASSEMBLY AND METHOD OF RECLAIMING POLYSILICON CHIPS FROM A POLYSILICON CLEANING APPARATUS

HEMLOCK SEMICONDUCTOR COR...

1. A polysilicon chip reclamation assembly comprising:a polysilicon cleaning apparatus configured to clean a plurality of bodies of polysilicon;
a plurality of polysilicon chips generated from the bodies of polysilicon during cleaning thereof, wherein each of the plurality of polysilicon chips has a longest dimensional length ranging from 0.1 mm to 25.0 mm;
a polysilicon apparatus drain line configured to route the plurality of polysilicon chips from the polysilicon cleaning apparatus to a main chip drain line, wherein the main chip drain line is oriented at a downward slope away from the polysilicon apparatus drain line;
a fluid source fluidly coupled to the main chip drain line and configured to inject a fluid into the main chip drain line to drive the plurality of polysilicon chips through the main chip drain line;
a chip collection tank, wherein the main chip drain line comprises an outlet proximate the chip collection tank, the outlet configured to direct the plurality of polysilicon chips into the chip collection tank; and
a chip routing line extending between an outlet of the chip collection tank and a conveyor.

US Pat. No. 10,431,446

WET PROCESSING APPARATUS

NATIONAL INSTITUTE OF ADV...

1. A heating wet processing method, comprising:a placing step of placing a plate-shaped object to be processed on a stage by mounting the object on engaging pins separated from one another at predetermined intervals in a circumferential direction around a condensing plate, the object being mounted on the engaging pins in a state when a surface of the object is oriented upward, and;
a supplying step of supplying a processing liquid from above the stage to the surface of the object placed on the stage; and
a processing step of heating at least an interface between the object and the processing liquid by emitting light:
to the condensing plate to irradiate the object with the light condensed by the condensing plate from a position facing the object engaged by the engaging pins in a state, and
from a position blocked with respect to the stage with a blocking member and irradiate the light to the condensing plate, when the supplying step is supplying the processing liquid, wherein the condensing plate is mounted on the blocking member.

US Pat. No. 10,431,445

ION ANALYSIS DEVICE

HITACHI HIGH-TECHNOLOGIES...

1. An ion analyzer comprising:a first spray unit for atomizing and spraying a liquid including a measurement target substance;
a second spray unit separate from the first spray unit for atomizing and spraying toward the sprayed measurement target substance a liquid containing an additive that reacts with the measurement target substance;
a separation analysis unit for separately analyzing an ion generated by a reaction between the measurement target substance and the additive;
a detector for detecting the ion that has been separately analyzed by the separation analysis unit; and
a control unit for lowering a flow rate of the additive supplied to the second spray unit during a time when the additive is not necessary;the second spray unit comprises:at least one first piping for supplying another liquid comprising the additive;
at least one second piping for supplying spray gas to periphery of the another liquid, and wherein:
the additive is supplied to the first piping even during a time when the second spray unit is not spraying the additive; and
wherein the control unit switches spraying and stopping of said additive by the second spray unit based on a flow rate of the spray gas supplied to said second piping.

US Pat. No. 10,431,444

SYSTEMS AND METHODS FOR AUTOMATED ANALYSIS OF OUTPUT IN SINGLE PARTICLE INDUCTIVELY COUPLED PLASMA MASS SPECTROMETRY AND SIMILAR DATA SETS

PerkinElmer Health Scienc...

1. A method for automated analysis of spectrometry data the method comprising:(a) accessing, by a processor of a computing device, a sequence of pulse count values acquired by a spectrometer to produce, for each of at least one given peak corresponding to particles comprising an analyte and being present in a sample, pulse count values being greater than a threshold background intensity value;
(b) determining, by the processor, from a first array of the pulse count values, a threshold for identifying pulse count values as corresponding to a peak signal, and adjusting the threshold based on remaining pulse count values following each of a series of iterations, with a given subsequent iteration including pulse count values not identified as corresponding to a peak in a preceding iteration, wherein a final background threshold is determined upon convergence of the threshold within acceptable tolerance;
(c) building, by the processor, from the first array of the pulse count values, a smoothed data array comprising smoothed values and identifying, as identified peaks, a subset of the smoothed values that are larger than both subsequent and preceding smoothed values of the smoothed data array and also larger than the final background threshold; and
(d) automatically determining, by the processor, based on the identified peaks, at least one of:
(A) a particle mass distribution and/or particle size distribution for the particles in the sample; and
(B) statistical data for the particles in the sample.

US Pat. No. 10,431,443

DEVICE FOR MANIPULATING CHARGED PARTICLES

Shimadzu Research Laborat...

1. A device for manipulating charged particles, the device comprising:a series of electrodes arranged so as to form a channel for transportation of the charged particles;
a power supply unit adapted to provide supply voltages to said electrodes so as to create a non-uniform high-frequency electric field within said channel, the pseudopotential of said field having two or more local maxima along the length of said channel for transportation of charged particles, at least within a certain interval of time, wherein transportation of the charged particles along the length of the channel is provided by transposition of the at least two of said maxima of the pseudopotential such that the at least two of said maxima are caused to travel with time along the channel, at least within a certain interval of time and at least within a part of the length of the channel, wherein the supply voltages are high-frequency voltages;
wherein the device is configured to transport ions/charged particles through a viscous gas region, wherein the gas pressure within said viscous gas region meets the condition ?/L<0.01, where L is a width of the transport channel (m) and ? is the mean free path of molecules of said viscous gas (m).

US Pat. No. 10,431,442

ELECTROSTATIC TRAP MASS SPECTROMETER WITH IMPROVED ION INJECTION

LECO Corporation, St. Jo...

1. A method of mass spectral analysis comprising:injecting a continuous ion beam into a multiplexed analytical electrostatic trap (i) including a pair of concentric, cylindrical trap electrodes having static and non-ramped potentials, the pair of cylindrical trap electrodes including a set of aligned slits, and (ii) defining a cylindrical electrostatic field volume, the cylindrical electrostatic field volume including multiple volumes of an electrostatic trapping field, wherein the continuous ion beam is injected through the aligned slits of the pair of cylindrical trap electrodes.

US Pat. No. 10,431,441

REDUCING CALIBRATION OF COMPONENTS IN AN IMAGING PLATE SCANNER

PALODEX GROUP OY, Tuusul...

1. A photomultiplier tube for use in an imaging plate scanner, the photomultiplier tube comprising:a housing having a window;
a focusing electrode located in the housing;
an electron multiplier dynode located in the housing;
an anode;
a cathode and
a memory storing parameters.

US Pat. No. 10,431,440

METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE

APPLIED MATERIALS, INC., ...

1. A process chamber, comprising:a chamber body defining an interior volume;
a substrate support to support a substrate within the interior volume;
a plurality of cathodes coupled to the chamber body and having a corresponding plurality of targets to be sputtered onto the substrate;
a shield rotatably coupled to an upper portion of the chamber body and having at least one hole to expose at least one of the plurality of targets to be sputtered and at least one pocket disposed in a backside of the shield to accommodate and cover at least another one of the plurality of targets not to be sputtered,
wherein a sputtering surface of at least one of the plurality of targets extends beyond the lowermost surface of the shield when the shield is in a retracted position,
wherein the shield is configured to rotate about and linearly move along a central axis of the process chamber, and
wherein the at least another one of the plurality of targets extends at least partially into the at least one pocket when the shield is in a retracted position;
a chamber body adapter coupled to an upper portion of the chamber body, wherein the chamber body adapter is grounded; and
a plurality of grounding rings disposed between the shield and the chamber body adapter to directly ground the shield to the chamber body adapter when the shield is in a retracted position.

US Pat. No. 10,431,438

TITANIUM TARGET FOR SPUTTERING AND MANUFACTURING METHOD THEREOF

1. A high-purity titanium target for sputtering having a purity of 5N5 (99.9995%) or higher, wherein the high-purity titanium target has no macro pattern in which a difference in average crystal grain size is 20% or more and a difference in crystal orientation ratio is 10% or more on the target surface.

US Pat. No. 10,431,436

METHOD AND SYSTEM OF MONITORING AND CONTROLLING DEFORMATION OF A WAFER SUBSTRATE

SPTS TECHNOLOGIES LIMITED...

1. A method of monitoring and controlling deformation of an electrically insulating wafer substrate during plasma etching of the wafer substrate, the method comprising:disposing an electrically insulating wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the electrically insulating wafer substrate is exposed;
passing a process gas into the process chamber;
applying a radio frequency bias voltage to the platen assembly;
etching the exposed entire upper surface of the electrically insulating wafer substrate by generating a plasma within the process chamber;
determining, during said etching, a warping of the electrically insulating wafer substrate relative to the platen assembly by monitoring a voltage difference between the platen assembly and the process chamber;
attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.

US Pat. No. 10,431,435

WAFER CARRIER WITH INDEPENDENT ISOLATED HEATER ZONES

Applied Materials, Inc., ...

1. An apparatus comprising:a puck to carry a workpiece for fabrication processes;
a heater plate having a plurality of thermally isolated blocks each thermally coupled to the puck, and each having a heater to heat a respective block of the heater plate; and
a cooling plate fastened to and thermally coupled to the heater plate, the cooling plate having a cooling channel to carry a heat transfer fluid to transfer heat from the cooling plate,
wherein each heater extends into a corresponding bore of the cooling plate,
wherein the cooling channel is on each of two opposite sides of each thermally isolated block and thermally coupled to each thermally isolated block to remove heat from the two sides of each thermally isolated block through a heat transfer surface, wherein the heat transfer surface is adjacent to and surrounds the heater of the respective block, and wherein the cooling plate is laterally adjacent to a portion of each of the plurality of thermally isolated blocks.

US Pat. No. 10,431,433

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a chamber main body defining a chamber;
a stage, provided in the chamber, including a lower electrode and an electrostatic chuck provided on the lower electrode, on which a focus ring is arranged to surround a substrate mounted on the electrostatic chuck;
a first high frequency power supply configured to supply a first high frequency power for generating plasma of a gas in the chamber;
a second high frequency power supply configured to supply a second high frequency power for ion attraction to the lower electrode;
a DC power supply configured to generate a negative DC voltage to be applied to the focus ring in order to correct inclination of an incident direction of ions to an edge region of the substrate mounted on the electrostatic chuck with respect to a vertical direction;
a switching unit configured to stop the application of the DC voltage to the focus ring; and
a controller configured to control one or both of the high frequency power supply and the second high frequency power supply and control the switching unit,
wherein the controller controls one or both of the first high frequency power supply and the second high frequency power supply to periodically stop the supply of one or both of the first high frequency power and the second high frequency power, and
the controller also controls the switching unit to apply the DC voltage to the focus ring from a first time after a predetermined period of time in which a self-bias voltage of the lower electrode is decreased from a start point of each period in which one or both of the first high frequency power and the second high frequency power are supplied and to stop the application of the DC voltage to the focus ring during each period in which the supply of one or both of the first high frequency power and the second high frequency power is stopped.

US Pat. No. 10,431,432

PLASMA TREATMENT SYSTEM INCLUDING COVER PLATE TO INSULATE WINDOW

SAMSUNG ELECTRONICS CO., ...

1. A plasma treatment system, comprising:a window;
an antenna electrode disposed on the window; and
a cover plate disposed between the antenna electrode and the window, the cover plate extending to a side surface of the window to cover a top surface and at least a portion of the side surface of the window,
wherein the cover plate comprises:
a disk portion disposed on the window to have an opening partially exposing the window;
an upper edge end portion connected to an edge of a top surface of the disk portion to enclose the antenna electrode; and
upper blocks upwardly protruding from the disk portion, the upper blocks disposed between the opening and the antenna electrode and the upper blocks being spaced apart from each other in a substantially equal interval.