US Pat. No. 10,249,656

CHARGE PACKET SIGNAL PROCESSING USING PINNED PHOTODIODE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:an image pixel comprising a first pinned photodiode of a first dopant type, wherein the image pixel produces an output signal based an amount of charge in the first pinned photodiode of the first dopant type;
an output line coupled to the image pixel, wherein the output line conveys the output signal from the image pixel;
a charge integrator circuit that includes a plurality of charge transfer circuits that are coupled between a summing node and the output line coupled to the image pixel; and
a charge subtraction circuit that is coupled to the summing node and that includes an additional plurality of charge transfer circuits that contain a pinned photodiode of a second dopant type that is different from the first dopant type.

US Pat. No. 10,249,655

SENSOR, MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A sensor, comprising:a base substrate;
a thin-film transistor (TFT) disposed on the base substrate and including a source electrode;
a first insulation layer disposed on the TFT and provided with a first through hole running through the first insulation layer;
a conductive layer disposed in the first through hole and on part of the first insulation layer and electrically connected with the source electrode via the first through hole;
a bias electrode disposed on the first insulation layer and separate from the conductive layer;
a sensing active layer respectively connected with the conductive layer and the bias electrode;
an auxiliary conductive layer disposed on the conductive layer;
a passivation layer provided with a second through hole; and
a metal shield provided with a third through hole,
wherein in an direction perpendicular to the base substrate, the passivation layer is disposed between the source electrode and the first insulation layer; the second through hole is configured to run through the passivation layer and communicate with the first through hole; and the conductive layer is electrically connected with the source electrode via the first through hole and the second through hole;
wherein the metal shield is disposed between the passivation layer and the first insulation layer; the third through hole is configured to run through the metal shield and communicate with the first through hole and the second through hole; and the conductive layer is electrically connected with the source electrode via the first through hole, the second through hole and the third through hole.

US Pat. No. 10,249,654

MANUFACTURING METHOD OF TOP-GATE TFT AND TOP-GATE TFT

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method of top-gate thin film transistor (TFT), comprising the steps of:Step S1: providing a base substrate, a first insulating layer and a second insulating layer being deposited on the base substrate sequentially;
Step S2: providing a first mask, using the first mask to form a first photo-resist layer on the second insulating layer, using the first photo-resist layer as a shielding layer to etch the second insulating layer to form a first via and a second via separated with interval on the second insulating layer;
Step S3: etching the first insulating layer to form a through groove under the first via and the second via, and connecting the first via and the second via, the through groove, the first via, and the second via forming a vertical U-shaped trench;
Step S4: providing a semiconductor solution, coating the semiconductor solution over the vertical U-shaped trench, curing the semiconductor solution to form an active layer filling the vertical U-shaped trench; removing the first photo-resist layer;
Step S5: providing a second mask, using the second mask to patternize to form a source, a drain and a gate separated with intervals on the second insulating layer, the gate being disposed on the second insulating layer between the first via and the second via, and the source and the drain being disposed on two sides of the gate and respectively covering and contacting the active layer inside the first via and the second via.

US Pat. No. 10,249,653

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A display panel, comprising:a substrate layer;
a first metal layer formed on the substrate layer, wherein the first metal layer comprises a gate line;
a first insulating layer formed on the first metal layer;
a second metal layer formed on the first insulating layer, wherein the second metal layer and the gate line form a thin film transistor;
a color resist layer formed on the second metal layer, wherein a first channel is formed on the color resist layer corresponding to the gate line, the first channel having a first color resist block and a second color resist block therein, and the first color resist block and the second color resist block are spaced apart from each other;
a protective layer formed on the color resist layer and configured to protect the color resist layer; and
a light-shielding layer formed on the protective layer and aligned with the first channel, wherein the light-shielding layer comprises a base, a first protrusion corresponding to the first color resist block, and a second protrusion corresponding to the second color resist block, the first protrusion is configured as a main photo spacer, the second protrusion is configured as a sub photo spacer, and a height difference between the main photo spacer and the sub photo spacer relative to the base is formed;
wherein a second channel is formed on the protective layer corresponding to the second color resist block, the sub photo spacer is directly connected to the second color resist block, such that the height difference between the main photo spacer and the sub photo spacer is formed;
wherein the first color resist block and the second color resist block are connected to two sides of the second channel, respectively, a width of the first color resist block is greater than a width of the second color resist block, such that a thickness of the light-shielding layer disposed on the first color resist layer is greater than a thickness of the light-shielding layer disposed on the second color resist layer, to increase the height difference between the main photo spacer and the sub photo spacer; and
wherein each of the first color resist block and the second color resist block comprise at least one layer of color resist.

US Pat. No. 10,249,652

MANUFACTURING METHOD OF FLEXIBLE TFT SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of flexible TFT substrate, comprising the steps of:Step S1: providing a flexible base substrate, depositing a buffer layer on the flexible base substrate, depositing and patternizing to form an active layer on the buffer layer, depositing a gate insulating layer on the active layer and the buffer layer, depositing and patternizing to form a gate on the gate insulating layer;
Step S2: depositing a silicon oxide layer on the gate and the gate insulating layer, patternizing the silicon oxide layer and the gate insulating layer to form a first contact hole respectively to corresponding to above of each of two sides of the active layer and form a buffer hole above the base substrate with an interval from the first contact hole, the first contact hole penetrating the silicon oxide layer and the gate insulating layer to expose the two sides of the active layer, the buffer hole having a larger size than the first contact hole, and the buffer hole having a deeper depth than the first contact hole;
Step S3: coating an organic photo-resist material on the silicon oxide layer to form an organic photo-resist layer, the organic photo-resist material filling the buffer hole during coating, the silicon oxide layer and the organic photo-resist layer together forming an interlayer dielectric layer, patternizing the organic photo-resist layer to form connection holes above the first contact holes so as to expose the first contact holes;
Step S4: depositing and patternizing on the interlayer dielectric layer to form a source and a drain, the source and the drain contacting respectively the two sides of the active layer through the first contact holes and the connection holes.

US Pat. No. 10,249,651

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

2. A semiconductor device comprising:an insulating layer;
an oxide semiconductor film including a source region and a drain region over and in contact with the insulating layer;
a gate insulating film over the oxide semiconductor film; and
a gate electrode layer over the gate insulating film,
wherein the source region and the drain region include impurities,
wherein the oxide semiconductor film contains a crystal having a c-axis which is substantially perpendicular to a top surface of the oxide semiconductor film,
wherein an average surface roughness of a top surface of the insulating layer is greater than or equal to 0.05 nm and less than 0.5 nm, and
wherein the impurities are added into the source region and the drain region through the gate insulating film.

US Pat. No. 10,249,650

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a pixel including a semiconductor layer, a first conductive layer below the semiconductor layer, and a second conductive layer above the semiconductor layer; and
an under layer below the semiconductor layer,
wherein the semiconductor layer includes a channel region which overlaps at least one of the first conductive layer and the second conductive layer in a plan view,
the first conductive layer includes a first edge located on a side of an edge of the channel region in a direction of a channel length of the semiconductor layer,
the second conductive layer includes a second edge located on a side of the edge of the channel region, and
a position of the first edge in the direction of the channel length is different from a position of the second edge in the direction of the channel length in the plan view.

US Pat. No. 10,249,649

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A thin film transistor array substrate, comprising:a plurality of fan-out areas located in a non-display area of the thin film transistor array substrate, wherein a display area of the thin film transistor array substrate has a plurality of sub display areas corresponding to the fan-out areas respectively, and the sub display areas and the fan-out areas are arranged opposite each other;
a plurality of scanning lines extended along a first direction;
a plurality of data line combinations comprising a plurality of data lines extended along a second direction, wherein the first direction and the second direction are orthogonal to each other;
a plurality of common line combinations comprising a plurality of common lines crossing with the data lines, wherein a parasitic capacitor is formed on an overlapping area of the common line and the data line; and
a plurality of connecting line combinations, each of which is located in one of the fan-out areas, wherein the connecting line combinations comprise a plurality of connecting lines connecting to the data lines;
wherein a capacitance value of the parasitic capacitor formed from the data line connected to the connecting line with a larger resistance value and the corresponding common line is less than that of the parasitic capacitor formed from the data line connected to the connecting line with a smaller resistance value and the corresponding common line;
wherein the resistance value of the connecting line is gradually increased from an intermediate area of the fan-out area to two sides of the fan-out area;
wherein the connecting line located in the intermediate area of the fan-out area connects to the data line located in an intermediate area of the sub display area, and the connecting line located at the two sides of the fan-out area connects to the data line located at the two sides of the sub display area;
wherein a capacitance value of the parasitic capacitors formed from the data line combination and the common line combination are reduced from the intermediate area of the sub display area to the two sides of the sub display area;
wherein the common line comprises:
a first sub line being parallel to the data line; and
at least one second sub line being parallel to the scanning line;
wherein the second sub line and the scanning line are formed from a first metal layer, the first sub line and the data line are formed from a second metal layer, the first sub line and the second sub line are connected by a through hole, and the through hole is disposed through an insulating layer between the scanning line and the data line; and
wherein the parasitic capacitor is formed from the data line and the second sub line of the common line.

US Pat. No. 10,249,648

MANUFACTURING METHODS OF ARRAY SUBSTRATES AND ARRAY SUBSTRATES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, comprising:forming a buffer layer on a substrate, and patterning the buffer layer to form trenches defined within the patterned buffer layer;
forming a conductive layer on the patterned buffer layer and the trenches, and patterning the conductive layer such that portions of the patterned conductive layer within the trenches are used as a data line and a source respectively, and portions of the patterned conductive layer on the patterned buffer layer are used as a gate and a gate line respectively;
forming an insulation layer on the source, the data line, the gate, and the gate line, wherein at least one portion of the source and at least one portion of the gate line are exposed by the insulation layer;
forming a semiconductor layer on the source, wherein the semiconductor layer is electrically connected to the exposed portion of the source, and the semiconductor layer and the gate are electrically insulated via the insulation layer; and
forming a first pixel electrode and a second pixel electrode on the insulation layer, wherein the first pixel electrode is electrically connected to the semiconductor layer, and the second pixel electrode is electrically connected to the exposed portion of the gate line,
wherein the gate comprises a first gate electrode and a second gate electrode, and the first gate electrode and the second gate electrode are configured to be located at two sides of the source and be parallel to the source.

US Pat. No. 10,249,647

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE COMPRISING OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode layer;
a gate insulating layer;
an oxide semiconductor layer comprising a channel formation region adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium; and
source and drain electrode layers in electrical contact with the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a crystalline region including a crystal with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, and
wherein a c-axis of the crystal is oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

US Pat. No. 10,249,646

DISPLAY DEVICE FABRICATED WITH FEWER MASKS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device, comprising:a base substrate comprising a first light blocking area extending in a first direction, a second light blocking area extending in a second direction intersecting the first direction, and a pixel area defined by the first light blocking area and the second light blocking area;
a light blocking pattern on the base substrate, at least a portion of the light blocking pattern positioned at the first light blocking area;
a data line on the base substrate and positioned at the second light blocking area;
a first insulating layer on the light blocking pattern and the data line;
a semiconductor layer on the first insulating layer, the semiconductor layer overlapping the light blocking pattern on a plane;
a second insulating layer on the semiconductor layer;
a color filter on the second insulating layer, the color filter having an island shape and at least a portion of the color filter positioned at the pixel area;
a third insulating layer on the second insulating layer and the color filter;
a gate line on the third insulating layer and positioned at the first light blocking area;
a pixel electrode on the third insulating layer, at least a portion of the pixel electrode positioned at the pixel area; and
a bridge electrode on the third insulating layer, at least a portion of the bridge electrode positioned at the first light blocking area,
wherein the second insulating layer and the third insulating layer directly contact one another over the semiconductor layer.

US Pat. No. 10,249,645

SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor comprising:
an oxide semiconductor layer over a first insulating film;
a second insulating film over the oxide semiconductor layer;
a gate electrode over the second insulating film;
a third insulating film over the gate electrode;
a source electrode over the third insulating film; and
a drain electrode over the third insulating film,
wherein the source electrode is electrically connected to the oxide semiconductor layer, and
wherein the drain electrode is electrically connected to the oxide semiconductor layer, and
a capacitor comprising:
a first conductive layer;
the third insulating film over the first conductive layer; and
a second conductive layer over the third insulating film,
wherein the first insulating film comprises silicon and oxygen,
wherein the oxide semiconductor layer comprises a first portion being a channel region, a second portion, and a third portion between the first portion and the second portion,
wherein the gate electrode overlaps with the first portion,
wherein a part of the third insulating film overlaps with the third portion,
wherein a resistivity of the third portion is higher than a resistivity of the second portion.

US Pat. No. 10,249,644

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising a gate electrode over a substrate;
a first electrode electrically connected to the first transistor, the first electrode being a pixel electrode;
a second transistor comprising a first gate electrode over the substrate;
a second electrode overlapping with the first gate electrode of the second transistor;
a third electrode over the substrate, the third electrode being supplied with a fixed potential, and
a fourth electrode comprising a low-resistance oxide film over the substrate;
wherein the second electrode and the third electrode are formed by processing a same light-transmitting conductive film comprising a light-transmitting material,
wherein a first capacitor is formed in a region where the first electrode and the third electrode overlap with each other with an insulating film provided therebetween, and
wherein a second capacitor is formed in a region where the third electrode and the fourth electrode overlap with each other.

US Pat. No. 10,249,643

HARD COPIED SEMICONDUCTOR DEVICE HAVING A RESISTANCE-VARIABLE NON-VOLATILE ELEMENT

NEC CORPORATION, Minato-...

1. A semiconductor device hard-copied so as to have a same logical operation function as a reconfigurable circuit chip, comprising a resistance-variable non-volatile element formed inside a multi-layered wiring layer on a semiconductor substrate, the resistance-variable non-volatile element having an arbitrary logical operation function being programmed, wherein a lower wiring and an upper wiring planarly overlapping with each other are short-circuited at a portion where the resistance-variable non-volatile element of the reconfigurable circuit chip is programmed to a low-resistance state, and a lower wiring and an upper wiring planarly overlapping with each other are electrically insulated at a portion where the resistance-variable non-volatile element of the reconfigurable circuit chip is programmed to a high-resistance state.

US Pat. No. 10,249,642

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a substrate;
a stacked body that is provided on the substrate and includes a plurality of electrode layers separately from each other, each of the electrode layers extending in a first direction and in a second direction, the second direction intersecting the first direction, the electrode layers being stacked in a third direction, the third direction intersecting the first direction and the second direction; and
a plurality of pillar portions that are provided in the stacked body and extend in the third direction, the pillar portions collectively passing through each of the electrode layers,
wherein the pillar portions include a first column that are arranged along the first direction while being staggered, and a second column that are arranged along the first direction apart from the first column in the second direction while being staggered,
when viewed in the third direction,
a first virtual line is defined along the first direction, such that the first virtual line passes through each of the pillar portions of the first column, and
a second virtual line is defined along the first direction apart from the first virtual line in the second direction, such that the second virtual line passes through each of the pillar portions of the second column.

US Pat. No. 10,249,641

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a stacked body provided on a first-direction side of the substrate, the stacked body including first insulating films and electrode films, each of the first insulating films and each of the electrode films being stacked alternately along the first direction;
a semiconductor member extending in the first direction; and
a charge storage film provided between the stacked body and the semiconductor member,
a recess being made in a surface of the stacked body facing the semiconductor member every one of the electrode films,
wherein one of the first insulating films includes a protrusion at the surface of the stacked body facing the semiconductor member, the protrusion protruding toward the semiconductor member, and a thickness of the protrusion in the first direction becomes thinner toward a tip of the protrusion.

US Pat. No. 10,249,640

WITHIN-ARRAY THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor structure comprising:a memory-level assembly located over a substrate and including an alternating stack of insulating layers and composite layers, wherein the insulating layers and the composite layers alternate along a vertical direction that is perpendicular to a top surface of the substrate, wherein each of the composite layers comprises:
a respective electrically conductive layer; and
a respective spacer dielectric portion, wherein the respective electrically conductive layer and spacer dielectric portion are laterally adjoined to each other, and wherein each vertically neighboring pair of the spacer dielectric portions is vertically spaced apart from each other by a thickness of an intervening one of the insulating layers;
memory stack structures vertically extending through the alternating stack and each of the memory stack structures comprising:
a respective memory film; and
a respective vertical semiconductor layer that is laterally surrounded by the respective memory film; and
at least one through-memory-level via structure that vertically extends through each of the spacer dielectric portions and the insulating layers, wherein the at least one through-memory-level via structure extends below bottommost surfaces of the memory stack structures.

US Pat. No. 10,249,639

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a semiconductor substrate extending in a second direction and a third direction;
first and second memory columnar bodies disposed above the semiconductor substrate in a first direction and aligned in the second direction, the first direction intersecting the second and third directions, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction;
a bit line disposed above the first and second memory columnar bodies in the first direction;
a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line;
a first connecting portion disposed between the first memory columnar body and the first connecting line in the first direction and electrically coupled to the semiconductor layer of the first memory columnar body and the first connecting line; and
a second connecting portion disposed between the second memory columnar body and the first connecting line in the first direction and electrically coupled to the semiconductor layer of the second memory columnar body and the first connecting line, wherein
the first connecting line extends linearly in the second direction, and a center line widthwise of the first connecting line is in a position displaced in the third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies, and
a center of the first connecting portion is in a position displaced in the third direction from the center of the first memory columnar body.

US Pat. No. 10,249,638

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a memory region arranged in a semiconductor substrate; and
a capacitive element region arranged in the semiconductor substrate,
wherein memory cells in the memory region comprise:
a plurality of first protrusions formed by parts of the semiconductor substrate, each of the first protrusions protruding from a main surface of the semiconductor substrate in a first direction and having a width in a second direction, the first protrusions extending in a third direction that intersects the second direction and being arranged along the second direction;
a plurality of first gate electrodes, each of the first gate electrodes being arranged with a first gate insulating film interposed between the first protrusion and the first gate electrode, the first gate electrodes extending in the second direction and being arranged along the third direction;
a plurality of second gate electrodes, each of the second gate electrodes being arranged with a second gate insulating film interposed between the first protrusion and the second gate electrode, each of the second gate electrodes being adjacent to a side surface of each of the first gate electrodes via the second gate insulating film, the second gate electrodes extending in the second direction and being arranged along the third direction; and
a first semiconductor region and a second semiconductor region provided in the first protrusion so as to sandwich therebetween the first gate electrode and the second gate electrode that are adjacent to each other, via the second gate insulating film,
wherein a capacitive element in the capacitive element region comprises:
a plurality of second protrusions formed by parts of the semiconductor substrate, each of the second protrusions protruding from the main surface of the semiconductor substrate in the first direction and having a width in the second direction, the second protrusions extending in the third direction and being arranged along the second direction;
a plurality of first capacitor electrodes, each of the first capacitor electrodes being arranged with an insulating film interposed between the second protrusion and the first capacitor electrode, the first capacitor electrodes extending in the second direction and being arranged along the third direction; and
a plurality of second capacitor electrodes, each of the second capacitor electrodes being arranged with a capacitive insulating film interposed between the second protrusion and the second capacitor electrode, each of the second capacitor electrodes being adjacent to a side surface of each of the first capacitor electrodes via the capacitive insulating film, the second capacitor electrodes extending in the second direction and being arranged along the third direction,
wherein the first gate electrodes and the first capacitor electrodes are formed of a first conductive film,
wherein the second gate electrodes and the second capacitor electrodes are formed of a second conductive film, and
wherein a distance between the adjacent second protrusions is smaller than a distance between the adjacent first protrusions.

US Pat. No. 10,249,637

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

MIE FUJITSU SEMICONDUCTOR...

1. A manufacturing method of a semiconductor device comprising a first transistor, a second transistor, a third transistor, and a flash memory transistor on a semiconductor substrate, the manufacturing method comprising:forming an element isolation that demarcates each of regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
forming a well and a channel in each of the regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
forming a tunnel oxide layer and a charge-storage layer in the region of the flash memory transistor;
forming a first oxide film in each of the regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
removing the first oxide film in the regions of the first transistor and the second transistor;
forming a third oxide film by adding a first oxide layer between the first oxide film and the semiconductor substrate in the region of the third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidizing the semiconductor substrate;
removing the second oxide film in the region of the first transistor;
forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidizing the semiconductor substrate, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor;
forming a gate electrode in each of the regions of the first transistor, the second transistor, the third transistor, and the flash memory transistor;
forming a sidewall film on sidewalls on both sides of the gate electrode; and
forming a source region and a drain region in the semiconductor substrate at side portions on both sides of the gate electrode.

US Pat. No. 10,249,636

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a vertical memory device, the method comprising:forming a support layer on a substrate;
alternately forming sacrificial layers and insulation layers on the support layer in a first direction perpendicular to an upper surface of the substrate;
forming a channel hole and a dummy channel hole through the support layer, the sacrificial layers and the insulation layers,
the dummy channel hole exposing the upper surface of the substrate;
removing a part of the support layer exposed by the channel hole and the dummy channel hole to enlarge lower portions of the channel hole and the dummy channel holes so that the channel hole and the dummy channel hole are in communication with each other, a remaining portion of the support layer forming a support pattern;
forming a channel filling the channel hole;
forming a dummy channel filling the dummy channel hole;
forming an opening through the support pattern, the insulation layers and the sacrificial layers to expose the upper surface of the substrate, the forming the opening through the support pattern including transforming the insulation layers and the sacrificial layers into insulation patterns and sacrificial patterns, respectively;
removing the sacrificial patterns to form a plurality of first gaps; and
forming gate electrodes to fill the first gaps, respectively.

US Pat. No. 10,249,635

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a substrate;
a first insulating layer provided on the substrate;
a conductive layer provided above the first insulating layer;
a first wiring layer extending in a first direction, the first wiring layer being provided in a layer above the conductive layer;
a second wiring layer being provided in the layer, the second wiring layer being arranged apart from the first wiring layer in a second direction crossing the first direction and extending in the first direction;
a third wiring layer being provided between the conductive layer and the first wiring layer, and extending in the first direction;
a fourth wiring layer being provided between the conductive layer and the second wiring layer, and extending in the first direction;
a first signal line extending in a third direction crossing the first and second directions to electrically contact with the conductive layer;
a second signal line being arranged apart from and adjacent to the first signal line in the second direction, the second signal line extending in the third direction to electrically contact with the conductive layer;
a first select transistor being provided to the first signal line, a gate electrode of the first select transistor being electrically connected to the first wiring layer;
a second select transistor being provided to the second signal line, a gate electrode of the second select transistor being electrically connected to the second signal line;
a second insulator provided between the first signal line and the second signal line;
a first contact being electrically connected to the first wiring layer, the first contact extending in the third direction;
a second contact being electrically connected to the second wiring layer, the second contact being provided apart from the first contact via the second insulating layer in the first direction, the second contact extending in the third direction;
a third contact being electrically connected to the third wiring layer, the third contact extending in the third direction; and
a fourth contact being electrically connected to the fourth wiring layer, the fourth contact being provided apart from the third contact via the second insulating layer in the first direction, the fourth contact extending in the third direction,
wherein the first contact is provided at a different location from the second contact in the second direction.

US Pat. No. 10,249,634

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a stack;
channel layers each comprising channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern disposed below the stack and coupling the channel patterns with the dummy channel patterns;
a bit line coupled with the channel patterns;
a well pick-up line coupled with the dummy channel patterns; and
an gap fill insulating layer comprising a base part disposed below the stack, first protrusions protruding from the base part and passing through the channel patterns, and second protrusions protruding from the base part and passing through the dummy channel patterns.

US Pat. No. 10,249,633

FLASH MEMORY DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit product, comprising:a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned above said semiconductor bulk substrate, and a semiconductor layer positioned above said buried insulating layer; and
a flash memory device positioned in a first area of said SOI substrate, said flash memory device comprising:
a flash transistor device comprising a floating gate, an insulating layer positioned above said floating gate, and a control gate positioned above said insulating layer, said floating gate comprising a portion of said semiconductor layer; and
a read transistor device comprising a gate dielectric layer positioned above said semiconductor bulk substrate and a read gate electrode positioned above said gate dielectric layer; and
a fully depleted silicon-on-insulator (FDSOI) transistor device positioned in a second area of said SOI substrate that is electrically isolated from said first area, wherein said FDSOI transistor device comprises a second portion of said semiconductor layer, a high-k gate dielectric layer positioned above said second portion of said semiconductor layer, and a first metal gate layer positioned above said high-k gate dielectric layer.

US Pat. No. 10,249,632

SIMPLE INTEGRATION OF NON-VOLATILE MEMORY AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

International Business Ma...

1. A method of forming a semiconductor structure comprising:providing a structure comprising a first gate cavity exposing a channel region of a first semiconductor material portion located in a first device region of a substrate, a second gate cavity exposing a channel region of a second semiconductor material portion located in a second device region of the substrate, and a third gate cavity exposing a channel region of a third semiconductor material portion located in a third device region of the substrate, wherein the first gate cavity, the second gate cavity and the third gate cavity are laterally surrounded by an interlevel dielectric (ILD) layer;
forming a first high-k dielectric layer along sidewalls and bottom surfaces of the first, the second and the third gate cavities and on a top surface of the ILD layer;
forming a capping material layer on the first high-k dielectric layer;
patterning the capping material layer and the first high-k dielectric layer to remove a portion of each of the capping material layer and the first high-k dielectric layer from the third device region, wherein the patterning provides a patterned capping material layer and a patterned first high-k dielectric layer covering the first device region and the second device region, and a portion of the ILD layer and the third gate cavity in the third device region are exposed;
forming a second high-k dielectric layer on the patterned capping material layer, the exposed portion of the ILD layer and along the sidewall and the bottom surface of the third gate cavity;
patterning the second high-k dielectric layer and the patterned capping material layer to remove a portion of each of the second high-k dielectric layer and the patterned capping material layer from the first device region, wherein the patterning provides a patterned second high-k dielectric layer covering the second device region and the third device region and a capping material portion solely in the second device region, and a portion of the patterned first high-k dielectric layer in the first device region is exposed; and
depositing a conductive material layer on the patterned first high-k dielectric layer and the patterned second high-k dielectric layer to completely fill the first, the second and the third gate cavities.

US Pat. No. 10,249,631

SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING METAL GATES

Silicon Storage Technolog...

1. A memory device, comprising:a silicon substrate having an upper surface, wherein:
the upper surface is planar in a memory cell area of the silicon substrate,
the upper surface includes an upwardly extending silicon fin in a logic device area of the silicon substrate, and
the silicon fin includes a pair of side surfaces extending up and terminating at a top surface;
a logic device in the logic device area, comprising:
spaced apart first source and first drain regions formed in the silicon substrate with a first channel region of the silicon substrate extending there between, wherein the first channel region extends along the top surface and the pair of side surfaces, and
a conductive logic gate disposed over and insulated from the top surface, and disposed laterally adjacent to and insulated from the pair of side surfaces;
a memory cell in the memory cell area, comprising:
spaced apart second source and second drain regions formed in the silicon substrate with a second channel region of the silicon substrate extending there between,
a conductive floating gate disposed over and insulated from a first portion of the second channel region that is adjacent the second source region,
a conductive word line gate disposed over and insulated from a second portion of the second channel region that is adjacent the second drain region,
a conductive control gate disposed over and insulated from the floating gate, and
a conductive erase gate disposed over and insulated from the second source region.

US Pat. No. 10,249,630

STRUCTURE FEATURING FERROELECTRIC CAPACITANCE IN INTERCONNECT LEVEL FOR STEEP SUB-THRESHOLD COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:forming a first functional gate stack on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack on a second body region of a second semiconductor material portion located in a second region of the substrate, wherein the first functional gate stack and the second functional gate stack are laterally surrounded by an interlevel dielectric (ILD) layer;
forming a contact level dielectric layer over the ILD layer, the first functional gate stack and the second functional gate stack;
forming a gate interconnect opening extending through the contact level dielectric layer, the gate interconnect opening exposing a portion of the first functional gate stack located outside the first semiconductor material portion and a portion of the second functional gate stack located outside the second semiconductor material portion; and
forming a ferroelectric gate interconnect structure in the gate interconnect opening, wherein the ferroelectric gate interconnect structure vertically contacts the portion of the first functional gate stack located outside the first semiconductor material portion and the portion of the second functional gate stack located outside the second semiconductor material portion.

US Pat. No. 10,249,629

METHOD FOR FORMING BURIED WORD LINES

UNITED MICROELECTRONICS C...

1. A method for forming buried word lines; comprising:providing a substrate, having a plurality of shallow trench isolations disposed therein;
forming a first oxide layer on the substrate;
forming a plurality of first patterned material layers on the first oxide layer, wherein a plurality of first recesses are disposed between every two adjacent first patterned material layers respectively;
forming a second patterned material layer in the first recesses;
forming a second oxide layer in the first recesses and covering at least two sidewalls of each of the first patterned material layers;
performing a first etching step to remove a portion of the first oxide layer and a portion of the second oxide layer, wherein the remaining first oxide layer and the remaining second oxide layer are defined as a plurality of oxide masks; and
using the first patterned material layers and the second patterned material layer as the protect layers, performing a second etching process, to form a plurality of second recesses in the substrate.

US Pat. No. 10,249,628

SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a device isolation region defining an active region in a substrate; and
gate structures buried in the active region of the substrate,
wherein at least one of the gate structures comprises:
a gate trench;
a gate insulating layer formed on the entire inner wall of the gate trench;
a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench;
a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench; and
a gate capping insulating layer formed on the gate electrode pattern and the gate barrier pattern to fill the upper portion of the gate trench,
wherein the gate barrier pattern has a top surface which is lower than a top of the gate electrode pattern,
wherein the top surface of the gate barrier pattern is in contact with an insulating layer.

US Pat. No. 10,249,627

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

15. A semiconductor device, comprising:a first interlayer insulating layer disposed on a substrate;
a second interlayer insulating layer on the first interlayer insulating layer;
a first support layer between the first interlayer insulating layer and the second interlayer insulating layer;
a second support layer on an upper surface of the second interlayer insulating layer;
a first electrode disposed on the substrate and spaced apart from the first and second interlayer insulating layers;
a contact structure disposed on the substrate and penetrating the first interlayer insulating layer, the first support layer, the second interlayer insulating layer and the second support layer;
a dielectric conformally covering the first electrode; and
a second electrode on the dielectric; and
a space between the first electrode and a side surface of the second interlayer insulating layer opposing the first electrode,
wherein a portion of the second electrode is disposed inside the space,
wherein a portion of the dielectric surrounds the second electrode inside the space and is in contact with the side surface of the second interlayer insulating layer, and
wherein the second support layer includes a first portion covering an upper surface of the second interlayer insulating layer and surrounding an upper side surface of the contact structure, and a second portion being disposed in a same plane as the first portion and contacting a portion of an upper side surface of the first electrode.

US Pat. No. 10,249,626

SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTILAYER WIRING LAYER

Semiconductor Energy Labo...

1. A semiconductor memory device comprising:a driver circuit; and
a memory cell over the driver circuit, the memory cell comprising:
a transistor; and
a capacitor over the transistor, the capacitor comprising:
a first layer comprising a first conductive material, the first layer electrically connected to one of a source and a drain of the transistor; and
a second layer over the first layer, the second layer comprising a second conductive material,
wherein the first layer has a concave shape,
wherein the first layer comprises a first portion and a second portion,
wherein the second layer comprises a portion,
wherein the portion of the second layer overlaps with the first portion of the first layer,
wherein a bottom surface of the portion of the second layer is below a top surface of the second portion of the first layer, and
wherein the memory cell is electrically connected to the driver circuit.

US Pat. No. 10,249,625

COATED PRINTED ELECTRONIC DEVICES EXHIBITING IMPROVED YIELD

XEROX CORPORATION, Norwa...

1. A coated, printed electronic device comprising:a plurality of contact pads arranged in a pattern,
a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads,
a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers, and
a protective layer covering the plurality of electrode traces and extending laterally beyond each edge of each electrode trace to provide a buffer zone surrounding each electrode trace, the buffer zone extending from an end of each electrode trace to cover a portion of each associated contact pad in an overlapping region, wherein each contact pad also has at least one uncovered edge, wherein the buffer zone is characterized by a buffer zone width which is no more than 2*?2*(line registration capability) in the overlapping region.

US Pat. No. 10,249,624

SEMICONDUCTOR STRUCTURE CONTAINING LOW-RESISTANCE SOURCE AND DRAIN CONTACTS

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:providing a structure comprising at least one first functional gate structure located on a first semiconductor material portion within a pFET device region of a semiconductor substrate and at least one second functional gate structure located on a second semiconductor material portion within an nFET device region of the semiconductor substrate, wherein a first epitaxial semiconductor material is located on each side of said at least one first functional gate structure and in contact with a surface of said first semiconductor material portion, and a second epitaxial semiconductor material is located on each side of said at least one second functional gate structure and in contact with a surface of said second semiconductor material portion, and wherein a high k dielectric layer is located on a topmost surface and a sidewall surface of said first epitaxial semiconductor material, and laterally surrounding a sidewall of said least one first functional gate structure;
forming a layer of a dipole metal or a metal-insulator-semiconductor oxide on said second epitaxial semiconductor material, but not said first epitaxial semiconductor material;
removing, by etching, said high k dielectric layer from a portion of said topmost surface of said first epitaxial semiconductor material to physically expose a portion of said first epitaxial semiconductor material; and
forming a first metal semiconductor alloy on said physically exposed portion of said first epitaxial semiconductor material and a second metal semiconductor alloy in direct contact with said layer of said dipole metal or said metal-insulator-semiconductor oxide.

US Pat. No. 10,249,623

SEMICONDUCTOR INTEGRATED CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit comprising:a semiconductor substrate having a plurality of first potential side areas, the plurality of first potential side area including a first two adjacent first potential side areas, each first potential side area including:
a high potential side circuit;
a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate;
a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, the second semiconductor region penetrating the first semiconductor region in a depth direction from the front surface of the semiconductor substrate; and
a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region, a potential of the third semiconductor region being fixed at a potential higher than a potential of the second semiconductor region, the high potential side circuit being arranged to be closer to a center of the first semiconductor region than the third semiconductor region, wherein
the first two adjacent first potential side areas includes respective first side areas that face each other, that each include the third semiconductor region thereof, and that each are free of the second semiconductor region thereof.

US Pat. No. 10,249,622

EPITAXIAL OXIDE FIN SEGMENTS TO PREVENT STRAINED SEMICONDUCTOR FIN END RELAXATION

International Business Ma...

1. A semiconductor device comprising:a plurality of fin structures having a uniform strain extending from edge to edge of each fin structure in said plurality of fin structures;
an epitaxial oxide present in a gate cut opening present between edges of said plurality of fin structures, the epitaxial oxide having a composition comprising lanthanum and yttrium;
a gate structure present on a channel region of the fin structures having the uniform strain; and
source and drain regions formed on opposing sides of the channel region.

US Pat. No. 10,249,621

DUMMY CONTACTS TO MITIGATE PLASMA CHARGING DAMAGE TO GATE DIELECTRICS

TEXAS INSTRUMENTS INCORPO...

11. A metal-oxide-semiconductor (MOS) integrated circuit (IC), comprising:a substrate having a semiconductor surface;
a plurality of MOS transistors each including a source, a drain, and a gate stack on said semiconductor surface including a gate electrode over a gate dielectric on active areas defined by a field dielectric on said substrate;
a plurality of dummy gate stacks including first dummy gate stacks and second dummy gate stacks, each of said first and second dummy gate stacks including a dummy gate electrode over a dummy gate dielectric, said first dummy gate stacks disposed on dummy portions of said active area and said second dummy gate stacks disposed on a field oxide region of said field dielectric, wherein each of said second dummy gate stacks is disposed only on said field oxide region so as to be separated from said substrate;
a pre-metal dielectric (PMD) layer over said gate electrodes of said plurality of gate stacks and over said dummy gate electrodes of said first and second dummy gate stacks;
contact openings through said PMD layer including active contacts and dummy contacts, said active contacts and said dummy contacts both filled with a plug material;
a patterned metal 1 (M1) layer including first M1 portions over said active contacts and dummy M1 portions over said dummy contacts, and
at least one patterned metal upper level above said patterned M1 layer;
a plurality of vias including first vias that connect said at least one patterned metal upper level to said first M1 portions, and dummy vias that connect said at least one patterned metal upper level to said dummy M1 portions; and
interconnects that connect said active contacts to said MOS transistors, and wherein said dummy contacts are not electrically connected by said interconnects to said MOS transistors and land on said dummy portions of said active area between adjacent ones of said first dummy gate stacks, said dummy portions of said active areas lacking source/drain implants.

US Pat. No. 10,249,620

SEMICONDUCTOR DEVICE AND POWER AMPLIFIER CIRCUIT

Murata Manufacturing Co.,...

1. A semiconductor device comprising:a semiconductor substrate including first and second main surfaces opposing each other;
a first bipolar transistor that is formed, without a resistor layer, on the first main surface of the semiconductor substrate and includes a first emitter layer; and
a second bipolar transistor that is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer, the resistor layer being stacked on the second emitter layer in a direction normal to the first main surface;
wherein:
in the first bipolar transistor, a first contact layer is stacked on the first emitter layer in the direction normal to the first main surface;
in the second bipolar transistor, a second contact layer is stacked on the second emitter layer, and a third contact layer having a multilayered structure is stacked on the resistor layer, in the direction normal to the first main surface; and
in the second bipolar transistor, a tunneling barrier layer is inserted between the second contact layer and the resistor layer.

US Pat. No. 10,249,619

POWER SEMICONDUCTOR DEVICE HAVING TRENCH GATE TYPE IGBT AND DIODE REGIONS

Mitsubishi Electric Corpo...

1. A power semiconductor device having an IGBT region and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising:a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including,
a first layer of a first conductivity type that is provided on said second surface and is at least partially included in said diode region,
a second layer of said first conductivity type that is in contact with said first layer in said diode region, and
a third layer of a second conductivity type that is provided on said first surface and away from said second surface, is at least partially included in said diode region, and is in contact with said second layer, said second conductivity type being different from said first conductivity type;
an interlayer insulating film that is provided on said first surface of said semiconductor substrate and has a diode opening that exposes part of said third layer;
a first electrode that is provided on said interlayer insulating film and is in contact with said third layer through said diode opening; and
a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said first layer,
wherein said third layer includes a first region, a second region that is disposed away from said first region, and a diffusion region that connects said first region and said second region, said second region having a higher impurity concentration than an impurity concentration of said first region and said diffusion region having a lower impurity concentration than impurity concentrations of said first region and said second region when impurities in a direction parallel to said first surface of said semiconductor substrate are compared, and
wherein said first electrode is in contact with only said second region of said third layer.

US Pat. No. 10,249,618

POWER SEMICONDUCTOR DEVICE HAVING TRENCH GATE TYPE IGBT AND DIODE REGIONS

Mitsubishi Electric Corpo...

1. A power semiconductor device having an IGBT region that includes a plurality of cells, and a diode region for reverse conduction of said IGBT region, the power semiconductor device comprising:a semiconductor substrate having a first surface and a second surface opposite said first surface, said first surface having a portion included in said IGBT region and a portion included in said diode region, said semiconductor substrate including,
a first layer of a first conductivity type that is provided on said second surface and is at least partially included in said diode region,
a second layer of said first conductivity type that is in contact with said first layer in said diode region, and
a third layer of a second conductivity type that is provided on said first surface and away from said second surface, is at least partially included in said diode region, and is in contact with said second layer, said second conductivity type being different from said first conductivity type;
an interlayer insulating film that is provided on said first surface of said semiconductor substrate and has a diode opening that exposes part of said third layer;
a first electrode that is provided on said interlayer insulating film and is in contact with said third layer through said diode opening; and
a second electrode that is provided on said second surface of said semiconductor substrate and is in contact with said first layer,
wherein said third layer includes a first region and a plurality of second regions, said first region being provided on the whole of said first surface in said diode region, said plurality of second regions being spaced from each other on said first region, and said plurality of second regions having a higher impurity concentration than an impurity concentration of said first region when impurity concentrations in a direction parallel to said first surface of said semiconductor substrate are compared, and
wherein said first electrode is in contact with only said plurality of second regions of said third layer.

US Pat. No. 10,249,617

TUNABLE DEVICE HAVING A FET INTEGRATED WITH A BJT

Skyworks Solutions, Inc.,...

1. A continuous tunable inductive capacitive resonator comprising:a bipolar junction transistor including a base and an emitter;
a field effect transistor integrated with at least a portion of the bipolar junction transistor, at least one of a back gate or a front gate of the field effect transistor sharing an electrical connection with the base of the bipolar junction transistor, a reverse voltage applied to the at least one of the back gate or the front gate of the field effect transistor creating a continuously variable capacitance in a channel of the field effect transistor; and
an inductor arranged to experience a capacitance that varies with the reverse voltage applied to the at least one of the back gate or the front gate of the field effect transistor, the front gate of the field effect transistor electrically connected to the back gate of the field effect transistor.

US Pat. No. 10,249,616

METHODS OF FORMING A RESISTOR STRUCTURE BETWEEN ADJACENT TRANSISTOR GATES ON AN INTEGRATED CIRCUIT PRODUCT AND THE RESULTING DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a resistor on an integrated circuit product, comprising:forming first and second adjacent gates above a semiconductor substrate, each of said first and second adjacent gates comprising a gate structure and a gate cap, said first and second adjacent gates having a space there between;
forming a conductive resistor structure in said space between said first and second adjacent gates by,
depositing a layer of conductive resistor material so as to overfill said space between said first and second adjacent gates;
performing a planarization process to remove portions of said layer of conductive resistor material positioned outside of said space so as to form an initial structure that comprises said conductive resistor material in said space, said initial structure comprising an initial thickness and an initial upper surface that us substantially planar with an uppermost surface of said gate caps of said first and second adjacent gates; and
performing a recess etching process on said initial structure so as to reduce said initial thickness and thereby form said conductive resistor structure, wherein said conductive resistor structure comprises said conductive resistor material and a recessed uppermost surface that is positioned at a level that is below a level of said uppermost surface of said gate caps of said first and second adjacent gates; and
forming first and second separate conductive resistor contact structures, each of which is conductively coupled to said conductive resistor structure.

US Pat. No. 10,249,615

MISHFET AND SCHOTTKY DEVICE INTEGRATION

NXP USA, INC., Austin, T...

1. A semiconductor device comprising: a substrate; first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate; a gate comprising a second metal layer supported by the substrate and disposed in a first opening in the first dielectric layer, the second dielectric layer being disposed between the gate and the substrate to form a metal-insulator gate configuration at a surface of the substrate; an electrode comprising a first metal layer, supported by the substrate, disposed in a second opening in the first and second dielectric layers, and disposed at the surface of the substrate and configured to establish a Schottky junction with the substrate; an inter-layer dielectric layer disposed over the electrode and first and second dielectric layers, wherein the gate is disposed within an opening in the inter-layer dielectric layer; and a field plate supported by the substrate, separate and distinct from the electrode, disposed adjacent the electrode, wherein the field plate comprises the second metal layer, and wherein the inter-layer dielectric layer is disposed between the field plate and the electrode.

US Pat. No. 10,249,614

SEMICONDUCTOR DEVICE

MACRONIX International Co...

1. A semiconductor device, comprising:a gate structure located on a substrate;
a first doped region of a first conductivity type located in the substrate on a first side of the gate structure, wherein the first doped region partially overlaps with the gate structure in top view at the first side of the gate structure but not at a second side of the gate structure;
a plurality of second doped regions of a second conductivity type located in the first doped region, wherein the second doped regions are separated from each other and are aligned with each other in a first direction;
a third doped region of the first conductivity type located in the substrate on the second side of the gate structure; and
a plurality of fourth doped regions of the second conductivity type each entirely located in the third doped region in top view, wherein the third doped region has therein only a single column of the plurality of fourth doped regions, the fourth doped regions are separated from each other and are aligned with each other in the first direction, the second doped regions are not aligned with the fourth doped regions in a second direction perpendicular to the first direction, the first doped region and the second doped regions are a source region, and the third doped region and the fourth doped regions are a drain region.

US Pat. No. 10,249,613

ELECTROSTATIC DISCHARGE DEVICE AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY PANEL AND DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An electrostatic discharge device, comprising: a transistor with one of its source and drain serving as an input terminal of said electrostatic discharge device and the other of its source and drain serving as an output terminal of said electrostatic discharge device,wherein said transistor comprises:
a first conductive layer used as a first floating gate;
a first insulating layer covering said first conductive layer;
an active layer disposed on said first insulating layer;
a second insulating layer covering said active layer;
a second conductive layer used as a second floating gate and disposed on said second insulating layer;
a third insulating layer covering said second conductive layer; and
a third conductive layer and a fourth conductive layer disposed on said third insulating layer and on both sides of the active layer, said third conductive layer and fourth conductive layer being isolated from each other;
wherein said third conductive layer serves as one of the source and the drain and said fourth conductive layer serves as the other of the source and the drain;
said first conductive layer, said third conductive layer, and said first insulating layer, second insulating layer and third insulating layer disposed between said first conductive layer and said third conductive layer form a first capacitor;
said first conductive layer, said fourth conductive layer, and said first insulating layer, second insulating layer and third insulating layer disposed between said first conductive layer and said fourth conductive layer form a second capacitor;
said second conductive layer, said third conductive layer, and said third insulating layer disposed between said second conductive layer and said third conductive layer form a third capacitor;
said second conductive layer, said fourth conductive layer, and said third insulating layer disposed between said second conductive layer and said fourth conductive layer form a fourth capacitor.

US Pat. No. 10,249,612

SEMICONDUCTOR DEVICE INCLUDING SELF-PROTECTING CURRENT SENSOR

Infineon Technologies AG,...

1. A semiconductor device comprising a semiconductor body having a first surface and a second surface opposite to the first surface, the semiconductor body comprising:a load current component comprising a load current transistor area; and
a sensor component comprising a sensor transistor area,
wherein the sensor component is operable to supply a current proportional to a load current flowing through the load current component,
wherein the sensor transistor area is at least partly surrounded by the load current transistor area, or arranged at a boundary portion of one or more sides of the load current transistor area,
wherein the sensor transistor area comprises first and third transistor area parts differing from a second transistor area part between the first and the third transistor area parts by a sensor transistor area element being absent in the second transistor area part,
wherein the second transistor area part is electrically disconnected from a parallel connection of the first and the third transistor area parts by the sensor transistor area element being absent in the second transistor area part.

US Pat. No. 10,249,611

DIODE STRING CONFIGURED WITH GUARD RING SILICON-CONTROLLED RECTIFIER FOR NEGATIVE ELECTROSTATIC DISCHARGE PROTECTION

Silicon Laboratories Inc....

1. A semiconductor circuit, comprising:an N-well structure formed in a substrate, wherein said N-well structure is electrically coupled to a positive voltage node;
a plurality of N+ doped regions formed in and distributed across said N-well structure each coupled to said positive voltage node;
a diode string comprising a plurality of NPN transistor diode structures formed in said N-well structure and electrically coupled in series having a first diode structure disposed at a first end of said diode string and a last diode structure disposed at a second and opposite end of said diode string, and wherein each of said plurality of diode structures is disposed between a corresponding consecutive pair of said plurality of N+ doped regions; and
a P+ guard ring comprising at least one P+ doped structure formed in said N-well structure disposed on either side of said first diode structure and electrically coupled to a reference voltage node, wherein said P+ guard ring forms a silicon-controlled rectifier (SCR) with said first diode structure.

US Pat. No. 10,249,610

IGBT COUPLED TO A REVERSE BIAS DEVICE IN SERIES

TEXAS INSTRUMENTS INCORPO...

1. An electrostatic discharge (ESD) device comprising:an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and
at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

US Pat. No. 10,249,609

APPARATUSES FOR COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES

Analog Devices, Inc., No...

1. An integrated circuit device, comprising:a first bipolar junction transistor (BJT);
a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), wherein a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT;
a triggering device comprising a first triggering device configured to provide a triggering current to the base of the first BJT; and
a third BJT cross-coupled with the second BJT to operate as a second SCR, wherein the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.

US Pat. No. 10,249,608

ESD PROTECTION CIRCUIT

Qorvo US, Inc., Greensbo...

1. An electrostatic discharge protection circuit comprising:delay circuitry coupled between a supply voltage node and a fixed voltage node;
latch circuitry comprising:
current-limiting circuitry; and
a latch; wherein
the current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node;
the current-limiting circuitry is coupled to the delay circuitry, and
the current-limiting circuitry comprises a gallium arsenide transistor and a diode coupled in series with the gallium arsenide transistor and the latch; and
discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

US Pat. No. 10,249,607

INTERNALLY STACKED NPN WITH SEGMENTED COLLECTOR

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:a substrate including a semiconductor material; and
a stacked NPN bipolar transistor pair (stacked NPN), including:
a first NPN bipolar transistor (first NPN), including a first collector including collector segments of a first n-type semiconductor material in the substrate; and
a second NPN bipolar transistor (second NPN), including a second collector coupled to a first emitter of the first NPN, and a second emitter including a second n-type semiconductor material in the substrate;
wherein:
each collector segment has an orientation direction that points to the second emitter;
adjacent collector segments are laterally separated by collector separators, the collector separators electrically isolating the adjacent collector segments from each other;
said each collector segment is continuous along the orientation direction of said each collector segment; and
the collector segments are located on at least two opposite sides of the second emitter.

US Pat. No. 10,249,606

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Yokohama...

1. A semiconductor device comprising:a first domain that includes a first high power source line, a first low power source line, and a first power clamp circuit provided between the first high power source line and the first low power source line;
a second domain that include a second high power source line separated from the first high power source line, a second low power source line separated from the first low power source line, and a second power clamp circuit provided between the second high power source line and the second low power source line;
a third power clamp circuit provided between the second high power source line and the first low power source line;
a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and
a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein
the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line,
wherein
the first relay circuit is a level shifter,
the first relay circuit includes a first complementary signal generation circuit that is connected to the first high power source line and the first low power source line, and that generates a complementary signal of a signal from the first domain, and
the first relay circuit includes a first differential circuit that is connected to the second high power source line and the first low power source line, that receives a complementary signal from the first complementary signal generation circuit, and that outputs a first output to the second domain.

US Pat. No. 10,249,605

INTEGRATED CIRCUIT DEVICES

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit device comprising at least one standard cell, wherein the at least one standard cell comprises:a first active region and a second active region respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction;
a first gate line and a second gate line extending parallel to each other in a second direction perpendicular to the first direction across the first active region and the second active region, wherein the first gate line comprises a first portion of the first gate line and a second portion of the first gate line, and the second gate line comprises a first portion of the second gate line and a second portion of the second gate line;
a first detour interconnection structure configured to electrically connect the first portion of the first gate line on the first active region with the second portion of the second gate line on the second active region; and
a second detour interconnection structure configured to electrically connect the first portion of the second gate line on the first active region with the second portion of the first gate line on the second active region,
wherein the first and second detour interconnection structures comprise a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via on at least one of the first active region and the second active region to connect the lower interconnection layer with the upper interconnection layer.

US Pat. No. 10,249,604

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a base substrate; and
a semiconductor chip on the base substrate, the semiconductor chip being an individual semiconductor chip, the semiconductor chip including:
a first layer structure and a second layer structure opposite to the first layer structure, the second layer structures is a semiconductor device portion, and
a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—Sn) compound portion and a nickel-tin (Ni—Sn) compound portion above and below the Ag—Sn compound portion, the Ag—Sn compound portion and the Ni—Sn compound portion having a same width in a horizontal direction such that edge portions of the Ag—Sn compound portion are exposed and edge portions of the Ni—Sn compound portion are exposed,
wherein the first layer structure is a chip substrate including a semiconductor substrate,
wherein the chip substrate including the semiconductor substrate is between the base substrate and the semiconductor device portion, and
wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding structure between the chip substrate and the semiconductor device portion.

US Pat. No. 10,249,603

PIXEL STRUCTURE, DISPLAY DEVICE INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE

SAMSUNG DISPLAY CO., LTD....

1. A pixel structure, comprising:a base substrate;
a plurality of first electrodes arranged in an upper portion of the base substrate;
a plurality of second electrodes each having a circular shape extending along a circumferential direction around an outer edge of one first electrode such that one second electrode surrounds the at least one first electrode; and
a plurality of LED elements connected between at least one first electrode and at least one adjacent second electrode such that the at least one first electrode is closer to a center of a circle formed by the circular-shaped at least one adjacent second electrode than the plurality of LED elements and the at least one adjacent second electrode,
wherein:
each second electrode of the plurality of second electrodes includes a first sub-second electrode and a second sub-second electrode, the first sub-second electrode and second sub-second electrode each having a semicircular shape, and the first sub-second electrode and the second sub-second electrode being spaced apart from each other, and
the pixel structure further includes:
a first electrode line connecting a plurality of the first sub-second electrodes to each other; and
a second electrode line connecting a plurality of the second sub-second electrodes to each other.

US Pat. No. 10,249,602

LIGHT EMITTING DIODE DISPLAY AND MANUFACTURE METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A manufacture method of a light emitting diode display, comprising steps of:step 1, providing a TFT backplate and a light emitting diode;
the TFT backplate comprising a substrate, a TFT layer located on the substrate, a first planarization layer located on the TFT layer, a first anode located on the first planarization layer, a second planarization layer located on the first anode and the first planarization layer and a first through hole being located on the second planarization layer and exposing at least a portion of the first anode;
the light emitting diode comprising a luminous lamp and a second anode and a second cathode respectively connected to two ends of the luminous lamp;
step 2, transferring the light emitting diode into the first through hole of the TFT backplate, and connecting the second anode of the light emitting diode with the first anode of the TFT backplate;
step 3, forming an anode contact layer, which is around the light emitting diode and on the first anode, inside the first through hole of the TFT backplate; the anode contact layer contacting with the second anode and not contacting with the second cathode;
step 4, forming a cathode insulation layer, which is around the light emitting diode and on the anode contact layer, inside the first through hole of the TFT backplate;
step 5, forming a first cathode on the cathode insulation layer, the light emitting diode and the second planarization layer, and the first cathode contacting with the second cathode.

US Pat. No. 10,249,601

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

Samsung Electro-Mechanics...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package, the fan-out semiconductor package including:
a semiconductor chip having an active surface and an inactive surface opposing the active surface, connection pads being disposed on the active surface,
a first heat dissipation member disposed side by side with the semiconductor chip,
a first encapsulant encapsulating at least portions of the semiconductor chip and at least portions of the first heat dissipation member, and
a connection member disposed below the semiconductor chip and the first heat dissipation member and comprising a redistribution layer electrically connected to the connection pads of the semiconductor chip; and
a component package disposed on the fan-out semiconductor package, the component package comprising:
a wiring substrate disposed on the first encapsulant,
a plurality of electronic components disposed on the wiring substrate,
a second encapsulant encapsulating at least portions of the plurality of electronic components, and
a second heat dissipation member formed in the wiring substrate,
wherein at least one of the plurality of electronic components of the component package is connected to the first heat dissipation member through the second heat dissipation member.

US Pat. No. 10,249,600

LIGHT EMITTING APPARATUS, ILLUMINATION APPARATUS AND DISPLAY APPARATUS

SONY CORPORATION, Tokyo ...

1. A light emitting apparatus comprising:a light emitting device having an upper side and a lower side and emitting configured to emit light from an upper surface at the upper side thereof;
a first electrode at the lower side and a second electrode at the upper side;
first and second terminal electrodes provided at the lower side with the light emitting device overlying the first terminal electrode and with its first electrode electrically connected to the first terminal electrode, the second terminal electrode laterally spaced from the first terminal electrode and not overlain by the light emitting device, the first terminal electrode and the second terminal electrode are for application of power to the light emitting device;
a first metal line electrically connecting the second terminal electrode and the second electrode;
a second metal line electrically connected to the first terminal electrode but not directly connected to the light emitting device; and
a transparent insulator in which the light emitting device, the first metal line, the second metal line are embedded, wherein, in cross section, the second electrode is surrounded on three sides by the first metal line.

US Pat. No. 10,249,599

LAMINATED PRINTED COLOR CONVERSION PHOSPHOR SHEETS

eLux, Inc., Vancouver, W...

1. An emissive display using printed phosphor color conversion sheets, the display comprising:a backplane comprising a top surface with a first number of light emitting diode (LED) devices aligned in an array and configured to emit light in a visible spectrum with a first color;
a first transparent substrate attached to the top surface of the backplane, wherein the first transparent substrate includes a top surface having a second number of printed phosphor dots configured to emit light in the visible spectrum with a second color different than the first color, and wherein the second number of printed phosphor dots overly a first subset of the first number of the LED devices; and,
a second transparent substrate attached to the top surface of the first transparent substrate, wherein the second transparent substrate includes a pattern of a third number of printed phosphor dots overlying a second subset of the first number of LED devices, and wherein the first subset of the first number of LED devices is exclusive of the second subset of the first number of LED devices, and wherein the third number is less than the first number.

US Pat. No. 10,249,598

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Intel Corporation, Santa...

1. A method of forming an integrated circuit (IC) package comprising:providing a first encapsulation layer having a first die and a plurality of electrical routing features at least partially embedded therein, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer on a first side of the first die, wherein the first die has a second side opposite the first side, wherein the plurality of electrical routing features electrically couple the first side of the first encapsulation layer with a second side of the first encapsulation layer, and wherein the first side of the first encapsulation layer is disposed opposite the second side of the first encapsulation layer, wherein the first encapsulation layer at least partially covers an electrically insulative material layer, wherein the plurality of electrical routing features fully extend through the electrically insulative material layer;
coupling a second die with the second side of the first encapsulation layer, wherein the second die includes a second plurality of die-level interconnect structures, and wherein the first encapsulation layer covers the second side of the first die;
electrically coupling the second plurality of die-level interconnect structures with at least a subset of the plurality of electrical routing features by bonding wires; and
forming a second encapsulation layer over the second die and the bonding wires to encapsulate at least a portion of the second die and the bonding wires in the second encapsulation layer, wherein the second encapsulation layer is in direct contact with the first encapsulation layer.

US Pat. No. 10,249,597

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING DIE RECOVERY IN TWO-LEVEL MEMORY (2LM) STACKED DIE SUBSYSTEMS

Intel Corporation, Santa...

1. A stacked semiconductor package, comprising:a processor functional silicon die at a first layer of the stacked semiconductor package, wherein the processor functional silicon die comprises a TSV repair register comprising a re-routing string;
one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package;
a plurality of Through Silicon Vias (TSVs) formed through the one or more memory dies, wherein each of the plurality of TSVs traverse through the one or more memory layers to the processor functional silicon die at the first layer of the stacked semiconductor package; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and
a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

US Pat. No. 10,249,596

FAN-OUT IN BALL GRID ARRAY (BGA) PACKAGE

Juniper Networks, Inc., ...

1. A device comprising:a set of at least four integrated circuits (ICs);
a first multi-chip module (MCM) substrate comprising a communication link and a first ball grid array (BGA), wherein the first BGA comprises a first pitch indicative of a distance between balls of the first BGA, wherein each IC of the set of at least four ICs is coplanar mounted to a surface of the first MCM substrate, wherein the communication link couples a first IC of the set of at least four ICs to a second IC of the set of at least four ICs, and wherein the first MCM substrate comprises organic, non-silicon insulating material;
a second MCM substrate coupled to the first MCM substrate with the first BGA, the second MCM substrate comprising a second BGA, wherein the second BGA comprises a second pitch indicative of a distance between balls of the second BGA, wherein the second pitch is greater than the first pitch, and wherein the second MCM substrate comprises organic, non-silicon insulating material; and
a printed circuit board (PCB) coupled to the second MCM substrate with the second BGA.

US Pat. No. 10,249,595

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) providing an arrangement having a semiconductor chip mounted on a die pad, a suspension lead connected to the die pad, and a lead spaced apart from the die pad and the suspension lead;
(b) sealing the semiconductor chip, the lead, and the suspension lead;
(c) after the step (b), cutting the lead with a punch;
(d) after the step (c), making a mark on a front surface of a sealing body formed by the step (b); and
(e) after the step (d), cutting the suspension lead with a punch.

US Pat. No. 10,249,594

DISPLAY DEVICE AND METHOD FOR ASSEMBLING THE SAME

BOE Technology Group Co.,...

1. A display device, comprising an electronic device and a flexible printed circuit board which are detachably connected,wherein the electronic device comprises a lead region and a port located at the lead region, the flexible printed circuit board comprises a first portion and a second portion,
wherein the first portion is a connector, the second portion comprises connecting fingers through which the flexible printed circuit board is connected to the port,
wherein the second portion of the flexible printed circuit board is arranged at a predetermined region, the predetermined region comprises the lead region and an extension region which is arranged outside the lead region and in a same plane where the lead region is located, and the extension region is a region extending outwards from the lead region until reaching other components and is within a surface of the electronic device where the lead region located,
wherein the flexible printed circuit board is provided with a hollow part, configured to allow a component which is arranged at the lead region to be exposed when the flexible printed circuit board is attached onto the lead region, a driving chip is arranged at the lead region, the flexible printed circuit board is provided with the hollow part located at a region corresponding to the driving chip to allow the driving chip to be exposed at the hollow part when the flexible printed circuit board is attached onto the lead region.

US Pat. No. 10,249,593

METHOD FOR BONDING A CHIP TO A WAFER

Agency for Science, Techn...

1. A method for chip on wafer bonding, comprising:forming posts on a wafer;
forming contacts on a chip such that the posts and the contacts align upon inversion of the chip onto the wafer;
planarizing each of the posts to have a contact surface with a surface roughness height less than 20 nanometers;
depositing, to the contact surface of the posts, a bonding material with a thickness not greater than the surface roughness height of the contact surface; and
temporarily bonding the posts to the contacts using the bonding material to stabilize a position of the chip relative to the wafer before subsequently permanently diffusion bonding of the chip to the wafer,
wherein the surface roughness height is a difference in height between a lowest point on a surface of the contact surface and a highest point on the surface of the contact surface.

US Pat. No. 10,249,592

WIRE BONDED WIDE I/O SEMICONDUCTOR DEVICE

SanDisk Technologies LLC,...

1. A semiconductor device, comprising:a substrate;
an interface chip mounted to the substrate;
a group of one or more semiconductor die stacked on one of the substrate and the interface chip;
a first set of wire bonds extending between the group of one or more semiconductor die and the interface chip, at least a pair of wire bonds in the first set of wire bonds extending in straight parallel paths from a semiconductor die of group of semiconductor die and the interface chip, the first set of wire bonds supporting wide I/O data exchange between the group of one or more semiconductor die and the interface chip; and
a second set of wire bonds extending between the interface chip and the substrate, the second set of wire bonds supporting narrow I/O data exchange between the interface chip and the substrate.

US Pat. No. 10,249,591

RESIN COMPOSITION, BONDED BODY AND SEMICONDUCTOR DEVICE

MITSUBISHI MATERIALS CORP...

1. A resin composition, comprising:a binder resin; and
silver-coated particles in which a functional group is introduced to a surface,
wherein a ratio (a/b) of Young's modulus (a) of the silver-coated particles to Young's modulus (b) of the binder resin after being cured is 0.1 to 2.0, and
the Young's modulus (a) of the silver-coated particles is 0.05 to 2.0 GPa.

US Pat. No. 10,249,590

STACKED DIES USING ONE OR MORE INTERPOSERS

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and
an interposer which includes interconnects that aligns to and electrically connects at least one functional via interconnect and a redundant functional via interconnect of a different die when the interposer is oriented in a predetermined orientation, wherein the interconnects of the interposer are directly connected by solder bumps to the at least one functional via interconnect of the at least one die and the redundant functional via interconnect of the different die.

US Pat. No. 10,249,589

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LAYER AND CONDUCTIVE PILLAR DISPOSED ON CONDUCTIVE LAYER AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor layer formed over the semiconductor substrate and including a first upper surface and a first lower surface;
a conductive pillar disposed on the first upper surface of the conductor layer and including a second upper surface, a second lower surface, and a sidewall;
a first insulating film covering the first upper surface of the conductor layer and including an opening which exposes the second upper surface and the sidewall of the conductive pillar;
a protection film covering the sidewall of the conductive pillar,
wherein, in a plan view, the opening is wider than the second upper surface and exposes an entire region of the second upper surface, and
wherein the second lower surface of the conductive pillar is in contact with the first upper surface of the conductor layer in an entire region of the conductive pillar; and
a second insulating film formed under the conductor layer in such a manner as to overlap with the entire region of the conductive pillar in the plan view,
wherein, in the plan view, the first upper surface of the conductor layer is exposed from the protection film and the conductive pillar.

US Pat. No. 10,249,588

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Intel Corporation, Santa...

1. A method of forming an assembly, comprising:providing a substrate, the substrate having a metal pad including aluminum, a base layer metal (BLM) disposed on the metal pad, the BLM including titanium, a bump disposed on the BLM, the bump including copper, and a first solder layer disposed on the bump, the first solder layer including tin and having a first material composition;
providing a die package, the die package having a first side and an opposing second side, and a second solder layer disposed on the first side of the die package, the second solder layer including tin and having a second material composition different from the first material composition, wherein one of the first solder layer or the second solder layer comprises an element not included in the other of the first solder layer or the second solder layer;
connecting the second solder layer of the die package to the first solder layer of the substrate to enable electrical current to flow between the die package and the substrate.

US Pat. No. 10,249,587

SEMICONDUCTOR DEVICE INCLUDING OPTIONAL PAD INTERCONNECT

Western Digital Technolog...

1. A semiconductor die, comprising:a plurality a die bond pads, comprising:
a first die bond pad, and
a second die bond pad configured to provide functional redundancy to the first die bond pad; and
a metal interconnect having a first end connected to the first die bond pad and a second end, opposite the first end, connected to at least a portion of the second die bond pad.

US Pat. No. 10,249,586

MIXED UBM AND MIXED PITCH ON A SINGLE DIE

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first set of micro under-bump metallizations (UBMs) on a surface of a photosensitive polyimide (PSPI) layer in a first region of a die comprising a first pitch constraint, each micro UBM comprising a via electrically coupling the respective UBM to a contact region of the die;
forming a second set of micro UBMs on a surface of the PSPI layer in a second region of the die comprising a second pitch constraint, each micro UBM comprising a via electrically coupling the respective UBM to a contact region of the die, the second pitch constraint higher than the first pitch constraint, wherein the first region and the second region are configured to have a matching plateable surface areas;
forming a single solder bump electrically shorting the first set of micro UBMs to a single contact region of a laminate, wherein the single solder bump has an elliptical shape; and
forming individual solder bumps electrically shorting each of the second set of micro UBMs to a contact region of a laminate.

US Pat. No. 10,249,585

STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A stackable semiconductor package, comprising:a carrier having a first surface, at least one sidewall substantially perpendicular to the first surface, and a plurality of through holes penetrating through the first surface, the through holes including a plurality of terminal holes and a chip-accommodating hole, wherein the carrier is only made of a rigid plate having no electrical transmission function;
a first redistribution layer (RDL) formed directly on and in physical contact with the first surface of the carrier, wherein the first RDL comprises a plurality of first pads and a plurality of second pads, the terminal holes correspondingly expose a portion of each of the second pads, and the chip-accommodating hole exposes the first pads;
an encapsulation layer formed directly on and in physical contact with the first surface of the carrier, the encapsulation layer encapsulating the first RDL, wherein the encapsulation layer has an outer surface and at least one sidewall substantially perpendicular to the outer surface of the encapsulation layer and the first surface of the carrier, the at least one sidewall of the encapsulation layer being correspondingly coplanar to the at least one sidewall of the carrier;
a plurality of vertical interposers disposed in the encapsulation layer, wherein the vertical interposers are electrically connected to the first RDL;
a second RDL formed on the outer surface of the encapsulation layer to electrically connect with the vertical interposers, the second RDL comprising a plurality of third pads; and
a chip disposed in the chip-accommodating hole, and electrically connected to the first pads.

US Pat. No. 10,249,584

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

ABLIC INC., Chiba-Shi (J...

1. A semiconductor device, comprising:a substrate;
a wiring formed above the substrate;
a titanium nitride film formed on the wiring;
an oxide film formed on the titanium nitride film;
a silicon nitride film formed on the oxide film; and
a pad portion exposing the wiring, and formed within a region where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in a plan view, and being inside a third opening portion formed in the oxide film in the plan view,
the silicon nitride film being formed on top of and in partial contact with the titanium nitride film inside the third opening portion in the plan view.

US Pat. No. 10,249,583

SEMICONDUCTOR DIE BOND PAD WITH INSULATING SEPARATOR

Infineon Technologies AG,...

1. A semiconductor die, comprising:a last metallization layer above a semiconductor substrate;
a bond pad above the last metallization layer;
a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad;
an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad; and
an electrically conductive interconnection structure that extends from the bond pad to the last metallization layer outside the contact area of the bond pad.

US Pat. No. 10,249,582

RADIO FREQUENCY (RF) DEVICES WITH RESONANT CIRCUITS TO REDUCE COUPLING

NXP USA, Inc., Austin, T...

1. A device comprising:a first conductor,
a second conductor adjacent to the first conductor; and
a resonant circuit, the resonant circuit physically located at least in part between the first conductor and the second conductor, the resonant circuit electromagnetically coupled to and configured to resonate with the first conductor and the second conductor at a frequency f0, and when resonating to provide a path to a ground node for crosstalk energy and reduce electromagnetic coupling between the first conductor and the second conductor, wherein the resonant circuit comprises a first capacitor in series with an inductance, and wherein the resonant circuit includes a first end and a second end, and wherein the first end is coupled to a first ground node and wherein the second end is coupled to a second ground node.

US Pat. No. 10,249,581

TRANSMISSION LINE FOR 3D INTEGRATED CIRCUIT

Taiwan Semiconductor Manu...

1. A semiconductor transmission line substructure comprising:a first semiconductor substrate;
a first signal line over said first semiconductor substrate;
a first ground line over said first semiconductor substrate;
a second semiconductor substrate over said first semiconductor substrate, wherein each of said first semiconductor substrate, said first signal line, said first ground line and said second semiconductor substrate are vertically spaced apart from one another, wherein said second semiconductor substrate is between said first signal line and said first ground line.

US Pat. No. 10,249,580

STACKED SUBSTRATE INDUCTOR

QUALCOMM Incorporated, S...

1. A stacked substrate inductor, comprising:a first substrate;
a second substrate stacked on the first substrate such that an upper side of the first substrate is in direct contact with a lower side of the second substrate;
a first inductor within and in direct contact with the first substrate, the first inductor including a first core region;
a second inductor within and in direct contact with the second substrate, the second inductor including a second core region;
an inductor interconnect within and in direct contact with the second substrate, the inductor interconnect configured to electrically couple the first inductor with the second inductor,
wherein at least a portion of the first core region overlaps with at least a portion of the second core region,
wherein the second inductor comprises a plurality of second substrate inductance loops, and
wherein the second substrate encapsulates the second inductor such that each of the plurality of second substrate inductance loops is in direct contact with the second substrate.

US Pat. No. 10,249,579

ACTIVE SHIELD FOR PROTECTING A DEVICE FROM BACKSIDE ATTACKS

NUVOTON TECHNOLOGY CORPOR...

1. An electronic apparatus, comprising:a substrate comprising active devices;
one or more routing layers, which are electrically connected to the active devices and are configured to route electrical signals to and from the active devices;
an active shield layer, which is disposed within a routing layer nearest to the substrate, wherein the active shield layer comprises metallic traces configured to conduct active-shield signals that provide an indication of an attack on the apparatus; and
protection circuitry, which is connected to the metallic traces of the active-shield layer and is configured to drive the active-shield signals and to detect the attack based on the active-shield signals.

US Pat. No. 10,249,578

CORE-SHELL PARTICLES FOR ANTI-TAMPERING APPLICATIONS

International Business Ma...

1. A method of making a tamper resistant apparatus, comprising:disposing a core-shell particle on a first surface of a tampering sensor, the first surface including a first conductive portion and a second conductive portion spaced from each other, wherein
the core-shell particle has a liquid metallic core and a shell surrounding the liquid metallic core, and
the tampering sensor is configured to trigger a security response when the first conductive portion and the second conductive portion are electrically connected to each other.

US Pat. No. 10,249,577

METHOD OF FORMING METAL INTERCONNECTION AND METHOD OF FABRICATING SEMICONDUCTOR APPARATUS USING THE METHOD

ASM IP Holding B.V., Alm...

1. A method of forming a metal interconnection, the method comprising:depositing a low-k dielectric layer;
forming a trench in the low-k dielectric layer;
forming a barrier layer in the trench;
filling a metal on the barrier layer;
planarizing the metal; and
forming a capping layer on the planarized metal,
wherein the capping layer comprises at least two layers and has a thickness equal to or less than 100 ?,
wherein the forming of the capping layer comprises depositing a first nitride layer and a second nitride layer, and
wherein the depositing of the first nitride layer and the second nitride layer comprises:
depositing an aluminum nitride (AlN) layer; and
depositing a silicon nitride (SiN) layer,
wherein a ratio of a thickness of the AIN layer to a thickness of the SiN layer ranges from 1:15 to 1:2, and
wherein, when the capping layer comprising the AlN layers and SiN layer is exposed for 17 hours at a temperature of 85° C. and a humidity of 85%, a change in strees of a thin film is equal to or less than 50 MPa.

US Pat. No. 10,249,576

CAVITY FORMATION USING SACRIFICIAL MATERIAL

Skyworks Solutions, Inc.,...

1. A method for fabricating a semiconductor device, the method comprising:providing a semiconductor substrate;
forming an oxide layer in the semiconductor substrate;
forming a transistor device over the oxide layer;
removing at least part of a backside of the semiconductor substrate;
applying a sacrificial material below the oxide layer;
covering the sacrificial material with an interface material; and
removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface material.

US Pat. No. 10,249,575

RADIO-FREQUENCY ISOLATION USING CAVITY FORMED IN INTERFACE LAYER

Skyworks Solutions, Inc.,...

1. A method for fabricating a semiconductor device, the method comprising:providing a transistor device;
forming one or more electrical connections to the transistor device;
forming one or more dielectric layers over at least a portion of the electrical connections;
applying an interface material over at least a portion of the one or more dielectric layers;
removing at least a portion of the interface material to form a trench; and
covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

US Pat. No. 10,249,574

METHOD FOR MANUFACTURING A SEAL RING STRUCTURE TO AVOID DELAMINATION DEFECT

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a semiconductor substrate;
forming a plurality of integrated circuit (IC) devices on the semiconductor substrate; and
forming a seal ring structure surrounding each of the IC devices, wherein forming the seal ring structure comprises:
forming a plurality of interlayer dielectric layers on the semiconductor substrate; and
forming a plurality of hollow through-hole structures within the interlayer dielectric layers, wherein forming a plurality of hollow through-hole structures within the interlayer dielectric layers comprises:
performing an etching process on each of the interlayer dielectric layers at a location of a cutting channel in the semiconductor substrate to form one or more through-holes;
sequentially forming a diffusion barrier layer and a seed layer at a bottom portion and sidewalls of the one or more through-holes, wherein the diffusion barrier layer and the seed layer seal an opening at a top portion of the one or more through-holes.

US Pat. No. 10,249,573

SEMICONDUCTOR DEVICE PACKAGE WITH A STRESS RELAX PATTERN

POWERTECH TECHNOLOGY INC....

1. A method of forming a semiconductor device package, the semiconductor device package comprising:a die;
a plurality of metal contacts electrically connected to the die;
a continuous pattern of dielectric material formed on an active surface of the die, the continuous pattern of dielectric material forming contours of at least one opening, each of the at least one opening surrounding at least one of the metal contacts electrically connected to the die;
a mold compound formed around the pattern, the die and the metal contacts, wherein at least a space between the metal contacts and the pattern is filled with the mold compound; and
a redistribution layer, formed on a grinded surface of the mold compound, and electrically connected to the metal contacts;the method comprising:disposing the die on a carrier;
forming the pattern of dielectric material on the active surface of the die to surround the plurality of metal contacts electrically connected to the die;
forming the mold compound around the die, the metal contacts and the pattern, wherein the dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound;
grinding the mold compound to expose the metal contacts;
removing the carrier; and
forming the redistribution layer on the grinded surface of the mold compound to electrically connect the metal contacts.

US Pat. No. 10,249,572

METHOD FOR ELECTROMAGNETIC SHIELDING AND THERMAL MANAGEMENT OF ACTIVE COMPONENTS

Atotech Deutschland GmbH,...

1. Method for forming a metal layer for electromagnetic shielding and thermal management of active components, comprising the following steps(i) providing at least one active component, said active component having a front side comprising at least one chip encased by a layer of molding compound, a back side and side walls;
(ii) forming on the back side a protective layer selected from a layer formed by lamination of an adhesive tape, a UV peelable tape and a layer of temporary ink;
(iii) forming on the front side and optionally on the side walls an adhesion promotion layer;
(iv) forming at least one metal layer on the adhesion promotion layer or
forming at least one metal layer on the adhesion promotion layer by wet chemical metal plating processes,
(v) heating of the at least one metal plated layer to a temperature of between 100° C. and 300° C.,
wherein the protective layer is removed after step (iv) or (v).

US Pat. No. 10,249,571

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL

BOE Technology Group Co.,...

1. A thin film transistor comprising:an active layer, and a light-protection layer disposed above the active layer and/or disposed beneath the active layer,
wherein the light-protection layer is configured to absorb light having a predetermined wavelength, and
wherein a forbidden band gap of the light-protection layer is greater 1.1 eV and less than 2.3 eV with a transmissivity lower than 70%.

US Pat. No. 10,249,570

OVERLAY MARK

TAIWAN SEMICONDUCTOR MANU...

1. An overlay mark, comprising:a first feature in a first layer, wherein the first feature comprises a plurality of first alignment segments extending along a first direction;
a second feature in a second layer over the first layer, wherein the second feature comprises a plurality of second alignment segments extending along a second direction different from the first direction; and
a third feature in a third layer over the second layer, wherein the third feature comprises a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction,
wherein, in a plan view, each first alignment segment of the plurality of first alignment segments is adjacent to a corresponding third alignment segment of the plurality of third alignment segments along the first direction, and each second alignment segment of the plurality of second alignment segments is adjacent to a corresponding fourth alignment segment of the plurality of fourth alignment segments along the second direction.

US Pat. No. 10,249,569

SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A system-on-chip, comprising:a processor; and
a hardware component connected to the processor,
wherein at least one of the processor and the hardware component comprises:
a semiconductor substrate; and
a plurality of metal layers formed above the semiconductor substrate,
wherein a first metal layer among the plurality of metal layers comprises:
a plurality of first power rails which extend in a first direction and transmit a first voltage;
a plurality of second power rails which extends in the first direction and transmit a second voltage; and
a first conductor which is coupled to one end of each of the first power rails and extends in a second direction,
wherein a second metal layer placed over the first metal layer comprises:
a third power rail transmitting the first voltage; and
a fourth power rail transmitting the second voltage, and
wherein the third power rail and the fourth power rail are spaced apart from the first conductor in the first direction.

US Pat. No. 10,249,568

METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STACKED ANALOG COMPONENTS IN BACK END OF LINE (BEOL) REGIONS

STMICROELECTRONICS, INC.,...

1. A device, comprising:a first dielectric layer;
a first recess in the first dielectric layer;
a first conductive layer in the first recess, the first conductive layer having a first area;
a second conductive layer in the first recess, the second conductive layer having a second area that is less than the first area; and
a third conductive layer in the first recess, the third conductive layer having a third area that is less than the first area.

US Pat. No. 10,249,567

REDISTRIBUTION LAYER STRUCTURE OF SEMICONDUCTOR PACKAGE

Industrial Technology Res...

17. A redistribution layer structure of a semiconductor package, comprising:a dielectric layer having a thickness, and the dielectric layer having a first surface and a second surface opposite to the first surface;
an upper conductive wire disposed on the first surface of the dielectric layer and having a first width;
a lower conductive wire disposed on the second surface of the dielectric layer and having a second width, wherein the upper conductive wire and the lower conductive wire are separated by the dielectric layer; and
a single via penetrating the dielectric layer and connecting the upper conductive wire and the lower conductive wire, wherein the single via has a cross-section at the upper conductive wire, and the cross-section has a third width, wherein a ratio of the third width of the cross-section of the single via to the thickness of the dielectric layer is less than or equal to 1.

US Pat. No. 10,249,566

SEMICONDUCTOR DEVICE INCLUDING FUSE STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a first region and a second region;
an eFuse structure formed in the first region; and
an interconnect structure formed in the second region, wherein:
the eFuse structure includes a first metal pattern formed at a first vertical level on the substrate, a second metal pattern formed at a second vertical level between the first vertical level and the substrate, a third metal pattern formed at a third vertical level between the second vertical level and the substrate, a first via physically connecting the first metal pattern to the second metal pattern, and a second via physically connecting the second metal pattern to the third metal pattern,
the first metal pattern includes a first bent portion in a U shape, and a first auxiliary pattern extending in a first direction and being adjacent to and electrically isolated from the first bent portion,
the first bent portion includes a first portion which extends in the first direction and is electrically connected to the first via, and a second portion extending in the first direction and being adjacent to the first portion,
the second portion is disposed between the first portion and the first auxiliary pattern, and
a first distance between the first portion and the second portion spaced apart from the first portion is greater than a width of the second portion in a second direction perpendicular to the first direction.

US Pat. No. 10,249,565

SEMICONDUCTOR DEVICE THAT TRANSFERS AN ELECTRIC SIGNAL WITH A SET OF INDUCTORS

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate of a substantially rectangular shape having a first surface and a second surface opposite the first surface, a first side, a second side opposite the first side, a third side and a fourth side, which intersect the first and second sides, a plurality of electrode pads formed on the first surface, and a plurality of soldering balls formed on the second surface;
the plurality of electrode pads including a plurality of first electrode pads closer to the first side than the second side and a plurality of second electrode pads closer to the second side than the first side;
the second surface having a first area which is closer to the first side than the second side and which is contiguous to the first, third and fourth sides, a second area which is closer to the second side than the first side and which is contiguous to the second, third and fourth sides, and a third area which is contiguous to the first and second areas, and the third and fourth sides;
the plurality of soldering balls including a plurality of first soldering balls which are shaped in a form of a lattice and which are on the first area, and a plurality of second soldering balls which are shaped in a form of a lattice and which are on the second area;
the plurality of first soldering balls electrically connected with the plurality of the first electrode pads of the wiring substrate;
the plurality of second soldering balls electrically connected with the plurality of the second electrode pads of the wiring substrate;
a first semiconductor chip of a substantially rectangular shape having a first main surface, a first side surface, a second side surface opposite the first side surface, and a first inductor which is closer to the first side surface than the second side surface and which is on the first main surface;
the first semiconductor chip being mounted on the first surface of the wiring substrate and closer to the first side of the wiring substrate than the second side of the wiring substrate;
a second semiconductor chip of a substantially rectangular shape having a second main surface, a third side surface, a fourth side surface opposite the third side surface, and a second inductor which is closer to the third side surface than the fourth side surface and which is on the second main surface;
the second semiconductor chip being mounted side by side with the first semiconductor chip on the first surface of the wiring substrate and closer to the second side of the wiring substrate than the first side of the wiring substrate such that the third side surface faces the first side surface of the first semiconductor chip;
a plurality of bonding wires including a plurality of first bonding wires by which the first main surface of the first semiconductor chip is connected with the plurality of first electrode pads of the wiring substrate, and a plurality of second bonding wires by which the second main surface of the second semiconductor chip is connected with the plurality of second electrode pads of the wiring substrate; and
a sealed resin body covering the first surface of the wiring substrate, the first semiconductor chip, the second semiconductor chip, and the plurality of bonding wires,
wherein, in the plan view, the plurality of first soldering balls include a first ball that is most proximate to the second side of the wiring substrate in the plurality of first soldering balls,
wherein, in the plan view, the plurality of second soldering balls include a second ball that is most proximate to the first side of the wiring substrate in the plurality of second soldering balls,
wherein a shortest distance between the first and second soldering balls is greater than a shortest distance from the first side surface of the first semiconductor chip and the third side surface of the second semiconductor chip in the plan view,
wherein, in the plan view, an area between the first side surface of the first semiconductor chip and the third side surface of the second semiconductor chip on the first surface of the wiring substrate is within the third area of the wiring substrate,
wherein a soldering ball is not in the third area of the wiring substrate;
wherein the first inductor of the first semiconductor chip is not electrically connected with the second inductor of the second semiconductor chip,
wherein the first semiconductor chip is not electrically connected with the second semiconductor chip via a bonding wire in the plan view, and
wherein the first soldering ball is not electrically connected with the second soldering ball.

US Pat. No. 10,249,564

ELECTRONIC COMPONENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

KYOCERA CORPORATION, Kyo...

1. An electronic component mounting substrate comprising:an insulating base having a rectangular shape in plan view and comprising a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface;
a band-shaped metal layer on a sidewall of the recess; and
an electrode extending from a bottom surface of the recess into the insulating base,
the electrode comprising an end disposed in the insulating base, the end comprising an inclined portion inclined toward the second main surface, the inclined portion having a tip, a part of which is closer to the second main surface than the bottom surface of recess when viewed in longitudinal section.

US Pat. No. 10,249,563

MULTILAYER WIRING SUBSTRATE

FUJIFILM Corporation, Mi...

1. A multilayer wiring substrate comprising:an anisotropic conductive member including an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each conductive path has a protrusion protruding from the surface of the insulating base; and
a wiring substrate having a substrate and one or more electrodes to be formed on the substrate,
wherein the multilayer wiring substrate is formed by laminating the anisotropic conductive member and the wiring substrate,
the wiring substrate has a resin layer which covers at least a part of the substrate,
the electrode is formed to be flush with the resin layer,
the resin layer is a layer that allows the protrusion to penetrate therein when pressure is applied at 20 MPa,
at least a part of the protrusions of the conductive paths other than the conductive paths which come in contact with the electrode among the plurality of conductive paths penetrates into the resin layer, and
conductive paths which come into contact with the electrode among the plurality of conductive paths are deformed so that adjacent conductive paths come into contact with each other.

US Pat. No. 10,249,562

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. A package structure, comprising:a carrier having opposite first and second surfaces, wherein at least a recess is formed on the first surface of the carrier;
at least an electronic element disposed in the recess of the carrier;
an insulating layer formed in the recess to encapsulate the electronic element and on the first surface of the carrier to cover the first surface, with a plurality of through holes penetrating the first and second surfaces of the carrier and the insulating layer, wherein the insulating layer is made of a material different from a material of the carrier;
a circuit structure formed on the first surface of the carrier and electrically connected to the electronic element; and
a plurality of conductors formed in the through holes, wherein the conductors are conductive columns and penetrate the first and second surfaces of the carrier and the insulating layer and are electrically connected to the circuit structure.

US Pat. No. 10,249,561

PRINTED WIRING BOARD HAVING EMBEDDED PADS AND METHOD FOR MANUFACTURING THE SAME

IBIDEN CO., LTD., Ogaki ...

1. A printed wiring board, comprising:a support plate; and
a build-up wiring layer comprising a plurality of resin insulating layers and a plurality of conductor layers and having a first surface and a second surface on an opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer,
wherein the plurality of resin insulating layers in the build-up wiring layer includes a first resin insulating layer that forms the second surface of the build-up wiring layer, the build-up wiring layer includes a plurality of first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer, and a plurality of via conductors formed in the plurality of resin insulating layers such that diameters of the via conductors are reducing from the first surface toward the second surface of the build-up wiring layer, each of the first conductor pads comprises a dissimilar metal layer comprising a plurality of metal layers such that the metal layers are formed of different metals with respect to each other, and the dissimilar metal layer comprises a copper plating layer and a corrosion resistant plating layer formed on the copper plating layer.

US Pat. No. 10,249,560

SEMICONDUCTOR DEVICE, SYSTEM IN PACKAGE, AND SYSTEM IN PACKAGE FOR VEHICLE

Renesas Electronics Corpo...

1. A semiconductor system in package comprising:a plurality of semiconductor integrated circuits including a first semiconductor integrated circuit; and
a package substrate having a first surface on which the semiconductor circuits are mounted,
wherein a coefficient of thermal expansion of the first semiconductor integrated circuit is different from a coefficient of thermal expansion of the package substrate,
wherein the package substrate includes electrodes for a plurality of soldering balls on a second surface opposite to the first surface where the semiconductor integrated circuits are mounted, and
wherein the package substrate does not have the electrodes for the soldering balls at a position corresponding to a length of at least one side of a fringe of the first semiconductor integrated circuit.

US Pat. No. 10,249,559

BALL GRID ARRAY AND LAND GRID ARRAY ASSEMBLIES FABRICATED USING TEMPORARY RESIST

International Business Ma...

1. A structure comprising:a substrate including a front side, a back side, and electrically conductive contact pads on the back side;
a patterned resist film directly contacting the back side of the substrate, the resist film including channels exposing a plurality of the contact pads;
a plurality of solder bumps, each of the solder bumps being within one of the channels in the patterned resist film and electrically contacting one of the contact pads;
a plurality of contact elements on the front side of the substrate configured for electrical connection to a chip;
a chip electrically and mechanically connected to the contact elements; and
one or more stand-off elements within one or more of the channels of the patterned resist film and solder material encasing the one or more stand-off elements, the one or more stand-off elements having substantially higher melting points than the solder material and the solder bumps.

US Pat. No. 10,249,558

ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE

NSK LTD., Tokyo (JP)

22. An electronic part mounting heat-dissipating substrate which comprises: a conductor plate which is formed on lead frames of wiring pattern shapes to mount an electronic part; and an insulating member which is provided between said lead frames of said wiring pattern shapes on said conductor plate; in which a plate surface of an electronic part arrangement surface of said conductor plate and a plate surface of an electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane, and a plate surface of a back surface of said electronic part arrangement surface of said conductor plate and a plate surface of a back surface of said electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane,wherein said lead frames of said wiring pattern shapes have different thicknesses of at least two types or more, a thickness of the lead frames being measured in a direction parallel to the mounting direction of the electronic part, and a thick lead frame is used for a large current signal and a thin lead frame is used for a small current signal,
wherein said plate surface of said back surface of said electronic part arrangement surface of said lead frames of said wiring pattern shapes and said plate surface of said back surface of said electronic part arrangement surface-side of said insulating member are formed in an identical vertical plane to meet said plate surface of said back surface of said electronic part arrangement surface of a thickest lead frame among said lead frames, and
wherein plural pin-shape cavities are disposed on a substrate surface that is a different surface on which a thin lead frame of said electronic part arrangement surface is provided, and are extended from a back surface side of said substrate of said thin lead frame to said different surface side of said substrate.

US Pat. No. 10,249,557

PACKAGED INTEGRATED CIRCUIT DEVICE AND METHODS

NXP USA, Inc., Austin, T...

1. A packaged lead frame comprising:a encapsulant having a first minor side, a second minor side opposite the first minor side, a third minor side between the first and second minor sides, and a fourth minor side between the first and second minor sides and opposite the third minor side; and
a first plurality of leads along the third minor side between the first minor side and a center plane that bisects the encapsulant between the first and second minor sides, wherein the first plurality of leads extend from the encapsulant, and
wherein each lead of the first plurality of leads, includes a corresponding jog external to the encapsulant which jogs away from the center plane, wherein the corresponding jog of each lead from a first lead of the plurality of leads closest to the center plane to a last lead of the first plurality of leads closest to the first minor side jogs incrementally further away from the center plane.

US Pat. No. 10,249,556

LEAD FRAME WITH PARTIALLY-ETCHED CONNECTING BAR

NXP B.V., San Jose, CA (...

1. A lead frame for semiconductor device assembly, the lead frame comprising:a die pad for receiving an integrated circuit (IC) die;
a plurality of lead fingers disposed along at least two opposing sides of the die pad, wherein each of the plurality of lead fingers has a proximal end near to the die pad and a distal end farther from the die pad, and wherein the plurality of lead fingers are perpendicular to the opposing sides of the die pad; and
at least one connection bar extending parallel to one of said at least two opposing sides of the die pad, wherein the distal ends of the plurality of lead fingers on said one of said at least two opposing sides of the die pad are connected to the connection bar, wherein the at least one connection bar has first portions where the plurality of lead fingers are connected thereto and second portions between adjacent lead finger connections to the connection bar, and
wherein the respective second portions comprise a bar that extends diagonally from a first one of the adjacent lead fingers connected thereto to a second one of the adjacent lead fingers connected thereto.

US Pat. No. 10,249,555

COMPOSITE HEAT SINK STRUCTURES

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:a composite heat sink structure including:
a thermally conductive base, the thermally conductive base including a main heat transfer surface to couple to at least one component to be cooled;
a compressible, continuous sealing member;
a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base;
a one-piece member molded over and affixed to the thermally conductive base, and molded over and securing in place the sealing member retainer, wherein a coolant-carrying compartment resides between the thermally conductive base and the one-piece member and wherein the one-piece member contacts a surface of the thermally conductive base opposite to the main heat transfer surface and wraps around at least a portion of the thermally conductive base to secure the one-piece member to the thermally conductive base absent use of separate fasteners; and
a coolant inlet and a coolant outlet, the coolant inlet and coolant outlet being in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow therethrough.

US Pat. No. 10,249,554

HEAT TRANSFER ASSEMBLY FOR A HEAT EMITTING DEVICE

GENERAL ELECTRIC COMPANY,...

1. A heat transfer assembly coupled to a heat emitting device for dissipating heat from the heat emitting device, the heat transfer assembly comprising:a module inlet for receiving a coolant;
at least one module comprising a first part having a recess to receive a portion of the heat emitting device, and a second part having a shaped cutout portion and a solid portion;
a sealing component disposed between the heat emitting device and the at least one module;
a module outlet for discharging a heat absorbed coolant after absorbing heat from the heat emitting device, wherein the at least one module is connected to the module inlet and the module outlet,wherein the second part allows a uniform compression of the seal component, and wherein the first part and the second part are mechanically connected to each other; andwherein the at least one module is flexible to achieve a convex curvature or a concave curvature for load balance for leak-proof sealing.

US Pat. No. 10,249,553

COOLING APPARATUS FOR A HEAT-GENERATING ELEMENT

Nissan Motor Co., Ltd., ...

1. A cooling apparatus for a heat-generating element, comprising:a heat sink having a main surface on which the heat-generating element is mounted and a heat radiation surface from which heat generated by the heat-generating element is radiated;
a cooling component having a recess and an interior gap,
the recess having an outer sidewall extending in a substantially perpendicular direction to the heat sink,
the interior gap being defined by an interior gap plane and an exterior gap plane, the interior gap plane being coplanar with the outer sidewall,
the cooling component and the heat sink facing and joining each other so that the recess forms a coolant passage in which a coolant flows; and
a sealing member provided between the heat sink and the cooling component so as to seal the coolant passage and separate an interior and exterior of the coolant passage, the sealing member having an internal side and an external side, the internal side being adjacent to the coolant passage, wherein
the sealing member is provided outside a plane which is coplanar with a first sidewall of the recess such that the internal side of the sealing member is coplanar with the interior gap plane,
a first distance is longer than a second distance with regard to a distance between facing surfaces of the heat sink and the cooling component near the sealing member,
the first distance is a distance between the facing surfaces within the interior gap between the sealing member and the first sidewall of the recess at an interior side of the coolant passage separated by the sealing member, the first distance having a minimal value at a point of the cooling component closest to the sealing member, and
the second distance is a distance between the facing surfaces at an exterior side of the coolant passage separated by the sealing member.

US Pat. No. 10,249,552

SEMICONDUCTOR PACKAGE HAVING DOUBLE-SIDED HEAT DISSIPATION STRUCTURE

JMJ Korea Co., Ltd., Gye...

1. A semiconductor package having a double-sided heat dissipation structure, the semiconductor package comprising:a package body formed by molding;
a first substrate which is provided at an inner lower portion of the package body 100 and has a lower surface exposed to the outside of the package body;
a semiconductor chip mounted on an upper surface of the first substrate;
a lead frame which is attached to the first substrate and extends to the outside of the package body;
a second substrate which is provided at an inner upper portion of the package body and has an upper surface exposed to the outside of the package body;
a first metal unit in which one side is bonded to an upper surface of the semiconductor chip and the other side is bonded to a lower surface of the second substrate; and
a second metal unit in which one side is bonded to an upper surface of the first substrate and the other side is bonded to the lower surface of the second substrate,
wherein the upper portions of the first metal unit and the second metal unit are bonded to the second substrate by an ultrasonic welding method, lower portions of the first metal unit and the second metal unit which are bonded to the semiconductor chip and the first substrate are bonded by an adhesive, in a portion at which the lower portion of the first metal unit is bonded to the semiconductor chip by an adhesive, a V-shaped or a U-shaped groove is further formed to be more firmly bonded and enhance a heat dissipation effect.

US Pat. No. 10,249,551

ELECTRONIC COMPONENT HAVING A HEAT-SINK THERMALLY COUPLED TO A HEAT-SPREADER

Infineon Technologies Aus...

1. An electronic component, comprising:one or more semiconductor dice embedded in a first dielectric layer;
a heat-spreader embedded in a second dielectric layer, wherein the heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice; and
a heat-sink thermally coupled to the heat-spreader, wherein the heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice, and the heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor dice.

US Pat. No. 10,249,550

POWER MODULE WITH LEAD COMPONENT AND MANUFACTURING METHOD THEREOF

DELTA ELECTRONICS, INC., ...

1. A power module comprising:a carrier board; and
at least one lead component, stacked and disposed on the carrier board, and comprising:
at least one initial plane, wherein the initial plane includes at least one pad, and a vertical projection of the initial plane at least partially overlaps with the carrier board;
at least one first pin electrically connected to the carrier board, wherein the first pin is vertical to the initial plane;
at least one second pin electrically connected to the carrier board, wherein the second pin is vertical to the initial plane; and
at least one isolation gap disposed in the initial plane and located between the first pin and the second pin, wherein the initial plane is separated into a first plane and a second plane by the isolation gap, so as to electrically isolate the first pin and the second pin from each other.

US Pat. No. 10,249,549

CERAMIC CIRCUIT BOARD, ELECTRONIC CIRCUIT MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC CIRCUIT MODULE

MURATA MANUFACTURING CO.,...

1. A ceramic circuit board comprising: a ceramic insulator layer; at least one grounding pattern conductor, the at least one grounding pattern conductor containing a metal and an oxide of at least one metal element contained in the ceramic insulator layer, the at least one grounding pattern conductor including a pattern main portion disposed within the ceramic circuit board and an extended portion having a first end thereof connected to the pattern main portion and a second end thereof exposed at a side surface of the ceramic circuit board, and a first metal content of the extended portion is lower than a second metal content of the pattern main portion; a connection land disposed on a first surface of the ceramic board; and a grounding electrode disposed on a second surface of the ceramic board and connected to the grounding pattern conductor, wherein the first metal content of the extended portion is 30 to 60 percent by volume, and the second metal content of the pattern main portion is 80 percent by volume or more.

US Pat. No. 10,249,548

TEST CELL FOR LAMINATE AND METHOD

INTERNATIONAL BUSINESS MA...

1. A method of designing a laminate comprising:forming a test laminate that includes:
a plurality of buildup layers disposed on a core; and
one or more unit cells defined in the buildup layers, each unit cell including:
at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and
two or more dummy vias;
wherein the dummy vias are arranged in the unit cell at one of a plurality of distances from the test via;
subjecting test laminate to a stress;
testing at least one of the one more unit cells;
determining that at least one of the one or more unit cells is a failed cell; and
designing the laminate such that it does not include a via configuration from the failed cell in a location under a computer chip where the failed cell was located.

US Pat. No. 10,249,547

METHOD FOR USING A TEST WAFER BY FORMING MODIFIED LAYER USING A LASER BEAM AND OBSERVING DAMAGE AFTER FORMING MODIFIED LAYER

DISCO CORPORTATION, Toky...

1. A test wafer using method for using a test wafer including a test substrate and a metal foil formed on a front side of said test substrate, said test wafer using method comprising:a modified layer forming step of applying a laser beam having a transmission wavelength to said test substrate from a back side of said test wafer in the condition where a focal point of said laser beam is set inside said test substrate, thereby forming a modified layer inside said test substrate;
a damage detecting step of observing a front side of said test wafer after performing said modified layer forming step, thereby detecting damage to said metal foil; and
a processing conditions adjusting step of adjusting at least one of the laser processing conditions adopted in said modified layer forming step according to the result of detection of said damage obtained in said damage detecting step, said at least one of the laser processing conditions being selected from the group consisting of the wavelength of said laser beam, average power of said laser beam, repetition frequency of said laser beam, pulse width of said laser beam, numerical aperture of a focusing lens for focusing said laser beam, focal position of said laser beam, and relative feed speed of said test wafer.

US Pat. No. 10,249,546

REVERSE DECORATION FOR DEFECT DETECTION AMPLIFICATION

KLA-Tencor Corporation, ...

1. A method comprising:applying a layer of a material on a surface of a plurality of NAND stacks such that a bridge structure between two of the NAND stacks is covered with the layer, wherein the material has a refractive index different from that of the surface thereby amplifying detection of the bridge structure; and
removing a first portion of the layer from the plurality of NAND stacks, wherein a second portion of the layer remains disposed on the bridge structure after the removing.

US Pat. No. 10,249,545

METHOD FOR PROCESSING SUBSTRATE INCLUDING FORMING A FILM ON A SILICON-CONTAINING SURFACE OF THE SUBSTRATE TO PREVENT RESIST FROM EXTRUDING FROM THE SUBSTRATE DURING AN IMPRINTING PROCESS

Toshiba Memory Corporatio...

1. A method for processing a substrate, comprising:exposing a silicon-containing surface at a circumferential edge portion of a first main surface of a substrate to be processed;
performing surface processing to the silicon-containing surface to increase a contact angle of the silicon-containing surface with respect to a resist material, comparing with the contact angle before the surface processing is performed;
supplying the resist material in sequence onto a different portion of one surface on the substrate to be processed after the surface processing;
transferring a template pattern to the resist material; and
repeating the supplying of the resist material and the transferring of the template pattern while changing a location of supplying the resist material onto the one surface on the substrate and arranging the template pattern,
wherein
the surface processing comprises forming a film on the silicon-containing surface, the film being formed by bonding silicon, carbon and fluorine, or being formed by bonding silicon, oxygen, carbon and fluorine; and
the forming of the film forms the film containing SiOCFn or SiCFn, where n is an integer that is one or more, at the circumferential edge portion that has not been covered with a shielding member, using CF based gas or a CF based solvent in a state where the shielding member is arranged on the first main surface of the substrate to be processed, the shielding member being configured to shield an inner circumferential side of the circumferential edge portion of the first main surface of the substrate to be processed.

US Pat. No. 10,249,544

METHOD OF INSPECTING SURFACE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method of inspecting a surface, the method comprising:preparing a substrate which is an inspection target;
selecting a spatial resolution of a first optical device,
the first optical device including a light source configured to emit light, an objective lens configured to transmit light received from the light source, a detector, and an imaging optical system configured to image light detected by the detector,
the selecting the spatial resolution of the first optical device including setting a magnification of the imaging optical system;
emitting multi-wavelength light toward a first measurement area of the substrate using the light source to emit the multi-wavelength light and the objective lens to transmit the multi-wavelength light received from the light source towards the first measurement area;
obtaining first wavelength-specific images using the imaging optical system and the detector;
generating first spectrum data of respective pixels based on the first wavelength-specific images;
extracting a spectrum of at least one first inspection area having a range of the first measurement area or less from the first spectrum data; and
analyzing the spectrum.

US Pat. No. 10,249,543

FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:an n-type field effect transistor (nFET) gate stack arranged over a first channel region of the device, the n-type gate stack comprising:
a dielectric layer arranged on a substrate;
a first nitride layer arranged on the dielectric layer, the first nitride layer comprising TaN;
a niobium aluminum carbonitride stack arranged on the first nitride layer:
a scavenging layer arranged on the niobium aluminum carbonitride stack, the scavenging layer comprising NbAlC or TiAlC;
a second nitride layer arranged on the scavenging layer, the second nitride layer comprising TiN or TaN; and
a gate electrode arranged on the second nitride layer; and
a p-type field effect transistor (pFET) gate stack arranged over a second channel region of the device, the p-type gate stack comprising:
the dielectric layer arranged on the substrate;
the first nitride layer arranged on the dielectric layer;
the scavenging layer arranged on the first nitride layer;
the second nitride layer arranged on the scavenging layer; and
the gate electrode arranged on the second nitride layer.

US Pat. No. 10,249,542

SELF-ALIGNED DOPING IN SOURCE/DRAIN REGIONS FOR LOW CONTACT RESISTANCE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first semiconductor fin formed in a pFET region of a substrate and a second semiconductor fin formed in a nFET region of the substrate;
a first gate formed over a first channel region of the first semiconductor fin and a second gate formed over a first channel region of the second semiconductor fin;
a first doped region formed on the first semiconductor fin and adjacent to the first gate, the first doped region comprising p-type dopants doped silicon germanium (SiGe), said p-type dopants selected from the group consisting of gallium (Ga), boron (B), difluoroboron (BF2), and aluminum (Al); and
a second doped region formed on the second semiconductor fin and adjacent to the second gate, the second doped region embedded below a surface of the second semiconductor fin, wherein the first doped region comprises an upper doped part and a bottom doped part, the first and second doped regions being adjacent to the first semiconductor fin but not in the first semiconductor fin, wherein the upper doped part has more dopants than the bottom doped part.

US Pat. No. 10,249,541

FORMING A HYBRID CHANNEL NANOSHEET SEMICONDUCTOR STRUCTURE

International Business Ma...

1. A method for fabricating a nanosheet semiconductor structure, the method comprising:forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material;
wherein the first material is different than the second material, and
further wherein forming the first nanosheet FET structure and the second nanosheet FET structure comprises:
creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region; and
creating a second inner spacer formation within a second SiGe channel, wherein the second SiGe channel is comprised in a second channel region of a second FET region,
forming a first stack on the first FET region and a second stack on the second FET region, wherein the first stack comprises a first substrate, the one or more first Si nanosheets, and the one or more first SiGe nanosheets, and wherein the second stack comprises the second substrate, the one or more second Si nanosheets, and the one or more second SiGe nanosheets;
forming a first pad insulator on the first channel region and a second pad insulator on the second channel region;
forming a first gate on the first pad insulator and a second gate on the second pad insulator;
forming a first hard mask on the first gate and a second hard mask on the second gate;
forming a first spacer on the first channel region, the first gate, and the first hard mask, and a second spacer on the second channel region, the second gate, and the second hard mask, wherein each spacer comprises silicon mononitride (SiN); and
forming the first channel region from the first stack and the second channel region from the second stack.

US Pat. No. 10,249,540

DUAL CHANNEL CMOS HAVING COMMON GATE STACKS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first semiconductor fin on a substrate;
forming a second semiconductor fin on the substrate;
forming an oxide layer over the first and second semiconductor fins; and
annealing the oxide layer at a temperature effective to increase a germanium concentration of the second semiconductor fin;
wherein said annealing does not increase a germanium concentration of the first semiconductor fin.

US Pat. No. 10,249,539

NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a first sacrificial layer between a first nanosheet and a second nanosheet;
forming a second sacrificial layer between a third nanosheet and a fourth nanosheet;
doping the first nanosheet;
forming another nanosheet over of the first nanosheet having been doped and the second nanosheet, subsequent to doping the first nanosheet;
wherein the first, second, another nanosheets are vertically stacked nanosheets in a first nanosheet stack and the third and fourth nanosheets are vertically stacked nanosheets in a second nanosheet stack;
concurrently removing the first sacrificial layer, the first nanosheet, and the second sacrificial layer, such that the first nanosheet is no longer present.

US Pat. No. 10,249,538

METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming, on a semiconductor substrate, a first lower source/drain region with a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region and a second lower source/drain region with a second semiconductor fin extending upward from a top surface of the second lower source/drain region,
wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and
wherein the first semiconductor fin and the second semiconductor fin are patterned from a monocrystalline epitaxial semiconductor layer and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively; and,
forming a first transistor with the first lower source/drain region and a second transistor with the second lower source/drain region.

US Pat. No. 10,249,537

METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a first fin of a first transistor in a substrate;
forming a second fin of a second transistor in the substrate;
disposing a first doped oxide layer comprising a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant;
disposing a mask over the first fin and removing the first doped oxide layer from the second fin;
removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first fin and directly onto the second fin, the second doped oxide layer comprising an n-type dopant or a p-type dopant that is different than the first dopant;
etching to recess the first doped oxide layer and the second doped oxide layer, leaving a layer of the first doped oxide layer on the first fin as a first doped oxide spacer and a layer of the second doped oxide layer on the second fin as a second doped oxide spacer;
annealing, after etching to recess, by a thermal process and under conditions sufficient to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin, and to drive the first dopant into the substrate beneath the first fin and the second dopant into the substrate beneath the second fin;
removing the first doped oxide spacer from the first fin and the second doped oxide spacer from the second fin;
depositing an oxide between the first fin and the second fin; and
forming a first gate on the first fin and a second gate on the second fin.

US Pat. No. 10,249,536

SEMICONDUCTOR FINS FOR FINFET DEVICES AND SIDEWALL IMAGE TRANSFER (SIT) PROCESSES FOR MANUFACTURING THE SAME

International Business Ma...

1. A semiconductor structure comprising:a semiconductor substrate; and
at least one semiconductor fin disposed on the semiconductor substrate, wherein the at least one semiconductor fin includes an inner core comprising a silicon germanium (SiGe) material having a germanium content of from 10 atomic % to 90 atomic %, and an outer shell laterally surrounding the inner core of the at least one semiconductor fin, wherein the outer shell is composed of Si.

US Pat. No. 10,249,535

FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming two gates across and perpendicular to first and second pairs of fins on a substrate;
forming first and second pairs of raised source/drain (RSD) between the two gates on the first and second pairs of fins, respectively;
forming a planar self-aligned contact (SAC) cap on each of the two gates;
forming a metal layer over the substrate coplanar with an upper surface of the SACs;
forming an oxide layer over the substrate subsequent to forming the metal layer;
forming a nitride layer over the oxide layer;
patterning the oxide and nitride layers, forming first and second oxide and nitride stacks above the first and second pairs of RSD, respectively, the first and second oxide and nitride stacks formed perpendicular to the two gates and each having with a width equal to or less than an overall width of a pair of fins;
etching the metal layer proximate to the oxide and nitride stacks forming trench silicide (TS) structure upper portions above the first and second pairs of RSD, and forming the TS structure in the metal layer over and perpendicular to the fins, the TS structure having first and second upper portions over the first and second pairs of RSD, respectively, each upper portion having a width equal to or less than an overall width of a pair of fins;
forming first and second spacers on opposite sides of the first and second upper portions, respectively;
removing the metal layer between adjacent first and second spacers;
forming an interlayer dielectric (ILD) over the substrate; and
forming a source/drain contact (CA) on each upper portion and a gate contact (CB) on one of the two gates through the ILD.

US Pat. No. 10,249,534

METHOD OF FORMING A CONTACT ELEMENT OF A SEMICONDUCTOR DEVICE AND CONTACT ELEMENT STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a contact element of a semiconductor device structure, the method comprising:forming an opening in an insulating material layer, said insulating material layer being provided over a semiconductor substrate, wherein said insulating material layer is exposed at a bottom of said opening and at sidewalls of said opening;
forming a contact liner portion within a lower portion of said opening, said contact liner portion covering said insulating material layer at said bottom of said opening and partially covering said insulating material layer at a lower sidewall portion of said sidewalls at said lower portion of said opening such that an upper sidewall portion at an upper portion of said opening is exposed to further processing;
forming an insulating liner portion within said opening, said insulating liner portion covering said exposed upper sidewall portion;
forming a contact liner within said opening, said contact liner covering said contact liner portion and said insulating liner portion; and
filling said opening with a conductive material, wherein said contact element is formed.

US Pat. No. 10,249,533

METHOD AND STRUCTURE FOR FORMING A REPLACEMENT CONTACT

International Business Ma...

1. A method for manufacturing a semiconductor device, comprising:forming a plurality of gate structures spaced apart from each other on a fin;
forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures;
forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures;
forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion;
removing a portion of the OPL to expose the inorganic plug portion;
selectively removing the inorganic plug portion; and
forming a contact on the fin in place of the removed inorganic plug portion.

US Pat. No. 10,249,532

MODULATING THE MICROSTRUCTURE OF METALLIC INTERCONNECT STRUCTURES

International Business Ma...

1. An apparatus, comprising:a single platform semiconductor processing chamber comprising a first sub-chamber, a second sub-chamber, a third sub-chamber, and a fourth sub-chamber, which is configured to process a substrate comprising a dielectric layer disposed on an upper surface of a substrate, wherein the dielectric layer comprises an opening etched in a surface of the dielectric layer;
wherein the first sub-chamber is configured to deposit a layer of metallic material to fill the opening and cover the surface of the dielectric layer with the metallic material;
wherein the second sub-chamber is configured to perform a furnace anneal process to reflow the layer of metallic material;
wherein the third sub-chamber is configured to deposit a stress control layer on the layer of metallic material subsequent to the furnace anneal process; and
wherein the fourth sub-chamber comprises a programmable hot plate, wherein the fourth sub-chamber is configured to perform a controlled thermal anneal process using the programmable hot plate to modulate a microstructure of the layer of metallic material from a first microstructure to a second microstructure while the stress control layer is disposed on the layer of metallic material, wherein the programmable hot plate is programmed to perform a controlled thermal anneal cycle with active heating and active cooling stages.

US Pat. No. 10,249,531

METHOD FOR FORMING METAL WIRING

Toshiba Memory Corporatio...

1. A method for forming a metal wiring, comprising:forming a first insulating layer on a substrate;
forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer;
patterning the second insulating layer to form a mask pattern;
etching the first insulating layer by a wet etching method using the mask pattern as a mask;
forming selectively a catalyst layer in a region where the first insulating layer is etched; and
forming a metal layer on the catalyst layer by an electroless plating method.

US Pat. No. 10,249,530

INTERLAYER DIELECTRIC FILM IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a fin on a substrate;
a gate structure disposed over the fin;
a doped strained region adjacent to the gate structure; and
a high temperature (HT) doped interlayer dielectric (ILD) layer disposed over the doped strained region, the HT doped ILD layer comprising dopant materials with a non-linear doping density throughout the HT doped ILD layer.

US Pat. No. 10,249,529

CHANNEL SILICON GERMANIUM FORMATION METHOD

INTERNATIONAL BUSINESS MA...

1. A semiconductor device, comprising:a first transistor area arranged on a silicon support layer of a common substrate, the first transistor area comprising a buried oxide layer arranged on the silicon support layer, and a silicon layer arranged directly on the buried oxide layer;
a second transistor area arranged adjacent to the first transistor area on the silicon support layer of the common substrate, the second transistor area comprising a buried oxide layer arranged on the silicon support layer, and a silicon germanium layer arranged directly on the buried oxide layer; and
a trench arranged between the first transistor area and the second transistor area that extends to the silicon support layer of the common substrate;
wherein all of the buried oxide layer of the second transistor comprises an implant comprising silicon dioxide and a reaction product of an implanted ion of phosphorus or boron and silicon dioxide.

US Pat. No. 10,249,528

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. An integrated circuit, comprising:a first insulation layer, wherein a first trench penetrates the first insulation layer;
a bottom plate partly disposed on the first insulation layer and partly disposed in the first trench;
a first patterned dielectric layer disposed on the bottom plate, wherein at least a part of the first patterned dielectric layer is disposed in the first trench;
a medium plate disposed on the first patterned dielectric layer, wherein at least a part of the medium plate is disposed in the first trench, and wherein the bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor;
a second patterned dielectric layer disposed on the medium plate; and
a top plate disposed on the second patterned dielectric layer, wherein the medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor, and the bottom plate is electrically connected with the top plate, wherein the top plate is electrically separated from the medium plate, and the bottom plate is electrically separated from the medium plate.

US Pat. No. 10,249,527

METHOD OF MANUFACTURING FLEXIBLE DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a flexible display device, comprising:providing a flexible substrate;
forming a first bonding layer on an entire surface of the flexible substrate;
patterning the first bonding layer to form a first bonding pattern by a photolithographic process, the first bonding pattern enclosing a display area without touching a boundary of the flexible substrate and being a multilayer;
forming a second bonding layer on an entire surface of a rigid substrate;
patterning the second bonding layer to form a second bonding pattern by a photolithographic process, the second bonding pattern corresponding to the first bonding pattern and being a multilayer;
bonding the first and second bonding patterns together to provide a bonding pattern between the flexible substrate and the rigid substrate such that at least a portion of the flexible substrate is in contact with the rigid substrate in the display area;
forming at least one display device on the display area of the flexible substrate; and
removing the bonding pattern by a cutting process performed so as to separate the flexible substrate having the display device thereon from the rigid substrate.

US Pat. No. 10,249,526

SUBSTRATE SUPPORT ASSEMBLY FOR HIGH TEMPERATURE PROCESSES

Applied Materials, Inc., ...

1. An electrostatic chuck comprising:a ceramic body having a top surface and a bottom surface;
one or more heating elements disposed in the ceramic body;
one or more electrodes disposed in the ceramic body; and
a plurality of adapter objects bonded to the bottom surface of the ceramic body by a metal bond, wherein collectively the plurality of adapter objects form a plurality of distributed over the bottom surface of the ceramic body at a plurality of different distances from a center of a circle defined by the bottom surface of the ceramic body, and wherein the plurality of openings comprise a first opening that is to couple to a fastener to secure a base plate against the bottom surface of the ceramic body.

US Pat. No. 10,249,525

DYNAMIC LEVELING PROCESS HEATER LIFT

APPLIED MATERIALS, INC., ...

1. A substrate support assembly, comprising:a support member that supports a pedestal having a substrate support surface;
a carrier plate attached to the support member; and
a positioning system comprising:
a base plate; and
two or more servo motor assemblies that each comprise a motor and a linear actuator, the servo motor assemblies each having a first end coupled to the base plate, wherein each of the linear actuators move the carrier plate in a direction that is non-parallel to the substrate supporting surface.

US Pat. No. 10,249,524

CASSETTE HOLDER ASSEMBLY FOR A SUBSTRATE CASSETTE AND HOLDING MEMBER FOR USE IN SUCH ASSEMBLY

ASM IP Holding B.V., Alm...

1. A cassette holder assembly for holding a cassette for storing at least one semiconductor material substrate in an interior space accessible from a front end of the cassette, the cassette holder assembly comprising:a base plate for receiving the cassette; and,
a right and a left holding member supported by the base plate to position the cassette on the right and left respectively seen from the front,
wherein the right and left holding members are substantially identical to each other,
wherein each of the holding members has at least two end surface to engage with the cassette to limit a position of the cassette in the front to the back direction substantially parallel to the base plate, the at least two end surfaces comprising at least one right end surface and at least one left end surface whereby the right end surface is located at the right of the holding member and the left end surface is located at the left of the holding member seen from the front, and
wherein the right end surface of the right holding member and the left end surface of the left holding member are arranged for engagement with the cassette.

US Pat. No. 10,249,523

OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC

KLA-Tencor Corporation, ...

1. A method for sorting wafers utilizing a slope of shape metric, comprising:receiving a plurality of wafers;
acquiring a set of wafer shape values from a surface of each wafer at a selected process level;
generating a set of residual slope shape metrics for each wafer by calculating a residual slope shape metric at each of a plurality of points of each wafer;
determining a neutral surface of each wafer in a chucked state;
calculating a neutral surface factor (NSF) for each wafer utilizing the determined neutral surface for each wafer and a plurality of positions associated with a plurality of patterns of each wafer;
determining a set of pattern placement error (PPE) residual values for each wafer, the PPE residual value for each point for each wafer being a product of at least the calculated NSF for each wafer, the residual slope shape metric for the point, and a thickness of the wafer;
determining one or more thresholds for the set of residual shape metrics suitable for maintaining the set of PPE residuals below one or more selected levels;
monitoring each of the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer; and
modifying one or more wafer fabrication processes, responsive to the monitoring of each of the plurality of wafers, in order to maintain the generated set of residual slope shape metrics for each wafer below the one or more thresholds.

US Pat. No. 10,249,522

IN-SITU TEMPERATURE MEASUREMENT IN A NOISY ENVIRONMENT

APPLIED MATERIALS, INC., ...

1. A lift pin for a semiconductor processing chamber, the lift pin comprising:a light pipe disposed within a body of the lift pin; and
a cover over an end of the light pipe and configured to contact a substrate to transmit thermal energy from the substrate to the light pipe, wherein the cover is a thermally conductive material.

US Pat. No. 10,249,521

WET-DRY INTEGRATED WAFER PROCESSING SYSTEM

LAM RESEARCH AG, Villach...

1. An apparatus for processing wafer-shaped articles, comprising:a vacuum transfer module;
an atmospheric transfer module;
a first airlock interconnecting said vacuum transfer module and said atmospheric transfer module;
an atmospheric process module connected to said atmospheric transfer module; and
a gas supply system configured to supply gas separately and at different controlled flows to each of said atmospheric transfer module, said first airlock and said atmospheric process module, so as to cause:
(i) a flow of gas from said first airlock to said atmospheric transfer module when said first airlock and said atmospheric transfer module are open to one another, and
(ii) a flow of gas from said atmospheric transfer module to said atmospheric process module when said atmospheric transfer module and said atmospheric process module are open to one another,
wherein the gas supply system includes
a first gas showerhead positioned in an upper region of said first airlock and configured to dispense gas downwardly within said first airlock,
a second gas showerhead positioned in an upper region of said atmospheric transfer module and configured to dispense gas downwardly within said atmospheric transfer module, and
a third gas showerhead positioned in an upper region of said atmospheric process module and configured to dispense gas downwardly within said atmospheric process module, and
wherein the gas supply system is configured to separately control respective flows of the first gas showerhead, the second gas showerhead, and the third gas showerhead.

US Pat. No. 10,249,520

TRANSFER PRINTING USING ULTRASOUND

INNOVASONIC, Inc., Dubli...

1. A method of transferring an object from a donor substrate surface to a receiving substrate surface comprising:providing a transfer device having a one or more ultrasonic transducers and an elastomeric material disposed over said transducers;
providing a donor substrate having a donor surface, said donor surface having at least one or more objects;
contacting at least a portion of said transfer device with at least a portion of said donor substrate, said portion having an object;
separating said transfer device from a donor surface at a separation rate required for transfer of said object from the donor substrate surface to the transfer device, thereby forming said transfer surface having said object deposited thereon;
contacting at least a portion of said object disposed on said transfer surface with said receiving surface of said receiving substrate,
directing a pulse of ultrasonic energy from one or more ultrasonic transducers located in close vicinity of said object, and separating said transfer surface from said object, thereby transferring said object to said receiving substrate.

US Pat. No. 10,249,519

LIGHT-IRRADIATION HEAT TREATMENT APPARATUS

SCREEN Holdings Co., Ltd....

1. A heat treatment apparatus for heating a disk-shaped substrate by irradiating the substrate with light, comprising:a chamber that houses a substrate;
a holder that holds said substrate in said chamber;
a light irradiation part in which a plurality of rod-shaped lamps are arranged in a light source region that is larger than a major surface of said substrate held by said holder and that faces the major surface;
a cylindrical louver that is provided between said light irradiation part and said holder, with a central axis of said louver passing through a center of said substrate, and that is impervious to light emitted from said light irradiation part, and an outer diameter of said louver being smaller than said light source region; and
a light-shielding member that is provided between said light irradiation part and said holder and that is impervious to the light emitted from said light irradiation part,
wherein said light-shielding member has a cut-out portion that allows light to reach a region of said substrate that is shielded from the light emitted from said light irradiation part by said louver.

US Pat. No. 10,249,518

POLISHING DEVICE AND POLISHING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A polishing device comprising:a stage configured to hold a wafer;
a polishing part configured to polish a film formed on a circumferential edge portion of the wafer;
a cleaner configured to clean the wafer;
a dryer configured to dry the wafer;
a detector configured to detect a residual portion of the film on the circumferential edge portion of the wafer and to identify a target region where the residual portion is located among regions of the circumferential edge portion of the wafer that divide the circumferential edge portion of the wafer along a direction that intersects a major surface of the wafer, the regions including at least a bottom region, a middle region, and a top region arranged from a lower surface side to an upper surface side of the wafer, the detector being configured to image the circumferential edge portion and to detect the residual portion according to brightness information of an imaged image, brightness of the residual portion in the imaged image being lower than brightness of an exposed portion of the wafer in the imaged image;
a first movable part configured to move the detector in the direction that intersects the major surface of the wafer such that the detector is movable along a surface of the circumferential edge portion of the wafer between the upper surface side and the lower surface side of the wafer; and
a controller configured to control the polishing part based on a state of the circumferential edge portion detected by the detector, including causing the polishing part to perform selective re-polishing on the wafer only at the target region on the circumferential edge portion of the wafer when the detector detects the residual portion of the film on the circumferential edge portion of the wafer after the wafer is polished by the polishing part, cleaned by the cleaner, and dried by the dryer, the controller causing the polishing part to polish the film formed on the circumferential edge portion of the wafer, causing the cleaner to clean the wafer, causing the dryer to dry the wafer, causing the detector to detect the residual portion of the film on the circumferential edge portion of the wafer by acquiring the brightness information from the imaged image of the circumferential edge portion of the wafer, and by analyzing the brightness information to identify the target region among the regions including at least the bottom region, the middle region, and the top region, and causing the polishing part to perform selective re-polishing on the wafer only at the identified target region to remove the detected residual portion of the film, to be executed in this order during a period that the wafer remains inside the polishing device.

US Pat. No. 10,249,517

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus for processing a substrate, comprising:a substrate holder for holding a substrate in a horizontal position;
an opposing member that opposes an upper surface of said substrate and has an opposing-member opening in a central part;
an opposing-member moving mechanism for holding said opposing member and moving said opposing member relative to said substrate holder in an up-down direction between a first position and a second position that is below said first position;
a substrate rotation mechanism for rotating said substrate along with said substrate holder about a central axis pointing in said up-down direction;
a processing liquid nozzle for supplying a processing liquid to said upper surface of said substrate through said opposing-member opening; and
a gas supply part for supplying a treatment atmospheric gas to a space between said opposing member and said substrate,
wherein said opposing member includes:
an opposing-member body that opposes said upper surface of said substrate and has said opposing-member opening in the central part;
an opposing-member tubular part that has a tubular shape and protrudes upward from a periphery of said opposing-member opening of said opposing-member body and in which said processing liquid nozzle is inserted;
an opposing-member flange part that annularly extends radially outward from an upper end of said opposing-member tubular part and is held by said opposing-member moving mechanism; and
a first uneven part in which a recessed portion and a raised portion are alternately disposed concentrically on an upper surface of said opposing-member flange part,
said opposing-member moving mechanism includes:
a holder lower part that opposes a lower surface of said opposing-member flange part in said up-down direction;
a holder upper part that opposes said upper surface of said opposing-member flange part in said up-down direction; and
a second uneven part in which a recessed portion and a raised portion are alternately disposed concentrically on a lower surface of said holder upper part,
in a state in which said opposing member is located at said first position, said opposing-member flange part is supported from below by said holder lower part, and said opposing member is held by said opposing-member moving mechanism and spaced above said substrate holder, and
in a state in which said opposing member is located at said second position, said opposing member is spaced from said opposing-member moving mechanism, is held by said substrate holder, and is rotatable along with said substrate holder by said substrate rotation mechanism, a labyrinth is formed as a result of the raised portion of one of said first uneven part and said second uneven part being disposed within the recessed portion of the other of said first uneven part and said second uneven part with a gap therebetween, and a seal gas is supplied to said labyrinth to seal a nozzle gap from a space located on the radially outer side of said labyrinth, said nozzle gap being a space between said processing liquid nozzle and said opposing-member tubular part.

US Pat. No. 10,249,516

UNDERFILL DISPENSING USING FUNNELS

International Business Ma...

1. A method for underfilling an array of objects on a substrate, comprising:forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate; and
curing the void-free layer of underfill material to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

US Pat. No. 10,249,515

ELECTRONIC DEVICE PACKAGE

Intel Corporation, Santa...

1. An electronic device package, comprising:a substrate;
an electronic component disposed on the substrate and electrically coupled to the substrate; and
an underfill material disposed at least partially between the electronic component and the substrate, wherein a lateral portion of the underfill material comprises an exposed lateral surface extending away from the substrate and intersecting a meniscus surface extending between the lateral surface and the electronic component, wherein a height of the lateral surface from the substrate is greater than a length of the meniscus surface, and wherein the lateral surface comprises an irregular surface that has a concavity from an upper surface of the substrate.

US Pat. No. 10,249,514

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a substrate including a main surface and formed with a recess that recedes from the main surface;
a conductive layer formed on the substrate;
a bonding layer electrically connecting the conductive layer to the semiconductor element, the bonding layer comprising a Ni layer and an alloy layer containing Sn; and
a sealing resin covering the semiconductor element at least from above,
wherein the substrate is made of an electrically insulative synthetic resin containing a filler,
the recess includes a bottom surface on which the semiconductor element is mounted and at least one intermediate surface connected to the main surface and the bottom surface, the bottom surface being orthogonal to a thickness direction of the substrate, and the intermediate surface being inclined with respect to the bottom surface,
the semiconductor element includes an inner surface that faces and is parallel to the bottom surface of the recess, and a gap between the inner surface and the bottom surface is filled with the sealing resin, the sealing resin covering the semiconductor element at least from above such that an integral part of the sealing resin extends into the gap,
the conductive layer includes a bottom surface conductive portion formed on the bottom surface of the recess, the bottom surface conductive portion comprising a flat plate part and a protrusion that protrudes from the flat plate part toward the semiconductor element, both the flat plate part and the protrusion being made of Cu, and
the protrusion of the bottom surface conductive portion is connected to the semiconductor element via the bonding layer.

US Pat. No. 10,249,513

ELECTRONIC DEVICE, ELECTRONIC APPARATUS, MOVING OBJECT, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. An electronic device comprising:an electronic component including external connection terminals; and
metal members each connected to an associated external connection terminal of the external connection terminals, wherein
each of the metal members has an elongated lead portion having a connecting portion, and a pad,
the connecting portion connects the elongated lead portion to the pad and is bent,
each pad has a longer width than the elongated lead portion in a direction perpendicular to an elongated direction,
each pad overlaps its associated external connection terminal in plan view,
at least a portion of each pad is located outside the external shape of the electronic component in plan view,
each pad and its associated external connection terminal are connected by means of a conductive bonding member,
each pad and the electronic component are bonded together with a resin,
the resin extends to a region of each pad located outside the external shape of the electronic component in plan view,
a portion of the external shape of the resin extends along the external shape of each pad that overlaps the electronic component in plan view and forms a fillet associated with each pad, thereby forming multiple spaced apart fillets, and
a surface of the electronic component, on which the external connection terminals are provided, is exposed without resin thereon between the fillets.

US Pat. No. 10,249,512

TUNABLE TIOXNY HARDMASK FOR MULTILAYER PATTERNING

INTERNATIONAL BUSINESS MA...

1. A multilayer lithographic structure comprisingan organic planarizing layer;
a titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride layer has an extinction coefficient less than 1.0 over a wavelength range from 400 nm to 800 nm and is configured to have an etch rate greater than 2 nm per minute in a wet etch solution comprising ammonium hydroxide, hydrogen peroxide and water at a temperature of 20° C.; and
a photosensitive resist layer on the titanium oxynitride layer.

US Pat. No. 10,249,511

CERAMIC SHOWERHEAD INCLUDING CENTRAL GAS INJECTOR FOR TUNABLE CONVECTIVE-DIFFUSIVE GAS FLOW IN SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS

LAM RESEARCH CORPORATION,...

1. An inductively coupled plasma processing apparatus comprising:a vacuum chamber;
a vacuum source adapted to exhaust the vacuum chamber;
a substrate support comprising a lower electrode on which a single semiconductor substrate is supported in an interior of the vacuum chamber;
a ceramic showerhead which forms an upper wall of the vacuum chamber wherein the ceramic showerhead includes a gas plenum in fluid communication with a plurality of showerhead gas outlets in a plasma exposed surface thereof for supplying a process gas as a diffusive gas flow to the interior of the vacuum chamber, a central opening in the ceramic showerhead that extends an entire thickness of the ceramic showerhead and the ceramic showerhead including a lower vacuum sealing surface which surrounds the plasma exposed surface and forms a vacuum seal with a vacuum sealing surface of the vacuum chamber;
a central gas injector disposed in the central opening of the ceramic showerhead, wherein the central gas injector includes one or more gas injector outlets, in a surface thereof that is exposed inside the vacuum chamber, for supplying the process gas as a convective gas flow to the interior of the vacuum chamber at least in a direction towards a center of the semiconductor substrate, wherein
the one or more gas injector outlets include a plurality of central gas outlets, wherein the plurality of central gas outlets are arranged to supply the process gas as the convective gas flow directly from the central gas injector into the vacuum chamber without passing through the gas plenum of the ceramic showerhead, and
the one or more gas injector outlets include a plurality of radial gas outlets arranged radially outward of the plurality of central gas outlets, wherein the plurality of radial gas outlets are arranged to supply the process gas as the diffusive gas flow radially outward from the central gas injector into the gas plenum of the ceramic showerhead and through the plurality of showerhead gas outlets;
an RF energy source which inductively couples RF energy through the ceramic showerhead and into the vacuum chamber to energize the process gas into a plasma state to process the semiconductor substrate; and
a control system configured to (i) control supply of the process gas as the convective gas flow through the central gas outlets via a first gas line at a first flow rate and (ii) control supply of, independently of the convective gas flow, the process gas as the diffusive gas flow through the showerhead gas outlets via a second gas line at a second flow rate, wherein the convective gas flow and the diffusive gas flow are supplied simultaneously, and wherein, to control the supply of the convective gas flow and the diffusive gas flow, the control system is further configured to select and control a pressure within the vacuum chamber, the first flow rate, and the second flow rate based on a desired eddy current above the semiconductor substrate, wherein, to achieve the desired eddy current, the control system is configured to independently control the first flow rate and the second flow rate.

US Pat. No. 10,249,510

ETCHING METHOD

UNITED MICROELECTRONICS C...

1. An etching method, comprising:providing a substrate, wherein a first region and a second region adjacent to the first region are defined on the substrate, and the substrate further comprises conductive lines located in the second region;
forming a material layer on the substrate, wherein the material layer is formed covering the conductive lines in the second region, and the material layer is partly located between the conductive lines;
forming a patterned mask on the material layer, wherein a part of the material layer is located between the patterned mask and the each of the conductive lines in a vertical direction, and the patterned mask comprises:
a first part covering the material layer on the first region; and
a second part located corresponding to the second region, wherein the second part comprises a lattice structure, and the lattice structure comprises:
openings, wherein each of the openings exposes a part of the material layer on the second region, and each of the openings is located corresponding to a part of at least one of the conductive line in the vertical direction; and
shielding parts, wherein each of the shielding parts is located between the openings adjacent to one another, and each of the shielding parts covers at least a part of the material layer located between two of the conductive lines adjacent to each other; and
performing an isotropic etching process to remove the material layer exposed by the openings and the material layer covered by the shielding parts.

US Pat. No. 10,249,509

SUBSTRATE CLEANING METHOD AND SYSTEM USING ATMOSPHERIC PRESSURE ATOMIC OXYGEN

Tokyo Electron Limited, ...

1. A method for cleaning a substrate in a single substrate cleaning system, the cleaning system comprising a pre-treatment system used in pre-treatment process and a wet cleaning system used in a wet cleaning process, the pre-treatment system including a processing chamber and a gas delivery sub-system, the method comprising:providing a substrate having a layer to be cleaned and an underlying dielectric layer, the underlying dielectric layer having a k-value;
delivering a pre-treatment gas into the processing chamber using the gas delivery sub-system, the pre-treatment gas comprising oxygen at a partial pressure and an oxygen temperature;
processing the pre-treatment gas in an atomic oxygen generator, the atomic oxygen generator powered using an RF, microwave, or electric power source and generating atomic oxygen at a target partial pressure of atomic oxygen;
exposing a portion of a surface of the substrate to the atomic oxygen;
obtaining one or more metrology measurements in the pre-treatment system during the exposing;
controlling two or more cleaning operating variables during the exposing using the one or more metrology measurements obtained in the cleaning system during the exposing in order to meet two or more cleaning objectives; and
optionally performing a wet cleaning process using the wet cleaning system;
wherein the two or more cleaning operating variables comprise substrate temperature, an atomic oxygen partial pressure, atomic oxygen temperature, atomic oxygen flow rate, a pre-treatment gas total pressure, and/or pre-treatment process time; and
wherein the two or more cleaning objectives comprise at least two cleaning objectives selected from a target pre-treatment cleaning percentage that is less than or equal to 100%, a target change in k-value of the underlying dielectric layer in pre-treatment, or a target pre-treatment process time.

US Pat. No. 10,249,508

METHOD FOR PREVENTING EXCESSIVE ETCHING OF EDGES OF AN INSULATOR LAYER

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:forming a first semiconductor layer on a semiconductor substrate;
forming a first insulator layer on the first semiconductor layer exposing an edge portion of the first semiconductor layer;
forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer;
forming a second insulator layer as a spacer on the exposed portion of the first insulator layer;
performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer.

US Pat. No. 10,249,507

METHODS FOR SELECTIVE ETCHING OF A SILICON MATERIAL

Applied Materials, Inc., ...

1. A method for etching features in a silicon material, the method comprising:performing a remote plasma process in a processing chamber formed from an etching gas mixture including chlorine containing gas to remove a silicon material disposed on a substrate, wherein the remote plasma process is configured to generate a remote plasma externally from an interior volume defined in the processing chamber without applying a RF source power to the processing chamber.

US Pat. No. 10,249,506

GAN-ON-SI SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GAN TRANSISTORS AND METHODS OF FABRICATION THEREOF

GaN Systems Inc.

1. A wafer scale nitride semiconductor device structure comprising:a silicon substrate having formed thereon a GaN epi-layer stack for a plurality of GaN die, said plurality of GaN die being arranged as an array with dicing streets therebetween;
each GaN die comprising:
a part of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two-dimensional electron gas (2DEG) active layer for a lateral GaN transistor; source, drain and gate electrodes of the lateral GaN transistor being provided on a front-side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of the GaN die, and an overlying interconnect structure comprising metallization and dielectric layers, the overlying interconnect structure defining respective source, drain and gate connections and contact areas; and
a trench structure formed around a periphery of each GaN die in said inactive area, the trench structure comprising a trench etched through layers of the overlying interconnect structure, through the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface region between the silicon substrate and the GaN epi-layer stack;
the trench structure further comprising a trench cladding, the trench cladding comprising a metal layer and an overlying dielectric passivation layer, the trench cladding extending over inner sidewalls of the trench and sealing surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region between the silicon substrate and the GaN epi-layer stack, the metal layer of the trench cladding contacting the silicon substrate within the trench, and the overlying dielectric passivation layer of the trench cladding sealing surfaces of the metal layer of the trench cladding within the trench.

US Pat. No. 10,249,504

ETCHING AND MECHANICAL GRINDING FILM-LAYERS STACKED ON A SEMICONDUCTOR SUBSTRATE

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:wet-etching a first film layer of a plurality of film layers stacked on a first side of a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, wherein the first film layer is an outermost film layer stacked on the semiconductor substrate;
wet-etching a second film layer of the plurality of film layers using a second chemical; and
using a mechanical grinding wheel to grind the semiconductor substrate from the first side to reduce a thickness of the semiconductor substrate.

US Pat. No. 10,249,503

PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. A printed circuit board comprising:an insulating layer;
a circuit layer disposed on a lower surface of the insulating layer; and
a metal post,
wherein a side surface of the metal post contacts the insulating layer, and the metal post extends from the lower surface of the insulating layer to an upper surface of the insulating layer; and
wherein a portion of the side surface of the metal post is spaced apart from the insulating layer.

US Pat. No. 10,249,502

LOW RESISTANCE SOURCE DRAIN CONTACT FORMATION WITH TRENCH METASTABLE ALLOYS AND LASER ANNEALING

International Business Ma...

1. A method for forming n-type source and drain contacts, the method comprising the steps of:forming a transistor on a substrate, the transistor comprising at least one gate stack, spacers alongside the gate stack, and epitaxial source and drain regions on opposite sides of the gate stack, wherein the epitaxial source and drain regions extend above the substrate and are in direct contact with one or more of the spacers;
depositing a dielectric over the transistor, such that the dielectric covers a top of the transistor;
forming contact trenches in the dielectric that extend down to the epitaxial source and drain regions, wherein the forming of the contact trenches comprises removing all of the dielectric from along at least one sidewall of the transistor;
forming a trench epitaxial material entirely above the substrate in the contact trenches on the epitaxial source and drain regions, wherein the trench epitaxial material is in direct contact with the one or more spacers;
implanting phosphorous into the trench epitaxial material to form an amorphous phosphorous-doped layer entirely above the substrate having a greater phosphorous concentration than the trench epitaxial material, and controlling the implanting to limit formation of the amorphous phosphorous-doped layer to the trench epitaxial material and at most only a top surface portion of the epitaxial source and drain regions such that, following the implanting, a majority of the epitaxial source and drain regions remains present beneath the amorphous phosphorous-doped layer, wherein the amorphous phosphorous-doped layer is in direct contact with the one or more spacers;
annealing the amorphous phosphorous-doped layer under conditions sufficient to form a crystalline phosphorous-doped layer entirely above the substrate having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3), wherein the crystalline phosphorous-doped layer is in direct contact with the one or more spacers;
lining the contact trenches with a metal liner, wherein the metal liner is a bilayer comprising a first metal liner layer present only at a bottom of the contact trenches and a second metal liner layer that is conformal and is present on the first metal liner layer at the bottom of the contact trenches and along sidewalls of the contact trenches; and
annealing the transistor to react the first metal liner layer with the crystalline phosphorous-doped layer to form a metal silicide layer on the epitaxial source and drain regions.

US Pat. No. 10,249,501

SINGLE PROCESS FOR LINER AND METAL FILL

International Business Ma...

1. A semiconductor structure comprising a gate structure, the gate structure comprising:a gate dielectric located along inner sidewalls of a gate spacer and a top surface and sidewalls of a channel region of a semiconductor fin located over a substrate;
a workfunction metal liner located on, and in direct physical contact with, the gate dielectric;
a first metal liner located on, and in direct physical contact with, the workfunction metal liner;
a second metal liner located on, and in direct physical contact with, the first metal liner; and
a metal gate electrode located on, and in direct physical contact, with the second metal liner, wherein the metal gate electrode is composed entirely of an alloy selected from the group consisting of MgAl, MgTi, MgV and AlV, the first metal liner is composed entirely of a carbide of the alloy that forms the metal gate electrode and the second metal liner is composed entirely of a nitride of the alloy that forms the metal gate electrode.

US Pat. No. 10,249,500

METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A method of manufacturing a substrate for semiconductor device, comprising:a step of forming on a back surface of a substrate a metal thin film layer having a transmittance with respect to red light or infrared light lower than that of the substrate;
a reaction step of diffusing a material of the metal thin film layer into the substrate by heating the substrate and the metal thin film layer so that a reaction layer is formed in which a material of the substrate and the material of the metal thin film layer are mixed with each other; and
a detection step of detecting, after the reaction step, the presence or absence of the substrate in accordance with the presence or absence of reflected red or infrared light from the metal thin film layer.

US Pat. No. 10,249,499

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A THIN SEMICONDUCTOR WAFER

ABB Schweiz AG, Baden (C...

1. A method for manufacturing a vertical power semiconductor device, wherein the method comprises the following steps:(a) providing a semiconductor wafer having a first main side and a second main side opposite to the first main side;
(b) applying a first impurity onto the first main side;
(c) forming a first oxide layer on at least the first main side of the semiconductor wafer;
(d) after step (c) bonding a carrier wafer to the first oxide layer on the first main side of the semiconductor wafer;
(e) after the bonding step (d) front-end-of-line processing on the second main side of the semiconductor wafer;
(f) after the front-end-of-line processing step (e) at least partially removing the carrier wafer and the first oxide layer on the first main side of the semiconductor wafer; and
(g) after the removing step (f) forming a back metallization layer on the first main side of the semiconductor wafer to form an Ohmic contact to the semiconductor wafer,
wherein
in step (c) partially doping the first oxide layer formed on the first main side of the semiconductor wafer with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer,
in step (e) diffusing the second impurity from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing,
in step (f) completely removing the carrier wafer and the first oxide layer on the first main side of the semiconductor wafer.

US Pat. No. 10,249,498

METHOD FOR USING HEATED SUBSTRATES FOR PROCESS CHEMISTRY CONTROL

TOKYO ELECTRON LIMITED, ...

1. A method of controlling doping of a substrate, the method comprising:providing the substrate in a process chamber of a doping system;
performing a doping process to impart a target dose on a surface of the substrate using an abruptness depth control technique that includes exposing the substrate to at least one of (i) a plasma at one or more predetermined temperatures, (ii) one or more predetermined source powers including at least one of a first source power and a second source power, (iii) one or more predetermined concentrations of dopant radicals, and (iv) one or more predetermined bias powers including at least one of a first bias power and a second bias power; and
controlling selected operating variables of plasma doping in order to meet doping objectives;
wherein performing the doping process further comprises:
exposing the substrate to light ion plasma, wherein the exposure to the light ion plasma is performed at the second source power and the second bias power; and
exposing the substrate to a surface wave plasma, wherein the exposure to the surface wave plasma is performed at the first source power and the first bias power;
wherein the second source power is less than the first source power, and the second bias power is less than the first bias power.

US Pat. No. 10,249,497

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device comprising:a silicon carbide semiconductor base of a first conductivity type;
a gate insulating film provided on a front surface of the silicon carbide semiconductor substrate and including any one or a plurality of an oxide film, a nitride film, and an oxynitride film; and
a gate electrode containing poly-silicon and provided on the gate insulating film, wherein
the gate insulating film has an interface state terminated by hydrogen or hydroxyl groups, wherein the hydrogen or the hydroxyl groups terminating the interface state is replaced with fluorine, and
a concentration of fluorine in the silicon carbide semiconductor device has a first peak and a second peak,
the first peak is in the gate electrode and is equal to or lower than 1×1018 atoms/cm3 and the second peak is in the gate insulating film and is equal to or higher than 1×1019 atoms/cm3.

US Pat. No. 10,249,496

NARROWED FEATURE FORMATION DURING A DOUBLE PATTERNING PROCESS

GLOBALFOUNDRIES Inc., Gr...

1. An interconnect structure comprising:a first interconnect having a first width and a cut extending through the first interconnect across the first width; and
a second interconnect having a first section with the first width, a second section with the first width, and a third section arranged between the first section and the second section,
wherein the third section of the second interconnect has a second width that is less than the first width.

US Pat. No. 10,249,495

DIAMOND LIKE CARBON LAYER FORMED BY AN ELECTRON BEAM PLASMA PROCESS

Applied Materials, Inc., ...

1. A method of forming a diamond like carbon layer, comprising:generating an electron beam plasma above a surface of a substrate disposed in a processing chamber, generating the electron beam plasma comprising:
applying a first RF source power to an electrode disposed in the processing chamber; and
bombarding the electrode to provide secondary electrons and a secondary electron beam flux to the surface of the substrate; and
forming a diamond like carbon layer on the surface of the substrate disposed in the processing chamber.

US Pat. No. 10,249,494

FREE-STANDING SUBSTRATE, FUNCTION ELEMENT AND METHOD FOR PRODUCING SAME

NGK INSULATORS, LTD., Na...

1. A self-supporting substrate comprising:a first nitride layer grown by a hydride vapor deposition method or an ammonothermal method and comprising a nitride of one or more elements selected from the group consisting of gallium, aluminum and indium; and
a second nitride layer grown by a sodium flux method on said first nitride layer and comprising a nitride of one or more elements selected from the group consisting of gallium, aluminum and indium;
wherein said first nitride layer comprises a plurality of single crystal grains arranged therein and extending between a pair of main faces of said first nitride layer;
said second nitride layer comprises a plurality of single crystal grains arranged therein and extending between a pair of main faces of said second nitride layer; and
said first nitride layer has a thickness larger than a thickness of said second nitride layer.

US Pat. No. 10,249,492

FABRICATION OF COMPOUND SEMICONDUCTOR STRUCTURES

International Business Ma...

1. A method for fabricating a compound semiconductor structure, the method comprising:providing a semiconductor substrate comprising a first semiconductor material;
forming an insulating layer on the semiconductor substrate;
forming an opening in the insulating layer, thereby exposing a seed surface of the substrate, the opening having sidewalls and a bottom, wherein the bottom corresponds to the seed surface of the substrate;
forming a cavity structure above the insulating layer, the cavity structure comprising the opening and a lateral growth channel extending laterally over the substrate;
growing a matching array on the seed surface of the substrate, the matching array comprising at least a first matching structure comprising a second semiconductor material and a second matching structure comprising a third semiconductor material;
growing the compound semiconductor structure comprising a fourth semiconductor material on a seed surface of the matching array;
wherein the first, the second, the third and the fourth semiconductor material are different from each other;
wherein:
the first matching structure provides a first matching level between the first and the second semiconductor material;
the second matching structure provides a second matching level between the second semiconductor material and the third semiconductor material; and
the compound semiconductor structure provides a third matching level between the third semiconductor material and the fourth semiconductor material;
wherein the first, the second and the third matching level address a plurality of matching parameters in a sequential way.

US Pat. No. 10,249,491

METHOD AND APPARATUS FOR FORMING DEVICE QUALITY GALLIUM NITRIDE LAYERS ON SILICON SUBSTRATES

Ultratech, Inc., San Jos...

1. A method comprising:supporting a silicon substrate inside a deposition chamber, the silicon substrate including a silicon substrate coating surface;
applying an aluminum nitride nucleation layer onto the silicon substrate coating surface using a first atomic layer deposition method;
applying a transition layer over the aluminum nitride nucleation layer using a second atomic layer deposition method, wherein applying the transition layer comprises applying a plurality of different material layers wherein each of the plurality of different material layers comprises an AlxGa1-xN compound and wherein each of the plurality of different AlxGa1-xN compounds is applied by a different atomic layer deposition method; and
applying a gallium nitride device layer over the transition layer using a third atomic layer deposition method.

US Pat. No. 10,249,490

NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:an insulating layer having a trench therein;
a semiconductor fin having a lower fin portion in the trench and an upper fin portion extending above the insulating layer, wherein the lower fin portion comprises a first semiconductor material, the upper fin portion having a top and sidewalls and comprising a second semiconductor material, and wherein the second semiconductor material meets the first semiconductor material at a non-planar interface; and
a third semiconductor material directly on the top and sidewalls of the upper fin portion and on a portion of the insulating layer, wherein the second semiconductor material is different than the first and third semiconductor materials.

US Pat. No. 10,249,489

USE OF SILYL BRIDGED ALKYL COMPOUNDS FOR DENSE OSG FILMS

VERSUM MATERIALS US, LLC,...

1. A chemical vapor deposition method for depositing an organosilicate film on at least a part of a substrate, the process comprising the steps of:providing a substrate within a vacuum chamber;
introducing into the vacuum chamber a gaseous structure forming composition comprising at least one organosilicon precursor selected from the group consisting of Formula (I) and Formula (II):
wherein,R1, R2, R3, R4, R5, and R6 are each independently selected from the group consisting of —CH3 and —OR8, wherein R8 is a C1-C4 alkyl group;
R7 is H or —CH3;
x is 1 or 2; and
n is 1, 2, 3, or 4, wherein at least one R7 is —CH3 when n is 1;
applying energy to the gaseous structure forming composition in the vacuum chamber to induce reaction of the at least one organosilicon precursor to deposit a film on at least a portion of the substrate.

US Pat. No. 10,249,488

SEMICONDUCTOR DEVICES WITH SAME CONDUCTIVE TYPE BUT DIFFERENT THRESHOLD VOLTAGES AND METHOD OF FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate;
a first transistor on said substrate, wherein said first transistor comprises a high-k dielectric layer, a first bottom barrier metal layer on said high-k dielectric layer, a second bottom barrier metal layer on said first bottom barrier metal layer, a work function metal layer on said second bottom barrier metal layer, and a low resistance metal directly contacting on said work function metal layer;
a second transistor on said substrate, wherein said second transistor comprises said high-k dielectric layer, said first bottom barrier metal layer on said high-k dielectric layer, said second bottom barrier metal layer on said first bottom barrier metal layer, and said low resistance metal directly contacting on said second bottom barrier metal layer; and
a third transistor on said substrate, wherein said third transistor comprises said high-k dielectric layer, said first bottom barrier metal layer on said high-k dielectric layer, and said low resistance metal directly contacting on said first bottom barrier metal layer, wherein said first transistor, said second transistor and said third transistor have same conductive type but different threshold voltage.

US Pat. No. 10,249,487

SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate processing method comprising:a substrate holding step of holding a substrate in a horizontal orientation by means of a substrate holding unit;
a liquid film forming step of supplying a processing liquid to an upper surface of the substrate held by the substrate holding unit to form a liquid film;
an upper surface covering step of discharging, above the liquid film formed on the upper surface of the substrate held by the substrate holding unit, an inert gas radially and parallel to the upper surface of the substrate from a center toward a peripheral edge of the substrate to form an inert gas stream flowing parallel to the upper surface of the substrate and covering the upper surface of the substrate; and
a liquid film removing step of discharging an inert gas toward the upper surface of the substrate to remove the liquid film, formed by the liquid film forming step, from the upper surface of the substrate during a time period in which the upper surface covering step is performed;
wherein the liquid film removing step includes
a perpendicular gas discharging step of rectilinearly discharging the inert gas perpendicular to the upper surface toward the center of the substrate so as to form a hole at a center of the liquid film and to spread the hole, and
an oblique gas discharging step of radially discharging the inert gas in an outwardly-directed oblique direction with respect to the upper surface of the substrate toward an intermediate position between the center and the peripheral edge of the substrate upper surface as a discharge target position, thereby generating an outwardly-directed oblique direction inert gas flow that further spreads the hole of the liquid film to push away the liquid film to the outer side of the substrate,
wherein, in the oblique gas discharging step, the inert gas is discharged toward a periphery of a central axis which extends perpendicular to the upper surface of the substrate, along a conical surface that is inclined with respect to the axis, to form the outwardly-directed oblique direction inert gas discharge having a conical profile that is obliquely incident on the upper surface of the substrate.

US Pat. No. 10,249,485

PULSED PLASMA ANALYZER AND METHOD FOR ANALYZING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A pulsed plasma analyzer comprising:a pulse modulator that controls an off-time of a pulsed plasma that includes a target radical;
an optical spectrometer that measures optical emissions of the pulsed plasma after the off-time and outputs optical emission data; and
a concentration estimating module that estimates a concentration of the target radical during the off-time, based on an initial optical emission value of the optical emission data that changes as a function of the off-time, and outputs the estimated concentration.

US Pat. No. 10,249,484

ELECTROSPRAY IONIZATION INTERFACE TO HIGH PRESSURE MASS SPECTROMETRY AND RELATED METHODS

The University of North C...

1. A method of analyzing a sample, comprising:providing a mass spectrometer comprising a vacuum chamber, a mass analyzer positioned in the vacuum chamber, and a sealing member positioned in a wall of the vacuum chamber in proximity to an entrance aperture;
positioning an electrospray ionization (ESI) device so that a portion of at least one emitter of the ESI device extends through the sealing member and into the vacuum chamber;
electrospraying ions of the sample from the ESI device directly into the vacuum chamber, wherein a gas pressure in the vacuum chamber is 50 mTorr or greater;
ejecting the ions from the mass analyzer;
detecting electrical signals corresponding to the ejected ions using at least one detector; and
generating mass spectral information based on the detected electrical signals to determine information about the sample.

US Pat. No. 10,249,483

ULTRA-COMPACT MASS ANALYSIS DEVICE AND ULTRA-COMPACT PARTICLE ACCELERATION DEVICE

1. A mass spectroscope, comprising:a main substrate having a first face and a second face,
a first substrate adhered to the first face of the main substrate,
a second substrate adhered to the second face of the main substrate,
a plurality of cavities penetrating from the first face of the main substrate to the second face of the main substrate,
at least one of the cavities penetrating from the first face of the main substrate to the second face of the main substrate is a mass spectroscopic cavity, and
a voltage or magnetic field generator configured to make orbits of charged particles change in the mass spectroscopic cavity for performing mass analysis.

US Pat. No. 10,249,482

TIME OF FLIGHT MASS SPECTROMETER

KRATOS ANALYTICAL LIMITED...

1. A time of flight mass spectrometer, comprising:an ion source including:
a first electrode, wherein the first electrode includes a sample plate for carrying a sample; and
a second electrode that has an aperture formed therein and is spaced apart from the first electrode;
a sample plate carrier on which the sample is mounted; and
a mechanism configured to translate the sample plate carrier laterally with respect to an ion optic axis so as to laterally offset the sample plate carrier with respect to the ion optic axis, wherein the ion optic axis extends between the first and second electrodes and through the aperture in the second electrode;
wherein the ion source is configured to apply voltages to the first and second electrodes to produce an extraction electric field in an extraction region between the first and second electrodes so as to extract ions from the extraction region through the aperture in the second electrode when the mass spectrometer is in use;
wherein a shield is formed on the first electrode and/or second electrode, wherein the shield is a raised element formed on a surface of one of the first and second electrodes that faces the other of the first and second electrodes so that the shield extends towards the other of the first and second electrodes, wherein the shield is configured to inhibit an electric field formed between edges of the first and second electrodes from penetrating into the extraction region between the first and second electrodes so as to inhibit changes in the extraction electric field in the extraction region when the sample plate is laterally offset with respect to the ion optic axis when the mass spectrometer is in use.

US Pat. No. 10,249,481

SYSTEM AND METHOD FOR FUSING CHEMICAL DETECTORS

Leidos, Inc., Reston, VA...

1. A chemical agent detector comprising:an ionization chamber including dual inlet ports and at least one ion source for generating unfiltered positive and negative ions from at least one sample received therein from a first direction, the ionization chamber further including a first gasket and first bracket on a first side thereof and a second gasket and a second bracket on a second side thereof for attaching to a first and second ion mobility spectrometry cell;
wherein the first ion mobility spectrometry cell is integrated with the ionization chamber via the first gasket and the first bracket for receiving at least a first portion of the unfiltered positive ions emanating therefrom in a second direction;
further wherein the second ion mobility spectrometry cell is integrated with the ionization chamber via the second gasket and the second bracket for receiving at least a first portion of the unfiltered negative ions emanating therefrom in a third direction;
a differential ion mobility spectrometry cell integrated with the ionization chamber for receiving at least a second portion of the unfiltered positive ions and at least a second portion of the unfiltered negative ions emanating therefrom in the first direction,
wherein the dual inlet ports for the sample are located on a front face of the ionization chamber and the differential ion mobility spectrometry cell is located on a back face of the ionization chamber opposite the front face and the first and second ion mobility spectrometry cells are on opposite sides of the ionization chamber and separated thereby, and further wherein the at least a first portion of the unfiltered positive ions and the at least a first portion of the unfiltered negative ions pass directly to the first ion mobility spectrometry cell and the second ion mobility spectrometry cell from the ionization chamber; and
a processor for separately receiving first detection data from the first ion mobility spectrometry cell, second detection data from the second ion mobility spectrometry cell, and third detection data from the differential ion mobility spectrometry cell and processing the first, second and third detection data to determine presence of one or more chemical agents in the sample; and
further wherein an exit port to the differential ion mobility spectrometry cell further includes at least one side port for allowing a first portion of a drift gas to exit prior to entering the differential ion mobility spectrometry cell.

US Pat. No. 10,249,480

TANDEM MASS SPECTROMETRY DATA PROCESSING SYSTEM

SHIMADZU CORPORATION, Ky...

1. A tandem mass spectrometry data processing system for processing MSn spectrum data obtained by performing a mass spectrometry for product ions obtained by dissociating ions collectively selected as precursor ions, the precursor ions originating from a plurality of different compounds and having mass-to-charge ratios within a predetermined mass-to-charge-ratio width, the system comprising:a) a compound database in which at least information on standard MSn spectra related to known compounds is stored;
b) a peak information collector for collecting peak information from an MSn spectrum created based on the MSn spectrum data obtained by an actual measurement;
c) a database searcher for finding a candidate compound for each of the ions of the plurality of compounds selected as the precursor ions, by performing a database search over the compound database based on a mass-to-charge-ratio value of the ion concerned and the peak information collected from an MSn spectrum by the peak information collector; and
d) a similarity calculator for retrieving, from the compound database, the standard MSn spectra for the candidate compounds selected for each of the ions of the plurality of compounds, for assuming a combination of the candidate compounds for the plurality of compounds, for creating a virtual MSn spectrum in which the standard MSn spectra corresponding to the candidate compounds included in the assumed combination are integrated with each other, and for calculating a degree of similarity between the virtual MSn spectrum and the measured MSn spectrum for each combination of the candidate compounds,
wherein the plurality of compounds is identifiable using the degree of similarity obtained by the similarity calculator.

US Pat. No. 10,249,479

MAGNET CONFIGURATIONS FOR RADIAL UNIFORMITY TUNING OF ICP PLASMAS

Applied Materials, Inc., ...

1. A plasma processing apparatus, comprising:a plasma source assembly, wherein the plasma source assembly comprises:
a first coil;
a second coil surrounding the first coil, the first coil and the second coil being electrically coupled in parallel;
a first magnetic device disposed outside the first coil and inside the second coil;
a third coil surrounding the second and first coils;
a second magnetic device disposed outside of the second coil and inside of the third coil; and
a permanent magnet distinct from the first and second magnetic devices disposed at a center of the first and second coils.