US Pat. No. 10,193,198

CELL MANAGEMENT DEVICE AND POWER SUPPLY DEVICE

PANASONIC INTELLECTUAL PR...

1. A battery management device comprising:an SOC estimation unit for estimating a State of Charge (SOC) of a lithium ion secondary battery;
a storage unit for retaining reference data for determining whether lithium is deposited in the lithium ion secondary battery; and
a lithium deposition determination unit for comparing a differential coefficient of a battery voltage with respect to an estimated SOC by the SOC estimation unit, with a differential coefficient of a battery voltage with respect to a reference SOC read from the storage unit, and for determining that lithium is deposited in the lithium ion secondary battery when a difference is observed between the differential coefficients.

US Pat. No. 10,193,196

INTERNAL BATTERY CELL COOLING WITH HEAT PIPE

MAINSTREAM ENGINEERDING C...

1. A battery cooling system, comprising at least one battery cell within a case, and a two-phase flow device having evaporator portion located centrally within and electrically isolated from the at least one battery cell, wherein the at least one battery cell wraps completely around an entire perimeter of the evaporator portion.

US Pat. No. 10,193,194

BATTERY ASSEMBLY CONTROLLER WHICH MONITORS VOLTAGES OF SECONDARY BATTERIES

PANASONIC INTELLECTUAL PR...

1. A battery assembly controller controlling terminal voltages of a plurality of series-connected secondary batteries to be equal, the controller comprising:a discharge circuit selectively reducing the terminal voltages of the secondary batteries; and
a monitoring circuit directly connected to positive and negative electrodes of the secondary batteries to monitor the terminal voltages of the secondary batteries, wherein
the discharge circuit includes:
a plurality of switches, each being connected to positive and negative electrodes of associated one of the secondary batteries, and
a control circuit controlling not to turn on odd-numbered and even-numbered switches simultaneously, where the switches are sequentially numbered as 1, 2, 3, . . . , from a high-potential side,
each of the switches is a MOS transistor, and
the discharge circuit further includes:
a plurality of resistors, each being connected between a gate and a source of one of the MOS transistors,
a plurality of current supplies, and
a plurality of other switches, each being connected between the gate of one of the MOS transistors and associated one of the current supplies.

US Pat. No. 10,193,178

REDOX FLOW BATTERY FRAME BODY, REDOX FLOW BATTERY, AND CELL STACK

Sumitomo Electric Inductr...

1. A frame body for a redox flow battery comprising a window,wherein the expressions A>C, B>D, and (B/A)?0.2 are satisfied, where A represents the length of a long side of a rectangle that envelops the window, B represents the width of a horizontal frame of the frame body corresponding to the long side, C represents the length of a short side of the rectangle, and D represents the width of a vertical frame of the frame body corresponding to the short side,
wherein the expression (D/C)?0.2 is satisfied.

US Pat. No. 10,193,176

SYSTEM AND METHOD FOR PRODUCTION OF ULTRA-PURE HYDROGEN FROM BIOMASS

The Research Foundation f...

1. An ultra-pure hydrogen synthesis system which comprises:a gasifier;
an oils and tars filtration system;
a steam generator;
a water gas shift reactor containing a catalyst, comprising oxides of copper, zinc and aluminum, that facilitates one or more chemical reactions between carbon monoxide and water in a temperature range of approximately 200° C. to approximately 250° C.;
a heat-exchange two-phase water condenser and separator;
a liquid-based, bubbling scrubber wherein a liquid contained within the scrubber includes
a methanol suspension of copper (I) chloride particles;
a hydrogen separator;
one or more fluid conduits, wherein the one or more fluid conduits connect to and establish fluid communication between each of the gasifier, the oils and tars filtration system, the steam generator, the water gas shift reactor, the scrubber, and the hydrogen separator.

US Pat. No. 10,193,164

FLOW FIELDS FOR ELECTROCHEMICAL CELL

Hydrogenics Corporation, ...

1. A set of flow field plates for an electrochemical cell comprising,a first flow field plate having a flow field wherein 50% or more of the area of the flow field of the first flow field plate is defined by a plurality of elongate ridges, and
a second flow field plate having a flow field wherein 50% or more of the area of the flow field of the second flow filed plate is defined by a plurality of discontinuous lines of short ridges, wherein the short ridges are less than 10 times as long as an average gap between successive elongate ridges, the gap measured perpendicular to the elongate ridges.

US Pat. No. 10,193,158

ELECTROLYTIC COPPER FOIL FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY COMPRISING THE SAME

KCF TECHNOLOGIES CO., LTD...

1. An electrolytic copper foil for a lithium secondary battery, which is applied as a negative electrode current collector of a lithium secondary battery,wherein the electrolytic copper foil for a lithium secondary battery has yield strength of 30 kgf/mm2 to 60 kgf/mm2, a surface area ratio of 1 to 3, and a weight deviation of 3% or below.

US Pat. No. 10,193,154

CATHODE COMPOSITION FOR PRIMARY BATTERY

Medtronic, Inc., Minneap...

1. A primary battery configured to supply operation power to an implantable medical device, the primary battery comprising:a cathode comprising an active material and at least one of a metal oxide or a metal fluoride, wherein the active material exhibits a first discharge capacity and the at least one of the metal oxide or the metal fluoride exhibits a second discharge capacity at a voltage lower than the first discharge capacity;
a current collector, wherein the cathode comprises a cathode layer on the current collector, wherein the cathode layer is formed of a mixture of the active material and the at least one of the metal oxide or the metal fluoride;
an anode comprising a metal as an electron source; and
an electrolyte between the cathode and anode, wherein the metal reacts with the electrolyte below a third discharge capacity at a voltage lower than the second discharge capacity to form a gas,
wherein the metal reacts with the active material at the first discharge capacity to consume the active material, and, following the consumption of the active material of the cathode, the metal reacts with the at least one of the metal oxide or the metal fluoride of the cathode prior to reacting with the electrolyte below the third discharge capacity, and
wherein the cathode includes an amount of the active material and the at least one of the metal oxide or the metal fluoride, and the anode includes an amount of metal such that an excess portion of the metal and an amount of the at least one of the metal oxide or the metal fluoride remains following the consumption of the active material, and wherein the amount of the at least one of the metal oxide or the metal fluoride is proportioned to consume all of the excess portion of the metal.

US Pat. No. 10,193,152

CATHODE ACTIVE MATERIAL PARTICLES, LITHIUM ION BATTERY PREPARED BY USING THE CATHODE ACTIVE MATERIAL PARTICLES, AND METHOD OF PREPARING THE CATHODE ACTIVE MATERIAL PARTICLES

SAMSUNG ELECTRONICS CO., ...

1. A lithium ion secondary battery comprising:a cathode comprising a plurality of cathode active material particles;
an electrolyte; and
an anode,
wherein a cathode active material particle of the plurality of cathode active material particles has a plate-shaped crystal structure having an aspect ratio of 2 to 1000,
wherein a major surface in at least one direction of the plate-shaped crystal structure is a 111 face,
wherein the cathode active material particle also has a spinel-type crystal structure, and
wherein the cathode active material particle has a composition represented by the formula LiCo2-xNixO4, wherein 0

US Pat. No. 10,193,136

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

AUTOMOTIVE ENERGY SUPPLY ...

1. A nonaqueous electrolyte secondary battery comprising:an electrode body;
an electrolyte solution; and
a laminate film package container housing the electrode body and the electrolyte solution, wherein
the laminate film package comprises a metal layer, a heat-seal layer, and a protective layer;
the electrode body includes a positive electrode, a negative electrode, and a separator disposed between the positive electrode and the negative electrode,
the positive electrode includes a positive electrode current collector, and a positive electrode active material layer formed on the positive electrode current collector,
the negative electrode includes a negative electrode current collector, and a negative electrode active material layer formed on the negative electrode current collector,
the positive electrode active material layer includes secondary particles of a lithium nickel cobalt manganese composite oxide,
the secondary particle includes a group of primary particles of a lithium nickel cobalt manganese composite oxide with a layered crystal structure,
the primary particle has an average cross-sectional area of 0.80 ?m2 or greater and 1.20 ?m2 or less,
the layered crystal structure has a lattice constant “c” of 14.240 ? or less, and
the lithium nickel cobalt manganese composite oxide is represented by the following Formula (1):
Li1-xNiaCobMncO2   (1)
wherein “x” satisfies 0?x?1, “a” satisfies 0.4?a?0.8, “b” satisfies 0.1?b?0.4, and “c” satisfies 0.1?c?0.5.

US Pat. No. 10,193,133

METHOD FOR MANUFACTURING OF METAL OXIDE NANOPARTICLES AND METAL OXIDE NANOPARTICLES THEREBY

KOREA ADVANCED INSTITUTE ...

1. A method for preparing metal oxide nanoparticles, the method comprising:dipping a cathode and an anode, each of the cathode and the anode being a different metal, in an inorganic electrolyte solution containing a halogen salt (step 1); and
applying a DC voltage between the anode and the cathode so as to oxidize the metal of the anode, to form, on the anode, a metal oxide forming an anode surface (step 2), whereby the metal oxide formed is an oxide of the metal of the anode,
wherein the anode is formed of at least one selected from the group consisting of indium, tin, zinc, zirconium, aluminum, titanium, nickel, iron and copper, and
wherein the cathode is formed of platinum.

US Pat. No. 10,193,129

PARALLEL BATTERY MODULE

CONTEMPORARY AMPEREX TECH...

1. A parallel battery module, comprising:a plurality of battery cells in parallel connection, each battery cell comprising:
a conducting top cover plate;
a first terminal that is assembled to be insulated from the conducting top cover plate;
a conducting connector that is electrically connected to the first terminal and insulated from the conducting top cover plate;
a second terminal that has an opposite polarity to the first terminal and is assembled to be electrically connected to the conducting top cover plate;
a bare cell that is electrically connected to the first terminal and the second terminal;
a fuse that is connected between the first terminal and the bare cell or connected between the second terminal and the bare cell; and
a conducting deformable piece that is electrically connected to the conducting top cover plate and is disposed below the conducting connector, wherein the conducting deformable piece deforms and becomes electrically connected to the conducting connector such that the first terminal and the second terminal are electrically connected to form an external short circuit when an internal gas pressure of a battery cell reaches a certain level;
a first current collection connector disposed on top of said plurality of battery cells and is electrically connected to the first terminals of said plurality of battery cells, wherein the first current collection connector comprises:
a plurality of first connection parts, a total number of the plurality of first connection parts being the same as a total number of the plurality of battery cells, each first connection part being electrically connected to the first terminal of a corresponding battery cell;
a first current collection part; and
one or more first fusing parts connected between the first current collection part and a corresponding first connection part for each of the plurality of first connection parts; and
a second current collection connector disposed on the top of said plurality of battery cells and is electrically connected to the second terminals of said plurality of battery cells,
wherein, when the conducting deformable piece of the battery cell deforms and is electrically connected to the conducting connector, an electrical connection between said battery cell and other battery cells of the plurality of battery cells is broken by blowing the one or more first fusing parts corresponding to said battery cell of the first current collection connector to electrically isolate said battery cell from the other battery cells.

US Pat. No. 10,193,116

CERAMIC COATING ON BATTERY SEPARATORS

Applied Materials, Inc., ...

1. A method, comprising:preparing a separator for an electrochemical storage device; and
using a controlled process to coat the separator with a ceramic layer having a desired thickness, wherein the controlled process comprises:
coating the separator with a first layer of ceramic particles having a first charge;
coating the first layer with a second layer of ceramic particles having a second charge opposite the first charge;
repeating the coating steps until a ceramic coating having the desired thickness is obtained.

US Pat. No. 10,193,114

ELECTRICITY STORAGE DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. An electricity storage device comprising:a plurality of batteries juxtaposed in a first direction to form a battery stack, each battery having a gas discharge valve on a first side, the gas discharge valve being configured to discharge a gas produced inside the battery, the first side being one side of a second direction, and the second direction being orthogonal to the first direction; and
a cooling path placed between the plurality of batteries that face each other in the first direction, a coolant that cools the batteries flowing through the cooling path, and the cooling path having:
an intake opening configured to take in the coolant to the cooling path, the intake opening being provided on a second side that is an opposite side to the first side;
a discharge opening configured to discharge the coolant, the discharge opening being provided on at least one of a third side or a fourth side, the third side and the fourth side being both sides of a third direction, the third direction being orthogonal to the second direction and to the first direction; and
a smoke discharge path provided on the first side of the plurality of batteries, the smoke discharge path configured to discharge the gas discharged from the gas discharge valve to an outside of the battery stack in the first direction without flowing in the cooling path,
wherein the cooling path is partitioned from the smoke discharge path to prevent communication between the cooling path and the smoke discharge path, wherein
the discharge opening is provided on each of the third side and the fourth side,
the cooling path has a T shape in a section orthogonal to the first direction, and
the cooling path includes:
a first path portion that extends from the intake opening toward the first side and then extends toward the third side; and
a second path portion that extends from the intake opening toward the first side and then extends toward the fourth side.

US Pat. No. 10,193,112

MODULAR ENERGY STORAGE COMPONENT ENCLOSURE

Lockheed Martin Energy, L...

17. An energy storage component (ESC) enclosure comprising:a plurality of ESC modules, each ESC module including at least one side portion having a plurality of side fastening mechanisms configured to be coupled to an adjacent ESC module, wherein the plurality of ESC modules are coupled together via the plurality of side fastening mechanisms to form an ESC enclosure;
a plurality of shelving kits, each shelving kit mounted to one of the ESC modules;
a roof coupled to the plurality of ESC modules; and
a plurality of panels coupled to the plurality of ESC modules about a perimeter of the ESC enclosure to form a shared air space within the ESC enclosure.

US Pat. No. 10,193,111

CONVERTIBLE BATTERY PACK

1. A battery pack comprising:a support board having a planar surface;
a plurality of contact pads arranged in a predefined configuration in the support board, each of the plurality of contact pads having an exposed planar surface generally parallel to the support board planar surface; and
a converter element including a housing having a first side facing the support board planar surface, at least one contact held in the housing, the at least one contact having a mating surface and extending towards the support board planar surface, and at least one spring held in the housing positioned between the housing and the at least one contact forcing the at least one contact towards the planar surface and the plurality of contact pads.

US Pat. No. 10,193,110

ELECTROCHEMICAL DEVICE, SUCH AS A MICROBATTERY OR AN ELECTROCHROMIC SYSTEM, COVERED BY AN ENCAPSULATION LAYER COMPRISING A BARRIER FILM AND AN ADHESIVE FILM, AND METHOD FOR FABRICATING ONE SUCH DEVICE

1. An electrochemical device comprising(1) a substrate,
(2) at least one stack of active layers containing lithium, said stack comprising
(2a) at least a first electrode connected to a first current collector and
(2b) at least a second electrode connected to a second current collector,
said stack being arranged on the substrate
(3) an encapsulation layer covering said at least one stack, the encapsulation layer comprising at least:
(3a) a barrier film presenting at least one electrically insulating surface and comprising at least one layer hermetic to oxidising species,
(3b) an adhesive film, provided with a first surface and a second surface,
the first surface being in contact with the electrically insulating surface of the barrier film and
the second surface covering a stack of active layers and a part of the substrate,
wherein the adhesive film comprises a juxtaposition of electrically conducting adhesive strips and of electrically insulating adhesive strips,
wherein two electrically conducting strips are separated by an electrically insulating strip to be electrically insulated from one another,
each electrically conducting strip being connected to the first current collector or to the second current collector of the stack of active layers.

US Pat. No. 10,193,108

SECONDARY BATTERY, ELECTRONIC DEVICE, AND VEHICLE

Semiconductor Energy Labo...

1. A secondary battery comprising:a film comprising flat portions and curved portions,
wherein the flat portions and the curved portions are alternately provided each other,
wherein a thickness of a top portion of each of the curved portions is thicker than a thickness of the flat portions.

US Pat. No. 10,193,090

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of forming a gate structure for a gate-all-around field effect transistor, the method comprising:disposing a carbon nanotube (CNT) over a substrate;
forming anchor structures on both ends of the CNT disposed over the substrate;
after the anchor structures are formed, recessing a part of the substrate under the CNT;
after the recessing, forming a gate dielectric layer wrapping around the CNT and forming a gate electrode layer over the gate dielectric layer; and
removing the CNT with the gate dielectric layer and the gate electrode layer from the substrate, thereby forming the gate structure.

US Pat. No. 10,193,089

DISPLAY DEVICE, ARRAY SUBSTRATE, AND MANUFACTURING METHOD

Shenzhen China Star Optoe...

1. An array substrate, comprising a substrate base, and two gates, a source, a drain, an active layer, and a pixel electrode on the substrate base, wherein the drain and the pixel electrode are connected together; the source and the drain contact the active layer, respectively; and the two gates control the conduction and cut off of the active layer, which in turn controls the conduction and cut off between the source and the drain;wherein the source, the two gates, the active layer, the drain, and the pixel electrode are sequentially stacked on the substrate base; and the drain and the pixel electrode are at a same level;
wherein the array substrate further comprises a buffer layer on the substrate base, wherein a buffer via is configured in the buffer layer, exposing the substrate base; the source is disposed in the buffer via; and the source has a top surface level with that of the buffer layer;
wherein the array substrate further comprises a passivation layer on the buffer layer and the source, wherein a passivation via is configured in the passivation layer, exposing the source; the two gates are disposed on the passivation layer oppositely across the passivation via; a gate metal, formed when the gates are formed, is disposed in the passivation via, contacting the source; and the gate metal has a top surface level with that of the passivation layer.

US Pat. No. 10,193,088

PEROVSKITE NANOCRYSTALLINE PARTICLES AND OPTOELECTRONIC DEVICE USING SAME

POSTECH ACADEMY-INDUSTRY ...

1. A perovskite nanocrystal particle capable of being dispersible in an organic solvent and comprising a perovskite nanocrystal structure,wherein the perovskite nanocrystal particle is an organic-inorganic-hybrid perovskite or an inorganic metal halide perovskite, and
the perovskite nanocrystal particle has a diameter greater than a Bohr exciton diameter on an area that is not affected by a quantum confinement effect.

US Pat. No. 10,193,087

PEROVSKITE AND OTHER SOLAR CELL MATERIALS

HEE Solar, L.L.C., Dalla...

1. A photovoltaic device comprising:a first electrode;
a second electrode;
an active layer disposed at least partially between the first and second electrodes, the active layer comprising:
photoactive material comprising a perovskite material;
a first interfacial layer comprising NiO; and
a second interfacial layer comprising carbon nanotubes.

US Pat. No. 10,193,086

LIGHT-EMITTING ELEMENT, COMPOUND, ORGANIC COMPOUND, DISPLAY MODULE, LIGHTING MODULE, LIGHT-EMITTING DEVICE, DISPLAY DEVICE, LIGHTING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

5. A method for synthesizing a compound, the method including:conducting a reaction according to the following scheme:

wherein X represents one of a halogen and a boronic acid,
wherein R1 to R5 separately represent any one of hydrogen, an alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted monocyclic saturated hydrocarbon having 5 to 7 carbon atoms, a substituted or unsubstituted polycyclic saturated hydrocarbon having 7 to 10 carbon atoms, and a substituted or unsubstituted aryl group having 6 to 13 carbon atoms,
wherein B represents the other of the halogen and the boronic acid, and
wherein A1 represents a group comprising at least one of a phenyl group, a fluorenyl group, a phenanthryl group, a triphenylenyl group, a dibenzothiophenyl group, a dibenzofuranyl group, a carbazolyl group, a benzimidazolyl group, a benzoxazolyl group, a benzthiazolyl group, and a triphenyl amine skeleton which are substituted or unsubstituted.

US Pat. No. 10,193,084

2,2?-BIBENZO[D]IMIDAZOLIDENE COMPOUND HAVING HETEROMONOCYCLIC GROUPS AT THE 1-, 1?-, 3- AND 3?- POSITIONS, AND ORGANIC LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE CONTAINING THE SAME

Canon Kabushiki Kaisha, ...

1. A 2,2?-bibenzo[d]imidazolidene compound expressed by the following general formula (1):
wherein Ar1 to Ar4 each represent a substituted or unsubstituted heteromonocyclic group; R1 to R8 each represent a hydrogen atom or a substituent selected from the group consisting of halogen atoms, alkyl groups having a carbon number in the range of 1 to 8, and substituted or unsubstituted aromatic hydrocarbon groups.

US Pat. No. 10,193,083

SPIRALLY CONFIGURED CIS-STILBENE/FLUORENE HYBRID COMPOUNDS AND ORGANIC LIGHT EMITTING DEVICE COMPRISING THE SAME

NICHEM FINE TECHNOLOGY CO...

1. A compound is represented by general formula I:
wherein A is carbon atom or silicon atom;
wherein R2 is independently a triazine group, pyrimidine group or phenyl group;
when R2 is a triazine group, R2 is selected from the group consisting of general formula II-1-1, general formula II-1-5 to general formula II-1-19;

when R2 is a pyrimidine group, R2 is selected from the group consisting of general formula II-2-1, general formula II-2-3 to formula II-2-10;

when R2 is phenyl group, R2 is selected from the group consisting of general formula II-3-2 to general formula II-3-4;

wherein R3 is independently a methyl group, phenyl group, tert-butyl group or two of R3 are linked by a single bond represented by general formula I-2, and

wherein R1 is a hydrogen atom, tert-butyl group or naphthyl group.

US Pat. No. 10,193,082

CONDENSED-CYCLIC COMPOUND AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A condensed-cyclic compound represented by Formula 1:
wherein, in Formula 1,
Ar11 is represented by one of Formulae 10-1 to 10-4:

wherein, in Formulae 1 and 10-1 to 10-4,
X1 is N or C(R1), X2 is N or C(R2), X3 is N or C(R3), X4 is N or C(R4), X5 is N or C(R5), X6 is N or C(R6), X7 is N or C(R7), X8 is N or C(R8), X11 is N or C(R11), X12 is N or C(R12), X13 is N or C(R13), X14 is N or C(R14), X15 is N or C(R15), X16 is N or C(R16), X17 is N or C(R17), and X18 is N or C(R18);
Y11 is O, S, N(R101), C(R101)(R102), or Si(R101)(R102);
Z11 is selected from N and C(A12);
Z12 to Z14 are each independently selected from C(A11) and C(A12); and at least one of Z12 to Z14 is C(A11); and
A11 comprises at least one cyano group (CN); and A11 is represented by one of Formulae 2-1 to 2-10:

wherein, in Formulae 2-1 to 2-10,
X21 is N or C(R21), X22 is N or C(R22), X23 is N or C(R23), X24 is N or C(R24), and X25 is N or C(R25);
A12, R1 to R8, R11 to R18, R101, R102, R21 to R25, and R201 to R203 are each independently selected from
a hydrogen, a deuterium, —F, a hydroxyl group, a cyano group (CN), a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group;
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one selected from a deuterium, —F, a hydroxyl group, a cyano group (CN), a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof;
a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group;
a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group, each substituted with at least one selected from a deuterium, —F, a hydroxyl group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, a dibenzothiophenyl group, and —Si(Q1)(Q2)(Q3); and
—Si(Q11)(Q12)(Q13),
b201 is selected from 1, 2, 3, 4, and 5;
b202 and b203 are each independently selected from 1, 2, 3, and 4; and
* indicates a carbon atom in Formula 1,
wherein Q1 to Q3 and Q11 to Q13 are each independently selected from a hydrogen, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group.

US Pat. No. 10,193,079

MATERIALS FOR ELECTRONIC DEVICES

Merck Patent GmbH, (DE)

1. A compound of the formula (I)
or a compound containing exactly two or three units of the formula (I) joined to one another via a single bond or an L group,
where:
L is any divalent or trivalent organic group;
A is a group of the formula (A)

bonded via the dotted bond;
Ar1 is the same or different at each instance and is an aromatic or heteroaromatic ring system which has 5 to 30 aromatic ring atoms and may be substituted by one or more R1 radicals;
Y is the same or different at each instance and is a single bond, BR1, C(R1)2, Si(R1)2, NR1, PR1, P(?O)R1, O, S, S?O or S(?O)2;
B is the same or different at each instance and is selected from H, a straight-chain alkyl group having 1 to 10 C atoms or a branched or cyclic alkyl group having 3 to 10 C atoms, each of which may be substituted by one or more R1 radicals, or an aryl group having 6 to 14 aromatic ring atoms, each of which may be substituted by one or more R1 radicals;
RA is the same or different at each instance and is CF3, CN, and an E group, which is an aryl or heteroaryl group which has 6 to 14 aromatic ring atoms and may be substituted by one or more R1 radicals, and which contains one or more V groups as constituents of the aromatic ring, where the V groups are the same or different at each instance and are selected from ?N—, ?C(F)—, ?C(CN)— and ?C(CF3)—, and where the heteroaryl group is not bonded via a nitrogen atom;
RB is selected from H, a straight-chain alkyl group having 1 to 10 carbon atoms or a branched or cyclic alkyl group having 3 to 10 carbon atoms, each of which may be substituted by one or more R1 radicals, and an aryl group having 6 to 14 aromatic ring atoms, which may be substituted by one or more R1 radicals;
R1 is the same or different at each instance and is H, D, F, C(?O)R2, CN, Si(R2)3, N(R2)2, P(?O)(R2)2, OR2, S(?O)R2, S(?O)2R2, a straight-chain alkyl or alkoxy group having 1 to 20 carbon atoms or a branched or cyclic alkyl or alkoxy group having 3 to 20 carbon atoms, where the abovementioned groups may each be substituted by one or more R2 radicals and where one or more CH2 groups in the abovementioned groups may be replaced by —R2C?CR2—, —C?C—,Si(R2)2, C?O, C?NR2, —C(?O)O—, —C(?O)NR2—, NR2, P(?O)(R2), —O—, —S—, SO or SO2, or an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, each of which may be substituted by one or more R2 radicals, where two or more R1 radicals may be joined to one another and may form a ring;
R2 is the same or different at each instance and is H, D, F or an aliphatic, aromatic or heteroaromatic organic radical having 1 to 20 carbon atoms, in which one or more hydrogen atoms may also be replaced by D or F; at the same time, two or more R2 substituents may be joined to one another and may form a ring.

US Pat. No. 10,193,077

BISCARBAZOLE DERIVATIVE, MATERIAL FOR ORGANIC ELECTROLUMINESCENCE DEVICE AND ORGANIC ELECTROLUMINESCENCE DEVICE USING THE SAME

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device comprising:a cathode;
an anode; and
a plurality of organic thin-film layers provided between the cathode and the anode, wherein
at least one of the organic thin-film layers is an emitting layer comprising a first host material, a second host material and a phosphorescent material that exhibits a phosphorescence,
the first host material is a compound represented by a formula (4) below, and
the second host material is a compound represented by a formula (5) below,

where
A1 represents a substituted or unsubstituted nitrogen-containing heterocyclic group having 1 to 30 ring carbon atoms,
when A1 has a substituent, the substituent of A1 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
A2 represents a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted nitrogen-containing heterocyclic group having 1 to 30 ring carbon atoms,
when A2 has a substituent, the substituent of A2 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
X1 and X2 are each a linking group and independently represent a single bond, substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms,
when X1 has a substituent and/or X2 has a substituent, the substituent for X1 and X2 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
Y1, Y3 and Y4 each independently represent a hydrogen atom, a fluorine atom, a cyano group, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted alkylsilyl group having 1 to 10 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 30 carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, a substituted or unsubstituted aromatic heterocyclic group having 2 to 30 ring carbon atoms, or a substituted or unsubstituted fused aromatic heterocyclic group having 2 to 30 ring carbon atoms,
Y2 represents a hydrogen atom, a fluorine atom, a cyano group, an unsubstituted alkyl group having 1 to 20 carbon atoms, an unsubstituted alkoxy group having 1 to 20 carbon atoms, an unsubstituted haloalkyl group having 1 to 20 carbon atoms, an unsubstituted haloalkoxy group having 1 to 20 carbon atoms, an unsubstituted alkylsilyl group having 1 to 10 carbon atoms, an unsubstituted arylsilyl group having 6 to 30 carbon atoms, an unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, an unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, an unsubstituted aromatic heterocyclic group having 2 to 30 ring carbon atoms, or an unsubstituted fused aromatic heterocyclic group having 2 to 30 ring carbon atoms,
adjacent ones of Y1 to Y4 are optionally bonded to each other to form a ring structure,
p and q represent an integer of 1 to 4, and r and s represent an integer of 1 to 3, and
when p and q are an integer of 2 to 4 and r and s are an integer of 2 to 3, a plurality of Y1 to Y4 may be the same or different,
(Cz?)aA3  (5)
where:
Cz represents a substituted or unsubstituted arylcarbazolyl group or carbazolylaryl group;
A3 represents a group represented by a formula (7A) below; and
a represents an integer of 1 to 3,
(M1)c?(L5)d?(M2)e  (7A)
where:
M1 and M2 each independently represent a substituted or unsubstituted nitrogen-containing fused aromatic heterocyclic ring having 2 to 40 ring carbon atoms, M1 and M2 being optionally the same or different;
L5 represents a single bond, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 carbon atoms, a substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 carbon atoms, a substituted or unsubstituted cycloalkylene group having 5 to 30 carbon atoms, or a substituted or unsubstituted fused aromatic heterocyclic group having 2 to 30 carbon atoms; and
c represents an integer of 0 to 2, d represents an integer of 1 to 2, and e represents an integer of 0 to 2 with a proviso that c+e is 1 or more.

US Pat. No. 10,193,066

APPARATUS AND TECHNIQUES FOR ANISOTROPIC SUBSTRATE ETCHING

VARIAN SEMICONDUCTOR EQUI...

12. A method of etching a substrate to form a surface feature, comprising:providing a chlorine-containing gas to a plasma chamber;
generating a plasma in the plasma chamber, the plasma comprising an etchant species derived from the chlorine-containing gas;
extracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to the substrate, the pulsed ion beam comprising an ON portion and an OFF portion; and
pulsing a level of RF power of the plasma in concert with the pulsed ion beam, wherein the plasma comprises a first RF power level during the ON portion and a second RF power level during the OFF portion, wherein the first RF power level is higher than the second RF power level,
wherein a duration of the OFF portion is less than a transit time of the etchant species from the plasma chamber to the substrate.

US Pat. No. 10,193,064

MEMORY CELLS INCLUDING DIELECTRIC MATERIALS, MEMORY DEVICES INCLUDING THE MEMORY CELLS, AND METHODS OF FORMING SAME

Micron Technology, Inc., ...

1. A memory cell, comprising:a threshold switching material comprising amorphous silicon doped with at least one of boron, aluminum, gallium, or phosphorus;
at least one doped dielectric material between the threshold switching material and at least one electrode of a pair of electrodes, the threshold switching material on a side of the at least one doped dielectric material; and
a memory material on a side of one of the electrodes of the pair of electrodes.

US Pat. No. 10,193,063

SWITCHING DEVICE FORMED FROM CORRELATED ELECTRON MATERIAL

ARM Ltd., Cambridge (GB)...

1. A method of constructing a switching device, comprising:forming, in a chamber, one or more voids between adjacent conductive traces of a plurality of conductive traces formed over an insulating substrate; and
converting localized portions of at least some of the adjacent conductive traces of the plurality of conductive traces to a correlated electron material (CEM), the CEM comprising an atomic concentration of at least 85.0% of an oxide of a d-block element or of an oxide of an f-block element, or an alloy of two or more oxides of d-block or f-block elements.

US Pat. No. 10,193,061

SPIN-ORBIT TORQUE MAGNETIZATION ROTATIONAL ELEMENT

TDK CORPORATION, Tokyo (...

1. A spin-orbit torque magnetization rotational element comprising:a ferromagnetic metal layer, a magnetization direction of which is configured to be changed;
a spin-orbit torque wiring bonded to the ferromagnetic metal layer; and
an interfacial distortion supply layer bonded to a surface of the spin-orbit torque wiring on a side opposite to the ferromagnetic metal layer,
wherein a degree of lattice mismatching between the spin-orbit torque wiring and the interfacial distortion supply layer is 5% or more.

US Pat. No. 10,193,060

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A magnetoresistive random access memory (MRAM) device, comprising:an insulating interlayer on a substrate, the insulating interlayer including an opening therethrough;
a first electrode in a lower portion of the opening, the first electrode having a pillar shape;
a second electrode on a sidewall of the opening, the second electrode contacting an edge portion of the first electrode and vertically protruding from an upper surface of the first electrode, and an upper surface of the second electrode having a ring shape;
an insulation pattern on the second electrode, the insulation pattern filling an upper portion of the opening; and
a variable resistance structure on the second electrode and the insulation pattern, the variable resistance structure including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked, wherein
the variable resistance structure includes a plurality of variable resistance structures,
an upper surface of the insulating interlayer between the plurality of variable resistance structures is lower than the upper surface of the second electrode, and is higher than the upper surface of the first electrode, and
an upper surface of the insulating interlayer under the variable resistance structure is higher than the upper surface of the insulating interlayer between the plurality of variable resistance structures.

US Pat. No. 10,193,056

MINIMAL THICKNESS SYNTHETIC ANTIFERROMAGNETIC (SAF) STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY FOR STT-MRAM

Headway Technologies, Inc...

1. A synthetic antiferromagnetic free layer structure, comprising:(a) a FL2 layer with intrinsic perpendicular magnetic anisotropy that is comprised of an (A1/A2)n laminate where n is an integer less than 6, A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Mg, Si, V, NiCo, and NiFe, or A1 is Fe and A2 is V, and wherein a magnetization direction thereof is perpendicular-to-plane of the FL2 layer;
(b) a CoFeB layer with perpendicular magnetic anisotropy in which a magnetization direction in said CoFeB layer is perpendicular-to-plane of the CoFeB layer and is established by antiferromagnetic coupling with the FL2 layer through an antiferromagnetic coupling layer formed between the FL2 layer and CoFeB layer; and
(c) the antiferromagnetic coupling layer that is made of a non-magnetic material to give an FL2 layer/antiferromagnetic coupling/CoFeB configuration or a CoFeB/antiferromagnetic coupling/FL2 layer configuration in a magnetic tunnel junction.

US Pat. No. 10,193,054

PIEZOELECTRIC CERAMIC, METHOD FOR PRODUCING PIEZOELECTRIC CERAMIC, AND PIEZOELECTRIC CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A piezoelectric ceramic comprising an alkali niobate compound as a main ingredient, the alkali niobate compound having a perovskite crystal structure represented by AmBO3 and containing at least one alkali metal, whereinSn exists in part of site A and Zr exists in part of site B.

US Pat. No. 10,193,052

DEVICE AND INSPECTION METHOD OF THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A device comprising:a substrate;
an element provided on the substrate;
a film on the substrate, the film and the substrate constituting a cavity in which the element is housed; and
a member provided outside the cavity, and capable of generating heat,
wherein the member generates the heat when current flows through the member.

US Pat. No. 10,193,050

HANDLE FOR A COOKING VESSEL, COMPRISING A LATENT HEAT SINK

SEB S.A., Ecully (FR)

1. A handle for a cooking vessel or lid that comprises at least one thermoelectric generator, wherein the thermoelectric generator comprises at least one first contact surface connected thermally to a heat sink, and the heat sink is comprised of a material that undergoes a phase transition when the material is heated to temperatures of 50° C. to 70° C.,wherein the heat sink fills a cavity of the handle with a heat diffuser comprising one or more rods that extend through the heat sink.

US Pat. No. 10,193,045

LIGHT EMITTING DEVICE HAVING HEAT DISIPATION TERMINAL ARRANGED ON SUBSTRATE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate having a first main surface, a second main surface that is opposite from the first main surface, and a mounting surface that is adjacent to at least the second main surface, the substrate including an insulating base material and a pair of connection terminals;
a plurality of light emitting elements mounted on the first main surface of the substrate;
a sealing member that is in contact with at least a part of a side surface of each of the light emitting elements, is formed substantially in the same plane as the substrate on the mounting surface, and a width of the sealing member between adjacent ones of the light emitting elements is larger than a width of the sealing member on an outside of an outermost one of the light emitting elements;
a light transmissive member that covers upper surfaces of the light emitting elements and a part of an upper surface of the sealing member, side surfaces of the light transmissive member being covered with the sealing member; and
a heat dissipation terminal that is arranged generally in the center on the second main surface of the substrate and that has a recess portion as viewed along a direction normal to the second main surface.

US Pat. No. 10,193,043

LIGHT EMITTING DEVICE PACKAGE WITH REFLECTIVE SIDE COATING

LUMILEDS LLC, San Jose, ...

1. A light-emitting device, comprising:a substrate;
a semiconductor structure disposed on the substrate, the semiconductor structure having an active region disposed between an n-type layer and a p-type layer;
a wavelength converter formed above the substrate;
an insulating side coating formed around the semiconductor structure; and
a reflective side coating formed around the wavelength converter and the substrate, the reflective side coating being stacked over the insulating side coating, the reflective side coating having a top surface that is flush with a top surface of the wavelength converter, and the reflective side coating having a bottom surface that is disposed above a top surface of the insulating side coating.

US Pat. No. 10,193,042

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a driving circuit disposed on the substrate;
a light-emitting unit disposed on the driving circuit and electrically connected to the driving circuit, wherein the light-emitting unit comprises:
a first semiconductor layer;
a quantum well layer disposed on the first semiconductor layer; and
a second semiconductor layer disposed on the quantum well layer, and the second semiconductor layer comprises a first top surface; and
a first protective layer disposed on the driving circuit and adjacent to the light-emitting unit, and the first protective layer comprises a second top surface and a plurality of conductive elements formed therein,
wherein an elevation of the first top surface is higher than an elevation of the second top surface.

US Pat. No. 10,193,040

LED PACKAGE WITH A PLURALITY OF LED CHIPS

Rohm Co., Ltd., Kyoto (J...

1. An LED package comprising:a substrate having a substrate main surface and a substrate back surface, which face opposite sides in a thickness direction;
a main surface electrode which is disposed on the substrate main surface, the main surface electrode including:
a first pad and a first die pad separated from each other, and
a second pad and a second die pad connected to each other;
a first LED chip which is mounted on the first die pad and has an electrode pad formed on a first chip main surface facing the same direction as the substrate main surface;
a first wire connecting the first pad and the electrode pad;
a second LED chip which is mounted on the second die pad and has a first electrode pad formed on a second chip main surface facing the same direction as the substrate main surface; and
a second wire connecting the second pad and the first electrode pad,
wherein the substrate main surface has a first side along a first direction perpendicular to the thickness direction of the substrate and a second side along a second direction perpendicular to both the thickness direction of the substrate and the first direction,
the first pad has a first base portion in contact with both the first side and the second side of the substrate main surface, and a first pad portion having one end connected to the first base portion,
the first pad portion of the first pad extends from the first base portion toward the first die pad, obliquely with respect to both the first direction and the second direction,
the second pad has a second base portion in contact with the first side of the substrate main surface, and a second pad portion having one end connected to the second base portion, and
the second pad portion of the second pad extends along the second direction.

US Pat. No. 10,193,039

METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEM

NICHIA CORPORATION, Anan...

1. A light emitting element mounting base member comprising:recesses formed on at least one surface of the light emitting element mounting base member;
a plurality of electrical conductor cores;
a plurality of light-reflecting insulating members that each cover a lateral surface of each of the electrical conductor cores; and
a light blocking resin that is disposed between the insulating members,
wherein the light blocking resin exposes one or more upper surfaces of the electrical conductor cores, one or more lower surfaces of the electrical conductor cores, and the insulating members disposed around the one or more upper surfaces and the one or more lower surfaces of the electrical conductor cores, and
the light blocking resin serves as lateral surfaces of recesses.

US Pat. No. 10,193,038

THROUGH BACKPLANE LASER IRRADIATION FOR DIE TRANSFER

GLO AB, Lund (SE)

1. A method of manufacturing an assembly of a backplane and light emitting devices, the method comprising:providing a substrate with dies of light emitting devices thereupon, wherein a device-side bonding pad is provided on each of the light emitting devices;
bonding at least one of the light emitting devices to the backplane without bonding at least another of the light emitting devices to the backplane;
dissociating the at least one bonded light emitting device from the substrate by irradiating a laser beam through the substrate and onto each region of the substrate in contact with the at least one bonded light emitting device while the at least another of the light emitting devices remains attached to the substrate and not bonded to the backplane; and
separating the substrate and the at least another of the light emitting devices from an assembly of the backplane and the at least one bonded light emitting device that is bonded to the backplane;
wherein the backplane comprises a metal interconnect layer including a plurality of metal interconnect structures embedded in at least one insulating material and providing electrical connections between the light emitting devices on the backplane and input/output pins of the backplane.

US Pat. No. 10,193,033

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements each having a pair of electrodes on a lower surface thereof;
a light-transmissive member disposed on an upper surface of each of the light emitting elements to transmit light from the light emitting elements;
a first member disposed on one or more lateral surfaces of the light-transmissive member, and constituting part of an upper surface of the light emitting device with an upper surface of the light-transmissive member being exposed from the first member; and
a second member surrounding an outer periphery of each of the light emitting elements, and constituting part of a bottom-most surface of the light emitting device,
wherein lower surfaces of the electrodes are exposed from the second member to constitute part of the bottom-most surface of the light emitting device,
the first member and the second member respectively constitute parts of an outermost lateral surface of the light emitting device, and
the second member is in contact with a part of each of the light emitting elements.

US Pat. No. 10,193,032

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a light emitting device comprising:providing a substrate including a placement region for placing a light emitting element on a top surface;
mounting the light emitting element in the placement region; and
forming a frame body surrounding the placement region on the substrate by
arranging a first frame body by discharging a resin material on the substrate to surround the placement region, and
successively arranging a second frame body having a larger diameter than the first frame body on the first frame body and having the same thickness as the first frame body by continuously discharging the resin material from the arranging of the first frame body.

US Pat. No. 10,193,029

LIGHT CONVERSION DEVICE AND DISPLAY DEVICE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A light conversion device, comprising:a light source; and
a light conversion film provided on one surface of the light source,
wherein the light conversion film includes a first light conversion film containing one first organic fluorescent dye, and a second light conversion film disposed to be closer to the light source than the first light conversion film and containing one second organic fluorescent dye, and a maximum light emission wavelength of the second light conversion film is smaller than a maximum light emission wavelength of the first light conversion film when the light is irradiated from the light source,
wherein the second organic fluorescent dye of the second light conversion film is a green emission fluorescent dye having a maximum emission wavelength of 500 to 550 nm and the first organic fluorescent dye of the first light conversion film is a red emission fluorescent dye having a maximum emission wavelength of 600 to 660 nm, and
wherein the organic fluorescent dye has a full width at half maximum (FWHM) of 60 nm or less and a molecular absorption coefficient of 50,000 to 150,000 M?1 cm?1.

US Pat. No. 10,193,027

LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a resin package comprising:
a plurality of leads that includes:
a first lead having an upper surface, and
a second lead having an upper surface,
a first resin portion having at least one inner lateral wall surface,
a second resin portion, and
a third resin portion having an upper surface,
the plurality of leads and the at least one inner lateral wall surface of the first resin portion defining a recess,
the third resin portion being located between the first lead and the second lead,
the upper surface of the first lead, the upper surface of the second lead and the upper surface of the third resin portion located at a bottom of the recess, and
the second resin portion disposed surrounding an element mounting region at the bottom of the recess; and
at least one light emitting element disposed on the element mounting region at the bottom of the recess of the resin package,
wherein at least one of the at least one inner lateral wall surface of the recess has at least one protruding portion that protrudes toward the at least one light emitting element, and
wherein a region of the recess between the at least one inner lateral wall surface and the second resin portion is covered by a light-reflective member.

US Pat. No. 10,193,023

LIGHT-EMITTING DIODE CHIP

PlayNitride Inc., Tainan...

1. A light-emitting diode chip, comprising:a p-type semiconductor layer;
a light-emitting layer;
an n-type semiconductor layer, the light-emitting layer being disposed between the p-type semiconductor layer and the n-type semiconductor layer, and the n-type semiconductor layer comprising:
a first n-type semiconductor sub-layer;
a second n-type semiconductor sub-layer; and
an ohmic contact layer, disposed between the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer, wherein the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer are separated by the ohmic contact layer; and
a first metal electrode, disposed on the first n-type semiconductor sub-layer, wherein a region of the first n-type semiconductor sub-layer located between the first metal electrode and the ohmic contact layer contains metal atoms diffusing from the first metal electrode, such that ohmic contact is formed between the first metal electrode and the ohmic contact layer.

US Pat. No. 10,193,013

LED STRUCTURES FOR REDUCED NON-RADIATIVE SIDEWALL RECOMBINATION

Apple Inc., Cupertino, C...

1. A light emitting diode (LED) comprising:a p-n diode layer including:
a top doped layer doped with a first dopant type;
a bottom doped layer doped with a second dopant type opposite the first dopant type; and
an active layer between the top doped layer and the bottom doped layer; and
p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer; and
a semiconductor passivation layer formed on the p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer, wherein the semiconductor passivation layer spans underneath the bottom doped layer and completely covers a bottom surface of the bottom doped layer.

US Pat. No. 10,193,006

NANOWIRE COMPOSITE STRUCTURE AND METHODS OF FORMING THE SAME, SENSING DEVICE AND METHODS OF FORMING THE SAME AND PROTECTIVE STRUCTURES OF A NANOWIRE

NATIONAL TSING HUA UNIVER...

1. A sensing device, comprising:a substrate;
a first electrode and a second electrode disposed on the substrate; and
a plurality of nanowires disposed on the substrate and between the first electrode and the second electrode, wherein the plurality of nanowires comprises a first nanowire in contact with the first electrode and a second nanowire in contact with the second electrode, and every nanowire of the plurality of nanowires is in contact with at least another nanowire, and wherein the plurality of nanowires is a photo sensor, and the sensing device is used for a bend sensing, a somatosensory sensing or a pressure sensing.

US Pat. No. 10,192,996

THIN FILM TRANSISTOR, DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising:a base substrate;
an active layer on the base substrate comprising a channel region, a source electrode contact region, and a drain electrode contact region;
an etch stop layer on a side of the channel region distal to the base substrate covering the channel region;
a source electrode on a side of the source electrode contact region distal to the base substrate; and
a drain electrode on a side of the drain electrode contact region distal to the base substrate;
wherein the active layer is made of a semiconductor material comprising M1OaNb, wherein M1 is a single metal or a combination of metals, a>0, and b?0;
the source electrode and the drain electrode are made of a metal material;
the etch stop layer is made of a doped semiconductor material comprising M1OaNb doped with a dopant; the doped semiconductor material being substantially resistant to an etchant for etching the metal material; and
a thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.

US Pat. No. 10,192,991

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A manufacturing method of an oxide thin film transistor, comprising:providing a substrate;
depositing an active layer film, a gate insulator layer film, and a gate metal layer film on the substrate in sequence, and patterning the active layer film, the gate insulator layer film, and the gate metal layer film to form an active layer, a gate insulator layer and a gate metal layer respectively; and
depositing an insulator layer film at a first temperature and patterning the insulator layer film to form an insulator layer;
wherein a portion of the active layer, which portion is not overlapped with the gate metal layer, is treated to become conductive to provide a conductor during deposition of the insulator layer film.

US Pat. No. 10,192,983

LDMOS WITH ADAPTIVELY BIASED GATE-SHIELD

Silanna Asia Pte Ltd, Si...

1. A system, comprising:a lateral diffusion field effect transistor comprising:
a source region of doped semiconductor material that is electrically coupled to a metallic source contact,
a first drain region of doped semiconductor material that has a lower dopant concentration than the source region,
a second drain region of doped semiconductor material that has a higher dopant concentration than the first drain region and forms an electrically conductive path between the first drain region and a metallic drain contact,
an active region between the source region and the first drain region,
a gate dielectric between a gate electrode and the active region, wherein the active region is responsive to a control signal applied to the gate electrode, and
an electrically conductive shield plate separated from the source contact and respective portions of the gate electrode and the first drain region by an interlayer dielectric; and
a control circuit electrically coupled to the shield plate and configured to apply to the shield plate a variable voltage that is temporally offset from the control signal applied to the gate electrode, wherein the variable voltage is applied to the shield plate at a first level that increases conductivity in the first drain region in a turn-on transition of the lateral diffusion field effect transistor, and the variable voltage is applied to the shield plate at a second level that decreases conductivity in the first drain region in a turn-off transition of the lateral diffusion field effect transistor.

US Pat. No. 10,192,975

LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR

Wuhan China Star Optoelec...

1. A low temperature polycrystalline silicon thin film transistor, wherein: the low temperature polycrystalline silicon thin film transistor comprises: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains source electrodes and drain electrodes formed respectively on the first contact hole and the second contact hole; and the semiconductor layer being a low temperature poly silicon layer, and one of a reflective layer and an insulation layer being disposed between the buffer layer and the semiconductor layer;wherein the low temperature polycrystalline silicon thin film transistor comprises a pixel thin film transistor and a driving thin film transistor; the substrate comprises a pixel region and a peripheral driving region; the pixel region is used for forming the pixel thin film transistor; and the peripheral driving region is used for forming the driving thin film transistor;
the driving thin film transistor comprises a substrate located inside the peripheral driving region, and all the buffer layer, the semiconductor layer, the gate insulation layer, gates, the dielectric layer and the passivation layer are formed sequentially from the top on the substrate inside the peripheral driving region; the first contact hole and the second contact hole are formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and the source electrodes and the drain electrodes are formed respectively on the first contact hole and the second contact hole; wherein the one of the reflective layer and the insulation layer is disposed between the buffer layer and the semiconductor layer; and
wherein the pixel thin film transistor comprises: a substrate inside the pixel region, and all the buffer layer, the semiconductor layer, the gate insulation layer, gates, the dielectric layer and the passivation layer are formed sequentially from the top on the substrate inside the pixel region; the first contact hole and the second contact hole are formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and the source electrodes and the drain electrodes are formed respectively on the first contact hole and the second contact hole.

US Pat. No. 10,192,966

SEMICONDUCTOR DEVICES INCLUDING RECESSED GATE ELECTRODE PORTIONS

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first active pattern and a second active pattern on a substrate;
a first gate electrode and a second gate electrode respectively extending across the first active pattern and the second active pattern;
an insulation pattern located between the first and second gate electrodes to separate the first and second gate electrodes from one another, and
a device isolation layer filling a trench between the first and second active patterns and covering lower sidewalls of the first and second active patterns,
wherein the first gate electrode, the insulation pattern, and the second gate electrode are arranged along a first direction, and
wherein the first gate electrode comprises:
a first part extending in the first direction; and
a second part between the first active pattern and the insulation pattern, the second part including a top surface having a height lower than a height of a top surface of the first part closest to the second part,
wherein the second part vertically overlaps with the device isolation layer, and
wherein the height of the top surface of the second part decreases with approaching the insulation pattern from the first part and then increases again after reaching an inflection point in the top surface of the second part.

US Pat. No. 10,192,962

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer, including a front surface having a plurality of first trenches formed therein and having a second trench formed therein in a region between mutually adjacent ones of the plurality of first trenches;
channel regions, formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer;
a first insulating film, covering an inner surface of each of the first trenches at a bottom portion side of each of the first trenches;
a field plate electrode, embedded in each of the first trenches so as to face the semiconductor layer across the first insulating film;
a first gate insulating film covering a lateral surface of each of the first trenches above the first insulating film in each of the first trenches;
a first gate electrode, embedded at an opening portion side of each of the first trenches so as to face the channel regions across the first gate insulating film;
a second insulating film, interposed between the field plate electrode and the first gate electrode in each of the first trenches;
an embedded insulating film, embedded at a bottom portion side of the second trench;
a second gate insulating film covering a lateral surface of the second trench above the embedded insulating film in the second trench; and
a second gate electrode, embedded at an opening portion side of the second trench so as to face the channel regions across the second gate insulating film.

US Pat. No. 10,192,953

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to said first main surface;
an epitaxial layer formed on said first main surface, said epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which said silicon carbide substrate is located;
a trench which is formed in said epitaxial layer and includes side walls intersecting with said third main surface and a bottom portion connected to said side walls; and
an embedded region, which is formed in said trench and has a second conductivity type different from said first conductivity type, said trench being filled with said embedded region;
an opening of said trench being wider than said bottom portion, and said epitaxial layer adjacent to said embedded region and said embedded region constituting a superjunction structure, said silicon carbide semiconductor device further comprising:
an impurity region formed on said embedded region and having said second conductivity type;
a first electrode provided on said impurity region; and
a second electrode in contact with said second main surface.

US Pat. No. 10,192,944

THIN FILM TRANSISTOR ARRAY PANEL WITH DIFFUSION BARRIER LAYER AND GATE INSULATION LAYER AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a semiconductor disposed on the substrate;
a first gate insulation layer disposed on the semiconductor;
a first diffusion barrier layer disposed on the first gate insulation layer;
a second diffusion barrier layer disposed on the first gate insulation layer and in contact with a lateral surface of the first diffusion barrier layer;
a first gate electrode disposed on the first diffusion barrier layer; and
a source electrode and a drain electrode connected to the semiconductor,
wherein the semiconductor is between the substrate and the first diffusion barrier layer, and
wherein the first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.

US Pat. No. 10,192,940

DOUBLE SIDED ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND ITS MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method for a double sided organic light-emitting display apparatus, comprising:providing a rigid substrate;
forming at least one transmission flexible substrate and at least one reflective flexible substrate on the rigid substrate;
forming a display substrate having a plurality of switching elements on the at least one transmission flexible substrate and the at least one reflective flexible substrate; and
forming at least one top-emission OLED light-emitting layer and at least one bottom-emission OLED light-emitting layer on the display substrate, wherein the at least one top-emission OLED light-emitting layer is corresponding to the at least one reflective flexible substrate and the at least one bottom-emission OLED light-emitting layer is corresponding to the at least one transmission flexible substrate;
wherein the at least one transmission flexible substrate and the at least one reflective flexible substrate are formed on a surface of the rigid substrate and are spaced from and corresponding to the at least one bottom-emission OLED light-emitting layer and the at least one top-emission OLED light-emitting layer, such that the at least one top-emission OLED light-emitting layer is separated by the display substrate from the at least one reflective flexible substrate.

US Pat. No. 10,192,935

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device having a substrate, comprising:a light shielding layer on the substrate;
first, second, third and fourth subpixels sequentially arranged on the substrate in a horizontal direction;
a first power line disposed on one side of the first subpixel and connected to the first and second subpixels;
a sensing line disposed between the second subpixel and the third subpixel and connected to the first to fourth subpixels;
a second power line disposed on one side of the fourth subpixel and connected to the third and fourth subpixels;
first and second data lines disposed between the first subpixel and the second subpixel and third and fourth data lines disposed between the third subpixel and the fourth subpixel; and
a scan line on the first to fourth subpixels and extended to the horizontal direction,
wherein the first to fourth data lines, the sensing line, and the first and second power lines are disposed on the same plane as the light shielding layer.

US Pat. No. 10,192,931

COMPLEMENTARY THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A complementary thin film transistor, comprising:a substrate defined by an n-type transistor region and a p-type transistor region adjacent to the n-type transistor region;
an n-type semiconductor layer disposed on the substrate and within the n-type transistor region, wherein the n-type semiconductor layer comprises a metal oxide material, and the metal oxide material of the n-type semiconductor layer is selected from indium gallium zinc oxide, indium zinc oxide or zinc tin oxide;
a p-type semiconductor layer disposed on the substrate and within the p-type transistor region, wherein the p-type semiconductor layer comprises organic semiconductor material; and
an etched barrier layer formed on the n-type semiconductor layer and disposed within the n-type transistor region and the p-type transistor region, wherein the p-type semiconductor layer is formed on the etched barrier layer and the organic semiconductor material of the p-type semiconductor layer is selected from pentacene, triphenylamine, fullerene, phthalocyanine, perylene derivative, or cyanine; and
a buffer layer formed on the whole etched barrier layer and disposed within the n-type transistor region and the p-type transistor region.

US Pat. No. 10,192,927

SEMICONDUCTOR DEVICE FOR A NON-VOLATILE (NV) RESISTIVE MEMORY AND ARRAY STRUCTURE FOR AN ARRAY OF NV RESISTIVE MEMORY

CROSSBAR, INC., Santa Cl...

1. A resistive switching device comprising:a substrate having a surface region;
a first dielectric material layer overlying the surface region of the substrate;
a first wiring structure comprising a first metal material overlying the first dielectric material layer;
a plurality of first structures overlying a surface region of the first wiring structure, wherein the plurality of first structures comprise a contact material, wherein the plurality of first structures are separated by a second dielectric material, and wherein the plurality of first structures are characterized by a first width;
a plurality of resistive switching material structures overlying the plurality of first structures, wherein each resistive switching material structure from the plurality of resistive switching material structures is characterized by a second width, wherein the plurality of resistive switching material structures comprise undoped silicon material;
a plurality of active conductive material structures overlying the plurality of resistive switching material structures, wherein each active conductive material structure from the plurality of active conductive material structures is characterized by a third width, wherein the plurality of active conductive material structures comprise an active metal material; and
a second wiring structure overlying the plurality of active conductive material structures;
wherein the plurality of first structures, the plurality of resistive switching material structures and the plurality of active conductive material structures form a plurality of non-volatile memory cells;
wherein a resistive switching material structure of a non-volatile memory cell from the plurality of non-volatile memory cells includes a conductive path disposed therein comprising a portion of the active metal material from an active conductive material structure from the plurality of active conductive material structures; and
wherein a resistance of the non-volatile memory cell is determined in response to a conductance state of the conductive path.

US Pat. No. 10,192,924

IMAGE PICKUP DEVICE AND IMAGE PICKUP APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:a substrate;
a first photoelectric conversion region disposed in the substrate;
a second photoelectric conversion region disposed in the substrate, the second photoelectric conversion region being adjacent to the first photoelectric conversion region;
a third photoelectric conversion region disposed in the substrate, the third photoelectric conversion being adjacent to the second photoelectric conversion region;
a first trench disposed between the first photoelectric conversion region and the second photoelectric conversion region; and
a second trench disposed between the second photoelectric conversion region and the third photoelectric conversion region,
wherein an area of the first photoelectric conversion region is larger than an area of the second photoelectric conversion region in a cross-sectional view,
wherein, in the cross-sectional view, the first trench extends a first distance along a first sidewall of the first photoelectric conversion region, wherein the first distance is taken along the first side wall from a first light receiving surface of the first photoelectric conversion region to an end of the first trench,
wherein, in the cross-sectional view, the second trench extends a second distance along a second sidewall of the second photoelectric conversion region, wherein the second distance is taken along the second sidewall from a second light receiving surface of the second photoelectric conversion region to an end of the second trench, and
wherein the first distance is greater than the second distance.

US Pat. No. 10,192,922

CHARGE PACKET SIGNAL PROCESSING USING PINNED PHOTODIODE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:an image pixel comprising a first pinned photodiode coupled to a pixel output line; and
analog-to-digital conversion (ADC) circuitry coupled to the pixel output line, wherein the ADC circuitry comprises:
a second pinned photodiode;
a comparator with first and second inputs;
a sampling transistor;
a first capacitive node that is coupled between the second pinned photodiode the first input of the comparator; and
a second capacitive node that is coupled between the sampling transistor and the second input of the comparator.

US Pat. No. 10,192,921

SOLID STATE IMAGING DEVICE FOR REDUCING DARK CURRENT, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. A solid state imaging device, comprising:a semiconductor substrate comprising a light sensing section and comprising a first surface and a second surface opposite to the first surface, wherein the first surface is at a light incident side of the semiconductor substrate;
a wiring layer on the second surface; and
at least three layers over the first surface, the at least three layers comprising a first layer, a second layer, and a third layer,
wherein the first layer and the third layer are insulating layers, and the second layer comprises a material selected from the group including hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), hafnium nitride, aluminum nitride, hafnium oxide nitride, and aluminum oxide nitride,
wherein the second layer is disposed between the first layer and third layer,
wherein the light sensing section includes at least a first light receiving surface and a second light receiving surface and a pixel separating region,
wherein the pixel separating region is disposed between the first light receiving surface and the second light receiving surface, and
wherein at least one of the first layer, the second layer, and the third layer is disposed over the first light receiving surface, the second light receiving surface, and the pixel separating region.

US Pat. No. 10,192,912

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. A back-illuminated type solid-state imaging device comprising:a first layer including at least one of an amplification transistor, a reset transistor, or a selection transistor;
a second layer including at least one photo diode, the second layer separated from the first layer in a depth direction;
a transfer transistor configured to control charge transfer of the photo diode, wherein the transfer transistor is at least partially disposed in the second layer; and
a floating diffusion configured to receive charge transferred from the photo diode, wherein the floating diffusion penetrates the first layer such that the photo diode is in electrical communication with the at least one of an amplification transistor, a reset transistor, or a selection transistor via the floating diffusion,
wherein the floating diffusion is formed at a position including the second layer.

US Pat. No. 10,192,911

HYBRID IMAGE SENSORS WITH IMPROVED CHARGE INJECTION EFFICIENCY

APPLE INC., Cupertino, C...

1. Imaging apparatus, comprising:a photosensitive medium configured to convert incident photons into charge carriers;
a bias electrode, which is at least partially transparent, overlying the photosensitive medium and configured to apply a bias potential to the photosensitive medium;
an array of pixel circuits formed on a semiconductor substrate, each pixel circuit defining a respective pixel and comprising:
a pixel electrode coupled to collect the charge carriers from the photosensitive medium;
a readout circuit configured to output a signal indicative of a quantity of the charge carriers collected by the pixel electrode;
a skimming gate coupled between the pixel electrode and the readout circuit; and
a shutter gate coupled in parallel with the skimming gate between a node in the pixel circuit and a sink site; and
control circuitry coupled to sequentially open and close the shutter gate and the skimming gate of each of the pixels in each of a sequence of image frames so as to apply a global shutter to the array and then to read out the collected charge carriers via the skimming gate to the readout circuit,
wherein the pixel circuit comprises:
a charge storage node between the skimming gate and the readout circuit;
at least one charge transfer gate that connects to the charge storage node; and
a reset gate coupled between the charge transfer gate and a reset potential and configured to reset the charge stored on the charge storage node under control of the control circuitry,
wherein the control circuitry is configured, in each of the image frames, to actuate one of the gates so as to fill a potential well at the pixel electrode with charge carriers, and then to close the shutter gate, whereby the charge carriers acquired at the pixel electrode from the photosensitive medium is transferred through the skimming gate to the readout circuit,
wherein while the one of the gates is actuated, a potential well of the charge storage node is filled with the charge carriers, and wherein the control circuitry is configured, prior to acquiring the charge carriers, to actuate the reset gate and the at least one charge transfer gate so as to allow the charge carriers to drain from the charge storage node while the charge carriers remain in the potential well at the pixel electrode, and
wherein the control circuitry is configured to apply a charge pump signal so as to inject an additional number of the charge carriers into the potential well of the pixel electrode after the acquisition of the photocharge but before reading out the charge carriers to the readout circuit.

US Pat. No. 10,192,908

TFT ARRAY MANUFACTURING METHOD OF OPTIMIZED 4M PRODUCTION PROCESS

SHENZHEN CHINA STAR OPTOE...

1. A thin-film transistor (TFT) array manufacturing method of an optimized 4M production process, comprising:Step 10: in a first mask-based process, making a gate layer on a glass substrate and patterning the gate layer; and then, making a gate insulation layer, an active layer, a source/drain layer, and a photoresist layer;
Step 20: in a second mask-based process, subjecting the photoresist layer to exposure and development; conducting a first wet etching operation to pattern the source/drain layer to form metal line structures of source and drain areas and an active area; conducting a first oxygen ashing operation to reduce a size of trailing of the active layer on edges of the source/drain metal layer; conducting a first dry etching operation to form an active layer island structure; conducting a second oxygen ashing operation to reduce a thickness of the photoresist layer in order to expose portions of the source/drain layer in a channel area; conducting a second wet etching operation to pattern a source and a drain; conducting a third oxygen ashing operation to reduce trailing of the contact layer; and conducting a second dry etching operation to etch the active layer so as to form a thin-film transistor structure;
Step 30: in a third mask-based process, making a passivation layer and patterning the passivation layer; and
Step 40: in a fourth mask-based process, making a transparent electrode layer and patterning the transparent electrode layer.

US Pat. No. 10,192,900

METHODS FOR FABRICATING THIN FILM TRANSISTOR AND ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A fabrication method of a thin film transistor, comprising an operation of forming an active layer, a source electrode and a drain electrode of a thin film transistor, wherein the source electrode and the drain electrode are separately provided on two sides of the active layer, an interval is provided between the source electrode and the drain electrode to define a channel area, the operation of forming the active layer, the source electrode and the drain electrode of the thin film transistor comprises:forming an active layer film;
forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern covers an area of the active layer film for forming the active layer, the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area of a second thickness, a thickness of the photoresist area of the first thickness is greater than a thickness of the photoresist area in the second thickness, and the photoresist area of the first thickness corresponds to the area of the active layer film for forming the channel area;
etching the active layer film by using the first photoresist pattern as a mask to form the active layer;
ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce the thickness of the photoresist area of the first thickness to form a second photoresist pattern, which corresponds to the area of the active layer for forming the channel area;
forming a source-drain electrode film on the active layer and the second photoresist pattern;
forming a third photoresist pattern on the source-drain electrode film;
etching the source-drain electrode film by using the third photoresist pattern as a mask to form the source electrode and the drain electrode and to expose the second photoresist pattern; and
stripping off the second photoresist pattern and the third photoresist pattern;
wherein a distance between photoresist that covers a position where the source electrode is to be formed in the source-drain electrode film and photoresist that covers a position where the drain electrode is to be formed in the source-drain electrode film in the third photoresist pattern is equal to a width of the second photoresist pattern between these positions correspondingly.

US Pat. No. 10,192,890

TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THEREOF

Samsung Display Co., Ltd,...

1. A transistor display panel comprising:a substrate; and
a transistor disposed on the substrate,
wherein the transistor comprises:
a gate electrode disposed on the substrate;
a semiconductor that overlaps the gate electrode;
an upper electrode disposed on the semiconductor and overlapping the gate electrode;
a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor;
a source electrode connected with the source connection member and the upper electrode; and
a drain electrode connected with the drain connection member.

US Pat. No. 10,192,889

DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first substrate including a display area and a non-display area;
a gate line and a gate electrode in the display area;
a data line connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a drain electrode and a source electrode on the semiconductor layer;
a first passivation layer on the drain electrode and the source electrode;
a color filter on the first passivation layer;
a common electrode on the first passivation layer;
a second passivation layer on the common electrode; and
a pixel electrode on the second passivation layer,
wherein the gate insulating layer has substantially a same shape as a shape of the gate electrode,
wherein the gate insulating layer has a width wider than a width of the gate electrode,
wherein the gate insulating layer is spaced apart from the first substrate, and
wherein a side surface of the gate electrode is exposed below a bottom surface of the gate insulating layer.

US Pat. No. 10,192,881

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate comprising a source region portion;
gate stacks disposed on the substrate and spaced apart from each other in a first direction, with a separation region directly contacting the source region portion of the substrate and interposed between the gate stacks, the source region portion of the substrate being disposed between the separation region and regions of the substrate not within the source region portion;
channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and
a guide region adjacent to the separation region, penetrating through at least a portion of one of the gate stacks, and having a bent portion that is bent toward the separation region;
wherein the channel regions are disposed in channel openings that penetrate through the gate stacks,
the guide region is disposed in a guide opening that penetrates through at least the portion of the one of the gate stacks,
the separation region is disposed in a separation opening that penetrates through the gate stacks, and
a width of the separation opening is greater than a width of each of the guide opening and the channel openings,
wherein the guide opening is closer to the separation region than the channel openings, and an upper portion of the guide opening is spaced apart from an upper portion of the separation region.

US Pat. No. 10,192,868

SEMICONDUCTOR DEVICE AND OPERATION THEREOF

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate;
an active area on the substrate, wherein the active area comprises:
a first active area; and
a second active area positioned along an extension direction of the first active area, wherein the first active area comprises a first component, a second component, and a connection component, and the first component and the second component each directly contact a side of the connection component, wherein the second active area comprises a third component and a fourth component being separated by a groove isolation, and wherein the groove isolation in the second active area corresponds to the connection component in the first active area; and
a first pseudo gate covering the connection component and the groove isolation.

US Pat. No. 10,192,866

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJITSU SEMICONDUCTOR LIM...

1. A semiconductor device, comprising:a semiconductor substrate including a first region and a second region;
a semiconductor layer formed on the upper surface of the semiconductor substrate;
a first impurity region formed in the first region of the semiconductor substrate and including a first impurity;
a second impurity region formed in the second region of the semiconductor layer and including a second impurity;
a first gate insulating film formed on the semiconductor layer in the first region;
a second gate insulating film formed on the semiconductor layer in the second region;
a first gate electrode formed on the first gate insulating film;
a second gate electrode formed on the second gate insulating film;
a first source region and a first drain region formed in the semiconductor layer at both sides of the first gate electrode, and having a conductivity type opposite to a conductivity type of the first impurity region; and
a second source region and a second drain region formed in the semiconductor layer at both sides of the second gate electrode, and having a conductivity type opposite to a conductivity type of the second impurity region, and wherein
a maximum concentration peak of the second impurity in the second region is positioned in the semiconductor layer, a maximum concentration peak of the first impurity in the first region is positioned in the first impurity region.

US Pat. No. 10,192,855

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING HEAT DISSIPATION PATTERN AND/OR HEAT CONDUCTING LINE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a lower semiconductor package including a lower package substrate and at least a first lower semiconductor chip mounted thereon;
an upper semiconductor package provided on the lower semiconductor package and including an upper package substrate and at least a first upper semiconductor chip mounted thereon; and
a solder bump provided between the upper package substrate and the lower package substrate adjacent to a sidewall of the first lower semiconductor chip to connect the lower semiconductor package and the upper semiconductor package,
wherein the upper package substrate comprises an upper heat-dissipation pattern not electrically connected to any circuitry for transmitting signals to, from, or through the first lower semiconductor chip or the upper package substrate, and
wherein the first lower semiconductor chip comprises at least a first lower heat-conducting via connected to the upper heat-dissipation pattern through the first lower semiconductor chip, the first lower heat-conducting via providing a pathway for dissipating heat generated in the first lower semiconductor chip.

US Pat. No. 10,192,854

LIGHT EMITTER COMPONENTS AND RELATED METHODS

Cree, Inc., Durham, NC (...

1. A light emitter component comprising:a submount comprising ceramic;
a reflective material disposed on portions of the submount, wherein the reflective material comprises a reflective surface; and
a plurality of light emitter chips disposed on the reflective surface of the reflective material and in contact with one or more electrical traces on the submount, wherein the reflective surface extends below each of the plurality of light emitter chips and between each of the one or more electrical traces, wherein each light emitter chip comprises a sapphire substrate, an epi area disposed over the sapphire substrate, and first and second electrical contacts that face the reflective surface;
wherein a ratio of a combined epi area of the plurality of light emitter chips to a surface area of the reflective surface not covered by the plurality of light emitter chips is at least 0.4 or more, and
wherein a ratio of a combined planar surface area of the plurality of light emitter chips to a planar surface area of the reflective surface not covered by the plurality of light emitter chips is at least approximately 0.25 or more.

US Pat. No. 10,192,851

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising:(a) providing a wiring substrate including:
an upper surface,
a lower surface opposite to the upper surface,
a first device region provided on the lower surface,
a second device region provided on the lower surface and also provided next to the first device region,
a dicing region provided between the first device region and the second device region
a peripheral region provided on the lower surface and also provided around the first device region, the second device region and the dicing region,
a target mark provided in the peripheral region and also not located on an extended line of the dicing region,
a plurality of first bump lands provided in a matrix, in the first device region,
a plurality of second bump lands provided in a matrix, in the second device region, and
a first insulating film formed over the lower surface such that the first insulating film exposes the plurality of first bump lands and the plurality of second bump lands,
wherein the plurality of first bump lands has a first outermost peripheral land row arranged on the outermost peripheral row of the plurality of first bump lands, which is closest to the dicing region,
wherein the plurality of second bump lands has a second outermost peripheral land row arranged on the outermost peripheral row of the plurality of second bump lands, which is closest to the dicing region,
wherein the target mark is comprised of a first pattern formed between the extended line of the dicing region and an extended line of the first outermost peripheral land row in plan view, and a second pattern formed between the extended line of the dicing region and an extended line of the second outermost peripheral land row in plan view, the first pattern and the second pattern being spaced apart from each other,
wherein a first feeder line and a second feeder line are connected to the first pattern and the second pattern, respectively,
wherein each of the first feeder line and the second feeder line has a first portion exposed from the first insulating film, and a second portion covered with the first insulating film,
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are comprised of a conductive member, and
wherein a first plating film is formed on a surface of each of the first pattern exposed from the first insulating film and the second pattern exposed from the first insulating film by using the first feeder line and the second feeder line, respectively;
(b) after (a), mounting a first semiconductor chip and a second semiconductor chip on the upper surface of the wiring substrate;
(c) after (b), sealing the first semiconductor chip and the second semiconductor chip with resin;
(d) after (c), forming a plurality of first external terminals and a plurality of second external terminals on the plurality of first bump lands and the plurality of second bump lands, respectively; and
(e) after (d), identifying the dicing region on the basis of the target mark, and cutting the wiring substrate along the dicing region,
wherein, in (e), the dicing region of the wiring substrate and a first region of the peripheral region of the wiring substrate are cut off by using a rotating cutting blade,
wherein the first region is located between the first pattern and the second pattern in plan view, and
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are not formed in the first region.

US Pat. No. 10,192,850

BONDING PROCESS WITH INHIBITED OXIDE FORMATION

SiTime Corporation, Sant...

1. A method of forming a wafer-to-wafer bond, the method comprising:forming, on a first wafer, a first contact from a first conductive material subject to surface oxidation when exposed to air;
disposing a layer of oxide-inhibiting material over a bonding surface of the first contact;
forming, on a second wafer, a second contact from a second conductive material that, upon heating while in physical contact with the first conductive material, will form a eutectic bond;
positioning the first and second wafers relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material; and
after positioning the first and second wafers relative to one another, heating the first and second contacts and the layer of oxide-inhibiting material to a first temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond;
the method further comprising, prior to positioning the first and second wafers relative to one another such that the bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material, heating the first contact and the layer of oxide-inhibiting material to a second temperature that alloys the oxide-inhibiting material with the first conductive material.

US Pat. No. 10,192,849

SEMICONDUCTOR MODULES WITH SEMICONDUCTOR DIES BONDED TO A METAL FOIL

Infineon Technologies AG,...

1. A method of manufacturing semiconductor modules, the method comprising:providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer;
attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil;
encasing the semiconductor dies attached to the metal foil in an electrically insulating material;
structuring the metal layer and the metal foil after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer; and
dividing the electrically insulating material along the surface regions devoid of the metal foil and the metal layer to form individual modules,
wherein structuring the metal layer and the metal foil comprises:
masking the metal layer so that regions of the metal layer are exposed;
removing the exposed regions of the metal layer so that regions of the metal foil are exposed; and
removing the exposed regions of the metal foil using the remaining metal layer as a mask.

US Pat. No. 10,192,848

PACKAGE ASSEMBLY

Taiwan Semiconductor Manu...

1. A package assembly, comprising:a bump on a first substrate;
a molding compound on the first substrate and contacting sidewalls of the bump;
a no-flow underfill layer on a conductive region of a second substrate, wherein the no-flow underfill layer and the conductive region contact the bump; and
a mask layer arranged on the second substrate and laterally surrounding the no-flow underfill layer, wherein the no-flow underfill layer contacts the second substrate between the conductive region and the mask layer, wherein the no-flow underfill layer physically contacts sidewalls and an upper surface of the mask layer facing the first substrate, and wherein the upper surface of the mask layer continuously extends from directly below the no-flow underfill layer to a non-zero distance laterally past an outermost edge of the no-flow underfill layer.

US Pat. No. 10,192,846

METHOD OF INSERTING AN ELECTRONIC COMPONENT INTO A SLOT IN A CIRCUIT BOARD

Infineon Technologies Aus...

1. A method, comprising:inserting an electronic component comprising a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board, wherein the inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot,
exerting pressure on the contact of the slot to electrically couple the one or more electrical contacts arranged on one or more surfaces of the slot to the one or more electrically conductive contacts of the electronic component, wherein the exerting the pressure comprises exerting pressure on a surface of the circuit board defining the slot by applying one or more fixation elements.

US Pat. No. 10,192,845

ELECTRONIC DEVICE AND MOUNTING STRUCTURE OF THE SAME

ROHM CO., LTD., Kyoto (J...

1. An electronic device comprising:a first electronic element; a second electronic element spaced apart from and electrically connected to the first electronic element; a main electrode on which the first electronic element and the second electronic element are disposed;
an insulating joining part directly interposed between the first electronic element and the main electrode;
a plurality of insulating spacers mixed in the joining part and each directly contacting the main electrode and the first electronic element; a joining layer interposed between the second electronic element and the main electrode, the joining layer being made of an electroconductive material comprising silver (Ag); and; and
a sealing resin covering the first electronic element, the second electronic element and the main electrode.

US Pat. No. 10,192,844

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip, a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant, the first interconnection member and the second interconnection member including, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip: and
a component package including a wiring substrate disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate,
wherein the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

US Pat. No. 10,192,840

BALL PAD WITH A PLURALITY OF LOBES

Intel Corporation, Santa...

1. An electronic assembly comprising:a substrate that includes a conductive trace embedded within the substrate, wherein the conductive trace is exposed to an upper exterior surface of the substrate; and
a ball pad mounted on the upper exterior surface of the substrate, wherein the ball pad engages the conductive trace and includes a plurality of lobes projecting distally from a center of the ball pad, wherein each lobe in the plurality of lobes includes two sides that form an edge with the two sides extending from the edge at an acute angle, wherein one of the two sides in each lobe forms a planar surface with a side of another lobe and the other of the two sides forms a separate planar surface with a side of a different lobe.

US Pat. No. 10,192,838

FABRICATION METHOD OF PACKAGING SUBSTRATE

Siliconware Precision Ind...

1. A fabrication method of a packaging substrate, comprising:providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the conductive pad;
forming at least a second opening in the dielectric layer around a periphery of the first opening, wherein the second opening is spaced apart from the first opening, and the second opening is free from being located directly above the conductive pad;
after forming the second opening in the dielectric layer around the periphery of the first opening, forming a metal layer on the dielectric layer and the conductive pad, allowing the metal layer to extend to only a part of a sidewall of the second opening without covering an entire surface of the second opening; and
forming at least a solder bump on the metal layer.

US Pat. No. 10,192,837

MULTI-VIA REDISTRIBUTION LAYER FOR INTEGRATED CIRCUITS HAVING SOLDER BALLS

NXP B.V., San Jose, CA (...

1. An article of manufacture comprising an integrated circuit (IC), the IC comprising:a top metal conducting layer;
a passivation layer on top of the top metal conducting layer, wherein the passivation layer comprises openings to the top conducting layer;
a redistribution layer on top of the passivation layer, wherein material of the redistribution layer fills the openings in the passivation layer to form via structures electrically connecting the redistribution layer to the top metal conducting layer; and
a solder ball placed on top of the redistribution layer that has a footprint that spans a first plurality of the via structures of the redistribution layer such that electricity can flow vertically between the solder ball and the top metal conducting layer through the redistribution layer and the first plurality of the via structures,
wherein there is no under-bump metallization (UBM) layer under the solder ball other than the redistribution layer, and
wherein the solder ball is in direct contact with the redistribution layer, and the footprint of the solder ball is vertically aligned with the first plurality of the via structures over the top metal conducting layer.

US Pat. No. 10,192,836

SEMICONDUCTOR DEVICE

PEZY COMPUTING K.K., Tok...

1. A semiconductor device comprising:a base board that has a base board terminal surface provided with a plurality of base board terminals;
a first element that has a first element board having a first element-first principal surface and a first element-second principal surface that is a surface opposite to the first element-first principal surface, a first element signal transmitting/receiving terminal provided on the first element-first principal surface of the first element board, and a first element contactless signal transmitting/receiving unit provided on the first element-first principal surface of the first element board;
a second element that has a second element board having a second element-first principal surface and a second element-second principal surface that is a surface opposite to the second element-first principal surface, a second element signal transmitting/receiving terminal provided on the second element-first principal surface of the second element board, and a second element contactless signal transmitting/receiving unit provided on the second element-first principal surface of the second element board; and
an interposer board with an interposer board-first principal surface that has an interposer board-first contactless signal transmitting/receiving unit provided on the interposer board-first principal surface and an interposer board-second contactless signal transmitting/receiving unit provided on the interposer board-first principal surface and electrically connected to the interposer board-first contactless signal transmitting/receiving unit,
wherein the first element is disposed on the base board such that the first element-first principal surface faces the base board terminal surface and the first element signal transmitting/receiving terminal and one of the plurality of base board terminals are in contact with each other and are capable of transmitting and receiving a signal,
the second element is disposed on the base board such that the second element-first principal surface faces the base board terminal surface, and the second element signal transmitting/receiving terminal and one of the plurality of base board terminals are in contact with each other and are capable of transmitting and receiving a signal,
the interposer board is disposed to extend on the first element and the second element such that the interposer board-first principal surface faces the first element-second principal surface and the second element-second principal surface, the interposer board-first contactless signal transmitting/receiving unit is capable of contactlessly transmitting and receiving a signal to and from the first element contactless signal transmitting/receiving unit via the first element board, and the interposer board-second contactless signal transmitting/receiving unit is capable of contactlessly transmitting and receiving a signal to and from the second element contactless signal transmitting/receiving unit via the second element board,
the first element-second principal surface has a first element-second principal surface terminal facing region that is a surface opposite to a region provided with the first element signal transmitting/receiving terminal in the first element-first principal surface and a first element-second principal surface contactless signal transmitting/receiving unit facing region that is a surface opposite to a region provided with the first element contactless signal transmitting/receiving unit in the first element-first principal surface,
the second element-second principal surface has a second element-second principal surface terminal facing region that is a surface opposite to a region provided with the second element signal transmitting/receiving terminal in the second element-first principal surface and a second element-second principal surface contactless signal transmitting/receiving unit facing region to be a surface opposite to a region provided with the second element contactless signal transmitting/receiving unit in the second element-first principal surface,
the interposer board-first principal surface of the interposer board faces the first element-second principal surface contactless signal transmitting/receiving unit facing region and the second element-second principal surface contactless signal transmitting/receiving unit facing region and faces at least one of a part of the first element-second principal surface terminal facing region and a part of the second element-second principal surface terminal facing region, and
the first element board, the second element board, and the interposer board are formed of a semiconductor material, the interposer board-first principal surface of the interposer board has an exposure portion in which the semiconductor material is exposed, and the exposure portion is in contact with at least one of the part of the first element-second principal surface terminal facing region and the part of the second element-second principal surface terminal facing region.

US Pat. No. 10,192,835

SUBSTRATE DESIGNED TO PROVIDE EMI SHIELDING

Apple Inc., Cupertino, C...

1. A package comprising:a package substrate including a top surface and a bottom surface;
a die bonded to the package substrate top surface;
a plurality of ground pads at a periphery of the package substrate top surface;
a plurality of electrically conductive wire bonds on the plurality of ground pads such that more than one electrically conductive wire bond is bonded to a corresponding ground pad;
a molding compound that encapsulates the die and the electrically conductive wire bonds on the package substrate top surface, the molding compound including top and side surfaces, wherein a corresponding plurality of surfaces of the plurality of electrically conductive wire bonds are exposed at a side surface of the molding compound; and
an electrically conductive shield layer on the top and side surfaces of the molding compound, and in physical contact with the plurality of surfaces of the exposed electrically conductive wire bonds.

US Pat. No. 10,192,834

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. A semiconductor package, comprising:a substrate;
a first semiconductor element disposed on the substrate and having a first conductive pad and a second conductive pad, wherein the second conductive pad is electrically connected to the first conductive pad by a first bonding wire and grounded to the substrate;
a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad, wherein the first semiconductor element is disposed between the conductive layer and the substrate, and the conductive layer is in direct contact with the first conductive pad and encapsulates the first conductive pad and a portion of the first bonding wire;
a second semiconductor element disposed on the conductive layer; and
an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.

US Pat. No. 10,192,833

INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES

Taiwan Semiconductor Manu...

1. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:a substrate body having opposed first and second surfaces;
a plurality of conductive layers disposed in a dielectric material on said substrate body, wherein a first one of said plurality of conductive layers includes a first lead and a second of said plurality of conductive layers includes a second lead, wherein said first lead is shielded from said second lead by a shield including portions of a first interposed conductive layer and a second interposed conductive layer of said plurality of conductive layers coupled by a via such that an entirety of a longitudinal width of each of the first interposed conductive layer and the second interposed conductive layer of the shield is contained within a boundary of a first coupling via and a second coupling via;
said first lead extending along a longitudinal direction of said interposer and said shield extending continuously along a transverse direction of said interposer, wherein said shield extends across at least a majority of a transverse width of said interposer between said first and second leads; and
wherein said plurality of conductive layers are formed of metal materials or semiconductor materials;wherein said shield forms a continuous member of said metal materials or semiconductor materials, and there is no dielectric path from said first lead to said second lead through said shield.

US Pat. No. 10,192,832

ALIGNMENT MARK STRUCTURE WITH DUMMY PATTERN

United Microelectronics C...

1. An alignment mark structure, comprising:a substrate;
an alignment mark disposed on the substrate;
dummy patterns disposed on the substrate and located adjacent to the alignment mark;
a first passivation layer covering a top surface of the dummy patterns; and
a second passivation layer covering the first passivation layer, wherein
a size of the dummy patterns is smaller than a size of the alignment mark,
a metal layer of the alignment mark and a metal layer of the dummy patterns are derived from the same metal layer, and
the second passivation layer directly contacts and covers entire top surface of the alignment mark, and the first passivation layer does not cover any of the top surface of the alignment mark.

US Pat. No. 10,192,830

SELF-SIMILAR AND FRACTAL DESIGN FOR STRETCHABLE ELECTRONICS

The Board of Trustees of ...

1. A electronic circuit comprising:an elastic substrate; and
a stretchable metallic or semiconducting device component supported by said elastic substrate; said stretchable metallic or semiconducting device component comprising a plurality of electrically conductive elements each having a primary unit cell shape, said electrically conductive elements connected in a sequence having a secondary shape providing an overall two-dimensional spatial geometry characterized by a plurality of spatial frequencies, wherein said two-dimensional spatial geometry is a self-similar two-dimensional geometry;
wherein said two-dimensional spatial geometry of said metallic or semiconducting device component allows for accommodation of elastic strain along one or more in-plane or out of plane dimensions, thereby providing stretchability of said electronic circuit, and
wherein said sequence of electrically conductive elements is further characterized by a tertiary shape comprising a repeating series of said electrically conductive elements comprising said secondary shape.

US Pat. No. 10,192,828

METAL GATE TRANSISTOR

SEMICONDUCTOR MANUFACTURI...

1. A metal gate transistor, comprising:a semiconductor substrate;
a metal gate structure and a first dielectric layer formed on the semiconductor substrate;
source/drain regions formed in the semiconductor substrate on sides of the metal gate structure;
an etch stop layer formed on a top surface of the metal gate structure with a top surface leveled with a top surface of the first dielectric layer;
an etch stop sidewall formed on each side of the metal gate structure with a top surface leveled with the top surface of the first dielectric layer; an offset spacer on each side of the metal gate structure between the etch stop sidewall and the metal gate structure, and a contact-via etch stop layer on the semiconductor substrate and the sidewall of the offset space; and
a contact plug formed in the first dielectric layer to electrically connect to each source/drain region formed in the semiconductor substrate.

US Pat. No. 10,192,827

TRANSMIT-AND-RECEIVE MODULE

MURATA MANUFACTURING CO.,...

1. A transmit-and-receive module comprising:a wiring substrate having first and second surfaces, the second surface being a back side of the first surface;
a low-noise amplifier including a first signal terminal and a first ground terminal, the first signal terminal being surface-mounted on the first surface;
a power amplifier including a second signal terminal and a second ground terminal, the second signal terminal and the second ground terminal being surface-mounted on the first surface;
an insulating resin covering the low-noise amplifier and the power amplifier; and
a conductive shield covering a surface of the insulating resin, wherein the first ground terminal is connected to the conductive shield, and wherein:
the wiring substrate includes a ground layer;
the first ground terminal is connected to the ground layer via the conductive shield;
the second ground terminal is connected to the ground layer by being surface-mounted on the first surface; and
the first ground terminal is a protruding metal terminal.

US Pat. No. 10,192,826

CONDUCTIVE LAYOUT STRUCTURE INCLUDING HIGH RESISTIVE LAYER

UNITED MICROELECTRONICS C...

1. A layout structure comprising a conductive structure comprising:a dielectric layer formed on a substrate; and
the conductive structure formed in the dielectric layer, the conductive structure further comprising:
a barrier layer;
a metal layer formed within the barrier layer;
a first nucleation layer sandwiched in between the barrier layer and the metal layer; and
a high resistive layer sandwiched in between the first nucleation layer and the metal layer.

US Pat. No. 10,192,825

SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A semiconductor device comprising:a first gate line, having a first long axis extending along a first direction;
a second gate line, parallel to the first gate line;
a first bar-shaped contact structure, having a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis, wherein the first bar-shaped contact structure at least partially covers on the first gate line and the second gate line;
a first semiconductor fin, having a third long axis perpendicular to the first direction and overlapping with the first gate line and the second gate line, and
a second semiconductor fin, parallel to and adjacent to the first semiconductor fin and overlapping with the first gate line and the second gate line,
wherein the first bar-shaped contact structure is completely disposed on a portion of an insulation structure disposed between the first semiconductor fin and the second semiconductor fin.

US Pat. No. 10,192,824

EDGE STRUCTURE FOR MULTIPLE LAYERS OF DEVICES, AND METHOD FOR FABRICATING THE SAME

MACRONIX International Co...

1. An edge structure for multiple layers of devices, wherein the multiple layers of devices comprises a plurality of unit layers being stacked, comprising:a first stair structure at a first direction of the multiple layers of devices where contacts for the devices are to be formed, including first edge portions of the unit layers at the first direction, wherein borders of the first edge portions gradually retreat with increase of a level height thereof, and an elevation angle from the border of the first edge portion of the bottom unit layer to the border of the first edge portion of the top unit layer is a first angle (?1); and
a second stair structure, including second edge portions of the unit layers at a second direction, wherein variation of border position of the second edge portion with increase of the level height is irregular, and an elevation angle from the border of the second edge portion of the bottom unit layer to the border of the second edge portion of the top unit layer is a second angle (?2) that is larger than the first angle ?1,
wherein a number of the unit layers is 16 or more,
the first direction is orthogonal with the second direction, and
the second stair structure has a first part and a second part above the first part, wherein
in the first part, variation of border position of the second edge portion with increase of the level height is regular,
in the second part, borders of the second edge portions of a corresponding part of the unit layers are aligned with each other, and
a height of the second part is over a half of a total height of the second stair structure.

US Pat. No. 10,192,823

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a transistor comprising a gate electrode and first and second dopant regions that are disposed on the first region of the substrate;
first, second, and third contact plugs electrically connected to the first dopant region, the second dopant region, and the gate electrode, respectively; and
a fuse structure disposed on the second region of the substrate, the fuse structure comprising: first and second fuse contact plugs having a same height as the first and second contact plugs; and a connection pattern having a same height as the third contact plug,
wherein the connection pattern is connected between the first and second fuse contact plugs,
wherein top surfaces of the first and second contact plugs are substantially coplanar with a top surface of the third contact plug, and
wherein the top surface of the third contact plug is substantially coplanar with a top surface of the connection pattern.

US Pat. No. 10,192,818

ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE

NSK LTD., Tokyo (JP)

1. An electronic part mounting heat-dissipating substrate which comprises: a conductor plate which is formed on lead frames of wiring pattern shapes to mount an electronic part; and an insulating member which is provided between said lead frames of said wiring pattern shapes on said conductor plate; in which a plate surface of a part arrangement surface of said conductor plate and a plate surface of a part arrangement surface-side of said insulating member are formed in an identical vertical plane, and a plate surface of a back surface of said part arrangement surface of said conductor plate and a plate surface of a back surface of said part arrangement surface-side of said insulating member are formed in an identical vertical plane,wherein said lead frames of said wiring pattern shapes have different thicknesses of at least two types or more, a thickness of the lead frames being measured in a direction parallel to the mounting direction of the electronic part, and a thick lead frame is used for a large current signal and a thin lead frame is used for a small current signal,
wherein said plate surface of said back surface of said part arrangement surface of said lead frames of said wiring pattern shapes and said plate surface of said back surface of said part arrangement surface-side of said insulating member are formed in an identical vertical plane to meet said plate surface of said back surface of said part arrangement surface of a thickest lead frame among said lead frames,
wherein said lead frames having different thicknesses are configured so that different wiring patterns are formed for said respective different thicknesses so as not to mutually cross and overlap and said lead frames having different thicknesses form an electronic circuit by mounting said electronic part,
wherein wiring widths of thin lead frames are smaller than wiring widths of thick lead frames, and said thin lead frames are arranged between said thick lead frames when said electronic part arrangement surface is seen from an upper side, and
wherein both side surfaces of said lead frames are formed with a plane vertical to said plate surface from a top surface of said electronic part arrangement surface to a back surface thereof.

US Pat. No. 10,192,817

ELECTROSTATIC DISCHARGE PROTECTION ELEMENT

REALTEK SEMICONDUCTOR COR...

1. An electrostatic discharge (ESD) protection element of a semiconductor device, the ESD protection element leading out an electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge, comprising:an input/output (I/O) pad connected between the I/O terminal and the internal circuit;
a first conductor connected to the I/O pad;
a second conductor connected to a ground terminal; and
a gap structure disposed between the first conductor and the second conductor and configured to establish a path from the I/O pad to the first conductor, the second conductor and to the ground terminal for conducting the electrostatic discharge current;
wherein the first conductor, the second conductor and the gap structure are disposed in a same layer of the semiconductor device with a substantially same thickness.

US Pat. No. 10,192,816

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Amkor Technology, Inc., ...

1. A semiconductor device comprising:a first redistribution structure comprising:
a first dielectric layer;
a first conductive trace embedded in the first dielectric layer and comprising:
a first trace top side that is at least partially covered by the first dielectric layer;
a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and
a first trace lateral side that is covered by the first dielectric layer; and
a first conductive via embedded in the first dielectric layer and comprising:
a first via top side that is exposed at a top side of the first dielectric layer;
a first via bottom side that is directly coupled to the first trace top side; and
a first via lateral side that is covered by the first dielectric layer;
a second redistribution structure on a bottom side of the first redistribution structure and comprising:
a second dielectric layer coupled under the bottom side of the first dielectric layer;
a third dielectric layer coupled under a bottom side of the second dielectric layer;
a second conductive trace embedded in the third dielectric layer; and
a second conductive via that extends through the second dielectric layer, wherein:
the second conductive trace extends along the bottom side of the second dielectric layer;
the first conductive trace extends along a top side of the second dielectric layer; and
the second conducive via couples the first conductive trace to the second conductive trace;
a semiconductor die attached to a top side of the first redistribution structure; and
a mold material covering at least a portion of the top side of the first redistribution structure and a lateral side of the semiconductor die,
wherein the first, second, and third dielectric layers comprise a same dielectric material.

US Pat. No. 10,192,815

WIRING BOARD AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring board comprising:a first insulating layer;
a first wiring layer formed on a lower surface of the first insulating layer;
a first through hole which penetrates the first insulating layer in a thickness direction of the first insulating layer;
a first via wiring comprising:
a filling portion formed to fill the first through hole and connected to the first wiring layer; and
a protruding portion protruding upward from an upper surface of the first insulating layer;
a second wiring layer comprising a land, wherein the land comprises:
an outer circumferential portion covering the upper surface of the first insulating layer; and
a central portion formed integrally with the outer circumferential portion to cover a side surface and an upper surface of the protruding portion and protruding upward from an upper surface of the outer circumferential portion,
a second insulating layer formed on the upper surface of the first insulating layer to cover the second wiring layer;
a second through hole which penetrates the second insulating layer in the thickness direction to expose a side surface and an upper surface of the central portion;
a second via wiring formed to fill the second through hole to cover the side surface and the upper surface of the central portion; and
a third wiring layer formed on an upper surface of the second insulating layer and connected to the second via wiring,
wherein
the filling portion comprises:
a first metal film covering an inner side surface of the first through hole, the first metal film including an upper end surface that is planar with the upper surface of the first insulating layer;
a second metal film covering the first metal film; and
a metal layer covering the second metal film,
the protruding portion comprises:
the metal layer protruding upward from the upper surface of the first insulating layer; and
the second metal film covering a side surface and an upper surface of the metal layer exposed from the upper surface of the first insulating layer, and
the first via wiring has a step at a boundary between the protruding portion and the filling portion, the step formed along the upper end surface of the first metal film and a side surface and an upper surface of the second metal film, the side surface and the upper surface of the second metal film being exposed from the first metal film.

US Pat. No. 10,192,812

POLYMER LAYER ON METAL CORE FOR PLURALITY OF BUMPS CONNECTED TO CONDUCTIVE PADS

Samsung Display Co., Ltd....

1. A semiconductor chip, comprising:a substrate;
one or more conductive pads disposed on the substrate; and
one or more bumps electrically connected to the one or more conductive pads,
wherein the one or more bumps comprise a metal core, a polymer layer disposed over side and upper surfaces of the metal core, and a conductive coating layer disposed over side and upper surfaces of the polymer layer and electrically connected to the one or more conductive pads.

US Pat. No. 10,192,811

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:a metallic lead frame that includes a mounting surface and a dissipating surface opposite to the mounting surface, and including a P-potential electrode, intermediate potential electrodes, and an N-potential electrode that are electrically independent;
power semiconductor chips and a current detection resistor that are disposed on the mounting surface of the metallic lead frame via conductive joining members;
a wiring member that connects an electrode of one of the power semiconductor chips to a portion of the metallic lead frame; and
a resin that covers a portion of the mounting surface of the metallic lead frame, the power semiconductor chips, the current detection resistor and the wiring member,
wherein the P-potential electrode and the N-potential electrode are disposed on a centerline of the metallic lead frame, and
the metallic lead frame, the power semiconductor chips, the wiring member and the current detection resistor are disposed in symmetry with respect to the centerline.

US Pat. No. 10,192,810

UNDERFILL MATERIAL FLOW CONTROL FOR REDUCED DIE-TO-DIE SPACING IN SEMICONDUCTOR PACKAGES

Intel Corporation, Santa...

1. A semiconductor apparatus, comprising:first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies laterally adjacent to one another and separated by a spacing;
a barrier structure disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die; and
an underfill material layer in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die, wherein the underfill material layer is disposed on and over an uppermost surface of the barrier structure at a location of a highest point of the uppermost surface of the barrier structure above the common semiconductor package substrate but is not on a portion of the uppermost surface of the barrier structure underneath the first semiconductor die.

US Pat. No. 10,192,809

SEMICONDUCTOR ARRAY AND PRODUCTION METHOD FOR MICRO DEVICE

TOYODA GOSEI CO., LTD., ...

1. A method for producing a micro device, the method comprising:forming a decomposition layer;
forming a bridging portion on the decomposition layer;
decomposing the decomposition layer;
forming a plurality of semiconductor laminates on the bridging portion;
and separating the substrate from the semiconductor laminates, wherein,
in the decomposition layer formation, a plurality of threading dislocations are extended during growth of the decomposition layer;
in the bridging portion formation, the bridging portion having a leg portion and a top portion is formed, and the threading dislocations are exposed to the surface of the bridging portion;
in the decomposition of the decomposition layer, the threading dislocations exposed to the surface of the bridging portion are widened to thereby provide a plurality of through holes penetrating the bridging portion, and the decomposition layer is decomposed through the through holes; and
in the semiconductor laminate formation, each of the semiconductor laminates is grown from the top portion of the bridging portion.

US Pat. No. 10,192,804

BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a first package component;
a first metal trace and a second metal trace on a top surface of the first package component, the first metal trace having a first thickness with respect to the top surface of the first package component and the second metal trace having a second thickness with respect to the top surface of the first package component, the first thickness and the second thickness being substantially equal;
a dielectric mask layer covering a top surface of the first package component and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace in a cross sectional view, the dielectric mask layer not exposing the second metal trace in the cross sectional view, wherein a first side surface of the second metal trace forms a first interface with the dielectric mask layer in the cross sectional view, wherein a second side surface of the second metal trace opposite the first side surface forms a second interface with the dielectric mask layer in the cross sectional view, the first interface and the second interface each extending continuously from a topmost surface of the second metal trace to a bottommost surface of the second metal trace, and the dielectric mask layer has constantly sloped sidewall surfaces defining the opening, the dielectric mask layer being a photodefinable layer;
a second package component; and
an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, the solder bump being in contact with a top surface and a side surface of the first metal trace in the opening of the dielectric mask layer, the constantly sloped sidewall surfaces of the dielectric mask layer being in contact with the side surface of the first metal trace at a first point, the solder bump being in contact with the side surface of the first metal trace at a second point, the first point being higher than the second point, an entirety of the side surface of the first metal trace being perpendicular to the top surface of the first metal trace, the side surface of the first metal trace extending continuously from a topmost surface of the first metal trace to a bottommost surface of the first metal trace, a continuous portion of the side surface of the first metal trace extending continuously from the first point to the second point being not in contact with the dielectric mask layer and not in contact with the solder bump, the second point being above a bottommost surface of the first metal trace.

US Pat. No. 10,192,800

SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A semiconductor device, comprising:two electrodes with opposite faces;
a semiconductor wafer sandwiched between the two electrodes;
an outer insulating ring attached to the two electrodes and surrounding the semiconductor wafer;
a middle insulating ring inside the outer insulating ring and surrounding the semiconductor wafer, whereby the middle insulating ring is made of a plastics material;
an inner insulating ring inside the middle insulating ring, whereby the inner insulating ring is made of ceramics and/or glass material;
wherein either the middle insulating ring or the inner insulating ring has a tongue and the other thereof has a groove such that the tongue fits into the groove for their rotational alignment and
wherein the middle insulating ring and the inner insulating ring have a radial opening for receiving a gate connection of the semiconductor device.

US Pat. No. 10,192,798

INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD

EM Microelectronic-Marin ...

1. An electronic system, comprising:an integrated circuit die having:
at least two bond pads, and
a redistribution layer having:
at least one solder pad comprising a first and second portion being separated from each other to provide a separation space between the first and second portion and being configured to provide an electrical connection between each of the first and second portion by a solder ball disposed on the at least one solder pad, and to electrically isolate the first and second portion in an absence of the solder ball on the at least one solder pad, and
at least two redistribution wires, each connecting a different one of the first and second portion to a different one of the at least two bond pads, a second bond pad of the at least two bond pads being connected via a second redistribution wire of the at least two redistribution wires to a second portion of the first and second portion of the at least one solder pad being dedicated to testing the integrated circuit die; and
a grounded printed circuit board track,
wherein the solder ball is disposed between the at least one solder pad and the grounded printed circuit board track, and
wherein no redistribution wires traverse the separation space between the first and second portion.

US Pat. No. 10,192,797

SEMICONDUCTOR DEVICE AND ELECTRICAL CONTACT STRUCTURE THEREOF

Mitsubishi Electric Corpo...

1. A semiconductor device having a semiconductor element region, in which a semiconductor element is formed, and a terminal region provided in an outer peripheral part of said semiconductor element, the semiconductor device comprising:a plurality of electrodes formed on a surface of said semiconductor element;
a protective layer having opening parts respectively provided vertically over the semiconductor element at each electrode such that a portion of each said electrode is exposed at the opening parts, and vertically over and covering the other portions of said electrodes excluding said portion of said electrodes exposed at said opening part, said protective layer being insulative; and
a conductive layer formed so as to cover said protective layer and said opening parts and directly connected to said electrodes at said opening parts, wherein
said electrodes have substantially the same electric potential, and
said conductive layer is formed across said electrodes, wherein said protective layer has a plurality of said opening parts for each said electrode.

US Pat. No. 10,192,796

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDED INTERCONNECT STRUCTURES IN FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a substrate;
a vertical interconnect structure formed in contact with a first surface of the substrate, wherein the substrate includes an opening extending from a second surface of the substrate opposite the first surface of the substrate to the vertical interconnect structure;
a semiconductor die disposed over the first surface of the substrate;
an encapsulant deposited over the first surface of the substrate, a side surface of the substrate, and around the semiconductor die, including a surface of the encapsulant outside the substrate coplanar with the second surface of the substrate; and
a first interconnect structure formed over the encapsulant opposite the substrate and coupled to the semiconductor die.

US Pat. No. 10,192,795

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a power transistor that passes a current from a high-potential terminal to a low-potential terminal, the power transistor comprising a gate electrode insulated from a channel region of the power transistor by an insulating film; and
a temperature sensing diode that senses a variation in temperature due to heating of the power transistor,
wherein the low-potential terminal of the power transistor and a cathode of the temperature sensing diode are directly electrically connected to each other so as to have a same potential.

US Pat. No. 10,192,794

WAFER TRANSFER DEVICE

SK SILTRON CO., LTD., Gu...

1. A wafer transfer device comprising:a guide configured to move in a vertical direction or in a horizontal direction;
a moving arm provided on the guide and supporting edge portions of wafers, which are spaced apart from each other such that front surfaces or rear surfaces of the wafers are parallel to the vertical direction;
a laser emission unit disposed on the guide and configured to emit a first laser to the wafers, which are seated on the moving arm and are spaced apart from each other; and
a laser detection unit disposed under the moving arm and configured to collect a second laser that is a portion of the first laser and has passed through a gap between the wafers, which are spaced apart from each other,
wherein the first laser has an emission area in the horizontal direction,
wherein a first end of the emission area is aligned with one end of a first wafer among the wafers, and a second end of the emission area is aligned with one end of a last wafer among the wafers,
wherein the one end of the first wafer is a surface of the first wafer opposite to another surface of the first wafer facing a second wafer among the wafers, and
wherein the one end of the last wafer is a surface of the last wafer opposite to another surface of the last wafer facing a wafer immediately before the last wafer.

US Pat. No. 10,192,793

PATTERN FORMATION METHOD, IMPRINT DEVICE, AND COMPUTER-READABLE NON-VOLATILE STORAGE MEDIUM STORING DROP RECIPE ADJUSTMENT PROGRAM

Toshiba Memory Corporatio...

1. A pattern formation method comprising:forming a first imprint pattern for a prepared sample;
measuring residual film thickness distribution of the first imprint pattern;
calculating change rate of the residual film thickness of the first imprint pattern with respect to drop density of a resist material at the time of formation of the first imprint pattern;
forming a first etching pattern using the first imprint pattern as a mask;
measuring dimension distribution of the first etching pattern;
calculating a correction coefficient based on the residual film thickness distribution of the first imprint pattern and the dimension distribution of the first etching pattern;
correcting the residual film thickness of the first imprint pattern based on the correction coefficient to reduce a variation in size of the first etching pattern;
calculating a first drop density of an imprint material based on the change rate of the residual film thickness of the first imprint pattern with respect to drop density to obtain the corrected residual film thickness;
dropping the imprint material onto an etching material based on the first drop density;
pressing a template against the dropped imprint material to form the second imprint pattern with the corrected residual film thickness on the etching material;
etching the etching material using the second imprint pattern as a mask to form a second etching pattern;
determining whether dimension distribution of the second etching pattern falls within a specification;
calculating, when the dimension distribution of the second etching pattern does not fall within the specification, an additional residual film thickness to compensate for insufficient adjustment of the dimension of the second etching pattern; and
calculating a second drop density of the imprint material to obtain the additional residual film thickness.

US Pat. No. 10,192,785

DEVICES AND METHODS RELATED TO FABRICATION OF SHIELDED MODULES

Skyworks Solutions, Inc.,...

1. A method for preparing a carrier assembly for processing of packaged modules, the method comprising:providing a plate having a first side and a second side, and defining a plurality of openings, such that each opening extends through the plate between the first side and the second side; and
implementing an adhesive layer on the first side of the plate, such that the adhesive layer defines a plurality of openings arranged to substantially match the openings of the plate, each opening of the adhesive layer dimensioned such that the adhesive layer is capable of providing an adhesive engagement between a perimeter portion of an underside of a package and a perimeter portion about the corresponding opening of the adhesive layer, and such that the underside of the package not in engagement with the adhesive layer is exposed through the respective opening on the second side of the plate.

US Pat. No. 10,192,783

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a gate electrode above a substrate, the gate electrode having a bottom surface, a first portion of the gate electrode bottom surface over a single crystalline region of the substrate and a second portion of the gate electrode bottom surface over a trench isolation layer of the substrate;
a source region or drain region in the single crystalline region of the substrate at a side of the gate electrode;
a dielectric sidewall spacer laterally adjacent the side of the gate electrode;
a gate etch stop layer over the gate electrode;
a trench contact structure on the source region or drain region, laterally adjacent the dielectric sidewall spacer; and
a single conductive via structure over and in contact with the trench contact structure, over the dielectric sidewall spacer, and over and in direct contact with the gate electrode, the conductive via structure in an opening in the gate etch stop layer, the opening exposing a portion of but not all of the gate electrode.

US Pat. No. 10,192,782

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING A PLURALITY OF ETCH STOP LAYERS

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device, the method comprising:providing a first interlayer dielectric layer having a conductive pattern;
sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer;
forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing a top surface of the second etch stop layer; and
performing an etching process in a single etch, the single etch including removing the mask pattern and the second etch stop layer exposed by the opening to expose a top surface of the first etch stop layer.

US Pat. No. 10,192,781

INTERCONNECT STRUCTURES INCORPORATING AIR GAP SPACERS

International Business Ma...

1. A process for manufacturing a dual damascene article of manufacture comprising a trench and a conductive metal column, said trench and said conductive metal column extending down into and contiguous with a via, said trench and said conductive metal column and said via having a common axis, wherein said trench and said via further comprise a sidewall air gap adjacent the side walls of said trench, said via, and said conductive metal column, said sidewall air-gap extending down to said via to a depth below a line fixed by the bottom of said trench, and continues downward in said via for a distance of from about 1 Angstrom below said line to the full depth of said via, said air gap being on opposite sides of said trench and said via, said process comprising forming said trench and said via of said dual damascene article of manufacture, coating the side wall of said trench and the side wall of said via with a dielectric material said dielectric material being on opposite sides of said trench and said via, damaging said dielectric material to form a damaged dielectric material on said side wall of said trench and said side wall of said via, metallizing said trench and said via having said damaged dielectric material to form a conductive metal column in said trench and a conductive metal column in said via and separately forming a metallization liner material in said trench and said via whereby said metallization liner is on opposite sides of said conductive metal column and contiguous with and interposed between said conductive metal column and said dielectric material, and removing said damaged dielectric material to form a sidewall air-gap adjacent said side wall, wherein said air gap is contiguous with said metallization liner and said metallization liner is contiguous with said conductive metal column, and further comprising providing a perforated pinched off cap operatively associated with said article, said perforated pinched off cap comprising a first cap layer patterned with a patterning layer that defines a narrower gap or narrower gaps extending from the top surface of said first cap layer to the bottom surface of said first cap layer, with said narrower gap or narrower gaps extending through said bottom surface of said first cap layer and being positioned over and projecting into said sidewall air-gap, and sealing only said narrower gap or narrower gaps, and further providing a second non-perforated cap layer operatively associated with and extending over said top surface of said first cap layer.

US Pat. No. 10,192,778

SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A SACRIFICIAL LAYER AND METHOD OF MANUFACTURE THEREOF

GlobalWafers Co., Ltd., ...

1. A method of preparing a multilayer structure, the method comprising:bonding a handle semiconductor oxide layer in interfacial contact with a front surface of a single crystal semiconductor handle substrate to a donor semiconductor nitride layer in interfacial contact with a donor semiconductor oxide layer in interfacial contact with a front surface of a single crystal semiconductor donor substrate to thereby prepare a bonded structure, wherein (i) the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is the back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, a central plane between the front and back surfaces of the semiconductor donor substrate, and a bulk region between the front and back surfaces of the semiconductor donor substrate, wherein the single crystal semiconductor donor substrate comprises a cleave plane, (ii) the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, and (iii) further wherein the handle semiconductor oxide layer comprises porous silicon dioxide and the handle semiconductor oxide layer has a wet etch rate ratio greater than 2.

US Pat. No. 10,192,777

METHOD OF FABRICATING STI TRENCH

UNITED MICROELECTRONICS C...

1. A method of fabricating a shallow trench isolation (hereafter abbreviated as STI) trench, comprising:providing a substrate;
forming a first mask covering the substrate, and the first mask comprising a plurality of sub-masks, wherein a first trench is disposed between the sub-masks adjacent to each other;
forming a protective layer filling up the first trench;
forming a second mask covering the first mask, and the second mask comprising an opening, wherein one of the sub-masks directly under the opening is defined as a joint STI pattern;
removing the joint STI pattern to transform the first mask into a third mask by taking the second mask as a first protective mask;
removing the second mask;
removing the protective layer; and
removing part of the substrate to form a plurality of STI trenches by taking the third mask as a second protective mask.

US Pat. No. 10,192,776

MANUFACTURING METHOD OF A FLASH WAFER

SHANGHAI HUALI MICROELECT...

1. A manufacturing method of a Flash wafer, comprising the following steps of:S01: fabricating the Flash wafer containing a cell area, a logical area and a capacitance area, and performing a planarization to an upper surface of the Flash wafer, wherein each of the cell area, the logical area and the capacitance area includes a STI and an active area, the STI is located in a gap of the active area, there is a floating gate above the active area, a silicon oxide filled shallow trench is contained in the STI, and the upper surfaces of the planarized silicon oxide filled shallow trench and floating gate are located on the same plane;
S02: adjusting the height of the silicon oxide filled shallow trench in the logical area and the capacitance area by protecting the cell area with a first mask, so that the height of the silicon oxide filled shallow trench in the logical area and the capacitance area is lower than the height of the floating gate after adjusting;
S03: sequentially depositing a silicon nitride layer and a silicon oxide layer on the upper surface of the Flash wafer, and sequentially removing the silicon oxide layer and the silicon nitride layer on the upper surface of the cell area and on the upper surface of the floating gate in the logical area and the capacitance area;
S04: adjusting the height of the silicon oxide filled shallow trench in the cell area and the capacitance area by protecting the logical area with a second mask, so that the height of the silicon oxide filled shallow trench in the cell area is lower than the height of the silicon oxide filled shallow trench in the capacitance area after adjusting;
S05: depositing an interlayer dielectric layer on the surface of the Flash wafer;
S06: removing the interlayer dielectric layer, the silicon oxide, the silicon nitride, the floating gate and a part of the silicon oxide filled shallow trench in the logical area by protecting the cell area and the capacitance area with a third mask, to obtain the cell area, the logical area and the capacitance area which are different in the height of the silicon oxide filled shallow trench.

US Pat. No. 10,192,775

METHODS FOR GAPFILL IN HIGH ASPECT RATIO STRUCTURES

APPLIED MATERIALS, INC., ...

1. A processing method comprising:providing a substrate surface having an opening formed by at least one feature, the at least one feature, the at least one feature extending a depth from the substrate surface to a bottom surface, the at least one feature having a width defined by a first sidewall and a second sidewall;
forming a first quantity of a film on the substrate surface and the first sidewall, second sidewall and bottom surface of the at least one feature in a first deposition sequence, the first quantity of the film having a seam located within the width of the at least one feature wherein a bottom of the seam being at a first distance from the bottom surface of the at least one feature; and
reducing a height of the first quantity of the film to less than the first distance to remove at least some of the first quantity of the film and to completely remove the seam.

US Pat. No. 10,192,774

TEMPERATURE CONTROL DEVICE FOR PROCESSING TARGET OBJECT AND METHOD OF SELECTIVELY ETCHING NITRIDE FILM FROM MULTILAYER FILM

TOKYO ELECTRON LIMITED, ...

6. A method of selectively etching a nitride film from a processing target object, which has a multilayer film in which an oxide film and the nitride film are alternately stacked on top of each other, by using a temperature control device comprising a moving stage allowed to be heated and configured to mount a processing target object on a top surface thereof; a cooling body allowed to be cooled and fixed at a position under the moving stage; a shaft, having one end connected to the moving stage; the other end positioned under the cooling body; a first flange provided at the other end; and a second flange provided between the first flange and the cooling body, extended between the one end and the other end; a driving plate, provided between the first flange and the second flange, having a top surface facing the second flange and a bottom surface opposite to the top surface; an elastic body provided between the bottom surface of the driving plate and the first flange; and a driving unit configured to move the driving plate up and down, the method comprising:placing the processing target object on the top surface of the moving stage;
bringing the moving stage into contact with the cooling body by moving the driving plate downwards;
adjusting a contact thermal resistance between the moving stage and the cooling body by adjusting an amount of a downward movement of the driving plate;
etching the nitride film selectively from the multilayer film by plasma of a processing gas containing fluorine and hydrogen after the bringing of the moving stage into contact with the cooling body;
spacing the moving stage apart from the cooling body by moving the driving plate upwards after the etching of the nitride film; and
removing a reaction product, which is generated in the etching of the nitride film, by heating the moving stage after the spacing of the moving stage apart from the cooling body.

US Pat. No. 10,192,773

SEMICONDUCTOR DEVICE POSITIONING SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE POSITIONING

Nexperia B.V., Nijmegen ...

1. A positioning system for positioning a semiconductor device, the positioning system comprising:a long-stroke stage configured to be linearly movable with respect to a supporting structure within a plane, wherein the long-stroke stage has a first range of motion relative to the supporting structure,
a short-stroke stage attached to the long-stroke stage and configured to carry a semiconductor device and to be linearly movable within the plane, wherein the short-stroke stage is supported by the long-stroke stage and has a second range of motion relative to the long-stroke stage that is smaller than the first range of motion,
wherein the short-stroke stage relative to the supporting structure has a position that is the sum of the position of the short-stroke stage relative to the position of a long-stroke stage and the position of the long-stoke stage relative to the supporting structure, and
a plurality of sensors configured to measure relative positions between the long-stroke stage, the short-stroke stage, and the supporting structure so that the long-stroke stage acts as a balance mass between the short-stroke stage and the supporting structure.

US Pat. No. 10,192,772

SUBSTRATE TABLE AND LITHOGRAPHIC APPARATUS

ASML Netherlands B.V., V...

1. A substrate table to support a substrate, the substrate table comprising:a main body;
burls extending from the main body and having first upper ends, the first upper ends defining a support surface to support the substrate; and
support pins having second upper ends, the support pins being movable between a retracted position, in which the second upper ends are arranged below the support surface, and an extended position, in which the second upper ends extend above the support surface,
wherein at least some of the support pins are arranged to support the substrate in the extended position,
wherein the support pins are arranged to be switched to a first stiffness mode and a second stiffness mode,
wherein, in the first stiffness mode, the at least some of the support pins have a first stiffness in a direction parallel to the support surface,
wherein, in the second stiffness mode, the at least some of the support pins have a second stiffness in the direction parallel to the support surface,
wherein the first stiffness is different from the second stiffness.

US Pat. No. 10,192,771

SUBSTRATE HOLDING/ROTATING DEVICE, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate holding/rotating device comprising:a rotary table;
a rotation driving unit that rotates the rotary table around a rotational axis aligned with a vertical direction; and
a plurality of movable pins that supports a substrate horizontally, each of the movable pins having a support portion movable between an open position that is far apart from the rotational axis and a hold position that has approached the rotational axis, the plurality of movable pins being arranged to rotate around the rotational axis together with the rotary table,
the plurality of movable pins including a first movable pin group including at least three movable pins, and a second movable pin group including at least three movable pins other than the movable pins belonging to the first movable pin group,
the substrate holding/rotating device further comprising:
an urging unit that urges the support portion of each of the movable pins to one of the open position and the hold position;
first driving magnets, mounted in correspondence to the respective movable pins of the first movable pin group, having magnetic pole directions orthogonal to the rotational axis and mutually equal with respect to the rotational axis;
second driving magnets, mounted in correspondence to the respective movable pins of the second movable pin group, having magnetic pole directions orthogonal to the rotational axis and opposite those of the first driving magnets with respect to the rotational axis;
a first moving magnet, arranged in a non-rotating state, having a magnetic pole direction such as to apply a repulsive force or an attractive force to the first driving magnets along directions orthogonal to the rotational axis, and, by the repulsive force or the attractive force, urging the support portions of the first movable pin group to the other of the open position and the hold position;
a second moving magnet, arranged in a non-rotating state, having a magnetic pole direction such as to apply a repulsive force or an attractive force to the second driving magnets along directions orthogonal to the rotational axis, and, by the repulsive force or the attractive force, urging the support portions of the second movable pin group to the other of the open position and the hold position;
a first relative movement unit that makes the first moving magnet and the rotary table move relatively between a first position, at which the first moving magnet applies the repulsive force or the attractive force to the first driving magnets, and a second position, at which the first moving magnet does not apply the repulsive force or the attractive force to the first driving magnets; and
a second relative movement unit that makes the second moving magnet and the rotary table move relatively between a third position, at which the second moving magnet applies the repulsive force or the attractive force to the second driving magnets, and a fourth position, at which the second moving magnet does not apply the repulsive force or the attractive force to the second driving magnets, independently of the relative movement of the first moving magnet and the rotary table.

US Pat. No. 10,192,770

SPRING-LOADED PINS FOR SUSCEPTOR ASSEMBLY AND PROCESSING METHODS USING SAME

Applied Materials, Inc., ...

1. A susceptor assembly, comprising:a susceptor having a susceptor body and a top surface with at least one recess therein sized to enclose a wafer during processing, each recess having a bottom surface with at least three flared openings; and
at least three lift pins positioned within each recess, each lift pin positioned within one of the at least three flared openings in the bottom surface of the recess, each lift pin comprising a sleeve having an elongate body with a flared top end, bottom, sides and an elongate axis, the sleeve movable within the recess along the elongate axis so that the flared top end of the sleeve can extend above the bottom surface of the recess, a spring within the elongate body of the sleeve adjacent the bottom of the sleeve and a pin positioned within the elongate sleeve in contact with the spring, the pin having a flared top portion and movable along the elongate axis of the sleeve so that a top surface of the pin can extend above the flared top end of the sleeve.

US Pat. No. 10,192,768

SHEET FOR SEMICONDUCTOR PROCESSING

LINTEC CORPORATION, Toky...

1. A semiconductor processing sheet, the sheet comprising a base material and a pressure sensitive adhesive layer laminated on at least one surface of the base material,the pressure sensitive adhesive layer being formed of a pressure sensitive adhesive composition, the pressure sensitive adhesive composition containing a polymer having an effective amount of a salt to provide antistatic properties during semiconductor processing and an energy ray curable group, and an energy ray curable pressure sensitive adhesive component excluding the polymer,
a content of the polymer in the pressure sensitive adhesive composition being 0.5 to 30 mass %, and
a weight-average molecular weight of the polymer being 30,000 to 200,000.

US Pat. No. 10,192,765

SUBSTRATE PROCESSING SYSTEMS, APPARATUS, AND METHODS WITH FACTORY INTERFACE ENVIRONMENTAL CONTROLS

Applied Materials, Inc., ...

1. A method of processing substrates within an electronic device processing system, comprising:providing a factory interface including a factory interface chamber, one or more substrate carriers docked to the factory interface, each of the one or more substrate carriers having a substrate carrier door, one or more carrier purge chambers within the factory interface chamber, and one or more load lock chambers coupled to the factory interface;
sealing a carrier purge housing to the factory interface chamber, the carrier purge housing having a carrier purge chamber located therein, the sealing covering a substrate carrier door and isolating the carrier purge chamber from the factory interface chamber;
monitoring one or more environmental conditions in the carrier purge chamber;
setting one or more environmental conditions in the carrier purge chamber in response to the monitoring;
opening the substrate carrier door by attaching a door opener to the substrate carrier door, the door opener being attached to a rack and pinion, the rack located within the carrier purge chamber, the pinion being attached to a motor at least partially located external to the carrier purge chamber; and
unsealing the carrier purge housing from the factory interface.

US Pat. No. 10,192,764

OVERHEAD TRANSPORT VEHICLE

MURATA MACHINERY, LTD., ...

1. An overhead transport vehicle comprising:a body capable of travelling along a track; and
a grip liftably provided in the body by a plurality of suspensions and capable of gripping an article; wherein
the overhead transport vehicle includes a vibration-proof portion disposed between the plurality of suspensions and the grip;
the vibration-proof portion includes:
a first vibration-proof portion disposed on a side, where a first load acts, in a travelling direction of the body or in a width direction perpendicular or substantially perpendicular to both the travelling direction and a lifting direction of the grip; and
a second vibration-proof portion disposed on a side, where a second load larger than the first load acts, in the travelling direction or in the width direction and having a larger repulsive force than a repulsive force of the first vibration-proof portion; and
the first vibration-proof portion and the second vibration-proof portion each includes a spring or a plurality of springs.

US Pat. No. 10,192,763

METHODOLOGY FOR CHAMBER PERFORMANCE MATCHING FOR SEMICONDUCTOR EQUIPMENT

Applied Materials, Inc., ...

1. A method for calibrating a plasma processing chamber for semiconductor manufacturing process, comprising:performing a first predetermined plasma process in a plasma processing chamber;
maintaining a desired gas pressure in the plasma processing chamber;
collecting a first set of signals transmitted from a first group of sensors disposed in the plasma processing chamber to a controller while performing the predetermined process;
analyzing the collected first set of signals;
comparing the collected first set of signals with database stored in the controller of the plasma processing chamber to check sensor responses from the first group of sensors;
calibrating sensors based on the collected first set of signals when a mismatch sensor response is found;
subsequently performing a first series of plasma processes including at least two processes in the processing chamber, wherein the first series of processes comprises multiple processes including the process parameters set in the first predetermined process, 20% above and below of the process parameters set in the first predetermined process, and 10% above and below of the process parameters set in the first predetermined process; and
collecting a second set of signals transmitted from the sensors to the controller while performing the series of plasma processes in the plasma processing chamber.

US Pat. No. 10,192,762

SYSTEMS AND METHODS FOR DETECTING THE EXISTENCE OF ONE OR MORE ENVIRONMENTAL CONDITIONS WITHIN A SUBSTRATE PROCESSING SYSTEM

APPLIED MATERIALS, INC., ...

1. A method for operating a substrate processing cluster tool, comprising:positioning a substrate storage cassette at least partially within a factory interface of the substrate processing cluster tool, the substrate storage cassette defining an interior volume dimensioned and arranged to receive one or more substrates;
sensing, with a plurality of sensors, at least one condition including temperature within the substrate storage cassette, an elapsed time between termination of a first process involving the substrate storage cassette and initiation of a second process involving the substrate storage cassette, a concentration of one or more airborne contaminants within at least one of the substrate storage cassette or the factory interface, or a humidity within the substrate storage cassette; and
responsive to a sensed condition generating an alert and performing a corrective operation involving the substrate storage cassette.

US Pat. No. 10,192,760

SUBSTRATE SUPPORTING UNIT, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SUBSTRATE SUPPORTING UNIT

Eugene Technology Co., Lt...

1. A method of manufacturing a substrate supporting unit provided with a susceptor, on which a substrate is placed, comprising installing a heat dissipating member at one side of the susceptor, including a first temperature region and a second temperature region having a higher temperature than that of the first temperature region, such that the heat dissipating member is in thermal contact with the second temperature region so as to emit heat of the second temperature region, and forming an opening corresponding to the first temperature region through the heat dissipating member to prevent thermal contact between the first temperature region and the heat dissipating member,wherein:
the heat dissipating member is formed in a ring shape, in which the opening corresponding to the first temperature region is surrounded with a contact surface corresponding to the second temperature region, and
the formation of the opening includes
forming a first opening part in a fan shape having a first radius, and
forming a second opening part in a fan shape having a second radius being different from the first radius.

US Pat. No. 10,192,759

IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING

LAM RESEARCH CORPORATION,...

1. A semiconductor processing tool, comprising:one or more process chambers;
one or more gas inlets into the one or more process chambers and associated flow-control hardware;
a low frequency radio frequency (LFRF) generator;
a high frequency radio frequency (HFRF) generator; and
a controller having at least one processor and a memory, wherein
the at least one processor and the memory are communicatively connected with one another,
the at least one processor is at least operatively connected with the flow-control hardware, the LFRF generator, and the HFRF generator, and
the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware, the HFRF generator, and the LFRF generator to:
etch a semiconductor substrate to transfer a pattern from an overlying photoresist to a core amorphous carbon layer on the semiconductor substrate;
deposit a conformal film over the patterned core amorphous carbon layer on the semiconductor substrate;
deposit a gap-fill amorphous carbon layer over the conformal film;
planarize the semiconductor substrate with a process that etches both the conformal film and the gap-fill amorphous carbon layer to remove the conformal film overlying the core amorphous carbon layer without removing the conformal film deposited between the core amorphous carbon layer and the gap-fill amorphous carbon layer; and
selectively etch the conformal film to form a mask.

US Pat. No. 10,192,758

SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus that processes a substrate with a processing liquid and dries the substrate, the substrate processing apparatus comprising:a substrate rotating device configured to rotate the substrate;
a processing liquid discharging unit configured to discharge the processing liquid toward the substrate;
a substitution liquid discharging unit configured to discharge a substitution liquid, which is substituted with the processing liquid on the substrate, toward the substrate while relatively moving with respect to the substrate to form a liquid film of the substitution liquid on the substrate; and
an inert gas discharging unit configured to:
discharge a first inert gas, from a first inert gas discharge nozzle provided vertically downward, vertically downward from above a central portion of the substrate toward a central portion of the liquid film of the substitution liquid formed on the substrate to form an interface where the liquid film of the substitution liquid is thicker at a peripheral portion side of the substrate than at a central portion side thereof and to increase an area confined by the interface uniformly from the central portion of the substrate toward a peripheral portion thereof, and then
push the interface from the central portion of the substrate toward the peripheral portion thereof by discharging a second inert gas, from a second inert gas discharge nozzle provided to be inclined downward, toward a peripheral portion of the substrate in an inclined direction from above the substrate while moving the second inert gas discharge nozzle relatively with respect to the substrate in a direction different from a direction in which the substitution liquid discharging unit is moved.

US Pat. No. 10,192,757

SUBSTRATE CLEANING APPARATUS AND SUBSTRATE CLEANING METHOD

EBARA CORPORATION, Tokyo...

1. A substrate cleaning apparatus, comprising:a substrate holder configured to hold a substrate and rotate the substrate about a rotational axis;
a roll cleaning tool configured to be placed in sliding contact with the substrate to thereby clean the substrate; and
a cleaning-tool rotating device coupled to the roll cleaning tool;
a vertically-moving device coupled to the cleaning-tool rotating device, the vertically-moving device being configured to change a vertical position of the roll cleaning tool toward the substrate held by the substrate holder and keep the vertical position of the roll cleaning tool while cleaning the substrate;
a cleaning-liquid supply nozzle configured to supply cleaning liquid onto a first region of the substrate;
a fluid supply nozzle arranged in parallel with a longitudinal direction of the roll cleaning tool as viewed from an extending direction of the rotational axis, the fluid supply nozzle being configured to supply fluid, which is constituted by pure water or chemical liquid, onto a second region of the substrate, the cleaning-liquid supply nozzle being located at one side of the roll cleaning tool, while the fluid supply nozzle being located at an opposite side of the roll cleaning tool beside the roll cleaning tool, the fluid supply nozzle being located at a position to form a flow of the fluid along the longitudinal direction of the roll cleaning tool at the second region located at an opposite side of the substrate from the first region across the roll cleaning tool.

US Pat. No. 10,192,755

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of wiring layers formed over the semiconductor substrate;
a pad electrode formed in the uppermost layer of the wiring layers;
a first protective film having an opening over the pad electrode;
a first redistribution line formed over the first protective film and having an upper surface, a side surface and a lower surface, the first redistribution line coupled electrically to the pad electrode through the opening;
a sidewall barrier film comprised of an insulating film formed on the side surface of the first redistribution line; and
a cap metallic film covering the upper surface of the first redistribution line and having an overlapping part with sidewall barrier film,
wherein the cap metallic film covers the side surface of the first redistribution line, and
wherein the cap metallic film and the sidewall barrier film are overlapped with each other at the side surface of the first redistribution line.

US Pat. No. 10,192,754

EPITAXIAL SILICON WAFER AND METHOD FOR PRODUCING THE EPITAXIAL SILICON WAFER

SUMCO CORPORATION, Tokyo...

1. A method for producing an epitaxial silicon wafer, comprising:subjecting a silicon wafer to preliminary thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×1017 atoms/cm3 to 16×1017 atoms/cm3, contains no dislocation cluster and no COP (Crystal Originated Particle), and contains an oxygen precipitation suppression region; and
forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment,
the method further comprising determining a thermal treatment condition for the preliminary thermal treatment based on a ratio (%) of a width of the oxygen precipitation suppression region in a radial direction of the silicon wafer to a maximum radius of the silicon wafer before the preliminary thermal treatment is carried out;
wherein the preliminary thermal treatment condition is determined so as to satisfy any one of the following relational expressions (1) to (3):
in a case of 9×1017 atoms/cm3?Co<11.5×1017 atoms/cm3:
(Co×(100?X)/5.3×1051)(?1/11.29) in a case of 11.5×1017 atoms/cm3?Co<13.5×1017 atoms/cm3:
(Co×(100?X)/5.3×1051)(?1/11.29) (Co×(100?X)/5.3×1051)(?1/11.29) the ratio (%) of the width of the oxygen precipitation suppression region in the radial direction of the silicon wafer to the maximum radius of the silicon wafer is X, and
the oxygen concentration (atoms/cm3) of the silicon wafer is Co.

US Pat. No. 10,192,753

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

10. A nonvolatile semiconductor memory device, comprising:a plurality of conductive layers arranged in a first direction and a second direction crossing the first direction, the plurality of conductive layers extending in a third direction, the third direction crossing the first direction and the second direction, the plurality of conductive layers including a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer being arranged in the second direction;
a first semiconductor layer having the first direction as a longitudinal direction and facing the first conductive layer;
a first charge accumulation layer disposed between the first semiconductor layer and the first conductive layer; and
a second semiconductor layer having the first direction as a longitudinal direction and facing the second conductive layer; and
a second charge accumulation layer disposed between the second semiconductor layer and the second conductive layer, wherein
at least a part of the first conductive layer is disposed between the first semiconductor layer and the second semiconductor layer,
at least a part of the second conductive layer is disposed between the first conductive layer and the second semiconductor layer, and
the first conductive layer having a first surface in the second direction facing the first semiconductor layer and a second surface in the second direction facing the second conductive layer, an upper end and a lower end of the second surface being rounded.

US Pat. No. 10,192,752

SELF-ASSEMBLED MONOLAYER BLOCKING WITH INTERMITTENT AIR-WATER EXPOSURE

Applied Materials, Inc., ...

14. A method of processing a substrate, comprising:exposing a substrate to a self-assembled monolayer (“SAM”) molecule for a first period of time to achieve selective deposition of a SAM on a first material in a first processing chamber, wherein the substrate comprises an exposed first material and an exposed second material;
transferring the substrate to a second processing chamber;
exposing the substrate to a hydroxyl moiety formed from water vapor in the second processing chamber for a second period of time;
repeating the exposing the substrate to a SAM molecule in the first processing chamber and the exposing the substrate to the hydroxyl moiety formed from water vapor in the second processing chamber in a time ratio of the first period of time to the second period of time between about 1:1 and about 100:1, respectively, and wherein a first repetition occurs for a first total time and a subsequent repetition occurs for a second total time that is less than the first total time;
after performing the repeating, exposing the substrate to the SAM molecule in the first processing chamber;
selectively depositing a third material on the exposed second material; and
removing the SAM from the first material.

US Pat. No. 10,192,751

SYSTEMS AND METHODS FOR ULTRAHIGH SELECTIVE NITRIDE ETCH

LAM RESEARCH CORPORATION,...

1. A method for selectively etching a silicon nitride layer on a substrate, comprising:arranging the substrate on a substrate support of a substrate processing chamber,
wherein the substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper chamber region and the lower chamber region, and
wherein the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region;
supplying an etch gas mixture to the upper chamber region;
striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil, wherein the etch gas mixture etches silicon nitride, promotes silicon dioxide passivation and promotes polysilicon passivation;
selectively etching the silicon nitride layer on the substrate;
extinguishing the inductively coupled plasma after a predetermined period; and
after the selectively etching, dry cleaning the substrate by supplying a dry clean gas mixture to the substrate processing chamber and striking plasma in the substrate processing chamber for another predetermined period.

US Pat. No. 10,192,747

MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF

Cypress Semiconductor Cor...

1. The method of fabricating a semiconductor device, comprising:forming, on a substrate, a first gate stack having a first gate conductor layer and a first gate dielectric structure between the first gate conductor layer and the substrate;
forming an inter-gate dielectric structure at a sidewall of the first gate conductor;
forming, adjacent to the inter-gate dielectric structure, a second gate stack having a second gate conductor layer and a second gate dielectric structure between the second gate conductor layer and the substrate; and
performing a wet etch to clean the first and second gate stacks prior to forming a dielectric layer to encapsulate at least the first and second gate stacks, and the inter-gate,
wherein the inter-gate dielectric structure includes four or more layers of two or more different dielectric films disposed in an alternating manner, and having significantly different wet etch rates against a same etchant, wherein each of the four or more layers includes a width in an approximate range of 30 ? or less, and wherein the inter-gate dielectric structure is substantially un-etched by the wet etch in a direction perpendicular to the substrate.

US Pat. No. 10,192,745

METHOD FOR MANUFACTURING A LAYER STACK FROM A P+-SUBSTRATE, A P?-LAYER, AN N?-LAYER AND A THIRD LAYER

3-5 Power Electronics Gmb...

1. A method for manufacturing a layer stack from a p+-substrate, a p?-layer, an n?-layer and a third layer, the method comprising:providing the p+-substrate with a dopant concentration of 5*1018-5*1020cm?3 and a layer thickness of 50-900 microns, and comprising a GaAs compound;
providing the p?-layer with a dopant concentration of 1014-1016 cm?3 and a layer thickness of 0.01-1 micron, and comprising a GaAs compound;
providing the n?-layer with a dopant concentration of 1014-1016 cm?3, a layer thickness of 10-200 microns, and comprising a GaAs compound;
producing a first partial stack and a second partial stack, an upper side of the first partial stack is integrally bonded with an upper side of the second partial stack via wafer bonding to manufacture the layer stack, the first partial stack comprising at least the p+-substrate, the second partial stack comprising at least the n?-layer;
producing the p?-layer via epitaxy or implantation on an upper side of the p+-substrate or via epitaxy on the n?-layer, the p?-layer forming the upper side of the first partial stack or of the second partial stack;
producing the third layer prior to or after the wafer bonding;
producing the n?-layer after the wafer bonding by abrading an n?-substrate and at least partially forming the second partial stack or producing the n?-layer before the wafer bonding on an n+-substrate.

US Pat. No. 10,192,744

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Semiconductor Manufacturi...

1. A semiconductor device comprising:a first substrate, wherein a through hole extends through the first substrate;
a second substrate, which overlaps the first substrate;
a first conductor, which is configured to electrically connect two elements associated with the first substrate, wherein the through hole is positioned between two opposite edges of the first conductor;
a second conductor, which is positioned on the first substrate and is electrically connected to the first conductor;
a third conductor, which is configured to electrically connect two elements associated with the second substrate;
a fourth conductor which is positioned on the second substrate and is electrically connected to the third conductor; and
a fifth conductor, which directly contacts each of the second conductor and the fourth conductor and is positioned between the second conductor and the fourth conductor.

US Pat. No. 10,192,743

METHOD OF ANISOTROPIC EXTRACTION OF SILICON NITRIDE MANDREL FOR FABRICATION OF SELF-ALIGNED BLOCK STRUCTURES

TOKYO ELECTRON LIMITED, ...

1. A method of preparing a self-aligned block (SAB) structure, comprising:providing a substrate having raised features defined by a first material containing silicon nitride and a second material containing silicon oxide formed on side walls of the first material, and a third material containing an organic material covering some of the raised features and exposing some raised features according to a block pattern formed in the third material;
forming a first chemical mixture by plasma-excitation of a first process gas containing H and optionally a noble gas;
exposing the first, second, and third materials on the substrate to the first chemical mixture;
thereafter, forming a second chemical mixture by plasma-excitation of a second process gas containing N, F, O, and optionally a noble element; and
exposing the first, second, and third materials on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second and third materials.

US Pat. No. 10,192,740

HIGH THROUGHPUT SEMICONDUCTOR DEPOSITION SYSTEM

Alliance for Sustainable ...

1. A method of performing hydride vapor phase epitaxy (HVPE) deposition, the method comprising:providing at least one first source material and at least one first carrier gas flow to a first HVPE mixing zone coupled to a first deposition zone;
providing at least one second source material and at least one second carrier gas flow to a second HVPE mixing zone coupled to a second deposition zone;
heating the first deposition zone to a first temperature;
heating the first HVPE mixing zone to a second temperature;
heating the second deposition zone to a third temperature, wherein the third temperature is different from the first temperature;
heating the second HVPE mixing zone to a fourth temperature;
outputting, from the first HVPE mixing zone into the first deposition zone, first reactant gases produced from the at least one first source material and the at least one first carrier gas flow;
outputting, from the second HVPE mixing zone into the second deposition zone, second reactant gases produced from the at least one second source material and the at least one second carrier gas flow;
placing a substrate into the first deposition zone to grow a first layer from the first reactant gases; and
placing the substrate into the second deposition zone to grow a second layer from the second reactant gases,
wherein the heating of the first deposition zone to the first temperature and the heating of the second deposition zone to the third temperature are performed concurrently.

US Pat. No. 10,192,736

METHOD FOR TRANSFERRING GRAPHENE BY ATTACHING REMOVABLE FRAME TO PROTECTIVE LAYER APPLIED ON A SAMPLE CONTAINING GRAPHENE MONOLAYER

GRAPHENEA S.A., Donostia...

1. A method of transferring graphene onto a target substrate, said target substrate being either a substrate having cavities and/or holes or a substrate having at least one water soluble layer, characterized in that it comprises the steps of:applying a protective layer (4) onto a sample comprising a stack (20) formed by a graphene monolayer (2) grown on a metal foil or on a metal thin film on a silicon substrate (1);
attaching to said protective layer (4) a frame (5) comprising at least one outer border and at least one inner border, said frame (5) comprising a substrate and a thermal release adhesive polymer layer, the thermal release adhesive polymer layer being made of a material different from the material of the substrate, the frame (5) having a Young's modulus equal or higher than 10 MPa providing integrity and allowing the handling of said sample, the frame (5) being thermally released at a temperature up to 150° C.;
removing or detaching said metal foil or metal thin film from the silicon substrate (1);
once the metal foil or metal thin film on the silicon substrate (1) has been removed or detached, drying the sample;
depositing the sample onto the target substrate (7); and
removing said frame (5) by cutting through said protective layer (4) at said at least one inner border of the frame (5), or by thermal release at a temperature up to 150° C.

US Pat. No. 10,192,734

SHORT INORGANIC TRISILYLAMINE-BASED POLYSILAZANES FOR THIN FILM DEPOSITION

Air Liquide Advanced Mate...

1. A silicon-containing film forming composition comprising a precursor selected from the group consisting of:[(SiR3)2NSiH2]m—NH2-m—C?N, with m=1 or 2;  (a)
[(SiR3)2NSiH2]n—NL3-n,with n=2 or 3;  (b)
(SiH3)2NSiH2—O—SiH2N(SiH3)2; and  (c)
(SiR?3)2N—SiH2—N(SiR?3)2;  (d)whereineach R is independently selected from H, a dialkylamino group having the formula NR1R2, or an amidinate,
Each R? is independently selected from H, a dialkylamino group having the formula NR1R2, or an amidinate, with the provision that all R? are not H,
R1 and R2 are independently selected from H or a C1-C12 hydrocarbyl group, with the provision that R1 and R2 cannot be simultaneously equal to H, and that if R1 is H, then R2 is a C2-C12 hydrocarbyl group, and NR? R2 may together form an N-containing heterocyclic ligand, and
L is selected from H or a C1-C6 hydrocarbyl group.

US Pat. No. 10,192,722

PLASMA TREATMENT METHOD, PLASMA TREATMENT APPARATUS, AND PLASMA-TREATED LONG OBJECT

SUNLINE CO., LTD., Iwaku...

1. A plasma treatment apparatus in which a lengthy object to be treat is subjected to plasma treatment by being placed in contact with plasma comprising:a first cylindrical portion in which plasma is generated therein;
two or more ring-shaped electrodes provided interspatially in a longitudinal direction, each of the ring-shaped electrodes surrounding the entire circumference of the first cylindrical portion, which electrodes generate plasma, distribution of plasma density varying in a radial direction within the first cylindrical portion wherein the plasma density is higher than the plasma density towards the center near an inner wall of the first cylindrical portion and the plasma density becomes lower towards a center in the radial direction in the first cylindrical portion;
a plasma generating gas introducing portion that introduces plasma generating gas into the first cylindrical portion; and
a guide portion that is provided on the inner side of the first cylindrical portion, guides the lengthy object to be treated in a manner advancing through an area near the inner having high plasma density relative to the plasma density towards the center in the radial direction in the first cylindrical portion, and is composed of a plurality of guide members which are arranged in the longitudinal direction of the first cylindrical portion,
wherein the plurality of guide members are formed into a shape enabling the lengthy object to be treated to advance in a spiraling manner through the area having high plasma density in the first cylindrical portion.

US Pat. No. 10,192,705

FUSE ELEMENT, A FUSE, A METHOD FOR PRODUCING A FUSE, SMD FUSE AND SMD CIRCUIT

SCHURTER AG, Lucerne (CH...

1. A method for producing a fuse (10), comprising the steps of:providing at least one fuse element (12; 12?, 12?) having two connecting contacts (24?, 24?) and an interposed conductive track (26), such that the conductive track (26) has a reduced line cross-section in relation to the connecting contacts (24?, 24?) at least in some sections;
providing a base support (14);
providing the fuse element (12; 12?, 12?) with at least one overlay (16; 16?, 16?), wherein the fuse element (12; 12?, 12?) and the overlay (16; 16?, 16?) are each selected from materials which undergo diffusion when a predetermined ambient temperature is exceeded and when an electric current is conducted by the fuse element (12; 12?, 12?), and
wherein the fuse element is being connected to an external component by a reflow soldering process without the fuse element triggering at a reflow soldering process temperature occurring in this process, wherein the reflow soldering process temperature is higher than the
predetermined ambient temperature, and
arranging the at least one fuse element (12; 12?, 12?) on the base support (14),
wherein the at least one overlay (16_1) is arranged within the conductive track (26_1) adjacent to one of the connecting contacts (24_1?, 24_1?) of the fuse element (12_1).

US Pat. No. 10,192,697

KEY AND KEYBOARD DEVICE

ASUSTEK COMPUTER INC., T...

1. A key disposed on a baseplate of a keyboard device, the key comprising:a sheet metal keycap including a body portion and two bending portions, wherein the body portion includes at least two punching holes corresponding to the bending portions, the at least two punching holes are disposed between an edge and a center of the body portion, and the two bending portions are extended downwardly from a side of the punching holes of the body portion, respectively; and
a supporting structure, disposed between the sheet metal keycap and the baseplate, and two sides of the supporting structure are pivotally connected to the bending portions and the baseplate, respectively.

US Pat. No. 10,192,688

ELECTROLYTIC CAPACITOR AND METHOD FOR IMPROVED ELECTROLYTIC CAPACITOR ANODES

COMPOSITE MATERIAL TECHNO...

1. A process for forming an electrolytic device comprising the steps of:(a) providing multiple components of a valve metal in a billet of a ductile material;
(b) working the billet to a series of reduction steps to form said valve metal components into elongated components;
(c) cutting the elongated components from step b), and leaching the ductile metal from the elongated components releasing elongated elements formed of the valve metal;
(d) washing the elongated elements from step c) with water and mixing the washed elongated elements with water to form a slurry in which the elements are evenly distributed;
(e) drying the elongated washed elements to form dried elongated washed elements;
(f) mixing the dried elongated washed elements from step (e) with electrically conductive particles in powder form, and agglomerating the mixture of dried elongated washed elements and electrically conductive particles;
(g) assembling, pressing and sintering the agglomerated mixture of dried elongated washed elements and electrically conductive particles into an electrolytic device.

US Pat. No. 10,192,680

PLANAR TRANSFORMER COMPONENTS COMPRISING ELECTROPHORETICALLY DEPOSITED COATING

PAYTON PLANAR MAGNETICS L...

1. An electrically insulated component configured for use in a planar transformer, the insulated component comprising:a planar transformer conductive component having two opposed surfaces comprising a first surface and a second surface and a plurality of edges; and
two distinct coating layers comprising a first layer and a second layer, the first layer being disposed between the conductive component and the second layer, wherein the first layer and the second layer cover at least the first surface and the plurality of edges of the conductive component,
wherein the first layer comprises an oxidized metal coating, which facilitates adhesion of the second layer to the conductive component, and the second layer comprises an electrophoretically deposited (EPD) insulating coating, comprising a polymer and an inorganic material and has a thickness in the range of about 10 ?m to about 50 ?m.

US Pat. No. 10,192,678

CURRENT TRANSFORMER SYSTEM WITH SENSOR CT AND GENERATOR CT SEPARATELY ARRANGED IN PARALLEL IN ELECTRIC POWER LINE, AND INTEGRATED SYSTEM FOR CONTROLLING SAME IN WIRELESS COMMUNICATIONS NETWORK

FERRARISPOWER CO., LTD, ...

1. A current transformer (CT) system comprising:a sensor CT installed detached/attached from/to a power transmission/distribution wire and detecting a current flowing through the wire by electromagnetic induction;
a generator CT installed detached/attached from/to the power transmission/distribution wire and generating power by electromagnetic induction;
wherein each of the sensor CT and each of the generator CT is discretely separate from each other so as to allow attachment or detachment from the wire independently of each other; and
a microprocessor controlling the sensor CT and the generator CT;wherein each of the sensor CT and the generator CT comprises:a top assembly in which a core and a coil are installed;
a bottom assembly corresponding to the top assembly;
a hinge to which the top assembly and the bottom assembly are rotatably coupled;
a lock clip selectively opening and closing the top assembly and the bottom assembly;
a support rib extended to a front of the top assembly and supporting a belt that fixes the structure to the wire; and
a stopper extended to a rear of the bottom assembly and maintaining a certain distance between neighboring structures to prevent the structure from becoming coupled to each other by magnetism.

US Pat. No. 10,192,675

PULSE TRANSFORMER

Tai-Tech Advanced Electro...

1. A pulse transformer comprising:a drum core including a winding core, a first flange and a second flange provided on end portions of said winding core respectively, said first and said second flanges each including an inner surface and an outer surface and an upper portion, said winding core including an upper surface,
said first and said second flanges each including a notch formed in said upper portion thereof and each of said notches being defined by a base surface,
said first and said second flanges each including a chamfered portion provided in each side of said notch of said first and said second flanges respectively,
said base surfaces of said first and said second flanges being flush with said upper surface of said winding core,
a first terminal electrode and a second terminal electrode provided on said upper portion of said first flange,
a first center tap and a third terminal electrode and a fourth terminal electrode provided on said upper portion of said second flange,
a second center tap provided on said upper portion of said first flange,
said notch of said first flange being located between said second terminal electrode and said second center tap, and said notch of said second flange being located between said first center tap and said third terminal electrode, and
a coil including a first wire, a second wire, a third wire and a fourth wire wound around said winding core of said drum core, said first wire including a first end portion connected to said second terminal electrode and a second end portion connected to said first center tap, said second wire including a first end portion connected to said second center tap and a second end portion connected to said third terminal electrode, said third wire including a first end portion connected to said first terminal electrode and a second end portion connected to said first center tap, said fourth wire including a first end portion connected to said second center tap and a second end portion connected to said fourth terminal electrode, and
said first and said second wires being wound in a first direction as seen from said first flange toward said winding core and said second flange, and said third and said fourth wires being wound in a second direction as seen from said first flange toward said winding core and said second flange, said first and said fourth wires crossing each other at said inner surface of said first flange, and said second and said third wires crossing each other at said inner surface of said second flange.

US Pat. No. 10,192,660

PROCESS FOR PREPARATION OF NANOPARTICLES FROM MAGNETITE ORE

Sri Lanka Institute of Na...

1. A process for making magnetite nanoparticle dispersions, wherein substantially all of the nanoparticles have a particle size of about 32 nm, consisting of:(a) providing a magnetite ore;
(b) destructuring the magnetite ore, wherein (i) the destructuring of the magnetic ore is done by grinding in a nano-grinder in the presence of oleic acid using at least one of tungsten carbide grinding balls or zirconium oxide grinding balls and (ii) the grinding is performed in an inert atmosphere with:
15 mm size tungsten carbide grinding balls at 700 rpm for about one hour,
further grinding using 5 mm size tungsten carbide grinding balls at 700 rpm for about one hour,
further grinding using 3 mm size zirconium oxide grinding balls at 1000 rpm for about one hour, and
further grinding using 1 mm size zirconium oxide grinding balls at 1000 rpm for about one hour;
(c) contacting the destructured magnetite ore with one of the group consisting of a long chain alkyl carboxylic acid, a natural oil containing long chain carboxylic acid carboxyl groups, and combinations thereof to form stabilized nanoparticles; and
(d) dispersing the stabilized nanoparticles in alcoholic solvent.

US Pat. No. 10,192,656

JOINTED POWER CABLE AND METHOD OF MANUFACTURING THE SAME

NKT HV Cables GmbH, Bade...

1. A power cable comprising:a conductive core comprising a conductor including a plurality of sections, and an electrical insulation system enclosing the conductor, and
a sheath enclosing the conductive core,
wherein one of the plurality of sections of the conductor is a first conductor section and another of the plurality of sections of the conductor is a second conductor section, the first conductor section having a first cross-sectional geometry that provides a first ampacity for the first conductor section, and the second conductor section having a second cross-sectional geometry that provides a second ampacity for the second conductor section, wherein the first ampacity is higher than the second ampacity,
wherein the plurality of sections are thermally joined, and wherein the electrical insulation system extends continually from the first conductor section to the second conductor section of the conductor,
wherein the first conductor section comprises a plurality of strands and wherein the first cross-sectional geometry is a first strand configuration, and wherein the second conductor section comprises a plurality of strands and wherein the second cross-sectional geometry is a second strand configuration.

US Pat. No. 10,192,654

FLAT CABLE AND MANUFACTURING METHOD THEREOF

Thomas Engineering Co., L...

1. A flat cable comprising:a pod (10) including pipe type insertion portions (11) formed to be separated from each other at both side ends thereof and a central insertion portion (12) of which both ends are integrally connected to the both pipe type insertion portions (11);
a pair of left and right support members (20) inserted into the pipe insertion portions (11);
multiple electric cables (30) inserted into the central insertion portion (12); and
a clamp (40) including an upper clamp (41) installed above the support member (20) and having upper insertion grooves (41a) formed at both side ends thereof and a lower clamp (42) installed below the support member (20) and having lower insertion grooves (42a) formed at both side ends thereof,
wherein the central insertion portion (12) of the pod (12) is partitioned into multiple spaces (R1, R2, and R3) separated from each other and multiple electric cables (30) are horizontally disposed in the separated spaces in one layer, and
the support members (20) are inserted into the upper and lower insertion grooves (41a and 42a), an upper suspension projection (41b) is formed the entrance portion of the upper insertion groove (41a), and the lower suspension projection (42b) is formed at the entrance portion of the lower insertion groove (42a), upper clamp (41), and the support member (20) and the lower clamp (42) are screw-joined by a bolt (B) consecutively penetrating the upper clamp (41), and the support member (20) and the lower clamp (42).

US Pat. No. 10,192,653

TWISTED STRING-SHAPED ELECTRIC CABLE FOR UNDERWATER PURPOSE

Panasonic Intellectual Pr...

1. An electric cable comprising:at least one electric wire; and
a plurality of string-shaped bodies each extending in a longitudinal direction of the electric cable and twisting with one another around the at least one electric wire being a core, wherein the plurality of string-shaped bodies has a connection part twisting with one another excluding the at least one electric wire, and
wherein the connection part is connected to a frame of an underwater robot.

US Pat. No. 10,192,644

FUEL ASSEMBLY

Lightbridge Corporation, ...

1. A fuel assembly for use in an internal core structure of a nuclear power reactor, the assembly comprising:a frame shaped and configured to fit within the nuclear power reactor internal core structure; and
a plurality of helically twisted fuel elements supported by the frame in a fuel rod bundle, each of the fuel elements comprising fissile material;
wherein as viewed in a cross-section that is perpendicular to an axial direction of the fuel assembly, the outermost fuel elements of the fuel rod bundle define a substantially circular perimeter,
wherein the plurality of fuel elements are arranged into a mixed grid pattern that includes a first, rectangular grid pattern and a second, triangular grid pattern,
wherein each of the plurality of fuel elements comprises a longitudinal centerline, and
wherein the longitudinal centerlines of the fuel elements of the second, triangular grid pattern are separated from the longitudinal centerlines of adjacent fuel elements of the second, triangular grid pattern by a centerline-to-centerline distance, and a circumscribed diameter of the fuel elements in the second, triangular grid pattern equals the centerline-to-centerline distance.

US Pat. No. 10,192,620

NONVOLATILE MEMORY DEVICE, OPERATING METHOD OF NONVOLATILE MEMORY DEVICE, AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE

Samsung Electronics Co., ...

1. A nonvolatile memory device, comprising:a memory cell array including a plurality of nonvolatile memory cells configured to store data therein, wherein each of the nonvolatile memory cells is connected to one of a plurality of word lines and one of a plurality of bit lines of the memory cell array;
a row decoder connected to the word lines and configured to selectively apply at least one word line voltage to at least one of the word lines;
a page buffer connected to the plurality of bit lines; and
a ready/busy signal pin,
wherein the nonvolatile memory device is configured to perform a word line precharge operation by:
causing the ready/busy signal pin to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for the nonvolatile memory cells;
applying one or more word line precharge voltages to one or more selected word lines among the plurality of word lines to precharge the selected word lines; and
after at least a portion of the word line precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for the nonvolatile memory cells.

US Pat. No. 10,192,618

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. An operating method of a nonvolatile memory device, the method comprising:first storing a first data in a first reference cell and a second data opposite to the first data in a second reference cell, the first reference cell connected to a word line and a first reference bit line and the second reference cell connected to the word line and a second reference bitline;
comparing a voltage of the first reference bit line with a voltage of the second reference bit line to determine whether at least one of the first and second data is abnormally stored in the first and second reference cells after the first storing is performed; and
when it is determined that at least one of the first and second data is abnormally stored in the first and second reference cells, second storing the second data in the first reference cell and the first data in the second reference cell.

US Pat. No. 10,192,617

CIRCUIT AND ARRAY CIRCUIT FOR IMPLEMENTING SHIFT OPERATION

Huawei Technologies Co., ...

1. A circuit for implementing a shift operation, the circuit comprising:a resistive random-access memory, a first switch, a second switch, a third switch, and a fourth switch;
wherein the first switch is closed when a first end of the first switch is at a low level, the second switch is closed when a first end of the second switch is at a high level, the third switch is closed when a first end of the third switch is at a high level, and the fourth switch is closed when a first end of the fourth switch is at a low level;
wherein a second end of the first switch and a second end of the third switch are connected to a negative input end of the resistive random-access memory;
wherein a second end of the second switch and a second end of the fourth switch are connected to a positive input end of the resistive random-access memory;
wherein the first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are connected to an output end of a previous-stage circuit for implementing the shift operation;
wherein a third end of the first switch and a third end of the second switch are connected to a bias voltage end; and
wherein a third end of the third switch and a third end of the fourth switch are connected to a ground end.

US Pat. No. 10,192,616

OVONIC THRESHOLD SWITCH (OTS) DRIVER/SELECTOR USES UNSELECT BIAS TO PRE-CHARGE MEMORY CHIP CIRCUIT AND REDUCES UNACCEPTABLE FALSE SELECTS

WESTERN DIGITAL TECHNOLOG...

1. A memory device, comprising:a word line;
a bit line disposed perpendicular to the word line;
a memory element disposed between the word line and the bit line;
a select element coupled to the memory element, wherein the select element is disposed adjacent to the bit line wherein the select element is selected from the group consisting of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a Field Assisted Superlinear Threshold selector (FAST);
a wire that at least partly overlaps the word line, the wire coupled with a voltage source providing a predefined unselect bias voltage; and
a connecting element comprising an undoped polysilicon material disposed between the word line and the wire wherein the connecting element comprises a second memory element and a second select element, wherein the second select element is constructed from one of a RRAM and a MRAM material.

US Pat. No. 10,192,615

ONE-TIME PROGRAMMABLE DEVICES HAVING A SEMICONDUCTOR FIN STRUCTURE WITH A DIVIDED ACTIVE REGION

Attopsemi Technology Co.,...

1. An One-Time Programmable (OTP) memory, comprising:a plurality of OTP cells, at least one of the OTP cells comprising:
a resistive element; and
at least one semiconductor fin structure residing in a common well or on an isolated substrate, the semiconductor fin structure including a plurality of fins, at least one of the plurality of fins being covered by at least one MOS gate to divide the at least one of the plurality of fins into at least a first active region and a second active region, the first active region having a first type of dopant, and the second active region having the first type of dopant or the second type of dopant; the first active region coupled to one end of the resistive element, the other end of the resistive element coupled to a first voltage supply line, the second active region coupled to a second voltage supply line, and the MOS gate coupled to a third voltage supply line,
wherein the first and/or the second active regions of two or more of the plurality of fins are coupled together by at least one extended source/drain, and
wherein the resistive element can be configured to be programmable into a different resistance state by applying voltages to the first, second, and the third voltage supply lines.

US Pat. No. 10,192,614

ADAPTIVE READ THRESHOLD VOLTAGE TRACKING WITH GAP ESTIMATION BETWEEN DEFAULT READ THRESHOLD VOLTAGES

Seagate Technology LLC, ...

1. A device comprising:a controller configured to adjust a read threshold voltage for a memory by performing the following steps, wherein the controller is distinct from the memory:
estimating a gap between two adjacent default read threshold voltages using binary data from the memory;
determining, using the controller, statistical characteristics comprising at least a mean and a standard deviation of each of two adjacent memory levels of the memory based at least in part on a type of statistical distribution of the memory levels, a distribution of data values read from one or more cells using a plurality of discrete read threshold voltages associated with at least one of the two adjacent default read threshold voltages and the gap, wherein each of the plurality of discrete read threshold voltages associated with a first one of the two adjacent default read threshold voltages is obtained by adding a corresponding offset value to the first default read threshold voltage, wherein the corresponding offset values are relative to the first default read threshold voltage, wherein the first default read threshold voltage has a first set of non-zero offset values that are independent of each other;
computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and
updating the read threshold voltage with the adjusted read threshold voltage.

US Pat. No. 10,192,613

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first memory module;
a second memory module; and
a third memory module,
each of the memory modules having a memory cell array including a plurality of memory cells,
each of the memory modules having a first state to consume less electric power than in a second state, and
the first memory module having a greater number of memory cells than the second memory module;
a first control signal line coupled with the first memory module and the second memory module to transmit a control signal for controlling the first state and the second state to the first memory module and the second memory module;
a second control signal line coupled with the first memory module and the third memory module to transmit the control signal from the first memory module to the third memory module;
wherein a first wiring is disposed in the first memory module, and coupled between the first control signal line and the second control signal line for transmitting the control signal from the first control signal line to the second control signal line via the first wiring, and
wherein the first wiring is coupled with a first MOS transistor in the first memory module.

US Pat. No. 10,192,611

SENSING CIRCUIT, SET OF PRE-AMPLIFIERS, AND OPERATING METHOD THEREOF

NATIONAL TSING HUA UNIVER...

1. A set of pre-amplifiers of a sense amplifier, comprising:a first pre-amplifier, coupled to a first input terminal of the sense amplifier; and
a second pre-amplifier, coupled to a second input terminal of the sense amplifier;
wherein the first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage; and
one of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier;
wherein the first pre-amplifier comprises:
a first switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to the predetermined voltage, the second terminal of the first switch is coupled to the first input terminal of the sense amplifier, and the control terminal of the first switch receives a pre-charge signal;
a second switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch and the control terminal of the second switch is coupled to the second input terminal of the sense amplifier;
a third switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the second terminal of the second switch, the second terminal of the third switch is coupled to a ground, and a control terminal of the third switch receives an initializing signal; and
a first capacitor, having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the second terminal of the second switch.

US Pat. No. 10,192,610

METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit device comprising:a data transmitter having a data input to receive a data input signal, a timing input to receive a timing signal, and a data output to transmit a data output signal timed to the timing signal;
a strobe transmitter to transmit a transmit-strobe signal synchronized with the timing signal; and
a phase-control circuit to control a phase of the timing signal and the transmit-strobe signal, the phase-control circuit including:
memory to store at least one transmit state setting the phase of the timing signal and the transmit-strobe signal.

US Pat. No. 10,192,609

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A controller to control operations of a memory component, the controller comprising:a first circuit to transmit commands to the memory component, the commands including:
a first command that specifies a first data pattern to be stored in a first register of the memory component;
a second command that specifies a second data pattern to be stored in a second register of the memory component; and,
a third command to select one of the first data pattern or the second data pattern to be output by the memory component;
a second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,
calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.

US Pat. No. 10,192,608

APPARATUSES AND METHODS FOR DETECTION REFRESH STARVATION OF A MEMORY

Micron Technology, Inc., ...

1. An apparatus comprising:a plurality of memory cells; and
a control circuit configured to monitor refresh request commands and to perform an action that prevents unauthorized access to data stored at the plurality of memory cells in response to detection that timing of the refresh request commands has failed to meet a refresh timing limit.

US Pat. No. 10,192,607

PERIODIC ZQ CALIBRATION WITH TRAFFIC-BASED SELF-REFRESH IN A MULTI-RANK DDR SYSTEM

QUALCOMM Incorporated, S...

1. A method for memory calibration, comprising:scheduling a ZQ calibration short (ZQCS) command to calibrate a multi-rank double data rate (DDR) memory system according to a ZQ interval;
recording that a dynamic random-access memory (DRAM) rank in the multi-rank DDR memory system missed the ZQCS command in response to determining that the DRAM rank was is in a self-refresh mode at the ZQ interval; and
scheduling a ZQ command to calibrate the DRAM rank after exiting the self-refresh mode based at least in part on a number of ZQCS commands that were missed while the DRAM rank was in the self-refresh mode.

US Pat. No. 10,192,606

CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL USING SENSE CAPACITORS

MICRON TECHNOLOGY, INC., ...

1. A method of operating a ferroelectric memory cell, comprising:selecting the ferroelectric memory cell that is in electronic communication with a digit line;
activating a switching component that is in electronic communication with the digit line to virtually ground the digit line, wherein activating the switching component comprises applying a charging voltage to a capacitor when the switching component and the capacitor are connected in parallel;
virtually grounding the digit line; and
activating a sense amplifier that is in electronic communication with the digit line based at least in part on virtually grounding the digit line.

US Pat. No. 10,192,605

MEMORY CELLS AND SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a ferroelectric material comprising hafnium oxide, zirconium oxide, or a combination thereof, the ferroelectric material configured to exhibit asymmetric characteristics and configured to switch from a first polarization state to a second polarization state responsive to exposure to a first bias voltage and configured to change from the second polarization state to the first polarization state responsive to exposure to a negative bias voltage having a different magnitude than the positive bias voltage.

US Pat. No. 10,192,604

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:a cell array including a plurality of memory cells;
a sense amplifier reading data of the memory cell;
write drivers writing data to the memory cell;
a sub cell area including the cell array, the sense amplifier, and the write driver;
a memory area including a plurality of sub cell areas; and
a control circuit, when performing a first operation of supplying a first voltage to a selected sub cell area, supplying first write data to the sub cell area which performs the first operation, for selecting the sub cell area as a target of the first operation.